openbcm

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allregs_o.i (2137911B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_o.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_88675_A0)
     16     { /* SOC_REG_INT_OAMP_ARBITER_CONTROLr */
     17         soc_block_list[22],
     18         soc_genreg,
     19         1,
     20         0,
     21         0x6e1,
     22         0,
     23         0,
     24         3,
     25         soc_OAMP_ARBITER_CONTROLr_fields,
     26         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     27         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
     28         -1,
     29         -1,
     30     },
     31 #endif /* chips */
     32 
     33 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
     34     defined(BCM_56270_A0)
     35     { /* SOC_REG_INT_OAMP_ARBITER_CONTROL_BCM56260_A0r */
     36         soc_block_list[22],
     37         soc_genreg,
     38         1,
     39         0,
     40         0x2018200,
     41         0,
     42         0,
     43         3,
     44         soc_OAMP_ARBITER_CONTROL_BCM56260_A0r_fields,
     45         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     46         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
     47         -1,
     48         -1,
     49     },
     50 #endif /* chips */
     51 
     52 #if defined(BCM_88375_A0)
     53     { /* SOC_REG_INT_OAMP_ARBITER_CONTROL_BCM88375_A0r */
     54         soc_block_list[22],
     55         soc_genreg,
     56         1,
     57         0,
     58         0x6e1,
     59         0,
     60         0,
     61         3,
     62         soc_OAMP_ARBITER_CONTROL_BCM88375_A0r_fields,
     63         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     64         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
     65         -1,
     66         -1,
     67     },
     68 #endif /* chips */
     69 
     70 #if defined(BCM_88375_B0)
     71     { /* SOC_REG_INT_OAMP_ARBITER_CONTROL_BCM88375_B0r */
     72         soc_block_list[22],
     73         soc_genreg,
     74         1,
     75         0,
     76         0x6e1,
     77         0,
     78         0,
     79         3,
     80         soc_OAMP_ARBITER_CONTROL_BCM88375_B0r_fields,
     81         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     82         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
     83         -1,
     84         -1,
     85     },
     86 #endif /* chips */
     87 
     88 #if defined(BCM_88675_B0)
     89     { /* SOC_REG_INT_OAMP_ARBITER_CONTROL_BCM88675_B0r */
     90         soc_block_list[22],
     91         soc_genreg,
     92         1,
     93         0,
     94         0x6e1,
     95         0,
     96         0,
     97         3,
     98         soc_OAMP_ARBITER_CONTROL_BCM88675_B0r_fields,
     99         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    100         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    101         -1,
    102         -1,
    103     },
    104 #endif /* chips */
    105 
    106 #if defined(BCM_88680_A0)
    107     { /* SOC_REG_INT_OAMP_ARBITER_CONTROL_BCM88680_A0r */
    108         soc_block_list[22],
    109         soc_genreg,
    110         1,
    111         0,
    112         0x6e1,
    113         0,
    114         0,
    115         3,
    116         soc_OAMP_ARBITER_CONTROL_BCM88680_A0r_fields,
    117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    118         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    119         -1,
    120         -1,
    121     },
    122 #endif /* chips */
    123 
    124 #if defined(BCM_88690_A0)
    125     { /* SOC_REG_INT_OAMP_ARBITER_CONTROL_BCM88690_A0r */
    126         soc_block_list[22],
    127         soc_genreg,
    128         1,
    129         0,
    130         0x66b,
    131         0,
    132         0,
    133         3,
    134         soc_OAMP_ARBITER_CONTROL_BCM88690_A0r_fields,
    135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    136         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    137         -1,
    138         -1,
    139     },
    140 #endif /* chips */
    141 
    142 #if defined(BCM_88690_B0)
    143     { /* SOC_REG_INT_OAMP_ARBITER_CONTROL_BCM88690_B0r */
    144         soc_block_list[22],
    145         soc_genreg,
    146         1,
    147         0,
    148         0x66b,
    149         0,
    150         0,
    151         3,
    152         soc_OAMP_ARBITER_CONTROL_BCM88690_B0r_fields,
    153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    154         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    155         -1,
    156         -1,
    157     },
    158 #endif /* chips */
    159 
    160 #if defined(BCM_88660_A0)
    161     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHTr */
    162         soc_block_list[22],
    163         soc_genreg,
    164         1,
    165         0,
    166         0x5e1,
    167         0,
    168         0,
    169         5,
    170         soc_OAMP_ARBITER_WEIGHTr_fields,
    171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    172         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
    173         -1,
    174         -1,
    175     },
    176 #endif /* chips */
    177 
    178 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
    179     defined(BCM_56270_A0)
    180     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM56260_A0r */
    181         soc_block_list[22],
    182         soc_genreg,
    183         1,
    184         0,
    185         0x2018300,
    186         0,
    187         0,
    188         6,
    189         soc_OAMP_ARBITER_WEIGHT_BCM56260_A0r_fields,
    190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    191         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    192         -1,
    193         -1,
    194     },
    195 #endif /* chips */
    196 
    197 #if defined(BCM_88270_A0)
    198     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88270_A0r */
    199         soc_block_list[22],
    200         soc_genreg,
    201         1,
    202         0,
    203         0x6e1,
    204         0,
    205         0,
    206         7,
    207         soc_OAMP_ARBITER_WEIGHT_BCM88270_A0r_fields,
    208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    209         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
    210         -1,
    211         -1,
    212     },
    213 #endif /* chips */
    214 
    215 #if defined(BCM_88375_A0)
    216     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88375_A0r */
    217         soc_block_list[22],
    218         soc_genreg,
    219         1,
    220         0,
    221         0x6e2,
    222         0,
    223         0,
    224         6,
    225         soc_OAMP_ARBITER_WEIGHT_BCM88375_A0r_fields,
    226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    227         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    228         -1,
    229         -1,
    230     },
    231 #endif /* chips */
    232 
    233 #if defined(BCM_88375_B0)
    234     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88375_B0r */
    235         soc_block_list[22],
    236         soc_genreg,
    237         1,
    238         0,
    239         0x6e2,
    240         0,
    241         0,
    242         6,
    243         soc_OAMP_ARBITER_WEIGHT_BCM88375_B0r_fields,
    244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    245         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    246         -1,
    247         -1,
    248     },
    249 #endif /* chips */
    250 
    251 #if defined(BCM_88470_A0)
    252     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88470_A0r */
    253         soc_block_list[22],
    254         soc_genreg,
    255         1,
    256         0,
    257         0x6e1,
    258         0,
    259         0,
    260         7,
    261         soc_OAMP_ARBITER_WEIGHT_BCM88470_A0r_fields,
    262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    263         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
    264         -1,
    265         -1,
    266     },
    267 #endif /* chips */
    268 
    269 #if defined(BCM_88470_B0)
    270     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88470_B0r */
    271         soc_block_list[22],
    272         soc_genreg,
    273         1,
    274         0,
    275         0x6e1,
    276         0,
    277         0,
    278         7,
    279         soc_OAMP_ARBITER_WEIGHT_BCM88470_B0r_fields,
    280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    281         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
    282         -1,
    283         -1,
    284     },
    285 #endif /* chips */
    286 
    287 #if defined(BCM_88675_A0)
    288     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88675_A0r */
    289         soc_block_list[22],
    290         soc_genreg,
    291         1,
    292         0,
    293         0x6e2,
    294         0,
    295         0,
    296         6,
    297         soc_OAMP_ARBITER_WEIGHT_BCM88675_A0r_fields,
    298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    299         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    300         -1,
    301         -1,
    302     },
    303 #endif /* chips */
    304 
    305 #if defined(BCM_88675_B0)
    306     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88675_B0r */
    307         soc_block_list[22],
    308         soc_genreg,
    309         1,
    310         0,
    311         0x6e2,
    312         0,
    313         0,
    314         6,
    315         soc_OAMP_ARBITER_WEIGHT_BCM88675_B0r_fields,
    316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    317         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    318         -1,
    319         -1,
    320     },
    321 #endif /* chips */
    322 
    323 #if defined(BCM_88680_A0)
    324     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88680_A0r */
    325         soc_block_list[22],
    326         soc_genreg,
    327         1,
    328         0,
    329         0x6e2,
    330         0,
    331         0,
    332         6,
    333         soc_OAMP_ARBITER_WEIGHT_BCM88680_A0r_fields,
    334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    335         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    336         -1,
    337         -1,
    338     },
    339 #endif /* chips */
    340 
    341 #if defined(BCM_88690_A0)
    342     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88690_A0r */
    343         soc_block_list[22],
    344         soc_genreg,
    345         1,
    346         0,
    347         0x66c,
    348         0,
    349         0,
    350         7,
    351         soc_OAMP_ARBITER_WEIGHT_BCM88690_A0r_fields,
    352         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
    353         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
    354         -1,
    355         -1,
    356     },
    357 #endif /* chips */
    358 
    359 #if defined(BCM_88690_B0)
    360     { /* SOC_REG_INT_OAMP_ARBITER_WEIGHT_BCM88690_B0r */
    361         soc_block_list[22],
    362         soc_genreg,
    363         1,
    364         0,
    365         0x66c,
    366         0,
    367         0,
    368         7,
    369         soc_OAMP_ARBITER_WEIGHT_BCM88690_B0r_fields,
    370         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
    371         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
    372         -1,
    373         -1,
    374     },
    375 #endif /* chips */
    376 
    377 #if defined(BCM_88650_A0)
    378     { /* SOC_REG_INT_OAMP_BFDCC_TX_MPLSr */
    379         soc_block_list[22],
    380         soc_genreg,
    381         1,
    382         0,
    383         0x186,
    384         SOC_REG_FLAG_SIGNAL,
    385         0,
    386         2,
    387         soc_OAMP_BFDCC_TX_MPLSr_fields,
    388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    389         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
    390         -1,
    391         -1,
    392     },
    393 #endif /* chips */
    394 
    395 #if defined(BCM_88650_B0)
    396     { /* SOC_REG_INT_OAMP_BFDCC_TX_MPLS_BCM88650_B0r */
    397         soc_block_list[22],
    398         soc_genreg,
    399         1,
    400         0,
    401         0x186,
    402         SOC_REG_FLAG_SIGNAL,
    403         0,
    404         2,
    405         soc_OAMP_BFDCC_TX_MPLS_BCM88650_B0r_fields,
    406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    407         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
    408         -1,
    409         -1,
    410     },
    411 #endif /* chips */
    412 
    413 #if defined(BCM_88650_A0)
    414     { /* SOC_REG_INT_OAMP_BFDCV_TX_MPLSr */
    415         soc_block_list[22],
    416         soc_genreg,
    417         1,
    418         0,
    419         0x187,
    420         SOC_REG_FLAG_SIGNAL,
    421         0,
    422         2,
    423         soc_OAMP_BFDCV_TX_MPLSr_fields,
    424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    425         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
    426         -1,
    427         -1,
    428     },
    429 #endif /* chips */
    430 
    431 #if defined(BCM_88650_B0)
    432     { /* SOC_REG_INT_OAMP_BFDCV_TX_MPLS_BCM88650_B0r */
    433         soc_block_list[22],
    434         soc_genreg,
    435         1,
    436         0,
    437         0x187,
    438         SOC_REG_FLAG_SIGNAL,
    439         0,
    440         2,
    441         soc_OAMP_BFDCV_TX_MPLS_BCM88650_B0r_fields,
    442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    443         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
    444         -1,
    445         -1,
    446     },
    447 #endif /* chips */
    448 
    449 #if defined(BCM_88650_A0)
    450     { /* SOC_REG_INT_OAMP_BFD_CC_MPLSTP_GACHr */
    451         soc_block_list[22],
    452         soc_genreg,
    453         1,
    454         0,
    455         0x1b2,
    456         SOC_REG_FLAG_SIGNAL,
    457         0,
    458         1,
    459         soc_OAMP_BFD_CC_MPLSTP_GACHr_fields,
    460         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
    461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    462         -1,
    463         -1,
    464     },
    465 #endif /* chips */
    466 
    467 #if defined(BCM_88650_B0)
    468     { /* SOC_REG_INT_OAMP_BFD_CC_MPLSTP_GACH_BCM88650_B0r */
    469         soc_block_list[22],
    470         soc_genreg,
    471         1,
    472         0,
    473         0x1b2,
    474         SOC_REG_FLAG_SIGNAL,
    475         0,
    476         1,
    477         soc_OAMP_BFD_CC_MPLSTP_GACH_BCM88650_B0r_fields,
    478         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
    479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    480         -1,
    481         -1,
    482     },
    483 #endif /* chips */
    484 
    485 #if defined(BCM_88650_A0)
    486     { /* SOC_REG_INT_OAMP_BFD_CC_MPLSTP_GALr */
    487         soc_block_list[22],
    488         soc_genreg,
    489         1,
    490         0,
    491         0x1b1,
    492         SOC_REG_FLAG_SIGNAL,
    493         0,
    494         1,
    495         soc_OAMP_BFD_CC_MPLSTP_GALr_fields,
    496         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
    497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    498         -1,
    499         -1,
    500     },
    501 #endif /* chips */
    502 
    503 #if defined(BCM_88650_B0)
    504     { /* SOC_REG_INT_OAMP_BFD_CC_MPLSTP_GAL_BCM88650_B0r */
    505         soc_block_list[22],
    506         soc_genreg,
    507         1,
    508         0,
    509         0x1b1,
    510         SOC_REG_FLAG_SIGNAL,
    511         0,
    512         1,
    513         soc_OAMP_BFD_CC_MPLSTP_GAL_BCM88650_B0r_fields,
    514         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
    515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    516         -1,
    517         -1,
    518     },
    519 #endif /* chips */
    520 
    521 #if defined(BCM_88650_A0)
    522     { /* SOC_REG_INT_OAMP_BFD_CC_PACKETr */
    523         soc_block_list[22],
    524         soc_genreg,
    525         1,
    526         0,
    527         0x1b3,
    528         SOC_REG_FLAG_ABOVE_64_BITS |
    529                           SOC_REG_FLAG_SIGNAL,
    530         0,
    531         1,
    532         soc_OAMP_BFD_CC_PACKETr_fields,
    533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    534         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    535         -1,
    536         -1,
    537     },
    538 #endif /* chips */
    539 
    540 #if defined(BCM_88650_B0)
    541     { /* SOC_REG_INT_OAMP_BFD_CC_PACKET_BCM88650_B0r */
    542         soc_block_list[22],
    543         soc_genreg,
    544         1,
    545         0,
    546         0x1b3,
    547         SOC_REG_FLAG_ABOVE_64_BITS |
    548                           SOC_REG_FLAG_SIGNAL,
    549         0,
    550         1,
    551         soc_OAMP_BFD_CC_PACKET_BCM88650_B0r_fields,
    552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    554         -1,
    555         -1,
    556     },
    557 #endif /* chips */
    558 
    559 #if defined(BCM_88650_A0)
    560     { /* SOC_REG_INT_OAMP_BFD_CV_MPLSTP_GACHr */
    561         soc_block_list[22],
    562         soc_genreg,
    563         1,
    564         0,
    565         0x1ba,
    566         SOC_REG_FLAG_SIGNAL,
    567         0,
    568         1,
    569         soc_OAMP_BFD_CV_MPLSTP_GACHr_fields,
    570         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
    571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    572         -1,
    573         -1,
    574     },
    575 #endif /* chips */
    576 
    577 #if defined(BCM_88650_B0)
    578     { /* SOC_REG_INT_OAMP_BFD_CV_MPLSTP_GACH_BCM88650_B0r */
    579         soc_block_list[22],
    580         soc_genreg,
    581         1,
    582         0,
    583         0x1ba,
    584         SOC_REG_FLAG_SIGNAL,
    585         0,
    586         1,
    587         soc_OAMP_BFD_CV_MPLSTP_GACH_BCM88650_B0r_fields,
    588         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
    589         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    590         -1,
    591         -1,
    592     },
    593 #endif /* chips */
    594 
    595 #if defined(BCM_88650_A0)
    596     { /* SOC_REG_INT_OAMP_BFD_CV_MPLSTP_GALr */
    597         soc_block_list[22],
    598         soc_genreg,
    599         1,
    600         0,
    601         0x1b9,
    602         SOC_REG_FLAG_SIGNAL,
    603         0,
    604         1,
    605         soc_OAMP_BFD_CV_MPLSTP_GALr_fields,
    606         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
    607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    608         -1,
    609         -1,
    610     },
    611 #endif /* chips */
    612 
    613 #if defined(BCM_88650_B0)
    614     { /* SOC_REG_INT_OAMP_BFD_CV_MPLSTP_GAL_BCM88650_B0r */
    615         soc_block_list[22],
    616         soc_genreg,
    617         1,
    618         0,
    619         0x1b9,
    620         SOC_REG_FLAG_SIGNAL,
    621         0,
    622         1,
    623         soc_OAMP_BFD_CV_MPLSTP_GAL_BCM88650_B0r_fields,
    624         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
    625         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    626         -1,
    627         -1,
    628     },
    629 #endif /* chips */
    630 
    631 #if defined(BCM_88650_A0)
    632     { /* SOC_REG_INT_OAMP_BFD_CV_MPLSTP_MEPID_TLV_TYPEr */
    633         soc_block_list[22],
    634         soc_genreg,
    635         1,
    636         0,
    637         0x1bc,
    638         SOC_REG_FLAG_SIGNAL,
    639         0,
    640         1,
    641         soc_OAMP_BFD_CV_MPLSTP_MEPID_TLV_TYPEr_fields,
    642         SOC_RESET_VAL_DEC(0x00001234, 0x00000000)
    643         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    644         -1,
    645         -1,
    646     },
    647 #endif /* chips */
    648 
    649 #if defined(BCM_88650_B0)
    650     { /* SOC_REG_INT_OAMP_BFD_CV_MPLSTP_MEPID_TLV_TYPE_BCM88650_B0r */
    651         soc_block_list[22],
    652         soc_genreg,
    653         1,
    654         0,
    655         0x1bc,
    656         SOC_REG_FLAG_SIGNAL,
    657         0,
    658         1,
    659         soc_OAMP_BFD_CV_MPLSTP_MEPID_TLV_TYPE_BCM88650_B0r_fields,
    660         SOC_RESET_VAL_DEC(0x00001234, 0x00000000)
    661         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    662         -1,
    663         -1,
    664     },
    665 #endif /* chips */
    666 
    667 #if defined(BCM_88650_A0)
    668     { /* SOC_REG_INT_OAMP_BFD_CV_MPLSTP_TLV_HEADERr */
    669         soc_block_list[22],
    670         soc_genreg,
    671         1,
    672         0,
    673         0x1bb,
    674         SOC_REG_FLAG_SIGNAL,
    675         0,
    676         1,
    677         soc_OAMP_BFD_CV_MPLSTP_TLV_HEADERr_fields,
    678         SOC_RESET_VAL_DEC(0x00080000, 0x00000000)
    679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    680         -1,
    681         -1,
    682     },
    683 #endif /* chips */
    684 
    685 #if defined(BCM_88650_B0)
    686     { /* SOC_REG_INT_OAMP_BFD_CV_MPLSTP_TLV_HEADER_BCM88650_B0r */
    687         soc_block_list[22],
    688         soc_genreg,
    689         1,
    690         0,
    691         0x1bb,
    692         SOC_REG_FLAG_SIGNAL,
    693         0,
    694         1,
    695         soc_OAMP_BFD_CV_MPLSTP_TLV_HEADER_BCM88650_B0r_fields,
    696         SOC_RESET_VAL_DEC(0x00080000, 0x00000000)
    697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    698         -1,
    699         -1,
    700     },
    701 #endif /* chips */
    702 
    703 #if defined(BCM_88650_A0)
    704     { /* SOC_REG_INT_OAMP_BFD_CV_PACKETr */
    705         soc_block_list[22],
    706         soc_genreg,
    707         1,
    708         0,
    709         0x1bd,
    710         SOC_REG_FLAG_ABOVE_64_BITS |
    711                           SOC_REG_FLAG_SIGNAL,
    712         0,
    713         1,
    714         soc_OAMP_BFD_CV_PACKETr_fields,
    715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    716         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    717         -1,
    718         -1,
    719     },
    720 #endif /* chips */
    721 
    722 #if defined(BCM_88650_B0)
    723     { /* SOC_REG_INT_OAMP_BFD_CV_PACKET_BCM88650_B0r */
    724         soc_block_list[22],
    725         soc_genreg,
    726         1,
    727         0,
    728         0x1bd,
    729         SOC_REG_FLAG_ABOVE_64_BITS |
    730                           SOC_REG_FLAG_SIGNAL,
    731         0,
    732         1,
    733         soc_OAMP_BFD_CV_PACKET_BCM88650_B0r_fields,
    734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    736         -1,
    737         -1,
    738     },
    739 #endif /* chips */
    740 
    741 #if defined(BCM_88660_A0)
    742     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILEr */
    743         soc_block_list[22],
    744         soc_genreg,
    745         1,
    746         0,
    747         0x440,
    748         SOC_REG_FLAG_ABOVE_64_BITS |
    749                           SOC_REG_FLAG_SIGNAL,
    750         0,
    751         16,
    752         soc_OAMP_BFD_DIAG_PROFILEr_fields,
    753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    754         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    755         -1,
    756         -1,
    757     },
    758 #endif /* chips */
    759 
    760 #if defined(BCM_88270_A0)
    761     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88270_A0r */
    762         soc_block_list[22],
    763         soc_genreg,
    764         1,
    765         0,
    766         0x448,
    767         SOC_REG_FLAG_ABOVE_64_BITS,
    768         0,
    769         16,
    770         soc_OAMP_BFD_DIAG_PROFILE_BCM88270_A0r_fields,
    771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    773         -1,
    774         -1,
    775     },
    776 #endif /* chips */
    777 
    778 #if defined(BCM_88375_A0)
    779     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88375_A0r */
    780         soc_block_list[22],
    781         soc_genreg,
    782         1,
    783         0,
    784         0x445,
    785         SOC_REG_FLAG_ABOVE_64_BITS,
    786         0,
    787         16,
    788         soc_OAMP_BFD_DIAG_PROFILE_BCM88375_A0r_fields,
    789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    791         -1,
    792         -1,
    793     },
    794 #endif /* chips */
    795 
    796 #if defined(BCM_88375_B0)
    797     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88375_B0r */
    798         soc_block_list[22],
    799         soc_genreg,
    800         1,
    801         0,
    802         0x445,
    803         SOC_REG_FLAG_ABOVE_64_BITS,
    804         0,
    805         16,
    806         soc_OAMP_BFD_DIAG_PROFILE_BCM88375_B0r_fields,
    807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    808         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    809         -1,
    810         -1,
    811     },
    812 #endif /* chips */
    813 
    814 #if defined(BCM_88470_A0)
    815     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88470_A0r */
    816         soc_block_list[22],
    817         soc_genreg,
    818         1,
    819         0,
    820         0x448,
    821         SOC_REG_FLAG_ABOVE_64_BITS,
    822         0,
    823         16,
    824         soc_OAMP_BFD_DIAG_PROFILE_BCM88470_A0r_fields,
    825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    826         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    827         -1,
    828         -1,
    829     },
    830 #endif /* chips */
    831 
    832 #if defined(BCM_88470_B0)
    833     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88470_B0r */
    834         soc_block_list[22],
    835         soc_genreg,
    836         1,
    837         0,
    838         0x448,
    839         SOC_REG_FLAG_ABOVE_64_BITS,
    840         0,
    841         16,
    842         soc_OAMP_BFD_DIAG_PROFILE_BCM88470_B0r_fields,
    843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    844         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    845         -1,
    846         -1,
    847     },
    848 #endif /* chips */
    849 
    850 #if defined(BCM_88675_A0)
    851     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88675_A0r */
    852         soc_block_list[22],
    853         soc_genreg,
    854         1,
    855         0,
    856         0x445,
    857         SOC_REG_FLAG_ABOVE_64_BITS,
    858         0,
    859         16,
    860         soc_OAMP_BFD_DIAG_PROFILE_BCM88675_A0r_fields,
    861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    862         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    863         -1,
    864         -1,
    865     },
    866 #endif /* chips */
    867 
    868 #if defined(BCM_88675_B0)
    869     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88675_B0r */
    870         soc_block_list[22],
    871         soc_genreg,
    872         1,
    873         0,
    874         0x445,
    875         SOC_REG_FLAG_ABOVE_64_BITS,
    876         0,
    877         16,
    878         soc_OAMP_BFD_DIAG_PROFILE_BCM88675_B0r_fields,
    879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    880         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    881         -1,
    882         -1,
    883     },
    884 #endif /* chips */
    885 
    886 #if defined(BCM_88680_A0)
    887     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88680_A0r */
    888         soc_block_list[22],
    889         soc_genreg,
    890         1,
    891         0,
    892         0x445,
    893         SOC_REG_FLAG_ABOVE_64_BITS,
    894         0,
    895         16,
    896         soc_OAMP_BFD_DIAG_PROFILE_BCM88680_A0r_fields,
    897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    899         -1,
    900         -1,
    901     },
    902 #endif /* chips */
    903 
    904 #if defined(BCM_88690_A0)
    905     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88690_A0r */
    906         soc_block_list[22],
    907         soc_genreg,
    908         1,
    909         0,
    910         0x538,
    911         SOC_REG_FLAG_ABOVE_64_BITS,
    912         0,
    913         16,
    914         soc_OAMP_BFD_DIAG_PROFILE_BCM88690_A0r_fields,
    915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    916         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    917         -1,
    918         -1,
    919     },
    920 #endif /* chips */
    921 
    922 #if defined(BCM_88690_B0)
    923     { /* SOC_REG_INT_OAMP_BFD_DIAG_PROFILE_BCM88690_B0r */
    924         soc_block_list[22],
    925         soc_genreg,
    926         1,
    927         0,
    928         0x538,
    929         SOC_REG_FLAG_ABOVE_64_BITS,
    930         0,
    931         16,
    932         soc_OAMP_BFD_DIAG_PROFILE_BCM88690_B0r_fields,
    933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    934         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    935         -1,
    936         -1,
    937     },
    938 #endif /* chips */
    939 
    940 #if defined(BCM_88650_A0)
    941     { /* SOC_REG_INT_OAMP_BFD_EMC_CONSTr */
    942         soc_block_list[22],
    943         soc_genreg,
    944         1,
    945         0,
    946         0x164,
    947         SOC_REG_FLAG_64_BITS |
    948                           SOC_REG_FLAG_SIGNAL,
    949         0,
    950         4,
    951         soc_OAMP_BFD_EMC_CONSTr_fields,
    952         SOC_RESET_VAL_DEC(0x00010000, 0x00030002)
    953         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
    954         -1,
    955         -1,
    956     },
    957 #endif /* chips */
    958 
    959 #if defined(BCM_88270_A0)
    960     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88270_A0r */
    961         soc_block_list[22],
    962         soc_genreg,
    963         1,
    964         0,
    965         0x196,
    966         SOC_REG_FLAG_64_BITS,
    967         0,
    968         3,
    969         soc_OAMP_BFD_EMC_CONST_BCM88270_A0r_fields,
    970         SOC_RESET_VAL_DEC(0x00010000, 0x00000002)
    971         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
    972         -1,
    973         -1,
    974     },
    975 #endif /* chips */
    976 
    977 #if defined(BCM_88375_A0)
    978     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88375_A0r */
    979         soc_block_list[22],
    980         soc_genreg,
    981         1,
    982         0,
    983         0x189,
    984         SOC_REG_FLAG_64_BITS,
    985         0,
    986         4,
    987         soc_OAMP_BFD_EMC_CONST_BCM88375_A0r_fields,
    988         SOC_RESET_VAL_DEC(0x00010000, 0x00030002)
    989         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
    990         -1,
    991         -1,
    992     },
    993 #endif /* chips */
    994 
    995 #if defined(BCM_88375_B0)
    996     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88375_B0r */
    997         soc_block_list[22],
    998         soc_genreg,
    999         1,
   1000         0,
   1001         0x189,
   1002         SOC_REG_FLAG_64_BITS,
   1003         0,
   1004         4,
   1005         soc_OAMP_BFD_EMC_CONST_BCM88375_B0r_fields,
   1006         SOC_RESET_VAL_DEC(0x00010000, 0x00030002)
   1007         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   1008         -1,
   1009         -1,
   1010     },
   1011 #endif /* chips */
   1012 
   1013 #if defined(BCM_88470_A0)
   1014     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88470_A0r */
   1015         soc_block_list[22],
   1016         soc_genreg,
   1017         1,
   1018         0,
   1019         0x196,
   1020         SOC_REG_FLAG_64_BITS,
   1021         0,
   1022         3,
   1023         soc_OAMP_BFD_EMC_CONST_BCM88470_A0r_fields,
   1024         SOC_RESET_VAL_DEC(0x00010000, 0x00000002)
   1025         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1026         -1,
   1027         -1,
   1028     },
   1029 #endif /* chips */
   1030 
   1031 #if defined(BCM_88470_B0)
   1032     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88470_B0r */
   1033         soc_block_list[22],
   1034         soc_genreg,
   1035         1,
   1036         0,
   1037         0x196,
   1038         SOC_REG_FLAG_64_BITS,
   1039         0,
   1040         3,
   1041         soc_OAMP_BFD_EMC_CONST_BCM88470_B0r_fields,
   1042         SOC_RESET_VAL_DEC(0x00010000, 0x00000002)
   1043         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1044         -1,
   1045         -1,
   1046     },
   1047 #endif /* chips */
   1048 
   1049 #if defined(BCM_88650_B0)
   1050     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88650_B0r */
   1051         soc_block_list[22],
   1052         soc_genreg,
   1053         1,
   1054         0,
   1055         0x164,
   1056         SOC_REG_FLAG_64_BITS |
   1057                           SOC_REG_FLAG_SIGNAL,
   1058         0,
   1059         4,
   1060         soc_OAMP_BFD_EMC_CONST_BCM88650_B0r_fields,
   1061         SOC_RESET_VAL_DEC(0x00010000, 0x00030002)
   1062         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   1063         -1,
   1064         -1,
   1065     },
   1066 #endif /* chips */
   1067 
   1068 #if defined(BCM_88660_A0)
   1069     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88660_A0r */
   1070         soc_block_list[22],
   1071         soc_genreg,
   1072         1,
   1073         0,
   1074         0x184,
   1075         SOC_REG_FLAG_64_BITS |
   1076                           SOC_REG_FLAG_SIGNAL,
   1077         0,
   1078         4,
   1079         soc_OAMP_BFD_EMC_CONST_BCM88660_A0r_fields,
   1080         SOC_RESET_VAL_DEC(0x00010000, 0x00030002)
   1081         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   1082         -1,
   1083         -1,
   1084     },
   1085 #endif /* chips */
   1086 
   1087 #if defined(BCM_88675_A0)
   1088     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88675_A0r */
   1089         soc_block_list[22],
   1090         soc_genreg,
   1091         1,
   1092         0,
   1093         0x189,
   1094         SOC_REG_FLAG_64_BITS,
   1095         0,
   1096         4,
   1097         soc_OAMP_BFD_EMC_CONST_BCM88675_A0r_fields,
   1098         SOC_RESET_VAL_DEC(0x00010000, 0x00030002)
   1099         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   1100         -1,
   1101         -1,
   1102     },
   1103 #endif /* chips */
   1104 
   1105 #if defined(BCM_88675_B0)
   1106     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88675_B0r */
   1107         soc_block_list[22],
   1108         soc_genreg,
   1109         1,
   1110         0,
   1111         0x189,
   1112         SOC_REG_FLAG_64_BITS,
   1113         0,
   1114         4,
   1115         soc_OAMP_BFD_EMC_CONST_BCM88675_B0r_fields,
   1116         SOC_RESET_VAL_DEC(0x00010000, 0x00030002)
   1117         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   1118         -1,
   1119         -1,
   1120     },
   1121 #endif /* chips */
   1122 
   1123 #if defined(BCM_88680_A0)
   1124     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88680_A0r */
   1125         soc_block_list[22],
   1126         soc_genreg,
   1127         1,
   1128         0,
   1129         0x189,
   1130         SOC_REG_FLAG_64_BITS,
   1131         0,
   1132         4,
   1133         soc_OAMP_BFD_EMC_CONST_BCM88680_A0r_fields,
   1134         SOC_RESET_VAL_DEC(0x00010000, 0x00030002)
   1135         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   1136         -1,
   1137         -1,
   1138     },
   1139 #endif /* chips */
   1140 
   1141 #if defined(BCM_88690_A0)
   1142     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88690_A0r */
   1143         soc_block_list[22],
   1144         soc_genreg,
   1145         1,
   1146         0,
   1147         0x193,
   1148         SOC_REG_FLAG_64_BITS,
   1149         0,
   1150         3,
   1151         soc_OAMP_BFD_EMC_CONST_BCM88690_A0r_fields,
   1152         SOC_RESET_VAL_DEC(0x00010000, 0x00000002)
   1153         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1154         -1,
   1155         -1,
   1156     },
   1157 #endif /* chips */
   1158 
   1159 #if defined(BCM_88690_B0)
   1160     { /* SOC_REG_INT_OAMP_BFD_EMC_CONST_BCM88690_B0r */
   1161         soc_block_list[22],
   1162         soc_genreg,
   1163         1,
   1164         0,
   1165         0x193,
   1166         SOC_REG_FLAG_64_BITS,
   1167         0,
   1168         3,
   1169         soc_OAMP_BFD_EMC_CONST_BCM88690_B0r_fields,
   1170         SOC_RESET_VAL_DEC(0x00010000, 0x00000002)
   1171         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1172         -1,
   1173         -1,
   1174     },
   1175 #endif /* chips */
   1176 
   1177 #if defined(BCM_88660_A0)
   1178     { /* SOC_REG_INT_OAMP_BFD_FLADS_PROFILEr */
   1179         soc_block_list[22],
   1180         soc_genreg,
   1181         1,
   1182         0,
   1183         0x443,
   1184         SOC_REG_FLAG_64_BITS |
   1185                           SOC_REG_FLAG_SIGNAL,
   1186         0,
   1187         8,
   1188         soc_OAMP_BFD_FLADS_PROFILEr_fields,
   1189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1190         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1191         -1,
   1192         -1,
   1193     },
   1194 #endif /* chips */
   1195 
   1196 #if defined(BCM_88270_A0)
   1197     { /* SOC_REG_INT_OAMP_BFD_FLADS_PROFILE_BCM88270_A0r */
   1198         soc_block_list[22],
   1199         soc_genreg,
   1200         1,
   1201         0,
   1202         0x44b,
   1203         SOC_REG_FLAG_64_BITS,
   1204         0,
   1205         8,
   1206         soc_OAMP_BFD_FLADS_PROFILE_BCM88270_A0r_fields,
   1207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1208         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1209         -1,
   1210         -1,
   1211     },
   1212 #endif /* chips */
   1213 
   1214 #if defined(BCM_88375_A0)
   1215     { /* SOC_REG_INT_OAMP_BFD_FLADS_PROFILE_BCM88375_A0r */
   1216         soc_block_list[22],
   1217         soc_genreg,
   1218         1,
   1219         0,
   1220         0x448,
   1221         SOC_REG_FLAG_64_BITS,
   1222         0,
   1223         8,
   1224         soc_OAMP_BFD_FLADS_PROFILE_BCM88375_A0r_fields,
   1225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1226         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1227         -1,
   1228         -1,
   1229     },
   1230 #endif /* chips */
   1231 
   1232 #if defined(BCM_88375_B0)
   1233     { /* SOC_REG_INT_OAMP_BFD_FLADS_PROFILE_BCM88375_B0r */
   1234         soc_block_list[22],
   1235         soc_genreg,
   1236         1,
   1237         0,
   1238         0x448,
   1239         SOC_REG_FLAG_64_BITS,
   1240         0,
   1241         8,
   1242         soc_OAMP_BFD_FLADS_PROFILE_BCM88375_B0r_fields,
   1243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1244         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1245         -1,
   1246         -1,
   1247     },
   1248 #endif /* chips */
   1249 
   1250 #if defined(BCM_88470_A0)
   1251     { /* SOC_REG_INT_OAMP_BFD_FLADS_PROFILE_BCM88470_A0r */
   1252         soc_block_list[22],
   1253         soc_genreg,
   1254         1,
   1255         0,
   1256         0x44b,
   1257         SOC_REG_FLAG_64_BITS,
   1258         0,
   1259         8,
   1260         soc_OAMP_BFD_FLADS_PROFILE_BCM88470_A0r_fields,
   1261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1262         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1263         -1,
   1264         -1,
   1265     },
   1266 #endif /* chips */
   1267 
   1268 #if defined(BCM_88470_B0)
   1269     { /* SOC_REG_INT_OAMP_BFD_FLADS_PROFILE_BCM88470_B0r */
   1270         soc_block_list[22],
   1271         soc_genreg,
   1272         1,
   1273         0,
   1274         0x44b,
   1275         SOC_REG_FLAG_64_BITS,
   1276         0,
   1277         8,
   1278         soc_OAMP_BFD_FLADS_PROFILE_BCM88470_B0r_fields,
   1279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1280         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1281         -1,
   1282         -1,
   1283     },
   1284 #endif /* chips */
   1285 
   1286 #if defined(BCM_88675_A0)
   1287     { /* SOC_REG_INT_OAMP_BFD_FLADS_PROFILE_BCM88675_A0r */
   1288         soc_block_list[22],
   1289         soc_genreg,
   1290         1,
   1291         0,
   1292         0x448,
   1293         SOC_REG_FLAG_64_BITS,
   1294         0,
   1295         8,
   1296         soc_OAMP_BFD_FLADS_PROFILE_BCM88675_A0r_fields,
   1297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1298         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1299         -1,
   1300         -1,
   1301     },
   1302 #endif /* chips */
   1303 
   1304 #if defined(BCM_88675_B0)
   1305     { /* SOC_REG_INT_OAMP_BFD_FLADS_PROFILE_BCM88675_B0r */
   1306         soc_block_list[22],
   1307         soc_genreg,
   1308         1,
   1309         0,
   1310         0x448,
   1311         SOC_REG_FLAG_64_BITS,
   1312         0,
   1313         8,
   1314         soc_OAMP_BFD_FLADS_PROFILE_BCM88675_B0r_fields,
   1315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1316         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1317         -1,
   1318         -1,
   1319     },
   1320 #endif /* chips */
   1321 
   1322 #if defined(BCM_88680_A0)
   1323     { /* SOC_REG_INT_OAMP_BFD_FLADS_PROFILE_BCM88680_A0r */
   1324         soc_block_list[22],
   1325         soc_genreg,
   1326         1,
   1327         0,
   1328         0x448,
   1329         SOC_REG_FLAG_64_BITS,
   1330         0,
   1331         8,
   1332         soc_OAMP_BFD_FLADS_PROFILE_BCM88680_A0r_fields,
   1333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1334         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1335         -1,
   1336         -1,
   1337     },
   1338 #endif /* chips */
   1339 
   1340 #if defined(BCM_88690_A0)
   1341     { /* SOC_REG_INT_OAMP_BFD_FLAGS_PROFILEr */
   1342         soc_block_list[22],
   1343         soc_genreg,
   1344         1,
   1345         0,
   1346         0x53b,
   1347         SOC_REG_FLAG_ABOVE_64_BITS,
   1348         0,
   1349         16,
   1350         soc_OAMP_BFD_FLAGS_PROFILEr_fields,
   1351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1352         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1353         -1,
   1354         -1,
   1355     },
   1356 #endif /* chips */
   1357 
   1358 #if defined(BCM_88690_B0)
   1359     { /* SOC_REG_INT_OAMP_BFD_FLAGS_PROFILE_BCM88690_B0r */
   1360         soc_block_list[22],
   1361         soc_genreg,
   1362         1,
   1363         0,
   1364         0x53b,
   1365         SOC_REG_FLAG_ABOVE_64_BITS,
   1366         0,
   1367         16,
   1368         soc_OAMP_BFD_FLAGS_PROFILE_BCM88690_B0r_fields,
   1369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1370         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1371         -1,
   1372         -1,
   1373     },
   1374 #endif /* chips */
   1375 
   1376 #if defined(BCM_88650_A0)
   1377     { /* SOC_REG_INT_OAMP_BFD_IPV4_CONTROLr */
   1378         soc_block_list[22],
   1379         soc_genreg,
   1380         1,
   1381         0,
   1382         0x161,
   1383         SOC_REG_FLAG_SIGNAL,
   1384         0,
   1385         4,
   1386         soc_OAMP_BFD_IPV4_CONTROLr_fields,
   1387         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   1388         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1389         -1,
   1390         -1,
   1391     },
   1392 #endif /* chips */
   1393 
   1394 #if defined(BCM_88375_A0)
   1395     { /* SOC_REG_INT_OAMP_BFD_IPV4_CONTROL_BCM88375_A0r */
   1396         soc_block_list[22],
   1397         soc_genreg,
   1398         1,
   1399         0,
   1400         0x186,
   1401         0,
   1402         0,
   1403         4,
   1404         soc_OAMP_BFD_IPV4_CONTROL_BCM88375_A0r_fields,
   1405         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   1406         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1407         -1,
   1408         -1,
   1409     },
   1410 #endif /* chips */
   1411 
   1412 #if defined(BCM_88375_B0)
   1413     { /* SOC_REG_INT_OAMP_BFD_IPV4_CONTROL_BCM88375_B0r */
   1414         soc_block_list[22],
   1415         soc_genreg,
   1416         1,
   1417         0,
   1418         0x186,
   1419         0,
   1420         0,
   1421         4,
   1422         soc_OAMP_BFD_IPV4_CONTROL_BCM88375_B0r_fields,
   1423         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   1424         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1425         -1,
   1426         -1,
   1427     },
   1428 #endif /* chips */
   1429 
   1430 #if defined(BCM_88650_B0)
   1431     { /* SOC_REG_INT_OAMP_BFD_IPV4_CONTROL_BCM88650_B0r */
   1432         soc_block_list[22],
   1433         soc_genreg,
   1434         1,
   1435         0,
   1436         0x161,
   1437         SOC_REG_FLAG_SIGNAL,
   1438         0,
   1439         4,
   1440         soc_OAMP_BFD_IPV4_CONTROL_BCM88650_B0r_fields,
   1441         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   1442         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1443         -1,
   1444         -1,
   1445     },
   1446 #endif /* chips */
   1447 
   1448 #if defined(BCM_88660_A0)
   1449     { /* SOC_REG_INT_OAMP_BFD_IPV4_CONTROL_BCM88660_A0r */
   1450         soc_block_list[22],
   1451         soc_genreg,
   1452         1,
   1453         0,
   1454         0x181,
   1455         SOC_REG_FLAG_SIGNAL,
   1456         0,
   1457         4,
   1458         soc_OAMP_BFD_IPV4_CONTROL_BCM88660_A0r_fields,
   1459         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   1460         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1461         -1,
   1462         -1,
   1463     },
   1464 #endif /* chips */
   1465 
   1466 #if defined(BCM_88675_A0)
   1467     { /* SOC_REG_INT_OAMP_BFD_IPV4_CONTROL_BCM88675_A0r */
   1468         soc_block_list[22],
   1469         soc_genreg,
   1470         1,
   1471         0,
   1472         0x186,
   1473         0,
   1474         0,
   1475         4,
   1476         soc_OAMP_BFD_IPV4_CONTROL_BCM88675_A0r_fields,
   1477         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   1478         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1479         -1,
   1480         -1,
   1481     },
   1482 #endif /* chips */
   1483 
   1484 #if defined(BCM_88675_B0)
   1485     { /* SOC_REG_INT_OAMP_BFD_IPV4_CONTROL_BCM88675_B0r */
   1486         soc_block_list[22],
   1487         soc_genreg,
   1488         1,
   1489         0,
   1490         0x186,
   1491         0,
   1492         0,
   1493         4,
   1494         soc_OAMP_BFD_IPV4_CONTROL_BCM88675_B0r_fields,
   1495         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   1496         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1497         -1,
   1498         -1,
   1499     },
   1500 #endif /* chips */
   1501 
   1502 #if defined(BCM_88680_A0)
   1503     { /* SOC_REG_INT_OAMP_BFD_IPV4_CONTROL_BCM88680_A0r */
   1504         soc_block_list[22],
   1505         soc_genreg,
   1506         1,
   1507         0,
   1508         0x186,
   1509         0,
   1510         0,
   1511         4,
   1512         soc_OAMP_BFD_IPV4_CONTROL_BCM88680_A0r_fields,
   1513         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   1514         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1515         -1,
   1516         -1,
   1517     },
   1518 #endif /* chips */
   1519 
   1520 #if defined(BCM_88690_B0)
   1521     { /* SOC_REG_INT_OAMP_BFD_IPV4_ONE_HOP_TOSr */
   1522         soc_block_list[22],
   1523         soc_genreg,
   1524         1,
   1525         0,
   1526         0xb2f,
   1527         0,
   1528         0,
   1529         3,
   1530         soc_OAMP_BFD_IPV4_ONE_HOP_TOSr_fields,
   1531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1532         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   1533         -1,
   1534         -1,
   1535     },
   1536 #endif /* chips */
   1537 
   1538 #if defined(BCM_88650_A0)
   1539     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTERr */
   1540         soc_block_list[22],
   1541         soc_genreg,
   1542         1,
   1543         0,
   1544         0x194,
   1545         SOC_REG_FLAG_SIGNAL,
   1546         0,
   1547         3,
   1548         soc_OAMP_BFD_IPV4_STATIC_REGISTERr_fields,
   1549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1550         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1551         -1,
   1552         -1,
   1553     },
   1554 #endif /* chips */
   1555 
   1556 #if defined(BCM_88270_A0)
   1557     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88270_A0r */
   1558         soc_block_list[22],
   1559         soc_genreg,
   1560         1,
   1561         0,
   1562         0x415,
   1563         0,
   1564         0,
   1565         3,
   1566         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88270_A0r_fields,
   1567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1568         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1569         -1,
   1570         -1,
   1571     },
   1572 #endif /* chips */
   1573 
   1574 #if defined(BCM_88375_A0)
   1575     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88375_A0r */
   1576         soc_block_list[22],
   1577         soc_genreg,
   1578         1,
   1579         0,
   1580         0x413,
   1581         0,
   1582         0,
   1583         3,
   1584         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88375_A0r_fields,
   1585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1586         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1587         -1,
   1588         -1,
   1589     },
   1590 #endif /* chips */
   1591 
   1592 #if defined(BCM_88375_B0)
   1593     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88375_B0r */
   1594         soc_block_list[22],
   1595         soc_genreg,
   1596         1,
   1597         0,
   1598         0x413,
   1599         0,
   1600         0,
   1601         3,
   1602         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88375_B0r_fields,
   1603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1604         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1605         -1,
   1606         -1,
   1607     },
   1608 #endif /* chips */
   1609 
   1610 #if defined(BCM_88470_A0)
   1611     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88470_A0r */
   1612         soc_block_list[22],
   1613         soc_genreg,
   1614         1,
   1615         0,
   1616         0x415,
   1617         0,
   1618         0,
   1619         3,
   1620         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88470_A0r_fields,
   1621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1622         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1623         -1,
   1624         -1,
   1625     },
   1626 #endif /* chips */
   1627 
   1628 #if defined(BCM_88470_B0)
   1629     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88470_B0r */
   1630         soc_block_list[22],
   1631         soc_genreg,
   1632         1,
   1633         0,
   1634         0x415,
   1635         0,
   1636         0,
   1637         3,
   1638         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88470_B0r_fields,
   1639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1640         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1641         -1,
   1642         -1,
   1643     },
   1644 #endif /* chips */
   1645 
   1646 #if defined(BCM_88650_B0)
   1647     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88650_B0r */
   1648         soc_block_list[22],
   1649         soc_genreg,
   1650         1,
   1651         0,
   1652         0x194,
   1653         SOC_REG_FLAG_SIGNAL,
   1654         0,
   1655         3,
   1656         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88650_B0r_fields,
   1657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1658         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1659         -1,
   1660         -1,
   1661     },
   1662 #endif /* chips */
   1663 
   1664 #if defined(BCM_88660_A0)
   1665     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88660_A0r */
   1666         soc_block_list[22],
   1667         soc_genreg,
   1668         1,
   1669         0,
   1670         0x412,
   1671         SOC_REG_FLAG_SIGNAL,
   1672         0,
   1673         3,
   1674         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88660_A0r_fields,
   1675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1676         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1677         -1,
   1678         -1,
   1679     },
   1680 #endif /* chips */
   1681 
   1682 #if defined(BCM_88675_A0)
   1683     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88675_A0r */
   1684         soc_block_list[22],
   1685         soc_genreg,
   1686         1,
   1687         0,
   1688         0x413,
   1689         0,
   1690         0,
   1691         3,
   1692         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88675_A0r_fields,
   1693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1694         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1695         -1,
   1696         -1,
   1697     },
   1698 #endif /* chips */
   1699 
   1700 #if defined(BCM_88675_B0)
   1701     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88675_B0r */
   1702         soc_block_list[22],
   1703         soc_genreg,
   1704         1,
   1705         0,
   1706         0x413,
   1707         0,
   1708         0,
   1709         3,
   1710         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88675_B0r_fields,
   1711         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1712         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1713         -1,
   1714         -1,
   1715     },
   1716 #endif /* chips */
   1717 
   1718 #if defined(BCM_88680_A0)
   1719     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88680_A0r */
   1720         soc_block_list[22],
   1721         soc_genreg,
   1722         1,
   1723         0,
   1724         0x413,
   1725         0,
   1726         0,
   1727         3,
   1728         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88680_A0r_fields,
   1729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1730         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1731         -1,
   1732         -1,
   1733     },
   1734 #endif /* chips */
   1735 
   1736 #if defined(BCM_88690_A0)
   1737     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88690_A0r */
   1738         soc_block_list[22],
   1739         soc_genreg,
   1740         1,
   1741         0,
   1742         0x415,
   1743         0,
   1744         0,
   1745         3,
   1746         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88690_A0r_fields,
   1747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1748         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1749         -1,
   1750         -1,
   1751     },
   1752 #endif /* chips */
   1753 
   1754 #if defined(BCM_88690_B0)
   1755     { /* SOC_REG_INT_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88690_B0r */
   1756         soc_block_list[22],
   1757         soc_genreg,
   1758         1,
   1759         0,
   1760         0x415,
   1761         0,
   1762         0,
   1763         3,
   1764         soc_OAMP_BFD_IPV4_STATIC_REGISTER_BCM88690_B0r_fields,
   1765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1766         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1767         -1,
   1768         -1,
   1769     },
   1770 #endif /* chips */
   1771 
   1772 #if defined(BCM_88650_A0)
   1773     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORTr */
   1774         soc_block_list[22],
   1775         soc_genreg,
   1776         1,
   1777         0,
   1778         0x1ad,
   1779         SOC_REG_FLAG_SIGNAL,
   1780         0,
   1781         1,
   1782         soc_OAMP_BFD_IPV4_UDP_SPORTr_fields,
   1783         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1784         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1785         -1,
   1786         -1,
   1787     },
   1788 #endif /* chips */
   1789 
   1790 #if defined(BCM_88270_A0)
   1791     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88270_A0r */
   1792         soc_block_list[22],
   1793         soc_genreg,
   1794         1,
   1795         0,
   1796         0x42e,
   1797         0,
   1798         0,
   1799         1,
   1800         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88270_A0r_fields,
   1801         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1802         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1803         -1,
   1804         -1,
   1805     },
   1806 #endif /* chips */
   1807 
   1808 #if defined(BCM_88375_A0)
   1809     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88375_A0r */
   1810         soc_block_list[22],
   1811         soc_genreg,
   1812         1,
   1813         0,
   1814         0x42c,
   1815         0,
   1816         0,
   1817         1,
   1818         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88375_A0r_fields,
   1819         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1820         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1821         -1,
   1822         -1,
   1823     },
   1824 #endif /* chips */
   1825 
   1826 #if defined(BCM_88375_B0)
   1827     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88375_B0r */
   1828         soc_block_list[22],
   1829         soc_genreg,
   1830         1,
   1831         0,
   1832         0x42c,
   1833         0,
   1834         0,
   1835         1,
   1836         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88375_B0r_fields,
   1837         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1838         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1839         -1,
   1840         -1,
   1841     },
   1842 #endif /* chips */
   1843 
   1844 #if defined(BCM_88470_A0)
   1845     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88470_A0r */
   1846         soc_block_list[22],
   1847         soc_genreg,
   1848         1,
   1849         0,
   1850         0x42e,
   1851         0,
   1852         0,
   1853         1,
   1854         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88470_A0r_fields,
   1855         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1856         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1857         -1,
   1858         -1,
   1859     },
   1860 #endif /* chips */
   1861 
   1862 #if defined(BCM_88470_B0)
   1863     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88470_B0r */
   1864         soc_block_list[22],
   1865         soc_genreg,
   1866         1,
   1867         0,
   1868         0x42e,
   1869         0,
   1870         0,
   1871         1,
   1872         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88470_B0r_fields,
   1873         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1874         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1875         -1,
   1876         -1,
   1877     },
   1878 #endif /* chips */
   1879 
   1880 #if defined(BCM_88650_B0)
   1881     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88650_B0r */
   1882         soc_block_list[22],
   1883         soc_genreg,
   1884         1,
   1885         0,
   1886         0x1ad,
   1887         SOC_REG_FLAG_SIGNAL,
   1888         0,
   1889         1,
   1890         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88650_B0r_fields,
   1891         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1892         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1893         -1,
   1894         -1,
   1895     },
   1896 #endif /* chips */
   1897 
   1898 #if defined(BCM_88660_A0)
   1899     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88660_A0r */
   1900         soc_block_list[22],
   1901         soc_genreg,
   1902         1,
   1903         0,
   1904         0x42b,
   1905         SOC_REG_FLAG_SIGNAL,
   1906         0,
   1907         1,
   1908         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88660_A0r_fields,
   1909         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1910         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1911         -1,
   1912         -1,
   1913     },
   1914 #endif /* chips */
   1915 
   1916 #if defined(BCM_88675_A0)
   1917     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88675_A0r */
   1918         soc_block_list[22],
   1919         soc_genreg,
   1920         1,
   1921         0,
   1922         0x42c,
   1923         0,
   1924         0,
   1925         1,
   1926         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88675_A0r_fields,
   1927         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1928         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1929         -1,
   1930         -1,
   1931     },
   1932 #endif /* chips */
   1933 
   1934 #if defined(BCM_88675_B0)
   1935     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88675_B0r */
   1936         soc_block_list[22],
   1937         soc_genreg,
   1938         1,
   1939         0,
   1940         0x42c,
   1941         0,
   1942         0,
   1943         1,
   1944         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88675_B0r_fields,
   1945         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1946         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1947         -1,
   1948         -1,
   1949     },
   1950 #endif /* chips */
   1951 
   1952 #if defined(BCM_88680_A0)
   1953     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88680_A0r */
   1954         soc_block_list[22],
   1955         soc_genreg,
   1956         1,
   1957         0,
   1958         0x42c,
   1959         0,
   1960         0,
   1961         1,
   1962         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88680_A0r_fields,
   1963         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1964         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1965         -1,
   1966         -1,
   1967     },
   1968 #endif /* chips */
   1969 
   1970 #if defined(BCM_88690_A0)
   1971     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88690_A0r */
   1972         soc_block_list[22],
   1973         soc_genreg,
   1974         1,
   1975         0,
   1976         0x51e,
   1977         0,
   1978         0,
   1979         1,
   1980         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88690_A0r_fields,
   1981         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   1982         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1983         -1,
   1984         -1,
   1985     },
   1986 #endif /* chips */
   1987 
   1988 #if defined(BCM_88690_B0)
   1989     { /* SOC_REG_INT_OAMP_BFD_IPV4_UDP_SPORT_BCM88690_B0r */
   1990         soc_block_list[22],
   1991         soc_genreg,
   1992         1,
   1993         0,
   1994         0x51e,
   1995         0,
   1996         0,
   1997         1,
   1998         soc_OAMP_BFD_IPV4_UDP_SPORT_BCM88690_B0r_fields,
   1999         SOC_RESET_VAL_DEC(0x00001001, 0x00000000)
   2000         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2001         -1,
   2002         -1,
   2003     },
   2004 #endif /* chips */
   2005 
   2006 #if defined(BCM_88650_A0)
   2007     { /* SOC_REG_INT_OAMP_BFD_I_MPLS_CONTROLr */
   2008         soc_block_list[22],
   2009         soc_genreg,
   2010         1,
   2011         0,
   2012         0x162,
   2013         SOC_REG_FLAG_SIGNAL,
   2014         0,
   2015         3,
   2016         soc_OAMP_BFD_I_MPLS_CONTROLr_fields,
   2017         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2018         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2019         -1,
   2020         -1,
   2021     },
   2022 #endif /* chips */
   2023 
   2024 #if defined(BCM_88375_A0)
   2025     { /* SOC_REG_INT_OAMP_BFD_I_MPLS_CONTROL_BCM88375_A0r */
   2026         soc_block_list[22],
   2027         soc_genreg,
   2028         1,
   2029         0,
   2030         0x187,
   2031         0,
   2032         0,
   2033         3,
   2034         soc_OAMP_BFD_I_MPLS_CONTROL_BCM88375_A0r_fields,
   2035         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2036         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2037         -1,
   2038         -1,
   2039     },
   2040 #endif /* chips */
   2041 
   2042 #if defined(BCM_88375_B0)
   2043     { /* SOC_REG_INT_OAMP_BFD_I_MPLS_CONTROL_BCM88375_B0r */
   2044         soc_block_list[22],
   2045         soc_genreg,
   2046         1,
   2047         0,
   2048         0x187,
   2049         0,
   2050         0,
   2051         3,
   2052         soc_OAMP_BFD_I_MPLS_CONTROL_BCM88375_B0r_fields,
   2053         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2054         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2055         -1,
   2056         -1,
   2057     },
   2058 #endif /* chips */
   2059 
   2060 #if defined(BCM_88650_B0)
   2061     { /* SOC_REG_INT_OAMP_BFD_I_MPLS_CONTROL_BCM88650_B0r */
   2062         soc_block_list[22],
   2063         soc_genreg,
   2064         1,
   2065         0,
   2066         0x162,
   2067         SOC_REG_FLAG_SIGNAL,
   2068         0,
   2069         3,
   2070         soc_OAMP_BFD_I_MPLS_CONTROL_BCM88650_B0r_fields,
   2071         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2072         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2073         -1,
   2074         -1,
   2075     },
   2076 #endif /* chips */
   2077 
   2078 #if defined(BCM_88660_A0)
   2079     { /* SOC_REG_INT_OAMP_BFD_I_MPLS_CONTROL_BCM88660_A0r */
   2080         soc_block_list[22],
   2081         soc_genreg,
   2082         1,
   2083         0,
   2084         0x182,
   2085         SOC_REG_FLAG_SIGNAL,
   2086         0,
   2087         3,
   2088         soc_OAMP_BFD_I_MPLS_CONTROL_BCM88660_A0r_fields,
   2089         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2090         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2091         -1,
   2092         -1,
   2093     },
   2094 #endif /* chips */
   2095 
   2096 #if defined(BCM_88675_A0)
   2097     { /* SOC_REG_INT_OAMP_BFD_I_MPLS_CONTROL_BCM88675_A0r */
   2098         soc_block_list[22],
   2099         soc_genreg,
   2100         1,
   2101         0,
   2102         0x187,
   2103         0,
   2104         0,
   2105         3,
   2106         soc_OAMP_BFD_I_MPLS_CONTROL_BCM88675_A0r_fields,
   2107         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2108         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2109         -1,
   2110         -1,
   2111     },
   2112 #endif /* chips */
   2113 
   2114 #if defined(BCM_88675_B0)
   2115     { /* SOC_REG_INT_OAMP_BFD_I_MPLS_CONTROL_BCM88675_B0r */
   2116         soc_block_list[22],
   2117         soc_genreg,
   2118         1,
   2119         0,
   2120         0x187,
   2121         0,
   2122         0,
   2123         3,
   2124         soc_OAMP_BFD_I_MPLS_CONTROL_BCM88675_B0r_fields,
   2125         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2126         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2127         -1,
   2128         -1,
   2129     },
   2130 #endif /* chips */
   2131 
   2132 #if defined(BCM_88680_A0)
   2133     { /* SOC_REG_INT_OAMP_BFD_I_MPLS_CONTROL_BCM88680_A0r */
   2134         soc_block_list[22],
   2135         soc_genreg,
   2136         1,
   2137         0,
   2138         0x187,
   2139         0,
   2140         0,
   2141         3,
   2142         soc_OAMP_BFD_I_MPLS_CONTROL_BCM88680_A0r_fields,
   2143         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2144         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2145         -1,
   2146         -1,
   2147     },
   2148 #endif /* chips */
   2149 
   2150 #if defined(BCM_88650_A0)
   2151     { /* SOC_REG_INT_OAMP_BFD_I_PWE_CONTROLr */
   2152         soc_block_list[22],
   2153         soc_genreg,
   2154         1,
   2155         0,
   2156         0x163,
   2157         SOC_REG_FLAG_SIGNAL,
   2158         0,
   2159         2,
   2160         soc_OAMP_BFD_I_PWE_CONTROLr_fields,
   2161         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   2162         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2163         -1,
   2164         -1,
   2165     },
   2166 #endif /* chips */
   2167 
   2168 #if defined(BCM_88375_A0)
   2169     { /* SOC_REG_INT_OAMP_BFD_I_PWE_CONTROL_BCM88375_A0r */
   2170         soc_block_list[22],
   2171         soc_genreg,
   2172         1,
   2173         0,
   2174         0x188,
   2175         0,
   2176         0,
   2177         2,
   2178         soc_OAMP_BFD_I_PWE_CONTROL_BCM88375_A0r_fields,
   2179         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   2180         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2181         -1,
   2182         -1,
   2183     },
   2184 #endif /* chips */
   2185 
   2186 #if defined(BCM_88375_B0)
   2187     { /* SOC_REG_INT_OAMP_BFD_I_PWE_CONTROL_BCM88375_B0r */
   2188         soc_block_list[22],
   2189         soc_genreg,
   2190         1,
   2191         0,
   2192         0x188,
   2193         0,
   2194         0,
   2195         2,
   2196         soc_OAMP_BFD_I_PWE_CONTROL_BCM88375_B0r_fields,
   2197         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   2198         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2199         -1,
   2200         -1,
   2201     },
   2202 #endif /* chips */
   2203 
   2204 #if defined(BCM_88650_B0)
   2205     { /* SOC_REG_INT_OAMP_BFD_I_PWE_CONTROL_BCM88650_B0r */
   2206         soc_block_list[22],
   2207         soc_genreg,
   2208         1,
   2209         0,
   2210         0x163,
   2211         SOC_REG_FLAG_SIGNAL,
   2212         0,
   2213         2,
   2214         soc_OAMP_BFD_I_PWE_CONTROL_BCM88650_B0r_fields,
   2215         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   2216         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2217         -1,
   2218         -1,
   2219     },
   2220 #endif /* chips */
   2221 
   2222 #if defined(BCM_88660_A0)
   2223     { /* SOC_REG_INT_OAMP_BFD_I_PWE_CONTROL_BCM88660_A0r */
   2224         soc_block_list[22],
   2225         soc_genreg,
   2226         1,
   2227         0,
   2228         0x183,
   2229         SOC_REG_FLAG_SIGNAL,
   2230         0,
   2231         2,
   2232         soc_OAMP_BFD_I_PWE_CONTROL_BCM88660_A0r_fields,
   2233         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   2234         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2235         -1,
   2236         -1,
   2237     },
   2238 #endif /* chips */
   2239 
   2240 #if defined(BCM_88675_A0)
   2241     { /* SOC_REG_INT_OAMP_BFD_I_PWE_CONTROL_BCM88675_A0r */
   2242         soc_block_list[22],
   2243         soc_genreg,
   2244         1,
   2245         0,
   2246         0x188,
   2247         0,
   2248         0,
   2249         2,
   2250         soc_OAMP_BFD_I_PWE_CONTROL_BCM88675_A0r_fields,
   2251         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   2252         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2253         -1,
   2254         -1,
   2255     },
   2256 #endif /* chips */
   2257 
   2258 #if defined(BCM_88675_B0)
   2259     { /* SOC_REG_INT_OAMP_BFD_I_PWE_CONTROL_BCM88675_B0r */
   2260         soc_block_list[22],
   2261         soc_genreg,
   2262         1,
   2263         0,
   2264         0x188,
   2265         0,
   2266         0,
   2267         2,
   2268         soc_OAMP_BFD_I_PWE_CONTROL_BCM88675_B0r_fields,
   2269         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   2270         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2271         -1,
   2272         -1,
   2273     },
   2274 #endif /* chips */
   2275 
   2276 #if defined(BCM_88680_A0)
   2277     { /* SOC_REG_INT_OAMP_BFD_I_PWE_CONTROL_BCM88680_A0r */
   2278         soc_block_list[22],
   2279         soc_genreg,
   2280         1,
   2281         0,
   2282         0x188,
   2283         0,
   2284         0,
   2285         2,
   2286         soc_OAMP_BFD_I_PWE_CONTROL_BCM88680_A0r_fields,
   2287         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   2288         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2289         -1,
   2290         -1,
   2291     },
   2292 #endif /* chips */
   2293 
   2294 #if defined(BCM_88650_A0)
   2295     { /* SOC_REG_INT_OAMP_BFD_MPLS_DST_IPr */
   2296         soc_block_list[22],
   2297         soc_genreg,
   2298         1,
   2299         0,
   2300         0x1af,
   2301         SOC_REG_FLAG_SIGNAL,
   2302         0,
   2303         1,
   2304         soc_OAMP_BFD_MPLS_DST_IPr_fields,
   2305         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   2306         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2307         -1,
   2308         -1,
   2309     },
   2310 #endif /* chips */
   2311 
   2312 #if defined(BCM_88650_B0)
   2313     { /* SOC_REG_INT_OAMP_BFD_MPLS_DST_IP_BCM88650_B0r */
   2314         soc_block_list[22],
   2315         soc_genreg,
   2316         1,
   2317         0,
   2318         0x1af,
   2319         SOC_REG_FLAG_SIGNAL,
   2320         0,
   2321         1,
   2322         soc_OAMP_BFD_MPLS_DST_IP_BCM88650_B0r_fields,
   2323         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   2324         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2325         -1,
   2326         -1,
   2327     },
   2328 #endif /* chips */
   2329 
   2330 #if defined(BCM_88660_A0)
   2331     { /* SOC_REG_INT_OAMP_BFD_MPLS_DST_IP_BCM88660_A0r */
   2332         soc_block_list[22],
   2333         soc_genreg,
   2334         1,
   2335         0,
   2336         0x42d,
   2337         SOC_REG_FLAG_SIGNAL,
   2338         0,
   2339         1,
   2340         soc_OAMP_BFD_MPLS_DST_IP_BCM88660_A0r_fields,
   2341         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   2342         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2343         -1,
   2344         -1,
   2345     },
   2346 #endif /* chips */
   2347 
   2348 #if defined(BCM_88650_A0)
   2349     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORTr */
   2350         soc_block_list[22],
   2351         soc_genreg,
   2352         1,
   2353         0,
   2354         0x1ae,
   2355         SOC_REG_FLAG_SIGNAL,
   2356         0,
   2357         1,
   2358         soc_OAMP_BFD_MPLS_UDP_SPORTr_fields,
   2359         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2360         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2361         -1,
   2362         -1,
   2363     },
   2364 #endif /* chips */
   2365 
   2366 #if defined(BCM_88270_A0)
   2367     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88270_A0r */
   2368         soc_block_list[22],
   2369         soc_genreg,
   2370         1,
   2371         0,
   2372         0x42f,
   2373         0,
   2374         0,
   2375         1,
   2376         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88270_A0r_fields,
   2377         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2378         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2379         -1,
   2380         -1,
   2381     },
   2382 #endif /* chips */
   2383 
   2384 #if defined(BCM_88375_A0)
   2385     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88375_A0r */
   2386         soc_block_list[22],
   2387         soc_genreg,
   2388         1,
   2389         0,
   2390         0x42d,
   2391         0,
   2392         0,
   2393         1,
   2394         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88375_A0r_fields,
   2395         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2396         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2397         -1,
   2398         -1,
   2399     },
   2400 #endif /* chips */
   2401 
   2402 #if defined(BCM_88375_B0)
   2403     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88375_B0r */
   2404         soc_block_list[22],
   2405         soc_genreg,
   2406         1,
   2407         0,
   2408         0x42d,
   2409         0,
   2410         0,
   2411         1,
   2412         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88375_B0r_fields,
   2413         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2414         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2415         -1,
   2416         -1,
   2417     },
   2418 #endif /* chips */
   2419 
   2420 #if defined(BCM_88470_A0)
   2421     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88470_A0r */
   2422         soc_block_list[22],
   2423         soc_genreg,
   2424         1,
   2425         0,
   2426         0x42f,
   2427         0,
   2428         0,
   2429         1,
   2430         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88470_A0r_fields,
   2431         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2432         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2433         -1,
   2434         -1,
   2435     },
   2436 #endif /* chips */
   2437 
   2438 #if defined(BCM_88470_B0)
   2439     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88470_B0r */
   2440         soc_block_list[22],
   2441         soc_genreg,
   2442         1,
   2443         0,
   2444         0x42f,
   2445         0,
   2446         0,
   2447         1,
   2448         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88470_B0r_fields,
   2449         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2450         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2451         -1,
   2452         -1,
   2453     },
   2454 #endif /* chips */
   2455 
   2456 #if defined(BCM_88650_B0)
   2457     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88650_B0r */
   2458         soc_block_list[22],
   2459         soc_genreg,
   2460         1,
   2461         0,
   2462         0x1ae,
   2463         SOC_REG_FLAG_SIGNAL,
   2464         0,
   2465         1,
   2466         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88650_B0r_fields,
   2467         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2468         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2469         -1,
   2470         -1,
   2471     },
   2472 #endif /* chips */
   2473 
   2474 #if defined(BCM_88660_A0)
   2475     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88660_A0r */
   2476         soc_block_list[22],
   2477         soc_genreg,
   2478         1,
   2479         0,
   2480         0x42c,
   2481         SOC_REG_FLAG_SIGNAL,
   2482         0,
   2483         1,
   2484         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88660_A0r_fields,
   2485         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2486         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2487         -1,
   2488         -1,
   2489     },
   2490 #endif /* chips */
   2491 
   2492 #if defined(BCM_88675_A0)
   2493     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88675_A0r */
   2494         soc_block_list[22],
   2495         soc_genreg,
   2496         1,
   2497         0,
   2498         0x42d,
   2499         0,
   2500         0,
   2501         1,
   2502         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88675_A0r_fields,
   2503         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2504         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2505         -1,
   2506         -1,
   2507     },
   2508 #endif /* chips */
   2509 
   2510 #if defined(BCM_88675_B0)
   2511     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88675_B0r */
   2512         soc_block_list[22],
   2513         soc_genreg,
   2514         1,
   2515         0,
   2516         0x42d,
   2517         0,
   2518         0,
   2519         1,
   2520         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88675_B0r_fields,
   2521         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2522         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2523         -1,
   2524         -1,
   2525     },
   2526 #endif /* chips */
   2527 
   2528 #if defined(BCM_88680_A0)
   2529     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88680_A0r */
   2530         soc_block_list[22],
   2531         soc_genreg,
   2532         1,
   2533         0,
   2534         0x42d,
   2535         0,
   2536         0,
   2537         1,
   2538         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88680_A0r_fields,
   2539         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2540         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2541         -1,
   2542         -1,
   2543     },
   2544 #endif /* chips */
   2545 
   2546 #if defined(BCM_88690_A0)
   2547     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88690_A0r */
   2548         soc_block_list[22],
   2549         soc_genreg,
   2550         1,
   2551         0,
   2552         0x51f,
   2553         0,
   2554         0,
   2555         1,
   2556         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88690_A0r_fields,
   2557         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2558         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2559         -1,
   2560         -1,
   2561     },
   2562 #endif /* chips */
   2563 
   2564 #if defined(BCM_88690_B0)
   2565     { /* SOC_REG_INT_OAMP_BFD_MPLS_UDP_SPORT_BCM88690_B0r */
   2566         soc_block_list[22],
   2567         soc_genreg,
   2568         1,
   2569         0,
   2570         0x51f,
   2571         0,
   2572         0,
   2573         1,
   2574         soc_OAMP_BFD_MPLS_UDP_SPORT_BCM88690_B0r_fields,
   2575         SOC_RESET_VAL_DEC(0x00001002, 0x00000000)
   2576         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2577         -1,
   2578         -1,
   2579     },
   2580 #endif /* chips */
   2581 
   2582 #if defined(BCM_88650_A0)
   2583     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_STARTr */
   2584         soc_block_list[22],
   2585         soc_genreg,
   2586         1,
   2587         0,
   2588         0x15b,
   2589         SOC_REG_FLAG_SIGNAL,
   2590         0,
   2591         1,
   2592         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_STARTr_fields,
   2593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2594         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2595         -1,
   2596         -1,
   2597     },
   2598 #endif /* chips */
   2599 
   2600 #if defined(BCM_88270_A0)
   2601     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88270_A0r */
   2602         soc_block_list[22],
   2603         soc_genreg,
   2604         1,
   2605         0,
   2606         0x184,
   2607         0,
   2608         0,
   2609         1,
   2610         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88270_A0r_fields,
   2611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2612         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2613         -1,
   2614         -1,
   2615     },
   2616 #endif /* chips */
   2617 
   2618 #if defined(BCM_88375_A0)
   2619     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88375_A0r */
   2620         soc_block_list[22],
   2621         soc_genreg,
   2622         1,
   2623         0,
   2624         0x182,
   2625         0,
   2626         0,
   2627         1,
   2628         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88375_A0r_fields,
   2629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2631         -1,
   2632         -1,
   2633     },
   2634 #endif /* chips */
   2635 
   2636 #if defined(BCM_88375_B0)
   2637     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88375_B0r */
   2638         soc_block_list[22],
   2639         soc_genreg,
   2640         1,
   2641         0,
   2642         0x182,
   2643         0,
   2644         0,
   2645         1,
   2646         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88375_B0r_fields,
   2647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2649         -1,
   2650         -1,
   2651     },
   2652 #endif /* chips */
   2653 
   2654 #if defined(BCM_88470_A0)
   2655     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88470_A0r */
   2656         soc_block_list[22],
   2657         soc_genreg,
   2658         1,
   2659         0,
   2660         0x184,
   2661         0,
   2662         0,
   2663         1,
   2664         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88470_A0r_fields,
   2665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2667         -1,
   2668         -1,
   2669     },
   2670 #endif /* chips */
   2671 
   2672 #if defined(BCM_88470_B0)
   2673     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88470_B0r */
   2674         soc_block_list[22],
   2675         soc_genreg,
   2676         1,
   2677         0,
   2678         0x184,
   2679         0,
   2680         0,
   2681         1,
   2682         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88470_B0r_fields,
   2683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2685         -1,
   2686         -1,
   2687     },
   2688 #endif /* chips */
   2689 
   2690 #if defined(BCM_88650_B0)
   2691     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88650_B0r */
   2692         soc_block_list[22],
   2693         soc_genreg,
   2694         1,
   2695         0,
   2696         0x15b,
   2697         SOC_REG_FLAG_SIGNAL,
   2698         0,
   2699         1,
   2700         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88650_B0r_fields,
   2701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2703         -1,
   2704         -1,
   2705     },
   2706 #endif /* chips */
   2707 
   2708 #if defined(BCM_88660_A0)
   2709     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88660_A0r */
   2710         soc_block_list[22],
   2711         soc_genreg,
   2712         1,
   2713         0,
   2714         0x16e,
   2715         SOC_REG_FLAG_SIGNAL,
   2716         0,
   2717         1,
   2718         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88660_A0r_fields,
   2719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2721         -1,
   2722         -1,
   2723     },
   2724 #endif /* chips */
   2725 
   2726 #if defined(BCM_88675_A0)
   2727     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88675_A0r */
   2728         soc_block_list[22],
   2729         soc_genreg,
   2730         1,
   2731         0,
   2732         0x182,
   2733         0,
   2734         0,
   2735         1,
   2736         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88675_A0r_fields,
   2737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2739         -1,
   2740         -1,
   2741     },
   2742 #endif /* chips */
   2743 
   2744 #if defined(BCM_88675_B0)
   2745     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88675_B0r */
   2746         soc_block_list[22],
   2747         soc_genreg,
   2748         1,
   2749         0,
   2750         0x182,
   2751         0,
   2752         0,
   2753         1,
   2754         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88675_B0r_fields,
   2755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2757         -1,
   2758         -1,
   2759     },
   2760 #endif /* chips */
   2761 
   2762 #if defined(BCM_88680_A0)
   2763     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88680_A0r */
   2764         soc_block_list[22],
   2765         soc_genreg,
   2766         1,
   2767         0,
   2768         0x182,
   2769         0,
   2770         0,
   2771         1,
   2772         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88680_A0r_fields,
   2773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2775         -1,
   2776         -1,
   2777     },
   2778 #endif /* chips */
   2779 
   2780 #if defined(BCM_88690_A0)
   2781     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88690_A0r */
   2782         soc_block_list[22],
   2783         soc_genreg,
   2784         1,
   2785         0,
   2786         0x181,
   2787         0,
   2788         0,
   2789         1,
   2790         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88690_A0r_fields,
   2791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2792         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2793         -1,
   2794         -1,
   2795     },
   2796 #endif /* chips */
   2797 
   2798 #if defined(BCM_88690_B0)
   2799     { /* SOC_REG_INT_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88690_B0r */
   2800         soc_block_list[22],
   2801         soc_genreg,
   2802         1,
   2803         0,
   2804         0x181,
   2805         0,
   2806         0,
   2807         1,
   2808         soc_OAMP_BFD_MY_DISCRIMINATOR_RANGE_START_BCM88690_B0r_fields,
   2809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2810         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2811         -1,
   2812         -1,
   2813     },
   2814 #endif /* chips */
   2815 
   2816 #if defined(BCM_88650_A0)
   2817     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTERr */
   2818         soc_block_list[22],
   2819         soc_genreg,
   2820         1,
   2821         0,
   2822         0x192,
   2823         SOC_REG_FLAG_64_BITS |
   2824                           SOC_REG_FLAG_SIGNAL,
   2825         0,
   2826         6,
   2827         soc_OAMP_BFD_PDU_STATIC_REGISTERr_fields,
   2828         SOC_RESET_VAL_DEC(0x00180000, 0x00000000)
   2829         SOC_RESET_MASK_DEC(0x00ffffff, 0xffffffff)
   2830         -1,
   2831         -1,
   2832     },
   2833 #endif /* chips */
   2834 
   2835 #if defined(BCM_88270_A0)
   2836     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88270_A0r */
   2837         soc_block_list[22],
   2838         soc_genreg,
   2839         1,
   2840         0,
   2841         0x413,
   2842         SOC_REG_FLAG_64_BITS,
   2843         0,
   2844         3,
   2845         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88270_A0r_fields,
   2846         SOC_RESET_VAL_DEC(0x000000c0, 0x00000000)
   2847         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   2848         -1,
   2849         -1,
   2850     },
   2851 #endif /* chips */
   2852 
   2853 #if defined(BCM_88375_A0)
   2854     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88375_A0r */
   2855         soc_block_list[22],
   2856         soc_genreg,
   2857         1,
   2858         0,
   2859         0x411,
   2860         SOC_REG_FLAG_64_BITS,
   2861         0,
   2862         3,
   2863         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88375_A0r_fields,
   2864         SOC_RESET_VAL_DEC(0x000000c0, 0x00000000)
   2865         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   2866         -1,
   2867         -1,
   2868     },
   2869 #endif /* chips */
   2870 
   2871 #if defined(BCM_88375_B0)
   2872     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88375_B0r */
   2873         soc_block_list[22],
   2874         soc_genreg,
   2875         1,
   2876         0,
   2877         0x411,
   2878         SOC_REG_FLAG_64_BITS,
   2879         0,
   2880         3,
   2881         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88375_B0r_fields,
   2882         SOC_RESET_VAL_DEC(0x000000c0, 0x00000000)
   2883         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   2884         -1,
   2885         -1,
   2886     },
   2887 #endif /* chips */
   2888 
   2889 #if defined(BCM_88470_A0)
   2890     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88470_A0r */
   2891         soc_block_list[22],
   2892         soc_genreg,
   2893         1,
   2894         0,
   2895         0x413,
   2896         SOC_REG_FLAG_64_BITS,
   2897         0,
   2898         3,
   2899         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88470_A0r_fields,
   2900         SOC_RESET_VAL_DEC(0x000000c0, 0x00000000)
   2901         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   2902         -1,
   2903         -1,
   2904     },
   2905 #endif /* chips */
   2906 
   2907 #if defined(BCM_88470_B0)
   2908     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88470_B0r */
   2909         soc_block_list[22],
   2910         soc_genreg,
   2911         1,
   2912         0,
   2913         0x413,
   2914         SOC_REG_FLAG_64_BITS,
   2915         0,
   2916         3,
   2917         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88470_B0r_fields,
   2918         SOC_RESET_VAL_DEC(0x000000c0, 0x00000000)
   2919         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   2920         -1,
   2921         -1,
   2922     },
   2923 #endif /* chips */
   2924 
   2925 #if defined(BCM_88650_B0)
   2926     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88650_B0r */
   2927         soc_block_list[22],
   2928         soc_genreg,
   2929         1,
   2930         0,
   2931         0x192,
   2932         SOC_REG_FLAG_64_BITS |
   2933                           SOC_REG_FLAG_SIGNAL,
   2934         0,
   2935         6,
   2936         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88650_B0r_fields,
   2937         SOC_RESET_VAL_DEC(0x00180000, 0x00000000)
   2938         SOC_RESET_MASK_DEC(0x00ffffff, 0xffffffff)
   2939         -1,
   2940         -1,
   2941     },
   2942 #endif /* chips */
   2943 
   2944 #if defined(BCM_88660_A0)
   2945     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88660_A0r */
   2946         soc_block_list[22],
   2947         soc_genreg,
   2948         1,
   2949         0,
   2950         0x410,
   2951         SOC_REG_FLAG_64_BITS |
   2952                           SOC_REG_FLAG_SIGNAL,
   2953         0,
   2954         3,
   2955         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88660_A0r_fields,
   2956         SOC_RESET_VAL_DEC(0x000000c0, 0x00000000)
   2957         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   2958         -1,
   2959         -1,
   2960     },
   2961 #endif /* chips */
   2962 
   2963 #if defined(BCM_88675_A0)
   2964     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88675_A0r */
   2965         soc_block_list[22],
   2966         soc_genreg,
   2967         1,
   2968         0,
   2969         0x411,
   2970         SOC_REG_FLAG_64_BITS,
   2971         0,
   2972         3,
   2973         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88675_A0r_fields,
   2974         SOC_RESET_VAL_DEC(0x000000c0, 0x00000000)
   2975         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   2976         -1,
   2977         -1,
   2978     },
   2979 #endif /* chips */
   2980 
   2981 #if defined(BCM_88675_B0)
   2982     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88675_B0r */
   2983         soc_block_list[22],
   2984         soc_genreg,
   2985         1,
   2986         0,
   2987         0x411,
   2988         SOC_REG_FLAG_64_BITS,
   2989         0,
   2990         3,
   2991         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88675_B0r_fields,
   2992         SOC_RESET_VAL_DEC(0x000000c0, 0x00000000)
   2993         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   2994         -1,
   2995         -1,
   2996     },
   2997 #endif /* chips */
   2998 
   2999 #if defined(BCM_88680_A0)
   3000     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88680_A0r */
   3001         soc_block_list[22],
   3002         soc_genreg,
   3003         1,
   3004         0,
   3005         0x411,
   3006         SOC_REG_FLAG_64_BITS,
   3007         0,
   3008         3,
   3009         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88680_A0r_fields,
   3010         SOC_RESET_VAL_DEC(0x000000c0, 0x00000000)
   3011         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   3012         -1,
   3013         -1,
   3014     },
   3015 #endif /* chips */
   3016 
   3017 #if defined(BCM_88690_A0)
   3018     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88690_A0r */
   3019         soc_block_list[22],
   3020         soc_genreg,
   3021         1,
   3022         0,
   3023         0x413,
   3024         SOC_REG_FLAG_64_BITS,
   3025         0,
   3026         3,
   3027         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88690_A0r_fields,
   3028         SOC_RESET_VAL_DEC(0x000000c1, 0x00000000)
   3029         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   3030         -1,
   3031         -1,
   3032     },
   3033 #endif /* chips */
   3034 
   3035 #if defined(BCM_88690_B0)
   3036     { /* SOC_REG_INT_OAMP_BFD_PDU_STATIC_REGISTER_BCM88690_B0r */
   3037         soc_block_list[22],
   3038         soc_genreg,
   3039         1,
   3040         0,
   3041         0x413,
   3042         SOC_REG_FLAG_64_BITS,
   3043         0,
   3044         3,
   3045         soc_OAMP_BFD_PDU_STATIC_REGISTER_BCM88690_B0r_fields,
   3046         SOC_RESET_VAL_DEC(0x000000c1, 0x00000000)
   3047         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
   3048         -1,
   3049         -1,
   3050     },
   3051 #endif /* chips */
   3052 
   3053 #if defined(BCM_88650_A0)
   3054     { /* SOC_REG_INT_OAMP_BFD_PWE_CWr */
   3055         soc_block_list[22],
   3056         soc_genreg,
   3057         1,
   3058         0,
   3059         0x1b0,
   3060         SOC_REG_FLAG_SIGNAL,
   3061         0,
   3062         1,
   3063         soc_OAMP_BFD_PWE_CWr_fields,
   3064         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3065         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3066         -1,
   3067         -1,
   3068     },
   3069 #endif /* chips */
   3070 
   3071 #if defined(BCM_88650_A0)
   3072     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0r */
   3073         soc_block_list[22],
   3074         soc_genreg,
   3075         1,
   3076         0,
   3077         0x1b0,
   3078         SOC_REG_FLAG_SIGNAL,
   3079         0,
   3080         1,
   3081         soc_OAMP_BFD_PWE_CW_0r_fields,
   3082         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3083         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3084         -1,
   3085         -1,
   3086     },
   3087 #endif /* chips */
   3088 
   3089 #if defined(BCM_88675_A0)
   3090     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1r */
   3091         soc_block_list[22],
   3092         soc_genreg,
   3093         1,
   3094         0,
   3095         0x42f,
   3096         0,
   3097         0,
   3098         1,
   3099         soc_OAMP_BFD_PWE_CW_1r_fields,
   3100         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3102         -1,
   3103         -1,
   3104     },
   3105 #endif /* chips */
   3106 
   3107 #if defined(BCM_88675_A0)
   3108     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2r */
   3109         soc_block_list[22],
   3110         soc_genreg,
   3111         1,
   3112         0,
   3113         0x430,
   3114         0,
   3115         0,
   3116         1,
   3117         soc_OAMP_BFD_PWE_CW_2r_fields,
   3118         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3120         -1,
   3121         -1,
   3122     },
   3123 #endif /* chips */
   3124 
   3125 #if defined(BCM_88675_A0)
   3126     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3r */
   3127         soc_block_list[22],
   3128         soc_genreg,
   3129         1,
   3130         0,
   3131         0x431,
   3132         0,
   3133         0,
   3134         1,
   3135         soc_OAMP_BFD_PWE_CW_3r_fields,
   3136         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3138         -1,
   3139         -1,
   3140     },
   3141 #endif /* chips */
   3142 
   3143 #if defined(BCM_88270_A0)
   3144     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88270_A0r */
   3145         soc_block_list[22],
   3146         soc_genreg,
   3147         1,
   3148         0,
   3149         0x430,
   3150         0,
   3151         0,
   3152         1,
   3153         soc_OAMP_BFD_PWE_CW_0_BCM88270_A0r_fields,
   3154         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3156         -1,
   3157         -1,
   3158     },
   3159 #endif /* chips */
   3160 
   3161 #if defined(BCM_88375_A0)
   3162     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88375_A0r */
   3163         soc_block_list[22],
   3164         soc_genreg,
   3165         1,
   3166         0,
   3167         0x42e,
   3168         0,
   3169         0,
   3170         1,
   3171         soc_OAMP_BFD_PWE_CW_0_BCM88375_A0r_fields,
   3172         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3174         -1,
   3175         -1,
   3176     },
   3177 #endif /* chips */
   3178 
   3179 #if defined(BCM_88375_B0)
   3180     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88375_B0r */
   3181         soc_block_list[22],
   3182         soc_genreg,
   3183         1,
   3184         0,
   3185         0x42e,
   3186         0,
   3187         0,
   3188         1,
   3189         soc_OAMP_BFD_PWE_CW_0_BCM88375_B0r_fields,
   3190         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3192         -1,
   3193         -1,
   3194     },
   3195 #endif /* chips */
   3196 
   3197 #if defined(BCM_88470_A0)
   3198     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88470_A0r */
   3199         soc_block_list[22],
   3200         soc_genreg,
   3201         1,
   3202         0,
   3203         0x430,
   3204         0,
   3205         0,
   3206         1,
   3207         soc_OAMP_BFD_PWE_CW_0_BCM88470_A0r_fields,
   3208         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3209         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3210         -1,
   3211         -1,
   3212     },
   3213 #endif /* chips */
   3214 
   3215 #if defined(BCM_88470_B0)
   3216     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88470_B0r */
   3217         soc_block_list[22],
   3218         soc_genreg,
   3219         1,
   3220         0,
   3221         0x430,
   3222         0,
   3223         0,
   3224         1,
   3225         soc_OAMP_BFD_PWE_CW_0_BCM88470_B0r_fields,
   3226         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3227         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3228         -1,
   3229         -1,
   3230     },
   3231 #endif /* chips */
   3232 
   3233 #if defined(BCM_88650_B0)
   3234     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88650_B0r */
   3235         soc_block_list[22],
   3236         soc_genreg,
   3237         1,
   3238         0,
   3239         0x1b0,
   3240         SOC_REG_FLAG_SIGNAL,
   3241         0,
   3242         1,
   3243         soc_OAMP_BFD_PWE_CW_0_BCM88650_B0r_fields,
   3244         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3246         -1,
   3247         -1,
   3248     },
   3249 #endif /* chips */
   3250 
   3251 #if defined(BCM_88660_A0)
   3252     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88660_A0r */
   3253         soc_block_list[22],
   3254         soc_genreg,
   3255         1,
   3256         0,
   3257         0x42e,
   3258         SOC_REG_FLAG_SIGNAL,
   3259         0,
   3260         1,
   3261         soc_OAMP_BFD_PWE_CW_0_BCM88660_A0r_fields,
   3262         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3264         -1,
   3265         -1,
   3266     },
   3267 #endif /* chips */
   3268 
   3269 #if defined(BCM_88675_A0)
   3270     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88675_A0r */
   3271         soc_block_list[22],
   3272         soc_genreg,
   3273         1,
   3274         0,
   3275         0x42e,
   3276         0,
   3277         0,
   3278         1,
   3279         soc_OAMP_BFD_PWE_CW_0_BCM88675_A0r_fields,
   3280         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3282         -1,
   3283         -1,
   3284     },
   3285 #endif /* chips */
   3286 
   3287 #if defined(BCM_88675_B0)
   3288     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88675_B0r */
   3289         soc_block_list[22],
   3290         soc_genreg,
   3291         1,
   3292         0,
   3293         0x42e,
   3294         0,
   3295         0,
   3296         1,
   3297         soc_OAMP_BFD_PWE_CW_0_BCM88675_B0r_fields,
   3298         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3300         -1,
   3301         -1,
   3302     },
   3303 #endif /* chips */
   3304 
   3305 #if defined(BCM_88680_A0)
   3306     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88680_A0r */
   3307         soc_block_list[22],
   3308         soc_genreg,
   3309         1,
   3310         0,
   3311         0x42e,
   3312         0,
   3313         0,
   3314         1,
   3315         soc_OAMP_BFD_PWE_CW_0_BCM88680_A0r_fields,
   3316         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3318         -1,
   3319         -1,
   3320     },
   3321 #endif /* chips */
   3322 
   3323 #if defined(BCM_88690_A0)
   3324     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88690_A0r */
   3325         soc_block_list[22],
   3326         soc_genreg,
   3327         1,
   3328         0,
   3329         0x520,
   3330         0,
   3331         0,
   3332         1,
   3333         soc_OAMP_BFD_PWE_CW_0_BCM88690_A0r_fields,
   3334         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3336         -1,
   3337         -1,
   3338     },
   3339 #endif /* chips */
   3340 
   3341 #if defined(BCM_88690_B0)
   3342     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_0_BCM88690_B0r */
   3343         soc_block_list[22],
   3344         soc_genreg,
   3345         1,
   3346         0,
   3347         0x520,
   3348         0,
   3349         0,
   3350         1,
   3351         soc_OAMP_BFD_PWE_CW_0_BCM88690_B0r_fields,
   3352         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3354         -1,
   3355         -1,
   3356     },
   3357 #endif /* chips */
   3358 
   3359 #if defined(BCM_88270_A0)
   3360     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1_BCM88270_A0r */
   3361         soc_block_list[22],
   3362         soc_genreg,
   3363         1,
   3364         0,
   3365         0x431,
   3366         0,
   3367         0,
   3368         1,
   3369         soc_OAMP_BFD_PWE_CW_1_BCM88270_A0r_fields,
   3370         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3372         -1,
   3373         -1,
   3374     },
   3375 #endif /* chips */
   3376 
   3377 #if defined(BCM_88375_A0)
   3378     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1_BCM88375_A0r */
   3379         soc_block_list[22],
   3380         soc_genreg,
   3381         1,
   3382         0,
   3383         0x42f,
   3384         0,
   3385         0,
   3386         1,
   3387         soc_OAMP_BFD_PWE_CW_1_BCM88375_A0r_fields,
   3388         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3389         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3390         -1,
   3391         -1,
   3392     },
   3393 #endif /* chips */
   3394 
   3395 #if defined(BCM_88375_B0)
   3396     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1_BCM88375_B0r */
   3397         soc_block_list[22],
   3398         soc_genreg,
   3399         1,
   3400         0,
   3401         0x42f,
   3402         0,
   3403         0,
   3404         1,
   3405         soc_OAMP_BFD_PWE_CW_1_BCM88375_B0r_fields,
   3406         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3407         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3408         -1,
   3409         -1,
   3410     },
   3411 #endif /* chips */
   3412 
   3413 #if defined(BCM_88470_A0)
   3414     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1_BCM88470_A0r */
   3415         soc_block_list[22],
   3416         soc_genreg,
   3417         1,
   3418         0,
   3419         0x431,
   3420         0,
   3421         0,
   3422         1,
   3423         soc_OAMP_BFD_PWE_CW_1_BCM88470_A0r_fields,
   3424         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3426         -1,
   3427         -1,
   3428     },
   3429 #endif /* chips */
   3430 
   3431 #if defined(BCM_88470_B0)
   3432     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1_BCM88470_B0r */
   3433         soc_block_list[22],
   3434         soc_genreg,
   3435         1,
   3436         0,
   3437         0x431,
   3438         0,
   3439         0,
   3440         1,
   3441         soc_OAMP_BFD_PWE_CW_1_BCM88470_B0r_fields,
   3442         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3444         -1,
   3445         -1,
   3446     },
   3447 #endif /* chips */
   3448 
   3449 #if defined(BCM_88675_B0)
   3450     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1_BCM88675_B0r */
   3451         soc_block_list[22],
   3452         soc_genreg,
   3453         1,
   3454         0,
   3455         0x42f,
   3456         0,
   3457         0,
   3458         1,
   3459         soc_OAMP_BFD_PWE_CW_1_BCM88675_B0r_fields,
   3460         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3462         -1,
   3463         -1,
   3464     },
   3465 #endif /* chips */
   3466 
   3467 #if defined(BCM_88680_A0)
   3468     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1_BCM88680_A0r */
   3469         soc_block_list[22],
   3470         soc_genreg,
   3471         1,
   3472         0,
   3473         0x42f,
   3474         0,
   3475         0,
   3476         1,
   3477         soc_OAMP_BFD_PWE_CW_1_BCM88680_A0r_fields,
   3478         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3480         -1,
   3481         -1,
   3482     },
   3483 #endif /* chips */
   3484 
   3485 #if defined(BCM_88690_A0)
   3486     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1_BCM88690_A0r */
   3487         soc_block_list[22],
   3488         soc_genreg,
   3489         1,
   3490         0,
   3491         0x521,
   3492         0,
   3493         0,
   3494         1,
   3495         soc_OAMP_BFD_PWE_CW_1_BCM88690_A0r_fields,
   3496         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3498         -1,
   3499         -1,
   3500     },
   3501 #endif /* chips */
   3502 
   3503 #if defined(BCM_88690_B0)
   3504     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_1_BCM88690_B0r */
   3505         soc_block_list[22],
   3506         soc_genreg,
   3507         1,
   3508         0,
   3509         0x521,
   3510         0,
   3511         0,
   3512         1,
   3513         soc_OAMP_BFD_PWE_CW_1_BCM88690_B0r_fields,
   3514         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3516         -1,
   3517         -1,
   3518     },
   3519 #endif /* chips */
   3520 
   3521 #if defined(BCM_88270_A0)
   3522     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2_BCM88270_A0r */
   3523         soc_block_list[22],
   3524         soc_genreg,
   3525         1,
   3526         0,
   3527         0x432,
   3528         0,
   3529         0,
   3530         1,
   3531         soc_OAMP_BFD_PWE_CW_2_BCM88270_A0r_fields,
   3532         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3534         -1,
   3535         -1,
   3536     },
   3537 #endif /* chips */
   3538 
   3539 #if defined(BCM_88375_A0)
   3540     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2_BCM88375_A0r */
   3541         soc_block_list[22],
   3542         soc_genreg,
   3543         1,
   3544         0,
   3545         0x430,
   3546         0,
   3547         0,
   3548         1,
   3549         soc_OAMP_BFD_PWE_CW_2_BCM88375_A0r_fields,
   3550         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3552         -1,
   3553         -1,
   3554     },
   3555 #endif /* chips */
   3556 
   3557 #if defined(BCM_88375_B0)
   3558     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2_BCM88375_B0r */
   3559         soc_block_list[22],
   3560         soc_genreg,
   3561         1,
   3562         0,
   3563         0x430,
   3564         0,
   3565         0,
   3566         1,
   3567         soc_OAMP_BFD_PWE_CW_2_BCM88375_B0r_fields,
   3568         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3570         -1,
   3571         -1,
   3572     },
   3573 #endif /* chips */
   3574 
   3575 #if defined(BCM_88470_A0)
   3576     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2_BCM88470_A0r */
   3577         soc_block_list[22],
   3578         soc_genreg,
   3579         1,
   3580         0,
   3581         0x432,
   3582         0,
   3583         0,
   3584         1,
   3585         soc_OAMP_BFD_PWE_CW_2_BCM88470_A0r_fields,
   3586         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3587         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3588         -1,
   3589         -1,
   3590     },
   3591 #endif /* chips */
   3592 
   3593 #if defined(BCM_88470_B0)
   3594     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2_BCM88470_B0r */
   3595         soc_block_list[22],
   3596         soc_genreg,
   3597         1,
   3598         0,
   3599         0x432,
   3600         0,
   3601         0,
   3602         1,
   3603         soc_OAMP_BFD_PWE_CW_2_BCM88470_B0r_fields,
   3604         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3605         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3606         -1,
   3607         -1,
   3608     },
   3609 #endif /* chips */
   3610 
   3611 #if defined(BCM_88675_B0)
   3612     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2_BCM88675_B0r */
   3613         soc_block_list[22],
   3614         soc_genreg,
   3615         1,
   3616         0,
   3617         0x430,
   3618         0,
   3619         0,
   3620         1,
   3621         soc_OAMP_BFD_PWE_CW_2_BCM88675_B0r_fields,
   3622         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3623         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3624         -1,
   3625         -1,
   3626     },
   3627 #endif /* chips */
   3628 
   3629 #if defined(BCM_88680_A0)
   3630     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2_BCM88680_A0r */
   3631         soc_block_list[22],
   3632         soc_genreg,
   3633         1,
   3634         0,
   3635         0x430,
   3636         0,
   3637         0,
   3638         1,
   3639         soc_OAMP_BFD_PWE_CW_2_BCM88680_A0r_fields,
   3640         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3641         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3642         -1,
   3643         -1,
   3644     },
   3645 #endif /* chips */
   3646 
   3647 #if defined(BCM_88690_A0)
   3648     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2_BCM88690_A0r */
   3649         soc_block_list[22],
   3650         soc_genreg,
   3651         1,
   3652         0,
   3653         0x522,
   3654         0,
   3655         0,
   3656         1,
   3657         soc_OAMP_BFD_PWE_CW_2_BCM88690_A0r_fields,
   3658         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3659         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3660         -1,
   3661         -1,
   3662     },
   3663 #endif /* chips */
   3664 
   3665 #if defined(BCM_88690_B0)
   3666     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_2_BCM88690_B0r */
   3667         soc_block_list[22],
   3668         soc_genreg,
   3669         1,
   3670         0,
   3671         0x522,
   3672         0,
   3673         0,
   3674         1,
   3675         soc_OAMP_BFD_PWE_CW_2_BCM88690_B0r_fields,
   3676         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3677         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3678         -1,
   3679         -1,
   3680     },
   3681 #endif /* chips */
   3682 
   3683 #if defined(BCM_88270_A0)
   3684     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3_BCM88270_A0r */
   3685         soc_block_list[22],
   3686         soc_genreg,
   3687         1,
   3688         0,
   3689         0x433,
   3690         0,
   3691         0,
   3692         1,
   3693         soc_OAMP_BFD_PWE_CW_3_BCM88270_A0r_fields,
   3694         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3695         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3696         -1,
   3697         -1,
   3698     },
   3699 #endif /* chips */
   3700 
   3701 #if defined(BCM_88375_A0)
   3702     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3_BCM88375_A0r */
   3703         soc_block_list[22],
   3704         soc_genreg,
   3705         1,
   3706         0,
   3707         0x431,
   3708         0,
   3709         0,
   3710         1,
   3711         soc_OAMP_BFD_PWE_CW_3_BCM88375_A0r_fields,
   3712         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3713         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3714         -1,
   3715         -1,
   3716     },
   3717 #endif /* chips */
   3718 
   3719 #if defined(BCM_88375_B0)
   3720     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3_BCM88375_B0r */
   3721         soc_block_list[22],
   3722         soc_genreg,
   3723         1,
   3724         0,
   3725         0x431,
   3726         0,
   3727         0,
   3728         1,
   3729         soc_OAMP_BFD_PWE_CW_3_BCM88375_B0r_fields,
   3730         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3731         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3732         -1,
   3733         -1,
   3734     },
   3735 #endif /* chips */
   3736 
   3737 #if defined(BCM_88470_A0)
   3738     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3_BCM88470_A0r */
   3739         soc_block_list[22],
   3740         soc_genreg,
   3741         1,
   3742         0,
   3743         0x433,
   3744         0,
   3745         0,
   3746         1,
   3747         soc_OAMP_BFD_PWE_CW_3_BCM88470_A0r_fields,
   3748         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3749         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3750         -1,
   3751         -1,
   3752     },
   3753 #endif /* chips */
   3754 
   3755 #if defined(BCM_88470_B0)
   3756     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3_BCM88470_B0r */
   3757         soc_block_list[22],
   3758         soc_genreg,
   3759         1,
   3760         0,
   3761         0x433,
   3762         0,
   3763         0,
   3764         1,
   3765         soc_OAMP_BFD_PWE_CW_3_BCM88470_B0r_fields,
   3766         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3767         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3768         -1,
   3769         -1,
   3770     },
   3771 #endif /* chips */
   3772 
   3773 #if defined(BCM_88675_B0)
   3774     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3_BCM88675_B0r */
   3775         soc_block_list[22],
   3776         soc_genreg,
   3777         1,
   3778         0,
   3779         0x431,
   3780         0,
   3781         0,
   3782         1,
   3783         soc_OAMP_BFD_PWE_CW_3_BCM88675_B0r_fields,
   3784         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3785         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3786         -1,
   3787         -1,
   3788     },
   3789 #endif /* chips */
   3790 
   3791 #if defined(BCM_88680_A0)
   3792     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3_BCM88680_A0r */
   3793         soc_block_list[22],
   3794         soc_genreg,
   3795         1,
   3796         0,
   3797         0x431,
   3798         0,
   3799         0,
   3800         1,
   3801         soc_OAMP_BFD_PWE_CW_3_BCM88680_A0r_fields,
   3802         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3803         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3804         -1,
   3805         -1,
   3806     },
   3807 #endif /* chips */
   3808 
   3809 #if defined(BCM_88690_A0)
   3810     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3_BCM88690_A0r */
   3811         soc_block_list[22],
   3812         soc_genreg,
   3813         1,
   3814         0,
   3815         0x523,
   3816         0,
   3817         0,
   3818         1,
   3819         soc_OAMP_BFD_PWE_CW_3_BCM88690_A0r_fields,
   3820         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3822         -1,
   3823         -1,
   3824     },
   3825 #endif /* chips */
   3826 
   3827 #if defined(BCM_88690_B0)
   3828     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_3_BCM88690_B0r */
   3829         soc_block_list[22],
   3830         soc_genreg,
   3831         1,
   3832         0,
   3833         0x523,
   3834         0,
   3835         0,
   3836         1,
   3837         soc_OAMP_BFD_PWE_CW_3_BCM88690_B0r_fields,
   3838         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3839         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3840         -1,
   3841         -1,
   3842     },
   3843 #endif /* chips */
   3844 
   3845 #if defined(BCM_88650_B0)
   3846     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_BCM88650_B0r */
   3847         soc_block_list[22],
   3848         soc_genreg,
   3849         1,
   3850         0,
   3851         0x1b0,
   3852         SOC_REG_FLAG_SIGNAL,
   3853         0,
   3854         1,
   3855         soc_OAMP_BFD_PWE_CW_BCM88650_B0r_fields,
   3856         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3858         -1,
   3859         -1,
   3860     },
   3861 #endif /* chips */
   3862 
   3863 #if defined(BCM_88660_A0)
   3864     { /* SOC_REG_INT_OAMP_BFD_PWE_CW_BCM88660_A0r */
   3865         soc_block_list[22],
   3866         soc_genreg,
   3867         1,
   3868         0,
   3869         0x42e,
   3870         SOC_REG_FLAG_SIGNAL,
   3871         0,
   3872         1,
   3873         soc_OAMP_BFD_PWE_CW_BCM88660_A0r_fields,
   3874         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3876         -1,
   3877         -1,
   3878     },
   3879 #endif /* chips */
   3880 
   3881 #if defined(BCM_88660_A0)
   3882     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERTr */
   3883         soc_block_list[22],
   3884         soc_genreg,
   3885         1,
   3886         0,
   3887         0x42f,
   3888         SOC_REG_FLAG_SIGNAL,
   3889         0,
   3890         1,
   3891         soc_OAMP_BFD_PWE_ROUTER_ALERTr_fields,
   3892         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3893         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3894         -1,
   3895         -1,
   3896     },
   3897 #endif /* chips */
   3898 
   3899 #if defined(BCM_88270_A0)
   3900     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88270_A0r */
   3901         soc_block_list[22],
   3902         soc_genreg,
   3903         1,
   3904         0,
   3905         0x434,
   3906         0,
   3907         0,
   3908         1,
   3909         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88270_A0r_fields,
   3910         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3912         -1,
   3913         -1,
   3914     },
   3915 #endif /* chips */
   3916 
   3917 #if defined(BCM_88375_A0)
   3918     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88375_A0r */
   3919         soc_block_list[22],
   3920         soc_genreg,
   3921         1,
   3922         0,
   3923         0x432,
   3924         0,
   3925         0,
   3926         1,
   3927         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88375_A0r_fields,
   3928         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3929         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3930         -1,
   3931         -1,
   3932     },
   3933 #endif /* chips */
   3934 
   3935 #if defined(BCM_88375_B0)
   3936     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88375_B0r */
   3937         soc_block_list[22],
   3938         soc_genreg,
   3939         1,
   3940         0,
   3941         0x432,
   3942         0,
   3943         0,
   3944         1,
   3945         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88375_B0r_fields,
   3946         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3947         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3948         -1,
   3949         -1,
   3950     },
   3951 #endif /* chips */
   3952 
   3953 #if defined(BCM_88470_A0)
   3954     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88470_A0r */
   3955         soc_block_list[22],
   3956         soc_genreg,
   3957         1,
   3958         0,
   3959         0x434,
   3960         0,
   3961         0,
   3962         1,
   3963         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88470_A0r_fields,
   3964         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3965         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3966         -1,
   3967         -1,
   3968     },
   3969 #endif /* chips */
   3970 
   3971 #if defined(BCM_88470_B0)
   3972     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88470_B0r */
   3973         soc_block_list[22],
   3974         soc_genreg,
   3975         1,
   3976         0,
   3977         0x434,
   3978         0,
   3979         0,
   3980         1,
   3981         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88470_B0r_fields,
   3982         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   3983         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3984         -1,
   3985         -1,
   3986     },
   3987 #endif /* chips */
   3988 
   3989 #if defined(BCM_88675_A0)
   3990     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88675_A0r */
   3991         soc_block_list[22],
   3992         soc_genreg,
   3993         1,
   3994         0,
   3995         0x432,
   3996         0,
   3997         0,
   3998         1,
   3999         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88675_A0r_fields,
   4000         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   4001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4002         -1,
   4003         -1,
   4004     },
   4005 #endif /* chips */
   4006 
   4007 #if defined(BCM_88675_B0)
   4008     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88675_B0r */
   4009         soc_block_list[22],
   4010         soc_genreg,
   4011         1,
   4012         0,
   4013         0x432,
   4014         0,
   4015         0,
   4016         1,
   4017         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88675_B0r_fields,
   4018         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   4019         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4020         -1,
   4021         -1,
   4022     },
   4023 #endif /* chips */
   4024 
   4025 #if defined(BCM_88680_A0)
   4026     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88680_A0r */
   4027         soc_block_list[22],
   4028         soc_genreg,
   4029         1,
   4030         0,
   4031         0x432,
   4032         0,
   4033         0,
   4034         1,
   4035         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88680_A0r_fields,
   4036         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   4037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4038         -1,
   4039         -1,
   4040     },
   4041 #endif /* chips */
   4042 
   4043 #if defined(BCM_88690_A0)
   4044     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88690_A0r */
   4045         soc_block_list[22],
   4046         soc_genreg,
   4047         1,
   4048         0,
   4049         0x524,
   4050         0,
   4051         0,
   4052         1,
   4053         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88690_A0r_fields,
   4054         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   4055         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4056         -1,
   4057         -1,
   4058     },
   4059 #endif /* chips */
   4060 
   4061 #if defined(BCM_88690_B0)
   4062     { /* SOC_REG_INT_OAMP_BFD_PWE_ROUTER_ALERT_BCM88690_B0r */
   4063         soc_block_list[22],
   4064         soc_genreg,
   4065         1,
   4066         0,
   4067         0x524,
   4068         0,
   4069         0,
   4070         1,
   4071         soc_OAMP_BFD_PWE_ROUTER_ALERT_BCM88690_B0r_fields,
   4072         SOC_RESET_VAL_DEC(0x12345678, 0x00000000)
   4073         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4074         -1,
   4075         -1,
   4076     },
   4077 #endif /* chips */
   4078 
   4079 #if defined(BCM_88650_A0)
   4080     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTERr */
   4081         soc_block_list[22],
   4082         soc_genreg,
   4083         1,
   4084         0,
   4085         0x1c3,
   4086         SOC_REG_FLAG_ABOVE_64_BITS |
   4087                           SOC_REG_FLAG_SIGNAL,
   4088         0,
   4089         8,
   4090         soc_OAMP_BFD_REQ_INTERVAL_POINTERr_fields,
   4091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4092         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4093         -1,
   4094         -1,
   4095     },
   4096 #endif /* chips */
   4097 
   4098 #if defined(BCM_88270_A0)
   4099     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88270_A0r */
   4100         soc_block_list[22],
   4101         soc_genreg,
   4102         1,
   4103         0,
   4104         0x438,
   4105         SOC_REG_FLAG_ABOVE_64_BITS,
   4106         0,
   4107         8,
   4108         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88270_A0r_fields,
   4109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4110         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4111         -1,
   4112         -1,
   4113     },
   4114 #endif /* chips */
   4115 
   4116 #if defined(BCM_88375_A0)
   4117     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88375_A0r */
   4118         soc_block_list[22],
   4119         soc_genreg,
   4120         1,
   4121         0,
   4122         0x435,
   4123         SOC_REG_FLAG_ABOVE_64_BITS,
   4124         0,
   4125         8,
   4126         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88375_A0r_fields,
   4127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4128         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4129         -1,
   4130         -1,
   4131     },
   4132 #endif /* chips */
   4133 
   4134 #if defined(BCM_88375_B0)
   4135     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88375_B0r */
   4136         soc_block_list[22],
   4137         soc_genreg,
   4138         1,
   4139         0,
   4140         0x435,
   4141         SOC_REG_FLAG_ABOVE_64_BITS,
   4142         0,
   4143         8,
   4144         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88375_B0r_fields,
   4145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4146         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4147         -1,
   4148         -1,
   4149     },
   4150 #endif /* chips */
   4151 
   4152 #if defined(BCM_88470_A0)
   4153     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88470_A0r */
   4154         soc_block_list[22],
   4155         soc_genreg,
   4156         1,
   4157         0,
   4158         0x438,
   4159         SOC_REG_FLAG_ABOVE_64_BITS,
   4160         0,
   4161         8,
   4162         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88470_A0r_fields,
   4163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4164         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4165         -1,
   4166         -1,
   4167     },
   4168 #endif /* chips */
   4169 
   4170 #if defined(BCM_88470_B0)
   4171     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88470_B0r */
   4172         soc_block_list[22],
   4173         soc_genreg,
   4174         1,
   4175         0,
   4176         0x438,
   4177         SOC_REG_FLAG_ABOVE_64_BITS,
   4178         0,
   4179         8,
   4180         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88470_B0r_fields,
   4181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4182         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4183         -1,
   4184         -1,
   4185     },
   4186 #endif /* chips */
   4187 
   4188 #if defined(BCM_88650_B0)
   4189     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88650_B0r */
   4190         soc_block_list[22],
   4191         soc_genreg,
   4192         1,
   4193         0,
   4194         0x1c3,
   4195         SOC_REG_FLAG_ABOVE_64_BITS |
   4196                           SOC_REG_FLAG_SIGNAL,
   4197         0,
   4198         8,
   4199         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88650_B0r_fields,
   4200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4201         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4202         -1,
   4203         -1,
   4204     },
   4205 #endif /* chips */
   4206 
   4207 #if defined(BCM_88660_A0)
   4208     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88660_A0r */
   4209         soc_block_list[22],
   4210         soc_genreg,
   4211         1,
   4212         0,
   4213         0x430,
   4214         SOC_REG_FLAG_ABOVE_64_BITS |
   4215                           SOC_REG_FLAG_SIGNAL,
   4216         0,
   4217         8,
   4218         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88660_A0r_fields,
   4219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4220         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4221         -1,
   4222         -1,
   4223     },
   4224 #endif /* chips */
   4225 
   4226 #if defined(BCM_88675_A0)
   4227     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88675_A0r */
   4228         soc_block_list[22],
   4229         soc_genreg,
   4230         1,
   4231         0,
   4232         0x435,
   4233         SOC_REG_FLAG_ABOVE_64_BITS,
   4234         0,
   4235         8,
   4236         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88675_A0r_fields,
   4237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4238         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4239         -1,
   4240         -1,
   4241     },
   4242 #endif /* chips */
   4243 
   4244 #if defined(BCM_88675_B0)
   4245     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88675_B0r */
   4246         soc_block_list[22],
   4247         soc_genreg,
   4248         1,
   4249         0,
   4250         0x435,
   4251         SOC_REG_FLAG_ABOVE_64_BITS,
   4252         0,
   4253         8,
   4254         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88675_B0r_fields,
   4255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4256         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4257         -1,
   4258         -1,
   4259     },
   4260 #endif /* chips */
   4261 
   4262 #if defined(BCM_88680_A0)
   4263     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88680_A0r */
   4264         soc_block_list[22],
   4265         soc_genreg,
   4266         1,
   4267         0,
   4268         0x435,
   4269         SOC_REG_FLAG_ABOVE_64_BITS,
   4270         0,
   4271         8,
   4272         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88680_A0r_fields,
   4273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4274         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4275         -1,
   4276         -1,
   4277     },
   4278 #endif /* chips */
   4279 
   4280 #if defined(BCM_88690_A0)
   4281     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88690_A0r */
   4282         soc_block_list[22],
   4283         soc_genreg,
   4284         1,
   4285         0,
   4286         0x528,
   4287         SOC_REG_FLAG_ABOVE_64_BITS,
   4288         0,
   4289         8,
   4290         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88690_A0r_fields,
   4291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4293         -1,
   4294         -1,
   4295     },
   4296 #endif /* chips */
   4297 
   4298 #if defined(BCM_88690_B0)
   4299     { /* SOC_REG_INT_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88690_B0r */
   4300         soc_block_list[22],
   4301         soc_genreg,
   4302         1,
   4303         0,
   4304         0x528,
   4305         SOC_REG_FLAG_ABOVE_64_BITS,
   4306         0,
   4307         8,
   4308         soc_OAMP_BFD_REQ_INTERVAL_POINTER_BCM88690_B0r_fields,
   4309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4310         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4311         -1,
   4312         -1,
   4313     },
   4314 #endif /* chips */
   4315 
   4316 #if defined(BCM_88650_A0)
   4317     { /* SOC_REG_INT_OAMP_BFD_TX_IPV4_MULTI_HOPr */
   4318         soc_block_list[22],
   4319         soc_genreg,
   4320         1,
   4321         0,
   4322         0x184,
   4323         SOC_REG_FLAG_SIGNAL,
   4324         0,
   4325         2,
   4326         soc_OAMP_BFD_TX_IPV4_MULTI_HOPr_fields,
   4327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4328         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4329         -1,
   4330         -1,
   4331     },
   4332 #endif /* chips */
   4333 
   4334 #if defined(BCM_88375_A0)
   4335     { /* SOC_REG_INT_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88375_A0r */
   4336         soc_block_list[22],
   4337         soc_genreg,
   4338         1,
   4339         0,
   4340         0x404,
   4341         0,
   4342         0,
   4343         2,
   4344         soc_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88375_A0r_fields,
   4345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4346         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4347         -1,
   4348         -1,
   4349     },
   4350 #endif /* chips */
   4351 
   4352 #if defined(BCM_88375_B0)
   4353     { /* SOC_REG_INT_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88375_B0r */
   4354         soc_block_list[22],
   4355         soc_genreg,
   4356         1,
   4357         0,
   4358         0x404,
   4359         0,
   4360         0,
   4361         2,
   4362         soc_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88375_B0r_fields,
   4363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4364         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4365         -1,
   4366         -1,
   4367     },
   4368 #endif /* chips */
   4369 
   4370 #if defined(BCM_88650_B0)
   4371     { /* SOC_REG_INT_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88650_B0r */
   4372         soc_block_list[22],
   4373         soc_genreg,
   4374         1,
   4375         0,
   4376         0x184,
   4377         SOC_REG_FLAG_SIGNAL,
   4378         0,
   4379         2,
   4380         soc_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88650_B0r_fields,
   4381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4382         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4383         -1,
   4384         -1,
   4385     },
   4386 #endif /* chips */
   4387 
   4388 #if defined(BCM_88660_A0)
   4389     { /* SOC_REG_INT_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88660_A0r */
   4390         soc_block_list[22],
   4391         soc_genreg,
   4392         1,
   4393         0,
   4394         0x404,
   4395         SOC_REG_FLAG_SIGNAL,
   4396         0,
   4397         2,
   4398         soc_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88660_A0r_fields,
   4399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4400         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4401         -1,
   4402         -1,
   4403     },
   4404 #endif /* chips */
   4405 
   4406 #if defined(BCM_88675_A0)
   4407     { /* SOC_REG_INT_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88675_A0r */
   4408         soc_block_list[22],
   4409         soc_genreg,
   4410         1,
   4411         0,
   4412         0x404,
   4413         0,
   4414         0,
   4415         2,
   4416         soc_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88675_A0r_fields,
   4417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4418         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4419         -1,
   4420         -1,
   4421     },
   4422 #endif /* chips */
   4423 
   4424 #if defined(BCM_88675_B0)
   4425     { /* SOC_REG_INT_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88675_B0r */
   4426         soc_block_list[22],
   4427         soc_genreg,
   4428         1,
   4429         0,
   4430         0x404,
   4431         0,
   4432         0,
   4433         2,
   4434         soc_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88675_B0r_fields,
   4435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4436         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4437         -1,
   4438         -1,
   4439     },
   4440 #endif /* chips */
   4441 
   4442 #if defined(BCM_88680_A0)
   4443     { /* SOC_REG_INT_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88680_A0r */
   4444         soc_block_list[22],
   4445         soc_genreg,
   4446         1,
   4447         0,
   4448         0x404,
   4449         0,
   4450         0,
   4451         2,
   4452         soc_OAMP_BFD_TX_IPV4_MULTI_HOP_BCM88680_A0r_fields,
   4453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4454         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4455         -1,
   4456         -1,
   4457     },
   4458 #endif /* chips */
   4459 
   4460 #if defined(BCM_88650_A0)
   4461     { /* SOC_REG_INT_OAMP_BFD_TX_MPLSr */
   4462         soc_block_list[22],
   4463         soc_genreg,
   4464         1,
   4465         0,
   4466         0x185,
   4467         SOC_REG_FLAG_SIGNAL,
   4468         0,
   4469         2,
   4470         soc_OAMP_BFD_TX_MPLSr_fields,
   4471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4472         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4473         -1,
   4474         -1,
   4475     },
   4476 #endif /* chips */
   4477 
   4478 #if defined(BCM_88375_A0)
   4479     { /* SOC_REG_INT_OAMP_BFD_TX_MPLS_BCM88375_A0r */
   4480         soc_block_list[22],
   4481         soc_genreg,
   4482         1,
   4483         0,
   4484         0x405,
   4485         0,
   4486         0,
   4487         2,
   4488         soc_OAMP_BFD_TX_MPLS_BCM88375_A0r_fields,
   4489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4490         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4491         -1,
   4492         -1,
   4493     },
   4494 #endif /* chips */
   4495 
   4496 #if defined(BCM_88375_B0)
   4497     { /* SOC_REG_INT_OAMP_BFD_TX_MPLS_BCM88375_B0r */
   4498         soc_block_list[22],
   4499         soc_genreg,
   4500         1,
   4501         0,
   4502         0x405,
   4503         0,
   4504         0,
   4505         2,
   4506         soc_OAMP_BFD_TX_MPLS_BCM88375_B0r_fields,
   4507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4508         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4509         -1,
   4510         -1,
   4511     },
   4512 #endif /* chips */
   4513 
   4514 #if defined(BCM_88650_B0)
   4515     { /* SOC_REG_INT_OAMP_BFD_TX_MPLS_BCM88650_B0r */
   4516         soc_block_list[22],
   4517         soc_genreg,
   4518         1,
   4519         0,
   4520         0x185,
   4521         SOC_REG_FLAG_SIGNAL,
   4522         0,
   4523         2,
   4524         soc_OAMP_BFD_TX_MPLS_BCM88650_B0r_fields,
   4525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4526         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4527         -1,
   4528         -1,
   4529     },
   4530 #endif /* chips */
   4531 
   4532 #if defined(BCM_88660_A0)
   4533     { /* SOC_REG_INT_OAMP_BFD_TX_MPLS_BCM88660_A0r */
   4534         soc_block_list[22],
   4535         soc_genreg,
   4536         1,
   4537         0,
   4538         0x405,
   4539         SOC_REG_FLAG_SIGNAL,
   4540         0,
   4541         2,
   4542         soc_OAMP_BFD_TX_MPLS_BCM88660_A0r_fields,
   4543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4544         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4545         -1,
   4546         -1,
   4547     },
   4548 #endif /* chips */
   4549 
   4550 #if defined(BCM_88675_A0)
   4551     { /* SOC_REG_INT_OAMP_BFD_TX_MPLS_BCM88675_A0r */
   4552         soc_block_list[22],
   4553         soc_genreg,
   4554         1,
   4555         0,
   4556         0x405,
   4557         0,
   4558         0,
   4559         2,
   4560         soc_OAMP_BFD_TX_MPLS_BCM88675_A0r_fields,
   4561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4562         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4563         -1,
   4564         -1,
   4565     },
   4566 #endif /* chips */
   4567 
   4568 #if defined(BCM_88675_B0)
   4569     { /* SOC_REG_INT_OAMP_BFD_TX_MPLS_BCM88675_B0r */
   4570         soc_block_list[22],
   4571         soc_genreg,
   4572         1,
   4573         0,
   4574         0x405,
   4575         0,
   4576         0,
   4577         2,
   4578         soc_OAMP_BFD_TX_MPLS_BCM88675_B0r_fields,
   4579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4580         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4581         -1,
   4582         -1,
   4583     },
   4584 #endif /* chips */
   4585 
   4586 #if defined(BCM_88680_A0)
   4587     { /* SOC_REG_INT_OAMP_BFD_TX_MPLS_BCM88680_A0r */
   4588         soc_block_list[22],
   4589         soc_genreg,
   4590         1,
   4591         0,
   4592         0x405,
   4593         0,
   4594         0,
   4595         2,
   4596         soc_OAMP_BFD_TX_MPLS_BCM88680_A0r_fields,
   4597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4598         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4599         -1,
   4600         -1,
   4601     },
   4602 #endif /* chips */
   4603 
   4604 #if defined(BCM_88650_A0)
   4605     { /* SOC_REG_INT_OAMP_BFD_TX_RATEr */
   4606         soc_block_list[22],
   4607         soc_genreg,
   4608         1,
   4609         0,
   4610         0x180,
   4611         SOC_REG_FLAG_ABOVE_64_BITS |
   4612                           SOC_REG_FLAG_SIGNAL,
   4613         0,
   4614         8,
   4615         soc_OAMP_BFD_TX_RATEr_fields,
   4616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4617         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4618         -1,
   4619         -1,
   4620     },
   4621 #endif /* chips */
   4622 
   4623 #if defined(BCM_88270_A0)
   4624     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88270_A0r */
   4625         soc_block_list[22],
   4626         soc_genreg,
   4627         1,
   4628         0,
   4629         0x405,
   4630         SOC_REG_FLAG_ABOVE_64_BITS,
   4631         0,
   4632         8,
   4633         soc_OAMP_BFD_TX_RATE_BCM88270_A0r_fields,
   4634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4635         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4636         -1,
   4637         -1,
   4638     },
   4639 #endif /* chips */
   4640 
   4641 #if defined(BCM_88375_A0)
   4642     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88375_A0r */
   4643         soc_block_list[22],
   4644         soc_genreg,
   4645         1,
   4646         0,
   4647         0x400,
   4648         SOC_REG_FLAG_ABOVE_64_BITS,
   4649         0,
   4650         8,
   4651         soc_OAMP_BFD_TX_RATE_BCM88375_A0r_fields,
   4652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4654         -1,
   4655         -1,
   4656     },
   4657 #endif /* chips */
   4658 
   4659 #if defined(BCM_88375_B0)
   4660     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88375_B0r */
   4661         soc_block_list[22],
   4662         soc_genreg,
   4663         1,
   4664         0,
   4665         0x400,
   4666         SOC_REG_FLAG_ABOVE_64_BITS,
   4667         0,
   4668         8,
   4669         soc_OAMP_BFD_TX_RATE_BCM88375_B0r_fields,
   4670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4671         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4672         -1,
   4673         -1,
   4674     },
   4675 #endif /* chips */
   4676 
   4677 #if defined(BCM_88470_A0)
   4678     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88470_A0r */
   4679         soc_block_list[22],
   4680         soc_genreg,
   4681         1,
   4682         0,
   4683         0x405,
   4684         SOC_REG_FLAG_ABOVE_64_BITS,
   4685         0,
   4686         8,
   4687         soc_OAMP_BFD_TX_RATE_BCM88470_A0r_fields,
   4688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4690         -1,
   4691         -1,
   4692     },
   4693 #endif /* chips */
   4694 
   4695 #if defined(BCM_88470_B0)
   4696     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88470_B0r */
   4697         soc_block_list[22],
   4698         soc_genreg,
   4699         1,
   4700         0,
   4701         0x405,
   4702         SOC_REG_FLAG_ABOVE_64_BITS,
   4703         0,
   4704         8,
   4705         soc_OAMP_BFD_TX_RATE_BCM88470_B0r_fields,
   4706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4707         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4708         -1,
   4709         -1,
   4710     },
   4711 #endif /* chips */
   4712 
   4713 #if defined(BCM_88650_B0)
   4714     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88650_B0r */
   4715         soc_block_list[22],
   4716         soc_genreg,
   4717         1,
   4718         0,
   4719         0x180,
   4720         SOC_REG_FLAG_ABOVE_64_BITS |
   4721                           SOC_REG_FLAG_SIGNAL,
   4722         0,
   4723         8,
   4724         soc_OAMP_BFD_TX_RATE_BCM88650_B0r_fields,
   4725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4726         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4727         -1,
   4728         -1,
   4729     },
   4730 #endif /* chips */
   4731 
   4732 #if defined(BCM_88660_A0)
   4733     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88660_A0r */
   4734         soc_block_list[22],
   4735         soc_genreg,
   4736         1,
   4737         0,
   4738         0x400,
   4739         SOC_REG_FLAG_ABOVE_64_BITS |
   4740                           SOC_REG_FLAG_SIGNAL,
   4741         0,
   4742         8,
   4743         soc_OAMP_BFD_TX_RATE_BCM88660_A0r_fields,
   4744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4745         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4746         -1,
   4747         -1,
   4748     },
   4749 #endif /* chips */
   4750 
   4751 #if defined(BCM_88675_A0)
   4752     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88675_A0r */
   4753         soc_block_list[22],
   4754         soc_genreg,
   4755         1,
   4756         0,
   4757         0x400,
   4758         SOC_REG_FLAG_ABOVE_64_BITS,
   4759         0,
   4760         8,
   4761         soc_OAMP_BFD_TX_RATE_BCM88675_A0r_fields,
   4762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4764         -1,
   4765         -1,
   4766     },
   4767 #endif /* chips */
   4768 
   4769 #if defined(BCM_88675_B0)
   4770     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88675_B0r */
   4771         soc_block_list[22],
   4772         soc_genreg,
   4773         1,
   4774         0,
   4775         0x400,
   4776         SOC_REG_FLAG_ABOVE_64_BITS,
   4777         0,
   4778         8,
   4779         soc_OAMP_BFD_TX_RATE_BCM88675_B0r_fields,
   4780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4782         -1,
   4783         -1,
   4784     },
   4785 #endif /* chips */
   4786 
   4787 #if defined(BCM_88680_A0)
   4788     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88680_A0r */
   4789         soc_block_list[22],
   4790         soc_genreg,
   4791         1,
   4792         0,
   4793         0x400,
   4794         SOC_REG_FLAG_ABOVE_64_BITS,
   4795         0,
   4796         8,
   4797         soc_OAMP_BFD_TX_RATE_BCM88680_A0r_fields,
   4798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4800         -1,
   4801         -1,
   4802     },
   4803 #endif /* chips */
   4804 
   4805 #if defined(BCM_88690_A0)
   4806     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88690_A0r */
   4807         soc_block_list[22],
   4808         soc_genreg,
   4809         1,
   4810         0,
   4811         0x405,
   4812         SOC_REG_FLAG_ABOVE_64_BITS,
   4813         0,
   4814         8,
   4815         soc_OAMP_BFD_TX_RATE_BCM88690_A0r_fields,
   4816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4818         -1,
   4819         -1,
   4820     },
   4821 #endif /* chips */
   4822 
   4823 #if defined(BCM_88690_B0)
   4824     { /* SOC_REG_INT_OAMP_BFD_TX_RATE_BCM88690_B0r */
   4825         soc_block_list[22],
   4826         soc_genreg,
   4827         1,
   4828         0,
   4829         0x405,
   4830         SOC_REG_FLAG_ABOVE_64_BITS,
   4831         0,
   4832         8,
   4833         soc_OAMP_BFD_TX_RATE_BCM88690_B0r_fields,
   4834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4835         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4836         -1,
   4837         -1,
   4838     },
   4839 #endif /* chips */
   4840 
   4841 #if defined(BCM_88690_A0)
   4842     { /* SOC_REG_INT_OAMP_BFM_UDP_SRC_PORTr */
   4843         soc_block_list[22],
   4844         soc_genreg,
   4845         1,
   4846         0,
   4847         0xb27,
   4848         0,
   4849         0,
   4850         2,
   4851         soc_OAMP_BFM_UDP_SRC_PORTr_fields,
   4852         SOC_RESET_VAL_DEC(0x12b00ec8, 0x00000000)
   4853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4854         -1,
   4855         -1,
   4856     },
   4857 #endif /* chips */
   4858 
   4859 #if defined(BCM_88690_B0)
   4860     { /* SOC_REG_INT_OAMP_BFM_UDP_SRC_PORT_BCM88690_B0r */
   4861         soc_block_list[22],
   4862         soc_genreg,
   4863         1,
   4864         0,
   4865         0xb28,
   4866         0,
   4867         0,
   4868         2,
   4869         soc_OAMP_BFM_UDP_SRC_PORT_BCM88690_B0r_fields,
   4870         SOC_RESET_VAL_DEC(0x12b00ec8, 0x00000000)
   4871         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4872         -1,
   4873         -1,
   4874     },
   4875 #endif /* chips */
   4876 
   4877 #if defined(BCM_88650_A0)
   4878     { /* SOC_REG_INT_OAMP_CCM_MAC_SAr */
   4879         soc_block_list[22],
   4880         soc_genreg,
   4881         1,
   4882         0,
   4883         0x108,
   4884         SOC_REG_FLAG_64_BITS |
   4885                           SOC_REG_FLAG_SIGNAL,
   4886         0,
   4887         1,
   4888         soc_OAMP_CCM_MAC_SAr_fields,
   4889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4890         SOC_RESET_MASK_DEC(0xffffff00, 0x0000ffff)
   4891         -1,
   4892         -1,
   4893     },
   4894 #endif /* chips */
   4895 
   4896 #if defined(BCM_88270_A0)
   4897     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88270_A0r */
   4898         soc_block_list[22],
   4899         soc_genreg,
   4900         1,
   4901         0,
   4902         0x108,
   4903         SOC_REG_FLAG_ABOVE_64_BITS,
   4904         0,
   4905         3,
   4906         soc_OAMP_CCM_MAC_SA_BCM88270_A0r_fields,
   4907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4908         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4909         -1,
   4910         -1,
   4911     },
   4912 #endif /* chips */
   4913 
   4914 #if defined(BCM_88375_A0)
   4915     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88375_A0r */
   4916         soc_block_list[22],
   4917         soc_genreg,
   4918         1,
   4919         0,
   4920         0x108,
   4921         SOC_REG_FLAG_ABOVE_64_BITS,
   4922         0,
   4923         3,
   4924         soc_OAMP_CCM_MAC_SA_BCM88375_A0r_fields,
   4925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4926         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4927         -1,
   4928         -1,
   4929     },
   4930 #endif /* chips */
   4931 
   4932 #if defined(BCM_88375_B0)
   4933     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88375_B0r */
   4934         soc_block_list[22],
   4935         soc_genreg,
   4936         1,
   4937         0,
   4938         0x108,
   4939         SOC_REG_FLAG_ABOVE_64_BITS,
   4940         0,
   4941         3,
   4942         soc_OAMP_CCM_MAC_SA_BCM88375_B0r_fields,
   4943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4944         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4945         -1,
   4946         -1,
   4947     },
   4948 #endif /* chips */
   4949 
   4950 #if defined(BCM_88470_A0)
   4951     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88470_A0r */
   4952         soc_block_list[22],
   4953         soc_genreg,
   4954         1,
   4955         0,
   4956         0x108,
   4957         SOC_REG_FLAG_ABOVE_64_BITS,
   4958         0,
   4959         3,
   4960         soc_OAMP_CCM_MAC_SA_BCM88470_A0r_fields,
   4961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4962         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4963         -1,
   4964         -1,
   4965     },
   4966 #endif /* chips */
   4967 
   4968 #if defined(BCM_88470_B0)
   4969     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88470_B0r */
   4970         soc_block_list[22],
   4971         soc_genreg,
   4972         1,
   4973         0,
   4974         0x108,
   4975         SOC_REG_FLAG_ABOVE_64_BITS,
   4976         0,
   4977         3,
   4978         soc_OAMP_CCM_MAC_SA_BCM88470_B0r_fields,
   4979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4980         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4981         -1,
   4982         -1,
   4983     },
   4984 #endif /* chips */
   4985 
   4986 #if defined(BCM_88650_B0)
   4987     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88650_B0r */
   4988         soc_block_list[22],
   4989         soc_genreg,
   4990         1,
   4991         0,
   4992         0x108,
   4993         SOC_REG_FLAG_64_BITS |
   4994                           SOC_REG_FLAG_SIGNAL,
   4995         0,
   4996         1,
   4997         soc_OAMP_CCM_MAC_SA_BCM88650_B0r_fields,
   4998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4999         SOC_RESET_MASK_DEC(0xffffff00, 0x0000ffff)
   5000         -1,
   5001         -1,
   5002     },
   5003 #endif /* chips */
   5004 
   5005 #if defined(BCM_88660_A0)
   5006     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88660_A0r */
   5007         soc_block_list[22],
   5008         soc_genreg,
   5009         1,
   5010         0,
   5011         0x108,
   5012         SOC_REG_FLAG_64_BITS |
   5013                           SOC_REG_FLAG_SIGNAL,
   5014         0,
   5015         1,
   5016         soc_OAMP_CCM_MAC_SA_BCM88660_A0r_fields,
   5017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5018         SOC_RESET_MASK_DEC(0xffffff00, 0x0000ffff)
   5019         -1,
   5020         -1,
   5021     },
   5022 #endif /* chips */
   5023 
   5024 #if defined(BCM_88675_A0)
   5025     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88675_A0r */
   5026         soc_block_list[22],
   5027         soc_genreg,
   5028         1,
   5029         0,
   5030         0x108,
   5031         SOC_REG_FLAG_ABOVE_64_BITS,
   5032         0,
   5033         3,
   5034         soc_OAMP_CCM_MAC_SA_BCM88675_A0r_fields,
   5035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5036         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5037         -1,
   5038         -1,
   5039     },
   5040 #endif /* chips */
   5041 
   5042 #if defined(BCM_88675_B0)
   5043     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88675_B0r */
   5044         soc_block_list[22],
   5045         soc_genreg,
   5046         1,
   5047         0,
   5048         0x108,
   5049         SOC_REG_FLAG_ABOVE_64_BITS,
   5050         0,
   5051         3,
   5052         soc_OAMP_CCM_MAC_SA_BCM88675_B0r_fields,
   5053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5054         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5055         -1,
   5056         -1,
   5057     },
   5058 #endif /* chips */
   5059 
   5060 #if defined(BCM_88680_A0)
   5061     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88680_A0r */
   5062         soc_block_list[22],
   5063         soc_genreg,
   5064         1,
   5065         0,
   5066         0x108,
   5067         SOC_REG_FLAG_ABOVE_64_BITS,
   5068         0,
   5069         3,
   5070         soc_OAMP_CCM_MAC_SA_BCM88680_A0r_fields,
   5071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5072         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5073         -1,
   5074         -1,
   5075     },
   5076 #endif /* chips */
   5077 
   5078 #if defined(BCM_88690_A0)
   5079     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88690_A0r */
   5080         soc_block_list[22],
   5081         soc_genreg,
   5082         1,
   5083         0,
   5084         0x108,
   5085         SOC_REG_FLAG_ABOVE_64_BITS,
   5086         0,
   5087         3,
   5088         soc_OAMP_CCM_MAC_SA_BCM88690_A0r_fields,
   5089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5091         -1,
   5092         -1,
   5093     },
   5094 #endif /* chips */
   5095 
   5096 #if defined(BCM_88690_B0)
   5097     { /* SOC_REG_INT_OAMP_CCM_MAC_SA_BCM88690_B0r */
   5098         soc_block_list[22],
   5099         soc_genreg,
   5100         1,
   5101         0,
   5102         0x108,
   5103         SOC_REG_FLAG_ABOVE_64_BITS,
   5104         0,
   5105         3,
   5106         soc_OAMP_CCM_MAC_SA_BCM88690_B0r_fields,
   5107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5109         -1,
   5110         -1,
   5111     },
   5112 #endif /* chips */
   5113 
   5114 #if defined(BCM_88650_A0)
   5115     { /* SOC_REG_INT_OAMP_CCM_TPID_MAPr */
   5116         soc_block_list[22],
   5117         soc_genreg,
   5118         1,
   5119         0,
   5120         0x10a,
   5121         SOC_REG_FLAG_64_BITS,
   5122         0,
   5123         4,
   5124         soc_OAMP_CCM_TPID_MAPr_fields,
   5125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5126         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5127         -1,
   5128         -1,
   5129     },
   5130 #endif /* chips */
   5131 
   5132 #if defined(BCM_88270_A0)
   5133     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88270_A0r */
   5134         soc_block_list[22],
   5135         soc_genreg,
   5136         1,
   5137         0,
   5138         0x10b,
   5139         SOC_REG_FLAG_64_BITS,
   5140         0,
   5141         4,
   5142         soc_OAMP_CCM_TPID_MAP_BCM88270_A0r_fields,
   5143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5144         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5145         -1,
   5146         -1,
   5147     },
   5148 #endif /* chips */
   5149 
   5150 #if defined(BCM_88375_A0)
   5151     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88375_A0r */
   5152         soc_block_list[22],
   5153         soc_genreg,
   5154         1,
   5155         0,
   5156         0x10b,
   5157         SOC_REG_FLAG_64_BITS,
   5158         0,
   5159         4,
   5160         soc_OAMP_CCM_TPID_MAP_BCM88375_A0r_fields,
   5161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5162         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5163         -1,
   5164         -1,
   5165     },
   5166 #endif /* chips */
   5167 
   5168 #if defined(BCM_88375_B0)
   5169     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88375_B0r */
   5170         soc_block_list[22],
   5171         soc_genreg,
   5172         1,
   5173         0,
   5174         0x10b,
   5175         SOC_REG_FLAG_64_BITS,
   5176         0,
   5177         4,
   5178         soc_OAMP_CCM_TPID_MAP_BCM88375_B0r_fields,
   5179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5180         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5181         -1,
   5182         -1,
   5183     },
   5184 #endif /* chips */
   5185 
   5186 #if defined(BCM_88470_A0)
   5187     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88470_A0r */
   5188         soc_block_list[22],
   5189         soc_genreg,
   5190         1,
   5191         0,
   5192         0x10b,
   5193         SOC_REG_FLAG_64_BITS,
   5194         0,
   5195         4,
   5196         soc_OAMP_CCM_TPID_MAP_BCM88470_A0r_fields,
   5197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5198         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5199         -1,
   5200         -1,
   5201     },
   5202 #endif /* chips */
   5203 
   5204 #if defined(BCM_88470_B0)
   5205     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88470_B0r */
   5206         soc_block_list[22],
   5207         soc_genreg,
   5208         1,
   5209         0,
   5210         0x10b,
   5211         SOC_REG_FLAG_64_BITS,
   5212         0,
   5213         4,
   5214         soc_OAMP_CCM_TPID_MAP_BCM88470_B0r_fields,
   5215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5216         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5217         -1,
   5218         -1,
   5219     },
   5220 #endif /* chips */
   5221 
   5222 #if defined(BCM_88650_B0)
   5223     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88650_B0r */
   5224         soc_block_list[22],
   5225         soc_genreg,
   5226         1,
   5227         0,
   5228         0x10a,
   5229         SOC_REG_FLAG_64_BITS,
   5230         0,
   5231         4,
   5232         soc_OAMP_CCM_TPID_MAP_BCM88650_B0r_fields,
   5233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5234         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5235         -1,
   5236         -1,
   5237     },
   5238 #endif /* chips */
   5239 
   5240 #if defined(BCM_88660_A0)
   5241     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88660_A0r */
   5242         soc_block_list[22],
   5243         soc_genreg,
   5244         1,
   5245         0,
   5246         0x10a,
   5247         SOC_REG_FLAG_64_BITS,
   5248         0,
   5249         4,
   5250         soc_OAMP_CCM_TPID_MAP_BCM88660_A0r_fields,
   5251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5252         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5253         -1,
   5254         -1,
   5255     },
   5256 #endif /* chips */
   5257 
   5258 #if defined(BCM_88675_A0)
   5259     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88675_A0r */
   5260         soc_block_list[22],
   5261         soc_genreg,
   5262         1,
   5263         0,
   5264         0x10b,
   5265         SOC_REG_FLAG_64_BITS,
   5266         0,
   5267         4,
   5268         soc_OAMP_CCM_TPID_MAP_BCM88675_A0r_fields,
   5269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5270         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5271         -1,
   5272         -1,
   5273     },
   5274 #endif /* chips */
   5275 
   5276 #if defined(BCM_88675_B0)
   5277     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88675_B0r */
   5278         soc_block_list[22],
   5279         soc_genreg,
   5280         1,
   5281         0,
   5282         0x10b,
   5283         SOC_REG_FLAG_64_BITS,
   5284         0,
   5285         4,
   5286         soc_OAMP_CCM_TPID_MAP_BCM88675_B0r_fields,
   5287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5288         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5289         -1,
   5290         -1,
   5291     },
   5292 #endif /* chips */
   5293 
   5294 #if defined(BCM_88680_A0)
   5295     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88680_A0r */
   5296         soc_block_list[22],
   5297         soc_genreg,
   5298         1,
   5299         0,
   5300         0x10b,
   5301         SOC_REG_FLAG_64_BITS,
   5302         0,
   5303         4,
   5304         soc_OAMP_CCM_TPID_MAP_BCM88680_A0r_fields,
   5305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5306         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5307         -1,
   5308         -1,
   5309     },
   5310 #endif /* chips */
   5311 
   5312 #if defined(BCM_88690_A0)
   5313     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88690_A0r */
   5314         soc_block_list[22],
   5315         soc_genreg,
   5316         1,
   5317         0,
   5318         0x10b,
   5319         SOC_REG_FLAG_64_BITS,
   5320         0,
   5321         4,
   5322         soc_OAMP_CCM_TPID_MAP_BCM88690_A0r_fields,
   5323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5324         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5325         -1,
   5326         -1,
   5327     },
   5328 #endif /* chips */
   5329 
   5330 #if defined(BCM_88690_B0)
   5331     { /* SOC_REG_INT_OAMP_CCM_TPID_MAP_BCM88690_B0r */
   5332         soc_block_list[22],
   5333         soc_genreg,
   5334         1,
   5335         0,
   5336         0x10b,
   5337         SOC_REG_FLAG_64_BITS,
   5338         0,
   5339         4,
   5340         soc_OAMP_CCM_TPID_MAP_BCM88690_B0r_fields,
   5341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5342         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5343         -1,
   5344         -1,
   5345     },
   5346 #endif /* chips */
   5347 
   5348 #if defined(BCM_88470_A0)
   5349     { /* SOC_REG_INT_OAMP_CCM_TX_RATEr */
   5350         soc_block_list[22],
   5351         soc_genreg,
   5352         1,
   5353         0,
   5354         0x400,
   5355         SOC_REG_FLAG_ABOVE_64_BITS,
   5356         0,
   5357         7,
   5358         soc_OAMP_CCM_TX_RATEr_fields,
   5359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5360         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5361         -1,
   5362         -1,
   5363     },
   5364 #endif /* chips */
   5365 
   5366 #if defined(BCM_88270_A0)
   5367     { /* SOC_REG_INT_OAMP_CCM_TX_RATE_BCM88270_A0r */
   5368         soc_block_list[22],
   5369         soc_genreg,
   5370         1,
   5371         0,
   5372         0x400,
   5373         SOC_REG_FLAG_ABOVE_64_BITS,
   5374         0,
   5375         7,
   5376         soc_OAMP_CCM_TX_RATE_BCM88270_A0r_fields,
   5377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5378         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5379         -1,
   5380         -1,
   5381     },
   5382 #endif /* chips */
   5383 
   5384 #if defined(BCM_88470_B0)
   5385     { /* SOC_REG_INT_OAMP_CCM_TX_RATE_BCM88470_B0r */
   5386         soc_block_list[22],
   5387         soc_genreg,
   5388         1,
   5389         0,
   5390         0x400,
   5391         SOC_REG_FLAG_ABOVE_64_BITS,
   5392         0,
   5393         7,
   5394         soc_OAMP_CCM_TX_RATE_BCM88470_B0r_fields,
   5395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5397         -1,
   5398         -1,
   5399     },
   5400 #endif /* chips */
   5401 
   5402 #if defined(BCM_88690_A0)
   5403     { /* SOC_REG_INT_OAMP_CCM_TX_RATE_BCM88690_A0r */
   5404         soc_block_list[22],
   5405         soc_genreg,
   5406         1,
   5407         0,
   5408         0x400,
   5409         SOC_REG_FLAG_ABOVE_64_BITS,
   5410         0,
   5411         7,
   5412         soc_OAMP_CCM_TX_RATE_BCM88690_A0r_fields,
   5413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5414         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5415         -1,
   5416         -1,
   5417     },
   5418 #endif /* chips */
   5419 
   5420 #if defined(BCM_88690_B0)
   5421     { /* SOC_REG_INT_OAMP_CCM_TX_RATE_BCM88690_B0r */
   5422         soc_block_list[22],
   5423         soc_genreg,
   5424         1,
   5425         0,
   5426         0x400,
   5427         SOC_REG_FLAG_ABOVE_64_BITS,
   5428         0,
   5429         7,
   5430         soc_OAMP_CCM_TX_RATE_BCM88690_B0r_fields,
   5431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5433         -1,
   5434         -1,
   5435     },
   5436 #endif /* chips */
   5437 
   5438 #if defined(BCM_88690_B0)
   5439     { /* SOC_REG_INT_OAMP_CFG_SAT_TX_WRAP_AROUND_NUMr */
   5440         soc_block_list[22],
   5441         soc_genreg,
   5442         1,
   5443         0,
   5444         0xb17,
   5445         0,
   5446         0,
   5447         1,
   5448         soc_OAMP_CFG_SAT_TX_WRAP_AROUND_NUMr_fields,
   5449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5451         -1,
   5452         -1,
   5453     },
   5454 #endif /* chips */
   5455 
   5456 #if defined(BCM_88650_A0)
   5457     { /* SOC_REG_INT_OAMP_CPUPORTr */
   5458         soc_block_list[22],
   5459         soc_genreg,
   5460         1,
   5461         0,
   5462         0x110,
   5463         SOC_REG_FLAG_ABOVE_64_BITS |
   5464                           SOC_REG_FLAG_SIGNAL,
   5465         0,
   5466         19,
   5467         soc_OAMP_CPUPORTr_fields,
   5468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5469         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5470         -1,
   5471         -1,
   5472     },
   5473 #endif /* chips */
   5474 
   5475 #if defined(BCM_88270_A0)
   5476     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88270_A0r */
   5477         soc_block_list[22],
   5478         soc_genreg,
   5479         1,
   5480         0,
   5481         0x111,
   5482         SOC_REG_FLAG_ABOVE_64_BITS,
   5483         0,
   5484         41,
   5485         soc_OAMP_CPUPORT_BCM88270_A0r_fields,
   5486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5488         -1,
   5489         -1,
   5490     },
   5491 #endif /* chips */
   5492 
   5493 #if defined(BCM_88375_A0)
   5494     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88375_A0r */
   5495         soc_block_list[22],
   5496         soc_genreg,
   5497         1,
   5498         0,
   5499         0x110,
   5500         SOC_REG_FLAG_ABOVE_64_BITS,
   5501         0,
   5502         37,
   5503         soc_OAMP_CPUPORT_BCM88375_A0r_fields,
   5504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5505         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5506         -1,
   5507         -1,
   5508     },
   5509 #endif /* chips */
   5510 
   5511 #if defined(BCM_88375_B0)
   5512     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88375_B0r */
   5513         soc_block_list[22],
   5514         soc_genreg,
   5515         1,
   5516         0,
   5517         0x110,
   5518         SOC_REG_FLAG_ABOVE_64_BITS,
   5519         0,
   5520         37,
   5521         soc_OAMP_CPUPORT_BCM88375_B0r_fields,
   5522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5524         -1,
   5525         -1,
   5526     },
   5527 #endif /* chips */
   5528 
   5529 #if defined(BCM_88470_A0)
   5530     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88470_A0r */
   5531         soc_block_list[22],
   5532         soc_genreg,
   5533         1,
   5534         0,
   5535         0x111,
   5536         SOC_REG_FLAG_ABOVE_64_BITS,
   5537         0,
   5538         41,
   5539         soc_OAMP_CPUPORT_BCM88470_A0r_fields,
   5540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5541         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5542         -1,
   5543         -1,
   5544     },
   5545 #endif /* chips */
   5546 
   5547 #if defined(BCM_88470_B0)
   5548     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88470_B0r */
   5549         soc_block_list[22],
   5550         soc_genreg,
   5551         1,
   5552         0,
   5553         0x111,
   5554         SOC_REG_FLAG_ABOVE_64_BITS,
   5555         0,
   5556         41,
   5557         soc_OAMP_CPUPORT_BCM88470_B0r_fields,
   5558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5559         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5560         -1,
   5561         -1,
   5562     },
   5563 #endif /* chips */
   5564 
   5565 #if defined(BCM_88650_B0)
   5566     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88650_B0r */
   5567         soc_block_list[22],
   5568         soc_genreg,
   5569         1,
   5570         0,
   5571         0x110,
   5572         SOC_REG_FLAG_ABOVE_64_BITS |
   5573                           SOC_REG_FLAG_SIGNAL,
   5574         0,
   5575         19,
   5576         soc_OAMP_CPUPORT_BCM88650_B0r_fields,
   5577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5578         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5579         -1,
   5580         -1,
   5581     },
   5582 #endif /* chips */
   5583 
   5584 #if defined(BCM_88660_A0)
   5585     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88660_A0r */
   5586         soc_block_list[22],
   5587         soc_genreg,
   5588         1,
   5589         0,
   5590         0x110,
   5591         SOC_REG_FLAG_ABOVE_64_BITS |
   5592                           SOC_REG_FLAG_SIGNAL,
   5593         0,
   5594         34,
   5595         soc_OAMP_CPUPORT_BCM88660_A0r_fields,
   5596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5598         -1,
   5599         -1,
   5600     },
   5601 #endif /* chips */
   5602 
   5603 #if defined(BCM_88675_A0)
   5604     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88675_A0r */
   5605         soc_block_list[22],
   5606         soc_genreg,
   5607         1,
   5608         0,
   5609         0x110,
   5610         SOC_REG_FLAG_ABOVE_64_BITS,
   5611         0,
   5612         37,
   5613         soc_OAMP_CPUPORT_BCM88675_A0r_fields,
   5614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5616         -1,
   5617         -1,
   5618     },
   5619 #endif /* chips */
   5620 
   5621 #if defined(BCM_88675_B0)
   5622     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88675_B0r */
   5623         soc_block_list[22],
   5624         soc_genreg,
   5625         1,
   5626         0,
   5627         0x110,
   5628         SOC_REG_FLAG_ABOVE_64_BITS,
   5629         0,
   5630         37,
   5631         soc_OAMP_CPUPORT_BCM88675_B0r_fields,
   5632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5634         -1,
   5635         -1,
   5636     },
   5637 #endif /* chips */
   5638 
   5639 #if defined(BCM_88680_A0)
   5640     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88680_A0r */
   5641         soc_block_list[22],
   5642         soc_genreg,
   5643         1,
   5644         0,
   5645         0x110,
   5646         SOC_REG_FLAG_ABOVE_64_BITS,
   5647         0,
   5648         37,
   5649         soc_OAMP_CPUPORT_BCM88680_A0r_fields,
   5650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5652         -1,
   5653         -1,
   5654     },
   5655 #endif /* chips */
   5656 
   5657 #if defined(BCM_88690_A0)
   5658     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88690_A0r */
   5659         soc_block_list[22],
   5660         soc_genreg,
   5661         1,
   5662         0,
   5663         0x111,
   5664         SOC_REG_FLAG_ABOVE_64_BITS,
   5665         0,
   5666         41,
   5667         soc_OAMP_CPUPORT_BCM88690_A0r_fields,
   5668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5670         -1,
   5671         -1,
   5672     },
   5673 #endif /* chips */
   5674 
   5675 #if defined(BCM_88690_B0)
   5676     { /* SOC_REG_INT_OAMP_CPUPORT_BCM88690_B0r */
   5677         soc_block_list[22],
   5678         soc_genreg,
   5679         1,
   5680         0,
   5681         0x111,
   5682         SOC_REG_FLAG_ABOVE_64_BITS,
   5683         0,
   5684         41,
   5685         soc_OAMP_CPUPORT_BCM88690_B0r_fields,
   5686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5687         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5688         -1,
   5689         -1,
   5690     },
   5691 #endif /* chips */
   5692 
   5693 #if defined(BCM_88675_A0)
   5694     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHTr */
   5695         soc_block_list[22],
   5696         soc_genreg,
   5697         1,
   5698         0,
   5699         0x6e3,
   5700         0,
   5701         0,
   5702         4,
   5703         soc_OAMP_DMA_ARBITER_WEIGHTr_fields,
   5704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5705         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5706         -1,
   5707         -1,
   5708     },
   5709 #endif /* chips */
   5710 
   5711 #if defined(BCM_88270_A0)
   5712     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHT_BCM88270_A0r */
   5713         soc_block_list[22],
   5714         soc_genreg,
   5715         1,
   5716         0,
   5717         0x6e2,
   5718         0,
   5719         0,
   5720         5,
   5721         soc_OAMP_DMA_ARBITER_WEIGHT_BCM88270_A0r_fields,
   5722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5723         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5724         -1,
   5725         -1,
   5726     },
   5727 #endif /* chips */
   5728 
   5729 #if defined(BCM_88375_A0)
   5730     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHT_BCM88375_A0r */
   5731         soc_block_list[22],
   5732         soc_genreg,
   5733         1,
   5734         0,
   5735         0x6e3,
   5736         0,
   5737         0,
   5738         4,
   5739         soc_OAMP_DMA_ARBITER_WEIGHT_BCM88375_A0r_fields,
   5740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5741         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5742         -1,
   5743         -1,
   5744     },
   5745 #endif /* chips */
   5746 
   5747 #if defined(BCM_88375_B0)
   5748     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHT_BCM88375_B0r */
   5749         soc_block_list[22],
   5750         soc_genreg,
   5751         1,
   5752         0,
   5753         0x6e3,
   5754         0,
   5755         0,
   5756         4,
   5757         soc_OAMP_DMA_ARBITER_WEIGHT_BCM88375_B0r_fields,
   5758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5759         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5760         -1,
   5761         -1,
   5762     },
   5763 #endif /* chips */
   5764 
   5765 #if defined(BCM_88470_A0)
   5766     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHT_BCM88470_A0r */
   5767         soc_block_list[22],
   5768         soc_genreg,
   5769         1,
   5770         0,
   5771         0x6e2,
   5772         0,
   5773         0,
   5774         5,
   5775         soc_OAMP_DMA_ARBITER_WEIGHT_BCM88470_A0r_fields,
   5776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5777         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5778         -1,
   5779         -1,
   5780     },
   5781 #endif /* chips */
   5782 
   5783 #if defined(BCM_88470_B0)
   5784     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHT_BCM88470_B0r */
   5785         soc_block_list[22],
   5786         soc_genreg,
   5787         1,
   5788         0,
   5789         0x6e2,
   5790         0,
   5791         0,
   5792         5,
   5793         soc_OAMP_DMA_ARBITER_WEIGHT_BCM88470_B0r_fields,
   5794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5795         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5796         -1,
   5797         -1,
   5798     },
   5799 #endif /* chips */
   5800 
   5801 #if defined(BCM_88675_B0)
   5802     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHT_BCM88675_B0r */
   5803         soc_block_list[22],
   5804         soc_genreg,
   5805         1,
   5806         0,
   5807         0x6e3,
   5808         0,
   5809         0,
   5810         4,
   5811         soc_OAMP_DMA_ARBITER_WEIGHT_BCM88675_B0r_fields,
   5812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5813         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5814         -1,
   5815         -1,
   5816     },
   5817 #endif /* chips */
   5818 
   5819 #if defined(BCM_88680_A0)
   5820     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHT_BCM88680_A0r */
   5821         soc_block_list[22],
   5822         soc_genreg,
   5823         1,
   5824         0,
   5825         0x6e3,
   5826         0,
   5827         0,
   5828         4,
   5829         soc_OAMP_DMA_ARBITER_WEIGHT_BCM88680_A0r_fields,
   5830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5831         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5832         -1,
   5833         -1,
   5834     },
   5835 #endif /* chips */
   5836 
   5837 #if defined(BCM_88690_A0)
   5838     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHT_BCM88690_A0r */
   5839         soc_block_list[22],
   5840         soc_genreg,
   5841         1,
   5842         0,
   5843         0x66d,
   5844         0,
   5845         0,
   5846         5,
   5847         soc_OAMP_DMA_ARBITER_WEIGHT_BCM88690_A0r_fields,
   5848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5849         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5850         -1,
   5851         -1,
   5852     },
   5853 #endif /* chips */
   5854 
   5855 #if defined(BCM_88690_B0)
   5856     { /* SOC_REG_INT_OAMP_DMA_ARBITER_WEIGHT_BCM88690_B0r */
   5857         soc_block_list[22],
   5858         soc_genreg,
   5859         1,
   5860         0,
   5861         0x66d,
   5862         0,
   5863         0,
   5864         5,
   5865         soc_OAMP_DMA_ARBITER_WEIGHT_BCM88690_B0r_fields,
   5866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5867         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5868         -1,
   5869         -1,
   5870     },
   5871 #endif /* chips */
   5872 
   5873 #if defined(BCM_88675_A0)
   5874     { /* SOC_REG_INT_OAMP_DMA_COS_MAPr */
   5875         soc_block_list[22],
   5876         soc_genreg,
   5877         1,
   5878         0,
   5879         0x6e4,
   5880         0,
   5881         0,
   5882         8,
   5883         soc_OAMP_DMA_COS_MAPr_fields,
   5884         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   5885         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   5886         -1,
   5887         -1,
   5888     },
   5889 #endif /* chips */
   5890 
   5891 #if defined(BCM_88270_A0)
   5892     { /* SOC_REG_INT_OAMP_DMA_COS_MAP_BCM88270_A0r */
   5893         soc_block_list[22],
   5894         soc_genreg,
   5895         1,
   5896         0,
   5897         0x6e3,
   5898         0,
   5899         0,
   5900         9,
   5901         soc_OAMP_DMA_COS_MAP_BCM88270_A0r_fields,
   5902         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   5903         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5904         -1,
   5905         -1,
   5906     },
   5907 #endif /* chips */
   5908 
   5909 #if defined(BCM_88375_A0)
   5910     { /* SOC_REG_INT_OAMP_DMA_COS_MAP_BCM88375_A0r */
   5911         soc_block_list[22],
   5912         soc_genreg,
   5913         1,
   5914         0,
   5915         0x6e4,
   5916         0,
   5917         0,
   5918         8,
   5919         soc_OAMP_DMA_COS_MAP_BCM88375_A0r_fields,
   5920         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   5921         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   5922         -1,
   5923         -1,
   5924     },
   5925 #endif /* chips */
   5926 
   5927 #if defined(BCM_88375_B0)
   5928     { /* SOC_REG_INT_OAMP_DMA_COS_MAP_BCM88375_B0r */
   5929         soc_block_list[22],
   5930         soc_genreg,
   5931         1,
   5932         0,
   5933         0x6e4,
   5934         0,
   5935         0,
   5936         8,
   5937         soc_OAMP_DMA_COS_MAP_BCM88375_B0r_fields,
   5938         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   5939         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   5940         -1,
   5941         -1,
   5942     },
   5943 #endif /* chips */
   5944 
   5945 #if defined(BCM_88470_A0)
   5946     { /* SOC_REG_INT_OAMP_DMA_COS_MAP_BCM88470_A0r */
   5947         soc_block_list[22],
   5948         soc_genreg,
   5949         1,
   5950         0,
   5951         0x6e3,
   5952         0,
   5953         0,
   5954         9,
   5955         soc_OAMP_DMA_COS_MAP_BCM88470_A0r_fields,
   5956         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   5957         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5958         -1,
   5959         -1,
   5960     },
   5961 #endif /* chips */
   5962 
   5963 #if defined(BCM_88470_B0)
   5964     { /* SOC_REG_INT_OAMP_DMA_COS_MAP_BCM88470_B0r */
   5965         soc_block_list[22],
   5966         soc_genreg,
   5967         1,
   5968         0,
   5969         0x6e3,
   5970         0,
   5971         0,
   5972         9,
   5973         soc_OAMP_DMA_COS_MAP_BCM88470_B0r_fields,
   5974         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   5975         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5976         -1,
   5977         -1,
   5978     },
   5979 #endif /* chips */
   5980 
   5981 #if defined(BCM_88675_B0)
   5982     { /* SOC_REG_INT_OAMP_DMA_COS_MAP_BCM88675_B0r */
   5983         soc_block_list[22],
   5984         soc_genreg,
   5985         1,
   5986         0,
   5987         0x6e4,
   5988         0,
   5989         0,
   5990         8,
   5991         soc_OAMP_DMA_COS_MAP_BCM88675_B0r_fields,
   5992         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   5993         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   5994         -1,
   5995         -1,
   5996     },
   5997 #endif /* chips */
   5998 
   5999 #if defined(BCM_88680_A0)
   6000     { /* SOC_REG_INT_OAMP_DMA_COS_MAP_BCM88680_A0r */
   6001         soc_block_list[22],
   6002         soc_genreg,
   6003         1,
   6004         0,
   6005         0x6e4,
   6006         0,
   6007         0,
   6008         8,
   6009         soc_OAMP_DMA_COS_MAP_BCM88680_A0r_fields,
   6010         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   6011         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   6012         -1,
   6013         -1,
   6014     },
   6015 #endif /* chips */
   6016 
   6017 #if defined(BCM_88690_A0)
   6018     { /* SOC_REG_INT_OAMP_DMA_COS_MAP_BCM88690_A0r */
   6019         soc_block_list[22],
   6020         soc_genreg,
   6021         1,
   6022         0,
   6023         0x66e,
   6024         0,
   6025         0,
   6026         9,
   6027         soc_OAMP_DMA_COS_MAP_BCM88690_A0r_fields,
   6028         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   6029         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   6030         -1,
   6031         -1,
   6032     },
   6033 #endif /* chips */
   6034 
   6035 #if defined(BCM_88690_B0)
   6036     { /* SOC_REG_INT_OAMP_DMA_COS_MAP_BCM88690_B0r */
   6037         soc_block_list[22],
   6038         soc_genreg,
   6039         1,
   6040         0,
   6041         0x66e,
   6042         0,
   6043         0,
   6044         9,
   6045         soc_OAMP_DMA_COS_MAP_BCM88690_B0r_fields,
   6046         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   6047         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   6048         -1,
   6049         -1,
   6050     },
   6051 #endif /* chips */
   6052 
   6053 #if defined(BCM_88675_A0)
   6054     { /* SOC_REG_INT_OAMP_DMA_FIFO_MAPr */
   6055         soc_block_list[22],
   6056         soc_genreg,
   6057         1,
   6058         0,
   6059         0x6e5,
   6060         0,
   6061         0,
   6062         5,
   6063         soc_OAMP_DMA_FIFO_MAPr_fields,
   6064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6065         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   6066         -1,
   6067         -1,
   6068     },
   6069 #endif /* chips */
   6070 
   6071 #if defined(BCM_88375_A0)
   6072     { /* SOC_REG_INT_OAMP_DMA_FIFO_MAP_BCM88375_A0r */
   6073         soc_block_list[22],
   6074         soc_genreg,
   6075         1,
   6076         0,
   6077         0x6e5,
   6078         0,
   6079         0,
   6080         5,
   6081         soc_OAMP_DMA_FIFO_MAP_BCM88375_A0r_fields,
   6082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6083         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   6084         -1,
   6085         -1,
   6086     },
   6087 #endif /* chips */
   6088 
   6089 #if defined(BCM_88375_B0)
   6090     { /* SOC_REG_INT_OAMP_DMA_FIFO_MAP_BCM88375_B0r */
   6091         soc_block_list[22],
   6092         soc_genreg,
   6093         1,
   6094         0,
   6095         0x6e5,
   6096         0,
   6097         0,
   6098         5,
   6099         soc_OAMP_DMA_FIFO_MAP_BCM88375_B0r_fields,
   6100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6101         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   6102         -1,
   6103         -1,
   6104     },
   6105 #endif /* chips */
   6106 
   6107 #if defined(BCM_88675_B0)
   6108     { /* SOC_REG_INT_OAMP_DMA_FIFO_MAP_BCM88675_B0r */
   6109         soc_block_list[22],
   6110         soc_genreg,
   6111         1,
   6112         0,
   6113         0x6e5,
   6114         0,
   6115         0,
   6116         5,
   6117         soc_OAMP_DMA_FIFO_MAP_BCM88675_B0r_fields,
   6118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6119         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   6120         -1,
   6121         -1,
   6122     },
   6123 #endif /* chips */
   6124 
   6125 #if defined(BCM_88680_A0)
   6126     { /* SOC_REG_INT_OAMP_DMA_FIFO_MAP_BCM88680_A0r */
   6127         soc_block_list[22],
   6128         soc_genreg,
   6129         1,
   6130         0,
   6131         0x6e5,
   6132         0,
   6133         0,
   6134         5,
   6135         soc_OAMP_DMA_FIFO_MAP_BCM88680_A0r_fields,
   6136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6137         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   6138         -1,
   6139         -1,
   6140     },
   6141 #endif /* chips */
   6142 
   6143 #if defined(BCM_88675_A0)
   6144     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROLr */
   6145         soc_block_list[22],
   6146         soc_genreg,
   6147         1,
   6148         0,
   6149         0x6e6,
   6150         0,
   6151         0,
   6152         2,
   6153         soc_OAMP_DMA_TX_CONTROLr_fields,
   6154         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6155         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6156         -1,
   6157         -1,
   6158     },
   6159 #endif /* chips */
   6160 
   6161 #if defined(BCM_88270_A0)
   6162     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROL_BCM88270_A0r */
   6163         soc_block_list[22],
   6164         soc_genreg,
   6165         1,
   6166         0,
   6167         0x6e4,
   6168         0,
   6169         0,
   6170         2,
   6171         soc_OAMP_DMA_TX_CONTROL_BCM88270_A0r_fields,
   6172         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6173         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6174         -1,
   6175         -1,
   6176     },
   6177 #endif /* chips */
   6178 
   6179 #if defined(BCM_88375_A0)
   6180     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROL_BCM88375_A0r */
   6181         soc_block_list[22],
   6182         soc_genreg,
   6183         1,
   6184         0,
   6185         0x6e6,
   6186         0,
   6187         0,
   6188         2,
   6189         soc_OAMP_DMA_TX_CONTROL_BCM88375_A0r_fields,
   6190         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6191         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6192         -1,
   6193         -1,
   6194     },
   6195 #endif /* chips */
   6196 
   6197 #if defined(BCM_88375_B0)
   6198     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROL_BCM88375_B0r */
   6199         soc_block_list[22],
   6200         soc_genreg,
   6201         1,
   6202         0,
   6203         0x6e6,
   6204         0,
   6205         0,
   6206         2,
   6207         soc_OAMP_DMA_TX_CONTROL_BCM88375_B0r_fields,
   6208         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6209         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6210         -1,
   6211         -1,
   6212     },
   6213 #endif /* chips */
   6214 
   6215 #if defined(BCM_88470_A0)
   6216     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROL_BCM88470_A0r */
   6217         soc_block_list[22],
   6218         soc_genreg,
   6219         1,
   6220         0,
   6221         0x6e4,
   6222         0,
   6223         0,
   6224         2,
   6225         soc_OAMP_DMA_TX_CONTROL_BCM88470_A0r_fields,
   6226         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6227         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6228         -1,
   6229         -1,
   6230     },
   6231 #endif /* chips */
   6232 
   6233 #if defined(BCM_88470_B0)
   6234     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROL_BCM88470_B0r */
   6235         soc_block_list[22],
   6236         soc_genreg,
   6237         1,
   6238         0,
   6239         0x6e4,
   6240         0,
   6241         0,
   6242         2,
   6243         soc_OAMP_DMA_TX_CONTROL_BCM88470_B0r_fields,
   6244         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6245         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6246         -1,
   6247         -1,
   6248     },
   6249 #endif /* chips */
   6250 
   6251 #if defined(BCM_88675_B0)
   6252     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROL_BCM88675_B0r */
   6253         soc_block_list[22],
   6254         soc_genreg,
   6255         1,
   6256         0,
   6257         0x6e6,
   6258         0,
   6259         0,
   6260         2,
   6261         soc_OAMP_DMA_TX_CONTROL_BCM88675_B0r_fields,
   6262         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6263         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6264         -1,
   6265         -1,
   6266     },
   6267 #endif /* chips */
   6268 
   6269 #if defined(BCM_88680_A0)
   6270     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROL_BCM88680_A0r */
   6271         soc_block_list[22],
   6272         soc_genreg,
   6273         1,
   6274         0,
   6275         0x6e6,
   6276         0,
   6277         0,
   6278         2,
   6279         soc_OAMP_DMA_TX_CONTROL_BCM88680_A0r_fields,
   6280         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6281         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6282         -1,
   6283         -1,
   6284     },
   6285 #endif /* chips */
   6286 
   6287 #if defined(BCM_88690_A0)
   6288     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROL_BCM88690_A0r */
   6289         soc_block_list[22],
   6290         soc_genreg,
   6291         1,
   6292         0,
   6293         0x66f,
   6294         0,
   6295         0,
   6296         2,
   6297         soc_OAMP_DMA_TX_CONTROL_BCM88690_A0r_fields,
   6298         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6299         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6300         -1,
   6301         -1,
   6302     },
   6303 #endif /* chips */
   6304 
   6305 #if defined(BCM_88690_B0)
   6306     { /* SOC_REG_INT_OAMP_DMA_TX_CONTROL_BCM88690_B0r */
   6307         soc_block_list[22],
   6308         soc_genreg,
   6309         1,
   6310         0,
   6311         0x66f,
   6312         0,
   6313         0,
   6314         2,
   6315         soc_OAMP_DMA_TX_CONTROL_BCM88690_B0r_fields,
   6316         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
   6317         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6318         -1,
   6319         -1,
   6320     },
   6321 #endif /* chips */
   6322 
   6323 #if defined(BCM_88650_A0)
   6324     { /* SOC_REG_INT_OAMP_DOWN_PTCHr */
   6325         soc_block_list[22],
   6326         soc_genreg,
   6327         1,
   6328         0,
   6329         0x188,
   6330         SOC_REG_FLAG_SIGNAL,
   6331         0,
   6332         2,
   6333         soc_OAMP_DOWN_PTCHr_fields,
   6334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6335         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6336         -1,
   6337         -1,
   6338     },
   6339 #endif /* chips */
   6340 
   6341 #if defined(BCM_88270_A0)
   6342     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88270_A0r */
   6343         soc_block_list[22],
   6344         soc_genreg,
   6345         1,
   6346         0,
   6347         0x408,
   6348         0,
   6349         0,
   6350         2,
   6351         soc_OAMP_DOWN_PTCH_BCM88270_A0r_fields,
   6352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6353         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6354         -1,
   6355         -1,
   6356     },
   6357 #endif /* chips */
   6358 
   6359 #if defined(BCM_88375_A0)
   6360     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88375_A0r */
   6361         soc_block_list[22],
   6362         soc_genreg,
   6363         1,
   6364         0,
   6365         0x406,
   6366         0,
   6367         0,
   6368         2,
   6369         soc_OAMP_DOWN_PTCH_BCM88375_A0r_fields,
   6370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6371         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6372         -1,
   6373         -1,
   6374     },
   6375 #endif /* chips */
   6376 
   6377 #if defined(BCM_88375_B0)
   6378     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88375_B0r */
   6379         soc_block_list[22],
   6380         soc_genreg,
   6381         1,
   6382         0,
   6383         0x406,
   6384         0,
   6385         0,
   6386         2,
   6387         soc_OAMP_DOWN_PTCH_BCM88375_B0r_fields,
   6388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6389         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6390         -1,
   6391         -1,
   6392     },
   6393 #endif /* chips */
   6394 
   6395 #if defined(BCM_88470_A0)
   6396     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88470_A0r */
   6397         soc_block_list[22],
   6398         soc_genreg,
   6399         1,
   6400         0,
   6401         0x408,
   6402         0,
   6403         0,
   6404         2,
   6405         soc_OAMP_DOWN_PTCH_BCM88470_A0r_fields,
   6406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6407         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6408         -1,
   6409         -1,
   6410     },
   6411 #endif /* chips */
   6412 
   6413 #if defined(BCM_88470_B0)
   6414     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88470_B0r */
   6415         soc_block_list[22],
   6416         soc_genreg,
   6417         1,
   6418         0,
   6419         0x408,
   6420         0,
   6421         0,
   6422         2,
   6423         soc_OAMP_DOWN_PTCH_BCM88470_B0r_fields,
   6424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6425         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6426         -1,
   6427         -1,
   6428     },
   6429 #endif /* chips */
   6430 
   6431 #if defined(BCM_88650_B0)
   6432     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88650_B0r */
   6433         soc_block_list[22],
   6434         soc_genreg,
   6435         1,
   6436         0,
   6437         0x188,
   6438         SOC_REG_FLAG_SIGNAL,
   6439         0,
   6440         2,
   6441         soc_OAMP_DOWN_PTCH_BCM88650_B0r_fields,
   6442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6443         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6444         -1,
   6445         -1,
   6446     },
   6447 #endif /* chips */
   6448 
   6449 #if defined(BCM_88660_A0)
   6450     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88660_A0r */
   6451         soc_block_list[22],
   6452         soc_genreg,
   6453         1,
   6454         0,
   6455         0x406,
   6456         SOC_REG_FLAG_SIGNAL,
   6457         0,
   6458         2,
   6459         soc_OAMP_DOWN_PTCH_BCM88660_A0r_fields,
   6460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6461         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6462         -1,
   6463         -1,
   6464     },
   6465 #endif /* chips */
   6466 
   6467 #if defined(BCM_88675_A0)
   6468     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88675_A0r */
   6469         soc_block_list[22],
   6470         soc_genreg,
   6471         1,
   6472         0,
   6473         0x406,
   6474         0,
   6475         0,
   6476         2,
   6477         soc_OAMP_DOWN_PTCH_BCM88675_A0r_fields,
   6478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6479         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6480         -1,
   6481         -1,
   6482     },
   6483 #endif /* chips */
   6484 
   6485 #if defined(BCM_88675_B0)
   6486     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88675_B0r */
   6487         soc_block_list[22],
   6488         soc_genreg,
   6489         1,
   6490         0,
   6491         0x406,
   6492         0,
   6493         0,
   6494         2,
   6495         soc_OAMP_DOWN_PTCH_BCM88675_B0r_fields,
   6496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6497         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6498         -1,
   6499         -1,
   6500     },
   6501 #endif /* chips */
   6502 
   6503 #if defined(BCM_88680_A0)
   6504     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88680_A0r */
   6505         soc_block_list[22],
   6506         soc_genreg,
   6507         1,
   6508         0,
   6509         0x406,
   6510         0,
   6511         0,
   6512         2,
   6513         soc_OAMP_DOWN_PTCH_BCM88680_A0r_fields,
   6514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6515         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6516         -1,
   6517         -1,
   6518     },
   6519 #endif /* chips */
   6520 
   6521 #if defined(BCM_88690_A0)
   6522     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88690_A0r */
   6523         soc_block_list[22],
   6524         soc_genreg,
   6525         1,
   6526         0,
   6527         0x408,
   6528         0,
   6529         0,
   6530         2,
   6531         soc_OAMP_DOWN_PTCH_BCM88690_A0r_fields,
   6532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6533         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6534         -1,
   6535         -1,
   6536     },
   6537 #endif /* chips */
   6538 
   6539 #if defined(BCM_88690_B0)
   6540     { /* SOC_REG_INT_OAMP_DOWN_PTCH_BCM88690_B0r */
   6541         soc_block_list[22],
   6542         soc_genreg,
   6543         1,
   6544         0,
   6545         0x408,
   6546         0,
   6547         0,
   6548         2,
   6549         soc_OAMP_DOWN_PTCH_BCM88690_B0r_fields,
   6550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6551         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   6552         -1,
   6553         -1,
   6554     },
   6555 #endif /* chips */
   6556 
   6557 #if defined(BCM_88660_A0)
   6558     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNTr */
   6559         soc_block_list[22],
   6560         soc_genreg,
   6561         1,
   6562         0,
   6563         0x555,
   6564         SOC_REG_FLAG_RO,
   6565         0,
   6566         1,
   6567         soc_OAMP_DROPPED_EVENTS_COUNTr_fields,
   6568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6569         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6570         -1,
   6571         -1,
   6572     },
   6573 #endif /* chips */
   6574 
   6575 #if defined(BCM_88270_A0)
   6576     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88270_A0r */
   6577         soc_block_list[22],
   6578         soc_genreg,
   6579         1,
   6580         0,
   6581         0x578,
   6582         SOC_REG_FLAG_RO,
   6583         0,
   6584         1,
   6585         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88270_A0r_fields,
   6586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6587         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6588         -1,
   6589         -1,
   6590     },
   6591 #endif /* chips */
   6592 
   6593 #if defined(BCM_88375_A0)
   6594     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88375_A0r */
   6595         soc_block_list[22],
   6596         soc_genreg,
   6597         1,
   6598         0,
   6599         0x529,
   6600         SOC_REG_FLAG_RO,
   6601         0,
   6602         1,
   6603         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88375_A0r_fields,
   6604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6605         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6606         -1,
   6607         -1,
   6608     },
   6609 #endif /* chips */
   6610 
   6611 #if defined(BCM_88375_B0)
   6612     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88375_B0r */
   6613         soc_block_list[22],
   6614         soc_genreg,
   6615         1,
   6616         0,
   6617         0x529,
   6618         SOC_REG_FLAG_RO,
   6619         0,
   6620         1,
   6621         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88375_B0r_fields,
   6622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6623         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6624         -1,
   6625         -1,
   6626     },
   6627 #endif /* chips */
   6628 
   6629 #if defined(BCM_88470_A0)
   6630     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88470_A0r */
   6631         soc_block_list[22],
   6632         soc_genreg,
   6633         1,
   6634         0,
   6635         0x578,
   6636         SOC_REG_FLAG_RO,
   6637         0,
   6638         1,
   6639         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88470_A0r_fields,
   6640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6641         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6642         -1,
   6643         -1,
   6644     },
   6645 #endif /* chips */
   6646 
   6647 #if defined(BCM_88470_B0)
   6648     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88470_B0r */
   6649         soc_block_list[22],
   6650         soc_genreg,
   6651         1,
   6652         0,
   6653         0x578,
   6654         SOC_REG_FLAG_RO,
   6655         0,
   6656         1,
   6657         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88470_B0r_fields,
   6658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6659         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6660         -1,
   6661         -1,
   6662     },
   6663 #endif /* chips */
   6664 
   6665 #if defined(BCM_88675_A0)
   6666     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88675_A0r */
   6667         soc_block_list[22],
   6668         soc_genreg,
   6669         1,
   6670         0,
   6671         0x529,
   6672         SOC_REG_FLAG_RO,
   6673         0,
   6674         1,
   6675         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88675_A0r_fields,
   6676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6677         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6678         -1,
   6679         -1,
   6680     },
   6681 #endif /* chips */
   6682 
   6683 #if defined(BCM_88675_B0)
   6684     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88675_B0r */
   6685         soc_block_list[22],
   6686         soc_genreg,
   6687         1,
   6688         0,
   6689         0x529,
   6690         SOC_REG_FLAG_RO,
   6691         0,
   6692         1,
   6693         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88675_B0r_fields,
   6694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6695         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6696         -1,
   6697         -1,
   6698     },
   6699 #endif /* chips */
   6700 
   6701 #if defined(BCM_88680_A0)
   6702     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88680_A0r */
   6703         soc_block_list[22],
   6704         soc_genreg,
   6705         1,
   6706         0,
   6707         0x529,
   6708         SOC_REG_FLAG_RO,
   6709         0,
   6710         1,
   6711         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88680_A0r_fields,
   6712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6713         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6714         -1,
   6715         -1,
   6716     },
   6717 #endif /* chips */
   6718 
   6719 #if defined(BCM_88690_A0)
   6720     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88690_A0r */
   6721         soc_block_list[22],
   6722         soc_genreg,
   6723         1,
   6724         0,
   6725         0x669,
   6726         SOC_REG_FLAG_RO,
   6727         SOC_REG_FLAG_INIT_ON_READ,
   6728         1,
   6729         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88690_A0r_fields,
   6730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6731         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6732         -1,
   6733         -1,
   6734     },
   6735 #endif /* chips */
   6736 
   6737 #if defined(BCM_88690_B0)
   6738     { /* SOC_REG_INT_OAMP_DROPPED_EVENTS_COUNT_BCM88690_B0r */
   6739         soc_block_list[22],
   6740         soc_genreg,
   6741         1,
   6742         0,
   6743         0x669,
   6744         SOC_REG_FLAG_RO,
   6745         SOC_REG_FLAG_INIT_ON_READ,
   6746         1,
   6747         soc_OAMP_DROPPED_EVENTS_COUNT_BCM88690_B0r_fields,
   6748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6749         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6750         -1,
   6751         -1,
   6752     },
   6753 #endif /* chips */
   6754 
   6755 #if defined(BCM_88650_A0)
   6756     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNTr */
   6757         soc_block_list[22],
   6758         soc_genreg,
   6759         1,
   6760         0,
   6761         0x94,
   6762         SOC_REG_FLAG_64_BITS |
   6763                           SOC_REG_FLAG_RO,
   6764         0,
   6765         4,
   6766         soc_OAMP_ECC_1B_ERR_CNTr_fields,
   6767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6768         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6769         -1,
   6770         -1,
   6771     },
   6772 #endif /* chips */
   6773 
   6774 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   6775     defined(BCM_56270_A0)
   6776     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM56260_A0r */
   6777         soc_block_list[22],
   6778         soc_genreg,
   6779         1,
   6780         0,
   6781         0x2009400,
   6782         SOC_REG_FLAG_64_BITS |
   6783                           SOC_REG_FLAG_RO,
   6784         0,
   6785         4,
   6786         soc_OAMP_ECC_1B_ERR_CNT_BCM56260_A0r_fields,
   6787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6788         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6789         -1,
   6790         -1,
   6791     },
   6792 #endif /* chips */
   6793 
   6794 #if defined(BCM_88270_A0)
   6795     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88270_A0r */
   6796         soc_block_list[22],
   6797         soc_genreg,
   6798         1,
   6799         0,
   6800         0x94,
   6801         SOC_REG_FLAG_64_BITS |
   6802                           SOC_REG_FLAG_RO,
   6803         0,
   6804         4,
   6805         soc_OAMP_ECC_1B_ERR_CNT_BCM88270_A0r_fields,
   6806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6807         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6808         -1,
   6809         -1,
   6810     },
   6811 #endif /* chips */
   6812 
   6813 #if defined(BCM_88375_A0)
   6814     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88375_A0r */
   6815         soc_block_list[22],
   6816         soc_genreg,
   6817         1,
   6818         0,
   6819         0x94,
   6820         SOC_REG_FLAG_64_BITS |
   6821                           SOC_REG_FLAG_RO,
   6822         0,
   6823         4,
   6824         soc_OAMP_ECC_1B_ERR_CNT_BCM88375_A0r_fields,
   6825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6826         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6827         -1,
   6828         -1,
   6829     },
   6830 #endif /* chips */
   6831 
   6832 #if defined(BCM_88375_B0)
   6833     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88375_B0r */
   6834         soc_block_list[22],
   6835         soc_genreg,
   6836         1,
   6837         0,
   6838         0x94,
   6839         SOC_REG_FLAG_64_BITS |
   6840                           SOC_REG_FLAG_RO,
   6841         0,
   6842         4,
   6843         soc_OAMP_ECC_1B_ERR_CNT_BCM88375_B0r_fields,
   6844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6845         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6846         -1,
   6847         -1,
   6848     },
   6849 #endif /* chips */
   6850 
   6851 #if defined(BCM_88470_A0)
   6852     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88470_A0r */
   6853         soc_block_list[22],
   6854         soc_genreg,
   6855         1,
   6856         0,
   6857         0x94,
   6858         SOC_REG_FLAG_64_BITS |
   6859                           SOC_REG_FLAG_RO,
   6860         0,
   6861         4,
   6862         soc_OAMP_ECC_1B_ERR_CNT_BCM88470_A0r_fields,
   6863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6864         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6865         -1,
   6866         -1,
   6867     },
   6868 #endif /* chips */
   6869 
   6870 #if defined(BCM_88470_B0)
   6871     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88470_B0r */
   6872         soc_block_list[22],
   6873         soc_genreg,
   6874         1,
   6875         0,
   6876         0x94,
   6877         SOC_REG_FLAG_64_BITS |
   6878                           SOC_REG_FLAG_RO,
   6879         0,
   6880         4,
   6881         soc_OAMP_ECC_1B_ERR_CNT_BCM88470_B0r_fields,
   6882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6883         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6884         -1,
   6885         -1,
   6886     },
   6887 #endif /* chips */
   6888 
   6889 #if defined(BCM_88650_B0)
   6890     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88650_B0r */
   6891         soc_block_list[22],
   6892         soc_genreg,
   6893         1,
   6894         0,
   6895         0x94,
   6896         SOC_REG_FLAG_64_BITS |
   6897                           SOC_REG_FLAG_RO,
   6898         0,
   6899         4,
   6900         soc_OAMP_ECC_1B_ERR_CNT_BCM88650_B0r_fields,
   6901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6902         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6903         -1,
   6904         -1,
   6905     },
   6906 #endif /* chips */
   6907 
   6908 #if defined(BCM_88660_A0)
   6909     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88660_A0r */
   6910         soc_block_list[22],
   6911         soc_genreg,
   6912         1,
   6913         0,
   6914         0x94,
   6915         SOC_REG_FLAG_64_BITS |
   6916                           SOC_REG_FLAG_RO,
   6917         0,
   6918         4,
   6919         soc_OAMP_ECC_1B_ERR_CNT_BCM88660_A0r_fields,
   6920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6921         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6922         -1,
   6923         -1,
   6924     },
   6925 #endif /* chips */
   6926 
   6927 #if defined(BCM_88675_A0)
   6928     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88675_A0r */
   6929         soc_block_list[22],
   6930         soc_genreg,
   6931         1,
   6932         0,
   6933         0x94,
   6934         SOC_REG_FLAG_64_BITS |
   6935                           SOC_REG_FLAG_RO,
   6936         0,
   6937         4,
   6938         soc_OAMP_ECC_1B_ERR_CNT_BCM88675_A0r_fields,
   6939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6940         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6941         -1,
   6942         -1,
   6943     },
   6944 #endif /* chips */
   6945 
   6946 #if defined(BCM_88675_B0)
   6947     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88675_B0r */
   6948         soc_block_list[22],
   6949         soc_genreg,
   6950         1,
   6951         0,
   6952         0x94,
   6953         SOC_REG_FLAG_64_BITS |
   6954                           SOC_REG_FLAG_RO,
   6955         0,
   6956         4,
   6957         soc_OAMP_ECC_1B_ERR_CNT_BCM88675_B0r_fields,
   6958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6959         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6960         -1,
   6961         -1,
   6962     },
   6963 #endif /* chips */
   6964 
   6965 #if defined(BCM_88680_A0)
   6966     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88680_A0r */
   6967         soc_block_list[22],
   6968         soc_genreg,
   6969         1,
   6970         0,
   6971         0x94,
   6972         SOC_REG_FLAG_64_BITS |
   6973                           SOC_REG_FLAG_RO,
   6974         0,
   6975         4,
   6976         soc_OAMP_ECC_1B_ERR_CNT_BCM88680_A0r_fields,
   6977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6978         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6979         -1,
   6980         -1,
   6981     },
   6982 #endif /* chips */
   6983 
   6984 #if defined(BCM_88690_A0)
   6985     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88690_A0r */
   6986         soc_block_list[22],
   6987         soc_genreg,
   6988         1,
   6989         0,
   6990         0x94,
   6991         SOC_REG_FLAG_64_BITS |
   6992                           SOC_REG_FLAG_RO,
   6993         SOC_REG_FLAG_COUNTER_FEILDS |
   6994                           SOC_REG_FLAG_INIT_ON_READ,
   6995         4,
   6996         soc_OAMP_ECC_1B_ERR_CNT_BCM88690_A0r_fields,
   6997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6998         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6999         -1,
   7000         -1,
   7001     },
   7002 #endif /* chips */
   7003 
   7004 #if defined(BCM_88690_B0)
   7005     { /* SOC_REG_INT_OAMP_ECC_1B_ERR_CNT_BCM88690_B0r */
   7006         soc_block_list[22],
   7007         soc_genreg,
   7008         1,
   7009         0,
   7010         0x94,
   7011         SOC_REG_FLAG_64_BITS |
   7012                           SOC_REG_FLAG_RO,
   7013         SOC_REG_FLAG_COUNTER_FEILDS |
   7014                           SOC_REG_FLAG_INIT_ON_READ,
   7015         4,
   7016         soc_OAMP_ECC_1B_ERR_CNT_BCM88690_B0r_fields,
   7017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7018         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7019         -1,
   7020         -1,
   7021     },
   7022 #endif /* chips */
   7023 
   7024 #if defined(BCM_88650_A0)
   7025     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNTr */
   7026         soc_block_list[22],
   7027         soc_genreg,
   7028         1,
   7029         0,
   7030         0x96,
   7031         SOC_REG_FLAG_64_BITS |
   7032                           SOC_REG_FLAG_RO,
   7033         0,
   7034         4,
   7035         soc_OAMP_ECC_2B_ERR_CNTr_fields,
   7036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7037         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7038         -1,
   7039         -1,
   7040     },
   7041 #endif /* chips */
   7042 
   7043 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   7044     defined(BCM_56270_A0)
   7045     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM56260_A0r */
   7046         soc_block_list[22],
   7047         soc_genreg,
   7048         1,
   7049         0,
   7050         0x2009600,
   7051         SOC_REG_FLAG_64_BITS |
   7052                           SOC_REG_FLAG_RO,
   7053         0,
   7054         4,
   7055         soc_OAMP_ECC_2B_ERR_CNT_BCM56260_A0r_fields,
   7056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7057         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7058         -1,
   7059         -1,
   7060     },
   7061 #endif /* chips */
   7062 
   7063 #if defined(BCM_88270_A0)
   7064     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88270_A0r */
   7065         soc_block_list[22],
   7066         soc_genreg,
   7067         1,
   7068         0,
   7069         0x96,
   7070         SOC_REG_FLAG_64_BITS |
   7071                           SOC_REG_FLAG_RO,
   7072         0,
   7073         4,
   7074         soc_OAMP_ECC_2B_ERR_CNT_BCM88270_A0r_fields,
   7075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7076         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7077         -1,
   7078         -1,
   7079     },
   7080 #endif /* chips */
   7081 
   7082 #if defined(BCM_88375_A0)
   7083     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88375_A0r */
   7084         soc_block_list[22],
   7085         soc_genreg,
   7086         1,
   7087         0,
   7088         0x96,
   7089         SOC_REG_FLAG_64_BITS |
   7090                           SOC_REG_FLAG_RO,
   7091         0,
   7092         4,
   7093         soc_OAMP_ECC_2B_ERR_CNT_BCM88375_A0r_fields,
   7094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7095         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7096         -1,
   7097         -1,
   7098     },
   7099 #endif /* chips */
   7100 
   7101 #if defined(BCM_88375_B0)
   7102     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88375_B0r */
   7103         soc_block_list[22],
   7104         soc_genreg,
   7105         1,
   7106         0,
   7107         0x96,
   7108         SOC_REG_FLAG_64_BITS |
   7109                           SOC_REG_FLAG_RO,
   7110         0,
   7111         4,
   7112         soc_OAMP_ECC_2B_ERR_CNT_BCM88375_B0r_fields,
   7113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7114         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7115         -1,
   7116         -1,
   7117     },
   7118 #endif /* chips */
   7119 
   7120 #if defined(BCM_88470_A0)
   7121     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88470_A0r */
   7122         soc_block_list[22],
   7123         soc_genreg,
   7124         1,
   7125         0,
   7126         0x96,
   7127         SOC_REG_FLAG_64_BITS |
   7128                           SOC_REG_FLAG_RO,
   7129         0,
   7130         4,
   7131         soc_OAMP_ECC_2B_ERR_CNT_BCM88470_A0r_fields,
   7132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7133         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7134         -1,
   7135         -1,
   7136     },
   7137 #endif /* chips */
   7138 
   7139 #if defined(BCM_88470_B0)
   7140     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88470_B0r */
   7141         soc_block_list[22],
   7142         soc_genreg,
   7143         1,
   7144         0,
   7145         0x96,
   7146         SOC_REG_FLAG_64_BITS |
   7147                           SOC_REG_FLAG_RO,
   7148         0,
   7149         4,
   7150         soc_OAMP_ECC_2B_ERR_CNT_BCM88470_B0r_fields,
   7151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7152         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7153         -1,
   7154         -1,
   7155     },
   7156 #endif /* chips */
   7157 
   7158 #if defined(BCM_88650_B0)
   7159     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88650_B0r */
   7160         soc_block_list[22],
   7161         soc_genreg,
   7162         1,
   7163         0,
   7164         0x96,
   7165         SOC_REG_FLAG_64_BITS |
   7166                           SOC_REG_FLAG_RO,
   7167         0,
   7168         4,
   7169         soc_OAMP_ECC_2B_ERR_CNT_BCM88650_B0r_fields,
   7170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7171         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7172         -1,
   7173         -1,
   7174     },
   7175 #endif /* chips */
   7176 
   7177 #if defined(BCM_88660_A0)
   7178     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88660_A0r */
   7179         soc_block_list[22],
   7180         soc_genreg,
   7181         1,
   7182         0,
   7183         0x96,
   7184         SOC_REG_FLAG_64_BITS |
   7185                           SOC_REG_FLAG_RO,
   7186         0,
   7187         4,
   7188         soc_OAMP_ECC_2B_ERR_CNT_BCM88660_A0r_fields,
   7189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7190         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7191         -1,
   7192         -1,
   7193     },
   7194 #endif /* chips */
   7195 
   7196 #if defined(BCM_88675_A0)
   7197     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88675_A0r */
   7198         soc_block_list[22],
   7199         soc_genreg,
   7200         1,
   7201         0,
   7202         0x96,
   7203         SOC_REG_FLAG_64_BITS |
   7204                           SOC_REG_FLAG_RO,
   7205         0,
   7206         4,
   7207         soc_OAMP_ECC_2B_ERR_CNT_BCM88675_A0r_fields,
   7208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7209         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7210         -1,
   7211         -1,
   7212     },
   7213 #endif /* chips */
   7214 
   7215 #if defined(BCM_88675_B0)
   7216     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88675_B0r */
   7217         soc_block_list[22],
   7218         soc_genreg,
   7219         1,
   7220         0,
   7221         0x96,
   7222         SOC_REG_FLAG_64_BITS |
   7223                           SOC_REG_FLAG_RO,
   7224         0,
   7225         4,
   7226         soc_OAMP_ECC_2B_ERR_CNT_BCM88675_B0r_fields,
   7227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7228         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7229         -1,
   7230         -1,
   7231     },
   7232 #endif /* chips */
   7233 
   7234 #if defined(BCM_88680_A0)
   7235     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88680_A0r */
   7236         soc_block_list[22],
   7237         soc_genreg,
   7238         1,
   7239         0,
   7240         0x96,
   7241         SOC_REG_FLAG_64_BITS |
   7242                           SOC_REG_FLAG_RO,
   7243         0,
   7244         4,
   7245         soc_OAMP_ECC_2B_ERR_CNT_BCM88680_A0r_fields,
   7246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7247         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7248         -1,
   7249         -1,
   7250     },
   7251 #endif /* chips */
   7252 
   7253 #if defined(BCM_88690_A0)
   7254     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88690_A0r */
   7255         soc_block_list[22],
   7256         soc_genreg,
   7257         1,
   7258         0,
   7259         0x96,
   7260         SOC_REG_FLAG_64_BITS |
   7261                           SOC_REG_FLAG_RO,
   7262         SOC_REG_FLAG_COUNTER_FEILDS |
   7263                           SOC_REG_FLAG_INIT_ON_READ,
   7264         4,
   7265         soc_OAMP_ECC_2B_ERR_CNT_BCM88690_A0r_fields,
   7266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7267         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7268         -1,
   7269         -1,
   7270     },
   7271 #endif /* chips */
   7272 
   7273 #if defined(BCM_88690_B0)
   7274     { /* SOC_REG_INT_OAMP_ECC_2B_ERR_CNT_BCM88690_B0r */
   7275         soc_block_list[22],
   7276         soc_genreg,
   7277         1,
   7278         0,
   7279         0x96,
   7280         SOC_REG_FLAG_64_BITS |
   7281                           SOC_REG_FLAG_RO,
   7282         SOC_REG_FLAG_COUNTER_FEILDS |
   7283                           SOC_REG_FLAG_INIT_ON_READ,
   7284         4,
   7285         soc_OAMP_ECC_2B_ERR_CNT_BCM88690_B0r_fields,
   7286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7287         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7288         -1,
   7289         -1,
   7290     },
   7291 #endif /* chips */
   7292 
   7293 #if defined(BCM_88675_A0)
   7294     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_INITIATEr */
   7295         soc_block_list[22],
   7296         soc_genreg,
   7297         1,
   7298         0,
   7299         0xa4,
   7300         SOC_REG_FLAG_64_BITS,
   7301         0,
   7302         33,
   7303         soc_OAMP_ECC_ERR_1B_INITIATEr_fields,
   7304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7306         -1,
   7307         -1,
   7308     },
   7309 #endif /* chips */
   7310 
   7311 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   7312     defined(BCM_56270_A0)
   7313     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_INITIATE_BCM56260_A0r */
   7314         soc_block_list[22],
   7315         soc_genreg,
   7316         1,
   7317         0,
   7318         0x200a400,
   7319         0,
   7320         0,
   7321         7,
   7322         soc_OAMP_ECC_ERR_1B_INITIATE_BCM56260_A0r_fields,
   7323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7324         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   7325         -1,
   7326         -1,
   7327     },
   7328 #endif /* chips */
   7329 
   7330 #if defined(BCM_88270_A0)
   7331     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_INITIATE_BCM88270_A0r */
   7332         soc_block_list[22],
   7333         soc_genreg,
   7334         1,
   7335         0,
   7336         0xa4,
   7337         SOC_REG_FLAG_64_BITS,
   7338         0,
   7339         53,
   7340         soc_OAMP_ECC_ERR_1B_INITIATE_BCM88270_A0r_fields,
   7341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7342         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7343         -1,
   7344         -1,
   7345     },
   7346 #endif /* chips */
   7347 
   7348 #if defined(BCM_88375_A0)
   7349     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_INITIATE_BCM88375_A0r */
   7350         soc_block_list[22],
   7351         soc_genreg,
   7352         1,
   7353         0,
   7354         0xa4,
   7355         SOC_REG_FLAG_64_BITS,
   7356         0,
   7357         33,
   7358         soc_OAMP_ECC_ERR_1B_INITIATE_BCM88375_A0r_fields,
   7359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7360         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7361         -1,
   7362         -1,
   7363     },
   7364 #endif /* chips */
   7365 
   7366 #if defined(BCM_88375_B0)
   7367     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_INITIATE_BCM88375_B0r */
   7368         soc_block_list[22],
   7369         soc_genreg,
   7370         1,
   7371         0,
   7372         0xa4,
   7373         SOC_REG_FLAG_64_BITS,
   7374         0,
   7375         33,
   7376         soc_OAMP_ECC_ERR_1B_INITIATE_BCM88375_B0r_fields,
   7377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7378         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7379         -1,
   7380         -1,
   7381     },
   7382 #endif /* chips */
   7383 
   7384 #if defined(BCM_88470_A0)
   7385     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_INITIATE_BCM88470_A0r */
   7386         soc_block_list[22],
   7387         soc_genreg,
   7388         1,
   7389         0,
   7390         0xa4,
   7391         SOC_REG_FLAG_64_BITS,
   7392         0,
   7393         53,
   7394         soc_OAMP_ECC_ERR_1B_INITIATE_BCM88470_A0r_fields,
   7395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7396         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7397         -1,
   7398         -1,
   7399     },
   7400 #endif /* chips */
   7401 
   7402 #if defined(BCM_88470_B0)
   7403     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_INITIATE_BCM88470_B0r */
   7404         soc_block_list[22],
   7405         soc_genreg,
   7406         1,
   7407         0,
   7408         0xa4,
   7409         SOC_REG_FLAG_64_BITS,
   7410         0,
   7411         53,
   7412         soc_OAMP_ECC_ERR_1B_INITIATE_BCM88470_B0r_fields,
   7413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7414         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7415         -1,
   7416         -1,
   7417     },
   7418 #endif /* chips */
   7419 
   7420 #if defined(BCM_88675_B0)
   7421     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_INITIATE_BCM88675_B0r */
   7422         soc_block_list[22],
   7423         soc_genreg,
   7424         1,
   7425         0,
   7426         0xa4,
   7427         SOC_REG_FLAG_64_BITS,
   7428         0,
   7429         33,
   7430         soc_OAMP_ECC_ERR_1B_INITIATE_BCM88675_B0r_fields,
   7431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7433         -1,
   7434         -1,
   7435     },
   7436 #endif /* chips */
   7437 
   7438 #if defined(BCM_88680_A0)
   7439     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_INITIATE_BCM88680_A0r */
   7440         soc_block_list[22],
   7441         soc_genreg,
   7442         1,
   7443         0,
   7444         0xa4,
   7445         SOC_REG_FLAG_64_BITS,
   7446         0,
   7447         33,
   7448         soc_OAMP_ECC_ERR_1B_INITIATE_BCM88680_A0r_fields,
   7449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7451         -1,
   7452         -1,
   7453     },
   7454 #endif /* chips */
   7455 
   7456 #if defined(BCM_88675_A0)
   7457     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASKr */
   7458         soc_block_list[22],
   7459         soc_genreg,
   7460         1,
   7461         0,
   7462         0x9a,
   7463         SOC_REG_FLAG_64_BITS,
   7464         0,
   7465         33,
   7466         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
   7467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7469         -1,
   7470         -1,
   7471     },
   7472 #endif /* chips */
   7473 
   7474 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   7475     defined(BCM_56270_A0)
   7476     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM56260_A0r */
   7477         soc_block_list[22],
   7478         soc_genreg,
   7479         1,
   7480         0,
   7481         0x2009a00,
   7482         0,
   7483         0,
   7484         7,
   7485         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM56260_A0r_fields,
   7486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7487         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   7488         -1,
   7489         -1,
   7490     },
   7491 #endif /* chips */
   7492 
   7493 #if defined(BCM_88270_A0)
   7494     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88270_A0r */
   7495         soc_block_list[22],
   7496         soc_genreg,
   7497         1,
   7498         0,
   7499         0x9a,
   7500         SOC_REG_FLAG_64_BITS,
   7501         0,
   7502         53,
   7503         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88270_A0r_fields,
   7504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7505         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7506         -1,
   7507         -1,
   7508     },
   7509 #endif /* chips */
   7510 
   7511 #if defined(BCM_88375_A0)
   7512     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r */
   7513         soc_block_list[22],
   7514         soc_genreg,
   7515         1,
   7516         0,
   7517         0x9a,
   7518         SOC_REG_FLAG_64_BITS,
   7519         0,
   7520         33,
   7521         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
   7522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7524         -1,
   7525         -1,
   7526     },
   7527 #endif /* chips */
   7528 
   7529 #if defined(BCM_88375_B0)
   7530     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r */
   7531         soc_block_list[22],
   7532         soc_genreg,
   7533         1,
   7534         0,
   7535         0x9a,
   7536         SOC_REG_FLAG_64_BITS,
   7537         0,
   7538         33,
   7539         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
   7540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7542         -1,
   7543         -1,
   7544     },
   7545 #endif /* chips */
   7546 
   7547 #if defined(BCM_88470_A0)
   7548     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_A0r */
   7549         soc_block_list[22],
   7550         soc_genreg,
   7551         1,
   7552         0,
   7553         0x9a,
   7554         SOC_REG_FLAG_64_BITS,
   7555         0,
   7556         53,
   7557         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_A0r_fields,
   7558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7559         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7560         -1,
   7561         -1,
   7562     },
   7563 #endif /* chips */
   7564 
   7565 #if defined(BCM_88470_B0)
   7566     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_B0r */
   7567         soc_block_list[22],
   7568         soc_genreg,
   7569         1,
   7570         0,
   7571         0x9a,
   7572         SOC_REG_FLAG_64_BITS,
   7573         0,
   7574         53,
   7575         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_B0r_fields,
   7576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7577         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7578         -1,
   7579         -1,
   7580     },
   7581 #endif /* chips */
   7582 
   7583 #if defined(BCM_88675_B0)
   7584     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r */
   7585         soc_block_list[22],
   7586         soc_genreg,
   7587         1,
   7588         0,
   7589         0x9a,
   7590         SOC_REG_FLAG_64_BITS,
   7591         0,
   7592         33,
   7593         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
   7594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7596         -1,
   7597         -1,
   7598     },
   7599 #endif /* chips */
   7600 
   7601 #if defined(BCM_88680_A0)
   7602     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r */
   7603         soc_block_list[22],
   7604         soc_genreg,
   7605         1,
   7606         0,
   7607         0x9a,
   7608         SOC_REG_FLAG_64_BITS,
   7609         0,
   7610         33,
   7611         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
   7612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7614         -1,
   7615         -1,
   7616     },
   7617 #endif /* chips */
   7618 
   7619 #if defined(BCM_88690_A0)
   7620     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r */
   7621         soc_block_list[22],
   7622         soc_genreg,
   7623         1,
   7624         0,
   7625         0x9a,
   7626         SOC_REG_FLAG_ABOVE_64_BITS,
   7627         0,
   7628         65,
   7629         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
   7630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7632         -1,
   7633         -1,
   7634     },
   7635 #endif /* chips */
   7636 
   7637 #if defined(BCM_88690_B0)
   7638     { /* SOC_REG_INT_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r */
   7639         soc_block_list[22],
   7640         soc_genreg,
   7641         1,
   7642         0,
   7643         0x9a,
   7644         SOC_REG_FLAG_ABOVE_64_BITS,
   7645         0,
   7646         70,
   7647         soc_OAMP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
   7648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7649         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7650         -1,
   7651         -1,
   7652     },
   7653 #endif /* chips */
   7654 
   7655 #if defined(BCM_88675_A0)
   7656     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_INITIATEr */
   7657         soc_block_list[22],
   7658         soc_genreg,
   7659         1,
   7660         0,
   7661         0xa6,
   7662         SOC_REG_FLAG_64_BITS,
   7663         0,
   7664         33,
   7665         soc_OAMP_ECC_ERR_2B_INITIATEr_fields,
   7666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7667         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7668         -1,
   7669         -1,
   7670     },
   7671 #endif /* chips */
   7672 
   7673 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   7674     defined(BCM_56270_A0)
   7675     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_INITIATE_BCM56260_A0r */
   7676         soc_block_list[22],
   7677         soc_genreg,
   7678         1,
   7679         0,
   7680         0x200a600,
   7681         0,
   7682         0,
   7683         7,
   7684         soc_OAMP_ECC_ERR_2B_INITIATE_BCM56260_A0r_fields,
   7685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7686         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   7687         -1,
   7688         -1,
   7689     },
   7690 #endif /* chips */
   7691 
   7692 #if defined(BCM_88270_A0)
   7693     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_INITIATE_BCM88270_A0r */
   7694         soc_block_list[22],
   7695         soc_genreg,
   7696         1,
   7697         0,
   7698         0xa6,
   7699         SOC_REG_FLAG_64_BITS,
   7700         0,
   7701         53,
   7702         soc_OAMP_ECC_ERR_2B_INITIATE_BCM88270_A0r_fields,
   7703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7704         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7705         -1,
   7706         -1,
   7707     },
   7708 #endif /* chips */
   7709 
   7710 #if defined(BCM_88375_A0)
   7711     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_INITIATE_BCM88375_A0r */
   7712         soc_block_list[22],
   7713         soc_genreg,
   7714         1,
   7715         0,
   7716         0xa6,
   7717         SOC_REG_FLAG_64_BITS,
   7718         0,
   7719         33,
   7720         soc_OAMP_ECC_ERR_2B_INITIATE_BCM88375_A0r_fields,
   7721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7723         -1,
   7724         -1,
   7725     },
   7726 #endif /* chips */
   7727 
   7728 #if defined(BCM_88375_B0)
   7729     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_INITIATE_BCM88375_B0r */
   7730         soc_block_list[22],
   7731         soc_genreg,
   7732         1,
   7733         0,
   7734         0xa6,
   7735         SOC_REG_FLAG_64_BITS,
   7736         0,
   7737         33,
   7738         soc_OAMP_ECC_ERR_2B_INITIATE_BCM88375_B0r_fields,
   7739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7741         -1,
   7742         -1,
   7743     },
   7744 #endif /* chips */
   7745 
   7746 #if defined(BCM_88470_A0)
   7747     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_INITIATE_BCM88470_A0r */
   7748         soc_block_list[22],
   7749         soc_genreg,
   7750         1,
   7751         0,
   7752         0xa6,
   7753         SOC_REG_FLAG_64_BITS,
   7754         0,
   7755         53,
   7756         soc_OAMP_ECC_ERR_2B_INITIATE_BCM88470_A0r_fields,
   7757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7758         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7759         -1,
   7760         -1,
   7761     },
   7762 #endif /* chips */
   7763 
   7764 #if defined(BCM_88470_B0)
   7765     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_INITIATE_BCM88470_B0r */
   7766         soc_block_list[22],
   7767         soc_genreg,
   7768         1,
   7769         0,
   7770         0xa6,
   7771         SOC_REG_FLAG_64_BITS,
   7772         0,
   7773         53,
   7774         soc_OAMP_ECC_ERR_2B_INITIATE_BCM88470_B0r_fields,
   7775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7776         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7777         -1,
   7778         -1,
   7779     },
   7780 #endif /* chips */
   7781 
   7782 #if defined(BCM_88675_B0)
   7783     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_INITIATE_BCM88675_B0r */
   7784         soc_block_list[22],
   7785         soc_genreg,
   7786         1,
   7787         0,
   7788         0xa6,
   7789         SOC_REG_FLAG_64_BITS,
   7790         0,
   7791         33,
   7792         soc_OAMP_ECC_ERR_2B_INITIATE_BCM88675_B0r_fields,
   7793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7794         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7795         -1,
   7796         -1,
   7797     },
   7798 #endif /* chips */
   7799 
   7800 #if defined(BCM_88680_A0)
   7801     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_INITIATE_BCM88680_A0r */
   7802         soc_block_list[22],
   7803         soc_genreg,
   7804         1,
   7805         0,
   7806         0xa6,
   7807         SOC_REG_FLAG_64_BITS,
   7808         0,
   7809         33,
   7810         soc_OAMP_ECC_ERR_2B_INITIATE_BCM88680_A0r_fields,
   7811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7812         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7813         -1,
   7814         -1,
   7815     },
   7816 #endif /* chips */
   7817 
   7818 #if defined(BCM_88675_A0)
   7819     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASKr */
   7820         soc_block_list[22],
   7821         soc_genreg,
   7822         1,
   7823         0,
   7824         0x9c,
   7825         SOC_REG_FLAG_64_BITS,
   7826         0,
   7827         33,
   7828         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
   7829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7830         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7831         -1,
   7832         -1,
   7833     },
   7834 #endif /* chips */
   7835 
   7836 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   7837     defined(BCM_56270_A0)
   7838     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM56260_A0r */
   7839         soc_block_list[22],
   7840         soc_genreg,
   7841         1,
   7842         0,
   7843         0x2009c00,
   7844         0,
   7845         0,
   7846         7,
   7847         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM56260_A0r_fields,
   7848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7849         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   7850         -1,
   7851         -1,
   7852     },
   7853 #endif /* chips */
   7854 
   7855 #if defined(BCM_88270_A0)
   7856     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88270_A0r */
   7857         soc_block_list[22],
   7858         soc_genreg,
   7859         1,
   7860         0,
   7861         0x9c,
   7862         SOC_REG_FLAG_64_BITS,
   7863         0,
   7864         53,
   7865         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88270_A0r_fields,
   7866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7867         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7868         -1,
   7869         -1,
   7870     },
   7871 #endif /* chips */
   7872 
   7873 #if defined(BCM_88375_A0)
   7874     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r */
   7875         soc_block_list[22],
   7876         soc_genreg,
   7877         1,
   7878         0,
   7879         0x9c,
   7880         SOC_REG_FLAG_64_BITS,
   7881         0,
   7882         33,
   7883         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
   7884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7885         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7886         -1,
   7887         -1,
   7888     },
   7889 #endif /* chips */
   7890 
   7891 #if defined(BCM_88375_B0)
   7892     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r */
   7893         soc_block_list[22],
   7894         soc_genreg,
   7895         1,
   7896         0,
   7897         0x9c,
   7898         SOC_REG_FLAG_64_BITS,
   7899         0,
   7900         33,
   7901         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
   7902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7903         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7904         -1,
   7905         -1,
   7906     },
   7907 #endif /* chips */
   7908 
   7909 #if defined(BCM_88470_A0)
   7910     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_A0r */
   7911         soc_block_list[22],
   7912         soc_genreg,
   7913         1,
   7914         0,
   7915         0x9c,
   7916         SOC_REG_FLAG_64_BITS,
   7917         0,
   7918         53,
   7919         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_A0r_fields,
   7920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7921         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7922         -1,
   7923         -1,
   7924     },
   7925 #endif /* chips */
   7926 
   7927 #if defined(BCM_88470_B0)
   7928     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_B0r */
   7929         soc_block_list[22],
   7930         soc_genreg,
   7931         1,
   7932         0,
   7933         0x9c,
   7934         SOC_REG_FLAG_64_BITS,
   7935         0,
   7936         53,
   7937         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_B0r_fields,
   7938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7939         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   7940         -1,
   7941         -1,
   7942     },
   7943 #endif /* chips */
   7944 
   7945 #if defined(BCM_88675_B0)
   7946     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r */
   7947         soc_block_list[22],
   7948         soc_genreg,
   7949         1,
   7950         0,
   7951         0x9c,
   7952         SOC_REG_FLAG_64_BITS,
   7953         0,
   7954         33,
   7955         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
   7956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7957         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7958         -1,
   7959         -1,
   7960     },
   7961 #endif /* chips */
   7962 
   7963 #if defined(BCM_88680_A0)
   7964     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r */
   7965         soc_block_list[22],
   7966         soc_genreg,
   7967         1,
   7968         0,
   7969         0x9c,
   7970         SOC_REG_FLAG_64_BITS,
   7971         0,
   7972         33,
   7973         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
   7974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7975         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7976         -1,
   7977         -1,
   7978     },
   7979 #endif /* chips */
   7980 
   7981 #if defined(BCM_88690_A0)
   7982     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r */
   7983         soc_block_list[22],
   7984         soc_genreg,
   7985         1,
   7986         0,
   7987         0x9c,
   7988         SOC_REG_FLAG_ABOVE_64_BITS,
   7989         0,
   7990         65,
   7991         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
   7992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7994         -1,
   7995         -1,
   7996     },
   7997 #endif /* chips */
   7998 
   7999 #if defined(BCM_88690_B0)
   8000     { /* SOC_REG_INT_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r */
   8001         soc_block_list[22],
   8002         soc_genreg,
   8003         1,
   8004         0,
   8005         0x9c,
   8006         SOC_REG_FLAG_ABOVE_64_BITS,
   8007         0,
   8008         70,
   8009         soc_OAMP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
   8010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8012         -1,
   8013         -1,
   8014     },
   8015 #endif /* chips */
   8016 
   8017 #if defined(BCM_88650_A0)
   8018     { /* SOC_REG_INT_OAMP_ECC_ERR_MONITOR_MEM_MASKr */
   8019         soc_block_list[22],
   8020         soc_genreg,
   8021         1,
   8022         0,
   8023         0x9a,
   8024         0,
   8025         0,
   8026         2,
   8027         soc_OAMP_ECC_ERR_MONITOR_MEM_MASKr_fields,
   8028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8029         SOC_RESET_MASK_DEC(0x00000012, 0x00000000)
   8030         -1,
   8031         -1,
   8032     },
   8033 #endif /* chips */
   8034 
   8035 #if defined(BCM_88650_B0)
   8036     { /* SOC_REG_INT_OAMP_ECC_ERR_MONITOR_MEM_MASK_BCM88650_B0r */
   8037         soc_block_list[22],
   8038         soc_genreg,
   8039         1,
   8040         0,
   8041         0x9a,
   8042         0,
   8043         0,
   8044         2,
   8045         soc_OAMP_ECC_ERR_MONITOR_MEM_MASK_BCM88650_B0r_fields,
   8046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8047         SOC_RESET_MASK_DEC(0x00000012, 0x00000000)
   8048         -1,
   8049         -1,
   8050     },
   8051 #endif /* chips */
   8052 
   8053 #if defined(BCM_88660_A0)
   8054     { /* SOC_REG_INT_OAMP_ECC_ERR_MONITOR_MEM_MASK_BCM88660_A0r */
   8055         soc_block_list[22],
   8056         soc_genreg,
   8057         1,
   8058         0,
   8059         0x9a,
   8060         0,
   8061         0,
   8062         2,
   8063         soc_OAMP_ECC_ERR_MONITOR_MEM_MASK_BCM88660_A0r_fields,
   8064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8065         SOC_RESET_MASK_DEC(0x00000012, 0x00000000)
   8066         -1,
   8067         -1,
   8068     },
   8069 #endif /* chips */
   8070 
   8071 #if defined(BCM_88650_A0)
   8072     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTERr */
   8073         soc_block_list[22],
   8074         soc_genreg,
   8075         1,
   8076         0,
   8077         0x7,
   8078         SOC_REG_FLAG_INTERRUPT,
   8079         0,
   8080         3,
   8081         soc_OAMP_ECC_INTERRUPT_REGISTERr_fields,
   8082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8083         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8084         -1,
   8085         -1,
   8086     },
   8087 #endif /* chips */
   8088 
   8089 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   8090     defined(BCM_56270_A0)
   8091     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM56260_A0r */
   8092         soc_block_list[22],
   8093         soc_genreg,
   8094         1,
   8095         0,
   8096         0x2000700,
   8097         SOC_REG_FLAG_RO |
   8098                           SOC_REG_FLAG_INTERRUPT,
   8099         0,
   8100         3,
   8101         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM56260_A0r_fields,
   8102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8103         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8104         -1,
   8105         -1,
   8106     },
   8107 #endif /* chips */
   8108 
   8109 #if defined(BCM_88270_A0)
   8110     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88270_A0r */
   8111         soc_block_list[22],
   8112         soc_genreg,
   8113         1,
   8114         0,
   8115         0x7,
   8116         SOC_REG_FLAG_INTERRUPT |
   8117                           SOC_REG_FLAG_SIGNAL,
   8118         0,
   8119         3,
   8120         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88270_A0r_fields,
   8121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8122         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8123         -1,
   8124         -1,
   8125     },
   8126 #endif /* chips */
   8127 
   8128 #if defined(BCM_88375_A0)
   8129     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88375_A0r */
   8130         soc_block_list[22],
   8131         soc_genreg,
   8132         1,
   8133         0,
   8134         0x7,
   8135         SOC_REG_FLAG_INTERRUPT,
   8136         0,
   8137         3,
   8138         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88375_A0r_fields,
   8139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8140         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8141         -1,
   8142         -1,
   8143     },
   8144 #endif /* chips */
   8145 
   8146 #if defined(BCM_88375_B0)
   8147     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88375_B0r */
   8148         soc_block_list[22],
   8149         soc_genreg,
   8150         1,
   8151         0,
   8152         0x7,
   8153         SOC_REG_FLAG_INTERRUPT,
   8154         0,
   8155         3,
   8156         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88375_B0r_fields,
   8157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8158         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8159         -1,
   8160         -1,
   8161     },
   8162 #endif /* chips */
   8163 
   8164 #if defined(BCM_88470_A0)
   8165     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88470_A0r */
   8166         soc_block_list[22],
   8167         soc_genreg,
   8168         1,
   8169         0,
   8170         0x7,
   8171         SOC_REG_FLAG_INTERRUPT |
   8172                           SOC_REG_FLAG_SIGNAL,
   8173         0,
   8174         3,
   8175         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88470_A0r_fields,
   8176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8177         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8178         -1,
   8179         -1,
   8180     },
   8181 #endif /* chips */
   8182 
   8183 #if defined(BCM_88470_B0)
   8184     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88470_B0r */
   8185         soc_block_list[22],
   8186         soc_genreg,
   8187         1,
   8188         0,
   8189         0x7,
   8190         SOC_REG_FLAG_INTERRUPT |
   8191                           SOC_REG_FLAG_SIGNAL,
   8192         0,
   8193         3,
   8194         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88470_B0r_fields,
   8195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8196         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8197         -1,
   8198         -1,
   8199     },
   8200 #endif /* chips */
   8201 
   8202 #if defined(BCM_88650_B0)
   8203     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88650_B0r */
   8204         soc_block_list[22],
   8205         soc_genreg,
   8206         1,
   8207         0,
   8208         0x7,
   8209         SOC_REG_FLAG_INTERRUPT,
   8210         0,
   8211         3,
   8212         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88650_B0r_fields,
   8213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8214         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8215         -1,
   8216         -1,
   8217     },
   8218 #endif /* chips */
   8219 
   8220 #if defined(BCM_88660_A0)
   8221     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88660_A0r */
   8222         soc_block_list[22],
   8223         soc_genreg,
   8224         1,
   8225         0,
   8226         0x7,
   8227         SOC_REG_FLAG_INTERRUPT,
   8228         0,
   8229         3,
   8230         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88660_A0r_fields,
   8231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8232         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8233         -1,
   8234         -1,
   8235     },
   8236 #endif /* chips */
   8237 
   8238 #if defined(BCM_88675_A0)
   8239     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88675_A0r */
   8240         soc_block_list[22],
   8241         soc_genreg,
   8242         1,
   8243         0,
   8244         0x7,
   8245         SOC_REG_FLAG_INTERRUPT,
   8246         0,
   8247         3,
   8248         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88675_A0r_fields,
   8249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8250         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8251         -1,
   8252         -1,
   8253     },
   8254 #endif /* chips */
   8255 
   8256 #if defined(BCM_88675_B0)
   8257     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88675_B0r */
   8258         soc_block_list[22],
   8259         soc_genreg,
   8260         1,
   8261         0,
   8262         0x7,
   8263         SOC_REG_FLAG_INTERRUPT,
   8264         0,
   8265         3,
   8266         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88675_B0r_fields,
   8267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8268         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8269         -1,
   8270         -1,
   8271     },
   8272 #endif /* chips */
   8273 
   8274 #if defined(BCM_88680_A0)
   8275     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88680_A0r */
   8276         soc_block_list[22],
   8277         soc_genreg,
   8278         1,
   8279         0,
   8280         0x7,
   8281         SOC_REG_FLAG_INTERRUPT,
   8282         0,
   8283         3,
   8284         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88680_A0r_fields,
   8285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8286         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8287         -1,
   8288         -1,
   8289     },
   8290 #endif /* chips */
   8291 
   8292 #if defined(BCM_88690_A0)
   8293     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88690_A0r */
   8294         soc_block_list[22],
   8295         soc_genreg,
   8296         1,
   8297         0,
   8298         0x7,
   8299         SOC_REG_FLAG_INTERRUPT |
   8300                           SOC_REG_FLAG_SIGNAL,
   8301         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   8302         3,
   8303         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88690_A0r_fields,
   8304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8305         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8306         -1,
   8307         -1,
   8308     },
   8309 #endif /* chips */
   8310 
   8311 #if defined(BCM_88690_B0)
   8312     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
   8313         soc_block_list[22],
   8314         soc_genreg,
   8315         1,
   8316         0,
   8317         0x7,
   8318         SOC_REG_FLAG_INTERRUPT |
   8319                           SOC_REG_FLAG_SIGNAL,
   8320         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   8321         3,
   8322         soc_OAMP_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   8323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8324         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8325         -1,
   8326         -1,
   8327     },
   8328 #endif /* chips */
   8329 
   8330 #if defined(BCM_88650_A0)
   8331     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASKr */
   8332         soc_block_list[22],
   8333         soc_genreg,
   8334         1,
   8335         0,
   8336         0x17,
   8337         SOC_REG_FLAG_INTERRUPT,
   8338         0,
   8339         3,
   8340         soc_OAMP_ECC_INTERRUPT_REGISTER_MASKr_fields,
   8341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8342         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8343         -1,
   8344         -1,
   8345     },
   8346 #endif /* chips */
   8347 
   8348 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   8349     defined(BCM_56270_A0)
   8350     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM56260_A0r */
   8351         soc_block_list[22],
   8352         soc_genreg,
   8353         1,
   8354         0,
   8355         0x2001700,
   8356         SOC_REG_FLAG_RO,
   8357         0,
   8358         3,
   8359         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM56260_A0r_fields,
   8360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8361         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8362         -1,
   8363         -1,
   8364     },
   8365 #endif /* chips */
   8366 
   8367 #if defined(BCM_88270_A0)
   8368     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88270_A0r */
   8369         soc_block_list[22],
   8370         soc_genreg,
   8371         1,
   8372         0,
   8373         0x17,
   8374         0,
   8375         0,
   8376         3,
   8377         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88270_A0r_fields,
   8378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8379         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8380         -1,
   8381         -1,
   8382     },
   8383 #endif /* chips */
   8384 
   8385 #if defined(BCM_88375_A0)
   8386     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r */
   8387         soc_block_list[22],
   8388         soc_genreg,
   8389         1,
   8390         0,
   8391         0x17,
   8392         0,
   8393         0,
   8394         3,
   8395         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r_fields,
   8396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8397         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8398         -1,
   8399         -1,
   8400     },
   8401 #endif /* chips */
   8402 
   8403 #if defined(BCM_88375_B0)
   8404     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r */
   8405         soc_block_list[22],
   8406         soc_genreg,
   8407         1,
   8408         0,
   8409         0x17,
   8410         0,
   8411         0,
   8412         3,
   8413         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r_fields,
   8414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8415         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8416         -1,
   8417         -1,
   8418     },
   8419 #endif /* chips */
   8420 
   8421 #if defined(BCM_88470_A0)
   8422     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88470_A0r */
   8423         soc_block_list[22],
   8424         soc_genreg,
   8425         1,
   8426         0,
   8427         0x17,
   8428         0,
   8429         0,
   8430         3,
   8431         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88470_A0r_fields,
   8432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8433         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8434         -1,
   8435         -1,
   8436     },
   8437 #endif /* chips */
   8438 
   8439 #if defined(BCM_88470_B0)
   8440     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88470_B0r */
   8441         soc_block_list[22],
   8442         soc_genreg,
   8443         1,
   8444         0,
   8445         0x17,
   8446         0,
   8447         0,
   8448         3,
   8449         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88470_B0r_fields,
   8450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8451         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8452         -1,
   8453         -1,
   8454     },
   8455 #endif /* chips */
   8456 
   8457 #if defined(BCM_88650_B0)
   8458     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88650_B0r */
   8459         soc_block_list[22],
   8460         soc_genreg,
   8461         1,
   8462         0,
   8463         0x17,
   8464         SOC_REG_FLAG_INTERRUPT,
   8465         0,
   8466         3,
   8467         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88650_B0r_fields,
   8468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8469         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8470         -1,
   8471         -1,
   8472     },
   8473 #endif /* chips */
   8474 
   8475 #if defined(BCM_88660_A0)
   8476     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88660_A0r */
   8477         soc_block_list[22],
   8478         soc_genreg,
   8479         1,
   8480         0,
   8481         0x17,
   8482         SOC_REG_FLAG_INTERRUPT,
   8483         0,
   8484         3,
   8485         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88660_A0r_fields,
   8486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8487         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8488         -1,
   8489         -1,
   8490     },
   8491 #endif /* chips */
   8492 
   8493 #if defined(BCM_88675_A0)
   8494     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88675_A0r */
   8495         soc_block_list[22],
   8496         soc_genreg,
   8497         1,
   8498         0,
   8499         0x17,
   8500         0,
   8501         0,
   8502         3,
   8503         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88675_A0r_fields,
   8504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8505         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8506         -1,
   8507         -1,
   8508     },
   8509 #endif /* chips */
   8510 
   8511 #if defined(BCM_88675_B0)
   8512     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r */
   8513         soc_block_list[22],
   8514         soc_genreg,
   8515         1,
   8516         0,
   8517         0x17,
   8518         0,
   8519         0,
   8520         3,
   8521         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r_fields,
   8522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8523         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8524         -1,
   8525         -1,
   8526     },
   8527 #endif /* chips */
   8528 
   8529 #if defined(BCM_88680_A0)
   8530     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r */
   8531         soc_block_list[22],
   8532         soc_genreg,
   8533         1,
   8534         0,
   8535         0x17,
   8536         0,
   8537         0,
   8538         3,
   8539         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r_fields,
   8540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8541         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8542         -1,
   8543         -1,
   8544     },
   8545 #endif /* chips */
   8546 
   8547 #if defined(BCM_88690_A0)
   8548     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r */
   8549         soc_block_list[22],
   8550         soc_genreg,
   8551         1,
   8552         0,
   8553         0x17,
   8554         0,
   8555         0,
   8556         3,
   8557         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r_fields,
   8558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8559         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8560         -1,
   8561         -1,
   8562     },
   8563 #endif /* chips */
   8564 
   8565 #if defined(BCM_88690_B0)
   8566     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
   8567         soc_block_list[22],
   8568         soc_genreg,
   8569         1,
   8570         0,
   8571         0x17,
   8572         0,
   8573         0,
   8574         3,
   8575         soc_OAMP_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
   8576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8577         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8578         -1,
   8579         -1,
   8580     },
   8581 #endif /* chips */
   8582 
   8583 #if defined(BCM_88650_A0)
   8584     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TESTr */
   8585         soc_block_list[22],
   8586         soc_genreg,
   8587         1,
   8588         0,
   8589         0x1f,
   8590         SOC_REG_FLAG_INTERRUPT |
   8591                           SOC_REG_FLAG_SIGNAL,
   8592         0,
   8593         1,
   8594         soc_OAMP_ECC_INTERRUPT_REGISTER_TESTr_fields,
   8595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8596         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8597         -1,
   8598         -1,
   8599     },
   8600 #endif /* chips */
   8601 
   8602 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   8603     defined(BCM_56270_A0)
   8604     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM56260_A0r */
   8605         soc_block_list[22],
   8606         soc_genreg,
   8607         1,
   8608         0,
   8609         0x2001f00,
   8610         0,
   8611         0,
   8612         1,
   8613         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM56260_A0r_fields,
   8614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8615         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8616         -1,
   8617         -1,
   8618     },
   8619 #endif /* chips */
   8620 
   8621 #if defined(BCM_88270_A0)
   8622     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88270_A0r */
   8623         soc_block_list[22],
   8624         soc_genreg,
   8625         1,
   8626         0,
   8627         0x1f,
   8628         0,
   8629         0,
   8630         1,
   8631         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88270_A0r_fields,
   8632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8633         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8634         -1,
   8635         -1,
   8636     },
   8637 #endif /* chips */
   8638 
   8639 #if defined(BCM_88375_A0)
   8640     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
   8641         soc_block_list[22],
   8642         soc_genreg,
   8643         1,
   8644         0,
   8645         0x1f,
   8646         0,
   8647         0,
   8648         1,
   8649         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
   8650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8651         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8652         -1,
   8653         -1,
   8654     },
   8655 #endif /* chips */
   8656 
   8657 #if defined(BCM_88375_B0)
   8658     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
   8659         soc_block_list[22],
   8660         soc_genreg,
   8661         1,
   8662         0,
   8663         0x1f,
   8664         0,
   8665         0,
   8666         1,
   8667         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
   8668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8669         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8670         -1,
   8671         -1,
   8672     },
   8673 #endif /* chips */
   8674 
   8675 #if defined(BCM_88470_A0)
   8676     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88470_A0r */
   8677         soc_block_list[22],
   8678         soc_genreg,
   8679         1,
   8680         0,
   8681         0x1f,
   8682         0,
   8683         0,
   8684         1,
   8685         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88470_A0r_fields,
   8686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8687         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8688         -1,
   8689         -1,
   8690     },
   8691 #endif /* chips */
   8692 
   8693 #if defined(BCM_88470_B0)
   8694     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88470_B0r */
   8695         soc_block_list[22],
   8696         soc_genreg,
   8697         1,
   8698         0,
   8699         0x1f,
   8700         0,
   8701         0,
   8702         1,
   8703         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88470_B0r_fields,
   8704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8705         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8706         -1,
   8707         -1,
   8708     },
   8709 #endif /* chips */
   8710 
   8711 #if defined(BCM_88650_B0)
   8712     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88650_B0r */
   8713         soc_block_list[22],
   8714         soc_genreg,
   8715         1,
   8716         0,
   8717         0x1f,
   8718         SOC_REG_FLAG_INTERRUPT |
   8719                           SOC_REG_FLAG_SIGNAL,
   8720         0,
   8721         1,
   8722         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88650_B0r_fields,
   8723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8724         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8725         -1,
   8726         -1,
   8727     },
   8728 #endif /* chips */
   8729 
   8730 #if defined(BCM_88660_A0)
   8731     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88660_A0r */
   8732         soc_block_list[22],
   8733         soc_genreg,
   8734         1,
   8735         0,
   8736         0x1f,
   8737         SOC_REG_FLAG_INTERRUPT |
   8738                           SOC_REG_FLAG_SIGNAL,
   8739         0,
   8740         1,
   8741         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88660_A0r_fields,
   8742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8743         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8744         -1,
   8745         -1,
   8746     },
   8747 #endif /* chips */
   8748 
   8749 #if defined(BCM_88675_A0)
   8750     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88675_A0r */
   8751         soc_block_list[22],
   8752         soc_genreg,
   8753         1,
   8754         0,
   8755         0x1f,
   8756         0,
   8757         0,
   8758         1,
   8759         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88675_A0r_fields,
   8760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8761         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8762         -1,
   8763         -1,
   8764     },
   8765 #endif /* chips */
   8766 
   8767 #if defined(BCM_88675_B0)
   8768     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
   8769         soc_block_list[22],
   8770         soc_genreg,
   8771         1,
   8772         0,
   8773         0x1f,
   8774         0,
   8775         0,
   8776         1,
   8777         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
   8778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8779         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8780         -1,
   8781         -1,
   8782     },
   8783 #endif /* chips */
   8784 
   8785 #if defined(BCM_88680_A0)
   8786     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
   8787         soc_block_list[22],
   8788         soc_genreg,
   8789         1,
   8790         0,
   8791         0x1f,
   8792         0,
   8793         0,
   8794         1,
   8795         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
   8796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8797         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8798         -1,
   8799         -1,
   8800     },
   8801 #endif /* chips */
   8802 
   8803 #if defined(BCM_88690_A0)
   8804     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
   8805         soc_block_list[22],
   8806         soc_genreg,
   8807         1,
   8808         0,
   8809         0x1f,
   8810         0,
   8811         0,
   8812         1,
   8813         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
   8814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8815         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8816         -1,
   8817         -1,
   8818     },
   8819 #endif /* chips */
   8820 
   8821 #if defined(BCM_88690_B0)
   8822     { /* SOC_REG_INT_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   8823         soc_block_list[22],
   8824         soc_genreg,
   8825         1,
   8826         0,
   8827         0x1f,
   8828         0,
   8829         0,
   8830         1,
   8831         soc_OAMP_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   8832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8833         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8834         -1,
   8835         -1,
   8836     },
   8837 #endif /* chips */
   8838 
   8839 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   8840     defined(BCM_56270_A0)
   8841     { /* SOC_REG_INT_OAMP_ENABLEr */
   8842         soc_block_list[5],
   8843         soc_genreg,
   8844         1,
   8845         0,
   8846         0x2001900,
   8847         0,
   8848         0,
   8849         1,
   8850         soc_CMIC_BS0_HEARTBEAT_CTRL_BCM88950_A0r_fields,
   8851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8852         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8853         -1,
   8854         -1,
   8855     },
   8856 #endif /* chips */
   8857 
   8858 #if defined(BCM_88675_A0)
   8859     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESSr */
   8860         soc_block_list[22],
   8861         soc_genreg,
   8862         1,
   8863         0,
   8864         0x84,
   8865         0,
   8866         0,
   8867         1,
   8868         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
   8869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8870         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8871         -1,
   8872         -1,
   8873     },
   8874 #endif /* chips */
   8875 
   8876 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   8877     defined(BCM_56270_A0)
   8878     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM56260_A0r */
   8879         soc_block_list[22],
   8880         soc_genreg,
   8881         1,
   8882         0,
   8883         0x2008400,
   8884         0,
   8885         0,
   8886         1,
   8887         soc_DCL_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
   8888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8889         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8890         -1,
   8891         -1,
   8892     },
   8893 #endif /* chips */
   8894 
   8895 #if defined(BCM_88270_A0)
   8896     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88270_A0r */
   8897         soc_block_list[22],
   8898         soc_genreg,
   8899         1,
   8900         0,
   8901         0x84,
   8902         0,
   8903         0,
   8904         1,
   8905         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88270_A0r_fields,
   8906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8907         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8908         -1,
   8909         -1,
   8910     },
   8911 #endif /* chips */
   8912 
   8913 #if defined(BCM_88375_A0)
   8914     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_A0r */
   8915         soc_block_list[22],
   8916         soc_genreg,
   8917         1,
   8918         0,
   8919         0x84,
   8920         0,
   8921         0,
   8922         1,
   8923         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_A0r_fields,
   8924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8925         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8926         -1,
   8927         -1,
   8928     },
   8929 #endif /* chips */
   8930 
   8931 #if defined(BCM_88375_B0)
   8932     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_B0r */
   8933         soc_block_list[22],
   8934         soc_genreg,
   8935         1,
   8936         0,
   8937         0x84,
   8938         0,
   8939         0,
   8940         1,
   8941         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_B0r_fields,
   8942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8943         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8944         -1,
   8945         -1,
   8946     },
   8947 #endif /* chips */
   8948 
   8949 #if defined(BCM_88470_A0)
   8950     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_A0r */
   8951         soc_block_list[22],
   8952         soc_genreg,
   8953         1,
   8954         0,
   8955         0x84,
   8956         0,
   8957         0,
   8958         1,
   8959         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_A0r_fields,
   8960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8961         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8962         -1,
   8963         -1,
   8964     },
   8965 #endif /* chips */
   8966 
   8967 #if defined(BCM_88470_B0)
   8968     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_B0r */
   8969         soc_block_list[22],
   8970         soc_genreg,
   8971         1,
   8972         0,
   8973         0x84,
   8974         0,
   8975         0,
   8976         1,
   8977         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_B0r_fields,
   8978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8979         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8980         -1,
   8981         -1,
   8982     },
   8983 #endif /* chips */
   8984 
   8985 #if defined(BCM_88675_B0)
   8986     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_B0r */
   8987         soc_block_list[22],
   8988         soc_genreg,
   8989         1,
   8990         0,
   8991         0x84,
   8992         0,
   8993         0,
   8994         1,
   8995         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_B0r_fields,
   8996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8997         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8998         -1,
   8999         -1,
   9000     },
   9001 #endif /* chips */
   9002 
   9003 #if defined(BCM_88680_A0)
   9004     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r */
   9005         soc_block_list[22],
   9006         soc_genreg,
   9007         1,
   9008         0,
   9009         0x84,
   9010         0,
   9011         0,
   9012         1,
   9013         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r_fields,
   9014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9015         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9016         -1,
   9017         -1,
   9018     },
   9019 #endif /* chips */
   9020 
   9021 #if defined(BCM_88690_A0)
   9022     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r */
   9023         soc_block_list[22],
   9024         soc_genreg,
   9025         1,
   9026         0,
   9027         0x84,
   9028         0,
   9029         0,
   9030         1,
   9031         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r_fields,
   9032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9033         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9034         -1,
   9035         -1,
   9036     },
   9037 #endif /* chips */
   9038 
   9039 #if defined(BCM_88690_B0)
   9040     { /* SOC_REG_INT_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r */
   9041         soc_block_list[22],
   9042         soc_genreg,
   9043         1,
   9044         0,
   9045         0x84,
   9046         0,
   9047         0,
   9048         1,
   9049         soc_OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r_fields,
   9050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9051         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9052         -1,
   9053         -1,
   9054     },
   9055 #endif /* chips */
   9056 
   9057 #if defined(BCM_88650_A0)
   9058     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENTr */
   9059         soc_block_list[22],
   9060         soc_genreg,
   9061         1,
   9062         0,
   9063         0x143,
   9064         SOC_REG_FLAG_INTERRUPT |
   9065                           SOC_REG_FLAG_SIGNAL,
   9066         0,
   9067         5,
   9068         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENTr_fields,
   9069         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9070         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9071         -1,
   9072         -1,
   9073     },
   9074 #endif /* chips */
   9075 
   9076 #if defined(BCM_88270_A0)
   9077     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88270_A0r */
   9078         soc_block_list[22],
   9079         soc_genreg,
   9080         1,
   9081         0,
   9082         0x16c,
   9083         0,
   9084         0,
   9085         5,
   9086         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88270_A0r_fields,
   9087         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9088         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9089         -1,
   9090         -1,
   9091     },
   9092 #endif /* chips */
   9093 
   9094 #if defined(BCM_88375_A0)
   9095     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88375_A0r */
   9096         soc_block_list[22],
   9097         soc_genreg,
   9098         1,
   9099         0,
   9100         0x16a,
   9101         0,
   9102         0,
   9103         5,
   9104         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88375_A0r_fields,
   9105         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9106         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9107         -1,
   9108         -1,
   9109     },
   9110 #endif /* chips */
   9111 
   9112 #if defined(BCM_88375_B0)
   9113     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88375_B0r */
   9114         soc_block_list[22],
   9115         soc_genreg,
   9116         1,
   9117         0,
   9118         0x16a,
   9119         0,
   9120         0,
   9121         5,
   9122         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88375_B0r_fields,
   9123         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9124         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9125         -1,
   9126         -1,
   9127     },
   9128 #endif /* chips */
   9129 
   9130 #if defined(BCM_88470_A0)
   9131     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88470_A0r */
   9132         soc_block_list[22],
   9133         soc_genreg,
   9134         1,
   9135         0,
   9136         0x16c,
   9137         0,
   9138         0,
   9139         5,
   9140         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88470_A0r_fields,
   9141         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9142         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9143         -1,
   9144         -1,
   9145     },
   9146 #endif /* chips */
   9147 
   9148 #if defined(BCM_88470_B0)
   9149     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88470_B0r */
   9150         soc_block_list[22],
   9151         soc_genreg,
   9152         1,
   9153         0,
   9154         0x16c,
   9155         0,
   9156         0,
   9157         5,
   9158         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88470_B0r_fields,
   9159         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9160         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9161         -1,
   9162         -1,
   9163     },
   9164 #endif /* chips */
   9165 
   9166 #if defined(BCM_88650_B0)
   9167     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88650_B0r */
   9168         soc_block_list[22],
   9169         soc_genreg,
   9170         1,
   9171         0,
   9172         0x143,
   9173         SOC_REG_FLAG_INTERRUPT |
   9174                           SOC_REG_FLAG_SIGNAL,
   9175         0,
   9176         5,
   9177         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88650_B0r_fields,
   9178         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9179         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9180         -1,
   9181         -1,
   9182     },
   9183 #endif /* chips */
   9184 
   9185 #if defined(BCM_88660_A0)
   9186     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88660_A0r */
   9187         soc_block_list[22],
   9188         soc_genreg,
   9189         1,
   9190         0,
   9191         0x156,
   9192         SOC_REG_FLAG_INTERRUPT |
   9193                           SOC_REG_FLAG_SIGNAL,
   9194         0,
   9195         5,
   9196         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88660_A0r_fields,
   9197         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9198         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9199         -1,
   9200         -1,
   9201     },
   9202 #endif /* chips */
   9203 
   9204 #if defined(BCM_88675_A0)
   9205     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88675_A0r */
   9206         soc_block_list[22],
   9207         soc_genreg,
   9208         1,
   9209         0,
   9210         0x16a,
   9211         0,
   9212         0,
   9213         5,
   9214         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88675_A0r_fields,
   9215         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9216         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9217         -1,
   9218         -1,
   9219     },
   9220 #endif /* chips */
   9221 
   9222 #if defined(BCM_88675_B0)
   9223     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88675_B0r */
   9224         soc_block_list[22],
   9225         soc_genreg,
   9226         1,
   9227         0,
   9228         0x16a,
   9229         0,
   9230         0,
   9231         5,
   9232         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88675_B0r_fields,
   9233         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9234         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9235         -1,
   9236         -1,
   9237     },
   9238 #endif /* chips */
   9239 
   9240 #if defined(BCM_88680_A0)
   9241     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88680_A0r */
   9242         soc_block_list[22],
   9243         soc_genreg,
   9244         1,
   9245         0,
   9246         0x16a,
   9247         0,
   9248         0,
   9249         5,
   9250         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88680_A0r_fields,
   9251         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9252         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9253         -1,
   9254         -1,
   9255     },
   9256 #endif /* chips */
   9257 
   9258 #if defined(BCM_88690_A0)
   9259     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88690_A0r */
   9260         soc_block_list[22],
   9261         soc_genreg,
   9262         1,
   9263         0,
   9264         0x169,
   9265         0,
   9266         0,
   9267         5,
   9268         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88690_A0r_fields,
   9269         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9270         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9271         -1,
   9272         -1,
   9273     },
   9274 #endif /* chips */
   9275 
   9276 #if defined(BCM_88690_B0)
   9277     { /* SOC_REG_INT_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88690_B0r */
   9278         soc_block_list[22],
   9279         soc_genreg,
   9280         1,
   9281         0,
   9282         0x169,
   9283         0,
   9284         0,
   9285         5,
   9286         soc_OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT_BCM88690_B0r_fields,
   9287         SOC_RESET_VAL_DEC(0x0000001f, 0x00000000)
   9288         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9289         -1,
   9290         -1,
   9291     },
   9292 #endif /* chips */
   9293 
   9294 #if defined(BCM_88650_A0)
   9295     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATAr */
   9296         soc_block_list[22],
   9297         soc_genreg,
   9298         1,
   9299         0,
   9300         0xa3,
   9301         0,
   9302         0,
   9303         1,
   9304         soc_OAMP_ERROR_INITIATION_DATAr_fields,
   9305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9306         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9307         -1,
   9308         -1,
   9309     },
   9310 #endif /* chips */
   9311 
   9312 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   9313     defined(BCM_56270_A0)
   9314     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM56260_A0r */
   9315         soc_block_list[22],
   9316         soc_genreg,
   9317         1,
   9318         0,
   9319         0x200a300,
   9320         0,
   9321         0,
   9322         1,
   9323         soc_OAMP_ERROR_INITIATION_DATA_BCM56260_A0r_fields,
   9324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9325         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9326         -1,
   9327         -1,
   9328     },
   9329 #endif /* chips */
   9330 
   9331 #if defined(BCM_88270_A0)
   9332     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88270_A0r */
   9333         soc_block_list[22],
   9334         soc_genreg,
   9335         1,
   9336         0,
   9337         0xa3,
   9338         0,
   9339         0,
   9340         1,
   9341         soc_OAMP_ERROR_INITIATION_DATA_BCM88270_A0r_fields,
   9342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9343         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9344         -1,
   9345         -1,
   9346     },
   9347 #endif /* chips */
   9348 
   9349 #if defined(BCM_88375_A0)
   9350     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88375_A0r */
   9351         soc_block_list[22],
   9352         soc_genreg,
   9353         1,
   9354         0,
   9355         0xa3,
   9356         0,
   9357         0,
   9358         1,
   9359         soc_OAMP_ERROR_INITIATION_DATA_BCM88375_A0r_fields,
   9360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9361         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9362         -1,
   9363         -1,
   9364     },
   9365 #endif /* chips */
   9366 
   9367 #if defined(BCM_88375_B0)
   9368     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88375_B0r */
   9369         soc_block_list[22],
   9370         soc_genreg,
   9371         1,
   9372         0,
   9373         0xa3,
   9374         0,
   9375         0,
   9376         1,
   9377         soc_OAMP_ERROR_INITIATION_DATA_BCM88375_B0r_fields,
   9378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9379         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9380         -1,
   9381         -1,
   9382     },
   9383 #endif /* chips */
   9384 
   9385 #if defined(BCM_88470_A0)
   9386     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88470_A0r */
   9387         soc_block_list[22],
   9388         soc_genreg,
   9389         1,
   9390         0,
   9391         0xa3,
   9392         0,
   9393         0,
   9394         1,
   9395         soc_OAMP_ERROR_INITIATION_DATA_BCM88470_A0r_fields,
   9396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9397         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9398         -1,
   9399         -1,
   9400     },
   9401 #endif /* chips */
   9402 
   9403 #if defined(BCM_88470_B0)
   9404     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88470_B0r */
   9405         soc_block_list[22],
   9406         soc_genreg,
   9407         1,
   9408         0,
   9409         0xa3,
   9410         0,
   9411         0,
   9412         1,
   9413         soc_OAMP_ERROR_INITIATION_DATA_BCM88470_B0r_fields,
   9414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9415         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9416         -1,
   9417         -1,
   9418     },
   9419 #endif /* chips */
   9420 
   9421 #if defined(BCM_88650_B0)
   9422     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88650_B0r */
   9423         soc_block_list[22],
   9424         soc_genreg,
   9425         1,
   9426         0,
   9427         0xa3,
   9428         0,
   9429         0,
   9430         1,
   9431         soc_OAMP_ERROR_INITIATION_DATA_BCM88650_B0r_fields,
   9432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9433         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9434         -1,
   9435         -1,
   9436     },
   9437 #endif /* chips */
   9438 
   9439 #if defined(BCM_88660_A0)
   9440     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88660_A0r */
   9441         soc_block_list[22],
   9442         soc_genreg,
   9443         1,
   9444         0,
   9445         0xa3,
   9446         0,
   9447         0,
   9448         1,
   9449         soc_OAMP_ERROR_INITIATION_DATA_BCM88660_A0r_fields,
   9450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9451         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9452         -1,
   9453         -1,
   9454     },
   9455 #endif /* chips */
   9456 
   9457 #if defined(BCM_88675_A0)
   9458     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88675_A0r */
   9459         soc_block_list[22],
   9460         soc_genreg,
   9461         1,
   9462         0,
   9463         0xa3,
   9464         0,
   9465         0,
   9466         1,
   9467         soc_OAMP_ERROR_INITIATION_DATA_BCM88675_A0r_fields,
   9468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9469         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9470         -1,
   9471         -1,
   9472     },
   9473 #endif /* chips */
   9474 
   9475 #if defined(BCM_88675_B0)
   9476     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88675_B0r */
   9477         soc_block_list[22],
   9478         soc_genreg,
   9479         1,
   9480         0,
   9481         0xa3,
   9482         0,
   9483         0,
   9484         1,
   9485         soc_OAMP_ERROR_INITIATION_DATA_BCM88675_B0r_fields,
   9486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9487         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9488         -1,
   9489         -1,
   9490     },
   9491 #endif /* chips */
   9492 
   9493 #if defined(BCM_88680_A0)
   9494     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88680_A0r */
   9495         soc_block_list[22],
   9496         soc_genreg,
   9497         1,
   9498         0,
   9499         0xa3,
   9500         0,
   9501         0,
   9502         1,
   9503         soc_OAMP_ERROR_INITIATION_DATA_BCM88680_A0r_fields,
   9504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9505         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9506         -1,
   9507         -1,
   9508     },
   9509 #endif /* chips */
   9510 
   9511 #if defined(BCM_88690_A0)
   9512     { /* SOC_REG_INT_OAMP_ERROR_INITIATION_DATA_BCM88690_A0r */
   9513         soc_block_list[22],
   9514         soc_genreg,
   9515         1,
   9516         0,
   9517         0xa3,
   9518         0,
   9519         0,
   9520         1,
   9521         soc_OAMP_ERROR_INITIATION_DATA_BCM88690_A0r_fields,
   9522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9523         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9524         -1,
   9525         -1,
   9526     },
   9527 #endif /* chips */
   9528 
   9529 #if defined(BCM_88660_A0)
   9530     { /* SOC_REG_INT_OAMP_ETH_1731_MEP_PROFILEr */
   9531         soc_block_list[22],
   9532         soc_genreg,
   9533         1,
   9534         0,
   9535         0x44f,
   9536         SOC_REG_FLAG_ABOVE_64_BITS |
   9537                           SOC_REG_FLAG_SIGNAL,
   9538         0,
   9539         80,
   9540         soc_OAMP_ETH_1731_MEP_PROFILEr_fields,
   9541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9542         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9543         -1,
   9544         -1,
   9545     },
   9546 #endif /* chips */
   9547 
   9548 #if defined(BCM_88690_A0)
   9549     { /* SOC_REG_INT_OAMP_ETH_MAID_MISS_INFOr */
   9550         soc_block_list[22],
   9551         soc_genreg,
   9552         1,
   9553         0,
   9554         0xb00,
   9555         SOC_REG_FLAG_ABOVE_64_BITS |
   9556                           SOC_REG_FLAG_RO |
   9557                           SOC_REG_FLAG_SIGNAL,
   9558         SOC_REG_FLAG_INIT_ON_READ,
   9559         3,
   9560         soc_OAMP_ETH_MAID_MISS_INFOr_fields,
   9561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9562         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9563         -1,
   9564         -1,
   9565     },
   9566 #endif /* chips */
   9567 
   9568 #if defined(BCM_88690_B0)
   9569     { /* SOC_REG_INT_OAMP_ETH_MAID_MISS_INFO_BCM88690_B0r */
   9570         soc_block_list[22],
   9571         soc_genreg,
   9572         1,
   9573         0,
   9574         0xb00,
   9575         SOC_REG_FLAG_ABOVE_64_BITS |
   9576                           SOC_REG_FLAG_RO |
   9577                           SOC_REG_FLAG_SIGNAL,
   9578         SOC_REG_FLAG_INIT_ON_READ,
   9579         3,
   9580         soc_OAMP_ETH_MAID_MISS_INFO_BCM88690_B0r_fields,
   9581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9582         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9583         -1,
   9584         -1,
   9585     },
   9586 #endif /* chips */
   9587 
   9588 #if defined(BCM_88690_A0)
   9589     { /* SOC_REG_INT_OAMP_ETH_MDL_MISS_INFOr */
   9590         soc_block_list[22],
   9591         soc_genreg,
   9592         1,
   9593         0,
   9594         0xb09,
   9595         SOC_REG_FLAG_RO |
   9596                           SOC_REG_FLAG_SIGNAL,
   9597         SOC_REG_FLAG_INIT_ON_READ,
   9598         2,
   9599         soc_OAMP_ETH_MDL_MISS_INFOr_fields,
   9600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9601         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9602         -1,
   9603         -1,
   9604     },
   9605 #endif /* chips */
   9606 
   9607 #if defined(BCM_88690_B0)
   9608     { /* SOC_REG_INT_OAMP_ETH_MDL_MISS_INFO_BCM88690_B0r */
   9609         soc_block_list[22],
   9610         soc_genreg,
   9611         1,
   9612         0,
   9613         0xb09,
   9614         SOC_REG_FLAG_RO |
   9615                           SOC_REG_FLAG_SIGNAL,
   9616         SOC_REG_FLAG_INIT_ON_READ,
   9617         2,
   9618         soc_OAMP_ETH_MDL_MISS_INFO_BCM88690_B0r_fields,
   9619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9620         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9621         -1,
   9622         -1,
   9623     },
   9624 #endif /* chips */
   9625 
   9626 #if defined(BCM_88650_A0)
   9627     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROLr */
   9628         soc_block_list[22],
   9629         soc_genreg,
   9630         1,
   9631         0,
   9632         0x160,
   9633         SOC_REG_FLAG_SIGNAL,
   9634         0,
   9635         3,
   9636         soc_OAMP_ETH_OAM_CONTROLr_fields,
   9637         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   9638         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9639         -1,
   9640         -1,
   9641     },
   9642 #endif /* chips */
   9643 
   9644 #if defined(BCM_88270_A0)
   9645     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88270_A0r */
   9646         soc_block_list[22],
   9647         soc_genreg,
   9648         1,
   9649         0,
   9650         0x195,
   9651         0,
   9652         0,
   9653         1,
   9654         soc_OAMP_ETH_OAM_CONTROL_BCM88270_A0r_fields,
   9655         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   9656         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9657         -1,
   9658         -1,
   9659     },
   9660 #endif /* chips */
   9661 
   9662 #if defined(BCM_88375_A0)
   9663     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88375_A0r */
   9664         soc_block_list[22],
   9665         soc_genreg,
   9666         1,
   9667         0,
   9668         0x185,
   9669         0,
   9670         0,
   9671         4,
   9672         soc_OAMP_ETH_OAM_CONTROL_BCM88375_A0r_fields,
   9673         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   9674         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9675         -1,
   9676         -1,
   9677     },
   9678 #endif /* chips */
   9679 
   9680 #if defined(BCM_88375_B0)
   9681     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88375_B0r */
   9682         soc_block_list[22],
   9683         soc_genreg,
   9684         1,
   9685         0,
   9686         0x185,
   9687         0,
   9688         0,
   9689         4,
   9690         soc_OAMP_ETH_OAM_CONTROL_BCM88375_B0r_fields,
   9691         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   9692         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9693         -1,
   9694         -1,
   9695     },
   9696 #endif /* chips */
   9697 
   9698 #if defined(BCM_88470_A0)
   9699     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88470_A0r */
   9700         soc_block_list[22],
   9701         soc_genreg,
   9702         1,
   9703         0,
   9704         0x195,
   9705         0,
   9706         0,
   9707         1,
   9708         soc_OAMP_ETH_OAM_CONTROL_BCM88470_A0r_fields,
   9709         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   9710         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9711         -1,
   9712         -1,
   9713     },
   9714 #endif /* chips */
   9715 
   9716 #if defined(BCM_88470_B0)
   9717     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88470_B0r */
   9718         soc_block_list[22],
   9719         soc_genreg,
   9720         1,
   9721         0,
   9722         0x195,
   9723         0,
   9724         0,
   9725         1,
   9726         soc_OAMP_ETH_OAM_CONTROL_BCM88470_B0r_fields,
   9727         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   9728         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9729         -1,
   9730         -1,
   9731     },
   9732 #endif /* chips */
   9733 
   9734 #if defined(BCM_88650_B0)
   9735     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88650_B0r */
   9736         soc_block_list[22],
   9737         soc_genreg,
   9738         1,
   9739         0,
   9740         0x160,
   9741         SOC_REG_FLAG_SIGNAL,
   9742         0,
   9743         3,
   9744         soc_OAMP_ETH_OAM_CONTROL_BCM88650_B0r_fields,
   9745         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   9746         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9747         -1,
   9748         -1,
   9749     },
   9750 #endif /* chips */
   9751 
   9752 #if defined(BCM_88660_A0)
   9753     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88660_A0r */
   9754         soc_block_list[22],
   9755         soc_genreg,
   9756         1,
   9757         0,
   9758         0x180,
   9759         SOC_REG_FLAG_SIGNAL,
   9760         0,
   9761         4,
   9762         soc_OAMP_ETH_OAM_CONTROL_BCM88660_A0r_fields,
   9763         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   9764         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9765         -1,
   9766         -1,
   9767     },
   9768 #endif /* chips */
   9769 
   9770 #if defined(BCM_88675_A0)
   9771     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88675_A0r */
   9772         soc_block_list[22],
   9773         soc_genreg,
   9774         1,
   9775         0,
   9776         0x185,
   9777         0,
   9778         0,
   9779         4,
   9780         soc_OAMP_ETH_OAM_CONTROL_BCM88675_A0r_fields,
   9781         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   9782         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9783         -1,
   9784         -1,
   9785     },
   9786 #endif /* chips */
   9787 
   9788 #if defined(BCM_88675_B0)
   9789     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88675_B0r */
   9790         soc_block_list[22],
   9791         soc_genreg,
   9792         1,
   9793         0,
   9794         0x185,
   9795         0,
   9796         0,
   9797         4,
   9798         soc_OAMP_ETH_OAM_CONTROL_BCM88675_B0r_fields,
   9799         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   9800         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9801         -1,
   9802         -1,
   9803     },
   9804 #endif /* chips */
   9805 
   9806 #if defined(BCM_88680_A0)
   9807     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88680_A0r */
   9808         soc_block_list[22],
   9809         soc_genreg,
   9810         1,
   9811         0,
   9812         0x185,
   9813         0,
   9814         0,
   9815         4,
   9816         soc_OAMP_ETH_OAM_CONTROL_BCM88680_A0r_fields,
   9817         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   9818         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9819         -1,
   9820         -1,
   9821     },
   9822 #endif /* chips */
   9823 
   9824 #if defined(BCM_88690_A0)
   9825     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88690_A0r */
   9826         soc_block_list[22],
   9827         soc_genreg,
   9828         1,
   9829         0,
   9830         0x192,
   9831         0,
   9832         0,
   9833         1,
   9834         soc_OAMP_ETH_OAM_CONTROL_BCM88690_A0r_fields,
   9835         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   9836         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9837         -1,
   9838         -1,
   9839     },
   9840 #endif /* chips */
   9841 
   9842 #if defined(BCM_88690_B0)
   9843     { /* SOC_REG_INT_OAMP_ETH_OAM_CONTROL_BCM88690_B0r */
   9844         soc_block_list[22],
   9845         soc_genreg,
   9846         1,
   9847         0,
   9848         0x192,
   9849         0,
   9850         0,
   9851         1,
   9852         soc_OAMP_ETH_OAM_CONTROL_BCM88690_B0r_fields,
   9853         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   9854         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9855         -1,
   9856         -1,
   9857     },
   9858 #endif /* chips */
   9859 
   9860 #if defined(BCM_88690_A0)
   9861     { /* SOC_REG_INT_OAMP_ETH_PERIOD_MISS_INFOr */
   9862         soc_block_list[22],
   9863         soc_genreg,
   9864         1,
   9865         0,
   9866         0xb0b,
   9867         SOC_REG_FLAG_RO |
   9868                           SOC_REG_FLAG_SIGNAL,
   9869         SOC_REG_FLAG_INIT_ON_READ,
   9870         2,
   9871         soc_OAMP_ETH_PERIOD_MISS_INFOr_fields,
   9872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9873         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9874         -1,
   9875         -1,
   9876     },
   9877 #endif /* chips */
   9878 
   9879 #if defined(BCM_88690_B0)
   9880     { /* SOC_REG_INT_OAMP_ETH_PERIOD_MISS_INFO_BCM88690_B0r */
   9881         soc_block_list[22],
   9882         soc_genreg,
   9883         1,
   9884         0,
   9885         0xb0b,
   9886         SOC_REG_FLAG_RO |
   9887                           SOC_REG_FLAG_SIGNAL,
   9888         SOC_REG_FLAG_INIT_ON_READ,
   9889         2,
   9890         soc_OAMP_ETH_PERIOD_MISS_INFO_BCM88690_B0r_fields,
   9891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9892         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9893         -1,
   9894         -1,
   9895     },
   9896 #endif /* chips */
   9897 
   9898 #if defined(BCM_88690_A0)
   9899     { /* SOC_REG_INT_OAMP_FLEX_CRC_MISS_INFOr */
   9900         soc_block_list[22],
   9901         soc_genreg,
   9902         1,
   9903         0,
   9904         0xb0a,
   9905         SOC_REG_FLAG_RO |
   9906                           SOC_REG_FLAG_SIGNAL,
   9907         SOC_REG_FLAG_INIT_ON_READ,
   9908         2,
   9909         soc_OAMP_FLEX_CRC_MISS_INFOr_fields,
   9910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9912         -1,
   9913         -1,
   9914     },
   9915 #endif /* chips */
   9916 
   9917 #if defined(BCM_88690_B0)
   9918     { /* SOC_REG_INT_OAMP_FLEX_CRC_MISS_INFO_BCM88690_B0r */
   9919         soc_block_list[22],
   9920         soc_genreg,
   9921         1,
   9922         0,
   9923         0xb0a,
   9924         SOC_REG_FLAG_RO |
   9925                           SOC_REG_FLAG_SIGNAL,
   9926         SOC_REG_FLAG_INIT_ON_READ,
   9927         2,
   9928         soc_OAMP_FLEX_CRC_MISS_INFO_BCM88690_B0r_fields,
   9929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9930         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9931         -1,
   9932         -1,
   9933     },
   9934 #endif /* chips */
   9935 
   9936 #if defined(BCM_88470_A0)
   9937     { /* SOC_REG_INT_OAMP_GACH_CHAN_TYPESr */
   9938         soc_block_list[22],
   9939         soc_genreg,
   9940         1,
   9941         0,
   9942         0x199,
   9943         SOC_REG_FLAG_64_BITS,
   9944         0,
   9945         4,
   9946         soc_OAMP_GACH_CHAN_TYPESr_fields,
   9947         SOC_RESET_VAL_DEC(0x000c0007, 0x000b000a)
   9948         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9949         -1,
   9950         -1,
   9951     },
   9952 #endif /* chips */
   9953 
   9954 #if defined(BCM_88270_A0)
   9955     { /* SOC_REG_INT_OAMP_GACH_CHAN_TYPES_BCM88270_A0r */
   9956         soc_block_list[22],
   9957         soc_genreg,
   9958         1,
   9959         0,
   9960         0x199,
   9961         SOC_REG_FLAG_64_BITS,
   9962         0,
   9963         4,
   9964         soc_OAMP_GACH_CHAN_TYPES_BCM88270_A0r_fields,
   9965         SOC_RESET_VAL_DEC(0x000c0007, 0x000b000a)
   9966         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9967         -1,
   9968         -1,
   9969     },
   9970 #endif /* chips */
   9971 
   9972 #if defined(BCM_88470_B0)
   9973     { /* SOC_REG_INT_OAMP_GACH_CHAN_TYPES_BCM88470_B0r */
   9974         soc_block_list[22],
   9975         soc_genreg,
   9976         1,
   9977         0,
   9978         0x199,
   9979         SOC_REG_FLAG_64_BITS,
   9980         0,
   9981         4,
   9982         soc_OAMP_GACH_CHAN_TYPES_BCM88470_B0r_fields,
   9983         SOC_RESET_VAL_DEC(0x000c0007, 0x000b000a)
   9984         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9985         -1,
   9986         -1,
   9987     },
   9988 #endif /* chips */
   9989 
   9990 #if defined(BCM_88690_A0)
   9991     { /* SOC_REG_INT_OAMP_GACH_CHAN_TYPES_BCM88690_A0r */
   9992         soc_block_list[22],
   9993         soc_genreg,
   9994         1,
   9995         0,
   9996         0x196,
   9997         SOC_REG_FLAG_64_BITS,
   9998         0,
   9999         4,
  10000         soc_OAMP_GACH_CHAN_TYPES_BCM88690_A0r_fields,
  10001         SOC_RESET_VAL_DEC(0x000c0007, 0x000b000a)
  10002         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10003         -1,
  10004         -1,
  10005     },
  10006 #endif /* chips */
  10007 
  10008 #if defined(BCM_88690_B0)
  10009     { /* SOC_REG_INT_OAMP_GACH_CHAN_TYPES_BCM88690_B0r */
  10010         soc_block_list[22],
  10011         soc_genreg,
  10012         1,
  10013         0,
  10014         0x196,
  10015         SOC_REG_FLAG_64_BITS,
  10016         0,
  10017         4,
  10018         soc_OAMP_GACH_CHAN_TYPES_BCM88690_B0r_fields,
  10019         SOC_RESET_VAL_DEC(0x000c0007, 0x000b000a)
  10020         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10021         -1,
  10022         -1,
  10023     },
  10024 #endif /* chips */
  10025 
  10026 #if defined(BCM_88650_B0)
  10027     { /* SOC_REG_INT_OAMP_GLOBAL_Fr */
  10028         soc_block_list[22],
  10029         soc_genreg,
  10030         1,
  10031         0,
  10032         0xcf,
  10033         0,
  10034         0,
  10035         6,
  10036         soc_OAMP_GLOBAL_Fr_fields,
  10037         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10038         SOC_RESET_MASK_DEC(0x0001c00f, 0x00000000)
  10039         -1,
  10040         -1,
  10041     },
  10042 #endif /* chips */
  10043 
  10044 #if defined(BCM_88660_A0)
  10045     { /* SOC_REG_INT_OAMP_GLOBAL_F_BCM88660_A0r */
  10046         soc_block_list[22],
  10047         soc_genreg,
  10048         1,
  10049         0,
  10050         0xcf,
  10051         0,
  10052         0,
  10053         6,
  10054         soc_OAMP_GLOBAL_F_BCM88660_A0r_fields,
  10055         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10056         SOC_RESET_MASK_DEC(0x0001c00f, 0x00000000)
  10057         -1,
  10058         -1,
  10059     },
  10060 #endif /* chips */
  10061 
  10062 #if defined(BCM_88675_A0)
  10063     { /* SOC_REG_INT_OAMP_GLOBAL_MEM_OPTIONSr */
  10064         soc_block_list[22],
  10065         soc_genreg,
  10066         1,
  10067         0,
  10068         0xc0,
  10069         0,
  10070         0,
  10071         4,
  10072         soc_OAMP_GLOBAL_MEM_OPTIONSr_fields,
  10073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10074         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  10075         -1,
  10076         -1,
  10077     },
  10078 #endif /* chips */
  10079 
  10080 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10081     defined(BCM_56270_A0)
  10082     { /* SOC_REG_INT_OAMP_GLOBAL_MEM_OPTIONS_BCM56260_A0r */
  10083         soc_block_list[22],
  10084         soc_genreg,
  10085         1,
  10086         0,
  10087         0x200c000,
  10088         0,
  10089         0,
  10090         4,
  10091         soc_OAMP_GLOBAL_MEM_OPTIONS_BCM56260_A0r_fields,
  10092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10093         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  10094         -1,
  10095         -1,
  10096     },
  10097 #endif /* chips */
  10098 
  10099 #if defined(BCM_88270_A0)
  10100     { /* SOC_REG_INT_OAMP_GLOBAL_MEM_OPTIONS_BCM88270_A0r */
  10101         soc_block_list[22],
  10102         soc_genreg,
  10103         1,
  10104         0,
  10105         0xc0,
  10106         0,
  10107         0,
  10108         6,
  10109         soc_OAMP_GLOBAL_MEM_OPTIONS_BCM88270_A0r_fields,
  10110         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  10111         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  10112         -1,
  10113         -1,
  10114     },
  10115 #endif /* chips */
  10116 
  10117 #if defined(BCM_88375_A0)
  10118     { /* SOC_REG_INT_OAMP_GLOBAL_MEM_OPTIONS_BCM88375_A0r */
  10119         soc_block_list[22],
  10120         soc_genreg,
  10121         1,
  10122         0,
  10123         0xc0,
  10124         0,
  10125         0,
  10126         4,
  10127         soc_OAMP_GLOBAL_MEM_OPTIONS_BCM88375_A0r_fields,
  10128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10129         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  10130         -1,
  10131         -1,
  10132     },
  10133 #endif /* chips */
  10134 
  10135 #if defined(BCM_88375_B0)
  10136     { /* SOC_REG_INT_OAMP_GLOBAL_MEM_OPTIONS_BCM88375_B0r */
  10137         soc_block_list[22],
  10138         soc_genreg,
  10139         1,
  10140         0,
  10141         0xc0,
  10142         0,
  10143         0,
  10144         4,
  10145         soc_OAMP_GLOBAL_MEM_OPTIONS_BCM88375_B0r_fields,
  10146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10147         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  10148         -1,
  10149         -1,
  10150     },
  10151 #endif /* chips */
  10152 
  10153 #if defined(BCM_88470_A0)
  10154     { /* SOC_REG_INT_OAMP_GLOBAL_MEM_OPTIONS_BCM88470_A0r */
  10155         soc_block_list[22],
  10156         soc_genreg,
  10157         1,
  10158         0,
  10159         0xc0,
  10160         0,
  10161         0,
  10162         6,
  10163         soc_OAMP_GLOBAL_MEM_OPTIONS_BCM88470_A0r_fields,
  10164         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  10165         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  10166         -1,
  10167         -1,
  10168     },
  10169 #endif /* chips */
  10170 
  10171 #if defined(BCM_88470_B0)
  10172     { /* SOC_REG_INT_OAMP_GLOBAL_MEM_OPTIONS_BCM88470_B0r */
  10173         soc_block_list[22],
  10174         soc_genreg,
  10175         1,
  10176         0,
  10177         0xc0,
  10178         0,
  10179         0,
  10180         6,
  10181         soc_OAMP_GLOBAL_MEM_OPTIONS_BCM88470_B0r_fields,
  10182         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  10183         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  10184         -1,
  10185         -1,
  10186     },
  10187 #endif /* chips */
  10188 
  10189 #if defined(BCM_88675_B0)
  10190     { /* SOC_REG_INT_OAMP_GLOBAL_MEM_OPTIONS_BCM88675_B0r */
  10191         soc_block_list[22],
  10192         soc_genreg,
  10193         1,
  10194         0,
  10195         0xc0,
  10196         0,
  10197         0,
  10198         4,
  10199         soc_OAMP_GLOBAL_MEM_OPTIONS_BCM88675_B0r_fields,
  10200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10201         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  10202         -1,
  10203         -1,
  10204     },
  10205 #endif /* chips */
  10206 
  10207 #if defined(BCM_88680_A0)
  10208     { /* SOC_REG_INT_OAMP_GLOBAL_MEM_OPTIONS_BCM88680_A0r */
  10209         soc_block_list[22],
  10210         soc_genreg,
  10211         1,
  10212         0,
  10213         0xc0,
  10214         0,
  10215         0,
  10216         4,
  10217         soc_OAMP_GLOBAL_MEM_OPTIONS_BCM88680_A0r_fields,
  10218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10219         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  10220         -1,
  10221         -1,
  10222     },
  10223 #endif /* chips */
  10224 
  10225 #if defined(BCM_88675_A0)
  10226     { /* SOC_REG_INT_OAMP_GLOBAL_SYS_HEADER_CFGr */
  10227         soc_block_list[22],
  10228         soc_genreg,
  10229         1,
  10230         0,
  10231         0xc5,
  10232         0,
  10233         0,
  10234         4,
  10235         soc_OAMP_GLOBAL_SYS_HEADER_CFGr_fields,
  10236         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10237         SOC_RESET_MASK_DEC(0x0000006f, 0x00000000)
  10238         -1,
  10239         -1,
  10240     },
  10241 #endif /* chips */
  10242 
  10243 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10244     defined(BCM_56270_A0)
  10245     { /* SOC_REG_INT_OAMP_GLOBAL_SYS_HEADER_CFG_BCM56260_A0r */
  10246         soc_block_list[22],
  10247         soc_genreg,
  10248         1,
  10249         0,
  10250         0x200c500,
  10251         0,
  10252         0,
  10253         4,
  10254         soc_ECI_GLOBAL_SYS_HEADER_CFG_BCM88950_A0r_fields,
  10255         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10256         SOC_RESET_MASK_DEC(0x0000006f, 0x00000000)
  10257         -1,
  10258         -1,
  10259     },
  10260 #endif /* chips */
  10261 
  10262 #if defined(BCM_88270_A0)
  10263     { /* SOC_REG_INT_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88270_A0r */
  10264         soc_block_list[22],
  10265         soc_genreg,
  10266         1,
  10267         0,
  10268         0xc4,
  10269         0,
  10270         0,
  10271         4,
  10272         soc_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88270_A0r_fields,
  10273         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10274         SOC_RESET_MASK_DEC(0x0000006f, 0x00000000)
  10275         -1,
  10276         -1,
  10277     },
  10278 #endif /* chips */
  10279 
  10280 #if defined(BCM_88375_A0)
  10281     { /* SOC_REG_INT_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88375_A0r */
  10282         soc_block_list[22],
  10283         soc_genreg,
  10284         1,
  10285         0,
  10286         0xc5,
  10287         0,
  10288         0,
  10289         4,
  10290         soc_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88375_A0r_fields,
  10291         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10292         SOC_RESET_MASK_DEC(0x0000006f, 0x00000000)
  10293         -1,
  10294         -1,
  10295     },
  10296 #endif /* chips */
  10297 
  10298 #if defined(BCM_88375_B0)
  10299     { /* SOC_REG_INT_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88375_B0r */
  10300         soc_block_list[22],
  10301         soc_genreg,
  10302         1,
  10303         0,
  10304         0xc5,
  10305         0,
  10306         0,
  10307         4,
  10308         soc_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88375_B0r_fields,
  10309         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10310         SOC_RESET_MASK_DEC(0x0000006f, 0x00000000)
  10311         -1,
  10312         -1,
  10313     },
  10314 #endif /* chips */
  10315 
  10316 #if defined(BCM_88470_A0)
  10317     { /* SOC_REG_INT_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88470_A0r */
  10318         soc_block_list[22],
  10319         soc_genreg,
  10320         1,
  10321         0,
  10322         0xc4,
  10323         0,
  10324         0,
  10325         4,
  10326         soc_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88470_A0r_fields,
  10327         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10328         SOC_RESET_MASK_DEC(0x0000006f, 0x00000000)
  10329         -1,
  10330         -1,
  10331     },
  10332 #endif /* chips */
  10333 
  10334 #if defined(BCM_88470_B0)
  10335     { /* SOC_REG_INT_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88470_B0r */
  10336         soc_block_list[22],
  10337         soc_genreg,
  10338         1,
  10339         0,
  10340         0xc4,
  10341         0,
  10342         0,
  10343         4,
  10344         soc_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88470_B0r_fields,
  10345         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10346         SOC_RESET_MASK_DEC(0x0000006f, 0x00000000)
  10347         -1,
  10348         -1,
  10349     },
  10350 #endif /* chips */
  10351 
  10352 #if defined(BCM_88675_B0)
  10353     { /* SOC_REG_INT_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88675_B0r */
  10354         soc_block_list[22],
  10355         soc_genreg,
  10356         1,
  10357         0,
  10358         0xc5,
  10359         0,
  10360         0,
  10361         4,
  10362         soc_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88675_B0r_fields,
  10363         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10364         SOC_RESET_MASK_DEC(0x0000006f, 0x00000000)
  10365         -1,
  10366         -1,
  10367     },
  10368 #endif /* chips */
  10369 
  10370 #if defined(BCM_88680_A0)
  10371     { /* SOC_REG_INT_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88680_A0r */
  10372         soc_block_list[22],
  10373         soc_genreg,
  10374         1,
  10375         0,
  10376         0xc5,
  10377         0,
  10378         0,
  10379         4,
  10380         soc_OAMP_GLOBAL_SYS_HEADER_CFG_BCM88680_A0r_fields,
  10381         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10382         SOC_RESET_MASK_DEC(0x0000006f, 0x00000000)
  10383         -1,
  10384         -1,
  10385     },
  10386 #endif /* chips */
  10387 
  10388 #if defined(BCM_88650_A0)
  10389     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATIONr */
  10390         soc_block_list[22],
  10391         soc_genreg,
  10392         1,
  10393         0,
  10394         0xd0,
  10395         0,
  10396         0,
  10397         3,
  10398         soc_OAMP_GTIMER_CONFIGURATIONr_fields,
  10399         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  10400         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10401         -1,
  10402         -1,
  10403     },
  10404 #endif /* chips */
  10405 
  10406 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10407     defined(BCM_56270_A0)
  10408     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM56260_A0r */
  10409         soc_block_list[22],
  10410         soc_genreg,
  10411         1,
  10412         0,
  10413         0x2008800,
  10414         0,
  10415         0,
  10416         3,
  10417         soc_OAMP_GTIMER_CONFIGURATION_BCM56260_A0r_fields,
  10418         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  10419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10420         -1,
  10421         -1,
  10422     },
  10423 #endif /* chips */
  10424 
  10425 #if defined(BCM_88270_A0)
  10426     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88270_A0r */
  10427         soc_block_list[22],
  10428         soc_genreg,
  10429         1,
  10430         0,
  10431         0x88,
  10432         SOC_REG_FLAG_64_BITS,
  10433         0,
  10434         4,
  10435         soc_OAMP_GTIMER_CONFIGURATION_BCM88270_A0r_fields,
  10436         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  10437         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  10438         -1,
  10439         -1,
  10440     },
  10441 #endif /* chips */
  10442 
  10443 #if defined(BCM_88375_A0)
  10444     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88375_A0r */
  10445         soc_block_list[22],
  10446         soc_genreg,
  10447         1,
  10448         0,
  10449         0x88,
  10450         0,
  10451         0,
  10452         3,
  10453         soc_OAMP_GTIMER_CONFIGURATION_BCM88375_A0r_fields,
  10454         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  10455         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10456         -1,
  10457         -1,
  10458     },
  10459 #endif /* chips */
  10460 
  10461 #if defined(BCM_88375_B0)
  10462     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88375_B0r */
  10463         soc_block_list[22],
  10464         soc_genreg,
  10465         1,
  10466         0,
  10467         0x88,
  10468         0,
  10469         0,
  10470         3,
  10471         soc_OAMP_GTIMER_CONFIGURATION_BCM88375_B0r_fields,
  10472         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  10473         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10474         -1,
  10475         -1,
  10476     },
  10477 #endif /* chips */
  10478 
  10479 #if defined(BCM_88470_A0)
  10480     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88470_A0r */
  10481         soc_block_list[22],
  10482         soc_genreg,
  10483         1,
  10484         0,
  10485         0x88,
  10486         SOC_REG_FLAG_64_BITS,
  10487         0,
  10488         4,
  10489         soc_OAMP_GTIMER_CONFIGURATION_BCM88470_A0r_fields,
  10490         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  10491         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  10492         -1,
  10493         -1,
  10494     },
  10495 #endif /* chips */
  10496 
  10497 #if defined(BCM_88470_B0)
  10498     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88470_B0r */
  10499         soc_block_list[22],
  10500         soc_genreg,
  10501         1,
  10502         0,
  10503         0x88,
  10504         SOC_REG_FLAG_64_BITS,
  10505         0,
  10506         4,
  10507         soc_OAMP_GTIMER_CONFIGURATION_BCM88470_B0r_fields,
  10508         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  10509         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  10510         -1,
  10511         -1,
  10512     },
  10513 #endif /* chips */
  10514 
  10515 #if defined(BCM_88650_B0)
  10516     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88650_B0r */
  10517         soc_block_list[22],
  10518         soc_genreg,
  10519         1,
  10520         0,
  10521         0xd0,
  10522         0,
  10523         0,
  10524         3,
  10525         soc_OAMP_GTIMER_CONFIGURATION_BCM88650_B0r_fields,
  10526         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  10527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10528         -1,
  10529         -1,
  10530     },
  10531 #endif /* chips */
  10532 
  10533 #if defined(BCM_88660_A0)
  10534     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88660_A0r */
  10535         soc_block_list[22],
  10536         soc_genreg,
  10537         1,
  10538         0,
  10539         0xd0,
  10540         0,
  10541         0,
  10542         3,
  10543         soc_OAMP_GTIMER_CONFIGURATION_BCM88660_A0r_fields,
  10544         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  10545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10546         -1,
  10547         -1,
  10548     },
  10549 #endif /* chips */
  10550 
  10551 #if defined(BCM_88675_A0)
  10552     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88675_A0r */
  10553         soc_block_list[22],
  10554         soc_genreg,
  10555         1,
  10556         0,
  10557         0x88,
  10558         SOC_REG_FLAG_IGNORE_DEFAULT,
  10559         0,
  10560         3,
  10561         soc_OAMP_GTIMER_CONFIGURATION_BCM88675_A0r_fields,
  10562         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  10563         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10564         -1,
  10565         -1,
  10566     },
  10567 #endif /* chips */
  10568 
  10569 #if defined(BCM_88675_B0)
  10570     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88675_B0r */
  10571         soc_block_list[22],
  10572         soc_genreg,
  10573         1,
  10574         0,
  10575         0x88,
  10576         SOC_REG_FLAG_IGNORE_DEFAULT,
  10577         0,
  10578         3,
  10579         soc_OAMP_GTIMER_CONFIGURATION_BCM88675_B0r_fields,
  10580         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  10581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10582         -1,
  10583         -1,
  10584     },
  10585 #endif /* chips */
  10586 
  10587 #if defined(BCM_88680_A0)
  10588     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88680_A0r */
  10589         soc_block_list[22],
  10590         soc_genreg,
  10591         1,
  10592         0,
  10593         0x88,
  10594         0,
  10595         0,
  10596         3,
  10597         soc_OAMP_GTIMER_CONFIGURATION_BCM88680_A0r_fields,
  10598         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  10599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10600         -1,
  10601         -1,
  10602     },
  10603 #endif /* chips */
  10604 
  10605 #if defined(BCM_88690_A0)
  10606     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88690_A0r */
  10607         soc_block_list[22],
  10608         soc_genreg,
  10609         1,
  10610         0,
  10611         0x89,
  10612         0,
  10613         0,
  10614         3,
  10615         soc_OAMP_GTIMER_CONFIGURATION_BCM88690_A0r_fields,
  10616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10617         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  10618         -1,
  10619         -1,
  10620     },
  10621 #endif /* chips */
  10622 
  10623 #if defined(BCM_88690_B0)
  10624     { /* SOC_REG_INT_OAMP_GTIMER_CONFIGURATION_BCM88690_B0r */
  10625         soc_block_list[22],
  10626         soc_genreg,
  10627         1,
  10628         0,
  10629         0x89,
  10630         0,
  10631         0,
  10632         3,
  10633         soc_OAMP_GTIMER_CONFIGURATION_BCM88690_B0r_fields,
  10634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10635         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  10636         -1,
  10637         -1,
  10638     },
  10639 #endif /* chips */
  10640 
  10641 #if defined(BCM_88690_A0)
  10642     { /* SOC_REG_INT_OAMP_GTIMER_CYCLEr */
  10643         soc_block_list[22],
  10644         soc_genreg,
  10645         1,
  10646         0,
  10647         0x88,
  10648         0,
  10649         0,
  10650         1,
  10651         soc_OAMP_GTIMER_CYCLEr_fields,
  10652         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  10653         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10654         -1,
  10655         -1,
  10656     },
  10657 #endif /* chips */
  10658 
  10659 #if defined(BCM_88690_B0)
  10660     { /* SOC_REG_INT_OAMP_GTIMER_CYCLE_BCM88690_B0r */
  10661         soc_block_list[22],
  10662         soc_genreg,
  10663         1,
  10664         0,
  10665         0x88,
  10666         0,
  10667         0,
  10668         1,
  10669         soc_OAMP_GTIMER_CYCLE_BCM88690_B0r_fields,
  10670         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  10671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10672         -1,
  10673         -1,
  10674     },
  10675 #endif /* chips */
  10676 
  10677 #if defined(BCM_88650_A0)
  10678     { /* SOC_REG_INT_OAMP_GTIMER_TRIGGERr */
  10679         soc_block_list[22],
  10680         soc_genreg,
  10681         1,
  10682         0,
  10683         0xd1,
  10684         SOC_REG_FLAG_SIGNAL,
  10685         0,
  10686         1,
  10687         soc_OAMP_GTIMER_TRIGGERr_fields,
  10688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10689         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10690         -1,
  10691         -1,
  10692     },
  10693 #endif /* chips */
  10694 
  10695 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10696     defined(BCM_56270_A0)
  10697     { /* SOC_REG_INT_OAMP_GTIMER_TRIGGER_BCM56260_A0r */
  10698         soc_block_list[22],
  10699         soc_genreg,
  10700         1,
  10701         0,
  10702         0x2008900,
  10703         SOC_REG_FLAG_RO,
  10704         0,
  10705         1,
  10706         soc_BRDC_CCS_GTIMER_TRIGGERr_fields,
  10707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10708         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10709         -1,
  10710         -1,
  10711     },
  10712 #endif /* chips */
  10713 
  10714 #if defined(BCM_88375_A0)
  10715     { /* SOC_REG_INT_OAMP_GTIMER_TRIGGER_BCM88375_A0r */
  10716         soc_block_list[22],
  10717         soc_genreg,
  10718         1,
  10719         0,
  10720         0x89,
  10721         SOC_REG_FLAG_RO,
  10722         0,
  10723         1,
  10724         soc_OAMP_GTIMER_TRIGGER_BCM88375_A0r_fields,
  10725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10726         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10727         -1,
  10728         -1,
  10729     },
  10730 #endif /* chips */
  10731 
  10732 #if defined(BCM_88375_B0)
  10733     { /* SOC_REG_INT_OAMP_GTIMER_TRIGGER_BCM88375_B0r */
  10734         soc_block_list[22],
  10735         soc_genreg,
  10736         1,
  10737         0,
  10738         0x89,
  10739         SOC_REG_FLAG_RO,
  10740         0,
  10741         1,
  10742         soc_OAMP_GTIMER_TRIGGER_BCM88375_B0r_fields,
  10743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10744         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10745         -1,
  10746         -1,
  10747     },
  10748 #endif /* chips */
  10749 
  10750 #if defined(BCM_88650_B0)
  10751     { /* SOC_REG_INT_OAMP_GTIMER_TRIGGER_BCM88650_B0r */
  10752         soc_block_list[22],
  10753         soc_genreg,
  10754         1,
  10755         0,
  10756         0xd1,
  10757         SOC_REG_FLAG_SIGNAL,
  10758         0,
  10759         1,
  10760         soc_OAMP_GTIMER_TRIGGER_BCM88650_B0r_fields,
  10761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10762         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10763         -1,
  10764         -1,
  10765     },
  10766 #endif /* chips */
  10767 
  10768 #if defined(BCM_88660_A0)
  10769     { /* SOC_REG_INT_OAMP_GTIMER_TRIGGER_BCM88660_A0r */
  10770         soc_block_list[22],
  10771         soc_genreg,
  10772         1,
  10773         0,
  10774         0xd1,
  10775         SOC_REG_FLAG_SIGNAL,
  10776         0,
  10777         1,
  10778         soc_OAMP_GTIMER_TRIGGER_BCM88660_A0r_fields,
  10779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10780         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10781         -1,
  10782         -1,
  10783     },
  10784 #endif /* chips */
  10785 
  10786 #if defined(BCM_88675_A0)
  10787     { /* SOC_REG_INT_OAMP_GTIMER_TRIGGER_BCM88675_A0r */
  10788         soc_block_list[22],
  10789         soc_genreg,
  10790         1,
  10791         0,
  10792         0x89,
  10793         SOC_REG_FLAG_RO,
  10794         0,
  10795         1,
  10796         soc_OAMP_GTIMER_TRIGGER_BCM88675_A0r_fields,
  10797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10798         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10799         -1,
  10800         -1,
  10801     },
  10802 #endif /* chips */
  10803 
  10804 #if defined(BCM_88675_B0)
  10805     { /* SOC_REG_INT_OAMP_GTIMER_TRIGGER_BCM88675_B0r */
  10806         soc_block_list[22],
  10807         soc_genreg,
  10808         1,
  10809         0,
  10810         0x89,
  10811         SOC_REG_FLAG_RO,
  10812         0,
  10813         1,
  10814         soc_OAMP_GTIMER_TRIGGER_BCM88675_B0r_fields,
  10815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10816         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10817         -1,
  10818         -1,
  10819     },
  10820 #endif /* chips */
  10821 
  10822 #if defined(BCM_88680_A0)
  10823     { /* SOC_REG_INT_OAMP_GTIMER_TRIGGER_BCM88680_A0r */
  10824         soc_block_list[22],
  10825         soc_genreg,
  10826         1,
  10827         0,
  10828         0x89,
  10829         SOC_REG_FLAG_RO,
  10830         0,
  10831         1,
  10832         soc_OAMP_GTIMER_TRIGGER_BCM88680_A0r_fields,
  10833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10834         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10835         -1,
  10836         -1,
  10837     },
  10838 #endif /* chips */
  10839 
  10840 #if defined(BCM_88690_A0)
  10841     { /* SOC_REG_INT_OAMP_HEADER_CONFIGr */
  10842         soc_block_list[22],
  10843         soc_genreg,
  10844         1,
  10845         0,
  10846         0x123,
  10847         SOC_REG_FLAG_ABOVE_64_BITS,
  10848         0,
  10849         10,
  10850         soc_OAMP_HEADER_CONFIGr_fields,
  10851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10852         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10853         -1,
  10854         -1,
  10855     },
  10856 #endif /* chips */
  10857 
  10858 #if defined(BCM_88690_B0)
  10859     { /* SOC_REG_INT_OAMP_HEADER_CONFIG_BCM88690_B0r */
  10860         soc_block_list[22],
  10861         soc_genreg,
  10862         1,
  10863         0,
  10864         0x123,
  10865         SOC_REG_FLAG_ABOVE_64_BITS,
  10866         0,
  10867         10,
  10868         soc_OAMP_HEADER_CONFIG_BCM88690_B0r_fields,
  10869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10870         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10871         -1,
  10872         -1,
  10873     },
  10874 #endif /* chips */
  10875 
  10876 #if defined(BCM_88650_A0)
  10877     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1r */
  10878         soc_block_list[22],
  10879         soc_genreg,
  10880         1,
  10881         0,
  10882         0x144,
  10883         SOC_REG_FLAG_ABOVE_64_BITS |
  10884                           SOC_REG_FLAG_SIGNAL,
  10885         0,
  10886         10,
  10887         soc_OAMP_ICC_MAP_REG_1r_fields,
  10888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10889         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10890         -1,
  10891         -1,
  10892     },
  10893 #endif /* chips */
  10894 
  10895 #if defined(BCM_88650_A0)
  10896     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2r */
  10897         soc_block_list[22],
  10898         soc_genreg,
  10899         1,
  10900         0,
  10901         0x153,
  10902         SOC_REG_FLAG_ABOVE_64_BITS |
  10903                           SOC_REG_FLAG_SIGNAL,
  10904         0,
  10905         5,
  10906         soc_OAMP_ICC_MAP_REG_2r_fields,
  10907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10908         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10909         -1,
  10910         -1,
  10911     },
  10912 #endif /* chips */
  10913 
  10914 #if defined(BCM_88270_A0)
  10915     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88270_A0r */
  10916         soc_block_list[22],
  10917         soc_genreg,
  10918         1,
  10919         0,
  10920         0x16d,
  10921         SOC_REG_FLAG_ABOVE_64_BITS,
  10922         0,
  10923         10,
  10924         soc_OAMP_ICC_MAP_REG_1_BCM88270_A0r_fields,
  10925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10926         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10927         -1,
  10928         -1,
  10929     },
  10930 #endif /* chips */
  10931 
  10932 #if defined(BCM_88375_A0)
  10933     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88375_A0r */
  10934         soc_block_list[22],
  10935         soc_genreg,
  10936         1,
  10937         0,
  10938         0x16b,
  10939         SOC_REG_FLAG_ABOVE_64_BITS,
  10940         0,
  10941         10,
  10942         soc_OAMP_ICC_MAP_REG_1_BCM88375_A0r_fields,
  10943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10944         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10945         -1,
  10946         -1,
  10947     },
  10948 #endif /* chips */
  10949 
  10950 #if defined(BCM_88375_B0)
  10951     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88375_B0r */
  10952         soc_block_list[22],
  10953         soc_genreg,
  10954         1,
  10955         0,
  10956         0x16b,
  10957         SOC_REG_FLAG_ABOVE_64_BITS,
  10958         0,
  10959         10,
  10960         soc_OAMP_ICC_MAP_REG_1_BCM88375_B0r_fields,
  10961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10962         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10963         -1,
  10964         -1,
  10965     },
  10966 #endif /* chips */
  10967 
  10968 #if defined(BCM_88470_A0)
  10969     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88470_A0r */
  10970         soc_block_list[22],
  10971         soc_genreg,
  10972         1,
  10973         0,
  10974         0x16d,
  10975         SOC_REG_FLAG_ABOVE_64_BITS,
  10976         0,
  10977         10,
  10978         soc_OAMP_ICC_MAP_REG_1_BCM88470_A0r_fields,
  10979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10980         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10981         -1,
  10982         -1,
  10983     },
  10984 #endif /* chips */
  10985 
  10986 #if defined(BCM_88470_B0)
  10987     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88470_B0r */
  10988         soc_block_list[22],
  10989         soc_genreg,
  10990         1,
  10991         0,
  10992         0x16d,
  10993         SOC_REG_FLAG_ABOVE_64_BITS,
  10994         0,
  10995         10,
  10996         soc_OAMP_ICC_MAP_REG_1_BCM88470_B0r_fields,
  10997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10998         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10999         -1,
  11000         -1,
  11001     },
  11002 #endif /* chips */
  11003 
  11004 #if defined(BCM_88650_B0)
  11005     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88650_B0r */
  11006         soc_block_list[22],
  11007         soc_genreg,
  11008         1,
  11009         0,
  11010         0x144,
  11011         SOC_REG_FLAG_ABOVE_64_BITS |
  11012                           SOC_REG_FLAG_SIGNAL,
  11013         0,
  11014         10,
  11015         soc_OAMP_ICC_MAP_REG_1_BCM88650_B0r_fields,
  11016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11017         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11018         -1,
  11019         -1,
  11020     },
  11021 #endif /* chips */
  11022 
  11023 #if defined(BCM_88660_A0)
  11024     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88660_A0r */
  11025         soc_block_list[22],
  11026         soc_genreg,
  11027         1,
  11028         0,
  11029         0x157,
  11030         SOC_REG_FLAG_ABOVE_64_BITS |
  11031                           SOC_REG_FLAG_SIGNAL,
  11032         0,
  11033         10,
  11034         soc_OAMP_ICC_MAP_REG_1_BCM88660_A0r_fields,
  11035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11036         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11037         -1,
  11038         -1,
  11039     },
  11040 #endif /* chips */
  11041 
  11042 #if defined(BCM_88675_A0)
  11043     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88675_A0r */
  11044         soc_block_list[22],
  11045         soc_genreg,
  11046         1,
  11047         0,
  11048         0x16b,
  11049         SOC_REG_FLAG_ABOVE_64_BITS,
  11050         0,
  11051         10,
  11052         soc_OAMP_ICC_MAP_REG_1_BCM88675_A0r_fields,
  11053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11054         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11055         -1,
  11056         -1,
  11057     },
  11058 #endif /* chips */
  11059 
  11060 #if defined(BCM_88675_B0)
  11061     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88675_B0r */
  11062         soc_block_list[22],
  11063         soc_genreg,
  11064         1,
  11065         0,
  11066         0x16b,
  11067         SOC_REG_FLAG_ABOVE_64_BITS,
  11068         0,
  11069         10,
  11070         soc_OAMP_ICC_MAP_REG_1_BCM88675_B0r_fields,
  11071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11072         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11073         -1,
  11074         -1,
  11075     },
  11076 #endif /* chips */
  11077 
  11078 #if defined(BCM_88680_A0)
  11079     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88680_A0r */
  11080         soc_block_list[22],
  11081         soc_genreg,
  11082         1,
  11083         0,
  11084         0x16b,
  11085         SOC_REG_FLAG_ABOVE_64_BITS,
  11086         0,
  11087         10,
  11088         soc_OAMP_ICC_MAP_REG_1_BCM88680_A0r_fields,
  11089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11091         -1,
  11092         -1,
  11093     },
  11094 #endif /* chips */
  11095 
  11096 #if defined(BCM_88690_A0)
  11097     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88690_A0r */
  11098         soc_block_list[22],
  11099         soc_genreg,
  11100         1,
  11101         0,
  11102         0x16a,
  11103         SOC_REG_FLAG_ABOVE_64_BITS,
  11104         0,
  11105         10,
  11106         soc_OAMP_ICC_MAP_REG_1_BCM88690_A0r_fields,
  11107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11109         -1,
  11110         -1,
  11111     },
  11112 #endif /* chips */
  11113 
  11114 #if defined(BCM_88690_B0)
  11115     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_1_BCM88690_B0r */
  11116         soc_block_list[22],
  11117         soc_genreg,
  11118         1,
  11119         0,
  11120         0x16a,
  11121         SOC_REG_FLAG_ABOVE_64_BITS,
  11122         0,
  11123         10,
  11124         soc_OAMP_ICC_MAP_REG_1_BCM88690_B0r_fields,
  11125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11126         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11127         -1,
  11128         -1,
  11129     },
  11130 #endif /* chips */
  11131 
  11132 #if defined(BCM_88270_A0)
  11133     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88270_A0r */
  11134         soc_block_list[22],
  11135         soc_genreg,
  11136         1,
  11137         0,
  11138         0x17c,
  11139         SOC_REG_FLAG_ABOVE_64_BITS,
  11140         0,
  11141         5,
  11142         soc_OAMP_ICC_MAP_REG_2_BCM88270_A0r_fields,
  11143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11144         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11145         -1,
  11146         -1,
  11147     },
  11148 #endif /* chips */
  11149 
  11150 #if defined(BCM_88375_A0)
  11151     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88375_A0r */
  11152         soc_block_list[22],
  11153         soc_genreg,
  11154         1,
  11155         0,
  11156         0x17a,
  11157         SOC_REG_FLAG_ABOVE_64_BITS,
  11158         0,
  11159         5,
  11160         soc_OAMP_ICC_MAP_REG_2_BCM88375_A0r_fields,
  11161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11163         -1,
  11164         -1,
  11165     },
  11166 #endif /* chips */
  11167 
  11168 #if defined(BCM_88375_B0)
  11169     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88375_B0r */
  11170         soc_block_list[22],
  11171         soc_genreg,
  11172         1,
  11173         0,
  11174         0x17a,
  11175         SOC_REG_FLAG_ABOVE_64_BITS,
  11176         0,
  11177         5,
  11178         soc_OAMP_ICC_MAP_REG_2_BCM88375_B0r_fields,
  11179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11180         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11181         -1,
  11182         -1,
  11183     },
  11184 #endif /* chips */
  11185 
  11186 #if defined(BCM_88470_A0)
  11187     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88470_A0r */
  11188         soc_block_list[22],
  11189         soc_genreg,
  11190         1,
  11191         0,
  11192         0x17c,
  11193         SOC_REG_FLAG_ABOVE_64_BITS,
  11194         0,
  11195         5,
  11196         soc_OAMP_ICC_MAP_REG_2_BCM88470_A0r_fields,
  11197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11198         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11199         -1,
  11200         -1,
  11201     },
  11202 #endif /* chips */
  11203 
  11204 #if defined(BCM_88470_B0)
  11205     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88470_B0r */
  11206         soc_block_list[22],
  11207         soc_genreg,
  11208         1,
  11209         0,
  11210         0x17c,
  11211         SOC_REG_FLAG_ABOVE_64_BITS,
  11212         0,
  11213         5,
  11214         soc_OAMP_ICC_MAP_REG_2_BCM88470_B0r_fields,
  11215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11216         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11217         -1,
  11218         -1,
  11219     },
  11220 #endif /* chips */
  11221 
  11222 #if defined(BCM_88650_B0)
  11223     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88650_B0r */
  11224         soc_block_list[22],
  11225         soc_genreg,
  11226         1,
  11227         0,
  11228         0x153,
  11229         SOC_REG_FLAG_ABOVE_64_BITS |
  11230                           SOC_REG_FLAG_SIGNAL,
  11231         0,
  11232         5,
  11233         soc_OAMP_ICC_MAP_REG_2_BCM88650_B0r_fields,
  11234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11235         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11236         -1,
  11237         -1,
  11238     },
  11239 #endif /* chips */
  11240 
  11241 #if defined(BCM_88660_A0)
  11242     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88660_A0r */
  11243         soc_block_list[22],
  11244         soc_genreg,
  11245         1,
  11246         0,
  11247         0x166,
  11248         SOC_REG_FLAG_ABOVE_64_BITS |
  11249                           SOC_REG_FLAG_SIGNAL,
  11250         0,
  11251         5,
  11252         soc_OAMP_ICC_MAP_REG_2_BCM88660_A0r_fields,
  11253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11254         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11255         -1,
  11256         -1,
  11257     },
  11258 #endif /* chips */
  11259 
  11260 #if defined(BCM_88675_A0)
  11261     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88675_A0r */
  11262         soc_block_list[22],
  11263         soc_genreg,
  11264         1,
  11265         0,
  11266         0x17a,
  11267         SOC_REG_FLAG_ABOVE_64_BITS,
  11268         0,
  11269         5,
  11270         soc_OAMP_ICC_MAP_REG_2_BCM88675_A0r_fields,
  11271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11272         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11273         -1,
  11274         -1,
  11275     },
  11276 #endif /* chips */
  11277 
  11278 #if defined(BCM_88675_B0)
  11279     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88675_B0r */
  11280         soc_block_list[22],
  11281         soc_genreg,
  11282         1,
  11283         0,
  11284         0x17a,
  11285         SOC_REG_FLAG_ABOVE_64_BITS,
  11286         0,
  11287         5,
  11288         soc_OAMP_ICC_MAP_REG_2_BCM88675_B0r_fields,
  11289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11290         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11291         -1,
  11292         -1,
  11293     },
  11294 #endif /* chips */
  11295 
  11296 #if defined(BCM_88680_A0)
  11297     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88680_A0r */
  11298         soc_block_list[22],
  11299         soc_genreg,
  11300         1,
  11301         0,
  11302         0x17a,
  11303         SOC_REG_FLAG_ABOVE_64_BITS,
  11304         0,
  11305         5,
  11306         soc_OAMP_ICC_MAP_REG_2_BCM88680_A0r_fields,
  11307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11308         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11309         -1,
  11310         -1,
  11311     },
  11312 #endif /* chips */
  11313 
  11314 #if defined(BCM_88690_A0)
  11315     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88690_A0r */
  11316         soc_block_list[22],
  11317         soc_genreg,
  11318         1,
  11319         0,
  11320         0x179,
  11321         SOC_REG_FLAG_ABOVE_64_BITS,
  11322         0,
  11323         5,
  11324         soc_OAMP_ICC_MAP_REG_2_BCM88690_A0r_fields,
  11325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11326         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11327         -1,
  11328         -1,
  11329     },
  11330 #endif /* chips */
  11331 
  11332 #if defined(BCM_88690_B0)
  11333     { /* SOC_REG_INT_OAMP_ICC_MAP_REG_2_BCM88690_B0r */
  11334         soc_block_list[22],
  11335         soc_genreg,
  11336         1,
  11337         0,
  11338         0x179,
  11339         SOC_REG_FLAG_ABOVE_64_BITS,
  11340         0,
  11341         5,
  11342         soc_OAMP_ICC_MAP_REG_2_BCM88690_B0r_fields,
  11343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11345         -1,
  11346         -1,
  11347     },
  11348 #endif /* chips */
  11349 
  11350 #if defined(BCM_88650_A0)
  11351     { /* SOC_REG_INT_OAMP_INDIRECT_COMMANDr */
  11352         soc_block_list[22],
  11353         soc_genreg,
  11354         1,
  11355         0,
  11356         0x80,
  11357         0,
  11358         0,
  11359         5,
  11360         soc_OAMP_INDIRECT_COMMANDr_fields,
  11361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11362         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11363         -1,
  11364         -1,
  11365     },
  11366 #endif /* chips */
  11367 
  11368 #if defined(BCM_88650_A0)
  11369     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESSr */
  11370         soc_block_list[22],
  11371         soc_genreg,
  11372         1,
  11373         0,
  11374         0x81,
  11375         0,
  11376         0,
  11377         2,
  11378         soc_OAMP_INDIRECT_COMMAND_ADDRESSr_fields,
  11379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11380         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11381         -1,
  11382         -1,
  11383     },
  11384 #endif /* chips */
  11385 
  11386 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  11387     defined(BCM_56270_A0)
  11388     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM56260_A0r */
  11389         soc_block_list[22],
  11390         soc_genreg,
  11391         1,
  11392         0,
  11393         0x2008100,
  11394         0,
  11395         0,
  11396         2,
  11397         soc_DCL_INDIRECT_COMMAND_ADDRESSr_fields,
  11398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11400         -1,
  11401         -1,
  11402     },
  11403 #endif /* chips */
  11404 
  11405 #if defined(BCM_88270_A0)
  11406     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88270_A0r */
  11407         soc_block_list[22],
  11408         soc_genreg,
  11409         1,
  11410         0,
  11411         0x81,
  11412         0,
  11413         0,
  11414         2,
  11415         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88270_A0r_fields,
  11416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11418         -1,
  11419         -1,
  11420     },
  11421 #endif /* chips */
  11422 
  11423 #if defined(BCM_88375_A0)
  11424     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88375_A0r */
  11425         soc_block_list[22],
  11426         soc_genreg,
  11427         1,
  11428         0,
  11429         0x81,
  11430         0,
  11431         0,
  11432         2,
  11433         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88375_A0r_fields,
  11434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11436         -1,
  11437         -1,
  11438     },
  11439 #endif /* chips */
  11440 
  11441 #if defined(BCM_88375_B0)
  11442     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88375_B0r */
  11443         soc_block_list[22],
  11444         soc_genreg,
  11445         1,
  11446         0,
  11447         0x81,
  11448         0,
  11449         0,
  11450         2,
  11451         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88375_B0r_fields,
  11452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11454         -1,
  11455         -1,
  11456     },
  11457 #endif /* chips */
  11458 
  11459 #if defined(BCM_88470_A0)
  11460     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88470_A0r */
  11461         soc_block_list[22],
  11462         soc_genreg,
  11463         1,
  11464         0,
  11465         0x81,
  11466         0,
  11467         0,
  11468         2,
  11469         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88470_A0r_fields,
  11470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11471         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11472         -1,
  11473         -1,
  11474     },
  11475 #endif /* chips */
  11476 
  11477 #if defined(BCM_88470_B0)
  11478     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88470_B0r */
  11479         soc_block_list[22],
  11480         soc_genreg,
  11481         1,
  11482         0,
  11483         0x81,
  11484         0,
  11485         0,
  11486         2,
  11487         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88470_B0r_fields,
  11488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11490         -1,
  11491         -1,
  11492     },
  11493 #endif /* chips */
  11494 
  11495 #if defined(BCM_88650_B0)
  11496     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88650_B0r */
  11497         soc_block_list[22],
  11498         soc_genreg,
  11499         1,
  11500         0,
  11501         0x81,
  11502         0,
  11503         0,
  11504         2,
  11505         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88650_B0r_fields,
  11506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11508         -1,
  11509         -1,
  11510     },
  11511 #endif /* chips */
  11512 
  11513 #if defined(BCM_88660_A0)
  11514     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88660_A0r */
  11515         soc_block_list[22],
  11516         soc_genreg,
  11517         1,
  11518         0,
  11519         0x81,
  11520         0,
  11521         0,
  11522         2,
  11523         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88660_A0r_fields,
  11524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11526         -1,
  11527         -1,
  11528     },
  11529 #endif /* chips */
  11530 
  11531 #if defined(BCM_88675_A0)
  11532     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88675_A0r */
  11533         soc_block_list[22],
  11534         soc_genreg,
  11535         1,
  11536         0,
  11537         0x81,
  11538         0,
  11539         0,
  11540         2,
  11541         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88675_A0r_fields,
  11542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11544         -1,
  11545         -1,
  11546     },
  11547 #endif /* chips */
  11548 
  11549 #if defined(BCM_88675_B0)
  11550     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88675_B0r */
  11551         soc_block_list[22],
  11552         soc_genreg,
  11553         1,
  11554         0,
  11555         0x81,
  11556         0,
  11557         0,
  11558         2,
  11559         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88675_B0r_fields,
  11560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11562         -1,
  11563         -1,
  11564     },
  11565 #endif /* chips */
  11566 
  11567 #if defined(BCM_88680_A0)
  11568     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r */
  11569         soc_block_list[22],
  11570         soc_genreg,
  11571         1,
  11572         0,
  11573         0x81,
  11574         0,
  11575         0,
  11576         2,
  11577         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r_fields,
  11578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11579         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11580         -1,
  11581         -1,
  11582     },
  11583 #endif /* chips */
  11584 
  11585 #if defined(BCM_88690_A0)
  11586     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r */
  11587         soc_block_list[22],
  11588         soc_genreg,
  11589         1,
  11590         0,
  11591         0x81,
  11592         0,
  11593         0,
  11594         2,
  11595         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r_fields,
  11596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11598         -1,
  11599         -1,
  11600     },
  11601 #endif /* chips */
  11602 
  11603 #if defined(BCM_88690_B0)
  11604     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r */
  11605         soc_block_list[22],
  11606         soc_genreg,
  11607         1,
  11608         0,
  11609         0x81,
  11610         0,
  11611         0,
  11612         2,
  11613         soc_OAMP_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r_fields,
  11614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11616         -1,
  11617         -1,
  11618     },
  11619 #endif /* chips */
  11620 
  11621 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  11622     defined(BCM_56270_A0)
  11623     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM56260_A0r */
  11624         soc_block_list[22],
  11625         soc_genreg,
  11626         1,
  11627         0,
  11628         0x2008000,
  11629         0,
  11630         0,
  11631         5,
  11632         soc_OAMP_INDIRECT_COMMAND_BCM56260_A0r_fields,
  11633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11634         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11635         -1,
  11636         -1,
  11637     },
  11638 #endif /* chips */
  11639 
  11640 #if defined(BCM_88270_A0)
  11641     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88270_A0r */
  11642         soc_block_list[22],
  11643         soc_genreg,
  11644         1,
  11645         0,
  11646         0x80,
  11647         0,
  11648         0,
  11649         5,
  11650         soc_OAMP_INDIRECT_COMMAND_BCM88270_A0r_fields,
  11651         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  11652         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11653         -1,
  11654         -1,
  11655     },
  11656 #endif /* chips */
  11657 
  11658 #if defined(BCM_88375_A0)
  11659     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88375_A0r */
  11660         soc_block_list[22],
  11661         soc_genreg,
  11662         1,
  11663         0,
  11664         0x80,
  11665         0,
  11666         0,
  11667         5,
  11668         soc_OAMP_INDIRECT_COMMAND_BCM88375_A0r_fields,
  11669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11670         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11671         -1,
  11672         -1,
  11673     },
  11674 #endif /* chips */
  11675 
  11676 #if defined(BCM_88375_B0)
  11677     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88375_B0r */
  11678         soc_block_list[22],
  11679         soc_genreg,
  11680         1,
  11681         0,
  11682         0x80,
  11683         0,
  11684         0,
  11685         5,
  11686         soc_OAMP_INDIRECT_COMMAND_BCM88375_B0r_fields,
  11687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11689         -1,
  11690         -1,
  11691     },
  11692 #endif /* chips */
  11693 
  11694 #if defined(BCM_88470_A0)
  11695     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88470_A0r */
  11696         soc_block_list[22],
  11697         soc_genreg,
  11698         1,
  11699         0,
  11700         0x80,
  11701         0,
  11702         0,
  11703         5,
  11704         soc_OAMP_INDIRECT_COMMAND_BCM88470_A0r_fields,
  11705         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  11706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11707         -1,
  11708         -1,
  11709     },
  11710 #endif /* chips */
  11711 
  11712 #if defined(BCM_88470_B0)
  11713     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88470_B0r */
  11714         soc_block_list[22],
  11715         soc_genreg,
  11716         1,
  11717         0,
  11718         0x80,
  11719         0,
  11720         0,
  11721         5,
  11722         soc_OAMP_INDIRECT_COMMAND_BCM88470_B0r_fields,
  11723         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  11724         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11725         -1,
  11726         -1,
  11727     },
  11728 #endif /* chips */
  11729 
  11730 #if defined(BCM_88650_B0)
  11731     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88650_B0r */
  11732         soc_block_list[22],
  11733         soc_genreg,
  11734         1,
  11735         0,
  11736         0x80,
  11737         0,
  11738         0,
  11739         5,
  11740         soc_OAMP_INDIRECT_COMMAND_BCM88650_B0r_fields,
  11741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11743         -1,
  11744         -1,
  11745     },
  11746 #endif /* chips */
  11747 
  11748 #if defined(BCM_88660_A0)
  11749     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88660_A0r */
  11750         soc_block_list[22],
  11751         soc_genreg,
  11752         1,
  11753         0,
  11754         0x80,
  11755         0,
  11756         0,
  11757         5,
  11758         soc_OAMP_INDIRECT_COMMAND_BCM88660_A0r_fields,
  11759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11760         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11761         -1,
  11762         -1,
  11763     },
  11764 #endif /* chips */
  11765 
  11766 #if defined(BCM_88675_A0)
  11767     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88675_A0r */
  11768         soc_block_list[22],
  11769         soc_genreg,
  11770         1,
  11771         0,
  11772         0x80,
  11773         SOC_REG_FLAG_IGNORE_DEFAULT,
  11774         0,
  11775         5,
  11776         soc_OAMP_INDIRECT_COMMAND_BCM88675_A0r_fields,
  11777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11778         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11779         -1,
  11780         -1,
  11781     },
  11782 #endif /* chips */
  11783 
  11784 #if defined(BCM_88675_B0)
  11785     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88675_B0r */
  11786         soc_block_list[22],
  11787         soc_genreg,
  11788         1,
  11789         0,
  11790         0x80,
  11791         SOC_REG_FLAG_IGNORE_DEFAULT,
  11792         0,
  11793         5,
  11794         soc_OAMP_INDIRECT_COMMAND_BCM88675_B0r_fields,
  11795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11797         -1,
  11798         -1,
  11799     },
  11800 #endif /* chips */
  11801 
  11802 #if defined(BCM_88680_A0)
  11803     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88680_A0r */
  11804         soc_block_list[22],
  11805         soc_genreg,
  11806         1,
  11807         0,
  11808         0x80,
  11809         0,
  11810         0,
  11811         5,
  11812         soc_OAMP_INDIRECT_COMMAND_BCM88680_A0r_fields,
  11813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11814         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11815         -1,
  11816         -1,
  11817     },
  11818 #endif /* chips */
  11819 
  11820 #if defined(BCM_88690_A0)
  11821     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88690_A0r */
  11822         soc_block_list[22],
  11823         soc_genreg,
  11824         1,
  11825         0,
  11826         0x80,
  11827         0,
  11828         0,
  11829         5,
  11830         soc_OAMP_INDIRECT_COMMAND_BCM88690_A0r_fields,
  11831         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
  11832         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11833         -1,
  11834         -1,
  11835     },
  11836 #endif /* chips */
  11837 
  11838 #if defined(BCM_88690_B0)
  11839     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_BCM88690_B0r */
  11840         soc_block_list[22],
  11841         soc_genreg,
  11842         1,
  11843         0,
  11844         0x80,
  11845         0,
  11846         0,
  11847         5,
  11848         soc_OAMP_INDIRECT_COMMAND_BCM88690_B0r_fields,
  11849         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
  11850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11851         -1,
  11852         -1,
  11853     },
  11854 #endif /* chips */
  11855 
  11856 #if defined(BCM_88650_A0)
  11857     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENTr */
  11858         soc_block_list[22],
  11859         soc_genreg,
  11860         1,
  11861         0,
  11862         0x82,
  11863         SOC_REG_FLAG_64_BITS |
  11864                           SOC_REG_FLAG_SIGNAL,
  11865         0,
  11866         1,
  11867         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
  11868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11869         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  11870         -1,
  11871         -1,
  11872     },
  11873 #endif /* chips */
  11874 
  11875 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  11876     defined(BCM_56270_A0)
  11877     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM56260_A0r */
  11878         soc_block_list[22],
  11879         soc_genreg,
  11880         1,
  11881         0,
  11882         0x2008200,
  11883         SOC_REG_FLAG_64_BITS,
  11884         0,
  11885         1,
  11886         soc_DCL_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
  11887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11888         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  11889         -1,
  11890         -1,
  11891     },
  11892 #endif /* chips */
  11893 
  11894 #if defined(BCM_88270_A0)
  11895     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88270_A0r */
  11896         soc_block_list[22],
  11897         soc_genreg,
  11898         1,
  11899         0,
  11900         0x82,
  11901         SOC_REG_FLAG_64_BITS,
  11902         0,
  11903         1,
  11904         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88270_A0r_fields,
  11905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11906         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  11907         -1,
  11908         -1,
  11909     },
  11910 #endif /* chips */
  11911 
  11912 #if defined(BCM_88375_A0)
  11913     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_A0r */
  11914         soc_block_list[22],
  11915         soc_genreg,
  11916         1,
  11917         0,
  11918         0x82,
  11919         SOC_REG_FLAG_64_BITS,
  11920         0,
  11921         1,
  11922         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_A0r_fields,
  11923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11924         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  11925         -1,
  11926         -1,
  11927     },
  11928 #endif /* chips */
  11929 
  11930 #if defined(BCM_88375_B0)
  11931     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_B0r */
  11932         soc_block_list[22],
  11933         soc_genreg,
  11934         1,
  11935         0,
  11936         0x82,
  11937         SOC_REG_FLAG_64_BITS,
  11938         0,
  11939         1,
  11940         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_B0r_fields,
  11941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11942         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  11943         -1,
  11944         -1,
  11945     },
  11946 #endif /* chips */
  11947 
  11948 #if defined(BCM_88470_A0)
  11949     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_A0r */
  11950         soc_block_list[22],
  11951         soc_genreg,
  11952         1,
  11953         0,
  11954         0x82,
  11955         SOC_REG_FLAG_64_BITS,
  11956         0,
  11957         1,
  11958         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_A0r_fields,
  11959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11960         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  11961         -1,
  11962         -1,
  11963     },
  11964 #endif /* chips */
  11965 
  11966 #if defined(BCM_88470_B0)
  11967     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_B0r */
  11968         soc_block_list[22],
  11969         soc_genreg,
  11970         1,
  11971         0,
  11972         0x82,
  11973         SOC_REG_FLAG_64_BITS,
  11974         0,
  11975         1,
  11976         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_B0r_fields,
  11977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11978         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  11979         -1,
  11980         -1,
  11981     },
  11982 #endif /* chips */
  11983 
  11984 #if defined(BCM_88650_B0)
  11985     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88650_B0r */
  11986         soc_block_list[22],
  11987         soc_genreg,
  11988         1,
  11989         0,
  11990         0x82,
  11991         SOC_REG_FLAG_64_BITS |
  11992                           SOC_REG_FLAG_SIGNAL,
  11993         0,
  11994         1,
  11995         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88650_B0r_fields,
  11996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11997         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  11998         -1,
  11999         -1,
  12000     },
  12001 #endif /* chips */
  12002 
  12003 #if defined(BCM_88660_A0)
  12004     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88660_A0r */
  12005         soc_block_list[22],
  12006         soc_genreg,
  12007         1,
  12008         0,
  12009         0x82,
  12010         SOC_REG_FLAG_64_BITS |
  12011                           SOC_REG_FLAG_SIGNAL,
  12012         0,
  12013         1,
  12014         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88660_A0r_fields,
  12015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12016         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  12017         -1,
  12018         -1,
  12019     },
  12020 #endif /* chips */
  12021 
  12022 #if defined(BCM_88675_A0)
  12023     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_A0r */
  12024         soc_block_list[22],
  12025         soc_genreg,
  12026         1,
  12027         0,
  12028         0x82,
  12029         SOC_REG_FLAG_64_BITS,
  12030         0,
  12031         1,
  12032         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_A0r_fields,
  12033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12034         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  12035         -1,
  12036         -1,
  12037     },
  12038 #endif /* chips */
  12039 
  12040 #if defined(BCM_88675_B0)
  12041     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_B0r */
  12042         soc_block_list[22],
  12043         soc_genreg,
  12044         1,
  12045         0,
  12046         0x82,
  12047         SOC_REG_FLAG_64_BITS,
  12048         0,
  12049         1,
  12050         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_B0r_fields,
  12051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12052         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  12053         -1,
  12054         -1,
  12055     },
  12056 #endif /* chips */
  12057 
  12058 #if defined(BCM_88680_A0)
  12059     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r */
  12060         soc_block_list[22],
  12061         soc_genreg,
  12062         1,
  12063         0,
  12064         0x82,
  12065         SOC_REG_FLAG_64_BITS,
  12066         0,
  12067         1,
  12068         soc_OAMP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r_fields,
  12069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12070         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  12071         -1,
  12072         -1,
  12073     },
  12074 #endif /* chips */
  12075 
  12076 #if defined(BCM_88650_A0)
  12077     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATAr */
  12078         soc_block_list[22],
  12079         soc_genreg,
  12080         1,
  12081         0,
  12082         0x60,
  12083         SOC_REG_FLAG_ABOVE_64_BITS |
  12084                           SOC_REG_FLAG_RO,
  12085         0,
  12086         1,
  12087         soc_OAMP_INDIRECT_COMMAND_RD_DATAr_fields,
  12088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12089         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12090         -1,
  12091         -1,
  12092     },
  12093 #endif /* chips */
  12094 
  12095 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12096     defined(BCM_56270_A0)
  12097     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM56260_A0r */
  12098         soc_block_list[22],
  12099         soc_genreg,
  12100         1,
  12101         0,
  12102         0x2006000,
  12103         SOC_REG_FLAG_ABOVE_64_BITS |
  12104                           SOC_REG_FLAG_RO,
  12105         0,
  12106         1,
  12107         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM56260_A0r_fields,
  12108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12110         -1,
  12111         -1,
  12112     },
  12113 #endif /* chips */
  12114 
  12115 #if defined(BCM_88270_A0)
  12116     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88270_A0r */
  12117         soc_block_list[22],
  12118         soc_genreg,
  12119         1,
  12120         0,
  12121         0x60,
  12122         SOC_REG_FLAG_ABOVE_64_BITS |
  12123                           SOC_REG_FLAG_RO |
  12124                           SOC_REG_FLAG_SIGNAL,
  12125         0,
  12126         1,
  12127         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88270_A0r_fields,
  12128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12129         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12130         -1,
  12131         -1,
  12132     },
  12133 #endif /* chips */
  12134 
  12135 #if defined(BCM_88375_A0)
  12136     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88375_A0r */
  12137         soc_block_list[22],
  12138         soc_genreg,
  12139         1,
  12140         0,
  12141         0x60,
  12142         SOC_REG_FLAG_ABOVE_64_BITS |
  12143                           SOC_REG_FLAG_RO |
  12144                           SOC_REG_FLAG_SIGNAL,
  12145         0,
  12146         1,
  12147         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88375_A0r_fields,
  12148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12150         -1,
  12151         -1,
  12152     },
  12153 #endif /* chips */
  12154 
  12155 #if defined(BCM_88375_B0)
  12156     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88375_B0r */
  12157         soc_block_list[22],
  12158         soc_genreg,
  12159         1,
  12160         0,
  12161         0x60,
  12162         SOC_REG_FLAG_ABOVE_64_BITS |
  12163                           SOC_REG_FLAG_RO |
  12164                           SOC_REG_FLAG_SIGNAL,
  12165         0,
  12166         1,
  12167         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88375_B0r_fields,
  12168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12169         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12170         -1,
  12171         -1,
  12172     },
  12173 #endif /* chips */
  12174 
  12175 #if defined(BCM_88470_A0)
  12176     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88470_A0r */
  12177         soc_block_list[22],
  12178         soc_genreg,
  12179         1,
  12180         0,
  12181         0x60,
  12182         SOC_REG_FLAG_ABOVE_64_BITS |
  12183                           SOC_REG_FLAG_RO |
  12184                           SOC_REG_FLAG_SIGNAL,
  12185         0,
  12186         1,
  12187         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88470_A0r_fields,
  12188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12189         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12190         -1,
  12191         -1,
  12192     },
  12193 #endif /* chips */
  12194 
  12195 #if defined(BCM_88470_B0)
  12196     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88470_B0r */
  12197         soc_block_list[22],
  12198         soc_genreg,
  12199         1,
  12200         0,
  12201         0x60,
  12202         SOC_REG_FLAG_ABOVE_64_BITS |
  12203                           SOC_REG_FLAG_RO |
  12204                           SOC_REG_FLAG_SIGNAL,
  12205         0,
  12206         1,
  12207         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88470_B0r_fields,
  12208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12209         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12210         -1,
  12211         -1,
  12212     },
  12213 #endif /* chips */
  12214 
  12215 #if defined(BCM_88650_B0)
  12216     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88650_B0r */
  12217         soc_block_list[22],
  12218         soc_genreg,
  12219         1,
  12220         0,
  12221         0x60,
  12222         SOC_REG_FLAG_ABOVE_64_BITS |
  12223                           SOC_REG_FLAG_RO,
  12224         0,
  12225         1,
  12226         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88650_B0r_fields,
  12227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12228         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12229         -1,
  12230         -1,
  12231     },
  12232 #endif /* chips */
  12233 
  12234 #if defined(BCM_88660_A0)
  12235     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88660_A0r */
  12236         soc_block_list[22],
  12237         soc_genreg,
  12238         1,
  12239         0,
  12240         0x60,
  12241         SOC_REG_FLAG_ABOVE_64_BITS |
  12242                           SOC_REG_FLAG_RO,
  12243         0,
  12244         1,
  12245         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88660_A0r_fields,
  12246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12247         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12248         -1,
  12249         -1,
  12250     },
  12251 #endif /* chips */
  12252 
  12253 #if defined(BCM_88675_A0)
  12254     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88675_A0r */
  12255         soc_block_list[22],
  12256         soc_genreg,
  12257         1,
  12258         0,
  12259         0x60,
  12260         SOC_REG_FLAG_ABOVE_64_BITS |
  12261                           SOC_REG_FLAG_RO |
  12262                           SOC_REG_FLAG_SIGNAL,
  12263         0,
  12264         1,
  12265         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88675_A0r_fields,
  12266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12267         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12268         -1,
  12269         -1,
  12270     },
  12271 #endif /* chips */
  12272 
  12273 #if defined(BCM_88675_B0)
  12274     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88675_B0r */
  12275         soc_block_list[22],
  12276         soc_genreg,
  12277         1,
  12278         0,
  12279         0x60,
  12280         SOC_REG_FLAG_ABOVE_64_BITS |
  12281                           SOC_REG_FLAG_RO |
  12282                           SOC_REG_FLAG_SIGNAL,
  12283         0,
  12284         1,
  12285         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88675_B0r_fields,
  12286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12288         -1,
  12289         -1,
  12290     },
  12291 #endif /* chips */
  12292 
  12293 #if defined(BCM_88680_A0)
  12294     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88680_A0r */
  12295         soc_block_list[22],
  12296         soc_genreg,
  12297         1,
  12298         0,
  12299         0x60,
  12300         SOC_REG_FLAG_ABOVE_64_BITS |
  12301                           SOC_REG_FLAG_RO |
  12302                           SOC_REG_FLAG_SIGNAL,
  12303         0,
  12304         1,
  12305         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88680_A0r_fields,
  12306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12308         -1,
  12309         -1,
  12310     },
  12311 #endif /* chips */
  12312 
  12313 #if defined(BCM_88690_A0)
  12314     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88690_A0r */
  12315         soc_block_list[22],
  12316         soc_genreg,
  12317         1,
  12318         0,
  12319         0x60,
  12320         SOC_REG_FLAG_ABOVE_64_BITS |
  12321                           SOC_REG_FLAG_RO |
  12322                           SOC_REG_FLAG_SIGNAL,
  12323         0,
  12324         1,
  12325         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88690_A0r_fields,
  12326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12328         -1,
  12329         -1,
  12330     },
  12331 #endif /* chips */
  12332 
  12333 #if defined(BCM_88690_B0)
  12334     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r */
  12335         soc_block_list[22],
  12336         soc_genreg,
  12337         1,
  12338         0,
  12339         0x60,
  12340         SOC_REG_FLAG_ABOVE_64_BITS |
  12341                           SOC_REG_FLAG_RO |
  12342                           SOC_REG_FLAG_SIGNAL,
  12343         0,
  12344         1,
  12345         soc_OAMP_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r_fields,
  12346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12347         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12348         -1,
  12349         -1,
  12350     },
  12351 #endif /* chips */
  12352 
  12353 #if defined(BCM_88675_A0)
  12354     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEMr */
  12355         soc_block_list[22],
  12356         soc_genreg,
  12357         1,
  12358         0,
  12359         0x41,
  12360         0,
  12361         0,
  12362         1,
  12363         soc_OAMP_INDIRECT_COMMAND_WIDE_MEMr_fields,
  12364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12365         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12366         -1,
  12367         -1,
  12368     },
  12369 #endif /* chips */
  12370 
  12371 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12372     defined(BCM_56270_A0)
  12373     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM56260_A0r */
  12374         soc_block_list[22],
  12375         soc_genreg,
  12376         1,
  12377         0,
  12378         0x2004100,
  12379         0,
  12380         0,
  12381         1,
  12382         soc_DCL_INDIRECT_COMMAND_WIDE_MEMr_fields,
  12383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12384         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12385         -1,
  12386         -1,
  12387     },
  12388 #endif /* chips */
  12389 
  12390 #if defined(BCM_88270_A0)
  12391     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88270_A0r */
  12392         soc_block_list[22],
  12393         soc_genreg,
  12394         1,
  12395         0,
  12396         0x41,
  12397         0,
  12398         0,
  12399         1,
  12400         soc_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88270_A0r_fields,
  12401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12402         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12403         -1,
  12404         -1,
  12405     },
  12406 #endif /* chips */
  12407 
  12408 #if defined(BCM_88375_A0)
  12409     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88375_A0r */
  12410         soc_block_list[22],
  12411         soc_genreg,
  12412         1,
  12413         0,
  12414         0x41,
  12415         0,
  12416         0,
  12417         1,
  12418         soc_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88375_A0r_fields,
  12419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12420         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12421         -1,
  12422         -1,
  12423     },
  12424 #endif /* chips */
  12425 
  12426 #if defined(BCM_88375_B0)
  12427     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88375_B0r */
  12428         soc_block_list[22],
  12429         soc_genreg,
  12430         1,
  12431         0,
  12432         0x41,
  12433         0,
  12434         0,
  12435         1,
  12436         soc_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88375_B0r_fields,
  12437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12438         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12439         -1,
  12440         -1,
  12441     },
  12442 #endif /* chips */
  12443 
  12444 #if defined(BCM_88470_A0)
  12445     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88470_A0r */
  12446         soc_block_list[22],
  12447         soc_genreg,
  12448         1,
  12449         0,
  12450         0x41,
  12451         0,
  12452         0,
  12453         1,
  12454         soc_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88470_A0r_fields,
  12455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12456         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12457         -1,
  12458         -1,
  12459     },
  12460 #endif /* chips */
  12461 
  12462 #if defined(BCM_88470_B0)
  12463     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88470_B0r */
  12464         soc_block_list[22],
  12465         soc_genreg,
  12466         1,
  12467         0,
  12468         0x41,
  12469         0,
  12470         0,
  12471         1,
  12472         soc_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88470_B0r_fields,
  12473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12474         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12475         -1,
  12476         -1,
  12477     },
  12478 #endif /* chips */
  12479 
  12480 #if defined(BCM_88675_B0)
  12481     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88675_B0r */
  12482         soc_block_list[22],
  12483         soc_genreg,
  12484         1,
  12485         0,
  12486         0x41,
  12487         0,
  12488         0,
  12489         1,
  12490         soc_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88675_B0r_fields,
  12491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12492         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12493         -1,
  12494         -1,
  12495     },
  12496 #endif /* chips */
  12497 
  12498 #if defined(BCM_88680_A0)
  12499     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r */
  12500         soc_block_list[22],
  12501         soc_genreg,
  12502         1,
  12503         0,
  12504         0x41,
  12505         0,
  12506         0,
  12507         1,
  12508         soc_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r_fields,
  12509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12510         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12511         -1,
  12512         -1,
  12513     },
  12514 #endif /* chips */
  12515 
  12516 #if defined(BCM_88690_A0)
  12517     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88690_A0r */
  12518         soc_block_list[22],
  12519         soc_genreg,
  12520         1,
  12521         0,
  12522         0x41,
  12523         0,
  12524         0,
  12525         1,
  12526         soc_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88690_A0r_fields,
  12527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12528         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12529         -1,
  12530         -1,
  12531     },
  12532 #endif /* chips */
  12533 
  12534 #if defined(BCM_88690_B0)
  12535     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88690_B0r */
  12536         soc_block_list[22],
  12537         soc_genreg,
  12538         1,
  12539         0,
  12540         0x41,
  12541         0,
  12542         0,
  12543         1,
  12544         soc_OAMP_INDIRECT_COMMAND_WIDE_MEM_BCM88690_B0r_fields,
  12545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12546         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12547         -1,
  12548         -1,
  12549     },
  12550 #endif /* chips */
  12551 
  12552 #if defined(BCM_88650_A0)
  12553     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATAr */
  12554         soc_block_list[22],
  12555         soc_genreg,
  12556         1,
  12557         0,
  12558         0x20,
  12559         SOC_REG_FLAG_ABOVE_64_BITS,
  12560         0,
  12561         1,
  12562         soc_OAMP_INDIRECT_COMMAND_WR_DATAr_fields,
  12563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12564         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12565         -1,
  12566         -1,
  12567     },
  12568 #endif /* chips */
  12569 
  12570 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12571     defined(BCM_56270_A0)
  12572     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM56260_A0r */
  12573         soc_block_list[22],
  12574         soc_genreg,
  12575         1,
  12576         0,
  12577         0x2002000,
  12578         SOC_REG_FLAG_ABOVE_64_BITS,
  12579         0,
  12580         1,
  12581         soc_DCL_INDIRECT_COMMAND_WR_DATAr_fields,
  12582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12584         -1,
  12585         -1,
  12586     },
  12587 #endif /* chips */
  12588 
  12589 #if defined(BCM_88270_A0)
  12590     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88270_A0r */
  12591         soc_block_list[22],
  12592         soc_genreg,
  12593         1,
  12594         0,
  12595         0x20,
  12596         SOC_REG_FLAG_ABOVE_64_BITS,
  12597         0,
  12598         1,
  12599         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88270_A0r_fields,
  12600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12602         -1,
  12603         -1,
  12604     },
  12605 #endif /* chips */
  12606 
  12607 #if defined(BCM_88375_A0)
  12608     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88375_A0r */
  12609         soc_block_list[22],
  12610         soc_genreg,
  12611         1,
  12612         0,
  12613         0x20,
  12614         SOC_REG_FLAG_ABOVE_64_BITS,
  12615         0,
  12616         1,
  12617         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88375_A0r_fields,
  12618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12619         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12620         -1,
  12621         -1,
  12622     },
  12623 #endif /* chips */
  12624 
  12625 #if defined(BCM_88375_B0)
  12626     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88375_B0r */
  12627         soc_block_list[22],
  12628         soc_genreg,
  12629         1,
  12630         0,
  12631         0x20,
  12632         SOC_REG_FLAG_ABOVE_64_BITS,
  12633         0,
  12634         1,
  12635         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88375_B0r_fields,
  12636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12637         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12638         -1,
  12639         -1,
  12640     },
  12641 #endif /* chips */
  12642 
  12643 #if defined(BCM_88470_A0)
  12644     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88470_A0r */
  12645         soc_block_list[22],
  12646         soc_genreg,
  12647         1,
  12648         0,
  12649         0x20,
  12650         SOC_REG_FLAG_ABOVE_64_BITS,
  12651         0,
  12652         1,
  12653         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88470_A0r_fields,
  12654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12655         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12656         -1,
  12657         -1,
  12658     },
  12659 #endif /* chips */
  12660 
  12661 #if defined(BCM_88470_B0)
  12662     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88470_B0r */
  12663         soc_block_list[22],
  12664         soc_genreg,
  12665         1,
  12666         0,
  12667         0x20,
  12668         SOC_REG_FLAG_ABOVE_64_BITS,
  12669         0,
  12670         1,
  12671         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88470_B0r_fields,
  12672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12673         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12674         -1,
  12675         -1,
  12676     },
  12677 #endif /* chips */
  12678 
  12679 #if defined(BCM_88650_B0)
  12680     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88650_B0r */
  12681         soc_block_list[22],
  12682         soc_genreg,
  12683         1,
  12684         0,
  12685         0x20,
  12686         SOC_REG_FLAG_ABOVE_64_BITS,
  12687         0,
  12688         1,
  12689         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88650_B0r_fields,
  12690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12692         -1,
  12693         -1,
  12694     },
  12695 #endif /* chips */
  12696 
  12697 #if defined(BCM_88660_A0)
  12698     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88660_A0r */
  12699         soc_block_list[22],
  12700         soc_genreg,
  12701         1,
  12702         0,
  12703         0x20,
  12704         SOC_REG_FLAG_ABOVE_64_BITS,
  12705         0,
  12706         1,
  12707         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88660_A0r_fields,
  12708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12710         -1,
  12711         -1,
  12712     },
  12713 #endif /* chips */
  12714 
  12715 #if defined(BCM_88675_A0)
  12716     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88675_A0r */
  12717         soc_block_list[22],
  12718         soc_genreg,
  12719         1,
  12720         0,
  12721         0x20,
  12722         SOC_REG_FLAG_ABOVE_64_BITS,
  12723         0,
  12724         1,
  12725         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88675_A0r_fields,
  12726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12727         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12728         -1,
  12729         -1,
  12730     },
  12731 #endif /* chips */
  12732 
  12733 #if defined(BCM_88675_B0)
  12734     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88675_B0r */
  12735         soc_block_list[22],
  12736         soc_genreg,
  12737         1,
  12738         0,
  12739         0x20,
  12740         SOC_REG_FLAG_ABOVE_64_BITS,
  12741         0,
  12742         1,
  12743         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88675_B0r_fields,
  12744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12745         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12746         -1,
  12747         -1,
  12748     },
  12749 #endif /* chips */
  12750 
  12751 #if defined(BCM_88680_A0)
  12752     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r */
  12753         soc_block_list[22],
  12754         soc_genreg,
  12755         1,
  12756         0,
  12757         0x20,
  12758         SOC_REG_FLAG_ABOVE_64_BITS,
  12759         0,
  12760         1,
  12761         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r_fields,
  12762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12764         -1,
  12765         -1,
  12766     },
  12767 #endif /* chips */
  12768 
  12769 #if defined(BCM_88690_A0)
  12770     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r */
  12771         soc_block_list[22],
  12772         soc_genreg,
  12773         1,
  12774         0,
  12775         0x20,
  12776         SOC_REG_FLAG_ABOVE_64_BITS,
  12777         0,
  12778         1,
  12779         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r_fields,
  12780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12782         -1,
  12783         -1,
  12784     },
  12785 #endif /* chips */
  12786 
  12787 #if defined(BCM_88690_B0)
  12788     { /* SOC_REG_INT_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r */
  12789         soc_block_list[22],
  12790         soc_genreg,
  12791         1,
  12792         0,
  12793         0x20,
  12794         SOC_REG_FLAG_ABOVE_64_BITS,
  12795         0,
  12796         1,
  12797         soc_OAMP_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r_fields,
  12798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12800         -1,
  12801         -1,
  12802     },
  12803 #endif /* chips */
  12804 
  12805 #if defined(BCM_88675_A0)
  12806     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLEr */
  12807         soc_block_list[22],
  12808         soc_genreg,
  12809         1,
  12810         0,
  12811         0x83,
  12812         0,
  12813         0,
  12814         4,
  12815         soc_OAMP_INDIRECT_FORCE_BUBBLEr_fields,
  12816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12817         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  12818         -1,
  12819         -1,
  12820     },
  12821 #endif /* chips */
  12822 
  12823 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12824     defined(BCM_56270_A0)
  12825     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM56260_A0r */
  12826         soc_block_list[22],
  12827         soc_genreg,
  12828         1,
  12829         0,
  12830         0x2008300,
  12831         0,
  12832         0,
  12833         4,
  12834         soc_DCL_INDIRECT_FORCE_BUBBLEr_fields,
  12835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12836         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  12837         -1,
  12838         -1,
  12839     },
  12840 #endif /* chips */
  12841 
  12842 #if defined(BCM_88270_A0)
  12843     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM88270_A0r */
  12844         soc_block_list[22],
  12845         soc_genreg,
  12846         1,
  12847         0,
  12848         0x83,
  12849         0,
  12850         0,
  12851         4,
  12852         soc_OAMP_INDIRECT_FORCE_BUBBLE_BCM88270_A0r_fields,
  12853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12854         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  12855         -1,
  12856         -1,
  12857     },
  12858 #endif /* chips */
  12859 
  12860 #if defined(BCM_88375_A0)
  12861     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM88375_A0r */
  12862         soc_block_list[22],
  12863         soc_genreg,
  12864         1,
  12865         0,
  12866         0x83,
  12867         0,
  12868         0,
  12869         4,
  12870         soc_OAMP_INDIRECT_FORCE_BUBBLE_BCM88375_A0r_fields,
  12871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12872         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  12873         -1,
  12874         -1,
  12875     },
  12876 #endif /* chips */
  12877 
  12878 #if defined(BCM_88375_B0)
  12879     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM88375_B0r */
  12880         soc_block_list[22],
  12881         soc_genreg,
  12882         1,
  12883         0,
  12884         0x83,
  12885         0,
  12886         0,
  12887         4,
  12888         soc_OAMP_INDIRECT_FORCE_BUBBLE_BCM88375_B0r_fields,
  12889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12890         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  12891         -1,
  12892         -1,
  12893     },
  12894 #endif /* chips */
  12895 
  12896 #if defined(BCM_88470_A0)
  12897     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM88470_A0r */
  12898         soc_block_list[22],
  12899         soc_genreg,
  12900         1,
  12901         0,
  12902         0x83,
  12903         0,
  12904         0,
  12905         4,
  12906         soc_OAMP_INDIRECT_FORCE_BUBBLE_BCM88470_A0r_fields,
  12907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12908         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  12909         -1,
  12910         -1,
  12911     },
  12912 #endif /* chips */
  12913 
  12914 #if defined(BCM_88470_B0)
  12915     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM88470_B0r */
  12916         soc_block_list[22],
  12917         soc_genreg,
  12918         1,
  12919         0,
  12920         0x83,
  12921         0,
  12922         0,
  12923         4,
  12924         soc_OAMP_INDIRECT_FORCE_BUBBLE_BCM88470_B0r_fields,
  12925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12926         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  12927         -1,
  12928         -1,
  12929     },
  12930 #endif /* chips */
  12931 
  12932 #if defined(BCM_88675_B0)
  12933     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM88675_B0r */
  12934         soc_block_list[22],
  12935         soc_genreg,
  12936         1,
  12937         0,
  12938         0x83,
  12939         0,
  12940         0,
  12941         4,
  12942         soc_OAMP_INDIRECT_FORCE_BUBBLE_BCM88675_B0r_fields,
  12943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12944         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  12945         -1,
  12946         -1,
  12947     },
  12948 #endif /* chips */
  12949 
  12950 #if defined(BCM_88680_A0)
  12951     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM88680_A0r */
  12952         soc_block_list[22],
  12953         soc_genreg,
  12954         1,
  12955         0,
  12956         0x83,
  12957         0,
  12958         0,
  12959         4,
  12960         soc_OAMP_INDIRECT_FORCE_BUBBLE_BCM88680_A0r_fields,
  12961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12962         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  12963         -1,
  12964         -1,
  12965     },
  12966 #endif /* chips */
  12967 
  12968 #if defined(BCM_88690_A0)
  12969     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM88690_A0r */
  12970         soc_block_list[22],
  12971         soc_genreg,
  12972         1,
  12973         0,
  12974         0x83,
  12975         0,
  12976         0,
  12977         4,
  12978         soc_OAMP_INDIRECT_FORCE_BUBBLE_BCM88690_A0r_fields,
  12979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12980         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  12981         -1,
  12982         -1,
  12983     },
  12984 #endif /* chips */
  12985 
  12986 #if defined(BCM_88690_B0)
  12987     { /* SOC_REG_INT_OAMP_INDIRECT_FORCE_BUBBLE_BCM88690_B0r */
  12988         soc_block_list[22],
  12989         soc_genreg,
  12990         1,
  12991         0,
  12992         0x83,
  12993         0,
  12994         0,
  12995         4,
  12996         soc_OAMP_INDIRECT_FORCE_BUBBLE_BCM88690_B0r_fields,
  12997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12998         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  12999         -1,
  13000         -1,
  13001     },
  13002 #endif /* chips */
  13003 
  13004 #if defined(BCM_88650_A0)
  13005     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASKr */
  13006         soc_block_list[22],
  13007         soc_genreg,
  13008         1,
  13009         0,
  13010         0x40,
  13011         SOC_REG_FLAG_ABOVE_64_BITS,
  13012         0,
  13013         1,
  13014         soc_OAMP_INDIRECT_WR_MASKr_fields,
  13015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13016         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13017         -1,
  13018         -1,
  13019     },
  13020 #endif /* chips */
  13021 
  13022 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  13023     defined(BCM_56270_A0)
  13024     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM56260_A0r */
  13025         soc_block_list[22],
  13026         soc_genreg,
  13027         1,
  13028         0,
  13029         0x2004000,
  13030         SOC_REG_FLAG_ABOVE_64_BITS,
  13031         0,
  13032         1,
  13033         soc_OAMP_INDIRECT_WR_MASK_BCM56260_A0r_fields,
  13034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13035         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13036         -1,
  13037         -1,
  13038     },
  13039 #endif /* chips */
  13040 
  13041 #if defined(BCM_88270_A0)
  13042     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88270_A0r */
  13043         soc_block_list[22],
  13044         soc_genreg,
  13045         1,
  13046         0,
  13047         0x40,
  13048         0,
  13049         0,
  13050         1,
  13051         soc_OAMP_INDIRECT_WR_MASK_BCM88270_A0r_fields,
  13052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13053         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  13054         -1,
  13055         -1,
  13056     },
  13057 #endif /* chips */
  13058 
  13059 #if defined(BCM_88375_A0)
  13060     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88375_A0r */
  13061         soc_block_list[22],
  13062         soc_genreg,
  13063         1,
  13064         0,
  13065         0x40,
  13066         SOC_REG_FLAG_ABOVE_64_BITS,
  13067         0,
  13068         1,
  13069         soc_OAMP_INDIRECT_WR_MASK_BCM88375_A0r_fields,
  13070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13072         -1,
  13073         -1,
  13074     },
  13075 #endif /* chips */
  13076 
  13077 #if defined(BCM_88375_B0)
  13078     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88375_B0r */
  13079         soc_block_list[22],
  13080         soc_genreg,
  13081         1,
  13082         0,
  13083         0x40,
  13084         SOC_REG_FLAG_ABOVE_64_BITS,
  13085         0,
  13086         1,
  13087         soc_OAMP_INDIRECT_WR_MASK_BCM88375_B0r_fields,
  13088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13089         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13090         -1,
  13091         -1,
  13092     },
  13093 #endif /* chips */
  13094 
  13095 #if defined(BCM_88470_A0)
  13096     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88470_A0r */
  13097         soc_block_list[22],
  13098         soc_genreg,
  13099         1,
  13100         0,
  13101         0x40,
  13102         0,
  13103         0,
  13104         1,
  13105         soc_OAMP_INDIRECT_WR_MASK_BCM88470_A0r_fields,
  13106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13107         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  13108         -1,
  13109         -1,
  13110     },
  13111 #endif /* chips */
  13112 
  13113 #if defined(BCM_88470_B0)
  13114     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88470_B0r */
  13115         soc_block_list[22],
  13116         soc_genreg,
  13117         1,
  13118         0,
  13119         0x40,
  13120         0,
  13121         0,
  13122         1,
  13123         soc_OAMP_INDIRECT_WR_MASK_BCM88470_B0r_fields,
  13124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13125         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  13126         -1,
  13127         -1,
  13128     },
  13129 #endif /* chips */
  13130 
  13131 #if defined(BCM_88650_B0)
  13132     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88650_B0r */
  13133         soc_block_list[22],
  13134         soc_genreg,
  13135         1,
  13136         0,
  13137         0x40,
  13138         SOC_REG_FLAG_ABOVE_64_BITS,
  13139         0,
  13140         1,
  13141         soc_OAMP_INDIRECT_WR_MASK_BCM88650_B0r_fields,
  13142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13143         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13144         -1,
  13145         -1,
  13146     },
  13147 #endif /* chips */
  13148 
  13149 #if defined(BCM_88660_A0)
  13150     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88660_A0r */
  13151         soc_block_list[22],
  13152         soc_genreg,
  13153         1,
  13154         0,
  13155         0x40,
  13156         SOC_REG_FLAG_ABOVE_64_BITS,
  13157         0,
  13158         1,
  13159         soc_OAMP_INDIRECT_WR_MASK_BCM88660_A0r_fields,
  13160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13162         -1,
  13163         -1,
  13164     },
  13165 #endif /* chips */
  13166 
  13167 #if defined(BCM_88675_A0)
  13168     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88675_A0r */
  13169         soc_block_list[22],
  13170         soc_genreg,
  13171         1,
  13172         0,
  13173         0x40,
  13174         SOC_REG_FLAG_ABOVE_64_BITS,
  13175         0,
  13176         1,
  13177         soc_OAMP_INDIRECT_WR_MASK_BCM88675_A0r_fields,
  13178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13179         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13180         -1,
  13181         -1,
  13182     },
  13183 #endif /* chips */
  13184 
  13185 #if defined(BCM_88675_B0)
  13186     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88675_B0r */
  13187         soc_block_list[22],
  13188         soc_genreg,
  13189         1,
  13190         0,
  13191         0x40,
  13192         SOC_REG_FLAG_ABOVE_64_BITS,
  13193         0,
  13194         1,
  13195         soc_OAMP_INDIRECT_WR_MASK_BCM88675_B0r_fields,
  13196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13197         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13198         -1,
  13199         -1,
  13200     },
  13201 #endif /* chips */
  13202 
  13203 #if defined(BCM_88680_A0)
  13204     { /* SOC_REG_INT_OAMP_INDIRECT_WR_MASK_BCM88680_A0r */
  13205         soc_block_list[22],
  13206         soc_genreg,
  13207         1,
  13208         0,
  13209         0x40,
  13210         SOC_REG_FLAG_ABOVE_64_BITS,
  13211         0,
  13212         1,
  13213         soc_OAMP_INDIRECT_WR_MASK_BCM88680_A0r_fields,
  13214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13215         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13216         -1,
  13217         -1,
  13218     },
  13219 #endif /* chips */
  13220 
  13221 #if defined(BCM_88650_A0)
  13222     { /* SOC_REG_INT_OAMP_INITIATE_ECC_ERR_0r */
  13223         soc_block_list[22],
  13224         soc_genreg,
  13225         1,
  13226         0,
  13227         0xa4,
  13228         0,
  13229         0,
  13230         2,
  13231         soc_OAMP_INITIATE_ECC_ERR_0r_fields,
  13232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13233         SOC_RESET_MASK_DEC(0x24000000, 0x00000000)
  13234         -1,
  13235         -1,
  13236     },
  13237 #endif /* chips */
  13238 
  13239 #if defined(BCM_88650_B0)
  13240     { /* SOC_REG_INT_OAMP_INITIATE_ECC_ERR_0_BCM88650_B0r */
  13241         soc_block_list[22],
  13242         soc_genreg,
  13243         1,
  13244         0,
  13245         0xa4,
  13246         0,
  13247         0,
  13248         2,
  13249         soc_OAMP_INITIATE_ECC_ERR_0_BCM88650_B0r_fields,
  13250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13251         SOC_RESET_MASK_DEC(0x24000000, 0x00000000)
  13252         -1,
  13253         -1,
  13254     },
  13255 #endif /* chips */
  13256 
  13257 #if defined(BCM_88660_A0)
  13258     { /* SOC_REG_INT_OAMP_INITIATE_ECC_ERR_0_BCM88660_A0r */
  13259         soc_block_list[22],
  13260         soc_genreg,
  13261         1,
  13262         0,
  13263         0xa4,
  13264         0,
  13265         0,
  13266         2,
  13267         soc_OAMP_INITIATE_ECC_ERR_0_BCM88660_A0r_fields,
  13268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13269         SOC_RESET_MASK_DEC(0x24000000, 0x00000000)
  13270         -1,
  13271         -1,
  13272     },
  13273 #endif /* chips */
  13274 
  13275 #if defined(BCM_88650_A0)
  13276     { /* SOC_REG_INT_OAMP_INITIATE_PAR_ERR_0r */
  13277         soc_block_list[22],
  13278         soc_genreg,
  13279         1,
  13280         0,
  13281         0xaa,
  13282         SOC_REG_FLAG_64_BITS,
  13283         0,
  13284         33,
  13285         soc_OAMP_INITIATE_PAR_ERR_0r_fields,
  13286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  13288         -1,
  13289         -1,
  13290     },
  13291 #endif /* chips */
  13292 
  13293 #if defined(BCM_88650_B0)
  13294     { /* SOC_REG_INT_OAMP_INITIATE_PAR_ERR_0_BCM88650_B0r */
  13295         soc_block_list[22],
  13296         soc_genreg,
  13297         1,
  13298         0,
  13299         0xaa,
  13300         SOC_REG_FLAG_64_BITS,
  13301         0,
  13302         33,
  13303         soc_OAMP_INITIATE_PAR_ERR_0_BCM88650_B0r_fields,
  13304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  13306         -1,
  13307         -1,
  13308     },
  13309 #endif /* chips */
  13310 
  13311 #if defined(BCM_88660_A0)
  13312     { /* SOC_REG_INT_OAMP_INITIATE_PAR_ERR_0_BCM88660_A0r */
  13313         soc_block_list[22],
  13314         soc_genreg,
  13315         1,
  13316         0,
  13317         0xaa,
  13318         SOC_REG_FLAG_64_BITS,
  13319         0,
  13320         38,
  13321         soc_OAMP_INITIATE_PAR_ERR_0_BCM88660_A0r_fields,
  13322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13323         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  13324         -1,
  13325         -1,
  13326     },
  13327 #endif /* chips */
  13328 
  13329 #if defined(BCM_88660_A0)
  13330     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLVr */
  13331         soc_block_list[22],
  13332         soc_genreg,
  13333         1,
  13334         0,
  13335         0x439,
  13336         SOC_REG_FLAG_SIGNAL,
  13337         0,
  13338         1,
  13339         soc_OAMP_INTERFACE_STAT_TLVr_fields,
  13340         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13341         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13342         -1,
  13343         -1,
  13344     },
  13345 #endif /* chips */
  13346 
  13347 #if defined(BCM_88270_A0)
  13348     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88270_A0r */
  13349         soc_block_list[22],
  13350         soc_genreg,
  13351         1,
  13352         0,
  13353         0x441,
  13354         0,
  13355         0,
  13356         1,
  13357         soc_OAMP_INTERFACE_STAT_TLV_BCM88270_A0r_fields,
  13358         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13359         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13360         -1,
  13361         -1,
  13362     },
  13363 #endif /* chips */
  13364 
  13365 #if defined(BCM_88375_A0)
  13366     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88375_A0r */
  13367         soc_block_list[22],
  13368         soc_genreg,
  13369         1,
  13370         0,
  13371         0x43e,
  13372         0,
  13373         0,
  13374         1,
  13375         soc_OAMP_INTERFACE_STAT_TLV_BCM88375_A0r_fields,
  13376         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13377         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13378         -1,
  13379         -1,
  13380     },
  13381 #endif /* chips */
  13382 
  13383 #if defined(BCM_88375_B0)
  13384     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88375_B0r */
  13385         soc_block_list[22],
  13386         soc_genreg,
  13387         1,
  13388         0,
  13389         0x43e,
  13390         0,
  13391         0,
  13392         1,
  13393         soc_OAMP_INTERFACE_STAT_TLV_BCM88375_B0r_fields,
  13394         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13395         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13396         -1,
  13397         -1,
  13398     },
  13399 #endif /* chips */
  13400 
  13401 #if defined(BCM_88470_A0)
  13402     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88470_A0r */
  13403         soc_block_list[22],
  13404         soc_genreg,
  13405         1,
  13406         0,
  13407         0x441,
  13408         0,
  13409         0,
  13410         1,
  13411         soc_OAMP_INTERFACE_STAT_TLV_BCM88470_A0r_fields,
  13412         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13413         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13414         -1,
  13415         -1,
  13416     },
  13417 #endif /* chips */
  13418 
  13419 #if defined(BCM_88470_B0)
  13420     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88470_B0r */
  13421         soc_block_list[22],
  13422         soc_genreg,
  13423         1,
  13424         0,
  13425         0x441,
  13426         0,
  13427         0,
  13428         1,
  13429         soc_OAMP_INTERFACE_STAT_TLV_BCM88470_B0r_fields,
  13430         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13431         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13432         -1,
  13433         -1,
  13434     },
  13435 #endif /* chips */
  13436 
  13437 #if defined(BCM_88675_A0)
  13438     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88675_A0r */
  13439         soc_block_list[22],
  13440         soc_genreg,
  13441         1,
  13442         0,
  13443         0x43e,
  13444         0,
  13445         0,
  13446         1,
  13447         soc_OAMP_INTERFACE_STAT_TLV_BCM88675_A0r_fields,
  13448         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13449         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13450         -1,
  13451         -1,
  13452     },
  13453 #endif /* chips */
  13454 
  13455 #if defined(BCM_88675_B0)
  13456     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88675_B0r */
  13457         soc_block_list[22],
  13458         soc_genreg,
  13459         1,
  13460         0,
  13461         0x43e,
  13462         0,
  13463         0,
  13464         1,
  13465         soc_OAMP_INTERFACE_STAT_TLV_BCM88675_B0r_fields,
  13466         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13467         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13468         -1,
  13469         -1,
  13470     },
  13471 #endif /* chips */
  13472 
  13473 #if defined(BCM_88680_A0)
  13474     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88680_A0r */
  13475         soc_block_list[22],
  13476         soc_genreg,
  13477         1,
  13478         0,
  13479         0x43e,
  13480         0,
  13481         0,
  13482         1,
  13483         soc_OAMP_INTERFACE_STAT_TLV_BCM88680_A0r_fields,
  13484         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13485         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13486         -1,
  13487         -1,
  13488     },
  13489 #endif /* chips */
  13490 
  13491 #if defined(BCM_88690_A0)
  13492     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88690_A0r */
  13493         soc_block_list[22],
  13494         soc_genreg,
  13495         1,
  13496         0,
  13497         0x531,
  13498         0,
  13499         0,
  13500         1,
  13501         soc_OAMP_INTERFACE_STAT_TLV_BCM88690_A0r_fields,
  13502         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13503         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13504         -1,
  13505         -1,
  13506     },
  13507 #endif /* chips */
  13508 
  13509 #if defined(BCM_88690_B0)
  13510     { /* SOC_REG_INT_OAMP_INTERFACE_STAT_TLV_BCM88690_B0r */
  13511         soc_block_list[22],
  13512         soc_genreg,
  13513         1,
  13514         0,
  13515         0x531,
  13516         0,
  13517         0,
  13518         1,
  13519         soc_OAMP_INTERFACE_STAT_TLV_BCM88690_B0r_fields,
  13520         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  13521         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13522         -1,
  13523         -1,
  13524     },
  13525 #endif /* chips */
  13526 
  13527 #if defined(BCM_88650_A0)
  13528     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTERr */
  13529         soc_block_list[22],
  13530         soc_genreg,
  13531         1,
  13532         0,
  13533         0x10,
  13534         0,
  13535         0,
  13536         3,
  13537         soc_OAMP_INTERRUPT_MASK_REGISTERr_fields,
  13538         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  13539         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13540         -1,
  13541         -1,
  13542     },
  13543 #endif /* chips */
  13544 
  13545 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  13546     defined(BCM_56270_A0)
  13547     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM56260_A0r */
  13548         soc_block_list[22],
  13549         soc_genreg,
  13550         1,
  13551         0,
  13552         0x2001000,
  13553         0,
  13554         0,
  13555         3,
  13556         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM56260_A0r_fields,
  13557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13558         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13559         -1,
  13560         -1,
  13561     },
  13562 #endif /* chips */
  13563 
  13564 #if defined(BCM_88270_A0)
  13565     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88270_A0r */
  13566         soc_block_list[22],
  13567         soc_genreg,
  13568         1,
  13569         0,
  13570         0x10,
  13571         0,
  13572         0,
  13573         8,
  13574         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88270_A0r_fields,
  13575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13576         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13577         -1,
  13578         -1,
  13579     },
  13580 #endif /* chips */
  13581 
  13582 #if defined(BCM_88375_A0)
  13583     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88375_A0r */
  13584         soc_block_list[22],
  13585         soc_genreg,
  13586         1,
  13587         0,
  13588         0x10,
  13589         0,
  13590         0,
  13591         6,
  13592         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88375_A0r_fields,
  13593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13594         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  13595         -1,
  13596         -1,
  13597     },
  13598 #endif /* chips */
  13599 
  13600 #if defined(BCM_88375_B0)
  13601     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88375_B0r */
  13602         soc_block_list[22],
  13603         soc_genreg,
  13604         1,
  13605         0,
  13606         0x10,
  13607         0,
  13608         0,
  13609         6,
  13610         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88375_B0r_fields,
  13611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13612         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  13613         -1,
  13614         -1,
  13615     },
  13616 #endif /* chips */
  13617 
  13618 #if defined(BCM_88470_A0)
  13619     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88470_A0r */
  13620         soc_block_list[22],
  13621         soc_genreg,
  13622         1,
  13623         0,
  13624         0x10,
  13625         0,
  13626         0,
  13627         8,
  13628         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88470_A0r_fields,
  13629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13630         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13631         -1,
  13632         -1,
  13633     },
  13634 #endif /* chips */
  13635 
  13636 #if defined(BCM_88470_B0)
  13637     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88470_B0r */
  13638         soc_block_list[22],
  13639         soc_genreg,
  13640         1,
  13641         0,
  13642         0x10,
  13643         0,
  13644         0,
  13645         8,
  13646         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88470_B0r_fields,
  13647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13648         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13649         -1,
  13650         -1,
  13651     },
  13652 #endif /* chips */
  13653 
  13654 #if defined(BCM_88650_B0)
  13655     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88650_B0r */
  13656         soc_block_list[22],
  13657         soc_genreg,
  13658         1,
  13659         0,
  13660         0x10,
  13661         0,
  13662         0,
  13663         3,
  13664         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88650_B0r_fields,
  13665         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  13666         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13667         -1,
  13668         -1,
  13669     },
  13670 #endif /* chips */
  13671 
  13672 #if defined(BCM_88660_A0)
  13673     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88660_A0r */
  13674         soc_block_list[22],
  13675         soc_genreg,
  13676         1,
  13677         0,
  13678         0x10,
  13679         0,
  13680         0,
  13681         3,
  13682         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88660_A0r_fields,
  13683         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  13684         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13685         -1,
  13686         -1,
  13687     },
  13688 #endif /* chips */
  13689 
  13690 #if defined(BCM_88675_A0)
  13691     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88675_A0r */
  13692         soc_block_list[22],
  13693         soc_genreg,
  13694         1,
  13695         0,
  13696         0x10,
  13697         0,
  13698         0,
  13699         6,
  13700         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88675_A0r_fields,
  13701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13702         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  13703         -1,
  13704         -1,
  13705     },
  13706 #endif /* chips */
  13707 
  13708 #if defined(BCM_88675_B0)
  13709     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88675_B0r */
  13710         soc_block_list[22],
  13711         soc_genreg,
  13712         1,
  13713         0,
  13714         0x10,
  13715         0,
  13716         0,
  13717         6,
  13718         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88675_B0r_fields,
  13719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13720         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  13721         -1,
  13722         -1,
  13723     },
  13724 #endif /* chips */
  13725 
  13726 #if defined(BCM_88680_A0)
  13727     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88680_A0r */
  13728         soc_block_list[22],
  13729         soc_genreg,
  13730         1,
  13731         0,
  13732         0x10,
  13733         0,
  13734         0,
  13735         6,
  13736         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88680_A0r_fields,
  13737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13738         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  13739         -1,
  13740         -1,
  13741     },
  13742 #endif /* chips */
  13743 
  13744 #if defined(BCM_88690_A0)
  13745     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88690_A0r */
  13746         soc_block_list[22],
  13747         soc_genreg,
  13748         1,
  13749         0,
  13750         0x10,
  13751         0,
  13752         0,
  13753         10,
  13754         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88690_A0r_fields,
  13755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13756         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  13757         -1,
  13758         -1,
  13759     },
  13760 #endif /* chips */
  13761 
  13762 #if defined(BCM_88690_B0)
  13763     { /* SOC_REG_INT_OAMP_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  13764         soc_block_list[22],
  13765         soc_genreg,
  13766         1,
  13767         0,
  13768         0x10,
  13769         0,
  13770         0,
  13771         10,
  13772         soc_OAMP_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  13773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13774         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  13775         -1,
  13776         -1,
  13777     },
  13778 #endif /* chips */
  13779 
  13780 #if defined(BCM_88650_A0)
  13781     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGEr */
  13782         soc_block_list[22],
  13783         soc_genreg,
  13784         1,
  13785         0,
  13786         0x140,
  13787         SOC_REG_FLAG_RO,
  13788         0,
  13789         1,
  13790         soc_OAMP_INTERRUPT_MESSAGEr_fields,
  13791         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  13792         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13793         -1,
  13794         -1,
  13795     },
  13796 #endif /* chips */
  13797 
  13798 #if defined(BCM_88270_A0)
  13799     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88270_A0r */
  13800         soc_block_list[22],
  13801         soc_genreg,
  13802         1,
  13803         0,
  13804         0x142,
  13805         SOC_REG_FLAG_ABOVE_64_BITS |
  13806                           SOC_REG_FLAG_RO |
  13807                           SOC_REG_FLAG_INTERRUPT |
  13808                           SOC_REG_FLAG_SIGNAL,
  13809         0,
  13810         1,
  13811         soc_OAMP_INTERRUPT_MESSAGE_BCM88270_A0r_fields,
  13812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13814         -1,
  13815         -1,
  13816     },
  13817 #endif /* chips */
  13818 
  13819 #if defined(BCM_88375_A0)
  13820     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88375_A0r */
  13821         soc_block_list[22],
  13822         soc_genreg,
  13823         1,
  13824         0,
  13825         0x140,
  13826         SOC_REG_FLAG_ABOVE_64_BITS |
  13827                           SOC_REG_FLAG_RO |
  13828                           SOC_REG_FLAG_INTERRUPT |
  13829                           SOC_REG_FLAG_SIGNAL,
  13830         0,
  13831         1,
  13832         soc_OAMP_INTERRUPT_MESSAGE_BCM88375_A0r_fields,
  13833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13835         -1,
  13836         -1,
  13837     },
  13838 #endif /* chips */
  13839 
  13840 #if defined(BCM_88375_B0)
  13841     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88375_B0r */
  13842         soc_block_list[22],
  13843         soc_genreg,
  13844         1,
  13845         0,
  13846         0x140,
  13847         SOC_REG_FLAG_ABOVE_64_BITS |
  13848                           SOC_REG_FLAG_RO |
  13849                           SOC_REG_FLAG_INTERRUPT |
  13850                           SOC_REG_FLAG_SIGNAL,
  13851         0,
  13852         1,
  13853         soc_OAMP_INTERRUPT_MESSAGE_BCM88375_B0r_fields,
  13854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13855         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13856         -1,
  13857         -1,
  13858     },
  13859 #endif /* chips */
  13860 
  13861 #if defined(BCM_88470_A0)
  13862     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88470_A0r */
  13863         soc_block_list[22],
  13864         soc_genreg,
  13865         1,
  13866         0,
  13867         0x142,
  13868         SOC_REG_FLAG_ABOVE_64_BITS |
  13869                           SOC_REG_FLAG_RO |
  13870                           SOC_REG_FLAG_INTERRUPT |
  13871                           SOC_REG_FLAG_SIGNAL,
  13872         0,
  13873         1,
  13874         soc_OAMP_INTERRUPT_MESSAGE_BCM88470_A0r_fields,
  13875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13877         -1,
  13878         -1,
  13879     },
  13880 #endif /* chips */
  13881 
  13882 #if defined(BCM_88470_B0)
  13883     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88470_B0r */
  13884         soc_block_list[22],
  13885         soc_genreg,
  13886         1,
  13887         0,
  13888         0x142,
  13889         SOC_REG_FLAG_ABOVE_64_BITS |
  13890                           SOC_REG_FLAG_RO |
  13891                           SOC_REG_FLAG_INTERRUPT |
  13892                           SOC_REG_FLAG_SIGNAL,
  13893         0,
  13894         1,
  13895         soc_OAMP_INTERRUPT_MESSAGE_BCM88470_B0r_fields,
  13896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13898         -1,
  13899         -1,
  13900     },
  13901 #endif /* chips */
  13902 
  13903 #if defined(BCM_88650_B0)
  13904     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88650_B0r */
  13905         soc_block_list[22],
  13906         soc_genreg,
  13907         1,
  13908         0,
  13909         0x140,
  13910         SOC_REG_FLAG_RO,
  13911         0,
  13912         1,
  13913         soc_OAMP_INTERRUPT_MESSAGE_BCM88650_B0r_fields,
  13914         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  13915         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13916         -1,
  13917         -1,
  13918     },
  13919 #endif /* chips */
  13920 
  13921 #if defined(BCM_88660_A0)
  13922     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88660_A0r */
  13923         soc_block_list[22],
  13924         soc_genreg,
  13925         1,
  13926         0,
  13927         0x140,
  13928         SOC_REG_FLAG_ABOVE_64_BITS |
  13929                           SOC_REG_FLAG_RO,
  13930         0,
  13931         1,
  13932         soc_OAMP_INTERRUPT_MESSAGE_BCM88660_A0r_fields,
  13933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13934         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13935         -1,
  13936         -1,
  13937     },
  13938 #endif /* chips */
  13939 
  13940 #if defined(BCM_88675_A0)
  13941     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88675_A0r */
  13942         soc_block_list[22],
  13943         soc_genreg,
  13944         1,
  13945         0,
  13946         0x140,
  13947         SOC_REG_FLAG_ABOVE_64_BITS |
  13948                           SOC_REG_FLAG_RO |
  13949                           SOC_REG_FLAG_INTERRUPT |
  13950                           SOC_REG_FLAG_SIGNAL,
  13951         0,
  13952         1,
  13953         soc_OAMP_INTERRUPT_MESSAGE_BCM88675_A0r_fields,
  13954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13956         -1,
  13957         -1,
  13958     },
  13959 #endif /* chips */
  13960 
  13961 #if defined(BCM_88675_B0)
  13962     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88675_B0r */
  13963         soc_block_list[22],
  13964         soc_genreg,
  13965         1,
  13966         0,
  13967         0x140,
  13968         SOC_REG_FLAG_ABOVE_64_BITS |
  13969                           SOC_REG_FLAG_RO |
  13970                           SOC_REG_FLAG_INTERRUPT |
  13971                           SOC_REG_FLAG_SIGNAL,
  13972         0,
  13973         1,
  13974         soc_OAMP_INTERRUPT_MESSAGE_BCM88675_B0r_fields,
  13975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13976         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13977         -1,
  13978         -1,
  13979     },
  13980 #endif /* chips */
  13981 
  13982 #if defined(BCM_88680_A0)
  13983     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88680_A0r */
  13984         soc_block_list[22],
  13985         soc_genreg,
  13986         1,
  13987         0,
  13988         0x140,
  13989         SOC_REG_FLAG_ABOVE_64_BITS |
  13990                           SOC_REG_FLAG_RO |
  13991                           SOC_REG_FLAG_INTERRUPT |
  13992                           SOC_REG_FLAG_SIGNAL,
  13993         0,
  13994         1,
  13995         soc_OAMP_INTERRUPT_MESSAGE_BCM88680_A0r_fields,
  13996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13997         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13998         -1,
  13999         -1,
  14000     },
  14001 #endif /* chips */
  14002 
  14003 #if defined(BCM_88690_A0)
  14004     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88690_A0r */
  14005         soc_block_list[22],
  14006         soc_genreg,
  14007         1,
  14008         0,
  14009         0x13d,
  14010         SOC_REG_FLAG_ABOVE_64_BITS |
  14011                           SOC_REG_FLAG_RO |
  14012                           SOC_REG_FLAG_INTERRUPT |
  14013                           SOC_REG_FLAG_SIGNAL,
  14014         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  14015         1,
  14016         soc_OAMP_INTERRUPT_MESSAGE_BCM88690_A0r_fields,
  14017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14018         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14019         -1,
  14020         -1,
  14021     },
  14022 #endif /* chips */
  14023 
  14024 #if defined(BCM_88690_B0)
  14025     { /* SOC_REG_INT_OAMP_INTERRUPT_MESSAGE_BCM88690_B0r */
  14026         soc_block_list[22],
  14027         soc_genreg,
  14028         1,
  14029         0,
  14030         0x13d,
  14031         SOC_REG_FLAG_ABOVE_64_BITS |
  14032                           SOC_REG_FLAG_RO |
  14033                           SOC_REG_FLAG_INTERRUPT |
  14034                           SOC_REG_FLAG_SIGNAL,
  14035         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  14036         1,
  14037         soc_OAMP_INTERRUPT_MESSAGE_BCM88690_B0r_fields,
  14038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14040         -1,
  14041         -1,
  14042     },
  14043 #endif /* chips */
  14044 
  14045 #if defined(BCM_88650_A0)
  14046     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTERr */
  14047         soc_block_list[22],
  14048         soc_genreg,
  14049         1,
  14050         0,
  14051         0,
  14052         SOC_REG_FLAG_INTERRUPT |
  14053                           SOC_REG_FLAG_SIGNAL,
  14054         0,
  14055         3,
  14056         soc_OAMP_INTERRUPT_REGISTERr_fields,
  14057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14058         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  14059         -1,
  14060         -1,
  14061     },
  14062 #endif /* chips */
  14063 
  14064 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  14065     defined(BCM_56270_A0)
  14066     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM56260_A0r */
  14067         soc_block_list[22],
  14068         soc_genreg,
  14069         1,
  14070         0,
  14071         0x2000000,
  14072         SOC_REG_FLAG_INTERRUPT,
  14073         0,
  14074         3,
  14075         soc_OAMP_INTERRUPT_REGISTER_BCM56260_A0r_fields,
  14076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14077         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  14078         -1,
  14079         -1,
  14080     },
  14081 #endif /* chips */
  14082 
  14083 #if defined(BCM_88270_A0)
  14084     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88270_A0r */
  14085         soc_block_list[22],
  14086         soc_genreg,
  14087         1,
  14088         0,
  14089         0,
  14090         SOC_REG_FLAG_INTERRUPT |
  14091                           SOC_REG_FLAG_SIGNAL,
  14092         0,
  14093         8,
  14094         soc_OAMP_INTERRUPT_REGISTER_BCM88270_A0r_fields,
  14095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14096         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14097         -1,
  14098         -1,
  14099     },
  14100 #endif /* chips */
  14101 
  14102 #if defined(BCM_88375_A0)
  14103     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88375_A0r */
  14104         soc_block_list[22],
  14105         soc_genreg,
  14106         1,
  14107         0,
  14108         0,
  14109         SOC_REG_FLAG_INTERRUPT,
  14110         0,
  14111         6,
  14112         soc_OAMP_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  14113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14114         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  14115         -1,
  14116         -1,
  14117     },
  14118 #endif /* chips */
  14119 
  14120 #if defined(BCM_88375_B0)
  14121     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88375_B0r */
  14122         soc_block_list[22],
  14123         soc_genreg,
  14124         1,
  14125         0,
  14126         0,
  14127         SOC_REG_FLAG_INTERRUPT,
  14128         0,
  14129         6,
  14130         soc_OAMP_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  14131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14132         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  14133         -1,
  14134         -1,
  14135     },
  14136 #endif /* chips */
  14137 
  14138 #if defined(BCM_88470_A0)
  14139     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88470_A0r */
  14140         soc_block_list[22],
  14141         soc_genreg,
  14142         1,
  14143         0,
  14144         0,
  14145         SOC_REG_FLAG_INTERRUPT |
  14146                           SOC_REG_FLAG_SIGNAL,
  14147         0,
  14148         8,
  14149         soc_OAMP_INTERRUPT_REGISTER_BCM88470_A0r_fields,
  14150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14151         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14152         -1,
  14153         -1,
  14154     },
  14155 #endif /* chips */
  14156 
  14157 #if defined(BCM_88470_B0)
  14158     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88470_B0r */
  14159         soc_block_list[22],
  14160         soc_genreg,
  14161         1,
  14162         0,
  14163         0,
  14164         SOC_REG_FLAG_INTERRUPT |
  14165                           SOC_REG_FLAG_SIGNAL,
  14166         0,
  14167         8,
  14168         soc_OAMP_INTERRUPT_REGISTER_BCM88470_B0r_fields,
  14169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14170         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14171         -1,
  14172         -1,
  14173     },
  14174 #endif /* chips */
  14175 
  14176 #if defined(BCM_88650_B0)
  14177     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88650_B0r */
  14178         soc_block_list[22],
  14179         soc_genreg,
  14180         1,
  14181         0,
  14182         0,
  14183         SOC_REG_FLAG_INTERRUPT |
  14184                           SOC_REG_FLAG_SIGNAL,
  14185         0,
  14186         3,
  14187         soc_OAMP_INTERRUPT_REGISTER_BCM88650_B0r_fields,
  14188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14189         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  14190         -1,
  14191         -1,
  14192     },
  14193 #endif /* chips */
  14194 
  14195 #if defined(BCM_88660_A0)
  14196     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88660_A0r */
  14197         soc_block_list[22],
  14198         soc_genreg,
  14199         1,
  14200         0,
  14201         0,
  14202         SOC_REG_FLAG_INTERRUPT |
  14203                           SOC_REG_FLAG_SIGNAL,
  14204         0,
  14205         3,
  14206         soc_OAMP_INTERRUPT_REGISTER_BCM88660_A0r_fields,
  14207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14208         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  14209         -1,
  14210         -1,
  14211     },
  14212 #endif /* chips */
  14213 
  14214 #if defined(BCM_88675_A0)
  14215     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88675_A0r */
  14216         soc_block_list[22],
  14217         soc_genreg,
  14218         1,
  14219         0,
  14220         0,
  14221         SOC_REG_FLAG_INTERRUPT,
  14222         0,
  14223         6,
  14224         soc_OAMP_INTERRUPT_REGISTER_BCM88675_A0r_fields,
  14225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14226         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  14227         -1,
  14228         -1,
  14229     },
  14230 #endif /* chips */
  14231 
  14232 #if defined(BCM_88675_B0)
  14233     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88675_B0r */
  14234         soc_block_list[22],
  14235         soc_genreg,
  14236         1,
  14237         0,
  14238         0,
  14239         SOC_REG_FLAG_INTERRUPT,
  14240         0,
  14241         6,
  14242         soc_OAMP_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  14243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14244         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  14245         -1,
  14246         -1,
  14247     },
  14248 #endif /* chips */
  14249 
  14250 #if defined(BCM_88680_A0)
  14251     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88680_A0r */
  14252         soc_block_list[22],
  14253         soc_genreg,
  14254         1,
  14255         0,
  14256         0,
  14257         SOC_REG_FLAG_INTERRUPT,
  14258         0,
  14259         6,
  14260         soc_OAMP_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  14261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14262         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  14263         -1,
  14264         -1,
  14265     },
  14266 #endif /* chips */
  14267 
  14268 #if defined(BCM_88690_A0)
  14269     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88690_A0r */
  14270         soc_block_list[22],
  14271         soc_genreg,
  14272         1,
  14273         0,
  14274         0,
  14275         SOC_REG_FLAG_INTERRUPT |
  14276                           SOC_REG_FLAG_SIGNAL,
  14277         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  14278         10,
  14279         soc_OAMP_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  14280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14281         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14282         -1,
  14283         -1,
  14284     },
  14285 #endif /* chips */
  14286 
  14287 #if defined(BCM_88690_B0)
  14288     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_BCM88690_B0r */
  14289         soc_block_list[22],
  14290         soc_genreg,
  14291         1,
  14292         0,
  14293         0,
  14294         SOC_REG_FLAG_INTERRUPT |
  14295                           SOC_REG_FLAG_SIGNAL,
  14296         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  14297         10,
  14298         soc_OAMP_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  14299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14300         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14301         -1,
  14302         -1,
  14303     },
  14304 #endif /* chips */
  14305 
  14306 #if defined(BCM_88650_A0)
  14307     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TESTr */
  14308         soc_block_list[22],
  14309         soc_genreg,
  14310         1,
  14311         0,
  14312         0x18,
  14313         SOC_REG_FLAG_INTERRUPT |
  14314                           SOC_REG_FLAG_SIGNAL,
  14315         0,
  14316         1,
  14317         soc_OAMP_INTERRUPT_REGISTER_TESTr_fields,
  14318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14319         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14320         -1,
  14321         -1,
  14322     },
  14323 #endif /* chips */
  14324 
  14325 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  14326     defined(BCM_56270_A0)
  14327     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM56260_A0r */
  14328         soc_block_list[22],
  14329         soc_genreg,
  14330         1,
  14331         0,
  14332         0x2001800,
  14333         0,
  14334         0,
  14335         1,
  14336         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM56260_A0r_fields,
  14337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14338         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14339         -1,
  14340         -1,
  14341     },
  14342 #endif /* chips */
  14343 
  14344 #if defined(BCM_88270_A0)
  14345     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88270_A0r */
  14346         soc_block_list[22],
  14347         soc_genreg,
  14348         1,
  14349         0,
  14350         0x18,
  14351         0,
  14352         0,
  14353         1,
  14354         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88270_A0r_fields,
  14355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14356         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14357         -1,
  14358         -1,
  14359     },
  14360 #endif /* chips */
  14361 
  14362 #if defined(BCM_88375_A0)
  14363     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  14364         soc_block_list[22],
  14365         soc_genreg,
  14366         1,
  14367         0,
  14368         0x18,
  14369         0,
  14370         0,
  14371         1,
  14372         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  14373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14374         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14375         -1,
  14376         -1,
  14377     },
  14378 #endif /* chips */
  14379 
  14380 #if defined(BCM_88375_B0)
  14381     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  14382         soc_block_list[22],
  14383         soc_genreg,
  14384         1,
  14385         0,
  14386         0x18,
  14387         0,
  14388         0,
  14389         1,
  14390         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  14391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14392         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14393         -1,
  14394         -1,
  14395     },
  14396 #endif /* chips */
  14397 
  14398 #if defined(BCM_88470_A0)
  14399     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88470_A0r */
  14400         soc_block_list[22],
  14401         soc_genreg,
  14402         1,
  14403         0,
  14404         0x18,
  14405         0,
  14406         0,
  14407         1,
  14408         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88470_A0r_fields,
  14409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14410         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14411         -1,
  14412         -1,
  14413     },
  14414 #endif /* chips */
  14415 
  14416 #if defined(BCM_88470_B0)
  14417     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88470_B0r */
  14418         soc_block_list[22],
  14419         soc_genreg,
  14420         1,
  14421         0,
  14422         0x18,
  14423         0,
  14424         0,
  14425         1,
  14426         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88470_B0r_fields,
  14427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14428         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14429         -1,
  14430         -1,
  14431     },
  14432 #endif /* chips */
  14433 
  14434 #if defined(BCM_88650_B0)
  14435     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88650_B0r */
  14436         soc_block_list[22],
  14437         soc_genreg,
  14438         1,
  14439         0,
  14440         0x18,
  14441         SOC_REG_FLAG_INTERRUPT |
  14442                           SOC_REG_FLAG_SIGNAL,
  14443         0,
  14444         1,
  14445         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88650_B0r_fields,
  14446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14447         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14448         -1,
  14449         -1,
  14450     },
  14451 #endif /* chips */
  14452 
  14453 #if defined(BCM_88660_A0)
  14454     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88660_A0r */
  14455         soc_block_list[22],
  14456         soc_genreg,
  14457         1,
  14458         0,
  14459         0x18,
  14460         SOC_REG_FLAG_INTERRUPT |
  14461                           SOC_REG_FLAG_SIGNAL,
  14462         0,
  14463         1,
  14464         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88660_A0r_fields,
  14465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14466         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14467         -1,
  14468         -1,
  14469     },
  14470 #endif /* chips */
  14471 
  14472 #if defined(BCM_88675_A0)
  14473     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88675_A0r */
  14474         soc_block_list[22],
  14475         soc_genreg,
  14476         1,
  14477         0,
  14478         0x18,
  14479         0,
  14480         0,
  14481         1,
  14482         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88675_A0r_fields,
  14483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14484         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14485         -1,
  14486         -1,
  14487     },
  14488 #endif /* chips */
  14489 
  14490 #if defined(BCM_88675_B0)
  14491     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  14492         soc_block_list[22],
  14493         soc_genreg,
  14494         1,
  14495         0,
  14496         0x18,
  14497         0,
  14498         0,
  14499         1,
  14500         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  14501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14502         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14503         -1,
  14504         -1,
  14505     },
  14506 #endif /* chips */
  14507 
  14508 #if defined(BCM_88680_A0)
  14509     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  14510         soc_block_list[22],
  14511         soc_genreg,
  14512         1,
  14513         0,
  14514         0x18,
  14515         0,
  14516         0,
  14517         1,
  14518         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  14519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14520         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14521         -1,
  14522         -1,
  14523     },
  14524 #endif /* chips */
  14525 
  14526 #if defined(BCM_88690_A0)
  14527     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  14528         soc_block_list[22],
  14529         soc_genreg,
  14530         1,
  14531         0,
  14532         0x18,
  14533         0,
  14534         0,
  14535         1,
  14536         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  14537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14538         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14539         -1,
  14540         -1,
  14541     },
  14542 #endif /* chips */
  14543 
  14544 #if defined(BCM_88690_B0)
  14545     { /* SOC_REG_INT_OAMP_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  14546         soc_block_list[22],
  14547         soc_genreg,
  14548         1,
  14549         0,
  14550         0x18,
  14551         0,
  14552         0,
  14553         1,
  14554         soc_OAMP_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  14555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14556         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14557         -1,
  14558         -1,
  14559     },
  14560 #endif /* chips */
  14561 
  14562 #if defined(BCM_88650_A0)
  14563     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECTr */
  14564         soc_block_list[22],
  14565         soc_genreg,
  14566         1,
  14567         0,
  14568         0x195,
  14569         SOC_REG_FLAG_ABOVE_64_BITS |
  14570                           SOC_REG_FLAG_SIGNAL,
  14571         0,
  14572         16,
  14573         soc_OAMP_IPV4_SRC_ADDR_SELECTr_fields,
  14574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14576         -1,
  14577         -1,
  14578     },
  14579 #endif /* chips */
  14580 
  14581 #if defined(BCM_88270_A0)
  14582     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88270_A0r */
  14583         soc_block_list[22],
  14584         soc_genreg,
  14585         1,
  14586         0,
  14587         0x416,
  14588         SOC_REG_FLAG_ABOVE_64_BITS,
  14589         0,
  14590         16,
  14591         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88270_A0r_fields,
  14592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14594         -1,
  14595         -1,
  14596     },
  14597 #endif /* chips */
  14598 
  14599 #if defined(BCM_88375_A0)
  14600     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88375_A0r */
  14601         soc_block_list[22],
  14602         soc_genreg,
  14603         1,
  14604         0,
  14605         0x414,
  14606         SOC_REG_FLAG_ABOVE_64_BITS,
  14607         0,
  14608         16,
  14609         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88375_A0r_fields,
  14610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14612         -1,
  14613         -1,
  14614     },
  14615 #endif /* chips */
  14616 
  14617 #if defined(BCM_88375_B0)
  14618     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88375_B0r */
  14619         soc_block_list[22],
  14620         soc_genreg,
  14621         1,
  14622         0,
  14623         0x414,
  14624         SOC_REG_FLAG_ABOVE_64_BITS,
  14625         0,
  14626         16,
  14627         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88375_B0r_fields,
  14628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14630         -1,
  14631         -1,
  14632     },
  14633 #endif /* chips */
  14634 
  14635 #if defined(BCM_88470_A0)
  14636     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88470_A0r */
  14637         soc_block_list[22],
  14638         soc_genreg,
  14639         1,
  14640         0,
  14641         0x416,
  14642         SOC_REG_FLAG_ABOVE_64_BITS,
  14643         0,
  14644         16,
  14645         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88470_A0r_fields,
  14646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14647         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14648         -1,
  14649         -1,
  14650     },
  14651 #endif /* chips */
  14652 
  14653 #if defined(BCM_88470_B0)
  14654     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88470_B0r */
  14655         soc_block_list[22],
  14656         soc_genreg,
  14657         1,
  14658         0,
  14659         0x416,
  14660         SOC_REG_FLAG_ABOVE_64_BITS,
  14661         0,
  14662         16,
  14663         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88470_B0r_fields,
  14664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14665         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14666         -1,
  14667         -1,
  14668     },
  14669 #endif /* chips */
  14670 
  14671 #if defined(BCM_88650_B0)
  14672     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88650_B0r */
  14673         soc_block_list[22],
  14674         soc_genreg,
  14675         1,
  14676         0,
  14677         0x195,
  14678         SOC_REG_FLAG_ABOVE_64_BITS |
  14679                           SOC_REG_FLAG_SIGNAL,
  14680         0,
  14681         16,
  14682         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88650_B0r_fields,
  14683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14684         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14685         -1,
  14686         -1,
  14687     },
  14688 #endif /* chips */
  14689 
  14690 #if defined(BCM_88660_A0)
  14691     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88660_A0r */
  14692         soc_block_list[22],
  14693         soc_genreg,
  14694         1,
  14695         0,
  14696         0x413,
  14697         SOC_REG_FLAG_ABOVE_64_BITS |
  14698                           SOC_REG_FLAG_SIGNAL,
  14699         0,
  14700         16,
  14701         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88660_A0r_fields,
  14702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14703         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14704         -1,
  14705         -1,
  14706     },
  14707 #endif /* chips */
  14708 
  14709 #if defined(BCM_88675_A0)
  14710     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88675_A0r */
  14711         soc_block_list[22],
  14712         soc_genreg,
  14713         1,
  14714         0,
  14715         0x414,
  14716         SOC_REG_FLAG_ABOVE_64_BITS,
  14717         0,
  14718         16,
  14719         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88675_A0r_fields,
  14720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14722         -1,
  14723         -1,
  14724     },
  14725 #endif /* chips */
  14726 
  14727 #if defined(BCM_88675_B0)
  14728     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88675_B0r */
  14729         soc_block_list[22],
  14730         soc_genreg,
  14731         1,
  14732         0,
  14733         0x414,
  14734         SOC_REG_FLAG_ABOVE_64_BITS,
  14735         0,
  14736         16,
  14737         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88675_B0r_fields,
  14738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14739         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14740         -1,
  14741         -1,
  14742     },
  14743 #endif /* chips */
  14744 
  14745 #if defined(BCM_88680_A0)
  14746     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88680_A0r */
  14747         soc_block_list[22],
  14748         soc_genreg,
  14749         1,
  14750         0,
  14751         0x414,
  14752         SOC_REG_FLAG_ABOVE_64_BITS,
  14753         0,
  14754         16,
  14755         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88680_A0r_fields,
  14756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14758         -1,
  14759         -1,
  14760     },
  14761 #endif /* chips */
  14762 
  14763 #if defined(BCM_88690_A0)
  14764     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88690_A0r */
  14765         soc_block_list[22],
  14766         soc_genreg,
  14767         256,
  14768         0,
  14769         0x416,
  14770         SOC_REG_FLAG_ARRAY |
  14771                           SOC_REG_FLAG_REG_ARRAY,
  14772         0,
  14773         1,
  14774         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88690_A0r_fields,
  14775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14777         -1,
  14778         -1,
  14779     },
  14780 #endif /* chips */
  14781 
  14782 #if defined(BCM_88690_B0)
  14783     { /* SOC_REG_INT_OAMP_IPV4_SRC_ADDR_SELECT_BCM88690_B0r */
  14784         soc_block_list[22],
  14785         soc_genreg,
  14786         256,
  14787         0,
  14788         0x416,
  14789         SOC_REG_FLAG_ARRAY |
  14790                           SOC_REG_FLAG_REG_ARRAY,
  14791         0,
  14792         1,
  14793         soc_OAMP_IPV4_SRC_ADDR_SELECT_BCM88690_B0r_fields,
  14794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14796         -1,
  14797         -1,
  14798     },
  14799 #endif /* chips */
  14800 
  14801 #if defined(BCM_88650_A0)
  14802     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECTr */
  14803         soc_block_list[22],
  14804         soc_genreg,
  14805         1,
  14806         0,
  14807         0x1a5,
  14808         SOC_REG_FLAG_ABOVE_64_BITS |
  14809                           SOC_REG_FLAG_SIGNAL,
  14810         0,
  14811         16,
  14812         soc_OAMP_IPV4_TOS_TTL_SELECTr_fields,
  14813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14814         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14815         -1,
  14816         -1,
  14817     },
  14818 #endif /* chips */
  14819 
  14820 #if defined(BCM_88270_A0)
  14821     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88270_A0r */
  14822         soc_block_list[22],
  14823         soc_genreg,
  14824         1,
  14825         0,
  14826         0x426,
  14827         SOC_REG_FLAG_ABOVE_64_BITS,
  14828         0,
  14829         16,
  14830         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88270_A0r_fields,
  14831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14833         -1,
  14834         -1,
  14835     },
  14836 #endif /* chips */
  14837 
  14838 #if defined(BCM_88375_A0)
  14839     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88375_A0r */
  14840         soc_block_list[22],
  14841         soc_genreg,
  14842         1,
  14843         0,
  14844         0x424,
  14845         SOC_REG_FLAG_ABOVE_64_BITS,
  14846         0,
  14847         16,
  14848         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88375_A0r_fields,
  14849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14851         -1,
  14852         -1,
  14853     },
  14854 #endif /* chips */
  14855 
  14856 #if defined(BCM_88375_B0)
  14857     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88375_B0r */
  14858         soc_block_list[22],
  14859         soc_genreg,
  14860         1,
  14861         0,
  14862         0x424,
  14863         SOC_REG_FLAG_ABOVE_64_BITS,
  14864         0,
  14865         16,
  14866         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88375_B0r_fields,
  14867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14868         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14869         -1,
  14870         -1,
  14871     },
  14872 #endif /* chips */
  14873 
  14874 #if defined(BCM_88470_A0)
  14875     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88470_A0r */
  14876         soc_block_list[22],
  14877         soc_genreg,
  14878         1,
  14879         0,
  14880         0x426,
  14881         SOC_REG_FLAG_ABOVE_64_BITS,
  14882         0,
  14883         16,
  14884         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88470_A0r_fields,
  14885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14886         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14887         -1,
  14888         -1,
  14889     },
  14890 #endif /* chips */
  14891 
  14892 #if defined(BCM_88470_B0)
  14893     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88470_B0r */
  14894         soc_block_list[22],
  14895         soc_genreg,
  14896         1,
  14897         0,
  14898         0x426,
  14899         SOC_REG_FLAG_ABOVE_64_BITS,
  14900         0,
  14901         16,
  14902         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88470_B0r_fields,
  14903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14904         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14905         -1,
  14906         -1,
  14907     },
  14908 #endif /* chips */
  14909 
  14910 #if defined(BCM_88650_B0)
  14911     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88650_B0r */
  14912         soc_block_list[22],
  14913         soc_genreg,
  14914         1,
  14915         0,
  14916         0x1a5,
  14917         SOC_REG_FLAG_ABOVE_64_BITS |
  14918                           SOC_REG_FLAG_SIGNAL,
  14919         0,
  14920         16,
  14921         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88650_B0r_fields,
  14922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14923         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14924         -1,
  14925         -1,
  14926     },
  14927 #endif /* chips */
  14928 
  14929 #if defined(BCM_88660_A0)
  14930     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88660_A0r */
  14931         soc_block_list[22],
  14932         soc_genreg,
  14933         1,
  14934         0,
  14935         0x423,
  14936         SOC_REG_FLAG_ABOVE_64_BITS |
  14937                           SOC_REG_FLAG_SIGNAL,
  14938         0,
  14939         16,
  14940         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88660_A0r_fields,
  14941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14942         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14943         -1,
  14944         -1,
  14945     },
  14946 #endif /* chips */
  14947 
  14948 #if defined(BCM_88675_A0)
  14949     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88675_A0r */
  14950         soc_block_list[22],
  14951         soc_genreg,
  14952         1,
  14953         0,
  14954         0x424,
  14955         SOC_REG_FLAG_ABOVE_64_BITS,
  14956         0,
  14957         16,
  14958         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88675_A0r_fields,
  14959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14960         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14961         -1,
  14962         -1,
  14963     },
  14964 #endif /* chips */
  14965 
  14966 #if defined(BCM_88675_B0)
  14967     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88675_B0r */
  14968         soc_block_list[22],
  14969         soc_genreg,
  14970         1,
  14971         0,
  14972         0x424,
  14973         SOC_REG_FLAG_ABOVE_64_BITS,
  14974         0,
  14975         16,
  14976         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88675_B0r_fields,
  14977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14978         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14979         -1,
  14980         -1,
  14981     },
  14982 #endif /* chips */
  14983 
  14984 #if defined(BCM_88680_A0)
  14985     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88680_A0r */
  14986         soc_block_list[22],
  14987         soc_genreg,
  14988         1,
  14989         0,
  14990         0x424,
  14991         SOC_REG_FLAG_ABOVE_64_BITS,
  14992         0,
  14993         16,
  14994         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88680_A0r_fields,
  14995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14996         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14997         -1,
  14998         -1,
  14999     },
  15000 #endif /* chips */
  15001 
  15002 #if defined(BCM_88690_A0)
  15003     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88690_A0r */
  15004         soc_block_list[22],
  15005         soc_genreg,
  15006         1,
  15007         0,
  15008         0x516,
  15009         SOC_REG_FLAG_ABOVE_64_BITS,
  15010         0,
  15011         16,
  15012         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88690_A0r_fields,
  15013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15014         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15015         -1,
  15016         -1,
  15017     },
  15018 #endif /* chips */
  15019 
  15020 #if defined(BCM_88690_B0)
  15021     { /* SOC_REG_INT_OAMP_IPV4_TOS_TTL_SELECT_BCM88690_B0r */
  15022         soc_block_list[22],
  15023         soc_genreg,
  15024         1,
  15025         0,
  15026         0x516,
  15027         SOC_REG_FLAG_ABOVE_64_BITS,
  15028         0,
  15029         16,
  15030         soc_OAMP_IPV4_TOS_TTL_SELECT_BCM88690_B0r_fields,
  15031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15032         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15033         -1,
  15034         -1,
  15035     },
  15036 #endif /* chips */
  15037 
  15038 #if defined(BCM_88660_A0)
  15039     { /* SOC_REG_INT_OAMP_LMM_DA_OUIr */
  15040         soc_block_list[22],
  15041         soc_genreg,
  15042         1,
  15043         0,
  15044         0x43a,
  15045         SOC_REG_FLAG_ABOVE_64_BITS |
  15046                           SOC_REG_FLAG_SIGNAL,
  15047         0,
  15048         8,
  15049         soc_OAMP_LMM_DA_OUIr_fields,
  15050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15052         -1,
  15053         -1,
  15054     },
  15055 #endif /* chips */
  15056 
  15057 #if defined(BCM_88270_A0)
  15058     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88270_A0r */
  15059         soc_block_list[22],
  15060         soc_genreg,
  15061         1,
  15062         0,
  15063         0x442,
  15064         SOC_REG_FLAG_ABOVE_64_BITS,
  15065         0,
  15066         8,
  15067         soc_OAMP_LMM_DA_OUI_BCM88270_A0r_fields,
  15068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15070         -1,
  15071         -1,
  15072     },
  15073 #endif /* chips */
  15074 
  15075 #if defined(BCM_88375_A0)
  15076     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88375_A0r */
  15077         soc_block_list[22],
  15078         soc_genreg,
  15079         1,
  15080         0,
  15081         0x43f,
  15082         SOC_REG_FLAG_ABOVE_64_BITS,
  15083         0,
  15084         8,
  15085         soc_OAMP_LMM_DA_OUI_BCM88375_A0r_fields,
  15086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15088         -1,
  15089         -1,
  15090     },
  15091 #endif /* chips */
  15092 
  15093 #if defined(BCM_88375_B0)
  15094     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88375_B0r */
  15095         soc_block_list[22],
  15096         soc_genreg,
  15097         1,
  15098         0,
  15099         0x43f,
  15100         SOC_REG_FLAG_ABOVE_64_BITS,
  15101         0,
  15102         8,
  15103         soc_OAMP_LMM_DA_OUI_BCM88375_B0r_fields,
  15104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15105         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15106         -1,
  15107         -1,
  15108     },
  15109 #endif /* chips */
  15110 
  15111 #if defined(BCM_88470_A0)
  15112     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88470_A0r */
  15113         soc_block_list[22],
  15114         soc_genreg,
  15115         1,
  15116         0,
  15117         0x442,
  15118         SOC_REG_FLAG_ABOVE_64_BITS,
  15119         0,
  15120         8,
  15121         soc_OAMP_LMM_DA_OUI_BCM88470_A0r_fields,
  15122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15124         -1,
  15125         -1,
  15126     },
  15127 #endif /* chips */
  15128 
  15129 #if defined(BCM_88470_B0)
  15130     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88470_B0r */
  15131         soc_block_list[22],
  15132         soc_genreg,
  15133         1,
  15134         0,
  15135         0x442,
  15136         SOC_REG_FLAG_ABOVE_64_BITS,
  15137         0,
  15138         8,
  15139         soc_OAMP_LMM_DA_OUI_BCM88470_B0r_fields,
  15140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15142         -1,
  15143         -1,
  15144     },
  15145 #endif /* chips */
  15146 
  15147 #if defined(BCM_88675_A0)
  15148     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88675_A0r */
  15149         soc_block_list[22],
  15150         soc_genreg,
  15151         1,
  15152         0,
  15153         0x43f,
  15154         SOC_REG_FLAG_ABOVE_64_BITS,
  15155         0,
  15156         8,
  15157         soc_OAMP_LMM_DA_OUI_BCM88675_A0r_fields,
  15158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15160         -1,
  15161         -1,
  15162     },
  15163 #endif /* chips */
  15164 
  15165 #if defined(BCM_88675_B0)
  15166     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88675_B0r */
  15167         soc_block_list[22],
  15168         soc_genreg,
  15169         1,
  15170         0,
  15171         0x43f,
  15172         SOC_REG_FLAG_ABOVE_64_BITS,
  15173         0,
  15174         8,
  15175         soc_OAMP_LMM_DA_OUI_BCM88675_B0r_fields,
  15176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15178         -1,
  15179         -1,
  15180     },
  15181 #endif /* chips */
  15182 
  15183 #if defined(BCM_88680_A0)
  15184     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88680_A0r */
  15185         soc_block_list[22],
  15186         soc_genreg,
  15187         1,
  15188         0,
  15189         0x43f,
  15190         SOC_REG_FLAG_ABOVE_64_BITS,
  15191         0,
  15192         8,
  15193         soc_OAMP_LMM_DA_OUI_BCM88680_A0r_fields,
  15194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15195         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15196         -1,
  15197         -1,
  15198     },
  15199 #endif /* chips */
  15200 
  15201 #if defined(BCM_88690_A0)
  15202     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88690_A0r */
  15203         soc_block_list[22],
  15204         soc_genreg,
  15205         1,
  15206         0,
  15207         0x532,
  15208         SOC_REG_FLAG_ABOVE_64_BITS,
  15209         0,
  15210         8,
  15211         soc_OAMP_LMM_DA_OUI_BCM88690_A0r_fields,
  15212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15213         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15214         -1,
  15215         -1,
  15216     },
  15217 #endif /* chips */
  15218 
  15219 #if defined(BCM_88690_B0)
  15220     { /* SOC_REG_INT_OAMP_LMM_DA_OUI_BCM88690_B0r */
  15221         soc_block_list[22],
  15222         soc_genreg,
  15223         1,
  15224         0,
  15225         0x532,
  15226         SOC_REG_FLAG_ABOVE_64_BITS,
  15227         0,
  15228         8,
  15229         soc_OAMP_LMM_DA_OUI_BCM88690_B0r_fields,
  15230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15232         -1,
  15233         -1,
  15234     },
  15235 #endif /* chips */
  15236 
  15237 #if defined(BCM_88690_A0)
  15238     { /* SOC_REG_INT_OAMP_MAP_OAM_IDr */
  15239         soc_block_list[22],
  15240         soc_genreg,
  15241         1,
  15242         0,
  15243         0xb17,
  15244         SOC_REG_FLAG_ABOVE_64_BITS,
  15245         0,
  15246         1,
  15247         soc_OAMP_MAP_OAM_IDr_fields,
  15248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15250         -1,
  15251         -1,
  15252     },
  15253 #endif /* chips */
  15254 
  15255 #if defined(BCM_88690_B0)
  15256     { /* SOC_REG_INT_OAMP_MAP_OAM_ID_BCM88690_B0r */
  15257         soc_block_list[22],
  15258         soc_genreg,
  15259         1,
  15260         0,
  15261         0xb18,
  15262         SOC_REG_FLAG_ABOVE_64_BITS,
  15263         0,
  15264         1,
  15265         soc_OAMP_MAP_OAM_ID_BCM88690_B0r_fields,
  15266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15267         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15268         -1,
  15269         -1,
  15270     },
  15271 #endif /* chips */
  15272 
  15273 #if defined(BCM_88690_A0)
  15274     { /* SOC_REG_INT_OAMP_MDB_APP_DBr */
  15275         soc_block_list[22],
  15276         soc_genreg,
  15277         1,
  15278         0,
  15279         0xb28,
  15280         0,
  15281         0,
  15282         4,
  15283         soc_OAMP_MDB_APP_DBr_fields,
  15284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15285         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  15286         -1,
  15287         -1,
  15288     },
  15289 #endif /* chips */
  15290 
  15291 #if defined(BCM_88690_B0)
  15292     { /* SOC_REG_INT_OAMP_MDB_APP_DB_BCM88690_B0r */
  15293         soc_block_list[22],
  15294         soc_genreg,
  15295         1,
  15296         0,
  15297         0xb29,
  15298         0,
  15299         0,
  15300         4,
  15301         soc_OAMP_MDB_APP_DB_BCM88690_B0r_fields,
  15302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15303         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  15304         -1,
  15305         -1,
  15306     },
  15307 #endif /* chips */
  15308 
  15309 #if defined(BCM_88690_B0)
  15310     { /* SOC_REG_INT_OAMP_MEMORY_HAZARD_PROTECTION_ENr */
  15311         soc_block_list[22],
  15312         soc_genreg,
  15313         1,
  15314         0,
  15315         0xb45,
  15316         0,
  15317         0,
  15318         3,
  15319         soc_OAMP_MEMORY_HAZARD_PROTECTION_ENr_fields,
  15320         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15321         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  15322         -1,
  15323         -1,
  15324     },
  15325 #endif /* chips */
  15326 
  15327 #if defined(BCM_88690_A0)
  15328     { /* SOC_REG_INT_OAMP_MEP_DB_FULL_ENTRY_THRESHOLDr */
  15329         soc_block_list[22],
  15330         soc_genreg,
  15331         1,
  15332         0,
  15333         0xb29,
  15334         0,
  15335         0,
  15336         1,
  15337         soc_OAMP_MEP_DB_FULL_ENTRY_THRESHOLDr_fields,
  15338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15339         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  15340         -1,
  15341         -1,
  15342     },
  15343 #endif /* chips */
  15344 
  15345 #if defined(BCM_88690_B0)
  15346     { /* SOC_REG_INT_OAMP_MEP_DB_FULL_ENTRY_THRESHOLD_BCM88690_B0r */
  15347         soc_block_list[22],
  15348         soc_genreg,
  15349         1,
  15350         0,
  15351         0xb2a,
  15352         0,
  15353         0,
  15354         1,
  15355         soc_OAMP_MEP_DB_FULL_ENTRY_THRESHOLD_BCM88690_B0r_fields,
  15356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15357         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  15358         -1,
  15359         -1,
  15360     },
  15361 #endif /* chips */
  15362 
  15363 #if defined(BCM_88675_A0)
  15364     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZEr */
  15365         soc_block_list[22],
  15366         soc_genreg,
  15367         1,
  15368         0,
  15369         0x455,
  15370         0,
  15371         0,
  15372         1,
  15373         soc_OAMP_MIN_NET_PKT_SIZEr_fields,
  15374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15375         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15376         -1,
  15377         -1,
  15378     },
  15379 #endif /* chips */
  15380 
  15381 #if defined(BCM_88270_A0)
  15382     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZE_BCM88270_A0r */
  15383         soc_block_list[22],
  15384         soc_genreg,
  15385         1,
  15386         0,
  15387         0x456,
  15388         0,
  15389         0,
  15390         1,
  15391         soc_OAMP_MIN_NET_PKT_SIZE_BCM88270_A0r_fields,
  15392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15393         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15394         -1,
  15395         -1,
  15396     },
  15397 #endif /* chips */
  15398 
  15399 #if defined(BCM_88375_A0)
  15400     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZE_BCM88375_A0r */
  15401         soc_block_list[22],
  15402         soc_genreg,
  15403         1,
  15404         0,
  15405         0x455,
  15406         0,
  15407         0,
  15408         1,
  15409         soc_OAMP_MIN_NET_PKT_SIZE_BCM88375_A0r_fields,
  15410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15411         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15412         -1,
  15413         -1,
  15414     },
  15415 #endif /* chips */
  15416 
  15417 #if defined(BCM_88375_B0)
  15418     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZE_BCM88375_B0r */
  15419         soc_block_list[22],
  15420         soc_genreg,
  15421         1,
  15422         0,
  15423         0x455,
  15424         0,
  15425         0,
  15426         1,
  15427         soc_OAMP_MIN_NET_PKT_SIZE_BCM88375_B0r_fields,
  15428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15429         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15430         -1,
  15431         -1,
  15432     },
  15433 #endif /* chips */
  15434 
  15435 #if defined(BCM_88470_A0)
  15436     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZE_BCM88470_A0r */
  15437         soc_block_list[22],
  15438         soc_genreg,
  15439         1,
  15440         0,
  15441         0x456,
  15442         0,
  15443         0,
  15444         1,
  15445         soc_OAMP_MIN_NET_PKT_SIZE_BCM88470_A0r_fields,
  15446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15447         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15448         -1,
  15449         -1,
  15450     },
  15451 #endif /* chips */
  15452 
  15453 #if defined(BCM_88470_B0)
  15454     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZE_BCM88470_B0r */
  15455         soc_block_list[22],
  15456         soc_genreg,
  15457         1,
  15458         0,
  15459         0x456,
  15460         0,
  15461         0,
  15462         1,
  15463         soc_OAMP_MIN_NET_PKT_SIZE_BCM88470_B0r_fields,
  15464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15465         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15466         -1,
  15467         -1,
  15468     },
  15469 #endif /* chips */
  15470 
  15471 #if defined(BCM_88675_B0)
  15472     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZE_BCM88675_B0r */
  15473         soc_block_list[22],
  15474         soc_genreg,
  15475         1,
  15476         0,
  15477         0x455,
  15478         0,
  15479         0,
  15480         1,
  15481         soc_OAMP_MIN_NET_PKT_SIZE_BCM88675_B0r_fields,
  15482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15483         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15484         -1,
  15485         -1,
  15486     },
  15487 #endif /* chips */
  15488 
  15489 #if defined(BCM_88680_A0)
  15490     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZE_BCM88680_A0r */
  15491         soc_block_list[22],
  15492         soc_genreg,
  15493         1,
  15494         0,
  15495         0x455,
  15496         0,
  15497         0,
  15498         1,
  15499         soc_OAMP_MIN_NET_PKT_SIZE_BCM88680_A0r_fields,
  15500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15501         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15502         -1,
  15503         -1,
  15504     },
  15505 #endif /* chips */
  15506 
  15507 #if defined(BCM_88690_A0)
  15508     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZE_BCM88690_A0r */
  15509         soc_block_list[22],
  15510         soc_genreg,
  15511         1,
  15512         0,
  15513         0x547,
  15514         0,
  15515         0,
  15516         1,
  15517         soc_OAMP_MIN_NET_PKT_SIZE_BCM88690_A0r_fields,
  15518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15519         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15520         -1,
  15521         -1,
  15522     },
  15523 #endif /* chips */
  15524 
  15525 #if defined(BCM_88690_B0)
  15526     { /* SOC_REG_INT_OAMP_MIN_NET_PKT_SIZE_BCM88690_B0r */
  15527         soc_block_list[22],
  15528         soc_genreg,
  15529         1,
  15530         0,
  15531         0x547,
  15532         0,
  15533         0,
  15534         1,
  15535         soc_OAMP_MIN_NET_PKT_SIZE_BCM88690_B0r_fields,
  15536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15537         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15538         -1,
  15539         -1,
  15540     },
  15541 #endif /* chips */
  15542 
  15543 #if defined(BCM_88650_A0)
  15544     { /* SOC_REG_INT_OAMP_MODE_REGISTERr */
  15545         soc_block_list[22],
  15546         soc_genreg,
  15547         1,
  15548         0,
  15549         0x100,
  15550         SOC_REG_FLAG_SIGNAL,
  15551         0,
  15552         4,
  15553         soc_OAMP_MODE_REGISTERr_fields,
  15554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15555         SOC_RESET_MASK_DEC(0x0000003c, 0x00000000)
  15556         -1,
  15557         -1,
  15558     },
  15559 #endif /* chips */
  15560 
  15561 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  15562     defined(BCM_56270_A0)
  15563     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM56260_A0r */
  15564         soc_block_list[22],
  15565         soc_genreg,
  15566         1,
  15567         0,
  15568         0x2010000,
  15569         0,
  15570         0,
  15571         1,
  15572         soc_OAMP_MODE_REGISTER_BCM56260_A0r_fields,
  15573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15574         SOC_RESET_MASK_DEC(0x00000200, 0x00000000)
  15575         -1,
  15576         -1,
  15577     },
  15578 #endif /* chips */
  15579 
  15580 #if defined(BCM_88270_A0)
  15581     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88270_A0r */
  15582         soc_block_list[22],
  15583         soc_genreg,
  15584         1,
  15585         0,
  15586         0x100,
  15587         0,
  15588         0,
  15589         7,
  15590         soc_OAMP_MODE_REGISTER_BCM88270_A0r_fields,
  15591         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  15592         SOC_RESET_MASK_DEC(0x000003fc, 0x00000000)
  15593         -1,
  15594         -1,
  15595     },
  15596 #endif /* chips */
  15597 
  15598 #if defined(BCM_88375_A0)
  15599     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88375_A0r */
  15600         soc_block_list[22],
  15601         soc_genreg,
  15602         1,
  15603         0,
  15604         0x100,
  15605         0,
  15606         0,
  15607         7,
  15608         soc_OAMP_MODE_REGISTER_BCM88375_A0r_fields,
  15609         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  15610         SOC_RESET_MASK_DEC(0x000003fc, 0x00000000)
  15611         -1,
  15612         -1,
  15613     },
  15614 #endif /* chips */
  15615 
  15616 #if defined(BCM_88375_B0)
  15617     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88375_B0r */
  15618         soc_block_list[22],
  15619         soc_genreg,
  15620         1,
  15621         0,
  15622         0x100,
  15623         0,
  15624         0,
  15625         7,
  15626         soc_OAMP_MODE_REGISTER_BCM88375_B0r_fields,
  15627         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  15628         SOC_RESET_MASK_DEC(0x000003fc, 0x00000000)
  15629         -1,
  15630         -1,
  15631     },
  15632 #endif /* chips */
  15633 
  15634 #if defined(BCM_88470_A0)
  15635     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88470_A0r */
  15636         soc_block_list[22],
  15637         soc_genreg,
  15638         1,
  15639         0,
  15640         0x100,
  15641         0,
  15642         0,
  15643         7,
  15644         soc_OAMP_MODE_REGISTER_BCM88470_A0r_fields,
  15645         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  15646         SOC_RESET_MASK_DEC(0x000003fc, 0x00000000)
  15647         -1,
  15648         -1,
  15649     },
  15650 #endif /* chips */
  15651 
  15652 #if defined(BCM_88470_B0)
  15653     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88470_B0r */
  15654         soc_block_list[22],
  15655         soc_genreg,
  15656         1,
  15657         0,
  15658         0x100,
  15659         0,
  15660         0,
  15661         7,
  15662         soc_OAMP_MODE_REGISTER_BCM88470_B0r_fields,
  15663         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  15664         SOC_RESET_MASK_DEC(0x000003fc, 0x00000000)
  15665         -1,
  15666         -1,
  15667     },
  15668 #endif /* chips */
  15669 
  15670 #if defined(BCM_88650_B0)
  15671     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88650_B0r */
  15672         soc_block_list[22],
  15673         soc_genreg,
  15674         1,
  15675         0,
  15676         0x100,
  15677         SOC_REG_FLAG_SIGNAL,
  15678         0,
  15679         4,
  15680         soc_OAMP_MODE_REGISTER_BCM88650_B0r_fields,
  15681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15682         SOC_RESET_MASK_DEC(0x0000003c, 0x00000000)
  15683         -1,
  15684         -1,
  15685     },
  15686 #endif /* chips */
  15687 
  15688 #if defined(BCM_88660_A0)
  15689     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88660_A0r */
  15690         soc_block_list[22],
  15691         soc_genreg,
  15692         1,
  15693         0,
  15694         0x100,
  15695         SOC_REG_FLAG_SIGNAL,
  15696         0,
  15697         5,
  15698         soc_OAMP_MODE_REGISTER_BCM88660_A0r_fields,
  15699         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  15700         SOC_RESET_MASK_DEC(0x0000007c, 0x00000000)
  15701         -1,
  15702         -1,
  15703     },
  15704 #endif /* chips */
  15705 
  15706 #if defined(BCM_88675_A0)
  15707     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88675_A0r */
  15708         soc_block_list[22],
  15709         soc_genreg,
  15710         1,
  15711         0,
  15712         0x100,
  15713         0,
  15714         0,
  15715         7,
  15716         soc_OAMP_MODE_REGISTER_BCM88675_A0r_fields,
  15717         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  15718         SOC_RESET_MASK_DEC(0x000003fc, 0x00000000)
  15719         -1,
  15720         -1,
  15721     },
  15722 #endif /* chips */
  15723 
  15724 #if defined(BCM_88675_B0)
  15725     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88675_B0r */
  15726         soc_block_list[22],
  15727         soc_genreg,
  15728         1,
  15729         0,
  15730         0x100,
  15731         0,
  15732         0,
  15733         7,
  15734         soc_OAMP_MODE_REGISTER_BCM88675_B0r_fields,
  15735         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  15736         SOC_RESET_MASK_DEC(0x000003fc, 0x00000000)
  15737         -1,
  15738         -1,
  15739     },
  15740 #endif /* chips */
  15741 
  15742 #if defined(BCM_88680_A0)
  15743     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88680_A0r */
  15744         soc_block_list[22],
  15745         soc_genreg,
  15746         1,
  15747         0,
  15748         0x100,
  15749         0,
  15750         0,
  15751         7,
  15752         soc_OAMP_MODE_REGISTER_BCM88680_A0r_fields,
  15753         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  15754         SOC_RESET_MASK_DEC(0x000003fc, 0x00000000)
  15755         -1,
  15756         -1,
  15757     },
  15758 #endif /* chips */
  15759 
  15760 #if defined(BCM_88690_A0)
  15761     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88690_A0r */
  15762         soc_block_list[22],
  15763         soc_genreg,
  15764         1,
  15765         0,
  15766         0x100,
  15767         0,
  15768         0,
  15769         9,
  15770         soc_OAMP_MODE_REGISTER_BCM88690_A0r_fields,
  15771         SOC_RESET_VAL_DEC(0x00000108, 0x00000000)
  15772         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  15773         -1,
  15774         -1,
  15775     },
  15776 #endif /* chips */
  15777 
  15778 #if defined(BCM_88690_B0)
  15779     { /* SOC_REG_INT_OAMP_MODE_REGISTER_BCM88690_B0r */
  15780         soc_block_list[22],
  15781         soc_genreg,
  15782         1,
  15783         0,
  15784         0x100,
  15785         0,
  15786         0,
  15787         10,
  15788         soc_OAMP_MODE_REGISTER_BCM88690_B0r_fields,
  15789         SOC_RESET_VAL_DEC(0x00000108, 0x00000000)
  15790         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  15791         -1,
  15792         -1,
  15793     },
  15794 #endif /* chips */
  15795 
  15796 #if defined(BCM_88650_A0)
  15797     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILEr */
  15798         soc_block_list[22],
  15799         soc_genreg,
  15800         1,
  15801         0,
  15802         0x189,
  15803         SOC_REG_FLAG_ABOVE_64_BITS |
  15804                           SOC_REG_FLAG_SIGNAL,
  15805         0,
  15806         16,
  15807         soc_OAMP_MPLS_PWE_PROFILEr_fields,
  15808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15810         -1,
  15811         -1,
  15812     },
  15813 #endif /* chips */
  15814 
  15815 #if defined(BCM_88270_A0)
  15816     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88270_A0r */
  15817         soc_block_list[22],
  15818         soc_genreg,
  15819         1,
  15820         0,
  15821         0x40a,
  15822         SOC_REG_FLAG_ABOVE_64_BITS,
  15823         0,
  15824         16,
  15825         soc_OAMP_MPLS_PWE_PROFILE_BCM88270_A0r_fields,
  15826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15828         -1,
  15829         -1,
  15830     },
  15831 #endif /* chips */
  15832 
  15833 #if defined(BCM_88375_A0)
  15834     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88375_A0r */
  15835         soc_block_list[22],
  15836         soc_genreg,
  15837         1,
  15838         0,
  15839         0x408,
  15840         SOC_REG_FLAG_ABOVE_64_BITS,
  15841         0,
  15842         16,
  15843         soc_OAMP_MPLS_PWE_PROFILE_BCM88375_A0r_fields,
  15844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15845         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15846         -1,
  15847         -1,
  15848     },
  15849 #endif /* chips */
  15850 
  15851 #if defined(BCM_88375_B0)
  15852     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88375_B0r */
  15853         soc_block_list[22],
  15854         soc_genreg,
  15855         1,
  15856         0,
  15857         0x408,
  15858         SOC_REG_FLAG_ABOVE_64_BITS,
  15859         0,
  15860         16,
  15861         soc_OAMP_MPLS_PWE_PROFILE_BCM88375_B0r_fields,
  15862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15863         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15864         -1,
  15865         -1,
  15866     },
  15867 #endif /* chips */
  15868 
  15869 #if defined(BCM_88470_A0)
  15870     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88470_A0r */
  15871         soc_block_list[22],
  15872         soc_genreg,
  15873         1,
  15874         0,
  15875         0x40a,
  15876         SOC_REG_FLAG_ABOVE_64_BITS,
  15877         0,
  15878         16,
  15879         soc_OAMP_MPLS_PWE_PROFILE_BCM88470_A0r_fields,
  15880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15882         -1,
  15883         -1,
  15884     },
  15885 #endif /* chips */
  15886 
  15887 #if defined(BCM_88470_B0)
  15888     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88470_B0r */
  15889         soc_block_list[22],
  15890         soc_genreg,
  15891         1,
  15892         0,
  15893         0x40a,
  15894         SOC_REG_FLAG_ABOVE_64_BITS,
  15895         0,
  15896         16,
  15897         soc_OAMP_MPLS_PWE_PROFILE_BCM88470_B0r_fields,
  15898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15899         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15900         -1,
  15901         -1,
  15902     },
  15903 #endif /* chips */
  15904 
  15905 #if defined(BCM_88650_B0)
  15906     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88650_B0r */
  15907         soc_block_list[22],
  15908         soc_genreg,
  15909         1,
  15910         0,
  15911         0x189,
  15912         SOC_REG_FLAG_ABOVE_64_BITS |
  15913                           SOC_REG_FLAG_SIGNAL,
  15914         0,
  15915         16,
  15916         soc_OAMP_MPLS_PWE_PROFILE_BCM88650_B0r_fields,
  15917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15919         -1,
  15920         -1,
  15921     },
  15922 #endif /* chips */
  15923 
  15924 #if defined(BCM_88660_A0)
  15925     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88660_A0r */
  15926         soc_block_list[22],
  15927         soc_genreg,
  15928         1,
  15929         0,
  15930         0x407,
  15931         SOC_REG_FLAG_ABOVE_64_BITS |
  15932                           SOC_REG_FLAG_SIGNAL,
  15933         0,
  15934         16,
  15935         soc_OAMP_MPLS_PWE_PROFILE_BCM88660_A0r_fields,
  15936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15938         -1,
  15939         -1,
  15940     },
  15941 #endif /* chips */
  15942 
  15943 #if defined(BCM_88675_A0)
  15944     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88675_A0r */
  15945         soc_block_list[22],
  15946         soc_genreg,
  15947         1,
  15948         0,
  15949         0x408,
  15950         SOC_REG_FLAG_ABOVE_64_BITS,
  15951         0,
  15952         16,
  15953         soc_OAMP_MPLS_PWE_PROFILE_BCM88675_A0r_fields,
  15954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15956         -1,
  15957         -1,
  15958     },
  15959 #endif /* chips */
  15960 
  15961 #if defined(BCM_88675_B0)
  15962     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88675_B0r */
  15963         soc_block_list[22],
  15964         soc_genreg,
  15965         1,
  15966         0,
  15967         0x408,
  15968         SOC_REG_FLAG_ABOVE_64_BITS,
  15969         0,
  15970         16,
  15971         soc_OAMP_MPLS_PWE_PROFILE_BCM88675_B0r_fields,
  15972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15973         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15974         -1,
  15975         -1,
  15976     },
  15977 #endif /* chips */
  15978 
  15979 #if defined(BCM_88680_A0)
  15980     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88680_A0r */
  15981         soc_block_list[22],
  15982         soc_genreg,
  15983         1,
  15984         0,
  15985         0x408,
  15986         SOC_REG_FLAG_ABOVE_64_BITS,
  15987         0,
  15988         16,
  15989         soc_OAMP_MPLS_PWE_PROFILE_BCM88680_A0r_fields,
  15990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15992         -1,
  15993         -1,
  15994     },
  15995 #endif /* chips */
  15996 
  15997 #if defined(BCM_88690_A0)
  15998     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88690_A0r */
  15999         soc_block_list[22],
  16000         soc_genreg,
  16001         1,
  16002         0,
  16003         0x40a,
  16004         SOC_REG_FLAG_ABOVE_64_BITS,
  16005         0,
  16006         16,
  16007         soc_OAMP_MPLS_PWE_PROFILE_BCM88690_A0r_fields,
  16008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16010         -1,
  16011         -1,
  16012     },
  16013 #endif /* chips */
  16014 
  16015 #if defined(BCM_88690_B0)
  16016     { /* SOC_REG_INT_OAMP_MPLS_PWE_PROFILE_BCM88690_B0r */
  16017         soc_block_list[22],
  16018         soc_genreg,
  16019         1,
  16020         0,
  16021         0x40a,
  16022         SOC_REG_FLAG_ABOVE_64_BITS,
  16023         0,
  16024         16,
  16025         soc_OAMP_MPLS_PWE_PROFILE_BCM88690_B0r_fields,
  16026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16027         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16028         -1,
  16029         -1,
  16030     },
  16031 #endif /* chips */
  16032 
  16033 #if defined(BCM_88690_A0)
  16034     { /* SOC_REG_INT_OAMP_MY_DISC_MISS_INFOr */
  16035         soc_block_list[22],
  16036         soc_genreg,
  16037         1,
  16038         0,
  16039         0xb0d,
  16040         SOC_REG_FLAG_64_BITS |
  16041                           SOC_REG_FLAG_RO |
  16042                           SOC_REG_FLAG_SIGNAL,
  16043         SOC_REG_FLAG_INIT_ON_READ,
  16044         2,
  16045         soc_OAMP_MY_DISC_MISS_INFOr_fields,
  16046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16047         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  16048         -1,
  16049         -1,
  16050     },
  16051 #endif /* chips */
  16052 
  16053 #if defined(BCM_88690_B0)
  16054     { /* SOC_REG_INT_OAMP_MY_DISC_MISS_INFO_BCM88690_B0r */
  16055         soc_block_list[22],
  16056         soc_genreg,
  16057         1,
  16058         0,
  16059         0xb0d,
  16060         SOC_REG_FLAG_64_BITS |
  16061                           SOC_REG_FLAG_RO |
  16062                           SOC_REG_FLAG_SIGNAL,
  16063         SOC_REG_FLAG_INIT_ON_READ,
  16064         2,
  16065         soc_OAMP_MY_DISC_MISS_INFO_BCM88690_B0r_fields,
  16066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16067         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  16068         -1,
  16069         -1,
  16070     },
  16071 #endif /* chips */
  16072 
  16073 #if defined(BCM_88660_A0)
  16074     { /* SOC_REG_INT_OAMP_NIBBLE_SELECT_FOR_PEr */
  16075         soc_block_list[22],
  16076         soc_genreg,
  16077         1,
  16078         0,
  16079         0x480,
  16080         SOC_REG_FLAG_ABOVE_64_BITS |
  16081                           SOC_REG_FLAG_SIGNAL,
  16082         0,
  16083         32,
  16084         soc_OAMP_NIBBLE_SELECT_FOR_PEr_fields,
  16085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16086         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16087         -1,
  16088         -1,
  16089     },
  16090 #endif /* chips */
  16091 
  16092 #if defined(BCM_88650_A0)
  16093     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPSr */
  16094         soc_block_list[22],
  16095         soc_genreg,
  16096         1,
  16097         0,
  16098         0x168,
  16099         SOC_REG_FLAG_SIGNAL,
  16100         0,
  16101         1,
  16102         soc_OAMP_NUMBER_OF_RMEPSr_fields,
  16103         SOC_RESET_VAL_DEC(0x00004000, 0x00000000)
  16104         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16105         -1,
  16106         -1,
  16107     },
  16108 #endif /* chips */
  16109 
  16110 #if defined(BCM_88270_A0)
  16111     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88270_A0r */
  16112         soc_block_list[22],
  16113         soc_genreg,
  16114         1,
  16115         0,
  16116         0x6e0,
  16117         0,
  16118         0,
  16119         1,
  16120         soc_OAMP_NUMBER_OF_RMEPS_BCM88270_A0r_fields,
  16121         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  16122         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16123         -1,
  16124         -1,
  16125     },
  16126 #endif /* chips */
  16127 
  16128 #if defined(BCM_88375_A0)
  16129     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88375_A0r */
  16130         soc_block_list[22],
  16131         soc_genreg,
  16132         1,
  16133         0,
  16134         0x6e0,
  16135         0,
  16136         0,
  16137         1,
  16138         soc_OAMP_NUMBER_OF_RMEPS_BCM88375_A0r_fields,
  16139         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  16140         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16141         -1,
  16142         -1,
  16143     },
  16144 #endif /* chips */
  16145 
  16146 #if defined(BCM_88375_B0)
  16147     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88375_B0r */
  16148         soc_block_list[22],
  16149         soc_genreg,
  16150         1,
  16151         0,
  16152         0x6e0,
  16153         0,
  16154         0,
  16155         1,
  16156         soc_OAMP_NUMBER_OF_RMEPS_BCM88375_B0r_fields,
  16157         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  16158         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16159         -1,
  16160         -1,
  16161     },
  16162 #endif /* chips */
  16163 
  16164 #if defined(BCM_88470_A0)
  16165     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88470_A0r */
  16166         soc_block_list[22],
  16167         soc_genreg,
  16168         1,
  16169         0,
  16170         0x6e0,
  16171         0,
  16172         0,
  16173         1,
  16174         soc_OAMP_NUMBER_OF_RMEPS_BCM88470_A0r_fields,
  16175         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  16176         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16177         -1,
  16178         -1,
  16179     },
  16180 #endif /* chips */
  16181 
  16182 #if defined(BCM_88470_B0)
  16183     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88470_B0r */
  16184         soc_block_list[22],
  16185         soc_genreg,
  16186         1,
  16187         0,
  16188         0x6e0,
  16189         0,
  16190         0,
  16191         1,
  16192         soc_OAMP_NUMBER_OF_RMEPS_BCM88470_B0r_fields,
  16193         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  16194         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16195         -1,
  16196         -1,
  16197     },
  16198 #endif /* chips */
  16199 
  16200 #if defined(BCM_88650_B0)
  16201     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88650_B0r */
  16202         soc_block_list[22],
  16203         soc_genreg,
  16204         1,
  16205         0,
  16206         0x168,
  16207         SOC_REG_FLAG_SIGNAL,
  16208         0,
  16209         1,
  16210         soc_OAMP_NUMBER_OF_RMEPS_BCM88650_B0r_fields,
  16211         SOC_RESET_VAL_DEC(0x00004000, 0x00000000)
  16212         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16213         -1,
  16214         -1,
  16215     },
  16216 #endif /* chips */
  16217 
  16218 #if defined(BCM_88660_A0)
  16219     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88660_A0r */
  16220         soc_block_list[22],
  16221         soc_genreg,
  16222         1,
  16223         0,
  16224         0x5e0,
  16225         SOC_REG_FLAG_SIGNAL,
  16226         0,
  16227         1,
  16228         soc_OAMP_NUMBER_OF_RMEPS_BCM88660_A0r_fields,
  16229         SOC_RESET_VAL_DEC(0x00004000, 0x00000000)
  16230         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16231         -1,
  16232         -1,
  16233     },
  16234 #endif /* chips */
  16235 
  16236 #if defined(BCM_88675_A0)
  16237     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88675_A0r */
  16238         soc_block_list[22],
  16239         soc_genreg,
  16240         1,
  16241         0,
  16242         0x6e0,
  16243         0,
  16244         0,
  16245         1,
  16246         soc_OAMP_NUMBER_OF_RMEPS_BCM88675_A0r_fields,
  16247         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  16248         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16249         -1,
  16250         -1,
  16251     },
  16252 #endif /* chips */
  16253 
  16254 #if defined(BCM_88675_B0)
  16255     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88675_B0r */
  16256         soc_block_list[22],
  16257         soc_genreg,
  16258         1,
  16259         0,
  16260         0x6e0,
  16261         0,
  16262         0,
  16263         1,
  16264         soc_OAMP_NUMBER_OF_RMEPS_BCM88675_B0r_fields,
  16265         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  16266         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16267         -1,
  16268         -1,
  16269     },
  16270 #endif /* chips */
  16271 
  16272 #if defined(BCM_88680_A0)
  16273     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88680_A0r */
  16274         soc_block_list[22],
  16275         soc_genreg,
  16276         1,
  16277         0,
  16278         0x6e0,
  16279         0,
  16280         0,
  16281         1,
  16282         soc_OAMP_NUMBER_OF_RMEPS_BCM88680_A0r_fields,
  16283         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  16284         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16285         -1,
  16286         -1,
  16287     },
  16288 #endif /* chips */
  16289 
  16290 #if defined(BCM_88690_A0)
  16291     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88690_A0r */
  16292         soc_block_list[22],
  16293         soc_genreg,
  16294         1,
  16295         0,
  16296         0x66a,
  16297         0,
  16298         0,
  16299         1,
  16300         soc_OAMP_NUMBER_OF_RMEPS_BCM88690_A0r_fields,
  16301         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  16302         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16303         -1,
  16304         -1,
  16305     },
  16306 #endif /* chips */
  16307 
  16308 #if defined(BCM_88690_B0)
  16309     { /* SOC_REG_INT_OAMP_NUMBER_OF_RMEPS_BCM88690_B0r */
  16310         soc_block_list[22],
  16311         soc_genreg,
  16312         1,
  16313         0,
  16314         0x66a,
  16315         0,
  16316         0,
  16317         1,
  16318         soc_OAMP_NUMBER_OF_RMEPS_BCM88690_B0r_fields,
  16319         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  16320         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  16321         -1,
  16322         -1,
  16323     },
  16324 #endif /* chips */
  16325 
  16326 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  16327     { /* SOC_REG_INT_OAMP_OAMP_RAM_CTRL_0r */
  16328         soc_block_list[22],
  16329         soc_genreg,
  16330         1,
  16331         0,
  16332         0x2010100,
  16333         0,
  16334         0,
  16335         3,
  16336         soc_OAMP_OAMP_RAM_CTRL_0r_fields,
  16337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16338         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  16339         -1,
  16340         -1,
  16341     },
  16342 #endif /* chips */
  16343 
  16344 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  16345     { /* SOC_REG_INT_OAMP_OAMP_RAM_CTRL_1r */
  16346         soc_block_list[22],
  16347         soc_genreg,
  16348         1,
  16349         0,
  16350         0x2010200,
  16351         0,
  16352         0,
  16353         3,
  16354         soc_OAMP_OAMP_RAM_CTRL_1r_fields,
  16355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16356         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  16357         -1,
  16358         -1,
  16359     },
  16360 #endif /* chips */
  16361 
  16362 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  16363     { /* SOC_REG_INT_OAMP_OAMP_RAM_CTRL_2r */
  16364         soc_block_list[22],
  16365         soc_genreg,
  16366         1,
  16367         0,
  16368         0x2010300,
  16369         0,
  16370         0,
  16371         2,
  16372         soc_OAMP_OAMP_RAM_CTRL_2r_fields,
  16373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16374         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16375         -1,
  16376         -1,
  16377     },
  16378 #endif /* chips */
  16379 
  16380 #if defined(BCM_56270_A0)
  16381     { /* SOC_REG_INT_OAMP_OAMP_RAM_CTRL_3r */
  16382         soc_block_list[22],
  16383         soc_genreg,
  16384         1,
  16385         0,
  16386         0x2030000,
  16387         0,
  16388         0,
  16389         1,
  16390         soc_OAMP_OAMP_RAM_CTRL_3r_fields,
  16391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16392         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  16393         -1,
  16394         -1,
  16395     },
  16396 #endif /* chips */
  16397 
  16398 #if defined(BCM_56270_A0)
  16399     { /* SOC_REG_INT_OAMP_OAMP_RAM_CTRL_4r */
  16400         soc_block_list[22],
  16401         soc_genreg,
  16402         1,
  16403         0,
  16404         0x2030100,
  16405         0,
  16406         0,
  16407         1,
  16408         soc_OAMP_OAMP_RAM_CTRL_4r_fields,
  16409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16410         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  16411         -1,
  16412         -1,
  16413     },
  16414 #endif /* chips */
  16415 
  16416 #if defined(BCM_56270_A0)
  16417     { /* SOC_REG_INT_OAMP_OAMP_RAM_CTRL_0_BCM56270_A0r */
  16418         soc_block_list[22],
  16419         soc_genreg,
  16420         1,
  16421         0,
  16422         0x2010100,
  16423         0,
  16424         0,
  16425         2,
  16426         soc_OAMP_OAMP_RAM_CTRL_0_BCM56270_A0r_fields,
  16427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16428         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  16429         -1,
  16430         -1,
  16431     },
  16432 #endif /* chips */
  16433 
  16434 #if defined(BCM_56270_A0)
  16435     { /* SOC_REG_INT_OAMP_OAMP_RAM_CTRL_1_BCM56270_A0r */
  16436         soc_block_list[22],
  16437         soc_genreg,
  16438         1,
  16439         0,
  16440         0x2010200,
  16441         0,
  16442         0,
  16443         2,
  16444         soc_OAMP_OAMP_RAM_CTRL_1_BCM56270_A0r_fields,
  16445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16446         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16447         -1,
  16448         -1,
  16449     },
  16450 #endif /* chips */
  16451 
  16452 #if defined(BCM_56270_A0)
  16453     { /* SOC_REG_INT_OAMP_OAMP_RAM_CTRL_2_BCM56270_A0r */
  16454         soc_block_list[22],
  16455         soc_genreg,
  16456         1,
  16457         0,
  16458         0x2010300,
  16459         0,
  16460         0,
  16461         2,
  16462         soc_OAMP_OAMP_RAM_CTRL_2_BCM56270_A0r_fields,
  16463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16464         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  16465         -1,
  16466         -1,
  16467     },
  16468 #endif /* chips */
  16469 
  16470 #if defined(BCM_88660_A0)
  16471     { /* SOC_REG_INT_OAMP_OAM_TS_OFFSET_PROFILEr */
  16472         soc_block_list[22],
  16473         soc_genreg,
  16474         1,
  16475         0,
  16476         0x455,
  16477         SOC_REG_FLAG_ABOVE_64_BITS |
  16478                           SOC_REG_FLAG_SIGNAL,
  16479         0,
  16480         64,
  16481         soc_OAMP_OAM_TS_OFFSET_PROFILEr_fields,
  16482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16484         -1,
  16485         -1,
  16486     },
  16487 #endif /* chips */
  16488 
  16489 #if defined(BCM_88675_A0)
  16490     { /* SOC_REG_INT_OAMP_OPCODE_CONFIGr */
  16491         soc_block_list[22],
  16492         soc_genreg,
  16493         1,
  16494         0,
  16495         0x454,
  16496         0,
  16497         0,
  16498         1,
  16499         soc_OAMP_OPCODE_CONFIGr_fields,
  16500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16501         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16502         -1,
  16503         -1,
  16504     },
  16505 #endif /* chips */
  16506 
  16507 #if defined(BCM_88270_A0)
  16508     { /* SOC_REG_INT_OAMP_OPCODE_CONFIG_BCM88270_A0r */
  16509         soc_block_list[22],
  16510         soc_genreg,
  16511         1,
  16512         0,
  16513         0x455,
  16514         0,
  16515         0,
  16516         1,
  16517         soc_OAMP_OPCODE_CONFIG_BCM88270_A0r_fields,
  16518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16519         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16520         -1,
  16521         -1,
  16522     },
  16523 #endif /* chips */
  16524 
  16525 #if defined(BCM_88375_A0)
  16526     { /* SOC_REG_INT_OAMP_OPCODE_CONFIG_BCM88375_A0r */
  16527         soc_block_list[22],
  16528         soc_genreg,
  16529         1,
  16530         0,
  16531         0x454,
  16532         0,
  16533         0,
  16534         1,
  16535         soc_OAMP_OPCODE_CONFIG_BCM88375_A0r_fields,
  16536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16537         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16538         -1,
  16539         -1,
  16540     },
  16541 #endif /* chips */
  16542 
  16543 #if defined(BCM_88375_B0)
  16544     { /* SOC_REG_INT_OAMP_OPCODE_CONFIG_BCM88375_B0r */
  16545         soc_block_list[22],
  16546         soc_genreg,
  16547         1,
  16548         0,
  16549         0x454,
  16550         0,
  16551         0,
  16552         1,
  16553         soc_OAMP_OPCODE_CONFIG_BCM88375_B0r_fields,
  16554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16555         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16556         -1,
  16557         -1,
  16558     },
  16559 #endif /* chips */
  16560 
  16561 #if defined(BCM_88470_A0)
  16562     { /* SOC_REG_INT_OAMP_OPCODE_CONFIG_BCM88470_A0r */
  16563         soc_block_list[22],
  16564         soc_genreg,
  16565         1,
  16566         0,
  16567         0x455,
  16568         0,
  16569         0,
  16570         1,
  16571         soc_OAMP_OPCODE_CONFIG_BCM88470_A0r_fields,
  16572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16573         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16574         -1,
  16575         -1,
  16576     },
  16577 #endif /* chips */
  16578 
  16579 #if defined(BCM_88470_B0)
  16580     { /* SOC_REG_INT_OAMP_OPCODE_CONFIG_BCM88470_B0r */
  16581         soc_block_list[22],
  16582         soc_genreg,
  16583         1,
  16584         0,
  16585         0x455,
  16586         0,
  16587         0,
  16588         1,
  16589         soc_OAMP_OPCODE_CONFIG_BCM88470_B0r_fields,
  16590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16591         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16592         -1,
  16593         -1,
  16594     },
  16595 #endif /* chips */
  16596 
  16597 #if defined(BCM_88675_B0)
  16598     { /* SOC_REG_INT_OAMP_OPCODE_CONFIG_BCM88675_B0r */
  16599         soc_block_list[22],
  16600         soc_genreg,
  16601         1,
  16602         0,
  16603         0x454,
  16604         0,
  16605         0,
  16606         1,
  16607         soc_OAMP_OPCODE_CONFIG_BCM88675_B0r_fields,
  16608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16609         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16610         -1,
  16611         -1,
  16612     },
  16613 #endif /* chips */
  16614 
  16615 #if defined(BCM_88680_A0)
  16616     { /* SOC_REG_INT_OAMP_OPCODE_CONFIG_BCM88680_A0r */
  16617         soc_block_list[22],
  16618         soc_genreg,
  16619         1,
  16620         0,
  16621         0x454,
  16622         0,
  16623         0,
  16624         1,
  16625         soc_OAMP_OPCODE_CONFIG_BCM88680_A0r_fields,
  16626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16627         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16628         -1,
  16629         -1,
  16630     },
  16631 #endif /* chips */
  16632 
  16633 #if defined(BCM_88690_A0)
  16634     { /* SOC_REG_INT_OAMP_OPCODE_CONFIG_BCM88690_A0r */
  16635         soc_block_list[22],
  16636         soc_genreg,
  16637         1,
  16638         0,
  16639         0x546,
  16640         0,
  16641         0,
  16642         1,
  16643         soc_OAMP_OPCODE_CONFIG_BCM88690_A0r_fields,
  16644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16645         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16646         -1,
  16647         -1,
  16648     },
  16649 #endif /* chips */
  16650 
  16651 #if defined(BCM_88690_B0)
  16652     { /* SOC_REG_INT_OAMP_OPCODE_CONFIG_BCM88690_B0r */
  16653         soc_block_list[22],
  16654         soc_genreg,
  16655         1,
  16656         0,
  16657         0x546,
  16658         0,
  16659         0,
  16660         1,
  16661         soc_OAMP_OPCODE_CONFIG_BCM88690_B0r_fields,
  16662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16663         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16664         -1,
  16665         -1,
  16666     },
  16667 #endif /* chips */
  16668 
  16669 #if defined(BCM_88690_A0)
  16670     { /* SOC_REG_INT_OAMP_OPCODE_FOR_COUNTr */
  16671         soc_block_list[22],
  16672         soc_genreg,
  16673         6,
  16674         0,
  16675         0xb2e,
  16676         SOC_REG_FLAG_ARRAY |
  16677                           SOC_REG_FLAG_REG_ARRAY,
  16678         0,
  16679         3,
  16680         soc_OAMP_OPCODE_FOR_COUNTr_fields,
  16681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16682         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  16683         -1,
  16684         -1,
  16685     },
  16686 #endif /* chips */
  16687 
  16688 #if defined(BCM_88690_B0)
  16689     { /* SOC_REG_INT_OAMP_OPCODE_FOR_COUNT_BCM88690_B0r */
  16690         soc_block_list[22],
  16691         soc_genreg,
  16692         6,
  16693         0,
  16694         0xb30,
  16695         SOC_REG_FLAG_ARRAY |
  16696                           SOC_REG_FLAG_REG_ARRAY,
  16697         0,
  16698         3,
  16699         soc_OAMP_OPCODE_FOR_COUNT_BCM88690_B0r_fields,
  16700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16701         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  16702         -1,
  16703         -1,
  16704     },
  16705 #endif /* chips */
  16706 
  16707 #if defined(BCM_88675_A0)
  16708     { /* SOC_REG_INT_OAMP_OPCODE_INFOr */
  16709         soc_block_list[22],
  16710         soc_genreg,
  16711         8,
  16712         0,
  16713         0x456,
  16714         SOC_REG_FLAG_ABOVE_64_BITS |
  16715                           SOC_REG_FLAG_ARRAY |
  16716                           SOC_REG_FLAG_REG_ARRAY,
  16717         0,
  16718         9,
  16719         soc_OAMP_OPCODE_INFOr_fields,
  16720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16722         -1,
  16723         -1,
  16724     },
  16725 #endif /* chips */
  16726 
  16727 #if defined(BCM_88270_A0)
  16728     { /* SOC_REG_INT_OAMP_OPCODE_INFO_BCM88270_A0r */
  16729         soc_block_list[22],
  16730         soc_genreg,
  16731         8,
  16732         0,
  16733         0x457,
  16734         SOC_REG_FLAG_ABOVE_64_BITS |
  16735                           SOC_REG_FLAG_ARRAY |
  16736                           SOC_REG_FLAG_REG_ARRAY,
  16737         0,
  16738         9,
  16739         soc_OAMP_OPCODE_INFO_BCM88270_A0r_fields,
  16740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16742         -1,
  16743         -1,
  16744     },
  16745 #endif /* chips */
  16746 
  16747 #if defined(BCM_88375_A0)
  16748     { /* SOC_REG_INT_OAMP_OPCODE_INFO_BCM88375_A0r */
  16749         soc_block_list[22],
  16750         soc_genreg,
  16751         8,
  16752         0,
  16753         0x456,
  16754         SOC_REG_FLAG_ABOVE_64_BITS |
  16755                           SOC_REG_FLAG_ARRAY |
  16756                           SOC_REG_FLAG_REG_ARRAY,
  16757         0,
  16758         9,
  16759         soc_OAMP_OPCODE_INFO_BCM88375_A0r_fields,
  16760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16762         -1,
  16763         -1,
  16764     },
  16765 #endif /* chips */
  16766 
  16767 #if defined(BCM_88375_B0)
  16768     { /* SOC_REG_INT_OAMP_OPCODE_INFO_BCM88375_B0r */
  16769         soc_block_list[22],
  16770         soc_genreg,
  16771         8,
  16772         0,
  16773         0x456,
  16774         SOC_REG_FLAG_ABOVE_64_BITS |
  16775                           SOC_REG_FLAG_ARRAY |
  16776                           SOC_REG_FLAG_REG_ARRAY,
  16777         0,
  16778         9,
  16779         soc_OAMP_OPCODE_INFO_BCM88375_B0r_fields,
  16780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16782         -1,
  16783         -1,
  16784     },
  16785 #endif /* chips */
  16786 
  16787 #if defined(BCM_88470_A0)
  16788     { /* SOC_REG_INT_OAMP_OPCODE_INFO_BCM88470_A0r */
  16789         soc_block_list[22],
  16790         soc_genreg,
  16791         8,
  16792         0,
  16793         0x457,
  16794         SOC_REG_FLAG_ABOVE_64_BITS |
  16795                           SOC_REG_FLAG_ARRAY |
  16796                           SOC_REG_FLAG_REG_ARRAY,
  16797         0,
  16798         9,
  16799         soc_OAMP_OPCODE_INFO_BCM88470_A0r_fields,
  16800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16801         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16802         -1,
  16803         -1,
  16804     },
  16805 #endif /* chips */
  16806 
  16807 #if defined(BCM_88470_B0)
  16808     { /* SOC_REG_INT_OAMP_OPCODE_INFO_BCM88470_B0r */
  16809         soc_block_list[22],
  16810         soc_genreg,
  16811         8,
  16812         0,
  16813         0x457,
  16814         SOC_REG_FLAG_ABOVE_64_BITS |
  16815                           SOC_REG_FLAG_ARRAY |
  16816                           SOC_REG_FLAG_REG_ARRAY,
  16817         0,
  16818         9,
  16819         soc_OAMP_OPCODE_INFO_BCM88470_B0r_fields,
  16820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16821         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16822         -1,
  16823         -1,
  16824     },
  16825 #endif /* chips */
  16826 
  16827 #if defined(BCM_88675_B0)
  16828     { /* SOC_REG_INT_OAMP_OPCODE_INFO_BCM88675_B0r */
  16829         soc_block_list[22],
  16830         soc_genreg,
  16831         8,
  16832         0,
  16833         0x456,
  16834         SOC_REG_FLAG_ABOVE_64_BITS |
  16835                           SOC_REG_FLAG_ARRAY |
  16836                           SOC_REG_FLAG_REG_ARRAY,
  16837         0,
  16838         9,
  16839         soc_OAMP_OPCODE_INFO_BCM88675_B0r_fields,
  16840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16841         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16842         -1,
  16843         -1,
  16844     },
  16845 #endif /* chips */
  16846 
  16847 #if defined(BCM_88680_A0)
  16848     { /* SOC_REG_INT_OAMP_OPCODE_INFO_BCM88680_A0r */
  16849         soc_block_list[22],
  16850         soc_genreg,
  16851         8,
  16852         0,
  16853         0x456,
  16854         SOC_REG_FLAG_ABOVE_64_BITS |
  16855                           SOC_REG_FLAG_ARRAY |
  16856                           SOC_REG_FLAG_REG_ARRAY,
  16857         0,
  16858         9,
  16859         soc_OAMP_OPCODE_INFO_BCM88680_A0r_fields,
  16860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16861         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16862         -1,
  16863         -1,
  16864     },
  16865 #endif /* chips */
  16866 
  16867 #if defined(BCM_88690_A0)
  16868     { /* SOC_REG_INT_OAMP_OPCODE_INFO_BCM88690_A0r */
  16869         soc_block_list[22],
  16870         soc_genreg,
  16871         8,
  16872         0,
  16873         0x548,
  16874         SOC_REG_FLAG_ABOVE_64_BITS |
  16875                           SOC_REG_FLAG_ARRAY |
  16876                           SOC_REG_FLAG_REG_ARRAY,
  16877         0,
  16878         9,
  16879         soc_OAMP_OPCODE_INFO_BCM88690_A0r_fields,
  16880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16882         -1,
  16883         -1,
  16884     },
  16885 #endif /* chips */
  16886 
  16887 #if defined(BCM_88690_B0)
  16888     { /* SOC_REG_INT_OAMP_OPCODE_INFO_BCM88690_B0r */
  16889         soc_block_list[22],
  16890         soc_genreg,
  16891         8,
  16892         0,
  16893         0x548,
  16894         SOC_REG_FLAG_ABOVE_64_BITS |
  16895                           SOC_REG_FLAG_ARRAY |
  16896                           SOC_REG_FLAG_REG_ARRAY,
  16897         0,
  16898         9,
  16899         soc_OAMP_OPCODE_INFO_BCM88690_B0r_fields,
  16900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16901         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16902         -1,
  16903         -1,
  16904     },
  16905 #endif /* chips */
  16906 
  16907 #if defined(BCM_88650_A0)
  16908     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNTr */
  16909         soc_block_list[22],
  16910         soc_genreg,
  16911         1,
  16912         0,
  16913         0x98,
  16914         SOC_REG_FLAG_64_BITS |
  16915                           SOC_REG_FLAG_RO,
  16916         0,
  16917         4,
  16918         soc_OAMP_PARITY_ERR_CNTr_fields,
  16919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16920         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  16921         -1,
  16922         -1,
  16923     },
  16924 #endif /* chips */
  16925 
  16926 #if defined(BCM_88270_A0)
  16927     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88270_A0r */
  16928         soc_block_list[22],
  16929         soc_genreg,
  16930         1,
  16931         0,
  16932         0x98,
  16933         SOC_REG_FLAG_64_BITS |
  16934                           SOC_REG_FLAG_RO,
  16935         0,
  16936         4,
  16937         soc_OAMP_PARITY_ERR_CNT_BCM88270_A0r_fields,
  16938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16939         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  16940         -1,
  16941         -1,
  16942     },
  16943 #endif /* chips */
  16944 
  16945 #if defined(BCM_88375_A0)
  16946     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88375_A0r */
  16947         soc_block_list[22],
  16948         soc_genreg,
  16949         1,
  16950         0,
  16951         0x98,
  16952         SOC_REG_FLAG_64_BITS |
  16953                           SOC_REG_FLAG_RO,
  16954         0,
  16955         4,
  16956         soc_OAMP_PARITY_ERR_CNT_BCM88375_A0r_fields,
  16957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16958         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  16959         -1,
  16960         -1,
  16961     },
  16962 #endif /* chips */
  16963 
  16964 #if defined(BCM_88375_B0)
  16965     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88375_B0r */
  16966         soc_block_list[22],
  16967         soc_genreg,
  16968         1,
  16969         0,
  16970         0x98,
  16971         SOC_REG_FLAG_64_BITS |
  16972                           SOC_REG_FLAG_RO,
  16973         0,
  16974         4,
  16975         soc_OAMP_PARITY_ERR_CNT_BCM88375_B0r_fields,
  16976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16977         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  16978         -1,
  16979         -1,
  16980     },
  16981 #endif /* chips */
  16982 
  16983 #if defined(BCM_88470_A0)
  16984     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88470_A0r */
  16985         soc_block_list[22],
  16986         soc_genreg,
  16987         1,
  16988         0,
  16989         0x98,
  16990         SOC_REG_FLAG_64_BITS |
  16991                           SOC_REG_FLAG_RO,
  16992         0,
  16993         4,
  16994         soc_OAMP_PARITY_ERR_CNT_BCM88470_A0r_fields,
  16995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16996         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  16997         -1,
  16998         -1,
  16999     },
  17000 #endif /* chips */
  17001 
  17002 #if defined(BCM_88470_B0)
  17003     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88470_B0r */
  17004         soc_block_list[22],
  17005         soc_genreg,
  17006         1,
  17007         0,
  17008         0x98,
  17009         SOC_REG_FLAG_64_BITS |
  17010                           SOC_REG_FLAG_RO,
  17011         0,
  17012         4,
  17013         soc_OAMP_PARITY_ERR_CNT_BCM88470_B0r_fields,
  17014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17015         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  17016         -1,
  17017         -1,
  17018     },
  17019 #endif /* chips */
  17020 
  17021 #if defined(BCM_88650_B0)
  17022     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88650_B0r */
  17023         soc_block_list[22],
  17024         soc_genreg,
  17025         1,
  17026         0,
  17027         0x98,
  17028         SOC_REG_FLAG_64_BITS |
  17029                           SOC_REG_FLAG_RO,
  17030         0,
  17031         4,
  17032         soc_OAMP_PARITY_ERR_CNT_BCM88650_B0r_fields,
  17033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17034         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  17035         -1,
  17036         -1,
  17037     },
  17038 #endif /* chips */
  17039 
  17040 #if defined(BCM_88660_A0)
  17041     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88660_A0r */
  17042         soc_block_list[22],
  17043         soc_genreg,
  17044         1,
  17045         0,
  17046         0x98,
  17047         SOC_REG_FLAG_64_BITS |
  17048                           SOC_REG_FLAG_RO,
  17049         0,
  17050         4,
  17051         soc_OAMP_PARITY_ERR_CNT_BCM88660_A0r_fields,
  17052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17053         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  17054         -1,
  17055         -1,
  17056     },
  17057 #endif /* chips */
  17058 
  17059 #if defined(BCM_88675_A0)
  17060     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88675_A0r */
  17061         soc_block_list[22],
  17062         soc_genreg,
  17063         1,
  17064         0,
  17065         0x98,
  17066         SOC_REG_FLAG_64_BITS |
  17067                           SOC_REG_FLAG_RO,
  17068         0,
  17069         4,
  17070         soc_OAMP_PARITY_ERR_CNT_BCM88675_A0r_fields,
  17071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17072         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  17073         -1,
  17074         -1,
  17075     },
  17076 #endif /* chips */
  17077 
  17078 #if defined(BCM_88675_B0)
  17079     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88675_B0r */
  17080         soc_block_list[22],
  17081         soc_genreg,
  17082         1,
  17083         0,
  17084         0x98,
  17085         SOC_REG_FLAG_64_BITS |
  17086                           SOC_REG_FLAG_RO,
  17087         0,
  17088         4,
  17089         soc_OAMP_PARITY_ERR_CNT_BCM88675_B0r_fields,
  17090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17091         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  17092         -1,
  17093         -1,
  17094     },
  17095 #endif /* chips */
  17096 
  17097 #if defined(BCM_88680_A0)
  17098     { /* SOC_REG_INT_OAMP_PARITY_ERR_CNT_BCM88680_A0r */
  17099         soc_block_list[22],
  17100         soc_genreg,
  17101         1,
  17102         0,
  17103         0x98,
  17104         SOC_REG_FLAG_64_BITS |
  17105                           SOC_REG_FLAG_RO,
  17106         0,
  17107         4,
  17108         soc_OAMP_PARITY_ERR_CNT_BCM88680_A0r_fields,
  17109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17110         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  17111         -1,
  17112         -1,
  17113     },
  17114 #endif /* chips */
  17115 
  17116 #if defined(BCM_88650_A0)
  17117     { /* SOC_REG_INT_OAMP_PAR_0_ERR_MONITOR_MEM_MASKr */
  17118         soc_block_list[22],
  17119         soc_genreg,
  17120         1,
  17121         0,
  17122         0xa0,
  17123         SOC_REG_FLAG_64_BITS,
  17124         0,
  17125         33,
  17126         soc_OAMP_PAR_0_ERR_MONITOR_MEM_MASKr_fields,
  17127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17128         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  17129         -1,
  17130         -1,
  17131     },
  17132 #endif /* chips */
  17133 
  17134 #if defined(BCM_88650_B0)
  17135     { /* SOC_REG_INT_OAMP_PAR_0_ERR_MONITOR_MEM_MASK_BCM88650_B0r */
  17136         soc_block_list[22],
  17137         soc_genreg,
  17138         1,
  17139         0,
  17140         0xa0,
  17141         SOC_REG_FLAG_64_BITS,
  17142         0,
  17143         33,
  17144         soc_OAMP_PAR_0_ERR_MONITOR_MEM_MASK_BCM88650_B0r_fields,
  17145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17146         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  17147         -1,
  17148         -1,
  17149     },
  17150 #endif /* chips */
  17151 
  17152 #if defined(BCM_88660_A0)
  17153     { /* SOC_REG_INT_OAMP_PAR_0_ERR_MONITOR_MEM_MASK_BCM88660_A0r */
  17154         soc_block_list[22],
  17155         soc_genreg,
  17156         1,
  17157         0,
  17158         0xa0,
  17159         SOC_REG_FLAG_64_BITS,
  17160         0,
  17161         38,
  17162         soc_OAMP_PAR_0_ERR_MONITOR_MEM_MASK_BCM88660_A0r_fields,
  17163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17164         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  17165         -1,
  17166         -1,
  17167     },
  17168 #endif /* chips */
  17169 
  17170 #if defined(BCM_88675_A0)
  17171     { /* SOC_REG_INT_OAMP_PAR_ERR_INITIATEr */
  17172         soc_block_list[22],
  17173         soc_genreg,
  17174         1,
  17175         0,
  17176         0xaa,
  17177         0,
  17178         0,
  17179         1,
  17180         soc_OAMP_PAR_ERR_INITIATEr_fields,
  17181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17182         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17183         -1,
  17184         -1,
  17185     },
  17186 #endif /* chips */
  17187 
  17188 #if defined(BCM_88270_A0)
  17189     { /* SOC_REG_INT_OAMP_PAR_ERR_INITIATE_BCM88270_A0r */
  17190         soc_block_list[22],
  17191         soc_genreg,
  17192         1,
  17193         0,
  17194         0xaa,
  17195         0,
  17196         0,
  17197         1,
  17198         soc_OAMP_PAR_ERR_INITIATE_BCM88270_A0r_fields,
  17199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17200         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17201         -1,
  17202         -1,
  17203     },
  17204 #endif /* chips */
  17205 
  17206 #if defined(BCM_88375_A0)
  17207     { /* SOC_REG_INT_OAMP_PAR_ERR_INITIATE_BCM88375_A0r */
  17208         soc_block_list[22],
  17209         soc_genreg,
  17210         1,
  17211         0,
  17212         0xaa,
  17213         0,
  17214         0,
  17215         1,
  17216         soc_OAMP_PAR_ERR_INITIATE_BCM88375_A0r_fields,
  17217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17218         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17219         -1,
  17220         -1,
  17221     },
  17222 #endif /* chips */
  17223 
  17224 #if defined(BCM_88375_B0)
  17225     { /* SOC_REG_INT_OAMP_PAR_ERR_INITIATE_BCM88375_B0r */
  17226         soc_block_list[22],
  17227         soc_genreg,
  17228         1,
  17229         0,
  17230         0xaa,
  17231         0,
  17232         0,
  17233         1,
  17234         soc_OAMP_PAR_ERR_INITIATE_BCM88375_B0r_fields,
  17235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17236         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17237         -1,
  17238         -1,
  17239     },
  17240 #endif /* chips */
  17241 
  17242 #if defined(BCM_88470_A0)
  17243     { /* SOC_REG_INT_OAMP_PAR_ERR_INITIATE_BCM88470_A0r */
  17244         soc_block_list[22],
  17245         soc_genreg,
  17246         1,
  17247         0,
  17248         0xaa,
  17249         0,
  17250         0,
  17251         1,
  17252         soc_OAMP_PAR_ERR_INITIATE_BCM88470_A0r_fields,
  17253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17254         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17255         -1,
  17256         -1,
  17257     },
  17258 #endif /* chips */
  17259 
  17260 #if defined(BCM_88470_B0)
  17261     { /* SOC_REG_INT_OAMP_PAR_ERR_INITIATE_BCM88470_B0r */
  17262         soc_block_list[22],
  17263         soc_genreg,
  17264         1,
  17265         0,
  17266         0xaa,
  17267         0,
  17268         0,
  17269         1,
  17270         soc_OAMP_PAR_ERR_INITIATE_BCM88470_B0r_fields,
  17271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17272         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17273         -1,
  17274         -1,
  17275     },
  17276 #endif /* chips */
  17277 
  17278 #if defined(BCM_88675_B0)
  17279     { /* SOC_REG_INT_OAMP_PAR_ERR_INITIATE_BCM88675_B0r */
  17280         soc_block_list[22],
  17281         soc_genreg,
  17282         1,
  17283         0,
  17284         0xaa,
  17285         0,
  17286         0,
  17287         1,
  17288         soc_OAMP_PAR_ERR_INITIATE_BCM88675_B0r_fields,
  17289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17290         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17291         -1,
  17292         -1,
  17293     },
  17294 #endif /* chips */
  17295 
  17296 #if defined(BCM_88680_A0)
  17297     { /* SOC_REG_INT_OAMP_PAR_ERR_INITIATE_BCM88680_A0r */
  17298         soc_block_list[22],
  17299         soc_genreg,
  17300         1,
  17301         0,
  17302         0xaa,
  17303         0,
  17304         0,
  17305         1,
  17306         soc_OAMP_PAR_ERR_INITIATE_BCM88680_A0r_fields,
  17307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17308         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17309         -1,
  17310         -1,
  17311     },
  17312 #endif /* chips */
  17313 
  17314 #if defined(BCM_88675_A0)
  17315     { /* SOC_REG_INT_OAMP_PAR_ERR_MEM_MASKr */
  17316         soc_block_list[22],
  17317         soc_genreg,
  17318         1,
  17319         0,
  17320         0xa0,
  17321         0,
  17322         0,
  17323         1,
  17324         soc_OAMP_PAR_ERR_MEM_MASKr_fields,
  17325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17326         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17327         -1,
  17328         -1,
  17329     },
  17330 #endif /* chips */
  17331 
  17332 #if defined(BCM_88270_A0)
  17333     { /* SOC_REG_INT_OAMP_PAR_ERR_MEM_MASK_BCM88270_A0r */
  17334         soc_block_list[22],
  17335         soc_genreg,
  17336         1,
  17337         0,
  17338         0xa0,
  17339         0,
  17340         0,
  17341         1,
  17342         soc_OAMP_PAR_ERR_MEM_MASK_BCM88270_A0r_fields,
  17343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17344         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17345         -1,
  17346         -1,
  17347     },
  17348 #endif /* chips */
  17349 
  17350 #if defined(BCM_88375_A0)
  17351     { /* SOC_REG_INT_OAMP_PAR_ERR_MEM_MASK_BCM88375_A0r */
  17352         soc_block_list[22],
  17353         soc_genreg,
  17354         1,
  17355         0,
  17356         0xa0,
  17357         0,
  17358         0,
  17359         1,
  17360         soc_OAMP_PAR_ERR_MEM_MASK_BCM88375_A0r_fields,
  17361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17362         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17363         -1,
  17364         -1,
  17365     },
  17366 #endif /* chips */
  17367 
  17368 #if defined(BCM_88375_B0)
  17369     { /* SOC_REG_INT_OAMP_PAR_ERR_MEM_MASK_BCM88375_B0r */
  17370         soc_block_list[22],
  17371         soc_genreg,
  17372         1,
  17373         0,
  17374         0xa0,
  17375         0,
  17376         0,
  17377         1,
  17378         soc_OAMP_PAR_ERR_MEM_MASK_BCM88375_B0r_fields,
  17379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17380         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17381         -1,
  17382         -1,
  17383     },
  17384 #endif /* chips */
  17385 
  17386 #if defined(BCM_88470_A0)
  17387     { /* SOC_REG_INT_OAMP_PAR_ERR_MEM_MASK_BCM88470_A0r */
  17388         soc_block_list[22],
  17389         soc_genreg,
  17390         1,
  17391         0,
  17392         0xa0,
  17393         0,
  17394         0,
  17395         1,
  17396         soc_OAMP_PAR_ERR_MEM_MASK_BCM88470_A0r_fields,
  17397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17398         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17399         -1,
  17400         -1,
  17401     },
  17402 #endif /* chips */
  17403 
  17404 #if defined(BCM_88470_B0)
  17405     { /* SOC_REG_INT_OAMP_PAR_ERR_MEM_MASK_BCM88470_B0r */
  17406         soc_block_list[22],
  17407         soc_genreg,
  17408         1,
  17409         0,
  17410         0xa0,
  17411         0,
  17412         0,
  17413         1,
  17414         soc_OAMP_PAR_ERR_MEM_MASK_BCM88470_B0r_fields,
  17415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17416         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17417         -1,
  17418         -1,
  17419     },
  17420 #endif /* chips */
  17421 
  17422 #if defined(BCM_88675_B0)
  17423     { /* SOC_REG_INT_OAMP_PAR_ERR_MEM_MASK_BCM88675_B0r */
  17424         soc_block_list[22],
  17425         soc_genreg,
  17426         1,
  17427         0,
  17428         0xa0,
  17429         0,
  17430         0,
  17431         1,
  17432         soc_OAMP_PAR_ERR_MEM_MASK_BCM88675_B0r_fields,
  17433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17434         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17435         -1,
  17436         -1,
  17437     },
  17438 #endif /* chips */
  17439 
  17440 #if defined(BCM_88680_A0)
  17441     { /* SOC_REG_INT_OAMP_PAR_ERR_MEM_MASK_BCM88680_A0r */
  17442         soc_block_list[22],
  17443         soc_genreg,
  17444         1,
  17445         0,
  17446         0xa0,
  17447         0,
  17448         0,
  17449         1,
  17450         soc_OAMP_PAR_ERR_MEM_MASK_BCM88680_A0r_fields,
  17451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17452         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  17453         -1,
  17454         -1,
  17455     },
  17456 #endif /* chips */
  17457 
  17458 #if defined(BCM_88690_A0)
  17459     { /* SOC_REG_INT_OAMP_PER_MEP_PROFILE_RX_COUNTER_CFGr */
  17460         soc_block_list[22],
  17461         soc_genreg,
  17462         1,
  17463         0,
  17464         0xb2b,
  17465         0,
  17466         0,
  17467         2,
  17468         soc_OAMP_PER_MEP_PROFILE_RX_COUNTER_CFGr_fields,
  17469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17470         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  17471         -1,
  17472         -1,
  17473     },
  17474 #endif /* chips */
  17475 
  17476 #if defined(BCM_88690_B0)
  17477     { /* SOC_REG_INT_OAMP_PER_MEP_PROFILE_RX_COUNTER_CFG_BCM88690_B0r */
  17478         soc_block_list[22],
  17479         soc_genreg,
  17480         1,
  17481         0,
  17482         0xb2c,
  17483         0,
  17484         0,
  17485         2,
  17486         soc_OAMP_PER_MEP_PROFILE_RX_COUNTER_CFG_BCM88690_B0r_fields,
  17487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17488         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  17489         -1,
  17490         -1,
  17491     },
  17492 #endif /* chips */
  17493 
  17494 #if defined(BCM_88690_A0)
  17495     { /* SOC_REG_INT_OAMP_PER_MEP_PROFILE_TX_COUNTER_CFGr */
  17496         soc_block_list[22],
  17497         soc_genreg,
  17498         1,
  17499         0,
  17500         0xb2c,
  17501         0,
  17502         0,
  17503         2,
  17504         soc_OAMP_PER_MEP_PROFILE_TX_COUNTER_CFGr_fields,
  17505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17506         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  17507         -1,
  17508         -1,
  17509     },
  17510 #endif /* chips */
  17511 
  17512 #if defined(BCM_88690_B0)
  17513     { /* SOC_REG_INT_OAMP_PER_MEP_PROFILE_TX_COUNTER_CFG_BCM88690_B0r */
  17514         soc_block_list[22],
  17515         soc_genreg,
  17516         1,
  17517         0,
  17518         0xb2d,
  17519         0,
  17520         0,
  17521         2,
  17522         soc_OAMP_PER_MEP_PROFILE_TX_COUNTER_CFG_BCM88690_B0r_fields,
  17523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17524         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  17525         -1,
  17526         -1,
  17527     },
  17528 #endif /* chips */
  17529 
  17530 #if defined(BCM_88675_A0)
  17531     { /* SOC_REG_INT_OAMP_PE_CONSTr */
  17532         soc_block_list[22],
  17533         soc_genreg,
  17534         32,
  17535         0,
  17536         0x4af,
  17537         SOC_REG_FLAG_ARRAY |
  17538                           SOC_REG_FLAG_REG_ARRAY,
  17539         0,
  17540         1,
  17541         soc_OAMP_PE_CONSTr_fields,
  17542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17544         -1,
  17545         -1,
  17546     },
  17547 #endif /* chips */
  17548 
  17549 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  17550     defined(BCM_56270_A0)
  17551     { /* SOC_REG_INT_OAMP_PE_CONST_BCM56260_A0r */
  17552         soc_block_list[22],
  17553         soc_genreg,
  17554         32,
  17555         0,
  17556         0x2011d00,
  17557         SOC_REG_FLAG_ARRAY |
  17558                           SOC_REG_FLAG_REG_ARRAY,
  17559         0,
  17560         1,
  17561         soc_OAMP_PE_CONST_BCM56260_A0r_fields,
  17562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17563         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17564         -1,
  17565         -1,
  17566     },
  17567 #endif /* chips */
  17568 
  17569 #if defined(BCM_88270_A0)
  17570     { /* SOC_REG_INT_OAMP_PE_CONST_BCM88270_A0r */
  17571         soc_block_list[22],
  17572         soc_genreg,
  17573         32,
  17574         0,
  17575         0x4bb,
  17576         SOC_REG_FLAG_ARRAY |
  17577                           SOC_REG_FLAG_REG_ARRAY,
  17578         0,
  17579         1,
  17580         soc_OAMP_PE_CONST_BCM88270_A0r_fields,
  17581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17582         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17583         -1,
  17584         -1,
  17585     },
  17586 #endif /* chips */
  17587 
  17588 #if defined(BCM_88375_A0)
  17589     { /* SOC_REG_INT_OAMP_PE_CONST_BCM88375_A0r */
  17590         soc_block_list[22],
  17591         soc_genreg,
  17592         32,
  17593         0,
  17594         0x4af,
  17595         SOC_REG_FLAG_ARRAY |
  17596                           SOC_REG_FLAG_REG_ARRAY,
  17597         0,
  17598         1,
  17599         soc_OAMP_PE_CONST_BCM88375_A0r_fields,
  17600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17601         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17602         -1,
  17603         -1,
  17604     },
  17605 #endif /* chips */
  17606 
  17607 #if defined(BCM_88375_B0)
  17608     { /* SOC_REG_INT_OAMP_PE_CONST_BCM88375_B0r */
  17609         soc_block_list[22],
  17610         soc_genreg,
  17611         32,
  17612         0,
  17613         0x4af,
  17614         SOC_REG_FLAG_ARRAY |
  17615                           SOC_REG_FLAG_REG_ARRAY,
  17616         0,
  17617         1,
  17618         soc_OAMP_PE_CONST_BCM88375_B0r_fields,
  17619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17620         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17621         -1,
  17622         -1,
  17623     },
  17624 #endif /* chips */
  17625 
  17626 #if defined(BCM_88470_A0)
  17627     { /* SOC_REG_INT_OAMP_PE_CONST_BCM88470_A0r */
  17628         soc_block_list[22],
  17629         soc_genreg,
  17630         32,
  17631         0,
  17632         0x4bb,
  17633         SOC_REG_FLAG_ARRAY |
  17634                           SOC_REG_FLAG_REG_ARRAY,
  17635         0,
  17636         1,
  17637         soc_OAMP_PE_CONST_BCM88470_A0r_fields,
  17638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17639         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17640         -1,
  17641         -1,
  17642     },
  17643 #endif /* chips */
  17644 
  17645 #if defined(BCM_88470_B0)
  17646     { /* SOC_REG_INT_OAMP_PE_CONST_BCM88470_B0r */
  17647         soc_block_list[22],
  17648         soc_genreg,
  17649         32,
  17650         0,
  17651         0x4bb,
  17652         SOC_REG_FLAG_ARRAY |
  17653                           SOC_REG_FLAG_REG_ARRAY,
  17654         0,
  17655         1,
  17656         soc_OAMP_PE_CONST_BCM88470_B0r_fields,
  17657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17658         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17659         -1,
  17660         -1,
  17661     },
  17662 #endif /* chips */
  17663 
  17664 #if defined(BCM_88675_B0)
  17665     { /* SOC_REG_INT_OAMP_PE_CONST_BCM88675_B0r */
  17666         soc_block_list[22],
  17667         soc_genreg,
  17668         32,
  17669         0,
  17670         0x4af,
  17671         SOC_REG_FLAG_ARRAY |
  17672                           SOC_REG_FLAG_REG_ARRAY,
  17673         0,
  17674         1,
  17675         soc_OAMP_PE_CONST_BCM88675_B0r_fields,
  17676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17677         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17678         -1,
  17679         -1,
  17680     },
  17681 #endif /* chips */
  17682 
  17683 #if defined(BCM_88680_A0)
  17684     { /* SOC_REG_INT_OAMP_PE_CONST_BCM88680_A0r */
  17685         soc_block_list[22],
  17686         soc_genreg,
  17687         32,
  17688         0,
  17689         0x4af,
  17690         SOC_REG_FLAG_ARRAY |
  17691                           SOC_REG_FLAG_REG_ARRAY,
  17692         0,
  17693         1,
  17694         soc_OAMP_PE_CONST_BCM88680_A0r_fields,
  17695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17696         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17697         -1,
  17698         -1,
  17699     },
  17700 #endif /* chips */
  17701 
  17702 #if defined(BCM_88690_A0)
  17703     { /* SOC_REG_INT_OAMP_PE_CONST_BCM88690_A0r */
  17704         soc_block_list[22],
  17705         soc_genreg,
  17706         32,
  17707         0,
  17708         0x5ac,
  17709         SOC_REG_FLAG_ARRAY |
  17710                           SOC_REG_FLAG_REG_ARRAY,
  17711         0,
  17712         1,
  17713         soc_OAMP_PE_CONST_BCM88690_A0r_fields,
  17714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17716         -1,
  17717         -1,
  17718     },
  17719 #endif /* chips */
  17720 
  17721 #if defined(BCM_88690_B0)
  17722     { /* SOC_REG_INT_OAMP_PE_CONST_BCM88690_B0r */
  17723         soc_block_list[22],
  17724         soc_genreg,
  17725         32,
  17726         0,
  17727         0x5ac,
  17728         SOC_REG_FLAG_ARRAY |
  17729                           SOC_REG_FLAG_REG_ARRAY,
  17730         0,
  17731         1,
  17732         soc_OAMP_PE_CONST_BCM88690_B0r_fields,
  17733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17734         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17735         -1,
  17736         -1,
  17737     },
  17738 #endif /* chips */
  17739 
  17740 #if defined(BCM_88660_A0)
  17741     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_1r */
  17742         soc_block_list[22],
  17743         soc_genreg,
  17744         1,
  17745         0,
  17746         0x50b,
  17747         SOC_REG_FLAG_ABOVE_64_BITS |
  17748                           SOC_REG_FLAG_SIGNAL,
  17749         0,
  17750         5,
  17751         soc_OAMP_PE_FEM_CFG_1r_fields,
  17752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17754         -1,
  17755         -1,
  17756     },
  17757 #endif /* chips */
  17758 
  17759 #if defined(BCM_88675_A0)
  17760     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_2r */
  17761         soc_block_list[22],
  17762         soc_genreg,
  17763         1,
  17764         0,
  17765         0x502,
  17766         SOC_REG_FLAG_ABOVE_64_BITS,
  17767         0,
  17768         5,
  17769         soc_OAMP_PE_FEM_CFG_2r_fields,
  17770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17772         -1,
  17773         -1,
  17774     },
  17775 #endif /* chips */
  17776 
  17777 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  17778     defined(BCM_56270_A0)
  17779     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_1_BCM56260_A0r */
  17780         soc_block_list[22],
  17781         soc_genreg,
  17782         1,
  17783         0,
  17784         0x2015e00,
  17785         SOC_REG_FLAG_ABOVE_64_BITS,
  17786         0,
  17787         6,
  17788         soc_OAMP_PE_FEM_CFG_1_BCM56260_A0r_fields,
  17789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17791         -1,
  17792         -1,
  17793     },
  17794 #endif /* chips */
  17795 
  17796 #if defined(BCM_88375_A0)
  17797     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_1_BCM88375_A0r */
  17798         soc_block_list[22],
  17799         soc_genreg,
  17800         1,
  17801         0,
  17802         0x4f0,
  17803         SOC_REG_FLAG_ABOVE_64_BITS,
  17804         0,
  17805         6,
  17806         soc_OAMP_PE_FEM_CFG_1_BCM88375_A0r_fields,
  17807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17808         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17809         -1,
  17810         -1,
  17811     },
  17812 #endif /* chips */
  17813 
  17814 #if defined(BCM_88375_B0)
  17815     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_1_BCM88375_B0r */
  17816         soc_block_list[22],
  17817         soc_genreg,
  17818         1,
  17819         0,
  17820         0x4f0,
  17821         SOC_REG_FLAG_ABOVE_64_BITS,
  17822         0,
  17823         6,
  17824         soc_OAMP_PE_FEM_CFG_1_BCM88375_B0r_fields,
  17825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17826         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17827         -1,
  17828         -1,
  17829     },
  17830 #endif /* chips */
  17831 
  17832 #if defined(BCM_88675_A0)
  17833     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_1_BCM88675_A0r */
  17834         soc_block_list[22],
  17835         soc_genreg,
  17836         1,
  17837         0,
  17838         0x4f0,
  17839         SOC_REG_FLAG_ABOVE_64_BITS,
  17840         0,
  17841         6,
  17842         soc_OAMP_PE_FEM_CFG_1_BCM88675_A0r_fields,
  17843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17844         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17845         -1,
  17846         -1,
  17847     },
  17848 #endif /* chips */
  17849 
  17850 #if defined(BCM_88675_B0)
  17851     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_1_BCM88675_B0r */
  17852         soc_block_list[22],
  17853         soc_genreg,
  17854         1,
  17855         0,
  17856         0x4f0,
  17857         SOC_REG_FLAG_ABOVE_64_BITS,
  17858         0,
  17859         6,
  17860         soc_OAMP_PE_FEM_CFG_1_BCM88675_B0r_fields,
  17861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17862         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17863         -1,
  17864         -1,
  17865     },
  17866 #endif /* chips */
  17867 
  17868 #if defined(BCM_88680_A0)
  17869     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_1_BCM88680_A0r */
  17870         soc_block_list[22],
  17871         soc_genreg,
  17872         1,
  17873         0,
  17874         0x4f0,
  17875         SOC_REG_FLAG_ABOVE_64_BITS,
  17876         0,
  17877         6,
  17878         soc_OAMP_PE_FEM_CFG_1_BCM88680_A0r_fields,
  17879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17880         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17881         -1,
  17882         -1,
  17883     },
  17884 #endif /* chips */
  17885 
  17886 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  17887     defined(BCM_56270_A0)
  17888     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_2_BCM56260_A0r */
  17889         soc_block_list[22],
  17890         soc_genreg,
  17891         1,
  17892         0,
  17893         0x2017000,
  17894         SOC_REG_FLAG_ABOVE_64_BITS,
  17895         0,
  17896         5,
  17897         soc_OAMP_PE_FEM_CFG_2_BCM56260_A0r_fields,
  17898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17899         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17900         -1,
  17901         -1,
  17902     },
  17903 #endif /* chips */
  17904 
  17905 #if defined(BCM_88375_A0)
  17906     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_2_BCM88375_A0r */
  17907         soc_block_list[22],
  17908         soc_genreg,
  17909         1,
  17910         0,
  17911         0x502,
  17912         SOC_REG_FLAG_ABOVE_64_BITS,
  17913         0,
  17914         5,
  17915         soc_OAMP_PE_FEM_CFG_2_BCM88375_A0r_fields,
  17916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17918         -1,
  17919         -1,
  17920     },
  17921 #endif /* chips */
  17922 
  17923 #if defined(BCM_88375_B0)
  17924     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_2_BCM88375_B0r */
  17925         soc_block_list[22],
  17926         soc_genreg,
  17927         1,
  17928         0,
  17929         0x502,
  17930         SOC_REG_FLAG_ABOVE_64_BITS,
  17931         0,
  17932         5,
  17933         soc_OAMP_PE_FEM_CFG_2_BCM88375_B0r_fields,
  17934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17936         -1,
  17937         -1,
  17938     },
  17939 #endif /* chips */
  17940 
  17941 #if defined(BCM_88675_B0)
  17942     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_2_BCM88675_B0r */
  17943         soc_block_list[22],
  17944         soc_genreg,
  17945         1,
  17946         0,
  17947         0x502,
  17948         SOC_REG_FLAG_ABOVE_64_BITS,
  17949         0,
  17950         5,
  17951         soc_OAMP_PE_FEM_CFG_2_BCM88675_B0r_fields,
  17952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17953         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17954         -1,
  17955         -1,
  17956     },
  17957 #endif /* chips */
  17958 
  17959 #if defined(BCM_88680_A0)
  17960     { /* SOC_REG_INT_OAMP_PE_FEM_CFG_2_BCM88680_A0r */
  17961         soc_block_list[22],
  17962         soc_genreg,
  17963         1,
  17964         0,
  17965         0x502,
  17966         SOC_REG_FLAG_ABOVE_64_BITS,
  17967         0,
  17968         5,
  17969         soc_OAMP_PE_FEM_CFG_2_BCM88680_A0r_fields,
  17970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17971         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17972         -1,
  17973         -1,
  17974     },
  17975 #endif /* chips */
  17976 
  17977 #if defined(BCM_88470_A0)
  17978     { /* SOC_REG_INT_OAMP_PE_FEM_MAPr */
  17979         soc_block_list[22],
  17980         soc_genreg,
  17981         31,
  17982         0,
  17983         0x4fc,
  17984         SOC_REG_FLAG_ABOVE_64_BITS |
  17985                           SOC_REG_FLAG_ARRAY |
  17986                           SOC_REG_FLAG_REG_ARRAY,
  17987         0,
  17988         1,
  17989         soc_OAMP_PE_FEM_MAPr_fields,
  17990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17992         -1,
  17993         -1,
  17994     },
  17995 #endif /* chips */
  17996 
  17997 #if defined(BCM_88270_A0)
  17998     { /* SOC_REG_INT_OAMP_PE_FEM_MAP_BCM88270_A0r */
  17999         soc_block_list[22],
  18000         soc_genreg,
  18001         31,
  18002         0,
  18003         0x4fc,
  18004         SOC_REG_FLAG_ABOVE_64_BITS |
  18005                           SOC_REG_FLAG_ARRAY |
  18006                           SOC_REG_FLAG_REG_ARRAY,
  18007         0,
  18008         1,
  18009         soc_OAMP_PE_FEM_MAP_BCM88270_A0r_fields,
  18010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18012         -1,
  18013         -1,
  18014     },
  18015 #endif /* chips */
  18016 
  18017 #if defined(BCM_88470_B0)
  18018     { /* SOC_REG_INT_OAMP_PE_FEM_MAP_BCM88470_B0r */
  18019         soc_block_list[22],
  18020         soc_genreg,
  18021         31,
  18022         0,
  18023         0x4fc,
  18024         SOC_REG_FLAG_ABOVE_64_BITS |
  18025                           SOC_REG_FLAG_ARRAY |
  18026                           SOC_REG_FLAG_REG_ARRAY,
  18027         0,
  18028         1,
  18029         soc_OAMP_PE_FEM_MAP_BCM88470_B0r_fields,
  18030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18032         -1,
  18033         -1,
  18034     },
  18035 #endif /* chips */
  18036 
  18037 #if defined(BCM_88690_A0)
  18038     { /* SOC_REG_INT_OAMP_PE_FEM_MAP_BCM88690_A0r */
  18039         soc_block_list[22],
  18040         soc_genreg,
  18041         31,
  18042         0,
  18043         0x5ed,
  18044         SOC_REG_FLAG_ABOVE_64_BITS |
  18045                           SOC_REG_FLAG_ARRAY |
  18046                           SOC_REG_FLAG_REG_ARRAY,
  18047         0,
  18048         1,
  18049         soc_OAMP_PE_FEM_MAP_BCM88690_A0r_fields,
  18050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18052         -1,
  18053         -1,
  18054     },
  18055 #endif /* chips */
  18056 
  18057 #if defined(BCM_88690_B0)
  18058     { /* SOC_REG_INT_OAMP_PE_FEM_MAP_BCM88690_B0r */
  18059         soc_block_list[22],
  18060         soc_genreg,
  18061         31,
  18062         0,
  18063         0x5ed,
  18064         SOC_REG_FLAG_ABOVE_64_BITS |
  18065                           SOC_REG_FLAG_ARRAY |
  18066                           SOC_REG_FLAG_REG_ARRAY,
  18067         0,
  18068         1,
  18069         soc_OAMP_PE_FEM_MAP_BCM88690_B0r_fields,
  18070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18072         -1,
  18073         -1,
  18074     },
  18075 #endif /* chips */
  18076 
  18077 #if defined(BCM_88660_A0)
  18078     { /* SOC_REG_INT_OAMP_PE_FIRST_INSTr */
  18079         soc_block_list[22],
  18080         soc_genreg,
  18081         1,
  18082         0,
  18083         0x500,
  18084         SOC_REG_FLAG_ABOVE_64_BITS |
  18085                           SOC_REG_FLAG_SIGNAL,
  18086         0,
  18087         18,
  18088         soc_OAMP_PE_FIRST_INSTr_fields,
  18089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18091         -1,
  18092         -1,
  18093     },
  18094 #endif /* chips */
  18095 
  18096 #if defined(BCM_88675_A0)
  18097     { /* SOC_REG_INT_OAMP_PE_INSTr */
  18098         soc_block_list[22],
  18099         soc_genreg,
  18100         1,
  18101         0,
  18102         0x4ef,
  18103         0,
  18104         0,
  18105         2,
  18106         soc_OAMP_PE_INSTr_fields,
  18107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18108         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  18109         -1,
  18110         -1,
  18111     },
  18112 #endif /* chips */
  18113 
  18114 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  18115     defined(BCM_56270_A0)
  18116     { /* SOC_REG_INT_OAMP_PE_INST_BCM56260_A0r */
  18117         soc_block_list[22],
  18118         soc_genreg,
  18119         1,
  18120         0,
  18121         0x2015d00,
  18122         0,
  18123         0,
  18124         2,
  18125         soc_OAMP_PE_INST_BCM56260_A0r_fields,
  18126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18127         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  18128         -1,
  18129         -1,
  18130     },
  18131 #endif /* chips */
  18132 
  18133 #if defined(BCM_88270_A0)
  18134     { /* SOC_REG_INT_OAMP_PE_INST_BCM88270_A0r */
  18135         soc_block_list[22],
  18136         soc_genreg,
  18137         1,
  18138         0,
  18139         0x4fb,
  18140         0,
  18141         0,
  18142         3,
  18143         soc_OAMP_PE_INST_BCM88270_A0r_fields,
  18144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18145         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  18146         -1,
  18147         -1,
  18148     },
  18149 #endif /* chips */
  18150 
  18151 #if defined(BCM_88375_A0)
  18152     { /* SOC_REG_INT_OAMP_PE_INST_BCM88375_A0r */
  18153         soc_block_list[22],
  18154         soc_genreg,
  18155         1,
  18156         0,
  18157         0x4ef,
  18158         0,
  18159         0,
  18160         2,
  18161         soc_OAMP_PE_INST_BCM88375_A0r_fields,
  18162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18163         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  18164         -1,
  18165         -1,
  18166     },
  18167 #endif /* chips */
  18168 
  18169 #if defined(BCM_88375_B0)
  18170     { /* SOC_REG_INT_OAMP_PE_INST_BCM88375_B0r */
  18171         soc_block_list[22],
  18172         soc_genreg,
  18173         1,
  18174         0,
  18175         0x4ef,
  18176         0,
  18177         0,
  18178         2,
  18179         soc_OAMP_PE_INST_BCM88375_B0r_fields,
  18180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18181         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  18182         -1,
  18183         -1,
  18184     },
  18185 #endif /* chips */
  18186 
  18187 #if defined(BCM_88470_A0)
  18188     { /* SOC_REG_INT_OAMP_PE_INST_BCM88470_A0r */
  18189         soc_block_list[22],
  18190         soc_genreg,
  18191         1,
  18192         0,
  18193         0x4fb,
  18194         0,
  18195         0,
  18196         3,
  18197         soc_OAMP_PE_INST_BCM88470_A0r_fields,
  18198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18199         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  18200         -1,
  18201         -1,
  18202     },
  18203 #endif /* chips */
  18204 
  18205 #if defined(BCM_88470_B0)
  18206     { /* SOC_REG_INT_OAMP_PE_INST_BCM88470_B0r */
  18207         soc_block_list[22],
  18208         soc_genreg,
  18209         1,
  18210         0,
  18211         0x4fb,
  18212         0,
  18213         0,
  18214         3,
  18215         soc_OAMP_PE_INST_BCM88470_B0r_fields,
  18216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18217         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  18218         -1,
  18219         -1,
  18220     },
  18221 #endif /* chips */
  18222 
  18223 #if defined(BCM_88675_B0)
  18224     { /* SOC_REG_INT_OAMP_PE_INST_BCM88675_B0r */
  18225         soc_block_list[22],
  18226         soc_genreg,
  18227         1,
  18228         0,
  18229         0x4ef,
  18230         0,
  18231         0,
  18232         2,
  18233         soc_OAMP_PE_INST_BCM88675_B0r_fields,
  18234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18235         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  18236         -1,
  18237         -1,
  18238     },
  18239 #endif /* chips */
  18240 
  18241 #if defined(BCM_88680_A0)
  18242     { /* SOC_REG_INT_OAMP_PE_INST_BCM88680_A0r */
  18243         soc_block_list[22],
  18244         soc_genreg,
  18245         1,
  18246         0,
  18247         0x4ef,
  18248         0,
  18249         0,
  18250         2,
  18251         soc_OAMP_PE_INST_BCM88680_A0r_fields,
  18252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18253         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  18254         -1,
  18255         -1,
  18256     },
  18257 #endif /* chips */
  18258 
  18259 #if defined(BCM_88690_A0)
  18260     { /* SOC_REG_INT_OAMP_PE_INST_BCM88690_A0r */
  18261         soc_block_list[22],
  18262         soc_genreg,
  18263         1,
  18264         0,
  18265         0x5ec,
  18266         0,
  18267         0,
  18268         3,
  18269         soc_OAMP_PE_INST_BCM88690_A0r_fields,
  18270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18271         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  18272         -1,
  18273         -1,
  18274     },
  18275 #endif /* chips */
  18276 
  18277 #if defined(BCM_88690_B0)
  18278     { /* SOC_REG_INT_OAMP_PE_INST_BCM88690_B0r */
  18279         soc_block_list[22],
  18280         soc_genreg,
  18281         1,
  18282         0,
  18283         0x5ec,
  18284         0,
  18285         0,
  18286         3,
  18287         soc_OAMP_PE_INST_BCM88690_B0r_fields,
  18288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18289         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  18290         -1,
  18291         -1,
  18292     },
  18293 #endif /* chips */
  18294 
  18295 #if defined(BCM_88675_A0)
  18296     { /* SOC_REG_INT_OAMP_PE_PROFr */
  18297         soc_block_list[22],
  18298         soc_genreg,
  18299         64,
  18300         0,
  18301         0x46f,
  18302         SOC_REG_FLAG_ARRAY |
  18303                           SOC_REG_FLAG_REG_ARRAY,
  18304         0,
  18305         8,
  18306         soc_OAMP_PE_PROFr_fields,
  18307         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18308         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18309         -1,
  18310         -1,
  18311     },
  18312 #endif /* chips */
  18313 
  18314 #if defined(BCM_88270_A0)
  18315     { /* SOC_REG_INT_OAMP_PE_PROF_BCM88270_A0r */
  18316         soc_block_list[22],
  18317         soc_genreg,
  18318         64,
  18319         0,
  18320         0x470,
  18321         SOC_REG_FLAG_ARRAY |
  18322                           SOC_REG_FLAG_REG_ARRAY,
  18323         0,
  18324         8,
  18325         soc_OAMP_PE_PROF_BCM88270_A0r_fields,
  18326         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18327         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18328         -1,
  18329         -1,
  18330     },
  18331 #endif /* chips */
  18332 
  18333 #if defined(BCM_88375_A0)
  18334     { /* SOC_REG_INT_OAMP_PE_PROF_BCM88375_A0r */
  18335         soc_block_list[22],
  18336         soc_genreg,
  18337         64,
  18338         0,
  18339         0x46f,
  18340         SOC_REG_FLAG_ARRAY |
  18341                           SOC_REG_FLAG_REG_ARRAY,
  18342         0,
  18343         8,
  18344         soc_OAMP_PE_PROF_BCM88375_A0r_fields,
  18345         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18346         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18347         -1,
  18348         -1,
  18349     },
  18350 #endif /* chips */
  18351 
  18352 #if defined(BCM_88375_B0)
  18353     { /* SOC_REG_INT_OAMP_PE_PROF_BCM88375_B0r */
  18354         soc_block_list[22],
  18355         soc_genreg,
  18356         64,
  18357         0,
  18358         0x46f,
  18359         SOC_REG_FLAG_ARRAY |
  18360                           SOC_REG_FLAG_REG_ARRAY,
  18361         0,
  18362         8,
  18363         soc_OAMP_PE_PROF_BCM88375_B0r_fields,
  18364         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18365         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18366         -1,
  18367         -1,
  18368     },
  18369 #endif /* chips */
  18370 
  18371 #if defined(BCM_88470_A0)
  18372     { /* SOC_REG_INT_OAMP_PE_PROF_BCM88470_A0r */
  18373         soc_block_list[22],
  18374         soc_genreg,
  18375         64,
  18376         0,
  18377         0x470,
  18378         SOC_REG_FLAG_ARRAY |
  18379                           SOC_REG_FLAG_REG_ARRAY,
  18380         0,
  18381         8,
  18382         soc_OAMP_PE_PROF_BCM88470_A0r_fields,
  18383         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18384         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18385         -1,
  18386         -1,
  18387     },
  18388 #endif /* chips */
  18389 
  18390 #if defined(BCM_88470_B0)
  18391     { /* SOC_REG_INT_OAMP_PE_PROF_BCM88470_B0r */
  18392         soc_block_list[22],
  18393         soc_genreg,
  18394         64,
  18395         0,
  18396         0x470,
  18397         SOC_REG_FLAG_ARRAY |
  18398                           SOC_REG_FLAG_REG_ARRAY,
  18399         0,
  18400         8,
  18401         soc_OAMP_PE_PROF_BCM88470_B0r_fields,
  18402         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18403         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18404         -1,
  18405         -1,
  18406     },
  18407 #endif /* chips */
  18408 
  18409 #if defined(BCM_88675_B0)
  18410     { /* SOC_REG_INT_OAMP_PE_PROF_BCM88675_B0r */
  18411         soc_block_list[22],
  18412         soc_genreg,
  18413         64,
  18414         0,
  18415         0x46f,
  18416         SOC_REG_FLAG_ARRAY |
  18417                           SOC_REG_FLAG_REG_ARRAY,
  18418         0,
  18419         8,
  18420         soc_OAMP_PE_PROF_BCM88675_B0r_fields,
  18421         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18422         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18423         -1,
  18424         -1,
  18425     },
  18426 #endif /* chips */
  18427 
  18428 #if defined(BCM_88680_A0)
  18429     { /* SOC_REG_INT_OAMP_PE_PROF_BCM88680_A0r */
  18430         soc_block_list[22],
  18431         soc_genreg,
  18432         64,
  18433         0,
  18434         0x46f,
  18435         SOC_REG_FLAG_ARRAY |
  18436                           SOC_REG_FLAG_REG_ARRAY,
  18437         0,
  18438         8,
  18439         soc_OAMP_PE_PROF_BCM88680_A0r_fields,
  18440         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18441         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18442         -1,
  18443         -1,
  18444     },
  18445 #endif /* chips */
  18446 
  18447 #if defined(BCM_88690_A0)
  18448     { /* SOC_REG_INT_OAMP_PE_PROF_BCM88690_A0r */
  18449         soc_block_list[22],
  18450         soc_genreg,
  18451         64,
  18452         0,
  18453         0x561,
  18454         SOC_REG_FLAG_ARRAY |
  18455                           SOC_REG_FLAG_REG_ARRAY,
  18456         0,
  18457         8,
  18458         soc_OAMP_PE_PROF_BCM88690_A0r_fields,
  18459         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18460         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18461         -1,
  18462         -1,
  18463     },
  18464 #endif /* chips */
  18465 
  18466 #if defined(BCM_88690_B0)
  18467     { /* SOC_REG_INT_OAMP_PE_PROF_BCM88690_B0r */
  18468         soc_block_list[22],
  18469         soc_genreg,
  18470         64,
  18471         0,
  18472         0x561,
  18473         SOC_REG_FLAG_ARRAY |
  18474                           SOC_REG_FLAG_REG_ARRAY,
  18475         0,
  18476         8,
  18477         soc_OAMP_PE_PROF_BCM88690_B0r_fields,
  18478         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  18479         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  18480         -1,
  18481         -1,
  18482     },
  18483 #endif /* chips */
  18484 
  18485 #if defined(BCM_88675_A0)
  18486     { /* SOC_REG_INT_OAMP_PE_PTRr */
  18487         soc_block_list[22],
  18488         soc_genreg,
  18489         32,
  18490         0,
  18491         0x4cf,
  18492         SOC_REG_FLAG_ARRAY |
  18493                           SOC_REG_FLAG_REG_ARRAY,
  18494         0,
  18495         1,
  18496         soc_OAMP_PE_PTRr_fields,
  18497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18498         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  18499         -1,
  18500         -1,
  18501     },
  18502 #endif /* chips */
  18503 
  18504 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  18505     defined(BCM_56270_A0)
  18506     { /* SOC_REG_INT_OAMP_PE_PTR_BCM56260_A0r */
  18507         soc_block_list[22],
  18508         soc_genreg,
  18509         32,
  18510         0,
  18511         0x2013d00,
  18512         SOC_REG_FLAG_ARRAY |
  18513                           SOC_REG_FLAG_REG_ARRAY,
  18514         0,
  18515         1,
  18516         soc_OAMP_PE_PTR_BCM56260_A0r_fields,
  18517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18518         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  18519         -1,
  18520         -1,
  18521     },
  18522 #endif /* chips */
  18523 
  18524 #if defined(BCM_88270_A0)
  18525     { /* SOC_REG_INT_OAMP_PE_PTR_BCM88270_A0r */
  18526         soc_block_list[22],
  18527         soc_genreg,
  18528         32,
  18529         0,
  18530         0x4db,
  18531         SOC_REG_FLAG_ARRAY |
  18532                           SOC_REG_FLAG_REG_ARRAY,
  18533         0,
  18534         1,
  18535         soc_OAMP_PE_PTR_BCM88270_A0r_fields,
  18536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18537         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  18538         -1,
  18539         -1,
  18540     },
  18541 #endif /* chips */
  18542 
  18543 #if defined(BCM_88375_A0)
  18544     { /* SOC_REG_INT_OAMP_PE_PTR_BCM88375_A0r */
  18545         soc_block_list[22],
  18546         soc_genreg,
  18547         32,
  18548         0,
  18549         0x4cf,
  18550         SOC_REG_FLAG_ARRAY |
  18551                           SOC_REG_FLAG_REG_ARRAY,
  18552         0,
  18553         1,
  18554         soc_OAMP_PE_PTR_BCM88375_A0r_fields,
  18555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18556         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  18557         -1,
  18558         -1,
  18559     },
  18560 #endif /* chips */
  18561 
  18562 #if defined(BCM_88375_B0)
  18563     { /* SOC_REG_INT_OAMP_PE_PTR_BCM88375_B0r */
  18564         soc_block_list[22],
  18565         soc_genreg,
  18566         32,
  18567         0,
  18568         0x4cf,
  18569         SOC_REG_FLAG_ARRAY |
  18570                           SOC_REG_FLAG_REG_ARRAY,
  18571         0,
  18572         1,
  18573         soc_OAMP_PE_PTR_BCM88375_B0r_fields,
  18574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18575         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  18576         -1,
  18577         -1,
  18578     },
  18579 #endif /* chips */
  18580 
  18581 #if defined(BCM_88470_A0)
  18582     { /* SOC_REG_INT_OAMP_PE_PTR_BCM88470_A0r */
  18583         soc_block_list[22],
  18584         soc_genreg,
  18585         32,
  18586         0,
  18587         0x4db,
  18588         SOC_REG_FLAG_ARRAY |
  18589                           SOC_REG_FLAG_REG_ARRAY,
  18590         0,
  18591         1,
  18592         soc_OAMP_PE_PTR_BCM88470_A0r_fields,
  18593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18594         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  18595         -1,
  18596         -1,
  18597     },
  18598 #endif /* chips */
  18599 
  18600 #if defined(BCM_88470_B0)
  18601     { /* SOC_REG_INT_OAMP_PE_PTR_BCM88470_B0r */
  18602         soc_block_list[22],
  18603         soc_genreg,
  18604         32,
  18605         0,
  18606         0x4db,
  18607         SOC_REG_FLAG_ARRAY |
  18608                           SOC_REG_FLAG_REG_ARRAY,
  18609         0,
  18610         1,
  18611         soc_OAMP_PE_PTR_BCM88470_B0r_fields,
  18612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18613         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  18614         -1,
  18615         -1,
  18616     },
  18617 #endif /* chips */
  18618 
  18619 #if defined(BCM_88675_B0)
  18620     { /* SOC_REG_INT_OAMP_PE_PTR_BCM88675_B0r */
  18621         soc_block_list[22],
  18622         soc_genreg,
  18623         32,
  18624         0,
  18625         0x4cf,
  18626         SOC_REG_FLAG_ARRAY |
  18627                           SOC_REG_FLAG_REG_ARRAY,
  18628         0,
  18629         1,
  18630         soc_OAMP_PE_PTR_BCM88675_B0r_fields,
  18631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18632         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  18633         -1,
  18634         -1,
  18635     },
  18636 #endif /* chips */
  18637 
  18638 #if defined(BCM_88680_A0)
  18639     { /* SOC_REG_INT_OAMP_PE_PTR_BCM88680_A0r */
  18640         soc_block_list[22],
  18641         soc_genreg,
  18642         32,
  18643         0,
  18644         0x4cf,
  18645         SOC_REG_FLAG_ARRAY |
  18646                           SOC_REG_FLAG_REG_ARRAY,
  18647         0,
  18648         1,
  18649         soc_OAMP_PE_PTR_BCM88680_A0r_fields,
  18650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18651         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  18652         -1,
  18653         -1,
  18654     },
  18655 #endif /* chips */
  18656 
  18657 #if defined(BCM_88690_A0)
  18658     { /* SOC_REG_INT_OAMP_PE_PTR_BCM88690_A0r */
  18659         soc_block_list[22],
  18660         soc_genreg,
  18661         32,
  18662         0,
  18663         0x5cc,
  18664         SOC_REG_FLAG_ARRAY |
  18665                           SOC_REG_FLAG_REG_ARRAY,
  18666         0,
  18667         1,
  18668         soc_OAMP_PE_PTR_BCM88690_A0r_fields,
  18669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18670         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  18671         -1,
  18672         -1,
  18673     },
  18674 #endif /* chips */
  18675 
  18676 #if defined(BCM_88690_B0)
  18677     { /* SOC_REG_INT_OAMP_PE_PTR_BCM88690_B0r */
  18678         soc_block_list[22],
  18679         soc_genreg,
  18680         32,
  18681         0,
  18682         0x5cc,
  18683         SOC_REG_FLAG_ARRAY |
  18684                           SOC_REG_FLAG_REG_ARRAY,
  18685         0,
  18686         1,
  18687         soc_OAMP_PE_PTR_BCM88690_B0r_fields,
  18688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18689         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  18690         -1,
  18691         -1,
  18692     },
  18693 #endif /* chips */
  18694 
  18695 #if defined(BCM_88675_A0)
  18696     { /* SOC_REG_INT_OAMP_PE_STATUSr */
  18697         soc_block_list[22],
  18698         soc_genreg,
  18699         1,
  18700         0,
  18701         0x511,
  18702         SOC_REG_FLAG_ABOVE_64_BITS |
  18703                           SOC_REG_FLAG_RO,
  18704         0,
  18705         8,
  18706         soc_OAMP_PE_STATUSr_fields,
  18707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18708         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18709         -1,
  18710         -1,
  18711     },
  18712 #endif /* chips */
  18713 
  18714 #if defined(BCM_88470_A0)
  18715     { /* SOC_REG_INT_OAMP_PE_STATUS_1r */
  18716         soc_block_list[22],
  18717         soc_genreg,
  18718         1,
  18719         0,
  18720         0x559,
  18721         SOC_REG_FLAG_ABOVE_64_BITS |
  18722                           SOC_REG_FLAG_RO,
  18723         0,
  18724         5,
  18725         soc_OAMP_PE_STATUS_1r_fields,
  18726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18727         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18728         -1,
  18729         -1,
  18730     },
  18731 #endif /* chips */
  18732 
  18733 #if defined(BCM_88470_A0)
  18734     { /* SOC_REG_INT_OAMP_PE_STATUS_2r */
  18735         soc_block_list[22],
  18736         soc_genreg,
  18737         1,
  18738         0,
  18739         0x55e,
  18740         SOC_REG_FLAG_ABOVE_64_BITS |
  18741                           SOC_REG_FLAG_RO,
  18742         0,
  18743         5,
  18744         soc_OAMP_PE_STATUS_2r_fields,
  18745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18746         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18747         -1,
  18748         -1,
  18749     },
  18750 #endif /* chips */
  18751 
  18752 #if defined(BCM_88270_A0)
  18753     { /* SOC_REG_INT_OAMP_PE_STATUS_1_BCM88270_A0r */
  18754         soc_block_list[22],
  18755         soc_genreg,
  18756         1,
  18757         0,
  18758         0x559,
  18759         SOC_REG_FLAG_ABOVE_64_BITS |
  18760                           SOC_REG_FLAG_RO,
  18761         0,
  18762         5,
  18763         soc_OAMP_PE_STATUS_1_BCM88270_A0r_fields,
  18764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18765         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18766         -1,
  18767         -1,
  18768     },
  18769 #endif /* chips */
  18770 
  18771 #if defined(BCM_88470_B0)
  18772     { /* SOC_REG_INT_OAMP_PE_STATUS_1_BCM88470_B0r */
  18773         soc_block_list[22],
  18774         soc_genreg,
  18775         1,
  18776         0,
  18777         0x559,
  18778         SOC_REG_FLAG_ABOVE_64_BITS |
  18779                           SOC_REG_FLAG_RO,
  18780         0,
  18781         5,
  18782         soc_OAMP_PE_STATUS_1_BCM88470_B0r_fields,
  18783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18784         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18785         -1,
  18786         -1,
  18787     },
  18788 #endif /* chips */
  18789 
  18790 #if defined(BCM_88690_A0)
  18791     { /* SOC_REG_INT_OAMP_PE_STATUS_1_BCM88690_A0r */
  18792         soc_block_list[22],
  18793         soc_genreg,
  18794         1,
  18795         0,
  18796         0x64a,
  18797         SOC_REG_FLAG_ABOVE_64_BITS |
  18798                           SOC_REG_FLAG_RO,
  18799         0,
  18800         5,
  18801         soc_OAMP_PE_STATUS_1_BCM88690_A0r_fields,
  18802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18803         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18804         -1,
  18805         -1,
  18806     },
  18807 #endif /* chips */
  18808 
  18809 #if defined(BCM_88690_B0)
  18810     { /* SOC_REG_INT_OAMP_PE_STATUS_1_BCM88690_B0r */
  18811         soc_block_list[22],
  18812         soc_genreg,
  18813         1,
  18814         0,
  18815         0x64a,
  18816         SOC_REG_FLAG_ABOVE_64_BITS |
  18817                           SOC_REG_FLAG_RO,
  18818         0,
  18819         5,
  18820         soc_OAMP_PE_STATUS_1_BCM88690_B0r_fields,
  18821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18822         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18823         -1,
  18824         -1,
  18825     },
  18826 #endif /* chips */
  18827 
  18828 #if defined(BCM_88270_A0)
  18829     { /* SOC_REG_INT_OAMP_PE_STATUS_2_BCM88270_A0r */
  18830         soc_block_list[22],
  18831         soc_genreg,
  18832         1,
  18833         0,
  18834         0x55e,
  18835         SOC_REG_FLAG_ABOVE_64_BITS |
  18836                           SOC_REG_FLAG_RO,
  18837         0,
  18838         5,
  18839         soc_OAMP_PE_STATUS_2_BCM88270_A0r_fields,
  18840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18841         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18842         -1,
  18843         -1,
  18844     },
  18845 #endif /* chips */
  18846 
  18847 #if defined(BCM_88470_B0)
  18848     { /* SOC_REG_INT_OAMP_PE_STATUS_2_BCM88470_B0r */
  18849         soc_block_list[22],
  18850         soc_genreg,
  18851         1,
  18852         0,
  18853         0x55e,
  18854         SOC_REG_FLAG_ABOVE_64_BITS |
  18855                           SOC_REG_FLAG_RO,
  18856         0,
  18857         5,
  18858         soc_OAMP_PE_STATUS_2_BCM88470_B0r_fields,
  18859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18860         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18861         -1,
  18862         -1,
  18863     },
  18864 #endif /* chips */
  18865 
  18866 #if defined(BCM_88690_A0)
  18867     { /* SOC_REG_INT_OAMP_PE_STATUS_2_BCM88690_A0r */
  18868         soc_block_list[22],
  18869         soc_genreg,
  18870         1,
  18871         0,
  18872         0x64f,
  18873         SOC_REG_FLAG_ABOVE_64_BITS |
  18874                           SOC_REG_FLAG_RO,
  18875         0,
  18876         5,
  18877         soc_OAMP_PE_STATUS_2_BCM88690_A0r_fields,
  18878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18879         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18880         -1,
  18881         -1,
  18882     },
  18883 #endif /* chips */
  18884 
  18885 #if defined(BCM_88690_B0)
  18886     { /* SOC_REG_INT_OAMP_PE_STATUS_2_BCM88690_B0r */
  18887         soc_block_list[22],
  18888         soc_genreg,
  18889         1,
  18890         0,
  18891         0x64f,
  18892         SOC_REG_FLAG_ABOVE_64_BITS |
  18893                           SOC_REG_FLAG_RO,
  18894         0,
  18895         5,
  18896         soc_OAMP_PE_STATUS_2_BCM88690_B0r_fields,
  18897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18899         -1,
  18900         -1,
  18901     },
  18902 #endif /* chips */
  18903 
  18904 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  18905     defined(BCM_56270_A0)
  18906     { /* SOC_REG_INT_OAMP_PE_STATUS_BCM56260_A0r */
  18907         soc_block_list[22],
  18908         soc_genreg,
  18909         1,
  18910         0,
  18911         0x2017f00,
  18912         SOC_REG_FLAG_ABOVE_64_BITS |
  18913                           SOC_REG_FLAG_RO,
  18914         0,
  18915         8,
  18916         soc_OAMP_PE_STATUS_BCM56260_A0r_fields,
  18917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18919         -1,
  18920         -1,
  18921     },
  18922 #endif /* chips */
  18923 
  18924 #if defined(BCM_88375_A0)
  18925     { /* SOC_REG_INT_OAMP_PE_STATUS_BCM88375_A0r */
  18926         soc_block_list[22],
  18927         soc_genreg,
  18928         1,
  18929         0,
  18930         0x511,
  18931         SOC_REG_FLAG_ABOVE_64_BITS |
  18932                           SOC_REG_FLAG_RO,
  18933         0,
  18934         8,
  18935         soc_OAMP_PE_STATUS_BCM88375_A0r_fields,
  18936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18938         -1,
  18939         -1,
  18940     },
  18941 #endif /* chips */
  18942 
  18943 #if defined(BCM_88375_B0)
  18944     { /* SOC_REG_INT_OAMP_PE_STATUS_BCM88375_B0r */
  18945         soc_block_list[22],
  18946         soc_genreg,
  18947         1,
  18948         0,
  18949         0x511,
  18950         SOC_REG_FLAG_ABOVE_64_BITS |
  18951                           SOC_REG_FLAG_RO,
  18952         0,
  18953         8,
  18954         soc_OAMP_PE_STATUS_BCM88375_B0r_fields,
  18955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18956         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18957         -1,
  18958         -1,
  18959     },
  18960 #endif /* chips */
  18961 
  18962 #if defined(BCM_88675_B0)
  18963     { /* SOC_REG_INT_OAMP_PE_STATUS_BCM88675_B0r */
  18964         soc_block_list[22],
  18965         soc_genreg,
  18966         1,
  18967         0,
  18968         0x511,
  18969         SOC_REG_FLAG_ABOVE_64_BITS |
  18970                           SOC_REG_FLAG_RO,
  18971         0,
  18972         8,
  18973         soc_OAMP_PE_STATUS_BCM88675_B0r_fields,
  18974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18976         -1,
  18977         -1,
  18978     },
  18979 #endif /* chips */
  18980 
  18981 #if defined(BCM_88680_A0)
  18982     { /* SOC_REG_INT_OAMP_PE_STATUS_BCM88680_A0r */
  18983         soc_block_list[22],
  18984         soc_genreg,
  18985         1,
  18986         0,
  18987         0x511,
  18988         SOC_REG_FLAG_ABOVE_64_BITS |
  18989                           SOC_REG_FLAG_RO,
  18990         0,
  18991         8,
  18992         soc_OAMP_PE_STATUS_BCM88680_A0r_fields,
  18993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18994         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18995         -1,
  18996         -1,
  18997     },
  18998 #endif /* chips */
  18999 
  19000 #if defined(BCM_88660_A0)
  19001     { /* SOC_REG_INT_OAMP_PORT_STAT_TLVr */
  19002         soc_block_list[22],
  19003         soc_genreg,
  19004         1,
  19005         0,
  19006         0x438,
  19007         SOC_REG_FLAG_SIGNAL,
  19008         0,
  19009         1,
  19010         soc_OAMP_PORT_STAT_TLVr_fields,
  19011         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19012         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19013         -1,
  19014         -1,
  19015     },
  19016 #endif /* chips */
  19017 
  19018 #if defined(BCM_88270_A0)
  19019     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88270_A0r */
  19020         soc_block_list[22],
  19021         soc_genreg,
  19022         1,
  19023         0,
  19024         0x440,
  19025         0,
  19026         0,
  19027         1,
  19028         soc_OAMP_PORT_STAT_TLV_BCM88270_A0r_fields,
  19029         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19030         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19031         -1,
  19032         -1,
  19033     },
  19034 #endif /* chips */
  19035 
  19036 #if defined(BCM_88375_A0)
  19037     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88375_A0r */
  19038         soc_block_list[22],
  19039         soc_genreg,
  19040         1,
  19041         0,
  19042         0x43d,
  19043         0,
  19044         0,
  19045         1,
  19046         soc_OAMP_PORT_STAT_TLV_BCM88375_A0r_fields,
  19047         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19048         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19049         -1,
  19050         -1,
  19051     },
  19052 #endif /* chips */
  19053 
  19054 #if defined(BCM_88375_B0)
  19055     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88375_B0r */
  19056         soc_block_list[22],
  19057         soc_genreg,
  19058         1,
  19059         0,
  19060         0x43d,
  19061         0,
  19062         0,
  19063         1,
  19064         soc_OAMP_PORT_STAT_TLV_BCM88375_B0r_fields,
  19065         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19066         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19067         -1,
  19068         -1,
  19069     },
  19070 #endif /* chips */
  19071 
  19072 #if defined(BCM_88470_A0)
  19073     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88470_A0r */
  19074         soc_block_list[22],
  19075         soc_genreg,
  19076         1,
  19077         0,
  19078         0x440,
  19079         0,
  19080         0,
  19081         1,
  19082         soc_OAMP_PORT_STAT_TLV_BCM88470_A0r_fields,
  19083         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19084         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19085         -1,
  19086         -1,
  19087     },
  19088 #endif /* chips */
  19089 
  19090 #if defined(BCM_88470_B0)
  19091     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88470_B0r */
  19092         soc_block_list[22],
  19093         soc_genreg,
  19094         1,
  19095         0,
  19096         0x440,
  19097         0,
  19098         0,
  19099         1,
  19100         soc_OAMP_PORT_STAT_TLV_BCM88470_B0r_fields,
  19101         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19102         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19103         -1,
  19104         -1,
  19105     },
  19106 #endif /* chips */
  19107 
  19108 #if defined(BCM_88675_A0)
  19109     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88675_A0r */
  19110         soc_block_list[22],
  19111         soc_genreg,
  19112         1,
  19113         0,
  19114         0x43d,
  19115         0,
  19116         0,
  19117         1,
  19118         soc_OAMP_PORT_STAT_TLV_BCM88675_A0r_fields,
  19119         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19120         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19121         -1,
  19122         -1,
  19123     },
  19124 #endif /* chips */
  19125 
  19126 #if defined(BCM_88675_B0)
  19127     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88675_B0r */
  19128         soc_block_list[22],
  19129         soc_genreg,
  19130         1,
  19131         0,
  19132         0x43d,
  19133         0,
  19134         0,
  19135         1,
  19136         soc_OAMP_PORT_STAT_TLV_BCM88675_B0r_fields,
  19137         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19138         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19139         -1,
  19140         -1,
  19141     },
  19142 #endif /* chips */
  19143 
  19144 #if defined(BCM_88680_A0)
  19145     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88680_A0r */
  19146         soc_block_list[22],
  19147         soc_genreg,
  19148         1,
  19149         0,
  19150         0x43d,
  19151         0,
  19152         0,
  19153         1,
  19154         soc_OAMP_PORT_STAT_TLV_BCM88680_A0r_fields,
  19155         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19156         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19157         -1,
  19158         -1,
  19159     },
  19160 #endif /* chips */
  19161 
  19162 #if defined(BCM_88690_A0)
  19163     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88690_A0r */
  19164         soc_block_list[22],
  19165         soc_genreg,
  19166         1,
  19167         0,
  19168         0x530,
  19169         0,
  19170         0,
  19171         1,
  19172         soc_OAMP_PORT_STAT_TLV_BCM88690_A0r_fields,
  19173         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19174         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19175         -1,
  19176         -1,
  19177     },
  19178 #endif /* chips */
  19179 
  19180 #if defined(BCM_88690_B0)
  19181     { /* SOC_REG_INT_OAMP_PORT_STAT_TLV_BCM88690_B0r */
  19182         soc_block_list[22],
  19183         soc_genreg,
  19184         1,
  19185         0,
  19186         0x530,
  19187         0,
  19188         0,
  19189         1,
  19190         soc_OAMP_PORT_STAT_TLV_BCM88690_B0r_fields,
  19191         SOC_RESET_VAL_DEC(0x00020001, 0x00000000)
  19192         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19193         -1,
  19194         -1,
  19195     },
  19196 #endif /* chips */
  19197 
  19198 #if defined(BCM_88660_A0)
  19199     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONFr */
  19200         soc_block_list[22],
  19201         soc_genreg,
  19202         1,
  19203         0,
  19204         0x554,
  19205         0,
  19206         0,
  19207         2,
  19208         soc_OAMP_PROTECTION_PACKET_CONFr_fields,
  19209         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19210         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  19211         -1,
  19212         -1,
  19213     },
  19214 #endif /* chips */
  19215 
  19216 #if defined(BCM_88270_A0)
  19217     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88270_A0r */
  19218         soc_block_list[22],
  19219         soc_genreg,
  19220         1,
  19221         0,
  19222         0x577,
  19223         0,
  19224         0,
  19225         3,
  19226         soc_OAMP_PROTECTION_PACKET_CONF_BCM88270_A0r_fields,
  19227         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19228         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19229         -1,
  19230         -1,
  19231     },
  19232 #endif /* chips */
  19233 
  19234 #if defined(BCM_88375_A0)
  19235     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88375_A0r */
  19236         soc_block_list[22],
  19237         soc_genreg,
  19238         1,
  19239         0,
  19240         0x528,
  19241         0,
  19242         0,
  19243         3,
  19244         soc_OAMP_PROTECTION_PACKET_CONF_BCM88375_A0r_fields,
  19245         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19246         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19247         -1,
  19248         -1,
  19249     },
  19250 #endif /* chips */
  19251 
  19252 #if defined(BCM_88375_B0)
  19253     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88375_B0r */
  19254         soc_block_list[22],
  19255         soc_genreg,
  19256         1,
  19257         0,
  19258         0x528,
  19259         0,
  19260         0,
  19261         3,
  19262         soc_OAMP_PROTECTION_PACKET_CONF_BCM88375_B0r_fields,
  19263         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19264         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19265         -1,
  19266         -1,
  19267     },
  19268 #endif /* chips */
  19269 
  19270 #if defined(BCM_88470_A0)
  19271     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88470_A0r */
  19272         soc_block_list[22],
  19273         soc_genreg,
  19274         1,
  19275         0,
  19276         0x577,
  19277         0,
  19278         0,
  19279         3,
  19280         soc_OAMP_PROTECTION_PACKET_CONF_BCM88470_A0r_fields,
  19281         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19282         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19283         -1,
  19284         -1,
  19285     },
  19286 #endif /* chips */
  19287 
  19288 #if defined(BCM_88470_B0)
  19289     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88470_B0r */
  19290         soc_block_list[22],
  19291         soc_genreg,
  19292         1,
  19293         0,
  19294         0x577,
  19295         0,
  19296         0,
  19297         3,
  19298         soc_OAMP_PROTECTION_PACKET_CONF_BCM88470_B0r_fields,
  19299         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19300         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19301         -1,
  19302         -1,
  19303     },
  19304 #endif /* chips */
  19305 
  19306 #if defined(BCM_88675_A0)
  19307     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88675_A0r */
  19308         soc_block_list[22],
  19309         soc_genreg,
  19310         1,
  19311         0,
  19312         0x528,
  19313         0,
  19314         0,
  19315         3,
  19316         soc_OAMP_PROTECTION_PACKET_CONF_BCM88675_A0r_fields,
  19317         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19318         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19319         -1,
  19320         -1,
  19321     },
  19322 #endif /* chips */
  19323 
  19324 #if defined(BCM_88675_B0)
  19325     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88675_B0r */
  19326         soc_block_list[22],
  19327         soc_genreg,
  19328         1,
  19329         0,
  19330         0x528,
  19331         0,
  19332         0,
  19333         3,
  19334         soc_OAMP_PROTECTION_PACKET_CONF_BCM88675_B0r_fields,
  19335         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19336         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19337         -1,
  19338         -1,
  19339     },
  19340 #endif /* chips */
  19341 
  19342 #if defined(BCM_88680_A0)
  19343     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88680_A0r */
  19344         soc_block_list[22],
  19345         soc_genreg,
  19346         1,
  19347         0,
  19348         0x528,
  19349         0,
  19350         0,
  19351         3,
  19352         soc_OAMP_PROTECTION_PACKET_CONF_BCM88680_A0r_fields,
  19353         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19354         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19355         -1,
  19356         -1,
  19357     },
  19358 #endif /* chips */
  19359 
  19360 #if defined(BCM_88690_A0)
  19361     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88690_A0r */
  19362         soc_block_list[22],
  19363         soc_genreg,
  19364         1,
  19365         0,
  19366         0x668,
  19367         0,
  19368         0,
  19369         3,
  19370         soc_OAMP_PROTECTION_PACKET_CONF_BCM88690_A0r_fields,
  19371         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19372         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19373         -1,
  19374         -1,
  19375     },
  19376 #endif /* chips */
  19377 
  19378 #if defined(BCM_88690_B0)
  19379     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_CONF_BCM88690_B0r */
  19380         soc_block_list[22],
  19381         soc_genreg,
  19382         1,
  19383         0,
  19384         0x668,
  19385         0,
  19386         0,
  19387         3,
  19388         soc_OAMP_PROTECTION_PACKET_CONF_BCM88690_B0r_fields,
  19389         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19390         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19391         -1,
  19392         -1,
  19393     },
  19394 #endif /* chips */
  19395 
  19396 #if defined(BCM_88650_A0)
  19397     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADERr */
  19398         soc_block_list[22],
  19399         soc_genreg,
  19400         1,
  19401         0,
  19402         0x240,
  19403         SOC_REG_FLAG_ABOVE_64_BITS |
  19404                           SOC_REG_FLAG_SIGNAL,
  19405         0,
  19406         1,
  19407         soc_OAMP_PROTECTION_PACKET_HEADERr_fields,
  19408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19409         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19410         -1,
  19411         -1,
  19412     },
  19413 #endif /* chips */
  19414 
  19415 #if defined(BCM_88270_A0)
  19416     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88270_A0r */
  19417         soc_block_list[22],
  19418         soc_genreg,
  19419         1,
  19420         0,
  19421         0x563,
  19422         SOC_REG_FLAG_ABOVE_64_BITS,
  19423         0,
  19424         1,
  19425         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88270_A0r_fields,
  19426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19427         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19428         -1,
  19429         -1,
  19430     },
  19431 #endif /* chips */
  19432 
  19433 #if defined(BCM_88375_A0)
  19434     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88375_A0r */
  19435         soc_block_list[22],
  19436         soc_genreg,
  19437         1,
  19438         0,
  19439         0x514,
  19440         SOC_REG_FLAG_ABOVE_64_BITS,
  19441         0,
  19442         1,
  19443         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88375_A0r_fields,
  19444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19446         -1,
  19447         -1,
  19448     },
  19449 #endif /* chips */
  19450 
  19451 #if defined(BCM_88375_B0)
  19452     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88375_B0r */
  19453         soc_block_list[22],
  19454         soc_genreg,
  19455         1,
  19456         0,
  19457         0x514,
  19458         SOC_REG_FLAG_ABOVE_64_BITS,
  19459         0,
  19460         1,
  19461         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88375_B0r_fields,
  19462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19464         -1,
  19465         -1,
  19466     },
  19467 #endif /* chips */
  19468 
  19469 #if defined(BCM_88470_A0)
  19470     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88470_A0r */
  19471         soc_block_list[22],
  19472         soc_genreg,
  19473         1,
  19474         0,
  19475         0x563,
  19476         SOC_REG_FLAG_ABOVE_64_BITS,
  19477         0,
  19478         1,
  19479         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88470_A0r_fields,
  19480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19482         -1,
  19483         -1,
  19484     },
  19485 #endif /* chips */
  19486 
  19487 #if defined(BCM_88470_B0)
  19488     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88470_B0r */
  19489         soc_block_list[22],
  19490         soc_genreg,
  19491         1,
  19492         0,
  19493         0x563,
  19494         SOC_REG_FLAG_ABOVE_64_BITS,
  19495         0,
  19496         1,
  19497         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88470_B0r_fields,
  19498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19499         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19500         -1,
  19501         -1,
  19502     },
  19503 #endif /* chips */
  19504 
  19505 #if defined(BCM_88650_B0)
  19506     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88650_B0r */
  19507         soc_block_list[22],
  19508         soc_genreg,
  19509         1,
  19510         0,
  19511         0x240,
  19512         SOC_REG_FLAG_ABOVE_64_BITS |
  19513                           SOC_REG_FLAG_SIGNAL,
  19514         0,
  19515         1,
  19516         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88650_B0r_fields,
  19517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19518         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19519         -1,
  19520         -1,
  19521     },
  19522 #endif /* chips */
  19523 
  19524 #if defined(BCM_88660_A0)
  19525     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88660_A0r */
  19526         soc_block_list[22],
  19527         soc_genreg,
  19528         1,
  19529         0,
  19530         0x540,
  19531         SOC_REG_FLAG_ABOVE_64_BITS |
  19532                           SOC_REG_FLAG_SIGNAL,
  19533         0,
  19534         1,
  19535         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88660_A0r_fields,
  19536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19538         -1,
  19539         -1,
  19540     },
  19541 #endif /* chips */
  19542 
  19543 #if defined(BCM_88675_A0)
  19544     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88675_A0r */
  19545         soc_block_list[22],
  19546         soc_genreg,
  19547         1,
  19548         0,
  19549         0x514,
  19550         SOC_REG_FLAG_ABOVE_64_BITS,
  19551         0,
  19552         1,
  19553         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88675_A0r_fields,
  19554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19556         -1,
  19557         -1,
  19558     },
  19559 #endif /* chips */
  19560 
  19561 #if defined(BCM_88675_B0)
  19562     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88675_B0r */
  19563         soc_block_list[22],
  19564         soc_genreg,
  19565         1,
  19566         0,
  19567         0x514,
  19568         SOC_REG_FLAG_ABOVE_64_BITS,
  19569         0,
  19570         1,
  19571         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88675_B0r_fields,
  19572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19574         -1,
  19575         -1,
  19576     },
  19577 #endif /* chips */
  19578 
  19579 #if defined(BCM_88680_A0)
  19580     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88680_A0r */
  19581         soc_block_list[22],
  19582         soc_genreg,
  19583         1,
  19584         0,
  19585         0x514,
  19586         SOC_REG_FLAG_ABOVE_64_BITS,
  19587         0,
  19588         1,
  19589         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88680_A0r_fields,
  19590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19592         -1,
  19593         -1,
  19594     },
  19595 #endif /* chips */
  19596 
  19597 #if defined(BCM_88690_A0)
  19598     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88690_A0r */
  19599         soc_block_list[22],
  19600         soc_genreg,
  19601         1,
  19602         0,
  19603         0x654,
  19604         SOC_REG_FLAG_ABOVE_64_BITS,
  19605         0,
  19606         1,
  19607         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88690_A0r_fields,
  19608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19609         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19610         -1,
  19611         -1,
  19612     },
  19613 #endif /* chips */
  19614 
  19615 #if defined(BCM_88690_B0)
  19616     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_BCM88690_B0r */
  19617         soc_block_list[22],
  19618         soc_genreg,
  19619         1,
  19620         0,
  19621         0x654,
  19622         SOC_REG_FLAG_ABOVE_64_BITS,
  19623         0,
  19624         1,
  19625         soc_OAMP_PROTECTION_PACKET_HEADER_BCM88690_B0r_fields,
  19626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19628         -1,
  19629         -1,
  19630     },
  19631 #endif /* chips */
  19632 
  19633 #if defined(BCM_88650_A0)
  19634     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_NUM_OF_BYTESr */
  19635         soc_block_list[22],
  19636         soc_genreg,
  19637         1,
  19638         0,
  19639         0x254,
  19640         SOC_REG_FLAG_SIGNAL,
  19641         0,
  19642         1,
  19643         soc_OAMP_PROTECTION_PACKET_HEADER_NUM_OF_BYTESr_fields,
  19644         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19645         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19646         -1,
  19647         -1,
  19648     },
  19649 #endif /* chips */
  19650 
  19651 #if defined(BCM_88650_B0)
  19652     { /* SOC_REG_INT_OAMP_PROTECTION_PACKET_HEADER_NUM_OF_BYTES_BCM88650_B0r */
  19653         soc_block_list[22],
  19654         soc_genreg,
  19655         1,
  19656         0,
  19657         0x254,
  19658         SOC_REG_FLAG_SIGNAL,
  19659         0,
  19660         1,
  19661         soc_OAMP_PROTECTION_PACKET_HEADER_NUM_OF_BYTES_BCM88650_B0r_fields,
  19662         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  19663         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19664         -1,
  19665         -1,
  19666     },
  19667 #endif /* chips */
  19668 
  19669 #if defined(BCM_88650_A0)
  19670     { /* SOC_REG_INT_OAMP_PR_2_FWDDPr */
  19671         soc_block_list[22],
  19672         soc_genreg,
  19673         1,
  19674         0,
  19675         0x10f,
  19676         SOC_REG_FLAG_SIGNAL,
  19677         0,
  19678         8,
  19679         soc_OAMP_PR_2_FWDDPr_fields,
  19680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19681         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19682         -1,
  19683         -1,
  19684     },
  19685 #endif /* chips */
  19686 
  19687 #if defined(BCM_88270_A0)
  19688     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88270_A0r */
  19689         soc_block_list[22],
  19690         soc_genreg,
  19691         1,
  19692         0,
  19693         0x10f,
  19694         0,
  19695         0,
  19696         8,
  19697         soc_OAMP_PR_2_FWDDP_BCM88270_A0r_fields,
  19698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19699         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19700         -1,
  19701         -1,
  19702     },
  19703 #endif /* chips */
  19704 
  19705 #if defined(BCM_88375_A0)
  19706     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88375_A0r */
  19707         soc_block_list[22],
  19708         soc_genreg,
  19709         1,
  19710         0,
  19711         0x10f,
  19712         0,
  19713         0,
  19714         8,
  19715         soc_OAMP_PR_2_FWDDP_BCM88375_A0r_fields,
  19716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19717         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19718         -1,
  19719         -1,
  19720     },
  19721 #endif /* chips */
  19722 
  19723 #if defined(BCM_88375_B0)
  19724     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88375_B0r */
  19725         soc_block_list[22],
  19726         soc_genreg,
  19727         1,
  19728         0,
  19729         0x10f,
  19730         0,
  19731         0,
  19732         8,
  19733         soc_OAMP_PR_2_FWDDP_BCM88375_B0r_fields,
  19734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19735         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19736         -1,
  19737         -1,
  19738     },
  19739 #endif /* chips */
  19740 
  19741 #if defined(BCM_88470_A0)
  19742     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88470_A0r */
  19743         soc_block_list[22],
  19744         soc_genreg,
  19745         1,
  19746         0,
  19747         0x10f,
  19748         0,
  19749         0,
  19750         8,
  19751         soc_OAMP_PR_2_FWDDP_BCM88470_A0r_fields,
  19752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19753         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19754         -1,
  19755         -1,
  19756     },
  19757 #endif /* chips */
  19758 
  19759 #if defined(BCM_88470_B0)
  19760     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88470_B0r */
  19761         soc_block_list[22],
  19762         soc_genreg,
  19763         1,
  19764         0,
  19765         0x10f,
  19766         0,
  19767         0,
  19768         8,
  19769         soc_OAMP_PR_2_FWDDP_BCM88470_B0r_fields,
  19770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19771         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19772         -1,
  19773         -1,
  19774     },
  19775 #endif /* chips */
  19776 
  19777 #if defined(BCM_88650_B0)
  19778     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88650_B0r */
  19779         soc_block_list[22],
  19780         soc_genreg,
  19781         1,
  19782         0,
  19783         0x10f,
  19784         SOC_REG_FLAG_SIGNAL,
  19785         0,
  19786         8,
  19787         soc_OAMP_PR_2_FWDDP_BCM88650_B0r_fields,
  19788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19789         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19790         -1,
  19791         -1,
  19792     },
  19793 #endif /* chips */
  19794 
  19795 #if defined(BCM_88660_A0)
  19796     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88660_A0r */
  19797         soc_block_list[22],
  19798         soc_genreg,
  19799         1,
  19800         0,
  19801         0x10f,
  19802         SOC_REG_FLAG_SIGNAL,
  19803         0,
  19804         8,
  19805         soc_OAMP_PR_2_FWDDP_BCM88660_A0r_fields,
  19806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19807         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19808         -1,
  19809         -1,
  19810     },
  19811 #endif /* chips */
  19812 
  19813 #if defined(BCM_88675_A0)
  19814     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88675_A0r */
  19815         soc_block_list[22],
  19816         soc_genreg,
  19817         1,
  19818         0,
  19819         0x10f,
  19820         0,
  19821         0,
  19822         8,
  19823         soc_OAMP_PR_2_FWDDP_BCM88675_A0r_fields,
  19824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19825         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19826         -1,
  19827         -1,
  19828     },
  19829 #endif /* chips */
  19830 
  19831 #if defined(BCM_88675_B0)
  19832     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88675_B0r */
  19833         soc_block_list[22],
  19834         soc_genreg,
  19835         1,
  19836         0,
  19837         0x10f,
  19838         0,
  19839         0,
  19840         8,
  19841         soc_OAMP_PR_2_FWDDP_BCM88675_B0r_fields,
  19842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19843         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19844         -1,
  19845         -1,
  19846     },
  19847 #endif /* chips */
  19848 
  19849 #if defined(BCM_88680_A0)
  19850     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88680_A0r */
  19851         soc_block_list[22],
  19852         soc_genreg,
  19853         1,
  19854         0,
  19855         0x10f,
  19856         0,
  19857         0,
  19858         8,
  19859         soc_OAMP_PR_2_FWDDP_BCM88680_A0r_fields,
  19860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19861         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19862         -1,
  19863         -1,
  19864     },
  19865 #endif /* chips */
  19866 
  19867 #if defined(BCM_88690_A0)
  19868     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88690_A0r */
  19869         soc_block_list[22],
  19870         soc_genreg,
  19871         1,
  19872         0,
  19873         0x10f,
  19874         0,
  19875         0,
  19876         8,
  19877         soc_OAMP_PR_2_FWDDP_BCM88690_A0r_fields,
  19878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19879         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19880         -1,
  19881         -1,
  19882     },
  19883 #endif /* chips */
  19884 
  19885 #if defined(BCM_88690_B0)
  19886     { /* SOC_REG_INT_OAMP_PR_2_FWDDP_BCM88690_B0r */
  19887         soc_block_list[22],
  19888         soc_genreg,
  19889         1,
  19890         0,
  19891         0x10f,
  19892         0,
  19893         0,
  19894         8,
  19895         soc_OAMP_PR_2_FWDDP_BCM88690_B0r_fields,
  19896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19897         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19898         -1,
  19899         -1,
  19900     },
  19901 #endif /* chips */
  19902 
  19903 #if defined(BCM_88650_A0)
  19904     { /* SOC_REG_INT_OAMP_PR_2_FW_DTCr */
  19905         soc_block_list[22],
  19906         soc_genreg,
  19907         1,
  19908         0,
  19909         0x10e,
  19910         SOC_REG_FLAG_SIGNAL,
  19911         0,
  19912         8,
  19913         soc_OAMP_PR_2_FW_DTCr_fields,
  19914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19915         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  19916         -1,
  19917         -1,
  19918     },
  19919 #endif /* chips */
  19920 
  19921 #if defined(BCM_88270_A0)
  19922     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88270_A0r */
  19923         soc_block_list[22],
  19924         soc_genreg,
  19925         1,
  19926         0,
  19927         0x10e,
  19928         0,
  19929         0,
  19930         8,
  19931         soc_OAMP_PR_2_FW_DTC_BCM88270_A0r_fields,
  19932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19933         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  19934         -1,
  19935         -1,
  19936     },
  19937 #endif /* chips */
  19938 
  19939 #if defined(BCM_88375_A0)
  19940     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88375_A0r */
  19941         soc_block_list[22],
  19942         soc_genreg,
  19943         1,
  19944         0,
  19945         0x10e,
  19946         0,
  19947         0,
  19948         8,
  19949         soc_OAMP_PR_2_FW_DTC_BCM88375_A0r_fields,
  19950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19951         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  19952         -1,
  19953         -1,
  19954     },
  19955 #endif /* chips */
  19956 
  19957 #if defined(BCM_88375_B0)
  19958     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88375_B0r */
  19959         soc_block_list[22],
  19960         soc_genreg,
  19961         1,
  19962         0,
  19963         0x10e,
  19964         0,
  19965         0,
  19966         8,
  19967         soc_OAMP_PR_2_FW_DTC_BCM88375_B0r_fields,
  19968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19969         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  19970         -1,
  19971         -1,
  19972     },
  19973 #endif /* chips */
  19974 
  19975 #if defined(BCM_88470_A0)
  19976     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88470_A0r */
  19977         soc_block_list[22],
  19978         soc_genreg,
  19979         1,
  19980         0,
  19981         0x10e,
  19982         0,
  19983         0,
  19984         8,
  19985         soc_OAMP_PR_2_FW_DTC_BCM88470_A0r_fields,
  19986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19987         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  19988         -1,
  19989         -1,
  19990     },
  19991 #endif /* chips */
  19992 
  19993 #if defined(BCM_88470_B0)
  19994     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88470_B0r */
  19995         soc_block_list[22],
  19996         soc_genreg,
  19997         1,
  19998         0,
  19999         0x10e,
  20000         0,
  20001         0,
  20002         8,
  20003         soc_OAMP_PR_2_FW_DTC_BCM88470_B0r_fields,
  20004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20005         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  20006         -1,
  20007         -1,
  20008     },
  20009 #endif /* chips */
  20010 
  20011 #if defined(BCM_88650_B0)
  20012     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88650_B0r */
  20013         soc_block_list[22],
  20014         soc_genreg,
  20015         1,
  20016         0,
  20017         0x10e,
  20018         SOC_REG_FLAG_SIGNAL,
  20019         0,
  20020         8,
  20021         soc_OAMP_PR_2_FW_DTC_BCM88650_B0r_fields,
  20022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20023         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  20024         -1,
  20025         -1,
  20026     },
  20027 #endif /* chips */
  20028 
  20029 #if defined(BCM_88660_A0)
  20030     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88660_A0r */
  20031         soc_block_list[22],
  20032         soc_genreg,
  20033         1,
  20034         0,
  20035         0x10e,
  20036         SOC_REG_FLAG_SIGNAL,
  20037         0,
  20038         8,
  20039         soc_OAMP_PR_2_FW_DTC_BCM88660_A0r_fields,
  20040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20041         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  20042         -1,
  20043         -1,
  20044     },
  20045 #endif /* chips */
  20046 
  20047 #if defined(BCM_88675_A0)
  20048     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88675_A0r */
  20049         soc_block_list[22],
  20050         soc_genreg,
  20051         1,
  20052         0,
  20053         0x10e,
  20054         0,
  20055         0,
  20056         8,
  20057         soc_OAMP_PR_2_FW_DTC_BCM88675_A0r_fields,
  20058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20059         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  20060         -1,
  20061         -1,
  20062     },
  20063 #endif /* chips */
  20064 
  20065 #if defined(BCM_88675_B0)
  20066     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88675_B0r */
  20067         soc_block_list[22],
  20068         soc_genreg,
  20069         1,
  20070         0,
  20071         0x10e,
  20072         0,
  20073         0,
  20074         8,
  20075         soc_OAMP_PR_2_FW_DTC_BCM88675_B0r_fields,
  20076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20077         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  20078         -1,
  20079         -1,
  20080     },
  20081 #endif /* chips */
  20082 
  20083 #if defined(BCM_88680_A0)
  20084     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88680_A0r */
  20085         soc_block_list[22],
  20086         soc_genreg,
  20087         1,
  20088         0,
  20089         0x10e,
  20090         0,
  20091         0,
  20092         8,
  20093         soc_OAMP_PR_2_FW_DTC_BCM88680_A0r_fields,
  20094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20095         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  20096         -1,
  20097         -1,
  20098     },
  20099 #endif /* chips */
  20100 
  20101 #if defined(BCM_88690_A0)
  20102     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88690_A0r */
  20103         soc_block_list[22],
  20104         soc_genreg,
  20105         1,
  20106         0,
  20107         0x10e,
  20108         0,
  20109         0,
  20110         8,
  20111         soc_OAMP_PR_2_FW_DTC_BCM88690_A0r_fields,
  20112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20113         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  20114         -1,
  20115         -1,
  20116     },
  20117 #endif /* chips */
  20118 
  20119 #if defined(BCM_88690_B0)
  20120     { /* SOC_REG_INT_OAMP_PR_2_FW_DTC_BCM88690_B0r */
  20121         soc_block_list[22],
  20122         soc_genreg,
  20123         1,
  20124         0,
  20125         0x10e,
  20126         0,
  20127         0,
  20128         8,
  20129         soc_OAMP_PR_2_FW_DTC_BCM88690_B0r_fields,
  20130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20131         SOC_RESET_MASK_DEC(0x77777777, 0x00000000)
  20132         -1,
  20133         -1,
  20134     },
  20135 #endif /* chips */
  20136 
  20137 #if defined(BCM_88660_A0)
  20138     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLINGr */
  20139         soc_block_list[22],
  20140         soc_genreg,
  20141         1,
  20142         0,
  20143         0x16f,
  20144         SOC_REG_FLAG_64_BITS |
  20145                           SOC_REG_FLAG_SIGNAL,
  20146         0,
  20147         28,
  20148         soc_OAMP_PUNT_EVENT_HENDLINGr_fields,
  20149         SOC_RESET_VAL_DEC(0x2a0540a8, 0x00000150)
  20150         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  20151         -1,
  20152         -1,
  20153     },
  20154 #endif /* chips */
  20155 
  20156 #if defined(BCM_88270_A0)
  20157     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88270_A0r */
  20158         soc_block_list[22],
  20159         soc_genreg,
  20160         16,
  20161         0,
  20162         0x185,
  20163         SOC_REG_FLAG_ARRAY |
  20164                           SOC_REG_FLAG_REG_ARRAY,
  20165         0,
  20166         7,
  20167         soc_OAMP_PUNT_EVENT_HENDLING_BCM88270_A0r_fields,
  20168         SOC_RESET_VAL_DEC(0x000000a8, 0x00000000)
  20169         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  20170         -1,
  20171         -1,
  20172     },
  20173 #endif /* chips */
  20174 
  20175 #if defined(BCM_88375_A0)
  20176     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88375_A0r */
  20177         soc_block_list[22],
  20178         soc_genreg,
  20179         1,
  20180         0,
  20181         0x183,
  20182         SOC_REG_FLAG_64_BITS,
  20183         0,
  20184         28,
  20185         soc_OAMP_PUNT_EVENT_HENDLING_BCM88375_A0r_fields,
  20186         SOC_RESET_VAL_DEC(0x2a0540a8, 0x00000150)
  20187         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  20188         -1,
  20189         -1,
  20190     },
  20191 #endif /* chips */
  20192 
  20193 #if defined(BCM_88375_B0)
  20194     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88375_B0r */
  20195         soc_block_list[22],
  20196         soc_genreg,
  20197         1,
  20198         0,
  20199         0x183,
  20200         SOC_REG_FLAG_64_BITS,
  20201         0,
  20202         28,
  20203         soc_OAMP_PUNT_EVENT_HENDLING_BCM88375_B0r_fields,
  20204         SOC_RESET_VAL_DEC(0x2a0540a8, 0x00000150)
  20205         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  20206         -1,
  20207         -1,
  20208     },
  20209 #endif /* chips */
  20210 
  20211 #if defined(BCM_88470_A0)
  20212     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88470_A0r */
  20213         soc_block_list[22],
  20214         soc_genreg,
  20215         16,
  20216         0,
  20217         0x185,
  20218         SOC_REG_FLAG_ARRAY |
  20219                           SOC_REG_FLAG_REG_ARRAY,
  20220         0,
  20221         7,
  20222         soc_OAMP_PUNT_EVENT_HENDLING_BCM88470_A0r_fields,
  20223         SOC_RESET_VAL_DEC(0x000000a8, 0x00000000)
  20224         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  20225         -1,
  20226         -1,
  20227     },
  20228 #endif /* chips */
  20229 
  20230 #if defined(BCM_88470_B0)
  20231     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88470_B0r */
  20232         soc_block_list[22],
  20233         soc_genreg,
  20234         16,
  20235         0,
  20236         0x185,
  20237         SOC_REG_FLAG_ARRAY |
  20238                           SOC_REG_FLAG_REG_ARRAY,
  20239         0,
  20240         7,
  20241         soc_OAMP_PUNT_EVENT_HENDLING_BCM88470_B0r_fields,
  20242         SOC_RESET_VAL_DEC(0x000000a8, 0x00000000)
  20243         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  20244         -1,
  20245         -1,
  20246     },
  20247 #endif /* chips */
  20248 
  20249 #if defined(BCM_88675_A0)
  20250     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88675_A0r */
  20251         soc_block_list[22],
  20252         soc_genreg,
  20253         1,
  20254         0,
  20255         0x183,
  20256         SOC_REG_FLAG_64_BITS,
  20257         0,
  20258         28,
  20259         soc_OAMP_PUNT_EVENT_HENDLING_BCM88675_A0r_fields,
  20260         SOC_RESET_VAL_DEC(0x2a0540a8, 0x00000150)
  20261         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  20262         -1,
  20263         -1,
  20264     },
  20265 #endif /* chips */
  20266 
  20267 #if defined(BCM_88675_B0)
  20268     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88675_B0r */
  20269         soc_block_list[22],
  20270         soc_genreg,
  20271         1,
  20272         0,
  20273         0x183,
  20274         SOC_REG_FLAG_64_BITS,
  20275         0,
  20276         28,
  20277         soc_OAMP_PUNT_EVENT_HENDLING_BCM88675_B0r_fields,
  20278         SOC_RESET_VAL_DEC(0x2a0540a8, 0x00000150)
  20279         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  20280         -1,
  20281         -1,
  20282     },
  20283 #endif /* chips */
  20284 
  20285 #if defined(BCM_88680_A0)
  20286     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88680_A0r */
  20287         soc_block_list[22],
  20288         soc_genreg,
  20289         1,
  20290         0,
  20291         0x183,
  20292         SOC_REG_FLAG_64_BITS,
  20293         0,
  20294         28,
  20295         soc_OAMP_PUNT_EVENT_HENDLING_BCM88680_A0r_fields,
  20296         SOC_RESET_VAL_DEC(0x2a0540a8, 0x00000150)
  20297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  20298         -1,
  20299         -1,
  20300     },
  20301 #endif /* chips */
  20302 
  20303 #if defined(BCM_88690_A0)
  20304     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88690_A0r */
  20305         soc_block_list[22],
  20306         soc_genreg,
  20307         16,
  20308         0,
  20309         0x182,
  20310         SOC_REG_FLAG_ARRAY |
  20311                           SOC_REG_FLAG_REG_ARRAY,
  20312         0,
  20313         7,
  20314         soc_OAMP_PUNT_EVENT_HENDLING_BCM88690_A0r_fields,
  20315         SOC_RESET_VAL_DEC(0x000000a8, 0x00000000)
  20316         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  20317         -1,
  20318         -1,
  20319     },
  20320 #endif /* chips */
  20321 
  20322 #if defined(BCM_88690_B0)
  20323     { /* SOC_REG_INT_OAMP_PUNT_EVENT_HENDLING_BCM88690_B0r */
  20324         soc_block_list[22],
  20325         soc_genreg,
  20326         16,
  20327         0,
  20328         0x182,
  20329         SOC_REG_FLAG_ARRAY |
  20330                           SOC_REG_FLAG_REG_ARRAY,
  20331         0,
  20332         7,
  20333         soc_OAMP_PUNT_EVENT_HENDLING_BCM88690_B0r_fields,
  20334         SOC_RESET_VAL_DEC(0x000000a8, 0x00000000)
  20335         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  20336         -1,
  20337         -1,
  20338     },
  20339 #endif /* chips */
  20340 
  20341 #if defined(BCM_88470_A0)
  20342     { /* SOC_REG_INT_OAMP_PUNT_PKT_SYS_HDRr */
  20343         soc_block_list[22],
  20344         soc_genreg,
  20345         1,
  20346         0,
  20347         0x110,
  20348         0,
  20349         0,
  20350         11,
  20351         soc_OAMP_PUNT_PKT_SYS_HDRr_fields,
  20352         SOC_RESET_VAL_DEC(0x005c0001, 0x00000000)
  20353         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  20354         -1,
  20355         -1,
  20356     },
  20357 #endif /* chips */
  20358 
  20359 #if defined(BCM_88270_A0)
  20360     { /* SOC_REG_INT_OAMP_PUNT_PKT_SYS_HDR_BCM88270_A0r */
  20361         soc_block_list[22],
  20362         soc_genreg,
  20363         1,
  20364         0,
  20365         0x110,
  20366         0,
  20367         0,
  20368         11,
  20369         soc_OAMP_PUNT_PKT_SYS_HDR_BCM88270_A0r_fields,
  20370         SOC_RESET_VAL_DEC(0x005c0001, 0x00000000)
  20371         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  20372         -1,
  20373         -1,
  20374     },
  20375 #endif /* chips */
  20376 
  20377 #if defined(BCM_88470_B0)
  20378     { /* SOC_REG_INT_OAMP_PUNT_PKT_SYS_HDR_BCM88470_B0r */
  20379         soc_block_list[22],
  20380         soc_genreg,
  20381         1,
  20382         0,
  20383         0x110,
  20384         0,
  20385         0,
  20386         11,
  20387         soc_OAMP_PUNT_PKT_SYS_HDR_BCM88470_B0r_fields,
  20388         SOC_RESET_VAL_DEC(0x005c0001, 0x00000000)
  20389         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  20390         -1,
  20391         -1,
  20392     },
  20393 #endif /* chips */
  20394 
  20395 #if defined(BCM_88690_A0)
  20396     { /* SOC_REG_INT_OAMP_PUNT_PKT_SYS_HDR_BCM88690_A0r */
  20397         soc_block_list[22],
  20398         soc_genreg,
  20399         1,
  20400         0,
  20401         0x110,
  20402         0,
  20403         0,
  20404         11,
  20405         soc_OAMP_PUNT_PKT_SYS_HDR_BCM88690_A0r_fields,
  20406         SOC_RESET_VAL_DEC(0x00b80001, 0x00000000)
  20407         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  20408         -1,
  20409         -1,
  20410     },
  20411 #endif /* chips */
  20412 
  20413 #if defined(BCM_88690_B0)
  20414     { /* SOC_REG_INT_OAMP_PUNT_PKT_SYS_HDR_BCM88690_B0r */
  20415         soc_block_list[22],
  20416         soc_genreg,
  20417         1,
  20418         0,
  20419         0x110,
  20420         0,
  20421         0,
  20422         11,
  20423         soc_OAMP_PUNT_PKT_SYS_HDR_BCM88690_B0r_fields,
  20424         SOC_RESET_VAL_DEC(0x00b80001, 0x00000000)
  20425         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  20426         -1,
  20427         -1,
  20428     },
  20429 #endif /* chips */
  20430 
  20431 #if defined(BCM_88650_A0)
  20432     { /* SOC_REG_INT_OAMP_REG_0085r */
  20433         soc_block_list[22],
  20434         soc_genreg,
  20435         1,
  20436         0,
  20437         0x85,
  20438         0,
  20439         0,
  20440         2,
  20441         soc_OAMP_REG_0085r_fields,
  20442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20443         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  20444         -1,
  20445         -1,
  20446     },
  20447 #endif /* chips */
  20448 
  20449 #if defined(BCM_88650_A0)
  20450     { /* SOC_REG_INT_OAMP_REG_0086r */
  20451         soc_block_list[22],
  20452         soc_genreg,
  20453         1,
  20454         0,
  20455         0x86,
  20456         SOC_REG_FLAG_SIGNAL,
  20457         0,
  20458         1,
  20459         soc_OAMP_REG_0086r_fields,
  20460         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  20461         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  20462         -1,
  20463         -1,
  20464     },
  20465 #endif /* chips */
  20466 
  20467 #if defined(BCM_88650_A0)
  20468     { /* SOC_REG_INT_OAMP_REG_0087r */
  20469         soc_block_list[22],
  20470         soc_genreg,
  20471         1,
  20472         0,
  20473         0x87,
  20474         SOC_REG_FLAG_SIGNAL,
  20475         0,
  20476         1,
  20477         soc_OAMP_REG_0087r_fields,
  20478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20479         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20480         -1,
  20481         -1,
  20482     },
  20483 #endif /* chips */
  20484 
  20485 #if defined(BCM_88650_A0)
  20486     { /* SOC_REG_INT_OAMP_REG_0090r */
  20487         soc_block_list[22],
  20488         soc_genreg,
  20489         1,
  20490         0,
  20491         0x90,
  20492         SOC_REG_FLAG_SIGNAL,
  20493         0,
  20494         1,
  20495         soc_OAMP_REG_0090r_fields,
  20496         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  20497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20498         -1,
  20499         -1,
  20500     },
  20501 #endif /* chips */
  20502 
  20503 #if defined(BCM_88650_A0)
  20504     { /* SOC_REG_INT_OAMP_REG_0091r */
  20505         soc_block_list[22],
  20506         soc_genreg,
  20507         1,
  20508         0,
  20509         0x91,
  20510         SOC_REG_FLAG_SIGNAL,
  20511         0,
  20512         1,
  20513         soc_OAMP_REG_0091r_fields,
  20514         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  20515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20516         -1,
  20517         -1,
  20518     },
  20519 #endif /* chips */
  20520 
  20521 #if defined(BCM_88650_A0)
  20522     { /* SOC_REG_INT_OAMP_REG_0092r */
  20523         soc_block_list[22],
  20524         soc_genreg,
  20525         1,
  20526         0,
  20527         0x92,
  20528         SOC_REG_FLAG_SIGNAL,
  20529         0,
  20530         1,
  20531         soc_OAMP_REG_0092r_fields,
  20532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20534         -1,
  20535         -1,
  20536     },
  20537 #endif /* chips */
  20538 
  20539 #if defined(BCM_88650_A0)
  20540     { /* SOC_REG_INT_OAMP_REG_0093r */
  20541         soc_block_list[22],
  20542         soc_genreg,
  20543         1,
  20544         0,
  20545         0x93,
  20546         SOC_REG_FLAG_SIGNAL,
  20547         0,
  20548         1,
  20549         soc_OAMP_REG_0093r_fields,
  20550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20552         -1,
  20553         -1,
  20554     },
  20555 #endif /* chips */
  20556 
  20557 #if defined(BCM_88690_A0)
  20558     { /* SOC_REG_INT_OAMP_REG_0098r */
  20559         soc_block_list[22],
  20560         soc_genreg,
  20561         1,
  20562         0,
  20563         0x98,
  20564         SOC_REG_FLAG_64_BITS |
  20565                           SOC_REG_FLAG_RO,
  20566         SOC_REG_FLAG_COUNTER_FEILDS |
  20567                           SOC_REG_FLAG_INIT_ON_READ,
  20568         4,
  20569         soc_OAMP_REG_0098r_fields,
  20570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20571         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  20572         -1,
  20573         -1,
  20574     },
  20575 #endif /* chips */
  20576 
  20577 #if defined(BCM_88690_A0)
  20578     { /* SOC_REG_INT_OAMP_REG_0127r */
  20579         soc_block_list[22],
  20580         soc_genreg,
  20581         1,
  20582         0,
  20583         0x127,
  20584         SOC_REG_FLAG_64_BITS,
  20585         0,
  20586         16,
  20587         soc_OAMP_REG_0127r_fields,
  20588         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  20589         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  20590         -1,
  20591         -1,
  20592     },
  20593 #endif /* chips */
  20594 
  20595 #if defined(BCM_88690_A0)
  20596     { /* SOC_REG_INT_OAMP_REG_0129r */
  20597         soc_block_list[22],
  20598         soc_genreg,
  20599         1,
  20600         0,
  20601         0x129,
  20602         SOC_REG_FLAG_ABOVE_64_BITS,
  20603         0,
  20604         18,
  20605         soc_OAMP_REG_0129r_fields,
  20606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20607         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20608         -1,
  20609         -1,
  20610     },
  20611 #endif /* chips */
  20612 
  20613 #if defined(BCM_88470_A0)
  20614     { /* SOC_REG_INT_OAMP_REG_0130r */
  20615         soc_block_list[22],
  20616         soc_genreg,
  20617         1,
  20618         0,
  20619         0x130,
  20620         SOC_REG_FLAG_64_BITS,
  20621         0,
  20622         16,
  20623         soc_OAMP_REG_0130r_fields,
  20624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20625         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  20626         -1,
  20627         -1,
  20628     },
  20629 #endif /* chips */
  20630 
  20631 #if defined(BCM_88650_A0)
  20632     { /* SOC_REG_INT_OAMP_REG_0141r */
  20633         soc_block_list[22],
  20634         soc_genreg,
  20635         1,
  20636         0,
  20637         0x141,
  20638         SOC_REG_FLAG_RO,
  20639         0,
  20640         1,
  20641         soc_OAMP_REG_0141r_fields,
  20642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20643         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20644         -1,
  20645         -1,
  20646     },
  20647 #endif /* chips */
  20648 
  20649 #if defined(BCM_88650_A0)
  20650     { /* SOC_REG_INT_OAMP_REG_0142r */
  20651         soc_block_list[22],
  20652         soc_genreg,
  20653         1,
  20654         0,
  20655         0x142,
  20656         SOC_REG_FLAG_RO,
  20657         0,
  20658         1,
  20659         soc_OAMP_REG_0142r_fields,
  20660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20661         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20662         -1,
  20663         -1,
  20664     },
  20665 #endif /* chips */
  20666 
  20667 #if defined(BCM_88660_A0)
  20668     { /* SOC_REG_INT_OAMP_REG_0154r */
  20669         soc_block_list[22],
  20670         soc_genreg,
  20671         1,
  20672         0,
  20673         0x154,
  20674         SOC_REG_FLAG_RO,
  20675         0,
  20676         1,
  20677         soc_OAMP_REG_0154r_fields,
  20678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20679         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20680         -1,
  20681         -1,
  20682     },
  20683 #endif /* chips */
  20684 
  20685 #if defined(BCM_88660_A0)
  20686     { /* SOC_REG_INT_OAMP_REG_0155r */
  20687         soc_block_list[22],
  20688         soc_genreg,
  20689         1,
  20690         0,
  20691         0x155,
  20692         SOC_REG_FLAG_RO,
  20693         0,
  20694         1,
  20695         soc_OAMP_REG_0155r_fields,
  20696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20697         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20698         -1,
  20699         -1,
  20700     },
  20701 #endif /* chips */
  20702 
  20703 #if defined(BCM_88690_A0)
  20704     { /* SOC_REG_INT_OAMP_REG_0165r */
  20705         soc_block_list[22],
  20706         soc_genreg,
  20707         1,
  20708         0,
  20709         0x165,
  20710         SOC_REG_FLAG_64_BITS |
  20711                           SOC_REG_FLAG_RO |
  20712                           SOC_REG_FLAG_SIGNAL,
  20713         0,
  20714         2,
  20715         soc_OAMP_REG_0165r_fields,
  20716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20717         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  20718         -1,
  20719         -1,
  20720     },
  20721 #endif /* chips */
  20722 
  20723 #if defined(BCM_88690_A0)
  20724     { /* SOC_REG_INT_OAMP_REG_0167r */
  20725         soc_block_list[22],
  20726         soc_genreg,
  20727         1,
  20728         0,
  20729         0x167,
  20730         SOC_REG_FLAG_64_BITS |
  20731                           SOC_REG_FLAG_RO |
  20732                           SOC_REG_FLAG_SIGNAL,
  20733         0,
  20734         2,
  20735         soc_OAMP_REG_0167r_fields,
  20736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20737         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  20738         -1,
  20739         -1,
  20740     },
  20741 #endif /* chips */
  20742 
  20743 #if defined(BCM_88675_A0)
  20744     { /* SOC_REG_INT_OAMP_REG_0168r */
  20745         soc_block_list[22],
  20746         soc_genreg,
  20747         1,
  20748         0,
  20749         0x168,
  20750         SOC_REG_FLAG_RO |
  20751                           SOC_REG_FLAG_SIGNAL,
  20752         0,
  20753         1,
  20754         soc_OAMP_REG_0168r_fields,
  20755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20756         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20757         -1,
  20758         -1,
  20759     },
  20760 #endif /* chips */
  20761 
  20762 #if defined(BCM_88675_A0)
  20763     { /* SOC_REG_INT_OAMP_REG_0169r */
  20764         soc_block_list[22],
  20765         soc_genreg,
  20766         1,
  20767         0,
  20768         0x169,
  20769         SOC_REG_FLAG_RO |
  20770                           SOC_REG_FLAG_SIGNAL,
  20771         0,
  20772         2,
  20773         soc_OAMP_REG_0169r_fields,
  20774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20775         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20776         -1,
  20777         -1,
  20778     },
  20779 #endif /* chips */
  20780 
  20781 #if defined(BCM_88690_A0)
  20782     { /* SOC_REG_INT_OAMP_REG_0199r */
  20783         soc_block_list[22],
  20784         soc_genreg,
  20785         1,
  20786         0,
  20787         0x199,
  20788         SOC_REG_FLAG_RO |
  20789                           SOC_REG_FLAG_SIGNAL,
  20790         SOC_REG_FLAG_INIT_ON_READ,
  20791         17,
  20792         soc_OAMP_REG_0199r_fields,
  20793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20794         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  20795         -1,
  20796         -1,
  20797     },
  20798 #endif /* chips */
  20799 
  20800 #if defined(BCM_88650_A0)
  20801     { /* SOC_REG_INT_OAMP_REG_0201r */
  20802         soc_block_list[22],
  20803         soc_genreg,
  20804         1,
  20805         0,
  20806         0x201,
  20807         0,
  20808         0,
  20809         1,
  20810         soc_OAMP_REG_0201r_fields,
  20811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20812         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20813         -1,
  20814         -1,
  20815     },
  20816 #endif /* chips */
  20817 
  20818 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  20819     defined(BCM_56270_A0)
  20820     { /* SOC_REG_INT_OAMP_REG_0085_BCM56260_A0r */
  20821         soc_block_list[22],
  20822         soc_genreg,
  20823         1,
  20824         0,
  20825         0x2008500,
  20826         0,
  20827         0,
  20828         2,
  20829         soc_CCS_RESERVED_MIRROR_ADDRr_fields,
  20830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20831         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  20832         -1,
  20833         -1,
  20834     },
  20835 #endif /* chips */
  20836 
  20837 #if defined(BCM_88375_A0)
  20838     { /* SOC_REG_INT_OAMP_REG_0085_BCM88375_A0r */
  20839         soc_block_list[22],
  20840         soc_genreg,
  20841         1,
  20842         0,
  20843         0x85,
  20844         0,
  20845         0,
  20846         2,
  20847         soc_OAMP_REG_0085_BCM88375_A0r_fields,
  20848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20849         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  20850         -1,
  20851         -1,
  20852     },
  20853 #endif /* chips */
  20854 
  20855 #if defined(BCM_88375_B0)
  20856     { /* SOC_REG_INT_OAMP_REG_0085_BCM88375_B0r */
  20857         soc_block_list[22],
  20858         soc_genreg,
  20859         1,
  20860         0,
  20861         0x85,
  20862         0,
  20863         0,
  20864         2,
  20865         soc_OAMP_REG_0085_BCM88375_B0r_fields,
  20866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20867         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  20868         -1,
  20869         -1,
  20870     },
  20871 #endif /* chips */
  20872 
  20873 #if defined(BCM_88650_B0)
  20874     { /* SOC_REG_INT_OAMP_REG_0085_BCM88650_B0r */
  20875         soc_block_list[22],
  20876         soc_genreg,
  20877         1,
  20878         0,
  20879         0x85,
  20880         0,
  20881         0,
  20882         2,
  20883         soc_OAMP_REG_0085_BCM88650_B0r_fields,
  20884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20885         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  20886         -1,
  20887         -1,
  20888     },
  20889 #endif /* chips */
  20890 
  20891 #if defined(BCM_88660_A0)
  20892     { /* SOC_REG_INT_OAMP_REG_0085_BCM88660_A0r */
  20893         soc_block_list[22],
  20894         soc_genreg,
  20895         1,
  20896         0,
  20897         0x85,
  20898         0,
  20899         0,
  20900         2,
  20901         soc_OAMP_REG_0085_BCM88660_A0r_fields,
  20902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20903         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  20904         -1,
  20905         -1,
  20906     },
  20907 #endif /* chips */
  20908 
  20909 #if defined(BCM_88675_A0)
  20910     { /* SOC_REG_INT_OAMP_REG_0085_BCM88675_A0r */
  20911         soc_block_list[22],
  20912         soc_genreg,
  20913         1,
  20914         0,
  20915         0x85,
  20916         0,
  20917         0,
  20918         2,
  20919         soc_OAMP_REG_0085_BCM88675_A0r_fields,
  20920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20921         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  20922         -1,
  20923         -1,
  20924     },
  20925 #endif /* chips */
  20926 
  20927 #if defined(BCM_88675_B0)
  20928     { /* SOC_REG_INT_OAMP_REG_0085_BCM88675_B0r */
  20929         soc_block_list[22],
  20930         soc_genreg,
  20931         1,
  20932         0,
  20933         0x85,
  20934         0,
  20935         0,
  20936         2,
  20937         soc_OAMP_REG_0085_BCM88675_B0r_fields,
  20938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20939         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  20940         -1,
  20941         -1,
  20942     },
  20943 #endif /* chips */
  20944 
  20945 #if defined(BCM_88680_A0)
  20946     { /* SOC_REG_INT_OAMP_REG_0085_BCM88680_A0r */
  20947         soc_block_list[22],
  20948         soc_genreg,
  20949         1,
  20950         0,
  20951         0x85,
  20952         0,
  20953         0,
  20954         2,
  20955         soc_OAMP_REG_0085_BCM88680_A0r_fields,
  20956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20957         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  20958         -1,
  20959         -1,
  20960     },
  20961 #endif /* chips */
  20962 
  20963 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  20964     defined(BCM_56270_A0)
  20965     { /* SOC_REG_INT_OAMP_REG_0086_BCM56260_A0r */
  20966         soc_block_list[22],
  20967         soc_genreg,
  20968         1,
  20969         0,
  20970         0x2008600,
  20971         0,
  20972         0,
  20973         1,
  20974         soc_OAMP_REG_0086_BCM56260_A0r_fields,
  20975         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  20976         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  20977         -1,
  20978         -1,
  20979     },
  20980 #endif /* chips */
  20981 
  20982 #if defined(BCM_88375_A0)
  20983     { /* SOC_REG_INT_OAMP_REG_0086_BCM88375_A0r */
  20984         soc_block_list[22],
  20985         soc_genreg,
  20986         1,
  20987         0,
  20988         0x86,
  20989         0,
  20990         0,
  20991         1,
  20992         soc_OAMP_REG_0086_BCM88375_A0r_fields,
  20993         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  20994         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  20995         -1,
  20996         -1,
  20997     },
  20998 #endif /* chips */
  20999 
  21000 #if defined(BCM_88375_B0)
  21001     { /* SOC_REG_INT_OAMP_REG_0086_BCM88375_B0r */
  21002         soc_block_list[22],
  21003         soc_genreg,
  21004         1,
  21005         0,
  21006         0x86,
  21007         0,
  21008         0,
  21009         1,
  21010         soc_OAMP_REG_0086_BCM88375_B0r_fields,
  21011         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  21012         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  21013         -1,
  21014         -1,
  21015     },
  21016 #endif /* chips */
  21017 
  21018 #if defined(BCM_88650_B0)
  21019     { /* SOC_REG_INT_OAMP_REG_0086_BCM88650_B0r */
  21020         soc_block_list[22],
  21021         soc_genreg,
  21022         1,
  21023         0,
  21024         0x86,
  21025         SOC_REG_FLAG_SIGNAL,
  21026         0,
  21027         1,
  21028         soc_OAMP_REG_0086_BCM88650_B0r_fields,
  21029         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  21030         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  21031         -1,
  21032         -1,
  21033     },
  21034 #endif /* chips */
  21035 
  21036 #if defined(BCM_88660_A0)
  21037     { /* SOC_REG_INT_OAMP_REG_0086_BCM88660_A0r */
  21038         soc_block_list[22],
  21039         soc_genreg,
  21040         1,
  21041         0,
  21042         0x86,
  21043         SOC_REG_FLAG_SIGNAL,
  21044         0,
  21045         1,
  21046         soc_OAMP_REG_0086_BCM88660_A0r_fields,
  21047         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  21048         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  21049         -1,
  21050         -1,
  21051     },
  21052 #endif /* chips */
  21053 
  21054 #if defined(BCM_88675_A0)
  21055     { /* SOC_REG_INT_OAMP_REG_0086_BCM88675_A0r */
  21056         soc_block_list[22],
  21057         soc_genreg,
  21058         1,
  21059         0,
  21060         0x86,
  21061         0,
  21062         0,
  21063         1,
  21064         soc_OAMP_REG_0086_BCM88675_A0r_fields,
  21065         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  21066         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  21067         -1,
  21068         -1,
  21069     },
  21070 #endif /* chips */
  21071 
  21072 #if defined(BCM_88675_B0)
  21073     { /* SOC_REG_INT_OAMP_REG_0086_BCM88675_B0r */
  21074         soc_block_list[22],
  21075         soc_genreg,
  21076         1,
  21077         0,
  21078         0x86,
  21079         0,
  21080         0,
  21081         1,
  21082         soc_OAMP_REG_0086_BCM88675_B0r_fields,
  21083         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  21084         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  21085         -1,
  21086         -1,
  21087     },
  21088 #endif /* chips */
  21089 
  21090 #if defined(BCM_88680_A0)
  21091     { /* SOC_REG_INT_OAMP_REG_0086_BCM88680_A0r */
  21092         soc_block_list[22],
  21093         soc_genreg,
  21094         1,
  21095         0,
  21096         0x86,
  21097         0,
  21098         0,
  21099         1,
  21100         soc_OAMP_REG_0086_BCM88680_A0r_fields,
  21101         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  21102         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  21103         -1,
  21104         -1,
  21105     },
  21106 #endif /* chips */
  21107 
  21108 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  21109     defined(BCM_56270_A0)
  21110     { /* SOC_REG_INT_OAMP_REG_0087_BCM56260_A0r */
  21111         soc_block_list[22],
  21112         soc_genreg,
  21113         1,
  21114         0,
  21115         0x2008700,
  21116         0,
  21117         0,
  21118         1,
  21119         soc_OCCG_REG_0087r_fields,
  21120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21121         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21122         -1,
  21123         -1,
  21124     },
  21125 #endif /* chips */
  21126 
  21127 #if defined(BCM_88375_A0)
  21128     { /* SOC_REG_INT_OAMP_REG_0087_BCM88375_A0r */
  21129         soc_block_list[22],
  21130         soc_genreg,
  21131         1,
  21132         0,
  21133         0x87,
  21134         0,
  21135         0,
  21136         1,
  21137         soc_OAMP_REG_0087_BCM88375_A0r_fields,
  21138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21139         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21140         -1,
  21141         -1,
  21142     },
  21143 #endif /* chips */
  21144 
  21145 #if defined(BCM_88375_B0)
  21146     { /* SOC_REG_INT_OAMP_REG_0087_BCM88375_B0r */
  21147         soc_block_list[22],
  21148         soc_genreg,
  21149         1,
  21150         0,
  21151         0x87,
  21152         0,
  21153         0,
  21154         1,
  21155         soc_OAMP_REG_0087_BCM88375_B0r_fields,
  21156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21157         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21158         -1,
  21159         -1,
  21160     },
  21161 #endif /* chips */
  21162 
  21163 #if defined(BCM_88650_B0)
  21164     { /* SOC_REG_INT_OAMP_REG_0087_BCM88650_B0r */
  21165         soc_block_list[22],
  21166         soc_genreg,
  21167         1,
  21168         0,
  21169         0x87,
  21170         SOC_REG_FLAG_SIGNAL,
  21171         0,
  21172         1,
  21173         soc_OAMP_REG_0087_BCM88650_B0r_fields,
  21174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21175         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21176         -1,
  21177         -1,
  21178     },
  21179 #endif /* chips */
  21180 
  21181 #if defined(BCM_88660_A0)
  21182     { /* SOC_REG_INT_OAMP_REG_0087_BCM88660_A0r */
  21183         soc_block_list[22],
  21184         soc_genreg,
  21185         1,
  21186         0,
  21187         0x87,
  21188         SOC_REG_FLAG_SIGNAL,
  21189         0,
  21190         1,
  21191         soc_OAMP_REG_0087_BCM88660_A0r_fields,
  21192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21193         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21194         -1,
  21195         -1,
  21196     },
  21197 #endif /* chips */
  21198 
  21199 #if defined(BCM_88675_A0)
  21200     { /* SOC_REG_INT_OAMP_REG_0087_BCM88675_A0r */
  21201         soc_block_list[22],
  21202         soc_genreg,
  21203         1,
  21204         0,
  21205         0x87,
  21206         0,
  21207         0,
  21208         1,
  21209         soc_OAMP_REG_0087_BCM88675_A0r_fields,
  21210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21211         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21212         -1,
  21213         -1,
  21214     },
  21215 #endif /* chips */
  21216 
  21217 #if defined(BCM_88675_B0)
  21218     { /* SOC_REG_INT_OAMP_REG_0087_BCM88675_B0r */
  21219         soc_block_list[22],
  21220         soc_genreg,
  21221         1,
  21222         0,
  21223         0x87,
  21224         0,
  21225         0,
  21226         1,
  21227         soc_OAMP_REG_0087_BCM88675_B0r_fields,
  21228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21229         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21230         -1,
  21231         -1,
  21232     },
  21233 #endif /* chips */
  21234 
  21235 #if defined(BCM_88680_A0)
  21236     { /* SOC_REG_INT_OAMP_REG_0087_BCM88680_A0r */
  21237         soc_block_list[22],
  21238         soc_genreg,
  21239         1,
  21240         0,
  21241         0x87,
  21242         0,
  21243         0,
  21244         1,
  21245         soc_OAMP_REG_0087_BCM88680_A0r_fields,
  21246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21247         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21248         -1,
  21249         -1,
  21250     },
  21251 #endif /* chips */
  21252 
  21253 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  21254     defined(BCM_56270_A0)
  21255     { /* SOC_REG_INT_OAMP_REG_0090_BCM56260_A0r */
  21256         soc_block_list[22],
  21257         soc_genreg,
  21258         1,
  21259         0,
  21260         0x2009000,
  21261         0,
  21262         0,
  21263         1,
  21264         soc_OAMP_REG_0090_BCM56260_A0r_fields,
  21265         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21266         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21267         -1,
  21268         -1,
  21269     },
  21270 #endif /* chips */
  21271 
  21272 #if defined(BCM_88375_A0)
  21273     { /* SOC_REG_INT_OAMP_REG_0090_BCM88375_A0r */
  21274         soc_block_list[22],
  21275         soc_genreg,
  21276         1,
  21277         0,
  21278         0x90,
  21279         0,
  21280         0,
  21281         1,
  21282         soc_OAMP_REG_0090_BCM88375_A0r_fields,
  21283         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21284         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21285         -1,
  21286         -1,
  21287     },
  21288 #endif /* chips */
  21289 
  21290 #if defined(BCM_88375_B0)
  21291     { /* SOC_REG_INT_OAMP_REG_0090_BCM88375_B0r */
  21292         soc_block_list[22],
  21293         soc_genreg,
  21294         1,
  21295         0,
  21296         0x90,
  21297         0,
  21298         0,
  21299         1,
  21300         soc_OAMP_REG_0090_BCM88375_B0r_fields,
  21301         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21302         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21303         -1,
  21304         -1,
  21305     },
  21306 #endif /* chips */
  21307 
  21308 #if defined(BCM_88650_B0)
  21309     { /* SOC_REG_INT_OAMP_REG_0090_BCM88650_B0r */
  21310         soc_block_list[22],
  21311         soc_genreg,
  21312         1,
  21313         0,
  21314         0x90,
  21315         SOC_REG_FLAG_SIGNAL,
  21316         0,
  21317         1,
  21318         soc_OAMP_REG_0090_BCM88650_B0r_fields,
  21319         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21320         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21321         -1,
  21322         -1,
  21323     },
  21324 #endif /* chips */
  21325 
  21326 #if defined(BCM_88660_A0)
  21327     { /* SOC_REG_INT_OAMP_REG_0090_BCM88660_A0r */
  21328         soc_block_list[22],
  21329         soc_genreg,
  21330         1,
  21331         0,
  21332         0x90,
  21333         SOC_REG_FLAG_SIGNAL,
  21334         0,
  21335         1,
  21336         soc_OAMP_REG_0090_BCM88660_A0r_fields,
  21337         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21338         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21339         -1,
  21340         -1,
  21341     },
  21342 #endif /* chips */
  21343 
  21344 #if defined(BCM_88675_A0)
  21345     { /* SOC_REG_INT_OAMP_REG_0090_BCM88675_A0r */
  21346         soc_block_list[22],
  21347         soc_genreg,
  21348         1,
  21349         0,
  21350         0x90,
  21351         0,
  21352         0,
  21353         1,
  21354         soc_OAMP_REG_0090_BCM88675_A0r_fields,
  21355         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21357         -1,
  21358         -1,
  21359     },
  21360 #endif /* chips */
  21361 
  21362 #if defined(BCM_88675_B0)
  21363     { /* SOC_REG_INT_OAMP_REG_0090_BCM88675_B0r */
  21364         soc_block_list[22],
  21365         soc_genreg,
  21366         1,
  21367         0,
  21368         0x90,
  21369         0,
  21370         0,
  21371         1,
  21372         soc_OAMP_REG_0090_BCM88675_B0r_fields,
  21373         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21374         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21375         -1,
  21376         -1,
  21377     },
  21378 #endif /* chips */
  21379 
  21380 #if defined(BCM_88680_A0)
  21381     { /* SOC_REG_INT_OAMP_REG_0090_BCM88680_A0r */
  21382         soc_block_list[22],
  21383         soc_genreg,
  21384         1,
  21385         0,
  21386         0x90,
  21387         0,
  21388         0,
  21389         1,
  21390         soc_OAMP_REG_0090_BCM88680_A0r_fields,
  21391         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21392         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21393         -1,
  21394         -1,
  21395     },
  21396 #endif /* chips */
  21397 
  21398 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  21399     defined(BCM_56270_A0)
  21400     { /* SOC_REG_INT_OAMP_REG_0091_BCM56260_A0r */
  21401         soc_block_list[22],
  21402         soc_genreg,
  21403         1,
  21404         0,
  21405         0x2009100,
  21406         0,
  21407         0,
  21408         1,
  21409         soc_OAMP_REG_0091_BCM56260_A0r_fields,
  21410         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21411         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21412         -1,
  21413         -1,
  21414     },
  21415 #endif /* chips */
  21416 
  21417 #if defined(BCM_88375_A0)
  21418     { /* SOC_REG_INT_OAMP_REG_0091_BCM88375_A0r */
  21419         soc_block_list[22],
  21420         soc_genreg,
  21421         1,
  21422         0,
  21423         0x91,
  21424         0,
  21425         0,
  21426         1,
  21427         soc_OAMP_REG_0091_BCM88375_A0r_fields,
  21428         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21429         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21430         -1,
  21431         -1,
  21432     },
  21433 #endif /* chips */
  21434 
  21435 #if defined(BCM_88375_B0)
  21436     { /* SOC_REG_INT_OAMP_REG_0091_BCM88375_B0r */
  21437         soc_block_list[22],
  21438         soc_genreg,
  21439         1,
  21440         0,
  21441         0x91,
  21442         0,
  21443         0,
  21444         1,
  21445         soc_OAMP_REG_0091_BCM88375_B0r_fields,
  21446         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21447         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21448         -1,
  21449         -1,
  21450     },
  21451 #endif /* chips */
  21452 
  21453 #if defined(BCM_88650_B0)
  21454     { /* SOC_REG_INT_OAMP_REG_0091_BCM88650_B0r */
  21455         soc_block_list[22],
  21456         soc_genreg,
  21457         1,
  21458         0,
  21459         0x91,
  21460         SOC_REG_FLAG_SIGNAL,
  21461         0,
  21462         1,
  21463         soc_OAMP_REG_0091_BCM88650_B0r_fields,
  21464         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21465         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21466         -1,
  21467         -1,
  21468     },
  21469 #endif /* chips */
  21470 
  21471 #if defined(BCM_88660_A0)
  21472     { /* SOC_REG_INT_OAMP_REG_0091_BCM88660_A0r */
  21473         soc_block_list[22],
  21474         soc_genreg,
  21475         1,
  21476         0,
  21477         0x91,
  21478         SOC_REG_FLAG_SIGNAL,
  21479         0,
  21480         1,
  21481         soc_OAMP_REG_0091_BCM88660_A0r_fields,
  21482         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21483         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21484         -1,
  21485         -1,
  21486     },
  21487 #endif /* chips */
  21488 
  21489 #if defined(BCM_88675_A0)
  21490     { /* SOC_REG_INT_OAMP_REG_0091_BCM88675_A0r */
  21491         soc_block_list[22],
  21492         soc_genreg,
  21493         1,
  21494         0,
  21495         0x91,
  21496         0,
  21497         0,
  21498         1,
  21499         soc_OAMP_REG_0091_BCM88675_A0r_fields,
  21500         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21501         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21502         -1,
  21503         -1,
  21504     },
  21505 #endif /* chips */
  21506 
  21507 #if defined(BCM_88675_B0)
  21508     { /* SOC_REG_INT_OAMP_REG_0091_BCM88675_B0r */
  21509         soc_block_list[22],
  21510         soc_genreg,
  21511         1,
  21512         0,
  21513         0x91,
  21514         0,
  21515         0,
  21516         1,
  21517         soc_OAMP_REG_0091_BCM88675_B0r_fields,
  21518         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21519         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21520         -1,
  21521         -1,
  21522     },
  21523 #endif /* chips */
  21524 
  21525 #if defined(BCM_88680_A0)
  21526     { /* SOC_REG_INT_OAMP_REG_0091_BCM88680_A0r */
  21527         soc_block_list[22],
  21528         soc_genreg,
  21529         1,
  21530         0,
  21531         0x91,
  21532         0,
  21533         0,
  21534         1,
  21535         soc_OAMP_REG_0091_BCM88680_A0r_fields,
  21536         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21538         -1,
  21539         -1,
  21540     },
  21541 #endif /* chips */
  21542 
  21543 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  21544     defined(BCM_56270_A0)
  21545     { /* SOC_REG_INT_OAMP_REG_0092_BCM56260_A0r */
  21546         soc_block_list[22],
  21547         soc_genreg,
  21548         1,
  21549         0,
  21550         0x2009200,
  21551         0,
  21552         0,
  21553         1,
  21554         soc_OAMP_REG_0092_BCM56260_A0r_fields,
  21555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21557         -1,
  21558         -1,
  21559     },
  21560 #endif /* chips */
  21561 
  21562 #if defined(BCM_88375_A0)
  21563     { /* SOC_REG_INT_OAMP_REG_0092_BCM88375_A0r */
  21564         soc_block_list[22],
  21565         soc_genreg,
  21566         1,
  21567         0,
  21568         0x92,
  21569         0,
  21570         0,
  21571         1,
  21572         soc_OAMP_REG_0092_BCM88375_A0r_fields,
  21573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21574         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21575         -1,
  21576         -1,
  21577     },
  21578 #endif /* chips */
  21579 
  21580 #if defined(BCM_88375_B0)
  21581     { /* SOC_REG_INT_OAMP_REG_0092_BCM88375_B0r */
  21582         soc_block_list[22],
  21583         soc_genreg,
  21584         1,
  21585         0,
  21586         0x92,
  21587         0,
  21588         0,
  21589         1,
  21590         soc_OAMP_REG_0092_BCM88375_B0r_fields,
  21591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21592         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21593         -1,
  21594         -1,
  21595     },
  21596 #endif /* chips */
  21597 
  21598 #if defined(BCM_88650_B0)
  21599     { /* SOC_REG_INT_OAMP_REG_0092_BCM88650_B0r */
  21600         soc_block_list[22],
  21601         soc_genreg,
  21602         1,
  21603         0,
  21604         0x92,
  21605         SOC_REG_FLAG_SIGNAL,
  21606         0,
  21607         1,
  21608         soc_OAMP_REG_0092_BCM88650_B0r_fields,
  21609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21610         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21611         -1,
  21612         -1,
  21613     },
  21614 #endif /* chips */
  21615 
  21616 #if defined(BCM_88660_A0)
  21617     { /* SOC_REG_INT_OAMP_REG_0092_BCM88660_A0r */
  21618         soc_block_list[22],
  21619         soc_genreg,
  21620         1,
  21621         0,
  21622         0x92,
  21623         SOC_REG_FLAG_SIGNAL,
  21624         0,
  21625         1,
  21626         soc_OAMP_REG_0092_BCM88660_A0r_fields,
  21627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21628         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21629         -1,
  21630         -1,
  21631     },
  21632 #endif /* chips */
  21633 
  21634 #if defined(BCM_88675_A0)
  21635     { /* SOC_REG_INT_OAMP_REG_0092_BCM88675_A0r */
  21636         soc_block_list[22],
  21637         soc_genreg,
  21638         1,
  21639         0,
  21640         0x92,
  21641         0,
  21642         0,
  21643         1,
  21644         soc_OAMP_REG_0092_BCM88675_A0r_fields,
  21645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21646         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21647         -1,
  21648         -1,
  21649     },
  21650 #endif /* chips */
  21651 
  21652 #if defined(BCM_88675_B0)
  21653     { /* SOC_REG_INT_OAMP_REG_0092_BCM88675_B0r */
  21654         soc_block_list[22],
  21655         soc_genreg,
  21656         1,
  21657         0,
  21658         0x92,
  21659         0,
  21660         0,
  21661         1,
  21662         soc_OAMP_REG_0092_BCM88675_B0r_fields,
  21663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21664         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21665         -1,
  21666         -1,
  21667     },
  21668 #endif /* chips */
  21669 
  21670 #if defined(BCM_88680_A0)
  21671     { /* SOC_REG_INT_OAMP_REG_0092_BCM88680_A0r */
  21672         soc_block_list[22],
  21673         soc_genreg,
  21674         1,
  21675         0,
  21676         0x92,
  21677         0,
  21678         0,
  21679         1,
  21680         soc_OAMP_REG_0092_BCM88680_A0r_fields,
  21681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21682         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21683         -1,
  21684         -1,
  21685     },
  21686 #endif /* chips */
  21687 
  21688 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  21689     defined(BCM_56270_A0)
  21690     { /* SOC_REG_INT_OAMP_REG_0093_BCM56260_A0r */
  21691         soc_block_list[22],
  21692         soc_genreg,
  21693         1,
  21694         0,
  21695         0x2009300,
  21696         0,
  21697         0,
  21698         1,
  21699         soc_OAMP_REG_0093_BCM56260_A0r_fields,
  21700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21702         -1,
  21703         -1,
  21704     },
  21705 #endif /* chips */
  21706 
  21707 #if defined(BCM_88690_B0)
  21708     { /* SOC_REG_INT_OAMP_REG_0098_BCM88690_B0r */
  21709         soc_block_list[22],
  21710         soc_genreg,
  21711         1,
  21712         0,
  21713         0x98,
  21714         SOC_REG_FLAG_64_BITS |
  21715                           SOC_REG_FLAG_RO,
  21716         SOC_REG_FLAG_COUNTER_FEILDS |
  21717                           SOC_REG_FLAG_INIT_ON_READ,
  21718         4,
  21719         soc_OAMP_REG_0098_BCM88690_B0r_fields,
  21720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21721         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21722         -1,
  21723         -1,
  21724     },
  21725 #endif /* chips */
  21726 
  21727 #if defined(BCM_88690_A0)
  21728     { /* SOC_REG_INT_OAMP_REG_00A0r */
  21729         soc_block_list[22],
  21730         soc_genreg,
  21731         1,
  21732         0,
  21733         0xa0,
  21734         0,
  21735         0,
  21736         1,
  21737         soc_OAMP_REG_00A0r_fields,
  21738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21739         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21740         -1,
  21741         -1,
  21742     },
  21743 #endif /* chips */
  21744 
  21745 #if defined(BCM_88690_A0)
  21746     { /* SOC_REG_INT_OAMP_REG_00A4r */
  21747         soc_block_list[22],
  21748         soc_genreg,
  21749         1,
  21750         0,
  21751         0xa4,
  21752         SOC_REG_FLAG_ABOVE_64_BITS,
  21753         0,
  21754         65,
  21755         soc_OAMP_REG_00A4r_fields,
  21756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21758         -1,
  21759         -1,
  21760     },
  21761 #endif /* chips */
  21762 
  21763 #if defined(BCM_88690_A0)
  21764     { /* SOC_REG_INT_OAMP_REG_00A6r */
  21765         soc_block_list[22],
  21766         soc_genreg,
  21767         1,
  21768         0,
  21769         0xa6,
  21770         SOC_REG_FLAG_ABOVE_64_BITS,
  21771         0,
  21772         65,
  21773         soc_OAMP_REG_00A6r_fields,
  21774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21775         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21776         -1,
  21777         -1,
  21778     },
  21779 #endif /* chips */
  21780 
  21781 #if defined(BCM_88690_B0)
  21782     { /* SOC_REG_INT_OAMP_REG_00A0_BCM88690_B0r */
  21783         soc_block_list[22],
  21784         soc_genreg,
  21785         1,
  21786         0,
  21787         0xa0,
  21788         0,
  21789         0,
  21790         1,
  21791         soc_OAMP_REG_00A0_BCM88690_B0r_fields,
  21792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21793         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21794         -1,
  21795         -1,
  21796     },
  21797 #endif /* chips */
  21798 
  21799 #if defined(BCM_88690_A0)
  21800     { /* SOC_REG_INT_OAMP_REG_00AAr */
  21801         soc_block_list[22],
  21802         soc_genreg,
  21803         1,
  21804         0,
  21805         0xaa,
  21806         0,
  21807         0,
  21808         1,
  21809         soc_OAMP_REG_00AAr_fields,
  21810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21811         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21812         -1,
  21813         -1,
  21814     },
  21815 #endif /* chips */
  21816 
  21817 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  21818     defined(BCM_56270_A0)
  21819     { /* SOC_REG_INT_OAMP_REG_00ADr */
  21820         soc_block_list[22],
  21821         soc_genreg,
  21822         1,
  21823         0,
  21824         0x200ad00,
  21825         SOC_REG_FLAG_64_BITS,
  21826         0,
  21827         17,
  21828         soc_OAMP_REG_00ADr_fields,
  21829         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  21830         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  21831         -1,
  21832         -1,
  21833     },
  21834 #endif /* chips */
  21835 
  21836 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  21837     defined(BCM_56270_A0)
  21838     { /* SOC_REG_INT_OAMP_REG_00AEr */
  21839         soc_block_list[22],
  21840         soc_genreg,
  21841         1,
  21842         0,
  21843         0x200ae00,
  21844         0,
  21845         0,
  21846         6,
  21847         soc_OAMP_REG_00AEr_fields,
  21848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21849         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  21850         -1,
  21851         -1,
  21852     },
  21853 #endif /* chips */
  21854 
  21855 #if defined(BCM_88650_A0)
  21856     { /* SOC_REG_INT_OAMP_REG_00AFr */
  21857         soc_block_list[22],
  21858         soc_genreg,
  21859         1,
  21860         0,
  21861         0xaf,
  21862         SOC_REG_FLAG_SIGNAL,
  21863         0,
  21864         6,
  21865         soc_OAMP_REG_00AFr_fields,
  21866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21867         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  21868         -1,
  21869         -1,
  21870     },
  21871 #endif /* chips */
  21872 
  21873 #if defined(BCM_88650_B0)
  21874     { /* SOC_REG_INT_OAMP_REG_00AF_BCM88650_B0r */
  21875         soc_block_list[22],
  21876         soc_genreg,
  21877         1,
  21878         0,
  21879         0xaf,
  21880         SOC_REG_FLAG_SIGNAL,
  21881         0,
  21882         6,
  21883         soc_OAMP_REG_00AF_BCM88650_B0r_fields,
  21884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21885         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  21886         -1,
  21887         -1,
  21888     },
  21889 #endif /* chips */
  21890 
  21891 #if defined(BCM_88660_A0)
  21892     { /* SOC_REG_INT_OAMP_REG_00AF_BCM88660_A0r */
  21893         soc_block_list[22],
  21894         soc_genreg,
  21895         1,
  21896         0,
  21897         0xaf,
  21898         SOC_REG_FLAG_SIGNAL,
  21899         0,
  21900         6,
  21901         soc_OAMP_REG_00AF_BCM88660_A0r_fields,
  21902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21903         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  21904         -1,
  21905         -1,
  21906     },
  21907 #endif /* chips */
  21908 
  21909 #if defined(BCM_88650_A0)
  21910     { /* SOC_REG_INT_OAMP_REG_00B0r */
  21911         soc_block_list[22],
  21912         soc_genreg,
  21913         1,
  21914         0,
  21915         0xb0,
  21916         0,
  21917         0,
  21918         1,
  21919         soc_OAMP_REG_00B0r_fields,
  21920         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  21921         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21922         -1,
  21923         -1,
  21924     },
  21925 #endif /* chips */
  21926 
  21927 #if defined(BCM_88650_A0)
  21928     { /* SOC_REG_INT_OAMP_REG_00B1r */
  21929         soc_block_list[22],
  21930         soc_genreg,
  21931         1,
  21932         0,
  21933         0xb1,
  21934         SOC_REG_FLAG_RO,
  21935         0,
  21936         3,
  21937         soc_OAMP_REG_00B1r_fields,
  21938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21939         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21940         -1,
  21941         -1,
  21942     },
  21943 #endif /* chips */
  21944 
  21945 #if defined(BCM_88650_A0)
  21946     { /* SOC_REG_INT_OAMP_REG_00B2r */
  21947         soc_block_list[22],
  21948         soc_genreg,
  21949         1,
  21950         0,
  21951         0xb2,
  21952         0,
  21953         0,
  21954         1,
  21955         soc_OAMP_REG_00B2r_fields,
  21956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21957         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  21958         -1,
  21959         -1,
  21960     },
  21961 #endif /* chips */
  21962 
  21963 #if defined(BCM_88650_A0)
  21964     { /* SOC_REG_INT_OAMP_REG_00B3r */
  21965         soc_block_list[22],
  21966         soc_genreg,
  21967         1,
  21968         0,
  21969         0xb3,
  21970         SOC_REG_FLAG_RO,
  21971         0,
  21972         1,
  21973         soc_OAMP_REG_00B3r_fields,
  21974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21975         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21976         -1,
  21977         -1,
  21978     },
  21979 #endif /* chips */
  21980 
  21981 #if defined(BCM_88650_B0)
  21982     { /* SOC_REG_INT_OAMP_REG_00B0_BCM88650_B0r */
  21983         soc_block_list[22],
  21984         soc_genreg,
  21985         1,
  21986         0,
  21987         0xb0,
  21988         0,
  21989         0,
  21990         1,
  21991         soc_OAMP_REG_00B0_BCM88650_B0r_fields,
  21992         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  21993         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21994         -1,
  21995         -1,
  21996     },
  21997 #endif /* chips */
  21998 
  21999 #if defined(BCM_88650_B0)
  22000     { /* SOC_REG_INT_OAMP_REG_00B1_BCM88650_B0r */
  22001         soc_block_list[22],
  22002         soc_genreg,
  22003         1,
  22004         0,
  22005         0xb1,
  22006         SOC_REG_FLAG_RO,
  22007         0,
  22008         3,
  22009         soc_OAMP_REG_00B1_BCM88650_B0r_fields,
  22010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22011         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22012         -1,
  22013         -1,
  22014     },
  22015 #endif /* chips */
  22016 
  22017 #if defined(BCM_88650_B0)
  22018     { /* SOC_REG_INT_OAMP_REG_00B2_BCM88650_B0r */
  22019         soc_block_list[22],
  22020         soc_genreg,
  22021         1,
  22022         0,
  22023         0xb2,
  22024         0,
  22025         0,
  22026         1,
  22027         soc_OAMP_REG_00B2_BCM88650_B0r_fields,
  22028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22029         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  22030         -1,
  22031         -1,
  22032     },
  22033 #endif /* chips */
  22034 
  22035 #if defined(BCM_88650_B0)
  22036     { /* SOC_REG_INT_OAMP_REG_00B3_BCM88650_B0r */
  22037         soc_block_list[22],
  22038         soc_genreg,
  22039         1,
  22040         0,
  22041         0xb3,
  22042         SOC_REG_FLAG_RO,
  22043         0,
  22044         1,
  22045         soc_OAMP_REG_00B3_BCM88650_B0r_fields,
  22046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22047         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22048         -1,
  22049         -1,
  22050     },
  22051 #endif /* chips */
  22052 
  22053 #if defined(BCM_88690_A0)
  22054     { /* SOC_REG_INT_OAMP_REG_00C2r */
  22055         soc_block_list[22],
  22056         soc_genreg,
  22057         1,
  22058         0,
  22059         0xc2,
  22060         0,
  22061         0,
  22062         6,
  22063         soc_OAMP_REG_00C2r_fields,
  22064         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  22065         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22066         -1,
  22067         -1,
  22068     },
  22069 #endif /* chips */
  22070 
  22071 #if defined(BCM_88690_A0)
  22072     { /* SOC_REG_INT_OAMP_REG_00C6r */
  22073         soc_block_list[22],
  22074         soc_genreg,
  22075         1,
  22076         0,
  22077         0xc6,
  22078         0,
  22079         0,
  22080         4,
  22081         soc_OAMP_REG_00C6r_fields,
  22082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22083         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  22084         -1,
  22085         -1,
  22086     },
  22087 #endif /* chips */
  22088 
  22089 #if defined(BCM_88690_B0)
  22090     { /* SOC_REG_INT_OAMP_REG_00C2_BCM88690_B0r */
  22091         soc_block_list[22],
  22092         soc_genreg,
  22093         1,
  22094         0,
  22095         0xc2,
  22096         0,
  22097         0,
  22098         6,
  22099         soc_OAMP_REG_00C2_BCM88690_B0r_fields,
  22100         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  22101         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22102         -1,
  22103         -1,
  22104     },
  22105 #endif /* chips */
  22106 
  22107 #if defined(BCM_88690_B0)
  22108     { /* SOC_REG_INT_OAMP_REG_00C6_BCM88690_B0r */
  22109         soc_block_list[22],
  22110         soc_genreg,
  22111         1,
  22112         0,
  22113         0xc6,
  22114         0,
  22115         0,
  22116         4,
  22117         soc_OAMP_REG_00C6_BCM88690_B0r_fields,
  22118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22119         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  22120         -1,
  22121         -1,
  22122     },
  22123 #endif /* chips */
  22124 
  22125 #if defined(BCM_88650_A0)
  22126     { /* SOC_REG_INT_OAMP_REG_00CFr */
  22127         soc_block_list[22],
  22128         soc_genreg,
  22129         1,
  22130         0,
  22131         0xcf,
  22132         0,
  22133         0,
  22134         6,
  22135         soc_OAMP_REG_00CFr_fields,
  22136         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  22137         SOC_RESET_MASK_DEC(0x0001c00f, 0x00000000)
  22138         -1,
  22139         -1,
  22140     },
  22141 #endif /* chips */
  22142 
  22143 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  22144     defined(BCM_56270_A0)
  22145     { /* SOC_REG_INT_OAMP_REG_011Br */
  22146         soc_block_list[22],
  22147         soc_genreg,
  22148         1,
  22149         0,
  22150         0x2011b00,
  22151         SOC_REG_FLAG_RO,
  22152         0,
  22153         1,
  22154         soc_OAMP_REG_011Br_fields,
  22155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22156         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22157         -1,
  22158         -1,
  22159     },
  22160 #endif /* chips */
  22161 
  22162 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  22163     defined(BCM_56270_A0)
  22164     { /* SOC_REG_INT_OAMP_REG_011Cr */
  22165         soc_block_list[22],
  22166         soc_genreg,
  22167         1,
  22168         0,
  22169         0x2011c00,
  22170         SOC_REG_FLAG_RO,
  22171         0,
  22172         1,
  22173         soc_OAMP_REG_011Br_fields,
  22174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22175         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22176         -1,
  22177         -1,
  22178     },
  22179 #endif /* chips */
  22180 
  22181 #if defined(BCM_88690_B0)
  22182     { /* SOC_REG_INT_OAMP_REG_0127_BCM88690_B0r */
  22183         soc_block_list[22],
  22184         soc_genreg,
  22185         1,
  22186         0,
  22187         0x127,
  22188         SOC_REG_FLAG_64_BITS,
  22189         0,
  22190         16,
  22191         soc_OAMP_REG_0127_BCM88690_B0r_fields,
  22192         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  22193         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  22194         -1,
  22195         -1,
  22196     },
  22197 #endif /* chips */
  22198 
  22199 #if defined(BCM_88690_B0)
  22200     { /* SOC_REG_INT_OAMP_REG_0129_BCM88690_B0r */
  22201         soc_block_list[22],
  22202         soc_genreg,
  22203         1,
  22204         0,
  22205         0x129,
  22206         SOC_REG_FLAG_ABOVE_64_BITS,
  22207         0,
  22208         18,
  22209         soc_OAMP_REG_0129_BCM88690_B0r_fields,
  22210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22212         -1,
  22213         -1,
  22214     },
  22215 #endif /* chips */
  22216 
  22217 #if defined(BCM_88270_A0)
  22218     { /* SOC_REG_INT_OAMP_REG_0130_BCM88270_A0r */
  22219         soc_block_list[22],
  22220         soc_genreg,
  22221         1,
  22222         0,
  22223         0x130,
  22224         SOC_REG_FLAG_64_BITS,
  22225         0,
  22226         16,
  22227         soc_OAMP_REG_0130_BCM88270_A0r_fields,
  22228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22229         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  22230         -1,
  22231         -1,
  22232     },
  22233 #endif /* chips */
  22234 
  22235 #if defined(BCM_88650_B0)
  22236     { /* SOC_REG_INT_OAMP_REG_0141_BCM88650_B0r */
  22237         soc_block_list[22],
  22238         soc_genreg,
  22239         1,
  22240         0,
  22241         0x141,
  22242         SOC_REG_FLAG_RO,
  22243         0,
  22244         1,
  22245         soc_OAMP_REG_0141_BCM88650_B0r_fields,
  22246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22247         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22248         -1,
  22249         -1,
  22250     },
  22251 #endif /* chips */
  22252 
  22253 #if defined(BCM_88650_B0)
  22254     { /* SOC_REG_INT_OAMP_REG_0142_BCM88650_B0r */
  22255         soc_block_list[22],
  22256         soc_genreg,
  22257         1,
  22258         0,
  22259         0x142,
  22260         SOC_REG_FLAG_RO,
  22261         0,
  22262         1,
  22263         soc_OAMP_REG_0142_BCM88650_B0r_fields,
  22264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22265         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22266         -1,
  22267         -1,
  22268     },
  22269 #endif /* chips */
  22270 
  22271 #if defined(BCM_88690_B0)
  22272     { /* SOC_REG_INT_OAMP_REG_0165_BCM88690_B0r */
  22273         soc_block_list[22],
  22274         soc_genreg,
  22275         1,
  22276         0,
  22277         0x165,
  22278         SOC_REG_FLAG_64_BITS |
  22279                           SOC_REG_FLAG_RO |
  22280                           SOC_REG_FLAG_SIGNAL,
  22281         0,
  22282         2,
  22283         soc_OAMP_REG_0165_BCM88690_B0r_fields,
  22284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22285         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22286         -1,
  22287         -1,
  22288     },
  22289 #endif /* chips */
  22290 
  22291 #if defined(BCM_88690_B0)
  22292     { /* SOC_REG_INT_OAMP_REG_0167_BCM88690_B0r */
  22293         soc_block_list[22],
  22294         soc_genreg,
  22295         1,
  22296         0,
  22297         0x167,
  22298         SOC_REG_FLAG_64_BITS |
  22299                           SOC_REG_FLAG_RO |
  22300                           SOC_REG_FLAG_SIGNAL,
  22301         0,
  22302         2,
  22303         soc_OAMP_REG_0167_BCM88690_B0r_fields,
  22304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22305         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22306         -1,
  22307         -1,
  22308     },
  22309 #endif /* chips */
  22310 
  22311 #if defined(BCM_88375_A0)
  22312     { /* SOC_REG_INT_OAMP_REG_0168_BCM88375_A0r */
  22313         soc_block_list[22],
  22314         soc_genreg,
  22315         1,
  22316         0,
  22317         0x168,
  22318         SOC_REG_FLAG_RO |
  22319                           SOC_REG_FLAG_SIGNAL,
  22320         0,
  22321         1,
  22322         soc_OAMP_REG_0168_BCM88375_A0r_fields,
  22323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22324         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22325         -1,
  22326         -1,
  22327     },
  22328 #endif /* chips */
  22329 
  22330 #if defined(BCM_88375_B0)
  22331     { /* SOC_REG_INT_OAMP_REG_0168_BCM88375_B0r */
  22332         soc_block_list[22],
  22333         soc_genreg,
  22334         1,
  22335         0,
  22336         0x168,
  22337         SOC_REG_FLAG_RO |
  22338                           SOC_REG_FLAG_SIGNAL,
  22339         0,
  22340         1,
  22341         soc_OAMP_REG_0168_BCM88375_B0r_fields,
  22342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22343         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22344         -1,
  22345         -1,
  22346     },
  22347 #endif /* chips */
  22348 
  22349 #if defined(BCM_88675_B0)
  22350     { /* SOC_REG_INT_OAMP_REG_0168_BCM88675_B0r */
  22351         soc_block_list[22],
  22352         soc_genreg,
  22353         1,
  22354         0,
  22355         0x168,
  22356         SOC_REG_FLAG_RO |
  22357                           SOC_REG_FLAG_SIGNAL,
  22358         0,
  22359         1,
  22360         soc_OAMP_REG_0168_BCM88675_B0r_fields,
  22361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22362         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22363         -1,
  22364         -1,
  22365     },
  22366 #endif /* chips */
  22367 
  22368 #if defined(BCM_88680_A0)
  22369     { /* SOC_REG_INT_OAMP_REG_0168_BCM88680_A0r */
  22370         soc_block_list[22],
  22371         soc_genreg,
  22372         1,
  22373         0,
  22374         0x168,
  22375         SOC_REG_FLAG_RO |
  22376                           SOC_REG_FLAG_SIGNAL,
  22377         0,
  22378         1,
  22379         soc_OAMP_REG_0168_BCM88680_A0r_fields,
  22380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22381         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22382         -1,
  22383         -1,
  22384     },
  22385 #endif /* chips */
  22386 
  22387 #if defined(BCM_88375_A0)
  22388     { /* SOC_REG_INT_OAMP_REG_0169_BCM88375_A0r */
  22389         soc_block_list[22],
  22390         soc_genreg,
  22391         1,
  22392         0,
  22393         0x169,
  22394         SOC_REG_FLAG_RO |
  22395                           SOC_REG_FLAG_SIGNAL,
  22396         0,
  22397         2,
  22398         soc_OAMP_REG_0169_BCM88375_A0r_fields,
  22399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22400         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22401         -1,
  22402         -1,
  22403     },
  22404 #endif /* chips */
  22405 
  22406 #if defined(BCM_88375_B0)
  22407     { /* SOC_REG_INT_OAMP_REG_0169_BCM88375_B0r */
  22408         soc_block_list[22],
  22409         soc_genreg,
  22410         1,
  22411         0,
  22412         0x169,
  22413         SOC_REG_FLAG_RO |
  22414                           SOC_REG_FLAG_SIGNAL,
  22415         0,
  22416         2,
  22417         soc_OAMP_REG_0169_BCM88375_B0r_fields,
  22418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22420         -1,
  22421         -1,
  22422     },
  22423 #endif /* chips */
  22424 
  22425 #if defined(BCM_88675_B0)
  22426     { /* SOC_REG_INT_OAMP_REG_0169_BCM88675_B0r */
  22427         soc_block_list[22],
  22428         soc_genreg,
  22429         1,
  22430         0,
  22431         0x169,
  22432         SOC_REG_FLAG_RO |
  22433                           SOC_REG_FLAG_SIGNAL,
  22434         0,
  22435         2,
  22436         soc_OAMP_REG_0169_BCM88675_B0r_fields,
  22437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22438         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22439         -1,
  22440         -1,
  22441     },
  22442 #endif /* chips */
  22443 
  22444 #if defined(BCM_88680_A0)
  22445     { /* SOC_REG_INT_OAMP_REG_0169_BCM88680_A0r */
  22446         soc_block_list[22],
  22447         soc_genreg,
  22448         1,
  22449         0,
  22450         0x169,
  22451         SOC_REG_FLAG_RO |
  22452                           SOC_REG_FLAG_SIGNAL,
  22453         0,
  22454         2,
  22455         soc_OAMP_REG_0169_BCM88680_A0r_fields,
  22456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22457         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22458         -1,
  22459         -1,
  22460     },
  22461 #endif /* chips */
  22462 
  22463 #if defined(BCM_88470_A0)
  22464     { /* SOC_REG_INT_OAMP_REG_016Ar */
  22465         soc_block_list[22],
  22466         soc_genreg,
  22467         1,
  22468         0,
  22469         0x16a,
  22470         SOC_REG_FLAG_RO |
  22471                           SOC_REG_FLAG_SIGNAL,
  22472         0,
  22473         2,
  22474         soc_OAMP_REG_016Ar_fields,
  22475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22477         -1,
  22478         -1,
  22479     },
  22480 #endif /* chips */
  22481 
  22482 #if defined(BCM_88270_A0)
  22483     { /* SOC_REG_INT_OAMP_REG_016A_BCM88270_A0r */
  22484         soc_block_list[22],
  22485         soc_genreg,
  22486         1,
  22487         0,
  22488         0x16a,
  22489         SOC_REG_FLAG_RO |
  22490                           SOC_REG_FLAG_SIGNAL,
  22491         0,
  22492         2,
  22493         soc_OAMP_REG_016A_BCM88270_A0r_fields,
  22494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22495         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22496         -1,
  22497         -1,
  22498     },
  22499 #endif /* chips */
  22500 
  22501 #if defined(BCM_88470_B0)
  22502     { /* SOC_REG_INT_OAMP_REG_016A_BCM88470_B0r */
  22503         soc_block_list[22],
  22504         soc_genreg,
  22505         1,
  22506         0,
  22507         0x16a,
  22508         SOC_REG_FLAG_RO |
  22509                           SOC_REG_FLAG_SIGNAL,
  22510         0,
  22511         2,
  22512         soc_OAMP_REG_016A_BCM88470_B0r_fields,
  22513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22514         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22515         -1,
  22516         -1,
  22517     },
  22518 #endif /* chips */
  22519 
  22520 #if defined(BCM_88470_A0)
  22521     { /* SOC_REG_INT_OAMP_REG_016Br */
  22522         soc_block_list[22],
  22523         soc_genreg,
  22524         1,
  22525         0,
  22526         0x16b,
  22527         SOC_REG_FLAG_RO |
  22528                           SOC_REG_FLAG_SIGNAL,
  22529         0,
  22530         2,
  22531         soc_OAMP_REG_016Br_fields,
  22532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22534         -1,
  22535         -1,
  22536     },
  22537 #endif /* chips */
  22538 
  22539 #if defined(BCM_88270_A0)
  22540     { /* SOC_REG_INT_OAMP_REG_016B_BCM88270_A0r */
  22541         soc_block_list[22],
  22542         soc_genreg,
  22543         1,
  22544         0,
  22545         0x16b,
  22546         SOC_REG_FLAG_RO |
  22547                           SOC_REG_FLAG_SIGNAL,
  22548         0,
  22549         2,
  22550         soc_OAMP_REG_016B_BCM88270_A0r_fields,
  22551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22552         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22553         -1,
  22554         -1,
  22555     },
  22556 #endif /* chips */
  22557 
  22558 #if defined(BCM_88470_B0)
  22559     { /* SOC_REG_INT_OAMP_REG_016B_BCM88470_B0r */
  22560         soc_block_list[22],
  22561         soc_genreg,
  22562         1,
  22563         0,
  22564         0x16b,
  22565         SOC_REG_FLAG_RO |
  22566                           SOC_REG_FLAG_SIGNAL,
  22567         0,
  22568         2,
  22569         soc_OAMP_REG_016B_BCM88470_B0r_fields,
  22570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22572         -1,
  22573         -1,
  22574     },
  22575 #endif /* chips */
  22576 
  22577 #if defined(BCM_88690_B0)
  22578     { /* SOC_REG_INT_OAMP_REG_0199_BCM88690_B0r */
  22579         soc_block_list[22],
  22580         soc_genreg,
  22581         1,
  22582         0,
  22583         0x199,
  22584         SOC_REG_FLAG_RO |
  22585                           SOC_REG_FLAG_SIGNAL,
  22586         SOC_REG_FLAG_INIT_ON_READ,
  22587         17,
  22588         soc_OAMP_REG_0199_BCM88690_B0r_fields,
  22589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22590         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  22591         -1,
  22592         -1,
  22593     },
  22594 #endif /* chips */
  22595 
  22596 #if defined(BCM_88650_B0)
  22597     { /* SOC_REG_INT_OAMP_REG_0201_BCM88650_B0r */
  22598         soc_block_list[22],
  22599         soc_genreg,
  22600         1,
  22601         0,
  22602         0x201,
  22603         0,
  22604         0,
  22605         1,
  22606         soc_OAMP_REG_0201_BCM88650_B0r_fields,
  22607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22608         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22609         -1,
  22610         -1,
  22611     },
  22612 #endif /* chips */
  22613 
  22614 #if defined(BCM_88660_A0)
  22615     { /* SOC_REG_INT_OAMP_REG_0201_BCM88660_A0r */
  22616         soc_block_list[22],
  22617         soc_genreg,
  22618         1,
  22619         0,
  22620         0x201,
  22621         0,
  22622         0,
  22623         1,
  22624         soc_OAMP_REG_0201_BCM88660_A0r_fields,
  22625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22626         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22627         -1,
  22628         -1,
  22629     },
  22630 #endif /* chips */
  22631 
  22632 #if defined(BCM_88650_A0)
  22633     { /* SOC_REG_INT_OAMP_REG_020Dr */
  22634         soc_block_list[22],
  22635         soc_genreg,
  22636         1,
  22637         0,
  22638         0x20d,
  22639         0,
  22640         0,
  22641         3,
  22642         soc_OAMP_REG_020Dr_fields,
  22643         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22644         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22645         -1,
  22646         -1,
  22647     },
  22648 #endif /* chips */
  22649 
  22650 #if defined(BCM_88650_B0)
  22651     { /* SOC_REG_INT_OAMP_REG_020D_BCM88650_B0r */
  22652         soc_block_list[22],
  22653         soc_genreg,
  22654         1,
  22655         0,
  22656         0x20d,
  22657         0,
  22658         0,
  22659         3,
  22660         soc_OAMP_REG_020D_BCM88650_B0r_fields,
  22661         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22662         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22663         -1,
  22664         -1,
  22665     },
  22666 #endif /* chips */
  22667 
  22668 #if defined(BCM_88660_A0)
  22669     { /* SOC_REG_INT_OAMP_REG_020D_BCM88660_A0r */
  22670         soc_block_list[22],
  22671         soc_genreg,
  22672         1,
  22673         0,
  22674         0x20d,
  22675         0,
  22676         0,
  22677         3,
  22678         soc_OAMP_REG_020D_BCM88660_A0r_fields,
  22679         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22680         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22681         -1,
  22682         -1,
  22683     },
  22684 #endif /* chips */
  22685 
  22686 #if defined(BCM_88675_A0)
  22687     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTERr */
  22688         soc_block_list[22],
  22689         soc_genreg,
  22690         1,
  22691         0,
  22692         0x215,
  22693         SOC_REG_FLAG_RO |
  22694                           SOC_REG_FLAG_SIGNAL,
  22695         0,
  22696         1,
  22697         soc_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTERr_fields,
  22698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22699         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22700         -1,
  22701         -1,
  22702     },
  22703 #endif /* chips */
  22704 
  22705 #if defined(BCM_88270_A0)
  22706     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88270_A0r */
  22707         soc_block_list[22],
  22708         soc_genreg,
  22709         1,
  22710         0,
  22711         0x215,
  22712         SOC_REG_FLAG_RO |
  22713                           SOC_REG_FLAG_SIGNAL,
  22714         0,
  22715         1,
  22716         soc_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88270_A0r_fields,
  22717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22718         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22719         -1,
  22720         -1,
  22721     },
  22722 #endif /* chips */
  22723 
  22724 #if defined(BCM_88375_A0)
  22725     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88375_A0r */
  22726         soc_block_list[22],
  22727         soc_genreg,
  22728         1,
  22729         0,
  22730         0x215,
  22731         SOC_REG_FLAG_RO |
  22732                           SOC_REG_FLAG_SIGNAL,
  22733         0,
  22734         1,
  22735         soc_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88375_A0r_fields,
  22736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22737         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22738         -1,
  22739         -1,
  22740     },
  22741 #endif /* chips */
  22742 
  22743 #if defined(BCM_88375_B0)
  22744     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88375_B0r */
  22745         soc_block_list[22],
  22746         soc_genreg,
  22747         1,
  22748         0,
  22749         0x215,
  22750         SOC_REG_FLAG_RO |
  22751                           SOC_REG_FLAG_SIGNAL,
  22752         0,
  22753         1,
  22754         soc_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88375_B0r_fields,
  22755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22756         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22757         -1,
  22758         -1,
  22759     },
  22760 #endif /* chips */
  22761 
  22762 #if defined(BCM_88470_A0)
  22763     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88470_A0r */
  22764         soc_block_list[22],
  22765         soc_genreg,
  22766         1,
  22767         0,
  22768         0x215,
  22769         SOC_REG_FLAG_RO |
  22770                           SOC_REG_FLAG_SIGNAL,
  22771         0,
  22772         1,
  22773         soc_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88470_A0r_fields,
  22774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22775         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22776         -1,
  22777         -1,
  22778     },
  22779 #endif /* chips */
  22780 
  22781 #if defined(BCM_88470_B0)
  22782     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88470_B0r */
  22783         soc_block_list[22],
  22784         soc_genreg,
  22785         1,
  22786         0,
  22787         0x215,
  22788         SOC_REG_FLAG_RO |
  22789                           SOC_REG_FLAG_SIGNAL,
  22790         0,
  22791         1,
  22792         soc_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88470_B0r_fields,
  22793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22794         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22795         -1,
  22796         -1,
  22797     },
  22798 #endif /* chips */
  22799 
  22800 #if defined(BCM_88675_B0)
  22801     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88675_B0r */
  22802         soc_block_list[22],
  22803         soc_genreg,
  22804         1,
  22805         0,
  22806         0x215,
  22807         SOC_REG_FLAG_RO |
  22808                           SOC_REG_FLAG_SIGNAL,
  22809         0,
  22810         1,
  22811         soc_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88675_B0r_fields,
  22812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22813         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22814         -1,
  22815         -1,
  22816     },
  22817 #endif /* chips */
  22818 
  22819 #if defined(BCM_88680_A0)
  22820     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88680_A0r */
  22821         soc_block_list[22],
  22822         soc_genreg,
  22823         1,
  22824         0,
  22825         0x215,
  22826         SOC_REG_FLAG_RO |
  22827                           SOC_REG_FLAG_SIGNAL,
  22828         0,
  22829         1,
  22830         soc_OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER_BCM88680_A0r_fields,
  22831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22832         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22833         -1,
  22834         -1,
  22835     },
  22836 #endif /* chips */
  22837 
  22838 #if defined(BCM_88675_A0)
  22839     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTERr */
  22840         soc_block_list[22],
  22841         soc_genreg,
  22842         1,
  22843         0,
  22844         0x20d,
  22845         0,
  22846         0,
  22847         3,
  22848         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTERr_fields,
  22849         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22850         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22851         -1,
  22852         -1,
  22853     },
  22854 #endif /* chips */
  22855 
  22856 #if defined(BCM_88270_A0)
  22857     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88270_A0r */
  22858         soc_block_list[22],
  22859         soc_genreg,
  22860         1,
  22861         0,
  22862         0x20d,
  22863         0,
  22864         0,
  22865         3,
  22866         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88270_A0r_fields,
  22867         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22868         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22869         -1,
  22870         -1,
  22871     },
  22872 #endif /* chips */
  22873 
  22874 #if defined(BCM_88375_A0)
  22875     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88375_A0r */
  22876         soc_block_list[22],
  22877         soc_genreg,
  22878         1,
  22879         0,
  22880         0x20d,
  22881         0,
  22882         0,
  22883         3,
  22884         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88375_A0r_fields,
  22885         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22886         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22887         -1,
  22888         -1,
  22889     },
  22890 #endif /* chips */
  22891 
  22892 #if defined(BCM_88375_B0)
  22893     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88375_B0r */
  22894         soc_block_list[22],
  22895         soc_genreg,
  22896         1,
  22897         0,
  22898         0x20d,
  22899         0,
  22900         0,
  22901         3,
  22902         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88375_B0r_fields,
  22903         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22904         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22905         -1,
  22906         -1,
  22907     },
  22908 #endif /* chips */
  22909 
  22910 #if defined(BCM_88470_A0)
  22911     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88470_A0r */
  22912         soc_block_list[22],
  22913         soc_genreg,
  22914         1,
  22915         0,
  22916         0x20d,
  22917         0,
  22918         0,
  22919         3,
  22920         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88470_A0r_fields,
  22921         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22922         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22923         -1,
  22924         -1,
  22925     },
  22926 #endif /* chips */
  22927 
  22928 #if defined(BCM_88470_B0)
  22929     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88470_B0r */
  22930         soc_block_list[22],
  22931         soc_genreg,
  22932         1,
  22933         0,
  22934         0x20d,
  22935         0,
  22936         0,
  22937         3,
  22938         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88470_B0r_fields,
  22939         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22940         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22941         -1,
  22942         -1,
  22943     },
  22944 #endif /* chips */
  22945 
  22946 #if defined(BCM_88675_B0)
  22947     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88675_B0r */
  22948         soc_block_list[22],
  22949         soc_genreg,
  22950         1,
  22951         0,
  22952         0x20d,
  22953         0,
  22954         0,
  22955         3,
  22956         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88675_B0r_fields,
  22957         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22958         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22959         -1,
  22960         -1,
  22961     },
  22962 #endif /* chips */
  22963 
  22964 #if defined(BCM_88680_A0)
  22965     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88680_A0r */
  22966         soc_block_list[22],
  22967         soc_genreg,
  22968         1,
  22969         0,
  22970         0x20d,
  22971         0,
  22972         0,
  22973         3,
  22974         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER_BCM88680_A0r_fields,
  22975         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22976         SOC_RESET_MASK_DEC(0xffffff11, 0x00000000)
  22977         -1,
  22978         -1,
  22979     },
  22980 #endif /* chips */
  22981 
  22982 #if defined(BCM_88650_A0)
  22983     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICSr */
  22984         soc_block_list[22],
  22985         soc_genreg,
  22986         1,
  22987         0,
  22988         0x207,
  22989         0,
  22990         0,
  22991         3,
  22992         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICSr_fields,
  22993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22994         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  22995         -1,
  22996         -1,
  22997     },
  22998 #endif /* chips */
  22999 
  23000 #if defined(BCM_88675_A0)
  23001     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODEr */
  23002         soc_block_list[22],
  23003         soc_genreg,
  23004         1,
  23005         0,
  23006         0x208,
  23007         0,
  23008         0,
  23009         1,
  23010         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODEr_fields,
  23011         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  23012         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23013         -1,
  23014         -1,
  23015     },
  23016 #endif /* chips */
  23017 
  23018 #if defined(BCM_88270_A0)
  23019     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88270_A0r */
  23020         soc_block_list[22],
  23021         soc_genreg,
  23022         1,
  23023         0,
  23024         0x208,
  23025         0,
  23026         0,
  23027         1,
  23028         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88270_A0r_fields,
  23029         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  23030         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23031         -1,
  23032         -1,
  23033     },
  23034 #endif /* chips */
  23035 
  23036 #if defined(BCM_88375_A0)
  23037     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88375_A0r */
  23038         soc_block_list[22],
  23039         soc_genreg,
  23040         1,
  23041         0,
  23042         0x208,
  23043         0,
  23044         0,
  23045         1,
  23046         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88375_A0r_fields,
  23047         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  23048         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23049         -1,
  23050         -1,
  23051     },
  23052 #endif /* chips */
  23053 
  23054 #if defined(BCM_88375_B0)
  23055     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88375_B0r */
  23056         soc_block_list[22],
  23057         soc_genreg,
  23058         1,
  23059         0,
  23060         0x208,
  23061         0,
  23062         0,
  23063         1,
  23064         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88375_B0r_fields,
  23065         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  23066         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23067         -1,
  23068         -1,
  23069     },
  23070 #endif /* chips */
  23071 
  23072 #if defined(BCM_88470_A0)
  23073     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88470_A0r */
  23074         soc_block_list[22],
  23075         soc_genreg,
  23076         1,
  23077         0,
  23078         0x208,
  23079         0,
  23080         0,
  23081         1,
  23082         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88470_A0r_fields,
  23083         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  23084         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23085         -1,
  23086         -1,
  23087     },
  23088 #endif /* chips */
  23089 
  23090 #if defined(BCM_88470_B0)
  23091     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88470_B0r */
  23092         soc_block_list[22],
  23093         soc_genreg,
  23094         1,
  23095         0,
  23096         0x208,
  23097         0,
  23098         0,
  23099         1,
  23100         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88470_B0r_fields,
  23101         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  23102         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23103         -1,
  23104         -1,
  23105     },
  23106 #endif /* chips */
  23107 
  23108 #if defined(BCM_88675_B0)
  23109     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88675_B0r */
  23110         soc_block_list[22],
  23111         soc_genreg,
  23112         1,
  23113         0,
  23114         0x208,
  23115         0,
  23116         0,
  23117         1,
  23118         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88675_B0r_fields,
  23119         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  23120         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23121         -1,
  23122         -1,
  23123     },
  23124 #endif /* chips */
  23125 
  23126 #if defined(BCM_88680_A0)
  23127     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88680_A0r */
  23128         soc_block_list[22],
  23129         soc_genreg,
  23130         1,
  23131         0,
  23132         0x208,
  23133         0,
  23134         0,
  23135         1,
  23136         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE_BCM88680_A0r_fields,
  23137         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  23138         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23139         -1,
  23140         -1,
  23141     },
  23142 #endif /* chips */
  23143 
  23144 #if defined(BCM_88270_A0)
  23145     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88270_A0r */
  23146         soc_block_list[22],
  23147         soc_genreg,
  23148         1,
  23149         0,
  23150         0x207,
  23151         0,
  23152         0,
  23153         3,
  23154         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88270_A0r_fields,
  23155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23156         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23157         -1,
  23158         -1,
  23159     },
  23160 #endif /* chips */
  23161 
  23162 #if defined(BCM_88375_A0)
  23163     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88375_A0r */
  23164         soc_block_list[22],
  23165         soc_genreg,
  23166         1,
  23167         0,
  23168         0x207,
  23169         0,
  23170         0,
  23171         3,
  23172         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88375_A0r_fields,
  23173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23174         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23175         -1,
  23176         -1,
  23177     },
  23178 #endif /* chips */
  23179 
  23180 #if defined(BCM_88375_B0)
  23181     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88375_B0r */
  23182         soc_block_list[22],
  23183         soc_genreg,
  23184         1,
  23185         0,
  23186         0x207,
  23187         0,
  23188         0,
  23189         3,
  23190         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88375_B0r_fields,
  23191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23192         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23193         -1,
  23194         -1,
  23195     },
  23196 #endif /* chips */
  23197 
  23198 #if defined(BCM_88470_A0)
  23199     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88470_A0r */
  23200         soc_block_list[22],
  23201         soc_genreg,
  23202         1,
  23203         0,
  23204         0x207,
  23205         0,
  23206         0,
  23207         3,
  23208         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88470_A0r_fields,
  23209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23210         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23211         -1,
  23212         -1,
  23213     },
  23214 #endif /* chips */
  23215 
  23216 #if defined(BCM_88470_B0)
  23217     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88470_B0r */
  23218         soc_block_list[22],
  23219         soc_genreg,
  23220         1,
  23221         0,
  23222         0x207,
  23223         0,
  23224         0,
  23225         3,
  23226         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88470_B0r_fields,
  23227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23228         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23229         -1,
  23230         -1,
  23231     },
  23232 #endif /* chips */
  23233 
  23234 #if defined(BCM_88650_B0)
  23235     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88650_B0r */
  23236         soc_block_list[22],
  23237         soc_genreg,
  23238         1,
  23239         0,
  23240         0x207,
  23241         0,
  23242         0,
  23243         3,
  23244         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88650_B0r_fields,
  23245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23246         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23247         -1,
  23248         -1,
  23249     },
  23250 #endif /* chips */
  23251 
  23252 #if defined(BCM_88660_A0)
  23253     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88660_A0r */
  23254         soc_block_list[22],
  23255         soc_genreg,
  23256         1,
  23257         0,
  23258         0x207,
  23259         0,
  23260         0,
  23261         3,
  23262         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88660_A0r_fields,
  23263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23264         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23265         -1,
  23266         -1,
  23267     },
  23268 #endif /* chips */
  23269 
  23270 #if defined(BCM_88675_A0)
  23271     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88675_A0r */
  23272         soc_block_list[22],
  23273         soc_genreg,
  23274         1,
  23275         0,
  23276         0x207,
  23277         0,
  23278         0,
  23279         3,
  23280         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88675_A0r_fields,
  23281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23282         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23283         -1,
  23284         -1,
  23285     },
  23286 #endif /* chips */
  23287 
  23288 #if defined(BCM_88675_B0)
  23289     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88675_B0r */
  23290         soc_block_list[22],
  23291         soc_genreg,
  23292         1,
  23293         0,
  23294         0x207,
  23295         0,
  23296         0,
  23297         3,
  23298         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88675_B0r_fields,
  23299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23300         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23301         -1,
  23302         -1,
  23303     },
  23304 #endif /* chips */
  23305 
  23306 #if defined(BCM_88680_A0)
  23307     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88680_A0r */
  23308         soc_block_list[22],
  23309         soc_genreg,
  23310         1,
  23311         0,
  23312         0x207,
  23313         0,
  23314         0,
  23315         3,
  23316         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_BCM88680_A0r_fields,
  23317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23318         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23319         -1,
  23320         -1,
  23321     },
  23322 #endif /* chips */
  23323 
  23324 #if defined(BCM_88675_A0)
  23325     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEXr */
  23326         soc_block_list[22],
  23327         soc_genreg,
  23328         1,
  23329         0,
  23330         0x209,
  23331         0,
  23332         0,
  23333         1,
  23334         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEXr_fields,
  23335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23336         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23337         -1,
  23338         -1,
  23339     },
  23340 #endif /* chips */
  23341 
  23342 #if defined(BCM_88270_A0)
  23343     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88270_A0r */
  23344         soc_block_list[22],
  23345         soc_genreg,
  23346         1,
  23347         0,
  23348         0x209,
  23349         0,
  23350         0,
  23351         1,
  23352         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88270_A0r_fields,
  23353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23354         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  23355         -1,
  23356         -1,
  23357     },
  23358 #endif /* chips */
  23359 
  23360 #if defined(BCM_88375_A0)
  23361     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88375_A0r */
  23362         soc_block_list[22],
  23363         soc_genreg,
  23364         1,
  23365         0,
  23366         0x209,
  23367         0,
  23368         0,
  23369         1,
  23370         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88375_A0r_fields,
  23371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23372         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23373         -1,
  23374         -1,
  23375     },
  23376 #endif /* chips */
  23377 
  23378 #if defined(BCM_88375_B0)
  23379     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88375_B0r */
  23380         soc_block_list[22],
  23381         soc_genreg,
  23382         1,
  23383         0,
  23384         0x209,
  23385         0,
  23386         0,
  23387         1,
  23388         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88375_B0r_fields,
  23389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23390         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23391         -1,
  23392         -1,
  23393     },
  23394 #endif /* chips */
  23395 
  23396 #if defined(BCM_88470_A0)
  23397     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88470_A0r */
  23398         soc_block_list[22],
  23399         soc_genreg,
  23400         1,
  23401         0,
  23402         0x209,
  23403         0,
  23404         0,
  23405         1,
  23406         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88470_A0r_fields,
  23407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23408         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23409         -1,
  23410         -1,
  23411     },
  23412 #endif /* chips */
  23413 
  23414 #if defined(BCM_88470_B0)
  23415     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88470_B0r */
  23416         soc_block_list[22],
  23417         soc_genreg,
  23418         1,
  23419         0,
  23420         0x209,
  23421         0,
  23422         0,
  23423         1,
  23424         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88470_B0r_fields,
  23425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23426         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23427         -1,
  23428         -1,
  23429     },
  23430 #endif /* chips */
  23431 
  23432 #if defined(BCM_88675_B0)
  23433     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88675_B0r */
  23434         soc_block_list[22],
  23435         soc_genreg,
  23436         1,
  23437         0,
  23438         0x209,
  23439         0,
  23440         0,
  23441         1,
  23442         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88675_B0r_fields,
  23443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23444         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23445         -1,
  23446         -1,
  23447     },
  23448 #endif /* chips */
  23449 
  23450 #if defined(BCM_88680_A0)
  23451     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88680_A0r */
  23452         soc_block_list[22],
  23453         soc_genreg,
  23454         1,
  23455         0,
  23456         0x209,
  23457         0,
  23458         0,
  23459         1,
  23460         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX_BCM88680_A0r_fields,
  23461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23462         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23463         -1,
  23464         -1,
  23465     },
  23466 #endif /* chips */
  23467 
  23468 #if defined(BCM_88650_A0)
  23469     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEYr */
  23470         soc_block_list[22],
  23471         soc_genreg,
  23472         1,
  23473         0,
  23474         0x20a,
  23475         SOC_REG_FLAG_SIGNAL,
  23476         0,
  23477         1,
  23478         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEYr_fields,
  23479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23480         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  23481         -1,
  23482         -1,
  23483     },
  23484 #endif /* chips */
  23485 
  23486 #if defined(BCM_88270_A0)
  23487     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88270_A0r */
  23488         soc_block_list[22],
  23489         soc_genreg,
  23490         1,
  23491         0,
  23492         0x20a,
  23493         0,
  23494         0,
  23495         1,
  23496         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88270_A0r_fields,
  23497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23498         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  23499         -1,
  23500         -1,
  23501     },
  23502 #endif /* chips */
  23503 
  23504 #if defined(BCM_88375_A0)
  23505     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88375_A0r */
  23506         soc_block_list[22],
  23507         soc_genreg,
  23508         1,
  23509         0,
  23510         0x20a,
  23511         0,
  23512         0,
  23513         1,
  23514         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88375_A0r_fields,
  23515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23516         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  23517         -1,
  23518         -1,
  23519     },
  23520 #endif /* chips */
  23521 
  23522 #if defined(BCM_88375_B0)
  23523     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88375_B0r */
  23524         soc_block_list[22],
  23525         soc_genreg,
  23526         1,
  23527         0,
  23528         0x20a,
  23529         0,
  23530         0,
  23531         1,
  23532         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88375_B0r_fields,
  23533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23534         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  23535         -1,
  23536         -1,
  23537     },
  23538 #endif /* chips */
  23539 
  23540 #if defined(BCM_88470_A0)
  23541     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88470_A0r */
  23542         soc_block_list[22],
  23543         soc_genreg,
  23544         1,
  23545         0,
  23546         0x20a,
  23547         0,
  23548         0,
  23549         1,
  23550         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88470_A0r_fields,
  23551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23552         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  23553         -1,
  23554         -1,
  23555     },
  23556 #endif /* chips */
  23557 
  23558 #if defined(BCM_88470_B0)
  23559     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88470_B0r */
  23560         soc_block_list[22],
  23561         soc_genreg,
  23562         1,
  23563         0,
  23564         0x20a,
  23565         0,
  23566         0,
  23567         1,
  23568         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88470_B0r_fields,
  23569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23570         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  23571         -1,
  23572         -1,
  23573     },
  23574 #endif /* chips */
  23575 
  23576 #if defined(BCM_88650_B0)
  23577     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88650_B0r */
  23578         soc_block_list[22],
  23579         soc_genreg,
  23580         1,
  23581         0,
  23582         0x20a,
  23583         SOC_REG_FLAG_SIGNAL,
  23584         0,
  23585         1,
  23586         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88650_B0r_fields,
  23587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23588         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  23589         -1,
  23590         -1,
  23591     },
  23592 #endif /* chips */
  23593 
  23594 #if defined(BCM_88660_A0)
  23595     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88660_A0r */
  23596         soc_block_list[22],
  23597         soc_genreg,
  23598         1,
  23599         0,
  23600         0x20a,
  23601         SOC_REG_FLAG_SIGNAL,
  23602         0,
  23603         1,
  23604         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88660_A0r_fields,
  23605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23606         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  23607         -1,
  23608         -1,
  23609     },
  23610 #endif /* chips */
  23611 
  23612 #if defined(BCM_88675_A0)
  23613     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88675_A0r */
  23614         soc_block_list[22],
  23615         soc_genreg,
  23616         1,
  23617         0,
  23618         0x20a,
  23619         0,
  23620         0,
  23621         1,
  23622         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88675_A0r_fields,
  23623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23624         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  23625         -1,
  23626         -1,
  23627     },
  23628 #endif /* chips */
  23629 
  23630 #if defined(BCM_88675_B0)
  23631     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88675_B0r */
  23632         soc_block_list[22],
  23633         soc_genreg,
  23634         1,
  23635         0,
  23636         0x20a,
  23637         0,
  23638         0,
  23639         1,
  23640         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88675_B0r_fields,
  23641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23642         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  23643         -1,
  23644         -1,
  23645     },
  23646 #endif /* chips */
  23647 
  23648 #if defined(BCM_88680_A0)
  23649     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88680_A0r */
  23650         soc_block_list[22],
  23651         soc_genreg,
  23652         1,
  23653         0,
  23654         0x20a,
  23655         0,
  23656         0,
  23657         1,
  23658         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY_BCM88680_A0r_fields,
  23659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23660         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  23661         -1,
  23662         -1,
  23663     },
  23664 #endif /* chips */
  23665 
  23666 #if defined(BCM_88650_A0)
  23667     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULTr */
  23668         soc_block_list[22],
  23669         soc_genreg,
  23670         1,
  23671         0,
  23672         0x20b,
  23673         SOC_REG_FLAG_RO,
  23674         0,
  23675         4,
  23676         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULTr_fields,
  23677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23678         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  23679         -1,
  23680         -1,
  23681     },
  23682 #endif /* chips */
  23683 
  23684 #if defined(BCM_88270_A0)
  23685     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88270_A0r */
  23686         soc_block_list[22],
  23687         soc_genreg,
  23688         1,
  23689         0,
  23690         0x20b,
  23691         SOC_REG_FLAG_RO |
  23692                           SOC_REG_FLAG_SIGNAL,
  23693         0,
  23694         4,
  23695         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88270_A0r_fields,
  23696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23697         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  23698         -1,
  23699         -1,
  23700     },
  23701 #endif /* chips */
  23702 
  23703 #if defined(BCM_88375_A0)
  23704     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88375_A0r */
  23705         soc_block_list[22],
  23706         soc_genreg,
  23707         1,
  23708         0,
  23709         0x20b,
  23710         SOC_REG_FLAG_RO |
  23711                           SOC_REG_FLAG_SIGNAL,
  23712         0,
  23713         4,
  23714         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88375_A0r_fields,
  23715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23716         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  23717         -1,
  23718         -1,
  23719     },
  23720 #endif /* chips */
  23721 
  23722 #if defined(BCM_88375_B0)
  23723     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88375_B0r */
  23724         soc_block_list[22],
  23725         soc_genreg,
  23726         1,
  23727         0,
  23728         0x20b,
  23729         SOC_REG_FLAG_RO |
  23730                           SOC_REG_FLAG_SIGNAL,
  23731         0,
  23732         4,
  23733         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88375_B0r_fields,
  23734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23735         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  23736         -1,
  23737         -1,
  23738     },
  23739 #endif /* chips */
  23740 
  23741 #if defined(BCM_88470_A0)
  23742     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88470_A0r */
  23743         soc_block_list[22],
  23744         soc_genreg,
  23745         1,
  23746         0,
  23747         0x20b,
  23748         SOC_REG_FLAG_RO |
  23749                           SOC_REG_FLAG_SIGNAL,
  23750         0,
  23751         4,
  23752         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88470_A0r_fields,
  23753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23754         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  23755         -1,
  23756         -1,
  23757     },
  23758 #endif /* chips */
  23759 
  23760 #if defined(BCM_88470_B0)
  23761     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88470_B0r */
  23762         soc_block_list[22],
  23763         soc_genreg,
  23764         1,
  23765         0,
  23766         0x20b,
  23767         SOC_REG_FLAG_RO |
  23768                           SOC_REG_FLAG_SIGNAL,
  23769         0,
  23770         4,
  23771         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88470_B0r_fields,
  23772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23773         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  23774         -1,
  23775         -1,
  23776     },
  23777 #endif /* chips */
  23778 
  23779 #if defined(BCM_88650_B0)
  23780     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88650_B0r */
  23781         soc_block_list[22],
  23782         soc_genreg,
  23783         1,
  23784         0,
  23785         0x20b,
  23786         SOC_REG_FLAG_RO,
  23787         0,
  23788         4,
  23789         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88650_B0r_fields,
  23790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23791         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  23792         -1,
  23793         -1,
  23794     },
  23795 #endif /* chips */
  23796 
  23797 #if defined(BCM_88660_A0)
  23798     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88660_A0r */
  23799         soc_block_list[22],
  23800         soc_genreg,
  23801         1,
  23802         0,
  23803         0x20b,
  23804         SOC_REG_FLAG_RO,
  23805         0,
  23806         4,
  23807         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88660_A0r_fields,
  23808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23809         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  23810         -1,
  23811         -1,
  23812     },
  23813 #endif /* chips */
  23814 
  23815 #if defined(BCM_88675_A0)
  23816     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88675_A0r */
  23817         soc_block_list[22],
  23818         soc_genreg,
  23819         1,
  23820         0,
  23821         0x20b,
  23822         SOC_REG_FLAG_RO |
  23823                           SOC_REG_FLAG_SIGNAL,
  23824         0,
  23825         4,
  23826         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88675_A0r_fields,
  23827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23828         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  23829         -1,
  23830         -1,
  23831     },
  23832 #endif /* chips */
  23833 
  23834 #if defined(BCM_88675_B0)
  23835     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88675_B0r */
  23836         soc_block_list[22],
  23837         soc_genreg,
  23838         1,
  23839         0,
  23840         0x20b,
  23841         SOC_REG_FLAG_RO |
  23842                           SOC_REG_FLAG_SIGNAL,
  23843         0,
  23844         4,
  23845         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88675_B0r_fields,
  23846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23847         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  23848         -1,
  23849         -1,
  23850     },
  23851 #endif /* chips */
  23852 
  23853 #if defined(BCM_88680_A0)
  23854     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88680_A0r */
  23855         soc_block_list[22],
  23856         soc_genreg,
  23857         1,
  23858         0,
  23859         0x20b,
  23860         SOC_REG_FLAG_RO |
  23861                           SOC_REG_FLAG_SIGNAL,
  23862         0,
  23863         4,
  23864         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT_BCM88680_A0r_fields,
  23865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23866         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  23867         -1,
  23868         -1,
  23869     },
  23870 #endif /* chips */
  23871 
  23872 #if defined(BCM_88675_A0)
  23873     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULTr */
  23874         soc_block_list[22],
  23875         soc_genreg,
  23876         1,
  23877         0,
  23878         0x20c,
  23879         SOC_REG_FLAG_RO |
  23880                           SOC_REG_FLAG_SIGNAL,
  23881         0,
  23882         2,
  23883         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULTr_fields,
  23884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23885         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  23886         -1,
  23887         -1,
  23888     },
  23889 #endif /* chips */
  23890 
  23891 #if defined(BCM_88270_A0)
  23892     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88270_A0r */
  23893         soc_block_list[22],
  23894         soc_genreg,
  23895         1,
  23896         0,
  23897         0x20c,
  23898         SOC_REG_FLAG_RO |
  23899                           SOC_REG_FLAG_SIGNAL,
  23900         0,
  23901         2,
  23902         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88270_A0r_fields,
  23903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23904         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  23905         -1,
  23906         -1,
  23907     },
  23908 #endif /* chips */
  23909 
  23910 #if defined(BCM_88375_A0)
  23911     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88375_A0r */
  23912         soc_block_list[22],
  23913         soc_genreg,
  23914         1,
  23915         0,
  23916         0x20c,
  23917         SOC_REG_FLAG_RO |
  23918                           SOC_REG_FLAG_SIGNAL,
  23919         0,
  23920         2,
  23921         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88375_A0r_fields,
  23922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23923         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  23924         -1,
  23925         -1,
  23926     },
  23927 #endif /* chips */
  23928 
  23929 #if defined(BCM_88375_B0)
  23930     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88375_B0r */
  23931         soc_block_list[22],
  23932         soc_genreg,
  23933         1,
  23934         0,
  23935         0x20c,
  23936         SOC_REG_FLAG_RO |
  23937                           SOC_REG_FLAG_SIGNAL,
  23938         0,
  23939         2,
  23940         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88375_B0r_fields,
  23941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23942         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  23943         -1,
  23944         -1,
  23945     },
  23946 #endif /* chips */
  23947 
  23948 #if defined(BCM_88470_A0)
  23949     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88470_A0r */
  23950         soc_block_list[22],
  23951         soc_genreg,
  23952         1,
  23953         0,
  23954         0x20c,
  23955         SOC_REG_FLAG_RO |
  23956                           SOC_REG_FLAG_SIGNAL,
  23957         0,
  23958         2,
  23959         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88470_A0r_fields,
  23960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23961         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  23962         -1,
  23963         -1,
  23964     },
  23965 #endif /* chips */
  23966 
  23967 #if defined(BCM_88470_B0)
  23968     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88470_B0r */
  23969         soc_block_list[22],
  23970         soc_genreg,
  23971         1,
  23972         0,
  23973         0x20c,
  23974         SOC_REG_FLAG_RO |
  23975                           SOC_REG_FLAG_SIGNAL,
  23976         0,
  23977         2,
  23978         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88470_B0r_fields,
  23979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23980         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  23981         -1,
  23982         -1,
  23983     },
  23984 #endif /* chips */
  23985 
  23986 #if defined(BCM_88675_B0)
  23987     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88675_B0r */
  23988         soc_block_list[22],
  23989         soc_genreg,
  23990         1,
  23991         0,
  23992         0x20c,
  23993         SOC_REG_FLAG_RO |
  23994                           SOC_REG_FLAG_SIGNAL,
  23995         0,
  23996         2,
  23997         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88675_B0r_fields,
  23998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23999         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  24000         -1,
  24001         -1,
  24002     },
  24003 #endif /* chips */
  24004 
  24005 #if defined(BCM_88680_A0)
  24006     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88680_A0r */
  24007         soc_block_list[22],
  24008         soc_genreg,
  24009         1,
  24010         0,
  24011         0x20c,
  24012         SOC_REG_FLAG_RO |
  24013                           SOC_REG_FLAG_SIGNAL,
  24014         0,
  24015         2,
  24016         soc_OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT_BCM88680_A0r_fields,
  24017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24018         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  24019         -1,
  24020         -1,
  24021     },
  24022 #endif /* chips */
  24023 
  24024 #if defined(BCM_88675_A0)
  24025     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTERr */
  24026         soc_block_list[22],
  24027         soc_genreg,
  24028         1,
  24029         0,
  24030         0x214,
  24031         SOC_REG_FLAG_RO |
  24032                           SOC_REG_FLAG_SIGNAL,
  24033         0,
  24034         1,
  24035         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTERr_fields,
  24036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24037         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24038         -1,
  24039         -1,
  24040     },
  24041 #endif /* chips */
  24042 
  24043 #if defined(BCM_88270_A0)
  24044     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88270_A0r */
  24045         soc_block_list[22],
  24046         soc_genreg,
  24047         1,
  24048         0,
  24049         0x214,
  24050         SOC_REG_FLAG_RO |
  24051                           SOC_REG_FLAG_SIGNAL,
  24052         0,
  24053         1,
  24054         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88270_A0r_fields,
  24055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24056         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24057         -1,
  24058         -1,
  24059     },
  24060 #endif /* chips */
  24061 
  24062 #if defined(BCM_88375_A0)
  24063     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88375_A0r */
  24064         soc_block_list[22],
  24065         soc_genreg,
  24066         1,
  24067         0,
  24068         0x214,
  24069         SOC_REG_FLAG_RO |
  24070                           SOC_REG_FLAG_SIGNAL,
  24071         0,
  24072         1,
  24073         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88375_A0r_fields,
  24074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24075         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24076         -1,
  24077         -1,
  24078     },
  24079 #endif /* chips */
  24080 
  24081 #if defined(BCM_88375_B0)
  24082     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88375_B0r */
  24083         soc_block_list[22],
  24084         soc_genreg,
  24085         1,
  24086         0,
  24087         0x214,
  24088         SOC_REG_FLAG_RO |
  24089                           SOC_REG_FLAG_SIGNAL,
  24090         0,
  24091         1,
  24092         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88375_B0r_fields,
  24093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24094         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24095         -1,
  24096         -1,
  24097     },
  24098 #endif /* chips */
  24099 
  24100 #if defined(BCM_88470_A0)
  24101     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88470_A0r */
  24102         soc_block_list[22],
  24103         soc_genreg,
  24104         1,
  24105         0,
  24106         0x214,
  24107         SOC_REG_FLAG_RO |
  24108                           SOC_REG_FLAG_SIGNAL,
  24109         0,
  24110         1,
  24111         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88470_A0r_fields,
  24112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24113         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24114         -1,
  24115         -1,
  24116     },
  24117 #endif /* chips */
  24118 
  24119 #if defined(BCM_88470_B0)
  24120     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88470_B0r */
  24121         soc_block_list[22],
  24122         soc_genreg,
  24123         1,
  24124         0,
  24125         0x214,
  24126         SOC_REG_FLAG_RO |
  24127                           SOC_REG_FLAG_SIGNAL,
  24128         0,
  24129         1,
  24130         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88470_B0r_fields,
  24131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24132         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24133         -1,
  24134         -1,
  24135     },
  24136 #endif /* chips */
  24137 
  24138 #if defined(BCM_88675_B0)
  24139     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88675_B0r */
  24140         soc_block_list[22],
  24141         soc_genreg,
  24142         1,
  24143         0,
  24144         0x214,
  24145         SOC_REG_FLAG_RO |
  24146                           SOC_REG_FLAG_SIGNAL,
  24147         0,
  24148         1,
  24149         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88675_B0r_fields,
  24150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24151         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24152         -1,
  24153         -1,
  24154     },
  24155 #endif /* chips */
  24156 
  24157 #if defined(BCM_88680_A0)
  24158     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88680_A0r */
  24159         soc_block_list[22],
  24160         soc_genreg,
  24161         1,
  24162         0,
  24163         0x214,
  24164         SOC_REG_FLAG_RO |
  24165                           SOC_REG_FLAG_SIGNAL,
  24166         0,
  24167         1,
  24168         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER_BCM88680_A0r_fields,
  24169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24170         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24171         -1,
  24172         -1,
  24173     },
  24174 #endif /* chips */
  24175 
  24176 #if defined(BCM_88675_A0)
  24177     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTERr */
  24178         soc_block_list[22],
  24179         soc_genreg,
  24180         1,
  24181         0,
  24182         0x212,
  24183         SOC_REG_FLAG_RO,
  24184         0,
  24185         2,
  24186         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTERr_fields,
  24187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24188         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24189         -1,
  24190         -1,
  24191     },
  24192 #endif /* chips */
  24193 
  24194 #if defined(BCM_88270_A0)
  24195     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88270_A0r */
  24196         soc_block_list[22],
  24197         soc_genreg,
  24198         1,
  24199         0,
  24200         0x212,
  24201         SOC_REG_FLAG_RO,
  24202         0,
  24203         2,
  24204         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88270_A0r_fields,
  24205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24206         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24207         -1,
  24208         -1,
  24209     },
  24210 #endif /* chips */
  24211 
  24212 #if defined(BCM_88375_A0)
  24213     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88375_A0r */
  24214         soc_block_list[22],
  24215         soc_genreg,
  24216         1,
  24217         0,
  24218         0x212,
  24219         SOC_REG_FLAG_RO,
  24220         0,
  24221         2,
  24222         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88375_A0r_fields,
  24223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24224         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24225         -1,
  24226         -1,
  24227     },
  24228 #endif /* chips */
  24229 
  24230 #if defined(BCM_88375_B0)
  24231     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88375_B0r */
  24232         soc_block_list[22],
  24233         soc_genreg,
  24234         1,
  24235         0,
  24236         0x212,
  24237         SOC_REG_FLAG_RO,
  24238         0,
  24239         2,
  24240         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88375_B0r_fields,
  24241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24242         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24243         -1,
  24244         -1,
  24245     },
  24246 #endif /* chips */
  24247 
  24248 #if defined(BCM_88470_A0)
  24249     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88470_A0r */
  24250         soc_block_list[22],
  24251         soc_genreg,
  24252         1,
  24253         0,
  24254         0x212,
  24255         SOC_REG_FLAG_RO,
  24256         0,
  24257         2,
  24258         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88470_A0r_fields,
  24259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24260         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24261         -1,
  24262         -1,
  24263     },
  24264 #endif /* chips */
  24265 
  24266 #if defined(BCM_88470_B0)
  24267     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88470_B0r */
  24268         soc_block_list[22],
  24269         soc_genreg,
  24270         1,
  24271         0,
  24272         0x212,
  24273         SOC_REG_FLAG_RO,
  24274         0,
  24275         2,
  24276         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88470_B0r_fields,
  24277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24278         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24279         -1,
  24280         -1,
  24281     },
  24282 #endif /* chips */
  24283 
  24284 #if defined(BCM_88675_B0)
  24285     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88675_B0r */
  24286         soc_block_list[22],
  24287         soc_genreg,
  24288         1,
  24289         0,
  24290         0x212,
  24291         SOC_REG_FLAG_RO,
  24292         0,
  24293         2,
  24294         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88675_B0r_fields,
  24295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24296         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24297         -1,
  24298         -1,
  24299     },
  24300 #endif /* chips */
  24301 
  24302 #if defined(BCM_88680_A0)
  24303     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88680_A0r */
  24304         soc_block_list[22],
  24305         soc_genreg,
  24306         1,
  24307         0,
  24308         0x212,
  24309         SOC_REG_FLAG_RO,
  24310         0,
  24311         2,
  24312         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER_BCM88680_A0r_fields,
  24313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24314         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24315         -1,
  24316         -1,
  24317     },
  24318 #endif /* chips */
  24319 
  24320 #if defined(BCM_88675_A0)
  24321     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTERr */
  24322         soc_block_list[22],
  24323         soc_genreg,
  24324         1,
  24325         0,
  24326         0x210,
  24327         SOC_REG_FLAG_RO,
  24328         0,
  24329         2,
  24330         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTERr_fields,
  24331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24332         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24333         -1,
  24334         -1,
  24335     },
  24336 #endif /* chips */
  24337 
  24338 #if defined(BCM_88270_A0)
  24339     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88270_A0r */
  24340         soc_block_list[22],
  24341         soc_genreg,
  24342         1,
  24343         0,
  24344         0x210,
  24345         SOC_REG_FLAG_RO,
  24346         0,
  24347         2,
  24348         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88270_A0r_fields,
  24349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24350         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24351         -1,
  24352         -1,
  24353     },
  24354 #endif /* chips */
  24355 
  24356 #if defined(BCM_88375_A0)
  24357     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88375_A0r */
  24358         soc_block_list[22],
  24359         soc_genreg,
  24360         1,
  24361         0,
  24362         0x210,
  24363         SOC_REG_FLAG_RO,
  24364         0,
  24365         2,
  24366         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88375_A0r_fields,
  24367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24368         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24369         -1,
  24370         -1,
  24371     },
  24372 #endif /* chips */
  24373 
  24374 #if defined(BCM_88375_B0)
  24375     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88375_B0r */
  24376         soc_block_list[22],
  24377         soc_genreg,
  24378         1,
  24379         0,
  24380         0x210,
  24381         SOC_REG_FLAG_RO,
  24382         0,
  24383         2,
  24384         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88375_B0r_fields,
  24385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24386         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24387         -1,
  24388         -1,
  24389     },
  24390 #endif /* chips */
  24391 
  24392 #if defined(BCM_88470_A0)
  24393     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88470_A0r */
  24394         soc_block_list[22],
  24395         soc_genreg,
  24396         1,
  24397         0,
  24398         0x210,
  24399         SOC_REG_FLAG_RO,
  24400         0,
  24401         2,
  24402         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88470_A0r_fields,
  24403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24404         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24405         -1,
  24406         -1,
  24407     },
  24408 #endif /* chips */
  24409 
  24410 #if defined(BCM_88470_B0)
  24411     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88470_B0r */
  24412         soc_block_list[22],
  24413         soc_genreg,
  24414         1,
  24415         0,
  24416         0x210,
  24417         SOC_REG_FLAG_RO,
  24418         0,
  24419         2,
  24420         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88470_B0r_fields,
  24421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24422         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24423         -1,
  24424         -1,
  24425     },
  24426 #endif /* chips */
  24427 
  24428 #if defined(BCM_88675_B0)
  24429     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88675_B0r */
  24430         soc_block_list[22],
  24431         soc_genreg,
  24432         1,
  24433         0,
  24434         0x210,
  24435         SOC_REG_FLAG_RO,
  24436         0,
  24437         2,
  24438         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88675_B0r_fields,
  24439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24440         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24441         -1,
  24442         -1,
  24443     },
  24444 #endif /* chips */
  24445 
  24446 #if defined(BCM_88680_A0)
  24447     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88680_A0r */
  24448         soc_block_list[22],
  24449         soc_genreg,
  24450         1,
  24451         0,
  24452         0x210,
  24453         SOC_REG_FLAG_RO,
  24454         0,
  24455         2,
  24456         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88680_A0r_fields,
  24457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24458         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24459         -1,
  24460         -1,
  24461     },
  24462 #endif /* chips */
  24463 
  24464 #if defined(BCM_88675_A0)
  24465     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTERr */
  24466         soc_block_list[22],
  24467         soc_genreg,
  24468         1,
  24469         0,
  24470         0x211,
  24471         SOC_REG_FLAG_RO,
  24472         0,
  24473         2,
  24474         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTERr_fields,
  24475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24476         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24477         -1,
  24478         -1,
  24479     },
  24480 #endif /* chips */
  24481 
  24482 #if defined(BCM_88270_A0)
  24483     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88270_A0r */
  24484         soc_block_list[22],
  24485         soc_genreg,
  24486         1,
  24487         0,
  24488         0x211,
  24489         SOC_REG_FLAG_RO,
  24490         0,
  24491         2,
  24492         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88270_A0r_fields,
  24493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24494         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24495         -1,
  24496         -1,
  24497     },
  24498 #endif /* chips */
  24499 
  24500 #if defined(BCM_88375_A0)
  24501     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88375_A0r */
  24502         soc_block_list[22],
  24503         soc_genreg,
  24504         1,
  24505         0,
  24506         0x211,
  24507         SOC_REG_FLAG_RO,
  24508         0,
  24509         2,
  24510         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88375_A0r_fields,
  24511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24512         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24513         -1,
  24514         -1,
  24515     },
  24516 #endif /* chips */
  24517 
  24518 #if defined(BCM_88375_B0)
  24519     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88375_B0r */
  24520         soc_block_list[22],
  24521         soc_genreg,
  24522         1,
  24523         0,
  24524         0x211,
  24525         SOC_REG_FLAG_RO,
  24526         0,
  24527         2,
  24528         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88375_B0r_fields,
  24529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24530         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24531         -1,
  24532         -1,
  24533     },
  24534 #endif /* chips */
  24535 
  24536 #if defined(BCM_88470_A0)
  24537     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88470_A0r */
  24538         soc_block_list[22],
  24539         soc_genreg,
  24540         1,
  24541         0,
  24542         0x211,
  24543         SOC_REG_FLAG_RO,
  24544         0,
  24545         2,
  24546         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88470_A0r_fields,
  24547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24548         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24549         -1,
  24550         -1,
  24551     },
  24552 #endif /* chips */
  24553 
  24554 #if defined(BCM_88470_B0)
  24555     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88470_B0r */
  24556         soc_block_list[22],
  24557         soc_genreg,
  24558         1,
  24559         0,
  24560         0x211,
  24561         SOC_REG_FLAG_RO,
  24562         0,
  24563         2,
  24564         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88470_B0r_fields,
  24565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24566         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24567         -1,
  24568         -1,
  24569     },
  24570 #endif /* chips */
  24571 
  24572 #if defined(BCM_88675_B0)
  24573     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88675_B0r */
  24574         soc_block_list[22],
  24575         soc_genreg,
  24576         1,
  24577         0,
  24578         0x211,
  24579         SOC_REG_FLAG_RO,
  24580         0,
  24581         2,
  24582         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88675_B0r_fields,
  24583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24584         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24585         -1,
  24586         -1,
  24587     },
  24588 #endif /* chips */
  24589 
  24590 #if defined(BCM_88680_A0)
  24591     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88680_A0r */
  24592         soc_block_list[22],
  24593         soc_genreg,
  24594         1,
  24595         0,
  24596         0x211,
  24597         SOC_REG_FLAG_RO,
  24598         0,
  24599         2,
  24600         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88680_A0r_fields,
  24601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24602         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24603         -1,
  24604         -1,
  24605     },
  24606 #endif /* chips */
  24607 
  24608 #if defined(BCM_88675_A0)
  24609     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTERr */
  24610         soc_block_list[22],
  24611         soc_genreg,
  24612         1,
  24613         0,
  24614         0x20f,
  24615         SOC_REG_FLAG_RO,
  24616         0,
  24617         2,
  24618         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTERr_fields,
  24619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24620         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24621         -1,
  24622         -1,
  24623     },
  24624 #endif /* chips */
  24625 
  24626 #if defined(BCM_88270_A0)
  24627     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88270_A0r */
  24628         soc_block_list[22],
  24629         soc_genreg,
  24630         1,
  24631         0,
  24632         0x20f,
  24633         SOC_REG_FLAG_RO,
  24634         0,
  24635         2,
  24636         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88270_A0r_fields,
  24637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24638         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24639         -1,
  24640         -1,
  24641     },
  24642 #endif /* chips */
  24643 
  24644 #if defined(BCM_88375_A0)
  24645     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88375_A0r */
  24646         soc_block_list[22],
  24647         soc_genreg,
  24648         1,
  24649         0,
  24650         0x20f,
  24651         SOC_REG_FLAG_RO,
  24652         0,
  24653         2,
  24654         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88375_A0r_fields,
  24655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24656         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24657         -1,
  24658         -1,
  24659     },
  24660 #endif /* chips */
  24661 
  24662 #if defined(BCM_88375_B0)
  24663     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88375_B0r */
  24664         soc_block_list[22],
  24665         soc_genreg,
  24666         1,
  24667         0,
  24668         0x20f,
  24669         SOC_REG_FLAG_RO,
  24670         0,
  24671         2,
  24672         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88375_B0r_fields,
  24673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24674         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24675         -1,
  24676         -1,
  24677     },
  24678 #endif /* chips */
  24679 
  24680 #if defined(BCM_88470_A0)
  24681     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88470_A0r */
  24682         soc_block_list[22],
  24683         soc_genreg,
  24684         1,
  24685         0,
  24686         0x20f,
  24687         SOC_REG_FLAG_RO,
  24688         0,
  24689         2,
  24690         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88470_A0r_fields,
  24691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24692         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24693         -1,
  24694         -1,
  24695     },
  24696 #endif /* chips */
  24697 
  24698 #if defined(BCM_88470_B0)
  24699     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88470_B0r */
  24700         soc_block_list[22],
  24701         soc_genreg,
  24702         1,
  24703         0,
  24704         0x20f,
  24705         SOC_REG_FLAG_RO,
  24706         0,
  24707         2,
  24708         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88470_B0r_fields,
  24709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24710         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24711         -1,
  24712         -1,
  24713     },
  24714 #endif /* chips */
  24715 
  24716 #if defined(BCM_88675_B0)
  24717     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88675_B0r */
  24718         soc_block_list[22],
  24719         soc_genreg,
  24720         1,
  24721         0,
  24722         0x20f,
  24723         SOC_REG_FLAG_RO,
  24724         0,
  24725         2,
  24726         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88675_B0r_fields,
  24727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24728         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24729         -1,
  24730         -1,
  24731     },
  24732 #endif /* chips */
  24733 
  24734 #if defined(BCM_88680_A0)
  24735     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88680_A0r */
  24736         soc_block_list[22],
  24737         soc_genreg,
  24738         1,
  24739         0,
  24740         0x20f,
  24741         SOC_REG_FLAG_RO,
  24742         0,
  24743         2,
  24744         soc_OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER_BCM88680_A0r_fields,
  24745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24746         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24747         -1,
  24748         -1,
  24749     },
  24750 #endif /* chips */
  24751 
  24752 #if defined(BCM_88650_A0)
  24753     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTERr */
  24754         soc_block_list[22],
  24755         soc_genreg,
  24756         1,
  24757         0,
  24758         0x202,
  24759         0,
  24760         0,
  24761         4,
  24762         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTERr_fields,
  24763         SOC_RESET_VAL_DEC(0x00001f10, 0x00000000)
  24764         SOC_RESET_MASK_DEC(0x00011f13, 0x00000000)
  24765         -1,
  24766         -1,
  24767     },
  24768 #endif /* chips */
  24769 
  24770 #if defined(BCM_88270_A0)
  24771     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88270_A0r */
  24772         soc_block_list[22],
  24773         soc_genreg,
  24774         1,
  24775         0,
  24776         0x202,
  24777         0,
  24778         0,
  24779         5,
  24780         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88270_A0r_fields,
  24781         SOC_RESET_VAL_DEC(0x000000fc, 0x00000000)
  24782         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  24783         -1,
  24784         -1,
  24785     },
  24786 #endif /* chips */
  24787 
  24788 #if defined(BCM_88375_A0)
  24789     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88375_A0r */
  24790         soc_block_list[22],
  24791         soc_genreg,
  24792         1,
  24793         0,
  24794         0x202,
  24795         0,
  24796         0,
  24797         5,
  24798         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88375_A0r_fields,
  24799         SOC_RESET_VAL_DEC(0x000000fc, 0x00000000)
  24800         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  24801         -1,
  24802         -1,
  24803     },
  24804 #endif /* chips */
  24805 
  24806 #if defined(BCM_88375_B0)
  24807     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88375_B0r */
  24808         soc_block_list[22],
  24809         soc_genreg,
  24810         1,
  24811         0,
  24812         0x202,
  24813         0,
  24814         0,
  24815         5,
  24816         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88375_B0r_fields,
  24817         SOC_RESET_VAL_DEC(0x000000fc, 0x00000000)
  24818         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  24819         -1,
  24820         -1,
  24821     },
  24822 #endif /* chips */
  24823 
  24824 #if defined(BCM_88470_A0)
  24825     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88470_A0r */
  24826         soc_block_list[22],
  24827         soc_genreg,
  24828         1,
  24829         0,
  24830         0x202,
  24831         0,
  24832         0,
  24833         5,
  24834         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88470_A0r_fields,
  24835         SOC_RESET_VAL_DEC(0x000000fc, 0x00000000)
  24836         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  24837         -1,
  24838         -1,
  24839     },
  24840 #endif /* chips */
  24841 
  24842 #if defined(BCM_88470_B0)
  24843     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88470_B0r */
  24844         soc_block_list[22],
  24845         soc_genreg,
  24846         1,
  24847         0,
  24848         0x202,
  24849         0,
  24850         0,
  24851         5,
  24852         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88470_B0r_fields,
  24853         SOC_RESET_VAL_DEC(0x000000fc, 0x00000000)
  24854         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  24855         -1,
  24856         -1,
  24857     },
  24858 #endif /* chips */
  24859 
  24860 #if defined(BCM_88650_B0)
  24861     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88650_B0r */
  24862         soc_block_list[22],
  24863         soc_genreg,
  24864         1,
  24865         0,
  24866         0x202,
  24867         0,
  24868         0,
  24869         4,
  24870         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88650_B0r_fields,
  24871         SOC_RESET_VAL_DEC(0x00001f10, 0x00000000)
  24872         SOC_RESET_MASK_DEC(0x00011f13, 0x00000000)
  24873         -1,
  24874         -1,
  24875     },
  24876 #endif /* chips */
  24877 
  24878 #if defined(BCM_88660_A0)
  24879     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88660_A0r */
  24880         soc_block_list[22],
  24881         soc_genreg,
  24882         1,
  24883         0,
  24884         0x202,
  24885         0,
  24886         0,
  24887         5,
  24888         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88660_A0r_fields,
  24889         SOC_RESET_VAL_DEC(0x00003f00, 0x00000000)
  24890         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  24891         -1,
  24892         -1,
  24893     },
  24894 #endif /* chips */
  24895 
  24896 #if defined(BCM_88675_A0)
  24897     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88675_A0r */
  24898         soc_block_list[22],
  24899         soc_genreg,
  24900         1,
  24901         0,
  24902         0x202,
  24903         0,
  24904         0,
  24905         5,
  24906         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88675_A0r_fields,
  24907         SOC_RESET_VAL_DEC(0x000000fc, 0x00000000)
  24908         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  24909         -1,
  24910         -1,
  24911     },
  24912 #endif /* chips */
  24913 
  24914 #if defined(BCM_88675_B0)
  24915     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88675_B0r */
  24916         soc_block_list[22],
  24917         soc_genreg,
  24918         1,
  24919         0,
  24920         0x202,
  24921         0,
  24922         0,
  24923         5,
  24924         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88675_B0r_fields,
  24925         SOC_RESET_VAL_DEC(0x000000fc, 0x00000000)
  24926         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  24927         -1,
  24928         -1,
  24929     },
  24930 #endif /* chips */
  24931 
  24932 #if defined(BCM_88680_A0)
  24933     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88680_A0r */
  24934         soc_block_list[22],
  24935         soc_genreg,
  24936         1,
  24937         0,
  24938         0x202,
  24939         0,
  24940         0,
  24941         5,
  24942         soc_OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER_BCM88680_A0r_fields,
  24943         SOC_RESET_VAL_DEC(0x000000fc, 0x00000000)
  24944         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  24945         -1,
  24946         -1,
  24947     },
  24948 #endif /* chips */
  24949 
  24950 #if defined(BCM_88675_A0)
  24951     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONEr */
  24952         soc_block_list[22],
  24953         soc_genreg,
  24954         1,
  24955         0,
  24956         0x12,
  24957         0,
  24958         0,
  24959         7,
  24960         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONEr_fields,
  24961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24962         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  24963         -1,
  24964         -1,
  24965     },
  24966 #endif /* chips */
  24967 
  24968 #if defined(BCM_88270_A0)
  24969     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88270_A0r */
  24970         soc_block_list[22],
  24971         soc_genreg,
  24972         1,
  24973         0,
  24974         0x12,
  24975         0,
  24976         0,
  24977         7,
  24978         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88270_A0r_fields,
  24979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24980         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  24981         -1,
  24982         -1,
  24983     },
  24984 #endif /* chips */
  24985 
  24986 #if defined(BCM_88375_A0)
  24987     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88375_A0r */
  24988         soc_block_list[22],
  24989         soc_genreg,
  24990         1,
  24991         0,
  24992         0x12,
  24993         0,
  24994         0,
  24995         7,
  24996         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88375_A0r_fields,
  24997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24998         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  24999         -1,
  25000         -1,
  25001     },
  25002 #endif /* chips */
  25003 
  25004 #if defined(BCM_88375_B0)
  25005     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88375_B0r */
  25006         soc_block_list[22],
  25007         soc_genreg,
  25008         1,
  25009         0,
  25010         0x12,
  25011         0,
  25012         0,
  25013         7,
  25014         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88375_B0r_fields,
  25015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25016         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25017         -1,
  25018         -1,
  25019     },
  25020 #endif /* chips */
  25021 
  25022 #if defined(BCM_88470_A0)
  25023     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88470_A0r */
  25024         soc_block_list[22],
  25025         soc_genreg,
  25026         1,
  25027         0,
  25028         0x12,
  25029         0,
  25030         0,
  25031         7,
  25032         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88470_A0r_fields,
  25033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25034         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25035         -1,
  25036         -1,
  25037     },
  25038 #endif /* chips */
  25039 
  25040 #if defined(BCM_88470_B0)
  25041     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88470_B0r */
  25042         soc_block_list[22],
  25043         soc_genreg,
  25044         1,
  25045         0,
  25046         0x12,
  25047         0,
  25048         0,
  25049         7,
  25050         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88470_B0r_fields,
  25051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25052         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25053         -1,
  25054         -1,
  25055     },
  25056 #endif /* chips */
  25057 
  25058 #if defined(BCM_88675_B0)
  25059     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88675_B0r */
  25060         soc_block_list[22],
  25061         soc_genreg,
  25062         1,
  25063         0,
  25064         0x12,
  25065         0,
  25066         0,
  25067         7,
  25068         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88675_B0r_fields,
  25069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25070         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25071         -1,
  25072         -1,
  25073     },
  25074 #endif /* chips */
  25075 
  25076 #if defined(BCM_88680_A0)
  25077     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88680_A0r */
  25078         soc_block_list[22],
  25079         soc_genreg,
  25080         1,
  25081         0,
  25082         0x12,
  25083         0,
  25084         0,
  25085         7,
  25086         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE_BCM88680_A0r_fields,
  25087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25088         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25089         -1,
  25090         -1,
  25091     },
  25092 #endif /* chips */
  25093 
  25094 #if defined(BCM_88650_A0)
  25095     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONEr */
  25096         soc_block_list[22],
  25097         soc_genreg,
  25098         1,
  25099         0,
  25100         0x2,
  25101         SOC_REG_FLAG_INTERRUPT,
  25102         0,
  25103         7,
  25104         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONEr_fields,
  25105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25106         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25107         -1,
  25108         -1,
  25109     },
  25110 #endif /* chips */
  25111 
  25112 #if defined(BCM_88270_A0)
  25113     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88270_A0r */
  25114         soc_block_list[22],
  25115         soc_genreg,
  25116         1,
  25117         0,
  25118         0x2,
  25119         SOC_REG_FLAG_INTERRUPT |
  25120                           SOC_REG_FLAG_SIGNAL,
  25121         0,
  25122         7,
  25123         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88270_A0r_fields,
  25124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25125         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25126         -1,
  25127         -1,
  25128     },
  25129 #endif /* chips */
  25130 
  25131 #if defined(BCM_88375_A0)
  25132     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88375_A0r */
  25133         soc_block_list[22],
  25134         soc_genreg,
  25135         1,
  25136         0,
  25137         0x2,
  25138         SOC_REG_FLAG_INTERRUPT,
  25139         0,
  25140         7,
  25141         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88375_A0r_fields,
  25142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25143         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25144         -1,
  25145         -1,
  25146     },
  25147 #endif /* chips */
  25148 
  25149 #if defined(BCM_88375_B0)
  25150     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88375_B0r */
  25151         soc_block_list[22],
  25152         soc_genreg,
  25153         1,
  25154         0,
  25155         0x2,
  25156         SOC_REG_FLAG_INTERRUPT,
  25157         0,
  25158         7,
  25159         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88375_B0r_fields,
  25160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25161         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25162         -1,
  25163         -1,
  25164     },
  25165 #endif /* chips */
  25166 
  25167 #if defined(BCM_88470_A0)
  25168     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88470_A0r */
  25169         soc_block_list[22],
  25170         soc_genreg,
  25171         1,
  25172         0,
  25173         0x2,
  25174         SOC_REG_FLAG_INTERRUPT |
  25175                           SOC_REG_FLAG_SIGNAL,
  25176         0,
  25177         7,
  25178         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88470_A0r_fields,
  25179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25180         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25181         -1,
  25182         -1,
  25183     },
  25184 #endif /* chips */
  25185 
  25186 #if defined(BCM_88470_B0)
  25187     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88470_B0r */
  25188         soc_block_list[22],
  25189         soc_genreg,
  25190         1,
  25191         0,
  25192         0x2,
  25193         SOC_REG_FLAG_INTERRUPT |
  25194                           SOC_REG_FLAG_SIGNAL,
  25195         0,
  25196         7,
  25197         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88470_B0r_fields,
  25198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25199         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25200         -1,
  25201         -1,
  25202     },
  25203 #endif /* chips */
  25204 
  25205 #if defined(BCM_88650_B0)
  25206     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88650_B0r */
  25207         soc_block_list[22],
  25208         soc_genreg,
  25209         1,
  25210         0,
  25211         0x2,
  25212         SOC_REG_FLAG_INTERRUPT,
  25213         0,
  25214         7,
  25215         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88650_B0r_fields,
  25216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25217         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25218         -1,
  25219         -1,
  25220     },
  25221 #endif /* chips */
  25222 
  25223 #if defined(BCM_88660_A0)
  25224     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88660_A0r */
  25225         soc_block_list[22],
  25226         soc_genreg,
  25227         1,
  25228         0,
  25229         0x2,
  25230         SOC_REG_FLAG_INTERRUPT,
  25231         0,
  25232         7,
  25233         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88660_A0r_fields,
  25234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25235         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25236         -1,
  25237         -1,
  25238     },
  25239 #endif /* chips */
  25240 
  25241 #if defined(BCM_88675_A0)
  25242     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88675_A0r */
  25243         soc_block_list[22],
  25244         soc_genreg,
  25245         1,
  25246         0,
  25247         0x2,
  25248         SOC_REG_FLAG_INTERRUPT,
  25249         0,
  25250         7,
  25251         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88675_A0r_fields,
  25252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25253         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25254         -1,
  25255         -1,
  25256     },
  25257 #endif /* chips */
  25258 
  25259 #if defined(BCM_88675_B0)
  25260     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88675_B0r */
  25261         soc_block_list[22],
  25262         soc_genreg,
  25263         1,
  25264         0,
  25265         0x2,
  25266         SOC_REG_FLAG_INTERRUPT,
  25267         0,
  25268         7,
  25269         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88675_B0r_fields,
  25270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25271         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25272         -1,
  25273         -1,
  25274     },
  25275 #endif /* chips */
  25276 
  25277 #if defined(BCM_88680_A0)
  25278     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88680_A0r */
  25279         soc_block_list[22],
  25280         soc_genreg,
  25281         1,
  25282         0,
  25283         0x2,
  25284         SOC_REG_FLAG_INTERRUPT,
  25285         0,
  25286         7,
  25287         soc_OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE_BCM88680_A0r_fields,
  25288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25289         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25290         -1,
  25291         -1,
  25292     },
  25293 #endif /* chips */
  25294 
  25295 #if defined(BCM_88675_A0)
  25296     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMITr */
  25297         soc_block_list[22],
  25298         soc_genreg,
  25299         1,
  25300         0,
  25301         0x204,
  25302         0,
  25303         0,
  25304         1,
  25305         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMITr_fields,
  25306         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  25307         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25308         -1,
  25309         -1,
  25310     },
  25311 #endif /* chips */
  25312 
  25313 #if defined(BCM_88270_A0)
  25314     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88270_A0r */
  25315         soc_block_list[22],
  25316         soc_genreg,
  25317         1,
  25318         0,
  25319         0x204,
  25320         0,
  25321         0,
  25322         1,
  25323         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88270_A0r_fields,
  25324         SOC_RESET_VAL_DEC(0x00001200, 0x00000000)
  25325         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  25326         -1,
  25327         -1,
  25328     },
  25329 #endif /* chips */
  25330 
  25331 #if defined(BCM_88375_A0)
  25332     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88375_A0r */
  25333         soc_block_list[22],
  25334         soc_genreg,
  25335         1,
  25336         0,
  25337         0x204,
  25338         0,
  25339         0,
  25340         1,
  25341         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88375_A0r_fields,
  25342         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  25343         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25344         -1,
  25345         -1,
  25346     },
  25347 #endif /* chips */
  25348 
  25349 #if defined(BCM_88375_B0)
  25350     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88375_B0r */
  25351         soc_block_list[22],
  25352         soc_genreg,
  25353         1,
  25354         0,
  25355         0x204,
  25356         0,
  25357         0,
  25358         1,
  25359         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88375_B0r_fields,
  25360         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  25361         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25362         -1,
  25363         -1,
  25364     },
  25365 #endif /* chips */
  25366 
  25367 #if defined(BCM_88470_A0)
  25368     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88470_A0r */
  25369         soc_block_list[22],
  25370         soc_genreg,
  25371         1,
  25372         0,
  25373         0x204,
  25374         0,
  25375         0,
  25376         1,
  25377         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88470_A0r_fields,
  25378         SOC_RESET_VAL_DEC(0x00006000, 0x00000000)
  25379         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25380         -1,
  25381         -1,
  25382     },
  25383 #endif /* chips */
  25384 
  25385 #if defined(BCM_88470_B0)
  25386     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88470_B0r */
  25387         soc_block_list[22],
  25388         soc_genreg,
  25389         1,
  25390         0,
  25391         0x204,
  25392         0,
  25393         0,
  25394         1,
  25395         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88470_B0r_fields,
  25396         SOC_RESET_VAL_DEC(0x00006000, 0x00000000)
  25397         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25398         -1,
  25399         -1,
  25400     },
  25401 #endif /* chips */
  25402 
  25403 #if defined(BCM_88675_B0)
  25404     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88675_B0r */
  25405         soc_block_list[22],
  25406         soc_genreg,
  25407         1,
  25408         0,
  25409         0x204,
  25410         0,
  25411         0,
  25412         1,
  25413         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88675_B0r_fields,
  25414         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  25415         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25416         -1,
  25417         -1,
  25418     },
  25419 #endif /* chips */
  25420 
  25421 #if defined(BCM_88680_A0)
  25422     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88680_A0r */
  25423         soc_block_list[22],
  25424         soc_genreg,
  25425         1,
  25426         0,
  25427         0x204,
  25428         0,
  25429         0,
  25430         1,
  25431         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT_BCM88680_A0r_fields,
  25432         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  25433         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25434         -1,
  25435         -1,
  25436     },
  25437 #endif /* chips */
  25438 
  25439 #if defined(BCM_88675_A0)
  25440     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCEr */
  25441         soc_block_list[22],
  25442         soc_genreg,
  25443         1,
  25444         0,
  25445         0x201,
  25446         0,
  25447         0,
  25448         1,
  25449         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCEr_fields,
  25450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25451         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25452         -1,
  25453         -1,
  25454     },
  25455 #endif /* chips */
  25456 
  25457 #if defined(BCM_88270_A0)
  25458     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88270_A0r */
  25459         soc_block_list[22],
  25460         soc_genreg,
  25461         1,
  25462         0,
  25463         0x201,
  25464         0,
  25465         0,
  25466         1,
  25467         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88270_A0r_fields,
  25468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25469         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25470         -1,
  25471         -1,
  25472     },
  25473 #endif /* chips */
  25474 
  25475 #if defined(BCM_88375_A0)
  25476     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88375_A0r */
  25477         soc_block_list[22],
  25478         soc_genreg,
  25479         1,
  25480         0,
  25481         0x201,
  25482         0,
  25483         0,
  25484         1,
  25485         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88375_A0r_fields,
  25486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25487         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25488         -1,
  25489         -1,
  25490     },
  25491 #endif /* chips */
  25492 
  25493 #if defined(BCM_88375_B0)
  25494     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88375_B0r */
  25495         soc_block_list[22],
  25496         soc_genreg,
  25497         1,
  25498         0,
  25499         0x201,
  25500         0,
  25501         0,
  25502         1,
  25503         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88375_B0r_fields,
  25504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25505         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25506         -1,
  25507         -1,
  25508     },
  25509 #endif /* chips */
  25510 
  25511 #if defined(BCM_88470_A0)
  25512     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88470_A0r */
  25513         soc_block_list[22],
  25514         soc_genreg,
  25515         1,
  25516         0,
  25517         0x201,
  25518         0,
  25519         0,
  25520         1,
  25521         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88470_A0r_fields,
  25522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25523         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25524         -1,
  25525         -1,
  25526     },
  25527 #endif /* chips */
  25528 
  25529 #if defined(BCM_88470_B0)
  25530     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88470_B0r */
  25531         soc_block_list[22],
  25532         soc_genreg,
  25533         1,
  25534         0,
  25535         0x201,
  25536         0,
  25537         0,
  25538         1,
  25539         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88470_B0r_fields,
  25540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25541         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25542         -1,
  25543         -1,
  25544     },
  25545 #endif /* chips */
  25546 
  25547 #if defined(BCM_88675_B0)
  25548     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88675_B0r */
  25549         soc_block_list[22],
  25550         soc_genreg,
  25551         1,
  25552         0,
  25553         0x201,
  25554         0,
  25555         0,
  25556         1,
  25557         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88675_B0r_fields,
  25558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25559         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25560         -1,
  25561         -1,
  25562     },
  25563 #endif /* chips */
  25564 
  25565 #if defined(BCM_88680_A0)
  25566     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88680_A0r */
  25567         soc_block_list[22],
  25568         soc_genreg,
  25569         1,
  25570         0,
  25571         0x201,
  25572         0,
  25573         0,
  25574         1,
  25575         soc_OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE_BCM88680_A0r_fields,
  25576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25577         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25578         -1,
  25579         -1,
  25580     },
  25581 #endif /* chips */
  25582 
  25583 #if defined(BCM_88650_A0)
  25584     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTERr */
  25585         soc_block_list[22],
  25586         soc_genreg,
  25587         1,
  25588         0,
  25589         0x203,
  25590         0,
  25591         0,
  25592         3,
  25593         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTERr_fields,
  25594         SOC_RESET_VAL_DEC(0x00003800, 0x00000000)
  25595         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25596         -1,
  25597         -1,
  25598     },
  25599 #endif /* chips */
  25600 
  25601 #if defined(BCM_88270_A0)
  25602     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88270_A0r */
  25603         soc_block_list[22],
  25604         soc_genreg,
  25605         1,
  25606         0,
  25607         0x203,
  25608         0,
  25609         0,
  25610         3,
  25611         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88270_A0r_fields,
  25612         SOC_RESET_VAL_DEC(0x00003e00, 0x00000000)
  25613         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25614         -1,
  25615         -1,
  25616     },
  25617 #endif /* chips */
  25618 
  25619 #if defined(BCM_88375_A0)
  25620     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88375_A0r */
  25621         soc_block_list[22],
  25622         soc_genreg,
  25623         1,
  25624         0,
  25625         0x203,
  25626         0,
  25627         0,
  25628         3,
  25629         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88375_A0r_fields,
  25630         SOC_RESET_VAL_DEC(0x00003700, 0x00000000)
  25631         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25632         -1,
  25633         -1,
  25634     },
  25635 #endif /* chips */
  25636 
  25637 #if defined(BCM_88375_B0)
  25638     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88375_B0r */
  25639         soc_block_list[22],
  25640         soc_genreg,
  25641         1,
  25642         0,
  25643         0x203,
  25644         0,
  25645         0,
  25646         3,
  25647         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88375_B0r_fields,
  25648         SOC_RESET_VAL_DEC(0x00003700, 0x00000000)
  25649         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25650         -1,
  25651         -1,
  25652     },
  25653 #endif /* chips */
  25654 
  25655 #if defined(BCM_88470_A0)
  25656     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88470_A0r */
  25657         soc_block_list[22],
  25658         soc_genreg,
  25659         1,
  25660         0,
  25661         0x203,
  25662         0,
  25663         0,
  25664         3,
  25665         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88470_A0r_fields,
  25666         SOC_RESET_VAL_DEC(0x00003e00, 0x00000000)
  25667         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25668         -1,
  25669         -1,
  25670     },
  25671 #endif /* chips */
  25672 
  25673 #if defined(BCM_88470_B0)
  25674     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88470_B0r */
  25675         soc_block_list[22],
  25676         soc_genreg,
  25677         1,
  25678         0,
  25679         0x203,
  25680         0,
  25681         0,
  25682         3,
  25683         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88470_B0r_fields,
  25684         SOC_RESET_VAL_DEC(0x00003e00, 0x00000000)
  25685         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25686         -1,
  25687         -1,
  25688     },
  25689 #endif /* chips */
  25690 
  25691 #if defined(BCM_88650_B0)
  25692     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88650_B0r */
  25693         soc_block_list[22],
  25694         soc_genreg,
  25695         1,
  25696         0,
  25697         0x203,
  25698         0,
  25699         0,
  25700         3,
  25701         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88650_B0r_fields,
  25702         SOC_RESET_VAL_DEC(0x00003800, 0x00000000)
  25703         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25704         -1,
  25705         -1,
  25706     },
  25707 #endif /* chips */
  25708 
  25709 #if defined(BCM_88660_A0)
  25710     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88660_A0r */
  25711         soc_block_list[22],
  25712         soc_genreg,
  25713         1,
  25714         0,
  25715         0x203,
  25716         0,
  25717         0,
  25718         3,
  25719         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88660_A0r_fields,
  25720         SOC_RESET_VAL_DEC(0x00003800, 0x00000000)
  25721         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25722         -1,
  25723         -1,
  25724     },
  25725 #endif /* chips */
  25726 
  25727 #if defined(BCM_88675_A0)
  25728     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88675_A0r */
  25729         soc_block_list[22],
  25730         soc_genreg,
  25731         1,
  25732         0,
  25733         0x203,
  25734         0,
  25735         0,
  25736         3,
  25737         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88675_A0r_fields,
  25738         SOC_RESET_VAL_DEC(0x00003700, 0x00000000)
  25739         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25740         -1,
  25741         -1,
  25742     },
  25743 #endif /* chips */
  25744 
  25745 #if defined(BCM_88675_B0)
  25746     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88675_B0r */
  25747         soc_block_list[22],
  25748         soc_genreg,
  25749         1,
  25750         0,
  25751         0x203,
  25752         0,
  25753         0,
  25754         3,
  25755         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88675_B0r_fields,
  25756         SOC_RESET_VAL_DEC(0x00003700, 0x00000000)
  25757         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25758         -1,
  25759         -1,
  25760     },
  25761 #endif /* chips */
  25762 
  25763 #if defined(BCM_88680_A0)
  25764     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88680_A0r */
  25765         soc_block_list[22],
  25766         soc_genreg,
  25767         1,
  25768         0,
  25769         0x203,
  25770         0,
  25771         0,
  25772         3,
  25773         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88680_A0r_fields,
  25774         SOC_RESET_VAL_DEC(0x00003700, 0x00000000)
  25775         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  25776         -1,
  25777         -1,
  25778     },
  25779 #endif /* chips */
  25780 
  25781 #if defined(BCM_88650_A0)
  25782     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILUREr */
  25783         soc_block_list[22],
  25784         soc_genreg,
  25785         1,
  25786         0,
  25787         0x205,
  25788         SOC_REG_FLAG_64_BITS |
  25789                           SOC_REG_FLAG_RO,
  25790         0,
  25791         3,
  25792         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILUREr_fields,
  25793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25794         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  25795         -1,
  25796         -1,
  25797     },
  25798 #endif /* chips */
  25799 
  25800 #if defined(BCM_88270_A0)
  25801     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88270_A0r */
  25802         soc_block_list[22],
  25803         soc_genreg,
  25804         1,
  25805         0,
  25806         0x205,
  25807         SOC_REG_FLAG_64_BITS |
  25808                           SOC_REG_FLAG_RO |
  25809                           SOC_REG_FLAG_SIGNAL,
  25810         0,
  25811         3,
  25812         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88270_A0r_fields,
  25813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25814         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  25815         -1,
  25816         -1,
  25817     },
  25818 #endif /* chips */
  25819 
  25820 #if defined(BCM_88375_A0)
  25821     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88375_A0r */
  25822         soc_block_list[22],
  25823         soc_genreg,
  25824         1,
  25825         0,
  25826         0x205,
  25827         SOC_REG_FLAG_64_BITS |
  25828                           SOC_REG_FLAG_RO |
  25829                           SOC_REG_FLAG_SIGNAL,
  25830         0,
  25831         3,
  25832         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88375_A0r_fields,
  25833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25834         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  25835         -1,
  25836         -1,
  25837     },
  25838 #endif /* chips */
  25839 
  25840 #if defined(BCM_88375_B0)
  25841     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88375_B0r */
  25842         soc_block_list[22],
  25843         soc_genreg,
  25844         1,
  25845         0,
  25846         0x205,
  25847         SOC_REG_FLAG_64_BITS |
  25848                           SOC_REG_FLAG_RO |
  25849                           SOC_REG_FLAG_SIGNAL,
  25850         0,
  25851         3,
  25852         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88375_B0r_fields,
  25853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25854         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  25855         -1,
  25856         -1,
  25857     },
  25858 #endif /* chips */
  25859 
  25860 #if defined(BCM_88470_A0)
  25861     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88470_A0r */
  25862         soc_block_list[22],
  25863         soc_genreg,
  25864         1,
  25865         0,
  25866         0x205,
  25867         SOC_REG_FLAG_64_BITS |
  25868                           SOC_REG_FLAG_RO |
  25869                           SOC_REG_FLAG_SIGNAL,
  25870         0,
  25871         3,
  25872         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88470_A0r_fields,
  25873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25874         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  25875         -1,
  25876         -1,
  25877     },
  25878 #endif /* chips */
  25879 
  25880 #if defined(BCM_88470_B0)
  25881     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88470_B0r */
  25882         soc_block_list[22],
  25883         soc_genreg,
  25884         1,
  25885         0,
  25886         0x205,
  25887         SOC_REG_FLAG_64_BITS |
  25888                           SOC_REG_FLAG_RO |
  25889                           SOC_REG_FLAG_SIGNAL,
  25890         0,
  25891         3,
  25892         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88470_B0r_fields,
  25893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25894         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  25895         -1,
  25896         -1,
  25897     },
  25898 #endif /* chips */
  25899 
  25900 #if defined(BCM_88650_B0)
  25901     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88650_B0r */
  25902         soc_block_list[22],
  25903         soc_genreg,
  25904         1,
  25905         0,
  25906         0x205,
  25907         SOC_REG_FLAG_64_BITS |
  25908                           SOC_REG_FLAG_RO,
  25909         0,
  25910         3,
  25911         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88650_B0r_fields,
  25912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25913         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  25914         -1,
  25915         -1,
  25916     },
  25917 #endif /* chips */
  25918 
  25919 #if defined(BCM_88660_A0)
  25920     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88660_A0r */
  25921         soc_block_list[22],
  25922         soc_genreg,
  25923         1,
  25924         0,
  25925         0x205,
  25926         SOC_REG_FLAG_64_BITS |
  25927                           SOC_REG_FLAG_RO,
  25928         0,
  25929         3,
  25930         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88660_A0r_fields,
  25931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25932         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  25933         -1,
  25934         -1,
  25935     },
  25936 #endif /* chips */
  25937 
  25938 #if defined(BCM_88675_A0)
  25939     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88675_A0r */
  25940         soc_block_list[22],
  25941         soc_genreg,
  25942         1,
  25943         0,
  25944         0x205,
  25945         SOC_REG_FLAG_64_BITS |
  25946                           SOC_REG_FLAG_RO |
  25947                           SOC_REG_FLAG_SIGNAL,
  25948         0,
  25949         3,
  25950         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88675_A0r_fields,
  25951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25952         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  25953         -1,
  25954         -1,
  25955     },
  25956 #endif /* chips */
  25957 
  25958 #if defined(BCM_88675_B0)
  25959     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88675_B0r */
  25960         soc_block_list[22],
  25961         soc_genreg,
  25962         1,
  25963         0,
  25964         0x205,
  25965         SOC_REG_FLAG_64_BITS |
  25966                           SOC_REG_FLAG_RO |
  25967                           SOC_REG_FLAG_SIGNAL,
  25968         0,
  25969         3,
  25970         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88675_B0r_fields,
  25971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25972         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  25973         -1,
  25974         -1,
  25975     },
  25976 #endif /* chips */
  25977 
  25978 #if defined(BCM_88680_A0)
  25979     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88680_A0r */
  25980         soc_block_list[22],
  25981         soc_genreg,
  25982         1,
  25983         0,
  25984         0x205,
  25985         SOC_REG_FLAG_64_BITS |
  25986                           SOC_REG_FLAG_RO |
  25987                           SOC_REG_FLAG_SIGNAL,
  25988         0,
  25989         3,
  25990         soc_OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE_BCM88680_A0r_fields,
  25991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25992         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  25993         -1,
  25994         -1,
  25995     },
  25996 #endif /* chips */
  25997 
  25998 #if defined(BCM_88675_A0)
  25999     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTERr */
  26000         soc_block_list[22],
  26001         soc_genreg,
  26002         1,
  26003         0,
  26004         0x20e,
  26005         SOC_REG_FLAG_RO,
  26006         0,
  26007         2,
  26008         soc_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTERr_fields,
  26009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26010         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26011         -1,
  26012         -1,
  26013     },
  26014 #endif /* chips */
  26015 
  26016 #if defined(BCM_88270_A0)
  26017     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88270_A0r */
  26018         soc_block_list[22],
  26019         soc_genreg,
  26020         1,
  26021         0,
  26022         0x20e,
  26023         SOC_REG_FLAG_RO,
  26024         0,
  26025         2,
  26026         soc_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88270_A0r_fields,
  26027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26028         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26029         -1,
  26030         -1,
  26031     },
  26032 #endif /* chips */
  26033 
  26034 #if defined(BCM_88375_A0)
  26035     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88375_A0r */
  26036         soc_block_list[22],
  26037         soc_genreg,
  26038         1,
  26039         0,
  26040         0x20e,
  26041         SOC_REG_FLAG_RO,
  26042         0,
  26043         2,
  26044         soc_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88375_A0r_fields,
  26045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26046         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26047         -1,
  26048         -1,
  26049     },
  26050 #endif /* chips */
  26051 
  26052 #if defined(BCM_88375_B0)
  26053     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88375_B0r */
  26054         soc_block_list[22],
  26055         soc_genreg,
  26056         1,
  26057         0,
  26058         0x20e,
  26059         SOC_REG_FLAG_RO,
  26060         0,
  26061         2,
  26062         soc_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88375_B0r_fields,
  26063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26065         -1,
  26066         -1,
  26067     },
  26068 #endif /* chips */
  26069 
  26070 #if defined(BCM_88470_A0)
  26071     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88470_A0r */
  26072         soc_block_list[22],
  26073         soc_genreg,
  26074         1,
  26075         0,
  26076         0x20e,
  26077         SOC_REG_FLAG_RO,
  26078         0,
  26079         2,
  26080         soc_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88470_A0r_fields,
  26081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26082         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26083         -1,
  26084         -1,
  26085     },
  26086 #endif /* chips */
  26087 
  26088 #if defined(BCM_88470_B0)
  26089     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88470_B0r */
  26090         soc_block_list[22],
  26091         soc_genreg,
  26092         1,
  26093         0,
  26094         0x20e,
  26095         SOC_REG_FLAG_RO,
  26096         0,
  26097         2,
  26098         soc_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88470_B0r_fields,
  26099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26100         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26101         -1,
  26102         -1,
  26103     },
  26104 #endif /* chips */
  26105 
  26106 #if defined(BCM_88675_B0)
  26107     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88675_B0r */
  26108         soc_block_list[22],
  26109         soc_genreg,
  26110         1,
  26111         0,
  26112         0x20e,
  26113         SOC_REG_FLAG_RO,
  26114         0,
  26115         2,
  26116         soc_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88675_B0r_fields,
  26117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26118         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26119         -1,
  26120         -1,
  26121     },
  26122 #endif /* chips */
  26123 
  26124 #if defined(BCM_88680_A0)
  26125     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88680_A0r */
  26126         soc_block_list[22],
  26127         soc_genreg,
  26128         1,
  26129         0,
  26130         0x20e,
  26131         SOC_REG_FLAG_RO,
  26132         0,
  26133         2,
  26134         soc_OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER_BCM88680_A0r_fields,
  26135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26137         -1,
  26138         -1,
  26139     },
  26140 #endif /* chips */
  26141 
  26142 #if defined(BCM_88675_A0)
  26143     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTERr */
  26144         soc_block_list[22],
  26145         soc_genreg,
  26146         1,
  26147         0,
  26148         0x200,
  26149         SOC_REG_FLAG_RO,
  26150         0,
  26151         1,
  26152         soc_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTERr_fields,
  26153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26154         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26155         -1,
  26156         -1,
  26157     },
  26158 #endif /* chips */
  26159 
  26160 #if defined(BCM_88270_A0)
  26161     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88270_A0r */
  26162         soc_block_list[22],
  26163         soc_genreg,
  26164         1,
  26165         0,
  26166         0x200,
  26167         SOC_REG_FLAG_RO,
  26168         0,
  26169         1,
  26170         soc_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88270_A0r_fields,
  26171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26172         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26173         -1,
  26174         -1,
  26175     },
  26176 #endif /* chips */
  26177 
  26178 #if defined(BCM_88375_A0)
  26179     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88375_A0r */
  26180         soc_block_list[22],
  26181         soc_genreg,
  26182         1,
  26183         0,
  26184         0x200,
  26185         SOC_REG_FLAG_RO,
  26186         0,
  26187         1,
  26188         soc_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88375_A0r_fields,
  26189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26190         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26191         -1,
  26192         -1,
  26193     },
  26194 #endif /* chips */
  26195 
  26196 #if defined(BCM_88375_B0)
  26197     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88375_B0r */
  26198         soc_block_list[22],
  26199         soc_genreg,
  26200         1,
  26201         0,
  26202         0x200,
  26203         SOC_REG_FLAG_RO,
  26204         0,
  26205         1,
  26206         soc_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88375_B0r_fields,
  26207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26208         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26209         -1,
  26210         -1,
  26211     },
  26212 #endif /* chips */
  26213 
  26214 #if defined(BCM_88470_A0)
  26215     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88470_A0r */
  26216         soc_block_list[22],
  26217         soc_genreg,
  26218         1,
  26219         0,
  26220         0x200,
  26221         SOC_REG_FLAG_RO,
  26222         0,
  26223         1,
  26224         soc_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88470_A0r_fields,
  26225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26226         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26227         -1,
  26228         -1,
  26229     },
  26230 #endif /* chips */
  26231 
  26232 #if defined(BCM_88470_B0)
  26233     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88470_B0r */
  26234         soc_block_list[22],
  26235         soc_genreg,
  26236         1,
  26237         0,
  26238         0x200,
  26239         SOC_REG_FLAG_RO,
  26240         0,
  26241         1,
  26242         soc_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88470_B0r_fields,
  26243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26244         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26245         -1,
  26246         -1,
  26247     },
  26248 #endif /* chips */
  26249 
  26250 #if defined(BCM_88675_B0)
  26251     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88675_B0r */
  26252         soc_block_list[22],
  26253         soc_genreg,
  26254         1,
  26255         0,
  26256         0x200,
  26257         SOC_REG_FLAG_RO,
  26258         0,
  26259         1,
  26260         soc_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88675_B0r_fields,
  26261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26262         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26263         -1,
  26264         -1,
  26265     },
  26266 #endif /* chips */
  26267 
  26268 #if defined(BCM_88680_A0)
  26269     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88680_A0r */
  26270         soc_block_list[22],
  26271         soc_genreg,
  26272         1,
  26273         0,
  26274         0x200,
  26275         SOC_REG_FLAG_RO,
  26276         0,
  26277         1,
  26278         soc_OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER_BCM88680_A0r_fields,
  26279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26280         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26281         -1,
  26282         -1,
  26283     },
  26284 #endif /* chips */
  26285 
  26286 #if defined(BCM_88675_A0)
  26287     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTERr */
  26288         soc_block_list[22],
  26289         soc_genreg,
  26290         1,
  26291         0,
  26292         0x213,
  26293         SOC_REG_FLAG_RO,
  26294         0,
  26295         2,
  26296         soc_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTERr_fields,
  26297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26298         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26299         -1,
  26300         -1,
  26301     },
  26302 #endif /* chips */
  26303 
  26304 #if defined(BCM_88270_A0)
  26305     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88270_A0r */
  26306         soc_block_list[22],
  26307         soc_genreg,
  26308         1,
  26309         0,
  26310         0x213,
  26311         SOC_REG_FLAG_RO,
  26312         0,
  26313         2,
  26314         soc_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88270_A0r_fields,
  26315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26316         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26317         -1,
  26318         -1,
  26319     },
  26320 #endif /* chips */
  26321 
  26322 #if defined(BCM_88375_A0)
  26323     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88375_A0r */
  26324         soc_block_list[22],
  26325         soc_genreg,
  26326         1,
  26327         0,
  26328         0x213,
  26329         SOC_REG_FLAG_RO,
  26330         0,
  26331         2,
  26332         soc_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88375_A0r_fields,
  26333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26334         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26335         -1,
  26336         -1,
  26337     },
  26338 #endif /* chips */
  26339 
  26340 #if defined(BCM_88375_B0)
  26341     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88375_B0r */
  26342         soc_block_list[22],
  26343         soc_genreg,
  26344         1,
  26345         0,
  26346         0x213,
  26347         SOC_REG_FLAG_RO,
  26348         0,
  26349         2,
  26350         soc_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88375_B0r_fields,
  26351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26352         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26353         -1,
  26354         -1,
  26355     },
  26356 #endif /* chips */
  26357 
  26358 #if defined(BCM_88470_A0)
  26359     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88470_A0r */
  26360         soc_block_list[22],
  26361         soc_genreg,
  26362         1,
  26363         0,
  26364         0x213,
  26365         SOC_REG_FLAG_RO,
  26366         0,
  26367         2,
  26368         soc_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88470_A0r_fields,
  26369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26370         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26371         -1,
  26372         -1,
  26373     },
  26374 #endif /* chips */
  26375 
  26376 #if defined(BCM_88470_B0)
  26377     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88470_B0r */
  26378         soc_block_list[22],
  26379         soc_genreg,
  26380         1,
  26381         0,
  26382         0x213,
  26383         SOC_REG_FLAG_RO,
  26384         0,
  26385         2,
  26386         soc_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88470_B0r_fields,
  26387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26388         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26389         -1,
  26390         -1,
  26391     },
  26392 #endif /* chips */
  26393 
  26394 #if defined(BCM_88675_B0)
  26395     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88675_B0r */
  26396         soc_block_list[22],
  26397         soc_genreg,
  26398         1,
  26399         0,
  26400         0x213,
  26401         SOC_REG_FLAG_RO,
  26402         0,
  26403         2,
  26404         soc_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88675_B0r_fields,
  26405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26406         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26407         -1,
  26408         -1,
  26409     },
  26410 #endif /* chips */
  26411 
  26412 #if defined(BCM_88680_A0)
  26413     { /* SOC_REG_INT_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88680_A0r */
  26414         soc_block_list[22],
  26415         soc_genreg,
  26416         1,
  26417         0,
  26418         0x213,
  26419         SOC_REG_FLAG_RO,
  26420         0,
  26421         2,
  26422         soc_OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER_BCM88680_A0r_fields,
  26423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26424         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26425         -1,
  26426         -1,
  26427     },
  26428 #endif /* chips */
  26429 
  26430 #if defined(BCM_88470_A0)
  26431     { /* SOC_REG_INT_OAMP_RESERVED_MIRROR_ADDRr */
  26432         soc_block_list[22],
  26433         soc_genreg,
  26434         1,
  26435         0,
  26436         0x85,
  26437         0,
  26438         0,
  26439         2,
  26440         soc_OAMP_RESERVED_MIRROR_ADDRr_fields,
  26441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26442         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  26443         -1,
  26444         -1,
  26445     },
  26446 #endif /* chips */
  26447 
  26448 #if defined(BCM_88270_A0)
  26449     { /* SOC_REG_INT_OAMP_RESERVED_MIRROR_ADDR_BCM88270_A0r */
  26450         soc_block_list[22],
  26451         soc_genreg,
  26452         1,
  26453         0,
  26454         0x85,
  26455         0,
  26456         0,
  26457         2,
  26458         soc_OAMP_RESERVED_MIRROR_ADDR_BCM88270_A0r_fields,
  26459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26460         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  26461         -1,
  26462         -1,
  26463     },
  26464 #endif /* chips */
  26465 
  26466 #if defined(BCM_88470_B0)
  26467     { /* SOC_REG_INT_OAMP_RESERVED_MIRROR_ADDR_BCM88470_B0r */
  26468         soc_block_list[22],
  26469         soc_genreg,
  26470         1,
  26471         0,
  26472         0x85,
  26473         0,
  26474         0,
  26475         2,
  26476         soc_OAMP_RESERVED_MIRROR_ADDR_BCM88470_B0r_fields,
  26477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26478         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  26479         -1,
  26480         -1,
  26481     },
  26482 #endif /* chips */
  26483 
  26484 #if defined(BCM_88690_A0)
  26485     { /* SOC_REG_INT_OAMP_RESERVED_MIRROR_ADDR_BCM88690_A0r */
  26486         soc_block_list[22],
  26487         soc_genreg,
  26488         1,
  26489         0,
  26490         0x85,
  26491         0,
  26492         0,
  26493         2,
  26494         soc_OAMP_RESERVED_MIRROR_ADDR_BCM88690_A0r_fields,
  26495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26496         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  26497         -1,
  26498         -1,
  26499     },
  26500 #endif /* chips */
  26501 
  26502 #if defined(BCM_88690_B0)
  26503     { /* SOC_REG_INT_OAMP_RESERVED_MIRROR_ADDR_BCM88690_B0r */
  26504         soc_block_list[22],
  26505         soc_genreg,
  26506         1,
  26507         0,
  26508         0x85,
  26509         0,
  26510         0,
  26511         2,
  26512         soc_OAMP_RESERVED_MIRROR_ADDR_BCM88690_B0r_fields,
  26513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26514         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  26515         -1,
  26516         -1,
  26517     },
  26518 #endif /* chips */
  26519 
  26520 #if defined(BCM_88675_A0)
  26521     { /* SOC_REG_INT_OAMP_RESERVED_MTCDr */
  26522         soc_block_list[22],
  26523         soc_genreg,
  26524         1,
  26525         0,
  26526         0xae,
  26527         0,
  26528         0,
  26529         6,
  26530         soc_OAMP_RESERVED_MTCDr_fields,
  26531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26532         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26533         -1,
  26534         -1,
  26535     },
  26536 #endif /* chips */
  26537 
  26538 #if defined(BCM_88270_A0)
  26539     { /* SOC_REG_INT_OAMP_RESERVED_MTCD_BCM88270_A0r */
  26540         soc_block_list[22],
  26541         soc_genreg,
  26542         1,
  26543         0,
  26544         0xae,
  26545         0,
  26546         0,
  26547         6,
  26548         soc_OAMP_RESERVED_MTCD_BCM88270_A0r_fields,
  26549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26550         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26551         -1,
  26552         -1,
  26553     },
  26554 #endif /* chips */
  26555 
  26556 #if defined(BCM_88375_A0)
  26557     { /* SOC_REG_INT_OAMP_RESERVED_MTCD_BCM88375_A0r */
  26558         soc_block_list[22],
  26559         soc_genreg,
  26560         1,
  26561         0,
  26562         0xae,
  26563         0,
  26564         0,
  26565         6,
  26566         soc_OAMP_RESERVED_MTCD_BCM88375_A0r_fields,
  26567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26568         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26569         -1,
  26570         -1,
  26571     },
  26572 #endif /* chips */
  26573 
  26574 #if defined(BCM_88375_B0)
  26575     { /* SOC_REG_INT_OAMP_RESERVED_MTCD_BCM88375_B0r */
  26576         soc_block_list[22],
  26577         soc_genreg,
  26578         1,
  26579         0,
  26580         0xae,
  26581         0,
  26582         0,
  26583         6,
  26584         soc_OAMP_RESERVED_MTCD_BCM88375_B0r_fields,
  26585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26586         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26587         -1,
  26588         -1,
  26589     },
  26590 #endif /* chips */
  26591 
  26592 #if defined(BCM_88470_A0)
  26593     { /* SOC_REG_INT_OAMP_RESERVED_MTCD_BCM88470_A0r */
  26594         soc_block_list[22],
  26595         soc_genreg,
  26596         1,
  26597         0,
  26598         0xae,
  26599         0,
  26600         0,
  26601         6,
  26602         soc_OAMP_RESERVED_MTCD_BCM88470_A0r_fields,
  26603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26604         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26605         -1,
  26606         -1,
  26607     },
  26608 #endif /* chips */
  26609 
  26610 #if defined(BCM_88470_B0)
  26611     { /* SOC_REG_INT_OAMP_RESERVED_MTCD_BCM88470_B0r */
  26612         soc_block_list[22],
  26613         soc_genreg,
  26614         1,
  26615         0,
  26616         0xae,
  26617         0,
  26618         0,
  26619         6,
  26620         soc_OAMP_RESERVED_MTCD_BCM88470_B0r_fields,
  26621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26622         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26623         -1,
  26624         -1,
  26625     },
  26626 #endif /* chips */
  26627 
  26628 #if defined(BCM_88675_B0)
  26629     { /* SOC_REG_INT_OAMP_RESERVED_MTCD_BCM88675_B0r */
  26630         soc_block_list[22],
  26631         soc_genreg,
  26632         1,
  26633         0,
  26634         0xae,
  26635         0,
  26636         0,
  26637         6,
  26638         soc_OAMP_RESERVED_MTCD_BCM88675_B0r_fields,
  26639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26640         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26641         -1,
  26642         -1,
  26643     },
  26644 #endif /* chips */
  26645 
  26646 #if defined(BCM_88680_A0)
  26647     { /* SOC_REG_INT_OAMP_RESERVED_MTCD_BCM88680_A0r */
  26648         soc_block_list[22],
  26649         soc_genreg,
  26650         1,
  26651         0,
  26652         0xae,
  26653         0,
  26654         0,
  26655         6,
  26656         soc_OAMP_RESERVED_MTCD_BCM88680_A0r_fields,
  26657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26658         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26659         -1,
  26660         -1,
  26661     },
  26662 #endif /* chips */
  26663 
  26664 #if defined(BCM_88690_A0)
  26665     { /* SOC_REG_INT_OAMP_RESERVED_MTCD_BCM88690_A0r */
  26666         soc_block_list[22],
  26667         soc_genreg,
  26668         1,
  26669         0,
  26670         0xae,
  26671         0,
  26672         0,
  26673         6,
  26674         soc_OAMP_RESERVED_MTCD_BCM88690_A0r_fields,
  26675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26676         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26677         -1,
  26678         -1,
  26679     },
  26680 #endif /* chips */
  26681 
  26682 #if defined(BCM_88690_B0)
  26683     { /* SOC_REG_INT_OAMP_RESERVED_MTCD_BCM88690_B0r */
  26684         soc_block_list[22],
  26685         soc_genreg,
  26686         1,
  26687         0,
  26688         0xae,
  26689         0,
  26690         0,
  26691         6,
  26692         soc_OAMP_RESERVED_MTCD_BCM88690_B0r_fields,
  26693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26694         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26695         -1,
  26696         -1,
  26697     },
  26698 #endif /* chips */
  26699 
  26700 #if defined(BCM_88675_A0)
  26701     { /* SOC_REG_INT_OAMP_RESERVED_MTCPr */
  26702         soc_block_list[22],
  26703         soc_genreg,
  26704         1,
  26705         0,
  26706         0xad,
  26707         SOC_REG_FLAG_64_BITS,
  26708         0,
  26709         17,
  26710         soc_OAMP_RESERVED_MTCPr_fields,
  26711         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26712         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26713         -1,
  26714         -1,
  26715     },
  26716 #endif /* chips */
  26717 
  26718 #if defined(BCM_88270_A0)
  26719     { /* SOC_REG_INT_OAMP_RESERVED_MTCP_BCM88270_A0r */
  26720         soc_block_list[22],
  26721         soc_genreg,
  26722         1,
  26723         0,
  26724         0xad,
  26725         SOC_REG_FLAG_64_BITS,
  26726         0,
  26727         17,
  26728         soc_OAMP_RESERVED_MTCP_BCM88270_A0r_fields,
  26729         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26730         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26731         -1,
  26732         -1,
  26733     },
  26734 #endif /* chips */
  26735 
  26736 #if defined(BCM_88375_A0)
  26737     { /* SOC_REG_INT_OAMP_RESERVED_MTCP_BCM88375_A0r */
  26738         soc_block_list[22],
  26739         soc_genreg,
  26740         1,
  26741         0,
  26742         0xad,
  26743         SOC_REG_FLAG_64_BITS,
  26744         0,
  26745         17,
  26746         soc_OAMP_RESERVED_MTCP_BCM88375_A0r_fields,
  26747         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26748         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26749         -1,
  26750         -1,
  26751     },
  26752 #endif /* chips */
  26753 
  26754 #if defined(BCM_88375_B0)
  26755     { /* SOC_REG_INT_OAMP_RESERVED_MTCP_BCM88375_B0r */
  26756         soc_block_list[22],
  26757         soc_genreg,
  26758         1,
  26759         0,
  26760         0xad,
  26761         SOC_REG_FLAG_64_BITS,
  26762         0,
  26763         17,
  26764         soc_OAMP_RESERVED_MTCP_BCM88375_B0r_fields,
  26765         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26766         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26767         -1,
  26768         -1,
  26769     },
  26770 #endif /* chips */
  26771 
  26772 #if defined(BCM_88470_A0)
  26773     { /* SOC_REG_INT_OAMP_RESERVED_MTCP_BCM88470_A0r */
  26774         soc_block_list[22],
  26775         soc_genreg,
  26776         1,
  26777         0,
  26778         0xad,
  26779         SOC_REG_FLAG_64_BITS,
  26780         0,
  26781         17,
  26782         soc_OAMP_RESERVED_MTCP_BCM88470_A0r_fields,
  26783         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26784         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26785         -1,
  26786         -1,
  26787     },
  26788 #endif /* chips */
  26789 
  26790 #if defined(BCM_88470_B0)
  26791     { /* SOC_REG_INT_OAMP_RESERVED_MTCP_BCM88470_B0r */
  26792         soc_block_list[22],
  26793         soc_genreg,
  26794         1,
  26795         0,
  26796         0xad,
  26797         SOC_REG_FLAG_64_BITS,
  26798         0,
  26799         17,
  26800         soc_OAMP_RESERVED_MTCP_BCM88470_B0r_fields,
  26801         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26802         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26803         -1,
  26804         -1,
  26805     },
  26806 #endif /* chips */
  26807 
  26808 #if defined(BCM_88675_B0)
  26809     { /* SOC_REG_INT_OAMP_RESERVED_MTCP_BCM88675_B0r */
  26810         soc_block_list[22],
  26811         soc_genreg,
  26812         1,
  26813         0,
  26814         0xad,
  26815         SOC_REG_FLAG_64_BITS,
  26816         0,
  26817         17,
  26818         soc_OAMP_RESERVED_MTCP_BCM88675_B0r_fields,
  26819         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26820         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26821         -1,
  26822         -1,
  26823     },
  26824 #endif /* chips */
  26825 
  26826 #if defined(BCM_88680_A0)
  26827     { /* SOC_REG_INT_OAMP_RESERVED_MTCP_BCM88680_A0r */
  26828         soc_block_list[22],
  26829         soc_genreg,
  26830         1,
  26831         0,
  26832         0xad,
  26833         SOC_REG_FLAG_64_BITS,
  26834         0,
  26835         17,
  26836         soc_OAMP_RESERVED_MTCP_BCM88680_A0r_fields,
  26837         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26838         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26839         -1,
  26840         -1,
  26841     },
  26842 #endif /* chips */
  26843 
  26844 #if defined(BCM_88690_A0)
  26845     { /* SOC_REG_INT_OAMP_RESERVED_MTCP_BCM88690_A0r */
  26846         soc_block_list[22],
  26847         soc_genreg,
  26848         1,
  26849         0,
  26850         0xad,
  26851         SOC_REG_FLAG_64_BITS,
  26852         0,
  26853         17,
  26854         soc_OAMP_RESERVED_MTCP_BCM88690_A0r_fields,
  26855         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26856         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26857         -1,
  26858         -1,
  26859     },
  26860 #endif /* chips */
  26861 
  26862 #if defined(BCM_88690_B0)
  26863     { /* SOC_REG_INT_OAMP_RESERVED_MTCP_BCM88690_B0r */
  26864         soc_block_list[22],
  26865         soc_genreg,
  26866         1,
  26867         0,
  26868         0xad,
  26869         SOC_REG_FLAG_64_BITS,
  26870         0,
  26871         17,
  26872         soc_OAMP_RESERVED_MTCP_BCM88690_B0r_fields,
  26873         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  26874         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  26875         -1,
  26876         -1,
  26877     },
  26878 #endif /* chips */
  26879 
  26880 #if defined(BCM_88470_A0)
  26881     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_0r */
  26882         soc_block_list[22],
  26883         soc_genreg,
  26884         1,
  26885         0,
  26886         0x90,
  26887         0,
  26888         0,
  26889         1,
  26890         soc_OAMP_RESERVED_SPARE_0r_fields,
  26891         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  26892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26893         -1,
  26894         -1,
  26895     },
  26896 #endif /* chips */
  26897 
  26898 #if defined(BCM_88470_A0)
  26899     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_1r */
  26900         soc_block_list[22],
  26901         soc_genreg,
  26902         1,
  26903         0,
  26904         0x91,
  26905         0,
  26906         0,
  26907         1,
  26908         soc_OAMP_RESERVED_SPARE_1r_fields,
  26909         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  26910         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26911         -1,
  26912         -1,
  26913     },
  26914 #endif /* chips */
  26915 
  26916 #if defined(BCM_88470_A0)
  26917     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_2r */
  26918         soc_block_list[22],
  26919         soc_genreg,
  26920         1,
  26921         0,
  26922         0x92,
  26923         0,
  26924         0,
  26925         1,
  26926         soc_OAMP_RESERVED_SPARE_2r_fields,
  26927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26928         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26929         -1,
  26930         -1,
  26931     },
  26932 #endif /* chips */
  26933 
  26934 #if defined(BCM_88675_A0)
  26935     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3r */
  26936         soc_block_list[22],
  26937         soc_genreg,
  26938         1,
  26939         0,
  26940         0x93,
  26941         0,
  26942         0,
  26943         1,
  26944         soc_OAMP_RESERVED_SPARE_3r_fields,
  26945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26946         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26947         -1,
  26948         -1,
  26949     },
  26950 #endif /* chips */
  26951 
  26952 #if defined(BCM_88270_A0)
  26953     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_0_BCM88270_A0r */
  26954         soc_block_list[22],
  26955         soc_genreg,
  26956         1,
  26957         0,
  26958         0x90,
  26959         0,
  26960         0,
  26961         1,
  26962         soc_OAMP_RESERVED_SPARE_0_BCM88270_A0r_fields,
  26963         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  26964         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26965         -1,
  26966         -1,
  26967     },
  26968 #endif /* chips */
  26969 
  26970 #if defined(BCM_88470_B0)
  26971     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_0_BCM88470_B0r */
  26972         soc_block_list[22],
  26973         soc_genreg,
  26974         1,
  26975         0,
  26976         0x90,
  26977         0,
  26978         0,
  26979         1,
  26980         soc_OAMP_RESERVED_SPARE_0_BCM88470_B0r_fields,
  26981         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  26982         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26983         -1,
  26984         -1,
  26985     },
  26986 #endif /* chips */
  26987 
  26988 #if defined(BCM_88690_A0)
  26989     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_0_BCM88690_A0r */
  26990         soc_block_list[22],
  26991         soc_genreg,
  26992         1,
  26993         0,
  26994         0x90,
  26995         0,
  26996         0,
  26997         1,
  26998         soc_OAMP_RESERVED_SPARE_0_BCM88690_A0r_fields,
  26999         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  27000         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27001         -1,
  27002         -1,
  27003     },
  27004 #endif /* chips */
  27005 
  27006 #if defined(BCM_88690_B0)
  27007     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_0_BCM88690_B0r */
  27008         soc_block_list[22],
  27009         soc_genreg,
  27010         1,
  27011         0,
  27012         0x90,
  27013         0,
  27014         0,
  27015         1,
  27016         soc_OAMP_RESERVED_SPARE_0_BCM88690_B0r_fields,
  27017         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  27018         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27019         -1,
  27020         -1,
  27021     },
  27022 #endif /* chips */
  27023 
  27024 #if defined(BCM_88270_A0)
  27025     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_1_BCM88270_A0r */
  27026         soc_block_list[22],
  27027         soc_genreg,
  27028         1,
  27029         0,
  27030         0x91,
  27031         0,
  27032         0,
  27033         1,
  27034         soc_OAMP_RESERVED_SPARE_1_BCM88270_A0r_fields,
  27035         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  27036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27037         -1,
  27038         -1,
  27039     },
  27040 #endif /* chips */
  27041 
  27042 #if defined(BCM_88470_B0)
  27043     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_1_BCM88470_B0r */
  27044         soc_block_list[22],
  27045         soc_genreg,
  27046         1,
  27047         0,
  27048         0x91,
  27049         0,
  27050         0,
  27051         1,
  27052         soc_OAMP_RESERVED_SPARE_1_BCM88470_B0r_fields,
  27053         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  27054         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27055         -1,
  27056         -1,
  27057     },
  27058 #endif /* chips */
  27059 
  27060 #if defined(BCM_88690_A0)
  27061     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_1_BCM88690_A0r */
  27062         soc_block_list[22],
  27063         soc_genreg,
  27064         1,
  27065         0,
  27066         0x91,
  27067         0,
  27068         0,
  27069         1,
  27070         soc_OAMP_RESERVED_SPARE_1_BCM88690_A0r_fields,
  27071         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  27072         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27073         -1,
  27074         -1,
  27075     },
  27076 #endif /* chips */
  27077 
  27078 #if defined(BCM_88690_B0)
  27079     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_1_BCM88690_B0r */
  27080         soc_block_list[22],
  27081         soc_genreg,
  27082         1,
  27083         0,
  27084         0x91,
  27085         0,
  27086         0,
  27087         1,
  27088         soc_OAMP_RESERVED_SPARE_1_BCM88690_B0r_fields,
  27089         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  27090         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27091         -1,
  27092         -1,
  27093     },
  27094 #endif /* chips */
  27095 
  27096 #if defined(BCM_88270_A0)
  27097     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_2_BCM88270_A0r */
  27098         soc_block_list[22],
  27099         soc_genreg,
  27100         1,
  27101         0,
  27102         0x92,
  27103         0,
  27104         0,
  27105         1,
  27106         soc_OAMP_RESERVED_SPARE_2_BCM88270_A0r_fields,
  27107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27108         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27109         -1,
  27110         -1,
  27111     },
  27112 #endif /* chips */
  27113 
  27114 #if defined(BCM_88470_B0)
  27115     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_2_BCM88470_B0r */
  27116         soc_block_list[22],
  27117         soc_genreg,
  27118         1,
  27119         0,
  27120         0x92,
  27121         0,
  27122         0,
  27123         1,
  27124         soc_OAMP_RESERVED_SPARE_2_BCM88470_B0r_fields,
  27125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27126         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27127         -1,
  27128         -1,
  27129     },
  27130 #endif /* chips */
  27131 
  27132 #if defined(BCM_88690_A0)
  27133     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_2_BCM88690_A0r */
  27134         soc_block_list[22],
  27135         soc_genreg,
  27136         1,
  27137         0,
  27138         0x92,
  27139         0,
  27140         0,
  27141         1,
  27142         soc_OAMP_RESERVED_SPARE_2_BCM88690_A0r_fields,
  27143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27144         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27145         -1,
  27146         -1,
  27147     },
  27148 #endif /* chips */
  27149 
  27150 #if defined(BCM_88690_B0)
  27151     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_2_BCM88690_B0r */
  27152         soc_block_list[22],
  27153         soc_genreg,
  27154         1,
  27155         0,
  27156         0x92,
  27157         0,
  27158         0,
  27159         1,
  27160         soc_OAMP_RESERVED_SPARE_2_BCM88690_B0r_fields,
  27161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27162         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27163         -1,
  27164         -1,
  27165     },
  27166 #endif /* chips */
  27167 
  27168 #if defined(BCM_88270_A0)
  27169     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3_BCM88270_A0r */
  27170         soc_block_list[22],
  27171         soc_genreg,
  27172         1,
  27173         0,
  27174         0x93,
  27175         0,
  27176         0,
  27177         1,
  27178         soc_OAMP_RESERVED_SPARE_3_BCM88270_A0r_fields,
  27179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27180         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27181         -1,
  27182         -1,
  27183     },
  27184 #endif /* chips */
  27185 
  27186 #if defined(BCM_88375_A0)
  27187     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3_BCM88375_A0r */
  27188         soc_block_list[22],
  27189         soc_genreg,
  27190         1,
  27191         0,
  27192         0x93,
  27193         0,
  27194         0,
  27195         1,
  27196         soc_OAMP_RESERVED_SPARE_3_BCM88375_A0r_fields,
  27197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27198         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27199         -1,
  27200         -1,
  27201     },
  27202 #endif /* chips */
  27203 
  27204 #if defined(BCM_88375_B0)
  27205     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3_BCM88375_B0r */
  27206         soc_block_list[22],
  27207         soc_genreg,
  27208         1,
  27209         0,
  27210         0x93,
  27211         0,
  27212         0,
  27213         1,
  27214         soc_OAMP_RESERVED_SPARE_3_BCM88375_B0r_fields,
  27215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27216         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27217         -1,
  27218         -1,
  27219     },
  27220 #endif /* chips */
  27221 
  27222 #if defined(BCM_88470_A0)
  27223     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3_BCM88470_A0r */
  27224         soc_block_list[22],
  27225         soc_genreg,
  27226         1,
  27227         0,
  27228         0x93,
  27229         0,
  27230         0,
  27231         1,
  27232         soc_OAMP_RESERVED_SPARE_3_BCM88470_A0r_fields,
  27233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27234         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27235         -1,
  27236         -1,
  27237     },
  27238 #endif /* chips */
  27239 
  27240 #if defined(BCM_88470_B0)
  27241     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3_BCM88470_B0r */
  27242         soc_block_list[22],
  27243         soc_genreg,
  27244         1,
  27245         0,
  27246         0x93,
  27247         0,
  27248         0,
  27249         1,
  27250         soc_OAMP_RESERVED_SPARE_3_BCM88470_B0r_fields,
  27251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27253         -1,
  27254         -1,
  27255     },
  27256 #endif /* chips */
  27257 
  27258 #if defined(BCM_88675_B0)
  27259     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3_BCM88675_B0r */
  27260         soc_block_list[22],
  27261         soc_genreg,
  27262         1,
  27263         0,
  27264         0x93,
  27265         0,
  27266         0,
  27267         1,
  27268         soc_OAMP_RESERVED_SPARE_3_BCM88675_B0r_fields,
  27269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27270         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27271         -1,
  27272         -1,
  27273     },
  27274 #endif /* chips */
  27275 
  27276 #if defined(BCM_88680_A0)
  27277     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3_BCM88680_A0r */
  27278         soc_block_list[22],
  27279         soc_genreg,
  27280         1,
  27281         0,
  27282         0x93,
  27283         0,
  27284         0,
  27285         1,
  27286         soc_OAMP_RESERVED_SPARE_3_BCM88680_A0r_fields,
  27287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27288         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27289         -1,
  27290         -1,
  27291     },
  27292 #endif /* chips */
  27293 
  27294 #if defined(BCM_88690_A0)
  27295     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3_BCM88690_A0r */
  27296         soc_block_list[22],
  27297         soc_genreg,
  27298         1,
  27299         0,
  27300         0x93,
  27301         0,
  27302         0,
  27303         1,
  27304         soc_OAMP_RESERVED_SPARE_3_BCM88690_A0r_fields,
  27305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27306         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27307         -1,
  27308         -1,
  27309     },
  27310 #endif /* chips */
  27311 
  27312 #if defined(BCM_88690_B0)
  27313     { /* SOC_REG_INT_OAMP_RESERVED_SPARE_3_BCM88690_B0r */
  27314         soc_block_list[22],
  27315         soc_genreg,
  27316         1,
  27317         0,
  27318         0x93,
  27319         0,
  27320         0,
  27321         1,
  27322         soc_OAMP_RESERVED_SPARE_3_BCM88690_B0r_fields,
  27323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27324         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27325         -1,
  27326         -1,
  27327     },
  27328 #endif /* chips */
  27329 
  27330 #if defined(BCM_88660_A0)
  27331     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADERr */
  27332         soc_block_list[22],
  27333         soc_genreg,
  27334         1,
  27335         0,
  27336         0x44a,
  27337         SOC_REG_FLAG_ABOVE_64_BITS |
  27338                           SOC_REG_FLAG_SIGNAL,
  27339         0,
  27340         6,
  27341         soc_OAMP_RFC_6374_DM_PDU_HEADERr_fields,
  27342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27343         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27344         -1,
  27345         -1,
  27346     },
  27347 #endif /* chips */
  27348 
  27349 #if defined(BCM_88270_A0)
  27350     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88270_A0r */
  27351         soc_block_list[22],
  27352         soc_genreg,
  27353         1,
  27354         0,
  27355         0x451,
  27356         SOC_REG_FLAG_ABOVE_64_BITS,
  27357         0,
  27358         4,
  27359         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88270_A0r_fields,
  27360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27361         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27362         -1,
  27363         -1,
  27364     },
  27365 #endif /* chips */
  27366 
  27367 #if defined(BCM_88375_A0)
  27368     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88375_A0r */
  27369         soc_block_list[22],
  27370         soc_genreg,
  27371         1,
  27372         0,
  27373         0x44f,
  27374         SOC_REG_FLAG_ABOVE_64_BITS,
  27375         0,
  27376         6,
  27377         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88375_A0r_fields,
  27378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27379         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27380         -1,
  27381         -1,
  27382     },
  27383 #endif /* chips */
  27384 
  27385 #if defined(BCM_88375_B0)
  27386     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88375_B0r */
  27387         soc_block_list[22],
  27388         soc_genreg,
  27389         1,
  27390         0,
  27391         0x44f,
  27392         SOC_REG_FLAG_ABOVE_64_BITS,
  27393         0,
  27394         6,
  27395         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88375_B0r_fields,
  27396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27397         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27398         -1,
  27399         -1,
  27400     },
  27401 #endif /* chips */
  27402 
  27403 #if defined(BCM_88470_A0)
  27404     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88470_A0r */
  27405         soc_block_list[22],
  27406         soc_genreg,
  27407         1,
  27408         0,
  27409         0x451,
  27410         SOC_REG_FLAG_ABOVE_64_BITS,
  27411         0,
  27412         4,
  27413         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88470_A0r_fields,
  27414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27415         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27416         -1,
  27417         -1,
  27418     },
  27419 #endif /* chips */
  27420 
  27421 #if defined(BCM_88470_B0)
  27422     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88470_B0r */
  27423         soc_block_list[22],
  27424         soc_genreg,
  27425         1,
  27426         0,
  27427         0x451,
  27428         SOC_REG_FLAG_ABOVE_64_BITS,
  27429         0,
  27430         4,
  27431         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88470_B0r_fields,
  27432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27433         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27434         -1,
  27435         -1,
  27436     },
  27437 #endif /* chips */
  27438 
  27439 #if defined(BCM_88675_A0)
  27440     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88675_A0r */
  27441         soc_block_list[22],
  27442         soc_genreg,
  27443         1,
  27444         0,
  27445         0x44f,
  27446         SOC_REG_FLAG_ABOVE_64_BITS,
  27447         0,
  27448         6,
  27449         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88675_A0r_fields,
  27450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27451         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27452         -1,
  27453         -1,
  27454     },
  27455 #endif /* chips */
  27456 
  27457 #if defined(BCM_88675_B0)
  27458     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88675_B0r */
  27459         soc_block_list[22],
  27460         soc_genreg,
  27461         1,
  27462         0,
  27463         0x44f,
  27464         SOC_REG_FLAG_ABOVE_64_BITS,
  27465         0,
  27466         6,
  27467         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88675_B0r_fields,
  27468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27469         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27470         -1,
  27471         -1,
  27472     },
  27473 #endif /* chips */
  27474 
  27475 #if defined(BCM_88680_A0)
  27476     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88680_A0r */
  27477         soc_block_list[22],
  27478         soc_genreg,
  27479         1,
  27480         0,
  27481         0x44f,
  27482         SOC_REG_FLAG_ABOVE_64_BITS,
  27483         0,
  27484         6,
  27485         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88680_A0r_fields,
  27486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27488         -1,
  27489         -1,
  27490     },
  27491 #endif /* chips */
  27492 
  27493 #if defined(BCM_88690_A0)
  27494     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88690_A0r */
  27495         soc_block_list[22],
  27496         soc_genreg,
  27497         1,
  27498         0,
  27499         0x542,
  27500         SOC_REG_FLAG_ABOVE_64_BITS,
  27501         0,
  27502         4,
  27503         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88690_A0r_fields,
  27504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27505         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27506         -1,
  27507         -1,
  27508     },
  27509 #endif /* chips */
  27510 
  27511 #if defined(BCM_88690_B0)
  27512     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PDU_HEADER_BCM88690_B0r */
  27513         soc_block_list[22],
  27514         soc_genreg,
  27515         1,
  27516         0,
  27517         0x542,
  27518         SOC_REG_FLAG_ABOVE_64_BITS,
  27519         0,
  27520         4,
  27521         soc_OAMP_RFC_6374_DM_PDU_HEADER_BCM88690_B0r_fields,
  27522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27524         -1,
  27525         -1,
  27526     },
  27527 #endif /* chips */
  27528 
  27529 #if defined(BCM_88675_A0)
  27530     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CWr */
  27531         soc_block_list[22],
  27532         soc_genreg,
  27533         1,
  27534         0,
  27535         0x433,
  27536         0,
  27537         0,
  27538         1,
  27539         soc_OAMP_RFC_6374_DM_PWE_CWr_fields,
  27540         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27542         -1,
  27543         -1,
  27544     },
  27545 #endif /* chips */
  27546 
  27547 #if defined(BCM_88270_A0)
  27548     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CW_BCM88270_A0r */
  27549         soc_block_list[22],
  27550         soc_genreg,
  27551         1,
  27552         0,
  27553         0x435,
  27554         0,
  27555         0,
  27556         1,
  27557         soc_OAMP_RFC_6374_DM_PWE_CW_BCM88270_A0r_fields,
  27558         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27559         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27560         -1,
  27561         -1,
  27562     },
  27563 #endif /* chips */
  27564 
  27565 #if defined(BCM_88375_A0)
  27566     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CW_BCM88375_A0r */
  27567         soc_block_list[22],
  27568         soc_genreg,
  27569         1,
  27570         0,
  27571         0x433,
  27572         0,
  27573         0,
  27574         1,
  27575         soc_OAMP_RFC_6374_DM_PWE_CW_BCM88375_A0r_fields,
  27576         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27578         -1,
  27579         -1,
  27580     },
  27581 #endif /* chips */
  27582 
  27583 #if defined(BCM_88375_B0)
  27584     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CW_BCM88375_B0r */
  27585         soc_block_list[22],
  27586         soc_genreg,
  27587         1,
  27588         0,
  27589         0x433,
  27590         0,
  27591         0,
  27592         1,
  27593         soc_OAMP_RFC_6374_DM_PWE_CW_BCM88375_B0r_fields,
  27594         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27596         -1,
  27597         -1,
  27598     },
  27599 #endif /* chips */
  27600 
  27601 #if defined(BCM_88470_A0)
  27602     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CW_BCM88470_A0r */
  27603         soc_block_list[22],
  27604         soc_genreg,
  27605         1,
  27606         0,
  27607         0x435,
  27608         0,
  27609         0,
  27610         1,
  27611         soc_OAMP_RFC_6374_DM_PWE_CW_BCM88470_A0r_fields,
  27612         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27614         -1,
  27615         -1,
  27616     },
  27617 #endif /* chips */
  27618 
  27619 #if defined(BCM_88470_B0)
  27620     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CW_BCM88470_B0r */
  27621         soc_block_list[22],
  27622         soc_genreg,
  27623         1,
  27624         0,
  27625         0x435,
  27626         0,
  27627         0,
  27628         1,
  27629         soc_OAMP_RFC_6374_DM_PWE_CW_BCM88470_B0r_fields,
  27630         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27631         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27632         -1,
  27633         -1,
  27634     },
  27635 #endif /* chips */
  27636 
  27637 #if defined(BCM_88675_B0)
  27638     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CW_BCM88675_B0r */
  27639         soc_block_list[22],
  27640         soc_genreg,
  27641         1,
  27642         0,
  27643         0x433,
  27644         0,
  27645         0,
  27646         1,
  27647         soc_OAMP_RFC_6374_DM_PWE_CW_BCM88675_B0r_fields,
  27648         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27649         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27650         -1,
  27651         -1,
  27652     },
  27653 #endif /* chips */
  27654 
  27655 #if defined(BCM_88680_A0)
  27656     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CW_BCM88680_A0r */
  27657         soc_block_list[22],
  27658         soc_genreg,
  27659         1,
  27660         0,
  27661         0x433,
  27662         0,
  27663         0,
  27664         1,
  27665         soc_OAMP_RFC_6374_DM_PWE_CW_BCM88680_A0r_fields,
  27666         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27667         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27668         -1,
  27669         -1,
  27670     },
  27671 #endif /* chips */
  27672 
  27673 #if defined(BCM_88690_A0)
  27674     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CW_BCM88690_A0r */
  27675         soc_block_list[22],
  27676         soc_genreg,
  27677         1,
  27678         0,
  27679         0x525,
  27680         0,
  27681         0,
  27682         1,
  27683         soc_OAMP_RFC_6374_DM_PWE_CW_BCM88690_A0r_fields,
  27684         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27685         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27686         -1,
  27687         -1,
  27688     },
  27689 #endif /* chips */
  27690 
  27691 #if defined(BCM_88690_B0)
  27692     { /* SOC_REG_INT_OAMP_RFC_6374_DM_PWE_CW_BCM88690_B0r */
  27693         soc_block_list[22],
  27694         soc_genreg,
  27695         1,
  27696         0,
  27697         0x525,
  27698         0,
  27699         0,
  27700         1,
  27701         soc_OAMP_RFC_6374_DM_PWE_CW_BCM88690_B0r_fields,
  27702         SOC_RESET_VAL_DEC(0x1000000c, 0x00000000)
  27703         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27704         -1,
  27705         -1,
  27706     },
  27707 #endif /* chips */
  27708 
  27709 #if defined(BCM_88660_A0)
  27710     { /* SOC_REG_INT_OAMP_RFC_6374_FIX_QUALIFIERr */
  27711         soc_block_list[22],
  27712         soc_genreg,
  27713         1,
  27714         0,
  27715         0x191,
  27716         SOC_REG_FLAG_SIGNAL,
  27717         0,
  27718         2,
  27719         soc_OAMP_RFC_6374_FIX_QUALIFIERr_fields,
  27720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27721         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  27722         -1,
  27723         -1,
  27724     },
  27725 #endif /* chips */
  27726 
  27727 #if defined(BCM_88375_A0)
  27728     { /* SOC_REG_INT_OAMP_RFC_6374_FIX_QUALIFIER_BCM88375_A0r */
  27729         soc_block_list[22],
  27730         soc_genreg,
  27731         1,
  27732         0,
  27733         0x194,
  27734         0,
  27735         0,
  27736         2,
  27737         soc_OAMP_RFC_6374_FIX_QUALIFIER_BCM88375_A0r_fields,
  27738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27739         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  27740         -1,
  27741         -1,
  27742     },
  27743 #endif /* chips */
  27744 
  27745 #if defined(BCM_88375_B0)
  27746     { /* SOC_REG_INT_OAMP_RFC_6374_FIX_QUALIFIER_BCM88375_B0r */
  27747         soc_block_list[22],
  27748         soc_genreg,
  27749         1,
  27750         0,
  27751         0x194,
  27752         0,
  27753         0,
  27754         2,
  27755         soc_OAMP_RFC_6374_FIX_QUALIFIER_BCM88375_B0r_fields,
  27756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27757         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  27758         -1,
  27759         -1,
  27760     },
  27761 #endif /* chips */
  27762 
  27763 #if defined(BCM_88675_A0)
  27764     { /* SOC_REG_INT_OAMP_RFC_6374_FIX_QUALIFIER_BCM88675_A0r */
  27765         soc_block_list[22],
  27766         soc_genreg,
  27767         1,
  27768         0,
  27769         0x194,
  27770         0,
  27771         0,
  27772         2,
  27773         soc_OAMP_RFC_6374_FIX_QUALIFIER_BCM88675_A0r_fields,
  27774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27775         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  27776         -1,
  27777         -1,
  27778     },
  27779 #endif /* chips */
  27780 
  27781 #if defined(BCM_88675_B0)
  27782     { /* SOC_REG_INT_OAMP_RFC_6374_FIX_QUALIFIER_BCM88675_B0r */
  27783         soc_block_list[22],
  27784         soc_genreg,
  27785         1,
  27786         0,
  27787         0x194,
  27788         0,
  27789         0,
  27790         2,
  27791         soc_OAMP_RFC_6374_FIX_QUALIFIER_BCM88675_B0r_fields,
  27792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27793         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  27794         -1,
  27795         -1,
  27796     },
  27797 #endif /* chips */
  27798 
  27799 #if defined(BCM_88680_A0)
  27800     { /* SOC_REG_INT_OAMP_RFC_6374_FIX_QUALIFIER_BCM88680_A0r */
  27801         soc_block_list[22],
  27802         soc_genreg,
  27803         1,
  27804         0,
  27805         0x194,
  27806         0,
  27807         0,
  27808         2,
  27809         soc_OAMP_RFC_6374_FIX_QUALIFIER_BCM88680_A0r_fields,
  27810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27811         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  27812         -1,
  27813         -1,
  27814     },
  27815 #endif /* chips */
  27816 
  27817 #if defined(BCM_88675_A0)
  27818     { /* SOC_REG_INT_OAMP_RFC_6374_IGNOREDr */
  27819         soc_block_list[22],
  27820         soc_genreg,
  27821         1,
  27822         0,
  27823         0x195,
  27824         SOC_REG_FLAG_RO |
  27825                           SOC_REG_FLAG_SIGNAL,
  27826         0,
  27827         3,
  27828         soc_OAMP_RFC_6374_IGNOREDr_fields,
  27829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27830         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27831         -1,
  27832         -1,
  27833     },
  27834 #endif /* chips */
  27835 
  27836 #if defined(BCM_88270_A0)
  27837     { /* SOC_REG_INT_OAMP_RFC_6374_IGNORED_BCM88270_A0r */
  27838         soc_block_list[22],
  27839         soc_genreg,
  27840         1,
  27841         0,
  27842         0x19b,
  27843         SOC_REG_FLAG_RO |
  27844                           SOC_REG_FLAG_SIGNAL,
  27845         0,
  27846         3,
  27847         soc_OAMP_RFC_6374_IGNORED_BCM88270_A0r_fields,
  27848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27849         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27850         -1,
  27851         -1,
  27852     },
  27853 #endif /* chips */
  27854 
  27855 #if defined(BCM_88375_A0)
  27856     { /* SOC_REG_INT_OAMP_RFC_6374_IGNORED_BCM88375_A0r */
  27857         soc_block_list[22],
  27858         soc_genreg,
  27859         1,
  27860         0,
  27861         0x195,
  27862         SOC_REG_FLAG_RO |
  27863                           SOC_REG_FLAG_SIGNAL,
  27864         0,
  27865         3,
  27866         soc_OAMP_RFC_6374_IGNORED_BCM88375_A0r_fields,
  27867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27868         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27869         -1,
  27870         -1,
  27871     },
  27872 #endif /* chips */
  27873 
  27874 #if defined(BCM_88375_B0)
  27875     { /* SOC_REG_INT_OAMP_RFC_6374_IGNORED_BCM88375_B0r */
  27876         soc_block_list[22],
  27877         soc_genreg,
  27878         1,
  27879         0,
  27880         0x195,
  27881         SOC_REG_FLAG_RO |
  27882                           SOC_REG_FLAG_SIGNAL,
  27883         0,
  27884         3,
  27885         soc_OAMP_RFC_6374_IGNORED_BCM88375_B0r_fields,
  27886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27887         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27888         -1,
  27889         -1,
  27890     },
  27891 #endif /* chips */
  27892 
  27893 #if defined(BCM_88470_A0)
  27894     { /* SOC_REG_INT_OAMP_RFC_6374_IGNORED_BCM88470_A0r */
  27895         soc_block_list[22],
  27896         soc_genreg,
  27897         1,
  27898         0,
  27899         0x19b,
  27900         SOC_REG_FLAG_RO |
  27901                           SOC_REG_FLAG_SIGNAL,
  27902         0,
  27903         3,
  27904         soc_OAMP_RFC_6374_IGNORED_BCM88470_A0r_fields,
  27905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27906         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27907         -1,
  27908         -1,
  27909     },
  27910 #endif /* chips */
  27911 
  27912 #if defined(BCM_88470_B0)
  27913     { /* SOC_REG_INT_OAMP_RFC_6374_IGNORED_BCM88470_B0r */
  27914         soc_block_list[22],
  27915         soc_genreg,
  27916         1,
  27917         0,
  27918         0x19b,
  27919         SOC_REG_FLAG_RO |
  27920                           SOC_REG_FLAG_SIGNAL,
  27921         0,
  27922         3,
  27923         soc_OAMP_RFC_6374_IGNORED_BCM88470_B0r_fields,
  27924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27925         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27926         -1,
  27927         -1,
  27928     },
  27929 #endif /* chips */
  27930 
  27931 #if defined(BCM_88675_B0)
  27932     { /* SOC_REG_INT_OAMP_RFC_6374_IGNORED_BCM88675_B0r */
  27933         soc_block_list[22],
  27934         soc_genreg,
  27935         1,
  27936         0,
  27937         0x195,
  27938         SOC_REG_FLAG_RO |
  27939                           SOC_REG_FLAG_SIGNAL,
  27940         0,
  27941         3,
  27942         soc_OAMP_RFC_6374_IGNORED_BCM88675_B0r_fields,
  27943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27944         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27945         -1,
  27946         -1,
  27947     },
  27948 #endif /* chips */
  27949 
  27950 #if defined(BCM_88680_A0)
  27951     { /* SOC_REG_INT_OAMP_RFC_6374_IGNORED_BCM88680_A0r */
  27952         soc_block_list[22],
  27953         soc_genreg,
  27954         1,
  27955         0,
  27956         0x195,
  27957         SOC_REG_FLAG_RO |
  27958                           SOC_REG_FLAG_SIGNAL,
  27959         0,
  27960         3,
  27961         soc_OAMP_RFC_6374_IGNORED_BCM88680_A0r_fields,
  27962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27963         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27964         -1,
  27965         -1,
  27966     },
  27967 #endif /* chips */
  27968 
  27969 #if defined(BCM_88690_A0)
  27970     { /* SOC_REG_INT_OAMP_RFC_6374_IGNORED_BCM88690_A0r */
  27971         soc_block_list[22],
  27972         soc_genreg,
  27973         1,
  27974         0,
  27975         0x198,
  27976         SOC_REG_FLAG_RO |
  27977                           SOC_REG_FLAG_SIGNAL,
  27978         0,
  27979         3,
  27980         soc_OAMP_RFC_6374_IGNORED_BCM88690_A0r_fields,
  27981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27982         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27983         -1,
  27984         -1,
  27985     },
  27986 #endif /* chips */
  27987 
  27988 #if defined(BCM_88690_B0)
  27989     { /* SOC_REG_INT_OAMP_RFC_6374_IGNORED_BCM88690_B0r */
  27990         soc_block_list[22],
  27991         soc_genreg,
  27992         1,
  27993         0,
  27994         0x198,
  27995         SOC_REG_FLAG_RO |
  27996                           SOC_REG_FLAG_SIGNAL,
  27997         0,
  27998         3,
  27999         soc_OAMP_RFC_6374_IGNORED_BCM88690_B0r_fields,
  28000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28001         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28002         -1,
  28003         -1,
  28004     },
  28005 #endif /* chips */
  28006 
  28007 #if defined(BCM_88660_A0)
  28008     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADERr */
  28009         soc_block_list[22],
  28010         soc_genreg,
  28011         1,
  28012         0,
  28013         0x445,
  28014         SOC_REG_FLAG_ABOVE_64_BITS |
  28015                           SOC_REG_FLAG_SIGNAL,
  28016         0,
  28017         6,
  28018         soc_OAMP_RFC_6374_LM_PDU_HEADERr_fields,
  28019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28020         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28021         -1,
  28022         -1,
  28023     },
  28024 #endif /* chips */
  28025 
  28026 #if defined(BCM_88270_A0)
  28027     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88270_A0r */
  28028         soc_block_list[22],
  28029         soc_genreg,
  28030         1,
  28031         0,
  28032         0x44d,
  28033         SOC_REG_FLAG_ABOVE_64_BITS,
  28034         0,
  28035         4,
  28036         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88270_A0r_fields,
  28037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28038         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28039         -1,
  28040         -1,
  28041     },
  28042 #endif /* chips */
  28043 
  28044 #if defined(BCM_88375_A0)
  28045     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88375_A0r */
  28046         soc_block_list[22],
  28047         soc_genreg,
  28048         1,
  28049         0,
  28050         0x44a,
  28051         SOC_REG_FLAG_ABOVE_64_BITS,
  28052         0,
  28053         6,
  28054         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88375_A0r_fields,
  28055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28056         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28057         -1,
  28058         -1,
  28059     },
  28060 #endif /* chips */
  28061 
  28062 #if defined(BCM_88375_B0)
  28063     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88375_B0r */
  28064         soc_block_list[22],
  28065         soc_genreg,
  28066         1,
  28067         0,
  28068         0x44a,
  28069         SOC_REG_FLAG_ABOVE_64_BITS,
  28070         0,
  28071         6,
  28072         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88375_B0r_fields,
  28073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28074         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28075         -1,
  28076         -1,
  28077     },
  28078 #endif /* chips */
  28079 
  28080 #if defined(BCM_88470_A0)
  28081     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88470_A0r */
  28082         soc_block_list[22],
  28083         soc_genreg,
  28084         1,
  28085         0,
  28086         0x44d,
  28087         SOC_REG_FLAG_ABOVE_64_BITS,
  28088         0,
  28089         4,
  28090         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88470_A0r_fields,
  28091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28092         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28093         -1,
  28094         -1,
  28095     },
  28096 #endif /* chips */
  28097 
  28098 #if defined(BCM_88470_B0)
  28099     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88470_B0r */
  28100         soc_block_list[22],
  28101         soc_genreg,
  28102         1,
  28103         0,
  28104         0x44d,
  28105         SOC_REG_FLAG_ABOVE_64_BITS,
  28106         0,
  28107         4,
  28108         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88470_B0r_fields,
  28109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28110         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28111         -1,
  28112         -1,
  28113     },
  28114 #endif /* chips */
  28115 
  28116 #if defined(BCM_88675_A0)
  28117     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88675_A0r */
  28118         soc_block_list[22],
  28119         soc_genreg,
  28120         1,
  28121         0,
  28122         0x44a,
  28123         SOC_REG_FLAG_ABOVE_64_BITS,
  28124         0,
  28125         6,
  28126         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88675_A0r_fields,
  28127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28128         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28129         -1,
  28130         -1,
  28131     },
  28132 #endif /* chips */
  28133 
  28134 #if defined(BCM_88675_B0)
  28135     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88675_B0r */
  28136         soc_block_list[22],
  28137         soc_genreg,
  28138         1,
  28139         0,
  28140         0x44a,
  28141         SOC_REG_FLAG_ABOVE_64_BITS,
  28142         0,
  28143         6,
  28144         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88675_B0r_fields,
  28145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28146         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28147         -1,
  28148         -1,
  28149     },
  28150 #endif /* chips */
  28151 
  28152 #if defined(BCM_88680_A0)
  28153     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88680_A0r */
  28154         soc_block_list[22],
  28155         soc_genreg,
  28156         1,
  28157         0,
  28158         0x44a,
  28159         SOC_REG_FLAG_ABOVE_64_BITS,
  28160         0,
  28161         6,
  28162         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88680_A0r_fields,
  28163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28164         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28165         -1,
  28166         -1,
  28167     },
  28168 #endif /* chips */
  28169 
  28170 #if defined(BCM_88690_A0)
  28171     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88690_A0r */
  28172         soc_block_list[22],
  28173         soc_genreg,
  28174         1,
  28175         0,
  28176         0x53e,
  28177         SOC_REG_FLAG_ABOVE_64_BITS,
  28178         0,
  28179         4,
  28180         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88690_A0r_fields,
  28181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28182         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28183         -1,
  28184         -1,
  28185     },
  28186 #endif /* chips */
  28187 
  28188 #if defined(BCM_88690_B0)
  28189     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PDU_HEADER_BCM88690_B0r */
  28190         soc_block_list[22],
  28191         soc_genreg,
  28192         1,
  28193         0,
  28194         0x53e,
  28195         SOC_REG_FLAG_ABOVE_64_BITS,
  28196         0,
  28197         4,
  28198         soc_OAMP_RFC_6374_LM_PDU_HEADER_BCM88690_B0r_fields,
  28199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28200         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28201         -1,
  28202         -1,
  28203     },
  28204 #endif /* chips */
  28205 
  28206 #if defined(BCM_88675_A0)
  28207     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CWr */
  28208         soc_block_list[22],
  28209         soc_genreg,
  28210         1,
  28211         0,
  28212         0x434,
  28213         0,
  28214         0,
  28215         1,
  28216         soc_OAMP_RFC_6374_LM_PWE_CWr_fields,
  28217         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28219         -1,
  28220         -1,
  28221     },
  28222 #endif /* chips */
  28223 
  28224 #if defined(BCM_88470_A0)
  28225     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_0r */
  28226         soc_block_list[22],
  28227         soc_genreg,
  28228         1,
  28229         0,
  28230         0x436,
  28231         0,
  28232         0,
  28233         1,
  28234         soc_OAMP_RFC_6374_LM_PWE_CW_0r_fields,
  28235         SOC_RESET_VAL_DEC(0x1000000a, 0x00000000)
  28236         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28237         -1,
  28238         -1,
  28239     },
  28240 #endif /* chips */
  28241 
  28242 #if defined(BCM_88470_A0)
  28243     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_1r */
  28244         soc_block_list[22],
  28245         soc_genreg,
  28246         1,
  28247         0,
  28248         0x437,
  28249         0,
  28250         0,
  28251         1,
  28252         soc_OAMP_RFC_6374_LM_PWE_CW_1r_fields,
  28253         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28254         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28255         -1,
  28256         -1,
  28257     },
  28258 #endif /* chips */
  28259 
  28260 #if defined(BCM_88270_A0)
  28261     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_0_BCM88270_A0r */
  28262         soc_block_list[22],
  28263         soc_genreg,
  28264         1,
  28265         0,
  28266         0x436,
  28267         0,
  28268         0,
  28269         1,
  28270         soc_OAMP_RFC_6374_LM_PWE_CW_0_BCM88270_A0r_fields,
  28271         SOC_RESET_VAL_DEC(0x1000000a, 0x00000000)
  28272         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28273         -1,
  28274         -1,
  28275     },
  28276 #endif /* chips */
  28277 
  28278 #if defined(BCM_88470_B0)
  28279     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_0_BCM88470_B0r */
  28280         soc_block_list[22],
  28281         soc_genreg,
  28282         1,
  28283         0,
  28284         0x436,
  28285         0,
  28286         0,
  28287         1,
  28288         soc_OAMP_RFC_6374_LM_PWE_CW_0_BCM88470_B0r_fields,
  28289         SOC_RESET_VAL_DEC(0x1000000a, 0x00000000)
  28290         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28291         -1,
  28292         -1,
  28293     },
  28294 #endif /* chips */
  28295 
  28296 #if defined(BCM_88690_A0)
  28297     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_0_BCM88690_A0r */
  28298         soc_block_list[22],
  28299         soc_genreg,
  28300         1,
  28301         0,
  28302         0x526,
  28303         0,
  28304         0,
  28305         1,
  28306         soc_OAMP_RFC_6374_LM_PWE_CW_0_BCM88690_A0r_fields,
  28307         SOC_RESET_VAL_DEC(0x1000000a, 0x00000000)
  28308         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28309         -1,
  28310         -1,
  28311     },
  28312 #endif /* chips */
  28313 
  28314 #if defined(BCM_88690_B0)
  28315     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_0_BCM88690_B0r */
  28316         soc_block_list[22],
  28317         soc_genreg,
  28318         1,
  28319         0,
  28320         0x526,
  28321         0,
  28322         0,
  28323         1,
  28324         soc_OAMP_RFC_6374_LM_PWE_CW_0_BCM88690_B0r_fields,
  28325         SOC_RESET_VAL_DEC(0x1000000a, 0x00000000)
  28326         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28327         -1,
  28328         -1,
  28329     },
  28330 #endif /* chips */
  28331 
  28332 #if defined(BCM_88270_A0)
  28333     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_1_BCM88270_A0r */
  28334         soc_block_list[22],
  28335         soc_genreg,
  28336         1,
  28337         0,
  28338         0x437,
  28339         0,
  28340         0,
  28341         1,
  28342         soc_OAMP_RFC_6374_LM_PWE_CW_1_BCM88270_A0r_fields,
  28343         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28344         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28345         -1,
  28346         -1,
  28347     },
  28348 #endif /* chips */
  28349 
  28350 #if defined(BCM_88470_B0)
  28351     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_1_BCM88470_B0r */
  28352         soc_block_list[22],
  28353         soc_genreg,
  28354         1,
  28355         0,
  28356         0x437,
  28357         0,
  28358         0,
  28359         1,
  28360         soc_OAMP_RFC_6374_LM_PWE_CW_1_BCM88470_B0r_fields,
  28361         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28362         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28363         -1,
  28364         -1,
  28365     },
  28366 #endif /* chips */
  28367 
  28368 #if defined(BCM_88690_A0)
  28369     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_1_BCM88690_A0r */
  28370         soc_block_list[22],
  28371         soc_genreg,
  28372         1,
  28373         0,
  28374         0x527,
  28375         0,
  28376         0,
  28377         1,
  28378         soc_OAMP_RFC_6374_LM_PWE_CW_1_BCM88690_A0r_fields,
  28379         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28380         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28381         -1,
  28382         -1,
  28383     },
  28384 #endif /* chips */
  28385 
  28386 #if defined(BCM_88690_B0)
  28387     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_1_BCM88690_B0r */
  28388         soc_block_list[22],
  28389         soc_genreg,
  28390         1,
  28391         0,
  28392         0x527,
  28393         0,
  28394         0,
  28395         1,
  28396         soc_OAMP_RFC_6374_LM_PWE_CW_1_BCM88690_B0r_fields,
  28397         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28398         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28399         -1,
  28400         -1,
  28401     },
  28402 #endif /* chips */
  28403 
  28404 #if defined(BCM_88375_A0)
  28405     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_BCM88375_A0r */
  28406         soc_block_list[22],
  28407         soc_genreg,
  28408         1,
  28409         0,
  28410         0x434,
  28411         0,
  28412         0,
  28413         1,
  28414         soc_OAMP_RFC_6374_LM_PWE_CW_BCM88375_A0r_fields,
  28415         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28416         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28417         -1,
  28418         -1,
  28419     },
  28420 #endif /* chips */
  28421 
  28422 #if defined(BCM_88375_B0)
  28423     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_BCM88375_B0r */
  28424         soc_block_list[22],
  28425         soc_genreg,
  28426         1,
  28427         0,
  28428         0x434,
  28429         0,
  28430         0,
  28431         1,
  28432         soc_OAMP_RFC_6374_LM_PWE_CW_BCM88375_B0r_fields,
  28433         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28434         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28435         -1,
  28436         -1,
  28437     },
  28438 #endif /* chips */
  28439 
  28440 #if defined(BCM_88675_B0)
  28441     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_BCM88675_B0r */
  28442         soc_block_list[22],
  28443         soc_genreg,
  28444         1,
  28445         0,
  28446         0x434,
  28447         0,
  28448         0,
  28449         1,
  28450         soc_OAMP_RFC_6374_LM_PWE_CW_BCM88675_B0r_fields,
  28451         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28452         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28453         -1,
  28454         -1,
  28455     },
  28456 #endif /* chips */
  28457 
  28458 #if defined(BCM_88680_A0)
  28459     { /* SOC_REG_INT_OAMP_RFC_6374_LM_PWE_CW_BCM88680_A0r */
  28460         soc_block_list[22],
  28461         soc_genreg,
  28462         1,
  28463         0,
  28464         0x434,
  28465         0,
  28466         0,
  28467         1,
  28468         soc_OAMP_RFC_6374_LM_PWE_CW_BCM88680_A0r_fields,
  28469         SOC_RESET_VAL_DEC(0x1000000b, 0x00000000)
  28470         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28471         -1,
  28472         -1,
  28473     },
  28474 #endif /* chips */
  28475 
  28476 #if defined(BCM_88650_A0)
  28477     { /* SOC_REG_INT_OAMP_RMAPEM_CAM_ENTRIES_COUNTERr */
  28478         soc_block_list[22],
  28479         soc_genreg,
  28480         1,
  28481         0,
  28482         0x215,
  28483         SOC_REG_FLAG_RO,
  28484         0,
  28485         1,
  28486         soc_OAMP_RMAPEM_CAM_ENTRIES_COUNTERr_fields,
  28487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28488         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  28489         -1,
  28490         -1,
  28491     },
  28492 #endif /* chips */
  28493 
  28494 #if defined(BCM_88650_B0)
  28495     { /* SOC_REG_INT_OAMP_RMAPEM_CAM_ENTRIES_COUNTER_BCM88650_B0r */
  28496         soc_block_list[22],
  28497         soc_genreg,
  28498         1,
  28499         0,
  28500         0x215,
  28501         SOC_REG_FLAG_RO,
  28502         0,
  28503         1,
  28504         soc_OAMP_RMAPEM_CAM_ENTRIES_COUNTER_BCM88650_B0r_fields,
  28505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28506         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  28507         -1,
  28508         -1,
  28509     },
  28510 #endif /* chips */
  28511 
  28512 #if defined(BCM_88660_A0)
  28513     { /* SOC_REG_INT_OAMP_RMAPEM_CAM_ENTRIES_COUNTER_BCM88660_A0r */
  28514         soc_block_list[22],
  28515         soc_genreg,
  28516         1,
  28517         0,
  28518         0x215,
  28519         SOC_REG_FLAG_RO,
  28520         0,
  28521         1,
  28522         soc_OAMP_RMAPEM_CAM_ENTRIES_COUNTER_BCM88660_A0r_fields,
  28523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28524         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  28525         -1,
  28526         -1,
  28527     },
  28528 #endif /* chips */
  28529 
  28530 #if defined(BCM_88650_A0)
  28531     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICSr */
  28532         soc_block_list[22],
  28533         soc_genreg,
  28534         1,
  28535         0,
  28536         0x207,
  28537         0,
  28538         0,
  28539         3,
  28540         soc_OAMP_RMAPEM_DIAGNOSTICSr_fields,
  28541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28542         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  28543         -1,
  28544         -1,
  28545     },
  28546 #endif /* chips */
  28547 
  28548 #if defined(BCM_88650_A0)
  28549     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_ACCESSED_MODEr */
  28550         soc_block_list[22],
  28551         soc_genreg,
  28552         1,
  28553         0,
  28554         0x208,
  28555         SOC_REG_FLAG_SIGNAL,
  28556         0,
  28557         1,
  28558         soc_OAMP_RMAPEM_DIAGNOSTICS_ACCESSED_MODEr_fields,
  28559         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  28560         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  28561         -1,
  28562         -1,
  28563     },
  28564 #endif /* chips */
  28565 
  28566 #if defined(BCM_88650_B0)
  28567     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_ACCESSED_MODE_BCM88650_B0r */
  28568         soc_block_list[22],
  28569         soc_genreg,
  28570         1,
  28571         0,
  28572         0x208,
  28573         SOC_REG_FLAG_SIGNAL,
  28574         0,
  28575         1,
  28576         soc_OAMP_RMAPEM_DIAGNOSTICS_ACCESSED_MODE_BCM88650_B0r_fields,
  28577         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  28578         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  28579         -1,
  28580         -1,
  28581     },
  28582 #endif /* chips */
  28583 
  28584 #if defined(BCM_88660_A0)
  28585     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_ACCESSED_MODE_BCM88660_A0r */
  28586         soc_block_list[22],
  28587         soc_genreg,
  28588         1,
  28589         0,
  28590         0x208,
  28591         SOC_REG_FLAG_SIGNAL,
  28592         0,
  28593         1,
  28594         soc_OAMP_RMAPEM_DIAGNOSTICS_ACCESSED_MODE_BCM88660_A0r_fields,
  28595         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  28596         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  28597         -1,
  28598         -1,
  28599     },
  28600 #endif /* chips */
  28601 
  28602 #if defined(BCM_88650_B0)
  28603     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_BCM88650_B0r */
  28604         soc_block_list[22],
  28605         soc_genreg,
  28606         1,
  28607         0,
  28608         0x207,
  28609         0,
  28610         0,
  28611         3,
  28612         soc_OAMP_RMAPEM_DIAGNOSTICS_BCM88650_B0r_fields,
  28613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28614         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  28615         -1,
  28616         -1,
  28617     },
  28618 #endif /* chips */
  28619 
  28620 #if defined(BCM_88660_A0)
  28621     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_BCM88660_A0r */
  28622         soc_block_list[22],
  28623         soc_genreg,
  28624         1,
  28625         0,
  28626         0x207,
  28627         0,
  28628         0,
  28629         3,
  28630         soc_OAMP_RMAPEM_DIAGNOSTICS_BCM88660_A0r_fields,
  28631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28632         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  28633         -1,
  28634         -1,
  28635     },
  28636 #endif /* chips */
  28637 
  28638 #if defined(BCM_88650_A0)
  28639     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_INDEXr */
  28640         soc_block_list[22],
  28641         soc_genreg,
  28642         1,
  28643         0,
  28644         0x209,
  28645         SOC_REG_FLAG_SIGNAL,
  28646         0,
  28647         1,
  28648         soc_OAMP_RMAPEM_DIAGNOSTICS_INDEXr_fields,
  28649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28650         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  28651         -1,
  28652         -1,
  28653     },
  28654 #endif /* chips */
  28655 
  28656 #if defined(BCM_88650_B0)
  28657     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_INDEX_BCM88650_B0r */
  28658         soc_block_list[22],
  28659         soc_genreg,
  28660         1,
  28661         0,
  28662         0x209,
  28663         SOC_REG_FLAG_SIGNAL,
  28664         0,
  28665         1,
  28666         soc_OAMP_RMAPEM_DIAGNOSTICS_INDEX_BCM88650_B0r_fields,
  28667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28668         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  28669         -1,
  28670         -1,
  28671     },
  28672 #endif /* chips */
  28673 
  28674 #if defined(BCM_88660_A0)
  28675     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_INDEX_BCM88660_A0r */
  28676         soc_block_list[22],
  28677         soc_genreg,
  28678         1,
  28679         0,
  28680         0x209,
  28681         SOC_REG_FLAG_SIGNAL,
  28682         0,
  28683         1,
  28684         soc_OAMP_RMAPEM_DIAGNOSTICS_INDEX_BCM88660_A0r_fields,
  28685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28686         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  28687         -1,
  28688         -1,
  28689     },
  28690 #endif /* chips */
  28691 
  28692 #if defined(BCM_88650_A0)
  28693     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_KEYr */
  28694         soc_block_list[22],
  28695         soc_genreg,
  28696         1,
  28697         0,
  28698         0x20a,
  28699         SOC_REG_FLAG_SIGNAL,
  28700         0,
  28701         1,
  28702         soc_OAMP_RMAPEM_DIAGNOSTICS_KEYr_fields,
  28703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28704         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  28705         -1,
  28706         -1,
  28707     },
  28708 #endif /* chips */
  28709 
  28710 #if defined(BCM_88650_B0)
  28711     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_KEY_BCM88650_B0r */
  28712         soc_block_list[22],
  28713         soc_genreg,
  28714         1,
  28715         0,
  28716         0x20a,
  28717         SOC_REG_FLAG_SIGNAL,
  28718         0,
  28719         1,
  28720         soc_OAMP_RMAPEM_DIAGNOSTICS_KEY_BCM88650_B0r_fields,
  28721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28722         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  28723         -1,
  28724         -1,
  28725     },
  28726 #endif /* chips */
  28727 
  28728 #if defined(BCM_88660_A0)
  28729     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_KEY_BCM88660_A0r */
  28730         soc_block_list[22],
  28731         soc_genreg,
  28732         1,
  28733         0,
  28734         0x20a,
  28735         SOC_REG_FLAG_SIGNAL,
  28736         0,
  28737         1,
  28738         soc_OAMP_RMAPEM_DIAGNOSTICS_KEY_BCM88660_A0r_fields,
  28739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28740         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  28741         -1,
  28742         -1,
  28743     },
  28744 #endif /* chips */
  28745 
  28746 #if defined(BCM_88650_A0)
  28747     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_LOOKUP_RESULTr */
  28748         soc_block_list[22],
  28749         soc_genreg,
  28750         1,
  28751         0,
  28752         0x20b,
  28753         SOC_REG_FLAG_RO,
  28754         0,
  28755         4,
  28756         soc_OAMP_RMAPEM_DIAGNOSTICS_LOOKUP_RESULTr_fields,
  28757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28758         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  28759         -1,
  28760         -1,
  28761     },
  28762 #endif /* chips */
  28763 
  28764 #if defined(BCM_88650_B0)
  28765     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_LOOKUP_RESULT_BCM88650_B0r */
  28766         soc_block_list[22],
  28767         soc_genreg,
  28768         1,
  28769         0,
  28770         0x20b,
  28771         SOC_REG_FLAG_RO,
  28772         0,
  28773         4,
  28774         soc_OAMP_RMAPEM_DIAGNOSTICS_LOOKUP_RESULT_BCM88650_B0r_fields,
  28775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28776         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  28777         -1,
  28778         -1,
  28779     },
  28780 #endif /* chips */
  28781 
  28782 #if defined(BCM_88660_A0)
  28783     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_LOOKUP_RESULT_BCM88660_A0r */
  28784         soc_block_list[22],
  28785         soc_genreg,
  28786         1,
  28787         0,
  28788         0x20b,
  28789         SOC_REG_FLAG_RO,
  28790         0,
  28791         4,
  28792         soc_OAMP_RMAPEM_DIAGNOSTICS_LOOKUP_RESULT_BCM88660_A0r_fields,
  28793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28794         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  28795         -1,
  28796         -1,
  28797     },
  28798 #endif /* chips */
  28799 
  28800 #if defined(BCM_88650_A0)
  28801     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_READ_RESULTr */
  28802         soc_block_list[22],
  28803         soc_genreg,
  28804         1,
  28805         0,
  28806         0x20c,
  28807         SOC_REG_FLAG_RO,
  28808         0,
  28809         2,
  28810         soc_OAMP_RMAPEM_DIAGNOSTICS_READ_RESULTr_fields,
  28811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28812         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  28813         -1,
  28814         -1,
  28815     },
  28816 #endif /* chips */
  28817 
  28818 #if defined(BCM_88650_B0)
  28819     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_READ_RESULT_BCM88650_B0r */
  28820         soc_block_list[22],
  28821         soc_genreg,
  28822         1,
  28823         0,
  28824         0x20c,
  28825         SOC_REG_FLAG_RO,
  28826         0,
  28827         2,
  28828         soc_OAMP_RMAPEM_DIAGNOSTICS_READ_RESULT_BCM88650_B0r_fields,
  28829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28830         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  28831         -1,
  28832         -1,
  28833     },
  28834 #endif /* chips */
  28835 
  28836 #if defined(BCM_88660_A0)
  28837     { /* SOC_REG_INT_OAMP_RMAPEM_DIAGNOSTICS_READ_RESULT_BCM88660_A0r */
  28838         soc_block_list[22],
  28839         soc_genreg,
  28840         1,
  28841         0,
  28842         0x20c,
  28843         SOC_REG_FLAG_RO,
  28844         0,
  28845         2,
  28846         soc_OAMP_RMAPEM_DIAGNOSTICS_READ_RESULT_BCM88660_A0r_fields,
  28847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28848         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  28849         -1,
  28850         -1,
  28851     },
  28852 #endif /* chips */
  28853 
  28854 #if defined(BCM_88650_A0)
  28855     { /* SOC_REG_INT_OAMP_RMAPEM_ENTRIES_COUNTERr */
  28856         soc_block_list[22],
  28857         soc_genreg,
  28858         1,
  28859         0,
  28860         0x214,
  28861         SOC_REG_FLAG_RO,
  28862         0,
  28863         1,
  28864         soc_OAMP_RMAPEM_ENTRIES_COUNTERr_fields,
  28865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28866         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  28867         -1,
  28868         -1,
  28869     },
  28870 #endif /* chips */
  28871 
  28872 #if defined(BCM_88650_B0)
  28873     { /* SOC_REG_INT_OAMP_RMAPEM_ENTRIES_COUNTER_BCM88650_B0r */
  28874         soc_block_list[22],
  28875         soc_genreg,
  28876         1,
  28877         0,
  28878         0x214,
  28879         SOC_REG_FLAG_RO,
  28880         0,
  28881         1,
  28882         soc_OAMP_RMAPEM_ENTRIES_COUNTER_BCM88650_B0r_fields,
  28883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28884         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  28885         -1,
  28886         -1,
  28887     },
  28888 #endif /* chips */
  28889 
  28890 #if defined(BCM_88660_A0)
  28891     { /* SOC_REG_INT_OAMP_RMAPEM_ENTRIES_COUNTER_BCM88660_A0r */
  28892         soc_block_list[22],
  28893         soc_genreg,
  28894         1,
  28895         0,
  28896         0x214,
  28897         SOC_REG_FLAG_RO,
  28898         0,
  28899         1,
  28900         soc_OAMP_RMAPEM_ENTRIES_COUNTER_BCM88660_A0r_fields,
  28901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28902         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  28903         -1,
  28904         -1,
  28905     },
  28906 #endif /* chips */
  28907 
  28908 #if defined(BCM_88650_A0)
  28909     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_CAM_TABLE_FULL_COUNTERr */
  28910         soc_block_list[22],
  28911         soc_genreg,
  28912         1,
  28913         0,
  28914         0x212,
  28915         SOC_REG_FLAG_RO,
  28916         0,
  28917         2,
  28918         soc_OAMP_RMAPEM_ERROR_CAM_TABLE_FULL_COUNTERr_fields,
  28919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28920         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28921         -1,
  28922         -1,
  28923     },
  28924 #endif /* chips */
  28925 
  28926 #if defined(BCM_88650_B0)
  28927     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_CAM_TABLE_FULL_COUNTER_BCM88650_B0r */
  28928         soc_block_list[22],
  28929         soc_genreg,
  28930         1,
  28931         0,
  28932         0x212,
  28933         SOC_REG_FLAG_RO,
  28934         0,
  28935         2,
  28936         soc_OAMP_RMAPEM_ERROR_CAM_TABLE_FULL_COUNTER_BCM88650_B0r_fields,
  28937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28938         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28939         -1,
  28940         -1,
  28941     },
  28942 #endif /* chips */
  28943 
  28944 #if defined(BCM_88660_A0)
  28945     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_CAM_TABLE_FULL_COUNTER_BCM88660_A0r */
  28946         soc_block_list[22],
  28947         soc_genreg,
  28948         1,
  28949         0,
  28950         0x212,
  28951         SOC_REG_FLAG_RO,
  28952         0,
  28953         2,
  28954         soc_OAMP_RMAPEM_ERROR_CAM_TABLE_FULL_COUNTER_BCM88660_A0r_fields,
  28955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28956         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28957         -1,
  28958         -1,
  28959     },
  28960 #endif /* chips */
  28961 
  28962 #if defined(BCM_88650_A0)
  28963     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_DELETE_UNKNOWN_KEY_COUNTERr */
  28964         soc_block_list[22],
  28965         soc_genreg,
  28966         1,
  28967         0,
  28968         0x210,
  28969         SOC_REG_FLAG_RO,
  28970         0,
  28971         2,
  28972         soc_OAMP_RMAPEM_ERROR_DELETE_UNKNOWN_KEY_COUNTERr_fields,
  28973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28974         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28975         -1,
  28976         -1,
  28977     },
  28978 #endif /* chips */
  28979 
  28980 #if defined(BCM_88650_B0)
  28981     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88650_B0r */
  28982         soc_block_list[22],
  28983         soc_genreg,
  28984         1,
  28985         0,
  28986         0x210,
  28987         SOC_REG_FLAG_RO,
  28988         0,
  28989         2,
  28990         soc_OAMP_RMAPEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88650_B0r_fields,
  28991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28992         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28993         -1,
  28994         -1,
  28995     },
  28996 #endif /* chips */
  28997 
  28998 #if defined(BCM_88660_A0)
  28999     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88660_A0r */
  29000         soc_block_list[22],
  29001         soc_genreg,
  29002         1,
  29003         0,
  29004         0x210,
  29005         SOC_REG_FLAG_RO,
  29006         0,
  29007         2,
  29008         soc_OAMP_RMAPEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER_BCM88660_A0r_fields,
  29009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29010         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29011         -1,
  29012         -1,
  29013     },
  29014 #endif /* chips */
  29015 
  29016 #if defined(BCM_88650_A0)
  29017     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTERr */
  29018         soc_block_list[22],
  29019         soc_genreg,
  29020         1,
  29021         0,
  29022         0x211,
  29023         SOC_REG_FLAG_RO,
  29024         0,
  29025         2,
  29026         soc_OAMP_RMAPEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTERr_fields,
  29027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29028         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29029         -1,
  29030         -1,
  29031     },
  29032 #endif /* chips */
  29033 
  29034 #if defined(BCM_88650_B0)
  29035     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88650_B0r */
  29036         soc_block_list[22],
  29037         soc_genreg,
  29038         1,
  29039         0,
  29040         0x211,
  29041         SOC_REG_FLAG_RO,
  29042         0,
  29043         2,
  29044         soc_OAMP_RMAPEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88650_B0r_fields,
  29045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29046         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29047         -1,
  29048         -1,
  29049     },
  29050 #endif /* chips */
  29051 
  29052 #if defined(BCM_88660_A0)
  29053     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88660_A0r */
  29054         soc_block_list[22],
  29055         soc_genreg,
  29056         1,
  29057         0,
  29058         0x211,
  29059         SOC_REG_FLAG_RO,
  29060         0,
  29061         2,
  29062         soc_OAMP_RMAPEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER_BCM88660_A0r_fields,
  29063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29064         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29065         -1,
  29066         -1,
  29067     },
  29068 #endif /* chips */
  29069 
  29070 #if defined(BCM_88650_A0)
  29071     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_TABLE_COHERENCY_COUNTERr */
  29072         soc_block_list[22],
  29073         soc_genreg,
  29074         1,
  29075         0,
  29076         0x20f,
  29077         SOC_REG_FLAG_RO,
  29078         0,
  29079         2,
  29080         soc_OAMP_RMAPEM_ERROR_TABLE_COHERENCY_COUNTERr_fields,
  29081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29082         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29083         -1,
  29084         -1,
  29085     },
  29086 #endif /* chips */
  29087 
  29088 #if defined(BCM_88650_B0)
  29089     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_TABLE_COHERENCY_COUNTER_BCM88650_B0r */
  29090         soc_block_list[22],
  29091         soc_genreg,
  29092         1,
  29093         0,
  29094         0x20f,
  29095         SOC_REG_FLAG_RO,
  29096         0,
  29097         2,
  29098         soc_OAMP_RMAPEM_ERROR_TABLE_COHERENCY_COUNTER_BCM88650_B0r_fields,
  29099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29100         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29101         -1,
  29102         -1,
  29103     },
  29104 #endif /* chips */
  29105 
  29106 #if defined(BCM_88660_A0)
  29107     { /* SOC_REG_INT_OAMP_RMAPEM_ERROR_TABLE_COHERENCY_COUNTER_BCM88660_A0r */
  29108         soc_block_list[22],
  29109         soc_genreg,
  29110         1,
  29111         0,
  29112         0x20f,
  29113         SOC_REG_FLAG_RO,
  29114         0,
  29115         2,
  29116         soc_OAMP_RMAPEM_ERROR_TABLE_COHERENCY_COUNTER_BCM88660_A0r_fields,
  29117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29118         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29119         -1,
  29120         -1,
  29121     },
  29122 #endif /* chips */
  29123 
  29124 #if defined(BCM_88650_A0)
  29125     { /* SOC_REG_INT_OAMP_RMAPEM_GENERAL_EM_CONFIGURATION_REGISTERr */
  29126         soc_block_list[22],
  29127         soc_genreg,
  29128         1,
  29129         0,
  29130         0x202,
  29131         0,
  29132         0,
  29133         4,
  29134         soc_OAMP_RMAPEM_GENERAL_EM_CONFIGURATION_REGISTERr_fields,
  29135         SOC_RESET_VAL_DEC(0x00001f10, 0x00000000)
  29136         SOC_RESET_MASK_DEC(0x00011f13, 0x00000000)
  29137         -1,
  29138         -1,
  29139     },
  29140 #endif /* chips */
  29141 
  29142 #if defined(BCM_88650_B0)
  29143     { /* SOC_REG_INT_OAMP_RMAPEM_GENERAL_EM_CONFIGURATION_REGISTER_BCM88650_B0r */
  29144         soc_block_list[22],
  29145         soc_genreg,
  29146         1,
  29147         0,
  29148         0x202,
  29149         0,
  29150         0,
  29151         4,
  29152         soc_OAMP_RMAPEM_GENERAL_EM_CONFIGURATION_REGISTER_BCM88650_B0r_fields,
  29153         SOC_RESET_VAL_DEC(0x00001f10, 0x00000000)
  29154         SOC_RESET_MASK_DEC(0x00011f13, 0x00000000)
  29155         -1,
  29156         -1,
  29157     },
  29158 #endif /* chips */
  29159 
  29160 #if defined(BCM_88660_A0)
  29161     { /* SOC_REG_INT_OAMP_RMAPEM_GENERAL_EM_CONFIGURATION_REGISTER_BCM88660_A0r */
  29162         soc_block_list[22],
  29163         soc_genreg,
  29164         1,
  29165         0,
  29166         0x202,
  29167         0,
  29168         0,
  29169         5,
  29170         soc_OAMP_RMAPEM_GENERAL_EM_CONFIGURATION_REGISTER_BCM88660_A0r_fields,
  29171         SOC_RESET_VAL_DEC(0x00003f00, 0x00000000)
  29172         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  29173         -1,
  29174         -1,
  29175     },
  29176 #endif /* chips */
  29177 
  29178 #if defined(BCM_88650_A0)
  29179     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_MASK_REGISTER_ONEr */
  29180         soc_block_list[22],
  29181         soc_genreg,
  29182         1,
  29183         0,
  29184         0x12,
  29185         SOC_REG_FLAG_INTERRUPT,
  29186         0,
  29187         7,
  29188         soc_OAMP_RMAPEM_INTERRUPT_MASK_REGISTER_ONEr_fields,
  29189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29190         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29191         -1,
  29192         -1,
  29193     },
  29194 #endif /* chips */
  29195 
  29196 #if defined(BCM_88650_B0)
  29197     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_MASK_REGISTER_ONE_BCM88650_B0r */
  29198         soc_block_list[22],
  29199         soc_genreg,
  29200         1,
  29201         0,
  29202         0x12,
  29203         SOC_REG_FLAG_INTERRUPT,
  29204         0,
  29205         7,
  29206         soc_OAMP_RMAPEM_INTERRUPT_MASK_REGISTER_ONE_BCM88650_B0r_fields,
  29207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29208         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29209         -1,
  29210         -1,
  29211     },
  29212 #endif /* chips */
  29213 
  29214 #if defined(BCM_88660_A0)
  29215     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_MASK_REGISTER_ONE_BCM88660_A0r */
  29216         soc_block_list[22],
  29217         soc_genreg,
  29218         1,
  29219         0,
  29220         0x12,
  29221         SOC_REG_FLAG_INTERRUPT,
  29222         0,
  29223         7,
  29224         soc_OAMP_RMAPEM_INTERRUPT_MASK_REGISTER_ONE_BCM88660_A0r_fields,
  29225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29226         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29227         -1,
  29228         -1,
  29229     },
  29230 #endif /* chips */
  29231 
  29232 #if defined(BCM_88650_A0)
  29233     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONEr */
  29234         soc_block_list[22],
  29235         soc_genreg,
  29236         1,
  29237         0,
  29238         0x2,
  29239         SOC_REG_FLAG_INTERRUPT,
  29240         0,
  29241         7,
  29242         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONEr_fields,
  29243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29244         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29245         -1,
  29246         -1,
  29247     },
  29248 #endif /* chips */
  29249 
  29250 #if defined(BCM_88650_B0)
  29251     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_BCM88650_B0r */
  29252         soc_block_list[22],
  29253         soc_genreg,
  29254         1,
  29255         0,
  29256         0x2,
  29257         SOC_REG_FLAG_INTERRUPT,
  29258         0,
  29259         7,
  29260         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_BCM88650_B0r_fields,
  29261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29262         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29263         -1,
  29264         -1,
  29265     },
  29266 #endif /* chips */
  29267 
  29268 #if defined(BCM_88660_A0)
  29269     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_BCM88660_A0r */
  29270         soc_block_list[22],
  29271         soc_genreg,
  29272         1,
  29273         0,
  29274         0x2,
  29275         SOC_REG_FLAG_INTERRUPT,
  29276         0,
  29277         7,
  29278         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_BCM88660_A0r_fields,
  29279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29280         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29281         -1,
  29282         -1,
  29283     },
  29284 #endif /* chips */
  29285 
  29286 #if defined(BCM_88650_A0)
  29287     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TESTr */
  29288         soc_block_list[22],
  29289         soc_genreg,
  29290         1,
  29291         0,
  29292         0x1b,
  29293         SOC_REG_FLAG_INTERRUPT |
  29294                           SOC_REG_FLAG_SIGNAL,
  29295         0,
  29296         1,
  29297         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TESTr_fields,
  29298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29299         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29300         -1,
  29301         -1,
  29302     },
  29303 #endif /* chips */
  29304 
  29305 #if defined(BCM_88270_A0)
  29306     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88270_A0r */
  29307         soc_block_list[22],
  29308         soc_genreg,
  29309         1,
  29310         0,
  29311         0x1b,
  29312         0,
  29313         0,
  29314         1,
  29315         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88270_A0r_fields,
  29316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29317         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29318         -1,
  29319         -1,
  29320     },
  29321 #endif /* chips */
  29322 
  29323 #if defined(BCM_88375_A0)
  29324     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88375_A0r */
  29325         soc_block_list[22],
  29326         soc_genreg,
  29327         1,
  29328         0,
  29329         0x1b,
  29330         0,
  29331         0,
  29332         1,
  29333         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88375_A0r_fields,
  29334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29335         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29336         -1,
  29337         -1,
  29338     },
  29339 #endif /* chips */
  29340 
  29341 #if defined(BCM_88375_B0)
  29342     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88375_B0r */
  29343         soc_block_list[22],
  29344         soc_genreg,
  29345         1,
  29346         0,
  29347         0x1b,
  29348         0,
  29349         0,
  29350         1,
  29351         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88375_B0r_fields,
  29352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29353         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29354         -1,
  29355         -1,
  29356     },
  29357 #endif /* chips */
  29358 
  29359 #if defined(BCM_88470_A0)
  29360     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88470_A0r */
  29361         soc_block_list[22],
  29362         soc_genreg,
  29363         1,
  29364         0,
  29365         0x1b,
  29366         0,
  29367         0,
  29368         1,
  29369         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88470_A0r_fields,
  29370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29371         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29372         -1,
  29373         -1,
  29374     },
  29375 #endif /* chips */
  29376 
  29377 #if defined(BCM_88470_B0)
  29378     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88470_B0r */
  29379         soc_block_list[22],
  29380         soc_genreg,
  29381         1,
  29382         0,
  29383         0x1b,
  29384         0,
  29385         0,
  29386         1,
  29387         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88470_B0r_fields,
  29388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29389         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29390         -1,
  29391         -1,
  29392     },
  29393 #endif /* chips */
  29394 
  29395 #if defined(BCM_88650_B0)
  29396     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88650_B0r */
  29397         soc_block_list[22],
  29398         soc_genreg,
  29399         1,
  29400         0,
  29401         0x1b,
  29402         SOC_REG_FLAG_INTERRUPT |
  29403                           SOC_REG_FLAG_SIGNAL,
  29404         0,
  29405         1,
  29406         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88650_B0r_fields,
  29407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29408         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29409         -1,
  29410         -1,
  29411     },
  29412 #endif /* chips */
  29413 
  29414 #if defined(BCM_88660_A0)
  29415     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88660_A0r */
  29416         soc_block_list[22],
  29417         soc_genreg,
  29418         1,
  29419         0,
  29420         0x1b,
  29421         SOC_REG_FLAG_INTERRUPT |
  29422                           SOC_REG_FLAG_SIGNAL,
  29423         0,
  29424         1,
  29425         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88660_A0r_fields,
  29426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29427         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29428         -1,
  29429         -1,
  29430     },
  29431 #endif /* chips */
  29432 
  29433 #if defined(BCM_88675_A0)
  29434     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88675_A0r */
  29435         soc_block_list[22],
  29436         soc_genreg,
  29437         1,
  29438         0,
  29439         0x1b,
  29440         0,
  29441         0,
  29442         1,
  29443         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88675_A0r_fields,
  29444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29445         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29446         -1,
  29447         -1,
  29448     },
  29449 #endif /* chips */
  29450 
  29451 #if defined(BCM_88675_B0)
  29452     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88675_B0r */
  29453         soc_block_list[22],
  29454         soc_genreg,
  29455         1,
  29456         0,
  29457         0x1b,
  29458         0,
  29459         0,
  29460         1,
  29461         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88675_B0r_fields,
  29462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29463         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29464         -1,
  29465         -1,
  29466     },
  29467 #endif /* chips */
  29468 
  29469 #if defined(BCM_88680_A0)
  29470     { /* SOC_REG_INT_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88680_A0r */
  29471         soc_block_list[22],
  29472         soc_genreg,
  29473         1,
  29474         0,
  29475         0x1b,
  29476         0,
  29477         0,
  29478         1,
  29479         soc_OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST_BCM88680_A0r_fields,
  29480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29481         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29482         -1,
  29483         -1,
  29484     },
  29485 #endif /* chips */
  29486 
  29487 #if defined(BCM_88650_A0)
  29488     { /* SOC_REG_INT_OAMP_RMAPEM_KEY_TABLE_ENTRY_LIMITr */
  29489         soc_block_list[22],
  29490         soc_genreg,
  29491         1,
  29492         0,
  29493         0x204,
  29494         0,
  29495         0,
  29496         1,
  29497         soc_OAMP_RMAPEM_KEY_TABLE_ENTRY_LIMITr_fields,
  29498         SOC_RESET_VAL_DEC(0x00004000, 0x00000000)
  29499         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  29500         -1,
  29501         -1,
  29502     },
  29503 #endif /* chips */
  29504 
  29505 #if defined(BCM_88650_B0)
  29506     { /* SOC_REG_INT_OAMP_RMAPEM_KEY_TABLE_ENTRY_LIMIT_BCM88650_B0r */
  29507         soc_block_list[22],
  29508         soc_genreg,
  29509         1,
  29510         0,
  29511         0x204,
  29512         0,
  29513         0,
  29514         1,
  29515         soc_OAMP_RMAPEM_KEY_TABLE_ENTRY_LIMIT_BCM88650_B0r_fields,
  29516         SOC_RESET_VAL_DEC(0x00004000, 0x00000000)
  29517         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  29518         -1,
  29519         -1,
  29520     },
  29521 #endif /* chips */
  29522 
  29523 #if defined(BCM_88660_A0)
  29524     { /* SOC_REG_INT_OAMP_RMAPEM_KEY_TABLE_ENTRY_LIMIT_BCM88660_A0r */
  29525         soc_block_list[22],
  29526         soc_genreg,
  29527         1,
  29528         0,
  29529         0x204,
  29530         0,
  29531         0,
  29532         1,
  29533         soc_OAMP_RMAPEM_KEY_TABLE_ENTRY_LIMIT_BCM88660_A0r_fields,
  29534         SOC_RESET_VAL_DEC(0x00004000, 0x00000000)
  29535         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  29536         -1,
  29537         -1,
  29538     },
  29539 #endif /* chips */
  29540 
  29541 #if defined(BCM_88650_A0)
  29542     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUPr */
  29543         soc_block_list[22],
  29544         soc_genreg,
  29545         1,
  29546         0,
  29547         0x221,
  29548         SOC_REG_FLAG_64_BITS |
  29549                           SOC_REG_FLAG_RO,
  29550         0,
  29551         3,
  29552         soc_OAMP_RMAPEM_LAST_LOOKUPr_fields,
  29553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29554         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  29555         -1,
  29556         -1,
  29557     },
  29558 #endif /* chips */
  29559 
  29560 #if defined(BCM_88270_A0)
  29561     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88270_A0r */
  29562         soc_block_list[22],
  29563         soc_genreg,
  29564         1,
  29565         0,
  29566         0x221,
  29567         SOC_REG_FLAG_64_BITS |
  29568                           SOC_REG_FLAG_RO |
  29569                           SOC_REG_FLAG_SIGNAL,
  29570         0,
  29571         3,
  29572         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88270_A0r_fields,
  29573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29574         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  29575         -1,
  29576         -1,
  29577     },
  29578 #endif /* chips */
  29579 
  29580 #if defined(BCM_88375_A0)
  29581     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88375_A0r */
  29582         soc_block_list[22],
  29583         soc_genreg,
  29584         1,
  29585         0,
  29586         0x221,
  29587         SOC_REG_FLAG_64_BITS |
  29588                           SOC_REG_FLAG_RO |
  29589                           SOC_REG_FLAG_SIGNAL,
  29590         0,
  29591         3,
  29592         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88375_A0r_fields,
  29593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29594         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  29595         -1,
  29596         -1,
  29597     },
  29598 #endif /* chips */
  29599 
  29600 #if defined(BCM_88375_B0)
  29601     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88375_B0r */
  29602         soc_block_list[22],
  29603         soc_genreg,
  29604         1,
  29605         0,
  29606         0x221,
  29607         SOC_REG_FLAG_64_BITS |
  29608                           SOC_REG_FLAG_RO |
  29609                           SOC_REG_FLAG_SIGNAL,
  29610         0,
  29611         3,
  29612         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88375_B0r_fields,
  29613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29614         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  29615         -1,
  29616         -1,
  29617     },
  29618 #endif /* chips */
  29619 
  29620 #if defined(BCM_88470_A0)
  29621     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88470_A0r */
  29622         soc_block_list[22],
  29623         soc_genreg,
  29624         1,
  29625         0,
  29626         0x221,
  29627         SOC_REG_FLAG_64_BITS |
  29628                           SOC_REG_FLAG_RO |
  29629                           SOC_REG_FLAG_SIGNAL,
  29630         0,
  29631         3,
  29632         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88470_A0r_fields,
  29633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29634         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  29635         -1,
  29636         -1,
  29637     },
  29638 #endif /* chips */
  29639 
  29640 #if defined(BCM_88470_B0)
  29641     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88470_B0r */
  29642         soc_block_list[22],
  29643         soc_genreg,
  29644         1,
  29645         0,
  29646         0x221,
  29647         SOC_REG_FLAG_64_BITS |
  29648                           SOC_REG_FLAG_RO |
  29649                           SOC_REG_FLAG_SIGNAL,
  29650         0,
  29651         3,
  29652         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88470_B0r_fields,
  29653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29654         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  29655         -1,
  29656         -1,
  29657     },
  29658 #endif /* chips */
  29659 
  29660 #if defined(BCM_88650_B0)
  29661     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88650_B0r */
  29662         soc_block_list[22],
  29663         soc_genreg,
  29664         1,
  29665         0,
  29666         0x221,
  29667         SOC_REG_FLAG_64_BITS |
  29668                           SOC_REG_FLAG_RO,
  29669         0,
  29670         3,
  29671         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88650_B0r_fields,
  29672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29673         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  29674         -1,
  29675         -1,
  29676     },
  29677 #endif /* chips */
  29678 
  29679 #if defined(BCM_88660_A0)
  29680     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88660_A0r */
  29681         soc_block_list[22],
  29682         soc_genreg,
  29683         1,
  29684         0,
  29685         0x221,
  29686         SOC_REG_FLAG_64_BITS |
  29687                           SOC_REG_FLAG_RO,
  29688         0,
  29689         3,
  29690         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88660_A0r_fields,
  29691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29692         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  29693         -1,
  29694         -1,
  29695     },
  29696 #endif /* chips */
  29697 
  29698 #if defined(BCM_88675_A0)
  29699     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88675_A0r */
  29700         soc_block_list[22],
  29701         soc_genreg,
  29702         1,
  29703         0,
  29704         0x221,
  29705         SOC_REG_FLAG_64_BITS |
  29706                           SOC_REG_FLAG_RO |
  29707                           SOC_REG_FLAG_SIGNAL,
  29708         0,
  29709         3,
  29710         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88675_A0r_fields,
  29711         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29712         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  29713         -1,
  29714         -1,
  29715     },
  29716 #endif /* chips */
  29717 
  29718 #if defined(BCM_88675_B0)
  29719     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88675_B0r */
  29720         soc_block_list[22],
  29721         soc_genreg,
  29722         1,
  29723         0,
  29724         0x221,
  29725         SOC_REG_FLAG_64_BITS |
  29726                           SOC_REG_FLAG_RO |
  29727                           SOC_REG_FLAG_SIGNAL,
  29728         0,
  29729         3,
  29730         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88675_B0r_fields,
  29731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29732         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  29733         -1,
  29734         -1,
  29735     },
  29736 #endif /* chips */
  29737 
  29738 #if defined(BCM_88680_A0)
  29739     { /* SOC_REG_INT_OAMP_RMAPEM_LAST_LOOKUP_BCM88680_A0r */
  29740         soc_block_list[22],
  29741         soc_genreg,
  29742         1,
  29743         0,
  29744         0x221,
  29745         SOC_REG_FLAG_64_BITS |
  29746                           SOC_REG_FLAG_RO |
  29747                           SOC_REG_FLAG_SIGNAL,
  29748         0,
  29749         3,
  29750         soc_OAMP_RMAPEM_LAST_LOOKUP_BCM88680_A0r_fields,
  29751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29752         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  29753         -1,
  29754         -1,
  29755     },
  29756 #endif /* chips */
  29757 
  29758 #if defined(BCM_88650_A0)
  29759     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTERr */
  29760         soc_block_list[22],
  29761         soc_genreg,
  29762         1,
  29763         0,
  29764         0x220,
  29765         SOC_REG_FLAG_RO,
  29766         0,
  29767         2,
  29768         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTERr_fields,
  29769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29770         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29771         -1,
  29772         -1,
  29773     },
  29774 #endif /* chips */
  29775 
  29776 #if defined(BCM_88270_A0)
  29777     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88270_A0r */
  29778         soc_block_list[22],
  29779         soc_genreg,
  29780         1,
  29781         0,
  29782         0x220,
  29783         SOC_REG_FLAG_RO,
  29784         0,
  29785         2,
  29786         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88270_A0r_fields,
  29787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29788         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29789         -1,
  29790         -1,
  29791     },
  29792 #endif /* chips */
  29793 
  29794 #if defined(BCM_88375_A0)
  29795     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88375_A0r */
  29796         soc_block_list[22],
  29797         soc_genreg,
  29798         1,
  29799         0,
  29800         0x220,
  29801         SOC_REG_FLAG_RO,
  29802         0,
  29803         2,
  29804         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88375_A0r_fields,
  29805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29806         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29807         -1,
  29808         -1,
  29809     },
  29810 #endif /* chips */
  29811 
  29812 #if defined(BCM_88375_B0)
  29813     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88375_B0r */
  29814         soc_block_list[22],
  29815         soc_genreg,
  29816         1,
  29817         0,
  29818         0x220,
  29819         SOC_REG_FLAG_RO,
  29820         0,
  29821         2,
  29822         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88375_B0r_fields,
  29823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29824         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29825         -1,
  29826         -1,
  29827     },
  29828 #endif /* chips */
  29829 
  29830 #if defined(BCM_88470_A0)
  29831     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88470_A0r */
  29832         soc_block_list[22],
  29833         soc_genreg,
  29834         1,
  29835         0,
  29836         0x220,
  29837         SOC_REG_FLAG_RO,
  29838         0,
  29839         2,
  29840         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88470_A0r_fields,
  29841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29842         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29843         -1,
  29844         -1,
  29845     },
  29846 #endif /* chips */
  29847 
  29848 #if defined(BCM_88470_B0)
  29849     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88470_B0r */
  29850         soc_block_list[22],
  29851         soc_genreg,
  29852         1,
  29853         0,
  29854         0x220,
  29855         SOC_REG_FLAG_RO,
  29856         0,
  29857         2,
  29858         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88470_B0r_fields,
  29859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29860         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29861         -1,
  29862         -1,
  29863     },
  29864 #endif /* chips */
  29865 
  29866 #if defined(BCM_88650_B0)
  29867     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88650_B0r */
  29868         soc_block_list[22],
  29869         soc_genreg,
  29870         1,
  29871         0,
  29872         0x220,
  29873         SOC_REG_FLAG_RO,
  29874         0,
  29875         2,
  29876         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88650_B0r_fields,
  29877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29878         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29879         -1,
  29880         -1,
  29881     },
  29882 #endif /* chips */
  29883 
  29884 #if defined(BCM_88660_A0)
  29885     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88660_A0r */
  29886         soc_block_list[22],
  29887         soc_genreg,
  29888         1,
  29889         0,
  29890         0x220,
  29891         SOC_REG_FLAG_RO,
  29892         0,
  29893         2,
  29894         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88660_A0r_fields,
  29895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29896         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29897         -1,
  29898         -1,
  29899     },
  29900 #endif /* chips */
  29901 
  29902 #if defined(BCM_88675_A0)
  29903     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88675_A0r */
  29904         soc_block_list[22],
  29905         soc_genreg,
  29906         1,
  29907         0,
  29908         0x220,
  29909         SOC_REG_FLAG_RO,
  29910         0,
  29911         2,
  29912         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88675_A0r_fields,
  29913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29915         -1,
  29916         -1,
  29917     },
  29918 #endif /* chips */
  29919 
  29920 #if defined(BCM_88675_B0)
  29921     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88675_B0r */
  29922         soc_block_list[22],
  29923         soc_genreg,
  29924         1,
  29925         0,
  29926         0x220,
  29927         SOC_REG_FLAG_RO,
  29928         0,
  29929         2,
  29930         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88675_B0r_fields,
  29931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29932         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29933         -1,
  29934         -1,
  29935     },
  29936 #endif /* chips */
  29937 
  29938 #if defined(BCM_88680_A0)
  29939     { /* SOC_REG_INT_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88680_A0r */
  29940         soc_block_list[22],
  29941         soc_genreg,
  29942         1,
  29943         0,
  29944         0x220,
  29945         SOC_REG_FLAG_RO,
  29946         0,
  29947         2,
  29948         soc_OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER_BCM88680_A0r_fields,
  29949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29950         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29951         -1,
  29952         -1,
  29953     },
  29954 #endif /* chips */
  29955 
  29956 #if defined(BCM_88650_A0)
  29957     { /* SOC_REG_INT_OAMP_RMAPEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTERr */
  29958         soc_block_list[22],
  29959         soc_genreg,
  29960         1,
  29961         0,
  29962         0x203,
  29963         0,
  29964         0,
  29965         3,
  29966         soc_OAMP_RMAPEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTERr_fields,
  29967         SOC_RESET_VAL_DEC(0x00003800, 0x00000000)
  29968         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  29969         -1,
  29970         -1,
  29971     },
  29972 #endif /* chips */
  29973 
  29974 #if defined(BCM_88650_B0)
  29975     { /* SOC_REG_INT_OAMP_RMAPEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88650_B0r */
  29976         soc_block_list[22],
  29977         soc_genreg,
  29978         1,
  29979         0,
  29980         0x203,
  29981         0,
  29982         0,
  29983         3,
  29984         soc_OAMP_RMAPEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88650_B0r_fields,
  29985         SOC_RESET_VAL_DEC(0x00003800, 0x00000000)
  29986         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  29987         -1,
  29988         -1,
  29989     },
  29990 #endif /* chips */
  29991 
  29992 #if defined(BCM_88660_A0)
  29993     { /* SOC_REG_INT_OAMP_RMAPEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88660_A0r */
  29994         soc_block_list[22],
  29995         soc_genreg,
  29996         1,
  29997         0,
  29998         0x203,
  29999         0,
  30000         0,
  30001         3,
  30002         soc_OAMP_RMAPEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER_BCM88660_A0r_fields,
  30003         SOC_RESET_VAL_DEC(0x00003800, 0x00000000)
  30004         SOC_RESET_MASK_DEC(0x00003f11, 0x00000000)
  30005         -1,
  30006         -1,
  30007     },
  30008 #endif /* chips */
  30009 
  30010 #if defined(BCM_88650_A0)
  30011     { /* SOC_REG_INT_OAMP_RMAPEM_MANAGEMENT_UNIT_FAILUREr */
  30012         soc_block_list[22],
  30013         soc_genreg,
  30014         1,
  30015         0,
  30016         0x205,
  30017         SOC_REG_FLAG_64_BITS |
  30018                           SOC_REG_FLAG_RO,
  30019         0,
  30020         3,
  30021         soc_OAMP_RMAPEM_MANAGEMENT_UNIT_FAILUREr_fields,
  30022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30023         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  30024         -1,
  30025         -1,
  30026     },
  30027 #endif /* chips */
  30028 
  30029 #if defined(BCM_88650_B0)
  30030     { /* SOC_REG_INT_OAMP_RMAPEM_MANAGEMENT_UNIT_FAILURE_BCM88650_B0r */
  30031         soc_block_list[22],
  30032         soc_genreg,
  30033         1,
  30034         0,
  30035         0x205,
  30036         SOC_REG_FLAG_64_BITS |
  30037                           SOC_REG_FLAG_RO,
  30038         0,
  30039         3,
  30040         soc_OAMP_RMAPEM_MANAGEMENT_UNIT_FAILURE_BCM88650_B0r_fields,
  30041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30042         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  30043         -1,
  30044         -1,
  30045     },
  30046 #endif /* chips */
  30047 
  30048 #if defined(BCM_88660_A0)
  30049     { /* SOC_REG_INT_OAMP_RMAPEM_MANAGEMENT_UNIT_FAILURE_BCM88660_A0r */
  30050         soc_block_list[22],
  30051         soc_genreg,
  30052         1,
  30053         0,
  30054         0x205,
  30055         SOC_REG_FLAG_64_BITS |
  30056                           SOC_REG_FLAG_RO,
  30057         0,
  30058         3,
  30059         soc_OAMP_RMAPEM_MANAGEMENT_UNIT_FAILURE_BCM88660_A0r_fields,
  30060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30061         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  30062         -1,
  30063         -1,
  30064     },
  30065 #endif /* chips */
  30066 
  30067 #if defined(BCM_88470_A0)
  30068     { /* SOC_REG_INT_OAMP_RMAPEM_MNGMNT_SER_INDICATIONr */
  30069         soc_block_list[22],
  30070         soc_genreg,
  30071         1,
  30072         0,
  30073         0x217,
  30074         SOC_REG_FLAG_SIGNAL,
  30075         0,
  30076         1,
  30077         soc_OAMP_RMAPEM_MNGMNT_SER_INDICATIONr_fields,
  30078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30079         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30080         -1,
  30081         -1,
  30082     },
  30083 #endif /* chips */
  30084 
  30085 #if defined(BCM_88270_A0)
  30086     { /* SOC_REG_INT_OAMP_RMAPEM_MNGMNT_SER_INDICATION_BCM88270_A0r */
  30087         soc_block_list[22],
  30088         soc_genreg,
  30089         1,
  30090         0,
  30091         0x217,
  30092         SOC_REG_FLAG_SIGNAL,
  30093         0,
  30094         1,
  30095         soc_OAMP_RMAPEM_MNGMNT_SER_INDICATION_BCM88270_A0r_fields,
  30096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30097         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30098         -1,
  30099         -1,
  30100     },
  30101 #endif /* chips */
  30102 
  30103 #if defined(BCM_88470_B0)
  30104     { /* SOC_REG_INT_OAMP_RMAPEM_MNGMNT_SER_INDICATION_BCM88470_B0r */
  30105         soc_block_list[22],
  30106         soc_genreg,
  30107         1,
  30108         0,
  30109         0x217,
  30110         SOC_REG_FLAG_SIGNAL,
  30111         0,
  30112         1,
  30113         soc_OAMP_RMAPEM_MNGMNT_SER_INDICATION_BCM88470_B0r_fields,
  30114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30115         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30116         -1,
  30117         -1,
  30118     },
  30119 #endif /* chips */
  30120 
  30121 #if defined(BCM_88650_A0)
  30122     { /* SOC_REG_INT_OAMP_RMAPEM_REQUESTS_COUNTERr */
  30123         soc_block_list[22],
  30124         soc_genreg,
  30125         1,
  30126         0,
  30127         0x20e,
  30128         SOC_REG_FLAG_RO |
  30129                           SOC_REG_FLAG_SIGNAL,
  30130         0,
  30131         2,
  30132         soc_OAMP_RMAPEM_REQUESTS_COUNTERr_fields,
  30133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30134         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30135         -1,
  30136         -1,
  30137     },
  30138 #endif /* chips */
  30139 
  30140 #if defined(BCM_88650_B0)
  30141     { /* SOC_REG_INT_OAMP_RMAPEM_REQUESTS_COUNTER_BCM88650_B0r */
  30142         soc_block_list[22],
  30143         soc_genreg,
  30144         1,
  30145         0,
  30146         0x20e,
  30147         SOC_REG_FLAG_RO |
  30148                           SOC_REG_FLAG_SIGNAL,
  30149         0,
  30150         2,
  30151         soc_OAMP_RMAPEM_REQUESTS_COUNTER_BCM88650_B0r_fields,
  30152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30153         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30154         -1,
  30155         -1,
  30156     },
  30157 #endif /* chips */
  30158 
  30159 #if defined(BCM_88660_A0)
  30160     { /* SOC_REG_INT_OAMP_RMAPEM_REQUESTS_COUNTER_BCM88660_A0r */
  30161         soc_block_list[22],
  30162         soc_genreg,
  30163         1,
  30164         0,
  30165         0x20e,
  30166         SOC_REG_FLAG_RO |
  30167                           SOC_REG_FLAG_SIGNAL,
  30168         0,
  30169         2,
  30170         soc_OAMP_RMAPEM_REQUESTS_COUNTER_BCM88660_A0r_fields,
  30171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30173         -1,
  30174         -1,
  30175     },
  30176 #endif /* chips */
  30177 
  30178 #if defined(BCM_88650_A0)
  30179     { /* SOC_REG_INT_OAMP_RMAPEM_RESET_STATUS_REGISTERr */
  30180         soc_block_list[22],
  30181         soc_genreg,
  30182         1,
  30183         0,
  30184         0x200,
  30185         SOC_REG_FLAG_RO,
  30186         0,
  30187         1,
  30188         soc_OAMP_RMAPEM_RESET_STATUS_REGISTERr_fields,
  30189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30190         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30191         -1,
  30192         -1,
  30193     },
  30194 #endif /* chips */
  30195 
  30196 #if defined(BCM_88650_B0)
  30197     { /* SOC_REG_INT_OAMP_RMAPEM_RESET_STATUS_REGISTER_BCM88650_B0r */
  30198         soc_block_list[22],
  30199         soc_genreg,
  30200         1,
  30201         0,
  30202         0x200,
  30203         SOC_REG_FLAG_RO,
  30204         0,
  30205         1,
  30206         soc_OAMP_RMAPEM_RESET_STATUS_REGISTER_BCM88650_B0r_fields,
  30207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30208         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30209         -1,
  30210         -1,
  30211     },
  30212 #endif /* chips */
  30213 
  30214 #if defined(BCM_88660_A0)
  30215     { /* SOC_REG_INT_OAMP_RMAPEM_RESET_STATUS_REGISTER_BCM88660_A0r */
  30216         soc_block_list[22],
  30217         soc_genreg,
  30218         1,
  30219         0,
  30220         0x200,
  30221         SOC_REG_FLAG_RO,
  30222         0,
  30223         1,
  30224         soc_OAMP_RMAPEM_RESET_STATUS_REGISTER_BCM88660_A0r_fields,
  30225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30226         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30227         -1,
  30228         -1,
  30229     },
  30230 #endif /* chips */
  30231 
  30232 #if defined(BCM_88470_A0)
  30233     { /* SOC_REG_INT_OAMP_RMAPEM_SER_DISABLES_MNGMNTr */
  30234         soc_block_list[22],
  30235         soc_genreg,
  30236         1,
  30237         0,
  30238         0x216,
  30239         0,
  30240         0,
  30241         1,
  30242         soc_OAMP_RMAPEM_SER_DISABLES_MNGMNTr_fields,
  30243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30244         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30245         -1,
  30246         -1,
  30247     },
  30248 #endif /* chips */
  30249 
  30250 #if defined(BCM_88270_A0)
  30251     { /* SOC_REG_INT_OAMP_RMAPEM_SER_DISABLES_MNGMNT_BCM88270_A0r */
  30252         soc_block_list[22],
  30253         soc_genreg,
  30254         1,
  30255         0,
  30256         0x216,
  30257         0,
  30258         0,
  30259         1,
  30260         soc_OAMP_RMAPEM_SER_DISABLES_MNGMNT_BCM88270_A0r_fields,
  30261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30262         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30263         -1,
  30264         -1,
  30265     },
  30266 #endif /* chips */
  30267 
  30268 #if defined(BCM_88470_B0)
  30269     { /* SOC_REG_INT_OAMP_RMAPEM_SER_DISABLES_MNGMNT_BCM88470_B0r */
  30270         soc_block_list[22],
  30271         soc_genreg,
  30272         1,
  30273         0,
  30274         0x216,
  30275         0,
  30276         0,
  30277         1,
  30278         soc_OAMP_RMAPEM_SER_DISABLES_MNGMNT_BCM88470_B0r_fields,
  30279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30280         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30281         -1,
  30282         -1,
  30283     },
  30284 #endif /* chips */
  30285 
  30286 #if defined(BCM_88650_A0)
  30287     { /* SOC_REG_INT_OAMP_RMAPEM_WARNING_INSERTED_EXISTING_COUNTERr */
  30288         soc_block_list[22],
  30289         soc_genreg,
  30290         1,
  30291         0,
  30292         0x213,
  30293         SOC_REG_FLAG_RO,
  30294         0,
  30295         2,
  30296         soc_OAMP_RMAPEM_WARNING_INSERTED_EXISTING_COUNTERr_fields,
  30297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30298         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  30299         -1,
  30300         -1,
  30301     },
  30302 #endif /* chips */
  30303 
  30304 #if defined(BCM_88650_B0)
  30305     { /* SOC_REG_INT_OAMP_RMAPEM_WARNING_INSERTED_EXISTING_COUNTER_BCM88650_B0r */
  30306         soc_block_list[22],
  30307         soc_genreg,
  30308         1,
  30309         0,
  30310         0x213,
  30311         SOC_REG_FLAG_RO,
  30312         0,
  30313         2,
  30314         soc_OAMP_RMAPEM_WARNING_INSERTED_EXISTING_COUNTER_BCM88650_B0r_fields,
  30315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30316         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  30317         -1,
  30318         -1,
  30319     },
  30320 #endif /* chips */
  30321 
  30322 #if defined(BCM_88660_A0)
  30323     { /* SOC_REG_INT_OAMP_RMAPEM_WARNING_INSERTED_EXISTING_COUNTER_BCM88660_A0r */
  30324         soc_block_list[22],
  30325         soc_genreg,
  30326         1,
  30327         0,
  30328         0x213,
  30329         SOC_REG_FLAG_RO,
  30330         0,
  30331         2,
  30332         soc_OAMP_RMAPEM_WARNING_INSERTED_EXISTING_COUNTER_BCM88660_A0r_fields,
  30333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30334         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  30335         -1,
  30336         -1,
  30337     },
  30338 #endif /* chips */
  30339 
  30340 #if defined(BCM_88690_A0)
  30341     { /* SOC_REG_INT_OAMP_RMEP_PUNT_GOOD_TIMERr */
  30342         soc_block_list[22],
  30343         soc_genreg,
  30344         7,
  30345         1,
  30346         0xb34,
  30347         SOC_REG_FLAG_ARRAY |
  30348                           SOC_REG_FLAG_REG_ARRAY,
  30349         0,
  30350         1,
  30351         soc_OAMP_RMEP_PUNT_GOOD_TIMERr_fields,
  30352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30353         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  30354         -1,
  30355         -1,
  30356     },
  30357 #endif /* chips */
  30358 
  30359 #if defined(BCM_88690_B0)
  30360     { /* SOC_REG_INT_OAMP_RMEP_PUNT_GOOD_TIMER_BCM88690_B0r */
  30361         soc_block_list[22],
  30362         soc_genreg,
  30363         7,
  30364         1,
  30365         0xb36,
  30366         SOC_REG_FLAG_ARRAY |
  30367                           SOC_REG_FLAG_REG_ARRAY,
  30368         0,
  30369         1,
  30370         soc_OAMP_RMEP_PUNT_GOOD_TIMER_BCM88690_B0r_fields,
  30371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30372         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  30373         -1,
  30374         -1,
  30375     },
  30376 #endif /* chips */
  30377 
  30378 #if defined(BCM_88470_A0)
  30379     { /* SOC_REG_INT_OAMP_RSP_PKT_COUNTERr */
  30380         soc_block_list[22],
  30381         soc_genreg,
  30382         1,
  30383         0,
  30384         0x4b2,
  30385         SOC_REG_FLAG_64_BITS,
  30386         0,
  30387         3,
  30388         soc_OAMP_RSP_PKT_COUNTERr_fields,
  30389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30390         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  30391         -1,
  30392         -1,
  30393     },
  30394 #endif /* chips */
  30395 
  30396 #if defined(BCM_88270_A0)
  30397     { /* SOC_REG_INT_OAMP_RSP_PKT_COUNTER_BCM88270_A0r */
  30398         soc_block_list[22],
  30399         soc_genreg,
  30400         1,
  30401         0,
  30402         0x4b2,
  30403         SOC_REG_FLAG_64_BITS,
  30404         0,
  30405         3,
  30406         soc_OAMP_RSP_PKT_COUNTER_BCM88270_A0r_fields,
  30407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30408         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  30409         -1,
  30410         -1,
  30411     },
  30412 #endif /* chips */
  30413 
  30414 #if defined(BCM_88470_B0)
  30415     { /* SOC_REG_INT_OAMP_RSP_PKT_COUNTER_BCM88470_B0r */
  30416         soc_block_list[22],
  30417         soc_genreg,
  30418         1,
  30419         0,
  30420         0x4b2,
  30421         SOC_REG_FLAG_64_BITS,
  30422         0,
  30423         3,
  30424         soc_OAMP_RSP_PKT_COUNTER_BCM88470_B0r_fields,
  30425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30426         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  30427         -1,
  30428         -1,
  30429     },
  30430 #endif /* chips */
  30431 
  30432 #if defined(BCM_88690_A0)
  30433     { /* SOC_REG_INT_OAMP_RSP_PKT_COUNTER_BCM88690_A0r */
  30434         soc_block_list[22],
  30435         soc_genreg,
  30436         1,
  30437         0,
  30438         0x5a3,
  30439         SOC_REG_FLAG_64_BITS,
  30440         SOC_REG_FLAG_COUNTER_FEILDS,
  30441         3,
  30442         soc_OAMP_RSP_PKT_COUNTER_BCM88690_A0r_fields,
  30443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30444         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  30445         -1,
  30446         -1,
  30447     },
  30448 #endif /* chips */
  30449 
  30450 #if defined(BCM_88690_B0)
  30451     { /* SOC_REG_INT_OAMP_RSP_PKT_COUNTER_BCM88690_B0r */
  30452         soc_block_list[22],
  30453         soc_genreg,
  30454         1,
  30455         0,
  30456         0x5a3,
  30457         SOC_REG_FLAG_64_BITS,
  30458         SOC_REG_FLAG_COUNTER_FEILDS,
  30459         3,
  30460         soc_OAMP_RSP_PKT_COUNTER_BCM88690_B0r_fields,
  30461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30462         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  30463         -1,
  30464         -1,
  30465     },
  30466 #endif /* chips */
  30467 
  30468 #if defined(BCM_88660_A0)
  30469     { /* SOC_REG_INT_OAMP_RXB_DEBUGr */
  30470         soc_block_list[22],
  30471         soc_genreg,
  30472         1,
  30473         0,
  30474         0x186,
  30475         SOC_REG_FLAG_64_BITS |
  30476                           SOC_REG_FLAG_RO,
  30477         0,
  30478         4,
  30479         soc_OAMP_RXB_DEBUGr_fields,
  30480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30481         SOC_RESET_MASK_DEC(0xffffffff, 0x000fffff)
  30482         -1,
  30483         -1,
  30484     },
  30485 #endif /* chips */
  30486 
  30487 #if defined(BCM_88270_A0)
  30488     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88270_A0r */
  30489         soc_block_list[22],
  30490         soc_genreg,
  30491         1,
  30492         0,
  30493         0x198,
  30494         SOC_REG_FLAG_RO |
  30495                           SOC_REG_FLAG_SIGNAL,
  30496         0,
  30497         3,
  30498         soc_OAMP_RXB_DEBUG_BCM88270_A0r_fields,
  30499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30500         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30501         -1,
  30502         -1,
  30503     },
  30504 #endif /* chips */
  30505 
  30506 #if defined(BCM_88375_A0)
  30507     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88375_A0r */
  30508         soc_block_list[22],
  30509         soc_genreg,
  30510         1,
  30511         0,
  30512         0x18b,
  30513         SOC_REG_FLAG_RO |
  30514                           SOC_REG_FLAG_SIGNAL,
  30515         0,
  30516         3,
  30517         soc_OAMP_RXB_DEBUG_BCM88375_A0r_fields,
  30518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30519         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30520         -1,
  30521         -1,
  30522     },
  30523 #endif /* chips */
  30524 
  30525 #if defined(BCM_88375_B0)
  30526     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88375_B0r */
  30527         soc_block_list[22],
  30528         soc_genreg,
  30529         1,
  30530         0,
  30531         0x18b,
  30532         SOC_REG_FLAG_RO |
  30533                           SOC_REG_FLAG_SIGNAL,
  30534         0,
  30535         3,
  30536         soc_OAMP_RXB_DEBUG_BCM88375_B0r_fields,
  30537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30538         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30539         -1,
  30540         -1,
  30541     },
  30542 #endif /* chips */
  30543 
  30544 #if defined(BCM_88470_A0)
  30545     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88470_A0r */
  30546         soc_block_list[22],
  30547         soc_genreg,
  30548         1,
  30549         0,
  30550         0x198,
  30551         SOC_REG_FLAG_RO |
  30552                           SOC_REG_FLAG_SIGNAL,
  30553         0,
  30554         3,
  30555         soc_OAMP_RXB_DEBUG_BCM88470_A0r_fields,
  30556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30557         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30558         -1,
  30559         -1,
  30560     },
  30561 #endif /* chips */
  30562 
  30563 #if defined(BCM_88470_B0)
  30564     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88470_B0r */
  30565         soc_block_list[22],
  30566         soc_genreg,
  30567         1,
  30568         0,
  30569         0x198,
  30570         SOC_REG_FLAG_RO |
  30571                           SOC_REG_FLAG_SIGNAL,
  30572         0,
  30573         3,
  30574         soc_OAMP_RXB_DEBUG_BCM88470_B0r_fields,
  30575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30576         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30577         -1,
  30578         -1,
  30579     },
  30580 #endif /* chips */
  30581 
  30582 #if defined(BCM_88675_A0)
  30583     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88675_A0r */
  30584         soc_block_list[22],
  30585         soc_genreg,
  30586         1,
  30587         0,
  30588         0x18b,
  30589         SOC_REG_FLAG_RO |
  30590                           SOC_REG_FLAG_SIGNAL,
  30591         0,
  30592         3,
  30593         soc_OAMP_RXB_DEBUG_BCM88675_A0r_fields,
  30594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30595         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30596         -1,
  30597         -1,
  30598     },
  30599 #endif /* chips */
  30600 
  30601 #if defined(BCM_88675_B0)
  30602     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88675_B0r */
  30603         soc_block_list[22],
  30604         soc_genreg,
  30605         1,
  30606         0,
  30607         0x18b,
  30608         SOC_REG_FLAG_RO |
  30609                           SOC_REG_FLAG_SIGNAL,
  30610         0,
  30611         3,
  30612         soc_OAMP_RXB_DEBUG_BCM88675_B0r_fields,
  30613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30614         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30615         -1,
  30616         -1,
  30617     },
  30618 #endif /* chips */
  30619 
  30620 #if defined(BCM_88680_A0)
  30621     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88680_A0r */
  30622         soc_block_list[22],
  30623         soc_genreg,
  30624         1,
  30625         0,
  30626         0x18b,
  30627         SOC_REG_FLAG_RO |
  30628                           SOC_REG_FLAG_SIGNAL,
  30629         0,
  30630         3,
  30631         soc_OAMP_RXB_DEBUG_BCM88680_A0r_fields,
  30632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30633         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30634         -1,
  30635         -1,
  30636     },
  30637 #endif /* chips */
  30638 
  30639 #if defined(BCM_88690_A0)
  30640     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88690_A0r */
  30641         soc_block_list[22],
  30642         soc_genreg,
  30643         1,
  30644         0,
  30645         0x195,
  30646         SOC_REG_FLAG_RO |
  30647                           SOC_REG_FLAG_SIGNAL,
  30648         0,
  30649         3,
  30650         soc_OAMP_RXB_DEBUG_BCM88690_A0r_fields,
  30651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30652         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30653         -1,
  30654         -1,
  30655     },
  30656 #endif /* chips */
  30657 
  30658 #if defined(BCM_88690_B0)
  30659     { /* SOC_REG_INT_OAMP_RXB_DEBUG_BCM88690_B0r */
  30660         soc_block_list[22],
  30661         soc_genreg,
  30662         1,
  30663         0,
  30664         0x195,
  30665         SOC_REG_FLAG_RO |
  30666                           SOC_REG_FLAG_SIGNAL,
  30667         0,
  30668         3,
  30669         soc_OAMP_RXB_DEBUG_BCM88690_B0r_fields,
  30670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30671         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30672         -1,
  30673         -1,
  30674     },
  30675 #endif /* chips */
  30676 
  30677 #if defined(BCM_88470_A0)
  30678     { /* SOC_REG_INT_OAMP_RXB_PKT_COUNTERr */
  30679         soc_block_list[22],
  30680         soc_genreg,
  30681         1,
  30682         0,
  30683         0x4b4,
  30684         SOC_REG_FLAG_64_BITS,
  30685         0,
  30686         4,
  30687         soc_OAMP_RXB_PKT_COUNTERr_fields,
  30688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30689         SOC_RESET_MASK_DEC(0xffffffff, 0x01ffffff)
  30690         -1,
  30691         -1,
  30692     },
  30693 #endif /* chips */
  30694 
  30695 #if defined(BCM_88270_A0)
  30696     { /* SOC_REG_INT_OAMP_RXB_PKT_COUNTER_BCM88270_A0r */
  30697         soc_block_list[22],
  30698         soc_genreg,
  30699         1,
  30700         0,
  30701         0x4b4,
  30702         SOC_REG_FLAG_64_BITS,
  30703         0,
  30704         4,
  30705         soc_OAMP_RXB_PKT_COUNTER_BCM88270_A0r_fields,
  30706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30707         SOC_RESET_MASK_DEC(0xffffffff, 0x01ffffff)
  30708         -1,
  30709         -1,
  30710     },
  30711 #endif /* chips */
  30712 
  30713 #if defined(BCM_88470_B0)
  30714     { /* SOC_REG_INT_OAMP_RXB_PKT_COUNTER_BCM88470_B0r */
  30715         soc_block_list[22],
  30716         soc_genreg,
  30717         1,
  30718         0,
  30719         0x4b4,
  30720         SOC_REG_FLAG_64_BITS,
  30721         0,
  30722         4,
  30723         soc_OAMP_RXB_PKT_COUNTER_BCM88470_B0r_fields,
  30724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30725         SOC_RESET_MASK_DEC(0xffffffff, 0x01ffffff)
  30726         -1,
  30727         -1,
  30728     },
  30729 #endif /* chips */
  30730 
  30731 #if defined(BCM_88690_A0)
  30732     { /* SOC_REG_INT_OAMP_RXB_PKT_COUNTER_BCM88690_A0r */
  30733         soc_block_list[22],
  30734         soc_genreg,
  30735         1,
  30736         0,
  30737         0x5a5,
  30738         SOC_REG_FLAG_64_BITS,
  30739         SOC_REG_FLAG_COUNTER_FEILDS,
  30740         4,
  30741         soc_OAMP_RXB_PKT_COUNTER_BCM88690_A0r_fields,
  30742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30743         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  30744         -1,
  30745         -1,
  30746     },
  30747 #endif /* chips */
  30748 
  30749 #if defined(BCM_88690_B0)
  30750     { /* SOC_REG_INT_OAMP_RXB_PKT_COUNTER_BCM88690_B0r */
  30751         soc_block_list[22],
  30752         soc_genreg,
  30753         1,
  30754         0,
  30755         0x5a5,
  30756         SOC_REG_FLAG_64_BITS,
  30757         SOC_REG_FLAG_COUNTER_FEILDS,
  30758         4,
  30759         soc_OAMP_RXB_PKT_COUNTER_BCM88690_B0r_fields,
  30760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30761         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  30762         -1,
  30763         -1,
  30764     },
  30765 #endif /* chips */
  30766 
  30767 #if defined(BCM_88470_A0)
  30768     { /* SOC_REG_INT_OAMP_RX_PKT_COUNTERr */
  30769         soc_block_list[22],
  30770         soc_genreg,
  30771         1,
  30772         0,
  30773         0x19c,
  30774         SOC_REG_FLAG_ABOVE_64_BITS,
  30775         0,
  30776         5,
  30777         soc_OAMP_RX_PKT_COUNTERr_fields,
  30778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30779         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30780         -1,
  30781         -1,
  30782     },
  30783 #endif /* chips */
  30784 
  30785 #if defined(BCM_88270_A0)
  30786     { /* SOC_REG_INT_OAMP_RX_PKT_COUNTER_BCM88270_A0r */
  30787         soc_block_list[22],
  30788         soc_genreg,
  30789         1,
  30790         0,
  30791         0x19c,
  30792         SOC_REG_FLAG_ABOVE_64_BITS,
  30793         0,
  30794         5,
  30795         soc_OAMP_RX_PKT_COUNTER_BCM88270_A0r_fields,
  30796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30797         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30798         -1,
  30799         -1,
  30800     },
  30801 #endif /* chips */
  30802 
  30803 #if defined(BCM_88470_B0)
  30804     { /* SOC_REG_INT_OAMP_RX_PKT_COUNTER_BCM88470_B0r */
  30805         soc_block_list[22],
  30806         soc_genreg,
  30807         1,
  30808         0,
  30809         0x19c,
  30810         SOC_REG_FLAG_ABOVE_64_BITS,
  30811         0,
  30812         5,
  30813         soc_OAMP_RX_PKT_COUNTER_BCM88470_B0r_fields,
  30814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30815         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30816         -1,
  30817         -1,
  30818     },
  30819 #endif /* chips */
  30820 
  30821 #if defined(BCM_88690_A0)
  30822     { /* SOC_REG_INT_OAMP_RX_PKT_COUNTER_BCM88690_A0r */
  30823         soc_block_list[22],
  30824         soc_genreg,
  30825         1,
  30826         0,
  30827         0x19a,
  30828         SOC_REG_FLAG_ABOVE_64_BITS,
  30829         SOC_REG_FLAG_COUNTER_FEILDS,
  30830         5,
  30831         soc_OAMP_RX_PKT_COUNTER_BCM88690_A0r_fields,
  30832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30833         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30834         -1,
  30835         -1,
  30836     },
  30837 #endif /* chips */
  30838 
  30839 #if defined(BCM_88690_B0)
  30840     { /* SOC_REG_INT_OAMP_RX_PKT_COUNTER_BCM88690_B0r */
  30841         soc_block_list[22],
  30842         soc_genreg,
  30843         1,
  30844         0,
  30845         0x19a,
  30846         SOC_REG_FLAG_ABOVE_64_BITS,
  30847         SOC_REG_FLAG_COUNTER_FEILDS,
  30848         5,
  30849         soc_OAMP_RX_PKT_COUNTER_BCM88690_B0r_fields,
  30850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30851         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30852         -1,
  30853         -1,
  30854     },
  30855 #endif /* chips */
  30856 
  30857 #if defined(BCM_88675_A0)
  30858     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0r */
  30859         soc_block_list[22],
  30860         soc_genreg,
  30861         1,
  30862         0,
  30863         0x6f5,
  30864         SOC_REG_FLAG_ABOVE_64_BITS |
  30865                           SOC_REG_FLAG_RO |
  30866                           SOC_REG_FLAG_SIGNAL,
  30867         0,
  30868         1,
  30869         soc_OAMP_RX_STATS_DATA_0r_fields,
  30870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30872         -1,
  30873         -1,
  30874     },
  30875 #endif /* chips */
  30876 
  30877 #if defined(BCM_88675_A0)
  30878     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1r */
  30879         soc_block_list[22],
  30880         soc_genreg,
  30881         1,
  30882         0,
  30883         0x709,
  30884         SOC_REG_FLAG_ABOVE_64_BITS |
  30885                           SOC_REG_FLAG_RO |
  30886                           SOC_REG_FLAG_SIGNAL,
  30887         0,
  30888         1,
  30889         soc_OAMP_RX_STATS_DATA_1r_fields,
  30890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30892         -1,
  30893         -1,
  30894     },
  30895 #endif /* chips */
  30896 
  30897 #if defined(BCM_88675_A0)
  30898     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2r */
  30899         soc_block_list[22],
  30900         soc_genreg,
  30901         1,
  30902         0,
  30903         0x71d,
  30904         SOC_REG_FLAG_ABOVE_64_BITS |
  30905                           SOC_REG_FLAG_RO |
  30906                           SOC_REG_FLAG_SIGNAL,
  30907         0,
  30908         1,
  30909         soc_OAMP_RX_STATS_DATA_2r_fields,
  30910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30912         -1,
  30913         -1,
  30914     },
  30915 #endif /* chips */
  30916 
  30917 #if defined(BCM_88675_A0)
  30918     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3r */
  30919         soc_block_list[22],
  30920         soc_genreg,
  30921         1,
  30922         0,
  30923         0x731,
  30924         SOC_REG_FLAG_ABOVE_64_BITS |
  30925                           SOC_REG_FLAG_RO |
  30926                           SOC_REG_FLAG_SIGNAL,
  30927         0,
  30928         1,
  30929         soc_OAMP_RX_STATS_DATA_3r_fields,
  30930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30931         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30932         -1,
  30933         -1,
  30934     },
  30935 #endif /* chips */
  30936 
  30937 #if defined(BCM_88675_A0)
  30938     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_4r */
  30939         soc_block_list[22],
  30940         soc_genreg,
  30941         1,
  30942         0,
  30943         0x745,
  30944         SOC_REG_FLAG_ABOVE_64_BITS |
  30945                           SOC_REG_FLAG_RO |
  30946                           SOC_REG_FLAG_SIGNAL,
  30947         0,
  30948         1,
  30949         soc_OAMP_RX_STATS_DATA_4r_fields,
  30950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30952         -1,
  30953         -1,
  30954     },
  30955 #endif /* chips */
  30956 
  30957 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  30958     defined(BCM_56270_A0)
  30959     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM56260_A0r */
  30960         soc_block_list[22],
  30961         soc_genreg,
  30962         1,
  30963         0,
  30964         0x2019200,
  30965         SOC_REG_FLAG_ABOVE_64_BITS |
  30966                           SOC_REG_FLAG_RO,
  30967         0,
  30968         1,
  30969         soc_OAMP_RX_STATS_DATA_0_BCM56260_A0r_fields,
  30970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30971         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30972         -1,
  30973         -1,
  30974     },
  30975 #endif /* chips */
  30976 
  30977 #if defined(BCM_88270_A0)
  30978     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM88270_A0r */
  30979         soc_block_list[22],
  30980         soc_genreg,
  30981         1,
  30982         0,
  30983         0x6f3,
  30984         SOC_REG_FLAG_ABOVE_64_BITS |
  30985                           SOC_REG_FLAG_RO |
  30986                           SOC_REG_FLAG_SIGNAL,
  30987         0,
  30988         1,
  30989         soc_OAMP_RX_STATS_DATA_0_BCM88270_A0r_fields,
  30990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30992         -1,
  30993         -1,
  30994     },
  30995 #endif /* chips */
  30996 
  30997 #if defined(BCM_88375_A0)
  30998     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM88375_A0r */
  30999         soc_block_list[22],
  31000         soc_genreg,
  31001         1,
  31002         0,
  31003         0x6f5,
  31004         SOC_REG_FLAG_ABOVE_64_BITS |
  31005                           SOC_REG_FLAG_RO |
  31006                           SOC_REG_FLAG_SIGNAL,
  31007         0,
  31008         1,
  31009         soc_OAMP_RX_STATS_DATA_0_BCM88375_A0r_fields,
  31010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31012         -1,
  31013         -1,
  31014     },
  31015 #endif /* chips */
  31016 
  31017 #if defined(BCM_88375_B0)
  31018     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM88375_B0r */
  31019         soc_block_list[22],
  31020         soc_genreg,
  31021         1,
  31022         0,
  31023         0x6f5,
  31024         SOC_REG_FLAG_ABOVE_64_BITS |
  31025                           SOC_REG_FLAG_RO |
  31026                           SOC_REG_FLAG_SIGNAL,
  31027         0,
  31028         1,
  31029         soc_OAMP_RX_STATS_DATA_0_BCM88375_B0r_fields,
  31030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31032         -1,
  31033         -1,
  31034     },
  31035 #endif /* chips */
  31036 
  31037 #if defined(BCM_88470_A0)
  31038     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM88470_A0r */
  31039         soc_block_list[22],
  31040         soc_genreg,
  31041         1,
  31042         0,
  31043         0x6f3,
  31044         SOC_REG_FLAG_ABOVE_64_BITS |
  31045                           SOC_REG_FLAG_RO |
  31046                           SOC_REG_FLAG_SIGNAL,
  31047         0,
  31048         1,
  31049         soc_OAMP_RX_STATS_DATA_0_BCM88470_A0r_fields,
  31050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31052         -1,
  31053         -1,
  31054     },
  31055 #endif /* chips */
  31056 
  31057 #if defined(BCM_88470_B0)
  31058     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM88470_B0r */
  31059         soc_block_list[22],
  31060         soc_genreg,
  31061         1,
  31062         0,
  31063         0x6f3,
  31064         SOC_REG_FLAG_ABOVE_64_BITS |
  31065                           SOC_REG_FLAG_RO |
  31066                           SOC_REG_FLAG_SIGNAL,
  31067         0,
  31068         1,
  31069         soc_OAMP_RX_STATS_DATA_0_BCM88470_B0r_fields,
  31070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31072         -1,
  31073         -1,
  31074     },
  31075 #endif /* chips */
  31076 
  31077 #if defined(BCM_88675_B0)
  31078     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM88675_B0r */
  31079         soc_block_list[22],
  31080         soc_genreg,
  31081         1,
  31082         0,
  31083         0x6f5,
  31084         SOC_REG_FLAG_ABOVE_64_BITS |
  31085                           SOC_REG_FLAG_RO |
  31086                           SOC_REG_FLAG_SIGNAL,
  31087         0,
  31088         1,
  31089         soc_OAMP_RX_STATS_DATA_0_BCM88675_B0r_fields,
  31090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31092         -1,
  31093         -1,
  31094     },
  31095 #endif /* chips */
  31096 
  31097 #if defined(BCM_88680_A0)
  31098     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM88680_A0r */
  31099         soc_block_list[22],
  31100         soc_genreg,
  31101         1,
  31102         0,
  31103         0x6f5,
  31104         SOC_REG_FLAG_ABOVE_64_BITS |
  31105                           SOC_REG_FLAG_RO |
  31106                           SOC_REG_FLAG_SIGNAL,
  31107         0,
  31108         1,
  31109         soc_OAMP_RX_STATS_DATA_0_BCM88680_A0r_fields,
  31110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31112         -1,
  31113         -1,
  31114     },
  31115 #endif /* chips */
  31116 
  31117 #if defined(BCM_88690_A0)
  31118     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM88690_A0r */
  31119         soc_block_list[22],
  31120         soc_genreg,
  31121         1,
  31122         0,
  31123         0x67f,
  31124         SOC_REG_FLAG_ABOVE_64_BITS |
  31125                           SOC_REG_FLAG_RO |
  31126                           SOC_REG_FLAG_SIGNAL,
  31127         0,
  31128         1,
  31129         soc_OAMP_RX_STATS_DATA_0_BCM88690_A0r_fields,
  31130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31131         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31132         -1,
  31133         -1,
  31134     },
  31135 #endif /* chips */
  31136 
  31137 #if defined(BCM_88690_B0)
  31138     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_0_BCM88690_B0r */
  31139         soc_block_list[22],
  31140         soc_genreg,
  31141         1,
  31142         0,
  31143         0x67f,
  31144         SOC_REG_FLAG_ABOVE_64_BITS |
  31145                           SOC_REG_FLAG_RO |
  31146                           SOC_REG_FLAG_SIGNAL,
  31147         0,
  31148         1,
  31149         soc_OAMP_RX_STATS_DATA_0_BCM88690_B0r_fields,
  31150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31151         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31152         -1,
  31153         -1,
  31154     },
  31155 #endif /* chips */
  31156 
  31157 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  31158     defined(BCM_56270_A0)
  31159     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM56260_A0r */
  31160         soc_block_list[22],
  31161         soc_genreg,
  31162         1,
  31163         0,
  31164         0x201a600,
  31165         SOC_REG_FLAG_ABOVE_64_BITS |
  31166                           SOC_REG_FLAG_RO,
  31167         0,
  31168         1,
  31169         soc_OAMP_RX_STATS_DATA_1_BCM56260_A0r_fields,
  31170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31171         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31172         -1,
  31173         -1,
  31174     },
  31175 #endif /* chips */
  31176 
  31177 #if defined(BCM_88270_A0)
  31178     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM88270_A0r */
  31179         soc_block_list[22],
  31180         soc_genreg,
  31181         1,
  31182         0,
  31183         0x707,
  31184         SOC_REG_FLAG_ABOVE_64_BITS |
  31185                           SOC_REG_FLAG_RO |
  31186                           SOC_REG_FLAG_SIGNAL,
  31187         0,
  31188         1,
  31189         soc_OAMP_RX_STATS_DATA_1_BCM88270_A0r_fields,
  31190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31192         -1,
  31193         -1,
  31194     },
  31195 #endif /* chips */
  31196 
  31197 #if defined(BCM_88375_A0)
  31198     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM88375_A0r */
  31199         soc_block_list[22],
  31200         soc_genreg,
  31201         1,
  31202         0,
  31203         0x709,
  31204         SOC_REG_FLAG_ABOVE_64_BITS |
  31205                           SOC_REG_FLAG_RO |
  31206                           SOC_REG_FLAG_SIGNAL,
  31207         0,
  31208         1,
  31209         soc_OAMP_RX_STATS_DATA_1_BCM88375_A0r_fields,
  31210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31212         -1,
  31213         -1,
  31214     },
  31215 #endif /* chips */
  31216 
  31217 #if defined(BCM_88375_B0)
  31218     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM88375_B0r */
  31219         soc_block_list[22],
  31220         soc_genreg,
  31221         1,
  31222         0,
  31223         0x709,
  31224         SOC_REG_FLAG_ABOVE_64_BITS |
  31225                           SOC_REG_FLAG_RO |
  31226                           SOC_REG_FLAG_SIGNAL,
  31227         0,
  31228         1,
  31229         soc_OAMP_RX_STATS_DATA_1_BCM88375_B0r_fields,
  31230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31232         -1,
  31233         -1,
  31234     },
  31235 #endif /* chips */
  31236 
  31237 #if defined(BCM_88470_A0)
  31238     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM88470_A0r */
  31239         soc_block_list[22],
  31240         soc_genreg,
  31241         1,
  31242         0,
  31243         0x707,
  31244         SOC_REG_FLAG_ABOVE_64_BITS |
  31245                           SOC_REG_FLAG_RO |
  31246                           SOC_REG_FLAG_SIGNAL,
  31247         0,
  31248         1,
  31249         soc_OAMP_RX_STATS_DATA_1_BCM88470_A0r_fields,
  31250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31252         -1,
  31253         -1,
  31254     },
  31255 #endif /* chips */
  31256 
  31257 #if defined(BCM_88470_B0)
  31258     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM88470_B0r */
  31259         soc_block_list[22],
  31260         soc_genreg,
  31261         1,
  31262         0,
  31263         0x707,
  31264         SOC_REG_FLAG_ABOVE_64_BITS |
  31265                           SOC_REG_FLAG_RO |
  31266                           SOC_REG_FLAG_SIGNAL,
  31267         0,
  31268         1,
  31269         soc_OAMP_RX_STATS_DATA_1_BCM88470_B0r_fields,
  31270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31272         -1,
  31273         -1,
  31274     },
  31275 #endif /* chips */
  31276 
  31277 #if defined(BCM_88675_B0)
  31278     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM88675_B0r */
  31279         soc_block_list[22],
  31280         soc_genreg,
  31281         1,
  31282         0,
  31283         0x709,
  31284         SOC_REG_FLAG_ABOVE_64_BITS |
  31285                           SOC_REG_FLAG_RO |
  31286                           SOC_REG_FLAG_SIGNAL,
  31287         0,
  31288         1,
  31289         soc_OAMP_RX_STATS_DATA_1_BCM88675_B0r_fields,
  31290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31291         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31292         -1,
  31293         -1,
  31294     },
  31295 #endif /* chips */
  31296 
  31297 #if defined(BCM_88680_A0)
  31298     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM88680_A0r */
  31299         soc_block_list[22],
  31300         soc_genreg,
  31301         1,
  31302         0,
  31303         0x709,
  31304         SOC_REG_FLAG_ABOVE_64_BITS |
  31305                           SOC_REG_FLAG_RO |
  31306                           SOC_REG_FLAG_SIGNAL,
  31307         0,
  31308         1,
  31309         soc_OAMP_RX_STATS_DATA_1_BCM88680_A0r_fields,
  31310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31312         -1,
  31313         -1,
  31314     },
  31315 #endif /* chips */
  31316 
  31317 #if defined(BCM_88690_A0)
  31318     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM88690_A0r */
  31319         soc_block_list[22],
  31320         soc_genreg,
  31321         1,
  31322         0,
  31323         0x693,
  31324         SOC_REG_FLAG_ABOVE_64_BITS |
  31325                           SOC_REG_FLAG_RO |
  31326                           SOC_REG_FLAG_SIGNAL,
  31327         0,
  31328         1,
  31329         soc_OAMP_RX_STATS_DATA_1_BCM88690_A0r_fields,
  31330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31332         -1,
  31333         -1,
  31334     },
  31335 #endif /* chips */
  31336 
  31337 #if defined(BCM_88690_B0)
  31338     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_1_BCM88690_B0r */
  31339         soc_block_list[22],
  31340         soc_genreg,
  31341         1,
  31342         0,
  31343         0x693,
  31344         SOC_REG_FLAG_ABOVE_64_BITS |
  31345                           SOC_REG_FLAG_RO |
  31346                           SOC_REG_FLAG_SIGNAL,
  31347         0,
  31348         1,
  31349         soc_OAMP_RX_STATS_DATA_1_BCM88690_B0r_fields,
  31350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31351         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31352         -1,
  31353         -1,
  31354     },
  31355 #endif /* chips */
  31356 
  31357 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  31358     defined(BCM_56270_A0)
  31359     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM56260_A0r */
  31360         soc_block_list[22],
  31361         soc_genreg,
  31362         1,
  31363         0,
  31364         0x201ba00,
  31365         SOC_REG_FLAG_ABOVE_64_BITS |
  31366                           SOC_REG_FLAG_RO,
  31367         0,
  31368         1,
  31369         soc_OAMP_RX_STATS_DATA_2_BCM56260_A0r_fields,
  31370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31372         -1,
  31373         -1,
  31374     },
  31375 #endif /* chips */
  31376 
  31377 #if defined(BCM_88270_A0)
  31378     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM88270_A0r */
  31379         soc_block_list[22],
  31380         soc_genreg,
  31381         1,
  31382         0,
  31383         0x71b,
  31384         SOC_REG_FLAG_ABOVE_64_BITS |
  31385                           SOC_REG_FLAG_RO |
  31386                           SOC_REG_FLAG_SIGNAL,
  31387         0,
  31388         1,
  31389         soc_OAMP_RX_STATS_DATA_2_BCM88270_A0r_fields,
  31390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31391         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31392         -1,
  31393         -1,
  31394     },
  31395 #endif /* chips */
  31396 
  31397 #if defined(BCM_88375_A0)
  31398     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM88375_A0r */
  31399         soc_block_list[22],
  31400         soc_genreg,
  31401         1,
  31402         0,
  31403         0x71d,
  31404         SOC_REG_FLAG_ABOVE_64_BITS |
  31405                           SOC_REG_FLAG_RO |
  31406                           SOC_REG_FLAG_SIGNAL,
  31407         0,
  31408         1,
  31409         soc_OAMP_RX_STATS_DATA_2_BCM88375_A0r_fields,
  31410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31411         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31412         -1,
  31413         -1,
  31414     },
  31415 #endif /* chips */
  31416 
  31417 #if defined(BCM_88375_B0)
  31418     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM88375_B0r */
  31419         soc_block_list[22],
  31420         soc_genreg,
  31421         1,
  31422         0,
  31423         0x71d,
  31424         SOC_REG_FLAG_ABOVE_64_BITS |
  31425                           SOC_REG_FLAG_RO |
  31426                           SOC_REG_FLAG_SIGNAL,
  31427         0,
  31428         1,
  31429         soc_OAMP_RX_STATS_DATA_2_BCM88375_B0r_fields,
  31430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31431         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31432         -1,
  31433         -1,
  31434     },
  31435 #endif /* chips */
  31436 
  31437 #if defined(BCM_88470_A0)
  31438     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM88470_A0r */
  31439         soc_block_list[22],
  31440         soc_genreg,
  31441         1,
  31442         0,
  31443         0x71b,
  31444         SOC_REG_FLAG_ABOVE_64_BITS |
  31445                           SOC_REG_FLAG_RO |
  31446                           SOC_REG_FLAG_SIGNAL,
  31447         0,
  31448         1,
  31449         soc_OAMP_RX_STATS_DATA_2_BCM88470_A0r_fields,
  31450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31451         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31452         -1,
  31453         -1,
  31454     },
  31455 #endif /* chips */
  31456 
  31457 #if defined(BCM_88470_B0)
  31458     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM88470_B0r */
  31459         soc_block_list[22],
  31460         soc_genreg,
  31461         1,
  31462         0,
  31463         0x71b,
  31464         SOC_REG_FLAG_ABOVE_64_BITS |
  31465                           SOC_REG_FLAG_RO |
  31466                           SOC_REG_FLAG_SIGNAL,
  31467         0,
  31468         1,
  31469         soc_OAMP_RX_STATS_DATA_2_BCM88470_B0r_fields,
  31470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31472         -1,
  31473         -1,
  31474     },
  31475 #endif /* chips */
  31476 
  31477 #if defined(BCM_88675_B0)
  31478     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM88675_B0r */
  31479         soc_block_list[22],
  31480         soc_genreg,
  31481         1,
  31482         0,
  31483         0x71d,
  31484         SOC_REG_FLAG_ABOVE_64_BITS |
  31485                           SOC_REG_FLAG_RO |
  31486                           SOC_REG_FLAG_SIGNAL,
  31487         0,
  31488         1,
  31489         soc_OAMP_RX_STATS_DATA_2_BCM88675_B0r_fields,
  31490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31491         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31492         -1,
  31493         -1,
  31494     },
  31495 #endif /* chips */
  31496 
  31497 #if defined(BCM_88680_A0)
  31498     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM88680_A0r */
  31499         soc_block_list[22],
  31500         soc_genreg,
  31501         1,
  31502         0,
  31503         0x71d,
  31504         SOC_REG_FLAG_ABOVE_64_BITS |
  31505                           SOC_REG_FLAG_RO |
  31506                           SOC_REG_FLAG_SIGNAL,
  31507         0,
  31508         1,
  31509         soc_OAMP_RX_STATS_DATA_2_BCM88680_A0r_fields,
  31510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31511         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31512         -1,
  31513         -1,
  31514     },
  31515 #endif /* chips */
  31516 
  31517 #if defined(BCM_88690_A0)
  31518     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM88690_A0r */
  31519         soc_block_list[22],
  31520         soc_genreg,
  31521         1,
  31522         0,
  31523         0x6a7,
  31524         SOC_REG_FLAG_ABOVE_64_BITS |
  31525                           SOC_REG_FLAG_RO |
  31526                           SOC_REG_FLAG_SIGNAL,
  31527         0,
  31528         1,
  31529         soc_OAMP_RX_STATS_DATA_2_BCM88690_A0r_fields,
  31530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31531         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31532         -1,
  31533         -1,
  31534     },
  31535 #endif /* chips */
  31536 
  31537 #if defined(BCM_88690_B0)
  31538     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_2_BCM88690_B0r */
  31539         soc_block_list[22],
  31540         soc_genreg,
  31541         1,
  31542         0,
  31543         0x6a7,
  31544         SOC_REG_FLAG_ABOVE_64_BITS |
  31545                           SOC_REG_FLAG_RO |
  31546                           SOC_REG_FLAG_SIGNAL,
  31547         0,
  31548         1,
  31549         soc_OAMP_RX_STATS_DATA_2_BCM88690_B0r_fields,
  31550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31551         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31552         -1,
  31553         -1,
  31554     },
  31555 #endif /* chips */
  31556 
  31557 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  31558     defined(BCM_56270_A0)
  31559     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM56260_A0r */
  31560         soc_block_list[22],
  31561         soc_genreg,
  31562         1,
  31563         0,
  31564         0x201ce00,
  31565         SOC_REG_FLAG_ABOVE_64_BITS |
  31566                           SOC_REG_FLAG_RO,
  31567         0,
  31568         1,
  31569         soc_OAMP_RX_STATS_DATA_3_BCM56260_A0r_fields,
  31570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31572         -1,
  31573         -1,
  31574     },
  31575 #endif /* chips */
  31576 
  31577 #if defined(BCM_88270_A0)
  31578     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM88270_A0r */
  31579         soc_block_list[22],
  31580         soc_genreg,
  31581         1,
  31582         0,
  31583         0x72f,
  31584         SOC_REG_FLAG_ABOVE_64_BITS |
  31585                           SOC_REG_FLAG_RO |
  31586                           SOC_REG_FLAG_SIGNAL,
  31587         0,
  31588         1,
  31589         soc_OAMP_RX_STATS_DATA_3_BCM88270_A0r_fields,
  31590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31592         -1,
  31593         -1,
  31594     },
  31595 #endif /* chips */
  31596 
  31597 #if defined(BCM_88375_A0)
  31598     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM88375_A0r */
  31599         soc_block_list[22],
  31600         soc_genreg,
  31601         1,
  31602         0,
  31603         0x731,
  31604         SOC_REG_FLAG_ABOVE_64_BITS |
  31605                           SOC_REG_FLAG_RO |
  31606                           SOC_REG_FLAG_SIGNAL,
  31607         0,
  31608         1,
  31609         soc_OAMP_RX_STATS_DATA_3_BCM88375_A0r_fields,
  31610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31612         -1,
  31613         -1,
  31614     },
  31615 #endif /* chips */
  31616 
  31617 #if defined(BCM_88375_B0)
  31618     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM88375_B0r */
  31619         soc_block_list[22],
  31620         soc_genreg,
  31621         1,
  31622         0,
  31623         0x731,
  31624         SOC_REG_FLAG_ABOVE_64_BITS |
  31625                           SOC_REG_FLAG_RO |
  31626                           SOC_REG_FLAG_SIGNAL,
  31627         0,
  31628         1,
  31629         soc_OAMP_RX_STATS_DATA_3_BCM88375_B0r_fields,
  31630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31632         -1,
  31633         -1,
  31634     },
  31635 #endif /* chips */
  31636 
  31637 #if defined(BCM_88470_A0)
  31638     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM88470_A0r */
  31639         soc_block_list[22],
  31640         soc_genreg,
  31641         1,
  31642         0,
  31643         0x72f,
  31644         SOC_REG_FLAG_ABOVE_64_BITS |
  31645                           SOC_REG_FLAG_RO |
  31646                           SOC_REG_FLAG_SIGNAL,
  31647         0,
  31648         1,
  31649         soc_OAMP_RX_STATS_DATA_3_BCM88470_A0r_fields,
  31650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31652         -1,
  31653         -1,
  31654     },
  31655 #endif /* chips */
  31656 
  31657 #if defined(BCM_88470_B0)
  31658     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM88470_B0r */
  31659         soc_block_list[22],
  31660         soc_genreg,
  31661         1,
  31662         0,
  31663         0x72f,
  31664         SOC_REG_FLAG_ABOVE_64_BITS |
  31665                           SOC_REG_FLAG_RO |
  31666                           SOC_REG_FLAG_SIGNAL,
  31667         0,
  31668         1,
  31669         soc_OAMP_RX_STATS_DATA_3_BCM88470_B0r_fields,
  31670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31671         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31672         -1,
  31673         -1,
  31674     },
  31675 #endif /* chips */
  31676 
  31677 #if defined(BCM_88675_B0)
  31678     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM88675_B0r */
  31679         soc_block_list[22],
  31680         soc_genreg,
  31681         1,
  31682         0,
  31683         0x731,
  31684         SOC_REG_FLAG_ABOVE_64_BITS |
  31685                           SOC_REG_FLAG_RO |
  31686                           SOC_REG_FLAG_SIGNAL,
  31687         0,
  31688         1,
  31689         soc_OAMP_RX_STATS_DATA_3_BCM88675_B0r_fields,
  31690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31692         -1,
  31693         -1,
  31694     },
  31695 #endif /* chips */
  31696 
  31697 #if defined(BCM_88680_A0)
  31698     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM88680_A0r */
  31699         soc_block_list[22],
  31700         soc_genreg,
  31701         1,
  31702         0,
  31703         0x731,
  31704         SOC_REG_FLAG_ABOVE_64_BITS |
  31705                           SOC_REG_FLAG_RO |
  31706                           SOC_REG_FLAG_SIGNAL,
  31707         0,
  31708         1,
  31709         soc_OAMP_RX_STATS_DATA_3_BCM88680_A0r_fields,
  31710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31711         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31712         -1,
  31713         -1,
  31714     },
  31715 #endif /* chips */
  31716 
  31717 #if defined(BCM_88690_A0)
  31718     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM88690_A0r */
  31719         soc_block_list[22],
  31720         soc_genreg,
  31721         1,
  31722         0,
  31723         0x6bb,
  31724         SOC_REG_FLAG_ABOVE_64_BITS |
  31725                           SOC_REG_FLAG_RO |
  31726                           SOC_REG_FLAG_SIGNAL,
  31727         0,
  31728         1,
  31729         soc_OAMP_RX_STATS_DATA_3_BCM88690_A0r_fields,
  31730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31731         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31732         -1,
  31733         -1,
  31734     },
  31735 #endif /* chips */
  31736 
  31737 #if defined(BCM_88690_B0)
  31738     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_3_BCM88690_B0r */
  31739         soc_block_list[22],
  31740         soc_genreg,
  31741         1,
  31742         0,
  31743         0x6bb,
  31744         SOC_REG_FLAG_ABOVE_64_BITS |
  31745                           SOC_REG_FLAG_RO |
  31746                           SOC_REG_FLAG_SIGNAL,
  31747         0,
  31748         1,
  31749         soc_OAMP_RX_STATS_DATA_3_BCM88690_B0r_fields,
  31750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31751         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31752         -1,
  31753         -1,
  31754     },
  31755 #endif /* chips */
  31756 
  31757 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  31758     defined(BCM_56270_A0)
  31759     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_4_BCM56260_A0r */
  31760         soc_block_list[22],
  31761         soc_genreg,
  31762         1,
  31763         0,
  31764         0x201e200,
  31765         SOC_REG_FLAG_ABOVE_64_BITS |
  31766                           SOC_REG_FLAG_RO,
  31767         0,
  31768         1,
  31769         soc_OAMP_RX_STATS_DATA_4_BCM56260_A0r_fields,
  31770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31772         -1,
  31773         -1,
  31774     },
  31775 #endif /* chips */
  31776 
  31777 #if defined(BCM_88270_A0)
  31778     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_4_BCM88270_A0r */
  31779         soc_block_list[22],
  31780         soc_genreg,
  31781         1,
  31782         0,
  31783         0x743,
  31784         SOC_REG_FLAG_ABOVE_64_BITS |
  31785                           SOC_REG_FLAG_RO |
  31786                           SOC_REG_FLAG_SIGNAL,
  31787         0,
  31788         1,
  31789         soc_OAMP_RX_STATS_DATA_4_BCM88270_A0r_fields,
  31790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31792         -1,
  31793         -1,
  31794     },
  31795 #endif /* chips */
  31796 
  31797 #if defined(BCM_88375_A0)
  31798     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_4_BCM88375_A0r */
  31799         soc_block_list[22],
  31800         soc_genreg,
  31801         1,
  31802         0,
  31803         0x745,
  31804         SOC_REG_FLAG_ABOVE_64_BITS |
  31805                           SOC_REG_FLAG_RO |
  31806                           SOC_REG_FLAG_SIGNAL,
  31807         0,
  31808         1,
  31809         soc_OAMP_RX_STATS_DATA_4_BCM88375_A0r_fields,
  31810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31811         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31812         -1,
  31813         -1,
  31814     },
  31815 #endif /* chips */
  31816 
  31817 #if defined(BCM_88375_B0)
  31818     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_4_BCM88375_B0r */
  31819         soc_block_list[22],
  31820         soc_genreg,
  31821         1,
  31822         0,
  31823         0x745,
  31824         SOC_REG_FLAG_ABOVE_64_BITS |
  31825                           SOC_REG_FLAG_RO |
  31826                           SOC_REG_FLAG_SIGNAL,
  31827         0,
  31828         1,
  31829         soc_OAMP_RX_STATS_DATA_4_BCM88375_B0r_fields,
  31830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31832         -1,
  31833         -1,
  31834     },
  31835 #endif /* chips */
  31836 
  31837 #if defined(BCM_88470_A0)
  31838     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_4_BCM88470_A0r */
  31839         soc_block_list[22],
  31840         soc_genreg,
  31841         1,
  31842         0,
  31843         0x743,
  31844         SOC_REG_FLAG_ABOVE_64_BITS |
  31845                           SOC_REG_FLAG_RO |
  31846                           SOC_REG_FLAG_SIGNAL,
  31847         0,
  31848         1,
  31849         soc_OAMP_RX_STATS_DATA_4_BCM88470_A0r_fields,
  31850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31851         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31852         -1,
  31853         -1,
  31854     },
  31855 #endif /* chips */
  31856 
  31857 #if defined(BCM_88470_B0)
  31858     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_4_BCM88470_B0r */
  31859         soc_block_list[22],
  31860         soc_genreg,
  31861         1,
  31862         0,
  31863         0x743,
  31864         SOC_REG_FLAG_ABOVE_64_BITS |
  31865                           SOC_REG_FLAG_RO |
  31866                           SOC_REG_FLAG_SIGNAL,
  31867         0,
  31868         1,
  31869         soc_OAMP_RX_STATS_DATA_4_BCM88470_B0r_fields,
  31870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31872         -1,
  31873         -1,
  31874     },
  31875 #endif /* chips */
  31876 
  31877 #if defined(BCM_88675_B0)
  31878     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_4_BCM88675_B0r */
  31879         soc_block_list[22],
  31880         soc_genreg,
  31881         1,
  31882         0,
  31883         0x745,
  31884         SOC_REG_FLAG_ABOVE_64_BITS |
  31885                           SOC_REG_FLAG_RO |
  31886                           SOC_REG_FLAG_SIGNAL,
  31887         0,
  31888         1,
  31889         soc_OAMP_RX_STATS_DATA_4_BCM88675_B0r_fields,
  31890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31892         -1,
  31893         -1,
  31894     },
  31895 #endif /* chips */
  31896 
  31897 #if defined(BCM_88680_A0)
  31898     { /* SOC_REG_INT_OAMP_RX_STATS_DATA_4_BCM88680_A0r */
  31899         soc_block_list[22],
  31900         soc_genreg,
  31901         1,
  31902         0,
  31903         0x745,
  31904         SOC_REG_FLAG_ABOVE_64_BITS |
  31905                           SOC_REG_FLAG_RO |
  31906                           SOC_REG_FLAG_SIGNAL,
  31907         0,
  31908         1,
  31909         soc_OAMP_RX_STATS_DATA_4_BCM88680_A0r_fields,
  31910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31912         -1,
  31913         -1,
  31914     },
  31915 #endif /* chips */
  31916 
  31917 #if defined(BCM_88660_A0)
  31918     { /* SOC_REG_INT_OAMP_RX_TRAP_CODESr */
  31919         soc_block_list[22],
  31920         soc_genreg,
  31921         4,
  31922         0,
  31923         0x188,
  31924         SOC_REG_FLAG_64_BITS |
  31925                           SOC_REG_FLAG_ARRAY |
  31926                           SOC_REG_FLAG_REG_ARRAY |
  31927                           SOC_REG_FLAG_SIGNAL,
  31928         0,
  31929         8,
  31930         soc_OAMP_RX_TRAP_CODESr_fields,
  31931         SOC_RESET_VAL_DEC(0xe3e2e1e0, 0xe7e6e5e4)
  31932         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  31933         -1,
  31934         -1,
  31935     },
  31936 #endif /* chips */
  31937 
  31938 #if defined(BCM_88375_A0)
  31939     { /* SOC_REG_INT_OAMP_RX_TRAP_CODES_BCM88375_A0r */
  31940         soc_block_list[22],
  31941         soc_genreg,
  31942         4,
  31943         0,
  31944         0x18c,
  31945         SOC_REG_FLAG_64_BITS |
  31946                           SOC_REG_FLAG_ARRAY |
  31947                           SOC_REG_FLAG_REG_ARRAY,
  31948         0,
  31949         8,
  31950         soc_OAMP_RX_TRAP_CODES_BCM88375_A0r_fields,
  31951         SOC_RESET_VAL_DEC(0xe3e2e1e0, 0xe7e6e5e4)
  31952         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  31953         -1,
  31954         -1,
  31955     },
  31956 #endif /* chips */
  31957 
  31958 #if defined(BCM_88375_B0)
  31959     { /* SOC_REG_INT_OAMP_RX_TRAP_CODES_BCM88375_B0r */
  31960         soc_block_list[22],
  31961         soc_genreg,
  31962         4,
  31963         0,
  31964         0x18c,
  31965         SOC_REG_FLAG_64_BITS |
  31966                           SOC_REG_FLAG_ARRAY |
  31967                           SOC_REG_FLAG_REG_ARRAY,
  31968         0,
  31969         8,
  31970         soc_OAMP_RX_TRAP_CODES_BCM88375_B0r_fields,
  31971         SOC_RESET_VAL_DEC(0xe3e2e1e0, 0xe7e6e5e4)
  31972         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  31973         -1,
  31974         -1,
  31975     },
  31976 #endif /* chips */
  31977 
  31978 #if defined(BCM_88675_A0)
  31979     { /* SOC_REG_INT_OAMP_RX_TRAP_CODES_BCM88675_A0r */
  31980         soc_block_list[22],
  31981         soc_genreg,
  31982         4,
  31983         0,
  31984         0x18c,
  31985         SOC_REG_FLAG_64_BITS |
  31986                           SOC_REG_FLAG_ARRAY |
  31987                           SOC_REG_FLAG_REG_ARRAY,
  31988         0,
  31989         8,
  31990         soc_OAMP_RX_TRAP_CODES_BCM88675_A0r_fields,
  31991         SOC_RESET_VAL_DEC(0xe3e2e1e0, 0xe7e6e5e4)
  31992         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  31993         -1,
  31994         -1,
  31995     },
  31996 #endif /* chips */
  31997 
  31998 #if defined(BCM_88675_B0)
  31999     { /* SOC_REG_INT_OAMP_RX_TRAP_CODES_BCM88675_B0r */
  32000         soc_block_list[22],
  32001         soc_genreg,
  32002         4,
  32003         0,
  32004         0x18c,
  32005         SOC_REG_FLAG_64_BITS |
  32006                           SOC_REG_FLAG_ARRAY |
  32007                           SOC_REG_FLAG_REG_ARRAY,
  32008         0,
  32009         8,
  32010         soc_OAMP_RX_TRAP_CODES_BCM88675_B0r_fields,
  32011         SOC_RESET_VAL_DEC(0xe3e2e1e0, 0xe7e6e5e4)
  32012         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  32013         -1,
  32014         -1,
  32015     },
  32016 #endif /* chips */
  32017 
  32018 #if defined(BCM_88680_A0)
  32019     { /* SOC_REG_INT_OAMP_RX_TRAP_CODES_BCM88680_A0r */
  32020         soc_block_list[22],
  32021         soc_genreg,
  32022         4,
  32023         0,
  32024         0x18c,
  32025         SOC_REG_FLAG_64_BITS |
  32026                           SOC_REG_FLAG_ARRAY |
  32027                           SOC_REG_FLAG_REG_ARRAY,
  32028         0,
  32029         8,
  32030         soc_OAMP_RX_TRAP_CODES_BCM88680_A0r_fields,
  32031         SOC_RESET_VAL_DEC(0xe3e2e1e0, 0xe7e6e5e4)
  32032         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  32033         -1,
  32034         -1,
  32035     },
  32036 #endif /* chips */
  32037 
  32038 #if defined(BCM_88690_A0)
  32039     { /* SOC_REG_INT_OAMP_R_MEP_DB_FULL_ENTRY_THRESHOLDr */
  32040         soc_block_list[22],
  32041         soc_genreg,
  32042         1,
  32043         0,
  32044         0xb2a,
  32045         0,
  32046         0,
  32047         1,
  32048         soc_OAMP_R_MEP_DB_FULL_ENTRY_THRESHOLDr_fields,
  32049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32050         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  32051         -1,
  32052         -1,
  32053     },
  32054 #endif /* chips */
  32055 
  32056 #if defined(BCM_88690_B0)
  32057     { /* SOC_REG_INT_OAMP_R_MEP_DB_FULL_ENTRY_THRESHOLD_BCM88690_B0r */
  32058         soc_block_list[22],
  32059         soc_genreg,
  32060         1,
  32061         0,
  32062         0xb2b,
  32063         0,
  32064         0,
  32065         1,
  32066         soc_OAMP_R_MEP_DB_FULL_ENTRY_THRESHOLD_BCM88690_B0r_fields,
  32067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32068         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  32069         -1,
  32070         -1,
  32071     },
  32072 #endif /* chips */
  32073 
  32074 #if defined(BCM_88675_A0)
  32075     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROLr */
  32076         soc_block_list[22],
  32077         soc_genreg,
  32078         8,
  32079         0,
  32080         0x7d9,
  32081         SOC_REG_FLAG_ABOVE_64_BITS |
  32082                           SOC_REG_FLAG_ARRAY |
  32083                           SOC_REG_FLAG_REG_ARRAY,
  32084         0,
  32085         9,
  32086         soc_OAMP_SAT_EVC_RATE_CONTROLr_fields,
  32087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32088         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32089         -1,
  32090         -1,
  32091     },
  32092 #endif /* chips */
  32093 
  32094 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  32095     defined(BCM_56270_A0)
  32096     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM56260_A0r */
  32097         soc_block_list[22],
  32098         soc_genreg,
  32099         8,
  32100         0,
  32101         0x2027600,
  32102         SOC_REG_FLAG_ABOVE_64_BITS |
  32103                           SOC_REG_FLAG_ARRAY |
  32104                           SOC_REG_FLAG_REG_ARRAY,
  32105         0,
  32106         9,
  32107         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM56260_A0r_fields,
  32108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32110         -1,
  32111         -1,
  32112     },
  32113 #endif /* chips */
  32114 
  32115 #if defined(BCM_88270_A0)
  32116     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM88270_A0r */
  32117         soc_block_list[22],
  32118         soc_genreg,
  32119         8,
  32120         0,
  32121         0x7d7,
  32122         SOC_REG_FLAG_ABOVE_64_BITS |
  32123                           SOC_REG_FLAG_ARRAY |
  32124                           SOC_REG_FLAG_REG_ARRAY,
  32125         0,
  32126         9,
  32127         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM88270_A0r_fields,
  32128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32129         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32130         -1,
  32131         -1,
  32132     },
  32133 #endif /* chips */
  32134 
  32135 #if defined(BCM_88375_A0)
  32136     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM88375_A0r */
  32137         soc_block_list[22],
  32138         soc_genreg,
  32139         8,
  32140         0,
  32141         0x7d9,
  32142         SOC_REG_FLAG_ABOVE_64_BITS |
  32143                           SOC_REG_FLAG_ARRAY |
  32144                           SOC_REG_FLAG_REG_ARRAY,
  32145         0,
  32146         9,
  32147         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM88375_A0r_fields,
  32148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32150         -1,
  32151         -1,
  32152     },
  32153 #endif /* chips */
  32154 
  32155 #if defined(BCM_88375_B0)
  32156     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM88375_B0r */
  32157         soc_block_list[22],
  32158         soc_genreg,
  32159         8,
  32160         0,
  32161         0x7d9,
  32162         SOC_REG_FLAG_ABOVE_64_BITS |
  32163                           SOC_REG_FLAG_ARRAY |
  32164                           SOC_REG_FLAG_REG_ARRAY,
  32165         0,
  32166         9,
  32167         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM88375_B0r_fields,
  32168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32169         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32170         -1,
  32171         -1,
  32172     },
  32173 #endif /* chips */
  32174 
  32175 #if defined(BCM_88470_A0)
  32176     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM88470_A0r */
  32177         soc_block_list[22],
  32178         soc_genreg,
  32179         8,
  32180         0,
  32181         0x7d7,
  32182         SOC_REG_FLAG_ABOVE_64_BITS |
  32183                           SOC_REG_FLAG_ARRAY |
  32184                           SOC_REG_FLAG_REG_ARRAY,
  32185         0,
  32186         9,
  32187         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM88470_A0r_fields,
  32188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32189         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32190         -1,
  32191         -1,
  32192     },
  32193 #endif /* chips */
  32194 
  32195 #if defined(BCM_88470_B0)
  32196     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM88470_B0r */
  32197         soc_block_list[22],
  32198         soc_genreg,
  32199         8,
  32200         0,
  32201         0x7d7,
  32202         SOC_REG_FLAG_ABOVE_64_BITS |
  32203                           SOC_REG_FLAG_ARRAY |
  32204                           SOC_REG_FLAG_REG_ARRAY,
  32205         0,
  32206         9,
  32207         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM88470_B0r_fields,
  32208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32209         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32210         -1,
  32211         -1,
  32212     },
  32213 #endif /* chips */
  32214 
  32215 #if defined(BCM_88675_B0)
  32216     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM88675_B0r */
  32217         soc_block_list[22],
  32218         soc_genreg,
  32219         8,
  32220         0,
  32221         0x7d9,
  32222         SOC_REG_FLAG_ABOVE_64_BITS |
  32223                           SOC_REG_FLAG_ARRAY |
  32224                           SOC_REG_FLAG_REG_ARRAY,
  32225         0,
  32226         9,
  32227         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM88675_B0r_fields,
  32228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32229         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32230         -1,
  32231         -1,
  32232     },
  32233 #endif /* chips */
  32234 
  32235 #if defined(BCM_88680_A0)
  32236     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM88680_A0r */
  32237         soc_block_list[22],
  32238         soc_genreg,
  32239         8,
  32240         0,
  32241         0x7d9,
  32242         SOC_REG_FLAG_ABOVE_64_BITS |
  32243                           SOC_REG_FLAG_ARRAY |
  32244                           SOC_REG_FLAG_REG_ARRAY,
  32245         0,
  32246         9,
  32247         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM88680_A0r_fields,
  32248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32250         -1,
  32251         -1,
  32252     },
  32253 #endif /* chips */
  32254 
  32255 #if defined(BCM_88690_A0)
  32256     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM88690_A0r */
  32257         soc_block_list[22],
  32258         soc_genreg,
  32259         8,
  32260         0,
  32261         0x6cf,
  32262         SOC_REG_FLAG_ABOVE_64_BITS |
  32263                           SOC_REG_FLAG_ARRAY |
  32264                           SOC_REG_FLAG_REG_ARRAY,
  32265         0,
  32266         10,
  32267         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM88690_A0r_fields,
  32268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32269         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32270         -1,
  32271         -1,
  32272     },
  32273 #endif /* chips */
  32274 
  32275 #if defined(BCM_88690_B0)
  32276     { /* SOC_REG_INT_OAMP_SAT_EVC_RATE_CONTROL_BCM88690_B0r */
  32277         soc_block_list[22],
  32278         soc_genreg,
  32279         8,
  32280         0,
  32281         0x6cf,
  32282         SOC_REG_FLAG_ABOVE_64_BITS |
  32283                           SOC_REG_FLAG_ARRAY |
  32284                           SOC_REG_FLAG_REG_ARRAY,
  32285         0,
  32286         10,
  32287         soc_OAMP_SAT_EVC_RATE_CONTROL_BCM88690_B0r_fields,
  32288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32289         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32290         -1,
  32291         -1,
  32292     },
  32293 #endif /* chips */
  32294 
  32295 #if defined(BCM_88675_A0)
  32296     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIGr */
  32297         soc_block_list[22],
  32298         soc_genreg,
  32299         1,
  32300         0,
  32301         0x6e7,
  32302         SOC_REG_FLAG_64_BITS,
  32303         0,
  32304         8,
  32305         soc_OAMP_SAT_GEN_CONFIGr_fields,
  32306         SOC_RESET_VAL_DEC(0xffe0000f, 0x001fffff)
  32307         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
  32308         -1,
  32309         -1,
  32310     },
  32311 #endif /* chips */
  32312 
  32313 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  32314     defined(BCM_56270_A0)
  32315     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM56260_A0r */
  32316         soc_block_list[22],
  32317         soc_genreg,
  32318         1,
  32319         0,
  32320         0x2018400,
  32321         SOC_REG_FLAG_64_BITS,
  32322         0,
  32323         8,
  32324         soc_OAMP_SAT_GEN_CONFIG_BCM56260_A0r_fields,
  32325         SOC_RESET_VAL_DEC(0xffe0000f, 0x001fffff)
  32326         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
  32327         -1,
  32328         -1,
  32329     },
  32330 #endif /* chips */
  32331 
  32332 #if defined(BCM_88270_A0)
  32333     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM88270_A0r */
  32334         soc_block_list[22],
  32335         soc_genreg,
  32336         1,
  32337         0,
  32338         0x6e5,
  32339         SOC_REG_FLAG_64_BITS,
  32340         0,
  32341         7,
  32342         soc_OAMP_SAT_GEN_CONFIG_BCM88270_A0r_fields,
  32343         SOC_RESET_VAL_DEC(0xffe0000f, 0x001fffff)
  32344         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  32345         -1,
  32346         -1,
  32347     },
  32348 #endif /* chips */
  32349 
  32350 #if defined(BCM_88375_A0)
  32351     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM88375_A0r */
  32352         soc_block_list[22],
  32353         soc_genreg,
  32354         1,
  32355         0,
  32356         0x6e7,
  32357         SOC_REG_FLAG_64_BITS,
  32358         0,
  32359         8,
  32360         soc_OAMP_SAT_GEN_CONFIG_BCM88375_A0r_fields,
  32361         SOC_RESET_VAL_DEC(0xffe0000f, 0x001fffff)
  32362         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
  32363         -1,
  32364         -1,
  32365     },
  32366 #endif /* chips */
  32367 
  32368 #if defined(BCM_88375_B0)
  32369     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM88375_B0r */
  32370         soc_block_list[22],
  32371         soc_genreg,
  32372         1,
  32373         0,
  32374         0x6e7,
  32375         SOC_REG_FLAG_64_BITS,
  32376         0,
  32377         8,
  32378         soc_OAMP_SAT_GEN_CONFIG_BCM88375_B0r_fields,
  32379         SOC_RESET_VAL_DEC(0xffe0000f, 0x001fffff)
  32380         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
  32381         -1,
  32382         -1,
  32383     },
  32384 #endif /* chips */
  32385 
  32386 #if defined(BCM_88470_A0)
  32387     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM88470_A0r */
  32388         soc_block_list[22],
  32389         soc_genreg,
  32390         1,
  32391         0,
  32392         0x6e5,
  32393         SOC_REG_FLAG_64_BITS,
  32394         0,
  32395         7,
  32396         soc_OAMP_SAT_GEN_CONFIG_BCM88470_A0r_fields,
  32397         SOC_RESET_VAL_DEC(0xffe0000f, 0x001fffff)
  32398         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  32399         -1,
  32400         -1,
  32401     },
  32402 #endif /* chips */
  32403 
  32404 #if defined(BCM_88470_B0)
  32405     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM88470_B0r */
  32406         soc_block_list[22],
  32407         soc_genreg,
  32408         1,
  32409         0,
  32410         0x6e5,
  32411         SOC_REG_FLAG_64_BITS,
  32412         0,
  32413         7,
  32414         soc_OAMP_SAT_GEN_CONFIG_BCM88470_B0r_fields,
  32415         SOC_RESET_VAL_DEC(0xffe0000f, 0x001fffff)
  32416         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  32417         -1,
  32418         -1,
  32419     },
  32420 #endif /* chips */
  32421 
  32422 #if defined(BCM_88675_B0)
  32423     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM88675_B0r */
  32424         soc_block_list[22],
  32425         soc_genreg,
  32426         1,
  32427         0,
  32428         0x6e7,
  32429         SOC_REG_FLAG_64_BITS,
  32430         0,
  32431         8,
  32432         soc_OAMP_SAT_GEN_CONFIG_BCM88675_B0r_fields,
  32433         SOC_RESET_VAL_DEC(0xffe0000f, 0x001fffff)
  32434         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
  32435         -1,
  32436         -1,
  32437     },
  32438 #endif /* chips */
  32439 
  32440 #if defined(BCM_88680_A0)
  32441     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM88680_A0r */
  32442         soc_block_list[22],
  32443         soc_genreg,
  32444         1,
  32445         0,
  32446         0x6e7,
  32447         SOC_REG_FLAG_64_BITS,
  32448         0,
  32449         8,
  32450         soc_OAMP_SAT_GEN_CONFIG_BCM88680_A0r_fields,
  32451         SOC_RESET_VAL_DEC(0xffe0000f, 0x001fffff)
  32452         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
  32453         -1,
  32454         -1,
  32455     },
  32456 #endif /* chips */
  32457 
  32458 #if defined(BCM_88690_A0)
  32459     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM88690_A0r */
  32460         soc_block_list[22],
  32461         soc_genreg,
  32462         1,
  32463         0,
  32464         0x670,
  32465         SOC_REG_FLAG_64_BITS,
  32466         0,
  32467         6,
  32468         soc_OAMP_SAT_GEN_CONFIG_BCM88690_A0r_fields,
  32469         SOC_RESET_VAL_DEC(0xffffffff, 0x0000000f)
  32470         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  32471         -1,
  32472         -1,
  32473     },
  32474 #endif /* chips */
  32475 
  32476 #if defined(BCM_88690_B0)
  32477     { /* SOC_REG_INT_OAMP_SAT_GEN_CONFIG_BCM88690_B0r */
  32478         soc_block_list[22],
  32479         soc_genreg,
  32480         1,
  32481         0,
  32482         0x670,
  32483         SOC_REG_FLAG_64_BITS,
  32484         0,
  32485         7,
  32486         soc_OAMP_SAT_GEN_CONFIG_BCM88690_B0r_fields,
  32487         SOC_RESET_VAL_DEC(0xffffffff, 0x0000000f)
  32488         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  32489         -1,
  32490         -1,
  32491     },
  32492 #endif /* chips */
  32493 
  32494 #if defined(BCM_88675_A0)
  32495     { /* SOC_REG_INT_OAMP_SAT_GEN_RATE_CONTROLr */
  32496         soc_block_list[22],
  32497         soc_genreg,
  32498         16,
  32499         0,
  32500         0x759,
  32501         SOC_REG_FLAG_ABOVE_64_BITS |
  32502                           SOC_REG_FLAG_ARRAY |
  32503                           SOC_REG_FLAG_REG_ARRAY,
  32504         0,
  32505         20,
  32506         soc_OAMP_SAT_GEN_RATE_CONTROLr_fields,
  32507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32508         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32509         -1,
  32510         -1,
  32511     },
  32512 #endif /* chips */
  32513 
  32514 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  32515     defined(BCM_56270_A0)
  32516     { /* SOC_REG_INT_OAMP_SAT_GEN_RATE_CONTROL_BCM56260_A0r */
  32517         soc_block_list[22],
  32518         soc_genreg,
  32519         16,
  32520         0,
  32521         0x201f600,
  32522         SOC_REG_FLAG_ABOVE_64_BITS |
  32523                           SOC_REG_FLAG_ARRAY |
  32524                           SOC_REG_FLAG_REG_ARRAY,
  32525         0,
  32526         20,
  32527         soc_OAMP_SAT_GEN_RATE_CONTROL_BCM56260_A0r_fields,
  32528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32529         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32530         -1,
  32531         -1,
  32532     },
  32533 #endif /* chips */
  32534 
  32535 #if defined(BCM_88270_A0)
  32536     { /* SOC_REG_INT_OAMP_SAT_GEN_RATE_CONTROL_BCM88270_A0r */
  32537         soc_block_list[22],
  32538         soc_genreg,
  32539         16,
  32540         0,
  32541         0x757,
  32542         SOC_REG_FLAG_ABOVE_64_BITS |
  32543                           SOC_REG_FLAG_ARRAY |
  32544                           SOC_REG_FLAG_REG_ARRAY,
  32545         0,
  32546         20,
  32547         soc_OAMP_SAT_GEN_RATE_CONTROL_BCM88270_A0r_fields,
  32548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32549         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32550         -1,
  32551         -1,
  32552     },
  32553 #endif /* chips */
  32554 
  32555 #if defined(BCM_88375_A0)
  32556     { /* SOC_REG_INT_OAMP_SAT_GEN_RATE_CONTROL_BCM88375_A0r */
  32557         soc_block_list[22],
  32558         soc_genreg,
  32559         16,
  32560         0,
  32561         0x759,
  32562         SOC_REG_FLAG_ABOVE_64_BITS |
  32563                           SOC_REG_FLAG_ARRAY |
  32564                           SOC_REG_FLAG_REG_ARRAY,
  32565         0,
  32566         20,
  32567         soc_OAMP_SAT_GEN_RATE_CONTROL_BCM88375_A0r_fields,
  32568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32569         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32570         -1,
  32571         -1,
  32572     },
  32573 #endif /* chips */
  32574 
  32575 #if defined(BCM_88375_B0)
  32576     { /* SOC_REG_INT_OAMP_SAT_GEN_RATE_CONTROL_BCM88375_B0r */
  32577         soc_block_list[22],
  32578         soc_genreg,
  32579         16,
  32580         0,
  32581         0x759,
  32582         SOC_REG_FLAG_ABOVE_64_BITS |
  32583                           SOC_REG_FLAG_ARRAY |
  32584                           SOC_REG_FLAG_REG_ARRAY,
  32585         0,
  32586         20,
  32587         soc_OAMP_SAT_GEN_RATE_CONTROL_BCM88375_B0r_fields,
  32588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32589         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32590         -1,
  32591         -1,
  32592     },
  32593 #endif /* chips */
  32594 
  32595 #if defined(BCM_88470_A0)
  32596     { /* SOC_REG_INT_OAMP_SAT_GEN_RATE_CONTROL_BCM88470_A0r */
  32597         soc_block_list[22],
  32598         soc_genreg,
  32599         16,
  32600         0,
  32601         0x757,
  32602         SOC_REG_FLAG_ABOVE_64_BITS |
  32603                           SOC_REG_FLAG_ARRAY |
  32604                           SOC_REG_FLAG_REG_ARRAY,
  32605         0,
  32606         20,
  32607         soc_OAMP_SAT_GEN_RATE_CONTROL_BCM88470_A0r_fields,
  32608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32609         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32610         -1,
  32611         -1,
  32612     },
  32613 #endif /* chips */
  32614 
  32615 #if defined(BCM_88470_B0)
  32616     { /* SOC_REG_INT_OAMP_SAT_GEN_RATE_CONTROL_BCM88470_B0r */
  32617         soc_block_list[22],
  32618         soc_genreg,
  32619         16,
  32620         0,
  32621         0x757,
  32622         SOC_REG_FLAG_ABOVE_64_BITS |
  32623                           SOC_REG_FLAG_ARRAY |
  32624                           SOC_REG_FLAG_REG_ARRAY,
  32625         0,
  32626         20,
  32627         soc_OAMP_SAT_GEN_RATE_CONTROL_BCM88470_B0r_fields,
  32628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32630         -1,
  32631         -1,
  32632     },
  32633 #endif /* chips */
  32634 
  32635 #if defined(BCM_88675_B0)
  32636     { /* SOC_REG_INT_OAMP_SAT_GEN_RATE_CONTROL_BCM88675_B0r */
  32637         soc_block_list[22],
  32638         soc_genreg,
  32639         16,
  32640         0,
  32641         0x759,
  32642         SOC_REG_FLAG_ABOVE_64_BITS |
  32643                           SOC_REG_FLAG_ARRAY |
  32644                           SOC_REG_FLAG_REG_ARRAY,
  32645         0,
  32646         20,
  32647         soc_OAMP_SAT_GEN_RATE_CONTROL_BCM88675_B0r_fields,
  32648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32649         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32650         -1,
  32651         -1,
  32652     },
  32653 #endif /* chips */
  32654 
  32655 #if defined(BCM_88680_A0)
  32656     { /* SOC_REG_INT_OAMP_SAT_GEN_RATE_CONTROL_BCM88680_A0r */
  32657         soc_block_list[22],
  32658         soc_genreg,
  32659         16,
  32660         0,
  32661         0x759,
  32662         SOC_REG_FLAG_ABOVE_64_BITS |
  32663                           SOC_REG_FLAG_ARRAY |
  32664                           SOC_REG_FLAG_REG_ARRAY,
  32665         0,
  32666         20,
  32667         soc_OAMP_SAT_GEN_RATE_CONTROL_BCM88680_A0r_fields,
  32668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32670         -1,
  32671         -1,
  32672     },
  32673 #endif /* chips */
  32674 
  32675 #if defined(BCM_88675_A0)
  32676     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIGr */
  32677         soc_block_list[22],
  32678         soc_genreg,
  32679         1,
  32680         0,
  32681         0x6e9,
  32682         SOC_REG_FLAG_ABOVE_64_BITS,
  32683         0,
  32684         12,
  32685         soc_OAMP_SAT_RX_CONFIGr_fields,
  32686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32687         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32688         -1,
  32689         -1,
  32690     },
  32691 #endif /* chips */
  32692 
  32693 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  32694     defined(BCM_56270_A0)
  32695     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM56260_A0r */
  32696         soc_block_list[22],
  32697         soc_genreg,
  32698         1,
  32699         0,
  32700         0x2018600,
  32701         SOC_REG_FLAG_ABOVE_64_BITS,
  32702         0,
  32703         12,
  32704         soc_OAMP_SAT_RX_CONFIG_BCM56260_A0r_fields,
  32705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32706         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32707         -1,
  32708         -1,
  32709     },
  32710 #endif /* chips */
  32711 
  32712 #if defined(BCM_88270_A0)
  32713     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM88270_A0r */
  32714         soc_block_list[22],
  32715         soc_genreg,
  32716         1,
  32717         0,
  32718         0x6e7,
  32719         SOC_REG_FLAG_ABOVE_64_BITS,
  32720         0,
  32721         12,
  32722         soc_OAMP_SAT_RX_CONFIG_BCM88270_A0r_fields,
  32723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32724         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32725         -1,
  32726         -1,
  32727     },
  32728 #endif /* chips */
  32729 
  32730 #if defined(BCM_88375_A0)
  32731     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM88375_A0r */
  32732         soc_block_list[22],
  32733         soc_genreg,
  32734         1,
  32735         0,
  32736         0x6e9,
  32737         SOC_REG_FLAG_ABOVE_64_BITS,
  32738         0,
  32739         12,
  32740         soc_OAMP_SAT_RX_CONFIG_BCM88375_A0r_fields,
  32741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32742         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32743         -1,
  32744         -1,
  32745     },
  32746 #endif /* chips */
  32747 
  32748 #if defined(BCM_88375_B0)
  32749     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM88375_B0r */
  32750         soc_block_list[22],
  32751         soc_genreg,
  32752         1,
  32753         0,
  32754         0x6e9,
  32755         SOC_REG_FLAG_ABOVE_64_BITS,
  32756         0,
  32757         12,
  32758         soc_OAMP_SAT_RX_CONFIG_BCM88375_B0r_fields,
  32759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32760         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32761         -1,
  32762         -1,
  32763     },
  32764 #endif /* chips */
  32765 
  32766 #if defined(BCM_88470_A0)
  32767     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM88470_A0r */
  32768         soc_block_list[22],
  32769         soc_genreg,
  32770         1,
  32771         0,
  32772         0x6e7,
  32773         SOC_REG_FLAG_ABOVE_64_BITS,
  32774         0,
  32775         12,
  32776         soc_OAMP_SAT_RX_CONFIG_BCM88470_A0r_fields,
  32777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32778         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32779         -1,
  32780         -1,
  32781     },
  32782 #endif /* chips */
  32783 
  32784 #if defined(BCM_88470_B0)
  32785     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM88470_B0r */
  32786         soc_block_list[22],
  32787         soc_genreg,
  32788         1,
  32789         0,
  32790         0x6e7,
  32791         SOC_REG_FLAG_ABOVE_64_BITS,
  32792         0,
  32793         12,
  32794         soc_OAMP_SAT_RX_CONFIG_BCM88470_B0r_fields,
  32795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32796         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32797         -1,
  32798         -1,
  32799     },
  32800 #endif /* chips */
  32801 
  32802 #if defined(BCM_88675_B0)
  32803     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM88675_B0r */
  32804         soc_block_list[22],
  32805         soc_genreg,
  32806         1,
  32807         0,
  32808         0x6e9,
  32809         SOC_REG_FLAG_ABOVE_64_BITS,
  32810         0,
  32811         12,
  32812         soc_OAMP_SAT_RX_CONFIG_BCM88675_B0r_fields,
  32813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32814         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32815         -1,
  32816         -1,
  32817     },
  32818 #endif /* chips */
  32819 
  32820 #if defined(BCM_88680_A0)
  32821     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM88680_A0r */
  32822         soc_block_list[22],
  32823         soc_genreg,
  32824         1,
  32825         0,
  32826         0x6e9,
  32827         SOC_REG_FLAG_ABOVE_64_BITS,
  32828         0,
  32829         12,
  32830         soc_OAMP_SAT_RX_CONFIG_BCM88680_A0r_fields,
  32831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32833         -1,
  32834         -1,
  32835     },
  32836 #endif /* chips */
  32837 
  32838 #if defined(BCM_88690_A0)
  32839     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM88690_A0r */
  32840         soc_block_list[22],
  32841         soc_genreg,
  32842         1,
  32843         0,
  32844         0x673,
  32845         SOC_REG_FLAG_ABOVE_64_BITS,
  32846         0,
  32847         12,
  32848         soc_OAMP_SAT_RX_CONFIG_BCM88690_A0r_fields,
  32849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32851         -1,
  32852         -1,
  32853     },
  32854 #endif /* chips */
  32855 
  32856 #if defined(BCM_88690_B0)
  32857     { /* SOC_REG_INT_OAMP_SAT_RX_CONFIG_BCM88690_B0r */
  32858         soc_block_list[22],
  32859         soc_genreg,
  32860         1,
  32861         0,
  32862         0x673,
  32863         SOC_REG_FLAG_ABOVE_64_BITS,
  32864         0,
  32865         12,
  32866         soc_OAMP_SAT_RX_CONFIG_BCM88690_B0r_fields,
  32867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32868         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32869         -1,
  32870         -1,
  32871     },
  32872 #endif /* chips */
  32873 
  32874 #if defined(BCM_88675_A0)
  32875     { /* SOC_REG_INT_OAMP_SAT_RX_STATr */
  32876         soc_block_list[22],
  32877         soc_genreg,
  32878         1,
  32879         0,
  32880         0x6f3,
  32881         SOC_REG_FLAG_64_BITS,
  32882         0,
  32883         7,
  32884         soc_OAMP_SAT_RX_STATr_fields,
  32885         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  32886         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  32887         -1,
  32888         -1,
  32889     },
  32890 #endif /* chips */
  32891 
  32892 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  32893     defined(BCM_56270_A0)
  32894     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM56260_A0r */
  32895         soc_block_list[22],
  32896         soc_genreg,
  32897         1,
  32898         0,
  32899         0x2019000,
  32900         SOC_REG_FLAG_64_BITS,
  32901         0,
  32902         7,
  32903         soc_OAMP_SAT_RX_STAT_BCM56260_A0r_fields,
  32904         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  32905         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  32906         -1,
  32907         -1,
  32908     },
  32909 #endif /* chips */
  32910 
  32911 #if defined(BCM_88270_A0)
  32912     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM88270_A0r */
  32913         soc_block_list[22],
  32914         soc_genreg,
  32915         1,
  32916         0,
  32917         0x6f1,
  32918         SOC_REG_FLAG_64_BITS,
  32919         0,
  32920         7,
  32921         soc_OAMP_SAT_RX_STAT_BCM88270_A0r_fields,
  32922         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  32923         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  32924         -1,
  32925         -1,
  32926     },
  32927 #endif /* chips */
  32928 
  32929 #if defined(BCM_88375_A0)
  32930     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM88375_A0r */
  32931         soc_block_list[22],
  32932         soc_genreg,
  32933         1,
  32934         0,
  32935         0x6f3,
  32936         SOC_REG_FLAG_64_BITS,
  32937         0,
  32938         7,
  32939         soc_OAMP_SAT_RX_STAT_BCM88375_A0r_fields,
  32940         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  32941         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  32942         -1,
  32943         -1,
  32944     },
  32945 #endif /* chips */
  32946 
  32947 #if defined(BCM_88375_B0)
  32948     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM88375_B0r */
  32949         soc_block_list[22],
  32950         soc_genreg,
  32951         1,
  32952         0,
  32953         0x6f3,
  32954         SOC_REG_FLAG_64_BITS,
  32955         0,
  32956         7,
  32957         soc_OAMP_SAT_RX_STAT_BCM88375_B0r_fields,
  32958         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  32959         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  32960         -1,
  32961         -1,
  32962     },
  32963 #endif /* chips */
  32964 
  32965 #if defined(BCM_88470_A0)
  32966     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM88470_A0r */
  32967         soc_block_list[22],
  32968         soc_genreg,
  32969         1,
  32970         0,
  32971         0x6f1,
  32972         SOC_REG_FLAG_64_BITS,
  32973         0,
  32974         7,
  32975         soc_OAMP_SAT_RX_STAT_BCM88470_A0r_fields,
  32976         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  32977         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  32978         -1,
  32979         -1,
  32980     },
  32981 #endif /* chips */
  32982 
  32983 #if defined(BCM_88470_B0)
  32984     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM88470_B0r */
  32985         soc_block_list[22],
  32986         soc_genreg,
  32987         1,
  32988         0,
  32989         0x6f1,
  32990         SOC_REG_FLAG_64_BITS,
  32991         0,
  32992         7,
  32993         soc_OAMP_SAT_RX_STAT_BCM88470_B0r_fields,
  32994         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  32995         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  32996         -1,
  32997         -1,
  32998     },
  32999 #endif /* chips */
  33000 
  33001 #if defined(BCM_88675_B0)
  33002     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM88675_B0r */
  33003         soc_block_list[22],
  33004         soc_genreg,
  33005         1,
  33006         0,
  33007         0x6f3,
  33008         SOC_REG_FLAG_64_BITS,
  33009         0,
  33010         7,
  33011         soc_OAMP_SAT_RX_STAT_BCM88675_B0r_fields,
  33012         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  33013         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  33014         -1,
  33015         -1,
  33016     },
  33017 #endif /* chips */
  33018 
  33019 #if defined(BCM_88680_A0)
  33020     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM88680_A0r */
  33021         soc_block_list[22],
  33022         soc_genreg,
  33023         1,
  33024         0,
  33025         0x6f3,
  33026         SOC_REG_FLAG_64_BITS,
  33027         0,
  33028         7,
  33029         soc_OAMP_SAT_RX_STAT_BCM88680_A0r_fields,
  33030         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  33031         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  33032         -1,
  33033         -1,
  33034     },
  33035 #endif /* chips */
  33036 
  33037 #if defined(BCM_88690_A0)
  33038     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM88690_A0r */
  33039         soc_block_list[22],
  33040         soc_genreg,
  33041         1,
  33042         0,
  33043         0x67d,
  33044         SOC_REG_FLAG_64_BITS,
  33045         0,
  33046         7,
  33047         soc_OAMP_SAT_RX_STAT_BCM88690_A0r_fields,
  33048         SOC_RESET_VAL_DEC(0x00001400, 0x00000000)
  33049         SOC_RESET_MASK_DEC(0xffffffff, 0x00001fff)
  33050         -1,
  33051         -1,
  33052     },
  33053 #endif /* chips */
  33054 
  33055 #if defined(BCM_88690_B0)
  33056     { /* SOC_REG_INT_OAMP_SAT_RX_STAT_BCM88690_B0r */
  33057         soc_block_list[22],
  33058         soc_genreg,
  33059         1,
  33060         0,
  33061         0x67d,
  33062         SOC_REG_FLAG_64_BITS,
  33063         0,
  33064         7,
  33065         soc_OAMP_SAT_RX_STAT_BCM88690_B0r_fields,
  33066         SOC_RESET_VAL_DEC(0x00001400, 0x00000000)
  33067         SOC_RESET_MASK_DEC(0xffffffff, 0x00001fff)
  33068         -1,
  33069         -1,
  33070     },
  33071 #endif /* chips */
  33072 
  33073 #if defined(BCM_88690_A0)
  33074     { /* SOC_REG_INT_OAMP_SAT_TX_CONFIGr */
  33075         soc_block_list[22],
  33076         soc_genreg,
  33077         1,
  33078         0,
  33079         0x672,
  33080         0,
  33081         0,
  33082         4,
  33083         soc_OAMP_SAT_TX_CONFIGr_fields,
  33084         SOC_RESET_VAL_DEC(0x02040810, 0x00000000)
  33085         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  33086         -1,
  33087         -1,
  33088     },
  33089 #endif /* chips */
  33090 
  33091 #if defined(BCM_88690_B0)
  33092     { /* SOC_REG_INT_OAMP_SAT_TX_CONFIG_BCM88690_B0r */
  33093         soc_block_list[22],
  33094         soc_genreg,
  33095         1,
  33096         0,
  33097         0x672,
  33098         0,
  33099         0,
  33100         4,
  33101         soc_OAMP_SAT_TX_CONFIG_BCM88690_B0r_fields,
  33102         SOC_RESET_VAL_DEC(0x02040810, 0x00000000)
  33103         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  33104         -1,
  33105         -1,
  33106     },
  33107 #endif /* chips */
  33108 
  33109 #if defined(BCM_88470_A0)
  33110     { /* SOC_REG_INT_OAMP_SAT_TX_EVC_CNTRr */
  33111         soc_block_list[22],
  33112         soc_genreg,
  33113         8,
  33114         0,
  33115         0x80f,
  33116         SOC_REG_FLAG_64_BITS |
  33117                           SOC_REG_FLAG_ARRAY |
  33118                           SOC_REG_FLAG_RO |
  33119                           SOC_REG_FLAG_REG_ARRAY,
  33120         0,
  33121         2,
  33122         soc_OAMP_SAT_TX_EVC_CNTRr_fields,
  33123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33124         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  33125         -1,
  33126         -1,
  33127     },
  33128 #endif /* chips */
  33129 
  33130 #if defined(BCM_88270_A0)
  33131     { /* SOC_REG_INT_OAMP_SAT_TX_EVC_CNTR_BCM88270_A0r */
  33132         soc_block_list[22],
  33133         soc_genreg,
  33134         8,
  33135         0,
  33136         0x80f,
  33137         SOC_REG_FLAG_64_BITS |
  33138                           SOC_REG_FLAG_ARRAY |
  33139                           SOC_REG_FLAG_RO |
  33140                           SOC_REG_FLAG_REG_ARRAY,
  33141         0,
  33142         2,
  33143         soc_OAMP_SAT_TX_EVC_CNTR_BCM88270_A0r_fields,
  33144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33145         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  33146         -1,
  33147         -1,
  33148     },
  33149 #endif /* chips */
  33150 
  33151 #if defined(BCM_88470_B0)
  33152     { /* SOC_REG_INT_OAMP_SAT_TX_EVC_CNTR_BCM88470_B0r */
  33153         soc_block_list[22],
  33154         soc_genreg,
  33155         8,
  33156         0,
  33157         0x80f,
  33158         SOC_REG_FLAG_64_BITS |
  33159                           SOC_REG_FLAG_ARRAY |
  33160                           SOC_REG_FLAG_RO |
  33161                           SOC_REG_FLAG_REG_ARRAY,
  33162         0,
  33163         2,
  33164         soc_OAMP_SAT_TX_EVC_CNTR_BCM88470_B0r_fields,
  33165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33166         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  33167         -1,
  33168         -1,
  33169     },
  33170 #endif /* chips */
  33171 
  33172 #if defined(BCM_88690_A0)
  33173     { /* SOC_REG_INT_OAMP_SAT_TX_EVC_CNTR_BCM88690_A0r */
  33174         soc_block_list[22],
  33175         soc_genreg,
  33176         8,
  33177         0,
  33178         0x8ef,
  33179         SOC_REG_FLAG_ABOVE_64_BITS |
  33180                           SOC_REG_FLAG_ARRAY |
  33181                           SOC_REG_FLAG_RO |
  33182                           SOC_REG_FLAG_REG_ARRAY,
  33183         SOC_REG_FLAG_COUNTER_FEILDS,
  33184         2,
  33185         soc_OAMP_SAT_TX_EVC_CNTR_BCM88690_A0r_fields,
  33186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33188         -1,
  33189         -1,
  33190     },
  33191 #endif /* chips */
  33192 
  33193 #if defined(BCM_88690_B0)
  33194     { /* SOC_REG_INT_OAMP_SAT_TX_EVC_CNTR_BCM88690_B0r */
  33195         soc_block_list[22],
  33196         soc_genreg,
  33197         8,
  33198         0,
  33199         0x8ef,
  33200         SOC_REG_FLAG_ABOVE_64_BITS |
  33201                           SOC_REG_FLAG_ARRAY |
  33202                           SOC_REG_FLAG_RO |
  33203                           SOC_REG_FLAG_REG_ARRAY,
  33204         SOC_REG_FLAG_COUNTER_FEILDS,
  33205         2,
  33206         soc_OAMP_SAT_TX_EVC_CNTR_BCM88690_B0r_fields,
  33207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33208         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33209         -1,
  33210         -1,
  33211     },
  33212 #endif /* chips */
  33213 
  33214 #if defined(BCM_88470_A0)
  33215     { /* SOC_REG_INT_OAMP_SAT_TX_GEN_CNTRr */
  33216         soc_block_list[22],
  33217         soc_genreg,
  33218         16,
  33219         0,
  33220         0x7ef,
  33221         SOC_REG_FLAG_64_BITS |
  33222                           SOC_REG_FLAG_ARRAY |
  33223                           SOC_REG_FLAG_RO |
  33224                           SOC_REG_FLAG_REG_ARRAY,
  33225         0,
  33226         2,
  33227         soc_OAMP_SAT_TX_GEN_CNTRr_fields,
  33228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33229         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  33230         -1,
  33231         -1,
  33232     },
  33233 #endif /* chips */
  33234 
  33235 #if defined(BCM_88270_A0)
  33236     { /* SOC_REG_INT_OAMP_SAT_TX_GEN_CNTR_BCM88270_A0r */
  33237         soc_block_list[22],
  33238         soc_genreg,
  33239         16,
  33240         0,
  33241         0x7ef,
  33242         SOC_REG_FLAG_64_BITS |
  33243                           SOC_REG_FLAG_ARRAY |
  33244                           SOC_REG_FLAG_RO |
  33245                           SOC_REG_FLAG_REG_ARRAY,
  33246         0,
  33247         2,
  33248         soc_OAMP_SAT_TX_GEN_CNTR_BCM88270_A0r_fields,
  33249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33250         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  33251         -1,
  33252         -1,
  33253     },
  33254 #endif /* chips */
  33255 
  33256 #if defined(BCM_88470_B0)
  33257     { /* SOC_REG_INT_OAMP_SAT_TX_GEN_CNTR_BCM88470_B0r */
  33258         soc_block_list[22],
  33259         soc_genreg,
  33260         16,
  33261         0,
  33262         0x7ef,
  33263         SOC_REG_FLAG_64_BITS |
  33264                           SOC_REG_FLAG_ARRAY |
  33265                           SOC_REG_FLAG_RO |
  33266                           SOC_REG_FLAG_REG_ARRAY,
  33267         0,
  33268         2,
  33269         soc_OAMP_SAT_TX_GEN_CNTR_BCM88470_B0r_fields,
  33270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33271         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  33272         -1,
  33273         -1,
  33274     },
  33275 #endif /* chips */
  33276 
  33277 #if defined(BCM_88690_A0)
  33278     { /* SOC_REG_INT_OAMP_SAT_TX_GEN_CNTR_BCM88690_A0r */
  33279         soc_block_list[22],
  33280         soc_genreg,
  33281         64,
  33282         0,
  33283         0x6ef,
  33284         SOC_REG_FLAG_ABOVE_64_BITS |
  33285                           SOC_REG_FLAG_ARRAY |
  33286                           SOC_REG_FLAG_RO |
  33287                           SOC_REG_FLAG_REG_ARRAY,
  33288         SOC_REG_FLAG_COUNTER_FEILDS,
  33289         2,
  33290         soc_OAMP_SAT_TX_GEN_CNTR_BCM88690_A0r_fields,
  33291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33293         -1,
  33294         -1,
  33295     },
  33296 #endif /* chips */
  33297 
  33298 #if defined(BCM_88690_B0)
  33299     { /* SOC_REG_INT_OAMP_SAT_TX_GEN_CNTR_BCM88690_B0r */
  33300         soc_block_list[22],
  33301         soc_genreg,
  33302         64,
  33303         0,
  33304         0x6ef,
  33305         SOC_REG_FLAG_ABOVE_64_BITS |
  33306                           SOC_REG_FLAG_ARRAY |
  33307                           SOC_REG_FLAG_RO |
  33308                           SOC_REG_FLAG_REG_ARRAY,
  33309         SOC_REG_FLAG_COUNTER_FEILDS,
  33310         2,
  33311         soc_OAMP_SAT_TX_GEN_CNTR_BCM88690_B0r_fields,
  33312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33313         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33314         -1,
  33315         -1,
  33316     },
  33317 #endif /* chips */
  33318 
  33319 #if defined(BCM_88690_A0)
  33320     { /* SOC_REG_INT_OAMP_SAT_TX_GEN_FLOW_RATE_CONTROLr */
  33321         soc_block_list[22],
  33322         soc_genreg,
  33323         64,
  33324         0,
  33325         0x900,
  33326         SOC_REG_FLAG_ABOVE_64_BITS |
  33327                           SOC_REG_FLAG_ARRAY |
  33328                           SOC_REG_FLAG_REG_ARRAY,
  33329         SOC_REG_FLAG_INIT_ON_READ,
  33330         22,
  33331         soc_OAMP_SAT_TX_GEN_FLOW_RATE_CONTROLr_fields,
  33332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33334         -1,
  33335         -1,
  33336     },
  33337 #endif /* chips */
  33338 
  33339 #if defined(BCM_88690_B0)
  33340     { /* SOC_REG_INT_OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL_BCM88690_B0r */
  33341         soc_block_list[22],
  33342         soc_genreg,
  33343         64,
  33344         0,
  33345         0x900,
  33346         SOC_REG_FLAG_ABOVE_64_BITS |
  33347                           SOC_REG_FLAG_ARRAY |
  33348                           SOC_REG_FLAG_REG_ARRAY,
  33349         SOC_REG_FLAG_INIT_ON_READ,
  33350         22,
  33351         soc_OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL_BCM88690_B0r_fields,
  33352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33353         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33354         -1,
  33355         -1,
  33356     },
  33357 #endif /* chips */
  33358 
  33359 #if defined(BCM_88470_A0)
  33360     { /* SOC_REG_INT_OAMP_SBUS_BROADCAST_IDr */
  33361         soc_block_list[22],
  33362         soc_genreg,
  33363         1,
  33364         0,
  33365         0x86,
  33366         0,
  33367         0,
  33368         1,
  33369         soc_OAMP_SBUS_BROADCAST_IDr_fields,
  33370         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  33371         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  33372         -1,
  33373         -1,
  33374     },
  33375 #endif /* chips */
  33376 
  33377 #if defined(BCM_88270_A0)
  33378     { /* SOC_REG_INT_OAMP_SBUS_BROADCAST_ID_BCM88270_A0r */
  33379         soc_block_list[22],
  33380         soc_genreg,
  33381         1,
  33382         0,
  33383         0x86,
  33384         0,
  33385         0,
  33386         1,
  33387         soc_OAMP_SBUS_BROADCAST_ID_BCM88270_A0r_fields,
  33388         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  33389         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  33390         -1,
  33391         -1,
  33392     },
  33393 #endif /* chips */
  33394 
  33395 #if defined(BCM_88470_B0)
  33396     { /* SOC_REG_INT_OAMP_SBUS_BROADCAST_ID_BCM88470_B0r */
  33397         soc_block_list[22],
  33398         soc_genreg,
  33399         1,
  33400         0,
  33401         0x86,
  33402         0,
  33403         0,
  33404         1,
  33405         soc_OAMP_SBUS_BROADCAST_ID_BCM88470_B0r_fields,
  33406         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  33407         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  33408         -1,
  33409         -1,
  33410     },
  33411 #endif /* chips */
  33412 
  33413 #if defined(BCM_88690_A0)
  33414     { /* SOC_REG_INT_OAMP_SBUS_BROADCAST_ID_BCM88690_A0r */
  33415         soc_block_list[22],
  33416         soc_genreg,
  33417         1,
  33418         0,
  33419         0x86,
  33420         0,
  33421         0,
  33422         1,
  33423         soc_OAMP_SBUS_BROADCAST_ID_BCM88690_A0r_fields,
  33424         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  33425         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  33426         -1,
  33427         -1,
  33428     },
  33429 #endif /* chips */
  33430 
  33431 #if defined(BCM_88690_B0)
  33432     { /* SOC_REG_INT_OAMP_SBUS_BROADCAST_ID_BCM88690_B0r */
  33433         soc_block_list[22],
  33434         soc_genreg,
  33435         1,
  33436         0,
  33437         0x86,
  33438         0,
  33439         0,
  33440         1,
  33441         soc_OAMP_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
  33442         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  33443         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  33444         -1,
  33445         -1,
  33446     },
  33447 #endif /* chips */
  33448 
  33449 #if defined(BCM_88470_A0)
  33450     { /* SOC_REG_INT_OAMP_SBUS_LAST_IN_CHAINr */
  33451         soc_block_list[22],
  33452         soc_genreg,
  33453         1,
  33454         0,
  33455         0x87,
  33456         0,
  33457         0,
  33458         1,
  33459         soc_OAMP_SBUS_LAST_IN_CHAINr_fields,
  33460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33461         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  33462         -1,
  33463         -1,
  33464     },
  33465 #endif /* chips */
  33466 
  33467 #if defined(BCM_88270_A0)
  33468     { /* SOC_REG_INT_OAMP_SBUS_LAST_IN_CHAIN_BCM88270_A0r */
  33469         soc_block_list[22],
  33470         soc_genreg,
  33471         1,
  33472         0,
  33473         0x87,
  33474         0,
  33475         0,
  33476         1,
  33477         soc_OAMP_SBUS_LAST_IN_CHAIN_BCM88270_A0r_fields,
  33478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33479         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  33480         -1,
  33481         -1,
  33482     },
  33483 #endif /* chips */
  33484 
  33485 #if defined(BCM_88470_B0)
  33486     { /* SOC_REG_INT_OAMP_SBUS_LAST_IN_CHAIN_BCM88470_B0r */
  33487         soc_block_list[22],
  33488         soc_genreg,
  33489         1,
  33490         0,
  33491         0x87,
  33492         0,
  33493         0,
  33494         1,
  33495         soc_OAMP_SBUS_LAST_IN_CHAIN_BCM88470_B0r_fields,
  33496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33497         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  33498         -1,
  33499         -1,
  33500     },
  33501 #endif /* chips */
  33502 
  33503 #if defined(BCM_88690_A0)
  33504     { /* SOC_REG_INT_OAMP_SBUS_LAST_IN_CHAIN_BCM88690_A0r */
  33505         soc_block_list[22],
  33506         soc_genreg,
  33507         1,
  33508         0,
  33509         0x87,
  33510         0,
  33511         0,
  33512         1,
  33513         soc_OAMP_SBUS_LAST_IN_CHAIN_BCM88690_A0r_fields,
  33514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33515         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  33516         -1,
  33517         -1,
  33518     },
  33519 #endif /* chips */
  33520 
  33521 #if defined(BCM_88690_B0)
  33522     { /* SOC_REG_INT_OAMP_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
  33523         soc_block_list[22],
  33524         soc_genreg,
  33525         1,
  33526         0,
  33527         0x87,
  33528         0,
  33529         0,
  33530         1,
  33531         soc_OAMP_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
  33532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33533         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  33534         -1,
  33535         -1,
  33536     },
  33537 #endif /* chips */
  33538 
  33539 #if defined(BCM_88470_A0)
  33540     { /* SOC_REG_INT_OAMP_SD_SF_SCANNER_CFGr */
  33541         soc_block_list[22],
  33542         soc_genreg,
  33543         1,
  33544         0,
  33545         0x81f,
  33546         SOC_REG_FLAG_ABOVE_64_BITS,
  33547         0,
  33548         9,
  33549         soc_OAMP_SD_SF_SCANNER_CFGr_fields,
  33550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33551         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33552         -1,
  33553         -1,
  33554     },
  33555 #endif /* chips */
  33556 
  33557 #if defined(BCM_88270_A0)
  33558     { /* SOC_REG_INT_OAMP_SD_SF_SCANNER_CFG_BCM88270_A0r */
  33559         soc_block_list[22],
  33560         soc_genreg,
  33561         1,
  33562         0,
  33563         0x81f,
  33564         SOC_REG_FLAG_ABOVE_64_BITS,
  33565         0,
  33566         9,
  33567         soc_OAMP_SD_SF_SCANNER_CFG_BCM88270_A0r_fields,
  33568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33569         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33570         -1,
  33571         -1,
  33572     },
  33573 #endif /* chips */
  33574 
  33575 #if defined(BCM_88470_B0)
  33576     { /* SOC_REG_INT_OAMP_SD_SF_SCANNER_CFG_BCM88470_B0r */
  33577         soc_block_list[22],
  33578         soc_genreg,
  33579         1,
  33580         0,
  33581         0x81f,
  33582         SOC_REG_FLAG_ABOVE_64_BITS,
  33583         0,
  33584         9,
  33585         soc_OAMP_SD_SF_SCANNER_CFG_BCM88470_B0r_fields,
  33586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33587         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33588         -1,
  33589         -1,
  33590     },
  33591 #endif /* chips */
  33592 
  33593 #if defined(BCM_88470_A0)
  33594     { /* SOC_REG_INT_OAMP_SD_SF_SHARE_CFGr */
  33595         soc_block_list[22],
  33596         soc_genreg,
  33597         1,
  33598         0,
  33599         0x825,
  33600         0,
  33601         0,
  33602         2,
  33603         soc_OAMP_SD_SF_SHARE_CFGr_fields,
  33604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33605         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  33606         -1,
  33607         -1,
  33608     },
  33609 #endif /* chips */
  33610 
  33611 #if defined(BCM_88270_A0)
  33612     { /* SOC_REG_INT_OAMP_SD_SF_SHARE_CFG_BCM88270_A0r */
  33613         soc_block_list[22],
  33614         soc_genreg,
  33615         1,
  33616         0,
  33617         0x825,
  33618         0,
  33619         0,
  33620         2,
  33621         soc_OAMP_SD_SF_SHARE_CFG_BCM88270_A0r_fields,
  33622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33623         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  33624         -1,
  33625         -1,
  33626     },
  33627 #endif /* chips */
  33628 
  33629 #if defined(BCM_88470_B0)
  33630     { /* SOC_REG_INT_OAMP_SD_SF_SHARE_CFG_BCM88470_B0r */
  33631         soc_block_list[22],
  33632         soc_genreg,
  33633         1,
  33634         0,
  33635         0x825,
  33636         0,
  33637         0,
  33638         2,
  33639         soc_OAMP_SD_SF_SHARE_CFG_BCM88470_B0r_fields,
  33640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33641         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  33642         -1,
  33643         -1,
  33644     },
  33645 #endif /* chips */
  33646 
  33647 #if defined(BCM_88690_A0)
  33648     { /* SOC_REG_INT_OAMP_SD_SF_SHARE_CFG_BCM88690_A0r */
  33649         soc_block_list[22],
  33650         soc_genreg,
  33651         1,
  33652         0,
  33653         0x8ff,
  33654         0,
  33655         0,
  33656         2,
  33657         soc_OAMP_SD_SF_SHARE_CFG_BCM88690_A0r_fields,
  33658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33659         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  33660         -1,
  33661         -1,
  33662     },
  33663 #endif /* chips */
  33664 
  33665 #if defined(BCM_88690_B0)
  33666     { /* SOC_REG_INT_OAMP_SD_SF_SHARE_CFG_BCM88690_B0r */
  33667         soc_block_list[22],
  33668         soc_genreg,
  33669         1,
  33670         0,
  33671         0x8ff,
  33672         0,
  33673         0,
  33674         2,
  33675         soc_OAMP_SD_SF_SHARE_CFG_BCM88690_B0r_fields,
  33676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33677         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  33678         -1,
  33679         -1,
  33680     },
  33681 #endif /* chips */
  33682 
  33683 #if defined(BCM_88470_A0)
  33684     { /* SOC_REG_INT_OAMP_SD_SF_Y_1711_CONFr */
  33685         soc_block_list[22],
  33686         soc_genreg,
  33687         1,
  33688         0,
  33689         0x824,
  33690         0,
  33691         0,
  33692         4,
  33693         soc_OAMP_SD_SF_Y_1711_CONFr_fields,
  33694         SOC_RESET_VAL_DEC(0x00002115, 0x00000000)
  33695         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  33696         -1,
  33697         -1,
  33698     },
  33699 #endif /* chips */
  33700 
  33701 #if defined(BCM_88270_A0)
  33702     { /* SOC_REG_INT_OAMP_SD_SF_Y_1711_CONF_BCM88270_A0r */
  33703         soc_block_list[22],
  33704         soc_genreg,
  33705         1,
  33706         0,
  33707         0x824,
  33708         0,
  33709         0,
  33710         4,
  33711         soc_OAMP_SD_SF_Y_1711_CONF_BCM88270_A0r_fields,
  33712         SOC_RESET_VAL_DEC(0x00002115, 0x00000000)
  33713         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  33714         -1,
  33715         -1,
  33716     },
  33717 #endif /* chips */
  33718 
  33719 #if defined(BCM_88470_B0)
  33720     { /* SOC_REG_INT_OAMP_SD_SF_Y_1711_CONF_BCM88470_B0r */
  33721         soc_block_list[22],
  33722         soc_genreg,
  33723         1,
  33724         0,
  33725         0x824,
  33726         0,
  33727         0,
  33728         4,
  33729         soc_OAMP_SD_SF_Y_1711_CONF_BCM88470_B0r_fields,
  33730         SOC_RESET_VAL_DEC(0x00002115, 0x00000000)
  33731         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  33732         -1,
  33733         -1,
  33734     },
  33735 #endif /* chips */
  33736 
  33737 #if defined(BCM_88690_B0)
  33738     { /* SOC_REG_INT_OAMP_SKIP_NEXT_BANKr */
  33739         soc_block_list[22],
  33740         soc_genreg,
  33741         1,
  33742         0,
  33743         0xb46,
  33744         0,
  33745         0,
  33746         4,
  33747         soc_OAMP_SKIP_NEXT_BANKr_fields,
  33748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33749         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  33750         -1,
  33751         -1,
  33752     },
  33753 #endif /* chips */
  33754 
  33755 #if defined(BCM_88675_A0)
  33756     { /* SOC_REG_INT_OAMP_SLM_CONFIGr */
  33757         soc_block_list[22],
  33758         soc_genreg,
  33759         1,
  33760         0,
  33761         0x46e,
  33762         0,
  33763         0,
  33764         1,
  33765         soc_OAMP_SLM_CONFIGr_fields,
  33766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33767         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33768         -1,
  33769         -1,
  33770     },
  33771 #endif /* chips */
  33772 
  33773 #if defined(BCM_88270_A0)
  33774     { /* SOC_REG_INT_OAMP_SLM_CONFIG_BCM88270_A0r */
  33775         soc_block_list[22],
  33776         soc_genreg,
  33777         1,
  33778         0,
  33779         0x46f,
  33780         0,
  33781         0,
  33782         1,
  33783         soc_OAMP_SLM_CONFIG_BCM88270_A0r_fields,
  33784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33785         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33786         -1,
  33787         -1,
  33788     },
  33789 #endif /* chips */
  33790 
  33791 #if defined(BCM_88375_A0)
  33792     { /* SOC_REG_INT_OAMP_SLM_CONFIG_BCM88375_A0r */
  33793         soc_block_list[22],
  33794         soc_genreg,
  33795         1,
  33796         0,
  33797         0x46e,
  33798         0,
  33799         0,
  33800         1,
  33801         soc_OAMP_SLM_CONFIG_BCM88375_A0r_fields,
  33802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33803         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33804         -1,
  33805         -1,
  33806     },
  33807 #endif /* chips */
  33808 
  33809 #if defined(BCM_88375_B0)
  33810     { /* SOC_REG_INT_OAMP_SLM_CONFIG_BCM88375_B0r */
  33811         soc_block_list[22],
  33812         soc_genreg,
  33813         1,
  33814         0,
  33815         0x46e,
  33816         0,
  33817         0,
  33818         1,
  33819         soc_OAMP_SLM_CONFIG_BCM88375_B0r_fields,
  33820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33822         -1,
  33823         -1,
  33824     },
  33825 #endif /* chips */
  33826 
  33827 #if defined(BCM_88470_A0)
  33828     { /* SOC_REG_INT_OAMP_SLM_CONFIG_BCM88470_A0r */
  33829         soc_block_list[22],
  33830         soc_genreg,
  33831         1,
  33832         0,
  33833         0x46f,
  33834         0,
  33835         0,
  33836         1,
  33837         soc_OAMP_SLM_CONFIG_BCM88470_A0r_fields,
  33838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33839         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33840         -1,
  33841         -1,
  33842     },
  33843 #endif /* chips */
  33844 
  33845 #if defined(BCM_88470_B0)
  33846     { /* SOC_REG_INT_OAMP_SLM_CONFIG_BCM88470_B0r */
  33847         soc_block_list[22],
  33848         soc_genreg,
  33849         1,
  33850         0,
  33851         0x46f,
  33852         0,
  33853         0,
  33854         1,
  33855         soc_OAMP_SLM_CONFIG_BCM88470_B0r_fields,
  33856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33858         -1,
  33859         -1,
  33860     },
  33861 #endif /* chips */
  33862 
  33863 #if defined(BCM_88675_B0)
  33864     { /* SOC_REG_INT_OAMP_SLM_CONFIG_BCM88675_B0r */
  33865         soc_block_list[22],
  33866         soc_genreg,
  33867         1,
  33868         0,
  33869         0x46e,
  33870         0,
  33871         0,
  33872         1,
  33873         soc_OAMP_SLM_CONFIG_BCM88675_B0r_fields,
  33874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33876         -1,
  33877         -1,
  33878     },
  33879 #endif /* chips */
  33880 
  33881 #if defined(BCM_88680_A0)
  33882     { /* SOC_REG_INT_OAMP_SLM_CONFIG_BCM88680_A0r */
  33883         soc_block_list[22],
  33884         soc_genreg,
  33885         1,
  33886         0,
  33887         0x46e,
  33888         0,
  33889         0,
  33890         1,
  33891         soc_OAMP_SLM_CONFIG_BCM88680_A0r_fields,
  33892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33893         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33894         -1,
  33895         -1,
  33896     },
  33897 #endif /* chips */
  33898 
  33899 #if defined(BCM_88690_A0)
  33900     { /* SOC_REG_INT_OAMP_SLM_CONFIG_BCM88690_A0r */
  33901         soc_block_list[22],
  33902         soc_genreg,
  33903         1,
  33904         0,
  33905         0x560,
  33906         0,
  33907         0,
  33908         1,
  33909         soc_OAMP_SLM_CONFIG_BCM88690_A0r_fields,
  33910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33912         -1,
  33913         -1,
  33914     },
  33915 #endif /* chips */
  33916 
  33917 #if defined(BCM_88690_B0)
  33918     { /* SOC_REG_INT_OAMP_SLM_CONFIG_BCM88690_B0r */
  33919         soc_block_list[22],
  33920         soc_genreg,
  33921         1,
  33922         0,
  33923         0x560,
  33924         0,
  33925         0,
  33926         1,
  33927         soc_OAMP_SLM_CONFIG_BCM88690_B0r_fields,
  33928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33929         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33930         -1,
  33931         -1,
  33932     },
  33933 #endif /* chips */
  33934 
  33935 #if defined(BCM_88690_A0)
  33936     { /* SOC_REG_INT_OAMP_SLM_MEASUREMENT_PERIOD_TIMERr */
  33937         soc_block_list[22],
  33938         soc_genreg,
  33939         1,
  33940         0,
  33941         0xb2d,
  33942         0,
  33943         0,
  33944         1,
  33945         soc_OAMP_SLM_MEASUREMENT_PERIOD_TIMERr_fields,
  33946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33947         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  33948         -1,
  33949         -1,
  33950     },
  33951 #endif /* chips */
  33952 
  33953 #if defined(BCM_88690_B0)
  33954     { /* SOC_REG_INT_OAMP_SLM_MEASUREMENT_PERIOD_TIMER_BCM88690_B0r */
  33955         soc_block_list[22],
  33956         soc_genreg,
  33957         1,
  33958         0,
  33959         0xb2e,
  33960         0,
  33961         0,
  33962         1,
  33963         soc_OAMP_SLM_MEASUREMENT_PERIOD_TIMER_BCM88690_B0r_fields,
  33964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33965         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  33966         -1,
  33967         -1,
  33968     },
  33969 #endif /* chips */
  33970 
  33971 #if defined(BCM_88650_B0)
  33972     { /* SOC_REG_INT_OAMP_SPARE_REGISTER_3r */
  33973         soc_block_list[22],
  33974         soc_genreg,
  33975         1,
  33976         0,
  33977         0x93,
  33978         SOC_REG_FLAG_SIGNAL,
  33979         0,
  33980         5,
  33981         soc_OAMP_SPARE_REGISTER_3r_fields,
  33982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33983         SOC_RESET_MASK_DEC(0xf8f8f8f9, 0x00000000)
  33984         -1,
  33985         -1,
  33986     },
  33987 #endif /* chips */
  33988 
  33989 #if defined(BCM_88660_A0)
  33990     { /* SOC_REG_INT_OAMP_SPARE_REGISTER_3_BCM88660_A0r */
  33991         soc_block_list[22],
  33992         soc_genreg,
  33993         1,
  33994         0,
  33995         0x93,
  33996         SOC_REG_FLAG_SIGNAL,
  33997         0,
  33998         1,
  33999         soc_OAMP_SPARE_REGISTER_3_BCM88660_A0r_fields,
  34000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34002         -1,
  34003         -1,
  34004     },
  34005 #endif /* chips */
  34006 
  34007 #if defined(BCM_88690_B0)
  34008     { /* SOC_REG_INT_OAMP_SPECIAL_CLOCK_CONTROLSr */
  34009         soc_block_list[22],
  34010         soc_genreg,
  34011         1,
  34012         0,
  34013         0xc1,
  34014         0,
  34015         0,
  34016         1,
  34017         soc_OAMP_SPECIAL_CLOCK_CONTROLSr_fields,
  34018         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  34019         SOC_RESET_MASK_DEC(0x00000002, 0x00000000)
  34020         -1,
  34021         -1,
  34022     },
  34023 #endif /* chips */
  34024 
  34025 #if defined(BCM_88690_A0)
  34026     { /* SOC_REG_INT_OAMP_SRC_IP_MISS_INFOr */
  34027         soc_block_list[22],
  34028         soc_genreg,
  34029         1,
  34030         0,
  34031         0xb11,
  34032         SOC_REG_FLAG_ABOVE_64_BITS |
  34033                           SOC_REG_FLAG_RO |
  34034                           SOC_REG_FLAG_SIGNAL,
  34035         SOC_REG_FLAG_INIT_ON_READ,
  34036         4,
  34037         soc_OAMP_SRC_IP_MISS_INFOr_fields,
  34038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34040         -1,
  34041         -1,
  34042     },
  34043 #endif /* chips */
  34044 
  34045 #if defined(BCM_88690_B0)
  34046     { /* SOC_REG_INT_OAMP_SRC_IP_MISS_INFO_BCM88690_B0r */
  34047         soc_block_list[22],
  34048         soc_genreg,
  34049         1,
  34050         0,
  34051         0xb11,
  34052         SOC_REG_FLAG_ABOVE_64_BITS |
  34053                           SOC_REG_FLAG_RO |
  34054                           SOC_REG_FLAG_SIGNAL,
  34055         SOC_REG_FLAG_INIT_ON_READ,
  34056         4,
  34057         soc_OAMP_SRC_IP_MISS_INFO_BCM88690_B0r_fields,
  34058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34059         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34060         -1,
  34061         -1,
  34062     },
  34063 #endif /* chips */
  34064 
  34065 #if defined(BCM_88690_A0)
  34066     { /* SOC_REG_INT_OAMP_SRC_PORT_MISS_INFOr */
  34067         soc_block_list[22],
  34068         soc_genreg,
  34069         1,
  34070         0,
  34071         0xb15,
  34072         SOC_REG_FLAG_RO |
  34073                           SOC_REG_FLAG_SIGNAL,
  34074         SOC_REG_FLAG_INIT_ON_READ,
  34075         1,
  34076         soc_OAMP_SRC_PORT_MISS_INFOr_fields,
  34077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34078         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  34079         -1,
  34080         -1,
  34081     },
  34082 #endif /* chips */
  34083 
  34084 #if defined(BCM_88690_B0)
  34085     { /* SOC_REG_INT_OAMP_SRC_PORT_MISS_INFO_BCM88690_B0r */
  34086         soc_block_list[22],
  34087         soc_genreg,
  34088         1,
  34089         0,
  34090         0xb15,
  34091         SOC_REG_FLAG_RO |
  34092                           SOC_REG_FLAG_SIGNAL,
  34093         SOC_REG_FLAG_INIT_ON_READ,
  34094         1,
  34095         soc_OAMP_SRC_PORT_MISS_INFO_BCM88690_B0r_fields,
  34096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34097         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  34098         -1,
  34099         -1,
  34100     },
  34101 #endif /* chips */
  34102 
  34103 #if defined(BCM_88650_A0)
  34104     { /* SOC_REG_INT_OAMP_STATUS_1_REGr */
  34105         soc_block_list[22],
  34106         soc_genreg,
  34107         1,
  34108         0,
  34109         0x122,
  34110         SOC_REG_FLAG_RO,
  34111         0,
  34112         4,
  34113         soc_OAMP_STATUS_1_REGr_fields,
  34114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34115         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34116         -1,
  34117         -1,
  34118     },
  34119 #endif /* chips */
  34120 
  34121 #if defined(BCM_88270_A0)
  34122     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88270_A0r */
  34123         soc_block_list[22],
  34124         soc_genreg,
  34125         1,
  34126         0,
  34127         0x132,
  34128         SOC_REG_FLAG_RO |
  34129                           SOC_REG_FLAG_SIGNAL,
  34130         0,
  34131         4,
  34132         soc_OAMP_STATUS_1_REG_BCM88270_A0r_fields,
  34133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34134         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34135         -1,
  34136         -1,
  34137     },
  34138 #endif /* chips */
  34139 
  34140 #if defined(BCM_88375_A0)
  34141     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88375_A0r */
  34142         soc_block_list[22],
  34143         soc_genreg,
  34144         1,
  34145         0,
  34146         0x132,
  34147         SOC_REG_FLAG_RO |
  34148                           SOC_REG_FLAG_SIGNAL,
  34149         0,
  34150         4,
  34151         soc_OAMP_STATUS_1_REG_BCM88375_A0r_fields,
  34152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34153         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34154         -1,
  34155         -1,
  34156     },
  34157 #endif /* chips */
  34158 
  34159 #if defined(BCM_88375_B0)
  34160     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88375_B0r */
  34161         soc_block_list[22],
  34162         soc_genreg,
  34163         1,
  34164         0,
  34165         0x132,
  34166         SOC_REG_FLAG_RO |
  34167                           SOC_REG_FLAG_SIGNAL,
  34168         0,
  34169         4,
  34170         soc_OAMP_STATUS_1_REG_BCM88375_B0r_fields,
  34171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34172         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34173         -1,
  34174         -1,
  34175     },
  34176 #endif /* chips */
  34177 
  34178 #if defined(BCM_88470_A0)
  34179     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88470_A0r */
  34180         soc_block_list[22],
  34181         soc_genreg,
  34182         1,
  34183         0,
  34184         0x132,
  34185         SOC_REG_FLAG_RO |
  34186                           SOC_REG_FLAG_SIGNAL,
  34187         0,
  34188         4,
  34189         soc_OAMP_STATUS_1_REG_BCM88470_A0r_fields,
  34190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34191         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34192         -1,
  34193         -1,
  34194     },
  34195 #endif /* chips */
  34196 
  34197 #if defined(BCM_88470_B0)
  34198     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88470_B0r */
  34199         soc_block_list[22],
  34200         soc_genreg,
  34201         1,
  34202         0,
  34203         0x132,
  34204         SOC_REG_FLAG_RO |
  34205                           SOC_REG_FLAG_SIGNAL,
  34206         0,
  34207         4,
  34208         soc_OAMP_STATUS_1_REG_BCM88470_B0r_fields,
  34209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34210         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34211         -1,
  34212         -1,
  34213     },
  34214 #endif /* chips */
  34215 
  34216 #if defined(BCM_88650_B0)
  34217     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88650_B0r */
  34218         soc_block_list[22],
  34219         soc_genreg,
  34220         1,
  34221         0,
  34222         0x122,
  34223         SOC_REG_FLAG_RO,
  34224         0,
  34225         4,
  34226         soc_OAMP_STATUS_1_REG_BCM88650_B0r_fields,
  34227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34228         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34229         -1,
  34230         -1,
  34231     },
  34232 #endif /* chips */
  34233 
  34234 #if defined(BCM_88660_A0)
  34235     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88660_A0r */
  34236         soc_block_list[22],
  34237         soc_genreg,
  34238         1,
  34239         0,
  34240         0x122,
  34241         SOC_REG_FLAG_RO,
  34242         0,
  34243         4,
  34244         soc_OAMP_STATUS_1_REG_BCM88660_A0r_fields,
  34245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34246         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34247         -1,
  34248         -1,
  34249     },
  34250 #endif /* chips */
  34251 
  34252 #if defined(BCM_88675_A0)
  34253     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88675_A0r */
  34254         soc_block_list[22],
  34255         soc_genreg,
  34256         1,
  34257         0,
  34258         0x132,
  34259         SOC_REG_FLAG_RO |
  34260                           SOC_REG_FLAG_SIGNAL,
  34261         0,
  34262         4,
  34263         soc_OAMP_STATUS_1_REG_BCM88675_A0r_fields,
  34264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34265         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34266         -1,
  34267         -1,
  34268     },
  34269 #endif /* chips */
  34270 
  34271 #if defined(BCM_88675_B0)
  34272     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88675_B0r */
  34273         soc_block_list[22],
  34274         soc_genreg,
  34275         1,
  34276         0,
  34277         0x132,
  34278         SOC_REG_FLAG_RO |
  34279                           SOC_REG_FLAG_SIGNAL,
  34280         0,
  34281         4,
  34282         soc_OAMP_STATUS_1_REG_BCM88675_B0r_fields,
  34283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34284         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34285         -1,
  34286         -1,
  34287     },
  34288 #endif /* chips */
  34289 
  34290 #if defined(BCM_88680_A0)
  34291     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88680_A0r */
  34292         soc_block_list[22],
  34293         soc_genreg,
  34294         1,
  34295         0,
  34296         0x132,
  34297         SOC_REG_FLAG_RO |
  34298                           SOC_REG_FLAG_SIGNAL,
  34299         0,
  34300         4,
  34301         soc_OAMP_STATUS_1_REG_BCM88680_A0r_fields,
  34302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34303         SOC_RESET_MASK_DEC(0xff000ffc, 0x00000000)
  34304         -1,
  34305         -1,
  34306     },
  34307 #endif /* chips */
  34308 
  34309 #if defined(BCM_88690_A0)
  34310     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88690_A0r */
  34311         soc_block_list[22],
  34312         soc_genreg,
  34313         1,
  34314         0,
  34315         0x12d,
  34316         SOC_REG_FLAG_RO |
  34317                           SOC_REG_FLAG_SIGNAL,
  34318         SOC_REG_FLAG_INIT_ON_READ,
  34319         5,
  34320         soc_OAMP_STATUS_1_REG_BCM88690_A0r_fields,
  34321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34322         SOC_RESET_MASK_DEC(0x0ffffffc, 0x00000000)
  34323         -1,
  34324         -1,
  34325     },
  34326 #endif /* chips */
  34327 
  34328 #if defined(BCM_88690_B0)
  34329     { /* SOC_REG_INT_OAMP_STATUS_1_REG_BCM88690_B0r */
  34330         soc_block_list[22],
  34331         soc_genreg,
  34332         1,
  34333         0,
  34334         0x12d,
  34335         SOC_REG_FLAG_RO |
  34336                           SOC_REG_FLAG_SIGNAL,
  34337         SOC_REG_FLAG_INIT_ON_READ,
  34338         5,
  34339         soc_OAMP_STATUS_1_REG_BCM88690_B0r_fields,
  34340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34341         SOC_RESET_MASK_DEC(0x0ffffffc, 0x00000000)
  34342         -1,
  34343         -1,
  34344     },
  34345 #endif /* chips */
  34346 
  34347 #if defined(BCM_88675_A0)
  34348     { /* SOC_REG_INT_OAMP_STATUS_2_REGr */
  34349         soc_block_list[22],
  34350         soc_genreg,
  34351         1,
  34352         0,
  34353         0x133,
  34354         SOC_REG_FLAG_RO |
  34355                           SOC_REG_FLAG_SIGNAL,
  34356         0,
  34357         2,
  34358         soc_OAMP_STATUS_2_REGr_fields,
  34359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34360         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34361         -1,
  34362         -1,
  34363     },
  34364 #endif /* chips */
  34365 
  34366 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  34367     defined(BCM_56270_A0)
  34368     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM56260_A0r */
  34369         soc_block_list[22],
  34370         soc_genreg,
  34371         1,
  34372         0,
  34373         0x2010400,
  34374         SOC_REG_FLAG_RO,
  34375         0,
  34376         1,
  34377         soc_OAMP_STATUS_2_REG_BCM56260_A0r_fields,
  34378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34379         SOC_RESET_MASK_DEC(0x000007f8, 0x00000000)
  34380         -1,
  34381         -1,
  34382     },
  34383 #endif /* chips */
  34384 
  34385 #if defined(BCM_88270_A0)
  34386     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM88270_A0r */
  34387         soc_block_list[22],
  34388         soc_genreg,
  34389         1,
  34390         0,
  34391         0x133,
  34392         SOC_REG_FLAG_RO |
  34393                           SOC_REG_FLAG_SIGNAL,
  34394         0,
  34395         2,
  34396         soc_OAMP_STATUS_2_REG_BCM88270_A0r_fields,
  34397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34398         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34399         -1,
  34400         -1,
  34401     },
  34402 #endif /* chips */
  34403 
  34404 #if defined(BCM_88375_A0)
  34405     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM88375_A0r */
  34406         soc_block_list[22],
  34407         soc_genreg,
  34408         1,
  34409         0,
  34410         0x133,
  34411         SOC_REG_FLAG_RO |
  34412                           SOC_REG_FLAG_SIGNAL,
  34413         0,
  34414         2,
  34415         soc_OAMP_STATUS_2_REG_BCM88375_A0r_fields,
  34416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34417         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34418         -1,
  34419         -1,
  34420     },
  34421 #endif /* chips */
  34422 
  34423 #if defined(BCM_88375_B0)
  34424     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM88375_B0r */
  34425         soc_block_list[22],
  34426         soc_genreg,
  34427         1,
  34428         0,
  34429         0x133,
  34430         SOC_REG_FLAG_RO |
  34431                           SOC_REG_FLAG_SIGNAL,
  34432         0,
  34433         2,
  34434         soc_OAMP_STATUS_2_REG_BCM88375_B0r_fields,
  34435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34436         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34437         -1,
  34438         -1,
  34439     },
  34440 #endif /* chips */
  34441 
  34442 #if defined(BCM_88470_A0)
  34443     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM88470_A0r */
  34444         soc_block_list[22],
  34445         soc_genreg,
  34446         1,
  34447         0,
  34448         0x133,
  34449         SOC_REG_FLAG_RO |
  34450                           SOC_REG_FLAG_SIGNAL,
  34451         0,
  34452         2,
  34453         soc_OAMP_STATUS_2_REG_BCM88470_A0r_fields,
  34454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34455         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34456         -1,
  34457         -1,
  34458     },
  34459 #endif /* chips */
  34460 
  34461 #if defined(BCM_88470_B0)
  34462     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM88470_B0r */
  34463         soc_block_list[22],
  34464         soc_genreg,
  34465         1,
  34466         0,
  34467         0x133,
  34468         SOC_REG_FLAG_RO |
  34469                           SOC_REG_FLAG_SIGNAL,
  34470         0,
  34471         2,
  34472         soc_OAMP_STATUS_2_REG_BCM88470_B0r_fields,
  34473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34474         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34475         -1,
  34476         -1,
  34477     },
  34478 #endif /* chips */
  34479 
  34480 #if defined(BCM_88675_B0)
  34481     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM88675_B0r */
  34482         soc_block_list[22],
  34483         soc_genreg,
  34484         1,
  34485         0,
  34486         0x133,
  34487         SOC_REG_FLAG_RO |
  34488                           SOC_REG_FLAG_SIGNAL,
  34489         0,
  34490         2,
  34491         soc_OAMP_STATUS_2_REG_BCM88675_B0r_fields,
  34492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34493         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34494         -1,
  34495         -1,
  34496     },
  34497 #endif /* chips */
  34498 
  34499 #if defined(BCM_88680_A0)
  34500     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM88680_A0r */
  34501         soc_block_list[22],
  34502         soc_genreg,
  34503         1,
  34504         0,
  34505         0x133,
  34506         SOC_REG_FLAG_RO |
  34507                           SOC_REG_FLAG_SIGNAL,
  34508         0,
  34509         2,
  34510         soc_OAMP_STATUS_2_REG_BCM88680_A0r_fields,
  34511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34512         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34513         -1,
  34514         -1,
  34515     },
  34516 #endif /* chips */
  34517 
  34518 #if defined(BCM_88690_A0)
  34519     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM88690_A0r */
  34520         soc_block_list[22],
  34521         soc_genreg,
  34522         1,
  34523         0,
  34524         0x12e,
  34525         SOC_REG_FLAG_RO |
  34526                           SOC_REG_FLAG_SIGNAL,
  34527         0,
  34528         2,
  34529         soc_OAMP_STATUS_2_REG_BCM88690_A0r_fields,
  34530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34531         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34532         -1,
  34533         -1,
  34534     },
  34535 #endif /* chips */
  34536 
  34537 #if defined(BCM_88690_B0)
  34538     { /* SOC_REG_INT_OAMP_STATUS_2_REG_BCM88690_B0r */
  34539         soc_block_list[22],
  34540         soc_genreg,
  34541         1,
  34542         0,
  34543         0x12e,
  34544         SOC_REG_FLAG_RO |
  34545                           SOC_REG_FLAG_SIGNAL,
  34546         0,
  34547         2,
  34548         soc_OAMP_STATUS_2_REG_BCM88690_B0r_fields,
  34549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34550         SOC_RESET_MASK_DEC(0x000007fc, 0x00000000)
  34551         -1,
  34552         -1,
  34553     },
  34554 #endif /* chips */
  34555 
  34556 #if defined(BCM_88675_A0)
  34557     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGEr */
  34558         soc_block_list[22],
  34559         soc_genreg,
  34560         1,
  34561         0,
  34562         0x154,
  34563         SOC_REG_FLAG_ABOVE_64_BITS |
  34564                           SOC_REG_FLAG_RO |
  34565                           SOC_REG_FLAG_INTERRUPT |
  34566                           SOC_REG_FLAG_SIGNAL,
  34567         0,
  34568         1,
  34569         soc_OAMP_STAT_INTERRUPT_MESSAGEr_fields,
  34570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34572         -1,
  34573         -1,
  34574     },
  34575 #endif /* chips */
  34576 
  34577 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  34578     defined(BCM_56270_A0)
  34579     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM56260_A0r */
  34580         soc_block_list[22],
  34581         soc_genreg,
  34582         1,
  34583         0,
  34584         0x2010700,
  34585         SOC_REG_FLAG_ABOVE_64_BITS |
  34586                           SOC_REG_FLAG_RO,
  34587         0,
  34588         1,
  34589         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM56260_A0r_fields,
  34590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34592         -1,
  34593         -1,
  34594     },
  34595 #endif /* chips */
  34596 
  34597 #if defined(BCM_88270_A0)
  34598     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM88270_A0r */
  34599         soc_block_list[22],
  34600         soc_genreg,
  34601         1,
  34602         0,
  34603         0x156,
  34604         SOC_REG_FLAG_ABOVE_64_BITS |
  34605                           SOC_REG_FLAG_RO |
  34606                           SOC_REG_FLAG_INTERRUPT |
  34607                           SOC_REG_FLAG_SIGNAL,
  34608         0,
  34609         1,
  34610         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM88270_A0r_fields,
  34611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34613         -1,
  34614         -1,
  34615     },
  34616 #endif /* chips */
  34617 
  34618 #if defined(BCM_88375_A0)
  34619     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM88375_A0r */
  34620         soc_block_list[22],
  34621         soc_genreg,
  34622         1,
  34623         0,
  34624         0x154,
  34625         SOC_REG_FLAG_ABOVE_64_BITS |
  34626                           SOC_REG_FLAG_RO |
  34627                           SOC_REG_FLAG_INTERRUPT |
  34628                           SOC_REG_FLAG_SIGNAL,
  34629         0,
  34630         1,
  34631         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM88375_A0r_fields,
  34632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34634         -1,
  34635         -1,
  34636     },
  34637 #endif /* chips */
  34638 
  34639 #if defined(BCM_88375_B0)
  34640     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM88375_B0r */
  34641         soc_block_list[22],
  34642         soc_genreg,
  34643         1,
  34644         0,
  34645         0x154,
  34646         SOC_REG_FLAG_ABOVE_64_BITS |
  34647                           SOC_REG_FLAG_RO |
  34648                           SOC_REG_FLAG_INTERRUPT |
  34649                           SOC_REG_FLAG_SIGNAL,
  34650         0,
  34651         1,
  34652         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM88375_B0r_fields,
  34653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34654         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34655         -1,
  34656         -1,
  34657     },
  34658 #endif /* chips */
  34659 
  34660 #if defined(BCM_88470_A0)
  34661     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM88470_A0r */
  34662         soc_block_list[22],
  34663         soc_genreg,
  34664         1,
  34665         0,
  34666         0x156,
  34667         SOC_REG_FLAG_ABOVE_64_BITS |
  34668                           SOC_REG_FLAG_RO |
  34669                           SOC_REG_FLAG_INTERRUPT |
  34670                           SOC_REG_FLAG_SIGNAL,
  34671         0,
  34672         1,
  34673         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM88470_A0r_fields,
  34674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34676         -1,
  34677         -1,
  34678     },
  34679 #endif /* chips */
  34680 
  34681 #if defined(BCM_88470_B0)
  34682     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM88470_B0r */
  34683         soc_block_list[22],
  34684         soc_genreg,
  34685         1,
  34686         0,
  34687         0x156,
  34688         SOC_REG_FLAG_ABOVE_64_BITS |
  34689                           SOC_REG_FLAG_RO |
  34690                           SOC_REG_FLAG_INTERRUPT |
  34691                           SOC_REG_FLAG_SIGNAL,
  34692         0,
  34693         1,
  34694         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM88470_B0r_fields,
  34695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34696         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34697         -1,
  34698         -1,
  34699     },
  34700 #endif /* chips */
  34701 
  34702 #if defined(BCM_88675_B0)
  34703     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM88675_B0r */
  34704         soc_block_list[22],
  34705         soc_genreg,
  34706         1,
  34707         0,
  34708         0x154,
  34709         SOC_REG_FLAG_ABOVE_64_BITS |
  34710                           SOC_REG_FLAG_RO |
  34711                           SOC_REG_FLAG_INTERRUPT |
  34712                           SOC_REG_FLAG_SIGNAL,
  34713         0,
  34714         1,
  34715         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM88675_B0r_fields,
  34716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34718         -1,
  34719         -1,
  34720     },
  34721 #endif /* chips */
  34722 
  34723 #if defined(BCM_88680_A0)
  34724     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM88680_A0r */
  34725         soc_block_list[22],
  34726         soc_genreg,
  34727         1,
  34728         0,
  34729         0x154,
  34730         SOC_REG_FLAG_ABOVE_64_BITS |
  34731                           SOC_REG_FLAG_RO |
  34732                           SOC_REG_FLAG_INTERRUPT |
  34733                           SOC_REG_FLAG_SIGNAL,
  34734         0,
  34735         1,
  34736         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM88680_A0r_fields,
  34737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34738         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34739         -1,
  34740         -1,
  34741     },
  34742 #endif /* chips */
  34743 
  34744 #if defined(BCM_88690_A0)
  34745     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM88690_A0r */
  34746         soc_block_list[22],
  34747         soc_genreg,
  34748         1,
  34749         0,
  34750         0x151,
  34751         SOC_REG_FLAG_ABOVE_64_BITS |
  34752                           SOC_REG_FLAG_RO |
  34753                           SOC_REG_FLAG_INTERRUPT |
  34754                           SOC_REG_FLAG_SIGNAL,
  34755         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  34756         1,
  34757         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM88690_A0r_fields,
  34758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34760         -1,
  34761         -1,
  34762     },
  34763 #endif /* chips */
  34764 
  34765 #if defined(BCM_88690_B0)
  34766     { /* SOC_REG_INT_OAMP_STAT_INTERRUPT_MESSAGE_BCM88690_B0r */
  34767         soc_block_list[22],
  34768         soc_genreg,
  34769         1,
  34770         0,
  34771         0x151,
  34772         SOC_REG_FLAG_ABOVE_64_BITS |
  34773                           SOC_REG_FLAG_RO |
  34774                           SOC_REG_FLAG_INTERRUPT |
  34775                           SOC_REG_FLAG_SIGNAL,
  34776         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  34777         1,
  34778         soc_OAMP_STAT_INTERRUPT_MESSAGE_BCM88690_B0r_fields,
  34779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34781         -1,
  34782         -1,
  34783     },
  34784 #endif /* chips */
  34785 
  34786 #if defined(BCM_88650_A0)
  34787     { /* SOC_REG_INT_OAMP_TIMER_CONFIGr */
  34788         soc_block_list[22],
  34789         soc_genreg,
  34790         1,
  34791         0,
  34792         0x123,
  34793         SOC_REG_FLAG_SIGNAL,
  34794         0,
  34795         2,
  34796         soc_OAMP_TIMER_CONFIGr_fields,
  34797         SOC_RESET_VAL_DEC(0x00196e6a, 0x00000000)
  34798         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34799         -1,
  34800         -1,
  34801     },
  34802 #endif /* chips */
  34803 
  34804 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  34805     defined(BCM_56270_A0)
  34806     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM56260_A0r */
  34807         soc_block_list[22],
  34808         soc_genreg,
  34809         1,
  34810         0,
  34811         0x2010500,
  34812         SOC_REG_FLAG_64_BITS,
  34813         0,
  34814         2,
  34815         soc_OAMP_TIMER_CONFIG_BCM56260_A0r_fields,
  34816         SOC_RESET_VAL_DEC(0x00124f80, 0x000aba95)
  34817         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  34818         -1,
  34819         -1,
  34820     },
  34821 #endif /* chips */
  34822 
  34823 #if defined(BCM_88270_A0)
  34824     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88270_A0r */
  34825         soc_block_list[22],
  34826         soc_genreg,
  34827         1,
  34828         0,
  34829         0x134,
  34830         SOC_REG_FLAG_64_BITS,
  34831         0,
  34832         2,
  34833         soc_OAMP_TIMER_CONFIG_BCM88270_A0r_fields,
  34834         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  34835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  34836         -1,
  34837         -1,
  34838     },
  34839 #endif /* chips */
  34840 
  34841 #if defined(BCM_88375_A0)
  34842     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88375_A0r */
  34843         soc_block_list[22],
  34844         soc_genreg,
  34845         1,
  34846         0,
  34847         0x134,
  34848         SOC_REG_FLAG_64_BITS,
  34849         0,
  34850         4,
  34851         soc_OAMP_TIMER_CONFIG_BCM88375_A0r_fields,
  34852         SOC_RESET_VAL_DEC(0x04924f80, 0x0aba9500)
  34853         SOC_RESET_MASK_DEC(0xffffffff, 0x3fffffff)
  34854         -1,
  34855         -1,
  34856     },
  34857 #endif /* chips */
  34858 
  34859 #if defined(BCM_88375_B0)
  34860     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88375_B0r */
  34861         soc_block_list[22],
  34862         soc_genreg,
  34863         1,
  34864         0,
  34865         0x134,
  34866         SOC_REG_FLAG_64_BITS,
  34867         0,
  34868         4,
  34869         soc_OAMP_TIMER_CONFIG_BCM88375_B0r_fields,
  34870         SOC_RESET_VAL_DEC(0x04924f80, 0x0aba9500)
  34871         SOC_RESET_MASK_DEC(0xffffffff, 0x3fffffff)
  34872         -1,
  34873         -1,
  34874     },
  34875 #endif /* chips */
  34876 
  34877 #if defined(BCM_88470_A0)
  34878     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88470_A0r */
  34879         soc_block_list[22],
  34880         soc_genreg,
  34881         1,
  34882         0,
  34883         0x134,
  34884         SOC_REG_FLAG_64_BITS,
  34885         0,
  34886         2,
  34887         soc_OAMP_TIMER_CONFIG_BCM88470_A0r_fields,
  34888         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  34889         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  34890         -1,
  34891         -1,
  34892     },
  34893 #endif /* chips */
  34894 
  34895 #if defined(BCM_88470_B0)
  34896     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88470_B0r */
  34897         soc_block_list[22],
  34898         soc_genreg,
  34899         1,
  34900         0,
  34901         0x134,
  34902         SOC_REG_FLAG_64_BITS,
  34903         0,
  34904         2,
  34905         soc_OAMP_TIMER_CONFIG_BCM88470_B0r_fields,
  34906         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  34907         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  34908         -1,
  34909         -1,
  34910     },
  34911 #endif /* chips */
  34912 
  34913 #if defined(BCM_88650_B0)
  34914     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88650_B0r */
  34915         soc_block_list[22],
  34916         soc_genreg,
  34917         1,
  34918         0,
  34919         0x123,
  34920         SOC_REG_FLAG_SIGNAL,
  34921         0,
  34922         2,
  34923         soc_OAMP_TIMER_CONFIG_BCM88650_B0r_fields,
  34924         SOC_RESET_VAL_DEC(0x00196e6a, 0x00000000)
  34925         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34926         -1,
  34927         -1,
  34928     },
  34929 #endif /* chips */
  34930 
  34931 #if defined(BCM_88660_A0)
  34932     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88660_A0r */
  34933         soc_block_list[22],
  34934         soc_genreg,
  34935         1,
  34936         0,
  34937         0x123,
  34938         SOC_REG_FLAG_SIGNAL,
  34939         0,
  34940         2,
  34941         soc_OAMP_TIMER_CONFIG_BCM88660_A0r_fields,
  34942         SOC_RESET_VAL_DEC(0x00196e6a, 0x00000000)
  34943         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34944         -1,
  34945         -1,
  34946     },
  34947 #endif /* chips */
  34948 
  34949 #if defined(BCM_88675_A0)
  34950     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88675_A0r */
  34951         soc_block_list[22],
  34952         soc_genreg,
  34953         1,
  34954         0,
  34955         0x134,
  34956         SOC_REG_FLAG_64_BITS,
  34957         0,
  34958         4,
  34959         soc_OAMP_TIMER_CONFIG_BCM88675_A0r_fields,
  34960         SOC_RESET_VAL_DEC(0x04924f80, 0x0aba9500)
  34961         SOC_RESET_MASK_DEC(0xffffffff, 0x3fffffff)
  34962         -1,
  34963         -1,
  34964     },
  34965 #endif /* chips */
  34966 
  34967 #if defined(BCM_88675_B0)
  34968     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88675_B0r */
  34969         soc_block_list[22],
  34970         soc_genreg,
  34971         1,
  34972         0,
  34973         0x134,
  34974         SOC_REG_FLAG_64_BITS,
  34975         0,
  34976         4,
  34977         soc_OAMP_TIMER_CONFIG_BCM88675_B0r_fields,
  34978         SOC_RESET_VAL_DEC(0x04924f80, 0x0aba9500)
  34979         SOC_RESET_MASK_DEC(0xffffffff, 0x3fffffff)
  34980         -1,
  34981         -1,
  34982     },
  34983 #endif /* chips */
  34984 
  34985 #if defined(BCM_88680_A0)
  34986     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88680_A0r */
  34987         soc_block_list[22],
  34988         soc_genreg,
  34989         1,
  34990         0,
  34991         0x134,
  34992         SOC_REG_FLAG_64_BITS,
  34993         0,
  34994         4,
  34995         soc_OAMP_TIMER_CONFIG_BCM88680_A0r_fields,
  34996         SOC_RESET_VAL_DEC(0x04924f80, 0x0aba9500)
  34997         SOC_RESET_MASK_DEC(0xffffffff, 0x3fffffff)
  34998         -1,
  34999         -1,
  35000     },
  35001 #endif /* chips */
  35002 
  35003 #if defined(BCM_88690_A0)
  35004     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88690_A0r */
  35005         soc_block_list[22],
  35006         soc_genreg,
  35007         1,
  35008         0,
  35009         0x12f,
  35010         SOC_REG_FLAG_64_BITS,
  35011         0,
  35012         2,
  35013         soc_OAMP_TIMER_CONFIG_BCM88690_A0r_fields,
  35014         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  35015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  35016         -1,
  35017         -1,
  35018     },
  35019 #endif /* chips */
  35020 
  35021 #if defined(BCM_88690_B0)
  35022     { /* SOC_REG_INT_OAMP_TIMER_CONFIG_BCM88690_B0r */
  35023         soc_block_list[22],
  35024         soc_genreg,
  35025         1,
  35026         0,
  35027         0x12f,
  35028         SOC_REG_FLAG_64_BITS,
  35029         0,
  35030         2,
  35031         soc_OAMP_TIMER_CONFIG_BCM88690_B0r_fields,
  35032         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  35033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  35034         -1,
  35035         -1,
  35036     },
  35037 #endif /* chips */
  35038 
  35039 #if defined(BCM_88690_A0)
  35040     { /* SOC_REG_INT_OAMP_TRAP_CODE_MISS_INFOr */
  35041         soc_block_list[22],
  35042         soc_genreg,
  35043         1,
  35044         0,
  35045         0xb0c,
  35046         SOC_REG_FLAG_RO |
  35047                           SOC_REG_FLAG_SIGNAL,
  35048         SOC_REG_FLAG_INIT_ON_READ,
  35049         2,
  35050         soc_OAMP_TRAP_CODE_MISS_INFOr_fields,
  35051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35052         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35053         -1,
  35054         -1,
  35055     },
  35056 #endif /* chips */
  35057 
  35058 #if defined(BCM_88690_B0)
  35059     { /* SOC_REG_INT_OAMP_TRAP_CODE_MISS_INFO_BCM88690_B0r */
  35060         soc_block_list[22],
  35061         soc_genreg,
  35062         1,
  35063         0,
  35064         0xb0c,
  35065         SOC_REG_FLAG_RO |
  35066                           SOC_REG_FLAG_SIGNAL,
  35067         SOC_REG_FLAG_INIT_ON_READ,
  35068         2,
  35069         soc_OAMP_TRAP_CODE_MISS_INFO_BCM88690_B0r_fields,
  35070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35071         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35072         -1,
  35073         -1,
  35074     },
  35075 #endif /* chips */
  35076 
  35077 #if defined(BCM_88660_A0)
  35078     { /* SOC_REG_INT_OAMP_TST_LBM_CTRLr */
  35079         soc_block_list[22],
  35080         soc_genreg,
  35081         1,
  35082         0,
  35083         0x47a,
  35084         SOC_REG_FLAG_ABOVE_64_BITS |
  35085                           SOC_REG_FLAG_SIGNAL,
  35086         0,
  35087         13,
  35088         soc_OAMP_TST_LBM_CTRLr_fields,
  35089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35091         -1,
  35092         -1,
  35093     },
  35094 #endif /* chips */
  35095 
  35096 #if defined(BCM_88660_A0)
  35097     { /* SOC_REG_INT_OAMP_TST_LBM_PACKET_HEADERr */
  35098         soc_block_list[22],
  35099         soc_genreg,
  35100         1,
  35101         0,
  35102         0x465,
  35103         SOC_REG_FLAG_ABOVE_64_BITS |
  35104                           SOC_REG_FLAG_SIGNAL,
  35105         0,
  35106         1,
  35107         soc_OAMP_TST_LBM_PACKET_HEADERr_fields,
  35108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35110         -1,
  35111         -1,
  35112     },
  35113 #endif /* chips */
  35114 
  35115 #if defined(BCM_88660_A0)
  35116     { /* SOC_REG_INT_OAMP_TST_LBM_PACKET_HEADER_NUM_OF_BYTESr */
  35117         soc_block_list[22],
  35118         soc_genreg,
  35119         1,
  35120         0,
  35121         0x479,
  35122         SOC_REG_FLAG_SIGNAL,
  35123         0,
  35124         1,
  35125         soc_OAMP_TST_LBM_PACKET_HEADER_NUM_OF_BYTESr_fields,
  35126         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  35127         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  35128         -1,
  35129         -1,
  35130     },
  35131 #endif /* chips */
  35132 
  35133 #if defined(BCM_88660_A0)
  35134     { /* SOC_REG_INT_OAMP_TST_LBM_STATUSr */
  35135         soc_block_list[22],
  35136         soc_genreg,
  35137         1,
  35138         0,
  35139         0x47d,
  35140         SOC_REG_FLAG_ABOVE_64_BITS |
  35141                           SOC_REG_FLAG_RO,
  35142         0,
  35143         3,
  35144         soc_OAMP_TST_LBM_STATUSr_fields,
  35145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35146         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35147         -1,
  35148         -1,
  35149     },
  35150 #endif /* chips */
  35151 
  35152 #if defined(BCM_88470_A0)
  35153     { /* SOC_REG_INT_OAMP_TXM_BANK_SCAN_CONFIGr */
  35154         soc_block_list[22],
  35155         soc_genreg,
  35156         12,
  35157         0,
  35158         0x136,
  35159         SOC_REG_FLAG_ARRAY |
  35160                           SOC_REG_FLAG_REG_ARRAY,
  35161         0,
  35162         4,
  35163         soc_OAMP_TXM_BANK_SCAN_CONFIGr_fields,
  35164         SOC_RESET_VAL_DEC(0x124f8012, 0x00000000)
  35165         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  35166         -1,
  35167         -1,
  35168     },
  35169 #endif /* chips */
  35170 
  35171 #if defined(BCM_88270_A0)
  35172     { /* SOC_REG_INT_OAMP_TXM_BANK_SCAN_CONFIG_BCM88270_A0r */
  35173         soc_block_list[22],
  35174         soc_genreg,
  35175         12,
  35176         0,
  35177         0x136,
  35178         SOC_REG_FLAG_ARRAY |
  35179                           SOC_REG_FLAG_REG_ARRAY,
  35180         0,
  35181         4,
  35182         soc_OAMP_TXM_BANK_SCAN_CONFIG_BCM88270_A0r_fields,
  35183         SOC_RESET_VAL_DEC(0x124f8012, 0x00000000)
  35184         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  35185         -1,
  35186         -1,
  35187     },
  35188 #endif /* chips */
  35189 
  35190 #if defined(BCM_88470_B0)
  35191     { /* SOC_REG_INT_OAMP_TXM_BANK_SCAN_CONFIG_BCM88470_B0r */
  35192         soc_block_list[22],
  35193         soc_genreg,
  35194         12,
  35195         0,
  35196         0x136,
  35197         SOC_REG_FLAG_ARRAY |
  35198                           SOC_REG_FLAG_REG_ARRAY,
  35199         0,
  35200         4,
  35201         soc_OAMP_TXM_BANK_SCAN_CONFIG_BCM88470_B0r_fields,
  35202         SOC_RESET_VAL_DEC(0x124f8012, 0x00000000)
  35203         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  35204         -1,
  35205         -1,
  35206     },
  35207 #endif /* chips */
  35208 
  35209 #if defined(BCM_88690_A0)
  35210     { /* SOC_REG_INT_OAMP_TXM_BANK_SCAN_CONFIG_BCM88690_A0r */
  35211         soc_block_list[22],
  35212         soc_genreg,
  35213         12,
  35214         0,
  35215         0x131,
  35216         SOC_REG_FLAG_ARRAY |
  35217                           SOC_REG_FLAG_REG_ARRAY,
  35218         0,
  35219         4,
  35220         soc_OAMP_TXM_BANK_SCAN_CONFIG_BCM88690_A0r_fields,
  35221         SOC_RESET_VAL_DEC(0x186a0012, 0x00000000)
  35222         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  35223         -1,
  35224         -1,
  35225     },
  35226 #endif /* chips */
  35227 
  35228 #if defined(BCM_88690_B0)
  35229     { /* SOC_REG_INT_OAMP_TXM_BANK_SCAN_CONFIG_BCM88690_B0r */
  35230         soc_block_list[22],
  35231         soc_genreg,
  35232         12,
  35233         0,
  35234         0x131,
  35235         SOC_REG_FLAG_ARRAY |
  35236                           SOC_REG_FLAG_REG_ARRAY,
  35237         0,
  35238         5,
  35239         soc_OAMP_TXM_BANK_SCAN_CONFIG_BCM88690_B0r_fields,
  35240         SOC_RESET_VAL_DEC(0x30d40024, 0x00000000)
  35241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35242         -1,
  35243         -1,
  35244     },
  35245 #endif /* chips */
  35246 
  35247 #if defined(BCM_88470_A0)
  35248     { /* SOC_REG_INT_OAMP_TXM_PKT_COUNTERr */
  35249         soc_block_list[22],
  35250         soc_genreg,
  35251         1,
  35252         0,
  35253         0x4b0,
  35254         SOC_REG_FLAG_64_BITS,
  35255         0,
  35256         3,
  35257         soc_OAMP_TXM_PKT_COUNTERr_fields,
  35258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35259         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  35260         -1,
  35261         -1,
  35262     },
  35263 #endif /* chips */
  35264 
  35265 #if defined(BCM_88270_A0)
  35266     { /* SOC_REG_INT_OAMP_TXM_PKT_COUNTER_BCM88270_A0r */
  35267         soc_block_list[22],
  35268         soc_genreg,
  35269         1,
  35270         0,
  35271         0x4b0,
  35272         SOC_REG_FLAG_64_BITS,
  35273         0,
  35274         3,
  35275         soc_OAMP_TXM_PKT_COUNTER_BCM88270_A0r_fields,
  35276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35277         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  35278         -1,
  35279         -1,
  35280     },
  35281 #endif /* chips */
  35282 
  35283 #if defined(BCM_88470_B0)
  35284     { /* SOC_REG_INT_OAMP_TXM_PKT_COUNTER_BCM88470_B0r */
  35285         soc_block_list[22],
  35286         soc_genreg,
  35287         1,
  35288         0,
  35289         0x4b0,
  35290         SOC_REG_FLAG_64_BITS,
  35291         0,
  35292         3,
  35293         soc_OAMP_TXM_PKT_COUNTER_BCM88470_B0r_fields,
  35294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35295         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  35296         -1,
  35297         -1,
  35298     },
  35299 #endif /* chips */
  35300 
  35301 #if defined(BCM_88690_A0)
  35302     { /* SOC_REG_INT_OAMP_TXM_PKT_COUNTER_BCM88690_A0r */
  35303         soc_block_list[22],
  35304         soc_genreg,
  35305         1,
  35306         0,
  35307         0x5a1,
  35308         SOC_REG_FLAG_64_BITS,
  35309         SOC_REG_FLAG_COUNTER_FEILDS,
  35310         3,
  35311         soc_OAMP_TXM_PKT_COUNTER_BCM88690_A0r_fields,
  35312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35313         SOC_RESET_MASK_DEC(0xffffffff, 0x01ffffff)
  35314         -1,
  35315         -1,
  35316     },
  35317 #endif /* chips */
  35318 
  35319 #if defined(BCM_88690_B0)
  35320     { /* SOC_REG_INT_OAMP_TXM_PKT_COUNTER_BCM88690_B0r */
  35321         soc_block_list[22],
  35322         soc_genreg,
  35323         1,
  35324         0,
  35325         0x5a1,
  35326         SOC_REG_FLAG_64_BITS,
  35327         SOC_REG_FLAG_COUNTER_FEILDS,
  35328         3,
  35329         soc_OAMP_TXM_PKT_COUNTER_BCM88690_B0r_fields,
  35330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35331         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  35332         -1,
  35333         -1,
  35334     },
  35335 #endif /* chips */
  35336 
  35337 #if defined(BCM_88690_A0)
  35338     { /* SOC_REG_INT_OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMERr */
  35339         soc_block_list[22],
  35340         soc_genreg,
  35341         8,
  35342         0,
  35343         0xb3b,
  35344         SOC_REG_FLAG_ARRAY |
  35345                           SOC_REG_FLAG_REG_ARRAY,
  35346         0,
  35347         1,
  35348         soc_OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMERr_fields,
  35349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35350         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  35351         -1,
  35352         -1,
  35353     },
  35354 #endif /* chips */
  35355 
  35356 #if defined(BCM_88690_B0)
  35357     { /* SOC_REG_INT_OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER_BCM88690_B0r */
  35358         soc_block_list[22],
  35359         soc_genreg,
  35360         8,
  35361         0,
  35362         0xb3d,
  35363         SOC_REG_FLAG_ARRAY |
  35364                           SOC_REG_FLAG_REG_ARRAY,
  35365         0,
  35366         1,
  35367         soc_OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER_BCM88690_B0r_fields,
  35368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35369         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  35370         -1,
  35371         -1,
  35372     },
  35373 #endif /* chips */
  35374 
  35375 #if defined(BCM_88470_A0)
  35376     { /* SOC_REG_INT_OAMP_TXO_PKT_COUNTERr */
  35377         soc_block_list[22],
  35378         soc_genreg,
  35379         1,
  35380         0,
  35381         0x4b9,
  35382         SOC_REG_FLAG_64_BITS,
  35383         0,
  35384         3,
  35385         soc_OAMP_TXO_PKT_COUNTERr_fields,
  35386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35387         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  35388         -1,
  35389         -1,
  35390     },
  35391 #endif /* chips */
  35392 
  35393 #if defined(BCM_88270_A0)
  35394     { /* SOC_REG_INT_OAMP_TXO_PKT_COUNTER_BCM88270_A0r */
  35395         soc_block_list[22],
  35396         soc_genreg,
  35397         1,
  35398         0,
  35399         0x4b9,
  35400         SOC_REG_FLAG_64_BITS,
  35401         0,
  35402         3,
  35403         soc_OAMP_TXO_PKT_COUNTER_BCM88270_A0r_fields,
  35404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35405         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  35406         -1,
  35407         -1,
  35408     },
  35409 #endif /* chips */
  35410 
  35411 #if defined(BCM_88470_B0)
  35412     { /* SOC_REG_INT_OAMP_TXO_PKT_COUNTER_BCM88470_B0r */
  35413         soc_block_list[22],
  35414         soc_genreg,
  35415         1,
  35416         0,
  35417         0x4b9,
  35418         SOC_REG_FLAG_64_BITS,
  35419         0,
  35420         3,
  35421         soc_OAMP_TXO_PKT_COUNTER_BCM88470_B0r_fields,
  35422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35423         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  35424         -1,
  35425         -1,
  35426     },
  35427 #endif /* chips */
  35428 
  35429 #if defined(BCM_88690_A0)
  35430     { /* SOC_REG_INT_OAMP_TXO_PKT_COUNTER_BCM88690_A0r */
  35431         soc_block_list[22],
  35432         soc_genreg,
  35433         1,
  35434         0,
  35435         0x5aa,
  35436         SOC_REG_FLAG_64_BITS,
  35437         SOC_REG_FLAG_COUNTER_FEILDS,
  35438         3,
  35439         soc_OAMP_TXO_PKT_COUNTER_BCM88690_A0r_fields,
  35440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35441         SOC_RESET_MASK_DEC(0xffffffff, 0x01ffffff)
  35442         -1,
  35443         -1,
  35444     },
  35445 #endif /* chips */
  35446 
  35447 #if defined(BCM_88690_B0)
  35448     { /* SOC_REG_INT_OAMP_TXO_PKT_COUNTER_BCM88690_B0r */
  35449         soc_block_list[22],
  35450         soc_genreg,
  35451         1,
  35452         0,
  35453         0x5aa,
  35454         SOC_REG_FLAG_64_BITS,
  35455         SOC_REG_FLAG_COUNTER_FEILDS,
  35456         3,
  35457         soc_OAMP_TXO_PKT_COUNTER_BCM88690_B0r_fields,
  35458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35459         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  35460         -1,
  35461         -1,
  35462     },
  35463 #endif /* chips */
  35464 
  35465 #if defined(BCM_88470_A0)
  35466     { /* SOC_REG_INT_OAMP_TXO_REQ_FIFO_DATAr */
  35467         soc_block_list[22],
  35468         soc_genreg,
  35469         1,
  35470         0,
  35471         0x4b6,
  35472         SOC_REG_FLAG_64_BITS |
  35473                           SOC_REG_FLAG_SIGNAL,
  35474         0,
  35475         1,
  35476         soc_OAMP_TXO_REQ_FIFO_DATAr_fields,
  35477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35478         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  35479         -1,
  35480         -1,
  35481     },
  35482 #endif /* chips */
  35483 
  35484 #if defined(BCM_88270_A0)
  35485     { /* SOC_REG_INT_OAMP_TXO_REQ_FIFO_DATA_BCM88270_A0r */
  35486         soc_block_list[22],
  35487         soc_genreg,
  35488         1,
  35489         0,
  35490         0x4b6,
  35491         SOC_REG_FLAG_64_BITS |
  35492                           SOC_REG_FLAG_SIGNAL,
  35493         0,
  35494         1,
  35495         soc_OAMP_TXO_REQ_FIFO_DATA_BCM88270_A0r_fields,
  35496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35497         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  35498         -1,
  35499         -1,
  35500     },
  35501 #endif /* chips */
  35502 
  35503 #if defined(BCM_88470_B0)
  35504     { /* SOC_REG_INT_OAMP_TXO_REQ_FIFO_DATA_BCM88470_B0r */
  35505         soc_block_list[22],
  35506         soc_genreg,
  35507         1,
  35508         0,
  35509         0x4b6,
  35510         SOC_REG_FLAG_64_BITS |
  35511                           SOC_REG_FLAG_SIGNAL,
  35512         0,
  35513         1,
  35514         soc_OAMP_TXO_REQ_FIFO_DATA_BCM88470_B0r_fields,
  35515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35516         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  35517         -1,
  35518         -1,
  35519     },
  35520 #endif /* chips */
  35521 
  35522 #if defined(BCM_88690_A0)
  35523     { /* SOC_REG_INT_OAMP_TXO_REQ_FIFO_DATA_BCM88690_A0r */
  35524         soc_block_list[22],
  35525         soc_genreg,
  35526         1,
  35527         0,
  35528         0x5a7,
  35529         SOC_REG_FLAG_64_BITS |
  35530                           SOC_REG_FLAG_SIGNAL,
  35531         0,
  35532         1,
  35533         soc_OAMP_TXO_REQ_FIFO_DATA_BCM88690_A0r_fields,
  35534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35535         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
  35536         -1,
  35537         -1,
  35538     },
  35539 #endif /* chips */
  35540 
  35541 #if defined(BCM_88690_B0)
  35542     { /* SOC_REG_INT_OAMP_TXO_REQ_FIFO_DATA_BCM88690_B0r */
  35543         soc_block_list[22],
  35544         soc_genreg,
  35545         1,
  35546         0,
  35547         0x5a7,
  35548         SOC_REG_FLAG_64_BITS |
  35549                           SOC_REG_FLAG_SIGNAL,
  35550         0,
  35551         1,
  35552         soc_OAMP_TXO_REQ_FIFO_DATA_BCM88690_B0r_fields,
  35553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35554         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  35555         -1,
  35556         -1,
  35557     },
  35558 #endif /* chips */
  35559 
  35560 #if defined(BCM_88470_A0)
  35561     { /* SOC_REG_INT_OAMP_TXO_REQ_STATUSr */
  35562         soc_block_list[22],
  35563         soc_genreg,
  35564         1,
  35565         0,
  35566         0x4b8,
  35567         SOC_REG_FLAG_RO |
  35568                           SOC_REG_FLAG_SIGNAL,
  35569         0,
  35570         2,
  35571         soc_OAMP_TXO_REQ_STATUSr_fields,
  35572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35573         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  35574         -1,
  35575         -1,
  35576     },
  35577 #endif /* chips */
  35578 
  35579 #if defined(BCM_88270_A0)
  35580     { /* SOC_REG_INT_OAMP_TXO_REQ_STATUS_BCM88270_A0r */
  35581         soc_block_list[22],
  35582         soc_genreg,
  35583         1,
  35584         0,
  35585         0x4b8,
  35586         SOC_REG_FLAG_RO |
  35587                           SOC_REG_FLAG_SIGNAL,
  35588         0,
  35589         2,
  35590         soc_OAMP_TXO_REQ_STATUS_BCM88270_A0r_fields,
  35591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35592         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  35593         -1,
  35594         -1,
  35595     },
  35596 #endif /* chips */
  35597 
  35598 #if defined(BCM_88470_B0)
  35599     { /* SOC_REG_INT_OAMP_TXO_REQ_STATUS_BCM88470_B0r */
  35600         soc_block_list[22],
  35601         soc_genreg,
  35602         1,
  35603         0,
  35604         0x4b8,
  35605         SOC_REG_FLAG_RO |
  35606                           SOC_REG_FLAG_SIGNAL,
  35607         0,
  35608         2,
  35609         soc_OAMP_TXO_REQ_STATUS_BCM88470_B0r_fields,
  35610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35611         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  35612         -1,
  35613         -1,
  35614     },
  35615 #endif /* chips */
  35616 
  35617 #if defined(BCM_88690_A0)
  35618     { /* SOC_REG_INT_OAMP_TXO_REQ_STATUS_BCM88690_A0r */
  35619         soc_block_list[22],
  35620         soc_genreg,
  35621         1,
  35622         0,
  35623         0x5a9,
  35624         SOC_REG_FLAG_RO |
  35625                           SOC_REG_FLAG_SIGNAL,
  35626         0,
  35627         2,
  35628         soc_OAMP_TXO_REQ_STATUS_BCM88690_A0r_fields,
  35629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35630         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  35631         -1,
  35632         -1,
  35633     },
  35634 #endif /* chips */
  35635 
  35636 #if defined(BCM_88690_B0)
  35637     { /* SOC_REG_INT_OAMP_TXO_REQ_STATUS_BCM88690_B0r */
  35638         soc_block_list[22],
  35639         soc_genreg,
  35640         1,
  35641         0,
  35642         0x5a9,
  35643         SOC_REG_FLAG_RO |
  35644                           SOC_REG_FLAG_SIGNAL,
  35645         0,
  35646         2,
  35647         soc_OAMP_TXO_REQ_STATUS_BCM88690_B0r_fields,
  35648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35649         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  35650         -1,
  35651         -1,
  35652     },
  35653 #endif /* chips */
  35654 
  35655 #if defined(BCM_88690_A0)
  35656     { /* SOC_REG_INT_OAMP_TX_JR_2_AS_OAMr */
  35657         soc_block_list[22],
  35658         soc_genreg,
  35659         1,
  35660         0,
  35661         0x126,
  35662         0,
  35663         0,
  35664         1,
  35665         soc_OAMP_TX_JR_2_AS_OAMr_fields,
  35666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35667         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35668         -1,
  35669         -1,
  35670     },
  35671 #endif /* chips */
  35672 
  35673 #if defined(BCM_88690_B0)
  35674     { /* SOC_REG_INT_OAMP_TX_JR_2_AS_OAM_BCM88690_B0r */
  35675         soc_block_list[22],
  35676         soc_genreg,
  35677         1,
  35678         0,
  35679         0x126,
  35680         0,
  35681         0,
  35682         1,
  35683         soc_OAMP_TX_JR_2_AS_OAM_BCM88690_B0r_fields,
  35684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35685         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35686         -1,
  35687         -1,
  35688     },
  35689 #endif /* chips */
  35690 
  35691 #if defined(BCM_88650_A0)
  35692     { /* SOC_REG_INT_OAMP_TX_PPHr */
  35693         soc_block_list[22],
  35694         soc_genreg,
  35695         1,
  35696         0,
  35697         0x120,
  35698         SOC_REG_FLAG_64_BITS |
  35699                           SOC_REG_FLAG_SIGNAL,
  35700         0,
  35701         4,
  35702         soc_OAMP_TX_PPHr_fields,
  35703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35704         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  35705         -1,
  35706         -1,
  35707     },
  35708 #endif /* chips */
  35709 
  35710 #if defined(BCM_88375_A0)
  35711     { /* SOC_REG_INT_OAMP_TX_PPH_BCM88375_A0r */
  35712         soc_block_list[22],
  35713         soc_genreg,
  35714         1,
  35715         0,
  35716         0x130,
  35717         SOC_REG_FLAG_64_BITS,
  35718         0,
  35719         8,
  35720         soc_OAMP_TX_PPH_BCM88375_A0r_fields,
  35721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35722         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  35723         -1,
  35724         -1,
  35725     },
  35726 #endif /* chips */
  35727 
  35728 #if defined(BCM_88375_B0)
  35729     { /* SOC_REG_INT_OAMP_TX_PPH_BCM88375_B0r */
  35730         soc_block_list[22],
  35731         soc_genreg,
  35732         1,
  35733         0,
  35734         0x130,
  35735         SOC_REG_FLAG_64_BITS,
  35736         0,
  35737         8,
  35738         soc_OAMP_TX_PPH_BCM88375_B0r_fields,
  35739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35740         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  35741         -1,
  35742         -1,
  35743     },
  35744 #endif /* chips */
  35745 
  35746 #if defined(BCM_88470_B0)
  35747     { /* SOC_REG_INT_OAMP_TX_PPH_BCM88470_B0r */
  35748         soc_block_list[22],
  35749         soc_genreg,
  35750         1,
  35751         0,
  35752         0x130,
  35753         SOC_REG_FLAG_64_BITS,
  35754         0,
  35755         16,
  35756         soc_OAMP_TX_PPH_BCM88470_B0r_fields,
  35757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35758         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  35759         -1,
  35760         -1,
  35761     },
  35762 #endif /* chips */
  35763 
  35764 #if defined(BCM_88650_B0)
  35765     { /* SOC_REG_INT_OAMP_TX_PPH_BCM88650_B0r */
  35766         soc_block_list[22],
  35767         soc_genreg,
  35768         1,
  35769         0,
  35770         0x120,
  35771         SOC_REG_FLAG_64_BITS |
  35772                           SOC_REG_FLAG_SIGNAL,
  35773         0,
  35774         4,
  35775         soc_OAMP_TX_PPH_BCM88650_B0r_fields,
  35776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35777         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  35778         -1,
  35779         -1,
  35780     },
  35781 #endif /* chips */
  35782 
  35783 #if defined(BCM_88660_A0)
  35784     { /* SOC_REG_INT_OAMP_TX_PPH_BCM88660_A0r */
  35785         soc_block_list[22],
  35786         soc_genreg,
  35787         1,
  35788         0,
  35789         0x120,
  35790         SOC_REG_FLAG_64_BITS |
  35791                           SOC_REG_FLAG_SIGNAL,
  35792         0,
  35793         4,
  35794         soc_OAMP_TX_PPH_BCM88660_A0r_fields,
  35795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35796         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  35797         -1,
  35798         -1,
  35799     },
  35800 #endif /* chips */
  35801 
  35802 #if defined(BCM_88675_A0)
  35803     { /* SOC_REG_INT_OAMP_TX_PPH_BCM88675_A0r */
  35804         soc_block_list[22],
  35805         soc_genreg,
  35806         1,
  35807         0,
  35808         0x130,
  35809         SOC_REG_FLAG_64_BITS,
  35810         0,
  35811         8,
  35812         soc_OAMP_TX_PPH_BCM88675_A0r_fields,
  35813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35814         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  35815         -1,
  35816         -1,
  35817     },
  35818 #endif /* chips */
  35819 
  35820 #if defined(BCM_88675_B0)
  35821     { /* SOC_REG_INT_OAMP_TX_PPH_BCM88675_B0r */
  35822         soc_block_list[22],
  35823         soc_genreg,
  35824         1,
  35825         0,
  35826         0x130,
  35827         SOC_REG_FLAG_64_BITS,
  35828         0,
  35829         8,
  35830         soc_OAMP_TX_PPH_BCM88675_B0r_fields,
  35831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35832         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  35833         -1,
  35834         -1,
  35835     },
  35836 #endif /* chips */
  35837 
  35838 #if defined(BCM_88680_A0)
  35839     { /* SOC_REG_INT_OAMP_TX_PPH_BCM88680_A0r */
  35840         soc_block_list[22],
  35841         soc_genreg,
  35842         1,
  35843         0,
  35844         0x130,
  35845         SOC_REG_FLAG_64_BITS,
  35846         0,
  35847         8,
  35848         soc_OAMP_TX_PPH_BCM88680_A0r_fields,
  35849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35850         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  35851         -1,
  35852         -1,
  35853     },
  35854 #endif /* chips */
  35855 
  35856 #if defined(BCM_88690_A0)
  35857     { /* SOC_REG_INT_OAMP_UDHr */
  35858         soc_block_list[22],
  35859         soc_genreg,
  35860         1,
  35861         0,
  35862         0xb16,
  35863         0,
  35864         0,
  35865         2,
  35866         soc_OAMP_UDHr_fields,
  35867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35868         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  35869         -1,
  35870         -1,
  35871     },
  35872 #endif /* chips */
  35873 
  35874 #if defined(BCM_88690_B0)
  35875     { /* SOC_REG_INT_OAMP_UDH_BCM88690_B0r */
  35876         soc_block_list[22],
  35877         soc_genreg,
  35878         1,
  35879         0,
  35880         0xb16,
  35881         0,
  35882         0,
  35883         2,
  35884         soc_OAMP_UDH_BCM88690_B0r_fields,
  35885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35886         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  35887         -1,
  35888         -1,
  35889     },
  35890 #endif /* chips */
  35891 
  35892 #if defined(BCM_88675_A0)
  35893     { /* SOC_REG_INT_OAMP_UP_PTCHr */
  35894         soc_block_list[22],
  35895         soc_genreg,
  35896         1,
  35897         0,
  35898         0x407,
  35899         0,
  35900         0,
  35901         3,
  35902         soc_OAMP_UP_PTCHr_fields,
  35903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35904         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  35905         -1,
  35906         -1,
  35907     },
  35908 #endif /* chips */
  35909 
  35910 #if defined(BCM_88270_A0)
  35911     { /* SOC_REG_INT_OAMP_UP_PTCH_BCM88270_A0r */
  35912         soc_block_list[22],
  35913         soc_genreg,
  35914         1,
  35915         0,
  35916         0x409,
  35917         0,
  35918         0,
  35919         3,
  35920         soc_OAMP_UP_PTCH_BCM88270_A0r_fields,
  35921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35922         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  35923         -1,
  35924         -1,
  35925     },
  35926 #endif /* chips */
  35927 
  35928 #if defined(BCM_88375_A0)
  35929     { /* SOC_REG_INT_OAMP_UP_PTCH_BCM88375_A0r */
  35930         soc_block_list[22],
  35931         soc_genreg,
  35932         1,
  35933         0,
  35934         0x407,
  35935         0,
  35936         0,
  35937         3,
  35938         soc_OAMP_UP_PTCH_BCM88375_A0r_fields,
  35939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35940         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  35941         -1,
  35942         -1,
  35943     },
  35944 #endif /* chips */
  35945 
  35946 #if defined(BCM_88375_B0)
  35947     { /* SOC_REG_INT_OAMP_UP_PTCH_BCM88375_B0r */
  35948         soc_block_list[22],
  35949         soc_genreg,
  35950         1,
  35951         0,
  35952         0x407,
  35953         0,
  35954         0,
  35955         3,
  35956         soc_OAMP_UP_PTCH_BCM88375_B0r_fields,
  35957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35958         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  35959         -1,
  35960         -1,
  35961     },
  35962 #endif /* chips */
  35963 
  35964 #if defined(BCM_88470_A0)
  35965     { /* SOC_REG_INT_OAMP_UP_PTCH_BCM88470_A0r */
  35966         soc_block_list[22],
  35967         soc_genreg,
  35968         1,
  35969         0,
  35970         0x409,
  35971         0,
  35972         0,
  35973         3,
  35974         soc_OAMP_UP_PTCH_BCM88470_A0r_fields,
  35975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35976         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  35977         -1,
  35978         -1,
  35979     },
  35980 #endif /* chips */
  35981 
  35982 #if defined(BCM_88470_B0)
  35983     { /* SOC_REG_INT_OAMP_UP_PTCH_BCM88470_B0r */
  35984         soc_block_list[22],
  35985         soc_genreg,
  35986         1,
  35987         0,
  35988         0x409,
  35989         0,
  35990         0,
  35991         3,
  35992         soc_OAMP_UP_PTCH_BCM88470_B0r_fields,
  35993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35994         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  35995         -1,
  35996         -1,
  35997     },
  35998 #endif /* chips */
  35999 
  36000 #if defined(BCM_88675_B0)
  36001     { /* SOC_REG_INT_OAMP_UP_PTCH_BCM88675_B0r */
  36002         soc_block_list[22],
  36003         soc_genreg,
  36004         1,
  36005         0,
  36006         0x407,
  36007         0,
  36008         0,
  36009         3,
  36010         soc_OAMP_UP_PTCH_BCM88675_B0r_fields,
  36011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36012         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  36013         -1,
  36014         -1,
  36015     },
  36016 #endif /* chips */
  36017 
  36018 #if defined(BCM_88680_A0)
  36019     { /* SOC_REG_INT_OAMP_UP_PTCH_BCM88680_A0r */
  36020         soc_block_list[22],
  36021         soc_genreg,
  36022         1,
  36023         0,
  36024         0x407,
  36025         0,
  36026         0,
  36027         3,
  36028         soc_OAMP_UP_PTCH_BCM88680_A0r_fields,
  36029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36030         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  36031         -1,
  36032         -1,
  36033     },
  36034 #endif /* chips */
  36035 
  36036 #if defined(BCM_88690_A0)
  36037     { /* SOC_REG_INT_OAMP_UP_PTCH_BCM88690_A0r */
  36038         soc_block_list[22],
  36039         soc_genreg,
  36040         1,
  36041         0,
  36042         0x409,
  36043         0,
  36044         0,
  36045         3,
  36046         soc_OAMP_UP_PTCH_BCM88690_A0r_fields,
  36047         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  36048         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  36049         -1,
  36050         -1,
  36051     },
  36052 #endif /* chips */
  36053 
  36054 #if defined(BCM_88690_B0)
  36055     { /* SOC_REG_INT_OAMP_UP_PTCH_BCM88690_B0r */
  36056         soc_block_list[22],
  36057         soc_genreg,
  36058         1,
  36059         0,
  36060         0x409,
  36061         0,
  36062         0,
  36063         3,
  36064         soc_OAMP_UP_PTCH_BCM88690_B0r_fields,
  36065         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  36066         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  36067         -1,
  36068         -1,
  36069     },
  36070 #endif /* chips */
  36071 
  36072 #if defined(BCM_88650_A0)
  36073     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKYr */
  36074         soc_block_list[22],
  36075         soc_genreg,
  36076         1,
  36077         0,
  36078         0x11a,
  36079         SOC_REG_FLAG_SIGNAL,
  36080         0,
  36081         14,
  36082         soc_OAMP_VALIDITY_CHECK_STICKYr_fields,
  36083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36084         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  36085         -1,
  36086         -1,
  36087     },
  36088 #endif /* chips */
  36089 
  36090 #if defined(BCM_88270_A0)
  36091     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88270_A0r */
  36092         soc_block_list[22],
  36093         soc_genreg,
  36094         1,
  36095         0,
  36096         0x122,
  36097         0,
  36098         0,
  36099         17,
  36100         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88270_A0r_fields,
  36101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36102         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  36103         -1,
  36104         -1,
  36105     },
  36106 #endif /* chips */
  36107 
  36108 #if defined(BCM_88375_A0)
  36109     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88375_A0r */
  36110         soc_block_list[22],
  36111         soc_genreg,
  36112         1,
  36113         0,
  36114         0x11f,
  36115         0,
  36116         0,
  36117         15,
  36118         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88375_A0r_fields,
  36119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36120         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  36121         -1,
  36122         -1,
  36123     },
  36124 #endif /* chips */
  36125 
  36126 #if defined(BCM_88375_B0)
  36127     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88375_B0r */
  36128         soc_block_list[22],
  36129         soc_genreg,
  36130         1,
  36131         0,
  36132         0x11f,
  36133         0,
  36134         0,
  36135         15,
  36136         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88375_B0r_fields,
  36137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36138         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  36139         -1,
  36140         -1,
  36141     },
  36142 #endif /* chips */
  36143 
  36144 #if defined(BCM_88470_A0)
  36145     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88470_A0r */
  36146         soc_block_list[22],
  36147         soc_genreg,
  36148         1,
  36149         0,
  36150         0x122,
  36151         0,
  36152         0,
  36153         17,
  36154         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88470_A0r_fields,
  36155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36156         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  36157         -1,
  36158         -1,
  36159     },
  36160 #endif /* chips */
  36161 
  36162 #if defined(BCM_88470_B0)
  36163     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88470_B0r */
  36164         soc_block_list[22],
  36165         soc_genreg,
  36166         1,
  36167         0,
  36168         0x122,
  36169         0,
  36170         0,
  36171         17,
  36172         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88470_B0r_fields,
  36173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36174         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  36175         -1,
  36176         -1,
  36177     },
  36178 #endif /* chips */
  36179 
  36180 #if defined(BCM_88650_B0)
  36181     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88650_B0r */
  36182         soc_block_list[22],
  36183         soc_genreg,
  36184         1,
  36185         0,
  36186         0x11a,
  36187         SOC_REG_FLAG_SIGNAL,
  36188         0,
  36189         14,
  36190         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88650_B0r_fields,
  36191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36192         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  36193         -1,
  36194         -1,
  36195     },
  36196 #endif /* chips */
  36197 
  36198 #if defined(BCM_88660_A0)
  36199     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88660_A0r */
  36200         soc_block_list[22],
  36201         soc_genreg,
  36202         1,
  36203         0,
  36204         0x11e,
  36205         SOC_REG_FLAG_SIGNAL,
  36206         0,
  36207         14,
  36208         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88660_A0r_fields,
  36209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36210         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  36211         -1,
  36212         -1,
  36213     },
  36214 #endif /* chips */
  36215 
  36216 #if defined(BCM_88675_A0)
  36217     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88675_A0r */
  36218         soc_block_list[22],
  36219         soc_genreg,
  36220         1,
  36221         0,
  36222         0x11f,
  36223         0,
  36224         0,
  36225         15,
  36226         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88675_A0r_fields,
  36227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36228         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  36229         -1,
  36230         -1,
  36231     },
  36232 #endif /* chips */
  36233 
  36234 #if defined(BCM_88675_B0)
  36235     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88675_B0r */
  36236         soc_block_list[22],
  36237         soc_genreg,
  36238         1,
  36239         0,
  36240         0x11f,
  36241         0,
  36242         0,
  36243         15,
  36244         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88675_B0r_fields,
  36245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36246         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  36247         -1,
  36248         -1,
  36249     },
  36250 #endif /* chips */
  36251 
  36252 #if defined(BCM_88680_A0)
  36253     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88680_A0r */
  36254         soc_block_list[22],
  36255         soc_genreg,
  36256         1,
  36257         0,
  36258         0x11f,
  36259         0,
  36260         0,
  36261         15,
  36262         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88680_A0r_fields,
  36263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36264         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  36265         -1,
  36266         -1,
  36267     },
  36268 #endif /* chips */
  36269 
  36270 #if defined(BCM_88690_A0)
  36271     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88690_A0r */
  36272         soc_block_list[22],
  36273         soc_genreg,
  36274         1,
  36275         0,
  36276         0x122,
  36277         0,
  36278         0,
  36279         17,
  36280         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88690_A0r_fields,
  36281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36282         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  36283         -1,
  36284         -1,
  36285     },
  36286 #endif /* chips */
  36287 
  36288 #if defined(BCM_88690_B0)
  36289     { /* SOC_REG_INT_OAMP_VALIDITY_CHECK_STICKY_BCM88690_B0r */
  36290         soc_block_list[22],
  36291         soc_genreg,
  36292         1,
  36293         0,
  36294         0x122,
  36295         0,
  36296         0,
  36297         17,
  36298         soc_OAMP_VALIDITY_CHECK_STICKY_BCM88690_B0r_fields,
  36299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36300         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  36301         -1,
  36302         -1,
  36303     },
  36304 #endif /* chips */
  36305 
  36306 #if defined(BCM_88690_A0)
  36307     { /* SOC_REG_INT_OAMP_YOUR_DISC_MISS_INFOr */
  36308         soc_block_list[22],
  36309         soc_genreg,
  36310         1,
  36311         0,
  36312         0xb0f,
  36313         SOC_REG_FLAG_64_BITS |
  36314                           SOC_REG_FLAG_RO |
  36315                           SOC_REG_FLAG_SIGNAL,
  36316         SOC_REG_FLAG_INIT_ON_READ,
  36317         2,
  36318         soc_OAMP_YOUR_DISC_MISS_INFOr_fields,
  36319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36320         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  36321         -1,
  36322         -1,
  36323     },
  36324 #endif /* chips */
  36325 
  36326 #if defined(BCM_88690_B0)
  36327     { /* SOC_REG_INT_OAMP_YOUR_DISC_MISS_INFO_BCM88690_B0r */
  36328         soc_block_list[22],
  36329         soc_genreg,
  36330         1,
  36331         0,
  36332         0xb0f,
  36333         SOC_REG_FLAG_64_BITS |
  36334                           SOC_REG_FLAG_RO |
  36335                           SOC_REG_FLAG_SIGNAL,
  36336         SOC_REG_FLAG_INIT_ON_READ,
  36337         2,
  36338         soc_OAMP_YOUR_DISC_MISS_INFO_BCM88690_B0r_fields,
  36339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36340         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  36341         -1,
  36342         -1,
  36343     },
  36344 #endif /* chips */
  36345 
  36346 #if defined(BCM_88650_A0)
  36347     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACHr */
  36348         soc_block_list[22],
  36349         soc_genreg,
  36350         1,
  36351         0,
  36352         0x190,
  36353         SOC_REG_FLAG_SIGNAL,
  36354         0,
  36355         1,
  36356         soc_OAMP_Y_1731O_MPLSTP_GACHr_fields,
  36357         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36358         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36359         -1,
  36360         -1,
  36361     },
  36362 #endif /* chips */
  36363 
  36364 #if defined(BCM_88270_A0)
  36365     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88270_A0r */
  36366         soc_block_list[22],
  36367         soc_genreg,
  36368         1,
  36369         0,
  36370         0x411,
  36371         0,
  36372         0,
  36373         1,
  36374         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88270_A0r_fields,
  36375         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36377         -1,
  36378         -1,
  36379     },
  36380 #endif /* chips */
  36381 
  36382 #if defined(BCM_88375_A0)
  36383     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88375_A0r */
  36384         soc_block_list[22],
  36385         soc_genreg,
  36386         1,
  36387         0,
  36388         0x40f,
  36389         0,
  36390         0,
  36391         1,
  36392         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88375_A0r_fields,
  36393         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36394         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36395         -1,
  36396         -1,
  36397     },
  36398 #endif /* chips */
  36399 
  36400 #if defined(BCM_88375_B0)
  36401     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88375_B0r */
  36402         soc_block_list[22],
  36403         soc_genreg,
  36404         1,
  36405         0,
  36406         0x40f,
  36407         0,
  36408         0,
  36409         1,
  36410         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88375_B0r_fields,
  36411         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36413         -1,
  36414         -1,
  36415     },
  36416 #endif /* chips */
  36417 
  36418 #if defined(BCM_88470_A0)
  36419     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88470_A0r */
  36420         soc_block_list[22],
  36421         soc_genreg,
  36422         1,
  36423         0,
  36424         0x411,
  36425         0,
  36426         0,
  36427         1,
  36428         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88470_A0r_fields,
  36429         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36430         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36431         -1,
  36432         -1,
  36433     },
  36434 #endif /* chips */
  36435 
  36436 #if defined(BCM_88470_B0)
  36437     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88470_B0r */
  36438         soc_block_list[22],
  36439         soc_genreg,
  36440         1,
  36441         0,
  36442         0x411,
  36443         0,
  36444         0,
  36445         1,
  36446         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88470_B0r_fields,
  36447         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36448         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36449         -1,
  36450         -1,
  36451     },
  36452 #endif /* chips */
  36453 
  36454 #if defined(BCM_88650_B0)
  36455     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88650_B0r */
  36456         soc_block_list[22],
  36457         soc_genreg,
  36458         1,
  36459         0,
  36460         0x190,
  36461         SOC_REG_FLAG_SIGNAL,
  36462         0,
  36463         1,
  36464         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88650_B0r_fields,
  36465         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36466         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36467         -1,
  36468         -1,
  36469     },
  36470 #endif /* chips */
  36471 
  36472 #if defined(BCM_88660_A0)
  36473     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88660_A0r */
  36474         soc_block_list[22],
  36475         soc_genreg,
  36476         1,
  36477         0,
  36478         0x40e,
  36479         SOC_REG_FLAG_SIGNAL,
  36480         0,
  36481         1,
  36482         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88660_A0r_fields,
  36483         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36484         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36485         -1,
  36486         -1,
  36487     },
  36488 #endif /* chips */
  36489 
  36490 #if defined(BCM_88675_A0)
  36491     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88675_A0r */
  36492         soc_block_list[22],
  36493         soc_genreg,
  36494         1,
  36495         0,
  36496         0x40f,
  36497         0,
  36498         0,
  36499         1,
  36500         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88675_A0r_fields,
  36501         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36502         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36503         -1,
  36504         -1,
  36505     },
  36506 #endif /* chips */
  36507 
  36508 #if defined(BCM_88675_B0)
  36509     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88675_B0r */
  36510         soc_block_list[22],
  36511         soc_genreg,
  36512         1,
  36513         0,
  36514         0x40f,
  36515         0,
  36516         0,
  36517         1,
  36518         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88675_B0r_fields,
  36519         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36520         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36521         -1,
  36522         -1,
  36523     },
  36524 #endif /* chips */
  36525 
  36526 #if defined(BCM_88680_A0)
  36527     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88680_A0r */
  36528         soc_block_list[22],
  36529         soc_genreg,
  36530         1,
  36531         0,
  36532         0x40f,
  36533         0,
  36534         0,
  36535         1,
  36536         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88680_A0r_fields,
  36537         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36538         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36539         -1,
  36540         -1,
  36541     },
  36542 #endif /* chips */
  36543 
  36544 #if defined(BCM_88690_A0)
  36545     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88690_A0r */
  36546         soc_block_list[22],
  36547         soc_genreg,
  36548         1,
  36549         0,
  36550         0x411,
  36551         0,
  36552         0,
  36553         1,
  36554         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88690_A0r_fields,
  36555         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36557         -1,
  36558         -1,
  36559     },
  36560 #endif /* chips */
  36561 
  36562 #if defined(BCM_88690_B0)
  36563     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GACH_BCM88690_B0r */
  36564         soc_block_list[22],
  36565         soc_genreg,
  36566         1,
  36567         0,
  36568         0x411,
  36569         0,
  36570         0,
  36571         1,
  36572         soc_OAMP_Y_1731O_MPLSTP_GACH_BCM88690_B0r_fields,
  36573         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36574         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36575         -1,
  36576         -1,
  36577     },
  36578 #endif /* chips */
  36579 
  36580 #if defined(BCM_88650_A0)
  36581     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GALr */
  36582         soc_block_list[22],
  36583         soc_genreg,
  36584         1,
  36585         0,
  36586         0x18f,
  36587         SOC_REG_FLAG_SIGNAL,
  36588         0,
  36589         1,
  36590         soc_OAMP_Y_1731O_MPLSTP_GALr_fields,
  36591         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36592         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36593         -1,
  36594         -1,
  36595     },
  36596 #endif /* chips */
  36597 
  36598 #if defined(BCM_88270_A0)
  36599     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88270_A0r */
  36600         soc_block_list[22],
  36601         soc_genreg,
  36602         1,
  36603         0,
  36604         0x410,
  36605         0,
  36606         0,
  36607         1,
  36608         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88270_A0r_fields,
  36609         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36610         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36611         -1,
  36612         -1,
  36613     },
  36614 #endif /* chips */
  36615 
  36616 #if defined(BCM_88375_A0)
  36617     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88375_A0r */
  36618         soc_block_list[22],
  36619         soc_genreg,
  36620         1,
  36621         0,
  36622         0x40e,
  36623         0,
  36624         0,
  36625         1,
  36626         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88375_A0r_fields,
  36627         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36628         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36629         -1,
  36630         -1,
  36631     },
  36632 #endif /* chips */
  36633 
  36634 #if defined(BCM_88375_B0)
  36635     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88375_B0r */
  36636         soc_block_list[22],
  36637         soc_genreg,
  36638         1,
  36639         0,
  36640         0x40e,
  36641         0,
  36642         0,
  36643         1,
  36644         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88375_B0r_fields,
  36645         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36646         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36647         -1,
  36648         -1,
  36649     },
  36650 #endif /* chips */
  36651 
  36652 #if defined(BCM_88470_A0)
  36653     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88470_A0r */
  36654         soc_block_list[22],
  36655         soc_genreg,
  36656         1,
  36657         0,
  36658         0x410,
  36659         0,
  36660         0,
  36661         1,
  36662         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88470_A0r_fields,
  36663         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36664         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36665         -1,
  36666         -1,
  36667     },
  36668 #endif /* chips */
  36669 
  36670 #if defined(BCM_88470_B0)
  36671     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88470_B0r */
  36672         soc_block_list[22],
  36673         soc_genreg,
  36674         1,
  36675         0,
  36676         0x410,
  36677         0,
  36678         0,
  36679         1,
  36680         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88470_B0r_fields,
  36681         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36682         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36683         -1,
  36684         -1,
  36685     },
  36686 #endif /* chips */
  36687 
  36688 #if defined(BCM_88650_B0)
  36689     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88650_B0r */
  36690         soc_block_list[22],
  36691         soc_genreg,
  36692         1,
  36693         0,
  36694         0x18f,
  36695         SOC_REG_FLAG_SIGNAL,
  36696         0,
  36697         1,
  36698         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88650_B0r_fields,
  36699         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36700         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36701         -1,
  36702         -1,
  36703     },
  36704 #endif /* chips */
  36705 
  36706 #if defined(BCM_88660_A0)
  36707     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88660_A0r */
  36708         soc_block_list[22],
  36709         soc_genreg,
  36710         1,
  36711         0,
  36712         0x40d,
  36713         SOC_REG_FLAG_SIGNAL,
  36714         0,
  36715         1,
  36716         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88660_A0r_fields,
  36717         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36718         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36719         -1,
  36720         -1,
  36721     },
  36722 #endif /* chips */
  36723 
  36724 #if defined(BCM_88675_A0)
  36725     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88675_A0r */
  36726         soc_block_list[22],
  36727         soc_genreg,
  36728         1,
  36729         0,
  36730         0x40e,
  36731         0,
  36732         0,
  36733         1,
  36734         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88675_A0r_fields,
  36735         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36736         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36737         -1,
  36738         -1,
  36739     },
  36740 #endif /* chips */
  36741 
  36742 #if defined(BCM_88675_B0)
  36743     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88675_B0r */
  36744         soc_block_list[22],
  36745         soc_genreg,
  36746         1,
  36747         0,
  36748         0x40e,
  36749         0,
  36750         0,
  36751         1,
  36752         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88675_B0r_fields,
  36753         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36754         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36755         -1,
  36756         -1,
  36757     },
  36758 #endif /* chips */
  36759 
  36760 #if defined(BCM_88680_A0)
  36761     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88680_A0r */
  36762         soc_block_list[22],
  36763         soc_genreg,
  36764         1,
  36765         0,
  36766         0x40e,
  36767         0,
  36768         0,
  36769         1,
  36770         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88680_A0r_fields,
  36771         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36772         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36773         -1,
  36774         -1,
  36775     },
  36776 #endif /* chips */
  36777 
  36778 #if defined(BCM_88690_A0)
  36779     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88690_A0r */
  36780         soc_block_list[22],
  36781         soc_genreg,
  36782         1,
  36783         0,
  36784         0x410,
  36785         0,
  36786         0,
  36787         1,
  36788         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88690_A0r_fields,
  36789         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36791         -1,
  36792         -1,
  36793     },
  36794 #endif /* chips */
  36795 
  36796 #if defined(BCM_88690_B0)
  36797     { /* SOC_REG_INT_OAMP_Y_1731O_MPLSTP_GAL_BCM88690_B0r */
  36798         soc_block_list[22],
  36799         soc_genreg,
  36800         1,
  36801         0,
  36802         0x410,
  36803         0,
  36804         0,
  36805         1,
  36806         soc_OAMP_Y_1731O_MPLSTP_GAL_BCM88690_B0r_fields,
  36807         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36808         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36809         -1,
  36810         -1,
  36811     },
  36812 #endif /* chips */
  36813 
  36814 #if defined(BCM_88650_A0)
  36815     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACHr */
  36816         soc_block_list[22],
  36817         soc_genreg,
  36818         1,
  36819         0,
  36820         0x191,
  36821         SOC_REG_FLAG_SIGNAL,
  36822         0,
  36823         1,
  36824         soc_OAMP_Y_1731O_PWE_GACHr_fields,
  36825         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36826         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36827         -1,
  36828         -1,
  36829     },
  36830 #endif /* chips */
  36831 
  36832 #if defined(BCM_88270_A0)
  36833     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88270_A0r */
  36834         soc_block_list[22],
  36835         soc_genreg,
  36836         1,
  36837         0,
  36838         0x412,
  36839         0,
  36840         0,
  36841         1,
  36842         soc_OAMP_Y_1731O_PWE_GACH_BCM88270_A0r_fields,
  36843         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36844         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36845         -1,
  36846         -1,
  36847     },
  36848 #endif /* chips */
  36849 
  36850 #if defined(BCM_88375_A0)
  36851     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88375_A0r */
  36852         soc_block_list[22],
  36853         soc_genreg,
  36854         1,
  36855         0,
  36856         0x410,
  36857         0,
  36858         0,
  36859         1,
  36860         soc_OAMP_Y_1731O_PWE_GACH_BCM88375_A0r_fields,
  36861         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36862         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36863         -1,
  36864         -1,
  36865     },
  36866 #endif /* chips */
  36867 
  36868 #if defined(BCM_88375_B0)
  36869     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88375_B0r */
  36870         soc_block_list[22],
  36871         soc_genreg,
  36872         1,
  36873         0,
  36874         0x410,
  36875         0,
  36876         0,
  36877         1,
  36878         soc_OAMP_Y_1731O_PWE_GACH_BCM88375_B0r_fields,
  36879         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36880         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36881         -1,
  36882         -1,
  36883     },
  36884 #endif /* chips */
  36885 
  36886 #if defined(BCM_88470_A0)
  36887     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88470_A0r */
  36888         soc_block_list[22],
  36889         soc_genreg,
  36890         1,
  36891         0,
  36892         0x412,
  36893         0,
  36894         0,
  36895         1,
  36896         soc_OAMP_Y_1731O_PWE_GACH_BCM88470_A0r_fields,
  36897         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36898         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36899         -1,
  36900         -1,
  36901     },
  36902 #endif /* chips */
  36903 
  36904 #if defined(BCM_88470_B0)
  36905     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88470_B0r */
  36906         soc_block_list[22],
  36907         soc_genreg,
  36908         1,
  36909         0,
  36910         0x412,
  36911         0,
  36912         0,
  36913         1,
  36914         soc_OAMP_Y_1731O_PWE_GACH_BCM88470_B0r_fields,
  36915         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36916         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36917         -1,
  36918         -1,
  36919     },
  36920 #endif /* chips */
  36921 
  36922 #if defined(BCM_88650_B0)
  36923     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88650_B0r */
  36924         soc_block_list[22],
  36925         soc_genreg,
  36926         1,
  36927         0,
  36928         0x191,
  36929         SOC_REG_FLAG_SIGNAL,
  36930         0,
  36931         1,
  36932         soc_OAMP_Y_1731O_PWE_GACH_BCM88650_B0r_fields,
  36933         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36935         -1,
  36936         -1,
  36937     },
  36938 #endif /* chips */
  36939 
  36940 #if defined(BCM_88660_A0)
  36941     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88660_A0r */
  36942         soc_block_list[22],
  36943         soc_genreg,
  36944         1,
  36945         0,
  36946         0x40f,
  36947         SOC_REG_FLAG_SIGNAL,
  36948         0,
  36949         1,
  36950         soc_OAMP_Y_1731O_PWE_GACH_BCM88660_A0r_fields,
  36951         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36952         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36953         -1,
  36954         -1,
  36955     },
  36956 #endif /* chips */
  36957 
  36958 #if defined(BCM_88675_A0)
  36959     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88675_A0r */
  36960         soc_block_list[22],
  36961         soc_genreg,
  36962         1,
  36963         0,
  36964         0x410,
  36965         0,
  36966         0,
  36967         1,
  36968         soc_OAMP_Y_1731O_PWE_GACH_BCM88675_A0r_fields,
  36969         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36970         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36971         -1,
  36972         -1,
  36973     },
  36974 #endif /* chips */
  36975 
  36976 #if defined(BCM_88675_B0)
  36977     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88675_B0r */
  36978         soc_block_list[22],
  36979         soc_genreg,
  36980         1,
  36981         0,
  36982         0x410,
  36983         0,
  36984         0,
  36985         1,
  36986         soc_OAMP_Y_1731O_PWE_GACH_BCM88675_B0r_fields,
  36987         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  36988         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36989         -1,
  36990         -1,
  36991     },
  36992 #endif /* chips */
  36993 
  36994 #if defined(BCM_88680_A0)
  36995     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88680_A0r */
  36996         soc_block_list[22],
  36997         soc_genreg,
  36998         1,
  36999         0,
  37000         0x410,
  37001         0,
  37002         0,
  37003         1,
  37004         soc_OAMP_Y_1731O_PWE_GACH_BCM88680_A0r_fields,
  37005         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  37006         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37007         -1,
  37008         -1,
  37009     },
  37010 #endif /* chips */
  37011 
  37012 #if defined(BCM_88690_A0)
  37013     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88690_A0r */
  37014         soc_block_list[22],
  37015         soc_genreg,
  37016         1,
  37017         0,
  37018         0x412,
  37019         0,
  37020         0,
  37021         1,
  37022         soc_OAMP_Y_1731O_PWE_GACH_BCM88690_A0r_fields,
  37023         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  37024         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37025         -1,
  37026         -1,
  37027     },
  37028 #endif /* chips */
  37029 
  37030 #if defined(BCM_88690_B0)
  37031     { /* SOC_REG_INT_OAMP_Y_1731O_PWE_GACH_BCM88690_B0r */
  37032         soc_block_list[22],
  37033         soc_genreg,
  37034         1,
  37035         0,
  37036         0x412,
  37037         0,
  37038         0,
  37039         1,
  37040         soc_OAMP_Y_1731O_PWE_GACH_BCM88690_B0r_fields,
  37041         SOC_RESET_VAL_DEC(0x1000acac, 0x00000000)
  37042         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37043         -1,
  37044         -1,
  37045     },
  37046 #endif /* chips */
  37047 
  37048 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  37049     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  37050     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  37051     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  37052     { /* SOC_REG_INT_OAM_CCM_COUNT_64r */
  37053         soc_block_list[5],
  37054         soc_genreg,
  37055         1,
  37056         0,
  37057         0x80015,
  37058         SOC_REG_FLAG_64_BITS,
  37059         0,
  37060         6,
  37061         soc_OAM_CCM_COUNT_64r_fields,
  37062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37064         -1,
  37065         -1,
  37066     },
  37067 #endif /* chips */
  37068 
  37069 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37070     defined(BCM_56160_A0)
  37071     { /* SOC_REG_INT_OAM_CCM_COUNT_64_BCM53400_A0r */
  37072         soc_block_list[5],
  37073         soc_genreg,
  37074         1,
  37075         0,
  37076         0x2001200,
  37077         SOC_REG_FLAG_64_BITS,
  37078         0,
  37079         6,
  37080         soc_OAM_CCM_COUNT_64_BCM53400_A0r_fields,
  37081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37082         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37083         -1,
  37084         -1,
  37085     },
  37086 #endif /* chips */
  37087 
  37088 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  37089     { /* SOC_REG_INT_OAM_CCM_COUNT_64_BCM53570_A0r */
  37090         soc_block_list[5],
  37091         soc_genreg,
  37092         1,
  37093         0,
  37094         0x2001300,
  37095         SOC_REG_FLAG_64_BITS,
  37096         0,
  37097         6,
  37098         soc_OAM_CCM_COUNT_64_BCM53400_A0r_fields,
  37099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37100         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37101         -1,
  37102         -1,
  37103     },
  37104 #endif /* chips */
  37105 
  37106 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37107     defined(BCM_56270_A0)
  37108     { /* SOC_REG_INT_OAM_CCM_COUNT_64_BCM56260_A0r */
  37109         soc_block_list[5],
  37110         soc_genreg,
  37111         1,
  37112         0,
  37113         0x2000100,
  37114         SOC_REG_FLAG_64_BITS,
  37115         0,
  37116         6,
  37117         soc_OAM_CCM_COUNT_64_BCM53400_A0r_fields,
  37118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37119         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37120         -1,
  37121         -1,
  37122     },
  37123 #endif /* chips */
  37124 
  37125 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  37126     { /* SOC_REG_INT_OAM_CCM_COUNT_64_BCM56440_A0r */
  37127         soc_block_list[5],
  37128         soc_genreg,
  37129         1,
  37130         0,
  37131         0x80601,
  37132         SOC_REG_FLAG_64_BITS,
  37133         0,
  37134         6,
  37135         soc_OAM_CCM_COUNT_64r_fields,
  37136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37137         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37138         -1,
  37139         -1,
  37140     },
  37141 #endif /* chips */
  37142 
  37143 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37144     defined(BCM_56450_B1)
  37145     { /* SOC_REG_INT_OAM_CCM_COUNT_64_BCM56450_A0r */
  37146         soc_block_list[5],
  37147         soc_genreg,
  37148         1,
  37149         0,
  37150         0x2000100,
  37151         SOC_REG_FLAG_64_BITS,
  37152         0,
  37153         6,
  37154         soc_OAM_CCM_COUNT_64_BCM56640_A0r_fields,
  37155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37156         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37157         -1,
  37158         -1,
  37159     },
  37160 #endif /* chips */
  37161 
  37162 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  37163     { /* SOC_REG_INT_OAM_CCM_COUNT_64_BCM56640_A0r */
  37164         soc_block_list[5],
  37165         soc_genreg,
  37166         1,
  37167         0,
  37168         0x2010600,
  37169         SOC_REG_FLAG_64_BITS,
  37170         0,
  37171         6,
  37172         soc_OAM_CCM_COUNT_64_BCM56640_A0r_fields,
  37173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37174         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37175         -1,
  37176         -1,
  37177     },
  37178 #endif /* chips */
  37179 
  37180 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  37181     { /* SOC_REG_INT_OAM_CCM_COUNT_64_BCM56840_A0r */
  37182         soc_block_list[5],
  37183         soc_genreg,
  37184         1,
  37185         0,
  37186         0x80310,
  37187         SOC_REG_FLAG_64_BITS,
  37188         0,
  37189         6,
  37190         soc_OAM_CCM_COUNT_64r_fields,
  37191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37192         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37193         -1,
  37194         -1,
  37195     },
  37196 #endif /* chips */
  37197 
  37198 #if defined(BCM_56850_A0)
  37199     { /* SOC_REG_INT_OAM_CCM_COUNT_64_BCM56850_A0r */
  37200         soc_block_list[5],
  37201         soc_genreg,
  37202         1,
  37203         0,
  37204         0x770e0000,
  37205         SOC_REG_FLAG_64_BITS |
  37206                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  37207         0,
  37208         6,
  37209         soc_OAM_CCM_COUNT_64_BCM56640_A0r_fields,
  37210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37212         -1,
  37213         -1,
  37214     },
  37215 #endif /* chips */
  37216 
  37217 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37218     defined(BCM_56450_B1)
  37219     { /* SOC_REG_INT_OAM_CONTROLr */
  37220         soc_block_list[5],
  37221         soc_genreg,
  37222         1,
  37223         0,
  37224         0xa002f00,
  37225         0,
  37226         0,
  37227         1,
  37228         soc_EGR_OAM_CONTROLr_fields,
  37229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37230         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37231         -1,
  37232         -1,
  37233     },
  37234 #endif /* chips */
  37235 
  37236 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37237     defined(BCM_56450_B1)
  37238     { /* SOC_REG_INT_OAM_CONTROL_1r */
  37239         soc_block_list[5],
  37240         soc_genreg,
  37241         1,
  37242         0,
  37243         0x2e002100,
  37244         0,
  37245         0,
  37246         1,
  37247         soc_EGR_OAM_ERROR_CONTROLr_fields,
  37248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37249         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37250         -1,
  37251         -1,
  37252     },
  37253 #endif /* chips */
  37254 
  37255 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37256     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37257     defined(BCM_56160_A0)
  37258     { /* SOC_REG_INT_OAM_CONTROL_1_BCM53400_A0r */
  37259         soc_block_list[5],
  37260         soc_genreg,
  37261         1,
  37262         0,
  37263         0x32001200,
  37264         0,
  37265         0,
  37266         1,
  37267         soc_OAM_CONTROL_1r_fields,
  37268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37269         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37270         -1,
  37271         -1,
  37272     },
  37273 #endif /* chips */
  37274 
  37275 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37276     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37277     defined(BCM_56160_A0)
  37278     { /* SOC_REG_INT_OAM_CONTROL_BCM53400_A0r */
  37279         soc_block_list[5],
  37280         soc_genreg,
  37281         1,
  37282         0,
  37283         0xa002700,
  37284         0,
  37285         0,
  37286         1,
  37287         soc_OAM_CONTROLr_fields,
  37288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37289         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37290         -1,
  37291         -1,
  37292     },
  37293 #endif /* chips */
  37294 
  37295 #if defined(BCM_56150_A0)
  37296     { /* SOC_REG_INT_OAM_CONTROL_BCM56150_A0r */
  37297         soc_block_list[5],
  37298         soc_genreg,
  37299         1,
  37300         0,
  37301         0xa002700,
  37302         0,
  37303         0,
  37304         1,
  37305         soc_EGR_OAM_CONTROLr_fields,
  37306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37307         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37308         -1,
  37309         -1,
  37310     },
  37311 #endif /* chips */
  37312 
  37313 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37314     defined(BCM_56270_A0)
  37315     { /* SOC_REG_INT_OAM_CONTROL_BCM56260_A0r */
  37316         soc_block_list[5],
  37317         soc_genreg,
  37318         1,
  37319         0,
  37320         0xa002f00,
  37321         0,
  37322         0,
  37323         1,
  37324         soc_OAM_CONTROLr_fields,
  37325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37326         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37327         -1,
  37328         -1,
  37329     },
  37330 #endif /* chips */
  37331 
  37332 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37333     defined(BCM_56270_A0)
  37334     { /* SOC_REG_INT_OAM_COPYTO_CPU_CONTROLr */
  37335         soc_block_list[5],
  37336         soc_genreg,
  37337         1,
  37338         0,
  37339         0x2e008200,
  37340         0,
  37341         0,
  37342         3,
  37343         soc_OAM_COPYTO_CPU_CONTROLr_fields,
  37344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37345         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37346         -1,
  37347         -1,
  37348     },
  37349 #endif /* chips */
  37350 
  37351 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37352     defined(BCM_56270_A0)
  37353     { /* SOC_REG_INT_OAM_COPYTO_CPU_CONTROL_FP_MEPSr */
  37354         soc_block_list[5],
  37355         soc_genreg,
  37356         1,
  37357         0,
  37358         0x3e005200,
  37359         0,
  37360         0,
  37361         3,
  37362         soc_OAM_COPYTO_CPU_CONTROLr_fields,
  37363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37364         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37365         -1,
  37366         -1,
  37367     },
  37368 #endif /* chips */
  37369 
  37370 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  37371     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  37372     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  37373     { /* SOC_REG_INT_OAM_CURRENT_TIMEr */
  37374         soc_block_list[5],
  37375         soc_genreg,
  37376         1,
  37377         0,
  37378         0xa080020,
  37379         0,
  37380         0,
  37381         1,
  37382         soc_OAM_CURRENT_TIMEr_fields,
  37383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37384         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37385         -1,
  37386         -1,
  37387     },
  37388 #endif /* chips */
  37389 
  37390 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37391     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37392     defined(BCM_56160_A0)
  37393     { /* SOC_REG_INT_OAM_CURRENT_TIME_BCM53400_A0r */
  37394         soc_block_list[5],
  37395         soc_genreg,
  37396         1,
  37397         0,
  37398         0x32000800,
  37399         0,
  37400         0,
  37401         1,
  37402         soc_OAM_CURRENT_TIME_BCM53400_A0r_fields,
  37403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37404         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37405         -1,
  37406         -1,
  37407     },
  37408 #endif /* chips */
  37409 
  37410 #if defined(BCM_56150_A0)
  37411     { /* SOC_REG_INT_OAM_CURRENT_TIME_BCM56150_A0r */
  37412         soc_block_list[5],
  37413         soc_genreg,
  37414         1,
  37415         0,
  37416         0x36000800,
  37417         0,
  37418         0,
  37419         1,
  37420         soc_OAM_CURRENT_TIME_BCM56640_A0r_fields,
  37421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37422         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37423         -1,
  37424         -1,
  37425     },
  37426 #endif /* chips */
  37427 
  37428 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37429     defined(BCM_56270_A0)
  37430     { /* SOC_REG_INT_OAM_CURRENT_TIME_BCM56260_A0r */
  37431         soc_block_list[5],
  37432         soc_genreg,
  37433         1,
  37434         0,
  37435         0x2e001200,
  37436         0,
  37437         0,
  37438         1,
  37439         soc_OAM_CURRENT_TIME_BCM53400_A0r_fields,
  37440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37441         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37442         -1,
  37443         -1,
  37444     },
  37445 #endif /* chips */
  37446 
  37447 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  37448     { /* SOC_REG_INT_OAM_CURRENT_TIME_BCM56334_A0r */
  37449         soc_block_list[5],
  37450         soc_genreg,
  37451         1,
  37452         0,
  37453         0xd080020,
  37454         0,
  37455         0,
  37456         1,
  37457         soc_OAM_CURRENT_TIMEr_fields,
  37458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37459         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37460         -1,
  37461         -1,
  37462     },
  37463 #endif /* chips */
  37464 
  37465 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  37466     { /* SOC_REG_INT_OAM_CURRENT_TIME_BCM56440_A0r */
  37467         soc_block_list[5],
  37468         soc_genreg,
  37469         1,
  37470         0,
  37471         0xb080612,
  37472         0,
  37473         0,
  37474         1,
  37475         soc_OAM_CURRENT_TIMEr_fields,
  37476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37477         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37478         -1,
  37479         -1,
  37480     },
  37481 #endif /* chips */
  37482 
  37483 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37484     defined(BCM_56450_B1)
  37485     { /* SOC_REG_INT_OAM_CURRENT_TIME_BCM56450_A0r */
  37486         soc_block_list[5],
  37487         soc_genreg,
  37488         1,
  37489         0,
  37490         0x2e001200,
  37491         0,
  37492         0,
  37493         1,
  37494         soc_OAM_CURRENT_TIME_BCM56640_A0r_fields,
  37495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37496         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37497         -1,
  37498         -1,
  37499     },
  37500 #endif /* chips */
  37501 
  37502 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  37503     { /* SOC_REG_INT_OAM_CURRENT_TIME_BCM56640_A0r */
  37504         soc_block_list[5],
  37505         soc_genreg,
  37506         1,
  37507         0,
  37508         0x2a000c00,
  37509         0,
  37510         0,
  37511         1,
  37512         soc_OAM_CURRENT_TIME_BCM56640_A0r_fields,
  37513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37514         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37515         -1,
  37516         -1,
  37517     },
  37518 #endif /* chips */
  37519 
  37520 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37521     defined(BCM_56450_B1)
  37522     { /* SOC_REG_INT_OAM_C_INTERFACE_DROP_CONTROLr */
  37523         soc_block_list[5],
  37524         soc_genreg,
  37525         1,
  37526         0,
  37527         0x2e001d00,
  37528         0,
  37529         0,
  37530         9,
  37531         soc_OAM_C_INTERFACE_DROP_CONTROLr_fields,
  37532         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  37533         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  37534         -1,
  37535         -1,
  37536     },
  37537 #endif /* chips */
  37538 
  37539 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37540     defined(BCM_56270_A0)
  37541     { /* SOC_REG_INT_OAM_C_INTERFACE_DROP_CONTROL_64r */
  37542         soc_block_list[5],
  37543         soc_genreg,
  37544         1,
  37545         0,
  37546         0x2e008500,
  37547         SOC_REG_FLAG_64_BITS,
  37548         0,
  37549         13,
  37550         soc_OAM_C_INTERFACE_DROP_CONTROL_64r_fields,
  37551         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  37552         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  37553         -1,
  37554         -1,
  37555     },
  37556 #endif /* chips */
  37557 
  37558 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  37559     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  37560     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  37561     { /* SOC_REG_INT_OAM_DROP_CONTROLr */
  37562         soc_block_list[5],
  37563         soc_genreg,
  37564         1,
  37565         0,
  37566         0xa080022,
  37567         0,
  37568         0,
  37569         1,
  37570         soc_OAM_DROP_CONTROLr_fields,
  37571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37572         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37573         -1,
  37574         -1,
  37575     },
  37576 #endif /* chips */
  37577 
  37578 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37579     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37580     defined(BCM_56160_A0)
  37581     { /* SOC_REG_INT_OAM_DROP_CONTROL_BCM53400_A0r */
  37582         soc_block_list[5],
  37583         soc_genreg,
  37584         1,
  37585         0,
  37586         0x32000900,
  37587         0,
  37588         0,
  37589         1,
  37590         soc_OAM_DROP_CONTROL_BCM53400_A0r_fields,
  37591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37592         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37593         -1,
  37594         -1,
  37595     },
  37596 #endif /* chips */
  37597 
  37598 #if defined(BCM_56150_A0)
  37599     { /* SOC_REG_INT_OAM_DROP_CONTROL_BCM56150_A0r */
  37600         soc_block_list[5],
  37601         soc_genreg,
  37602         1,
  37603         0,
  37604         0x36000900,
  37605         0,
  37606         0,
  37607         1,
  37608         soc_OAM_DROP_CONTROL_BCM56640_A0r_fields,
  37609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37610         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37611         -1,
  37612         -1,
  37613     },
  37614 #endif /* chips */
  37615 
  37616 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37617     defined(BCM_56270_A0)
  37618     { /* SOC_REG_INT_OAM_DROP_CONTROL_BCM56260_A0r */
  37619         soc_block_list[5],
  37620         soc_genreg,
  37621         1,
  37622         0,
  37623         0x3e005300,
  37624         0,
  37625         0,
  37626         1,
  37627         soc_OAM_DROP_CONTROL_BCM56260_A0r_fields,
  37628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37629         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37630         -1,
  37631         -1,
  37632     },
  37633 #endif /* chips */
  37634 
  37635 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  37636     { /* SOC_REG_INT_OAM_DROP_CONTROL_BCM56334_A0r */
  37637         soc_block_list[5],
  37638         soc_genreg,
  37639         1,
  37640         0,
  37641         0xd080022,
  37642         0,
  37643         0,
  37644         1,
  37645         soc_OAM_DROP_CONTROLr_fields,
  37646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37647         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37648         -1,
  37649         -1,
  37650     },
  37651 #endif /* chips */
  37652 
  37653 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  37654     { /* SOC_REG_INT_OAM_DROP_CONTROL_BCM56440_A0r */
  37655         soc_block_list[5],
  37656         soc_genreg,
  37657         1,
  37658         0,
  37659         0xb080616,
  37660         0,
  37661         0,
  37662         1,
  37663         soc_OAM_DROP_CONTROLr_fields,
  37664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37665         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37666         -1,
  37667         -1,
  37668     },
  37669 #endif /* chips */
  37670 
  37671 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37672     defined(BCM_56450_B1)
  37673     { /* SOC_REG_INT_OAM_DROP_CONTROL_BCM56450_A0r */
  37674         soc_block_list[5],
  37675         soc_genreg,
  37676         1,
  37677         0,
  37678         0x2e001600,
  37679         0,
  37680         0,
  37681         1,
  37682         soc_OAM_DROP_CONTROL_BCM56450_A0r_fields,
  37683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37684         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37685         -1,
  37686         -1,
  37687     },
  37688 #endif /* chips */
  37689 
  37690 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  37691     { /* SOC_REG_INT_OAM_DROP_CONTROL_BCM56640_A0r */
  37692         soc_block_list[5],
  37693         soc_genreg,
  37694         1,
  37695         0,
  37696         0x2a000d00,
  37697         0,
  37698         0,
  37699         1,
  37700         soc_OAM_DROP_CONTROL_BCM56640_A0r_fields,
  37701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37702         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37703         -1,
  37704         -1,
  37705     },
  37706 #endif /* chips */
  37707 
  37708 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37709     defined(BCM_56270_A0)
  37710     { /* SOC_REG_INT_OAM_ERROR_CONTROLr */
  37711         soc_block_list[5],
  37712         soc_genreg,
  37713         1,
  37714         0,
  37715         0x2e008300,
  37716         0,
  37717         0,
  37718         1,
  37719         soc_OAM_CONTROL_1r_fields,
  37720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37721         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37722         -1,
  37723         -1,
  37724     },
  37725 #endif /* chips */
  37726 
  37727 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37728     defined(BCM_56270_A0)
  37729     { /* SOC_REG_INT_OAM_ERROR_CONTROL_FP_MEPSr */
  37730         soc_block_list[5],
  37731         soc_genreg,
  37732         1,
  37733         0,
  37734         0x3e005100,
  37735         0,
  37736         0,
  37737         1,
  37738         soc_OAM_CONTROL_1r_fields,
  37739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37740         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37741         -1,
  37742         -1,
  37743     },
  37744 #endif /* chips */
  37745 
  37746 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37747     defined(BCM_56270_A0)
  37748     { /* SOC_REG_INT_OAM_FLEXIBLE_DOMAIN_CONTROL_PARITY_CONTROLr */
  37749         soc_block_list[5],
  37750         soc_genreg,
  37751         1,
  37752         0,
  37753         0x2e018100,
  37754         0,
  37755         0,
  37756         1,
  37757         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  37758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37760         -1,
  37761         -1,
  37762     },
  37763 #endif /* chips */
  37764 
  37765 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37766     defined(BCM_56270_A0)
  37767     { /* SOC_REG_INT_OAM_INTF_PROC_SELECT_CONTROL_64r */
  37768         soc_block_list[5],
  37769         soc_genreg,
  37770         1,
  37771         0,
  37772         0x2e008100,
  37773         SOC_REG_FLAG_64_BITS,
  37774         0,
  37775         10,
  37776         soc_EGR_OAM_INTF_PROC_SELECT_CONTROL_64r_fields,
  37777         SOC_RESET_VAL_DEC(0x76543210, 0x00000088)
  37778         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  37779         -1,
  37780         -1,
  37781     },
  37782 #endif /* chips */
  37783 
  37784 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  37785     defined(BCM_56270_A0)
  37786     { /* SOC_REG_INT_OAM_KEY_SELECT_CONTROL_64r */
  37787         soc_block_list[5],
  37788         soc_genreg,
  37789         1,
  37790         0,
  37791         0x2e008000,
  37792         SOC_REG_FLAG_64_BITS,
  37793         0,
  37794         9,
  37795         soc_EGR_OAM_KEY_SELECT_CONTROL_64r_fields,
  37796         SOC_RESET_VAL_DEC(0x76543210, 0x00000008)
  37797         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  37798         -1,
  37799         -1,
  37800     },
  37801 #endif /* chips */
  37802 
  37803 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37804     defined(BCM_56450_B1)
  37805     { /* SOC_REG_INT_OAM_LM_CNG_CONTROLr */
  37806         soc_block_list[5],
  37807         soc_genreg,
  37808         1,
  37809         0,
  37810         0x3e005100,
  37811         0,
  37812         0,
  37813         3,
  37814         soc_OAM_LM_CNG_CONTROLr_fields,
  37815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37816         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37817         -1,
  37818         -1,
  37819     },
  37820 #endif /* chips */
  37821 
  37822 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37823     defined(BCM_56450_B1)
  37824     { /* SOC_REG_INT_OAM_LM_COUNTERS_0_PARITY_CONTROLr */
  37825         soc_block_list[5],
  37826         soc_genreg,
  37827         1,
  37828         0,
  37829         0x3e019200,
  37830         0,
  37831         0,
  37832         1,
  37833         soc_FT_CNTR_SER_CONTROLr_fields,
  37834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37835         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37836         -1,
  37837         -1,
  37838     },
  37839 #endif /* chips */
  37840 
  37841 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37842     defined(BCM_56450_B1)
  37843     { /* SOC_REG_INT_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr */
  37844         soc_block_list[5],
  37845         soc_genreg,
  37846         1,
  37847         0,
  37848         0x3e019300,
  37849         0,
  37850         0,
  37851         3,
  37852         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  37853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37855         -1,
  37856         -1,
  37857     },
  37858 #endif /* chips */
  37859 
  37860 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37861     defined(BCM_56450_B1)
  37862     { /* SOC_REG_INT_OAM_LM_COUNTERS_0_PARITY_STATUS_NACKr */
  37863         soc_block_list[5],
  37864         soc_genreg,
  37865         1,
  37866         0,
  37867         0x3e019400,
  37868         0,
  37869         0,
  37870         3,
  37871         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  37872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37874         -1,
  37875         -1,
  37876     },
  37877 #endif /* chips */
  37878 
  37879 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37880     defined(BCM_56450_B1)
  37881     { /* SOC_REG_INT_OAM_LM_COUNTERS_1_PARITY_CONTROLr */
  37882         soc_block_list[5],
  37883         soc_genreg,
  37884         1,
  37885         0,
  37886         0x3e019500,
  37887         0,
  37888         0,
  37889         1,
  37890         soc_FT_CNTR_SER_CONTROLr_fields,
  37891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37892         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37893         -1,
  37894         -1,
  37895     },
  37896 #endif /* chips */
  37897 
  37898 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37899     defined(BCM_56450_B1)
  37900     { /* SOC_REG_INT_OAM_LM_COUNTERS_1_PARITY_STATUS_INTRr */
  37901         soc_block_list[5],
  37902         soc_genreg,
  37903         1,
  37904         0,
  37905         0x3e019600,
  37906         0,
  37907         0,
  37908         3,
  37909         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  37910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37912         -1,
  37913         -1,
  37914     },
  37915 #endif /* chips */
  37916 
  37917 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37918     defined(BCM_56450_B1)
  37919     { /* SOC_REG_INT_OAM_LM_COUNTERS_1_PARITY_STATUS_NACKr */
  37920         soc_block_list[5],
  37921         soc_genreg,
  37922         1,
  37923         0,
  37924         0x3e019700,
  37925         0,
  37926         0,
  37927         3,
  37928         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  37929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37930         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37931         -1,
  37932         -1,
  37933     },
  37934 #endif /* chips */
  37935 
  37936 #if defined(BCM_56150_A0)
  37937     { /* SOC_REG_INT_OAM_LM_COUNTERS_PARITY_CONTROLr */
  37938         soc_block_list[5],
  37939         soc_genreg,
  37940         1,
  37941         0,
  37942         0x46011500,
  37943         0,
  37944         0,
  37945         1,
  37946         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  37947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37948         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37949         -1,
  37950         -1,
  37951     },
  37952 #endif /* chips */
  37953 
  37954 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37955     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37956     defined(BCM_56160_A0)
  37957     { /* SOC_REG_INT_OAM_LM_COUNTERS_PARITY_CONTROL_BCM53400_A0r */
  37958         soc_block_list[5],
  37959         soc_genreg,
  37960         1,
  37961         0,
  37962         0x42011600,
  37963         0,
  37964         0,
  37965         1,
  37966         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  37967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37968         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37969         -1,
  37970         -1,
  37971     },
  37972 #endif /* chips */
  37973 
  37974 #if defined(BCM_56150_A0)
  37975     { /* SOC_REG_INT_OAM_LM_COUNTERS_PARITY_STATUSr */
  37976         soc_block_list[5],
  37977         soc_genreg,
  37978         1,
  37979         0,
  37980         0x46011600,
  37981         0,
  37982         0,
  37983         3,
  37984         soc_AXP_WTX_DSCP_MAP_PAR_STATUS_INTRr_fields,
  37985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37986         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  37987         -1,
  37988         -1,
  37989     },
  37990 #endif /* chips */
  37991 
  37992 #if defined(BCM_53400_A0)
  37993     { /* SOC_REG_INT_OAM_LM_COUNTERS_PARITY_STATUS_BCM53400_A0r */
  37994         soc_block_list[5],
  37995         soc_genreg,
  37996         1,
  37997         0,
  37998         0x42011700,
  37999         0,
  38000         0,
  38001         3,
  38002         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  38003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38004         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  38005         -1,
  38006         -1,
  38007     },
  38008 #endif /* chips */
  38009 
  38010 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  38011     { /* SOC_REG_INT_OAM_LM_COUNTERS_PARITY_STATUS_BCM53570_A0r */
  38012         soc_block_list[5],
  38013         soc_genreg,
  38014         1,
  38015         0,
  38016         0x42011f00,
  38017         0,
  38018         0,
  38019         3,
  38020         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  38021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38022         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  38023         -1,
  38024         -1,
  38025     },
  38026 #endif /* chips */
  38027 
  38028 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  38029     { /* SOC_REG_INT_OAM_LM_COUNTERS_PARITY_STATUS_BCM56160_A0r */
  38030         soc_block_list[5],
  38031         soc_genreg,
  38032         1,
  38033         0,
  38034         0x42011900,
  38035         0,
  38036         0,
  38037         3,
  38038         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  38039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38040         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  38041         -1,
  38042         -1,
  38043     },
  38044 #endif /* chips */
  38045 
  38046 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  38047     { /* SOC_REG_INT_OAM_LM_COUNTERS_PARITY_STATUS_INTRr */
  38048         soc_block_list[5],
  38049         soc_genreg,
  38050         1,
  38051         0,
  38052         0xf080d8e,
  38053         0,
  38054         0,
  38055         3,
  38056         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  38057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38058         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38059         -1,
  38060         -1,
  38061     },
  38062 #endif /* chips */
  38063 
  38064 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  38065     { /* SOC_REG_INT_OAM_LM_COUNTERS_PARITY_STATUS_NACKr */
  38066         soc_block_list[5],
  38067         soc_genreg,
  38068         1,
  38069         0,
  38070         0xf080d8f,
  38071         0,
  38072         0,
  38073         3,
  38074         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  38075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38076         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38077         -1,
  38078         -1,
  38079     },
  38080 #endif /* chips */
  38081 
  38082 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  38083     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROLr */
  38084         soc_block_list[5],
  38085         soc_genreg,
  38086         1,
  38087         0,
  38088         0x1108005e,
  38089         0,
  38090         0,
  38091         4,
  38092         soc_OAM_LM_CPU_DATA_CONTROLr_fields,
  38093         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38094         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38095         -1,
  38096         -1,
  38097     },
  38098 #endif /* chips */
  38099 
  38100 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38101     defined(BCM_56160_A0)
  38102     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROL_BCM53400_A0r */
  38103         soc_block_list[5],
  38104         soc_genreg,
  38105         1,
  38106         0,
  38107         0x42006700,
  38108         0,
  38109         0,
  38110         4,
  38111         soc_OAM_LM_CPU_DATA_CONTROL_BCM53400_A0r_fields,
  38112         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38113         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38114         -1,
  38115         -1,
  38116     },
  38117 #endif /* chips */
  38118 
  38119 #if defined(BCM_53570_A0)
  38120     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROL_BCM53570_A0r */
  38121         soc_block_list[5],
  38122         soc_genreg,
  38123         1,
  38124         0,
  38125         0x42009800,
  38126         0,
  38127         0,
  38128         4,
  38129         soc_OAM_LM_CPU_DATA_CONTROL_BCM53400_A0r_fields,
  38130         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38131         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38132         -1,
  38133         -1,
  38134     },
  38135 #endif /* chips */
  38136 
  38137 #if defined(BCM_53570_B0)
  38138     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROL_BCM53570_B0r */
  38139         soc_block_list[5],
  38140         soc_genreg,
  38141         1,
  38142         0,
  38143         0x42009c00,
  38144         0,
  38145         0,
  38146         4,
  38147         soc_OAM_LM_CPU_DATA_CONTROL_BCM53400_A0r_fields,
  38148         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38149         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38150         -1,
  38151         -1,
  38152     },
  38153 #endif /* chips */
  38154 
  38155 #if defined(BCM_56150_A0)
  38156     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROL_BCM56150_A0r */
  38157         soc_block_list[5],
  38158         soc_genreg,
  38159         1,
  38160         0,
  38161         0x46006700,
  38162         0,
  38163         0,
  38164         4,
  38165         soc_OAM_LM_CPU_DATA_CONTROL_BCM56640_A0r_fields,
  38166         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38167         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38168         -1,
  38169         -1,
  38170     },
  38171 #endif /* chips */
  38172 
  38173 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38174     defined(BCM_56270_A0)
  38175     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROL_BCM56260_A0r */
  38176         soc_block_list[5],
  38177         soc_genreg,
  38178         1,
  38179         0,
  38180         0x3e005000,
  38181         0,
  38182         0,
  38183         4,
  38184         soc_OAM_LM_CPU_DATA_CONTROL_BCM53400_A0r_fields,
  38185         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38186         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38187         -1,
  38188         -1,
  38189     },
  38190 #endif /* chips */
  38191 
  38192 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  38193     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROL_BCM56440_A0r */
  38194         soc_block_list[5],
  38195         soc_genreg,
  38196         1,
  38197         0,
  38198         0xf080680,
  38199         0,
  38200         0,
  38201         4,
  38202         soc_OAM_LM_CPU_DATA_CONTROLr_fields,
  38203         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38204         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38205         -1,
  38206         -1,
  38207     },
  38208 #endif /* chips */
  38209 
  38210 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38211     defined(BCM_56450_B1)
  38212     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROL_BCM56450_A0r */
  38213         soc_block_list[5],
  38214         soc_genreg,
  38215         1,
  38216         0,
  38217         0x3e005000,
  38218         0,
  38219         0,
  38220         4,
  38221         soc_OAM_LM_CPU_DATA_CONTROL_BCM56640_A0r_fields,
  38222         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38223         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38224         -1,
  38225         -1,
  38226     },
  38227 #endif /* chips */
  38228 
  38229 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  38230     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROL_BCM56640_A0r */
  38231         soc_block_list[5],
  38232         soc_genreg,
  38233         1,
  38234         0,
  38235         0x3a005600,
  38236         0,
  38237         0,
  38238         4,
  38239         soc_OAM_LM_CPU_DATA_CONTROL_BCM56640_A0r_fields,
  38240         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38241         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38242         -1,
  38243         -1,
  38244     },
  38245 #endif /* chips */
  38246 
  38247 #if defined(BCM_56850_A0)
  38248     { /* SOC_REG_INT_OAM_LM_CPU_DATA_CONTROL_BCM56850_A0r */
  38249         soc_block_list[5],
  38250         soc_genreg,
  38251         1,
  38252         0,
  38253         0x46007a00,
  38254         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  38255         0,
  38256         4,
  38257         soc_OAM_LM_CPU_DATA_CONTROL_BCM56640_A0r_fields,
  38258         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38259         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38260         -1,
  38261         -1,
  38262     },
  38263 #endif /* chips */
  38264 
  38265 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  38266     { /* SOC_REG_INT_OAM_LPR_TM_CONTROL_0r */
  38267         soc_block_list[5],
  38268         soc_genreg,
  38269         1,
  38270         0,
  38271         0x2e018500,
  38272         SOC_REG_FLAG_64_BITS,
  38273         0,
  38274         5,
  38275         soc_EGR_OAM_LPR_TM_CONTROL_0_64r_fields,
  38276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38277         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38278         -1,
  38279         -1,
  38280     },
  38281 #endif /* chips */
  38282 
  38283 #if defined(BCM_56270_A0)
  38284     { /* SOC_REG_INT_OAM_LPR_TM_CONTROL_0_BCM56270_A0r */
  38285         soc_block_list[5],
  38286         soc_genreg,
  38287         1,
  38288         0,
  38289         0x2e018500,
  38290         SOC_REG_FLAG_64_BITS,
  38291         0,
  38292         5,
  38293         soc_EGR_OAM_LPR_TM_CONTROL_0_64_BCM56270_A0r_fields,
  38294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38296         -1,
  38297         -1,
  38298     },
  38299 #endif /* chips */
  38300 
  38301 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38302     defined(BCM_56270_A0)
  38303     { /* SOC_REG_INT_OAM_LSP_INTERFACE_DROP_CONTROL_64r */
  38304         soc_block_list[5],
  38305         soc_genreg,
  38306         1,
  38307         0,
  38308         0x2e008a00,
  38309         SOC_REG_FLAG_64_BITS,
  38310         0,
  38311         13,
  38312         soc_OAM_C_INTERFACE_DROP_CONTROL_64r_fields,
  38313         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38314         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  38315         -1,
  38316         -1,
  38317     },
  38318 #endif /* chips */
  38319 
  38320 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38321     defined(BCM_56270_A0)
  38322     { /* SOC_REG_INT_OAM_OPCODE_CONTROL_PROFILE_PARITY_CONTROLr */
  38323         soc_block_list[5],
  38324         soc_genreg,
  38325         1,
  38326         0,
  38327         0x2e018400,
  38328         0,
  38329         0,
  38330         1,
  38331         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  38332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38334         -1,
  38335         -1,
  38336     },
  38337 #endif /* chips */
  38338 
  38339 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38340     defined(BCM_56270_A0)
  38341     { /* SOC_REG_INT_OAM_OPCODE_GROUP_PARITY_CONTROLr */
  38342         soc_block_list[5],
  38343         soc_genreg,
  38344         1,
  38345         0,
  38346         0x2e018300,
  38347         0,
  38348         0,
  38349         1,
  38350         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  38351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38352         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38353         -1,
  38354         -1,
  38355     },
  38356 #endif /* chips */
  38357 
  38358 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38359     defined(BCM_56450_B1)
  38360     { /* SOC_REG_INT_OAM_PORT_INTERFACE_DROP_CONTROLr */
  38361         soc_block_list[5],
  38362         soc_genreg,
  38363         1,
  38364         0,
  38365         0x2e001c00,
  38366         0,
  38367         0,
  38368         9,
  38369         soc_OAM_C_INTERFACE_DROP_CONTROLr_fields,
  38370         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38371         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  38372         -1,
  38373         -1,
  38374     },
  38375 #endif /* chips */
  38376 
  38377 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38378     defined(BCM_56270_A0)
  38379     { /* SOC_REG_INT_OAM_PORT_INTERFACE_DROP_CONTROL_64r */
  38380         soc_block_list[5],
  38381         soc_genreg,
  38382         1,
  38383         0,
  38384         0x2e008400,
  38385         SOC_REG_FLAG_64_BITS,
  38386         0,
  38387         13,
  38388         soc_OAM_C_INTERFACE_DROP_CONTROL_64r_fields,
  38389         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38390         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  38391         -1,
  38392         -1,
  38393     },
  38394 #endif /* chips */
  38395 
  38396 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38397     defined(BCM_56270_A0)
  38398     { /* SOC_REG_INT_OAM_PW_INTERFACE_DROP_CONTROL_64r */
  38399         soc_block_list[5],
  38400         soc_genreg,
  38401         1,
  38402         0,
  38403         0x2e008b00,
  38404         SOC_REG_FLAG_64_BITS,
  38405         0,
  38406         13,
  38407         soc_OAM_C_INTERFACE_DROP_CONTROL_64r_fields,
  38408         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38409         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  38410         -1,
  38411         -1,
  38412     },
  38413 #endif /* chips */
  38414 
  38415 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38416     defined(BCM_56270_A0)
  38417     { /* SOC_REG_INT_OAM_SECTION_INTERFACE_DROP_CONTROL_64r */
  38418         soc_block_list[5],
  38419         soc_genreg,
  38420         1,
  38421         0,
  38422         0x2e008900,
  38423         SOC_REG_FLAG_64_BITS,
  38424         0,
  38425         13,
  38426         soc_OAM_C_INTERFACE_DROP_CONTROL_64r_fields,
  38427         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38428         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  38429         -1,
  38430         -1,
  38431     },
  38432 #endif /* chips */
  38433 
  38434 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  38435     { /* SOC_REG_INT_OAM_SEC_NS_COUNTER_64r */
  38436         soc_block_list[5],
  38437         soc_genreg,
  38438         1,
  38439         0,
  38440         0x80016,
  38441         SOC_REG_FLAG_64_BITS |
  38442                           SOC_REG_FLAG_COUNTER,
  38443         0,
  38444         2,
  38445         soc_OAM_SEC_NS_COUNTER_64r_fields,
  38446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38447         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  38448         22,
  38449         -1,
  38450     },
  38451 #endif /* chips */
  38452 
  38453 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  38454     { /* SOC_REG_INT_OAM_SEC_NS_COUNTER_64_BCM56440_A0r */
  38455         soc_block_list[5],
  38456         soc_genreg,
  38457         1,
  38458         0,
  38459         0x8070d,
  38460         SOC_REG_FLAG_64_BITS |
  38461                           SOC_REG_FLAG_COUNTER,
  38462         0,
  38463         2,
  38464         soc_OAM_SEC_NS_COUNTER_64r_fields,
  38465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38466         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  38467         13,
  38468         -1,
  38469     },
  38470 #endif /* chips */
  38471 
  38472 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  38473     { /* SOC_REG_INT_OAM_SEC_NS_COUNTER_ENABLEr */
  38474         soc_block_list[5],
  38475         soc_genreg,
  38476         1,
  38477         0,
  38478         0x80017,
  38479         0,
  38480         0,
  38481         1,
  38482         soc_OAM_SEC_NS_COUNTER_ENABLEr_fields,
  38483         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38484         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  38485         -1,
  38486         -1,
  38487     },
  38488 #endif /* chips */
  38489 
  38490 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  38491     { /* SOC_REG_INT_OAM_SEC_NS_COUNTER_ENABLE_BCM56440_A0r */
  38492         soc_block_list[5],
  38493         soc_genreg,
  38494         1,
  38495         0,
  38496         0x8070e,
  38497         0,
  38498         0,
  38499         1,
  38500         soc_OAM_SEC_NS_COUNTER_ENABLEr_fields,
  38501         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38502         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  38503         -1,
  38504         -1,
  38505     },
  38506 #endif /* chips */
  38507 
  38508 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38509     defined(BCM_56450_B1)
  38510     { /* SOC_REG_INT_OAM_SVP_INTERFACE_DROP_CONTROLr */
  38511         soc_block_list[5],
  38512         soc_genreg,
  38513         1,
  38514         0,
  38515         0x2e002000,
  38516         0,
  38517         0,
  38518         9,
  38519         soc_OAM_C_INTERFACE_DROP_CONTROLr_fields,
  38520         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38521         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  38522         -1,
  38523         -1,
  38524     },
  38525 #endif /* chips */
  38526 
  38527 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38528     defined(BCM_56450_B1)
  38529     { /* SOC_REG_INT_OAM_S_C_INTERFACE_DROP_CONTROLr */
  38530         soc_block_list[5],
  38531         soc_genreg,
  38532         1,
  38533         0,
  38534         0x2e001f00,
  38535         0,
  38536         0,
  38537         9,
  38538         soc_OAM_C_INTERFACE_DROP_CONTROLr_fields,
  38539         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38540         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  38541         -1,
  38542         -1,
  38543     },
  38544 #endif /* chips */
  38545 
  38546 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38547     defined(BCM_56270_A0)
  38548     { /* SOC_REG_INT_OAM_S_C_INTERFACE_DROP_CONTROL_64r */
  38549         soc_block_list[5],
  38550         soc_genreg,
  38551         1,
  38552         0,
  38553         0x2e008700,
  38554         SOC_REG_FLAG_64_BITS,
  38555         0,
  38556         13,
  38557         soc_OAM_C_INTERFACE_DROP_CONTROL_64r_fields,
  38558         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38559         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  38560         -1,
  38561         -1,
  38562     },
  38563 #endif /* chips */
  38564 
  38565 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38566     defined(BCM_56450_B1)
  38567     { /* SOC_REG_INT_OAM_S_INTERFACE_DROP_CONTROLr */
  38568         soc_block_list[5],
  38569         soc_genreg,
  38570         1,
  38571         0,
  38572         0x2e001e00,
  38573         0,
  38574         0,
  38575         9,
  38576         soc_OAM_C_INTERFACE_DROP_CONTROLr_fields,
  38577         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38578         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  38579         -1,
  38580         -1,
  38581     },
  38582 #endif /* chips */
  38583 
  38584 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38585     defined(BCM_56270_A0)
  38586     { /* SOC_REG_INT_OAM_S_INTERFACE_DROP_CONTROL_64r */
  38587         soc_block_list[5],
  38588         soc_genreg,
  38589         1,
  38590         0,
  38591         0x2e008600,
  38592         SOC_REG_FLAG_64_BITS,
  38593         0,
  38594         13,
  38595         soc_OAM_C_INTERFACE_DROP_CONTROL_64r_fields,
  38596         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  38597         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  38598         -1,
  38599         -1,
  38600     },
  38601 #endif /* chips */
  38602 
  38603 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38604     defined(BCM_56450_B1)
  38605     { /* SOC_REG_INT_OAM_S_INTERFACE_PASSIVE_PROCESSING_CONTROLr */
  38606         soc_block_list[5],
  38607         soc_genreg,
  38608         1,
  38609         0,
  38610         0x2e002200,
  38611         0,
  38612         0,
  38613         2,
  38614         soc_OAM_S_INTERFACE_PASSIVE_PROCESSING_CONTROLr_fields,
  38615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38616         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38617         -1,
  38618         -1,
  38619     },
  38620 #endif /* chips */
  38621 
  38622 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38623     defined(BCM_56270_A0)
  38624     { /* SOC_REG_INT_OAM_S_INTERFACE_PASSIVE_PROCESSING_CONTROL_BCM56260_A0r */
  38625         soc_block_list[5],
  38626         soc_genreg,
  38627         1,
  38628         0,
  38629         0x2e008c00,
  38630         0,
  38631         0,
  38632         3,
  38633         soc_OAM_S_INTERFACE_PASSIVE_PROCESSING_CONTROL_BCM56260_A0r_fields,
  38634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38635         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38636         -1,
  38637         -1,
  38638     },
  38639 #endif /* chips */
  38640 
  38641 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  38642     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  38643     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  38644     { /* SOC_REG_INT_OAM_TIMER_CONTROLr */
  38645         soc_block_list[5],
  38646         soc_genreg,
  38647         1,
  38648         0,
  38649         0x808000f,
  38650         0,
  38651         0,
  38652         3,
  38653         soc_OAM_TIMER_CONTROLr_fields,
  38654         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38655         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38656         -1,
  38657         -1,
  38658     },
  38659 #endif /* chips */
  38660 
  38661 #if defined(BCM_56142_A0)
  38662     { /* SOC_REG_INT_OAM_TIMER_CONTROL_BCM56142_A0r */
  38663         soc_block_list[5],
  38664         soc_genreg,
  38665         1,
  38666         0,
  38667         0x8080147,
  38668         0,
  38669         0,
  38670         3,
  38671         soc_OAM_TIMER_CONTROLr_fields,
  38672         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38673         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38674         -1,
  38675         -1,
  38676     },
  38677 #endif /* chips */
  38678 
  38679 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  38680     { /* SOC_REG_INT_OAM_TIMER_CONTROL_BCM56260_A0r */
  38681         soc_block_list[5],
  38682         soc_genreg,
  38683         1,
  38684         0,
  38685         0x2011200,
  38686         0,
  38687         0,
  38688         3,
  38689         soc_OAM_TIMER_CONTROL_BCM56260_A0r_fields,
  38690         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38691         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38692         -1,
  38693         -1,
  38694     },
  38695 #endif /* chips */
  38696 
  38697 #if defined(BCM_56270_A0)
  38698     { /* SOC_REG_INT_OAM_TIMER_CONTROL_BCM56270_A0r */
  38699         soc_block_list[5],
  38700         soc_genreg,
  38701         1,
  38702         0,
  38703         0x2011300,
  38704         0,
  38705         0,
  38706         3,
  38707         soc_OAM_TIMER_CONTROL_BCM56260_A0r_fields,
  38708         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38709         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38710         -1,
  38711         -1,
  38712     },
  38713 #endif /* chips */
  38714 
  38715 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  38716     { /* SOC_REG_INT_OAM_TIMER_CONTROL_BCM56334_A0r */
  38717         soc_block_list[5],
  38718         soc_genreg,
  38719         1,
  38720         0,
  38721         0x808015f,
  38722         0,
  38723         0,
  38724         3,
  38725         soc_OAM_TIMER_CONTROLr_fields,
  38726         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38727         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38728         -1,
  38729         -1,
  38730     },
  38731 #endif /* chips */
  38732 
  38733 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38734     defined(BCM_56450_B1)
  38735     { /* SOC_REG_INT_OAM_TIMER_CONTROL_BCM56450_A0r */
  38736         soc_block_list[5],
  38737         soc_genreg,
  38738         1,
  38739         0,
  38740         0x2010f00,
  38741         0,
  38742         0,
  38743         3,
  38744         soc_OAM_TIMER_CONTROL_BCM56640_A0r_fields,
  38745         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38746         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38747         -1,
  38748         -1,
  38749     },
  38750 #endif /* chips */
  38751 
  38752 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  38753     { /* SOC_REG_INT_OAM_TIMER_CONTROL_BCM56640_A0r */
  38754         soc_block_list[5],
  38755         soc_genreg,
  38756         1,
  38757         0,
  38758         0x2010700,
  38759         0,
  38760         0,
  38761         3,
  38762         soc_OAM_TIMER_CONTROL_BCM56640_A0r_fields,
  38763         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38764         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38765         -1,
  38766         -1,
  38767     },
  38768 #endif /* chips */
  38769 
  38770 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  38771     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  38772     { /* SOC_REG_INT_OAM_TIMER_CONTROL_BCM56840_A0r */
  38773         soc_block_list[5],
  38774         soc_genreg,
  38775         1,
  38776         0,
  38777         0x80311,
  38778         0,
  38779         0,
  38780         3,
  38781         soc_OAM_TIMER_CONTROLr_fields,
  38782         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38783         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38784         -1,
  38785         -1,
  38786     },
  38787 #endif /* chips */
  38788 
  38789 #if defined(BCM_56850_A0)
  38790     { /* SOC_REG_INT_OAM_TIMER_CONTROL_BCM56850_A0r */
  38791         soc_block_list[5],
  38792         soc_genreg,
  38793         1,
  38794         0,
  38795         0x770f0000,
  38796         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  38797         0,
  38798         3,
  38799         soc_OAM_TIMER_CONTROL_BCM56850_A0r_fields,
  38800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38801         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38802         -1,
  38803         -1,
  38804     },
  38805 #endif /* chips */
  38806 
  38807 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  38808     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  38809     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  38810     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  38811     { /* SOC_REG_INT_OAM_TX_CONTROLr */
  38812         soc_block_list[5],
  38813         soc_genreg,
  38814         1,
  38815         0,
  38816         0x80014,
  38817         0,
  38818         0,
  38819         3,
  38820         soc_OAM_TX_CONTROLr_fields,
  38821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38822         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38823         -1,
  38824         -1,
  38825     },
  38826 #endif /* chips */
  38827 
  38828 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38829     defined(BCM_56160_A0)
  38830     { /* SOC_REG_INT_OAM_TX_CONTROL_BCM53400_A0r */
  38831         soc_block_list[5],
  38832         soc_genreg,
  38833         1,
  38834         0,
  38835         0x2001100,
  38836         0,
  38837         0,
  38838         3,
  38839         soc_OAM_TX_CONTROL_BCM53400_A0r_fields,
  38840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38841         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38842         -1,
  38843         -1,
  38844     },
  38845 #endif /* chips */
  38846 
  38847 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  38848     { /* SOC_REG_INT_OAM_TX_CONTROL_BCM53570_A0r */
  38849         soc_block_list[5],
  38850         soc_genreg,
  38851         1,
  38852         0,
  38853         0x2001200,
  38854         0,
  38855         0,
  38856         3,
  38857         soc_OAM_TX_CONTROL_BCM53400_A0r_fields,
  38858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38859         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38860         -1,
  38861         -1,
  38862     },
  38863 #endif /* chips */
  38864 
  38865 #if defined(BCM_56150_A0)
  38866     { /* SOC_REG_INT_OAM_TX_CONTROL_BCM56150_A0r */
  38867         soc_block_list[5],
  38868         soc_genreg,
  38869         1,
  38870         0,
  38871         0x2001100,
  38872         0,
  38873         0,
  38874         3,
  38875         soc_OAM_TX_CONTROL_BCM56640_A0r_fields,
  38876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38877         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38878         -1,
  38879         -1,
  38880     },
  38881 #endif /* chips */
  38882 
  38883 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38884     defined(BCM_56270_A0)
  38885     { /* SOC_REG_INT_OAM_TX_CONTROL_BCM56260_A0r */
  38886         soc_block_list[5],
  38887         soc_genreg,
  38888         1,
  38889         0,
  38890         0x2000000,
  38891         0,
  38892         0,
  38893         3,
  38894         soc_OAM_TX_CONTROL_BCM53400_A0r_fields,
  38895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38896         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38897         -1,
  38898         -1,
  38899     },
  38900 #endif /* chips */
  38901 
  38902 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  38903     { /* SOC_REG_INT_OAM_TX_CONTROL_BCM56440_A0r */
  38904         soc_block_list[5],
  38905         soc_genreg,
  38906         1,
  38907         0,
  38908         0x80600,
  38909         0,
  38910         0,
  38911         3,
  38912         soc_OAM_TX_CONTROLr_fields,
  38913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38914         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38915         -1,
  38916         -1,
  38917     },
  38918 #endif /* chips */
  38919 
  38920 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38921     defined(BCM_56450_B1)
  38922     { /* SOC_REG_INT_OAM_TX_CONTROL_BCM56450_A0r */
  38923         soc_block_list[5],
  38924         soc_genreg,
  38925         1,
  38926         0,
  38927         0x2000000,
  38928         0,
  38929         0,
  38930         3,
  38931         soc_OAM_TX_CONTROL_BCM56640_A0r_fields,
  38932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38933         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38934         -1,
  38935         -1,
  38936     },
  38937 #endif /* chips */
  38938 
  38939 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  38940     { /* SOC_REG_INT_OAM_TX_CONTROL_BCM56640_A0r */
  38941         soc_block_list[5],
  38942         soc_genreg,
  38943         1,
  38944         0,
  38945         0x2010500,
  38946         0,
  38947         0,
  38948         3,
  38949         soc_OAM_TX_CONTROL_BCM56640_A0r_fields,
  38950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38951         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38952         -1,
  38953         -1,
  38954     },
  38955 #endif /* chips */
  38956 
  38957 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  38958     { /* SOC_REG_INT_OAM_TX_CONTROL_BCM56840_A0r */
  38959         soc_block_list[5],
  38960         soc_genreg,
  38961         1,
  38962         0,
  38963         0x8030f,
  38964         0,
  38965         0,
  38966         3,
  38967         soc_OAM_TX_CONTROLr_fields,
  38968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38969         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38970         -1,
  38971         -1,
  38972     },
  38973 #endif /* chips */
  38974 
  38975 #if defined(BCM_56850_A0)
  38976     { /* SOC_REG_INT_OAM_TX_CONTROL_BCM56850_A0r */
  38977         soc_block_list[5],
  38978         soc_genreg,
  38979         1,
  38980         0,
  38981         0x770d0000,
  38982         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  38983         0,
  38984         4,
  38985         soc_OAM_TX_CONTROL_BCM56850_A0r_fields,
  38986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38987         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38988         -1,
  38989         -1,
  38990     },
  38991 #endif /* chips */
  38992 
  38993 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  38994     defined(BCM_56270_A0)
  38995     { /* SOC_REG_INT_OAM_VP_INTERFACE_DROP_CONTROL_64r */
  38996         soc_block_list[5],
  38997         soc_genreg,
  38998         1,
  38999         0,
  39000         0x2e008800,
  39001         SOC_REG_FLAG_64_BITS,
  39002         0,
  39003         13,
  39004         soc_OAM_C_INTERFACE_DROP_CONTROL_64r_fields,
  39005         SOC_RESET_VAL_DEC(0x000e01c1, 0x00000000)
  39006         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  39007         -1,
  39008         -1,
  39009     },
  39010 #endif /* chips */
  39011 
  39012 #if defined(BCM_88690_A0)
  39013     { /* SOC_REG_INT_OCB_BANKS_FULL_TH_REGISTERr */
  39014         soc_block_list[51],
  39015         soc_genreg,
  39016         1,
  39017         0,
  39018         0x105,
  39019         0,
  39020         0,
  39021         2,
  39022         soc_OCB_BANKS_FULL_TH_REGISTERr_fields,
  39023         SOC_RESET_VAL_DEC(0x0000c190, 0x00000000)
  39024         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  39025         -1,
  39026         -1,
  39027     },
  39028 #endif /* chips */
  39029 
  39030 #if defined(BCM_88690_B0)
  39031     { /* SOC_REG_INT_OCB_BANKS_FULL_TH_REGISTER_BCM88690_B0r */
  39032         soc_block_list[51],
  39033         soc_genreg,
  39034         1,
  39035         0,
  39036         0x107,
  39037         0,
  39038         0,
  39039         2,
  39040         soc_OCB_BANKS_FULL_TH_REGISTER_BCM88690_B0r_fields,
  39041         SOC_RESET_VAL_DEC(0x0000c190, 0x00000000)
  39042         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  39043         -1,
  39044         -1,
  39045     },
  39046 #endif /* chips */
  39047 
  39048 #if defined(BCM_88675_A0)
  39049     { /* SOC_REG_INT_OCB_BANK_ORDER_FIFO_STATUSr */
  39050         soc_block_list[51],
  39051         soc_genreg,
  39052         1,
  39053         0,
  39054         0x245,
  39055         SOC_REG_FLAG_RO |
  39056                           SOC_REG_FLAG_SIGNAL,
  39057         0,
  39058         1,
  39059         soc_OCB_BANK_ORDER_FIFO_STATUSr_fields,
  39060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39061         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  39062         -1,
  39063         -1,
  39064     },
  39065 #endif /* chips */
  39066 
  39067 #if defined(BCM_88375_A0)
  39068     { /* SOC_REG_INT_OCB_BANK_ORDER_FIFO_STATUS_BCM88375_A0r */
  39069         soc_block_list[51],
  39070         soc_genreg,
  39071         1,
  39072         0,
  39073         0x245,
  39074         SOC_REG_FLAG_RO |
  39075                           SOC_REG_FLAG_SIGNAL,
  39076         0,
  39077         1,
  39078         soc_OCB_BANK_ORDER_FIFO_STATUS_BCM88375_A0r_fields,
  39079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39080         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  39081         -1,
  39082         -1,
  39083     },
  39084 #endif /* chips */
  39085 
  39086 #if defined(BCM_88375_B0)
  39087     { /* SOC_REG_INT_OCB_BANK_ORDER_FIFO_STATUS_BCM88375_B0r */
  39088         soc_block_list[51],
  39089         soc_genreg,
  39090         1,
  39091         0,
  39092         0x245,
  39093         SOC_REG_FLAG_RO |
  39094                           SOC_REG_FLAG_SIGNAL,
  39095         0,
  39096         1,
  39097         soc_OCB_BANK_ORDER_FIFO_STATUS_BCM88375_B0r_fields,
  39098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39099         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  39100         -1,
  39101         -1,
  39102     },
  39103 #endif /* chips */
  39104 
  39105 #if defined(BCM_88675_B0)
  39106     { /* SOC_REG_INT_OCB_BANK_ORDER_FIFO_STATUS_BCM88675_B0r */
  39107         soc_block_list[51],
  39108         soc_genreg,
  39109         1,
  39110         0,
  39111         0x245,
  39112         SOC_REG_FLAG_RO |
  39113                           SOC_REG_FLAG_SIGNAL,
  39114         0,
  39115         1,
  39116         soc_OCB_BANK_ORDER_FIFO_STATUS_BCM88675_B0r_fields,
  39117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39118         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  39119         -1,
  39120         -1,
  39121     },
  39122 #endif /* chips */
  39123 
  39124 #if defined(BCM_88680_A0)
  39125     { /* SOC_REG_INT_OCB_BANK_ORDER_FIFO_STATUS_BCM88680_A0r */
  39126         soc_block_list[51],
  39127         soc_genreg,
  39128         1,
  39129         0,
  39130         0x245,
  39131         SOC_REG_FLAG_RO |
  39132                           SOC_REG_FLAG_SIGNAL,
  39133         0,
  39134         1,
  39135         soc_OCB_BANK_ORDER_FIFO_STATUS_BCM88680_A0r_fields,
  39136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39137         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  39138         -1,
  39139         -1,
  39140     },
  39141 #endif /* chips */
  39142 
  39143 #if defined(BCM_88675_A0)
  39144     { /* SOC_REG_INT_OCB_DEBUG_CRC_FORCE_ERRr */
  39145         soc_block_list[51],
  39146         soc_genreg,
  39147         1,
  39148         0,
  39149         0x201,
  39150         0,
  39151         0,
  39152         5,
  39153         soc_OCB_DEBUG_CRC_FORCE_ERRr_fields,
  39154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39155         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  39156         -1,
  39157         -1,
  39158     },
  39159 #endif /* chips */
  39160 
  39161 #if defined(BCM_88375_A0)
  39162     { /* SOC_REG_INT_OCB_DEBUG_CRC_FORCE_ERR_BCM88375_A0r */
  39163         soc_block_list[51],
  39164         soc_genreg,
  39165         1,
  39166         0,
  39167         0x201,
  39168         0,
  39169         0,
  39170         5,
  39171         soc_OCB_DEBUG_CRC_FORCE_ERR_BCM88375_A0r_fields,
  39172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39173         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  39174         -1,
  39175         -1,
  39176     },
  39177 #endif /* chips */
  39178 
  39179 #if defined(BCM_88375_B0)
  39180     { /* SOC_REG_INT_OCB_DEBUG_CRC_FORCE_ERR_BCM88375_B0r */
  39181         soc_block_list[51],
  39182         soc_genreg,
  39183         1,
  39184         0,
  39185         0x201,
  39186         0,
  39187         0,
  39188         5,
  39189         soc_OCB_DEBUG_CRC_FORCE_ERR_BCM88375_B0r_fields,
  39190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39191         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  39192         -1,
  39193         -1,
  39194     },
  39195 #endif /* chips */
  39196 
  39197 #if defined(BCM_88675_B0)
  39198     { /* SOC_REG_INT_OCB_DEBUG_CRC_FORCE_ERR_BCM88675_B0r */
  39199         soc_block_list[51],
  39200         soc_genreg,
  39201         1,
  39202         0,
  39203         0x201,
  39204         0,
  39205         0,
  39206         5,
  39207         soc_OCB_DEBUG_CRC_FORCE_ERR_BCM88675_B0r_fields,
  39208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39209         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  39210         -1,
  39211         -1,
  39212     },
  39213 #endif /* chips */
  39214 
  39215 #if defined(BCM_88680_A0)
  39216     { /* SOC_REG_INT_OCB_DEBUG_CRC_FORCE_ERR_BCM88680_A0r */
  39217         soc_block_list[51],
  39218         soc_genreg,
  39219         1,
  39220         0,
  39221         0x201,
  39222         0,
  39223         0,
  39224         5,
  39225         soc_OCB_DEBUG_CRC_FORCE_ERR_BCM88680_A0r_fields,
  39226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39227         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  39228         -1,
  39229         -1,
  39230     },
  39231 #endif /* chips */
  39232 
  39233 #if defined(BCM_88690_A0)
  39234     { /* SOC_REG_INT_OCB_DISABLE_BANK_DBGr */
  39235         soc_block_list[51],
  39236         soc_genreg,
  39237         1,
  39238         0,
  39239         0x140,
  39240         0,
  39241         0,
  39242         1,
  39243         soc_OCB_DISABLE_BANK_DBGr_fields,
  39244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39245         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  39246         -1,
  39247         -1,
  39248     },
  39249 #endif /* chips */
  39250 
  39251 #if defined(BCM_88690_B0)
  39252     { /* SOC_REG_INT_OCB_DISABLE_BANK_DBG_BCM88690_B0r */
  39253         soc_block_list[51],
  39254         soc_genreg,
  39255         1,
  39256         0,
  39257         0x142,
  39258         0,
  39259         0,
  39260         1,
  39261         soc_OCB_DISABLE_BANK_DBG_BCM88690_B0r_fields,
  39262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39263         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  39264         -1,
  39265         -1,
  39266     },
  39267 #endif /* chips */
  39268 
  39269 #if defined(BCM_88690_A0)
  39270     { /* SOC_REG_INT_OCB_DISABLE_REQ_DBGr */
  39271         soc_block_list[51],
  39272         soc_genreg,
  39273         1,
  39274         0,
  39275         0x141,
  39276         0,
  39277         0,
  39278         2,
  39279         soc_OCB_DISABLE_REQ_DBGr_fields,
  39280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39281         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  39282         -1,
  39283         -1,
  39284     },
  39285 #endif /* chips */
  39286 
  39287 #if defined(BCM_88690_B0)
  39288     { /* SOC_REG_INT_OCB_DISABLE_REQ_DBG_BCM88690_B0r */
  39289         soc_block_list[51],
  39290         soc_genreg,
  39291         1,
  39292         0,
  39293         0x143,
  39294         0,
  39295         0,
  39296         2,
  39297         soc_OCB_DISABLE_REQ_DBG_BCM88690_B0r_fields,
  39298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39299         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  39300         -1,
  39301         -1,
  39302     },
  39303 #endif /* chips */
  39304 
  39305 #if defined(BCM_88690_A0)
  39306     { /* SOC_REG_INT_OCB_DYNAMIC_CONFIGURATIONr */
  39307         soc_block_list[51],
  39308         soc_genreg,
  39309         1,
  39310         0,
  39311         0x103,
  39312         0,
  39313         0,
  39314         2,
  39315         soc_OCB_DYNAMIC_CONFIGURATIONr_fields,
  39316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39317         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  39318         -1,
  39319         -1,
  39320     },
  39321 #endif /* chips */
  39322 
  39323 #if defined(BCM_88690_B0)
  39324     { /* SOC_REG_INT_OCB_DYNAMIC_CONFIGURATION_BCM88690_B0r */
  39325         soc_block_list[51],
  39326         soc_genreg,
  39327         1,
  39328         0,
  39329         0x105,
  39330         0,
  39331         0,
  39332         2,
  39333         soc_OCB_DYNAMIC_CONFIGURATION_BCM88690_B0r_fields,
  39334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39335         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  39336         -1,
  39337         -1,
  39338     },
  39339 #endif /* chips */
  39340 
  39341 #if defined(BCM_88202_A0)
  39342     { /* SOC_REG_INT_OCB_ECC_1B_ERR_CNTr */
  39343         soc_block_list[51],
  39344         soc_genreg,
  39345         1,
  39346         0,
  39347         0x94,
  39348         SOC_REG_FLAG_64_BITS |
  39349                           SOC_REG_FLAG_RO,
  39350         0,
  39351         4,
  39352         soc_OCB_ECC_1B_ERR_CNTr_fields,
  39353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39354         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39355         -1,
  39356         -1,
  39357     },
  39358 #endif /* chips */
  39359 
  39360 #if defined(BCM_88375_A0)
  39361     { /* SOC_REG_INT_OCB_ECC_1B_ERR_CNT_BCM88375_A0r */
  39362         soc_block_list[51],
  39363         soc_genreg,
  39364         1,
  39365         0,
  39366         0x94,
  39367         SOC_REG_FLAG_64_BITS |
  39368                           SOC_REG_FLAG_RO,
  39369         0,
  39370         4,
  39371         soc_OCB_ECC_1B_ERR_CNT_BCM88375_A0r_fields,
  39372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39373         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39374         -1,
  39375         -1,
  39376     },
  39377 #endif /* chips */
  39378 
  39379 #if defined(BCM_88375_B0)
  39380     { /* SOC_REG_INT_OCB_ECC_1B_ERR_CNT_BCM88375_B0r */
  39381         soc_block_list[51],
  39382         soc_genreg,
  39383         1,
  39384         0,
  39385         0x94,
  39386         SOC_REG_FLAG_64_BITS |
  39387                           SOC_REG_FLAG_RO,
  39388         0,
  39389         4,
  39390         soc_OCB_ECC_1B_ERR_CNT_BCM88375_B0r_fields,
  39391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39392         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39393         -1,
  39394         -1,
  39395     },
  39396 #endif /* chips */
  39397 
  39398 #if defined(BCM_88675_A0)
  39399     { /* SOC_REG_INT_OCB_ECC_1B_ERR_CNT_BCM88675_A0r */
  39400         soc_block_list[51],
  39401         soc_genreg,
  39402         1,
  39403         0,
  39404         0x94,
  39405         SOC_REG_FLAG_64_BITS |
  39406                           SOC_REG_FLAG_RO,
  39407         0,
  39408         4,
  39409         soc_OCB_ECC_1B_ERR_CNT_BCM88675_A0r_fields,
  39410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39411         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39412         -1,
  39413         -1,
  39414     },
  39415 #endif /* chips */
  39416 
  39417 #if defined(BCM_88675_B0)
  39418     { /* SOC_REG_INT_OCB_ECC_1B_ERR_CNT_BCM88675_B0r */
  39419         soc_block_list[51],
  39420         soc_genreg,
  39421         1,
  39422         0,
  39423         0x94,
  39424         SOC_REG_FLAG_64_BITS |
  39425                           SOC_REG_FLAG_RO,
  39426         0,
  39427         4,
  39428         soc_OCB_ECC_1B_ERR_CNT_BCM88675_B0r_fields,
  39429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39430         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39431         -1,
  39432         -1,
  39433     },
  39434 #endif /* chips */
  39435 
  39436 #if defined(BCM_88680_A0)
  39437     { /* SOC_REG_INT_OCB_ECC_1B_ERR_CNT_BCM88680_A0r */
  39438         soc_block_list[51],
  39439         soc_genreg,
  39440         1,
  39441         0,
  39442         0x94,
  39443         SOC_REG_FLAG_64_BITS |
  39444                           SOC_REG_FLAG_RO,
  39445         0,
  39446         4,
  39447         soc_OCB_ECC_1B_ERR_CNT_BCM88680_A0r_fields,
  39448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39449         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39450         -1,
  39451         -1,
  39452     },
  39453 #endif /* chips */
  39454 
  39455 #if defined(BCM_88690_A0)
  39456     { /* SOC_REG_INT_OCB_ECC_1B_ERR_CNT_BCM88690_A0r */
  39457         soc_block_list[51],
  39458         soc_genreg,
  39459         1,
  39460         0,
  39461         0x94,
  39462         SOC_REG_FLAG_64_BITS |
  39463                           SOC_REG_FLAG_RO,
  39464         SOC_REG_FLAG_COUNTER_FEILDS |
  39465                           SOC_REG_FLAG_INIT_ON_READ,
  39466         4,
  39467         soc_OCB_ECC_1B_ERR_CNT_BCM88690_A0r_fields,
  39468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39469         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39470         -1,
  39471         -1,
  39472     },
  39473 #endif /* chips */
  39474 
  39475 #if defined(BCM_88690_B0)
  39476     { /* SOC_REG_INT_OCB_ECC_1B_ERR_CNT_BCM88690_B0r */
  39477         soc_block_list[51],
  39478         soc_genreg,
  39479         1,
  39480         0,
  39481         0x94,
  39482         SOC_REG_FLAG_64_BITS |
  39483                           SOC_REG_FLAG_RO,
  39484         SOC_REG_FLAG_COUNTER_FEILDS |
  39485                           SOC_REG_FLAG_INIT_ON_READ,
  39486         4,
  39487         soc_OCB_ECC_1B_ERR_CNT_BCM88690_B0r_fields,
  39488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39489         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39490         -1,
  39491         -1,
  39492     },
  39493 #endif /* chips */
  39494 
  39495 #if defined(BCM_88202_A0)
  39496     { /* SOC_REG_INT_OCB_ECC_2B_ERR_CNTr */
  39497         soc_block_list[51],
  39498         soc_genreg,
  39499         1,
  39500         0,
  39501         0x96,
  39502         SOC_REG_FLAG_64_BITS |
  39503                           SOC_REG_FLAG_RO,
  39504         0,
  39505         4,
  39506         soc_OCB_ECC_2B_ERR_CNTr_fields,
  39507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39508         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39509         -1,
  39510         -1,
  39511     },
  39512 #endif /* chips */
  39513 
  39514 #if defined(BCM_88375_A0)
  39515     { /* SOC_REG_INT_OCB_ECC_2B_ERR_CNT_BCM88375_A0r */
  39516         soc_block_list[51],
  39517         soc_genreg,
  39518         1,
  39519         0,
  39520         0x96,
  39521         SOC_REG_FLAG_64_BITS |
  39522                           SOC_REG_FLAG_RO,
  39523         0,
  39524         4,
  39525         soc_OCB_ECC_2B_ERR_CNT_BCM88375_A0r_fields,
  39526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39527         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39528         -1,
  39529         -1,
  39530     },
  39531 #endif /* chips */
  39532 
  39533 #if defined(BCM_88375_B0)
  39534     { /* SOC_REG_INT_OCB_ECC_2B_ERR_CNT_BCM88375_B0r */
  39535         soc_block_list[51],
  39536         soc_genreg,
  39537         1,
  39538         0,
  39539         0x96,
  39540         SOC_REG_FLAG_64_BITS |
  39541                           SOC_REG_FLAG_RO,
  39542         0,
  39543         4,
  39544         soc_OCB_ECC_2B_ERR_CNT_BCM88375_B0r_fields,
  39545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39546         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39547         -1,
  39548         -1,
  39549     },
  39550 #endif /* chips */
  39551 
  39552 #if defined(BCM_88675_A0)
  39553     { /* SOC_REG_INT_OCB_ECC_2B_ERR_CNT_BCM88675_A0r */
  39554         soc_block_list[51],
  39555         soc_genreg,
  39556         1,
  39557         0,
  39558         0x96,
  39559         SOC_REG_FLAG_64_BITS |
  39560                           SOC_REG_FLAG_RO,
  39561         0,
  39562         4,
  39563         soc_OCB_ECC_2B_ERR_CNT_BCM88675_A0r_fields,
  39564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39565         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39566         -1,
  39567         -1,
  39568     },
  39569 #endif /* chips */
  39570 
  39571 #if defined(BCM_88675_B0)
  39572     { /* SOC_REG_INT_OCB_ECC_2B_ERR_CNT_BCM88675_B0r */
  39573         soc_block_list[51],
  39574         soc_genreg,
  39575         1,
  39576         0,
  39577         0x96,
  39578         SOC_REG_FLAG_64_BITS |
  39579                           SOC_REG_FLAG_RO,
  39580         0,
  39581         4,
  39582         soc_OCB_ECC_2B_ERR_CNT_BCM88675_B0r_fields,
  39583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39584         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39585         -1,
  39586         -1,
  39587     },
  39588 #endif /* chips */
  39589 
  39590 #if defined(BCM_88680_A0)
  39591     { /* SOC_REG_INT_OCB_ECC_2B_ERR_CNT_BCM88680_A0r */
  39592         soc_block_list[51],
  39593         soc_genreg,
  39594         1,
  39595         0,
  39596         0x96,
  39597         SOC_REG_FLAG_64_BITS |
  39598                           SOC_REG_FLAG_RO,
  39599         0,
  39600         4,
  39601         soc_OCB_ECC_2B_ERR_CNT_BCM88680_A0r_fields,
  39602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39603         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39604         -1,
  39605         -1,
  39606     },
  39607 #endif /* chips */
  39608 
  39609 #if defined(BCM_88690_A0)
  39610     { /* SOC_REG_INT_OCB_ECC_2B_ERR_CNT_BCM88690_A0r */
  39611         soc_block_list[51],
  39612         soc_genreg,
  39613         1,
  39614         0,
  39615         0x96,
  39616         SOC_REG_FLAG_64_BITS |
  39617                           SOC_REG_FLAG_RO,
  39618         SOC_REG_FLAG_COUNTER_FEILDS |
  39619                           SOC_REG_FLAG_INIT_ON_READ,
  39620         4,
  39621         soc_OCB_ECC_2B_ERR_CNT_BCM88690_A0r_fields,
  39622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39623         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39624         -1,
  39625         -1,
  39626     },
  39627 #endif /* chips */
  39628 
  39629 #if defined(BCM_88690_B0)
  39630     { /* SOC_REG_INT_OCB_ECC_2B_ERR_CNT_BCM88690_B0r */
  39631         soc_block_list[51],
  39632         soc_genreg,
  39633         1,
  39634         0,
  39635         0x96,
  39636         SOC_REG_FLAG_64_BITS |
  39637                           SOC_REG_FLAG_RO,
  39638         SOC_REG_FLAG_COUNTER_FEILDS |
  39639                           SOC_REG_FLAG_INIT_ON_READ,
  39640         4,
  39641         soc_OCB_ECC_2B_ERR_CNT_BCM88690_B0r_fields,
  39642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39643         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  39644         -1,
  39645         -1,
  39646     },
  39647 #endif /* chips */
  39648 
  39649 #if defined(BCM_88675_A0)
  39650     { /* SOC_REG_INT_OCB_ECC_ERR_1B_INITIATEr */
  39651         soc_block_list[51],
  39652         soc_genreg,
  39653         1,
  39654         0,
  39655         0xa4,
  39656         0,
  39657         0,
  39658         1,
  39659         soc_OCB_ECC_ERR_1B_INITIATEr_fields,
  39660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39661         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39662         -1,
  39663         -1,
  39664     },
  39665 #endif /* chips */
  39666 
  39667 #if defined(BCM_88202_A0)
  39668     { /* SOC_REG_INT_OCB_ECC_ERR_1B_INITIATE_1r */
  39669         soc_block_list[51],
  39670         soc_genreg,
  39671         1,
  39672         0,
  39673         0xa6,
  39674         0,
  39675         0,
  39676         2,
  39677         soc_OCB_ECC_ERR_1B_INITIATE_1r_fields,
  39678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39679         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  39680         -1,
  39681         -1,
  39682     },
  39683 #endif /* chips */
  39684 
  39685 #if defined(BCM_88375_A0)
  39686     { /* SOC_REG_INT_OCB_ECC_ERR_1B_INITIATE_BCM88375_A0r */
  39687         soc_block_list[51],
  39688         soc_genreg,
  39689         1,
  39690         0,
  39691         0xa4,
  39692         0,
  39693         0,
  39694         1,
  39695         soc_OCB_ECC_ERR_1B_INITIATE_BCM88375_A0r_fields,
  39696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39697         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39698         -1,
  39699         -1,
  39700     },
  39701 #endif /* chips */
  39702 
  39703 #if defined(BCM_88375_B0)
  39704     { /* SOC_REG_INT_OCB_ECC_ERR_1B_INITIATE_BCM88375_B0r */
  39705         soc_block_list[51],
  39706         soc_genreg,
  39707         1,
  39708         0,
  39709         0xa4,
  39710         0,
  39711         0,
  39712         1,
  39713         soc_OCB_ECC_ERR_1B_INITIATE_BCM88375_B0r_fields,
  39714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39715         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39716         -1,
  39717         -1,
  39718     },
  39719 #endif /* chips */
  39720 
  39721 #if defined(BCM_88675_B0)
  39722     { /* SOC_REG_INT_OCB_ECC_ERR_1B_INITIATE_BCM88675_B0r */
  39723         soc_block_list[51],
  39724         soc_genreg,
  39725         1,
  39726         0,
  39727         0xa4,
  39728         0,
  39729         0,
  39730         1,
  39731         soc_OCB_ECC_ERR_1B_INITIATE_BCM88675_B0r_fields,
  39732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39733         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39734         -1,
  39735         -1,
  39736     },
  39737 #endif /* chips */
  39738 
  39739 #if defined(BCM_88680_A0)
  39740     { /* SOC_REG_INT_OCB_ECC_ERR_1B_INITIATE_BCM88680_A0r */
  39741         soc_block_list[51],
  39742         soc_genreg,
  39743         1,
  39744         0,
  39745         0xa4,
  39746         0,
  39747         0,
  39748         1,
  39749         soc_OCB_ECC_ERR_1B_INITIATE_BCM88680_A0r_fields,
  39750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39751         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39752         -1,
  39753         -1,
  39754     },
  39755 #endif /* chips */
  39756 
  39757 #if defined(BCM_88202_A0)
  39758     { /* SOC_REG_INT_OCB_ECC_ERR_1B_MONITOR_MEM_MASKr */
  39759         soc_block_list[51],
  39760         soc_genreg,
  39761         1,
  39762         0,
  39763         0x9c,
  39764         0,
  39765         0,
  39766         2,
  39767         soc_OCB_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  39768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39769         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  39770         -1,
  39771         -1,
  39772     },
  39773 #endif /* chips */
  39774 
  39775 #if defined(BCM_88375_A0)
  39776     { /* SOC_REG_INT_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r */
  39777         soc_block_list[51],
  39778         soc_genreg,
  39779         1,
  39780         0,
  39781         0x9a,
  39782         0,
  39783         0,
  39784         1,
  39785         soc_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
  39786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39787         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39788         -1,
  39789         -1,
  39790     },
  39791 #endif /* chips */
  39792 
  39793 #if defined(BCM_88375_B0)
  39794     { /* SOC_REG_INT_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r */
  39795         soc_block_list[51],
  39796         soc_genreg,
  39797         1,
  39798         0,
  39799         0x9a,
  39800         0,
  39801         0,
  39802         1,
  39803         soc_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
  39804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39805         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39806         -1,
  39807         -1,
  39808     },
  39809 #endif /* chips */
  39810 
  39811 #if defined(BCM_88675_A0)
  39812     { /* SOC_REG_INT_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_A0r */
  39813         soc_block_list[51],
  39814         soc_genreg,
  39815         1,
  39816         0,
  39817         0x9a,
  39818         0,
  39819         0,
  39820         1,
  39821         soc_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_A0r_fields,
  39822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39823         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39824         -1,
  39825         -1,
  39826     },
  39827 #endif /* chips */
  39828 
  39829 #if defined(BCM_88675_B0)
  39830     { /* SOC_REG_INT_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r */
  39831         soc_block_list[51],
  39832         soc_genreg,
  39833         1,
  39834         0,
  39835         0x9a,
  39836         0,
  39837         0,
  39838         1,
  39839         soc_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
  39840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39841         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39842         -1,
  39843         -1,
  39844     },
  39845 #endif /* chips */
  39846 
  39847 #if defined(BCM_88680_A0)
  39848     { /* SOC_REG_INT_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r */
  39849         soc_block_list[51],
  39850         soc_genreg,
  39851         1,
  39852         0,
  39853         0x9a,
  39854         0,
  39855         0,
  39856         1,
  39857         soc_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
  39858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39859         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39860         -1,
  39861         -1,
  39862     },
  39863 #endif /* chips */
  39864 
  39865 #if defined(BCM_88690_A0)
  39866     { /* SOC_REG_INT_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r */
  39867         soc_block_list[51],
  39868         soc_genreg,
  39869         1,
  39870         0,
  39871         0x9a,
  39872         SOC_REG_FLAG_64_BITS,
  39873         0,
  39874         49,
  39875         soc_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
  39876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39877         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  39878         -1,
  39879         -1,
  39880     },
  39881 #endif /* chips */
  39882 
  39883 #if defined(BCM_88690_B0)
  39884     { /* SOC_REG_INT_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r */
  39885         soc_block_list[51],
  39886         soc_genreg,
  39887         1,
  39888         0,
  39889         0x9a,
  39890         SOC_REG_FLAG_ABOVE_64_BITS,
  39891         0,
  39892         177,
  39893         soc_OCB_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
  39894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39895         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39896         -1,
  39897         -1,
  39898     },
  39899 #endif /* chips */
  39900 
  39901 #if defined(BCM_88675_A0)
  39902     { /* SOC_REG_INT_OCB_ECC_ERR_2B_INITIATEr */
  39903         soc_block_list[51],
  39904         soc_genreg,
  39905         1,
  39906         0,
  39907         0xa6,
  39908         0,
  39909         0,
  39910         1,
  39911         soc_OCB_ECC_ERR_2B_INITIATEr_fields,
  39912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39913         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39914         -1,
  39915         -1,
  39916     },
  39917 #endif /* chips */
  39918 
  39919 #if defined(BCM_88202_A0)
  39920     { /* SOC_REG_INT_OCB_ECC_ERR_2B_INITIATE_1r */
  39921         soc_block_list[51],
  39922         soc_genreg,
  39923         1,
  39924         0,
  39925         0xa4,
  39926         0,
  39927         0,
  39928         2,
  39929         soc_OCB_ECC_ERR_2B_INITIATE_1r_fields,
  39930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39931         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  39932         -1,
  39933         -1,
  39934     },
  39935 #endif /* chips */
  39936 
  39937 #if defined(BCM_88375_A0)
  39938     { /* SOC_REG_INT_OCB_ECC_ERR_2B_INITIATE_BCM88375_A0r */
  39939         soc_block_list[51],
  39940         soc_genreg,
  39941         1,
  39942         0,
  39943         0xa6,
  39944         0,
  39945         0,
  39946         1,
  39947         soc_OCB_ECC_ERR_2B_INITIATE_BCM88375_A0r_fields,
  39948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39949         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39950         -1,
  39951         -1,
  39952     },
  39953 #endif /* chips */
  39954 
  39955 #if defined(BCM_88375_B0)
  39956     { /* SOC_REG_INT_OCB_ECC_ERR_2B_INITIATE_BCM88375_B0r */
  39957         soc_block_list[51],
  39958         soc_genreg,
  39959         1,
  39960         0,
  39961         0xa6,
  39962         0,
  39963         0,
  39964         1,
  39965         soc_OCB_ECC_ERR_2B_INITIATE_BCM88375_B0r_fields,
  39966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39967         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39968         -1,
  39969         -1,
  39970     },
  39971 #endif /* chips */
  39972 
  39973 #if defined(BCM_88675_B0)
  39974     { /* SOC_REG_INT_OCB_ECC_ERR_2B_INITIATE_BCM88675_B0r */
  39975         soc_block_list[51],
  39976         soc_genreg,
  39977         1,
  39978         0,
  39979         0xa6,
  39980         0,
  39981         0,
  39982         1,
  39983         soc_OCB_ECC_ERR_2B_INITIATE_BCM88675_B0r_fields,
  39984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39985         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39986         -1,
  39987         -1,
  39988     },
  39989 #endif /* chips */
  39990 
  39991 #if defined(BCM_88680_A0)
  39992     { /* SOC_REG_INT_OCB_ECC_ERR_2B_INITIATE_BCM88680_A0r */
  39993         soc_block_list[51],
  39994         soc_genreg,
  39995         1,
  39996         0,
  39997         0xa6,
  39998         0,
  39999         0,
  40000         1,
  40001         soc_OCB_ECC_ERR_2B_INITIATE_BCM88680_A0r_fields,
  40002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40003         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40004         -1,
  40005         -1,
  40006     },
  40007 #endif /* chips */
  40008 
  40009 #if defined(BCM_88202_A0)
  40010     { /* SOC_REG_INT_OCB_ECC_ERR_2B_MONITOR_MEM_MASKr */
  40011         soc_block_list[51],
  40012         soc_genreg,
  40013         1,
  40014         0,
  40015         0x9a,
  40016         0,
  40017         0,
  40018         2,
  40019         soc_OCB_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  40020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40021         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  40022         -1,
  40023         -1,
  40024     },
  40025 #endif /* chips */
  40026 
  40027 #if defined(BCM_88375_A0)
  40028     { /* SOC_REG_INT_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r */
  40029         soc_block_list[51],
  40030         soc_genreg,
  40031         1,
  40032         0,
  40033         0x9c,
  40034         0,
  40035         0,
  40036         1,
  40037         soc_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
  40038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40039         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40040         -1,
  40041         -1,
  40042     },
  40043 #endif /* chips */
  40044 
  40045 #if defined(BCM_88375_B0)
  40046     { /* SOC_REG_INT_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r */
  40047         soc_block_list[51],
  40048         soc_genreg,
  40049         1,
  40050         0,
  40051         0x9c,
  40052         0,
  40053         0,
  40054         1,
  40055         soc_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
  40056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40057         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40058         -1,
  40059         -1,
  40060     },
  40061 #endif /* chips */
  40062 
  40063 #if defined(BCM_88675_A0)
  40064     { /* SOC_REG_INT_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_A0r */
  40065         soc_block_list[51],
  40066         soc_genreg,
  40067         1,
  40068         0,
  40069         0x9c,
  40070         0,
  40071         0,
  40072         1,
  40073         soc_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_A0r_fields,
  40074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40075         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40076         -1,
  40077         -1,
  40078     },
  40079 #endif /* chips */
  40080 
  40081 #if defined(BCM_88675_B0)
  40082     { /* SOC_REG_INT_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r */
  40083         soc_block_list[51],
  40084         soc_genreg,
  40085         1,
  40086         0,
  40087         0x9c,
  40088         0,
  40089         0,
  40090         1,
  40091         soc_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
  40092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40093         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40094         -1,
  40095         -1,
  40096     },
  40097 #endif /* chips */
  40098 
  40099 #if defined(BCM_88680_A0)
  40100     { /* SOC_REG_INT_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r */
  40101         soc_block_list[51],
  40102         soc_genreg,
  40103         1,
  40104         0,
  40105         0x9c,
  40106         0,
  40107         0,
  40108         1,
  40109         soc_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
  40110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40111         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40112         -1,
  40113         -1,
  40114     },
  40115 #endif /* chips */
  40116 
  40117 #if defined(BCM_88690_A0)
  40118     { /* SOC_REG_INT_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r */
  40119         soc_block_list[51],
  40120         soc_genreg,
  40121         1,
  40122         0,
  40123         0x9c,
  40124         SOC_REG_FLAG_64_BITS,
  40125         0,
  40126         49,
  40127         soc_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
  40128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40129         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  40130         -1,
  40131         -1,
  40132     },
  40133 #endif /* chips */
  40134 
  40135 #if defined(BCM_88690_B0)
  40136     { /* SOC_REG_INT_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r */
  40137         soc_block_list[51],
  40138         soc_genreg,
  40139         1,
  40140         0,
  40141         0x9c,
  40142         SOC_REG_FLAG_ABOVE_64_BITS,
  40143         0,
  40144         177,
  40145         soc_OCB_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
  40146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40148         -1,
  40149         -1,
  40150     },
  40151 #endif /* chips */
  40152 
  40153 #if defined(BCM_88202_A0)
  40154     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTERr */
  40155         soc_block_list[51],
  40156         soc_genreg,
  40157         1,
  40158         0,
  40159         0x7,
  40160         SOC_REG_FLAG_INTERRUPT,
  40161         0,
  40162         2,
  40163         soc_OCB_ECC_INTERRUPT_REGISTERr_fields,
  40164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40165         SOC_RESET_MASK_DEC(0x00000006, 0x00000000)
  40166         -1,
  40167         -1,
  40168     },
  40169 #endif /* chips */
  40170 
  40171 #if defined(BCM_88375_A0)
  40172     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_BCM88375_A0r */
  40173         soc_block_list[51],
  40174         soc_genreg,
  40175         1,
  40176         0,
  40177         0x7,
  40178         SOC_REG_FLAG_INTERRUPT,
  40179         0,
  40180         3,
  40181         soc_OCB_ECC_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  40182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40183         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40184         -1,
  40185         -1,
  40186     },
  40187 #endif /* chips */
  40188 
  40189 #if defined(BCM_88375_B0)
  40190     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_BCM88375_B0r */
  40191         soc_block_list[51],
  40192         soc_genreg,
  40193         1,
  40194         0,
  40195         0x7,
  40196         SOC_REG_FLAG_INTERRUPT,
  40197         0,
  40198         3,
  40199         soc_OCB_ECC_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  40200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40201         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40202         -1,
  40203         -1,
  40204     },
  40205 #endif /* chips */
  40206 
  40207 #if defined(BCM_88675_A0)
  40208     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_BCM88675_A0r */
  40209         soc_block_list[51],
  40210         soc_genreg,
  40211         1,
  40212         0,
  40213         0x7,
  40214         SOC_REG_FLAG_INTERRUPT,
  40215         0,
  40216         3,
  40217         soc_OCB_ECC_INTERRUPT_REGISTER_BCM88675_A0r_fields,
  40218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40219         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40220         -1,
  40221         -1,
  40222     },
  40223 #endif /* chips */
  40224 
  40225 #if defined(BCM_88675_B0)
  40226     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_BCM88675_B0r */
  40227         soc_block_list[51],
  40228         soc_genreg,
  40229         1,
  40230         0,
  40231         0x7,
  40232         SOC_REG_FLAG_INTERRUPT,
  40233         0,
  40234         3,
  40235         soc_OCB_ECC_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  40236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40237         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40238         -1,
  40239         -1,
  40240     },
  40241 #endif /* chips */
  40242 
  40243 #if defined(BCM_88680_A0)
  40244     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_BCM88680_A0r */
  40245         soc_block_list[51],
  40246         soc_genreg,
  40247         1,
  40248         0,
  40249         0x7,
  40250         SOC_REG_FLAG_INTERRUPT,
  40251         0,
  40252         3,
  40253         soc_OCB_ECC_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  40254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40255         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40256         -1,
  40257         -1,
  40258     },
  40259 #endif /* chips */
  40260 
  40261 #if defined(BCM_88690_A0)
  40262     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_BCM88690_A0r */
  40263         soc_block_list[51],
  40264         soc_genreg,
  40265         1,
  40266         0,
  40267         0x7,
  40268         SOC_REG_FLAG_INTERRUPT |
  40269                           SOC_REG_FLAG_SIGNAL,
  40270         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40271         3,
  40272         soc_OCB_ECC_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  40273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40274         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40275         -1,
  40276         -1,
  40277     },
  40278 #endif /* chips */
  40279 
  40280 #if defined(BCM_88690_B0)
  40281     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
  40282         soc_block_list[51],
  40283         soc_genreg,
  40284         1,
  40285         0,
  40286         0x7,
  40287         SOC_REG_FLAG_INTERRUPT |
  40288                           SOC_REG_FLAG_SIGNAL,
  40289         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40290         3,
  40291         soc_OCB_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  40292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40293         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40294         -1,
  40295         -1,
  40296     },
  40297 #endif /* chips */
  40298 
  40299 #if defined(BCM_88202_A0)
  40300     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_MASKr */
  40301         soc_block_list[51],
  40302         soc_genreg,
  40303         1,
  40304         0,
  40305         0x17,
  40306         SOC_REG_FLAG_INTERRUPT,
  40307         0,
  40308         2,
  40309         soc_OCB_ECC_INTERRUPT_REGISTER_MASKr_fields,
  40310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40311         SOC_RESET_MASK_DEC(0x00000006, 0x00000000)
  40312         -1,
  40313         -1,
  40314     },
  40315 #endif /* chips */
  40316 
  40317 #if defined(BCM_88375_A0)
  40318     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r */
  40319         soc_block_list[51],
  40320         soc_genreg,
  40321         1,
  40322         0,
  40323         0x17,
  40324         0,
  40325         0,
  40326         3,
  40327         soc_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r_fields,
  40328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40329         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40330         -1,
  40331         -1,
  40332     },
  40333 #endif /* chips */
  40334 
  40335 #if defined(BCM_88375_B0)
  40336     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r */
  40337         soc_block_list[51],
  40338         soc_genreg,
  40339         1,
  40340         0,
  40341         0x17,
  40342         0,
  40343         0,
  40344         3,
  40345         soc_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r_fields,
  40346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40347         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40348         -1,
  40349         -1,
  40350     },
  40351 #endif /* chips */
  40352 
  40353 #if defined(BCM_88675_A0)
  40354     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88675_A0r */
  40355         soc_block_list[51],
  40356         soc_genreg,
  40357         1,
  40358         0,
  40359         0x17,
  40360         0,
  40361         0,
  40362         3,
  40363         soc_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88675_A0r_fields,
  40364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40365         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40366         -1,
  40367         -1,
  40368     },
  40369 #endif /* chips */
  40370 
  40371 #if defined(BCM_88675_B0)
  40372     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r */
  40373         soc_block_list[51],
  40374         soc_genreg,
  40375         1,
  40376         0,
  40377         0x17,
  40378         0,
  40379         0,
  40380         3,
  40381         soc_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r_fields,
  40382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40383         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40384         -1,
  40385         -1,
  40386     },
  40387 #endif /* chips */
  40388 
  40389 #if defined(BCM_88680_A0)
  40390     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r */
  40391         soc_block_list[51],
  40392         soc_genreg,
  40393         1,
  40394         0,
  40395         0x17,
  40396         0,
  40397         0,
  40398         3,
  40399         soc_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r_fields,
  40400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40401         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40402         -1,
  40403         -1,
  40404     },
  40405 #endif /* chips */
  40406 
  40407 #if defined(BCM_88690_A0)
  40408     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r */
  40409         soc_block_list[51],
  40410         soc_genreg,
  40411         1,
  40412         0,
  40413         0x17,
  40414         0,
  40415         0,
  40416         3,
  40417         soc_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r_fields,
  40418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40419         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40420         -1,
  40421         -1,
  40422     },
  40423 #endif /* chips */
  40424 
  40425 #if defined(BCM_88690_B0)
  40426     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
  40427         soc_block_list[51],
  40428         soc_genreg,
  40429         1,
  40430         0,
  40431         0x17,
  40432         0,
  40433         0,
  40434         3,
  40435         soc_OCB_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
  40436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40437         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40438         -1,
  40439         -1,
  40440     },
  40441 #endif /* chips */
  40442 
  40443 #if defined(BCM_88202_A0)
  40444     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_TESTr */
  40445         soc_block_list[51],
  40446         soc_genreg,
  40447         1,
  40448         0,
  40449         0x1f,
  40450         SOC_REG_FLAG_INTERRUPT |
  40451                           SOC_REG_FLAG_SIGNAL,
  40452         0,
  40453         1,
  40454         soc_OCB_ECC_INTERRUPT_REGISTER_TESTr_fields,
  40455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40456         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40457         -1,
  40458         -1,
  40459     },
  40460 #endif /* chips */
  40461 
  40462 #if defined(BCM_88375_A0)
  40463     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  40464         soc_block_list[51],
  40465         soc_genreg,
  40466         1,
  40467         0,
  40468         0x1f,
  40469         0,
  40470         0,
  40471         1,
  40472         soc_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  40473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40474         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40475         -1,
  40476         -1,
  40477     },
  40478 #endif /* chips */
  40479 
  40480 #if defined(BCM_88375_B0)
  40481     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  40482         soc_block_list[51],
  40483         soc_genreg,
  40484         1,
  40485         0,
  40486         0x1f,
  40487         0,
  40488         0,
  40489         1,
  40490         soc_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  40491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40492         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40493         -1,
  40494         -1,
  40495     },
  40496 #endif /* chips */
  40497 
  40498 #if defined(BCM_88675_A0)
  40499     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88675_A0r */
  40500         soc_block_list[51],
  40501         soc_genreg,
  40502         1,
  40503         0,
  40504         0x1f,
  40505         0,
  40506         0,
  40507         1,
  40508         soc_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88675_A0r_fields,
  40509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40510         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40511         -1,
  40512         -1,
  40513     },
  40514 #endif /* chips */
  40515 
  40516 #if defined(BCM_88675_B0)
  40517     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  40518         soc_block_list[51],
  40519         soc_genreg,
  40520         1,
  40521         0,
  40522         0x1f,
  40523         0,
  40524         0,
  40525         1,
  40526         soc_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  40527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40528         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40529         -1,
  40530         -1,
  40531     },
  40532 #endif /* chips */
  40533 
  40534 #if defined(BCM_88680_A0)
  40535     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  40536         soc_block_list[51],
  40537         soc_genreg,
  40538         1,
  40539         0,
  40540         0x1f,
  40541         0,
  40542         0,
  40543         1,
  40544         soc_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  40545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40546         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40547         -1,
  40548         -1,
  40549     },
  40550 #endif /* chips */
  40551 
  40552 #if defined(BCM_88690_A0)
  40553     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  40554         soc_block_list[51],
  40555         soc_genreg,
  40556         1,
  40557         0,
  40558         0x1f,
  40559         0,
  40560         0,
  40561         1,
  40562         soc_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  40563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40564         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40565         -1,
  40566         -1,
  40567     },
  40568 #endif /* chips */
  40569 
  40570 #if defined(BCM_88690_B0)
  40571     { /* SOC_REG_INT_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  40572         soc_block_list[51],
  40573         soc_genreg,
  40574         1,
  40575         0,
  40576         0x1f,
  40577         0,
  40578         0,
  40579         1,
  40580         soc_OCB_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  40581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40582         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40583         -1,
  40584         -1,
  40585     },
  40586 #endif /* chips */
  40587 
  40588 #if defined(BCM_88675_A0)
  40589     { /* SOC_REG_INT_OCB_ENABLE_DYNAMIC_MEMORY_ACCESSr */
  40590         soc_block_list[51],
  40591         soc_genreg,
  40592         1,
  40593         0,
  40594         0x84,
  40595         0,
  40596         0,
  40597         1,
  40598         soc_OCB_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
  40599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40600         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40601         -1,
  40602         -1,
  40603     },
  40604 #endif /* chips */
  40605 
  40606 #if defined(BCM_88375_A0)
  40607     { /* SOC_REG_INT_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_A0r */
  40608         soc_block_list[51],
  40609         soc_genreg,
  40610         1,
  40611         0,
  40612         0x84,
  40613         0,
  40614         0,
  40615         1,
  40616         soc_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_A0r_fields,
  40617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40618         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40619         -1,
  40620         -1,
  40621     },
  40622 #endif /* chips */
  40623 
  40624 #if defined(BCM_88375_B0)
  40625     { /* SOC_REG_INT_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_B0r */
  40626         soc_block_list[51],
  40627         soc_genreg,
  40628         1,
  40629         0,
  40630         0x84,
  40631         0,
  40632         0,
  40633         1,
  40634         soc_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_B0r_fields,
  40635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40636         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40637         -1,
  40638         -1,
  40639     },
  40640 #endif /* chips */
  40641 
  40642 #if defined(BCM_88675_B0)
  40643     { /* SOC_REG_INT_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_B0r */
  40644         soc_block_list[51],
  40645         soc_genreg,
  40646         1,
  40647         0,
  40648         0x84,
  40649         0,
  40650         0,
  40651         1,
  40652         soc_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_B0r_fields,
  40653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40654         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40655         -1,
  40656         -1,
  40657     },
  40658 #endif /* chips */
  40659 
  40660 #if defined(BCM_88680_A0)
  40661     { /* SOC_REG_INT_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r */
  40662         soc_block_list[51],
  40663         soc_genreg,
  40664         1,
  40665         0,
  40666         0x84,
  40667         0,
  40668         0,
  40669         1,
  40670         soc_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r_fields,
  40671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40672         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40673         -1,
  40674         -1,
  40675     },
  40676 #endif /* chips */
  40677 
  40678 #if defined(BCM_88690_A0)
  40679     { /* SOC_REG_INT_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r */
  40680         soc_block_list[51],
  40681         soc_genreg,
  40682         1,
  40683         0,
  40684         0x84,
  40685         0,
  40686         0,
  40687         1,
  40688         soc_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r_fields,
  40689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40690         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40691         -1,
  40692         -1,
  40693     },
  40694 #endif /* chips */
  40695 
  40696 #if defined(BCM_88690_B0)
  40697     { /* SOC_REG_INT_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r */
  40698         soc_block_list[51],
  40699         soc_genreg,
  40700         1,
  40701         0,
  40702         0x84,
  40703         0,
  40704         0,
  40705         1,
  40706         soc_OCB_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r_fields,
  40707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40708         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40709         -1,
  40710         -1,
  40711     },
  40712 #endif /* chips */
  40713 
  40714 #if defined(BCM_88202_A0)
  40715     { /* SOC_REG_INT_OCB_ERROR_INITIATION_DATAr */
  40716         soc_block_list[51],
  40717         soc_genreg,
  40718         1,
  40719         0,
  40720         0xa3,
  40721         0,
  40722         0,
  40723         1,
  40724         soc_OCB_ERROR_INITIATION_DATAr_fields,
  40725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40726         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40727         -1,
  40728         -1,
  40729     },
  40730 #endif /* chips */
  40731 
  40732 #if defined(BCM_88375_A0)
  40733     { /* SOC_REG_INT_OCB_ERROR_INITIATION_DATA_BCM88375_A0r */
  40734         soc_block_list[51],
  40735         soc_genreg,
  40736         1,
  40737         0,
  40738         0xa3,
  40739         0,
  40740         0,
  40741         1,
  40742         soc_OCB_ERROR_INITIATION_DATA_BCM88375_A0r_fields,
  40743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40744         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40745         -1,
  40746         -1,
  40747     },
  40748 #endif /* chips */
  40749 
  40750 #if defined(BCM_88375_B0)
  40751     { /* SOC_REG_INT_OCB_ERROR_INITIATION_DATA_BCM88375_B0r */
  40752         soc_block_list[51],
  40753         soc_genreg,
  40754         1,
  40755         0,
  40756         0xa3,
  40757         0,
  40758         0,
  40759         1,
  40760         soc_OCB_ERROR_INITIATION_DATA_BCM88375_B0r_fields,
  40761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40762         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40763         -1,
  40764         -1,
  40765     },
  40766 #endif /* chips */
  40767 
  40768 #if defined(BCM_88675_A0)
  40769     { /* SOC_REG_INT_OCB_ERROR_INITIATION_DATA_BCM88675_A0r */
  40770         soc_block_list[51],
  40771         soc_genreg,
  40772         1,
  40773         0,
  40774         0xa3,
  40775         0,
  40776         0,
  40777         1,
  40778         soc_OCB_ERROR_INITIATION_DATA_BCM88675_A0r_fields,
  40779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40780         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40781         -1,
  40782         -1,
  40783     },
  40784 #endif /* chips */
  40785 
  40786 #if defined(BCM_88675_B0)
  40787     { /* SOC_REG_INT_OCB_ERROR_INITIATION_DATA_BCM88675_B0r */
  40788         soc_block_list[51],
  40789         soc_genreg,
  40790         1,
  40791         0,
  40792         0xa3,
  40793         0,
  40794         0,
  40795         1,
  40796         soc_OCB_ERROR_INITIATION_DATA_BCM88675_B0r_fields,
  40797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40798         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40799         -1,
  40800         -1,
  40801     },
  40802 #endif /* chips */
  40803 
  40804 #if defined(BCM_88680_A0)
  40805     { /* SOC_REG_INT_OCB_ERROR_INITIATION_DATA_BCM88680_A0r */
  40806         soc_block_list[51],
  40807         soc_genreg,
  40808         1,
  40809         0,
  40810         0xa3,
  40811         0,
  40812         0,
  40813         1,
  40814         soc_OCB_ERROR_INITIATION_DATA_BCM88680_A0r_fields,
  40815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40816         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40817         -1,
  40818         -1,
  40819     },
  40820 #endif /* chips */
  40821 
  40822 #if defined(BCM_88690_A0)
  40823     { /* SOC_REG_INT_OCB_ERROR_INITIATION_DATA_BCM88690_A0r */
  40824         soc_block_list[51],
  40825         soc_genreg,
  40826         1,
  40827         0,
  40828         0xa3,
  40829         0,
  40830         0,
  40831         1,
  40832         soc_OCB_ERROR_INITIATION_DATA_BCM88690_A0r_fields,
  40833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40834         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  40835         -1,
  40836         -1,
  40837     },
  40838 #endif /* chips */
  40839 
  40840 #if defined(BCM_88690_A0)
  40841     { /* SOC_REG_INT_OCB_FBC_BANK_CFGr */
  40842         soc_block_list[51],
  40843         soc_genreg,
  40844         16,
  40845         0,
  40846         0x106,
  40847         SOC_REG_FLAG_ARRAY |
  40848                           SOC_REG_FLAG_REG_ARRAY,
  40849         0,
  40850         2,
  40851         soc_OCB_FBC_BANK_CFGr_fields,
  40852         SOC_RESET_VAL_DEC(0x00fff000, 0x00000000)
  40853         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  40854         -1,
  40855         -1,
  40856     },
  40857 #endif /* chips */
  40858 
  40859 #if defined(BCM_88690_B0)
  40860     { /* SOC_REG_INT_OCB_FBC_BANK_CFG_BCM88690_B0r */
  40861         soc_block_list[51],
  40862         soc_genreg,
  40863         16,
  40864         0,
  40865         0x108,
  40866         SOC_REG_FLAG_ARRAY |
  40867                           SOC_REG_FLAG_REG_ARRAY,
  40868         0,
  40869         2,
  40870         soc_OCB_FBC_BANK_CFG_BCM88690_B0r_fields,
  40871         SOC_RESET_VAL_DEC(0x00fff000, 0x00000000)
  40872         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  40873         -1,
  40874         -1,
  40875     },
  40876 #endif /* chips */
  40877 
  40878 #if defined(BCM_88690_A0)
  40879     { /* SOC_REG_INT_OCB_FBC_BANK_INTERRUPT_REGISTERr */
  40880         soc_block_list[51],
  40881         soc_genreg,
  40882         1,
  40883         0,
  40884         0x100,
  40885         SOC_REG_FLAG_INTERRUPT |
  40886                           SOC_REG_FLAG_SIGNAL,
  40887         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40888         16,
  40889         soc_OCB_FBC_BANK_INTERRUPT_REGISTERr_fields,
  40890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40891         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  40892         -1,
  40893         -1,
  40894     },
  40895 #endif /* chips */
  40896 
  40897 #if defined(BCM_88690_B0)
  40898     { /* SOC_REG_INT_OCB_FBC_BANK_INTERRUPT_REGISTER_BCM88690_B0r */
  40899         soc_block_list[51],
  40900         soc_genreg,
  40901         1,
  40902         0,
  40903         0x100,
  40904         SOC_REG_FLAG_INTERRUPT |
  40905                           SOC_REG_FLAG_SIGNAL,
  40906         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40907         16,
  40908         soc_OCB_FBC_BANK_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  40909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40910         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  40911         -1,
  40912         -1,
  40913     },
  40914 #endif /* chips */
  40915 
  40916 #if defined(BCM_88690_A0)
  40917     { /* SOC_REG_INT_OCB_FBC_BANK_INTERRUPT_REGISTER_MASKr */
  40918         soc_block_list[51],
  40919         soc_genreg,
  40920         1,
  40921         0,
  40922         0x101,
  40923         0,
  40924         0,
  40925         16,
  40926         soc_OCB_FBC_BANK_INTERRUPT_REGISTER_MASKr_fields,
  40927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40928         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  40929         -1,
  40930         -1,
  40931     },
  40932 #endif /* chips */
  40933 
  40934 #if defined(BCM_88690_B0)
  40935     { /* SOC_REG_INT_OCB_FBC_BANK_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
  40936         soc_block_list[51],
  40937         soc_genreg,
  40938         1,
  40939         0,
  40940         0x103,
  40941         0,
  40942         0,
  40943         16,
  40944         soc_OCB_FBC_BANK_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
  40945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40946         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  40947         -1,
  40948         -1,
  40949     },
  40950 #endif /* chips */
  40951 
  40952 #if defined(BCM_88690_A0)
  40953     { /* SOC_REG_INT_OCB_FBC_BANK_INTERRUPT_REGISTER_TESTr */
  40954         soc_block_list[51],
  40955         soc_genreg,
  40956         1,
  40957         0,
  40958         0x102,
  40959         0,
  40960         0,
  40961         1,
  40962         soc_OCB_FBC_BANK_INTERRUPT_REGISTER_TESTr_fields,
  40963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40964         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  40965         -1,
  40966         -1,
  40967     },
  40968 #endif /* chips */
  40969 
  40970 #if defined(BCM_88690_B0)
  40971     { /* SOC_REG_INT_OCB_FBC_BANK_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  40972         soc_block_list[51],
  40973         soc_genreg,
  40974         1,
  40975         0,
  40976         0x104,
  40977         0,
  40978         0,
  40979         1,
  40980         soc_OCB_FBC_BANK_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  40981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40982         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  40983         -1,
  40984         -1,
  40985     },
  40986 #endif /* chips */
  40987 
  40988 #if defined(BCM_88690_A0)
  40989     { /* SOC_REG_INT_OCB_FREE_BUFFERS_BANK_STATUS_REGISTERr */
  40990         soc_block_list[51],
  40991         soc_genreg,
  40992         16,
  40993         0,
  40994         0x120,
  40995         SOC_REG_FLAG_64_BITS |
  40996                           SOC_REG_FLAG_ARRAY |
  40997                           SOC_REG_FLAG_RO |
  40998                           SOC_REG_FLAG_REG_ARRAY,
  40999         SOC_REG_FLAG_INIT_ON_READ,
  41000         3,
  41001         soc_OCB_FREE_BUFFERS_BANK_STATUS_REGISTERr_fields,
  41002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41003         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  41004         -1,
  41005         -1,
  41006     },
  41007 #endif /* chips */
  41008 
  41009 #if defined(BCM_88690_B0)
  41010     { /* SOC_REG_INT_OCB_FREE_BUFFERS_BANK_STATUS_REGISTER_BCM88690_B0r */
  41011         soc_block_list[51],
  41012         soc_genreg,
  41013         16,
  41014         0,
  41015         0x122,
  41016         SOC_REG_FLAG_64_BITS |
  41017                           SOC_REG_FLAG_ARRAY |
  41018                           SOC_REG_FLAG_RO |
  41019                           SOC_REG_FLAG_REG_ARRAY,
  41020         SOC_REG_FLAG_INIT_ON_READ,
  41021         3,
  41022         soc_OCB_FREE_BUFFERS_BANK_STATUS_REGISTER_BCM88690_B0r_fields,
  41023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41024         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  41025         -1,
  41026         -1,
  41027     },
  41028 #endif /* chips */
  41029 
  41030 #if defined(BCM_88690_A0)
  41031     { /* SOC_REG_INT_OCB_FREE_BUFFERS_STATUS_REGISTERr */
  41032         soc_block_list[51],
  41033         soc_genreg,
  41034         1,
  41035         0,
  41036         0x11e,
  41037         SOC_REG_FLAG_64_BITS |
  41038                           SOC_REG_FLAG_RO,
  41039         SOC_REG_FLAG_INIT_ON_READ,
  41040         3,
  41041         soc_OCB_FREE_BUFFERS_STATUS_REGISTERr_fields,
  41042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41043         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  41044         -1,
  41045         -1,
  41046     },
  41047 #endif /* chips */
  41048 
  41049 #if defined(BCM_88690_B0)
  41050     { /* SOC_REG_INT_OCB_FREE_BUFFERS_STATUS_REGISTER_BCM88690_B0r */
  41051         soc_block_list[51],
  41052         soc_genreg,
  41053         1,
  41054         0,
  41055         0x120,
  41056         SOC_REG_FLAG_64_BITS |
  41057                           SOC_REG_FLAG_RO,
  41058         SOC_REG_FLAG_INIT_ON_READ,
  41059         3,
  41060         soc_OCB_FREE_BUFFERS_STATUS_REGISTER_BCM88690_B0r_fields,
  41061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41062         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  41063         -1,
  41064         -1,
  41065     },
  41066 #endif /* chips */
  41067 
  41068 #if defined(BCM_88690_A0)
  41069     { /* SOC_REG_INT_OCB_FREE_ERRORr */
  41070         soc_block_list[51],
  41071         soc_genreg,
  41072         1,
  41073         0,
  41074         0x142,
  41075         SOC_REG_FLAG_RO,
  41076         SOC_REG_FLAG_INIT_ON_READ,
  41077         2,
  41078         soc_OCB_FREE_ERRORr_fields,
  41079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41080         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  41081         -1,
  41082         -1,
  41083     },
  41084 #endif /* chips */
  41085 
  41086 #if defined(BCM_88690_B0)
  41087     { /* SOC_REG_INT_OCB_FREE_ERROR_BCM88690_B0r */
  41088         soc_block_list[51],
  41089         soc_genreg,
  41090         1,
  41091         0,
  41092         0x144,
  41093         SOC_REG_FLAG_RO,
  41094         SOC_REG_FLAG_INIT_ON_READ,
  41095         2,
  41096         soc_OCB_FREE_ERROR_BCM88690_B0r_fields,
  41097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41098         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  41099         -1,
  41100         -1,
  41101     },
  41102 #endif /* chips */
  41103 
  41104 #if defined(BCM_88675_A0)
  41105     { /* SOC_REG_INT_OCB_GENERAL_CONFIGr */
  41106         soc_block_list[51],
  41107         soc_genreg,
  41108         1,
  41109         0,
  41110         0x200,
  41111         0,
  41112         0,
  41113         2,
  41114         soc_OCB_GENERAL_CONFIGr_fields,
  41115         SOC_RESET_VAL_DEC(0x0000010a, 0x00000000)
  41116         SOC_RESET_MASK_DEC(0x0000017f, 0x00000000)
  41117         -1,
  41118         -1,
  41119     },
  41120 #endif /* chips */
  41121 
  41122 #if defined(BCM_88375_A0)
  41123     { /* SOC_REG_INT_OCB_GENERAL_CONFIG_BCM88375_A0r */
  41124         soc_block_list[51],
  41125         soc_genreg,
  41126         1,
  41127         0,
  41128         0x200,
  41129         0,
  41130         0,
  41131         2,
  41132         soc_OCB_GENERAL_CONFIG_BCM88375_A0r_fields,
  41133         SOC_RESET_VAL_DEC(0x0000010a, 0x00000000)
  41134         SOC_RESET_MASK_DEC(0x0000017f, 0x00000000)
  41135         -1,
  41136         -1,
  41137     },
  41138 #endif /* chips */
  41139 
  41140 #if defined(BCM_88375_B0)
  41141     { /* SOC_REG_INT_OCB_GENERAL_CONFIG_BCM88375_B0r */
  41142         soc_block_list[51],
  41143         soc_genreg,
  41144         1,
  41145         0,
  41146         0x200,
  41147         0,
  41148         0,
  41149         2,
  41150         soc_OCB_GENERAL_CONFIG_BCM88375_B0r_fields,
  41151         SOC_RESET_VAL_DEC(0x0000010a, 0x00000000)
  41152         SOC_RESET_MASK_DEC(0x0000017f, 0x00000000)
  41153         -1,
  41154         -1,
  41155     },
  41156 #endif /* chips */
  41157 
  41158 #if defined(BCM_88675_B0)
  41159     { /* SOC_REG_INT_OCB_GENERAL_CONFIG_BCM88675_B0r */
  41160         soc_block_list[51],
  41161         soc_genreg,
  41162         1,
  41163         0,
  41164         0x200,
  41165         0,
  41166         0,
  41167         2,
  41168         soc_OCB_GENERAL_CONFIG_BCM88675_B0r_fields,
  41169         SOC_RESET_VAL_DEC(0x0000010a, 0x00000000)
  41170         SOC_RESET_MASK_DEC(0x0000017f, 0x00000000)
  41171         -1,
  41172         -1,
  41173     },
  41174 #endif /* chips */
  41175 
  41176 #if defined(BCM_88680_A0)
  41177     { /* SOC_REG_INT_OCB_GENERAL_CONFIG_BCM88680_A0r */
  41178         soc_block_list[51],
  41179         soc_genreg,
  41180         1,
  41181         0,
  41182         0x200,
  41183         0,
  41184         0,
  41185         2,
  41186         soc_OCB_GENERAL_CONFIG_BCM88680_A0r_fields,
  41187         SOC_RESET_VAL_DEC(0x0000010a, 0x00000000)
  41188         SOC_RESET_MASK_DEC(0x0000017f, 0x00000000)
  41189         -1,
  41190         -1,
  41191     },
  41192 #endif /* chips */
  41193 
  41194 #if defined(BCM_88660_A0)
  41195     { /* SOC_REG_INT_OCB_GLOBALFr */
  41196         soc_block_list[51],
  41197         soc_genreg,
  41198         1,
  41199         0,
  41200         0xcf,
  41201         0,
  41202         0,
  41203         1,
  41204         soc_OCB_GLOBALFr_fields,
  41205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41206         SOC_RESET_MASK_DEC(0x00004000, 0x00000000)
  41207         -1,
  41208         -1,
  41209     },
  41210 #endif /* chips */
  41211 
  41212 #if defined(BCM_88202_A0)
  41213     { /* SOC_REG_INT_OCB_GLOBALF_BCM88202_A0r */
  41214         soc_block_list[51],
  41215         soc_genreg,
  41216         1,
  41217         0,
  41218         0xcf,
  41219         0,
  41220         0,
  41221         3,
  41222         soc_OCB_GLOBALF_BCM88202_A0r_fields,
  41223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41224         SOC_RESET_MASK_DEC(0x0001c000, 0x00000000)
  41225         -1,
  41226         -1,
  41227     },
  41228 #endif /* chips */
  41229 
  41230 #if defined(BCM_88660_A0)
  41231     { /* SOC_REG_INT_OCB_GLOBAL_1r */
  41232         soc_block_list[51],
  41233         soc_genreg,
  41234         1,
  41235         0,
  41236         0xc1,
  41237         0,
  41238         0,
  41239         1,
  41240         soc_OCB_GLOBAL_1r_fields,
  41241         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  41242         SOC_RESET_MASK_DEC(0x00000040, 0x00000000)
  41243         -1,
  41244         -1,
  41245     },
  41246 #endif /* chips */
  41247 
  41248 #if defined(BCM_88202_A0)
  41249     { /* SOC_REG_INT_OCB_GLOBAL_1_BCM88202_A0r */
  41250         soc_block_list[51],
  41251         soc_genreg,
  41252         1,
  41253         0,
  41254         0xc1,
  41255         0,
  41256         0,
  41257         1,
  41258         soc_OCB_GLOBAL_1_BCM88202_A0r_fields,
  41259         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  41260         SOC_RESET_MASK_DEC(0x00000040, 0x00000000)
  41261         -1,
  41262         -1,
  41263     },
  41264 #endif /* chips */
  41265 
  41266 #if defined(BCM_88675_A0)
  41267     { /* SOC_REG_INT_OCB_GLOBAL_GENERAL_CFG_3r */
  41268         soc_block_list[51],
  41269         soc_genreg,
  41270         1,
  41271         0,
  41272         0xc3,
  41273         0,
  41274         0,
  41275         3,
  41276         soc_OCB_GLOBAL_GENERAL_CFG_3r_fields,
  41277         SOC_RESET_VAL_DEC(0x00000201, 0x00000000)
  41278         SOC_RESET_MASK_DEC(0x00000209, 0x00000000)
  41279         -1,
  41280         -1,
  41281     },
  41282 #endif /* chips */
  41283 
  41284 #if defined(BCM_88375_A0)
  41285     { /* SOC_REG_INT_OCB_GLOBAL_GENERAL_CFG_3_BCM88375_A0r */
  41286         soc_block_list[51],
  41287         soc_genreg,
  41288         1,
  41289         0,
  41290         0xc3,
  41291         0,
  41292         0,
  41293         3,
  41294         soc_OCB_GLOBAL_GENERAL_CFG_3_BCM88375_A0r_fields,
  41295         SOC_RESET_VAL_DEC(0x00000201, 0x00000000)
  41296         SOC_RESET_MASK_DEC(0x00000209, 0x00000000)
  41297         -1,
  41298         -1,
  41299     },
  41300 #endif /* chips */
  41301 
  41302 #if defined(BCM_88375_B0)
  41303     { /* SOC_REG_INT_OCB_GLOBAL_GENERAL_CFG_3_BCM88375_B0r */
  41304         soc_block_list[51],
  41305         soc_genreg,
  41306         1,
  41307         0,
  41308         0xc3,
  41309         0,
  41310         0,
  41311         3,
  41312         soc_OCB_GLOBAL_GENERAL_CFG_3_BCM88375_B0r_fields,
  41313         SOC_RESET_VAL_DEC(0x00000201, 0x00000000)
  41314         SOC_RESET_MASK_DEC(0x00000209, 0x00000000)
  41315         -1,
  41316         -1,
  41317     },
  41318 #endif /* chips */
  41319 
  41320 #if defined(BCM_88675_B0)
  41321     { /* SOC_REG_INT_OCB_GLOBAL_GENERAL_CFG_3_BCM88675_B0r */
  41322         soc_block_list[51],
  41323         soc_genreg,
  41324         1,
  41325         0,
  41326         0xc3,
  41327         0,
  41328         0,
  41329         3,
  41330         soc_OCB_GLOBAL_GENERAL_CFG_3_BCM88675_B0r_fields,
  41331         SOC_RESET_VAL_DEC(0x00000201, 0x00000000)
  41332         SOC_RESET_MASK_DEC(0x00000209, 0x00000000)
  41333         -1,
  41334         -1,
  41335     },
  41336 #endif /* chips */
  41337 
  41338 #if defined(BCM_88680_A0)
  41339     { /* SOC_REG_INT_OCB_GLOBAL_GENERAL_CFG_3_BCM88680_A0r */
  41340         soc_block_list[51],
  41341         soc_genreg,
  41342         1,
  41343         0,
  41344         0xc3,
  41345         0,
  41346         0,
  41347         3,
  41348         soc_OCB_GLOBAL_GENERAL_CFG_3_BCM88680_A0r_fields,
  41349         SOC_RESET_VAL_DEC(0x00000201, 0x00000000)
  41350         SOC_RESET_MASK_DEC(0x00000209, 0x00000000)
  41351         -1,
  41352         -1,
  41353     },
  41354 #endif /* chips */
  41355 
  41356 #if defined(BCM_88675_A0)
  41357     { /* SOC_REG_INT_OCB_GLOBAL_MEM_OPTIONSr */
  41358         soc_block_list[51],
  41359         soc_genreg,
  41360         1,
  41361         0,
  41362         0xc0,
  41363         0,
  41364         0,
  41365         4,
  41366         soc_OCB_GLOBAL_MEM_OPTIONSr_fields,
  41367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41368         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41369         -1,
  41370         -1,
  41371     },
  41372 #endif /* chips */
  41373 
  41374 #if defined(BCM_88375_A0)
  41375     { /* SOC_REG_INT_OCB_GLOBAL_MEM_OPTIONS_BCM88375_A0r */
  41376         soc_block_list[51],
  41377         soc_genreg,
  41378         1,
  41379         0,
  41380         0xc0,
  41381         0,
  41382         0,
  41383         4,
  41384         soc_OCB_GLOBAL_MEM_OPTIONS_BCM88375_A0r_fields,
  41385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41386         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41387         -1,
  41388         -1,
  41389     },
  41390 #endif /* chips */
  41391 
  41392 #if defined(BCM_88375_B0)
  41393     { /* SOC_REG_INT_OCB_GLOBAL_MEM_OPTIONS_BCM88375_B0r */
  41394         soc_block_list[51],
  41395         soc_genreg,
  41396         1,
  41397         0,
  41398         0xc0,
  41399         0,
  41400         0,
  41401         4,
  41402         soc_OCB_GLOBAL_MEM_OPTIONS_BCM88375_B0r_fields,
  41403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41404         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41405         -1,
  41406         -1,
  41407     },
  41408 #endif /* chips */
  41409 
  41410 #if defined(BCM_88675_B0)
  41411     { /* SOC_REG_INT_OCB_GLOBAL_MEM_OPTIONS_BCM88675_B0r */
  41412         soc_block_list[51],
  41413         soc_genreg,
  41414         1,
  41415         0,
  41416         0xc0,
  41417         0,
  41418         0,
  41419         4,
  41420         soc_OCB_GLOBAL_MEM_OPTIONS_BCM88675_B0r_fields,
  41421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41422         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41423         -1,
  41424         -1,
  41425     },
  41426 #endif /* chips */
  41427 
  41428 #if defined(BCM_88680_A0)
  41429     { /* SOC_REG_INT_OCB_GLOBAL_MEM_OPTIONS_BCM88680_A0r */
  41430         soc_block_list[51],
  41431         soc_genreg,
  41432         1,
  41433         0,
  41434         0xc0,
  41435         0,
  41436         0,
  41437         4,
  41438         soc_OCB_GLOBAL_MEM_OPTIONS_BCM88680_A0r_fields,
  41439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41440         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41441         -1,
  41442         -1,
  41443     },
  41444 #endif /* chips */
  41445 
  41446 #if defined(BCM_88675_A0)
  41447     { /* SOC_REG_INT_OCB_GLOBAL_OCB_BANK_RANGEr */
  41448         soc_block_list[51],
  41449         soc_genreg,
  41450         16,
  41451         0,
  41452         0xd2,
  41453         SOC_REG_FLAG_64_BITS |
  41454                           SOC_REG_FLAG_ARRAY |
  41455                           SOC_REG_FLAG_REG_ARRAY,
  41456         0,
  41457         2,
  41458         soc_OCB_GLOBAL_OCB_BANK_RANGEr_fields,
  41459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41460         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  41461         -1,
  41462         -1,
  41463     },
  41464 #endif /* chips */
  41465 
  41466 #if defined(BCM_88375_A0)
  41467     { /* SOC_REG_INT_OCB_GLOBAL_OCB_BANK_RANGE_BCM88375_A0r */
  41468         soc_block_list[51],
  41469         soc_genreg,
  41470         16,
  41471         0,
  41472         0xd2,
  41473         SOC_REG_FLAG_64_BITS |
  41474                           SOC_REG_FLAG_ARRAY |
  41475                           SOC_REG_FLAG_REG_ARRAY,
  41476         0,
  41477         2,
  41478         soc_OCB_GLOBAL_OCB_BANK_RANGE_BCM88375_A0r_fields,
  41479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41480         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  41481         -1,
  41482         -1,
  41483     },
  41484 #endif /* chips */
  41485 
  41486 #if defined(BCM_88375_B0)
  41487     { /* SOC_REG_INT_OCB_GLOBAL_OCB_BANK_RANGE_BCM88375_B0r */
  41488         soc_block_list[51],
  41489         soc_genreg,
  41490         16,
  41491         0,
  41492         0xd2,
  41493         SOC_REG_FLAG_64_BITS |
  41494                           SOC_REG_FLAG_ARRAY |
  41495                           SOC_REG_FLAG_REG_ARRAY,
  41496         0,
  41497         2,
  41498         soc_OCB_GLOBAL_OCB_BANK_RANGE_BCM88375_B0r_fields,
  41499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  41501         -1,
  41502         -1,
  41503     },
  41504 #endif /* chips */
  41505 
  41506 #if defined(BCM_88675_B0)
  41507     { /* SOC_REG_INT_OCB_GLOBAL_OCB_BANK_RANGE_BCM88675_B0r */
  41508         soc_block_list[51],
  41509         soc_genreg,
  41510         16,
  41511         0,
  41512         0xd2,
  41513         SOC_REG_FLAG_64_BITS |
  41514                           SOC_REG_FLAG_ARRAY |
  41515                           SOC_REG_FLAG_REG_ARRAY,
  41516         0,
  41517         2,
  41518         soc_OCB_GLOBAL_OCB_BANK_RANGE_BCM88675_B0r_fields,
  41519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41520         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  41521         -1,
  41522         -1,
  41523     },
  41524 #endif /* chips */
  41525 
  41526 #if defined(BCM_88680_A0)
  41527     { /* SOC_REG_INT_OCB_GLOBAL_OCB_BANK_RANGE_BCM88680_A0r */
  41528         soc_block_list[51],
  41529         soc_genreg,
  41530         16,
  41531         0,
  41532         0xd2,
  41533         SOC_REG_FLAG_64_BITS |
  41534                           SOC_REG_FLAG_ARRAY |
  41535                           SOC_REG_FLAG_REG_ARRAY,
  41536         0,
  41537         2,
  41538         soc_OCB_GLOBAL_OCB_BANK_RANGE_BCM88680_A0r_fields,
  41539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41540         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  41541         -1,
  41542         -1,
  41543     },
  41544 #endif /* chips */
  41545 
  41546 #if defined(BCM_88650_A0)
  41547     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATIONr */
  41548         soc_block_list[51],
  41549         soc_genreg,
  41550         1,
  41551         0,
  41552         0x88,
  41553         0,
  41554         0,
  41555         3,
  41556         soc_OCB_GTIMER_CONFIGURATIONr_fields,
  41557         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  41558         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41559         -1,
  41560         -1,
  41561     },
  41562 #endif /* chips */
  41563 
  41564 #if defined(BCM_88202_A0)
  41565     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88202_A0r */
  41566         soc_block_list[51],
  41567         soc_genreg,
  41568         1,
  41569         0,
  41570         0x88,
  41571         0,
  41572         0,
  41573         3,
  41574         soc_OCB_GTIMER_CONFIGURATION_BCM88202_A0r_fields,
  41575         SOC_RESET_VAL_DEC(0x1ad27480, 0x00000000)
  41576         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41577         -1,
  41578         -1,
  41579     },
  41580 #endif /* chips */
  41581 
  41582 #if defined(BCM_88375_A0)
  41583     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88375_A0r */
  41584         soc_block_list[51],
  41585         soc_genreg,
  41586         1,
  41587         0,
  41588         0x88,
  41589         0,
  41590         0,
  41591         3,
  41592         soc_OCB_GTIMER_CONFIGURATION_BCM88375_A0r_fields,
  41593         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  41594         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41595         -1,
  41596         -1,
  41597     },
  41598 #endif /* chips */
  41599 
  41600 #if defined(BCM_88375_B0)
  41601     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88375_B0r */
  41602         soc_block_list[51],
  41603         soc_genreg,
  41604         1,
  41605         0,
  41606         0x88,
  41607         0,
  41608         0,
  41609         3,
  41610         soc_OCB_GTIMER_CONFIGURATION_BCM88375_B0r_fields,
  41611         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  41612         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41613         -1,
  41614         -1,
  41615     },
  41616 #endif /* chips */
  41617 
  41618 #if defined(BCM_88650_B0)
  41619     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88650_B0r */
  41620         soc_block_list[51],
  41621         soc_genreg,
  41622         1,
  41623         0,
  41624         0x88,
  41625         0,
  41626         0,
  41627         3,
  41628         soc_OCB_GTIMER_CONFIGURATION_BCM88650_B0r_fields,
  41629         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  41630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41631         -1,
  41632         -1,
  41633     },
  41634 #endif /* chips */
  41635 
  41636 #if defined(BCM_88660_A0)
  41637     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88660_A0r */
  41638         soc_block_list[51],
  41639         soc_genreg,
  41640         1,
  41641         0,
  41642         0x88,
  41643         0,
  41644         0,
  41645         3,
  41646         soc_OCB_GTIMER_CONFIGURATION_BCM88660_A0r_fields,
  41647         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  41648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41649         -1,
  41650         -1,
  41651     },
  41652 #endif /* chips */
  41653 
  41654 #if defined(BCM_88675_A0)
  41655     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88675_A0r */
  41656         soc_block_list[51],
  41657         soc_genreg,
  41658         1,
  41659         0,
  41660         0x88,
  41661         0,
  41662         0,
  41663         3,
  41664         soc_OCB_GTIMER_CONFIGURATION_BCM88675_A0r_fields,
  41665         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  41666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41667         -1,
  41668         -1,
  41669     },
  41670 #endif /* chips */
  41671 
  41672 #if defined(BCM_88675_B0)
  41673     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88675_B0r */
  41674         soc_block_list[51],
  41675         soc_genreg,
  41676         1,
  41677         0,
  41678         0x88,
  41679         0,
  41680         0,
  41681         3,
  41682         soc_OCB_GTIMER_CONFIGURATION_BCM88675_B0r_fields,
  41683         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  41684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41685         -1,
  41686         -1,
  41687     },
  41688 #endif /* chips */
  41689 
  41690 #if defined(BCM_88680_A0)
  41691     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88680_A0r */
  41692         soc_block_list[51],
  41693         soc_genreg,
  41694         1,
  41695         0,
  41696         0x88,
  41697         0,
  41698         0,
  41699         3,
  41700         soc_OCB_GTIMER_CONFIGURATION_BCM88680_A0r_fields,
  41701         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  41702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41703         -1,
  41704         -1,
  41705     },
  41706 #endif /* chips */
  41707 
  41708 #if defined(BCM_88690_A0)
  41709     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88690_A0r */
  41710         soc_block_list[51],
  41711         soc_genreg,
  41712         1,
  41713         0,
  41714         0x89,
  41715         0,
  41716         0,
  41717         3,
  41718         soc_OCB_GTIMER_CONFIGURATION_BCM88690_A0r_fields,
  41719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41720         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  41721         -1,
  41722         -1,
  41723     },
  41724 #endif /* chips */
  41725 
  41726 #if defined(BCM_88690_B0)
  41727     { /* SOC_REG_INT_OCB_GTIMER_CONFIGURATION_BCM88690_B0r */
  41728         soc_block_list[51],
  41729         soc_genreg,
  41730         1,
  41731         0,
  41732         0x89,
  41733         0,
  41734         0,
  41735         3,
  41736         soc_OCB_GTIMER_CONFIGURATION_BCM88690_B0r_fields,
  41737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41738         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  41739         -1,
  41740         -1,
  41741     },
  41742 #endif /* chips */
  41743 
  41744 #if defined(BCM_88690_A0)
  41745     { /* SOC_REG_INT_OCB_GTIMER_CYCLEr */
  41746         soc_block_list[51],
  41747         soc_genreg,
  41748         1,
  41749         0,
  41750         0x88,
  41751         0,
  41752         0,
  41753         1,
  41754         soc_OCB_GTIMER_CYCLEr_fields,
  41755         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  41756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41757         -1,
  41758         -1,
  41759     },
  41760 #endif /* chips */
  41761 
  41762 #if defined(BCM_88690_B0)
  41763     { /* SOC_REG_INT_OCB_GTIMER_CYCLE_BCM88690_B0r */
  41764         soc_block_list[51],
  41765         soc_genreg,
  41766         1,
  41767         0,
  41768         0x88,
  41769         0,
  41770         0,
  41771         1,
  41772         soc_OCB_GTIMER_CYCLE_BCM88690_B0r_fields,
  41773         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  41774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41775         -1,
  41776         -1,
  41777     },
  41778 #endif /* chips */
  41779 
  41780 #if defined(BCM_88650_A0)
  41781     { /* SOC_REG_INT_OCB_GTIMER_TRIGGERr */
  41782         soc_block_list[51],
  41783         soc_genreg,
  41784         1,
  41785         0,
  41786         0x89,
  41787         SOC_REG_FLAG_SIGNAL,
  41788         0,
  41789         1,
  41790         soc_OCB_GTIMER_TRIGGERr_fields,
  41791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41792         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  41793         -1,
  41794         -1,
  41795     },
  41796 #endif /* chips */
  41797 
  41798 #if defined(BCM_88202_A0)
  41799     { /* SOC_REG_INT_OCB_GTIMER_TRIGGER_BCM88202_A0r */
  41800         soc_block_list[51],
  41801         soc_genreg,
  41802         1,
  41803         0,
  41804         0x89,
  41805         SOC_REG_FLAG_SIGNAL,
  41806         0,
  41807         1,
  41808         soc_OCB_GTIMER_TRIGGER_BCM88202_A0r_fields,
  41809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41810         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  41811         -1,
  41812         -1,
  41813     },
  41814 #endif /* chips */
  41815 
  41816 #if defined(BCM_88375_A0)
  41817     { /* SOC_REG_INT_OCB_GTIMER_TRIGGER_BCM88375_A0r */
  41818         soc_block_list[51],
  41819         soc_genreg,
  41820         1,
  41821         0,
  41822         0x89,
  41823         SOC_REG_FLAG_RO,
  41824         0,
  41825         1,
  41826         soc_OCB_GTIMER_TRIGGER_BCM88375_A0r_fields,
  41827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41828         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  41829         -1,
  41830         -1,
  41831     },
  41832 #endif /* chips */
  41833 
  41834 #if defined(BCM_88375_B0)
  41835     { /* SOC_REG_INT_OCB_GTIMER_TRIGGER_BCM88375_B0r */
  41836         soc_block_list[51],
  41837         soc_genreg,
  41838         1,
  41839         0,
  41840         0x89,
  41841         SOC_REG_FLAG_RO,
  41842         0,
  41843         1,
  41844         soc_OCB_GTIMER_TRIGGER_BCM88375_B0r_fields,
  41845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41846         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  41847         -1,
  41848         -1,
  41849     },
  41850 #endif /* chips */
  41851 
  41852 #if defined(BCM_88650_B0)
  41853     { /* SOC_REG_INT_OCB_GTIMER_TRIGGER_BCM88650_B0r */
  41854         soc_block_list[51],
  41855         soc_genreg,
  41856         1,
  41857         0,
  41858         0x89,
  41859         SOC_REG_FLAG_SIGNAL,
  41860         0,
  41861         1,
  41862         soc_OCB_GTIMER_TRIGGER_BCM88650_B0r_fields,
  41863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41864         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  41865         -1,
  41866         -1,
  41867     },
  41868 #endif /* chips */
  41869 
  41870 #if defined(BCM_88660_A0)
  41871     { /* SOC_REG_INT_OCB_GTIMER_TRIGGER_BCM88660_A0r */
  41872         soc_block_list[51],
  41873         soc_genreg,
  41874         1,
  41875         0,
  41876         0x89,
  41877         SOC_REG_FLAG_SIGNAL,
  41878         0,
  41879         1,
  41880         soc_OCB_GTIMER_TRIGGER_BCM88660_A0r_fields,
  41881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41882         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  41883         -1,
  41884         -1,
  41885     },
  41886 #endif /* chips */
  41887 
  41888 #if defined(BCM_88675_A0)
  41889     { /* SOC_REG_INT_OCB_GTIMER_TRIGGER_BCM88675_A0r */
  41890         soc_block_list[51],
  41891         soc_genreg,
  41892         1,
  41893         0,
  41894         0x89,
  41895         SOC_REG_FLAG_RO,
  41896         0,
  41897         1,
  41898         soc_OCB_GTIMER_TRIGGER_BCM88675_A0r_fields,
  41899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41900         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  41901         -1,
  41902         -1,
  41903     },
  41904 #endif /* chips */
  41905 
  41906 #if defined(BCM_88675_B0)
  41907     { /* SOC_REG_INT_OCB_GTIMER_TRIGGER_BCM88675_B0r */
  41908         soc_block_list[51],
  41909         soc_genreg,
  41910         1,
  41911         0,
  41912         0x89,
  41913         SOC_REG_FLAG_RO,
  41914         0,
  41915         1,
  41916         soc_OCB_GTIMER_TRIGGER_BCM88675_B0r_fields,
  41917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41918         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  41919         -1,
  41920         -1,
  41921     },
  41922 #endif /* chips */
  41923 
  41924 #if defined(BCM_88680_A0)
  41925     { /* SOC_REG_INT_OCB_GTIMER_TRIGGER_BCM88680_A0r */
  41926         soc_block_list[51],
  41927         soc_genreg,
  41928         1,
  41929         0,
  41930         0x89,
  41931         SOC_REG_FLAG_RO,
  41932         0,
  41933         1,
  41934         soc_OCB_GTIMER_TRIGGER_BCM88680_A0r_fields,
  41935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41936         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  41937         -1,
  41938         -1,
  41939     },
  41940 #endif /* chips */
  41941 
  41942 #if defined(BCM_88650_A0)
  41943     { /* SOC_REG_INT_OCB_INDIRECT_COMMANDr */
  41944         soc_block_list[51],
  41945         soc_genreg,
  41946         1,
  41947         0,
  41948         0x80,
  41949         0,
  41950         0,
  41951         5,
  41952         soc_OCB_INDIRECT_COMMANDr_fields,
  41953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41954         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41955         -1,
  41956         -1,
  41957     },
  41958 #endif /* chips */
  41959 
  41960 #if defined(BCM_88650_A0)
  41961     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESSr */
  41962         soc_block_list[51],
  41963         soc_genreg,
  41964         1,
  41965         0,
  41966         0x81,
  41967         0,
  41968         0,
  41969         2,
  41970         soc_OCB_INDIRECT_COMMAND_ADDRESSr_fields,
  41971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41972         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41973         -1,
  41974         -1,
  41975     },
  41976 #endif /* chips */
  41977 
  41978 #if defined(BCM_88202_A0)
  41979     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88202_A0r */
  41980         soc_block_list[51],
  41981         soc_genreg,
  41982         1,
  41983         0,
  41984         0x81,
  41985         0,
  41986         0,
  41987         2,
  41988         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88202_A0r_fields,
  41989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41990         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41991         -1,
  41992         -1,
  41993     },
  41994 #endif /* chips */
  41995 
  41996 #if defined(BCM_88375_A0)
  41997     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88375_A0r */
  41998         soc_block_list[51],
  41999         soc_genreg,
  42000         1,
  42001         0,
  42002         0x81,
  42003         0,
  42004         0,
  42005         2,
  42006         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88375_A0r_fields,
  42007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42008         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42009         -1,
  42010         -1,
  42011     },
  42012 #endif /* chips */
  42013 
  42014 #if defined(BCM_88375_B0)
  42015     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88375_B0r */
  42016         soc_block_list[51],
  42017         soc_genreg,
  42018         1,
  42019         0,
  42020         0x81,
  42021         0,
  42022         0,
  42023         2,
  42024         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88375_B0r_fields,
  42025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42026         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42027         -1,
  42028         -1,
  42029     },
  42030 #endif /* chips */
  42031 
  42032 #if defined(BCM_88650_B0)
  42033     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88650_B0r */
  42034         soc_block_list[51],
  42035         soc_genreg,
  42036         1,
  42037         0,
  42038         0x81,
  42039         0,
  42040         0,
  42041         2,
  42042         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88650_B0r_fields,
  42043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42044         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42045         -1,
  42046         -1,
  42047     },
  42048 #endif /* chips */
  42049 
  42050 #if defined(BCM_88660_A0)
  42051     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88660_A0r */
  42052         soc_block_list[51],
  42053         soc_genreg,
  42054         1,
  42055         0,
  42056         0x81,
  42057         0,
  42058         0,
  42059         2,
  42060         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88660_A0r_fields,
  42061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42062         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42063         -1,
  42064         -1,
  42065     },
  42066 #endif /* chips */
  42067 
  42068 #if defined(BCM_88675_A0)
  42069     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88675_A0r */
  42070         soc_block_list[51],
  42071         soc_genreg,
  42072         1,
  42073         0,
  42074         0x81,
  42075         0,
  42076         0,
  42077         2,
  42078         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88675_A0r_fields,
  42079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42080         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42081         -1,
  42082         -1,
  42083     },
  42084 #endif /* chips */
  42085 
  42086 #if defined(BCM_88675_B0)
  42087     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88675_B0r */
  42088         soc_block_list[51],
  42089         soc_genreg,
  42090         1,
  42091         0,
  42092         0x81,
  42093         0,
  42094         0,
  42095         2,
  42096         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88675_B0r_fields,
  42097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42098         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42099         -1,
  42100         -1,
  42101     },
  42102 #endif /* chips */
  42103 
  42104 #if defined(BCM_88680_A0)
  42105     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r */
  42106         soc_block_list[51],
  42107         soc_genreg,
  42108         1,
  42109         0,
  42110         0x81,
  42111         0,
  42112         0,
  42113         2,
  42114         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r_fields,
  42115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42116         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42117         -1,
  42118         -1,
  42119     },
  42120 #endif /* chips */
  42121 
  42122 #if defined(BCM_88690_A0)
  42123     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r */
  42124         soc_block_list[51],
  42125         soc_genreg,
  42126         1,
  42127         0,
  42128         0x81,
  42129         0,
  42130         0,
  42131         2,
  42132         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r_fields,
  42133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42134         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42135         -1,
  42136         -1,
  42137     },
  42138 #endif /* chips */
  42139 
  42140 #if defined(BCM_88690_B0)
  42141     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r */
  42142         soc_block_list[51],
  42143         soc_genreg,
  42144         1,
  42145         0,
  42146         0x81,
  42147         0,
  42148         0,
  42149         2,
  42150         soc_OCB_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r_fields,
  42151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42152         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42153         -1,
  42154         -1,
  42155     },
  42156 #endif /* chips */
  42157 
  42158 #if defined(BCM_88202_A0)
  42159     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88202_A0r */
  42160         soc_block_list[51],
  42161         soc_genreg,
  42162         1,
  42163         0,
  42164         0x80,
  42165         0,
  42166         0,
  42167         5,
  42168         soc_OCB_INDIRECT_COMMAND_BCM88202_A0r_fields,
  42169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42170         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42171         -1,
  42172         -1,
  42173     },
  42174 #endif /* chips */
  42175 
  42176 #if defined(BCM_88375_A0)
  42177     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88375_A0r */
  42178         soc_block_list[51],
  42179         soc_genreg,
  42180         1,
  42181         0,
  42182         0x80,
  42183         0,
  42184         0,
  42185         5,
  42186         soc_OCB_INDIRECT_COMMAND_BCM88375_A0r_fields,
  42187         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  42188         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42189         -1,
  42190         -1,
  42191     },
  42192 #endif /* chips */
  42193 
  42194 #if defined(BCM_88375_B0)
  42195     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88375_B0r */
  42196         soc_block_list[51],
  42197         soc_genreg,
  42198         1,
  42199         0,
  42200         0x80,
  42201         0,
  42202         0,
  42203         5,
  42204         soc_OCB_INDIRECT_COMMAND_BCM88375_B0r_fields,
  42205         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  42206         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42207         -1,
  42208         -1,
  42209     },
  42210 #endif /* chips */
  42211 
  42212 #if defined(BCM_88650_B0)
  42213     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88650_B0r */
  42214         soc_block_list[51],
  42215         soc_genreg,
  42216         1,
  42217         0,
  42218         0x80,
  42219         0,
  42220         0,
  42221         5,
  42222         soc_OCB_INDIRECT_COMMAND_BCM88650_B0r_fields,
  42223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42224         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42225         -1,
  42226         -1,
  42227     },
  42228 #endif /* chips */
  42229 
  42230 #if defined(BCM_88660_A0)
  42231     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88660_A0r */
  42232         soc_block_list[51],
  42233         soc_genreg,
  42234         1,
  42235         0,
  42236         0x80,
  42237         0,
  42238         0,
  42239         5,
  42240         soc_OCB_INDIRECT_COMMAND_BCM88660_A0r_fields,
  42241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42242         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42243         -1,
  42244         -1,
  42245     },
  42246 #endif /* chips */
  42247 
  42248 #if defined(BCM_88675_A0)
  42249     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88675_A0r */
  42250         soc_block_list[51],
  42251         soc_genreg,
  42252         1,
  42253         0,
  42254         0x80,
  42255         0,
  42256         0,
  42257         5,
  42258         soc_OCB_INDIRECT_COMMAND_BCM88675_A0r_fields,
  42259         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  42260         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42261         -1,
  42262         -1,
  42263     },
  42264 #endif /* chips */
  42265 
  42266 #if defined(BCM_88675_B0)
  42267     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88675_B0r */
  42268         soc_block_list[51],
  42269         soc_genreg,
  42270         1,
  42271         0,
  42272         0x80,
  42273         0,
  42274         0,
  42275         5,
  42276         soc_OCB_INDIRECT_COMMAND_BCM88675_B0r_fields,
  42277         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  42278         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42279         -1,
  42280         -1,
  42281     },
  42282 #endif /* chips */
  42283 
  42284 #if defined(BCM_88680_A0)
  42285     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88680_A0r */
  42286         soc_block_list[51],
  42287         soc_genreg,
  42288         1,
  42289         0,
  42290         0x80,
  42291         0,
  42292         0,
  42293         5,
  42294         soc_OCB_INDIRECT_COMMAND_BCM88680_A0r_fields,
  42295         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  42296         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42297         -1,
  42298         -1,
  42299     },
  42300 #endif /* chips */
  42301 
  42302 #if defined(BCM_88690_A0)
  42303     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88690_A0r */
  42304         soc_block_list[51],
  42305         soc_genreg,
  42306         1,
  42307         0,
  42308         0x80,
  42309         0,
  42310         0,
  42311         5,
  42312         soc_OCB_INDIRECT_COMMAND_BCM88690_A0r_fields,
  42313         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
  42314         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42315         -1,
  42316         -1,
  42317     },
  42318 #endif /* chips */
  42319 
  42320 #if defined(BCM_88690_B0)
  42321     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_BCM88690_B0r */
  42322         soc_block_list[51],
  42323         soc_genreg,
  42324         1,
  42325         0,
  42326         0x80,
  42327         0,
  42328         0,
  42329         5,
  42330         soc_OCB_INDIRECT_COMMAND_BCM88690_B0r_fields,
  42331         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
  42332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42333         -1,
  42334         -1,
  42335     },
  42336 #endif /* chips */
  42337 
  42338 #if defined(BCM_88650_A0)
  42339     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_DATA_INCREMENTr */
  42340         soc_block_list[51],
  42341         soc_genreg,
  42342         1,
  42343         0,
  42344         0x82,
  42345         SOC_REG_FLAG_64_BITS |
  42346                           SOC_REG_FLAG_SIGNAL,
  42347         0,
  42348         1,
  42349         soc_OCB_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
  42350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42351         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  42352         -1,
  42353         -1,
  42354     },
  42355 #endif /* chips */
  42356 
  42357 #if defined(BCM_88202_A0)
  42358     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88202_A0r */
  42359         soc_block_list[51],
  42360         soc_genreg,
  42361         1,
  42362         0,
  42363         0x82,
  42364         SOC_REG_FLAG_64_BITS |
  42365                           SOC_REG_FLAG_SIGNAL,
  42366         0,
  42367         1,
  42368         soc_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88202_A0r_fields,
  42369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42370         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  42371         -1,
  42372         -1,
  42373     },
  42374 #endif /* chips */
  42375 
  42376 #if defined(BCM_88375_A0)
  42377     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_A0r */
  42378         soc_block_list[51],
  42379         soc_genreg,
  42380         1,
  42381         0,
  42382         0x82,
  42383         SOC_REG_FLAG_64_BITS,
  42384         0,
  42385         1,
  42386         soc_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_A0r_fields,
  42387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42388         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  42389         -1,
  42390         -1,
  42391     },
  42392 #endif /* chips */
  42393 
  42394 #if defined(BCM_88375_B0)
  42395     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_B0r */
  42396         soc_block_list[51],
  42397         soc_genreg,
  42398         1,
  42399         0,
  42400         0x82,
  42401         SOC_REG_FLAG_64_BITS,
  42402         0,
  42403         1,
  42404         soc_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_B0r_fields,
  42405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42406         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  42407         -1,
  42408         -1,
  42409     },
  42410 #endif /* chips */
  42411 
  42412 #if defined(BCM_88650_B0)
  42413     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88650_B0r */
  42414         soc_block_list[51],
  42415         soc_genreg,
  42416         1,
  42417         0,
  42418         0x82,
  42419         SOC_REG_FLAG_64_BITS |
  42420                           SOC_REG_FLAG_SIGNAL,
  42421         0,
  42422         1,
  42423         soc_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88650_B0r_fields,
  42424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42425         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  42426         -1,
  42427         -1,
  42428     },
  42429 #endif /* chips */
  42430 
  42431 #if defined(BCM_88660_A0)
  42432     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88660_A0r */
  42433         soc_block_list[51],
  42434         soc_genreg,
  42435         1,
  42436         0,
  42437         0x82,
  42438         SOC_REG_FLAG_64_BITS |
  42439                           SOC_REG_FLAG_SIGNAL,
  42440         0,
  42441         1,
  42442         soc_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88660_A0r_fields,
  42443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42444         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  42445         -1,
  42446         -1,
  42447     },
  42448 #endif /* chips */
  42449 
  42450 #if defined(BCM_88675_A0)
  42451     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_A0r */
  42452         soc_block_list[51],
  42453         soc_genreg,
  42454         1,
  42455         0,
  42456         0x82,
  42457         SOC_REG_FLAG_64_BITS,
  42458         0,
  42459         1,
  42460         soc_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_A0r_fields,
  42461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42462         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  42463         -1,
  42464         -1,
  42465     },
  42466 #endif /* chips */
  42467 
  42468 #if defined(BCM_88675_B0)
  42469     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_B0r */
  42470         soc_block_list[51],
  42471         soc_genreg,
  42472         1,
  42473         0,
  42474         0x82,
  42475         SOC_REG_FLAG_64_BITS,
  42476         0,
  42477         1,
  42478         soc_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_B0r_fields,
  42479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42480         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  42481         -1,
  42482         -1,
  42483     },
  42484 #endif /* chips */
  42485 
  42486 #if defined(BCM_88680_A0)
  42487     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r */
  42488         soc_block_list[51],
  42489         soc_genreg,
  42490         1,
  42491         0,
  42492         0x82,
  42493         SOC_REG_FLAG_64_BITS,
  42494         0,
  42495         1,
  42496         soc_OCB_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r_fields,
  42497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42498         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  42499         -1,
  42500         -1,
  42501     },
  42502 #endif /* chips */
  42503 
  42504 #if defined(BCM_88675_A0)
  42505     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_RD_DATAr */
  42506         soc_block_list[51],
  42507         soc_genreg,
  42508         1,
  42509         0,
  42510         0x60,
  42511         SOC_REG_FLAG_ABOVE_64_BITS |
  42512                           SOC_REG_FLAG_RO |
  42513                           SOC_REG_FLAG_SIGNAL,
  42514         0,
  42515         1,
  42516         soc_OCB_INDIRECT_COMMAND_RD_DATAr_fields,
  42517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42518         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42519         -1,
  42520         -1,
  42521     },
  42522 #endif /* chips */
  42523 
  42524 #if defined(BCM_88375_A0)
  42525     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_RD_DATA_BCM88375_A0r */
  42526         soc_block_list[51],
  42527         soc_genreg,
  42528         1,
  42529         0,
  42530         0x60,
  42531         SOC_REG_FLAG_ABOVE_64_BITS |
  42532                           SOC_REG_FLAG_RO |
  42533                           SOC_REG_FLAG_SIGNAL,
  42534         0,
  42535         1,
  42536         soc_OCB_INDIRECT_COMMAND_RD_DATA_BCM88375_A0r_fields,
  42537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42539         -1,
  42540         -1,
  42541     },
  42542 #endif /* chips */
  42543 
  42544 #if defined(BCM_88375_B0)
  42545     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_RD_DATA_BCM88375_B0r */
  42546         soc_block_list[51],
  42547         soc_genreg,
  42548         1,
  42549         0,
  42550         0x60,
  42551         SOC_REG_FLAG_ABOVE_64_BITS |
  42552                           SOC_REG_FLAG_RO |
  42553                           SOC_REG_FLAG_SIGNAL,
  42554         0,
  42555         1,
  42556         soc_OCB_INDIRECT_COMMAND_RD_DATA_BCM88375_B0r_fields,
  42557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42559         -1,
  42560         -1,
  42561     },
  42562 #endif /* chips */
  42563 
  42564 #if defined(BCM_88675_B0)
  42565     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_RD_DATA_BCM88675_B0r */
  42566         soc_block_list[51],
  42567         soc_genreg,
  42568         1,
  42569         0,
  42570         0x60,
  42571         SOC_REG_FLAG_ABOVE_64_BITS |
  42572                           SOC_REG_FLAG_RO |
  42573                           SOC_REG_FLAG_SIGNAL,
  42574         0,
  42575         1,
  42576         soc_OCB_INDIRECT_COMMAND_RD_DATA_BCM88675_B0r_fields,
  42577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42578         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42579         -1,
  42580         -1,
  42581     },
  42582 #endif /* chips */
  42583 
  42584 #if defined(BCM_88680_A0)
  42585     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_RD_DATA_BCM88680_A0r */
  42586         soc_block_list[51],
  42587         soc_genreg,
  42588         1,
  42589         0,
  42590         0x60,
  42591         SOC_REG_FLAG_ABOVE_64_BITS |
  42592                           SOC_REG_FLAG_RO |
  42593                           SOC_REG_FLAG_SIGNAL,
  42594         0,
  42595         1,
  42596         soc_OCB_INDIRECT_COMMAND_RD_DATA_BCM88680_A0r_fields,
  42597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42598         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42599         -1,
  42600         -1,
  42601     },
  42602 #endif /* chips */
  42603 
  42604 #if defined(BCM_88690_A0)
  42605     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_RD_DATA_BCM88690_A0r */
  42606         soc_block_list[51],
  42607         soc_genreg,
  42608         1,
  42609         0,
  42610         0x60,
  42611         SOC_REG_FLAG_ABOVE_64_BITS |
  42612                           SOC_REG_FLAG_RO |
  42613                           SOC_REG_FLAG_SIGNAL,
  42614         0,
  42615         1,
  42616         soc_OCB_INDIRECT_COMMAND_RD_DATA_BCM88690_A0r_fields,
  42617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42618         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42619         -1,
  42620         -1,
  42621     },
  42622 #endif /* chips */
  42623 
  42624 #if defined(BCM_88690_B0)
  42625     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r */
  42626         soc_block_list[51],
  42627         soc_genreg,
  42628         1,
  42629         0,
  42630         0x60,
  42631         SOC_REG_FLAG_ABOVE_64_BITS |
  42632                           SOC_REG_FLAG_RO |
  42633                           SOC_REG_FLAG_SIGNAL,
  42634         0,
  42635         1,
  42636         soc_OCB_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r_fields,
  42637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42638         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42639         -1,
  42640         -1,
  42641     },
  42642 #endif /* chips */
  42643 
  42644 #if defined(BCM_88675_A0)
  42645     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WIDE_MEMr */
  42646         soc_block_list[51],
  42647         soc_genreg,
  42648         1,
  42649         0,
  42650         0x41,
  42651         0,
  42652         0,
  42653         1,
  42654         soc_OCB_INDIRECT_COMMAND_WIDE_MEMr_fields,
  42655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42656         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42657         -1,
  42658         -1,
  42659     },
  42660 #endif /* chips */
  42661 
  42662 #if defined(BCM_88375_A0)
  42663     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88375_A0r */
  42664         soc_block_list[51],
  42665         soc_genreg,
  42666         1,
  42667         0,
  42668         0x41,
  42669         0,
  42670         0,
  42671         1,
  42672         soc_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88375_A0r_fields,
  42673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42674         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42675         -1,
  42676         -1,
  42677     },
  42678 #endif /* chips */
  42679 
  42680 #if defined(BCM_88375_B0)
  42681     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88375_B0r */
  42682         soc_block_list[51],
  42683         soc_genreg,
  42684         1,
  42685         0,
  42686         0x41,
  42687         0,
  42688         0,
  42689         1,
  42690         soc_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88375_B0r_fields,
  42691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42692         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42693         -1,
  42694         -1,
  42695     },
  42696 #endif /* chips */
  42697 
  42698 #if defined(BCM_88675_B0)
  42699     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88675_B0r */
  42700         soc_block_list[51],
  42701         soc_genreg,
  42702         1,
  42703         0,
  42704         0x41,
  42705         0,
  42706         0,
  42707         1,
  42708         soc_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88675_B0r_fields,
  42709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42710         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42711         -1,
  42712         -1,
  42713     },
  42714 #endif /* chips */
  42715 
  42716 #if defined(BCM_88680_A0)
  42717     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r */
  42718         soc_block_list[51],
  42719         soc_genreg,
  42720         1,
  42721         0,
  42722         0x41,
  42723         0,
  42724         0,
  42725         1,
  42726         soc_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r_fields,
  42727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42728         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42729         -1,
  42730         -1,
  42731     },
  42732 #endif /* chips */
  42733 
  42734 #if defined(BCM_88690_A0)
  42735     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88690_A0r */
  42736         soc_block_list[51],
  42737         soc_genreg,
  42738         1,
  42739         0,
  42740         0x41,
  42741         0,
  42742         0,
  42743         1,
  42744         soc_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88690_A0r_fields,
  42745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42746         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42747         -1,
  42748         -1,
  42749     },
  42750 #endif /* chips */
  42751 
  42752 #if defined(BCM_88690_B0)
  42753     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88690_B0r */
  42754         soc_block_list[51],
  42755         soc_genreg,
  42756         1,
  42757         0,
  42758         0x41,
  42759         0,
  42760         0,
  42761         1,
  42762         soc_OCB_INDIRECT_COMMAND_WIDE_MEM_BCM88690_B0r_fields,
  42763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42764         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42765         -1,
  42766         -1,
  42767     },
  42768 #endif /* chips */
  42769 
  42770 #if defined(BCM_88675_A0)
  42771     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WR_DATAr */
  42772         soc_block_list[51],
  42773         soc_genreg,
  42774         1,
  42775         0,
  42776         0x20,
  42777         SOC_REG_FLAG_ABOVE_64_BITS,
  42778         0,
  42779         1,
  42780         soc_OCB_INDIRECT_COMMAND_WR_DATAr_fields,
  42781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42782         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42783         -1,
  42784         -1,
  42785     },
  42786 #endif /* chips */
  42787 
  42788 #if defined(BCM_88375_A0)
  42789     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WR_DATA_BCM88375_A0r */
  42790         soc_block_list[51],
  42791         soc_genreg,
  42792         1,
  42793         0,
  42794         0x20,
  42795         SOC_REG_FLAG_ABOVE_64_BITS,
  42796         0,
  42797         1,
  42798         soc_OCB_INDIRECT_COMMAND_WR_DATA_BCM88375_A0r_fields,
  42799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42801         -1,
  42802         -1,
  42803     },
  42804 #endif /* chips */
  42805 
  42806 #if defined(BCM_88375_B0)
  42807     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WR_DATA_BCM88375_B0r */
  42808         soc_block_list[51],
  42809         soc_genreg,
  42810         1,
  42811         0,
  42812         0x20,
  42813         SOC_REG_FLAG_ABOVE_64_BITS,
  42814         0,
  42815         1,
  42816         soc_OCB_INDIRECT_COMMAND_WR_DATA_BCM88375_B0r_fields,
  42817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42819         -1,
  42820         -1,
  42821     },
  42822 #endif /* chips */
  42823 
  42824 #if defined(BCM_88675_B0)
  42825     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WR_DATA_BCM88675_B0r */
  42826         soc_block_list[51],
  42827         soc_genreg,
  42828         1,
  42829         0,
  42830         0x20,
  42831         SOC_REG_FLAG_ABOVE_64_BITS,
  42832         0,
  42833         1,
  42834         soc_OCB_INDIRECT_COMMAND_WR_DATA_BCM88675_B0r_fields,
  42835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42836         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42837         -1,
  42838         -1,
  42839     },
  42840 #endif /* chips */
  42841 
  42842 #if defined(BCM_88680_A0)
  42843     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r */
  42844         soc_block_list[51],
  42845         soc_genreg,
  42846         1,
  42847         0,
  42848         0x20,
  42849         SOC_REG_FLAG_ABOVE_64_BITS,
  42850         0,
  42851         1,
  42852         soc_OCB_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r_fields,
  42853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42855         -1,
  42856         -1,
  42857     },
  42858 #endif /* chips */
  42859 
  42860 #if defined(BCM_88690_A0)
  42861     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r */
  42862         soc_block_list[51],
  42863         soc_genreg,
  42864         1,
  42865         0,
  42866         0x20,
  42867         SOC_REG_FLAG_ABOVE_64_BITS,
  42868         0,
  42869         1,
  42870         soc_OCB_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r_fields,
  42871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42873         -1,
  42874         -1,
  42875     },
  42876 #endif /* chips */
  42877 
  42878 #if defined(BCM_88690_B0)
  42879     { /* SOC_REG_INT_OCB_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r */
  42880         soc_block_list[51],
  42881         soc_genreg,
  42882         1,
  42883         0,
  42884         0x20,
  42885         SOC_REG_FLAG_ABOVE_64_BITS,
  42886         0,
  42887         1,
  42888         soc_OCB_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r_fields,
  42889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42890         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42891         -1,
  42892         -1,
  42893     },
  42894 #endif /* chips */
  42895 
  42896 #if defined(BCM_88675_A0)
  42897     { /* SOC_REG_INT_OCB_INDIRECT_FORCE_BUBBLEr */
  42898         soc_block_list[51],
  42899         soc_genreg,
  42900         1,
  42901         0,
  42902         0x83,
  42903         0,
  42904         0,
  42905         4,
  42906         soc_OCB_INDIRECT_FORCE_BUBBLEr_fields,
  42907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42908         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  42909         -1,
  42910         -1,
  42911     },
  42912 #endif /* chips */
  42913 
  42914 #if defined(BCM_88375_A0)
  42915     { /* SOC_REG_INT_OCB_INDIRECT_FORCE_BUBBLE_BCM88375_A0r */
  42916         soc_block_list[51],
  42917         soc_genreg,
  42918         1,
  42919         0,
  42920         0x83,
  42921         0,
  42922         0,
  42923         4,
  42924         soc_OCB_INDIRECT_FORCE_BUBBLE_BCM88375_A0r_fields,
  42925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42926         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  42927         -1,
  42928         -1,
  42929     },
  42930 #endif /* chips */
  42931 
  42932 #if defined(BCM_88375_B0)
  42933     { /* SOC_REG_INT_OCB_INDIRECT_FORCE_BUBBLE_BCM88375_B0r */
  42934         soc_block_list[51],
  42935         soc_genreg,
  42936         1,
  42937         0,
  42938         0x83,
  42939         0,
  42940         0,
  42941         4,
  42942         soc_OCB_INDIRECT_FORCE_BUBBLE_BCM88375_B0r_fields,
  42943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42944         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  42945         -1,
  42946         -1,
  42947     },
  42948 #endif /* chips */
  42949 
  42950 #if defined(BCM_88675_B0)
  42951     { /* SOC_REG_INT_OCB_INDIRECT_FORCE_BUBBLE_BCM88675_B0r */
  42952         soc_block_list[51],
  42953         soc_genreg,
  42954         1,
  42955         0,
  42956         0x83,
  42957         0,
  42958         0,
  42959         4,
  42960         soc_OCB_INDIRECT_FORCE_BUBBLE_BCM88675_B0r_fields,
  42961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42962         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  42963         -1,
  42964         -1,
  42965     },
  42966 #endif /* chips */
  42967 
  42968 #if defined(BCM_88680_A0)
  42969     { /* SOC_REG_INT_OCB_INDIRECT_FORCE_BUBBLE_BCM88680_A0r */
  42970         soc_block_list[51],
  42971         soc_genreg,
  42972         1,
  42973         0,
  42974         0x83,
  42975         0,
  42976         0,
  42977         4,
  42978         soc_OCB_INDIRECT_FORCE_BUBBLE_BCM88680_A0r_fields,
  42979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42980         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  42981         -1,
  42982         -1,
  42983     },
  42984 #endif /* chips */
  42985 
  42986 #if defined(BCM_88690_A0)
  42987     { /* SOC_REG_INT_OCB_INDIRECT_FORCE_BUBBLE_BCM88690_A0r */
  42988         soc_block_list[51],
  42989         soc_genreg,
  42990         1,
  42991         0,
  42992         0x83,
  42993         0,
  42994         0,
  42995         4,
  42996         soc_OCB_INDIRECT_FORCE_BUBBLE_BCM88690_A0r_fields,
  42997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42998         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  42999         -1,
  43000         -1,
  43001     },
  43002 #endif /* chips */
  43003 
  43004 #if defined(BCM_88690_B0)
  43005     { /* SOC_REG_INT_OCB_INDIRECT_FORCE_BUBBLE_BCM88690_B0r */
  43006         soc_block_list[51],
  43007         soc_genreg,
  43008         1,
  43009         0,
  43010         0x83,
  43011         0,
  43012         0,
  43013         4,
  43014         soc_OCB_INDIRECT_FORCE_BUBBLE_BCM88690_B0r_fields,
  43015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43016         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  43017         -1,
  43018         -1,
  43019     },
  43020 #endif /* chips */
  43021 
  43022 #if defined(BCM_88650_A0)
  43023     { /* SOC_REG_INT_OCB_INDIRECT_READ_DATA_0r */
  43024         soc_block_list[51],
  43025         soc_genreg,
  43026         1,
  43027         0,
  43028         0x130,
  43029         SOC_REG_FLAG_ABOVE_64_BITS,
  43030         0,
  43031         1,
  43032         soc_OCB_INDIRECT_READ_DATA_0r_fields,
  43033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43034         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43035         -1,
  43036         -1,
  43037     },
  43038 #endif /* chips */
  43039 
  43040 #if defined(BCM_88650_A0)
  43041     { /* SOC_REG_INT_OCB_INDIRECT_READ_DATA_1r */
  43042         soc_block_list[51],
  43043         soc_genreg,
  43044         1,
  43045         0,
  43046         0x140,
  43047         SOC_REG_FLAG_ABOVE_64_BITS,
  43048         0,
  43049         1,
  43050         soc_OCB_INDIRECT_READ_DATA_1r_fields,
  43051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43052         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43053         -1,
  43054         -1,
  43055     },
  43056 #endif /* chips */
  43057 
  43058 #if defined(BCM_88202_A0)
  43059     { /* SOC_REG_INT_OCB_INDIRECT_READ_DATA_0_BCM88202_A0r */
  43060         soc_block_list[51],
  43061         soc_genreg,
  43062         1,
  43063         0,
  43064         0x130,
  43065         SOC_REG_FLAG_ABOVE_64_BITS,
  43066         0,
  43067         1,
  43068         soc_OCB_INDIRECT_READ_DATA_0_BCM88202_A0r_fields,
  43069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43070         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43071         -1,
  43072         -1,
  43073     },
  43074 #endif /* chips */
  43075 
  43076 #if defined(BCM_88650_B0)
  43077     { /* SOC_REG_INT_OCB_INDIRECT_READ_DATA_0_BCM88650_B0r */
  43078         soc_block_list[51],
  43079         soc_genreg,
  43080         1,
  43081         0,
  43082         0x130,
  43083         SOC_REG_FLAG_ABOVE_64_BITS,
  43084         0,
  43085         1,
  43086         soc_OCB_INDIRECT_READ_DATA_0_BCM88650_B0r_fields,
  43087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43088         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43089         -1,
  43090         -1,
  43091     },
  43092 #endif /* chips */
  43093 
  43094 #if defined(BCM_88660_A0)
  43095     { /* SOC_REG_INT_OCB_INDIRECT_READ_DATA_0_BCM88660_A0r */
  43096         soc_block_list[51],
  43097         soc_genreg,
  43098         1,
  43099         0,
  43100         0x130,
  43101         SOC_REG_FLAG_ABOVE_64_BITS,
  43102         0,
  43103         1,
  43104         soc_OCB_INDIRECT_READ_DATA_0_BCM88660_A0r_fields,
  43105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43106         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43107         -1,
  43108         -1,
  43109     },
  43110 #endif /* chips */
  43111 
  43112 #if defined(BCM_88202_A0)
  43113     { /* SOC_REG_INT_OCB_INDIRECT_READ_DATA_1_BCM88202_A0r */
  43114         soc_block_list[51],
  43115         soc_genreg,
  43116         1,
  43117         0,
  43118         0x140,
  43119         SOC_REG_FLAG_ABOVE_64_BITS,
  43120         0,
  43121         1,
  43122         soc_OCB_INDIRECT_READ_DATA_1_BCM88202_A0r_fields,
  43123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43124         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43125         -1,
  43126         -1,
  43127     },
  43128 #endif /* chips */
  43129 
  43130 #if defined(BCM_88650_B0)
  43131     { /* SOC_REG_INT_OCB_INDIRECT_READ_DATA_1_BCM88650_B0r */
  43132         soc_block_list[51],
  43133         soc_genreg,
  43134         1,
  43135         0,
  43136         0x140,
  43137         SOC_REG_FLAG_ABOVE_64_BITS,
  43138         0,
  43139         1,
  43140         soc_OCB_INDIRECT_READ_DATA_1_BCM88650_B0r_fields,
  43141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43142         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43143         -1,
  43144         -1,
  43145     },
  43146 #endif /* chips */
  43147 
  43148 #if defined(BCM_88660_A0)
  43149     { /* SOC_REG_INT_OCB_INDIRECT_READ_DATA_1_BCM88660_A0r */
  43150         soc_block_list[51],
  43151         soc_genreg,
  43152         1,
  43153         0,
  43154         0x140,
  43155         SOC_REG_FLAG_ABOVE_64_BITS,
  43156         0,
  43157         1,
  43158         soc_OCB_INDIRECT_READ_DATA_1_BCM88660_A0r_fields,
  43159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43161         -1,
  43162         -1,
  43163     },
  43164 #endif /* chips */
  43165 
  43166 #if defined(BCM_88650_A0)
  43167     { /* SOC_REG_INT_OCB_INDIRECT_WRITE_DATA_0r */
  43168         soc_block_list[51],
  43169         soc_genreg,
  43170         1,
  43171         0,
  43172         0x110,
  43173         SOC_REG_FLAG_ABOVE_64_BITS,
  43174         0,
  43175         1,
  43176         soc_OCB_INDIRECT_WRITE_DATA_0r_fields,
  43177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43178         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43179         -1,
  43180         -1,
  43181     },
  43182 #endif /* chips */
  43183 
  43184 #if defined(BCM_88650_A0)
  43185     { /* SOC_REG_INT_OCB_INDIRECT_WRITE_DATA_1r */
  43186         soc_block_list[51],
  43187         soc_genreg,
  43188         1,
  43189         0,
  43190         0x120,
  43191         SOC_REG_FLAG_ABOVE_64_BITS,
  43192         0,
  43193         1,
  43194         soc_OCB_INDIRECT_WRITE_DATA_1r_fields,
  43195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43196         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43197         -1,
  43198         -1,
  43199     },
  43200 #endif /* chips */
  43201 
  43202 #if defined(BCM_88202_A0)
  43203     { /* SOC_REG_INT_OCB_INDIRECT_WRITE_DATA_0_BCM88202_A0r */
  43204         soc_block_list[51],
  43205         soc_genreg,
  43206         1,
  43207         0,
  43208         0x110,
  43209         SOC_REG_FLAG_ABOVE_64_BITS,
  43210         0,
  43211         1,
  43212         soc_OCB_INDIRECT_WRITE_DATA_0_BCM88202_A0r_fields,
  43213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43214         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43215         -1,
  43216         -1,
  43217     },
  43218 #endif /* chips */
  43219 
  43220 #if defined(BCM_88650_B0)
  43221     { /* SOC_REG_INT_OCB_INDIRECT_WRITE_DATA_0_BCM88650_B0r */
  43222         soc_block_list[51],
  43223         soc_genreg,
  43224         1,
  43225         0,
  43226         0x110,
  43227         SOC_REG_FLAG_ABOVE_64_BITS,
  43228         0,
  43229         1,
  43230         soc_OCB_INDIRECT_WRITE_DATA_0_BCM88650_B0r_fields,
  43231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43233         -1,
  43234         -1,
  43235     },
  43236 #endif /* chips */
  43237 
  43238 #if defined(BCM_88660_A0)
  43239     { /* SOC_REG_INT_OCB_INDIRECT_WRITE_DATA_0_BCM88660_A0r */
  43240         soc_block_list[51],
  43241         soc_genreg,
  43242         1,
  43243         0,
  43244         0x110,
  43245         SOC_REG_FLAG_ABOVE_64_BITS,
  43246         0,
  43247         1,
  43248         soc_OCB_INDIRECT_WRITE_DATA_0_BCM88660_A0r_fields,
  43249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43250         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43251         -1,
  43252         -1,
  43253     },
  43254 #endif /* chips */
  43255 
  43256 #if defined(BCM_88202_A0)
  43257     { /* SOC_REG_INT_OCB_INDIRECT_WRITE_DATA_1_BCM88202_A0r */
  43258         soc_block_list[51],
  43259         soc_genreg,
  43260         1,
  43261         0,
  43262         0x120,
  43263         SOC_REG_FLAG_ABOVE_64_BITS,
  43264         0,
  43265         1,
  43266         soc_OCB_INDIRECT_WRITE_DATA_1_BCM88202_A0r_fields,
  43267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43268         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43269         -1,
  43270         -1,
  43271     },
  43272 #endif /* chips */
  43273 
  43274 #if defined(BCM_88650_B0)
  43275     { /* SOC_REG_INT_OCB_INDIRECT_WRITE_DATA_1_BCM88650_B0r */
  43276         soc_block_list[51],
  43277         soc_genreg,
  43278         1,
  43279         0,
  43280         0x120,
  43281         SOC_REG_FLAG_ABOVE_64_BITS,
  43282         0,
  43283         1,
  43284         soc_OCB_INDIRECT_WRITE_DATA_1_BCM88650_B0r_fields,
  43285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43286         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43287         -1,
  43288         -1,
  43289     },
  43290 #endif /* chips */
  43291 
  43292 #if defined(BCM_88660_A0)
  43293     { /* SOC_REG_INT_OCB_INDIRECT_WRITE_DATA_1_BCM88660_A0r */
  43294         soc_block_list[51],
  43295         soc_genreg,
  43296         1,
  43297         0,
  43298         0x120,
  43299         SOC_REG_FLAG_ABOVE_64_BITS,
  43300         0,
  43301         1,
  43302         soc_OCB_INDIRECT_WRITE_DATA_1_BCM88660_A0r_fields,
  43303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43304         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43305         -1,
  43306         -1,
  43307     },
  43308 #endif /* chips */
  43309 
  43310 #if defined(BCM_88202_A0)
  43311     { /* SOC_REG_INT_OCB_INTERRUPT_MASK_REGISTERr */
  43312         soc_block_list[51],
  43313         soc_genreg,
  43314         1,
  43315         0,
  43316         0x10,
  43317         SOC_REG_FLAG_SIGNAL,
  43318         0,
  43319         1,
  43320         soc_OCB_INTERRUPT_MASK_REGISTERr_fields,
  43321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43322         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43323         -1,
  43324         -1,
  43325     },
  43326 #endif /* chips */
  43327 
  43328 #if defined(BCM_88375_A0)
  43329     { /* SOC_REG_INT_OCB_INTERRUPT_MASK_REGISTER_BCM88375_A0r */
  43330         soc_block_list[51],
  43331         soc_genreg,
  43332         1,
  43333         0,
  43334         0x10,
  43335         0,
  43336         0,
  43337         6,
  43338         soc_OCB_INTERRUPT_MASK_REGISTER_BCM88375_A0r_fields,
  43339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43340         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43341         -1,
  43342         -1,
  43343     },
  43344 #endif /* chips */
  43345 
  43346 #if defined(BCM_88375_B0)
  43347     { /* SOC_REG_INT_OCB_INTERRUPT_MASK_REGISTER_BCM88375_B0r */
  43348         soc_block_list[51],
  43349         soc_genreg,
  43350         1,
  43351         0,
  43352         0x10,
  43353         0,
  43354         0,
  43355         6,
  43356         soc_OCB_INTERRUPT_MASK_REGISTER_BCM88375_B0r_fields,
  43357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43358         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43359         -1,
  43360         -1,
  43361     },
  43362 #endif /* chips */
  43363 
  43364 #if defined(BCM_88675_A0)
  43365     { /* SOC_REG_INT_OCB_INTERRUPT_MASK_REGISTER_BCM88675_A0r */
  43366         soc_block_list[51],
  43367         soc_genreg,
  43368         1,
  43369         0,
  43370         0x10,
  43371         0,
  43372         0,
  43373         6,
  43374         soc_OCB_INTERRUPT_MASK_REGISTER_BCM88675_A0r_fields,
  43375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43376         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43377         -1,
  43378         -1,
  43379     },
  43380 #endif /* chips */
  43381 
  43382 #if defined(BCM_88675_B0)
  43383     { /* SOC_REG_INT_OCB_INTERRUPT_MASK_REGISTER_BCM88675_B0r */
  43384         soc_block_list[51],
  43385         soc_genreg,
  43386         1,
  43387         0,
  43388         0x10,
  43389         0,
  43390         0,
  43391         6,
  43392         soc_OCB_INTERRUPT_MASK_REGISTER_BCM88675_B0r_fields,
  43393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43394         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43395         -1,
  43396         -1,
  43397     },
  43398 #endif /* chips */
  43399 
  43400 #if defined(BCM_88680_A0)
  43401     { /* SOC_REG_INT_OCB_INTERRUPT_MASK_REGISTER_BCM88680_A0r */
  43402         soc_block_list[51],
  43403         soc_genreg,
  43404         1,
  43405         0,
  43406         0x10,
  43407         0,
  43408         0,
  43409         6,
  43410         soc_OCB_INTERRUPT_MASK_REGISTER_BCM88680_A0r_fields,
  43411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43412         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43413         -1,
  43414         -1,
  43415     },
  43416 #endif /* chips */
  43417 
  43418 #if defined(BCM_88690_A0)
  43419     { /* SOC_REG_INT_OCB_INTERRUPT_MASK_REGISTER_BCM88690_A0r */
  43420         soc_block_list[51],
  43421         soc_genreg,
  43422         1,
  43423         0,
  43424         0x10,
  43425         0,
  43426         0,
  43427         3,
  43428         soc_OCB_INTERRUPT_MASK_REGISTER_BCM88690_A0r_fields,
  43429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43430         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43431         -1,
  43432         -1,
  43433     },
  43434 #endif /* chips */
  43435 
  43436 #if defined(BCM_88690_B0)
  43437     { /* SOC_REG_INT_OCB_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  43438         soc_block_list[51],
  43439         soc_genreg,
  43440         1,
  43441         0,
  43442         0x10,
  43443         0,
  43444         0,
  43445         3,
  43446         soc_OCB_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  43447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43448         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43449         -1,
  43450         -1,
  43451     },
  43452 #endif /* chips */
  43453 
  43454 #if defined(BCM_88202_A0)
  43455     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTERr */
  43456         soc_block_list[51],
  43457         soc_genreg,
  43458         1,
  43459         0,
  43460         0,
  43461         SOC_REG_FLAG_INTERRUPT,
  43462         0,
  43463         1,
  43464         soc_OCB_INTERRUPT_REGISTERr_fields,
  43465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43466         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43467         -1,
  43468         -1,
  43469     },
  43470 #endif /* chips */
  43471 
  43472 #if defined(BCM_88375_A0)
  43473     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_BCM88375_A0r */
  43474         soc_block_list[51],
  43475         soc_genreg,
  43476         1,
  43477         0,
  43478         0,
  43479         SOC_REG_FLAG_INTERRUPT,
  43480         0,
  43481         6,
  43482         soc_OCB_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  43483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43484         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43485         -1,
  43486         -1,
  43487     },
  43488 #endif /* chips */
  43489 
  43490 #if defined(BCM_88375_B0)
  43491     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_BCM88375_B0r */
  43492         soc_block_list[51],
  43493         soc_genreg,
  43494         1,
  43495         0,
  43496         0,
  43497         SOC_REG_FLAG_INTERRUPT,
  43498         0,
  43499         6,
  43500         soc_OCB_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  43501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43502         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43503         -1,
  43504         -1,
  43505     },
  43506 #endif /* chips */
  43507 
  43508 #if defined(BCM_88675_A0)
  43509     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_BCM88675_A0r */
  43510         soc_block_list[51],
  43511         soc_genreg,
  43512         1,
  43513         0,
  43514         0,
  43515         SOC_REG_FLAG_INTERRUPT,
  43516         0,
  43517         6,
  43518         soc_OCB_INTERRUPT_REGISTER_BCM88675_A0r_fields,
  43519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43520         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43521         -1,
  43522         -1,
  43523     },
  43524 #endif /* chips */
  43525 
  43526 #if defined(BCM_88675_B0)
  43527     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_BCM88675_B0r */
  43528         soc_block_list[51],
  43529         soc_genreg,
  43530         1,
  43531         0,
  43532         0,
  43533         SOC_REG_FLAG_INTERRUPT,
  43534         0,
  43535         6,
  43536         soc_OCB_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  43537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43538         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43539         -1,
  43540         -1,
  43541     },
  43542 #endif /* chips */
  43543 
  43544 #if defined(BCM_88680_A0)
  43545     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_BCM88680_A0r */
  43546         soc_block_list[51],
  43547         soc_genreg,
  43548         1,
  43549         0,
  43550         0,
  43551         SOC_REG_FLAG_INTERRUPT,
  43552         0,
  43553         6,
  43554         soc_OCB_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  43555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43556         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43557         -1,
  43558         -1,
  43559     },
  43560 #endif /* chips */
  43561 
  43562 #if defined(BCM_88690_A0)
  43563     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_BCM88690_A0r */
  43564         soc_block_list[51],
  43565         soc_genreg,
  43566         1,
  43567         0,
  43568         0,
  43569         SOC_REG_FLAG_INTERRUPT |
  43570                           SOC_REG_FLAG_SIGNAL,
  43571         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  43572         3,
  43573         soc_OCB_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  43574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43575         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43576         -1,
  43577         -1,
  43578     },
  43579 #endif /* chips */
  43580 
  43581 #if defined(BCM_88690_B0)
  43582     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_BCM88690_B0r */
  43583         soc_block_list[51],
  43584         soc_genreg,
  43585         1,
  43586         0,
  43587         0,
  43588         SOC_REG_FLAG_INTERRUPT |
  43589                           SOC_REG_FLAG_SIGNAL,
  43590         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  43591         3,
  43592         soc_OCB_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  43593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43594         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43595         -1,
  43596         -1,
  43597     },
  43598 #endif /* chips */
  43599 
  43600 #if defined(BCM_88202_A0)
  43601     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_TESTr */
  43602         soc_block_list[51],
  43603         soc_genreg,
  43604         1,
  43605         0,
  43606         0x18,
  43607         SOC_REG_FLAG_INTERRUPT |
  43608                           SOC_REG_FLAG_SIGNAL,
  43609         0,
  43610         1,
  43611         soc_OCB_INTERRUPT_REGISTER_TESTr_fields,
  43612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43613         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43614         -1,
  43615         -1,
  43616     },
  43617 #endif /* chips */
  43618 
  43619 #if defined(BCM_88375_A0)
  43620     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  43621         soc_block_list[51],
  43622         soc_genreg,
  43623         1,
  43624         0,
  43625         0x18,
  43626         0,
  43627         0,
  43628         1,
  43629         soc_OCB_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  43630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43631         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43632         -1,
  43633         -1,
  43634     },
  43635 #endif /* chips */
  43636 
  43637 #if defined(BCM_88375_B0)
  43638     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  43639         soc_block_list[51],
  43640         soc_genreg,
  43641         1,
  43642         0,
  43643         0x18,
  43644         0,
  43645         0,
  43646         1,
  43647         soc_OCB_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  43648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43649         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43650         -1,
  43651         -1,
  43652     },
  43653 #endif /* chips */
  43654 
  43655 #if defined(BCM_88675_A0)
  43656     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_TEST_BCM88675_A0r */
  43657         soc_block_list[51],
  43658         soc_genreg,
  43659         1,
  43660         0,
  43661         0x18,
  43662         0,
  43663         0,
  43664         1,
  43665         soc_OCB_INTERRUPT_REGISTER_TEST_BCM88675_A0r_fields,
  43666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43667         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43668         -1,
  43669         -1,
  43670     },
  43671 #endif /* chips */
  43672 
  43673 #if defined(BCM_88675_B0)
  43674     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  43675         soc_block_list[51],
  43676         soc_genreg,
  43677         1,
  43678         0,
  43679         0x18,
  43680         0,
  43681         0,
  43682         1,
  43683         soc_OCB_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  43684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43685         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43686         -1,
  43687         -1,
  43688     },
  43689 #endif /* chips */
  43690 
  43691 #if defined(BCM_88680_A0)
  43692     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  43693         soc_block_list[51],
  43694         soc_genreg,
  43695         1,
  43696         0,
  43697         0x18,
  43698         0,
  43699         0,
  43700         1,
  43701         soc_OCB_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  43702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43703         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43704         -1,
  43705         -1,
  43706     },
  43707 #endif /* chips */
  43708 
  43709 #if defined(BCM_88690_A0)
  43710     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  43711         soc_block_list[51],
  43712         soc_genreg,
  43713         1,
  43714         0,
  43715         0x18,
  43716         0,
  43717         0,
  43718         1,
  43719         soc_OCB_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  43720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43721         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43722         -1,
  43723         -1,
  43724     },
  43725 #endif /* chips */
  43726 
  43727 #if defined(BCM_88690_B0)
  43728     { /* SOC_REG_INT_OCB_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  43729         soc_block_list[51],
  43730         soc_genreg,
  43731         1,
  43732         0,
  43733         0x18,
  43734         0,
  43735         0,
  43736         1,
  43737         soc_OCB_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  43738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43739         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43740         -1,
  43741         -1,
  43742     },
  43743 #endif /* chips */
  43744 
  43745 #if defined(BCM_88675_A0)
  43746     { /* SOC_REG_INT_OCB_LAST_RD_ADDRr */
  43747         soc_block_list[51],
  43748         soc_genreg,
  43749         1,
  43750         0,
  43751         0x26c,
  43752         SOC_REG_FLAG_RO |
  43753                           SOC_REG_FLAG_SIGNAL,
  43754         0,
  43755         1,
  43756         soc_OCB_LAST_RD_ADDRr_fields,
  43757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43758         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  43759         -1,
  43760         -1,
  43761     },
  43762 #endif /* chips */
  43763 
  43764 #if defined(BCM_88375_A0)
  43765     { /* SOC_REG_INT_OCB_LAST_RD_ADDR_BCM88375_A0r */
  43766         soc_block_list[51],
  43767         soc_genreg,
  43768         1,
  43769         0,
  43770         0x26c,
  43771         SOC_REG_FLAG_RO |
  43772                           SOC_REG_FLAG_SIGNAL,
  43773         0,
  43774         1,
  43775         soc_OCB_LAST_RD_ADDR_BCM88375_A0r_fields,
  43776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43777         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  43778         -1,
  43779         -1,
  43780     },
  43781 #endif /* chips */
  43782 
  43783 #if defined(BCM_88375_B0)
  43784     { /* SOC_REG_INT_OCB_LAST_RD_ADDR_BCM88375_B0r */
  43785         soc_block_list[51],
  43786         soc_genreg,
  43787         1,
  43788         0,
  43789         0x26c,
  43790         SOC_REG_FLAG_RO |
  43791                           SOC_REG_FLAG_SIGNAL,
  43792         0,
  43793         1,
  43794         soc_OCB_LAST_RD_ADDR_BCM88375_B0r_fields,
  43795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43796         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  43797         -1,
  43798         -1,
  43799     },
  43800 #endif /* chips */
  43801 
  43802 #if defined(BCM_88675_B0)
  43803     { /* SOC_REG_INT_OCB_LAST_RD_ADDR_BCM88675_B0r */
  43804         soc_block_list[51],
  43805         soc_genreg,
  43806         1,
  43807         0,
  43808         0x26c,
  43809         SOC_REG_FLAG_RO |
  43810                           SOC_REG_FLAG_SIGNAL,
  43811         0,
  43812         1,
  43813         soc_OCB_LAST_RD_ADDR_BCM88675_B0r_fields,
  43814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43815         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  43816         -1,
  43817         -1,
  43818     },
  43819 #endif /* chips */
  43820 
  43821 #if defined(BCM_88680_A0)
  43822     { /* SOC_REG_INT_OCB_LAST_RD_ADDR_BCM88680_A0r */
  43823         soc_block_list[51],
  43824         soc_genreg,
  43825         1,
  43826         0,
  43827         0x26c,
  43828         SOC_REG_FLAG_RO |
  43829                           SOC_REG_FLAG_SIGNAL,
  43830         0,
  43831         1,
  43832         soc_OCB_LAST_RD_ADDR_BCM88680_A0r_fields,
  43833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43834         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  43835         -1,
  43836         -1,
  43837     },
  43838 #endif /* chips */
  43839 
  43840 #if defined(BCM_88675_A0)
  43841     { /* SOC_REG_INT_OCB_LAST_RD_BANKr */
  43842         soc_block_list[51],
  43843         soc_genreg,
  43844         1,
  43845         0,
  43846         0x26d,
  43847         SOC_REG_FLAG_RO |
  43848                           SOC_REG_FLAG_SIGNAL,
  43849         0,
  43850         1,
  43851         soc_OCB_LAST_RD_BANKr_fields,
  43852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43853         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  43854         -1,
  43855         -1,
  43856     },
  43857 #endif /* chips */
  43858 
  43859 #if defined(BCM_88375_A0)
  43860     { /* SOC_REG_INT_OCB_LAST_RD_BANK_BCM88375_A0r */
  43861         soc_block_list[51],
  43862         soc_genreg,
  43863         1,
  43864         0,
  43865         0x26d,
  43866         SOC_REG_FLAG_RO |
  43867                           SOC_REG_FLAG_SIGNAL,
  43868         0,
  43869         1,
  43870         soc_OCB_LAST_RD_BANK_BCM88375_A0r_fields,
  43871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43872         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  43873         -1,
  43874         -1,
  43875     },
  43876 #endif /* chips */
  43877 
  43878 #if defined(BCM_88375_B0)
  43879     { /* SOC_REG_INT_OCB_LAST_RD_BANK_BCM88375_B0r */
  43880         soc_block_list[51],
  43881         soc_genreg,
  43882         1,
  43883         0,
  43884         0x26d,
  43885         SOC_REG_FLAG_RO |
  43886                           SOC_REG_FLAG_SIGNAL,
  43887         0,
  43888         1,
  43889         soc_OCB_LAST_RD_BANK_BCM88375_B0r_fields,
  43890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43891         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  43892         -1,
  43893         -1,
  43894     },
  43895 #endif /* chips */
  43896 
  43897 #if defined(BCM_88675_B0)
  43898     { /* SOC_REG_INT_OCB_LAST_RD_BANK_BCM88675_B0r */
  43899         soc_block_list[51],
  43900         soc_genreg,
  43901         1,
  43902         0,
  43903         0x26d,
  43904         SOC_REG_FLAG_RO |
  43905                           SOC_REG_FLAG_SIGNAL,
  43906         0,
  43907         1,
  43908         soc_OCB_LAST_RD_BANK_BCM88675_B0r_fields,
  43909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43910         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  43911         -1,
  43912         -1,
  43913     },
  43914 #endif /* chips */
  43915 
  43916 #if defined(BCM_88680_A0)
  43917     { /* SOC_REG_INT_OCB_LAST_RD_BANK_BCM88680_A0r */
  43918         soc_block_list[51],
  43919         soc_genreg,
  43920         1,
  43921         0,
  43922         0x26d,
  43923         SOC_REG_FLAG_RO |
  43924                           SOC_REG_FLAG_SIGNAL,
  43925         0,
  43926         1,
  43927         soc_OCB_LAST_RD_BANK_BCM88680_A0r_fields,
  43928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43929         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  43930         -1,
  43931         -1,
  43932     },
  43933 #endif /* chips */
  43934 
  43935 #if defined(BCM_88675_A0)
  43936     { /* SOC_REG_INT_OCB_LAST_RD_DBUFF_POINTERr */
  43937         soc_block_list[51],
  43938         soc_genreg,
  43939         1,
  43940         0,
  43941         0x26a,
  43942         SOC_REG_FLAG_RO |
  43943                           SOC_REG_FLAG_SIGNAL,
  43944         0,
  43945         1,
  43946         soc_OCB_LAST_RD_DBUFF_POINTERr_fields,
  43947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43948         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  43949         -1,
  43950         -1,
  43951     },
  43952 #endif /* chips */
  43953 
  43954 #if defined(BCM_88375_A0)
  43955     { /* SOC_REG_INT_OCB_LAST_RD_DBUFF_POINTER_BCM88375_A0r */
  43956         soc_block_list[51],
  43957         soc_genreg,
  43958         1,
  43959         0,
  43960         0x26a,
  43961         SOC_REG_FLAG_RO |
  43962                           SOC_REG_FLAG_SIGNAL,
  43963         0,
  43964         1,
  43965         soc_OCB_LAST_RD_DBUFF_POINTER_BCM88375_A0r_fields,
  43966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43967         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  43968         -1,
  43969         -1,
  43970     },
  43971 #endif /* chips */
  43972 
  43973 #if defined(BCM_88375_B0)
  43974     { /* SOC_REG_INT_OCB_LAST_RD_DBUFF_POINTER_BCM88375_B0r */
  43975         soc_block_list[51],
  43976         soc_genreg,
  43977         1,
  43978         0,
  43979         0x26a,
  43980         SOC_REG_FLAG_RO |
  43981                           SOC_REG_FLAG_SIGNAL,
  43982         0,
  43983         1,
  43984         soc_OCB_LAST_RD_DBUFF_POINTER_BCM88375_B0r_fields,
  43985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43986         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  43987         -1,
  43988         -1,
  43989     },
  43990 #endif /* chips */
  43991 
  43992 #if defined(BCM_88675_B0)
  43993     { /* SOC_REG_INT_OCB_LAST_RD_DBUFF_POINTER_BCM88675_B0r */
  43994         soc_block_list[51],
  43995         soc_genreg,
  43996         1,
  43997         0,
  43998         0x26a,
  43999         SOC_REG_FLAG_RO |
  44000                           SOC_REG_FLAG_SIGNAL,
  44001         0,
  44002         1,
  44003         soc_OCB_LAST_RD_DBUFF_POINTER_BCM88675_B0r_fields,
  44004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44005         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  44006         -1,
  44007         -1,
  44008     },
  44009 #endif /* chips */
  44010 
  44011 #if defined(BCM_88680_A0)
  44012     { /* SOC_REG_INT_OCB_LAST_RD_DBUFF_POINTER_BCM88680_A0r */
  44013         soc_block_list[51],
  44014         soc_genreg,
  44015         1,
  44016         0,
  44017         0x26a,
  44018         SOC_REG_FLAG_RO |
  44019                           SOC_REG_FLAG_SIGNAL,
  44020         0,
  44021         1,
  44022         soc_OCB_LAST_RD_DBUFF_POINTER_BCM88680_A0r_fields,
  44023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44024         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  44025         -1,
  44026         -1,
  44027     },
  44028 #endif /* chips */
  44029 
  44030 #if defined(BCM_88675_A0)
  44031     { /* SOC_REG_INT_OCB_LAST_RD_OFFSETr */
  44032         soc_block_list[51],
  44033         soc_genreg,
  44034         1,
  44035         0,
  44036         0x26b,
  44037         SOC_REG_FLAG_RO |
  44038                           SOC_REG_FLAG_SIGNAL,
  44039         0,
  44040         1,
  44041         soc_OCB_LAST_RD_OFFSETr_fields,
  44042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44043         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44044         -1,
  44045         -1,
  44046     },
  44047 #endif /* chips */
  44048 
  44049 #if defined(BCM_88375_A0)
  44050     { /* SOC_REG_INT_OCB_LAST_RD_OFFSET_BCM88375_A0r */
  44051         soc_block_list[51],
  44052         soc_genreg,
  44053         1,
  44054         0,
  44055         0x26b,
  44056         SOC_REG_FLAG_RO |
  44057                           SOC_REG_FLAG_SIGNAL,
  44058         0,
  44059         1,
  44060         soc_OCB_LAST_RD_OFFSET_BCM88375_A0r_fields,
  44061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44062         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44063         -1,
  44064         -1,
  44065     },
  44066 #endif /* chips */
  44067 
  44068 #if defined(BCM_88375_B0)
  44069     { /* SOC_REG_INT_OCB_LAST_RD_OFFSET_BCM88375_B0r */
  44070         soc_block_list[51],
  44071         soc_genreg,
  44072         1,
  44073         0,
  44074         0x26b,
  44075         SOC_REG_FLAG_RO |
  44076                           SOC_REG_FLAG_SIGNAL,
  44077         0,
  44078         1,
  44079         soc_OCB_LAST_RD_OFFSET_BCM88375_B0r_fields,
  44080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44081         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44082         -1,
  44083         -1,
  44084     },
  44085 #endif /* chips */
  44086 
  44087 #if defined(BCM_88675_B0)
  44088     { /* SOC_REG_INT_OCB_LAST_RD_OFFSET_BCM88675_B0r */
  44089         soc_block_list[51],
  44090         soc_genreg,
  44091         1,
  44092         0,
  44093         0x26b,
  44094         SOC_REG_FLAG_RO |
  44095                           SOC_REG_FLAG_SIGNAL,
  44096         0,
  44097         1,
  44098         soc_OCB_LAST_RD_OFFSET_BCM88675_B0r_fields,
  44099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44100         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44101         -1,
  44102         -1,
  44103     },
  44104 #endif /* chips */
  44105 
  44106 #if defined(BCM_88680_A0)
  44107     { /* SOC_REG_INT_OCB_LAST_RD_OFFSET_BCM88680_A0r */
  44108         soc_block_list[51],
  44109         soc_genreg,
  44110         1,
  44111         0,
  44112         0x26b,
  44113         SOC_REG_FLAG_RO |
  44114                           SOC_REG_FLAG_SIGNAL,
  44115         0,
  44116         1,
  44117         soc_OCB_LAST_RD_OFFSET_BCM88680_A0r_fields,
  44118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44119         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44120         -1,
  44121         -1,
  44122     },
  44123 #endif /* chips */
  44124 
  44125 #if defined(BCM_88675_A0)
  44126     { /* SOC_REG_INT_OCB_LAST_WR_ADDRr */
  44127         soc_block_list[51],
  44128         soc_genreg,
  44129         1,
  44130         0,
  44131         0x268,
  44132         SOC_REG_FLAG_RO |
  44133                           SOC_REG_FLAG_SIGNAL,
  44134         0,
  44135         1,
  44136         soc_OCB_LAST_WR_ADDRr_fields,
  44137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44138         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  44139         -1,
  44140         -1,
  44141     },
  44142 #endif /* chips */
  44143 
  44144 #if defined(BCM_88375_A0)
  44145     { /* SOC_REG_INT_OCB_LAST_WR_ADDR_BCM88375_A0r */
  44146         soc_block_list[51],
  44147         soc_genreg,
  44148         1,
  44149         0,
  44150         0x268,
  44151         SOC_REG_FLAG_RO |
  44152                           SOC_REG_FLAG_SIGNAL,
  44153         0,
  44154         1,
  44155         soc_OCB_LAST_WR_ADDR_BCM88375_A0r_fields,
  44156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44157         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  44158         -1,
  44159         -1,
  44160     },
  44161 #endif /* chips */
  44162 
  44163 #if defined(BCM_88375_B0)
  44164     { /* SOC_REG_INT_OCB_LAST_WR_ADDR_BCM88375_B0r */
  44165         soc_block_list[51],
  44166         soc_genreg,
  44167         1,
  44168         0,
  44169         0x268,
  44170         SOC_REG_FLAG_RO |
  44171                           SOC_REG_FLAG_SIGNAL,
  44172         0,
  44173         1,
  44174         soc_OCB_LAST_WR_ADDR_BCM88375_B0r_fields,
  44175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44176         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  44177         -1,
  44178         -1,
  44179     },
  44180 #endif /* chips */
  44181 
  44182 #if defined(BCM_88675_B0)
  44183     { /* SOC_REG_INT_OCB_LAST_WR_ADDR_BCM88675_B0r */
  44184         soc_block_list[51],
  44185         soc_genreg,
  44186         1,
  44187         0,
  44188         0x268,
  44189         SOC_REG_FLAG_RO |
  44190                           SOC_REG_FLAG_SIGNAL,
  44191         0,
  44192         1,
  44193         soc_OCB_LAST_WR_ADDR_BCM88675_B0r_fields,
  44194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44195         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  44196         -1,
  44197         -1,
  44198     },
  44199 #endif /* chips */
  44200 
  44201 #if defined(BCM_88680_A0)
  44202     { /* SOC_REG_INT_OCB_LAST_WR_ADDR_BCM88680_A0r */
  44203         soc_block_list[51],
  44204         soc_genreg,
  44205         1,
  44206         0,
  44207         0x268,
  44208         SOC_REG_FLAG_RO |
  44209                           SOC_REG_FLAG_SIGNAL,
  44210         0,
  44211         1,
  44212         soc_OCB_LAST_WR_ADDR_BCM88680_A0r_fields,
  44213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44214         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  44215         -1,
  44216         -1,
  44217     },
  44218 #endif /* chips */
  44219 
  44220 #if defined(BCM_88675_A0)
  44221     { /* SOC_REG_INT_OCB_LAST_WR_BANKr */
  44222         soc_block_list[51],
  44223         soc_genreg,
  44224         1,
  44225         0,
  44226         0x269,
  44227         SOC_REG_FLAG_RO |
  44228                           SOC_REG_FLAG_SIGNAL,
  44229         0,
  44230         1,
  44231         soc_OCB_LAST_WR_BANKr_fields,
  44232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44233         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44234         -1,
  44235         -1,
  44236     },
  44237 #endif /* chips */
  44238 
  44239 #if defined(BCM_88375_A0)
  44240     { /* SOC_REG_INT_OCB_LAST_WR_BANK_BCM88375_A0r */
  44241         soc_block_list[51],
  44242         soc_genreg,
  44243         1,
  44244         0,
  44245         0x269,
  44246         SOC_REG_FLAG_RO |
  44247                           SOC_REG_FLAG_SIGNAL,
  44248         0,
  44249         1,
  44250         soc_OCB_LAST_WR_BANK_BCM88375_A0r_fields,
  44251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44252         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44253         -1,
  44254         -1,
  44255     },
  44256 #endif /* chips */
  44257 
  44258 #if defined(BCM_88375_B0)
  44259     { /* SOC_REG_INT_OCB_LAST_WR_BANK_BCM88375_B0r */
  44260         soc_block_list[51],
  44261         soc_genreg,
  44262         1,
  44263         0,
  44264         0x269,
  44265         SOC_REG_FLAG_RO |
  44266                           SOC_REG_FLAG_SIGNAL,
  44267         0,
  44268         1,
  44269         soc_OCB_LAST_WR_BANK_BCM88375_B0r_fields,
  44270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44271         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44272         -1,
  44273         -1,
  44274     },
  44275 #endif /* chips */
  44276 
  44277 #if defined(BCM_88675_B0)
  44278     { /* SOC_REG_INT_OCB_LAST_WR_BANK_BCM88675_B0r */
  44279         soc_block_list[51],
  44280         soc_genreg,
  44281         1,
  44282         0,
  44283         0x269,
  44284         SOC_REG_FLAG_RO |
  44285                           SOC_REG_FLAG_SIGNAL,
  44286         0,
  44287         1,
  44288         soc_OCB_LAST_WR_BANK_BCM88675_B0r_fields,
  44289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44290         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44291         -1,
  44292         -1,
  44293     },
  44294 #endif /* chips */
  44295 
  44296 #if defined(BCM_88680_A0)
  44297     { /* SOC_REG_INT_OCB_LAST_WR_BANK_BCM88680_A0r */
  44298         soc_block_list[51],
  44299         soc_genreg,
  44300         1,
  44301         0,
  44302         0x269,
  44303         SOC_REG_FLAG_RO |
  44304                           SOC_REG_FLAG_SIGNAL,
  44305         0,
  44306         1,
  44307         soc_OCB_LAST_WR_BANK_BCM88680_A0r_fields,
  44308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44309         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44310         -1,
  44311         -1,
  44312     },
  44313 #endif /* chips */
  44314 
  44315 #if defined(BCM_88675_A0)
  44316     { /* SOC_REG_INT_OCB_LAST_WR_DBUFF_POINTERr */
  44317         soc_block_list[51],
  44318         soc_genreg,
  44319         1,
  44320         0,
  44321         0x266,
  44322         SOC_REG_FLAG_RO |
  44323                           SOC_REG_FLAG_SIGNAL,
  44324         0,
  44325         1,
  44326         soc_OCB_LAST_WR_DBUFF_POINTERr_fields,
  44327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44328         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  44329         -1,
  44330         -1,
  44331     },
  44332 #endif /* chips */
  44333 
  44334 #if defined(BCM_88375_A0)
  44335     { /* SOC_REG_INT_OCB_LAST_WR_DBUFF_POINTER_BCM88375_A0r */
  44336         soc_block_list[51],
  44337         soc_genreg,
  44338         1,
  44339         0,
  44340         0x266,
  44341         SOC_REG_FLAG_RO |
  44342                           SOC_REG_FLAG_SIGNAL,
  44343         0,
  44344         1,
  44345         soc_OCB_LAST_WR_DBUFF_POINTER_BCM88375_A0r_fields,
  44346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44347         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  44348         -1,
  44349         -1,
  44350     },
  44351 #endif /* chips */
  44352 
  44353 #if defined(BCM_88375_B0)
  44354     { /* SOC_REG_INT_OCB_LAST_WR_DBUFF_POINTER_BCM88375_B0r */
  44355         soc_block_list[51],
  44356         soc_genreg,
  44357         1,
  44358         0,
  44359         0x266,
  44360         SOC_REG_FLAG_RO |
  44361                           SOC_REG_FLAG_SIGNAL,
  44362         0,
  44363         1,
  44364         soc_OCB_LAST_WR_DBUFF_POINTER_BCM88375_B0r_fields,
  44365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44366         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  44367         -1,
  44368         -1,
  44369     },
  44370 #endif /* chips */
  44371 
  44372 #if defined(BCM_88675_B0)
  44373     { /* SOC_REG_INT_OCB_LAST_WR_DBUFF_POINTER_BCM88675_B0r */
  44374         soc_block_list[51],
  44375         soc_genreg,
  44376         1,
  44377         0,
  44378         0x266,
  44379         SOC_REG_FLAG_RO |
  44380                           SOC_REG_FLAG_SIGNAL,
  44381         0,
  44382         1,
  44383         soc_OCB_LAST_WR_DBUFF_POINTER_BCM88675_B0r_fields,
  44384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44385         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  44386         -1,
  44387         -1,
  44388     },
  44389 #endif /* chips */
  44390 
  44391 #if defined(BCM_88680_A0)
  44392     { /* SOC_REG_INT_OCB_LAST_WR_DBUFF_POINTER_BCM88680_A0r */
  44393         soc_block_list[51],
  44394         soc_genreg,
  44395         1,
  44396         0,
  44397         0x266,
  44398         SOC_REG_FLAG_RO |
  44399                           SOC_REG_FLAG_SIGNAL,
  44400         0,
  44401         1,
  44402         soc_OCB_LAST_WR_DBUFF_POINTER_BCM88680_A0r_fields,
  44403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44404         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  44405         -1,
  44406         -1,
  44407     },
  44408 #endif /* chips */
  44409 
  44410 #if defined(BCM_88675_A0)
  44411     { /* SOC_REG_INT_OCB_LAST_WR_OFFSETr */
  44412         soc_block_list[51],
  44413         soc_genreg,
  44414         1,
  44415         0,
  44416         0x267,
  44417         SOC_REG_FLAG_RO |
  44418                           SOC_REG_FLAG_SIGNAL,
  44419         0,
  44420         1,
  44421         soc_OCB_LAST_WR_OFFSETr_fields,
  44422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44423         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44424         -1,
  44425         -1,
  44426     },
  44427 #endif /* chips */
  44428 
  44429 #if defined(BCM_88375_A0)
  44430     { /* SOC_REG_INT_OCB_LAST_WR_OFFSET_BCM88375_A0r */
  44431         soc_block_list[51],
  44432         soc_genreg,
  44433         1,
  44434         0,
  44435         0x267,
  44436         SOC_REG_FLAG_RO |
  44437                           SOC_REG_FLAG_SIGNAL,
  44438         0,
  44439         1,
  44440         soc_OCB_LAST_WR_OFFSET_BCM88375_A0r_fields,
  44441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44442         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44443         -1,
  44444         -1,
  44445     },
  44446 #endif /* chips */
  44447 
  44448 #if defined(BCM_88375_B0)
  44449     { /* SOC_REG_INT_OCB_LAST_WR_OFFSET_BCM88375_B0r */
  44450         soc_block_list[51],
  44451         soc_genreg,
  44452         1,
  44453         0,
  44454         0x267,
  44455         SOC_REG_FLAG_RO |
  44456                           SOC_REG_FLAG_SIGNAL,
  44457         0,
  44458         1,
  44459         soc_OCB_LAST_WR_OFFSET_BCM88375_B0r_fields,
  44460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44461         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44462         -1,
  44463         -1,
  44464     },
  44465 #endif /* chips */
  44466 
  44467 #if defined(BCM_88675_B0)
  44468     { /* SOC_REG_INT_OCB_LAST_WR_OFFSET_BCM88675_B0r */
  44469         soc_block_list[51],
  44470         soc_genreg,
  44471         1,
  44472         0,
  44473         0x267,
  44474         SOC_REG_FLAG_RO |
  44475                           SOC_REG_FLAG_SIGNAL,
  44476         0,
  44477         1,
  44478         soc_OCB_LAST_WR_OFFSET_BCM88675_B0r_fields,
  44479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44480         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44481         -1,
  44482         -1,
  44483     },
  44484 #endif /* chips */
  44485 
  44486 #if defined(BCM_88680_A0)
  44487     { /* SOC_REG_INT_OCB_LAST_WR_OFFSET_BCM88680_A0r */
  44488         soc_block_list[51],
  44489         soc_genreg,
  44490         1,
  44491         0,
  44492         0x267,
  44493         SOC_REG_FLAG_RO |
  44494                           SOC_REG_FLAG_SIGNAL,
  44495         0,
  44496         1,
  44497         soc_OCB_LAST_WR_OFFSET_BCM88680_A0r_fields,
  44498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44499         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  44500         -1,
  44501         -1,
  44502     },
  44503 #endif /* chips */
  44504 
  44505 #if defined(BCM_88675_A0)
  44506     { /* SOC_REG_INT_OCB_MASK_ECC_PER_BANKr */
  44507         soc_block_list[51],
  44508         soc_genreg,
  44509         1,
  44510         0,
  44511         0x26e,
  44512         0,
  44513         0,
  44514         2,
  44515         soc_OCB_MASK_ECC_PER_BANKr_fields,
  44516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44517         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44518         -1,
  44519         -1,
  44520     },
  44521 #endif /* chips */
  44522 
  44523 #if defined(BCM_88375_A0)
  44524     { /* SOC_REG_INT_OCB_MASK_ECC_PER_BANK_BCM88375_A0r */
  44525         soc_block_list[51],
  44526         soc_genreg,
  44527         1,
  44528         0,
  44529         0x26e,
  44530         0,
  44531         0,
  44532         2,
  44533         soc_OCB_MASK_ECC_PER_BANK_BCM88375_A0r_fields,
  44534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44535         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44536         -1,
  44537         -1,
  44538     },
  44539 #endif /* chips */
  44540 
  44541 #if defined(BCM_88375_B0)
  44542     { /* SOC_REG_INT_OCB_MASK_ECC_PER_BANK_BCM88375_B0r */
  44543         soc_block_list[51],
  44544         soc_genreg,
  44545         1,
  44546         0,
  44547         0x26e,
  44548         0,
  44549         0,
  44550         2,
  44551         soc_OCB_MASK_ECC_PER_BANK_BCM88375_B0r_fields,
  44552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44553         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44554         -1,
  44555         -1,
  44556     },
  44557 #endif /* chips */
  44558 
  44559 #if defined(BCM_88675_B0)
  44560     { /* SOC_REG_INT_OCB_MASK_ECC_PER_BANK_BCM88675_B0r */
  44561         soc_block_list[51],
  44562         soc_genreg,
  44563         1,
  44564         0,
  44565         0x26e,
  44566         0,
  44567         0,
  44568         2,
  44569         soc_OCB_MASK_ECC_PER_BANK_BCM88675_B0r_fields,
  44570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44572         -1,
  44573         -1,
  44574     },
  44575 #endif /* chips */
  44576 
  44577 #if defined(BCM_88680_A0)
  44578     { /* SOC_REG_INT_OCB_MASK_ECC_PER_BANK_BCM88680_A0r */
  44579         soc_block_list[51],
  44580         soc_genreg,
  44581         1,
  44582         0,
  44583         0x26e,
  44584         0,
  44585         0,
  44586         2,
  44587         soc_OCB_MASK_ECC_PER_BANK_BCM88680_A0r_fields,
  44588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44589         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44590         -1,
  44591         -1,
  44592     },
  44593 #endif /* chips */
  44594 
  44595 #if defined(BCM_88675_A0)
  44596     { /* SOC_REG_INT_OCB_OCB_BANK_CRC_ERRr */
  44597         soc_block_list[51],
  44598         soc_genreg,
  44599         16,
  44600         0,
  44601         0x205,
  44602         SOC_REG_FLAG_ARRAY |
  44603                           SOC_REG_FLAG_RO |
  44604                           SOC_REG_FLAG_REG_ARRAY |
  44605                           SOC_REG_FLAG_SIGNAL,
  44606         0,
  44607         1,
  44608         soc_OCB_OCB_BANK_CRC_ERRr_fields,
  44609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44610         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44611         -1,
  44612         -1,
  44613     },
  44614 #endif /* chips */
  44615 
  44616 #if defined(BCM_88375_A0)
  44617     { /* SOC_REG_INT_OCB_OCB_BANK_CRC_ERR_BCM88375_A0r */
  44618         soc_block_list[51],
  44619         soc_genreg,
  44620         16,
  44621         0,
  44622         0x205,
  44623         SOC_REG_FLAG_ARRAY |
  44624                           SOC_REG_FLAG_RO |
  44625                           SOC_REG_FLAG_REG_ARRAY |
  44626                           SOC_REG_FLAG_SIGNAL,
  44627         0,
  44628         1,
  44629         soc_OCB_OCB_BANK_CRC_ERR_BCM88375_A0r_fields,
  44630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44631         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44632         -1,
  44633         -1,
  44634     },
  44635 #endif /* chips */
  44636 
  44637 #if defined(BCM_88375_B0)
  44638     { /* SOC_REG_INT_OCB_OCB_BANK_CRC_ERR_BCM88375_B0r */
  44639         soc_block_list[51],
  44640         soc_genreg,
  44641         16,
  44642         0,
  44643         0x205,
  44644         SOC_REG_FLAG_ARRAY |
  44645                           SOC_REG_FLAG_RO |
  44646                           SOC_REG_FLAG_REG_ARRAY |
  44647                           SOC_REG_FLAG_SIGNAL,
  44648         0,
  44649         1,
  44650         soc_OCB_OCB_BANK_CRC_ERR_BCM88375_B0r_fields,
  44651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44652         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44653         -1,
  44654         -1,
  44655     },
  44656 #endif /* chips */
  44657 
  44658 #if defined(BCM_88675_B0)
  44659     { /* SOC_REG_INT_OCB_OCB_BANK_CRC_ERR_BCM88675_B0r */
  44660         soc_block_list[51],
  44661         soc_genreg,
  44662         16,
  44663         0,
  44664         0x205,
  44665         SOC_REG_FLAG_ARRAY |
  44666                           SOC_REG_FLAG_RO |
  44667                           SOC_REG_FLAG_REG_ARRAY |
  44668                           SOC_REG_FLAG_SIGNAL,
  44669         0,
  44670         1,
  44671         soc_OCB_OCB_BANK_CRC_ERR_BCM88675_B0r_fields,
  44672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44673         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44674         -1,
  44675         -1,
  44676     },
  44677 #endif /* chips */
  44678 
  44679 #if defined(BCM_88680_A0)
  44680     { /* SOC_REG_INT_OCB_OCB_BANK_CRC_ERR_BCM88680_A0r */
  44681         soc_block_list[51],
  44682         soc_genreg,
  44683         16,
  44684         0,
  44685         0x205,
  44686         SOC_REG_FLAG_ARRAY |
  44687                           SOC_REG_FLAG_RO |
  44688                           SOC_REG_FLAG_REG_ARRAY |
  44689                           SOC_REG_FLAG_SIGNAL,
  44690         0,
  44691         1,
  44692         soc_OCB_OCB_BANK_CRC_ERR_BCM88680_A0r_fields,
  44693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44694         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44695         -1,
  44696         -1,
  44697     },
  44698 #endif /* chips */
  44699 
  44700 #if defined(BCM_88650_A0)
  44701     { /* SOC_REG_INT_OCB_OCB_CONFIGURATION_REGISTERr */
  44702         soc_block_list[51],
  44703         soc_genreg,
  44704         1,
  44705         0,
  44706         0x200,
  44707         0,
  44708         0,
  44709         1,
  44710         soc_OCB_OCB_CONFIGURATION_REGISTERr_fields,
  44711         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44712         SOC_RESET_MASK_DEC(0x00000010, 0x00000000)
  44713         -1,
  44714         -1,
  44715     },
  44716 #endif /* chips */
  44717 
  44718 #if defined(BCM_88202_A0)
  44719     { /* SOC_REG_INT_OCB_OCB_CONFIGURATION_REGISTER_BCM88202_A0r */
  44720         soc_block_list[51],
  44721         soc_genreg,
  44722         1,
  44723         0,
  44724         0x200,
  44725         0,
  44726         0,
  44727         1,
  44728         soc_OCB_OCB_CONFIGURATION_REGISTER_BCM88202_A0r_fields,
  44729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44730         SOC_RESET_MASK_DEC(0x00000010, 0x00000000)
  44731         -1,
  44732         -1,
  44733     },
  44734 #endif /* chips */
  44735 
  44736 #if defined(BCM_88650_B0)
  44737     { /* SOC_REG_INT_OCB_OCB_CONFIGURATION_REGISTER_BCM88650_B0r */
  44738         soc_block_list[51],
  44739         soc_genreg,
  44740         1,
  44741         0,
  44742         0x200,
  44743         0,
  44744         0,
  44745         1,
  44746         soc_OCB_OCB_CONFIGURATION_REGISTER_BCM88650_B0r_fields,
  44747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44748         SOC_RESET_MASK_DEC(0x00000010, 0x00000000)
  44749         -1,
  44750         -1,
  44751     },
  44752 #endif /* chips */
  44753 
  44754 #if defined(BCM_88660_A0)
  44755     { /* SOC_REG_INT_OCB_OCB_CONFIGURATION_REGISTER_BCM88660_A0r */
  44756         soc_block_list[51],
  44757         soc_genreg,
  44758         1,
  44759         0,
  44760         0x200,
  44761         0,
  44762         0,
  44763         1,
  44764         soc_OCB_OCB_CONFIGURATION_REGISTER_BCM88660_A0r_fields,
  44765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44766         SOC_RESET_MASK_DEC(0x00000010, 0x00000000)
  44767         -1,
  44768         -1,
  44769     },
  44770 #endif /* chips */
  44771 
  44772 #if defined(BCM_88675_A0)
  44773     { /* SOC_REG_INT_OCB_OCB_CRC_ERRr */
  44774         soc_block_list[51],
  44775         soc_genreg,
  44776         1,
  44777         0,
  44778         0x204,
  44779         SOC_REG_FLAG_RO |
  44780                           SOC_REG_FLAG_SIGNAL,
  44781         0,
  44782         1,
  44783         soc_OCB_OCB_CRC_ERRr_fields,
  44784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44785         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44786         -1,
  44787         -1,
  44788     },
  44789 #endif /* chips */
  44790 
  44791 #if defined(BCM_88375_A0)
  44792     { /* SOC_REG_INT_OCB_OCB_CRC_ERR_BCM88375_A0r */
  44793         soc_block_list[51],
  44794         soc_genreg,
  44795         1,
  44796         0,
  44797         0x204,
  44798         SOC_REG_FLAG_RO |
  44799                           SOC_REG_FLAG_SIGNAL,
  44800         0,
  44801         1,
  44802         soc_OCB_OCB_CRC_ERR_BCM88375_A0r_fields,
  44803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44804         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44805         -1,
  44806         -1,
  44807     },
  44808 #endif /* chips */
  44809 
  44810 #if defined(BCM_88375_B0)
  44811     { /* SOC_REG_INT_OCB_OCB_CRC_ERR_BCM88375_B0r */
  44812         soc_block_list[51],
  44813         soc_genreg,
  44814         1,
  44815         0,
  44816         0x204,
  44817         SOC_REG_FLAG_RO |
  44818                           SOC_REG_FLAG_SIGNAL,
  44819         0,
  44820         1,
  44821         soc_OCB_OCB_CRC_ERR_BCM88375_B0r_fields,
  44822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44824         -1,
  44825         -1,
  44826     },
  44827 #endif /* chips */
  44828 
  44829 #if defined(BCM_88675_B0)
  44830     { /* SOC_REG_INT_OCB_OCB_CRC_ERR_BCM88675_B0r */
  44831         soc_block_list[51],
  44832         soc_genreg,
  44833         1,
  44834         0,
  44835         0x204,
  44836         SOC_REG_FLAG_RO |
  44837                           SOC_REG_FLAG_SIGNAL,
  44838         0,
  44839         1,
  44840         soc_OCB_OCB_CRC_ERR_BCM88675_B0r_fields,
  44841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44842         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44843         -1,
  44844         -1,
  44845     },
  44846 #endif /* chips */
  44847 
  44848 #if defined(BCM_88680_A0)
  44849     { /* SOC_REG_INT_OCB_OCB_CRC_ERR_BCM88680_A0r */
  44850         soc_block_list[51],
  44851         soc_genreg,
  44852         1,
  44853         0,
  44854         0x204,
  44855         SOC_REG_FLAG_RO |
  44856                           SOC_REG_FLAG_SIGNAL,
  44857         0,
  44858         1,
  44859         soc_OCB_OCB_CRC_ERR_BCM88680_A0r_fields,
  44860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44861         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44862         -1,
  44863         -1,
  44864     },
  44865 #endif /* chips */
  44866 
  44867 #if defined(BCM_88650_A0)
  44868     { /* SOC_REG_INT_OCB_OCB_EVEN_RD_CTRr */
  44869         soc_block_list[51],
  44870         soc_genreg,
  44871         1,
  44872         0,
  44873         0x204,
  44874         SOC_REG_FLAG_RO,
  44875         0,
  44876         1,
  44877         soc_OCB_OCB_EVEN_RD_CTRr_fields,
  44878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44879         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44880         -1,
  44881         -1,
  44882     },
  44883 #endif /* chips */
  44884 
  44885 #if defined(BCM_88202_A0)
  44886     { /* SOC_REG_INT_OCB_OCB_EVEN_RD_CTR_BCM88202_A0r */
  44887         soc_block_list[51],
  44888         soc_genreg,
  44889         1,
  44890         0,
  44891         0x204,
  44892         SOC_REG_FLAG_RO,
  44893         0,
  44894         1,
  44895         soc_OCB_OCB_EVEN_RD_CTR_BCM88202_A0r_fields,
  44896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44898         -1,
  44899         -1,
  44900     },
  44901 #endif /* chips */
  44902 
  44903 #if defined(BCM_88650_B0)
  44904     { /* SOC_REG_INT_OCB_OCB_EVEN_RD_CTR_BCM88650_B0r */
  44905         soc_block_list[51],
  44906         soc_genreg,
  44907         1,
  44908         0,
  44909         0x204,
  44910         SOC_REG_FLAG_RO,
  44911         0,
  44912         1,
  44913         soc_OCB_OCB_EVEN_RD_CTR_BCM88650_B0r_fields,
  44914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44916         -1,
  44917         -1,
  44918     },
  44919 #endif /* chips */
  44920 
  44921 #if defined(BCM_88660_A0)
  44922     { /* SOC_REG_INT_OCB_OCB_EVEN_RD_CTR_BCM88660_A0r */
  44923         soc_block_list[51],
  44924         soc_genreg,
  44925         1,
  44926         0,
  44927         0x204,
  44928         SOC_REG_FLAG_RO,
  44929         0,
  44930         1,
  44931         soc_OCB_OCB_EVEN_RD_CTR_BCM88660_A0r_fields,
  44932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44933         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44934         -1,
  44935         -1,
  44936     },
  44937 #endif /* chips */
  44938 
  44939 #if defined(BCM_88650_A0)
  44940     { /* SOC_REG_INT_OCB_OCB_EVEN_WR_CTRr */
  44941         soc_block_list[51],
  44942         soc_genreg,
  44943         1,
  44944         0,
  44945         0x203,
  44946         SOC_REG_FLAG_RO,
  44947         0,
  44948         1,
  44949         soc_OCB_OCB_EVEN_WR_CTRr_fields,
  44950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44952         -1,
  44953         -1,
  44954     },
  44955 #endif /* chips */
  44956 
  44957 #if defined(BCM_88202_A0)
  44958     { /* SOC_REG_INT_OCB_OCB_EVEN_WR_CTR_BCM88202_A0r */
  44959         soc_block_list[51],
  44960         soc_genreg,
  44961         1,
  44962         0,
  44963         0x203,
  44964         SOC_REG_FLAG_RO,
  44965         0,
  44966         1,
  44967         soc_OCB_OCB_EVEN_WR_CTR_BCM88202_A0r_fields,
  44968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44969         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44970         -1,
  44971         -1,
  44972     },
  44973 #endif /* chips */
  44974 
  44975 #if defined(BCM_88650_B0)
  44976     { /* SOC_REG_INT_OCB_OCB_EVEN_WR_CTR_BCM88650_B0r */
  44977         soc_block_list[51],
  44978         soc_genreg,
  44979         1,
  44980         0,
  44981         0x203,
  44982         SOC_REG_FLAG_RO,
  44983         0,
  44984         1,
  44985         soc_OCB_OCB_EVEN_WR_CTR_BCM88650_B0r_fields,
  44986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44987         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44988         -1,
  44989         -1,
  44990     },
  44991 #endif /* chips */
  44992 
  44993 #if defined(BCM_88660_A0)
  44994     { /* SOC_REG_INT_OCB_OCB_EVEN_WR_CTR_BCM88660_A0r */
  44995         soc_block_list[51],
  44996         soc_genreg,
  44997         1,
  44998         0,
  44999         0x203,
  45000         SOC_REG_FLAG_RO,
  45001         0,
  45002         1,
  45003         soc_OCB_OCB_EVEN_WR_CTR_BCM88660_A0r_fields,
  45004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45005         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45006         -1,
  45007         -1,
  45008     },
  45009 #endif /* chips */
  45010 
  45011 #if defined(BCM_88650_A0)
  45012     { /* SOC_REG_INT_OCB_OCB_ODD_RD_CTRr */
  45013         soc_block_list[51],
  45014         soc_genreg,
  45015         1,
  45016         0,
  45017         0x202,
  45018         SOC_REG_FLAG_RO,
  45019         0,
  45020         1,
  45021         soc_OCB_OCB_ODD_RD_CTRr_fields,
  45022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45023         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45024         -1,
  45025         -1,
  45026     },
  45027 #endif /* chips */
  45028 
  45029 #if defined(BCM_88202_A0)
  45030     { /* SOC_REG_INT_OCB_OCB_ODD_RD_CTR_BCM88202_A0r */
  45031         soc_block_list[51],
  45032         soc_genreg,
  45033         1,
  45034         0,
  45035         0x202,
  45036         SOC_REG_FLAG_RO,
  45037         0,
  45038         1,
  45039         soc_OCB_OCB_ODD_RD_CTR_BCM88202_A0r_fields,
  45040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45041         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45042         -1,
  45043         -1,
  45044     },
  45045 #endif /* chips */
  45046 
  45047 #if defined(BCM_88650_B0)
  45048     { /* SOC_REG_INT_OCB_OCB_ODD_RD_CTR_BCM88650_B0r */
  45049         soc_block_list[51],
  45050         soc_genreg,
  45051         1,
  45052         0,
  45053         0x202,
  45054         SOC_REG_FLAG_RO,
  45055         0,
  45056         1,
  45057         soc_OCB_OCB_ODD_RD_CTR_BCM88650_B0r_fields,
  45058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45060         -1,
  45061         -1,
  45062     },
  45063 #endif /* chips */
  45064 
  45065 #if defined(BCM_88660_A0)
  45066     { /* SOC_REG_INT_OCB_OCB_ODD_RD_CTR_BCM88660_A0r */
  45067         soc_block_list[51],
  45068         soc_genreg,
  45069         1,
  45070         0,
  45071         0x202,
  45072         SOC_REG_FLAG_RO,
  45073         0,
  45074         1,
  45075         soc_OCB_OCB_ODD_RD_CTR_BCM88660_A0r_fields,
  45076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45078         -1,
  45079         -1,
  45080     },
  45081 #endif /* chips */
  45082 
  45083 #if defined(BCM_88650_A0)
  45084     { /* SOC_REG_INT_OCB_OCB_ODD_WR_CTRr */
  45085         soc_block_list[51],
  45086         soc_genreg,
  45087         1,
  45088         0,
  45089         0x201,
  45090         SOC_REG_FLAG_RO,
  45091         0,
  45092         1,
  45093         soc_OCB_OCB_ODD_WR_CTRr_fields,
  45094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45096         -1,
  45097         -1,
  45098     },
  45099 #endif /* chips */
  45100 
  45101 #if defined(BCM_88202_A0)
  45102     { /* SOC_REG_INT_OCB_OCB_ODD_WR_CTR_BCM88202_A0r */
  45103         soc_block_list[51],
  45104         soc_genreg,
  45105         1,
  45106         0,
  45107         0x201,
  45108         SOC_REG_FLAG_RO,
  45109         0,
  45110         1,
  45111         soc_OCB_OCB_ODD_WR_CTR_BCM88202_A0r_fields,
  45112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45113         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45114         -1,
  45115         -1,
  45116     },
  45117 #endif /* chips */
  45118 
  45119 #if defined(BCM_88650_B0)
  45120     { /* SOC_REG_INT_OCB_OCB_ODD_WR_CTR_BCM88650_B0r */
  45121         soc_block_list[51],
  45122         soc_genreg,
  45123         1,
  45124         0,
  45125         0x201,
  45126         SOC_REG_FLAG_RO,
  45127         0,
  45128         1,
  45129         soc_OCB_OCB_ODD_WR_CTR_BCM88650_B0r_fields,
  45130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45132         -1,
  45133         -1,
  45134     },
  45135 #endif /* chips */
  45136 
  45137 #if defined(BCM_88660_A0)
  45138     { /* SOC_REG_INT_OCB_OCB_ODD_WR_CTR_BCM88660_A0r */
  45139         soc_block_list[51],
  45140         soc_genreg,
  45141         1,
  45142         0,
  45143         0x201,
  45144         SOC_REG_FLAG_RO,
  45145         0,
  45146         1,
  45147         soc_OCB_OCB_ODD_WR_CTR_BCM88660_A0r_fields,
  45148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45150         -1,
  45151         -1,
  45152     },
  45153 #endif /* chips */
  45154 
  45155 #if defined(BCM_88675_A0)
  45156     { /* SOC_REG_INT_OCB_OCB_RD_CTRr */
  45157         soc_block_list[51],
  45158         soc_genreg,
  45159         1,
  45160         0,
  45161         0x203,
  45162         SOC_REG_FLAG_RO |
  45163                           SOC_REG_FLAG_SIGNAL,
  45164         0,
  45165         1,
  45166         soc_OCB_OCB_RD_CTRr_fields,
  45167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45168         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45169         -1,
  45170         -1,
  45171     },
  45172 #endif /* chips */
  45173 
  45174 #if defined(BCM_88675_A0)
  45175     { /* SOC_REG_INT_OCB_OCB_RD_CTR_BANKr */
  45176         soc_block_list[51],
  45177         soc_genreg,
  45178         16,
  45179         0,
  45180         0x225,
  45181         SOC_REG_FLAG_ARRAY |
  45182                           SOC_REG_FLAG_RO |
  45183                           SOC_REG_FLAG_REG_ARRAY |
  45184                           SOC_REG_FLAG_SIGNAL,
  45185         0,
  45186         1,
  45187         soc_OCB_OCB_RD_CTR_BANKr_fields,
  45188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45189         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45190         -1,
  45191         -1,
  45192     },
  45193 #endif /* chips */
  45194 
  45195 #if defined(BCM_88375_A0)
  45196     { /* SOC_REG_INT_OCB_OCB_RD_CTR_BANK_BCM88375_A0r */
  45197         soc_block_list[51],
  45198         soc_genreg,
  45199         16,
  45200         0,
  45201         0x225,
  45202         SOC_REG_FLAG_ARRAY |
  45203                           SOC_REG_FLAG_RO |
  45204                           SOC_REG_FLAG_REG_ARRAY |
  45205                           SOC_REG_FLAG_SIGNAL,
  45206         0,
  45207         1,
  45208         soc_OCB_OCB_RD_CTR_BANK_BCM88375_A0r_fields,
  45209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45210         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45211         -1,
  45212         -1,
  45213     },
  45214 #endif /* chips */
  45215 
  45216 #if defined(BCM_88375_B0)
  45217     { /* SOC_REG_INT_OCB_OCB_RD_CTR_BANK_BCM88375_B0r */
  45218         soc_block_list[51],
  45219         soc_genreg,
  45220         16,
  45221         0,
  45222         0x225,
  45223         SOC_REG_FLAG_ARRAY |
  45224                           SOC_REG_FLAG_RO |
  45225                           SOC_REG_FLAG_REG_ARRAY |
  45226                           SOC_REG_FLAG_SIGNAL,
  45227         0,
  45228         1,
  45229         soc_OCB_OCB_RD_CTR_BANK_BCM88375_B0r_fields,
  45230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45231         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45232         -1,
  45233         -1,
  45234     },
  45235 #endif /* chips */
  45236 
  45237 #if defined(BCM_88675_B0)
  45238     { /* SOC_REG_INT_OCB_OCB_RD_CTR_BANK_BCM88675_B0r */
  45239         soc_block_list[51],
  45240         soc_genreg,
  45241         16,
  45242         0,
  45243         0x225,
  45244         SOC_REG_FLAG_ARRAY |
  45245                           SOC_REG_FLAG_RO |
  45246                           SOC_REG_FLAG_REG_ARRAY |
  45247                           SOC_REG_FLAG_SIGNAL,
  45248         0,
  45249         1,
  45250         soc_OCB_OCB_RD_CTR_BANK_BCM88675_B0r_fields,
  45251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45253         -1,
  45254         -1,
  45255     },
  45256 #endif /* chips */
  45257 
  45258 #if defined(BCM_88680_A0)
  45259     { /* SOC_REG_INT_OCB_OCB_RD_CTR_BANK_BCM88680_A0r */
  45260         soc_block_list[51],
  45261         soc_genreg,
  45262         16,
  45263         0,
  45264         0x225,
  45265         SOC_REG_FLAG_ARRAY |
  45266                           SOC_REG_FLAG_RO |
  45267                           SOC_REG_FLAG_REG_ARRAY |
  45268                           SOC_REG_FLAG_SIGNAL,
  45269         0,
  45270         1,
  45271         soc_OCB_OCB_RD_CTR_BANK_BCM88680_A0r_fields,
  45272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45273         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45274         -1,
  45275         -1,
  45276     },
  45277 #endif /* chips */
  45278 
  45279 #if defined(BCM_88375_A0)
  45280     { /* SOC_REG_INT_OCB_OCB_RD_CTR_BCM88375_A0r */
  45281         soc_block_list[51],
  45282         soc_genreg,
  45283         1,
  45284         0,
  45285         0x203,
  45286         SOC_REG_FLAG_RO |
  45287                           SOC_REG_FLAG_SIGNAL,
  45288         0,
  45289         1,
  45290         soc_OCB_OCB_RD_CTR_BCM88375_A0r_fields,
  45291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45292         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45293         -1,
  45294         -1,
  45295     },
  45296 #endif /* chips */
  45297 
  45298 #if defined(BCM_88375_B0)
  45299     { /* SOC_REG_INT_OCB_OCB_RD_CTR_BCM88375_B0r */
  45300         soc_block_list[51],
  45301         soc_genreg,
  45302         1,
  45303         0,
  45304         0x203,
  45305         SOC_REG_FLAG_RO |
  45306                           SOC_REG_FLAG_SIGNAL,
  45307         0,
  45308         1,
  45309         soc_OCB_OCB_RD_CTR_BCM88375_B0r_fields,
  45310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45311         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45312         -1,
  45313         -1,
  45314     },
  45315 #endif /* chips */
  45316 
  45317 #if defined(BCM_88675_B0)
  45318     { /* SOC_REG_INT_OCB_OCB_RD_CTR_BCM88675_B0r */
  45319         soc_block_list[51],
  45320         soc_genreg,
  45321         1,
  45322         0,
  45323         0x203,
  45324         SOC_REG_FLAG_RO |
  45325                           SOC_REG_FLAG_SIGNAL,
  45326         0,
  45327         1,
  45328         soc_OCB_OCB_RD_CTR_BCM88675_B0r_fields,
  45329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45330         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45331         -1,
  45332         -1,
  45333     },
  45334 #endif /* chips */
  45335 
  45336 #if defined(BCM_88680_A0)
  45337     { /* SOC_REG_INT_OCB_OCB_RD_CTR_BCM88680_A0r */
  45338         soc_block_list[51],
  45339         soc_genreg,
  45340         1,
  45341         0,
  45342         0x203,
  45343         SOC_REG_FLAG_RO |
  45344                           SOC_REG_FLAG_SIGNAL,
  45345         0,
  45346         1,
  45347         soc_OCB_OCB_RD_CTR_BCM88680_A0r_fields,
  45348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45349         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45350         -1,
  45351         -1,
  45352     },
  45353 #endif /* chips */
  45354 
  45355 #if defined(BCM_88675_A0)
  45356     { /* SOC_REG_INT_OCB_OCB_WR_CTRr */
  45357         soc_block_list[51],
  45358         soc_genreg,
  45359         1,
  45360         0,
  45361         0x202,
  45362         SOC_REG_FLAG_RO |
  45363                           SOC_REG_FLAG_SIGNAL,
  45364         0,
  45365         1,
  45366         soc_OCB_OCB_WR_CTRr_fields,
  45367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45369         -1,
  45370         -1,
  45371     },
  45372 #endif /* chips */
  45373 
  45374 #if defined(BCM_88675_A0)
  45375     { /* SOC_REG_INT_OCB_OCB_WR_CTR_BANKr */
  45376         soc_block_list[51],
  45377         soc_genreg,
  45378         16,
  45379         0,
  45380         0x215,
  45381         SOC_REG_FLAG_ARRAY |
  45382                           SOC_REG_FLAG_RO |
  45383                           SOC_REG_FLAG_REG_ARRAY |
  45384                           SOC_REG_FLAG_SIGNAL,
  45385         0,
  45386         1,
  45387         soc_OCB_OCB_WR_CTR_BANKr_fields,
  45388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45389         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45390         -1,
  45391         -1,
  45392     },
  45393 #endif /* chips */
  45394 
  45395 #if defined(BCM_88375_A0)
  45396     { /* SOC_REG_INT_OCB_OCB_WR_CTR_BANK_BCM88375_A0r */
  45397         soc_block_list[51],
  45398         soc_genreg,
  45399         16,
  45400         0,
  45401         0x215,
  45402         SOC_REG_FLAG_ARRAY |
  45403                           SOC_REG_FLAG_RO |
  45404                           SOC_REG_FLAG_REG_ARRAY |
  45405                           SOC_REG_FLAG_SIGNAL,
  45406         0,
  45407         1,
  45408         soc_OCB_OCB_WR_CTR_BANK_BCM88375_A0r_fields,
  45409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45410         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45411         -1,
  45412         -1,
  45413     },
  45414 #endif /* chips */
  45415 
  45416 #if defined(BCM_88375_B0)
  45417     { /* SOC_REG_INT_OCB_OCB_WR_CTR_BANK_BCM88375_B0r */
  45418         soc_block_list[51],
  45419         soc_genreg,
  45420         16,
  45421         0,
  45422         0x215,
  45423         SOC_REG_FLAG_ARRAY |
  45424                           SOC_REG_FLAG_RO |
  45425                           SOC_REG_FLAG_REG_ARRAY |
  45426                           SOC_REG_FLAG_SIGNAL,
  45427         0,
  45428         1,
  45429         soc_OCB_OCB_WR_CTR_BANK_BCM88375_B0r_fields,
  45430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45431         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45432         -1,
  45433         -1,
  45434     },
  45435 #endif /* chips */
  45436 
  45437 #if defined(BCM_88675_B0)
  45438     { /* SOC_REG_INT_OCB_OCB_WR_CTR_BANK_BCM88675_B0r */
  45439         soc_block_list[51],
  45440         soc_genreg,
  45441         16,
  45442         0,
  45443         0x215,
  45444         SOC_REG_FLAG_ARRAY |
  45445                           SOC_REG_FLAG_RO |
  45446                           SOC_REG_FLAG_REG_ARRAY |
  45447                           SOC_REG_FLAG_SIGNAL,
  45448         0,
  45449         1,
  45450         soc_OCB_OCB_WR_CTR_BANK_BCM88675_B0r_fields,
  45451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45452         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45453         -1,
  45454         -1,
  45455     },
  45456 #endif /* chips */
  45457 
  45458 #if defined(BCM_88680_A0)
  45459     { /* SOC_REG_INT_OCB_OCB_WR_CTR_BANK_BCM88680_A0r */
  45460         soc_block_list[51],
  45461         soc_genreg,
  45462         16,
  45463         0,
  45464         0x215,
  45465         SOC_REG_FLAG_ARRAY |
  45466                           SOC_REG_FLAG_RO |
  45467                           SOC_REG_FLAG_REG_ARRAY |
  45468                           SOC_REG_FLAG_SIGNAL,
  45469         0,
  45470         1,
  45471         soc_OCB_OCB_WR_CTR_BANK_BCM88680_A0r_fields,
  45472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45473         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45474         -1,
  45475         -1,
  45476     },
  45477 #endif /* chips */
  45478 
  45479 #if defined(BCM_88375_A0)
  45480     { /* SOC_REG_INT_OCB_OCB_WR_CTR_BCM88375_A0r */
  45481         soc_block_list[51],
  45482         soc_genreg,
  45483         1,
  45484         0,
  45485         0x202,
  45486         SOC_REG_FLAG_RO |
  45487                           SOC_REG_FLAG_SIGNAL,
  45488         0,
  45489         1,
  45490         soc_OCB_OCB_WR_CTR_BCM88375_A0r_fields,
  45491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45492         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45493         -1,
  45494         -1,
  45495     },
  45496 #endif /* chips */
  45497 
  45498 #if defined(BCM_88375_B0)
  45499     { /* SOC_REG_INT_OCB_OCB_WR_CTR_BCM88375_B0r */
  45500         soc_block_list[51],
  45501         soc_genreg,
  45502         1,
  45503         0,
  45504         0x202,
  45505         SOC_REG_FLAG_RO |
  45506                           SOC_REG_FLAG_SIGNAL,
  45507         0,
  45508         1,
  45509         soc_OCB_OCB_WR_CTR_BCM88375_B0r_fields,
  45510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45511         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45512         -1,
  45513         -1,
  45514     },
  45515 #endif /* chips */
  45516 
  45517 #if defined(BCM_88675_B0)
  45518     { /* SOC_REG_INT_OCB_OCB_WR_CTR_BCM88675_B0r */
  45519         soc_block_list[51],
  45520         soc_genreg,
  45521         1,
  45522         0,
  45523         0x202,
  45524         SOC_REG_FLAG_RO |
  45525                           SOC_REG_FLAG_SIGNAL,
  45526         0,
  45527         1,
  45528         soc_OCB_OCB_WR_CTR_BCM88675_B0r_fields,
  45529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45530         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45531         -1,
  45532         -1,
  45533     },
  45534 #endif /* chips */
  45535 
  45536 #if defined(BCM_88680_A0)
  45537     { /* SOC_REG_INT_OCB_OCB_WR_CTR_BCM88680_A0r */
  45538         soc_block_list[51],
  45539         soc_genreg,
  45540         1,
  45541         0,
  45542         0x202,
  45543         SOC_REG_FLAG_RO |
  45544                           SOC_REG_FLAG_SIGNAL,
  45545         0,
  45546         1,
  45547         soc_OCB_OCB_WR_CTR_BCM88680_A0r_fields,
  45548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45549         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45550         -1,
  45551         -1,
  45552     },
  45553 #endif /* chips */
  45554 
  45555 #if defined(BCM_88675_A0)
  45556     { /* SOC_REG_INT_OCB_PARITY_ERR_CNTr */
  45557         soc_block_list[51],
  45558         soc_genreg,
  45559         1,
  45560         0,
  45561         0x98,
  45562         SOC_REG_FLAG_64_BITS |
  45563                           SOC_REG_FLAG_RO,
  45564         0,
  45565         4,
  45566         soc_OCB_PARITY_ERR_CNTr_fields,
  45567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45568         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  45569         -1,
  45570         -1,
  45571     },
  45572 #endif /* chips */
  45573 
  45574 #if defined(BCM_88375_A0)
  45575     { /* SOC_REG_INT_OCB_PARITY_ERR_CNT_BCM88375_A0r */
  45576         soc_block_list[51],
  45577         soc_genreg,
  45578         1,
  45579         0,
  45580         0x98,
  45581         SOC_REG_FLAG_64_BITS |
  45582                           SOC_REG_FLAG_RO,
  45583         0,
  45584         4,
  45585         soc_OCB_PARITY_ERR_CNT_BCM88375_A0r_fields,
  45586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45587         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  45588         -1,
  45589         -1,
  45590     },
  45591 #endif /* chips */
  45592 
  45593 #if defined(BCM_88375_B0)
  45594     { /* SOC_REG_INT_OCB_PARITY_ERR_CNT_BCM88375_B0r */
  45595         soc_block_list[51],
  45596         soc_genreg,
  45597         1,
  45598         0,
  45599         0x98,
  45600         SOC_REG_FLAG_64_BITS |
  45601                           SOC_REG_FLAG_RO,
  45602         0,
  45603         4,
  45604         soc_OCB_PARITY_ERR_CNT_BCM88375_B0r_fields,
  45605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45606         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  45607         -1,
  45608         -1,
  45609     },
  45610 #endif /* chips */
  45611 
  45612 #if defined(BCM_88675_B0)
  45613     { /* SOC_REG_INT_OCB_PARITY_ERR_CNT_BCM88675_B0r */
  45614         soc_block_list[51],
  45615         soc_genreg,
  45616         1,
  45617         0,
  45618         0x98,
  45619         SOC_REG_FLAG_64_BITS |
  45620                           SOC_REG_FLAG_RO,
  45621         0,
  45622         4,
  45623         soc_OCB_PARITY_ERR_CNT_BCM88675_B0r_fields,
  45624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45625         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  45626         -1,
  45627         -1,
  45628     },
  45629 #endif /* chips */
  45630 
  45631 #if defined(BCM_88680_A0)
  45632     { /* SOC_REG_INT_OCB_PARITY_ERR_CNT_BCM88680_A0r */
  45633         soc_block_list[51],
  45634         soc_genreg,
  45635         1,
  45636         0,
  45637         0x98,
  45638         SOC_REG_FLAG_64_BITS |
  45639                           SOC_REG_FLAG_RO,
  45640         0,
  45641         4,
  45642         soc_OCB_PARITY_ERR_CNT_BCM88680_A0r_fields,
  45643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45644         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  45645         -1,
  45646         -1,
  45647     },
  45648 #endif /* chips */
  45649 
  45650 #if defined(BCM_88675_A0)
  45651     { /* SOC_REG_INT_OCB_PAR_ERR_INITIATEr */
  45652         soc_block_list[51],
  45653         soc_genreg,
  45654         1,
  45655         0,
  45656         0xaa,
  45657         0,
  45658         0,
  45659         1,
  45660         soc_OCB_PAR_ERR_INITIATEr_fields,
  45661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45662         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45663         -1,
  45664         -1,
  45665     },
  45666 #endif /* chips */
  45667 
  45668 #if defined(BCM_88375_A0)
  45669     { /* SOC_REG_INT_OCB_PAR_ERR_INITIATE_BCM88375_A0r */
  45670         soc_block_list[51],
  45671         soc_genreg,
  45672         1,
  45673         0,
  45674         0xaa,
  45675         0,
  45676         0,
  45677         1,
  45678         soc_OCB_PAR_ERR_INITIATE_BCM88375_A0r_fields,
  45679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45680         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45681         -1,
  45682         -1,
  45683     },
  45684 #endif /* chips */
  45685 
  45686 #if defined(BCM_88375_B0)
  45687     { /* SOC_REG_INT_OCB_PAR_ERR_INITIATE_BCM88375_B0r */
  45688         soc_block_list[51],
  45689         soc_genreg,
  45690         1,
  45691         0,
  45692         0xaa,
  45693         0,
  45694         0,
  45695         1,
  45696         soc_OCB_PAR_ERR_INITIATE_BCM88375_B0r_fields,
  45697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45698         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45699         -1,
  45700         -1,
  45701     },
  45702 #endif /* chips */
  45703 
  45704 #if defined(BCM_88675_B0)
  45705     { /* SOC_REG_INT_OCB_PAR_ERR_INITIATE_BCM88675_B0r */
  45706         soc_block_list[51],
  45707         soc_genreg,
  45708         1,
  45709         0,
  45710         0xaa,
  45711         0,
  45712         0,
  45713         1,
  45714         soc_OCB_PAR_ERR_INITIATE_BCM88675_B0r_fields,
  45715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45716         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45717         -1,
  45718         -1,
  45719     },
  45720 #endif /* chips */
  45721 
  45722 #if defined(BCM_88680_A0)
  45723     { /* SOC_REG_INT_OCB_PAR_ERR_INITIATE_BCM88680_A0r */
  45724         soc_block_list[51],
  45725         soc_genreg,
  45726         1,
  45727         0,
  45728         0xaa,
  45729         0,
  45730         0,
  45731         1,
  45732         soc_OCB_PAR_ERR_INITIATE_BCM88680_A0r_fields,
  45733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45734         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45735         -1,
  45736         -1,
  45737     },
  45738 #endif /* chips */
  45739 
  45740 #if defined(BCM_88675_A0)
  45741     { /* SOC_REG_INT_OCB_PAR_ERR_MEM_MASKr */
  45742         soc_block_list[51],
  45743         soc_genreg,
  45744         1,
  45745         0,
  45746         0xa0,
  45747         0,
  45748         0,
  45749         1,
  45750         soc_OCB_PAR_ERR_MEM_MASKr_fields,
  45751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45752         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45753         -1,
  45754         -1,
  45755     },
  45756 #endif /* chips */
  45757 
  45758 #if defined(BCM_88375_A0)
  45759     { /* SOC_REG_INT_OCB_PAR_ERR_MEM_MASK_BCM88375_A0r */
  45760         soc_block_list[51],
  45761         soc_genreg,
  45762         1,
  45763         0,
  45764         0xa0,
  45765         0,
  45766         0,
  45767         1,
  45768         soc_OCB_PAR_ERR_MEM_MASK_BCM88375_A0r_fields,
  45769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45770         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45771         -1,
  45772         -1,
  45773     },
  45774 #endif /* chips */
  45775 
  45776 #if defined(BCM_88375_B0)
  45777     { /* SOC_REG_INT_OCB_PAR_ERR_MEM_MASK_BCM88375_B0r */
  45778         soc_block_list[51],
  45779         soc_genreg,
  45780         1,
  45781         0,
  45782         0xa0,
  45783         0,
  45784         0,
  45785         1,
  45786         soc_OCB_PAR_ERR_MEM_MASK_BCM88375_B0r_fields,
  45787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45788         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45789         -1,
  45790         -1,
  45791     },
  45792 #endif /* chips */
  45793 
  45794 #if defined(BCM_88675_B0)
  45795     { /* SOC_REG_INT_OCB_PAR_ERR_MEM_MASK_BCM88675_B0r */
  45796         soc_block_list[51],
  45797         soc_genreg,
  45798         1,
  45799         0,
  45800         0xa0,
  45801         0,
  45802         0,
  45803         1,
  45804         soc_OCB_PAR_ERR_MEM_MASK_BCM88675_B0r_fields,
  45805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45806         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45807         -1,
  45808         -1,
  45809     },
  45810 #endif /* chips */
  45811 
  45812 #if defined(BCM_88680_A0)
  45813     { /* SOC_REG_INT_OCB_PAR_ERR_MEM_MASK_BCM88680_A0r */
  45814         soc_block_list[51],
  45815         soc_genreg,
  45816         1,
  45817         0,
  45818         0xa0,
  45819         0,
  45820         0,
  45821         1,
  45822         soc_OCB_PAR_ERR_MEM_MASK_BCM88680_A0r_fields,
  45823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45824         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45825         -1,
  45826         -1,
  45827     },
  45828 #endif /* chips */
  45829 
  45830 #if defined(BCM_88690_A0)
  45831     { /* SOC_REG_INT_OCB_PCMI_0r */
  45832         soc_block_list[51],
  45833         soc_genreg,
  45834         1,
  45835         0,
  45836         0xb0,
  45837         0,
  45838         0,
  45839         1,
  45840         soc_OCB_PCMI_0r_fields,
  45841         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  45842         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45843         -1,
  45844         -1,
  45845     },
  45846 #endif /* chips */
  45847 
  45848 #if defined(BCM_88690_A0)
  45849     { /* SOC_REG_INT_OCB_PCMI_1r */
  45850         soc_block_list[51],
  45851         soc_genreg,
  45852         1,
  45853         0,
  45854         0xb3,
  45855         0,
  45856         0,
  45857         1,
  45858         soc_OCB_PCMI_1r_fields,
  45859         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  45860         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45861         -1,
  45862         -1,
  45863     },
  45864 #endif /* chips */
  45865 
  45866 #if defined(BCM_88690_A0)
  45867     { /* SOC_REG_INT_OCB_PCMI_2r */
  45868         soc_block_list[51],
  45869         soc_genreg,
  45870         1,
  45871         0,
  45872         0xb6,
  45873         0,
  45874         0,
  45875         1,
  45876         soc_OCB_PCMI_2r_fields,
  45877         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  45878         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45879         -1,
  45880         -1,
  45881     },
  45882 #endif /* chips */
  45883 
  45884 #if defined(BCM_88690_A0)
  45885     { /* SOC_REG_INT_OCB_PCMI_3r */
  45886         soc_block_list[51],
  45887         soc_genreg,
  45888         1,
  45889         0,
  45890         0xb9,
  45891         0,
  45892         0,
  45893         1,
  45894         soc_OCB_PCMI_3r_fields,
  45895         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  45896         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45897         -1,
  45898         -1,
  45899     },
  45900 #endif /* chips */
  45901 
  45902 #if defined(BCM_88690_A0)
  45903     { /* SOC_REG_INT_OCB_PCMI_4r */
  45904         soc_block_list[51],
  45905         soc_genreg,
  45906         1,
  45907         0,
  45908         0xbc,
  45909         0,
  45910         0,
  45911         1,
  45912         soc_OCB_PCMI_4r_fields,
  45913         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  45914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45915         -1,
  45916         -1,
  45917     },
  45918 #endif /* chips */
  45919 
  45920 #if defined(BCM_88690_B0)
  45921     { /* SOC_REG_INT_OCB_PCMI_0_BCM88690_B0r */
  45922         soc_block_list[51],
  45923         soc_genreg,
  45924         1,
  45925         0,
  45926         0xb0,
  45927         0,
  45928         0,
  45929         1,
  45930         soc_OCB_PCMI_0_BCM88690_B0r_fields,
  45931         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  45932         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45933         -1,
  45934         -1,
  45935     },
  45936 #endif /* chips */
  45937 
  45938 #if defined(BCM_88690_A0)
  45939     { /* SOC_REG_INT_OCB_PCMI_0_Sr */
  45940         soc_block_list[51],
  45941         soc_genreg,
  45942         1,
  45943         0,
  45944         0xb1,
  45945         SOC_REG_FLAG_RO,
  45946         0,
  45947         3,
  45948         soc_OCB_PCMI_0_Sr_fields,
  45949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45950         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45951         -1,
  45952         -1,
  45953     },
  45954 #endif /* chips */
  45955 
  45956 #if defined(BCM_88690_B0)
  45957     { /* SOC_REG_INT_OCB_PCMI_0_S_BCM88690_B0r */
  45958         soc_block_list[51],
  45959         soc_genreg,
  45960         1,
  45961         0,
  45962         0xb1,
  45963         SOC_REG_FLAG_RO,
  45964         0,
  45965         3,
  45966         soc_OCB_PCMI_0_S_BCM88690_B0r_fields,
  45967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45968         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45969         -1,
  45970         -1,
  45971     },
  45972 #endif /* chips */
  45973 
  45974 #if defined(BCM_88690_A0)
  45975     { /* SOC_REG_INT_OCB_PCMI_0_Tr */
  45976         soc_block_list[51],
  45977         soc_genreg,
  45978         1,
  45979         0,
  45980         0xb2,
  45981         0,
  45982         0,
  45983         2,
  45984         soc_OCB_PCMI_0_Tr_fields,
  45985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45986         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  45987         -1,
  45988         -1,
  45989     },
  45990 #endif /* chips */
  45991 
  45992 #if defined(BCM_88690_B0)
  45993     { /* SOC_REG_INT_OCB_PCMI_0_T_BCM88690_B0r */
  45994         soc_block_list[51],
  45995         soc_genreg,
  45996         1,
  45997         0,
  45998         0xb2,
  45999         0,
  46000         0,
  46001         2,
  46002         soc_OCB_PCMI_0_T_BCM88690_B0r_fields,
  46003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46004         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  46005         -1,
  46006         -1,
  46007     },
  46008 #endif /* chips */
  46009 
  46010 #if defined(BCM_88690_B0)
  46011     { /* SOC_REG_INT_OCB_PCMI_1_BCM88690_B0r */
  46012         soc_block_list[51],
  46013         soc_genreg,
  46014         1,
  46015         0,
  46016         0xb3,
  46017         0,
  46018         0,
  46019         1,
  46020         soc_OCB_PCMI_1_BCM88690_B0r_fields,
  46021         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  46022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46023         -1,
  46024         -1,
  46025     },
  46026 #endif /* chips */
  46027 
  46028 #if defined(BCM_88690_A0)
  46029     { /* SOC_REG_INT_OCB_PCMI_1_Sr */
  46030         soc_block_list[51],
  46031         soc_genreg,
  46032         1,
  46033         0,
  46034         0xb4,
  46035         SOC_REG_FLAG_RO,
  46036         0,
  46037         3,
  46038         soc_OCB_PCMI_1_Sr_fields,
  46039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46040         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46041         -1,
  46042         -1,
  46043     },
  46044 #endif /* chips */
  46045 
  46046 #if defined(BCM_88690_B0)
  46047     { /* SOC_REG_INT_OCB_PCMI_1_S_BCM88690_B0r */
  46048         soc_block_list[51],
  46049         soc_genreg,
  46050         1,
  46051         0,
  46052         0xb4,
  46053         SOC_REG_FLAG_RO,
  46054         0,
  46055         3,
  46056         soc_OCB_PCMI_1_S_BCM88690_B0r_fields,
  46057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46058         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46059         -1,
  46060         -1,
  46061     },
  46062 #endif /* chips */
  46063 
  46064 #if defined(BCM_88690_A0)
  46065     { /* SOC_REG_INT_OCB_PCMI_1_Tr */
  46066         soc_block_list[51],
  46067         soc_genreg,
  46068         1,
  46069         0,
  46070         0xb5,
  46071         0,
  46072         0,
  46073         2,
  46074         soc_OCB_PCMI_1_Tr_fields,
  46075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46076         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  46077         -1,
  46078         -1,
  46079     },
  46080 #endif /* chips */
  46081 
  46082 #if defined(BCM_88690_B0)
  46083     { /* SOC_REG_INT_OCB_PCMI_1_T_BCM88690_B0r */
  46084         soc_block_list[51],
  46085         soc_genreg,
  46086         1,
  46087         0,
  46088         0xb5,
  46089         0,
  46090         0,
  46091         2,
  46092         soc_OCB_PCMI_1_T_BCM88690_B0r_fields,
  46093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46094         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  46095         -1,
  46096         -1,
  46097     },
  46098 #endif /* chips */
  46099 
  46100 #if defined(BCM_88690_B0)
  46101     { /* SOC_REG_INT_OCB_PCMI_2_BCM88690_B0r */
  46102         soc_block_list[51],
  46103         soc_genreg,
  46104         1,
  46105         0,
  46106         0xb6,
  46107         0,
  46108         0,
  46109         1,
  46110         soc_OCB_PCMI_2_BCM88690_B0r_fields,
  46111         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  46112         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46113         -1,
  46114         -1,
  46115     },
  46116 #endif /* chips */
  46117 
  46118 #if defined(BCM_88690_A0)
  46119     { /* SOC_REG_INT_OCB_PCMI_2_Sr */
  46120         soc_block_list[51],
  46121         soc_genreg,
  46122         1,
  46123         0,
  46124         0xb7,
  46125         SOC_REG_FLAG_RO,
  46126         0,
  46127         3,
  46128         soc_OCB_PCMI_2_Sr_fields,
  46129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46130         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46131         -1,
  46132         -1,
  46133     },
  46134 #endif /* chips */
  46135 
  46136 #if defined(BCM_88690_B0)
  46137     { /* SOC_REG_INT_OCB_PCMI_2_S_BCM88690_B0r */
  46138         soc_block_list[51],
  46139         soc_genreg,
  46140         1,
  46141         0,
  46142         0xb7,
  46143         SOC_REG_FLAG_RO,
  46144         0,
  46145         3,
  46146         soc_OCB_PCMI_2_S_BCM88690_B0r_fields,
  46147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46149         -1,
  46150         -1,
  46151     },
  46152 #endif /* chips */
  46153 
  46154 #if defined(BCM_88690_A0)
  46155     { /* SOC_REG_INT_OCB_PCMI_2_Tr */
  46156         soc_block_list[51],
  46157         soc_genreg,
  46158         1,
  46159         0,
  46160         0xb8,
  46161         0,
  46162         0,
  46163         2,
  46164         soc_OCB_PCMI_2_Tr_fields,
  46165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46166         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  46167         -1,
  46168         -1,
  46169     },
  46170 #endif /* chips */
  46171 
  46172 #if defined(BCM_88690_B0)
  46173     { /* SOC_REG_INT_OCB_PCMI_2_T_BCM88690_B0r */
  46174         soc_block_list[51],
  46175         soc_genreg,
  46176         1,
  46177         0,
  46178         0xb8,
  46179         0,
  46180         0,
  46181         2,
  46182         soc_OCB_PCMI_2_T_BCM88690_B0r_fields,
  46183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46184         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  46185         -1,
  46186         -1,
  46187     },
  46188 #endif /* chips */
  46189 
  46190 #if defined(BCM_88690_B0)
  46191     { /* SOC_REG_INT_OCB_PCMI_3_BCM88690_B0r */
  46192         soc_block_list[51],
  46193         soc_genreg,
  46194         1,
  46195         0,
  46196         0xb9,
  46197         0,
  46198         0,
  46199         1,
  46200         soc_OCB_PCMI_3_BCM88690_B0r_fields,
  46201         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  46202         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46203         -1,
  46204         -1,
  46205     },
  46206 #endif /* chips */
  46207 
  46208 #if defined(BCM_88690_A0)
  46209     { /* SOC_REG_INT_OCB_PCMI_3_Sr */
  46210         soc_block_list[51],
  46211         soc_genreg,
  46212         1,
  46213         0,
  46214         0xba,
  46215         SOC_REG_FLAG_RO,
  46216         0,
  46217         3,
  46218         soc_OCB_PCMI_3_Sr_fields,
  46219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46220         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46221         -1,
  46222         -1,
  46223     },
  46224 #endif /* chips */
  46225 
  46226 #if defined(BCM_88690_B0)
  46227     { /* SOC_REG_INT_OCB_PCMI_3_S_BCM88690_B0r */
  46228         soc_block_list[51],
  46229         soc_genreg,
  46230         1,
  46231         0,
  46232         0xba,
  46233         SOC_REG_FLAG_RO,
  46234         0,
  46235         3,
  46236         soc_OCB_PCMI_3_S_BCM88690_B0r_fields,
  46237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46238         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46239         -1,
  46240         -1,
  46241     },
  46242 #endif /* chips */
  46243 
  46244 #if defined(BCM_88690_A0)
  46245     { /* SOC_REG_INT_OCB_PCMI_3_Tr */
  46246         soc_block_list[51],
  46247         soc_genreg,
  46248         1,
  46249         0,
  46250         0xbb,
  46251         0,
  46252         0,
  46253         2,
  46254         soc_OCB_PCMI_3_Tr_fields,
  46255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46256         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  46257         -1,
  46258         -1,
  46259     },
  46260 #endif /* chips */
  46261 
  46262 #if defined(BCM_88690_B0)
  46263     { /* SOC_REG_INT_OCB_PCMI_3_T_BCM88690_B0r */
  46264         soc_block_list[51],
  46265         soc_genreg,
  46266         1,
  46267         0,
  46268         0xbb,
  46269         0,
  46270         0,
  46271         2,
  46272         soc_OCB_PCMI_3_T_BCM88690_B0r_fields,
  46273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46274         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  46275         -1,
  46276         -1,
  46277     },
  46278 #endif /* chips */
  46279 
  46280 #if defined(BCM_88690_B0)
  46281     { /* SOC_REG_INT_OCB_PCMI_4_BCM88690_B0r */
  46282         soc_block_list[51],
  46283         soc_genreg,
  46284         1,
  46285         0,
  46286         0xbc,
  46287         0,
  46288         0,
  46289         1,
  46290         soc_OCB_PCMI_4_BCM88690_B0r_fields,
  46291         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  46292         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46293         -1,
  46294         -1,
  46295     },
  46296 #endif /* chips */
  46297 
  46298 #if defined(BCM_88690_A0)
  46299     { /* SOC_REG_INT_OCB_PCMI_4_Sr */
  46300         soc_block_list[51],
  46301         soc_genreg,
  46302         1,
  46303         0,
  46304         0xbd,
  46305         SOC_REG_FLAG_RO,
  46306         0,
  46307         3,
  46308         soc_OCB_PCMI_4_Sr_fields,
  46309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46310         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46311         -1,
  46312         -1,
  46313     },
  46314 #endif /* chips */
  46315 
  46316 #if defined(BCM_88690_B0)
  46317     { /* SOC_REG_INT_OCB_PCMI_4_S_BCM88690_B0r */
  46318         soc_block_list[51],
  46319         soc_genreg,
  46320         1,
  46321         0,
  46322         0xbd,
  46323         SOC_REG_FLAG_RO,
  46324         0,
  46325         3,
  46326         soc_OCB_PCMI_4_S_BCM88690_B0r_fields,
  46327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46328         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46329         -1,
  46330         -1,
  46331     },
  46332 #endif /* chips */
  46333 
  46334 #if defined(BCM_88690_A0)
  46335     { /* SOC_REG_INT_OCB_PCMI_4_Tr */
  46336         soc_block_list[51],
  46337         soc_genreg,
  46338         1,
  46339         0,
  46340         0xbe,
  46341         0,
  46342         0,
  46343         2,
  46344         soc_OCB_PCMI_4_Tr_fields,
  46345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46346         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  46347         -1,
  46348         -1,
  46349     },
  46350 #endif /* chips */
  46351 
  46352 #if defined(BCM_88690_B0)
  46353     { /* SOC_REG_INT_OCB_PCMI_4_T_BCM88690_B0r */
  46354         soc_block_list[51],
  46355         soc_genreg,
  46356         1,
  46357         0,
  46358         0xbe,
  46359         0,
  46360         0,
  46361         2,
  46362         soc_OCB_PCMI_4_T_BCM88690_B0r_fields,
  46363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46364         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  46365         -1,
  46366         -1,
  46367     },
  46368 #endif /* chips */
  46369 
  46370 #if defined(BCM_88675_A0)
  46371     { /* SOC_REG_INT_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANKr */
  46372         soc_block_list[51],
  46373         soc_genreg,
  46374         16,
  46375         0,
  46376         0x235,
  46377         SOC_REG_FLAG_ARRAY |
  46378                           SOC_REG_FLAG_RO |
  46379                           SOC_REG_FLAG_REG_ARRAY |
  46380                           SOC_REG_FLAG_SIGNAL,
  46381         0,
  46382         1,
  46383         soc_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANKr_fields,
  46384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46385         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46386         -1,
  46387         -1,
  46388     },
  46389 #endif /* chips */
  46390 
  46391 #if defined(BCM_88375_A0)
  46392     { /* SOC_REG_INT_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANK_BCM88375_A0r */
  46393         soc_block_list[51],
  46394         soc_genreg,
  46395         16,
  46396         0,
  46397         0x235,
  46398         SOC_REG_FLAG_ARRAY |
  46399                           SOC_REG_FLAG_RO |
  46400                           SOC_REG_FLAG_REG_ARRAY |
  46401                           SOC_REG_FLAG_SIGNAL,
  46402         0,
  46403         1,
  46404         soc_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANK_BCM88375_A0r_fields,
  46405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46406         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46407         -1,
  46408         -1,
  46409     },
  46410 #endif /* chips */
  46411 
  46412 #if defined(BCM_88375_B0)
  46413     { /* SOC_REG_INT_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANK_BCM88375_B0r */
  46414         soc_block_list[51],
  46415         soc_genreg,
  46416         16,
  46417         0,
  46418         0x235,
  46419         SOC_REG_FLAG_ARRAY |
  46420                           SOC_REG_FLAG_RO |
  46421                           SOC_REG_FLAG_REG_ARRAY |
  46422                           SOC_REG_FLAG_SIGNAL,
  46423         0,
  46424         1,
  46425         soc_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANK_BCM88375_B0r_fields,
  46426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46428         -1,
  46429         -1,
  46430     },
  46431 #endif /* chips */
  46432 
  46433 #if defined(BCM_88675_B0)
  46434     { /* SOC_REG_INT_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANK_BCM88675_B0r */
  46435         soc_block_list[51],
  46436         soc_genreg,
  46437         16,
  46438         0,
  46439         0x235,
  46440         SOC_REG_FLAG_ARRAY |
  46441                           SOC_REG_FLAG_RO |
  46442                           SOC_REG_FLAG_REG_ARRAY |
  46443                           SOC_REG_FLAG_SIGNAL,
  46444         0,
  46445         1,
  46446         soc_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANK_BCM88675_B0r_fields,
  46447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46448         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46449         -1,
  46450         -1,
  46451     },
  46452 #endif /* chips */
  46453 
  46454 #if defined(BCM_88680_A0)
  46455     { /* SOC_REG_INT_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANK_BCM88680_A0r */
  46456         soc_block_list[51],
  46457         soc_genreg,
  46458         16,
  46459         0,
  46460         0x235,
  46461         SOC_REG_FLAG_ARRAY |
  46462                           SOC_REG_FLAG_RO |
  46463                           SOC_REG_FLAG_REG_ARRAY |
  46464                           SOC_REG_FLAG_SIGNAL,
  46465         0,
  46466         1,
  46467         soc_OCB_RD_ADDR_FIFO_ALMOST_FULL_BANK_BCM88680_A0r_fields,
  46468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46469         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46470         -1,
  46471         -1,
  46472     },
  46473 #endif /* chips */
  46474 
  46475 #if defined(BCM_88675_A0)
  46476     { /* SOC_REG_INT_OCB_READ_ADDR_FIFO_STATUS_BANKr */
  46477         soc_block_list[51],
  46478         soc_genreg,
  46479         16,
  46480         0,
  46481         0x246,
  46482         SOC_REG_FLAG_ARRAY |
  46483                           SOC_REG_FLAG_RO |
  46484                           SOC_REG_FLAG_REG_ARRAY |
  46485                           SOC_REG_FLAG_SIGNAL,
  46486         0,
  46487         1,
  46488         soc_OCB_READ_ADDR_FIFO_STATUS_BANKr_fields,
  46489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46490         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  46491         -1,
  46492         -1,
  46493     },
  46494 #endif /* chips */
  46495 
  46496 #if defined(BCM_88375_A0)
  46497     { /* SOC_REG_INT_OCB_READ_ADDR_FIFO_STATUS_BANK_BCM88375_A0r */
  46498         soc_block_list[51],
  46499         soc_genreg,
  46500         16,
  46501         0,
  46502         0x246,
  46503         SOC_REG_FLAG_ARRAY |
  46504                           SOC_REG_FLAG_RO |
  46505                           SOC_REG_FLAG_REG_ARRAY |
  46506                           SOC_REG_FLAG_SIGNAL,
  46507         0,
  46508         1,
  46509         soc_OCB_READ_ADDR_FIFO_STATUS_BANK_BCM88375_A0r_fields,
  46510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46511         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  46512         -1,
  46513         -1,
  46514     },
  46515 #endif /* chips */
  46516 
  46517 #if defined(BCM_88375_B0)
  46518     { /* SOC_REG_INT_OCB_READ_ADDR_FIFO_STATUS_BANK_BCM88375_B0r */
  46519         soc_block_list[51],
  46520         soc_genreg,
  46521         16,
  46522         0,
  46523         0x246,
  46524         SOC_REG_FLAG_ARRAY |
  46525                           SOC_REG_FLAG_RO |
  46526                           SOC_REG_FLAG_REG_ARRAY |
  46527                           SOC_REG_FLAG_SIGNAL,
  46528         0,
  46529         1,
  46530         soc_OCB_READ_ADDR_FIFO_STATUS_BANK_BCM88375_B0r_fields,
  46531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46532         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  46533         -1,
  46534         -1,
  46535     },
  46536 #endif /* chips */
  46537 
  46538 #if defined(BCM_88675_B0)
  46539     { /* SOC_REG_INT_OCB_READ_ADDR_FIFO_STATUS_BANK_BCM88675_B0r */
  46540         soc_block_list[51],
  46541         soc_genreg,
  46542         16,
  46543         0,
  46544         0x246,
  46545         SOC_REG_FLAG_ARRAY |
  46546                           SOC_REG_FLAG_RO |
  46547                           SOC_REG_FLAG_REG_ARRAY |
  46548                           SOC_REG_FLAG_SIGNAL,
  46549         0,
  46550         1,
  46551         soc_OCB_READ_ADDR_FIFO_STATUS_BANK_BCM88675_B0r_fields,
  46552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46553         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  46554         -1,
  46555         -1,
  46556     },
  46557 #endif /* chips */
  46558 
  46559 #if defined(BCM_88680_A0)
  46560     { /* SOC_REG_INT_OCB_READ_ADDR_FIFO_STATUS_BANK_BCM88680_A0r */
  46561         soc_block_list[51],
  46562         soc_genreg,
  46563         16,
  46564         0,
  46565         0x246,
  46566         SOC_REG_FLAG_ARRAY |
  46567                           SOC_REG_FLAG_RO |
  46568                           SOC_REG_FLAG_REG_ARRAY |
  46569                           SOC_REG_FLAG_SIGNAL,
  46570         0,
  46571         1,
  46572         soc_OCB_READ_ADDR_FIFO_STATUS_BANK_BCM88680_A0r_fields,
  46573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46574         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  46575         -1,
  46576         -1,
  46577     },
  46578 #endif /* chips */
  46579 
  46580 #if defined(BCM_88675_A0)
  46581     { /* SOC_REG_INT_OCB_READ_DATA_FIFO_STATUS_BANKr */
  46582         soc_block_list[51],
  46583         soc_genreg,
  46584         16,
  46585         0,
  46586         0x256,
  46587         SOC_REG_FLAG_ARRAY |
  46588                           SOC_REG_FLAG_RO |
  46589                           SOC_REG_FLAG_REG_ARRAY |
  46590                           SOC_REG_FLAG_SIGNAL,
  46591         0,
  46592         1,
  46593         soc_OCB_READ_DATA_FIFO_STATUS_BANKr_fields,
  46594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46595         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  46596         -1,
  46597         -1,
  46598     },
  46599 #endif /* chips */
  46600 
  46601 #if defined(BCM_88375_A0)
  46602     { /* SOC_REG_INT_OCB_READ_DATA_FIFO_STATUS_BANK_BCM88375_A0r */
  46603         soc_block_list[51],
  46604         soc_genreg,
  46605         16,
  46606         0,
  46607         0x256,
  46608         SOC_REG_FLAG_ARRAY |
  46609                           SOC_REG_FLAG_RO |
  46610                           SOC_REG_FLAG_REG_ARRAY |
  46611                           SOC_REG_FLAG_SIGNAL,
  46612         0,
  46613         1,
  46614         soc_OCB_READ_DATA_FIFO_STATUS_BANK_BCM88375_A0r_fields,
  46615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46616         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  46617         -1,
  46618         -1,
  46619     },
  46620 #endif /* chips */
  46621 
  46622 #if defined(BCM_88375_B0)
  46623     { /* SOC_REG_INT_OCB_READ_DATA_FIFO_STATUS_BANK_BCM88375_B0r */
  46624         soc_block_list[51],
  46625         soc_genreg,
  46626         16,
  46627         0,
  46628         0x256,
  46629         SOC_REG_FLAG_ARRAY |
  46630                           SOC_REG_FLAG_RO |
  46631                           SOC_REG_FLAG_REG_ARRAY |
  46632                           SOC_REG_FLAG_SIGNAL,
  46633         0,
  46634         1,
  46635         soc_OCB_READ_DATA_FIFO_STATUS_BANK_BCM88375_B0r_fields,
  46636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46637         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  46638         -1,
  46639         -1,
  46640     },
  46641 #endif /* chips */
  46642 
  46643 #if defined(BCM_88675_B0)
  46644     { /* SOC_REG_INT_OCB_READ_DATA_FIFO_STATUS_BANK_BCM88675_B0r */
  46645         soc_block_list[51],
  46646         soc_genreg,
  46647         16,
  46648         0,
  46649         0x256,
  46650         SOC_REG_FLAG_ARRAY |
  46651                           SOC_REG_FLAG_RO |
  46652                           SOC_REG_FLAG_REG_ARRAY |
  46653                           SOC_REG_FLAG_SIGNAL,
  46654         0,
  46655         1,
  46656         soc_OCB_READ_DATA_FIFO_STATUS_BANK_BCM88675_B0r_fields,
  46657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46658         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  46659         -1,
  46660         -1,
  46661     },
  46662 #endif /* chips */
  46663 
  46664 #if defined(BCM_88680_A0)
  46665     { /* SOC_REG_INT_OCB_READ_DATA_FIFO_STATUS_BANK_BCM88680_A0r */
  46666         soc_block_list[51],
  46667         soc_genreg,
  46668         16,
  46669         0,
  46670         0x256,
  46671         SOC_REG_FLAG_ARRAY |
  46672                           SOC_REG_FLAG_RO |
  46673                           SOC_REG_FLAG_REG_ARRAY |
  46674                           SOC_REG_FLAG_SIGNAL,
  46675         0,
  46676         1,
  46677         soc_OCB_READ_DATA_FIFO_STATUS_BANK_BCM88680_A0r_fields,
  46678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46679         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  46680         -1,
  46681         -1,
  46682     },
  46683 #endif /* chips */
  46684 
  46685 #if defined(BCM_88650_A0)
  46686     { /* SOC_REG_INT_OCB_REG_0020r */
  46687         soc_block_list[51],
  46688         soc_genreg,
  46689         1,
  46690         0,
  46691         0x20,
  46692         0,
  46693         0,
  46694         1,
  46695         soc_OCB_REG_0020r_fields,
  46696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46697         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  46698         -1,
  46699         -1,
  46700     },
  46701 #endif /* chips */
  46702 
  46703 #if defined(BCM_88650_A0)
  46704     { /* SOC_REG_INT_OCB_REG_0040r */
  46705         soc_block_list[51],
  46706         soc_genreg,
  46707         1,
  46708         0,
  46709         0x40,
  46710         SOC_REG_FLAG_RO,
  46711         0,
  46712         1,
  46713         soc_OCB_REG_0040r_fields,
  46714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46715         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  46716         -1,
  46717         -1,
  46718     },
  46719 #endif /* chips */
  46720 
  46721 #if defined(BCM_88650_A0)
  46722     { /* SOC_REG_INT_OCB_REG_0085r */
  46723         soc_block_list[51],
  46724         soc_genreg,
  46725         1,
  46726         0,
  46727         0x85,
  46728         0,
  46729         0,
  46730         2,
  46731         soc_OCB_REG_0085r_fields,
  46732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46733         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  46734         -1,
  46735         -1,
  46736     },
  46737 #endif /* chips */
  46738 
  46739 #if defined(BCM_88650_A0)
  46740     { /* SOC_REG_INT_OCB_REG_0086r */
  46741         soc_block_list[51],
  46742         soc_genreg,
  46743         1,
  46744         0,
  46745         0x86,
  46746         SOC_REG_FLAG_SIGNAL,
  46747         0,
  46748         1,
  46749         soc_OCB_REG_0086r_fields,
  46750         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  46751         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  46752         -1,
  46753         -1,
  46754     },
  46755 #endif /* chips */
  46756 
  46757 #if defined(BCM_88650_A0)
  46758     { /* SOC_REG_INT_OCB_REG_0087r */
  46759         soc_block_list[51],
  46760         soc_genreg,
  46761         1,
  46762         0,
  46763         0x87,
  46764         SOC_REG_FLAG_SIGNAL,
  46765         0,
  46766         1,
  46767         soc_OCB_REG_0087r_fields,
  46768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46769         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46770         -1,
  46771         -1,
  46772     },
  46773 #endif /* chips */
  46774 
  46775 #if defined(BCM_88650_A0)
  46776     { /* SOC_REG_INT_OCB_REG_0090r */
  46777         soc_block_list[51],
  46778         soc_genreg,
  46779         1,
  46780         0,
  46781         0x90,
  46782         SOC_REG_FLAG_SIGNAL,
  46783         0,
  46784         1,
  46785         soc_OCB_REG_0090r_fields,
  46786         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  46787         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46788         -1,
  46789         -1,
  46790     },
  46791 #endif /* chips */
  46792 
  46793 #if defined(BCM_88650_A0)
  46794     { /* SOC_REG_INT_OCB_REG_0091r */
  46795         soc_block_list[51],
  46796         soc_genreg,
  46797         1,
  46798         0,
  46799         0x91,
  46800         SOC_REG_FLAG_SIGNAL,
  46801         0,
  46802         1,
  46803         soc_OCB_REG_0091r_fields,
  46804         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  46805         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46806         -1,
  46807         -1,
  46808     },
  46809 #endif /* chips */
  46810 
  46811 #if defined(BCM_88650_A0)
  46812     { /* SOC_REG_INT_OCB_REG_0092r */
  46813         soc_block_list[51],
  46814         soc_genreg,
  46815         1,
  46816         0,
  46817         0x92,
  46818         SOC_REG_FLAG_SIGNAL,
  46819         0,
  46820         1,
  46821         soc_OCB_REG_0092r_fields,
  46822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46824         -1,
  46825         -1,
  46826     },
  46827 #endif /* chips */
  46828 
  46829 #if defined(BCM_88650_A0)
  46830     { /* SOC_REG_INT_OCB_REG_0093r */
  46831         soc_block_list[51],
  46832         soc_genreg,
  46833         1,
  46834         0,
  46835         0x93,
  46836         SOC_REG_FLAG_SIGNAL,
  46837         0,
  46838         1,
  46839         soc_OCB_REG_0093r_fields,
  46840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46842         -1,
  46843         -1,
  46844     },
  46845 #endif /* chips */
  46846 
  46847 #if defined(BCM_88202_A0)
  46848     { /* SOC_REG_INT_OCB_REG_0020_BCM88202_A0r */
  46849         soc_block_list[51],
  46850         soc_genreg,
  46851         1,
  46852         0,
  46853         0x20,
  46854         0,
  46855         0,
  46856         1,
  46857         soc_OCB_REG_0020_BCM88202_A0r_fields,
  46858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46859         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  46860         -1,
  46861         -1,
  46862     },
  46863 #endif /* chips */
  46864 
  46865 #if defined(BCM_88650_B0)
  46866     { /* SOC_REG_INT_OCB_REG_0020_BCM88650_B0r */
  46867         soc_block_list[51],
  46868         soc_genreg,
  46869         1,
  46870         0,
  46871         0x20,
  46872         0,
  46873         0,
  46874         1,
  46875         soc_OCB_REG_0020_BCM88650_B0r_fields,
  46876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46877         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  46878         -1,
  46879         -1,
  46880     },
  46881 #endif /* chips */
  46882 
  46883 #if defined(BCM_88660_A0)
  46884     { /* SOC_REG_INT_OCB_REG_0020_BCM88660_A0r */
  46885         soc_block_list[51],
  46886         soc_genreg,
  46887         1,
  46888         0,
  46889         0x20,
  46890         0,
  46891         0,
  46892         1,
  46893         soc_OCB_REG_0020_BCM88660_A0r_fields,
  46894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46895         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  46896         -1,
  46897         -1,
  46898     },
  46899 #endif /* chips */
  46900 
  46901 #if defined(BCM_88202_A0)
  46902     { /* SOC_REG_INT_OCB_REG_0040_BCM88202_A0r */
  46903         soc_block_list[51],
  46904         soc_genreg,
  46905         1,
  46906         0,
  46907         0x40,
  46908         SOC_REG_FLAG_RO,
  46909         0,
  46910         1,
  46911         soc_OCB_REG_0040_BCM88202_A0r_fields,
  46912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46913         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  46914         -1,
  46915         -1,
  46916     },
  46917 #endif /* chips */
  46918 
  46919 #if defined(BCM_88650_B0)
  46920     { /* SOC_REG_INT_OCB_REG_0040_BCM88650_B0r */
  46921         soc_block_list[51],
  46922         soc_genreg,
  46923         1,
  46924         0,
  46925         0x40,
  46926         SOC_REG_FLAG_RO,
  46927         0,
  46928         1,
  46929         soc_OCB_REG_0040_BCM88650_B0r_fields,
  46930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46931         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  46932         -1,
  46933         -1,
  46934     },
  46935 #endif /* chips */
  46936 
  46937 #if defined(BCM_88660_A0)
  46938     { /* SOC_REG_INT_OCB_REG_0040_BCM88660_A0r */
  46939         soc_block_list[51],
  46940         soc_genreg,
  46941         1,
  46942         0,
  46943         0x40,
  46944         SOC_REG_FLAG_RO,
  46945         0,
  46946         1,
  46947         soc_OCB_REG_0040_BCM88660_A0r_fields,
  46948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46949         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  46950         -1,
  46951         -1,
  46952     },
  46953 #endif /* chips */
  46954 
  46955 #if defined(BCM_88202_A0)
  46956     { /* SOC_REG_INT_OCB_REG_0085_BCM88202_A0r */
  46957         soc_block_list[51],
  46958         soc_genreg,
  46959         1,
  46960         0,
  46961         0x85,
  46962         0,
  46963         0,
  46964         2,
  46965         soc_OCB_REG_0085_BCM88202_A0r_fields,
  46966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46967         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  46968         -1,
  46969         -1,
  46970     },
  46971 #endif /* chips */
  46972 
  46973 #if defined(BCM_88650_B0)
  46974     { /* SOC_REG_INT_OCB_REG_0085_BCM88650_B0r */
  46975         soc_block_list[51],
  46976         soc_genreg,
  46977         1,
  46978         0,
  46979         0x85,
  46980         0,
  46981         0,
  46982         2,
  46983         soc_OCB_REG_0085_BCM88650_B0r_fields,
  46984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46985         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  46986         -1,
  46987         -1,
  46988     },
  46989 #endif /* chips */
  46990 
  46991 #if defined(BCM_88660_A0)
  46992     { /* SOC_REG_INT_OCB_REG_0085_BCM88660_A0r */
  46993         soc_block_list[51],
  46994         soc_genreg,
  46995         1,
  46996         0,
  46997         0x85,
  46998         0,
  46999         0,
  47000         2,
  47001         soc_OCB_REG_0085_BCM88660_A0r_fields,
  47002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47003         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  47004         -1,
  47005         -1,
  47006     },
  47007 #endif /* chips */
  47008 
  47009 #if defined(BCM_88202_A0)
  47010     { /* SOC_REG_INT_OCB_REG_0086_BCM88202_A0r */
  47011         soc_block_list[51],
  47012         soc_genreg,
  47013         1,
  47014         0,
  47015         0x86,
  47016         SOC_REG_FLAG_SIGNAL,
  47017         0,
  47018         1,
  47019         soc_OCB_REG_0086_BCM88202_A0r_fields,
  47020         SOC_RESET_VAL_DEC(0x0000003d, 0x00000000)
  47021         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47022         -1,
  47023         -1,
  47024     },
  47025 #endif /* chips */
  47026 
  47027 #if defined(BCM_88650_B0)
  47028     { /* SOC_REG_INT_OCB_REG_0086_BCM88650_B0r */
  47029         soc_block_list[51],
  47030         soc_genreg,
  47031         1,
  47032         0,
  47033         0x86,
  47034         SOC_REG_FLAG_SIGNAL,
  47035         0,
  47036         1,
  47037         soc_OCB_REG_0086_BCM88650_B0r_fields,
  47038         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  47039         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47040         -1,
  47041         -1,
  47042     },
  47043 #endif /* chips */
  47044 
  47045 #if defined(BCM_88660_A0)
  47046     { /* SOC_REG_INT_OCB_REG_0086_BCM88660_A0r */
  47047         soc_block_list[51],
  47048         soc_genreg,
  47049         1,
  47050         0,
  47051         0x86,
  47052         SOC_REG_FLAG_SIGNAL,
  47053         0,
  47054         1,
  47055         soc_OCB_REG_0086_BCM88660_A0r_fields,
  47056         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  47057         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47058         -1,
  47059         -1,
  47060     },
  47061 #endif /* chips */
  47062 
  47063 #if defined(BCM_88202_A0)
  47064     { /* SOC_REG_INT_OCB_REG_0087_BCM88202_A0r */
  47065         soc_block_list[51],
  47066         soc_genreg,
  47067         1,
  47068         0,
  47069         0x87,
  47070         SOC_REG_FLAG_SIGNAL,
  47071         0,
  47072         1,
  47073         soc_OCB_REG_0087_BCM88202_A0r_fields,
  47074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47075         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47076         -1,
  47077         -1,
  47078     },
  47079 #endif /* chips */
  47080 
  47081 #if defined(BCM_88650_B0)
  47082     { /* SOC_REG_INT_OCB_REG_0087_BCM88650_B0r */
  47083         soc_block_list[51],
  47084         soc_genreg,
  47085         1,
  47086         0,
  47087         0x87,
  47088         SOC_REG_FLAG_SIGNAL,
  47089         0,
  47090         1,
  47091         soc_OCB_REG_0087_BCM88650_B0r_fields,
  47092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47093         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47094         -1,
  47095         -1,
  47096     },
  47097 #endif /* chips */
  47098 
  47099 #if defined(BCM_88660_A0)
  47100     { /* SOC_REG_INT_OCB_REG_0087_BCM88660_A0r */
  47101         soc_block_list[51],
  47102         soc_genreg,
  47103         1,
  47104         0,
  47105         0x87,
  47106         SOC_REG_FLAG_SIGNAL,
  47107         0,
  47108         1,
  47109         soc_OCB_REG_0087_BCM88660_A0r_fields,
  47110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47111         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47112         -1,
  47113         -1,
  47114     },
  47115 #endif /* chips */
  47116 
  47117 #if defined(BCM_88202_A0)
  47118     { /* SOC_REG_INT_OCB_REG_0090_BCM88202_A0r */
  47119         soc_block_list[51],
  47120         soc_genreg,
  47121         1,
  47122         0,
  47123         0x90,
  47124         SOC_REG_FLAG_SIGNAL,
  47125         0,
  47126         1,
  47127         soc_OCB_REG_0090_BCM88202_A0r_fields,
  47128         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  47129         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47130         -1,
  47131         -1,
  47132     },
  47133 #endif /* chips */
  47134 
  47135 #if defined(BCM_88650_B0)
  47136     { /* SOC_REG_INT_OCB_REG_0090_BCM88650_B0r */
  47137         soc_block_list[51],
  47138         soc_genreg,
  47139         1,
  47140         0,
  47141         0x90,
  47142         SOC_REG_FLAG_SIGNAL,
  47143         0,
  47144         1,
  47145         soc_OCB_REG_0090_BCM88650_B0r_fields,
  47146         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  47147         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47148         -1,
  47149         -1,
  47150     },
  47151 #endif /* chips */
  47152 
  47153 #if defined(BCM_88660_A0)
  47154     { /* SOC_REG_INT_OCB_REG_0090_BCM88660_A0r */
  47155         soc_block_list[51],
  47156         soc_genreg,
  47157         1,
  47158         0,
  47159         0x90,
  47160         SOC_REG_FLAG_SIGNAL,
  47161         0,
  47162         1,
  47163         soc_OCB_REG_0090_BCM88660_A0r_fields,
  47164         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  47165         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47166         -1,
  47167         -1,
  47168     },
  47169 #endif /* chips */
  47170 
  47171 #if defined(BCM_88202_A0)
  47172     { /* SOC_REG_INT_OCB_REG_0091_BCM88202_A0r */
  47173         soc_block_list[51],
  47174         soc_genreg,
  47175         1,
  47176         0,
  47177         0x91,
  47178         SOC_REG_FLAG_SIGNAL,
  47179         0,
  47180         1,
  47181         soc_OCB_REG_0091_BCM88202_A0r_fields,
  47182         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  47183         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47184         -1,
  47185         -1,
  47186     },
  47187 #endif /* chips */
  47188 
  47189 #if defined(BCM_88650_B0)
  47190     { /* SOC_REG_INT_OCB_REG_0091_BCM88650_B0r */
  47191         soc_block_list[51],
  47192         soc_genreg,
  47193         1,
  47194         0,
  47195         0x91,
  47196         SOC_REG_FLAG_SIGNAL,
  47197         0,
  47198         1,
  47199         soc_OCB_REG_0091_BCM88650_B0r_fields,
  47200         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  47201         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47202         -1,
  47203         -1,
  47204     },
  47205 #endif /* chips */
  47206 
  47207 #if defined(BCM_88660_A0)
  47208     { /* SOC_REG_INT_OCB_REG_0091_BCM88660_A0r */
  47209         soc_block_list[51],
  47210         soc_genreg,
  47211         1,
  47212         0,
  47213         0x91,
  47214         SOC_REG_FLAG_SIGNAL,
  47215         0,
  47216         1,
  47217         soc_OCB_REG_0091_BCM88660_A0r_fields,
  47218         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  47219         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47220         -1,
  47221         -1,
  47222     },
  47223 #endif /* chips */
  47224 
  47225 #if defined(BCM_88202_A0)
  47226     { /* SOC_REG_INT_OCB_REG_0092_BCM88202_A0r */
  47227         soc_block_list[51],
  47228         soc_genreg,
  47229         1,
  47230         0,
  47231         0x92,
  47232         SOC_REG_FLAG_SIGNAL,
  47233         0,
  47234         1,
  47235         soc_OCB_REG_0092_BCM88202_A0r_fields,
  47236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47238         -1,
  47239         -1,
  47240     },
  47241 #endif /* chips */
  47242 
  47243 #if defined(BCM_88650_B0)
  47244     { /* SOC_REG_INT_OCB_REG_0092_BCM88650_B0r */
  47245         soc_block_list[51],
  47246         soc_genreg,
  47247         1,
  47248         0,
  47249         0x92,
  47250         SOC_REG_FLAG_SIGNAL,
  47251         0,
  47252         1,
  47253         soc_OCB_REG_0092_BCM88650_B0r_fields,
  47254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47255         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47256         -1,
  47257         -1,
  47258     },
  47259 #endif /* chips */
  47260 
  47261 #if defined(BCM_88660_A0)
  47262     { /* SOC_REG_INT_OCB_REG_0092_BCM88660_A0r */
  47263         soc_block_list[51],
  47264         soc_genreg,
  47265         1,
  47266         0,
  47267         0x92,
  47268         SOC_REG_FLAG_SIGNAL,
  47269         0,
  47270         1,
  47271         soc_OCB_REG_0092_BCM88660_A0r_fields,
  47272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47273         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47274         -1,
  47275         -1,
  47276     },
  47277 #endif /* chips */
  47278 
  47279 #if defined(BCM_88202_A0)
  47280     { /* SOC_REG_INT_OCB_REG_0093_BCM88202_A0r */
  47281         soc_block_list[51],
  47282         soc_genreg,
  47283         1,
  47284         0,
  47285         0x93,
  47286         SOC_REG_FLAG_SIGNAL,
  47287         0,
  47288         1,
  47289         soc_OCB_REG_0093_BCM88202_A0r_fields,
  47290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47291         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47292         -1,
  47293         -1,
  47294     },
  47295 #endif /* chips */
  47296 
  47297 #if defined(BCM_88650_B0)
  47298     { /* SOC_REG_INT_OCB_REG_0093_BCM88650_B0r */
  47299         soc_block_list[51],
  47300         soc_genreg,
  47301         1,
  47302         0,
  47303         0x93,
  47304         SOC_REG_FLAG_SIGNAL,
  47305         0,
  47306         1,
  47307         soc_OCB_REG_0093_BCM88650_B0r_fields,
  47308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47309         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47310         -1,
  47311         -1,
  47312     },
  47313 #endif /* chips */
  47314 
  47315 #if defined(BCM_88660_A0)
  47316     { /* SOC_REG_INT_OCB_REG_0093_BCM88660_A0r */
  47317         soc_block_list[51],
  47318         soc_genreg,
  47319         1,
  47320         0,
  47321         0x93,
  47322         SOC_REG_FLAG_SIGNAL,
  47323         0,
  47324         1,
  47325         soc_OCB_REG_0093_BCM88660_A0r_fields,
  47326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47327         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47328         -1,
  47329         -1,
  47330     },
  47331 #endif /* chips */
  47332 
  47333 #if defined(BCM_88690_A0)
  47334     { /* SOC_REG_INT_OCB_REG_00A4r */
  47335         soc_block_list[51],
  47336         soc_genreg,
  47337         1,
  47338         0,
  47339         0xa4,
  47340         SOC_REG_FLAG_64_BITS,
  47341         0,
  47342         49,
  47343         soc_OCB_REG_00A4r_fields,
  47344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47345         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  47346         -1,
  47347         -1,
  47348     },
  47349 #endif /* chips */
  47350 
  47351 #if defined(BCM_88690_A0)
  47352     { /* SOC_REG_INT_OCB_REG_00A6r */
  47353         soc_block_list[51],
  47354         soc_genreg,
  47355         1,
  47356         0,
  47357         0xa6,
  47358         SOC_REG_FLAG_64_BITS,
  47359         0,
  47360         49,
  47361         soc_OCB_REG_00A6r_fields,
  47362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47363         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  47364         -1,
  47365         -1,
  47366     },
  47367 #endif /* chips */
  47368 
  47369 #if defined(BCM_88650_A0)
  47370     { /* SOC_REG_INT_OCB_REG_00AFr */
  47371         soc_block_list[51],
  47372         soc_genreg,
  47373         1,
  47374         0,
  47375         0xaf,
  47376         SOC_REG_FLAG_SIGNAL,
  47377         0,
  47378         6,
  47379         soc_OCB_REG_00AFr_fields,
  47380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47381         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  47382         -1,
  47383         -1,
  47384     },
  47385 #endif /* chips */
  47386 
  47387 #if defined(BCM_88202_A0)
  47388     { /* SOC_REG_INT_OCB_REG_00AF_BCM88202_A0r */
  47389         soc_block_list[51],
  47390         soc_genreg,
  47391         1,
  47392         0,
  47393         0xaf,
  47394         SOC_REG_FLAG_64_BITS |
  47395                           SOC_REG_FLAG_SIGNAL,
  47396         0,
  47397         6,
  47398         soc_OCB_REG_00AF_BCM88202_A0r_fields,
  47399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47400         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  47401         -1,
  47402         -1,
  47403     },
  47404 #endif /* chips */
  47405 
  47406 #if defined(BCM_88650_B0)
  47407     { /* SOC_REG_INT_OCB_REG_00AF_BCM88650_B0r */
  47408         soc_block_list[51],
  47409         soc_genreg,
  47410         1,
  47411         0,
  47412         0xaf,
  47413         SOC_REG_FLAG_SIGNAL,
  47414         0,
  47415         6,
  47416         soc_OCB_REG_00AF_BCM88650_B0r_fields,
  47417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47418         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  47419         -1,
  47420         -1,
  47421     },
  47422 #endif /* chips */
  47423 
  47424 #if defined(BCM_88660_A0)
  47425     { /* SOC_REG_INT_OCB_REG_00AF_BCM88660_A0r */
  47426         soc_block_list[51],
  47427         soc_genreg,
  47428         1,
  47429         0,
  47430         0xaf,
  47431         SOC_REG_FLAG_SIGNAL,
  47432         0,
  47433         6,
  47434         soc_OCB_REG_00AF_BCM88660_A0r_fields,
  47435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47436         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  47437         -1,
  47438         -1,
  47439     },
  47440 #endif /* chips */
  47441 
  47442 #if defined(BCM_88650_A0)
  47443     { /* SOC_REG_INT_OCB_REG_00B4r */
  47444         soc_block_list[51],
  47445         soc_genreg,
  47446         1,
  47447         0,
  47448         0xb4,
  47449         0,
  47450         0,
  47451         1,
  47452         soc_OCB_REG_00B4r_fields,
  47453         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  47454         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47455         -1,
  47456         -1,
  47457     },
  47458 #endif /* chips */
  47459 
  47460 #if defined(BCM_88650_A0)
  47461     { /* SOC_REG_INT_OCB_REG_00B5r */
  47462         soc_block_list[51],
  47463         soc_genreg,
  47464         1,
  47465         0,
  47466         0xb5,
  47467         SOC_REG_FLAG_RO,
  47468         0,
  47469         3,
  47470         soc_OCB_REG_00B5r_fields,
  47471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47472         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47473         -1,
  47474         -1,
  47475     },
  47476 #endif /* chips */
  47477 
  47478 #if defined(BCM_88650_A0)
  47479     { /* SOC_REG_INT_OCB_REG_00B6r */
  47480         soc_block_list[51],
  47481         soc_genreg,
  47482         1,
  47483         0,
  47484         0xb6,
  47485         0,
  47486         0,
  47487         1,
  47488         soc_OCB_REG_00B6r_fields,
  47489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47490         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  47491         -1,
  47492         -1,
  47493     },
  47494 #endif /* chips */
  47495 
  47496 #if defined(BCM_88650_A0)
  47497     { /* SOC_REG_INT_OCB_REG_00B7r */
  47498         soc_block_list[51],
  47499         soc_genreg,
  47500         1,
  47501         0,
  47502         0xb7,
  47503         SOC_REG_FLAG_RO,
  47504         0,
  47505         1,
  47506         soc_OCB_REG_00B7r_fields,
  47507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47508         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47509         -1,
  47510         -1,
  47511     },
  47512 #endif /* chips */
  47513 
  47514 #if defined(BCM_88202_A0)
  47515     { /* SOC_REG_INT_OCB_REG_00B4_BCM88202_A0r */
  47516         soc_block_list[51],
  47517         soc_genreg,
  47518         1,
  47519         0,
  47520         0xb4,
  47521         0,
  47522         0,
  47523         1,
  47524         soc_OCB_REG_00B4_BCM88202_A0r_fields,
  47525         SOC_RESET_VAL_DEC(0x1ad27480, 0x00000000)
  47526         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47527         -1,
  47528         -1,
  47529     },
  47530 #endif /* chips */
  47531 
  47532 #if defined(BCM_88650_B0)
  47533     { /* SOC_REG_INT_OCB_REG_00B4_BCM88650_B0r */
  47534         soc_block_list[51],
  47535         soc_genreg,
  47536         1,
  47537         0,
  47538         0xb4,
  47539         0,
  47540         0,
  47541         1,
  47542         soc_OCB_REG_00B4_BCM88650_B0r_fields,
  47543         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  47544         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47545         -1,
  47546         -1,
  47547     },
  47548 #endif /* chips */
  47549 
  47550 #if defined(BCM_88660_A0)
  47551     { /* SOC_REG_INT_OCB_REG_00B4_BCM88660_A0r */
  47552         soc_block_list[51],
  47553         soc_genreg,
  47554         1,
  47555         0,
  47556         0xb4,
  47557         0,
  47558         0,
  47559         1,
  47560         soc_OCB_REG_00B4_BCM88660_A0r_fields,
  47561         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  47562         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47563         -1,
  47564         -1,
  47565     },
  47566 #endif /* chips */
  47567 
  47568 #if defined(BCM_88202_A0)
  47569     { /* SOC_REG_INT_OCB_REG_00B5_BCM88202_A0r */
  47570         soc_block_list[51],
  47571         soc_genreg,
  47572         1,
  47573         0,
  47574         0xb5,
  47575         SOC_REG_FLAG_RO,
  47576         0,
  47577         3,
  47578         soc_OCB_REG_00B5_BCM88202_A0r_fields,
  47579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47580         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47581         -1,
  47582         -1,
  47583     },
  47584 #endif /* chips */
  47585 
  47586 #if defined(BCM_88650_B0)
  47587     { /* SOC_REG_INT_OCB_REG_00B5_BCM88650_B0r */
  47588         soc_block_list[51],
  47589         soc_genreg,
  47590         1,
  47591         0,
  47592         0xb5,
  47593         SOC_REG_FLAG_RO,
  47594         0,
  47595         3,
  47596         soc_OCB_REG_00B5_BCM88650_B0r_fields,
  47597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47598         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47599         -1,
  47600         -1,
  47601     },
  47602 #endif /* chips */
  47603 
  47604 #if defined(BCM_88660_A0)
  47605     { /* SOC_REG_INT_OCB_REG_00B5_BCM88660_A0r */
  47606         soc_block_list[51],
  47607         soc_genreg,
  47608         1,
  47609         0,
  47610         0xb5,
  47611         SOC_REG_FLAG_RO,
  47612         0,
  47613         3,
  47614         soc_OCB_REG_00B5_BCM88660_A0r_fields,
  47615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47616         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47617         -1,
  47618         -1,
  47619     },
  47620 #endif /* chips */
  47621 
  47622 #if defined(BCM_88202_A0)
  47623     { /* SOC_REG_INT_OCB_REG_00B6_BCM88202_A0r */
  47624         soc_block_list[51],
  47625         soc_genreg,
  47626         1,
  47627         0,
  47628         0xb6,
  47629         0,
  47630         0,
  47631         1,
  47632         soc_OCB_REG_00B6_BCM88202_A0r_fields,
  47633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47634         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  47635         -1,
  47636         -1,
  47637     },
  47638 #endif /* chips */
  47639 
  47640 #if defined(BCM_88650_B0)
  47641     { /* SOC_REG_INT_OCB_REG_00B6_BCM88650_B0r */
  47642         soc_block_list[51],
  47643         soc_genreg,
  47644         1,
  47645         0,
  47646         0xb6,
  47647         0,
  47648         0,
  47649         1,
  47650         soc_OCB_REG_00B6_BCM88650_B0r_fields,
  47651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47652         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  47653         -1,
  47654         -1,
  47655     },
  47656 #endif /* chips */
  47657 
  47658 #if defined(BCM_88660_A0)
  47659     { /* SOC_REG_INT_OCB_REG_00B6_BCM88660_A0r */
  47660         soc_block_list[51],
  47661         soc_genreg,
  47662         1,
  47663         0,
  47664         0xb6,
  47665         0,
  47666         0,
  47667         1,
  47668         soc_OCB_REG_00B6_BCM88660_A0r_fields,
  47669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47670         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  47671         -1,
  47672         -1,
  47673     },
  47674 #endif /* chips */
  47675 
  47676 #if defined(BCM_88202_A0)
  47677     { /* SOC_REG_INT_OCB_REG_00B7_BCM88202_A0r */
  47678         soc_block_list[51],
  47679         soc_genreg,
  47680         1,
  47681         0,
  47682         0xb7,
  47683         SOC_REG_FLAG_RO,
  47684         0,
  47685         1,
  47686         soc_OCB_REG_00B7_BCM88202_A0r_fields,
  47687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47688         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47689         -1,
  47690         -1,
  47691     },
  47692 #endif /* chips */
  47693 
  47694 #if defined(BCM_88650_B0)
  47695     { /* SOC_REG_INT_OCB_REG_00B7_BCM88650_B0r */
  47696         soc_block_list[51],
  47697         soc_genreg,
  47698         1,
  47699         0,
  47700         0xb7,
  47701         SOC_REG_FLAG_RO,
  47702         0,
  47703         1,
  47704         soc_OCB_REG_00B7_BCM88650_B0r_fields,
  47705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47706         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47707         -1,
  47708         -1,
  47709     },
  47710 #endif /* chips */
  47711 
  47712 #if defined(BCM_88660_A0)
  47713     { /* SOC_REG_INT_OCB_REG_00B7_BCM88660_A0r */
  47714         soc_block_list[51],
  47715         soc_genreg,
  47716         1,
  47717         0,
  47718         0xb7,
  47719         SOC_REG_FLAG_RO,
  47720         0,
  47721         1,
  47722         soc_OCB_REG_00B7_BCM88660_A0r_fields,
  47723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47724         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47725         -1,
  47726         -1,
  47727     },
  47728 #endif /* chips */
  47729 
  47730 #if defined(BCM_88650_A0)
  47731     { /* SOC_REG_INT_OCB_REG_00C1r */
  47732         soc_block_list[51],
  47733         soc_genreg,
  47734         1,
  47735         0,
  47736         0xc1,
  47737         0,
  47738         0,
  47739         1,
  47740         soc_OCB_REG_00C1r_fields,
  47741         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  47742         SOC_RESET_MASK_DEC(0x00000040, 0x00000000)
  47743         -1,
  47744         -1,
  47745     },
  47746 #endif /* chips */
  47747 
  47748 #if defined(BCM_88690_A0)
  47749     { /* SOC_REG_INT_OCB_REG_00C2r */
  47750         soc_block_list[51],
  47751         soc_genreg,
  47752         1,
  47753         0,
  47754         0xc2,
  47755         0,
  47756         0,
  47757         6,
  47758         soc_OCB_REG_00C2r_fields,
  47759         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  47760         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47761         -1,
  47762         -1,
  47763     },
  47764 #endif /* chips */
  47765 
  47766 #if defined(BCM_88650_B0)
  47767     { /* SOC_REG_INT_OCB_REG_00C1_BCM88650_B0r */
  47768         soc_block_list[51],
  47769         soc_genreg,
  47770         1,
  47771         0,
  47772         0xc1,
  47773         0,
  47774         0,
  47775         1,
  47776         soc_OCB_REG_00C1_BCM88650_B0r_fields,
  47777         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  47778         SOC_RESET_MASK_DEC(0x00000040, 0x00000000)
  47779         -1,
  47780         -1,
  47781     },
  47782 #endif /* chips */
  47783 
  47784 #if defined(BCM_88690_B0)
  47785     { /* SOC_REG_INT_OCB_REG_00C2_BCM88690_B0r */
  47786         soc_block_list[51],
  47787         soc_genreg,
  47788         1,
  47789         0,
  47790         0xc2,
  47791         0,
  47792         0,
  47793         6,
  47794         soc_OCB_REG_00C2_BCM88690_B0r_fields,
  47795         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  47796         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47797         -1,
  47798         -1,
  47799     },
  47800 #endif /* chips */
  47801 
  47802 #if defined(BCM_88650_A0)
  47803     { /* SOC_REG_INT_OCB_REG_00CFr */
  47804         soc_block_list[51],
  47805         soc_genreg,
  47806         1,
  47807         0,
  47808         0xcf,
  47809         0,
  47810         0,
  47811         1,
  47812         soc_OCB_REG_00CFr_fields,
  47813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47814         SOC_RESET_MASK_DEC(0x00004000, 0x00000000)
  47815         -1,
  47816         -1,
  47817     },
  47818 #endif /* chips */
  47819 
  47820 #if defined(BCM_88650_B0)
  47821     { /* SOC_REG_INT_OCB_REG_00CF_BCM88650_B0r */
  47822         soc_block_list[51],
  47823         soc_genreg,
  47824         1,
  47825         0,
  47826         0xcf,
  47827         0,
  47828         0,
  47829         1,
  47830         soc_OCB_REG_00CF_BCM88650_B0r_fields,
  47831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47832         SOC_RESET_MASK_DEC(0x00004000, 0x00000000)
  47833         -1,
  47834         -1,
  47835     },
  47836 #endif /* chips */
  47837 
  47838 #if defined(BCM_88675_A0)
  47839     { /* SOC_REG_INT_OCB_RESERVED_MIRROR_ADDRr */
  47840         soc_block_list[51],
  47841         soc_genreg,
  47842         1,
  47843         0,
  47844         0x85,
  47845         0,
  47846         0,
  47847         2,
  47848         soc_OCB_RESERVED_MIRROR_ADDRr_fields,
  47849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47850         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  47851         -1,
  47852         -1,
  47853     },
  47854 #endif /* chips */
  47855 
  47856 #if defined(BCM_88375_A0)
  47857     { /* SOC_REG_INT_OCB_RESERVED_MIRROR_ADDR_BCM88375_A0r */
  47858         soc_block_list[51],
  47859         soc_genreg,
  47860         1,
  47861         0,
  47862         0x85,
  47863         0,
  47864         0,
  47865         2,
  47866         soc_OCB_RESERVED_MIRROR_ADDR_BCM88375_A0r_fields,
  47867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47868         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  47869         -1,
  47870         -1,
  47871     },
  47872 #endif /* chips */
  47873 
  47874 #if defined(BCM_88375_B0)
  47875     { /* SOC_REG_INT_OCB_RESERVED_MIRROR_ADDR_BCM88375_B0r */
  47876         soc_block_list[51],
  47877         soc_genreg,
  47878         1,
  47879         0,
  47880         0x85,
  47881         0,
  47882         0,
  47883         2,
  47884         soc_OCB_RESERVED_MIRROR_ADDR_BCM88375_B0r_fields,
  47885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47886         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  47887         -1,
  47888         -1,
  47889     },
  47890 #endif /* chips */
  47891 
  47892 #if defined(BCM_88675_B0)
  47893     { /* SOC_REG_INT_OCB_RESERVED_MIRROR_ADDR_BCM88675_B0r */
  47894         soc_block_list[51],
  47895         soc_genreg,
  47896         1,
  47897         0,
  47898         0x85,
  47899         0,
  47900         0,
  47901         2,
  47902         soc_OCB_RESERVED_MIRROR_ADDR_BCM88675_B0r_fields,
  47903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47904         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  47905         -1,
  47906         -1,
  47907     },
  47908 #endif /* chips */
  47909 
  47910 #if defined(BCM_88680_A0)
  47911     { /* SOC_REG_INT_OCB_RESERVED_MIRROR_ADDR_BCM88680_A0r */
  47912         soc_block_list[51],
  47913         soc_genreg,
  47914         1,
  47915         0,
  47916         0x85,
  47917         0,
  47918         0,
  47919         2,
  47920         soc_OCB_RESERVED_MIRROR_ADDR_BCM88680_A0r_fields,
  47921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47922         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  47923         -1,
  47924         -1,
  47925     },
  47926 #endif /* chips */
  47927 
  47928 #if defined(BCM_88690_A0)
  47929     { /* SOC_REG_INT_OCB_RESERVED_MIRROR_ADDR_BCM88690_A0r */
  47930         soc_block_list[51],
  47931         soc_genreg,
  47932         1,
  47933         0,
  47934         0x85,
  47935         0,
  47936         0,
  47937         2,
  47938         soc_OCB_RESERVED_MIRROR_ADDR_BCM88690_A0r_fields,
  47939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47940         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  47941         -1,
  47942         -1,
  47943     },
  47944 #endif /* chips */
  47945 
  47946 #if defined(BCM_88690_B0)
  47947     { /* SOC_REG_INT_OCB_RESERVED_MIRROR_ADDR_BCM88690_B0r */
  47948         soc_block_list[51],
  47949         soc_genreg,
  47950         1,
  47951         0,
  47952         0x85,
  47953         0,
  47954         0,
  47955         2,
  47956         soc_OCB_RESERVED_MIRROR_ADDR_BCM88690_B0r_fields,
  47957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47958         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  47959         -1,
  47960         -1,
  47961     },
  47962 #endif /* chips */
  47963 
  47964 #if defined(BCM_88675_A0)
  47965     { /* SOC_REG_INT_OCB_RESERVED_MTCDr */
  47966         soc_block_list[51],
  47967         soc_genreg,
  47968         1,
  47969         0,
  47970         0xae,
  47971         0,
  47972         0,
  47973         6,
  47974         soc_OCB_RESERVED_MTCDr_fields,
  47975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47976         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47977         -1,
  47978         -1,
  47979     },
  47980 #endif /* chips */
  47981 
  47982 #if defined(BCM_88375_A0)
  47983     { /* SOC_REG_INT_OCB_RESERVED_MTCD_BCM88375_A0r */
  47984         soc_block_list[51],
  47985         soc_genreg,
  47986         1,
  47987         0,
  47988         0xae,
  47989         0,
  47990         0,
  47991         6,
  47992         soc_OCB_RESERVED_MTCD_BCM88375_A0r_fields,
  47993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47994         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47995         -1,
  47996         -1,
  47997     },
  47998 #endif /* chips */
  47999 
  48000 #if defined(BCM_88375_B0)
  48001     { /* SOC_REG_INT_OCB_RESERVED_MTCD_BCM88375_B0r */
  48002         soc_block_list[51],
  48003         soc_genreg,
  48004         1,
  48005         0,
  48006         0xae,
  48007         0,
  48008         0,
  48009         6,
  48010         soc_OCB_RESERVED_MTCD_BCM88375_B0r_fields,
  48011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48012         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  48013         -1,
  48014         -1,
  48015     },
  48016 #endif /* chips */
  48017 
  48018 #if defined(BCM_88675_B0)
  48019     { /* SOC_REG_INT_OCB_RESERVED_MTCD_BCM88675_B0r */
  48020         soc_block_list[51],
  48021         soc_genreg,
  48022         1,
  48023         0,
  48024         0xae,
  48025         0,
  48026         0,
  48027         6,
  48028         soc_OCB_RESERVED_MTCD_BCM88675_B0r_fields,
  48029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48030         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  48031         -1,
  48032         -1,
  48033     },
  48034 #endif /* chips */
  48035 
  48036 #if defined(BCM_88680_A0)
  48037     { /* SOC_REG_INT_OCB_RESERVED_MTCD_BCM88680_A0r */
  48038         soc_block_list[51],
  48039         soc_genreg,
  48040         1,
  48041         0,
  48042         0xae,
  48043         0,
  48044         0,
  48045         6,
  48046         soc_OCB_RESERVED_MTCD_BCM88680_A0r_fields,
  48047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48048         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  48049         -1,
  48050         -1,
  48051     },
  48052 #endif /* chips */
  48053 
  48054 #if defined(BCM_88690_A0)
  48055     { /* SOC_REG_INT_OCB_RESERVED_MTCD_BCM88690_A0r */
  48056         soc_block_list[51],
  48057         soc_genreg,
  48058         1,
  48059         0,
  48060         0xae,
  48061         0,
  48062         0,
  48063         6,
  48064         soc_OCB_RESERVED_MTCD_BCM88690_A0r_fields,
  48065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48066         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  48067         -1,
  48068         -1,
  48069     },
  48070 #endif /* chips */
  48071 
  48072 #if defined(BCM_88690_B0)
  48073     { /* SOC_REG_INT_OCB_RESERVED_MTCD_BCM88690_B0r */
  48074         soc_block_list[51],
  48075         soc_genreg,
  48076         1,
  48077         0,
  48078         0xae,
  48079         0,
  48080         0,
  48081         6,
  48082         soc_OCB_RESERVED_MTCD_BCM88690_B0r_fields,
  48083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48084         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  48085         -1,
  48086         -1,
  48087     },
  48088 #endif /* chips */
  48089 
  48090 #if defined(BCM_88675_A0)
  48091     { /* SOC_REG_INT_OCB_RESERVED_MTCPr */
  48092         soc_block_list[51],
  48093         soc_genreg,
  48094         1,
  48095         0,
  48096         0xad,
  48097         SOC_REG_FLAG_64_BITS,
  48098         0,
  48099         17,
  48100         soc_OCB_RESERVED_MTCPr_fields,
  48101         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  48102         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  48103         -1,
  48104         -1,
  48105     },
  48106 #endif /* chips */
  48107 
  48108 #if defined(BCM_88375_A0)
  48109     { /* SOC_REG_INT_OCB_RESERVED_MTCP_BCM88375_A0r */
  48110         soc_block_list[51],
  48111         soc_genreg,
  48112         1,
  48113         0,
  48114         0xad,
  48115         SOC_REG_FLAG_64_BITS,
  48116         0,
  48117         17,
  48118         soc_OCB_RESERVED_MTCP_BCM88375_A0r_fields,
  48119         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  48120         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  48121         -1,
  48122         -1,
  48123     },
  48124 #endif /* chips */
  48125 
  48126 #if defined(BCM_88375_B0)
  48127     { /* SOC_REG_INT_OCB_RESERVED_MTCP_BCM88375_B0r */
  48128         soc_block_list[51],
  48129         soc_genreg,
  48130         1,
  48131         0,
  48132         0xad,
  48133         SOC_REG_FLAG_64_BITS,
  48134         0,
  48135         17,
  48136         soc_OCB_RESERVED_MTCP_BCM88375_B0r_fields,
  48137         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  48138         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  48139         -1,
  48140         -1,
  48141     },
  48142 #endif /* chips */
  48143 
  48144 #if defined(BCM_88675_B0)
  48145     { /* SOC_REG_INT_OCB_RESERVED_MTCP_BCM88675_B0r */
  48146         soc_block_list[51],
  48147         soc_genreg,
  48148         1,
  48149         0,
  48150         0xad,
  48151         SOC_REG_FLAG_64_BITS,
  48152         0,
  48153         17,
  48154         soc_OCB_RESERVED_MTCP_BCM88675_B0r_fields,
  48155         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  48156         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  48157         -1,
  48158         -1,
  48159     },
  48160 #endif /* chips */
  48161 
  48162 #if defined(BCM_88680_A0)
  48163     { /* SOC_REG_INT_OCB_RESERVED_MTCP_BCM88680_A0r */
  48164         soc_block_list[51],
  48165         soc_genreg,
  48166         1,
  48167         0,
  48168         0xad,
  48169         SOC_REG_FLAG_64_BITS,
  48170         0,
  48171         17,
  48172         soc_OCB_RESERVED_MTCP_BCM88680_A0r_fields,
  48173         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  48174         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  48175         -1,
  48176         -1,
  48177     },
  48178 #endif /* chips */
  48179 
  48180 #if defined(BCM_88690_A0)
  48181     { /* SOC_REG_INT_OCB_RESERVED_MTCP_BCM88690_A0r */
  48182         soc_block_list[51],
  48183         soc_genreg,
  48184         1,
  48185         0,
  48186         0xad,
  48187         SOC_REG_FLAG_64_BITS,
  48188         0,
  48189         17,
  48190         soc_OCB_RESERVED_MTCP_BCM88690_A0r_fields,
  48191         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  48192         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  48193         -1,
  48194         -1,
  48195     },
  48196 #endif /* chips */
  48197 
  48198 #if defined(BCM_88690_B0)
  48199     { /* SOC_REG_INT_OCB_RESERVED_MTCP_BCM88690_B0r */
  48200         soc_block_list[51],
  48201         soc_genreg,
  48202         1,
  48203         0,
  48204         0xad,
  48205         SOC_REG_FLAG_64_BITS,
  48206         0,
  48207         17,
  48208         soc_OCB_RESERVED_MTCP_BCM88690_B0r_fields,
  48209         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  48210         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  48211         -1,
  48212         -1,
  48213     },
  48214 #endif /* chips */
  48215 
  48216 #if defined(BCM_88675_A0)
  48217     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0r */
  48218         soc_block_list[51],
  48219         soc_genreg,
  48220         1,
  48221         0,
  48222         0xb0,
  48223         0,
  48224         0,
  48225         1,
  48226         soc_OCB_RESERVED_PCMI_0r_fields,
  48227         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48228         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48229         -1,
  48230         -1,
  48231     },
  48232 #endif /* chips */
  48233 
  48234 #if defined(BCM_88675_A0)
  48235     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1r */
  48236         soc_block_list[51],
  48237         soc_genreg,
  48238         1,
  48239         0,
  48240         0xb3,
  48241         0,
  48242         0,
  48243         1,
  48244         soc_OCB_RESERVED_PCMI_1r_fields,
  48245         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48246         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48247         -1,
  48248         -1,
  48249     },
  48250 #endif /* chips */
  48251 
  48252 #if defined(BCM_88675_A0)
  48253     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2r */
  48254         soc_block_list[51],
  48255         soc_genreg,
  48256         1,
  48257         0,
  48258         0xb6,
  48259         0,
  48260         0,
  48261         1,
  48262         soc_OCB_RESERVED_PCMI_2r_fields,
  48263         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48264         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48265         -1,
  48266         -1,
  48267     },
  48268 #endif /* chips */
  48269 
  48270 #if defined(BCM_88675_A0)
  48271     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3r */
  48272         soc_block_list[51],
  48273         soc_genreg,
  48274         1,
  48275         0,
  48276         0xb9,
  48277         0,
  48278         0,
  48279         1,
  48280         soc_OCB_RESERVED_PCMI_3r_fields,
  48281         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48282         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48283         -1,
  48284         -1,
  48285     },
  48286 #endif /* chips */
  48287 
  48288 #if defined(BCM_88675_A0)
  48289     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4r */
  48290         soc_block_list[51],
  48291         soc_genreg,
  48292         1,
  48293         0,
  48294         0xbc,
  48295         0,
  48296         0,
  48297         1,
  48298         soc_OCB_RESERVED_PCMI_4r_fields,
  48299         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48300         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48301         -1,
  48302         -1,
  48303     },
  48304 #endif /* chips */
  48305 
  48306 #if defined(BCM_88375_A0)
  48307     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_BCM88375_A0r */
  48308         soc_block_list[51],
  48309         soc_genreg,
  48310         1,
  48311         0,
  48312         0xb0,
  48313         0,
  48314         0,
  48315         1,
  48316         soc_OCB_RESERVED_PCMI_0_BCM88375_A0r_fields,
  48317         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48318         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48319         -1,
  48320         -1,
  48321     },
  48322 #endif /* chips */
  48323 
  48324 #if defined(BCM_88375_B0)
  48325     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_BCM88375_B0r */
  48326         soc_block_list[51],
  48327         soc_genreg,
  48328         1,
  48329         0,
  48330         0xb0,
  48331         0,
  48332         0,
  48333         1,
  48334         soc_OCB_RESERVED_PCMI_0_BCM88375_B0r_fields,
  48335         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48336         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48337         -1,
  48338         -1,
  48339     },
  48340 #endif /* chips */
  48341 
  48342 #if defined(BCM_88675_B0)
  48343     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_BCM88675_B0r */
  48344         soc_block_list[51],
  48345         soc_genreg,
  48346         1,
  48347         0,
  48348         0xb0,
  48349         0,
  48350         0,
  48351         1,
  48352         soc_OCB_RESERVED_PCMI_0_BCM88675_B0r_fields,
  48353         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48354         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48355         -1,
  48356         -1,
  48357     },
  48358 #endif /* chips */
  48359 
  48360 #if defined(BCM_88680_A0)
  48361     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_BCM88680_A0r */
  48362         soc_block_list[51],
  48363         soc_genreg,
  48364         1,
  48365         0,
  48366         0xb0,
  48367         0,
  48368         0,
  48369         1,
  48370         soc_OCB_RESERVED_PCMI_0_BCM88680_A0r_fields,
  48371         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48372         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48373         -1,
  48374         -1,
  48375     },
  48376 #endif /* chips */
  48377 
  48378 #if defined(BCM_88675_A0)
  48379     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_Sr */
  48380         soc_block_list[51],
  48381         soc_genreg,
  48382         1,
  48383         0,
  48384         0xb1,
  48385         SOC_REG_FLAG_RO,
  48386         0,
  48387         3,
  48388         soc_OCB_RESERVED_PCMI_0_Sr_fields,
  48389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48390         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48391         -1,
  48392         -1,
  48393     },
  48394 #endif /* chips */
  48395 
  48396 #if defined(BCM_88375_A0)
  48397     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_S_BCM88375_A0r */
  48398         soc_block_list[51],
  48399         soc_genreg,
  48400         1,
  48401         0,
  48402         0xb1,
  48403         SOC_REG_FLAG_RO,
  48404         0,
  48405         3,
  48406         soc_OCB_RESERVED_PCMI_0_S_BCM88375_A0r_fields,
  48407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48408         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48409         -1,
  48410         -1,
  48411     },
  48412 #endif /* chips */
  48413 
  48414 #if defined(BCM_88375_B0)
  48415     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_S_BCM88375_B0r */
  48416         soc_block_list[51],
  48417         soc_genreg,
  48418         1,
  48419         0,
  48420         0xb1,
  48421         SOC_REG_FLAG_RO,
  48422         0,
  48423         3,
  48424         soc_OCB_RESERVED_PCMI_0_S_BCM88375_B0r_fields,
  48425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48426         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48427         -1,
  48428         -1,
  48429     },
  48430 #endif /* chips */
  48431 
  48432 #if defined(BCM_88675_B0)
  48433     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_S_BCM88675_B0r */
  48434         soc_block_list[51],
  48435         soc_genreg,
  48436         1,
  48437         0,
  48438         0xb1,
  48439         SOC_REG_FLAG_RO,
  48440         0,
  48441         3,
  48442         soc_OCB_RESERVED_PCMI_0_S_BCM88675_B0r_fields,
  48443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48444         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48445         -1,
  48446         -1,
  48447     },
  48448 #endif /* chips */
  48449 
  48450 #if defined(BCM_88680_A0)
  48451     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_S_BCM88680_A0r */
  48452         soc_block_list[51],
  48453         soc_genreg,
  48454         1,
  48455         0,
  48456         0xb1,
  48457         SOC_REG_FLAG_RO,
  48458         0,
  48459         3,
  48460         soc_OCB_RESERVED_PCMI_0_S_BCM88680_A0r_fields,
  48461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48462         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48463         -1,
  48464         -1,
  48465     },
  48466 #endif /* chips */
  48467 
  48468 #if defined(BCM_88675_A0)
  48469     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_Tr */
  48470         soc_block_list[51],
  48471         soc_genreg,
  48472         1,
  48473         0,
  48474         0xb2,
  48475         0,
  48476         0,
  48477         2,
  48478         soc_OCB_RESERVED_PCMI_0_Tr_fields,
  48479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48480         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48481         -1,
  48482         -1,
  48483     },
  48484 #endif /* chips */
  48485 
  48486 #if defined(BCM_88375_A0)
  48487     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_T_BCM88375_A0r */
  48488         soc_block_list[51],
  48489         soc_genreg,
  48490         1,
  48491         0,
  48492         0xb2,
  48493         0,
  48494         0,
  48495         2,
  48496         soc_OCB_RESERVED_PCMI_0_T_BCM88375_A0r_fields,
  48497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48498         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48499         -1,
  48500         -1,
  48501     },
  48502 #endif /* chips */
  48503 
  48504 #if defined(BCM_88375_B0)
  48505     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_T_BCM88375_B0r */
  48506         soc_block_list[51],
  48507         soc_genreg,
  48508         1,
  48509         0,
  48510         0xb2,
  48511         0,
  48512         0,
  48513         2,
  48514         soc_OCB_RESERVED_PCMI_0_T_BCM88375_B0r_fields,
  48515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48516         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48517         -1,
  48518         -1,
  48519     },
  48520 #endif /* chips */
  48521 
  48522 #if defined(BCM_88675_B0)
  48523     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_T_BCM88675_B0r */
  48524         soc_block_list[51],
  48525         soc_genreg,
  48526         1,
  48527         0,
  48528         0xb2,
  48529         0,
  48530         0,
  48531         2,
  48532         soc_OCB_RESERVED_PCMI_0_T_BCM88675_B0r_fields,
  48533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48534         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48535         -1,
  48536         -1,
  48537     },
  48538 #endif /* chips */
  48539 
  48540 #if defined(BCM_88680_A0)
  48541     { /* SOC_REG_INT_OCB_RESERVED_PCMI_0_T_BCM88680_A0r */
  48542         soc_block_list[51],
  48543         soc_genreg,
  48544         1,
  48545         0,
  48546         0xb2,
  48547         0,
  48548         0,
  48549         2,
  48550         soc_OCB_RESERVED_PCMI_0_T_BCM88680_A0r_fields,
  48551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48552         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48553         -1,
  48554         -1,
  48555     },
  48556 #endif /* chips */
  48557 
  48558 #if defined(BCM_88375_A0)
  48559     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_BCM88375_A0r */
  48560         soc_block_list[51],
  48561         soc_genreg,
  48562         1,
  48563         0,
  48564         0xb3,
  48565         0,
  48566         0,
  48567         1,
  48568         soc_OCB_RESERVED_PCMI_1_BCM88375_A0r_fields,
  48569         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48570         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48571         -1,
  48572         -1,
  48573     },
  48574 #endif /* chips */
  48575 
  48576 #if defined(BCM_88375_B0)
  48577     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_BCM88375_B0r */
  48578         soc_block_list[51],
  48579         soc_genreg,
  48580         1,
  48581         0,
  48582         0xb3,
  48583         0,
  48584         0,
  48585         1,
  48586         soc_OCB_RESERVED_PCMI_1_BCM88375_B0r_fields,
  48587         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48588         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48589         -1,
  48590         -1,
  48591     },
  48592 #endif /* chips */
  48593 
  48594 #if defined(BCM_88675_B0)
  48595     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_BCM88675_B0r */
  48596         soc_block_list[51],
  48597         soc_genreg,
  48598         1,
  48599         0,
  48600         0xb3,
  48601         0,
  48602         0,
  48603         1,
  48604         soc_OCB_RESERVED_PCMI_1_BCM88675_B0r_fields,
  48605         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48606         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48607         -1,
  48608         -1,
  48609     },
  48610 #endif /* chips */
  48611 
  48612 #if defined(BCM_88680_A0)
  48613     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_BCM88680_A0r */
  48614         soc_block_list[51],
  48615         soc_genreg,
  48616         1,
  48617         0,
  48618         0xb3,
  48619         0,
  48620         0,
  48621         1,
  48622         soc_OCB_RESERVED_PCMI_1_BCM88680_A0r_fields,
  48623         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48624         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48625         -1,
  48626         -1,
  48627     },
  48628 #endif /* chips */
  48629 
  48630 #if defined(BCM_88675_A0)
  48631     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_Sr */
  48632         soc_block_list[51],
  48633         soc_genreg,
  48634         1,
  48635         0,
  48636         0xb4,
  48637         SOC_REG_FLAG_RO,
  48638         0,
  48639         3,
  48640         soc_OCB_RESERVED_PCMI_1_Sr_fields,
  48641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48642         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48643         -1,
  48644         -1,
  48645     },
  48646 #endif /* chips */
  48647 
  48648 #if defined(BCM_88375_A0)
  48649     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_S_BCM88375_A0r */
  48650         soc_block_list[51],
  48651         soc_genreg,
  48652         1,
  48653         0,
  48654         0xb4,
  48655         SOC_REG_FLAG_RO,
  48656         0,
  48657         3,
  48658         soc_OCB_RESERVED_PCMI_1_S_BCM88375_A0r_fields,
  48659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48660         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48661         -1,
  48662         -1,
  48663     },
  48664 #endif /* chips */
  48665 
  48666 #if defined(BCM_88375_B0)
  48667     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_S_BCM88375_B0r */
  48668         soc_block_list[51],
  48669         soc_genreg,
  48670         1,
  48671         0,
  48672         0xb4,
  48673         SOC_REG_FLAG_RO,
  48674         0,
  48675         3,
  48676         soc_OCB_RESERVED_PCMI_1_S_BCM88375_B0r_fields,
  48677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48678         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48679         -1,
  48680         -1,
  48681     },
  48682 #endif /* chips */
  48683 
  48684 #if defined(BCM_88675_B0)
  48685     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_S_BCM88675_B0r */
  48686         soc_block_list[51],
  48687         soc_genreg,
  48688         1,
  48689         0,
  48690         0xb4,
  48691         SOC_REG_FLAG_RO,
  48692         0,
  48693         3,
  48694         soc_OCB_RESERVED_PCMI_1_S_BCM88675_B0r_fields,
  48695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48696         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48697         -1,
  48698         -1,
  48699     },
  48700 #endif /* chips */
  48701 
  48702 #if defined(BCM_88680_A0)
  48703     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_S_BCM88680_A0r */
  48704         soc_block_list[51],
  48705         soc_genreg,
  48706         1,
  48707         0,
  48708         0xb4,
  48709         SOC_REG_FLAG_RO,
  48710         0,
  48711         3,
  48712         soc_OCB_RESERVED_PCMI_1_S_BCM88680_A0r_fields,
  48713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48714         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48715         -1,
  48716         -1,
  48717     },
  48718 #endif /* chips */
  48719 
  48720 #if defined(BCM_88675_A0)
  48721     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_Tr */
  48722         soc_block_list[51],
  48723         soc_genreg,
  48724         1,
  48725         0,
  48726         0xb5,
  48727         0,
  48728         0,
  48729         2,
  48730         soc_OCB_RESERVED_PCMI_1_Tr_fields,
  48731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48732         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48733         -1,
  48734         -1,
  48735     },
  48736 #endif /* chips */
  48737 
  48738 #if defined(BCM_88375_A0)
  48739     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_T_BCM88375_A0r */
  48740         soc_block_list[51],
  48741         soc_genreg,
  48742         1,
  48743         0,
  48744         0xb5,
  48745         0,
  48746         0,
  48747         2,
  48748         soc_OCB_RESERVED_PCMI_1_T_BCM88375_A0r_fields,
  48749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48750         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48751         -1,
  48752         -1,
  48753     },
  48754 #endif /* chips */
  48755 
  48756 #if defined(BCM_88375_B0)
  48757     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_T_BCM88375_B0r */
  48758         soc_block_list[51],
  48759         soc_genreg,
  48760         1,
  48761         0,
  48762         0xb5,
  48763         0,
  48764         0,
  48765         2,
  48766         soc_OCB_RESERVED_PCMI_1_T_BCM88375_B0r_fields,
  48767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48768         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48769         -1,
  48770         -1,
  48771     },
  48772 #endif /* chips */
  48773 
  48774 #if defined(BCM_88675_B0)
  48775     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_T_BCM88675_B0r */
  48776         soc_block_list[51],
  48777         soc_genreg,
  48778         1,
  48779         0,
  48780         0xb5,
  48781         0,
  48782         0,
  48783         2,
  48784         soc_OCB_RESERVED_PCMI_1_T_BCM88675_B0r_fields,
  48785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48786         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48787         -1,
  48788         -1,
  48789     },
  48790 #endif /* chips */
  48791 
  48792 #if defined(BCM_88680_A0)
  48793     { /* SOC_REG_INT_OCB_RESERVED_PCMI_1_T_BCM88680_A0r */
  48794         soc_block_list[51],
  48795         soc_genreg,
  48796         1,
  48797         0,
  48798         0xb5,
  48799         0,
  48800         0,
  48801         2,
  48802         soc_OCB_RESERVED_PCMI_1_T_BCM88680_A0r_fields,
  48803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48804         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48805         -1,
  48806         -1,
  48807     },
  48808 #endif /* chips */
  48809 
  48810 #if defined(BCM_88375_A0)
  48811     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_BCM88375_A0r */
  48812         soc_block_list[51],
  48813         soc_genreg,
  48814         1,
  48815         0,
  48816         0xb6,
  48817         0,
  48818         0,
  48819         1,
  48820         soc_OCB_RESERVED_PCMI_2_BCM88375_A0r_fields,
  48821         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48822         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48823         -1,
  48824         -1,
  48825     },
  48826 #endif /* chips */
  48827 
  48828 #if defined(BCM_88375_B0)
  48829     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_BCM88375_B0r */
  48830         soc_block_list[51],
  48831         soc_genreg,
  48832         1,
  48833         0,
  48834         0xb6,
  48835         0,
  48836         0,
  48837         1,
  48838         soc_OCB_RESERVED_PCMI_2_BCM88375_B0r_fields,
  48839         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48840         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48841         -1,
  48842         -1,
  48843     },
  48844 #endif /* chips */
  48845 
  48846 #if defined(BCM_88675_B0)
  48847     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_BCM88675_B0r */
  48848         soc_block_list[51],
  48849         soc_genreg,
  48850         1,
  48851         0,
  48852         0xb6,
  48853         0,
  48854         0,
  48855         1,
  48856         soc_OCB_RESERVED_PCMI_2_BCM88675_B0r_fields,
  48857         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48859         -1,
  48860         -1,
  48861     },
  48862 #endif /* chips */
  48863 
  48864 #if defined(BCM_88680_A0)
  48865     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_BCM88680_A0r */
  48866         soc_block_list[51],
  48867         soc_genreg,
  48868         1,
  48869         0,
  48870         0xb6,
  48871         0,
  48872         0,
  48873         1,
  48874         soc_OCB_RESERVED_PCMI_2_BCM88680_A0r_fields,
  48875         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48877         -1,
  48878         -1,
  48879     },
  48880 #endif /* chips */
  48881 
  48882 #if defined(BCM_88675_A0)
  48883     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_Sr */
  48884         soc_block_list[51],
  48885         soc_genreg,
  48886         1,
  48887         0,
  48888         0xb7,
  48889         SOC_REG_FLAG_RO,
  48890         0,
  48891         3,
  48892         soc_OCB_RESERVED_PCMI_2_Sr_fields,
  48893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48894         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48895         -1,
  48896         -1,
  48897     },
  48898 #endif /* chips */
  48899 
  48900 #if defined(BCM_88375_A0)
  48901     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_S_BCM88375_A0r */
  48902         soc_block_list[51],
  48903         soc_genreg,
  48904         1,
  48905         0,
  48906         0xb7,
  48907         SOC_REG_FLAG_RO,
  48908         0,
  48909         3,
  48910         soc_OCB_RESERVED_PCMI_2_S_BCM88375_A0r_fields,
  48911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48912         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48913         -1,
  48914         -1,
  48915     },
  48916 #endif /* chips */
  48917 
  48918 #if defined(BCM_88375_B0)
  48919     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_S_BCM88375_B0r */
  48920         soc_block_list[51],
  48921         soc_genreg,
  48922         1,
  48923         0,
  48924         0xb7,
  48925         SOC_REG_FLAG_RO,
  48926         0,
  48927         3,
  48928         soc_OCB_RESERVED_PCMI_2_S_BCM88375_B0r_fields,
  48929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48930         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48931         -1,
  48932         -1,
  48933     },
  48934 #endif /* chips */
  48935 
  48936 #if defined(BCM_88675_B0)
  48937     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_S_BCM88675_B0r */
  48938         soc_block_list[51],
  48939         soc_genreg,
  48940         1,
  48941         0,
  48942         0xb7,
  48943         SOC_REG_FLAG_RO,
  48944         0,
  48945         3,
  48946         soc_OCB_RESERVED_PCMI_2_S_BCM88675_B0r_fields,
  48947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48948         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48949         -1,
  48950         -1,
  48951     },
  48952 #endif /* chips */
  48953 
  48954 #if defined(BCM_88680_A0)
  48955     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_S_BCM88680_A0r */
  48956         soc_block_list[51],
  48957         soc_genreg,
  48958         1,
  48959         0,
  48960         0xb7,
  48961         SOC_REG_FLAG_RO,
  48962         0,
  48963         3,
  48964         soc_OCB_RESERVED_PCMI_2_S_BCM88680_A0r_fields,
  48965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48966         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48967         -1,
  48968         -1,
  48969     },
  48970 #endif /* chips */
  48971 
  48972 #if defined(BCM_88675_A0)
  48973     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_Tr */
  48974         soc_block_list[51],
  48975         soc_genreg,
  48976         1,
  48977         0,
  48978         0xb8,
  48979         0,
  48980         0,
  48981         2,
  48982         soc_OCB_RESERVED_PCMI_2_Tr_fields,
  48983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48984         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  48985         -1,
  48986         -1,
  48987     },
  48988 #endif /* chips */
  48989 
  48990 #if defined(BCM_88375_A0)
  48991     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_T_BCM88375_A0r */
  48992         soc_block_list[51],
  48993         soc_genreg,
  48994         1,
  48995         0,
  48996         0xb8,
  48997         0,
  48998         0,
  48999         2,
  49000         soc_OCB_RESERVED_PCMI_2_T_BCM88375_A0r_fields,
  49001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49002         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49003         -1,
  49004         -1,
  49005     },
  49006 #endif /* chips */
  49007 
  49008 #if defined(BCM_88375_B0)
  49009     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_T_BCM88375_B0r */
  49010         soc_block_list[51],
  49011         soc_genreg,
  49012         1,
  49013         0,
  49014         0xb8,
  49015         0,
  49016         0,
  49017         2,
  49018         soc_OCB_RESERVED_PCMI_2_T_BCM88375_B0r_fields,
  49019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49020         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49021         -1,
  49022         -1,
  49023     },
  49024 #endif /* chips */
  49025 
  49026 #if defined(BCM_88675_B0)
  49027     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_T_BCM88675_B0r */
  49028         soc_block_list[51],
  49029         soc_genreg,
  49030         1,
  49031         0,
  49032         0xb8,
  49033         0,
  49034         0,
  49035         2,
  49036         soc_OCB_RESERVED_PCMI_2_T_BCM88675_B0r_fields,
  49037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49038         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49039         -1,
  49040         -1,
  49041     },
  49042 #endif /* chips */
  49043 
  49044 #if defined(BCM_88680_A0)
  49045     { /* SOC_REG_INT_OCB_RESERVED_PCMI_2_T_BCM88680_A0r */
  49046         soc_block_list[51],
  49047         soc_genreg,
  49048         1,
  49049         0,
  49050         0xb8,
  49051         0,
  49052         0,
  49053         2,
  49054         soc_OCB_RESERVED_PCMI_2_T_BCM88680_A0r_fields,
  49055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49056         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49057         -1,
  49058         -1,
  49059     },
  49060 #endif /* chips */
  49061 
  49062 #if defined(BCM_88375_A0)
  49063     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_BCM88375_A0r */
  49064         soc_block_list[51],
  49065         soc_genreg,
  49066         1,
  49067         0,
  49068         0xb9,
  49069         0,
  49070         0,
  49071         1,
  49072         soc_OCB_RESERVED_PCMI_3_BCM88375_A0r_fields,
  49073         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  49074         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49075         -1,
  49076         -1,
  49077     },
  49078 #endif /* chips */
  49079 
  49080 #if defined(BCM_88375_B0)
  49081     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_BCM88375_B0r */
  49082         soc_block_list[51],
  49083         soc_genreg,
  49084         1,
  49085         0,
  49086         0xb9,
  49087         0,
  49088         0,
  49089         1,
  49090         soc_OCB_RESERVED_PCMI_3_BCM88375_B0r_fields,
  49091         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  49092         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49093         -1,
  49094         -1,
  49095     },
  49096 #endif /* chips */
  49097 
  49098 #if defined(BCM_88675_B0)
  49099     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_BCM88675_B0r */
  49100         soc_block_list[51],
  49101         soc_genreg,
  49102         1,
  49103         0,
  49104         0xb9,
  49105         0,
  49106         0,
  49107         1,
  49108         soc_OCB_RESERVED_PCMI_3_BCM88675_B0r_fields,
  49109         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  49110         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49111         -1,
  49112         -1,
  49113     },
  49114 #endif /* chips */
  49115 
  49116 #if defined(BCM_88680_A0)
  49117     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_BCM88680_A0r */
  49118         soc_block_list[51],
  49119         soc_genreg,
  49120         1,
  49121         0,
  49122         0xb9,
  49123         0,
  49124         0,
  49125         1,
  49126         soc_OCB_RESERVED_PCMI_3_BCM88680_A0r_fields,
  49127         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  49128         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49129         -1,
  49130         -1,
  49131     },
  49132 #endif /* chips */
  49133 
  49134 #if defined(BCM_88675_A0)
  49135     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_Sr */
  49136         soc_block_list[51],
  49137         soc_genreg,
  49138         1,
  49139         0,
  49140         0xba,
  49141         SOC_REG_FLAG_RO,
  49142         0,
  49143         3,
  49144         soc_OCB_RESERVED_PCMI_3_Sr_fields,
  49145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49146         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49147         -1,
  49148         -1,
  49149     },
  49150 #endif /* chips */
  49151 
  49152 #if defined(BCM_88375_A0)
  49153     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_S_BCM88375_A0r */
  49154         soc_block_list[51],
  49155         soc_genreg,
  49156         1,
  49157         0,
  49158         0xba,
  49159         SOC_REG_FLAG_RO,
  49160         0,
  49161         3,
  49162         soc_OCB_RESERVED_PCMI_3_S_BCM88375_A0r_fields,
  49163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49164         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49165         -1,
  49166         -1,
  49167     },
  49168 #endif /* chips */
  49169 
  49170 #if defined(BCM_88375_B0)
  49171     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_S_BCM88375_B0r */
  49172         soc_block_list[51],
  49173         soc_genreg,
  49174         1,
  49175         0,
  49176         0xba,
  49177         SOC_REG_FLAG_RO,
  49178         0,
  49179         3,
  49180         soc_OCB_RESERVED_PCMI_3_S_BCM88375_B0r_fields,
  49181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49182         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49183         -1,
  49184         -1,
  49185     },
  49186 #endif /* chips */
  49187 
  49188 #if defined(BCM_88675_B0)
  49189     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_S_BCM88675_B0r */
  49190         soc_block_list[51],
  49191         soc_genreg,
  49192         1,
  49193         0,
  49194         0xba,
  49195         SOC_REG_FLAG_RO,
  49196         0,
  49197         3,
  49198         soc_OCB_RESERVED_PCMI_3_S_BCM88675_B0r_fields,
  49199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49200         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49201         -1,
  49202         -1,
  49203     },
  49204 #endif /* chips */
  49205 
  49206 #if defined(BCM_88680_A0)
  49207     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_S_BCM88680_A0r */
  49208         soc_block_list[51],
  49209         soc_genreg,
  49210         1,
  49211         0,
  49212         0xba,
  49213         SOC_REG_FLAG_RO,
  49214         0,
  49215         3,
  49216         soc_OCB_RESERVED_PCMI_3_S_BCM88680_A0r_fields,
  49217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49219         -1,
  49220         -1,
  49221     },
  49222 #endif /* chips */
  49223 
  49224 #if defined(BCM_88675_A0)
  49225     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_Tr */
  49226         soc_block_list[51],
  49227         soc_genreg,
  49228         1,
  49229         0,
  49230         0xbb,
  49231         0,
  49232         0,
  49233         2,
  49234         soc_OCB_RESERVED_PCMI_3_Tr_fields,
  49235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49236         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49237         -1,
  49238         -1,
  49239     },
  49240 #endif /* chips */
  49241 
  49242 #if defined(BCM_88375_A0)
  49243     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_T_BCM88375_A0r */
  49244         soc_block_list[51],
  49245         soc_genreg,
  49246         1,
  49247         0,
  49248         0xbb,
  49249         0,
  49250         0,
  49251         2,
  49252         soc_OCB_RESERVED_PCMI_3_T_BCM88375_A0r_fields,
  49253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49254         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49255         -1,
  49256         -1,
  49257     },
  49258 #endif /* chips */
  49259 
  49260 #if defined(BCM_88375_B0)
  49261     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_T_BCM88375_B0r */
  49262         soc_block_list[51],
  49263         soc_genreg,
  49264         1,
  49265         0,
  49266         0xbb,
  49267         0,
  49268         0,
  49269         2,
  49270         soc_OCB_RESERVED_PCMI_3_T_BCM88375_B0r_fields,
  49271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49272         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49273         -1,
  49274         -1,
  49275     },
  49276 #endif /* chips */
  49277 
  49278 #if defined(BCM_88675_B0)
  49279     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_T_BCM88675_B0r */
  49280         soc_block_list[51],
  49281         soc_genreg,
  49282         1,
  49283         0,
  49284         0xbb,
  49285         0,
  49286         0,
  49287         2,
  49288         soc_OCB_RESERVED_PCMI_3_T_BCM88675_B0r_fields,
  49289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49290         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49291         -1,
  49292         -1,
  49293     },
  49294 #endif /* chips */
  49295 
  49296 #if defined(BCM_88680_A0)
  49297     { /* SOC_REG_INT_OCB_RESERVED_PCMI_3_T_BCM88680_A0r */
  49298         soc_block_list[51],
  49299         soc_genreg,
  49300         1,
  49301         0,
  49302         0xbb,
  49303         0,
  49304         0,
  49305         2,
  49306         soc_OCB_RESERVED_PCMI_3_T_BCM88680_A0r_fields,
  49307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49308         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49309         -1,
  49310         -1,
  49311     },
  49312 #endif /* chips */
  49313 
  49314 #if defined(BCM_88375_A0)
  49315     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_BCM88375_A0r */
  49316         soc_block_list[51],
  49317         soc_genreg,
  49318         1,
  49319         0,
  49320         0xbc,
  49321         0,
  49322         0,
  49323         1,
  49324         soc_OCB_RESERVED_PCMI_4_BCM88375_A0r_fields,
  49325         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  49326         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49327         -1,
  49328         -1,
  49329     },
  49330 #endif /* chips */
  49331 
  49332 #if defined(BCM_88375_B0)
  49333     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_BCM88375_B0r */
  49334         soc_block_list[51],
  49335         soc_genreg,
  49336         1,
  49337         0,
  49338         0xbc,
  49339         0,
  49340         0,
  49341         1,
  49342         soc_OCB_RESERVED_PCMI_4_BCM88375_B0r_fields,
  49343         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  49344         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49345         -1,
  49346         -1,
  49347     },
  49348 #endif /* chips */
  49349 
  49350 #if defined(BCM_88675_B0)
  49351     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_BCM88675_B0r */
  49352         soc_block_list[51],
  49353         soc_genreg,
  49354         1,
  49355         0,
  49356         0xbc,
  49357         0,
  49358         0,
  49359         1,
  49360         soc_OCB_RESERVED_PCMI_4_BCM88675_B0r_fields,
  49361         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  49362         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49363         -1,
  49364         -1,
  49365     },
  49366 #endif /* chips */
  49367 
  49368 #if defined(BCM_88680_A0)
  49369     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_BCM88680_A0r */
  49370         soc_block_list[51],
  49371         soc_genreg,
  49372         1,
  49373         0,
  49374         0xbc,
  49375         0,
  49376         0,
  49377         1,
  49378         soc_OCB_RESERVED_PCMI_4_BCM88680_A0r_fields,
  49379         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  49380         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49381         -1,
  49382         -1,
  49383     },
  49384 #endif /* chips */
  49385 
  49386 #if defined(BCM_88675_A0)
  49387     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_Sr */
  49388         soc_block_list[51],
  49389         soc_genreg,
  49390         1,
  49391         0,
  49392         0xbd,
  49393         SOC_REG_FLAG_RO,
  49394         0,
  49395         3,
  49396         soc_OCB_RESERVED_PCMI_4_Sr_fields,
  49397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49398         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49399         -1,
  49400         -1,
  49401     },
  49402 #endif /* chips */
  49403 
  49404 #if defined(BCM_88375_A0)
  49405     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_S_BCM88375_A0r */
  49406         soc_block_list[51],
  49407         soc_genreg,
  49408         1,
  49409         0,
  49410         0xbd,
  49411         SOC_REG_FLAG_RO,
  49412         0,
  49413         3,
  49414         soc_OCB_RESERVED_PCMI_4_S_BCM88375_A0r_fields,
  49415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49416         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49417         -1,
  49418         -1,
  49419     },
  49420 #endif /* chips */
  49421 
  49422 #if defined(BCM_88375_B0)
  49423     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_S_BCM88375_B0r */
  49424         soc_block_list[51],
  49425         soc_genreg,
  49426         1,
  49427         0,
  49428         0xbd,
  49429         SOC_REG_FLAG_RO,
  49430         0,
  49431         3,
  49432         soc_OCB_RESERVED_PCMI_4_S_BCM88375_B0r_fields,
  49433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49434         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49435         -1,
  49436         -1,
  49437     },
  49438 #endif /* chips */
  49439 
  49440 #if defined(BCM_88675_B0)
  49441     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_S_BCM88675_B0r */
  49442         soc_block_list[51],
  49443         soc_genreg,
  49444         1,
  49445         0,
  49446         0xbd,
  49447         SOC_REG_FLAG_RO,
  49448         0,
  49449         3,
  49450         soc_OCB_RESERVED_PCMI_4_S_BCM88675_B0r_fields,
  49451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49452         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49453         -1,
  49454         -1,
  49455     },
  49456 #endif /* chips */
  49457 
  49458 #if defined(BCM_88680_A0)
  49459     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_S_BCM88680_A0r */
  49460         soc_block_list[51],
  49461         soc_genreg,
  49462         1,
  49463         0,
  49464         0xbd,
  49465         SOC_REG_FLAG_RO,
  49466         0,
  49467         3,
  49468         soc_OCB_RESERVED_PCMI_4_S_BCM88680_A0r_fields,
  49469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49470         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49471         -1,
  49472         -1,
  49473     },
  49474 #endif /* chips */
  49475 
  49476 #if defined(BCM_88675_A0)
  49477     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_Tr */
  49478         soc_block_list[51],
  49479         soc_genreg,
  49480         1,
  49481         0,
  49482         0xbe,
  49483         0,
  49484         0,
  49485         2,
  49486         soc_OCB_RESERVED_PCMI_4_Tr_fields,
  49487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49488         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49489         -1,
  49490         -1,
  49491     },
  49492 #endif /* chips */
  49493 
  49494 #if defined(BCM_88375_A0)
  49495     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_T_BCM88375_A0r */
  49496         soc_block_list[51],
  49497         soc_genreg,
  49498         1,
  49499         0,
  49500         0xbe,
  49501         0,
  49502         0,
  49503         2,
  49504         soc_OCB_RESERVED_PCMI_4_T_BCM88375_A0r_fields,
  49505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49506         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49507         -1,
  49508         -1,
  49509     },
  49510 #endif /* chips */
  49511 
  49512 #if defined(BCM_88375_B0)
  49513     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_T_BCM88375_B0r */
  49514         soc_block_list[51],
  49515         soc_genreg,
  49516         1,
  49517         0,
  49518         0xbe,
  49519         0,
  49520         0,
  49521         2,
  49522         soc_OCB_RESERVED_PCMI_4_T_BCM88375_B0r_fields,
  49523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49524         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49525         -1,
  49526         -1,
  49527     },
  49528 #endif /* chips */
  49529 
  49530 #if defined(BCM_88675_B0)
  49531     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_T_BCM88675_B0r */
  49532         soc_block_list[51],
  49533         soc_genreg,
  49534         1,
  49535         0,
  49536         0xbe,
  49537         0,
  49538         0,
  49539         2,
  49540         soc_OCB_RESERVED_PCMI_4_T_BCM88675_B0r_fields,
  49541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49542         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49543         -1,
  49544         -1,
  49545     },
  49546 #endif /* chips */
  49547 
  49548 #if defined(BCM_88680_A0)
  49549     { /* SOC_REG_INT_OCB_RESERVED_PCMI_4_T_BCM88680_A0r */
  49550         soc_block_list[51],
  49551         soc_genreg,
  49552         1,
  49553         0,
  49554         0xbe,
  49555         0,
  49556         0,
  49557         2,
  49558         soc_OCB_RESERVED_PCMI_4_T_BCM88680_A0r_fields,
  49559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49560         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  49561         -1,
  49562         -1,
  49563     },
  49564 #endif /* chips */
  49565 
  49566 #if defined(BCM_88675_A0)
  49567     { /* SOC_REG_INT_OCB_RESERVED_SPARE_0r */
  49568         soc_block_list[51],
  49569         soc_genreg,
  49570         1,
  49571         0,
  49572         0x90,
  49573         0,
  49574         0,
  49575         1,
  49576         soc_OCB_RESERVED_SPARE_0r_fields,
  49577         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49578         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49579         -1,
  49580         -1,
  49581     },
  49582 #endif /* chips */
  49583 
  49584 #if defined(BCM_88675_A0)
  49585     { /* SOC_REG_INT_OCB_RESERVED_SPARE_1r */
  49586         soc_block_list[51],
  49587         soc_genreg,
  49588         1,
  49589         0,
  49590         0x91,
  49591         0,
  49592         0,
  49593         1,
  49594         soc_OCB_RESERVED_SPARE_1r_fields,
  49595         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49597         -1,
  49598         -1,
  49599     },
  49600 #endif /* chips */
  49601 
  49602 #if defined(BCM_88675_A0)
  49603     { /* SOC_REG_INT_OCB_RESERVED_SPARE_2r */
  49604         soc_block_list[51],
  49605         soc_genreg,
  49606         1,
  49607         0,
  49608         0x92,
  49609         0,
  49610         0,
  49611         1,
  49612         soc_OCB_RESERVED_SPARE_2r_fields,
  49613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49615         -1,
  49616         -1,
  49617     },
  49618 #endif /* chips */
  49619 
  49620 #if defined(BCM_88675_A0)
  49621     { /* SOC_REG_INT_OCB_RESERVED_SPARE_3r */
  49622         soc_block_list[51],
  49623         soc_genreg,
  49624         1,
  49625         0,
  49626         0x93,
  49627         0,
  49628         0,
  49629         1,
  49630         soc_OCB_RESERVED_SPARE_3r_fields,
  49631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49633         -1,
  49634         -1,
  49635     },
  49636 #endif /* chips */
  49637 
  49638 #if defined(BCM_88375_A0)
  49639     { /* SOC_REG_INT_OCB_RESERVED_SPARE_0_BCM88375_A0r */
  49640         soc_block_list[51],
  49641         soc_genreg,
  49642         1,
  49643         0,
  49644         0x90,
  49645         0,
  49646         0,
  49647         1,
  49648         soc_OCB_RESERVED_SPARE_0_BCM88375_A0r_fields,
  49649         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49651         -1,
  49652         -1,
  49653     },
  49654 #endif /* chips */
  49655 
  49656 #if defined(BCM_88375_B0)
  49657     { /* SOC_REG_INT_OCB_RESERVED_SPARE_0_BCM88375_B0r */
  49658         soc_block_list[51],
  49659         soc_genreg,
  49660         1,
  49661         0,
  49662         0x90,
  49663         0,
  49664         0,
  49665         1,
  49666         soc_OCB_RESERVED_SPARE_0_BCM88375_B0r_fields,
  49667         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49669         -1,
  49670         -1,
  49671     },
  49672 #endif /* chips */
  49673 
  49674 #if defined(BCM_88675_B0)
  49675     { /* SOC_REG_INT_OCB_RESERVED_SPARE_0_BCM88675_B0r */
  49676         soc_block_list[51],
  49677         soc_genreg,
  49678         1,
  49679         0,
  49680         0x90,
  49681         0,
  49682         0,
  49683         1,
  49684         soc_OCB_RESERVED_SPARE_0_BCM88675_B0r_fields,
  49685         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49687         -1,
  49688         -1,
  49689     },
  49690 #endif /* chips */
  49691 
  49692 #if defined(BCM_88680_A0)
  49693     { /* SOC_REG_INT_OCB_RESERVED_SPARE_0_BCM88680_A0r */
  49694         soc_block_list[51],
  49695         soc_genreg,
  49696         1,
  49697         0,
  49698         0x90,
  49699         0,
  49700         0,
  49701         1,
  49702         soc_OCB_RESERVED_SPARE_0_BCM88680_A0r_fields,
  49703         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49705         -1,
  49706         -1,
  49707     },
  49708 #endif /* chips */
  49709 
  49710 #if defined(BCM_88690_A0)
  49711     { /* SOC_REG_INT_OCB_RESERVED_SPARE_0_BCM88690_A0r */
  49712         soc_block_list[51],
  49713         soc_genreg,
  49714         1,
  49715         0,
  49716         0x90,
  49717         0,
  49718         0,
  49719         1,
  49720         soc_OCB_RESERVED_SPARE_0_BCM88690_A0r_fields,
  49721         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49723         -1,
  49724         -1,
  49725     },
  49726 #endif /* chips */
  49727 
  49728 #if defined(BCM_88690_B0)
  49729     { /* SOC_REG_INT_OCB_RESERVED_SPARE_0_BCM88690_B0r */
  49730         soc_block_list[51],
  49731         soc_genreg,
  49732         1,
  49733         0,
  49734         0x90,
  49735         0,
  49736         0,
  49737         1,
  49738         soc_OCB_RESERVED_SPARE_0_BCM88690_B0r_fields,
  49739         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49741         -1,
  49742         -1,
  49743     },
  49744 #endif /* chips */
  49745 
  49746 #if defined(BCM_88375_A0)
  49747     { /* SOC_REG_INT_OCB_RESERVED_SPARE_1_BCM88375_A0r */
  49748         soc_block_list[51],
  49749         soc_genreg,
  49750         1,
  49751         0,
  49752         0x91,
  49753         0,
  49754         0,
  49755         1,
  49756         soc_OCB_RESERVED_SPARE_1_BCM88375_A0r_fields,
  49757         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49759         -1,
  49760         -1,
  49761     },
  49762 #endif /* chips */
  49763 
  49764 #if defined(BCM_88375_B0)
  49765     { /* SOC_REG_INT_OCB_RESERVED_SPARE_1_BCM88375_B0r */
  49766         soc_block_list[51],
  49767         soc_genreg,
  49768         1,
  49769         0,
  49770         0x91,
  49771         0,
  49772         0,
  49773         1,
  49774         soc_OCB_RESERVED_SPARE_1_BCM88375_B0r_fields,
  49775         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49777         -1,
  49778         -1,
  49779     },
  49780 #endif /* chips */
  49781 
  49782 #if defined(BCM_88675_B0)
  49783     { /* SOC_REG_INT_OCB_RESERVED_SPARE_1_BCM88675_B0r */
  49784         soc_block_list[51],
  49785         soc_genreg,
  49786         1,
  49787         0,
  49788         0x91,
  49789         0,
  49790         0,
  49791         1,
  49792         soc_OCB_RESERVED_SPARE_1_BCM88675_B0r_fields,
  49793         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49794         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49795         -1,
  49796         -1,
  49797     },
  49798 #endif /* chips */
  49799 
  49800 #if defined(BCM_88680_A0)
  49801     { /* SOC_REG_INT_OCB_RESERVED_SPARE_1_BCM88680_A0r */
  49802         soc_block_list[51],
  49803         soc_genreg,
  49804         1,
  49805         0,
  49806         0x91,
  49807         0,
  49808         0,
  49809         1,
  49810         soc_OCB_RESERVED_SPARE_1_BCM88680_A0r_fields,
  49811         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49812         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49813         -1,
  49814         -1,
  49815     },
  49816 #endif /* chips */
  49817 
  49818 #if defined(BCM_88690_A0)
  49819     { /* SOC_REG_INT_OCB_RESERVED_SPARE_1_BCM88690_A0r */
  49820         soc_block_list[51],
  49821         soc_genreg,
  49822         1,
  49823         0,
  49824         0x91,
  49825         0,
  49826         0,
  49827         1,
  49828         soc_OCB_RESERVED_SPARE_1_BCM88690_A0r_fields,
  49829         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49830         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49831         -1,
  49832         -1,
  49833     },
  49834 #endif /* chips */
  49835 
  49836 #if defined(BCM_88690_B0)
  49837     { /* SOC_REG_INT_OCB_RESERVED_SPARE_1_BCM88690_B0r */
  49838         soc_block_list[51],
  49839         soc_genreg,
  49840         1,
  49841         0,
  49842         0x91,
  49843         0,
  49844         0,
  49845         1,
  49846         soc_OCB_RESERVED_SPARE_1_BCM88690_B0r_fields,
  49847         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  49848         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49849         -1,
  49850         -1,
  49851     },
  49852 #endif /* chips */
  49853 
  49854 #if defined(BCM_88375_A0)
  49855     { /* SOC_REG_INT_OCB_RESERVED_SPARE_2_BCM88375_A0r */
  49856         soc_block_list[51],
  49857         soc_genreg,
  49858         1,
  49859         0,
  49860         0x92,
  49861         0,
  49862         0,
  49863         1,
  49864         soc_OCB_RESERVED_SPARE_2_BCM88375_A0r_fields,
  49865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49866         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49867         -1,
  49868         -1,
  49869     },
  49870 #endif /* chips */
  49871 
  49872 #if defined(BCM_88375_B0)
  49873     { /* SOC_REG_INT_OCB_RESERVED_SPARE_2_BCM88375_B0r */
  49874         soc_block_list[51],
  49875         soc_genreg,
  49876         1,
  49877         0,
  49878         0x92,
  49879         0,
  49880         0,
  49881         1,
  49882         soc_OCB_RESERVED_SPARE_2_BCM88375_B0r_fields,
  49883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49884         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49885         -1,
  49886         -1,
  49887     },
  49888 #endif /* chips */
  49889 
  49890 #if defined(BCM_88675_B0)
  49891     { /* SOC_REG_INT_OCB_RESERVED_SPARE_2_BCM88675_B0r */
  49892         soc_block_list[51],
  49893         soc_genreg,
  49894         1,
  49895         0,
  49896         0x92,
  49897         0,
  49898         0,
  49899         1,
  49900         soc_OCB_RESERVED_SPARE_2_BCM88675_B0r_fields,
  49901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49902         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49903         -1,
  49904         -1,
  49905     },
  49906 #endif /* chips */
  49907 
  49908 #if defined(BCM_88680_A0)
  49909     { /* SOC_REG_INT_OCB_RESERVED_SPARE_2_BCM88680_A0r */
  49910         soc_block_list[51],
  49911         soc_genreg,
  49912         1,
  49913         0,
  49914         0x92,
  49915         0,
  49916         0,
  49917         1,
  49918         soc_OCB_RESERVED_SPARE_2_BCM88680_A0r_fields,
  49919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49920         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49921         -1,
  49922         -1,
  49923     },
  49924 #endif /* chips */
  49925 
  49926 #if defined(BCM_88690_A0)
  49927     { /* SOC_REG_INT_OCB_RESERVED_SPARE_2_BCM88690_A0r */
  49928         soc_block_list[51],
  49929         soc_genreg,
  49930         1,
  49931         0,
  49932         0x92,
  49933         0,
  49934         0,
  49935         1,
  49936         soc_OCB_RESERVED_SPARE_2_BCM88690_A0r_fields,
  49937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49938         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49939         -1,
  49940         -1,
  49941     },
  49942 #endif /* chips */
  49943 
  49944 #if defined(BCM_88690_B0)
  49945     { /* SOC_REG_INT_OCB_RESERVED_SPARE_2_BCM88690_B0r */
  49946         soc_block_list[51],
  49947         soc_genreg,
  49948         1,
  49949         0,
  49950         0x92,
  49951         0,
  49952         0,
  49953         1,
  49954         soc_OCB_RESERVED_SPARE_2_BCM88690_B0r_fields,
  49955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49957         -1,
  49958         -1,
  49959     },
  49960 #endif /* chips */
  49961 
  49962 #if defined(BCM_88375_A0)
  49963     { /* SOC_REG_INT_OCB_RESERVED_SPARE_3_BCM88375_A0r */
  49964         soc_block_list[51],
  49965         soc_genreg,
  49966         1,
  49967         0,
  49968         0x93,
  49969         0,
  49970         0,
  49971         1,
  49972         soc_OCB_RESERVED_SPARE_3_BCM88375_A0r_fields,
  49973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49974         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49975         -1,
  49976         -1,
  49977     },
  49978 #endif /* chips */
  49979 
  49980 #if defined(BCM_88375_B0)
  49981     { /* SOC_REG_INT_OCB_RESERVED_SPARE_3_BCM88375_B0r */
  49982         soc_block_list[51],
  49983         soc_genreg,
  49984         1,
  49985         0,
  49986         0x93,
  49987         0,
  49988         0,
  49989         1,
  49990         soc_OCB_RESERVED_SPARE_3_BCM88375_B0r_fields,
  49991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49993         -1,
  49994         -1,
  49995     },
  49996 #endif /* chips */
  49997 
  49998 #if defined(BCM_88675_B0)
  49999     { /* SOC_REG_INT_OCB_RESERVED_SPARE_3_BCM88675_B0r */
  50000         soc_block_list[51],
  50001         soc_genreg,
  50002         1,
  50003         0,
  50004         0x93,
  50005         0,
  50006         0,
  50007         1,
  50008         soc_OCB_RESERVED_SPARE_3_BCM88675_B0r_fields,
  50009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50010         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50011         -1,
  50012         -1,
  50013     },
  50014 #endif /* chips */
  50015 
  50016 #if defined(BCM_88680_A0)
  50017     { /* SOC_REG_INT_OCB_RESERVED_SPARE_3_BCM88680_A0r */
  50018         soc_block_list[51],
  50019         soc_genreg,
  50020         1,
  50021         0,
  50022         0x93,
  50023         0,
  50024         0,
  50025         1,
  50026         soc_OCB_RESERVED_SPARE_3_BCM88680_A0r_fields,
  50027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50028         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50029         -1,
  50030         -1,
  50031     },
  50032 #endif /* chips */
  50033 
  50034 #if defined(BCM_88690_A0)
  50035     { /* SOC_REG_INT_OCB_RESERVED_SPARE_3_BCM88690_A0r */
  50036         soc_block_list[51],
  50037         soc_genreg,
  50038         1,
  50039         0,
  50040         0x93,
  50041         0,
  50042         0,
  50043         1,
  50044         soc_OCB_RESERVED_SPARE_3_BCM88690_A0r_fields,
  50045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50046         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50047         -1,
  50048         -1,
  50049     },
  50050 #endif /* chips */
  50051 
  50052 #if defined(BCM_88690_B0)
  50053     { /* SOC_REG_INT_OCB_RESERVED_SPARE_3_BCM88690_B0r */
  50054         soc_block_list[51],
  50055         soc_genreg,
  50056         1,
  50057         0,
  50058         0x93,
  50059         0,
  50060         0,
  50061         1,
  50062         soc_OCB_RESERVED_SPARE_3_BCM88690_B0r_fields,
  50063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50065         -1,
  50066         -1,
  50067     },
  50068 #endif /* chips */
  50069 
  50070 #if defined(BCM_88690_A0)
  50071     { /* SOC_REG_INT_OCB_RESET_STATUS_REGISTERr */
  50072         soc_block_list[51],
  50073         soc_genreg,
  50074         1,
  50075         0,
  50076         0x104,
  50077         SOC_REG_FLAG_RO,
  50078         0,
  50079         1,
  50080         soc_OCB_RESET_STATUS_REGISTERr_fields,
  50081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50082         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50083         -1,
  50084         -1,
  50085     },
  50086 #endif /* chips */
  50087 
  50088 #if defined(BCM_88690_B0)
  50089     { /* SOC_REG_INT_OCB_RESET_STATUS_REGISTER_BCM88690_B0r */
  50090         soc_block_list[51],
  50091         soc_genreg,
  50092         1,
  50093         0,
  50094         0x106,
  50095         SOC_REG_FLAG_RO,
  50096         0,
  50097         1,
  50098         soc_OCB_RESET_STATUS_REGISTER_BCM88690_B0r_fields,
  50099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50100         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50101         -1,
  50102         -1,
  50103     },
  50104 #endif /* chips */
  50105 
  50106 #if defined(BCM_88675_A0)
  50107     { /* SOC_REG_INT_OCB_SBUS_BROADCAST_IDr */
  50108         soc_block_list[51],
  50109         soc_genreg,
  50110         1,
  50111         0,
  50112         0x86,
  50113         0,
  50114         0,
  50115         1,
  50116         soc_OCB_SBUS_BROADCAST_IDr_fields,
  50117         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  50118         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50119         -1,
  50120         -1,
  50121     },
  50122 #endif /* chips */
  50123 
  50124 #if defined(BCM_88375_A0)
  50125     { /* SOC_REG_INT_OCB_SBUS_BROADCAST_ID_BCM88375_A0r */
  50126         soc_block_list[51],
  50127         soc_genreg,
  50128         1,
  50129         0,
  50130         0x86,
  50131         0,
  50132         0,
  50133         1,
  50134         soc_OCB_SBUS_BROADCAST_ID_BCM88375_A0r_fields,
  50135         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  50136         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50137         -1,
  50138         -1,
  50139     },
  50140 #endif /* chips */
  50141 
  50142 #if defined(BCM_88375_B0)
  50143     { /* SOC_REG_INT_OCB_SBUS_BROADCAST_ID_BCM88375_B0r */
  50144         soc_block_list[51],
  50145         soc_genreg,
  50146         1,
  50147         0,
  50148         0x86,
  50149         0,
  50150         0,
  50151         1,
  50152         soc_OCB_SBUS_BROADCAST_ID_BCM88375_B0r_fields,
  50153         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  50154         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50155         -1,
  50156         -1,
  50157     },
  50158 #endif /* chips */
  50159 
  50160 #if defined(BCM_88675_B0)
  50161     { /* SOC_REG_INT_OCB_SBUS_BROADCAST_ID_BCM88675_B0r */
  50162         soc_block_list[51],
  50163         soc_genreg,
  50164         1,
  50165         0,
  50166         0x86,
  50167         0,
  50168         0,
  50169         1,
  50170         soc_OCB_SBUS_BROADCAST_ID_BCM88675_B0r_fields,
  50171         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  50172         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50173         -1,
  50174         -1,
  50175     },
  50176 #endif /* chips */
  50177 
  50178 #if defined(BCM_88680_A0)
  50179     { /* SOC_REG_INT_OCB_SBUS_BROADCAST_ID_BCM88680_A0r */
  50180         soc_block_list[51],
  50181         soc_genreg,
  50182         1,
  50183         0,
  50184         0x86,
  50185         0,
  50186         0,
  50187         1,
  50188         soc_OCB_SBUS_BROADCAST_ID_BCM88680_A0r_fields,
  50189         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  50190         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50191         -1,
  50192         -1,
  50193     },
  50194 #endif /* chips */
  50195 
  50196 #if defined(BCM_88690_A0)
  50197     { /* SOC_REG_INT_OCB_SBUS_BROADCAST_ID_BCM88690_A0r */
  50198         soc_block_list[51],
  50199         soc_genreg,
  50200         1,
  50201         0,
  50202         0x86,
  50203         0,
  50204         0,
  50205         1,
  50206         soc_OCB_SBUS_BROADCAST_ID_BCM88690_A0r_fields,
  50207         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  50208         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  50209         -1,
  50210         -1,
  50211     },
  50212 #endif /* chips */
  50213 
  50214 #if defined(BCM_88690_B0)
  50215     { /* SOC_REG_INT_OCB_SBUS_BROADCAST_ID_BCM88690_B0r */
  50216         soc_block_list[51],
  50217         soc_genreg,
  50218         1,
  50219         0,
  50220         0x86,
  50221         0,
  50222         0,
  50223         1,
  50224         soc_OCB_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
  50225         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  50226         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  50227         -1,
  50228         -1,
  50229     },
  50230 #endif /* chips */
  50231 
  50232 #if defined(BCM_88675_A0)
  50233     { /* SOC_REG_INT_OCB_SBUS_LAST_IN_CHAINr */
  50234         soc_block_list[51],
  50235         soc_genreg,
  50236         1,
  50237         0,
  50238         0x87,
  50239         0,
  50240         0,
  50241         1,
  50242         soc_OCB_SBUS_LAST_IN_CHAINr_fields,
  50243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50244         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50245         -1,
  50246         -1,
  50247     },
  50248 #endif /* chips */
  50249 
  50250 #if defined(BCM_88375_A0)
  50251     { /* SOC_REG_INT_OCB_SBUS_LAST_IN_CHAIN_BCM88375_A0r */
  50252         soc_block_list[51],
  50253         soc_genreg,
  50254         1,
  50255         0,
  50256         0x87,
  50257         0,
  50258         0,
  50259         1,
  50260         soc_OCB_SBUS_LAST_IN_CHAIN_BCM88375_A0r_fields,
  50261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50262         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50263         -1,
  50264         -1,
  50265     },
  50266 #endif /* chips */
  50267 
  50268 #if defined(BCM_88375_B0)
  50269     { /* SOC_REG_INT_OCB_SBUS_LAST_IN_CHAIN_BCM88375_B0r */
  50270         soc_block_list[51],
  50271         soc_genreg,
  50272         1,
  50273         0,
  50274         0x87,
  50275         0,
  50276         0,
  50277         1,
  50278         soc_OCB_SBUS_LAST_IN_CHAIN_BCM88375_B0r_fields,
  50279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50280         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50281         -1,
  50282         -1,
  50283     },
  50284 #endif /* chips */
  50285 
  50286 #if defined(BCM_88675_B0)
  50287     { /* SOC_REG_INT_OCB_SBUS_LAST_IN_CHAIN_BCM88675_B0r */
  50288         soc_block_list[51],
  50289         soc_genreg,
  50290         1,
  50291         0,
  50292         0x87,
  50293         0,
  50294         0,
  50295         1,
  50296         soc_OCB_SBUS_LAST_IN_CHAIN_BCM88675_B0r_fields,
  50297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50298         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50299         -1,
  50300         -1,
  50301     },
  50302 #endif /* chips */
  50303 
  50304 #if defined(BCM_88680_A0)
  50305     { /* SOC_REG_INT_OCB_SBUS_LAST_IN_CHAIN_BCM88680_A0r */
  50306         soc_block_list[51],
  50307         soc_genreg,
  50308         1,
  50309         0,
  50310         0x87,
  50311         0,
  50312         0,
  50313         1,
  50314         soc_OCB_SBUS_LAST_IN_CHAIN_BCM88680_A0r_fields,
  50315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50316         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50317         -1,
  50318         -1,
  50319     },
  50320 #endif /* chips */
  50321 
  50322 #if defined(BCM_88690_A0)
  50323     { /* SOC_REG_INT_OCB_SBUS_LAST_IN_CHAIN_BCM88690_A0r */
  50324         soc_block_list[51],
  50325         soc_genreg,
  50326         1,
  50327         0,
  50328         0x87,
  50329         0,
  50330         0,
  50331         1,
  50332         soc_OCB_SBUS_LAST_IN_CHAIN_BCM88690_A0r_fields,
  50333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50334         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50335         -1,
  50336         -1,
  50337     },
  50338 #endif /* chips */
  50339 
  50340 #if defined(BCM_88690_B0)
  50341     { /* SOC_REG_INT_OCB_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
  50342         soc_block_list[51],
  50343         soc_genreg,
  50344         1,
  50345         0,
  50346         0x87,
  50347         0,
  50348         0,
  50349         1,
  50350         soc_OCB_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
  50351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50352         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50353         -1,
  50354         -1,
  50355     },
  50356 #endif /* chips */
  50357 
  50358 #if defined(BCM_88690_B0)
  50359     { /* SOC_REG_INT_OCB_SPECIAL_CLOCK_CONTROLSr */
  50360         soc_block_list[51],
  50361         soc_genreg,
  50362         1,
  50363         0,
  50364         0xc1,
  50365         0,
  50366         0,
  50367         1,
  50368         soc_OCB_SPECIAL_CLOCK_CONTROLSr_fields,
  50369         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  50370         SOC_RESET_MASK_DEC(0x00000002, 0x00000000)
  50371         -1,
  50372         -1,
  50373     },
  50374 #endif /* chips */
  50375 
  50376 #if defined(BCM_88690_A0)
  50377     { /* SOC_REG_INT_OCB_STATISTICS_COUNTERSr */
  50378         soc_block_list[51],
  50379         soc_genreg,
  50380         1,
  50381         0,
  50382         0x116,
  50383         SOC_REG_FLAG_ABOVE_64_BITS |
  50384                           SOC_REG_FLAG_RO,
  50385         SOC_REG_FLAG_COUNTER_FEILDS,
  50386         4,
  50387         soc_OCB_STATISTICS_COUNTERSr_fields,
  50388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50389         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50390         -1,
  50391         -1,
  50392     },
  50393 #endif /* chips */
  50394 
  50395 #if defined(BCM_88690_B0)
  50396     { /* SOC_REG_INT_OCB_STATISTICS_COUNTERS_BCM88690_B0r */
  50397         soc_block_list[51],
  50398         soc_genreg,
  50399         1,
  50400         0,
  50401         0x118,
  50402         SOC_REG_FLAG_ABOVE_64_BITS |
  50403                           SOC_REG_FLAG_RO,
  50404         SOC_REG_FLAG_COUNTER_FEILDS,
  50405         4,
  50406         soc_OCB_STATISTICS_COUNTERS_BCM88690_B0r_fields,
  50407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50408         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50409         -1,
  50410         -1,
  50411     },
  50412 #endif /* chips */
  50413 
  50414 #if defined(BCM_88790_A0)
  50415     { /* SOC_REG_INT_OCCG_ECC_INTERRUPT_REGISTERr */
  50416         soc_block_list[98],
  50417         soc_genreg,
  50418         1,
  50419         0,
  50420         0x7,
  50421         SOC_REG_FLAG_INTERRUPT |
  50422                           SOC_REG_FLAG_SIGNAL,
  50423         0,
  50424         3,
  50425         soc_OCCG_ECC_INTERRUPT_REGISTERr_fields,
  50426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50427         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  50428         -1,
  50429         -1,
  50430     },
  50431 #endif /* chips */
  50432 
  50433 #if defined(BCM_88790_A0)
  50434     { /* SOC_REG_INT_OCCG_ECC_INTERRUPT_REGISTER_MASKr */
  50435         soc_block_list[98],
  50436         soc_genreg,
  50437         1,
  50438         0,
  50439         0x17,
  50440         0,
  50441         0,
  50442         3,
  50443         soc_OCCG_ECC_INTERRUPT_REGISTER_MASKr_fields,
  50444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50445         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  50446         -1,
  50447         -1,
  50448     },
  50449 #endif /* chips */
  50450 
  50451 #if defined(BCM_88790_A0)
  50452     { /* SOC_REG_INT_OCCG_ECC_INTERRUPT_REGISTER_TESTr */
  50453         soc_block_list[98],
  50454         soc_genreg,
  50455         1,
  50456         0,
  50457         0x1f,
  50458         0,
  50459         0,
  50460         1,
  50461         soc_OCCG_ECC_INTERRUPT_REGISTER_TESTr_fields,
  50462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50463         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  50464         -1,
  50465         -1,
  50466     },
  50467 #endif /* chips */
  50468 
  50469 #if defined(BCM_88950_A0)
  50470     { /* SOC_REG_INT_OCCG_GTIMER_CONFIGURATIONr */
  50471         soc_block_list[98],
  50472         soc_genreg,
  50473         1,
  50474         0,
  50475         0x88,
  50476         0,
  50477         0,
  50478         3,
  50479         soc_CCS_GTIMER_CONFIGURATION_BCM88950_A0r_fields,
  50480         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  50481         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50482         -1,
  50483         -1,
  50484     },
  50485 #endif /* chips */
  50486 
  50487 #if defined(BCM_88950_A0)
  50488     { /* SOC_REG_INT_OCCG_GTIMER_TRIGGERr */
  50489         soc_block_list[98],
  50490         soc_genreg,
  50491         1,
  50492         0,
  50493         0x89,
  50494         SOC_REG_FLAG_RO,
  50495         0,
  50496         1,
  50497         soc_BRDC_CCS_GTIMER_TRIGGERr_fields,
  50498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50499         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50500         -1,
  50501         -1,
  50502     },
  50503 #endif /* chips */
  50504 
  50505 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50506     defined(BCM_88754_A0)
  50507     { /* SOC_REG_INT_OCCG_INTERRUPT_MASK_REGISTERr */
  50508         soc_block_list[98],
  50509         soc_genreg,
  50510         1,
  50511         0,
  50512         0x10,
  50513         0,
  50514         0,
  50515         6,
  50516         soc_OCCG_INTERRUPT_MASK_REGISTERr_fields,
  50517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50518         SOC_RESET_MASK_DEC(0x0000009f, 0x00000000)
  50519         -1,
  50520         -1,
  50521     },
  50522 #endif /* chips */
  50523 
  50524 #if defined(BCM_88790_A0)
  50525     { /* SOC_REG_INT_OCCG_INTERRUPT_MASK_REGISTER_BCM88790_A0r */
  50526         soc_block_list[98],
  50527         soc_genreg,
  50528         1,
  50529         0,
  50530         0x10,
  50531         0,
  50532         0,
  50533         7,
  50534         soc_OCCG_INTERRUPT_MASK_REGISTER_BCM88790_A0r_fields,
  50535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50536         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50537         -1,
  50538         -1,
  50539     },
  50540 #endif /* chips */
  50541 
  50542 #if defined(BCM_88950_A0)
  50543     { /* SOC_REG_INT_OCCG_INTERRUPT_MASK_REGISTER_BCM88950_A0r */
  50544         soc_block_list[98],
  50545         soc_genreg,
  50546         1,
  50547         0,
  50548         0x10,
  50549         0,
  50550         0,
  50551         7,
  50552         soc_OCCG_INTERRUPT_MASK_REGISTER_BCM88950_A0r_fields,
  50553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50554         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50555         -1,
  50556         -1,
  50557     },
  50558 #endif /* chips */
  50559 
  50560 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50561     defined(BCM_88754_A0)
  50562     { /* SOC_REG_INT_OCCG_INTERRUPT_REGISTERr */
  50563         soc_block_list[98],
  50564         soc_genreg,
  50565         1,
  50566         0,
  50567         0,
  50568         SOC_REG_FLAG_RO |
  50569                           SOC_REG_FLAG_INTERRUPT,
  50570         0,
  50571         6,
  50572         soc_OCCG_INTERRUPT_REGISTERr_fields,
  50573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50574         SOC_RESET_MASK_DEC(0x0000009f, 0x00000000)
  50575         -1,
  50576         -1,
  50577     },
  50578 #endif /* chips */
  50579 
  50580 #if defined(BCM_88790_A0)
  50581     { /* SOC_REG_INT_OCCG_INTERRUPT_REGISTER_BCM88790_A0r */
  50582         soc_block_list[98],
  50583         soc_genreg,
  50584         1,
  50585         0,
  50586         0,
  50587         SOC_REG_FLAG_INTERRUPT |
  50588                           SOC_REG_FLAG_SIGNAL,
  50589         0,
  50590         7,
  50591         soc_OCCG_INTERRUPT_REGISTER_BCM88790_A0r_fields,
  50592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50593         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50594         -1,
  50595         -1,
  50596     },
  50597 #endif /* chips */
  50598 
  50599 #if defined(BCM_88950_A0)
  50600     { /* SOC_REG_INT_OCCG_INTERRUPT_REGISTER_BCM88950_A0r */
  50601         soc_block_list[98],
  50602         soc_genreg,
  50603         1,
  50604         0,
  50605         0,
  50606         SOC_REG_FLAG_INTERRUPT,
  50607         0,
  50608         7,
  50609         soc_OCCG_INTERRUPT_REGISTER_BCM88950_A0r_fields,
  50610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50611         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50612         -1,
  50613         -1,
  50614     },
  50615 #endif /* chips */
  50616 
  50617 #if defined(BCM_88950_A0)
  50618     { /* SOC_REG_INT_OCCG_INTERRUPT_REGISTER_TESTr */
  50619         soc_block_list[98],
  50620         soc_genreg,
  50621         1,
  50622         0,
  50623         0x18,
  50624         0,
  50625         0,
  50626         1,
  50627         soc_CCS_INTERRUPT_REGISTER_TESTr_fields,
  50628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50629         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50630         -1,
  50631         -1,
  50632     },
  50633 #endif /* chips */
  50634 
  50635 #if defined(BCM_88790_A0)
  50636     { /* SOC_REG_INT_OCCG_INTERRUPT_REGISTER_TEST_BCM88790_A0r */
  50637         soc_block_list[98],
  50638         soc_genreg,
  50639         1,
  50640         0,
  50641         0x18,
  50642         0,
  50643         0,
  50644         1,
  50645         soc_OCCG_INTERRUPT_REGISTER_TESTr_fields,
  50646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50647         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50648         -1,
  50649         -1,
  50650     },
  50651 #endif /* chips */
  50652 
  50653 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50654     defined(BCM_88754_A0)
  50655     { /* SOC_REG_INT_OCCG_REG_0050r */
  50656         soc_block_list[98],
  50657         soc_genreg,
  50658         1,
  50659         0,
  50660         0x50,
  50661         0,
  50662         0,
  50663         1,
  50664         soc_ECI_REG_0050r_fields,
  50665         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  50666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50667         -1,
  50668         -1,
  50669     },
  50670 #endif /* chips */
  50671 
  50672 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50673     defined(BCM_88754_A0)
  50674     { /* SOC_REG_INT_OCCG_REG_0051r */
  50675         soc_block_list[98],
  50676         soc_genreg,
  50677         1,
  50678         0,
  50679         0x51,
  50680         0,
  50681         0,
  50682         1,
  50683         soc_ECI_REG_0051r_fields,
  50684         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  50685         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50686         -1,
  50687         -1,
  50688     },
  50689 #endif /* chips */
  50690 
  50691 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50692     defined(BCM_88754_A0)
  50693     { /* SOC_REG_INT_OCCG_REG_0052r */
  50694         soc_block_list[98],
  50695         soc_genreg,
  50696         1,
  50697         0,
  50698         0x52,
  50699         0,
  50700         0,
  50701         1,
  50702         soc_ECI_REG_0052r_fields,
  50703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50705         -1,
  50706         -1,
  50707     },
  50708 #endif /* chips */
  50709 
  50710 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50711     defined(BCM_88754_A0)
  50712     { /* SOC_REG_INT_OCCG_REG_0053r */
  50713         soc_block_list[98],
  50714         soc_genreg,
  50715         1,
  50716         0,
  50717         0x53,
  50718         0,
  50719         0,
  50720         1,
  50721         soc_ECI_REG_0053r_fields,
  50722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50724         -1,
  50725         -1,
  50726     },
  50727 #endif /* chips */
  50728 
  50729 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50730     defined(BCM_88754_A0)
  50731     { /* SOC_REG_INT_OCCG_REG_0055r */
  50732         soc_block_list[98],
  50733         soc_genreg,
  50734         1,
  50735         0,
  50736         0x55,
  50737         0,
  50738         0,
  50739         1,
  50740         soc_DCMA_REG_0055r_fields,
  50741         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  50742         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  50743         -1,
  50744         -1,
  50745     },
  50746 #endif /* chips */
  50747 
  50748 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50749     defined(BCM_88754_A0)
  50750     { /* SOC_REG_INT_OCCG_REG_0056r */
  50751         soc_block_list[98],
  50752         soc_genreg,
  50753         1,
  50754         0,
  50755         0x56,
  50756         SOC_REG_FLAG_ABOVE_64_BITS,
  50757         0,
  50758         16,
  50759         soc_OCCG_REG_0056r_fields,
  50760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50762         -1,
  50763         -1,
  50764     },
  50765 #endif /* chips */
  50766 
  50767 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50768     defined(BCM_88754_A0)
  50769     { /* SOC_REG_INT_OCCG_REG_0059r */
  50770         soc_block_list[98],
  50771         soc_genreg,
  50772         1,
  50773         0,
  50774         0x59,
  50775         SOC_REG_FLAG_RO,
  50776         0,
  50777         5,
  50778         soc_OCCG_REG_0059r_fields,
  50779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50781         -1,
  50782         -1,
  50783     },
  50784 #endif /* chips */
  50785 
  50786 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50787     defined(BCM_88754_A0)
  50788     { /* SOC_REG_INT_OCCG_REG_0062r */
  50789         soc_block_list[98],
  50790         soc_genreg,
  50791         1,
  50792         0,
  50793         0x62,
  50794         SOC_REG_FLAG_RO,
  50795         0,
  50796         2,
  50797         soc_OCCG_REG_0062r_fields,
  50798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50799         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50800         -1,
  50801         -1,
  50802     },
  50803 #endif /* chips */
  50804 
  50805 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50806     defined(BCM_88754_A0)
  50807     { /* SOC_REG_INT_OCCG_REG_0063r */
  50808         soc_block_list[98],
  50809         soc_genreg,
  50810         1,
  50811         0,
  50812         0x63,
  50813         SOC_REG_FLAG_ABOVE_64_BITS,
  50814         0,
  50815         21,
  50816         soc_OCCG_REG_0063r_fields,
  50817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50819         -1,
  50820         -1,
  50821     },
  50822 #endif /* chips */
  50823 
  50824 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50825     defined(BCM_88754_A0)
  50826     { /* SOC_REG_INT_OCCG_REG_0067r */
  50827         soc_block_list[98],
  50828         soc_genreg,
  50829         1,
  50830         0,
  50831         0x67,
  50832         SOC_REG_FLAG_RO,
  50833         0,
  50834         2,
  50835         soc_OCCG_REG_0062r_fields,
  50836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50837         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50838         -1,
  50839         -1,
  50840     },
  50841 #endif /* chips */
  50842 
  50843 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50844     defined(BCM_88754_A0)
  50845     { /* SOC_REG_INT_OCCG_REG_0068r */
  50846         soc_block_list[98],
  50847         soc_genreg,
  50848         1,
  50849         0,
  50850         0x68,
  50851         SOC_REG_FLAG_64_BITS,
  50852         0,
  50853         4,
  50854         soc_OCCG_REG_0068r_fields,
  50855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50856         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  50857         -1,
  50858         -1,
  50859     },
  50860 #endif /* chips */
  50861 
  50862 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  50863     defined(BCM_88754_A0)
  50864     { /* SOC_REG_INT_OCCG_REG_0078r */
  50865         soc_block_list[98],
  50866         soc_genreg,
  50867         1,
  50868         0,
  50869         0x78,
  50870         SOC_REG_FLAG_64_BITS |
  50871                           SOC_REG_FLAG_RO,
  50872         0,
  50873         4,
  50874         soc_OCCG_REG_0078r_fields,
  50875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50876         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  50877         -1,
  50878         -1,
  50879     },
  50880 #endif /* chips */
  50881 
  50882 #if defined(BCM_88950_A0)
  50883     { /* SOC_REG_INT_OCCG_REG_0087r */
  50884         soc_block_list[98],
  50885         soc_genreg,
  50886         1,
  50887         0,
  50888         0x87,
  50889         0,
  50890         0,
  50891         1,
  50892         soc_OCCG_REG_0087r_fields,
  50893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50894         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50895         -1,
  50896         -1,
  50897     },
  50898 #endif /* chips */
  50899 
  50900 #if defined(BCM_88790_A0)
  50901     { /* SOC_REG_INT_OCCG_REG_0100r */
  50902         soc_block_list[98],
  50903         soc_genreg,
  50904         1,
  50905         0,
  50906         0x100,
  50907         SOC_REG_FLAG_ABOVE_64_BITS,
  50908         0,
  50909         16,
  50910         soc_OCCG_REG_0100r_fields,
  50911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50912         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50913         -1,
  50914         -1,
  50915     },
  50916 #endif /* chips */
  50917 
  50918 #if defined(BCM_88790_A0)
  50919     { /* SOC_REG_INT_OCCG_REG_0104r */
  50920         soc_block_list[98],
  50921         soc_genreg,
  50922         1,
  50923         0,
  50924         0x104,
  50925         SOC_REG_FLAG_64_BITS,
  50926         0,
  50927         5,
  50928         soc_OCCG_REG_0104r_fields,
  50929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50930         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  50931         -1,
  50932         -1,
  50933     },
  50934 #endif /* chips */
  50935 
  50936 #if defined(BCM_88790_A0)
  50937     { /* SOC_REG_INT_OCCG_REG_0106r */
  50938         soc_block_list[98],
  50939         soc_genreg,
  50940         1,
  50941         0,
  50942         0x106,
  50943         SOC_REG_FLAG_ABOVE_64_BITS,
  50944         0,
  50945         17,
  50946         soc_OCCG_REG_0106r_fields,
  50947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50948         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50949         -1,
  50950         -1,
  50951     },
  50952 #endif /* chips */
  50953 
  50954 #if defined(BCM_88790_A0)
  50955     { /* SOC_REG_INT_OCCG_REG_0110r */
  50956         soc_block_list[98],
  50957         soc_genreg,
  50958         1,
  50959         0,
  50960         0x110,
  50961         SOC_REG_FLAG_ABOVE_64_BITS,
  50962         0,
  50963         21,
  50964         soc_OCCG_REG_0110r_fields,
  50965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50966         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50967         -1,
  50968         -1,
  50969     },
  50970 #endif /* chips */
  50971 
  50972 #if defined(BCM_88790_A0)
  50973     { /* SOC_REG_INT_OCCG_REG_0114r */
  50974         soc_block_list[98],
  50975         soc_genreg,
  50976         1,
  50977         0,
  50978         0x114,
  50979         0,
  50980         0,
  50981         2,
  50982         soc_OCCG_REG_0114r_fields,
  50983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50984         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50985         -1,
  50986         -1,
  50987     },
  50988 #endif /* chips */
  50989 
  50990 #if defined(BCM_88790_A0)
  50991     { /* SOC_REG_INT_OCCG_REG_0115r */
  50992         soc_block_list[98],
  50993         soc_genreg,
  50994         1,
  50995         0,
  50996         0x115,
  50997         SOC_REG_FLAG_64_BITS,
  50998         0,
  50999         4,
  51000         soc_OCCG_REG_0115r_fields,
  51001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51002         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  51003         -1,
  51004         -1,
  51005     },
  51006 #endif /* chips */
  51007 
  51008 #if defined(BCM_88790_A0)
  51009     { /* SOC_REG_INT_OCCG_REG_0117r */
  51010         soc_block_list[98],
  51011         soc_genreg,
  51012         1,
  51013         0,
  51014         0x117,
  51015         0,
  51016         0,
  51017         2,
  51018         soc_OCCG_REG_0117r_fields,
  51019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51020         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  51021         -1,
  51022         -1,
  51023     },
  51024 #endif /* chips */
  51025 
  51026 #if defined(BCM_88790_A0)
  51027     { /* SOC_REG_INT_OCCG_REG_0118r */
  51028         soc_block_list[98],
  51029         soc_genreg,
  51030         1,
  51031         0,
  51032         0x118,
  51033         SOC_REG_FLAG_ABOVE_64_BITS |
  51034                           SOC_REG_FLAG_RO,
  51035         0,
  51036         1,
  51037         soc_OCCG_REG_0118r_fields,
  51038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51040         -1,
  51041         -1,
  51042     },
  51043 #endif /* chips */
  51044 
  51045 #if defined(BCM_88790_A0)
  51046     { /* SOC_REG_INT_OCCG_REG_0120r */
  51047         soc_block_list[98],
  51048         soc_genreg,
  51049         1,
  51050         0,
  51051         0x120,
  51052         SOC_REG_FLAG_ABOVE_64_BITS,
  51053         0,
  51054         1,
  51055         soc_OCCG_REG_0120r_fields,
  51056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51057         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51058         -1,
  51059         -1,
  51060     },
  51061 #endif /* chips */
  51062 
  51063 #if defined(BCM_88790_A0)
  51064     { /* SOC_REG_INT_OCCG_REG_0130r */
  51065         soc_block_list[98],
  51066         soc_genreg,
  51067         1,
  51068         0,
  51069         0x130,
  51070         SOC_REG_FLAG_64_BITS,
  51071         0,
  51072         6,
  51073         soc_OCCG_REG_0130r_fields,
  51074         SOC_RESET_VAL_DEC(0x190000c8, 0x00032000)
  51075         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  51076         -1,
  51077         -1,
  51078     },
  51079 #endif /* chips */
  51080 
  51081 #if defined(BCM_88790_A0)
  51082     { /* SOC_REG_INT_OCCG_REG_0132r */
  51083         soc_block_list[98],
  51084         soc_genreg,
  51085         1,
  51086         0,
  51087         0x132,
  51088         SOC_REG_FLAG_64_BITS,
  51089         0,
  51090         4,
  51091         soc_OCCG_REG_0132r_fields,
  51092         SOC_RESET_VAL_DEC(0x190000c8, 0x00000000)
  51093         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  51094         -1,
  51095         -1,
  51096     },
  51097 #endif /* chips */
  51098 
  51099 #if defined(BCM_88950_A0)
  51100     { /* SOC_REG_INT_OCCG_REG_0056_BCM88950_A0r */
  51101         soc_block_list[98],
  51102         soc_genreg,
  51103         1,
  51104         0,
  51105         0x56,
  51106         SOC_REG_FLAG_ABOVE_64_BITS,
  51107         0,
  51108         16,
  51109         soc_OCCG_REG_0056_BCM88950_A0r_fields,
  51110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51112         -1,
  51113         -1,
  51114     },
  51115 #endif /* chips */
  51116 
  51117 #if defined(BCM_88950_A0)
  51118     { /* SOC_REG_INT_OCCG_REG_0059_BCM88950_A0r */
  51119         soc_block_list[98],
  51120         soc_genreg,
  51121         1,
  51122         0,
  51123         0x59,
  51124         0,
  51125         0,
  51126         5,
  51127         soc_OCCG_REG_0059_BCM88950_A0r_fields,
  51128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51129         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51130         -1,
  51131         -1,
  51132     },
  51133 #endif /* chips */
  51134 
  51135 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  51136     defined(BCM_88754_A0)
  51137     { /* SOC_REG_INT_OCCG_REG_005Ar */
  51138         soc_block_list[98],
  51139         soc_genreg,
  51140         1,
  51141         0,
  51142         0x5a,
  51143         SOC_REG_FLAG_ABOVE_64_BITS,
  51144         0,
  51145         17,
  51146         soc_OCCG_REG_005Ar_fields,
  51147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51148         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51149         -1,
  51150         -1,
  51151     },
  51152 #endif /* chips */
  51153 
  51154 #if defined(BCM_88950_A0)
  51155     { /* SOC_REG_INT_OCCG_REG_005A_BCM88950_A0r */
  51156         soc_block_list[98],
  51157         soc_genreg,
  51158         1,
  51159         0,
  51160         0x5a,
  51161         SOC_REG_FLAG_ABOVE_64_BITS,
  51162         0,
  51163         17,
  51164         soc_OCCG_REG_005A_BCM88950_A0r_fields,
  51165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51166         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51167         -1,
  51168         -1,
  51169     },
  51170 #endif /* chips */
  51171 
  51172 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  51173     defined(BCM_88754_A0)
  51174     { /* SOC_REG_INT_OCCG_REG_005Er */
  51175         soc_block_list[98],
  51176         soc_genreg,
  51177         1,
  51178         0,
  51179         0x5e,
  51180         SOC_REG_FLAG_RO,
  51181         0,
  51182         4,
  51183         soc_OCCG_REG_005Er_fields,
  51184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51185         SOC_RESET_MASK_DEC(0x80007fff, 0x00000000)
  51186         -1,
  51187         -1,
  51188     },
  51189 #endif /* chips */
  51190 
  51191 #if defined(BCM_88950_A0)
  51192     { /* SOC_REG_INT_OCCG_REG_005E_BCM88950_A0r */
  51193         soc_block_list[98],
  51194         soc_genreg,
  51195         1,
  51196         0,
  51197         0x5e,
  51198         0,
  51199         0,
  51200         4,
  51201         soc_OCCG_REG_005E_BCM88950_A0r_fields,
  51202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51203         SOC_RESET_MASK_DEC(0x80007fff, 0x00000000)
  51204         -1,
  51205         -1,
  51206     },
  51207 #endif /* chips */
  51208 
  51209 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  51210     defined(BCM_88754_A0)
  51211     { /* SOC_REG_INT_OCCG_REG_005Fr */
  51212         soc_block_list[98],
  51213         soc_genreg,
  51214         1,
  51215         0,
  51216         0x5f,
  51217         SOC_REG_FLAG_ABOVE_64_BITS,
  51218         0,
  51219         22,
  51220         soc_OCCG_REG_005Fr_fields,
  51221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51222         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51223         -1,
  51224         -1,
  51225     },
  51226 #endif /* chips */
  51227 
  51228 #if defined(BCM_88950_A0)
  51229     { /* SOC_REG_INT_OCCG_REG_005F_BCM88950_A0r */
  51230         soc_block_list[98],
  51231         soc_genreg,
  51232         1,
  51233         0,
  51234         0x5f,
  51235         SOC_REG_FLAG_ABOVE_64_BITS,
  51236         0,
  51237         19,
  51238         soc_OCCG_REG_005F_BCM88950_A0r_fields,
  51239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51240         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51241         -1,
  51242         -1,
  51243     },
  51244 #endif /* chips */
  51245 
  51246 #if defined(BCM_88950_A0)
  51247     { /* SOC_REG_INT_OCCG_REG_0062_BCM88950_A0r */
  51248         soc_block_list[98],
  51249         soc_genreg,
  51250         1,
  51251         0,
  51252         0x62,
  51253         0,
  51254         0,
  51255         2,
  51256         soc_OCCG_REG_0062_BCM88950_A0r_fields,
  51257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51258         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  51259         -1,
  51260         -1,
  51261     },
  51262 #endif /* chips */
  51263 
  51264 #if defined(BCM_88950_A0)
  51265     { /* SOC_REG_INT_OCCG_REG_0063_BCM88950_A0r */
  51266         soc_block_list[98],
  51267         soc_genreg,
  51268         1,
  51269         0,
  51270         0x63,
  51271         SOC_REG_FLAG_ABOVE_64_BITS,
  51272         0,
  51273         21,
  51274         soc_OCCG_REG_0063_BCM88950_A0r_fields,
  51275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51276         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51277         -1,
  51278         -1,
  51279     },
  51280 #endif /* chips */
  51281 
  51282 #if defined(BCM_88950_A0)
  51283     { /* SOC_REG_INT_OCCG_REG_0067_BCM88950_A0r */
  51284         soc_block_list[98],
  51285         soc_genreg,
  51286         1,
  51287         0,
  51288         0x67,
  51289         0,
  51290         0,
  51291         2,
  51292         soc_OCCG_REG_0062_BCM88950_A0r_fields,
  51293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51294         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  51295         -1,
  51296         -1,
  51297     },
  51298 #endif /* chips */
  51299 
  51300 #if defined(BCM_88950_A0)
  51301     { /* SOC_REG_INT_OCCG_REG_0068_BCM88950_A0r */
  51302         soc_block_list[98],
  51303         soc_genreg,
  51304         1,
  51305         0,
  51306         0x68,
  51307         SOC_REG_FLAG_64_BITS,
  51308         0,
  51309         4,
  51310         soc_OCCG_REG_0068_BCM88950_A0r_fields,
  51311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51312         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  51313         -1,
  51314         -1,
  51315     },
  51316 #endif /* chips */
  51317 
  51318 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  51319     defined(BCM_88754_A0)
  51320     { /* SOC_REG_INT_OCCG_REG_006Ar */
  51321         soc_block_list[98],
  51322         soc_genreg,
  51323         1,
  51324         0,
  51325         0x6a,
  51326         SOC_REG_FLAG_RO,
  51327         0,
  51328         2,
  51329         soc_OCCG_REG_0062r_fields,
  51330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51331         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  51332         -1,
  51333         -1,
  51334     },
  51335 #endif /* chips */
  51336 
  51337 #if defined(BCM_88950_A0)
  51338     { /* SOC_REG_INT_OCCG_REG_006A_BCM88950_A0r */
  51339         soc_block_list[98],
  51340         soc_genreg,
  51341         1,
  51342         0,
  51343         0x6a,
  51344         0,
  51345         0,
  51346         2,
  51347         soc_OCCG_REG_0062_BCM88950_A0r_fields,
  51348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51349         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  51350         -1,
  51351         -1,
  51352     },
  51353 #endif /* chips */
  51354 
  51355 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  51356     defined(BCM_88754_A0)
  51357     { /* SOC_REG_INT_OCCG_REG_006Br */
  51358         soc_block_list[98],
  51359         soc_genreg,
  51360         1,
  51361         0,
  51362         0x6b,
  51363         SOC_REG_FLAG_ABOVE_64_BITS |
  51364                           SOC_REG_FLAG_RO,
  51365         0,
  51366         1,
  51367         soc_DCL_REG_00AAr_fields,
  51368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51370         -1,
  51371         -1,
  51372     },
  51373 #endif /* chips */
  51374 
  51375 #if defined(BCM_88950_A0)
  51376     { /* SOC_REG_INT_OCCG_REG_006B_BCM88950_A0r */
  51377         soc_block_list[98],
  51378         soc_genreg,
  51379         1,
  51380         0,
  51381         0x6b,
  51382         SOC_REG_FLAG_ABOVE_64_BITS |
  51383                           SOC_REG_FLAG_RO,
  51384         0,
  51385         1,
  51386         soc_OCCG_REG_006Br_fields,
  51387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51388         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51389         -1,
  51390         -1,
  51391     },
  51392 #endif /* chips */
  51393 
  51394 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  51395     defined(BCM_88754_A0)
  51396     { /* SOC_REG_INT_OCCG_REG_006Fr */
  51397         soc_block_list[98],
  51398         soc_genreg,
  51399         1,
  51400         0,
  51401         0x6f,
  51402         SOC_REG_FLAG_ABOVE_64_BITS,
  51403         0,
  51404         1,
  51405         soc_OCCG_REG_006Fr_fields,
  51406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51408         -1,
  51409         -1,
  51410     },
  51411 #endif /* chips */
  51412 
  51413 #if defined(BCM_88950_A0)
  51414     { /* SOC_REG_INT_OCCG_REG_006F_BCM88950_A0r */
  51415         soc_block_list[98],
  51416         soc_genreg,
  51417         1,
  51418         0,
  51419         0x6f,
  51420         SOC_REG_FLAG_ABOVE_64_BITS,
  51421         0,
  51422         1,
  51423         soc_OCCG_REG_006F_BCM88950_A0r_fields,
  51424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51426         -1,
  51427         -1,
  51428     },
  51429 #endif /* chips */
  51430 
  51431 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  51432     defined(BCM_88754_A0)
  51433     { /* SOC_REG_INT_OCCG_REG_007Cr */
  51434         soc_block_list[98],
  51435         soc_genreg,
  51436         1,
  51437         0,
  51438         0x7c,
  51439         0,
  51440         0,
  51441         1,
  51442         soc_OCCG_REG_007Cr_fields,
  51443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51444         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  51445         -1,
  51446         -1,
  51447     },
  51448 #endif /* chips */
  51449 
  51450 #if defined(BCM_88790_A0)
  51451     { /* SOC_REG_INT_OCCG_REG_0087_BCM88790_A0r */
  51452         soc_block_list[98],
  51453         soc_genreg,
  51454         1,
  51455         0,
  51456         0x87,
  51457         0,
  51458         0,
  51459         1,
  51460         soc_OCCG_REG_0087_BCM88790_A0r_fields,
  51461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51462         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  51463         -1,
  51464         -1,
  51465     },
  51466 #endif /* chips */
  51467 
  51468 #if defined(BCM_88790_A0)
  51469     { /* SOC_REG_INT_OCCG_REG_010Ar */
  51470         soc_block_list[98],
  51471         soc_genreg,
  51472         1,
  51473         0,
  51474         0x10a,
  51475         0,
  51476         0,
  51477         4,
  51478         soc_OCCG_REG_010Ar_fields,
  51479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51480         SOC_RESET_MASK_DEC(0x803fffff, 0x00000000)
  51481         -1,
  51482         -1,
  51483     },
  51484 #endif /* chips */
  51485 
  51486 #if defined(BCM_88790_A0)
  51487     { /* SOC_REG_INT_OCCG_REG_010Br */
  51488         soc_block_list[98],
  51489         soc_genreg,
  51490         1,
  51491         0,
  51492         0x10b,
  51493         SOC_REG_FLAG_ABOVE_64_BITS,
  51494         0,
  51495         19,
  51496         soc_OCCG_REG_010Br_fields,
  51497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51498         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51499         -1,
  51500         -1,
  51501     },
  51502 #endif /* chips */
  51503 
  51504 #if defined(BCM_88790_A0)
  51505     { /* SOC_REG_INT_OCCG_REG_010Fr */
  51506         soc_block_list[98],
  51507         soc_genreg,
  51508         1,
  51509         0,
  51510         0x10f,
  51511         0,
  51512         0,
  51513         2,
  51514         soc_OCCG_REG_010Fr_fields,
  51515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51516         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  51517         -1,
  51518         -1,
  51519     },
  51520 #endif /* chips */
  51521 
  51522 #if defined(BCM_88950_A0)
  51523     { /* SOC_REG_INT_OCCG_RESERVED_MIRROR_ADDRr */
  51524         soc_block_list[98],
  51525         soc_genreg,
  51526         1,
  51527         0,
  51528         0x85,
  51529         0,
  51530         0,
  51531         2,
  51532         soc_CCS_RESERVED_MIRROR_ADDRr_fields,
  51533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51534         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  51535         -1,
  51536         -1,
  51537     },
  51538 #endif /* chips */
  51539 
  51540 #if defined(BCM_88790_A0)
  51541     { /* SOC_REG_INT_OCCG_RESERVED_MIRROR_ADDR_BCM88790_A0r */
  51542         soc_block_list[98],
  51543         soc_genreg,
  51544         1,
  51545         0,
  51546         0x85,
  51547         0,
  51548         0,
  51549         2,
  51550         soc_OCCG_RESERVED_MIRROR_ADDRr_fields,
  51551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51552         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  51553         -1,
  51554         -1,
  51555     },
  51556 #endif /* chips */
  51557 
  51558 #if defined(BCM_88950_A0)
  51559     { /* SOC_REG_INT_OCCG_RESERVED_SPARE_0r */
  51560         soc_block_list[98],
  51561         soc_genreg,
  51562         1,
  51563         0,
  51564         0x90,
  51565         0,
  51566         0,
  51567         1,
  51568         soc_CCS_RESERVED_SPARE_0r_fields,
  51569         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  51570         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51571         -1,
  51572         -1,
  51573     },
  51574 #endif /* chips */
  51575 
  51576 #if defined(BCM_88950_A0)
  51577     { /* SOC_REG_INT_OCCG_RESERVED_SPARE_1r */
  51578         soc_block_list[98],
  51579         soc_genreg,
  51580         1,
  51581         0,
  51582         0x91,
  51583         0,
  51584         0,
  51585         1,
  51586         soc_CCS_RESERVED_SPARE_1r_fields,
  51587         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  51588         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51589         -1,
  51590         -1,
  51591     },
  51592 #endif /* chips */
  51593 
  51594 #if defined(BCM_88950_A0)
  51595     { /* SOC_REG_INT_OCCG_RESERVED_SPARE_2r */
  51596         soc_block_list[98],
  51597         soc_genreg,
  51598         1,
  51599         0,
  51600         0x92,
  51601         0,
  51602         0,
  51603         1,
  51604         soc_CCS_RESERVED_SPARE_2r_fields,
  51605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51606         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51607         -1,
  51608         -1,
  51609     },
  51610 #endif /* chips */
  51611 
  51612 #if defined(BCM_88950_A0)
  51613     { /* SOC_REG_INT_OCCG_RESERVED_SPARE_3r */
  51614         soc_block_list[98],
  51615         soc_genreg,
  51616         1,
  51617         0,
  51618         0x93,
  51619         0,
  51620         0,
  51621         1,
  51622         soc_CCS_RESERVED_SPARE_3r_fields,
  51623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51624         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51625         -1,
  51626         -1,
  51627     },
  51628 #endif /* chips */
  51629 
  51630 #if defined(BCM_88790_A0)
  51631     { /* SOC_REG_INT_OCCG_RESERVED_SPARE_0_BCM88790_A0r */
  51632         soc_block_list[98],
  51633         soc_genreg,
  51634         1,
  51635         0,
  51636         0x90,
  51637         0,
  51638         0,
  51639         1,
  51640         soc_OCCG_RESERVED_SPARE_0r_fields,
  51641         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  51642         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51643         -1,
  51644         -1,
  51645     },
  51646 #endif /* chips */
  51647 
  51648 #if defined(BCM_88790_A0)
  51649     { /* SOC_REG_INT_OCCG_RESERVED_SPARE_1_BCM88790_A0r */
  51650         soc_block_list[98],
  51651         soc_genreg,
  51652         1,
  51653         0,
  51654         0x91,
  51655         0,
  51656         0,
  51657         1,
  51658         soc_OCCG_RESERVED_SPARE_1r_fields,
  51659         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  51660         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51661         -1,
  51662         -1,
  51663     },
  51664 #endif /* chips */
  51665 
  51666 #if defined(BCM_88790_A0)
  51667     { /* SOC_REG_INT_OCCG_RESERVED_SPARE_2_BCM88790_A0r */
  51668         soc_block_list[98],
  51669         soc_genreg,
  51670         1,
  51671         0,
  51672         0x92,
  51673         0,
  51674         0,
  51675         1,
  51676         soc_OCCG_RESERVED_SPARE_2r_fields,
  51677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51678         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51679         -1,
  51680         -1,
  51681     },
  51682 #endif /* chips */
  51683 
  51684 #if defined(BCM_88790_A0)
  51685     { /* SOC_REG_INT_OCCG_RESERVED_SPARE_3_BCM88790_A0r */
  51686         soc_block_list[98],
  51687         soc_genreg,
  51688         1,
  51689         0,
  51690         0x93,
  51691         0,
  51692         0,
  51693         1,
  51694         soc_OCCG_RESERVED_SPARE_3r_fields,
  51695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51696         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51697         -1,
  51698         -1,
  51699     },
  51700 #endif /* chips */
  51701 
  51702 #if defined(BCM_88950_A0)
  51703     { /* SOC_REG_INT_OCCG_SBUS_BROADCAST_IDr */
  51704         soc_block_list[98],
  51705         soc_genreg,
  51706         1,
  51707         0,
  51708         0x86,
  51709         0,
  51710         0,
  51711         1,
  51712         soc_DCMC_SBUS_BROADCAST_IDr_fields,
  51713         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  51714         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  51715         -1,
  51716         -1,
  51717     },
  51718 #endif /* chips */
  51719 
  51720 #if defined(BCM_88790_A0)
  51721     { /* SOC_REG_INT_OCCG_SBUS_BROADCAST_ID_BCM88790_A0r */
  51722         soc_block_list[98],
  51723         soc_genreg,
  51724         1,
  51725         0,
  51726         0x86,
  51727         0,
  51728         0,
  51729         1,
  51730         soc_OCCG_SBUS_BROADCAST_IDr_fields,
  51731         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  51732         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  51733         -1,
  51734         -1,
  51735     },
  51736 #endif /* chips */
  51737 
  51738 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  51739     defined(BCM_88754_A0)
  51740     { /* SOC_REG_INT_OCCG_SYNC_TEST_MODE_OPERATIONr */
  51741         soc_block_list[98],
  51742         soc_genreg,
  51743         1,
  51744         0,
  51745         0x7a,
  51746         0,
  51747         0,
  51748         3,
  51749         soc_OCCG_SYNC_TEST_MODE_OPERATIONr_fields,
  51750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51751         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  51752         -1,
  51753         -1,
  51754     },
  51755 #endif /* chips */
  51756 
  51757 #if defined(BCM_88790_A0)
  51758     { /* SOC_REG_INT_OCCG_SYNC_TEST_MODE_OPERATION_BCM88790_A0r */
  51759         soc_block_list[98],
  51760         soc_genreg,
  51761         1,
  51762         0,
  51763         0x12f,
  51764         0,
  51765         0,
  51766         3,
  51767         soc_OCCG_SYNC_TEST_MODE_OPERATION_BCM88790_A0r_fields,
  51768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51769         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  51770         -1,
  51771         -1,
  51772     },
  51773 #endif /* chips */
  51774 
  51775 #if defined(BCM_88950_A0)
  51776     { /* SOC_REG_INT_OCCG_SYNC_TEST_MODE_OPERATION_BCM88950_A0r */
  51777         soc_block_list[98],
  51778         soc_genreg,
  51779         1,
  51780         0,
  51781         0x7a,
  51782         0,
  51783         0,
  51784         3,
  51785         soc_OCCG_SYNC_TEST_MODE_OPERATION_BCM88950_A0r_fields,
  51786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51787         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  51788         -1,
  51789         -1,
  51790     },
  51791 #endif /* chips */
  51792 
  51793 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  51794     { /* SOC_REG_INT_OCCG_TEST_MODE_CMD_REGr */
  51795         soc_block_list[98],
  51796         soc_genreg,
  51797         1,
  51798         0,
  51799         0x73,
  51800         0,
  51801         0,
  51802         6,
  51803         soc_OCCG_TEST_MODE_CMD_REGr_fields,
  51804         SOC_RESET_VAL_DEC(0x00001eff, 0x00000000)
  51805         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  51806         -1,
  51807         -1,
  51808     },
  51809 #endif /* chips */
  51810 
  51811 #if defined(BCM_88754_A0)
  51812     { /* SOC_REG_INT_OCCG_TEST_MODE_CMD_REG_BCM88754_A0r */
  51813         soc_block_list[98],
  51814         soc_genreg,
  51815         1,
  51816         0,
  51817         0x73,
  51818         0,
  51819         0,
  51820         8,
  51821         soc_OCCG_TEST_MODE_CMD_REG_BCM88754_A0r_fields,
  51822         SOC_RESET_VAL_DEC(0x00ffdeff, 0x00000000)
  51823         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  51824         -1,
  51825         -1,
  51826     },
  51827 #endif /* chips */
  51828 
  51829 #if defined(BCM_88790_A0)
  51830     { /* SOC_REG_INT_OCCG_TEST_MODE_CMD_REG_BCM88790_A0r */
  51831         soc_block_list[98],
  51832         soc_genreg,
  51833         1,
  51834         0,
  51835         0x128,
  51836         0,
  51837         0,
  51838         9,
  51839         soc_OCCG_TEST_MODE_CMD_REG_BCM88790_A0r_fields,
  51840         SOC_RESET_VAL_DEC(0x007fdf83, 0x00000000)
  51841         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  51842         -1,
  51843         -1,
  51844     },
  51845 #endif /* chips */
  51846 
  51847 #if defined(BCM_88950_A0)
  51848     { /* SOC_REG_INT_OCCG_TEST_MODE_CMD_REG_BCM88950_A0r */
  51849         soc_block_list[98],
  51850         soc_genreg,
  51851         1,
  51852         0,
  51853         0x73,
  51854         0,
  51855         0,
  51856         8,
  51857         soc_OCCG_TEST_MODE_CMD_REG_BCM88950_A0r_fields,
  51858         SOC_RESET_VAL_DEC(0x007fdeff, 0x00000000)
  51859         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  51860         -1,
  51861         -1,
  51862     },
  51863 #endif /* chips */
  51864 
  51865 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  51866     defined(BCM_88754_A0)
  51867     { /* SOC_REG_INT_OCCG_TEST_MODE_CMD_RESULT_REGr */
  51868         soc_block_list[98],
  51869         soc_genreg,
  51870         1,
  51871         0,
  51872         0x74,
  51873         SOC_REG_FLAG_ABOVE_64_BITS |
  51874                           SOC_REG_FLAG_RO,
  51875         0,
  51876         6,
  51877         soc_OCCG_TEST_MODE_CMD_RESULT_REGr_fields,
  51878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51879         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51880         -1,
  51881         -1,
  51882     },
  51883 #endif /* chips */
  51884 
  51885 #if defined(BCM_88790_A0)
  51886     { /* SOC_REG_INT_OCCG_TEST_MODE_CMD_RESULT_REG_BCM88790_A0r */
  51887         soc_block_list[98],
  51888         soc_genreg,
  51889         1,
  51890         0,
  51891         0x129,
  51892         SOC_REG_FLAG_ABOVE_64_BITS,
  51893         0,
  51894         7,
  51895         soc_OCCG_TEST_MODE_CMD_RESULT_REG_BCM88790_A0r_fields,
  51896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51898         -1,
  51899         -1,
  51900     },
  51901 #endif /* chips */
  51902 
  51903 #if defined(BCM_88950_A0)
  51904     { /* SOC_REG_INT_OCCG_TEST_MODE_CMD_RESULT_REG_BCM88950_A0r */
  51905         soc_block_list[98],
  51906         soc_genreg,
  51907         1,
  51908         0,
  51909         0x74,
  51910         SOC_REG_FLAG_ABOVE_64_BITS,
  51911         0,
  51912         7,
  51913         soc_OCCG_TEST_MODE_CMD_RESULT_REG_BCM88950_A0r_fields,
  51914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51916         -1,
  51917         -1,
  51918     },
  51919 #endif /* chips */
  51920 
  51921 #if defined(BCM_88690_A0)
  51922     { /* SOC_REG_INT_OLP_APP_DB_TO_APP_DB_INDEX_MAPr */
  51923         soc_block_list[42],
  51924         soc_genreg,
  51925         1,
  51926         0,
  51927         0x11f,
  51928         SOC_REG_FLAG_ABOVE_64_BITS,
  51929         0,
  51930         1,
  51931         soc_OLP_APP_DB_TO_APP_DB_INDEX_MAPr_fields,
  51932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51934         -1,
  51935         -1,
  51936     },
  51937 #endif /* chips */
  51938 
  51939 #if defined(BCM_88690_B0)
  51940     { /* SOC_REG_INT_OLP_APP_DB_TO_APP_DB_INDEX_MAP_BCM88690_B0r */
  51941         soc_block_list[42],
  51942         soc_genreg,
  51943         1,
  51944         0,
  51945         0x11f,
  51946         SOC_REG_FLAG_ABOVE_64_BITS,
  51947         0,
  51948         1,
  51949         soc_OLP_APP_DB_TO_APP_DB_INDEX_MAP_BCM88690_B0r_fields,
  51950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51952         -1,
  51953         -1,
  51954     },
  51955 #endif /* chips */
  51956 
  51957 #if defined(BCM_88690_B0)
  51958     { /* SOC_REG_INT_OLP_APP_DB_TO_APP_DB_INDEX_MAP_FOR_ROUTINGr */
  51959         soc_block_list[42],
  51960         soc_genreg,
  51961         1,
  51962         0,
  51963         0x159,
  51964         SOC_REG_FLAG_ABOVE_64_BITS,
  51965         0,
  51966         1,
  51967         soc_OLP_APP_DB_TO_APP_DB_INDEX_MAP_FOR_ROUTINGr_fields,
  51968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51970         -1,
  51971         -1,
  51972     },
  51973 #endif /* chips */
  51974 
  51975 #if defined(BCM_88690_A0)
  51976     { /* SOC_REG_INT_OLP_AUTO_DOC_NAME_0r */
  51977         soc_block_list[42],
  51978         soc_genreg,
  51979         2,
  51980         0,
  51981         0x12b,
  51982         SOC_REG_FLAG_ARRAY |
  51983                           SOC_REG_FLAG_RO |
  51984                           SOC_REG_FLAG_REG_ARRAY |
  51985                           SOC_REG_FLAG_SIGNAL,
  51986         0,
  51987         1,
  51988         soc_OLP_AUTO_DOC_NAME_0r_fields,
  51989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51990         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  51991         -1,
  51992         -1,
  51993     },
  51994 #endif /* chips */
  51995 
  51996 #if defined(BCM_88690_A0)
  51997     { /* SOC_REG_INT_OLP_AUTO_DOC_NAME_1r */
  51998         soc_block_list[42],
  51999         soc_genreg,
  52000         2,
  52001         0,
  52002         0x12f,
  52003         SOC_REG_FLAG_ARRAY |
  52004                           SOC_REG_FLAG_RO |
  52005                           SOC_REG_FLAG_REG_ARRAY,
  52006         SOC_REG_FLAG_INIT_ON_READ,
  52007         1,
  52008         soc_OLP_AUTO_DOC_NAME_1r_fields,
  52009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52010         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  52011         -1,
  52012         -1,
  52013     },
  52014 #endif /* chips */
  52015 
  52016 #if defined(BCM_88690_A0)
  52017     { /* SOC_REG_INT_OLP_AUTO_DOC_NAME_2r */
  52018         soc_block_list[42],
  52019         soc_genreg,
  52020         1,
  52021         0,
  52022         0x133,
  52023         SOC_REG_FLAG_RO |
  52024                           SOC_REG_FLAG_SIGNAL,
  52025         0,
  52026         1,
  52027         soc_OLP_AUTO_DOC_NAME_2r_fields,
  52028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52029         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  52030         -1,
  52031         -1,
  52032     },
  52033 #endif /* chips */
  52034 
  52035 #if defined(BCM_88690_A0)
  52036     { /* SOC_REG_INT_OLP_AUTO_DOC_NAME_3r */
  52037         soc_block_list[42],
  52038         soc_genreg,
  52039         1,
  52040         0,
  52041         0x134,
  52042         SOC_REG_FLAG_RO,
  52043         SOC_REG_FLAG_INIT_ON_READ,
  52044         1,
  52045         soc_OLP_AUTO_DOC_NAME_3r_fields,
  52046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52047         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  52048         -1,
  52049         -1,
  52050     },
  52051 #endif /* chips */
  52052 
  52053 #if defined(BCM_88690_B0)
  52054     { /* SOC_REG_INT_OLP_AUTO_DOC_NAME_0_BCM88690_B0r */
  52055         soc_block_list[42],
  52056         soc_genreg,
  52057         2,
  52058         0,
  52059         0x12b,
  52060         SOC_REG_FLAG_ARRAY |
  52061                           SOC_REG_FLAG_RO |
  52062                           SOC_REG_FLAG_REG_ARRAY |
  52063                           SOC_REG_FLAG_SIGNAL,
  52064         0,
  52065         1,
  52066         soc_OLP_AUTO_DOC_NAME_0_BCM88690_B0r_fields,
  52067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52068         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  52069         -1,
  52070         -1,
  52071     },
  52072 #endif /* chips */
  52073 
  52074 #if defined(BCM_88690_B0)
  52075     { /* SOC_REG_INT_OLP_AUTO_DOC_NAME_1_BCM88690_B0r */
  52076         soc_block_list[42],
  52077         soc_genreg,
  52078         2,
  52079         0,
  52080         0x12f,
  52081         SOC_REG_FLAG_ARRAY |
  52082                           SOC_REG_FLAG_RO |
  52083                           SOC_REG_FLAG_REG_ARRAY,
  52084         SOC_REG_FLAG_INIT_ON_READ,
  52085         1,
  52086         soc_OLP_AUTO_DOC_NAME_1_BCM88690_B0r_fields,
  52087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52088         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  52089         -1,
  52090         -1,
  52091     },
  52092 #endif /* chips */
  52093 
  52094 #if defined(BCM_88690_B0)
  52095     { /* SOC_REG_INT_OLP_AUTO_DOC_NAME_2_BCM88690_B0r */
  52096         soc_block_list[42],
  52097         soc_genreg,
  52098         1,
  52099         0,
  52100         0x133,
  52101         SOC_REG_FLAG_RO |
  52102                           SOC_REG_FLAG_SIGNAL,
  52103         0,
  52104         1,
  52105         soc_OLP_AUTO_DOC_NAME_2_BCM88690_B0r_fields,
  52106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52107         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  52108         -1,
  52109         -1,
  52110     },
  52111 #endif /* chips */
  52112 
  52113 #if defined(BCM_88690_B0)
  52114     { /* SOC_REG_INT_OLP_AUTO_DOC_NAME_3_BCM88690_B0r */
  52115         soc_block_list[42],
  52116         soc_genreg,
  52117         1,
  52118         0,
  52119         0x134,
  52120         SOC_REG_FLAG_RO,
  52121         SOC_REG_FLAG_INIT_ON_READ,
  52122         1,
  52123         soc_OLP_AUTO_DOC_NAME_3_BCM88690_B0r_fields,
  52124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52125         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  52126         -1,
  52127         -1,
  52128     },
  52129 #endif /* chips */
  52130 
  52131 #if defined(BCM_88690_A0)
  52132     { /* SOC_REG_INT_OLP_CFG_JR_2_CMD_TO_JR_CMD_MAPr */
  52133         soc_block_list[42],
  52134         soc_genreg,
  52135         1,
  52136         0,
  52137         0x12a,
  52138         0,
  52139         0,
  52140         8,
  52141         soc_OLP_CFG_JR_2_CMD_TO_JR_CMD_MAPr_fields,
  52142         SOC_RESET_VAL_DEC(0x00f2b431, 0x00000000)
  52143         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  52144         -1,
  52145         -1,
  52146     },
  52147 #endif /* chips */
  52148 
  52149 #if defined(BCM_88690_B0)
  52150     { /* SOC_REG_INT_OLP_CFG_JR_2_CMD_TO_JR_CMD_MAP_BCM88690_B0r */
  52151         soc_block_list[42],
  52152         soc_genreg,
  52153         1,
  52154         0,
  52155         0x12a,
  52156         0,
  52157         0,
  52158         8,
  52159         soc_OLP_CFG_JR_2_CMD_TO_JR_CMD_MAP_BCM88690_B0r_fields,
  52160         SOC_RESET_VAL_DEC(0x00f2b431, 0x00000000)
  52161         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  52162         -1,
  52163         -1,
  52164     },
  52165 #endif /* chips */
  52166 
  52167 #if defined(BCM_88690_A0)
  52168     { /* SOC_REG_INT_OLP_CFG_JR_CMD_TO_JR_2_CMD_MAPr */
  52169         soc_block_list[42],
  52170         soc_genreg,
  52171         1,
  52172         0,
  52173         0x129,
  52174         0,
  52175         0,
  52176         8,
  52177         soc_OLP_CFG_JR_CMD_TO_JR_2_CMD_MAPr_fields,
  52178         SOC_RESET_VAL_DEC(0x00e6e8c2, 0x00000000)
  52179         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  52180         -1,
  52181         -1,
  52182     },
  52183 #endif /* chips */
  52184 
  52185 #if defined(BCM_88690_B0)
  52186     { /* SOC_REG_INT_OLP_CFG_JR_CMD_TO_JR_2_CMD_MAP_BCM88690_B0r */
  52187         soc_block_list[42],
  52188         soc_genreg,
  52189         1,
  52190         0,
  52191         0x129,
  52192         0,
  52193         0,
  52194         8,
  52195         soc_OLP_CFG_JR_CMD_TO_JR_2_CMD_MAP_BCM88690_B0r_fields,
  52196         SOC_RESET_VAL_DEC(0x00e6e8c2, 0x00000000)
  52197         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  52198         -1,
  52199         -1,
  52200     },
  52201 #endif /* chips */
  52202 
  52203 #if defined(BCM_88690_A0)
  52204     { /* SOC_REG_INT_OLP_CFG_JR_LOGICAL_DB_TYPEr */
  52205         soc_block_list[42],
  52206         soc_genreg,
  52207         1,
  52208         0,
  52209         0x128,
  52210         0,
  52211         0,
  52212         1,
  52213         soc_OLP_CFG_JR_LOGICAL_DB_TYPEr_fields,
  52214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52215         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52216         -1,
  52217         -1,
  52218     },
  52219 #endif /* chips */
  52220 
  52221 #if defined(BCM_88690_B0)
  52222     { /* SOC_REG_INT_OLP_CFG_JR_LOGICAL_DB_TYPE_BCM88690_B0r */
  52223         soc_block_list[42],
  52224         soc_genreg,
  52225         1,
  52226         0,
  52227         0x128,
  52228         0,
  52229         0,
  52230         1,
  52231         soc_OLP_CFG_JR_LOGICAL_DB_TYPE_BCM88690_B0r_fields,
  52232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52233         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52234         -1,
  52235         -1,
  52236     },
  52237 #endif /* chips */
  52238 
  52239 #if defined(BCM_88690_A0)
  52240     { /* SOC_REG_INT_OLP_CFG_JR_TO_JR_2_AGEr */
  52241         soc_block_list[42],
  52242         soc_genreg,
  52243         1,
  52244         0,
  52245         0x125,
  52246         0,
  52247         0,
  52248         1,
  52249         soc_OLP_CFG_JR_TO_JR_2_AGEr_fields,
  52250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52251         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52252         -1,
  52253         -1,
  52254     },
  52255 #endif /* chips */
  52256 
  52257 #if defined(BCM_88690_B0)
  52258     { /* SOC_REG_INT_OLP_CFG_JR_TO_JR_2_AGE_BCM88690_B0r */
  52259         soc_block_list[42],
  52260         soc_genreg,
  52261         1,
  52262         0,
  52263         0x125,
  52264         0,
  52265         0,
  52266         1,
  52267         soc_OLP_CFG_JR_TO_JR_2_AGE_BCM88690_B0r_fields,
  52268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52269         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52270         -1,
  52271         -1,
  52272     },
  52273 #endif /* chips */
  52274 
  52275 #if defined(BCM_88690_A0)
  52276     { /* SOC_REG_INT_OLP_CFG_JR_TO_JR_2_APP_DBr */
  52277         soc_block_list[42],
  52278         soc_genreg,
  52279         1,
  52280         0,
  52281         0x126,
  52282         0,
  52283         0,
  52284         1,
  52285         soc_OLP_CFG_JR_TO_JR_2_APP_DBr_fields,
  52286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52287         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  52288         -1,
  52289         -1,
  52290     },
  52291 #endif /* chips */
  52292 
  52293 #if defined(BCM_88690_B0)
  52294     { /* SOC_REG_INT_OLP_CFG_JR_TO_JR_2_APP_DB_BCM88690_B0r */
  52295         soc_block_list[42],
  52296         soc_genreg,
  52297         1,
  52298         0,
  52299         0x126,
  52300         0,
  52301         0,
  52302         1,
  52303         soc_OLP_CFG_JR_TO_JR_2_APP_DB_BCM88690_B0r_fields,
  52304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52305         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  52306         -1,
  52307         -1,
  52308     },
  52309 #endif /* chips */
  52310 
  52311 #if defined(BCM_88690_A0)
  52312     { /* SOC_REG_INT_OLP_CFG_JR_TO_JR_2_KEY_MASKr */
  52313         soc_block_list[42],
  52314         soc_genreg,
  52315         1,
  52316         0,
  52317         0x127,
  52318         0,
  52319         0,
  52320         1,
  52321         soc_OLP_CFG_JR_TO_JR_2_KEY_MASKr_fields,
  52322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52323         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  52324         -1,
  52325         -1,
  52326     },
  52327 #endif /* chips */
  52328 
  52329 #if defined(BCM_88690_B0)
  52330     { /* SOC_REG_INT_OLP_CFG_JR_TO_JR_2_KEY_MASK_BCM88690_B0r */
  52331         soc_block_list[42],
  52332         soc_genreg,
  52333         1,
  52334         0,
  52335         0x127,
  52336         0,
  52337         0,
  52338         1,
  52339         soc_OLP_CFG_JR_TO_JR_2_KEY_MASK_BCM88690_B0r_fields,
  52340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52341         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  52342         -1,
  52343         -1,
  52344     },
  52345 #endif /* chips */
  52346 
  52347 #if defined(BCM_88690_A0)
  52348     { /* SOC_REG_INT_OLP_CFG_JR_TO_JR_2_VMVr */
  52349         soc_block_list[42],
  52350         soc_genreg,
  52351         1,
  52352         0,
  52353         0x124,
  52354         0,
  52355         0,
  52356         1,
  52357         soc_OLP_CFG_JR_TO_JR_2_VMVr_fields,
  52358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52359         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  52360         -1,
  52361         -1,
  52362     },
  52363 #endif /* chips */
  52364 
  52365 #if defined(BCM_88690_B0)
  52366     { /* SOC_REG_INT_OLP_CFG_JR_TO_JR_2_VMV_BCM88690_B0r */
  52367         soc_block_list[42],
  52368         soc_genreg,
  52369         1,
  52370         0,
  52371         0x124,
  52372         0,
  52373         0,
  52374         1,
  52375         soc_OLP_CFG_JR_TO_JR_2_VMV_BCM88690_B0r_fields,
  52376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52377         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  52378         -1,
  52379         -1,
  52380     },
  52381 #endif /* chips */
  52382 
  52383 #if defined(BCM_88650_A0)
  52384     { /* SOC_REG_INT_OLP_CONFIGS_GENERALr */
  52385         soc_block_list[42],
  52386         soc_genreg,
  52387         1,
  52388         0,
  52389         0x108,
  52390         SOC_REG_FLAG_SIGNAL,
  52391         0,
  52392         2,
  52393         soc_OLP_CONFIGS_GENERALr_fields,
  52394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52395         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  52396         -1,
  52397         -1,
  52398     },
  52399 #endif /* chips */
  52400 
  52401 #if defined(BCM_88650_B0)
  52402     { /* SOC_REG_INT_OLP_CONFIGS_GENERAL_BCM88650_B0r */
  52403         soc_block_list[42],
  52404         soc_genreg,
  52405         1,
  52406         0,
  52407         0x108,
  52408         SOC_REG_FLAG_SIGNAL,
  52409         0,
  52410         2,
  52411         soc_OLP_CONFIGS_GENERAL_BCM88650_B0r_fields,
  52412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52413         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  52414         -1,
  52415         -1,
  52416     },
  52417 #endif /* chips */
  52418 
  52419 #if defined(BCM_88660_A0)
  52420     { /* SOC_REG_INT_OLP_CONFIGS_GENERAL_BCM88660_A0r */
  52421         soc_block_list[42],
  52422         soc_genreg,
  52423         1,
  52424         0,
  52425         0x108,
  52426         SOC_REG_FLAG_SIGNAL,
  52427         0,
  52428         2,
  52429         soc_OLP_CONFIGS_GENERAL_BCM88660_A0r_fields,
  52430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52431         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  52432         -1,
  52433         -1,
  52434     },
  52435 #endif /* chips */
  52436 
  52437 #if defined(BCM_88650_A0)
  52438     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATIONr */
  52439         soc_block_list[42],
  52440         soc_genreg,
  52441         2,
  52442         0,
  52443         0x10d,
  52444         SOC_REG_FLAG_ARRAY |
  52445                           SOC_REG_FLAG_REG_ARRAY |
  52446                           SOC_REG_FLAG_SIGNAL,
  52447         0,
  52448         5,
  52449         soc_OLP_DSP_ENGINE_CONFIGURATIONr_fields,
  52450         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52451         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52452         -1,
  52453         -1,
  52454     },
  52455 #endif /* chips */
  52456 
  52457 #if defined(BCM_88270_A0)
  52458     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88270_A0r */
  52459         soc_block_list[42],
  52460         soc_genreg,
  52461         2,
  52462         0,
  52463         0x113,
  52464         SOC_REG_FLAG_ARRAY |
  52465                           SOC_REG_FLAG_REG_ARRAY,
  52466         0,
  52467         5,
  52468         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88270_A0r_fields,
  52469         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52470         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52471         -1,
  52472         -1,
  52473     },
  52474 #endif /* chips */
  52475 
  52476 #if defined(BCM_88375_A0)
  52477     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88375_A0r */
  52478         soc_block_list[42],
  52479         soc_genreg,
  52480         2,
  52481         0,
  52482         0x113,
  52483         SOC_REG_FLAG_ARRAY |
  52484                           SOC_REG_FLAG_REG_ARRAY,
  52485         0,
  52486         5,
  52487         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88375_A0r_fields,
  52488         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52489         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52490         -1,
  52491         -1,
  52492     },
  52493 #endif /* chips */
  52494 
  52495 #if defined(BCM_88375_B0)
  52496     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88375_B0r */
  52497         soc_block_list[42],
  52498         soc_genreg,
  52499         2,
  52500         0,
  52501         0x113,
  52502         SOC_REG_FLAG_ARRAY |
  52503                           SOC_REG_FLAG_REG_ARRAY,
  52504         0,
  52505         5,
  52506         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88375_B0r_fields,
  52507         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52508         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52509         -1,
  52510         -1,
  52511     },
  52512 #endif /* chips */
  52513 
  52514 #if defined(BCM_88470_A0)
  52515     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88470_A0r */
  52516         soc_block_list[42],
  52517         soc_genreg,
  52518         2,
  52519         0,
  52520         0x113,
  52521         SOC_REG_FLAG_ARRAY |
  52522                           SOC_REG_FLAG_REG_ARRAY,
  52523         0,
  52524         5,
  52525         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88470_A0r_fields,
  52526         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52527         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52528         -1,
  52529         -1,
  52530     },
  52531 #endif /* chips */
  52532 
  52533 #if defined(BCM_88470_B0)
  52534     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88470_B0r */
  52535         soc_block_list[42],
  52536         soc_genreg,
  52537         2,
  52538         0,
  52539         0x113,
  52540         SOC_REG_FLAG_ARRAY |
  52541                           SOC_REG_FLAG_REG_ARRAY,
  52542         0,
  52543         5,
  52544         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88470_B0r_fields,
  52545         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52546         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52547         -1,
  52548         -1,
  52549     },
  52550 #endif /* chips */
  52551 
  52552 #if defined(BCM_88650_B0)
  52553     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88650_B0r */
  52554         soc_block_list[42],
  52555         soc_genreg,
  52556         2,
  52557         0,
  52558         0x10d,
  52559         SOC_REG_FLAG_ARRAY |
  52560                           SOC_REG_FLAG_REG_ARRAY |
  52561                           SOC_REG_FLAG_SIGNAL,
  52562         0,
  52563         5,
  52564         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88650_B0r_fields,
  52565         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52566         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52567         -1,
  52568         -1,
  52569     },
  52570 #endif /* chips */
  52571 
  52572 #if defined(BCM_88660_A0)
  52573     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88660_A0r */
  52574         soc_block_list[42],
  52575         soc_genreg,
  52576         2,
  52577         0,
  52578         0x10d,
  52579         SOC_REG_FLAG_ARRAY |
  52580                           SOC_REG_FLAG_REG_ARRAY |
  52581                           SOC_REG_FLAG_SIGNAL,
  52582         0,
  52583         5,
  52584         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88660_A0r_fields,
  52585         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52586         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52587         -1,
  52588         -1,
  52589     },
  52590 #endif /* chips */
  52591 
  52592 #if defined(BCM_88675_A0)
  52593     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88675_A0r */
  52594         soc_block_list[42],
  52595         soc_genreg,
  52596         2,
  52597         0,
  52598         0x113,
  52599         SOC_REG_FLAG_ARRAY |
  52600                           SOC_REG_FLAG_REG_ARRAY,
  52601         0,
  52602         5,
  52603         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88675_A0r_fields,
  52604         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52605         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52606         -1,
  52607         -1,
  52608     },
  52609 #endif /* chips */
  52610 
  52611 #if defined(BCM_88675_B0)
  52612     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88675_B0r */
  52613         soc_block_list[42],
  52614         soc_genreg,
  52615         2,
  52616         0,
  52617         0x113,
  52618         SOC_REG_FLAG_ARRAY |
  52619                           SOC_REG_FLAG_REG_ARRAY,
  52620         0,
  52621         5,
  52622         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88675_B0r_fields,
  52623         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52624         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52625         -1,
  52626         -1,
  52627     },
  52628 #endif /* chips */
  52629 
  52630 #if defined(BCM_88680_A0)
  52631     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88680_A0r */
  52632         soc_block_list[42],
  52633         soc_genreg,
  52634         2,
  52635         0,
  52636         0x113,
  52637         SOC_REG_FLAG_ARRAY |
  52638                           SOC_REG_FLAG_REG_ARRAY,
  52639         0,
  52640         5,
  52641         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88680_A0r_fields,
  52642         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52643         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52644         -1,
  52645         -1,
  52646     },
  52647 #endif /* chips */
  52648 
  52649 #if defined(BCM_88690_A0)
  52650     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88690_A0r */
  52651         soc_block_list[42],
  52652         soc_genreg,
  52653         2,
  52654         0,
  52655         0x135,
  52656         SOC_REG_FLAG_ARRAY |
  52657                           SOC_REG_FLAG_REG_ARRAY,
  52658         0,
  52659         5,
  52660         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88690_A0r_fields,
  52661         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52662         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52663         -1,
  52664         -1,
  52665     },
  52666 #endif /* chips */
  52667 
  52668 #if defined(BCM_88690_B0)
  52669     { /* SOC_REG_INT_OLP_DSP_ENGINE_CONFIGURATION_BCM88690_B0r */
  52670         soc_block_list[42],
  52671         soc_genreg,
  52672         2,
  52673         0,
  52674         0x135,
  52675         SOC_REG_FLAG_ARRAY |
  52676                           SOC_REG_FLAG_REG_ARRAY,
  52677         0,
  52678         5,
  52679         soc_OLP_DSP_ENGINE_CONFIGURATION_BCM88690_B0r_fields,
  52680         SOC_RESET_VAL_DEC(0x00003002, 0x00000000)
  52681         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  52682         -1,
  52683         -1,
  52684     },
  52685 #endif /* chips */
  52686 
  52687 #if defined(BCM_88650_A0)
  52688     { /* SOC_REG_INT_OLP_DSP_HEADERr */
  52689         soc_block_list[42],
  52690         soc_genreg,
  52691         2,
  52692         0,
  52693         0x10f,
  52694         SOC_REG_FLAG_ABOVE_64_BITS |
  52695                           SOC_REG_FLAG_ARRAY |
  52696                           SOC_REG_FLAG_REG_ARRAY |
  52697                           SOC_REG_FLAG_SIGNAL,
  52698         0,
  52699         1,
  52700         soc_OLP_DSP_HEADERr_fields,
  52701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52703         -1,
  52704         -1,
  52705     },
  52706 #endif /* chips */
  52707 
  52708 #if defined(BCM_88270_A0)
  52709     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88270_A0r */
  52710         soc_block_list[42],
  52711         soc_genreg,
  52712         2,
  52713         0,
  52714         0x115,
  52715         SOC_REG_FLAG_ABOVE_64_BITS |
  52716                           SOC_REG_FLAG_ARRAY |
  52717                           SOC_REG_FLAG_REG_ARRAY,
  52718         0,
  52719         1,
  52720         soc_OLP_DSP_HEADER_BCM88270_A0r_fields,
  52721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52722         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52723         -1,
  52724         -1,
  52725     },
  52726 #endif /* chips */
  52727 
  52728 #if defined(BCM_88375_A0)
  52729     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88375_A0r */
  52730         soc_block_list[42],
  52731         soc_genreg,
  52732         2,
  52733         0,
  52734         0x115,
  52735         SOC_REG_FLAG_ABOVE_64_BITS |
  52736                           SOC_REG_FLAG_ARRAY |
  52737                           SOC_REG_FLAG_REG_ARRAY,
  52738         0,
  52739         1,
  52740         soc_OLP_DSP_HEADER_BCM88375_A0r_fields,
  52741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52742         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52743         -1,
  52744         -1,
  52745     },
  52746 #endif /* chips */
  52747 
  52748 #if defined(BCM_88375_B0)
  52749     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88375_B0r */
  52750         soc_block_list[42],
  52751         soc_genreg,
  52752         2,
  52753         0,
  52754         0x115,
  52755         SOC_REG_FLAG_ABOVE_64_BITS |
  52756                           SOC_REG_FLAG_ARRAY |
  52757                           SOC_REG_FLAG_REG_ARRAY,
  52758         0,
  52759         1,
  52760         soc_OLP_DSP_HEADER_BCM88375_B0r_fields,
  52761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52763         -1,
  52764         -1,
  52765     },
  52766 #endif /* chips */
  52767 
  52768 #if defined(BCM_88470_A0)
  52769     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88470_A0r */
  52770         soc_block_list[42],
  52771         soc_genreg,
  52772         2,
  52773         0,
  52774         0x115,
  52775         SOC_REG_FLAG_ABOVE_64_BITS |
  52776                           SOC_REG_FLAG_ARRAY |
  52777                           SOC_REG_FLAG_REG_ARRAY,
  52778         0,
  52779         1,
  52780         soc_OLP_DSP_HEADER_BCM88470_A0r_fields,
  52781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52782         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52783         -1,
  52784         -1,
  52785     },
  52786 #endif /* chips */
  52787 
  52788 #if defined(BCM_88470_B0)
  52789     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88470_B0r */
  52790         soc_block_list[42],
  52791         soc_genreg,
  52792         2,
  52793         0,
  52794         0x115,
  52795         SOC_REG_FLAG_ABOVE_64_BITS |
  52796                           SOC_REG_FLAG_ARRAY |
  52797                           SOC_REG_FLAG_REG_ARRAY,
  52798         0,
  52799         1,
  52800         soc_OLP_DSP_HEADER_BCM88470_B0r_fields,
  52801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52802         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52803         -1,
  52804         -1,
  52805     },
  52806 #endif /* chips */
  52807 
  52808 #if defined(BCM_88650_B0)
  52809     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88650_B0r */
  52810         soc_block_list[42],
  52811         soc_genreg,
  52812         2,
  52813         0,
  52814         0x10f,
  52815         SOC_REG_FLAG_ABOVE_64_BITS |
  52816                           SOC_REG_FLAG_ARRAY |
  52817                           SOC_REG_FLAG_REG_ARRAY |
  52818                           SOC_REG_FLAG_SIGNAL,
  52819         0,
  52820         1,
  52821         soc_OLP_DSP_HEADER_BCM88650_B0r_fields,
  52822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52823         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52824         -1,
  52825         -1,
  52826     },
  52827 #endif /* chips */
  52828 
  52829 #if defined(BCM_88660_A0)
  52830     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88660_A0r */
  52831         soc_block_list[42],
  52832         soc_genreg,
  52833         2,
  52834         0,
  52835         0x10f,
  52836         SOC_REG_FLAG_ABOVE_64_BITS |
  52837                           SOC_REG_FLAG_ARRAY |
  52838                           SOC_REG_FLAG_REG_ARRAY |
  52839                           SOC_REG_FLAG_SIGNAL,
  52840         0,
  52841         1,
  52842         soc_OLP_DSP_HEADER_BCM88660_A0r_fields,
  52843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52844         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52845         -1,
  52846         -1,
  52847     },
  52848 #endif /* chips */
  52849 
  52850 #if defined(BCM_88675_A0)
  52851     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88675_A0r */
  52852         soc_block_list[42],
  52853         soc_genreg,
  52854         2,
  52855         0,
  52856         0x115,
  52857         SOC_REG_FLAG_ABOVE_64_BITS |
  52858                           SOC_REG_FLAG_ARRAY |
  52859                           SOC_REG_FLAG_REG_ARRAY,
  52860         0,
  52861         1,
  52862         soc_OLP_DSP_HEADER_BCM88675_A0r_fields,
  52863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52864         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52865         -1,
  52866         -1,
  52867     },
  52868 #endif /* chips */
  52869 
  52870 #if defined(BCM_88675_B0)
  52871     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88675_B0r */
  52872         soc_block_list[42],
  52873         soc_genreg,
  52874         2,
  52875         0,
  52876         0x115,
  52877         SOC_REG_FLAG_ABOVE_64_BITS |
  52878                           SOC_REG_FLAG_ARRAY |
  52879                           SOC_REG_FLAG_REG_ARRAY,
  52880         0,
  52881         1,
  52882         soc_OLP_DSP_HEADER_BCM88675_B0r_fields,
  52883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52884         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52885         -1,
  52886         -1,
  52887     },
  52888 #endif /* chips */
  52889 
  52890 #if defined(BCM_88680_A0)
  52891     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88680_A0r */
  52892         soc_block_list[42],
  52893         soc_genreg,
  52894         2,
  52895         0,
  52896         0x115,
  52897         SOC_REG_FLAG_ABOVE_64_BITS |
  52898                           SOC_REG_FLAG_ARRAY |
  52899                           SOC_REG_FLAG_REG_ARRAY,
  52900         0,
  52901         1,
  52902         soc_OLP_DSP_HEADER_BCM88680_A0r_fields,
  52903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52904         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52905         -1,
  52906         -1,
  52907     },
  52908 #endif /* chips */
  52909 
  52910 #if defined(BCM_88690_A0)
  52911     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88690_A0r */
  52912         soc_block_list[42],
  52913         soc_genreg,
  52914         2,
  52915         0,
  52916         0x137,
  52917         SOC_REG_FLAG_ABOVE_64_BITS |
  52918                           SOC_REG_FLAG_ARRAY |
  52919                           SOC_REG_FLAG_REG_ARRAY,
  52920         0,
  52921         1,
  52922         soc_OLP_DSP_HEADER_BCM88690_A0r_fields,
  52923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52924         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52925         -1,
  52926         -1,
  52927     },
  52928 #endif /* chips */
  52929 
  52930 #if defined(BCM_88690_B0)
  52931     { /* SOC_REG_INT_OLP_DSP_HEADER_BCM88690_B0r */
  52932         soc_block_list[42],
  52933         soc_genreg,
  52934         2,
  52935         0,
  52936         0x137,
  52937         SOC_REG_FLAG_ABOVE_64_BITS |
  52938                           SOC_REG_FLAG_ARRAY |
  52939                           SOC_REG_FLAG_REG_ARRAY,
  52940         0,
  52941         1,
  52942         soc_OLP_DSP_HEADER_BCM88690_B0r_fields,
  52943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52944         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52945         -1,
  52946         -1,
  52947     },
  52948 #endif /* chips */
  52949 
  52950 #if defined(BCM_88650_A0)
  52951     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNTr */
  52952         soc_block_list[42],
  52953         soc_genreg,
  52954         1,
  52955         0,
  52956         0x94,
  52957         SOC_REG_FLAG_64_BITS |
  52958                           SOC_REG_FLAG_RO,
  52959         0,
  52960         4,
  52961         soc_OLP_ECC_1B_ERR_CNTr_fields,
  52962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52963         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  52964         -1,
  52965         -1,
  52966     },
  52967 #endif /* chips */
  52968 
  52969 #if defined(BCM_88270_A0)
  52970     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88270_A0r */
  52971         soc_block_list[42],
  52972         soc_genreg,
  52973         1,
  52974         0,
  52975         0x94,
  52976         SOC_REG_FLAG_64_BITS |
  52977                           SOC_REG_FLAG_RO,
  52978         0,
  52979         4,
  52980         soc_OLP_ECC_1B_ERR_CNT_BCM88270_A0r_fields,
  52981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52982         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  52983         -1,
  52984         -1,
  52985     },
  52986 #endif /* chips */
  52987 
  52988 #if defined(BCM_88375_A0)
  52989     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88375_A0r */
  52990         soc_block_list[42],
  52991         soc_genreg,
  52992         1,
  52993         0,
  52994         0x94,
  52995         SOC_REG_FLAG_64_BITS |
  52996                           SOC_REG_FLAG_RO,
  52997         0,
  52998         4,
  52999         soc_OLP_ECC_1B_ERR_CNT_BCM88375_A0r_fields,
  53000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53001         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53002         -1,
  53003         -1,
  53004     },
  53005 #endif /* chips */
  53006 
  53007 #if defined(BCM_88375_B0)
  53008     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88375_B0r */
  53009         soc_block_list[42],
  53010         soc_genreg,
  53011         1,
  53012         0,
  53013         0x94,
  53014         SOC_REG_FLAG_64_BITS |
  53015                           SOC_REG_FLAG_RO,
  53016         0,
  53017         4,
  53018         soc_OLP_ECC_1B_ERR_CNT_BCM88375_B0r_fields,
  53019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53020         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53021         -1,
  53022         -1,
  53023     },
  53024 #endif /* chips */
  53025 
  53026 #if defined(BCM_88470_A0)
  53027     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88470_A0r */
  53028         soc_block_list[42],
  53029         soc_genreg,
  53030         1,
  53031         0,
  53032         0x94,
  53033         SOC_REG_FLAG_64_BITS |
  53034                           SOC_REG_FLAG_RO,
  53035         0,
  53036         4,
  53037         soc_OLP_ECC_1B_ERR_CNT_BCM88470_A0r_fields,
  53038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53039         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53040         -1,
  53041         -1,
  53042     },
  53043 #endif /* chips */
  53044 
  53045 #if defined(BCM_88470_B0)
  53046     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88470_B0r */
  53047         soc_block_list[42],
  53048         soc_genreg,
  53049         1,
  53050         0,
  53051         0x94,
  53052         SOC_REG_FLAG_64_BITS |
  53053                           SOC_REG_FLAG_RO,
  53054         0,
  53055         4,
  53056         soc_OLP_ECC_1B_ERR_CNT_BCM88470_B0r_fields,
  53057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53058         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53059         -1,
  53060         -1,
  53061     },
  53062 #endif /* chips */
  53063 
  53064 #if defined(BCM_88650_B0)
  53065     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88650_B0r */
  53066         soc_block_list[42],
  53067         soc_genreg,
  53068         1,
  53069         0,
  53070         0x94,
  53071         SOC_REG_FLAG_64_BITS |
  53072                           SOC_REG_FLAG_RO,
  53073         0,
  53074         4,
  53075         soc_OLP_ECC_1B_ERR_CNT_BCM88650_B0r_fields,
  53076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53077         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53078         -1,
  53079         -1,
  53080     },
  53081 #endif /* chips */
  53082 
  53083 #if defined(BCM_88660_A0)
  53084     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88660_A0r */
  53085         soc_block_list[42],
  53086         soc_genreg,
  53087         1,
  53088         0,
  53089         0x94,
  53090         SOC_REG_FLAG_64_BITS |
  53091                           SOC_REG_FLAG_RO,
  53092         0,
  53093         4,
  53094         soc_OLP_ECC_1B_ERR_CNT_BCM88660_A0r_fields,
  53095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53096         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53097         -1,
  53098         -1,
  53099     },
  53100 #endif /* chips */
  53101 
  53102 #if defined(BCM_88675_A0)
  53103     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88675_A0r */
  53104         soc_block_list[42],
  53105         soc_genreg,
  53106         1,
  53107         0,
  53108         0x94,
  53109         SOC_REG_FLAG_64_BITS |
  53110                           SOC_REG_FLAG_RO,
  53111         0,
  53112         4,
  53113         soc_OLP_ECC_1B_ERR_CNT_BCM88675_A0r_fields,
  53114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53115         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53116         -1,
  53117         -1,
  53118     },
  53119 #endif /* chips */
  53120 
  53121 #if defined(BCM_88675_B0)
  53122     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88675_B0r */
  53123         soc_block_list[42],
  53124         soc_genreg,
  53125         1,
  53126         0,
  53127         0x94,
  53128         SOC_REG_FLAG_64_BITS |
  53129                           SOC_REG_FLAG_RO,
  53130         0,
  53131         4,
  53132         soc_OLP_ECC_1B_ERR_CNT_BCM88675_B0r_fields,
  53133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53134         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53135         -1,
  53136         -1,
  53137     },
  53138 #endif /* chips */
  53139 
  53140 #if defined(BCM_88680_A0)
  53141     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88680_A0r */
  53142         soc_block_list[42],
  53143         soc_genreg,
  53144         1,
  53145         0,
  53146         0x94,
  53147         SOC_REG_FLAG_64_BITS |
  53148                           SOC_REG_FLAG_RO,
  53149         0,
  53150         4,
  53151         soc_OLP_ECC_1B_ERR_CNT_BCM88680_A0r_fields,
  53152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53153         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53154         -1,
  53155         -1,
  53156     },
  53157 #endif /* chips */
  53158 
  53159 #if defined(BCM_88690_A0)
  53160     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88690_A0r */
  53161         soc_block_list[42],
  53162         soc_genreg,
  53163         1,
  53164         0,
  53165         0x94,
  53166         SOC_REG_FLAG_64_BITS |
  53167                           SOC_REG_FLAG_RO,
  53168         SOC_REG_FLAG_COUNTER_FEILDS |
  53169                           SOC_REG_FLAG_INIT_ON_READ,
  53170         4,
  53171         soc_OLP_ECC_1B_ERR_CNT_BCM88690_A0r_fields,
  53172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53173         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53174         -1,
  53175         -1,
  53176     },
  53177 #endif /* chips */
  53178 
  53179 #if defined(BCM_88690_B0)
  53180     { /* SOC_REG_INT_OLP_ECC_1B_ERR_CNT_BCM88690_B0r */
  53181         soc_block_list[42],
  53182         soc_genreg,
  53183         1,
  53184         0,
  53185         0x94,
  53186         SOC_REG_FLAG_64_BITS |
  53187                           SOC_REG_FLAG_RO,
  53188         SOC_REG_FLAG_COUNTER_FEILDS |
  53189                           SOC_REG_FLAG_INIT_ON_READ,
  53190         4,
  53191         soc_OLP_ECC_1B_ERR_CNT_BCM88690_B0r_fields,
  53192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53193         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53194         -1,
  53195         -1,
  53196     },
  53197 #endif /* chips */
  53198 
  53199 #if defined(BCM_88650_A0)
  53200     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNTr */
  53201         soc_block_list[42],
  53202         soc_genreg,
  53203         1,
  53204         0,
  53205         0x96,
  53206         SOC_REG_FLAG_64_BITS |
  53207                           SOC_REG_FLAG_RO,
  53208         0,
  53209         4,
  53210         soc_OLP_ECC_2B_ERR_CNTr_fields,
  53211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53212         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53213         -1,
  53214         -1,
  53215     },
  53216 #endif /* chips */
  53217 
  53218 #if defined(BCM_88270_A0)
  53219     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88270_A0r */
  53220         soc_block_list[42],
  53221         soc_genreg,
  53222         1,
  53223         0,
  53224         0x96,
  53225         SOC_REG_FLAG_64_BITS |
  53226                           SOC_REG_FLAG_RO,
  53227         0,
  53228         4,
  53229         soc_OLP_ECC_2B_ERR_CNT_BCM88270_A0r_fields,
  53230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53231         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53232         -1,
  53233         -1,
  53234     },
  53235 #endif /* chips */
  53236 
  53237 #if defined(BCM_88375_A0)
  53238     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88375_A0r */
  53239         soc_block_list[42],
  53240         soc_genreg,
  53241         1,
  53242         0,
  53243         0x96,
  53244         SOC_REG_FLAG_64_BITS |
  53245                           SOC_REG_FLAG_RO,
  53246         0,
  53247         4,
  53248         soc_OLP_ECC_2B_ERR_CNT_BCM88375_A0r_fields,
  53249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53250         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53251         -1,
  53252         -1,
  53253     },
  53254 #endif /* chips */
  53255 
  53256 #if defined(BCM_88375_B0)
  53257     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88375_B0r */
  53258         soc_block_list[42],
  53259         soc_genreg,
  53260         1,
  53261         0,
  53262         0x96,
  53263         SOC_REG_FLAG_64_BITS |
  53264                           SOC_REG_FLAG_RO,
  53265         0,
  53266         4,
  53267         soc_OLP_ECC_2B_ERR_CNT_BCM88375_B0r_fields,
  53268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53269         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53270         -1,
  53271         -1,
  53272     },
  53273 #endif /* chips */
  53274 
  53275 #if defined(BCM_88470_A0)
  53276     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88470_A0r */
  53277         soc_block_list[42],
  53278         soc_genreg,
  53279         1,
  53280         0,
  53281         0x96,
  53282         SOC_REG_FLAG_64_BITS |
  53283                           SOC_REG_FLAG_RO,
  53284         0,
  53285         4,
  53286         soc_OLP_ECC_2B_ERR_CNT_BCM88470_A0r_fields,
  53287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53288         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53289         -1,
  53290         -1,
  53291     },
  53292 #endif /* chips */
  53293 
  53294 #if defined(BCM_88470_B0)
  53295     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88470_B0r */
  53296         soc_block_list[42],
  53297         soc_genreg,
  53298         1,
  53299         0,
  53300         0x96,
  53301         SOC_REG_FLAG_64_BITS |
  53302                           SOC_REG_FLAG_RO,
  53303         0,
  53304         4,
  53305         soc_OLP_ECC_2B_ERR_CNT_BCM88470_B0r_fields,
  53306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53307         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53308         -1,
  53309         -1,
  53310     },
  53311 #endif /* chips */
  53312 
  53313 #if defined(BCM_88650_B0)
  53314     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88650_B0r */
  53315         soc_block_list[42],
  53316         soc_genreg,
  53317         1,
  53318         0,
  53319         0x96,
  53320         SOC_REG_FLAG_64_BITS |
  53321                           SOC_REG_FLAG_RO,
  53322         0,
  53323         4,
  53324         soc_OLP_ECC_2B_ERR_CNT_BCM88650_B0r_fields,
  53325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53326         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53327         -1,
  53328         -1,
  53329     },
  53330 #endif /* chips */
  53331 
  53332 #if defined(BCM_88660_A0)
  53333     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88660_A0r */
  53334         soc_block_list[42],
  53335         soc_genreg,
  53336         1,
  53337         0,
  53338         0x96,
  53339         SOC_REG_FLAG_64_BITS |
  53340                           SOC_REG_FLAG_RO,
  53341         0,
  53342         4,
  53343         soc_OLP_ECC_2B_ERR_CNT_BCM88660_A0r_fields,
  53344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53345         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53346         -1,
  53347         -1,
  53348     },
  53349 #endif /* chips */
  53350 
  53351 #if defined(BCM_88675_A0)
  53352     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88675_A0r */
  53353         soc_block_list[42],
  53354         soc_genreg,
  53355         1,
  53356         0,
  53357         0x96,
  53358         SOC_REG_FLAG_64_BITS |
  53359                           SOC_REG_FLAG_RO,
  53360         0,
  53361         4,
  53362         soc_OLP_ECC_2B_ERR_CNT_BCM88675_A0r_fields,
  53363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53364         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53365         -1,
  53366         -1,
  53367     },
  53368 #endif /* chips */
  53369 
  53370 #if defined(BCM_88675_B0)
  53371     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88675_B0r */
  53372         soc_block_list[42],
  53373         soc_genreg,
  53374         1,
  53375         0,
  53376         0x96,
  53377         SOC_REG_FLAG_64_BITS |
  53378                           SOC_REG_FLAG_RO,
  53379         0,
  53380         4,
  53381         soc_OLP_ECC_2B_ERR_CNT_BCM88675_B0r_fields,
  53382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53383         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53384         -1,
  53385         -1,
  53386     },
  53387 #endif /* chips */
  53388 
  53389 #if defined(BCM_88680_A0)
  53390     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88680_A0r */
  53391         soc_block_list[42],
  53392         soc_genreg,
  53393         1,
  53394         0,
  53395         0x96,
  53396         SOC_REG_FLAG_64_BITS |
  53397                           SOC_REG_FLAG_RO,
  53398         0,
  53399         4,
  53400         soc_OLP_ECC_2B_ERR_CNT_BCM88680_A0r_fields,
  53401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53402         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53403         -1,
  53404         -1,
  53405     },
  53406 #endif /* chips */
  53407 
  53408 #if defined(BCM_88690_A0)
  53409     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88690_A0r */
  53410         soc_block_list[42],
  53411         soc_genreg,
  53412         1,
  53413         0,
  53414         0x96,
  53415         SOC_REG_FLAG_64_BITS |
  53416                           SOC_REG_FLAG_RO,
  53417         SOC_REG_FLAG_COUNTER_FEILDS |
  53418                           SOC_REG_FLAG_INIT_ON_READ,
  53419         4,
  53420         soc_OLP_ECC_2B_ERR_CNT_BCM88690_A0r_fields,
  53421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53422         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53423         -1,
  53424         -1,
  53425     },
  53426 #endif /* chips */
  53427 
  53428 #if defined(BCM_88690_B0)
  53429     { /* SOC_REG_INT_OLP_ECC_2B_ERR_CNT_BCM88690_B0r */
  53430         soc_block_list[42],
  53431         soc_genreg,
  53432         1,
  53433         0,
  53434         0x96,
  53435         SOC_REG_FLAG_64_BITS |
  53436                           SOC_REG_FLAG_RO,
  53437         SOC_REG_FLAG_COUNTER_FEILDS |
  53438                           SOC_REG_FLAG_INIT_ON_READ,
  53439         4,
  53440         soc_OLP_ECC_2B_ERR_CNT_BCM88690_B0r_fields,
  53441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53442         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  53443         -1,
  53444         -1,
  53445     },
  53446 #endif /* chips */
  53447 
  53448 #if defined(BCM_88675_A0)
  53449     { /* SOC_REG_INT_OLP_ECC_ERR_1B_INITIATEr */
  53450         soc_block_list[42],
  53451         soc_genreg,
  53452         1,
  53453         0,
  53454         0xa4,
  53455         0,
  53456         0,
  53457         4,
  53458         soc_OLP_ECC_ERR_1B_INITIATEr_fields,
  53459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53460         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53461         -1,
  53462         -1,
  53463     },
  53464 #endif /* chips */
  53465 
  53466 #if defined(BCM_88270_A0)
  53467     { /* SOC_REG_INT_OLP_ECC_ERR_1B_INITIATE_BCM88270_A0r */
  53468         soc_block_list[42],
  53469         soc_genreg,
  53470         1,
  53471         0,
  53472         0xa4,
  53473         0,
  53474         0,
  53475         4,
  53476         soc_OLP_ECC_ERR_1B_INITIATE_BCM88270_A0r_fields,
  53477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53478         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53479         -1,
  53480         -1,
  53481     },
  53482 #endif /* chips */
  53483 
  53484 #if defined(BCM_88375_A0)
  53485     { /* SOC_REG_INT_OLP_ECC_ERR_1B_INITIATE_BCM88375_A0r */
  53486         soc_block_list[42],
  53487         soc_genreg,
  53488         1,
  53489         0,
  53490         0xa4,
  53491         0,
  53492         0,
  53493         4,
  53494         soc_OLP_ECC_ERR_1B_INITIATE_BCM88375_A0r_fields,
  53495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53496         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53497         -1,
  53498         -1,
  53499     },
  53500 #endif /* chips */
  53501 
  53502 #if defined(BCM_88375_B0)
  53503     { /* SOC_REG_INT_OLP_ECC_ERR_1B_INITIATE_BCM88375_B0r */
  53504         soc_block_list[42],
  53505         soc_genreg,
  53506         1,
  53507         0,
  53508         0xa4,
  53509         0,
  53510         0,
  53511         4,
  53512         soc_OLP_ECC_ERR_1B_INITIATE_BCM88375_B0r_fields,
  53513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53514         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53515         -1,
  53516         -1,
  53517     },
  53518 #endif /* chips */
  53519 
  53520 #if defined(BCM_88470_A0)
  53521     { /* SOC_REG_INT_OLP_ECC_ERR_1B_INITIATE_BCM88470_A0r */
  53522         soc_block_list[42],
  53523         soc_genreg,
  53524         1,
  53525         0,
  53526         0xa4,
  53527         0,
  53528         0,
  53529         4,
  53530         soc_OLP_ECC_ERR_1B_INITIATE_BCM88470_A0r_fields,
  53531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53532         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53533         -1,
  53534         -1,
  53535     },
  53536 #endif /* chips */
  53537 
  53538 #if defined(BCM_88470_B0)
  53539     { /* SOC_REG_INT_OLP_ECC_ERR_1B_INITIATE_BCM88470_B0r */
  53540         soc_block_list[42],
  53541         soc_genreg,
  53542         1,
  53543         0,
  53544         0xa4,
  53545         0,
  53546         0,
  53547         4,
  53548         soc_OLP_ECC_ERR_1B_INITIATE_BCM88470_B0r_fields,
  53549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53550         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53551         -1,
  53552         -1,
  53553     },
  53554 #endif /* chips */
  53555 
  53556 #if defined(BCM_88675_B0)
  53557     { /* SOC_REG_INT_OLP_ECC_ERR_1B_INITIATE_BCM88675_B0r */
  53558         soc_block_list[42],
  53559         soc_genreg,
  53560         1,
  53561         0,
  53562         0xa4,
  53563         0,
  53564         0,
  53565         4,
  53566         soc_OLP_ECC_ERR_1B_INITIATE_BCM88675_B0r_fields,
  53567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53568         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53569         -1,
  53570         -1,
  53571     },
  53572 #endif /* chips */
  53573 
  53574 #if defined(BCM_88680_A0)
  53575     { /* SOC_REG_INT_OLP_ECC_ERR_1B_INITIATE_BCM88680_A0r */
  53576         soc_block_list[42],
  53577         soc_genreg,
  53578         1,
  53579         0,
  53580         0xa4,
  53581         0,
  53582         0,
  53583         4,
  53584         soc_OLP_ECC_ERR_1B_INITIATE_BCM88680_A0r_fields,
  53585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53586         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53587         -1,
  53588         -1,
  53589     },
  53590 #endif /* chips */
  53591 
  53592 #if defined(BCM_88675_A0)
  53593     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASKr */
  53594         soc_block_list[42],
  53595         soc_genreg,
  53596         1,
  53597         0,
  53598         0x9a,
  53599         0,
  53600         0,
  53601         4,
  53602         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  53603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53604         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53605         -1,
  53606         -1,
  53607     },
  53608 #endif /* chips */
  53609 
  53610 #if defined(BCM_88270_A0)
  53611     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88270_A0r */
  53612         soc_block_list[42],
  53613         soc_genreg,
  53614         1,
  53615         0,
  53616         0x9a,
  53617         0,
  53618         0,
  53619         4,
  53620         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88270_A0r_fields,
  53621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53622         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53623         -1,
  53624         -1,
  53625     },
  53626 #endif /* chips */
  53627 
  53628 #if defined(BCM_88375_A0)
  53629     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r */
  53630         soc_block_list[42],
  53631         soc_genreg,
  53632         1,
  53633         0,
  53634         0x9a,
  53635         0,
  53636         0,
  53637         4,
  53638         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
  53639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53640         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53641         -1,
  53642         -1,
  53643     },
  53644 #endif /* chips */
  53645 
  53646 #if defined(BCM_88375_B0)
  53647     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r */
  53648         soc_block_list[42],
  53649         soc_genreg,
  53650         1,
  53651         0,
  53652         0x9a,
  53653         0,
  53654         0,
  53655         4,
  53656         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
  53657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53658         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53659         -1,
  53660         -1,
  53661     },
  53662 #endif /* chips */
  53663 
  53664 #if defined(BCM_88470_A0)
  53665     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_A0r */
  53666         soc_block_list[42],
  53667         soc_genreg,
  53668         1,
  53669         0,
  53670         0x9a,
  53671         0,
  53672         0,
  53673         4,
  53674         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_A0r_fields,
  53675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53676         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53677         -1,
  53678         -1,
  53679     },
  53680 #endif /* chips */
  53681 
  53682 #if defined(BCM_88470_B0)
  53683     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_B0r */
  53684         soc_block_list[42],
  53685         soc_genreg,
  53686         1,
  53687         0,
  53688         0x9a,
  53689         0,
  53690         0,
  53691         4,
  53692         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_B0r_fields,
  53693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53694         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53695         -1,
  53696         -1,
  53697     },
  53698 #endif /* chips */
  53699 
  53700 #if defined(BCM_88675_B0)
  53701     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r */
  53702         soc_block_list[42],
  53703         soc_genreg,
  53704         1,
  53705         0,
  53706         0x9a,
  53707         0,
  53708         0,
  53709         4,
  53710         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
  53711         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53712         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53713         -1,
  53714         -1,
  53715     },
  53716 #endif /* chips */
  53717 
  53718 #if defined(BCM_88680_A0)
  53719     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r */
  53720         soc_block_list[42],
  53721         soc_genreg,
  53722         1,
  53723         0,
  53724         0x9a,
  53725         0,
  53726         0,
  53727         4,
  53728         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
  53729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53730         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53731         -1,
  53732         -1,
  53733     },
  53734 #endif /* chips */
  53735 
  53736 #if defined(BCM_88690_A0)
  53737     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r */
  53738         soc_block_list[42],
  53739         soc_genreg,
  53740         1,
  53741         0,
  53742         0x9a,
  53743         0,
  53744         0,
  53745         6,
  53746         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
  53747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53748         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  53749         -1,
  53750         -1,
  53751     },
  53752 #endif /* chips */
  53753 
  53754 #if defined(BCM_88690_B0)
  53755     { /* SOC_REG_INT_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r */
  53756         soc_block_list[42],
  53757         soc_genreg,
  53758         1,
  53759         0,
  53760         0x9a,
  53761         0,
  53762         0,
  53763         6,
  53764         soc_OLP_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
  53765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53766         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  53767         -1,
  53768         -1,
  53769     },
  53770 #endif /* chips */
  53771 
  53772 #if defined(BCM_88675_A0)
  53773     { /* SOC_REG_INT_OLP_ECC_ERR_2B_INITIATEr */
  53774         soc_block_list[42],
  53775         soc_genreg,
  53776         1,
  53777         0,
  53778         0xa6,
  53779         0,
  53780         0,
  53781         4,
  53782         soc_OLP_ECC_ERR_2B_INITIATEr_fields,
  53783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53784         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53785         -1,
  53786         -1,
  53787     },
  53788 #endif /* chips */
  53789 
  53790 #if defined(BCM_88270_A0)
  53791     { /* SOC_REG_INT_OLP_ECC_ERR_2B_INITIATE_BCM88270_A0r */
  53792         soc_block_list[42],
  53793         soc_genreg,
  53794         1,
  53795         0,
  53796         0xa6,
  53797         0,
  53798         0,
  53799         4,
  53800         soc_OLP_ECC_ERR_2B_INITIATE_BCM88270_A0r_fields,
  53801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53802         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53803         -1,
  53804         -1,
  53805     },
  53806 #endif /* chips */
  53807 
  53808 #if defined(BCM_88375_A0)
  53809     { /* SOC_REG_INT_OLP_ECC_ERR_2B_INITIATE_BCM88375_A0r */
  53810         soc_block_list[42],
  53811         soc_genreg,
  53812         1,
  53813         0,
  53814         0xa6,
  53815         0,
  53816         0,
  53817         4,
  53818         soc_OLP_ECC_ERR_2B_INITIATE_BCM88375_A0r_fields,
  53819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53820         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53821         -1,
  53822         -1,
  53823     },
  53824 #endif /* chips */
  53825 
  53826 #if defined(BCM_88375_B0)
  53827     { /* SOC_REG_INT_OLP_ECC_ERR_2B_INITIATE_BCM88375_B0r */
  53828         soc_block_list[42],
  53829         soc_genreg,
  53830         1,
  53831         0,
  53832         0xa6,
  53833         0,
  53834         0,
  53835         4,
  53836         soc_OLP_ECC_ERR_2B_INITIATE_BCM88375_B0r_fields,
  53837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53838         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53839         -1,
  53840         -1,
  53841     },
  53842 #endif /* chips */
  53843 
  53844 #if defined(BCM_88470_A0)
  53845     { /* SOC_REG_INT_OLP_ECC_ERR_2B_INITIATE_BCM88470_A0r */
  53846         soc_block_list[42],
  53847         soc_genreg,
  53848         1,
  53849         0,
  53850         0xa6,
  53851         0,
  53852         0,
  53853         4,
  53854         soc_OLP_ECC_ERR_2B_INITIATE_BCM88470_A0r_fields,
  53855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53856         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53857         -1,
  53858         -1,
  53859     },
  53860 #endif /* chips */
  53861 
  53862 #if defined(BCM_88470_B0)
  53863     { /* SOC_REG_INT_OLP_ECC_ERR_2B_INITIATE_BCM88470_B0r */
  53864         soc_block_list[42],
  53865         soc_genreg,
  53866         1,
  53867         0,
  53868         0xa6,
  53869         0,
  53870         0,
  53871         4,
  53872         soc_OLP_ECC_ERR_2B_INITIATE_BCM88470_B0r_fields,
  53873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53874         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53875         -1,
  53876         -1,
  53877     },
  53878 #endif /* chips */
  53879 
  53880 #if defined(BCM_88675_B0)
  53881     { /* SOC_REG_INT_OLP_ECC_ERR_2B_INITIATE_BCM88675_B0r */
  53882         soc_block_list[42],
  53883         soc_genreg,
  53884         1,
  53885         0,
  53886         0xa6,
  53887         0,
  53888         0,
  53889         4,
  53890         soc_OLP_ECC_ERR_2B_INITIATE_BCM88675_B0r_fields,
  53891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53892         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53893         -1,
  53894         -1,
  53895     },
  53896 #endif /* chips */
  53897 
  53898 #if defined(BCM_88680_A0)
  53899     { /* SOC_REG_INT_OLP_ECC_ERR_2B_INITIATE_BCM88680_A0r */
  53900         soc_block_list[42],
  53901         soc_genreg,
  53902         1,
  53903         0,
  53904         0xa6,
  53905         0,
  53906         0,
  53907         4,
  53908         soc_OLP_ECC_ERR_2B_INITIATE_BCM88680_A0r_fields,
  53909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53910         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53911         -1,
  53912         -1,
  53913     },
  53914 #endif /* chips */
  53915 
  53916 #if defined(BCM_88675_A0)
  53917     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASKr */
  53918         soc_block_list[42],
  53919         soc_genreg,
  53920         1,
  53921         0,
  53922         0x9c,
  53923         0,
  53924         0,
  53925         4,
  53926         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  53927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53928         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53929         -1,
  53930         -1,
  53931     },
  53932 #endif /* chips */
  53933 
  53934 #if defined(BCM_88270_A0)
  53935     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88270_A0r */
  53936         soc_block_list[42],
  53937         soc_genreg,
  53938         1,
  53939         0,
  53940         0x9c,
  53941         0,
  53942         0,
  53943         4,
  53944         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88270_A0r_fields,
  53945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53946         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53947         -1,
  53948         -1,
  53949     },
  53950 #endif /* chips */
  53951 
  53952 #if defined(BCM_88375_A0)
  53953     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r */
  53954         soc_block_list[42],
  53955         soc_genreg,
  53956         1,
  53957         0,
  53958         0x9c,
  53959         0,
  53960         0,
  53961         4,
  53962         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
  53963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53964         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53965         -1,
  53966         -1,
  53967     },
  53968 #endif /* chips */
  53969 
  53970 #if defined(BCM_88375_B0)
  53971     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r */
  53972         soc_block_list[42],
  53973         soc_genreg,
  53974         1,
  53975         0,
  53976         0x9c,
  53977         0,
  53978         0,
  53979         4,
  53980         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
  53981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53982         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53983         -1,
  53984         -1,
  53985     },
  53986 #endif /* chips */
  53987 
  53988 #if defined(BCM_88470_A0)
  53989     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_A0r */
  53990         soc_block_list[42],
  53991         soc_genreg,
  53992         1,
  53993         0,
  53994         0x9c,
  53995         0,
  53996         0,
  53997         4,
  53998         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_A0r_fields,
  53999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54000         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54001         -1,
  54002         -1,
  54003     },
  54004 #endif /* chips */
  54005 
  54006 #if defined(BCM_88470_B0)
  54007     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_B0r */
  54008         soc_block_list[42],
  54009         soc_genreg,
  54010         1,
  54011         0,
  54012         0x9c,
  54013         0,
  54014         0,
  54015         4,
  54016         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_B0r_fields,
  54017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54018         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54019         -1,
  54020         -1,
  54021     },
  54022 #endif /* chips */
  54023 
  54024 #if defined(BCM_88675_B0)
  54025     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r */
  54026         soc_block_list[42],
  54027         soc_genreg,
  54028         1,
  54029         0,
  54030         0x9c,
  54031         0,
  54032         0,
  54033         4,
  54034         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
  54035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54036         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54037         -1,
  54038         -1,
  54039     },
  54040 #endif /* chips */
  54041 
  54042 #if defined(BCM_88680_A0)
  54043     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r */
  54044         soc_block_list[42],
  54045         soc_genreg,
  54046         1,
  54047         0,
  54048         0x9c,
  54049         0,
  54050         0,
  54051         4,
  54052         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
  54053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54054         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54055         -1,
  54056         -1,
  54057     },
  54058 #endif /* chips */
  54059 
  54060 #if defined(BCM_88690_A0)
  54061     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r */
  54062         soc_block_list[42],
  54063         soc_genreg,
  54064         1,
  54065         0,
  54066         0x9c,
  54067         0,
  54068         0,
  54069         6,
  54070         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
  54071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54072         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  54073         -1,
  54074         -1,
  54075     },
  54076 #endif /* chips */
  54077 
  54078 #if defined(BCM_88690_B0)
  54079     { /* SOC_REG_INT_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r */
  54080         soc_block_list[42],
  54081         soc_genreg,
  54082         1,
  54083         0,
  54084         0x9c,
  54085         0,
  54086         0,
  54087         6,
  54088         soc_OLP_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
  54089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54090         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  54091         -1,
  54092         -1,
  54093     },
  54094 #endif /* chips */
  54095 
  54096 #if defined(BCM_88650_A0)
  54097     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTERr */
  54098         soc_block_list[42],
  54099         soc_genreg,
  54100         1,
  54101         0,
  54102         0x7,
  54103         SOC_REG_FLAG_INTERRUPT,
  54104         0,
  54105         3,
  54106         soc_OLP_ECC_INTERRUPT_REGISTERr_fields,
  54107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54108         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54109         -1,
  54110         -1,
  54111     },
  54112 #endif /* chips */
  54113 
  54114 #if defined(BCM_88270_A0)
  54115     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88270_A0r */
  54116         soc_block_list[42],
  54117         soc_genreg,
  54118         1,
  54119         0,
  54120         0x7,
  54121         SOC_REG_FLAG_INTERRUPT |
  54122                           SOC_REG_FLAG_SIGNAL,
  54123         0,
  54124         3,
  54125         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88270_A0r_fields,
  54126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54127         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54128         -1,
  54129         -1,
  54130     },
  54131 #endif /* chips */
  54132 
  54133 #if defined(BCM_88375_A0)
  54134     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88375_A0r */
  54135         soc_block_list[42],
  54136         soc_genreg,
  54137         1,
  54138         0,
  54139         0x7,
  54140         SOC_REG_FLAG_INTERRUPT,
  54141         0,
  54142         3,
  54143         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  54144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54145         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54146         -1,
  54147         -1,
  54148     },
  54149 #endif /* chips */
  54150 
  54151 #if defined(BCM_88375_B0)
  54152     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88375_B0r */
  54153         soc_block_list[42],
  54154         soc_genreg,
  54155         1,
  54156         0,
  54157         0x7,
  54158         SOC_REG_FLAG_INTERRUPT,
  54159         0,
  54160         3,
  54161         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  54162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54163         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54164         -1,
  54165         -1,
  54166     },
  54167 #endif /* chips */
  54168 
  54169 #if defined(BCM_88470_A0)
  54170     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88470_A0r */
  54171         soc_block_list[42],
  54172         soc_genreg,
  54173         1,
  54174         0,
  54175         0x7,
  54176         SOC_REG_FLAG_INTERRUPT |
  54177                           SOC_REG_FLAG_SIGNAL,
  54178         0,
  54179         3,
  54180         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88470_A0r_fields,
  54181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54182         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54183         -1,
  54184         -1,
  54185     },
  54186 #endif /* chips */
  54187 
  54188 #if defined(BCM_88470_B0)
  54189     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88470_B0r */
  54190         soc_block_list[42],
  54191         soc_genreg,
  54192         1,
  54193         0,
  54194         0x7,
  54195         SOC_REG_FLAG_INTERRUPT |
  54196                           SOC_REG_FLAG_SIGNAL,
  54197         0,
  54198         3,
  54199         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88470_B0r_fields,
  54200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54201         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54202         -1,
  54203         -1,
  54204     },
  54205 #endif /* chips */
  54206 
  54207 #if defined(BCM_88650_B0)
  54208     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88650_B0r */
  54209         soc_block_list[42],
  54210         soc_genreg,
  54211         1,
  54212         0,
  54213         0x7,
  54214         SOC_REG_FLAG_INTERRUPT,
  54215         0,
  54216         3,
  54217         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88650_B0r_fields,
  54218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54219         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54220         -1,
  54221         -1,
  54222     },
  54223 #endif /* chips */
  54224 
  54225 #if defined(BCM_88660_A0)
  54226     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88660_A0r */
  54227         soc_block_list[42],
  54228         soc_genreg,
  54229         1,
  54230         0,
  54231         0x7,
  54232         SOC_REG_FLAG_INTERRUPT,
  54233         0,
  54234         3,
  54235         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88660_A0r_fields,
  54236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54237         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54238         -1,
  54239         -1,
  54240     },
  54241 #endif /* chips */
  54242 
  54243 #if defined(BCM_88675_A0)
  54244     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88675_A0r */
  54245         soc_block_list[42],
  54246         soc_genreg,
  54247         1,
  54248         0,
  54249         0x7,
  54250         SOC_REG_FLAG_INTERRUPT,
  54251         0,
  54252         3,
  54253         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88675_A0r_fields,
  54254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54255         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54256         -1,
  54257         -1,
  54258     },
  54259 #endif /* chips */
  54260 
  54261 #if defined(BCM_88675_B0)
  54262     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88675_B0r */
  54263         soc_block_list[42],
  54264         soc_genreg,
  54265         1,
  54266         0,
  54267         0x7,
  54268         SOC_REG_FLAG_INTERRUPT,
  54269         0,
  54270         3,
  54271         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  54272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54273         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54274         -1,
  54275         -1,
  54276     },
  54277 #endif /* chips */
  54278 
  54279 #if defined(BCM_88680_A0)
  54280     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88680_A0r */
  54281         soc_block_list[42],
  54282         soc_genreg,
  54283         1,
  54284         0,
  54285         0x7,
  54286         SOC_REG_FLAG_INTERRUPT,
  54287         0,
  54288         3,
  54289         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  54290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54291         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54292         -1,
  54293         -1,
  54294     },
  54295 #endif /* chips */
  54296 
  54297 #if defined(BCM_88690_A0)
  54298     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88690_A0r */
  54299         soc_block_list[42],
  54300         soc_genreg,
  54301         1,
  54302         0,
  54303         0x7,
  54304         SOC_REG_FLAG_INTERRUPT |
  54305                           SOC_REG_FLAG_SIGNAL,
  54306         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  54307         3,
  54308         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  54309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54310         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54311         -1,
  54312         -1,
  54313     },
  54314 #endif /* chips */
  54315 
  54316 #if defined(BCM_88690_B0)
  54317     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
  54318         soc_block_list[42],
  54319         soc_genreg,
  54320         1,
  54321         0,
  54322         0x7,
  54323         SOC_REG_FLAG_INTERRUPT |
  54324                           SOC_REG_FLAG_SIGNAL,
  54325         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  54326         3,
  54327         soc_OLP_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  54328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54329         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54330         -1,
  54331         -1,
  54332     },
  54333 #endif /* chips */
  54334 
  54335 #if defined(BCM_88650_A0)
  54336     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASKr */
  54337         soc_block_list[42],
  54338         soc_genreg,
  54339         1,
  54340         0,
  54341         0x17,
  54342         SOC_REG_FLAG_INTERRUPT,
  54343         0,
  54344         3,
  54345         soc_OLP_ECC_INTERRUPT_REGISTER_MASKr_fields,
  54346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54347         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54348         -1,
  54349         -1,
  54350     },
  54351 #endif /* chips */
  54352 
  54353 #if defined(BCM_88270_A0)
  54354     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88270_A0r */
  54355         soc_block_list[42],
  54356         soc_genreg,
  54357         1,
  54358         0,
  54359         0x17,
  54360         0,
  54361         0,
  54362         3,
  54363         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88270_A0r_fields,
  54364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54365         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54366         -1,
  54367         -1,
  54368     },
  54369 #endif /* chips */
  54370 
  54371 #if defined(BCM_88375_A0)
  54372     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r */
  54373         soc_block_list[42],
  54374         soc_genreg,
  54375         1,
  54376         0,
  54377         0x17,
  54378         0,
  54379         0,
  54380         3,
  54381         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r_fields,
  54382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54383         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54384         -1,
  54385         -1,
  54386     },
  54387 #endif /* chips */
  54388 
  54389 #if defined(BCM_88375_B0)
  54390     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r */
  54391         soc_block_list[42],
  54392         soc_genreg,
  54393         1,
  54394         0,
  54395         0x17,
  54396         0,
  54397         0,
  54398         3,
  54399         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r_fields,
  54400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54401         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54402         -1,
  54403         -1,
  54404     },
  54405 #endif /* chips */
  54406 
  54407 #if defined(BCM_88470_A0)
  54408     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88470_A0r */
  54409         soc_block_list[42],
  54410         soc_genreg,
  54411         1,
  54412         0,
  54413         0x17,
  54414         0,
  54415         0,
  54416         3,
  54417         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88470_A0r_fields,
  54418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54419         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54420         -1,
  54421         -1,
  54422     },
  54423 #endif /* chips */
  54424 
  54425 #if defined(BCM_88470_B0)
  54426     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88470_B0r */
  54427         soc_block_list[42],
  54428         soc_genreg,
  54429         1,
  54430         0,
  54431         0x17,
  54432         0,
  54433         0,
  54434         3,
  54435         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88470_B0r_fields,
  54436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54437         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54438         -1,
  54439         -1,
  54440     },
  54441 #endif /* chips */
  54442 
  54443 #if defined(BCM_88650_B0)
  54444     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88650_B0r */
  54445         soc_block_list[42],
  54446         soc_genreg,
  54447         1,
  54448         0,
  54449         0x17,
  54450         SOC_REG_FLAG_INTERRUPT,
  54451         0,
  54452         3,
  54453         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88650_B0r_fields,
  54454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54455         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54456         -1,
  54457         -1,
  54458     },
  54459 #endif /* chips */
  54460 
  54461 #if defined(BCM_88660_A0)
  54462     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88660_A0r */
  54463         soc_block_list[42],
  54464         soc_genreg,
  54465         1,
  54466         0,
  54467         0x17,
  54468         SOC_REG_FLAG_INTERRUPT,
  54469         0,
  54470         3,
  54471         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88660_A0r_fields,
  54472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54473         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54474         -1,
  54475         -1,
  54476     },
  54477 #endif /* chips */
  54478 
  54479 #if defined(BCM_88675_A0)
  54480     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88675_A0r */
  54481         soc_block_list[42],
  54482         soc_genreg,
  54483         1,
  54484         0,
  54485         0x17,
  54486         0,
  54487         0,
  54488         3,
  54489         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88675_A0r_fields,
  54490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54491         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54492         -1,
  54493         -1,
  54494     },
  54495 #endif /* chips */
  54496 
  54497 #if defined(BCM_88675_B0)
  54498     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r */
  54499         soc_block_list[42],
  54500         soc_genreg,
  54501         1,
  54502         0,
  54503         0x17,
  54504         0,
  54505         0,
  54506         3,
  54507         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r_fields,
  54508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54509         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54510         -1,
  54511         -1,
  54512     },
  54513 #endif /* chips */
  54514 
  54515 #if defined(BCM_88680_A0)
  54516     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r */
  54517         soc_block_list[42],
  54518         soc_genreg,
  54519         1,
  54520         0,
  54521         0x17,
  54522         0,
  54523         0,
  54524         3,
  54525         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r_fields,
  54526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54527         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54528         -1,
  54529         -1,
  54530     },
  54531 #endif /* chips */
  54532 
  54533 #if defined(BCM_88690_A0)
  54534     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r */
  54535         soc_block_list[42],
  54536         soc_genreg,
  54537         1,
  54538         0,
  54539         0x17,
  54540         0,
  54541         0,
  54542         3,
  54543         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r_fields,
  54544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54545         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54546         -1,
  54547         -1,
  54548     },
  54549 #endif /* chips */
  54550 
  54551 #if defined(BCM_88690_B0)
  54552     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
  54553         soc_block_list[42],
  54554         soc_genreg,
  54555         1,
  54556         0,
  54557         0x17,
  54558         0,
  54559         0,
  54560         3,
  54561         soc_OLP_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
  54562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54563         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54564         -1,
  54565         -1,
  54566     },
  54567 #endif /* chips */
  54568 
  54569 #if defined(BCM_88650_A0)
  54570     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TESTr */
  54571         soc_block_list[42],
  54572         soc_genreg,
  54573         1,
  54574         0,
  54575         0x1f,
  54576         SOC_REG_FLAG_INTERRUPT |
  54577                           SOC_REG_FLAG_SIGNAL,
  54578         0,
  54579         1,
  54580         soc_OLP_ECC_INTERRUPT_REGISTER_TESTr_fields,
  54581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54582         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54583         -1,
  54584         -1,
  54585     },
  54586 #endif /* chips */
  54587 
  54588 #if defined(BCM_88270_A0)
  54589     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88270_A0r */
  54590         soc_block_list[42],
  54591         soc_genreg,
  54592         1,
  54593         0,
  54594         0x1f,
  54595         0,
  54596         0,
  54597         1,
  54598         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88270_A0r_fields,
  54599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54600         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54601         -1,
  54602         -1,
  54603     },
  54604 #endif /* chips */
  54605 
  54606 #if defined(BCM_88375_A0)
  54607     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  54608         soc_block_list[42],
  54609         soc_genreg,
  54610         1,
  54611         0,
  54612         0x1f,
  54613         0,
  54614         0,
  54615         1,
  54616         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  54617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54618         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54619         -1,
  54620         -1,
  54621     },
  54622 #endif /* chips */
  54623 
  54624 #if defined(BCM_88375_B0)
  54625     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  54626         soc_block_list[42],
  54627         soc_genreg,
  54628         1,
  54629         0,
  54630         0x1f,
  54631         0,
  54632         0,
  54633         1,
  54634         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  54635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54637         -1,
  54638         -1,
  54639     },
  54640 #endif /* chips */
  54641 
  54642 #if defined(BCM_88470_A0)
  54643     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88470_A0r */
  54644         soc_block_list[42],
  54645         soc_genreg,
  54646         1,
  54647         0,
  54648         0x1f,
  54649         0,
  54650         0,
  54651         1,
  54652         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88470_A0r_fields,
  54653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54654         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54655         -1,
  54656         -1,
  54657     },
  54658 #endif /* chips */
  54659 
  54660 #if defined(BCM_88470_B0)
  54661     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88470_B0r */
  54662         soc_block_list[42],
  54663         soc_genreg,
  54664         1,
  54665         0,
  54666         0x1f,
  54667         0,
  54668         0,
  54669         1,
  54670         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88470_B0r_fields,
  54671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54672         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54673         -1,
  54674         -1,
  54675     },
  54676 #endif /* chips */
  54677 
  54678 #if defined(BCM_88650_B0)
  54679     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88650_B0r */
  54680         soc_block_list[42],
  54681         soc_genreg,
  54682         1,
  54683         0,
  54684         0x1f,
  54685         SOC_REG_FLAG_INTERRUPT |
  54686                           SOC_REG_FLAG_SIGNAL,
  54687         0,
  54688         1,
  54689         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88650_B0r_fields,
  54690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54691         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54692         -1,
  54693         -1,
  54694     },
  54695 #endif /* chips */
  54696 
  54697 #if defined(BCM_88660_A0)
  54698     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88660_A0r */
  54699         soc_block_list[42],
  54700         soc_genreg,
  54701         1,
  54702         0,
  54703         0x1f,
  54704         SOC_REG_FLAG_INTERRUPT |
  54705                           SOC_REG_FLAG_SIGNAL,
  54706         0,
  54707         1,
  54708         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88660_A0r_fields,
  54709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54710         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54711         -1,
  54712         -1,
  54713     },
  54714 #endif /* chips */
  54715 
  54716 #if defined(BCM_88675_A0)
  54717     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88675_A0r */
  54718         soc_block_list[42],
  54719         soc_genreg,
  54720         1,
  54721         0,
  54722         0x1f,
  54723         0,
  54724         0,
  54725         1,
  54726         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88675_A0r_fields,
  54727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54728         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54729         -1,
  54730         -1,
  54731     },
  54732 #endif /* chips */
  54733 
  54734 #if defined(BCM_88675_B0)
  54735     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  54736         soc_block_list[42],
  54737         soc_genreg,
  54738         1,
  54739         0,
  54740         0x1f,
  54741         0,
  54742         0,
  54743         1,
  54744         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  54745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54746         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54747         -1,
  54748         -1,
  54749     },
  54750 #endif /* chips */
  54751 
  54752 #if defined(BCM_88680_A0)
  54753     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  54754         soc_block_list[42],
  54755         soc_genreg,
  54756         1,
  54757         0,
  54758         0x1f,
  54759         0,
  54760         0,
  54761         1,
  54762         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  54763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54764         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54765         -1,
  54766         -1,
  54767     },
  54768 #endif /* chips */
  54769 
  54770 #if defined(BCM_88690_A0)
  54771     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  54772         soc_block_list[42],
  54773         soc_genreg,
  54774         1,
  54775         0,
  54776         0x1f,
  54777         0,
  54778         0,
  54779         1,
  54780         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  54781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54782         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54783         -1,
  54784         -1,
  54785     },
  54786 #endif /* chips */
  54787 
  54788 #if defined(BCM_88690_B0)
  54789     { /* SOC_REG_INT_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  54790         soc_block_list[42],
  54791         soc_genreg,
  54792         1,
  54793         0,
  54794         0x1f,
  54795         0,
  54796         0,
  54797         1,
  54798         soc_OLP_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  54799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54800         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54801         -1,
  54802         -1,
  54803     },
  54804 #endif /* chips */
  54805 
  54806 #if defined(BCM_88650_A0)
  54807     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESSr */
  54808         soc_block_list[42],
  54809         soc_genreg,
  54810         1,
  54811         0,
  54812         0x84,
  54813         SOC_REG_FLAG_SIGNAL,
  54814         0,
  54815         1,
  54816         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
  54817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54818         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54819         -1,
  54820         -1,
  54821     },
  54822 #endif /* chips */
  54823 
  54824 #if defined(BCM_88270_A0)
  54825     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88270_A0r */
  54826         soc_block_list[42],
  54827         soc_genreg,
  54828         1,
  54829         0,
  54830         0x84,
  54831         0,
  54832         0,
  54833         1,
  54834         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88270_A0r_fields,
  54835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54836         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54837         -1,
  54838         -1,
  54839     },
  54840 #endif /* chips */
  54841 
  54842 #if defined(BCM_88375_A0)
  54843     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_A0r */
  54844         soc_block_list[42],
  54845         soc_genreg,
  54846         1,
  54847         0,
  54848         0x84,
  54849         0,
  54850         0,
  54851         1,
  54852         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_A0r_fields,
  54853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54854         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54855         -1,
  54856         -1,
  54857     },
  54858 #endif /* chips */
  54859 
  54860 #if defined(BCM_88375_B0)
  54861     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_B0r */
  54862         soc_block_list[42],
  54863         soc_genreg,
  54864         1,
  54865         0,
  54866         0x84,
  54867         0,
  54868         0,
  54869         1,
  54870         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_B0r_fields,
  54871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54872         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54873         -1,
  54874         -1,
  54875     },
  54876 #endif /* chips */
  54877 
  54878 #if defined(BCM_88470_A0)
  54879     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_A0r */
  54880         soc_block_list[42],
  54881         soc_genreg,
  54882         1,
  54883         0,
  54884         0x84,
  54885         0,
  54886         0,
  54887         1,
  54888         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_A0r_fields,
  54889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54890         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54891         -1,
  54892         -1,
  54893     },
  54894 #endif /* chips */
  54895 
  54896 #if defined(BCM_88470_B0)
  54897     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_B0r */
  54898         soc_block_list[42],
  54899         soc_genreg,
  54900         1,
  54901         0,
  54902         0x84,
  54903         0,
  54904         0,
  54905         1,
  54906         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_B0r_fields,
  54907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54908         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54909         -1,
  54910         -1,
  54911     },
  54912 #endif /* chips */
  54913 
  54914 #if defined(BCM_88650_B0)
  54915     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88650_B0r */
  54916         soc_block_list[42],
  54917         soc_genreg,
  54918         1,
  54919         0,
  54920         0x84,
  54921         SOC_REG_FLAG_SIGNAL,
  54922         0,
  54923         1,
  54924         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88650_B0r_fields,
  54925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54926         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54927         -1,
  54928         -1,
  54929     },
  54930 #endif /* chips */
  54931 
  54932 #if defined(BCM_88660_A0)
  54933     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88660_A0r */
  54934         soc_block_list[42],
  54935         soc_genreg,
  54936         1,
  54937         0,
  54938         0x84,
  54939         SOC_REG_FLAG_SIGNAL,
  54940         0,
  54941         1,
  54942         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88660_A0r_fields,
  54943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54944         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54945         -1,
  54946         -1,
  54947     },
  54948 #endif /* chips */
  54949 
  54950 #if defined(BCM_88675_A0)
  54951     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_A0r */
  54952         soc_block_list[42],
  54953         soc_genreg,
  54954         1,
  54955         0,
  54956         0x84,
  54957         0,
  54958         0,
  54959         1,
  54960         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_A0r_fields,
  54961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54962         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54963         -1,
  54964         -1,
  54965     },
  54966 #endif /* chips */
  54967 
  54968 #if defined(BCM_88675_B0)
  54969     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_B0r */
  54970         soc_block_list[42],
  54971         soc_genreg,
  54972         1,
  54973         0,
  54974         0x84,
  54975         0,
  54976         0,
  54977         1,
  54978         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_B0r_fields,
  54979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54980         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54981         -1,
  54982         -1,
  54983     },
  54984 #endif /* chips */
  54985 
  54986 #if defined(BCM_88680_A0)
  54987     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r */
  54988         soc_block_list[42],
  54989         soc_genreg,
  54990         1,
  54991         0,
  54992         0x84,
  54993         0,
  54994         0,
  54995         1,
  54996         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r_fields,
  54997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54998         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  54999         -1,
  55000         -1,
  55001     },
  55002 #endif /* chips */
  55003 
  55004 #if defined(BCM_88690_A0)
  55005     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r */
  55006         soc_block_list[42],
  55007         soc_genreg,
  55008         1,
  55009         0,
  55010         0x84,
  55011         0,
  55012         0,
  55013         1,
  55014         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r_fields,
  55015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55016         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55017         -1,
  55018         -1,
  55019     },
  55020 #endif /* chips */
  55021 
  55022 #if defined(BCM_88690_B0)
  55023     { /* SOC_REG_INT_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r */
  55024         soc_block_list[42],
  55025         soc_genreg,
  55026         1,
  55027         0,
  55028         0x84,
  55029         0,
  55030         0,
  55031         1,
  55032         soc_OLP_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r_fields,
  55033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55034         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55035         -1,
  55036         -1,
  55037     },
  55038 #endif /* chips */
  55039 
  55040 #if defined(BCM_88650_A0)
  55041     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTERr */
  55042         soc_block_list[42],
  55043         soc_genreg,
  55044         1,
  55045         0,
  55046         0x125,
  55047         SOC_REG_FLAG_RO,
  55048         0,
  55049         1,
  55050         soc_OLP_EP_TRANSACTION_COUNTERr_fields,
  55051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55052         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55053         -1,
  55054         -1,
  55055     },
  55056 #endif /* chips */
  55057 
  55058 #if defined(BCM_88270_A0)
  55059     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88270_A0r */
  55060         soc_block_list[42],
  55061         soc_genreg,
  55062         1,
  55063         0,
  55064         0x12c,
  55065         SOC_REG_FLAG_RO |
  55066                           SOC_REG_FLAG_SIGNAL,
  55067         0,
  55068         1,
  55069         soc_OLP_EP_TRANSACTION_COUNTER_BCM88270_A0r_fields,
  55070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55071         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55072         -1,
  55073         -1,
  55074     },
  55075 #endif /* chips */
  55076 
  55077 #if defined(BCM_88375_A0)
  55078     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88375_A0r */
  55079         soc_block_list[42],
  55080         soc_genreg,
  55081         1,
  55082         0,
  55083         0x12c,
  55084         SOC_REG_FLAG_RO |
  55085                           SOC_REG_FLAG_SIGNAL,
  55086         0,
  55087         1,
  55088         soc_OLP_EP_TRANSACTION_COUNTER_BCM88375_A0r_fields,
  55089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55090         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55091         -1,
  55092         -1,
  55093     },
  55094 #endif /* chips */
  55095 
  55096 #if defined(BCM_88375_B0)
  55097     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88375_B0r */
  55098         soc_block_list[42],
  55099         soc_genreg,
  55100         1,
  55101         0,
  55102         0x12c,
  55103         SOC_REG_FLAG_RO |
  55104                           SOC_REG_FLAG_SIGNAL,
  55105         0,
  55106         1,
  55107         soc_OLP_EP_TRANSACTION_COUNTER_BCM88375_B0r_fields,
  55108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55109         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55110         -1,
  55111         -1,
  55112     },
  55113 #endif /* chips */
  55114 
  55115 #if defined(BCM_88470_A0)
  55116     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88470_A0r */
  55117         soc_block_list[42],
  55118         soc_genreg,
  55119         1,
  55120         0,
  55121         0x12c,
  55122         SOC_REG_FLAG_RO |
  55123                           SOC_REG_FLAG_SIGNAL,
  55124         0,
  55125         1,
  55126         soc_OLP_EP_TRANSACTION_COUNTER_BCM88470_A0r_fields,
  55127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55128         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55129         -1,
  55130         -1,
  55131     },
  55132 #endif /* chips */
  55133 
  55134 #if defined(BCM_88470_B0)
  55135     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88470_B0r */
  55136         soc_block_list[42],
  55137         soc_genreg,
  55138         1,
  55139         0,
  55140         0x12c,
  55141         SOC_REG_FLAG_RO |
  55142                           SOC_REG_FLAG_SIGNAL,
  55143         0,
  55144         1,
  55145         soc_OLP_EP_TRANSACTION_COUNTER_BCM88470_B0r_fields,
  55146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55147         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55148         -1,
  55149         -1,
  55150     },
  55151 #endif /* chips */
  55152 
  55153 #if defined(BCM_88650_B0)
  55154     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88650_B0r */
  55155         soc_block_list[42],
  55156         soc_genreg,
  55157         1,
  55158         0,
  55159         0x125,
  55160         SOC_REG_FLAG_RO,
  55161         0,
  55162         1,
  55163         soc_OLP_EP_TRANSACTION_COUNTER_BCM88650_B0r_fields,
  55164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55165         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55166         -1,
  55167         -1,
  55168     },
  55169 #endif /* chips */
  55170 
  55171 #if defined(BCM_88660_A0)
  55172     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88660_A0r */
  55173         soc_block_list[42],
  55174         soc_genreg,
  55175         1,
  55176         0,
  55177         0x125,
  55178         SOC_REG_FLAG_RO,
  55179         0,
  55180         1,
  55181         soc_OLP_EP_TRANSACTION_COUNTER_BCM88660_A0r_fields,
  55182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55183         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55184         -1,
  55185         -1,
  55186     },
  55187 #endif /* chips */
  55188 
  55189 #if defined(BCM_88675_A0)
  55190     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88675_A0r */
  55191         soc_block_list[42],
  55192         soc_genreg,
  55193         1,
  55194         0,
  55195         0x12c,
  55196         SOC_REG_FLAG_RO |
  55197                           SOC_REG_FLAG_SIGNAL,
  55198         0,
  55199         1,
  55200         soc_OLP_EP_TRANSACTION_COUNTER_BCM88675_A0r_fields,
  55201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55202         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55203         -1,
  55204         -1,
  55205     },
  55206 #endif /* chips */
  55207 
  55208 #if defined(BCM_88675_B0)
  55209     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88675_B0r */
  55210         soc_block_list[42],
  55211         soc_genreg,
  55212         1,
  55213         0,
  55214         0x12c,
  55215         SOC_REG_FLAG_RO |
  55216                           SOC_REG_FLAG_SIGNAL,
  55217         0,
  55218         1,
  55219         soc_OLP_EP_TRANSACTION_COUNTER_BCM88675_B0r_fields,
  55220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55221         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55222         -1,
  55223         -1,
  55224     },
  55225 #endif /* chips */
  55226 
  55227 #if defined(BCM_88680_A0)
  55228     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88680_A0r */
  55229         soc_block_list[42],
  55230         soc_genreg,
  55231         1,
  55232         0,
  55233         0x12c,
  55234         SOC_REG_FLAG_RO |
  55235                           SOC_REG_FLAG_SIGNAL,
  55236         0,
  55237         1,
  55238         soc_OLP_EP_TRANSACTION_COUNTER_BCM88680_A0r_fields,
  55239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55240         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55241         -1,
  55242         -1,
  55243     },
  55244 #endif /* chips */
  55245 
  55246 #if defined(BCM_88690_A0)
  55247     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88690_A0r */
  55248         soc_block_list[42],
  55249         soc_genreg,
  55250         1,
  55251         0,
  55252         0x14e,
  55253         SOC_REG_FLAG_RO,
  55254         SOC_REG_FLAG_COUNTER_FEILDS,
  55255         1,
  55256         soc_OLP_EP_TRANSACTION_COUNTER_BCM88690_A0r_fields,
  55257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55258         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55259         -1,
  55260         -1,
  55261     },
  55262 #endif /* chips */
  55263 
  55264 #if defined(BCM_88690_B0)
  55265     { /* SOC_REG_INT_OLP_EP_TRANSACTION_COUNTER_BCM88690_B0r */
  55266         soc_block_list[42],
  55267         soc_genreg,
  55268         1,
  55269         0,
  55270         0x14e,
  55271         SOC_REG_FLAG_RO,
  55272         SOC_REG_FLAG_COUNTER_FEILDS,
  55273         1,
  55274         soc_OLP_EP_TRANSACTION_COUNTER_BCM88690_B0r_fields,
  55275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55276         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55277         -1,
  55278         -1,
  55279     },
  55280 #endif /* chips */
  55281 
  55282 #if defined(BCM_88650_A0)
  55283     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATAr */
  55284         soc_block_list[42],
  55285         soc_genreg,
  55286         1,
  55287         0,
  55288         0xa3,
  55289         0,
  55290         0,
  55291         1,
  55292         soc_OLP_ERROR_INITIATION_DATAr_fields,
  55293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55294         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55295         -1,
  55296         -1,
  55297     },
  55298 #endif /* chips */
  55299 
  55300 #if defined(BCM_88270_A0)
  55301     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88270_A0r */
  55302         soc_block_list[42],
  55303         soc_genreg,
  55304         1,
  55305         0,
  55306         0xa3,
  55307         0,
  55308         0,
  55309         1,
  55310         soc_OLP_ERROR_INITIATION_DATA_BCM88270_A0r_fields,
  55311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55312         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55313         -1,
  55314         -1,
  55315     },
  55316 #endif /* chips */
  55317 
  55318 #if defined(BCM_88375_A0)
  55319     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88375_A0r */
  55320         soc_block_list[42],
  55321         soc_genreg,
  55322         1,
  55323         0,
  55324         0xa3,
  55325         0,
  55326         0,
  55327         1,
  55328         soc_OLP_ERROR_INITIATION_DATA_BCM88375_A0r_fields,
  55329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55330         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55331         -1,
  55332         -1,
  55333     },
  55334 #endif /* chips */
  55335 
  55336 #if defined(BCM_88375_B0)
  55337     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88375_B0r */
  55338         soc_block_list[42],
  55339         soc_genreg,
  55340         1,
  55341         0,
  55342         0xa3,
  55343         0,
  55344         0,
  55345         1,
  55346         soc_OLP_ERROR_INITIATION_DATA_BCM88375_B0r_fields,
  55347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55348         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55349         -1,
  55350         -1,
  55351     },
  55352 #endif /* chips */
  55353 
  55354 #if defined(BCM_88470_A0)
  55355     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88470_A0r */
  55356         soc_block_list[42],
  55357         soc_genreg,
  55358         1,
  55359         0,
  55360         0xa3,
  55361         0,
  55362         0,
  55363         1,
  55364         soc_OLP_ERROR_INITIATION_DATA_BCM88470_A0r_fields,
  55365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55366         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55367         -1,
  55368         -1,
  55369     },
  55370 #endif /* chips */
  55371 
  55372 #if defined(BCM_88470_B0)
  55373     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88470_B0r */
  55374         soc_block_list[42],
  55375         soc_genreg,
  55376         1,
  55377         0,
  55378         0xa3,
  55379         0,
  55380         0,
  55381         1,
  55382         soc_OLP_ERROR_INITIATION_DATA_BCM88470_B0r_fields,
  55383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55384         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55385         -1,
  55386         -1,
  55387     },
  55388 #endif /* chips */
  55389 
  55390 #if defined(BCM_88650_B0)
  55391     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88650_B0r */
  55392         soc_block_list[42],
  55393         soc_genreg,
  55394         1,
  55395         0,
  55396         0xa3,
  55397         0,
  55398         0,
  55399         1,
  55400         soc_OLP_ERROR_INITIATION_DATA_BCM88650_B0r_fields,
  55401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55402         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55403         -1,
  55404         -1,
  55405     },
  55406 #endif /* chips */
  55407 
  55408 #if defined(BCM_88660_A0)
  55409     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88660_A0r */
  55410         soc_block_list[42],
  55411         soc_genreg,
  55412         1,
  55413         0,
  55414         0xa3,
  55415         0,
  55416         0,
  55417         1,
  55418         soc_OLP_ERROR_INITIATION_DATA_BCM88660_A0r_fields,
  55419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55420         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55421         -1,
  55422         -1,
  55423     },
  55424 #endif /* chips */
  55425 
  55426 #if defined(BCM_88675_A0)
  55427     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88675_A0r */
  55428         soc_block_list[42],
  55429         soc_genreg,
  55430         1,
  55431         0,
  55432         0xa3,
  55433         0,
  55434         0,
  55435         1,
  55436         soc_OLP_ERROR_INITIATION_DATA_BCM88675_A0r_fields,
  55437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55438         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55439         -1,
  55440         -1,
  55441     },
  55442 #endif /* chips */
  55443 
  55444 #if defined(BCM_88675_B0)
  55445     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88675_B0r */
  55446         soc_block_list[42],
  55447         soc_genreg,
  55448         1,
  55449         0,
  55450         0xa3,
  55451         0,
  55452         0,
  55453         1,
  55454         soc_OLP_ERROR_INITIATION_DATA_BCM88675_B0r_fields,
  55455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55456         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55457         -1,
  55458         -1,
  55459     },
  55460 #endif /* chips */
  55461 
  55462 #if defined(BCM_88680_A0)
  55463     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88680_A0r */
  55464         soc_block_list[42],
  55465         soc_genreg,
  55466         1,
  55467         0,
  55468         0xa3,
  55469         0,
  55470         0,
  55471         1,
  55472         soc_OLP_ERROR_INITIATION_DATA_BCM88680_A0r_fields,
  55473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55474         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55475         -1,
  55476         -1,
  55477     },
  55478 #endif /* chips */
  55479 
  55480 #if defined(BCM_88690_A0)
  55481     { /* SOC_REG_INT_OLP_ERROR_INITIATION_DATA_BCM88690_A0r */
  55482         soc_block_list[42],
  55483         soc_genreg,
  55484         1,
  55485         0,
  55486         0xa3,
  55487         0,
  55488         0,
  55489         1,
  55490         soc_OLP_ERROR_INITIATION_DATA_BCM88690_A0r_fields,
  55491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55492         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55493         -1,
  55494         -1,
  55495     },
  55496 #endif /* chips */
  55497 
  55498 #if defined(BCM_88650_A0)
  55499     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTERr */
  55500         soc_block_list[42],
  55501         soc_genreg,
  55502         1,
  55503         0,
  55504         0x121,
  55505         SOC_REG_FLAG_RO,
  55506         0,
  55507         1,
  55508         soc_OLP_FIFO_0_EVENT_COUNTERr_fields,
  55509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55510         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55511         -1,
  55512         -1,
  55513     },
  55514 #endif /* chips */
  55515 
  55516 #if defined(BCM_88270_A0)
  55517     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88270_A0r */
  55518         soc_block_list[42],
  55519         soc_genreg,
  55520         1,
  55521         0,
  55522         0x127,
  55523         SOC_REG_FLAG_RO |
  55524                           SOC_REG_FLAG_SIGNAL,
  55525         0,
  55526         1,
  55527         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88270_A0r_fields,
  55528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55529         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55530         -1,
  55531         -1,
  55532     },
  55533 #endif /* chips */
  55534 
  55535 #if defined(BCM_88375_A0)
  55536     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88375_A0r */
  55537         soc_block_list[42],
  55538         soc_genreg,
  55539         1,
  55540         0,
  55541         0x127,
  55542         SOC_REG_FLAG_RO |
  55543                           SOC_REG_FLAG_SIGNAL,
  55544         0,
  55545         1,
  55546         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88375_A0r_fields,
  55547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55548         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55549         -1,
  55550         -1,
  55551     },
  55552 #endif /* chips */
  55553 
  55554 #if defined(BCM_88375_B0)
  55555     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88375_B0r */
  55556         soc_block_list[42],
  55557         soc_genreg,
  55558         1,
  55559         0,
  55560         0x127,
  55561         SOC_REG_FLAG_RO |
  55562                           SOC_REG_FLAG_SIGNAL,
  55563         0,
  55564         1,
  55565         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88375_B0r_fields,
  55566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55567         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55568         -1,
  55569         -1,
  55570     },
  55571 #endif /* chips */
  55572 
  55573 #if defined(BCM_88470_A0)
  55574     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88470_A0r */
  55575         soc_block_list[42],
  55576         soc_genreg,
  55577         1,
  55578         0,
  55579         0x127,
  55580         SOC_REG_FLAG_RO |
  55581                           SOC_REG_FLAG_SIGNAL,
  55582         0,
  55583         1,
  55584         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88470_A0r_fields,
  55585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55586         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55587         -1,
  55588         -1,
  55589     },
  55590 #endif /* chips */
  55591 
  55592 #if defined(BCM_88470_B0)
  55593     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88470_B0r */
  55594         soc_block_list[42],
  55595         soc_genreg,
  55596         1,
  55597         0,
  55598         0x127,
  55599         SOC_REG_FLAG_RO |
  55600                           SOC_REG_FLAG_SIGNAL,
  55601         0,
  55602         1,
  55603         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88470_B0r_fields,
  55604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55605         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55606         -1,
  55607         -1,
  55608     },
  55609 #endif /* chips */
  55610 
  55611 #if defined(BCM_88650_B0)
  55612     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88650_B0r */
  55613         soc_block_list[42],
  55614         soc_genreg,
  55615         1,
  55616         0,
  55617         0x121,
  55618         SOC_REG_FLAG_RO,
  55619         0,
  55620         1,
  55621         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88650_B0r_fields,
  55622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55623         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55624         -1,
  55625         -1,
  55626     },
  55627 #endif /* chips */
  55628 
  55629 #if defined(BCM_88660_A0)
  55630     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88660_A0r */
  55631         soc_block_list[42],
  55632         soc_genreg,
  55633         1,
  55634         0,
  55635         0x121,
  55636         SOC_REG_FLAG_RO,
  55637         0,
  55638         1,
  55639         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88660_A0r_fields,
  55640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55641         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55642         -1,
  55643         -1,
  55644     },
  55645 #endif /* chips */
  55646 
  55647 #if defined(BCM_88675_A0)
  55648     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88675_A0r */
  55649         soc_block_list[42],
  55650         soc_genreg,
  55651         1,
  55652         0,
  55653         0x127,
  55654         SOC_REG_FLAG_RO |
  55655                           SOC_REG_FLAG_SIGNAL,
  55656         0,
  55657         1,
  55658         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88675_A0r_fields,
  55659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55660         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55661         -1,
  55662         -1,
  55663     },
  55664 #endif /* chips */
  55665 
  55666 #if defined(BCM_88675_B0)
  55667     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88675_B0r */
  55668         soc_block_list[42],
  55669         soc_genreg,
  55670         1,
  55671         0,
  55672         0x127,
  55673         SOC_REG_FLAG_RO |
  55674                           SOC_REG_FLAG_SIGNAL,
  55675         0,
  55676         1,
  55677         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88675_B0r_fields,
  55678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55679         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55680         -1,
  55681         -1,
  55682     },
  55683 #endif /* chips */
  55684 
  55685 #if defined(BCM_88680_A0)
  55686     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88680_A0r */
  55687         soc_block_list[42],
  55688         soc_genreg,
  55689         1,
  55690         0,
  55691         0x127,
  55692         SOC_REG_FLAG_RO |
  55693                           SOC_REG_FLAG_SIGNAL,
  55694         0,
  55695         1,
  55696         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88680_A0r_fields,
  55697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55698         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55699         -1,
  55700         -1,
  55701     },
  55702 #endif /* chips */
  55703 
  55704 #if defined(BCM_88690_A0)
  55705     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88690_A0r */
  55706         soc_block_list[42],
  55707         soc_genreg,
  55708         1,
  55709         0,
  55710         0x149,
  55711         SOC_REG_FLAG_RO,
  55712         SOC_REG_FLAG_COUNTER_FEILDS,
  55713         1,
  55714         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88690_A0r_fields,
  55715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55716         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55717         -1,
  55718         -1,
  55719     },
  55720 #endif /* chips */
  55721 
  55722 #if defined(BCM_88690_B0)
  55723     { /* SOC_REG_INT_OLP_FIFO_0_EVENT_COUNTER_BCM88690_B0r */
  55724         soc_block_list[42],
  55725         soc_genreg,
  55726         1,
  55727         0,
  55728         0x149,
  55729         SOC_REG_FLAG_RO,
  55730         SOC_REG_FLAG_COUNTER_FEILDS,
  55731         1,
  55732         soc_OLP_FIFO_0_EVENT_COUNTER_BCM88690_B0r_fields,
  55733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55734         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55735         -1,
  55736         -1,
  55737     },
  55738 #endif /* chips */
  55739 
  55740 #if defined(BCM_88650_A0)
  55741     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTERr */
  55742         soc_block_list[42],
  55743         soc_genreg,
  55744         1,
  55745         0,
  55746         0x122,
  55747         SOC_REG_FLAG_RO,
  55748         0,
  55749         1,
  55750         soc_OLP_FIFO_1_EVENT_COUNTERr_fields,
  55751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55752         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55753         -1,
  55754         -1,
  55755     },
  55756 #endif /* chips */
  55757 
  55758 #if defined(BCM_88270_A0)
  55759     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88270_A0r */
  55760         soc_block_list[42],
  55761         soc_genreg,
  55762         1,
  55763         0,
  55764         0x128,
  55765         SOC_REG_FLAG_RO |
  55766                           SOC_REG_FLAG_SIGNAL,
  55767         0,
  55768         1,
  55769         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88270_A0r_fields,
  55770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55771         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55772         -1,
  55773         -1,
  55774     },
  55775 #endif /* chips */
  55776 
  55777 #if defined(BCM_88375_A0)
  55778     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88375_A0r */
  55779         soc_block_list[42],
  55780         soc_genreg,
  55781         1,
  55782         0,
  55783         0x128,
  55784         SOC_REG_FLAG_RO |
  55785                           SOC_REG_FLAG_SIGNAL,
  55786         0,
  55787         1,
  55788         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88375_A0r_fields,
  55789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55790         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55791         -1,
  55792         -1,
  55793     },
  55794 #endif /* chips */
  55795 
  55796 #if defined(BCM_88375_B0)
  55797     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88375_B0r */
  55798         soc_block_list[42],
  55799         soc_genreg,
  55800         1,
  55801         0,
  55802         0x128,
  55803         SOC_REG_FLAG_RO |
  55804                           SOC_REG_FLAG_SIGNAL,
  55805         0,
  55806         1,
  55807         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88375_B0r_fields,
  55808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55809         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55810         -1,
  55811         -1,
  55812     },
  55813 #endif /* chips */
  55814 
  55815 #if defined(BCM_88470_A0)
  55816     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88470_A0r */
  55817         soc_block_list[42],
  55818         soc_genreg,
  55819         1,
  55820         0,
  55821         0x128,
  55822         SOC_REG_FLAG_RO |
  55823                           SOC_REG_FLAG_SIGNAL,
  55824         0,
  55825         1,
  55826         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88470_A0r_fields,
  55827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55828         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55829         -1,
  55830         -1,
  55831     },
  55832 #endif /* chips */
  55833 
  55834 #if defined(BCM_88470_B0)
  55835     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88470_B0r */
  55836         soc_block_list[42],
  55837         soc_genreg,
  55838         1,
  55839         0,
  55840         0x128,
  55841         SOC_REG_FLAG_RO |
  55842                           SOC_REG_FLAG_SIGNAL,
  55843         0,
  55844         1,
  55845         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88470_B0r_fields,
  55846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55847         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55848         -1,
  55849         -1,
  55850     },
  55851 #endif /* chips */
  55852 
  55853 #if defined(BCM_88650_B0)
  55854     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88650_B0r */
  55855         soc_block_list[42],
  55856         soc_genreg,
  55857         1,
  55858         0,
  55859         0x122,
  55860         SOC_REG_FLAG_RO,
  55861         0,
  55862         1,
  55863         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88650_B0r_fields,
  55864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55865         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55866         -1,
  55867         -1,
  55868     },
  55869 #endif /* chips */
  55870 
  55871 #if defined(BCM_88660_A0)
  55872     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88660_A0r */
  55873         soc_block_list[42],
  55874         soc_genreg,
  55875         1,
  55876         0,
  55877         0x122,
  55878         SOC_REG_FLAG_RO,
  55879         0,
  55880         1,
  55881         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88660_A0r_fields,
  55882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55883         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55884         -1,
  55885         -1,
  55886     },
  55887 #endif /* chips */
  55888 
  55889 #if defined(BCM_88675_A0)
  55890     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88675_A0r */
  55891         soc_block_list[42],
  55892         soc_genreg,
  55893         1,
  55894         0,
  55895         0x128,
  55896         SOC_REG_FLAG_RO |
  55897                           SOC_REG_FLAG_SIGNAL,
  55898         0,
  55899         1,
  55900         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88675_A0r_fields,
  55901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55902         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55903         -1,
  55904         -1,
  55905     },
  55906 #endif /* chips */
  55907 
  55908 #if defined(BCM_88675_B0)
  55909     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88675_B0r */
  55910         soc_block_list[42],
  55911         soc_genreg,
  55912         1,
  55913         0,
  55914         0x128,
  55915         SOC_REG_FLAG_RO |
  55916                           SOC_REG_FLAG_SIGNAL,
  55917         0,
  55918         1,
  55919         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88675_B0r_fields,
  55920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55921         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55922         -1,
  55923         -1,
  55924     },
  55925 #endif /* chips */
  55926 
  55927 #if defined(BCM_88680_A0)
  55928     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88680_A0r */
  55929         soc_block_list[42],
  55930         soc_genreg,
  55931         1,
  55932         0,
  55933         0x128,
  55934         SOC_REG_FLAG_RO |
  55935                           SOC_REG_FLAG_SIGNAL,
  55936         0,
  55937         1,
  55938         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88680_A0r_fields,
  55939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55940         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55941         -1,
  55942         -1,
  55943     },
  55944 #endif /* chips */
  55945 
  55946 #if defined(BCM_88690_A0)
  55947     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88690_A0r */
  55948         soc_block_list[42],
  55949         soc_genreg,
  55950         1,
  55951         0,
  55952         0x14a,
  55953         SOC_REG_FLAG_RO,
  55954         SOC_REG_FLAG_COUNTER_FEILDS,
  55955         1,
  55956         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88690_A0r_fields,
  55957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55958         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55959         -1,
  55960         -1,
  55961     },
  55962 #endif /* chips */
  55963 
  55964 #if defined(BCM_88690_B0)
  55965     { /* SOC_REG_INT_OLP_FIFO_1_EVENT_COUNTER_BCM88690_B0r */
  55966         soc_block_list[42],
  55967         soc_genreg,
  55968         1,
  55969         0,
  55970         0x14a,
  55971         SOC_REG_FLAG_RO,
  55972         SOC_REG_FLAG_COUNTER_FEILDS,
  55973         1,
  55974         soc_OLP_FIFO_1_EVENT_COUNTER_BCM88690_B0r_fields,
  55975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55976         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55977         -1,
  55978         -1,
  55979     },
  55980 #endif /* chips */
  55981 
  55982 #if defined(BCM_88675_A0)
  55983     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTERr */
  55984         soc_block_list[42],
  55985         soc_genreg,
  55986         1,
  55987         0,
  55988         0x129,
  55989         SOC_REG_FLAG_RO |
  55990                           SOC_REG_FLAG_SIGNAL,
  55991         0,
  55992         1,
  55993         soc_OLP_FIFO_DMA_EVENT_COUNTERr_fields,
  55994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55995         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55996         -1,
  55997         -1,
  55998     },
  55999 #endif /* chips */
  56000 
  56001 #if defined(BCM_88270_A0)
  56002     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTER_BCM88270_A0r */
  56003         soc_block_list[42],
  56004         soc_genreg,
  56005         1,
  56006         0,
  56007         0x129,
  56008         SOC_REG_FLAG_RO |
  56009                           SOC_REG_FLAG_SIGNAL,
  56010         0,
  56011         1,
  56012         soc_OLP_FIFO_DMA_EVENT_COUNTER_BCM88270_A0r_fields,
  56013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56014         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  56015         -1,
  56016         -1,
  56017     },
  56018 #endif /* chips */
  56019 
  56020 #if defined(BCM_88375_A0)
  56021     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTER_BCM88375_A0r */
  56022         soc_block_list[42],
  56023         soc_genreg,
  56024         1,
  56025         0,
  56026         0x129,
  56027         SOC_REG_FLAG_RO |
  56028                           SOC_REG_FLAG_SIGNAL,
  56029         0,
  56030         1,
  56031         soc_OLP_FIFO_DMA_EVENT_COUNTER_BCM88375_A0r_fields,
  56032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56033         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  56034         -1,
  56035         -1,
  56036     },
  56037 #endif /* chips */
  56038 
  56039 #if defined(BCM_88375_B0)
  56040     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTER_BCM88375_B0r */
  56041         soc_block_list[42],
  56042         soc_genreg,
  56043         1,
  56044         0,
  56045         0x129,
  56046         SOC_REG_FLAG_RO |
  56047                           SOC_REG_FLAG_SIGNAL,
  56048         0,
  56049         1,
  56050         soc_OLP_FIFO_DMA_EVENT_COUNTER_BCM88375_B0r_fields,
  56051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56052         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  56053         -1,
  56054         -1,
  56055     },
  56056 #endif /* chips */
  56057 
  56058 #if defined(BCM_88470_A0)
  56059     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTER_BCM88470_A0r */
  56060         soc_block_list[42],
  56061         soc_genreg,
  56062         1,
  56063         0,
  56064         0x129,
  56065         SOC_REG_FLAG_RO |
  56066                           SOC_REG_FLAG_SIGNAL,
  56067         0,
  56068         1,
  56069         soc_OLP_FIFO_DMA_EVENT_COUNTER_BCM88470_A0r_fields,
  56070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56071         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  56072         -1,
  56073         -1,
  56074     },
  56075 #endif /* chips */
  56076 
  56077 #if defined(BCM_88470_B0)
  56078     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTER_BCM88470_B0r */
  56079         soc_block_list[42],
  56080         soc_genreg,
  56081         1,
  56082         0,
  56083         0x129,
  56084         SOC_REG_FLAG_RO |
  56085                           SOC_REG_FLAG_SIGNAL,
  56086         0,
  56087         1,
  56088         soc_OLP_FIFO_DMA_EVENT_COUNTER_BCM88470_B0r_fields,
  56089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56090         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  56091         -1,
  56092         -1,
  56093     },
  56094 #endif /* chips */
  56095 
  56096 #if defined(BCM_88675_B0)
  56097     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTER_BCM88675_B0r */
  56098         soc_block_list[42],
  56099         soc_genreg,
  56100         1,
  56101         0,
  56102         0x129,
  56103         SOC_REG_FLAG_RO |
  56104                           SOC_REG_FLAG_SIGNAL,
  56105         0,
  56106         1,
  56107         soc_OLP_FIFO_DMA_EVENT_COUNTER_BCM88675_B0r_fields,
  56108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56109         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  56110         -1,
  56111         -1,
  56112     },
  56113 #endif /* chips */
  56114 
  56115 #if defined(BCM_88680_A0)
  56116     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTER_BCM88680_A0r */
  56117         soc_block_list[42],
  56118         soc_genreg,
  56119         1,
  56120         0,
  56121         0x129,
  56122         SOC_REG_FLAG_RO |
  56123                           SOC_REG_FLAG_SIGNAL,
  56124         0,
  56125         1,
  56126         soc_OLP_FIFO_DMA_EVENT_COUNTER_BCM88680_A0r_fields,
  56127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56128         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  56129         -1,
  56130         -1,
  56131     },
  56132 #endif /* chips */
  56133 
  56134 #if defined(BCM_88690_A0)
  56135     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTER_BCM88690_A0r */
  56136         soc_block_list[42],
  56137         soc_genreg,
  56138         1,
  56139         0,
  56140         0x14b,
  56141         SOC_REG_FLAG_RO,
  56142         SOC_REG_FLAG_COUNTER_FEILDS,
  56143         1,
  56144         soc_OLP_FIFO_DMA_EVENT_COUNTER_BCM88690_A0r_fields,
  56145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56146         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  56147         -1,
  56148         -1,
  56149     },
  56150 #endif /* chips */
  56151 
  56152 #if defined(BCM_88690_B0)
  56153     { /* SOC_REG_INT_OLP_FIFO_DMA_EVENT_COUNTER_BCM88690_B0r */
  56154         soc_block_list[42],
  56155         soc_genreg,
  56156         1,
  56157         0,
  56158         0x14b,
  56159         SOC_REG_FLAG_RO,
  56160         SOC_REG_FLAG_COUNTER_FEILDS,
  56161         1,
  56162         soc_OLP_FIFO_DMA_EVENT_COUNTER_BCM88690_B0r_fields,
  56163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56164         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  56165         -1,
  56166         -1,
  56167     },
  56168 #endif /* chips */
  56169 
  56170 #if defined(BCM_88675_A0)
  56171     { /* SOC_REG_INT_OLP_GLOBAL_MEM_OPTIONSr */
  56172         soc_block_list[42],
  56173         soc_genreg,
  56174         1,
  56175         0,
  56176         0xc0,
  56177         0,
  56178         0,
  56179         4,
  56180         soc_OLP_GLOBAL_MEM_OPTIONSr_fields,
  56181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56182         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  56183         -1,
  56184         -1,
  56185     },
  56186 #endif /* chips */
  56187 
  56188 #if defined(BCM_88270_A0)
  56189     { /* SOC_REG_INT_OLP_GLOBAL_MEM_OPTIONS_BCM88270_A0r */
  56190         soc_block_list[42],
  56191         soc_genreg,
  56192         1,
  56193         0,
  56194         0xc0,
  56195         0,
  56196         0,
  56197         6,
  56198         soc_OLP_GLOBAL_MEM_OPTIONS_BCM88270_A0r_fields,
  56199         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  56200         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  56201         -1,
  56202         -1,
  56203     },
  56204 #endif /* chips */
  56205 
  56206 #if defined(BCM_88375_A0)
  56207     { /* SOC_REG_INT_OLP_GLOBAL_MEM_OPTIONS_BCM88375_A0r */
  56208         soc_block_list[42],
  56209         soc_genreg,
  56210         1,
  56211         0,
  56212         0xc0,
  56213         0,
  56214         0,
  56215         4,
  56216         soc_OLP_GLOBAL_MEM_OPTIONS_BCM88375_A0r_fields,
  56217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56218         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  56219         -1,
  56220         -1,
  56221     },
  56222 #endif /* chips */
  56223 
  56224 #if defined(BCM_88375_B0)
  56225     { /* SOC_REG_INT_OLP_GLOBAL_MEM_OPTIONS_BCM88375_B0r */
  56226         soc_block_list[42],
  56227         soc_genreg,
  56228         1,
  56229         0,
  56230         0xc0,
  56231         0,
  56232         0,
  56233         4,
  56234         soc_OLP_GLOBAL_MEM_OPTIONS_BCM88375_B0r_fields,
  56235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56236         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  56237         -1,
  56238         -1,
  56239     },
  56240 #endif /* chips */
  56241 
  56242 #if defined(BCM_88470_A0)
  56243     { /* SOC_REG_INT_OLP_GLOBAL_MEM_OPTIONS_BCM88470_A0r */
  56244         soc_block_list[42],
  56245         soc_genreg,
  56246         1,
  56247         0,
  56248         0xc0,
  56249         0,
  56250         0,
  56251         6,
  56252         soc_OLP_GLOBAL_MEM_OPTIONS_BCM88470_A0r_fields,
  56253         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  56254         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  56255         -1,
  56256         -1,
  56257     },
  56258 #endif /* chips */
  56259 
  56260 #if defined(BCM_88470_B0)
  56261     { /* SOC_REG_INT_OLP_GLOBAL_MEM_OPTIONS_BCM88470_B0r */
  56262         soc_block_list[42],
  56263         soc_genreg,
  56264         1,
  56265         0,
  56266         0xc0,
  56267         0,
  56268         0,
  56269         6,
  56270         soc_OLP_GLOBAL_MEM_OPTIONS_BCM88470_B0r_fields,
  56271         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  56272         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  56273         -1,
  56274         -1,
  56275     },
  56276 #endif /* chips */
  56277 
  56278 #if defined(BCM_88675_B0)
  56279     { /* SOC_REG_INT_OLP_GLOBAL_MEM_OPTIONS_BCM88675_B0r */
  56280         soc_block_list[42],
  56281         soc_genreg,
  56282         1,
  56283         0,
  56284         0xc0,
  56285         0,
  56286         0,
  56287         4,
  56288         soc_OLP_GLOBAL_MEM_OPTIONS_BCM88675_B0r_fields,
  56289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56290         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  56291         -1,
  56292         -1,
  56293     },
  56294 #endif /* chips */
  56295 
  56296 #if defined(BCM_88680_A0)
  56297     { /* SOC_REG_INT_OLP_GLOBAL_MEM_OPTIONS_BCM88680_A0r */
  56298         soc_block_list[42],
  56299         soc_genreg,
  56300         1,
  56301         0,
  56302         0xc0,
  56303         0,
  56304         0,
  56305         4,
  56306         soc_OLP_GLOBAL_MEM_OPTIONS_BCM88680_A0r_fields,
  56307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56308         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  56309         -1,
  56310         -1,
  56311     },
  56312 #endif /* chips */
  56313 
  56314 #if defined(BCM_88675_A0)
  56315     { /* SOC_REG_INT_OLP_GLOBAL_PP_1r */
  56316         soc_block_list[42],
  56317         soc_genreg,
  56318         1,
  56319         0,
  56320         0xe7,
  56321         0,
  56322         0,
  56323         6,
  56324         soc_OLP_GLOBAL_PP_1r_fields,
  56325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56326         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56327         -1,
  56328         -1,
  56329     },
  56330 #endif /* chips */
  56331 
  56332 #if defined(BCM_88270_A0)
  56333     { /* SOC_REG_INT_OLP_GLOBAL_PP_1_BCM88270_A0r */
  56334         soc_block_list[42],
  56335         soc_genreg,
  56336         1,
  56337         0,
  56338         0xe7,
  56339         0,
  56340         0,
  56341         6,
  56342         soc_OLP_GLOBAL_PP_1_BCM88270_A0r_fields,
  56343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56344         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56345         -1,
  56346         -1,
  56347     },
  56348 #endif /* chips */
  56349 
  56350 #if defined(BCM_88375_A0)
  56351     { /* SOC_REG_INT_OLP_GLOBAL_PP_1_BCM88375_A0r */
  56352         soc_block_list[42],
  56353         soc_genreg,
  56354         1,
  56355         0,
  56356         0xe7,
  56357         0,
  56358         0,
  56359         6,
  56360         soc_OLP_GLOBAL_PP_1_BCM88375_A0r_fields,
  56361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56362         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56363         -1,
  56364         -1,
  56365     },
  56366 #endif /* chips */
  56367 
  56368 #if defined(BCM_88375_B0)
  56369     { /* SOC_REG_INT_OLP_GLOBAL_PP_1_BCM88375_B0r */
  56370         soc_block_list[42],
  56371         soc_genreg,
  56372         1,
  56373         0,
  56374         0xe7,
  56375         0,
  56376         0,
  56377         6,
  56378         soc_OLP_GLOBAL_PP_1_BCM88375_B0r_fields,
  56379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56380         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56381         -1,
  56382         -1,
  56383     },
  56384 #endif /* chips */
  56385 
  56386 #if defined(BCM_88470_A0)
  56387     { /* SOC_REG_INT_OLP_GLOBAL_PP_1_BCM88470_A0r */
  56388         soc_block_list[42],
  56389         soc_genreg,
  56390         1,
  56391         0,
  56392         0xe7,
  56393         0,
  56394         0,
  56395         6,
  56396         soc_OLP_GLOBAL_PP_1_BCM88470_A0r_fields,
  56397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56398         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56399         -1,
  56400         -1,
  56401     },
  56402 #endif /* chips */
  56403 
  56404 #if defined(BCM_88470_B0)
  56405     { /* SOC_REG_INT_OLP_GLOBAL_PP_1_BCM88470_B0r */
  56406         soc_block_list[42],
  56407         soc_genreg,
  56408         1,
  56409         0,
  56410         0xe7,
  56411         0,
  56412         0,
  56413         6,
  56414         soc_OLP_GLOBAL_PP_1_BCM88470_B0r_fields,
  56415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56416         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56417         -1,
  56418         -1,
  56419     },
  56420 #endif /* chips */
  56421 
  56422 #if defined(BCM_88675_B0)
  56423     { /* SOC_REG_INT_OLP_GLOBAL_PP_1_BCM88675_B0r */
  56424         soc_block_list[42],
  56425         soc_genreg,
  56426         1,
  56427         0,
  56428         0xe7,
  56429         0,
  56430         0,
  56431         6,
  56432         soc_OLP_GLOBAL_PP_1_BCM88675_B0r_fields,
  56433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56434         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56435         -1,
  56436         -1,
  56437     },
  56438 #endif /* chips */
  56439 
  56440 #if defined(BCM_88680_A0)
  56441     { /* SOC_REG_INT_OLP_GLOBAL_PP_1_BCM88680_A0r */
  56442         soc_block_list[42],
  56443         soc_genreg,
  56444         1,
  56445         0,
  56446         0xe7,
  56447         0,
  56448         0,
  56449         6,
  56450         soc_OLP_GLOBAL_PP_1_BCM88680_A0r_fields,
  56451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56452         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56453         -1,
  56454         -1,
  56455     },
  56456 #endif /* chips */
  56457 
  56458 #if defined(BCM_88650_B0)
  56459     { /* SOC_REG_INT_OLP_GLOBAL_REGISTER_1r */
  56460         soc_block_list[42],
  56461         soc_genreg,
  56462         1,
  56463         0,
  56464         0x100,
  56465         SOC_REG_FLAG_SIGNAL,
  56466         0,
  56467         6,
  56468         soc_OLP_GLOBAL_REGISTER_1r_fields,
  56469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56470         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56471         -1,
  56472         -1,
  56473     },
  56474 #endif /* chips */
  56475 
  56476 #if defined(BCM_88660_A0)
  56477     { /* SOC_REG_INT_OLP_GLOBAL_REGISTER_1_BCM88660_A0r */
  56478         soc_block_list[42],
  56479         soc_genreg,
  56480         1,
  56481         0,
  56482         0x100,
  56483         SOC_REG_FLAG_SIGNAL,
  56484         0,
  56485         6,
  56486         soc_OLP_GLOBAL_REGISTER_1_BCM88660_A0r_fields,
  56487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56488         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56489         -1,
  56490         -1,
  56491     },
  56492 #endif /* chips */
  56493 
  56494 #if defined(BCM_88650_A0)
  56495     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATIONr */
  56496         soc_block_list[42],
  56497         soc_genreg,
  56498         1,
  56499         0,
  56500         0x88,
  56501         0,
  56502         0,
  56503         3,
  56504         soc_OLP_GTIMER_CONFIGURATIONr_fields,
  56505         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  56506         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56507         -1,
  56508         -1,
  56509     },
  56510 #endif /* chips */
  56511 
  56512 #if defined(BCM_88270_A0)
  56513     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88270_A0r */
  56514         soc_block_list[42],
  56515         soc_genreg,
  56516         1,
  56517         0,
  56518         0x88,
  56519         SOC_REG_FLAG_64_BITS,
  56520         0,
  56521         4,
  56522         soc_OLP_GTIMER_CONFIGURATION_BCM88270_A0r_fields,
  56523         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  56524         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  56525         -1,
  56526         -1,
  56527     },
  56528 #endif /* chips */
  56529 
  56530 #if defined(BCM_88375_A0)
  56531     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88375_A0r */
  56532         soc_block_list[42],
  56533         soc_genreg,
  56534         1,
  56535         0,
  56536         0x88,
  56537         0,
  56538         0,
  56539         3,
  56540         soc_OLP_GTIMER_CONFIGURATION_BCM88375_A0r_fields,
  56541         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  56542         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56543         -1,
  56544         -1,
  56545     },
  56546 #endif /* chips */
  56547 
  56548 #if defined(BCM_88375_B0)
  56549     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88375_B0r */
  56550         soc_block_list[42],
  56551         soc_genreg,
  56552         1,
  56553         0,
  56554         0x88,
  56555         0,
  56556         0,
  56557         3,
  56558         soc_OLP_GTIMER_CONFIGURATION_BCM88375_B0r_fields,
  56559         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  56560         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56561         -1,
  56562         -1,
  56563     },
  56564 #endif /* chips */
  56565 
  56566 #if defined(BCM_88470_A0)
  56567     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88470_A0r */
  56568         soc_block_list[42],
  56569         soc_genreg,
  56570         1,
  56571         0,
  56572         0x88,
  56573         SOC_REG_FLAG_64_BITS,
  56574         0,
  56575         4,
  56576         soc_OLP_GTIMER_CONFIGURATION_BCM88470_A0r_fields,
  56577         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  56578         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  56579         -1,
  56580         -1,
  56581     },
  56582 #endif /* chips */
  56583 
  56584 #if defined(BCM_88470_B0)
  56585     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88470_B0r */
  56586         soc_block_list[42],
  56587         soc_genreg,
  56588         1,
  56589         0,
  56590         0x88,
  56591         SOC_REG_FLAG_64_BITS,
  56592         0,
  56593         4,
  56594         soc_OLP_GTIMER_CONFIGURATION_BCM88470_B0r_fields,
  56595         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  56596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  56597         -1,
  56598         -1,
  56599     },
  56600 #endif /* chips */
  56601 
  56602 #if defined(BCM_88650_B0)
  56603     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88650_B0r */
  56604         soc_block_list[42],
  56605         soc_genreg,
  56606         1,
  56607         0,
  56608         0x88,
  56609         0,
  56610         0,
  56611         3,
  56612         soc_OLP_GTIMER_CONFIGURATION_BCM88650_B0r_fields,
  56613         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  56614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56615         -1,
  56616         -1,
  56617     },
  56618 #endif /* chips */
  56619 
  56620 #if defined(BCM_88660_A0)
  56621     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88660_A0r */
  56622         soc_block_list[42],
  56623         soc_genreg,
  56624         1,
  56625         0,
  56626         0x88,
  56627         0,
  56628         0,
  56629         3,
  56630         soc_OLP_GTIMER_CONFIGURATION_BCM88660_A0r_fields,
  56631         SOC_RESET_VAL_DEC(0x23c34600, 0x00000000)
  56632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56633         -1,
  56634         -1,
  56635     },
  56636 #endif /* chips */
  56637 
  56638 #if defined(BCM_88675_A0)
  56639     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88675_A0r */
  56640         soc_block_list[42],
  56641         soc_genreg,
  56642         1,
  56643         0,
  56644         0x88,
  56645         0,
  56646         0,
  56647         3,
  56648         soc_OLP_GTIMER_CONFIGURATION_BCM88675_A0r_fields,
  56649         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  56650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56651         -1,
  56652         -1,
  56653     },
  56654 #endif /* chips */
  56655 
  56656 #if defined(BCM_88675_B0)
  56657     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88675_B0r */
  56658         soc_block_list[42],
  56659         soc_genreg,
  56660         1,
  56661         0,
  56662         0x88,
  56663         0,
  56664         0,
  56665         3,
  56666         soc_OLP_GTIMER_CONFIGURATION_BCM88675_B0r_fields,
  56667         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  56668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56669         -1,
  56670         -1,
  56671     },
  56672 #endif /* chips */
  56673 
  56674 #if defined(BCM_88680_A0)
  56675     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88680_A0r */
  56676         soc_block_list[42],
  56677         soc_genreg,
  56678         1,
  56679         0,
  56680         0x88,
  56681         0,
  56682         0,
  56683         3,
  56684         soc_OLP_GTIMER_CONFIGURATION_BCM88680_A0r_fields,
  56685         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  56686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56687         -1,
  56688         -1,
  56689     },
  56690 #endif /* chips */
  56691 
  56692 #if defined(BCM_88690_A0)
  56693     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88690_A0r */
  56694         soc_block_list[42],
  56695         soc_genreg,
  56696         1,
  56697         0,
  56698         0x89,
  56699         0,
  56700         0,
  56701         3,
  56702         soc_OLP_GTIMER_CONFIGURATION_BCM88690_A0r_fields,
  56703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56704         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  56705         -1,
  56706         -1,
  56707     },
  56708 #endif /* chips */
  56709 
  56710 #if defined(BCM_88690_B0)
  56711     { /* SOC_REG_INT_OLP_GTIMER_CONFIGURATION_BCM88690_B0r */
  56712         soc_block_list[42],
  56713         soc_genreg,
  56714         1,
  56715         0,
  56716         0x89,
  56717         0,
  56718         0,
  56719         3,
  56720         soc_OLP_GTIMER_CONFIGURATION_BCM88690_B0r_fields,
  56721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56722         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  56723         -1,
  56724         -1,
  56725     },
  56726 #endif /* chips */
  56727 
  56728 #if defined(BCM_88690_A0)
  56729     { /* SOC_REG_INT_OLP_GTIMER_CYCLEr */
  56730         soc_block_list[42],
  56731         soc_genreg,
  56732         1,
  56733         0,
  56734         0x88,
  56735         0,
  56736         0,
  56737         1,
  56738         soc_OLP_GTIMER_CYCLEr_fields,
  56739         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  56740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56741         -1,
  56742         -1,
  56743     },
  56744 #endif /* chips */
  56745 
  56746 #if defined(BCM_88690_B0)
  56747     { /* SOC_REG_INT_OLP_GTIMER_CYCLE_BCM88690_B0r */
  56748         soc_block_list[42],
  56749         soc_genreg,
  56750         1,
  56751         0,
  56752         0x88,
  56753         0,
  56754         0,
  56755         1,
  56756         soc_OLP_GTIMER_CYCLE_BCM88690_B0r_fields,
  56757         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  56758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56759         -1,
  56760         -1,
  56761     },
  56762 #endif /* chips */
  56763 
  56764 #if defined(BCM_88650_A0)
  56765     { /* SOC_REG_INT_OLP_GTIMER_TRIGGERr */
  56766         soc_block_list[42],
  56767         soc_genreg,
  56768         1,
  56769         0,
  56770         0x89,
  56771         SOC_REG_FLAG_SIGNAL,
  56772         0,
  56773         1,
  56774         soc_OLP_GTIMER_TRIGGERr_fields,
  56775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56776         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56777         -1,
  56778         -1,
  56779     },
  56780 #endif /* chips */
  56781 
  56782 #if defined(BCM_88375_A0)
  56783     { /* SOC_REG_INT_OLP_GTIMER_TRIGGER_BCM88375_A0r */
  56784         soc_block_list[42],
  56785         soc_genreg,
  56786         1,
  56787         0,
  56788         0x89,
  56789         SOC_REG_FLAG_RO,
  56790         0,
  56791         1,
  56792         soc_OLP_GTIMER_TRIGGER_BCM88375_A0r_fields,
  56793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56794         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56795         -1,
  56796         -1,
  56797     },
  56798 #endif /* chips */
  56799 
  56800 #if defined(BCM_88375_B0)
  56801     { /* SOC_REG_INT_OLP_GTIMER_TRIGGER_BCM88375_B0r */
  56802         soc_block_list[42],
  56803         soc_genreg,
  56804         1,
  56805         0,
  56806         0x89,
  56807         SOC_REG_FLAG_RO,
  56808         0,
  56809         1,
  56810         soc_OLP_GTIMER_TRIGGER_BCM88375_B0r_fields,
  56811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56812         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56813         -1,
  56814         -1,
  56815     },
  56816 #endif /* chips */
  56817 
  56818 #if defined(BCM_88650_B0)
  56819     { /* SOC_REG_INT_OLP_GTIMER_TRIGGER_BCM88650_B0r */
  56820         soc_block_list[42],
  56821         soc_genreg,
  56822         1,
  56823         0,
  56824         0x89,
  56825         SOC_REG_FLAG_SIGNAL,
  56826         0,
  56827         1,
  56828         soc_OLP_GTIMER_TRIGGER_BCM88650_B0r_fields,
  56829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56830         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56831         -1,
  56832         -1,
  56833     },
  56834 #endif /* chips */
  56835 
  56836 #if defined(BCM_88660_A0)
  56837     { /* SOC_REG_INT_OLP_GTIMER_TRIGGER_BCM88660_A0r */
  56838         soc_block_list[42],
  56839         soc_genreg,
  56840         1,
  56841         0,
  56842         0x89,
  56843         SOC_REG_FLAG_SIGNAL,
  56844         0,
  56845         1,
  56846         soc_OLP_GTIMER_TRIGGER_BCM88660_A0r_fields,
  56847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56848         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56849         -1,
  56850         -1,
  56851     },
  56852 #endif /* chips */
  56853 
  56854 #if defined(BCM_88675_A0)
  56855     { /* SOC_REG_INT_OLP_GTIMER_TRIGGER_BCM88675_A0r */
  56856         soc_block_list[42],
  56857         soc_genreg,
  56858         1,
  56859         0,
  56860         0x89,
  56861         SOC_REG_FLAG_RO,
  56862         0,
  56863         1,
  56864         soc_OLP_GTIMER_TRIGGER_BCM88675_A0r_fields,
  56865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56866         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56867         -1,
  56868         -1,
  56869     },
  56870 #endif /* chips */
  56871 
  56872 #if defined(BCM_88675_B0)
  56873     { /* SOC_REG_INT_OLP_GTIMER_TRIGGER_BCM88675_B0r */
  56874         soc_block_list[42],
  56875         soc_genreg,
  56876         1,
  56877         0,
  56878         0x89,
  56879         SOC_REG_FLAG_RO,
  56880         0,
  56881         1,
  56882         soc_OLP_GTIMER_TRIGGER_BCM88675_B0r_fields,
  56883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56884         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56885         -1,
  56886         -1,
  56887     },
  56888 #endif /* chips */
  56889 
  56890 #if defined(BCM_88680_A0)
  56891     { /* SOC_REG_INT_OLP_GTIMER_TRIGGER_BCM88680_A0r */
  56892         soc_block_list[42],
  56893         soc_genreg,
  56894         1,
  56895         0,
  56896         0x89,
  56897         SOC_REG_FLAG_RO,
  56898         0,
  56899         1,
  56900         soc_OLP_GTIMER_TRIGGER_BCM88680_A0r_fields,
  56901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56902         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56903         -1,
  56904         -1,
  56905     },
  56906 #endif /* chips */
  56907 
  56908 #if defined(BCM_88675_A0)
  56909     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFOr */
  56910         soc_block_list[42],
  56911         soc_genreg,
  56912         1,
  56913         0,
  56914         0x131,
  56915         SOC_REG_FLAG_ABOVE_64_BITS |
  56916                           SOC_REG_FLAG_RO |
  56917                           SOC_REG_FLAG_SIGNAL,
  56918         0,
  56919         1,
  56920         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFOr_fields,
  56921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56922         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56923         -1,
  56924         -1,
  56925     },
  56926 #endif /* chips */
  56927 
  56928 #if defined(BCM_88270_A0)
  56929     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88270_A0r */
  56930         soc_block_list[42],
  56931         soc_genreg,
  56932         1,
  56933         0,
  56934         0x131,
  56935         SOC_REG_FLAG_ABOVE_64_BITS |
  56936                           SOC_REG_FLAG_RO |
  56937                           SOC_REG_FLAG_SIGNAL,
  56938         0,
  56939         1,
  56940         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88270_A0r_fields,
  56941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56942         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56943         -1,
  56944         -1,
  56945     },
  56946 #endif /* chips */
  56947 
  56948 #if defined(BCM_88375_A0)
  56949     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88375_A0r */
  56950         soc_block_list[42],
  56951         soc_genreg,
  56952         1,
  56953         0,
  56954         0x131,
  56955         SOC_REG_FLAG_ABOVE_64_BITS |
  56956                           SOC_REG_FLAG_RO |
  56957                           SOC_REG_FLAG_SIGNAL,
  56958         0,
  56959         1,
  56960         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88375_A0r_fields,
  56961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56962         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56963         -1,
  56964         -1,
  56965     },
  56966 #endif /* chips */
  56967 
  56968 #if defined(BCM_88375_B0)
  56969     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88375_B0r */
  56970         soc_block_list[42],
  56971         soc_genreg,
  56972         1,
  56973         0,
  56974         0x131,
  56975         SOC_REG_FLAG_ABOVE_64_BITS |
  56976                           SOC_REG_FLAG_RO |
  56977                           SOC_REG_FLAG_SIGNAL,
  56978         0,
  56979         1,
  56980         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88375_B0r_fields,
  56981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56982         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56983         -1,
  56984         -1,
  56985     },
  56986 #endif /* chips */
  56987 
  56988 #if defined(BCM_88470_A0)
  56989     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88470_A0r */
  56990         soc_block_list[42],
  56991         soc_genreg,
  56992         1,
  56993         0,
  56994         0x131,
  56995         SOC_REG_FLAG_ABOVE_64_BITS |
  56996                           SOC_REG_FLAG_RO |
  56997                           SOC_REG_FLAG_SIGNAL,
  56998         0,
  56999         1,
  57000         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88470_A0r_fields,
  57001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57002         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57003         -1,
  57004         -1,
  57005     },
  57006 #endif /* chips */
  57007 
  57008 #if defined(BCM_88470_B0)
  57009     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88470_B0r */
  57010         soc_block_list[42],
  57011         soc_genreg,
  57012         1,
  57013         0,
  57014         0x131,
  57015         SOC_REG_FLAG_ABOVE_64_BITS |
  57016                           SOC_REG_FLAG_RO |
  57017                           SOC_REG_FLAG_SIGNAL,
  57018         0,
  57019         1,
  57020         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88470_B0r_fields,
  57021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57022         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57023         -1,
  57024         -1,
  57025     },
  57026 #endif /* chips */
  57027 
  57028 #if defined(BCM_88675_B0)
  57029     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88675_B0r */
  57030         soc_block_list[42],
  57031         soc_genreg,
  57032         1,
  57033         0,
  57034         0x131,
  57035         SOC_REG_FLAG_ABOVE_64_BITS |
  57036                           SOC_REG_FLAG_RO |
  57037                           SOC_REG_FLAG_SIGNAL,
  57038         0,
  57039         1,
  57040         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88675_B0r_fields,
  57041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57042         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57043         -1,
  57044         -1,
  57045     },
  57046 #endif /* chips */
  57047 
  57048 #if defined(BCM_88680_A0)
  57049     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88680_A0r */
  57050         soc_block_list[42],
  57051         soc_genreg,
  57052         1,
  57053         0,
  57054         0x131,
  57055         SOC_REG_FLAG_ABOVE_64_BITS |
  57056                           SOC_REG_FLAG_RO |
  57057                           SOC_REG_FLAG_SIGNAL,
  57058         0,
  57059         1,
  57060         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88680_A0r_fields,
  57061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57062         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57063         -1,
  57064         -1,
  57065     },
  57066 #endif /* chips */
  57067 
  57068 #if defined(BCM_88690_A0)
  57069     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88690_A0r */
  57070         soc_block_list[42],
  57071         soc_genreg,
  57072         1,
  57073         0,
  57074         0x153,
  57075         SOC_REG_FLAG_ABOVE_64_BITS |
  57076                           SOC_REG_FLAG_RO |
  57077                           SOC_REG_FLAG_SIGNAL,
  57078         SOC_REG_FLAG_INIT_ON_READ,
  57079         1,
  57080         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88690_A0r_fields,
  57081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57082         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57083         -1,
  57084         -1,
  57085     },
  57086 #endif /* chips */
  57087 
  57088 #if defined(BCM_88690_B0)
  57089     { /* SOC_REG_INT_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88690_B0r */
  57090         soc_block_list[42],
  57091         soc_genreg,
  57092         1,
  57093         0,
  57094         0x153,
  57095         SOC_REG_FLAG_ABOVE_64_BITS |
  57096                           SOC_REG_FLAG_RO |
  57097                           SOC_REG_FLAG_SIGNAL,
  57098         SOC_REG_FLAG_INIT_ON_READ,
  57099         1,
  57100         soc_OLP_HEAD_OF_CPU_DSPG_CMD_FIFO_BCM88690_B0r_fields,
  57101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57102         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57103         -1,
  57104         -1,
  57105     },
  57106 #endif /* chips */
  57107 
  57108 #if defined(BCM_88650_A0)
  57109     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTERr */
  57110         soc_block_list[42],
  57111         soc_genreg,
  57112         1,
  57113         0,
  57114         0x127,
  57115         SOC_REG_FLAG_RO,
  57116         0,
  57117         2,
  57118         soc_OLP_INCOMING_BAD_PACKET_COUNTERr_fields,
  57119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57120         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57121         -1,
  57122         -1,
  57123     },
  57124 #endif /* chips */
  57125 
  57126 #if defined(BCM_88270_A0)
  57127     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88270_A0r */
  57128         soc_block_list[42],
  57129         soc_genreg,
  57130         1,
  57131         0,
  57132         0x12e,
  57133         SOC_REG_FLAG_RO,
  57134         0,
  57135         2,
  57136         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88270_A0r_fields,
  57137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57138         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57139         -1,
  57140         -1,
  57141     },
  57142 #endif /* chips */
  57143 
  57144 #if defined(BCM_88375_A0)
  57145     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88375_A0r */
  57146         soc_block_list[42],
  57147         soc_genreg,
  57148         1,
  57149         0,
  57150         0x12e,
  57151         SOC_REG_FLAG_RO,
  57152         0,
  57153         2,
  57154         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88375_A0r_fields,
  57155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57157         -1,
  57158         -1,
  57159     },
  57160 #endif /* chips */
  57161 
  57162 #if defined(BCM_88375_B0)
  57163     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88375_B0r */
  57164         soc_block_list[42],
  57165         soc_genreg,
  57166         1,
  57167         0,
  57168         0x12e,
  57169         SOC_REG_FLAG_RO,
  57170         0,
  57171         2,
  57172         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88375_B0r_fields,
  57173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57174         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57175         -1,
  57176         -1,
  57177     },
  57178 #endif /* chips */
  57179 
  57180 #if defined(BCM_88470_A0)
  57181     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88470_A0r */
  57182         soc_block_list[42],
  57183         soc_genreg,
  57184         1,
  57185         0,
  57186         0x12e,
  57187         SOC_REG_FLAG_RO,
  57188         0,
  57189         2,
  57190         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88470_A0r_fields,
  57191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57192         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57193         -1,
  57194         -1,
  57195     },
  57196 #endif /* chips */
  57197 
  57198 #if defined(BCM_88470_B0)
  57199     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88470_B0r */
  57200         soc_block_list[42],
  57201         soc_genreg,
  57202         1,
  57203         0,
  57204         0x12e,
  57205         SOC_REG_FLAG_RO,
  57206         0,
  57207         2,
  57208         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88470_B0r_fields,
  57209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57210         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57211         -1,
  57212         -1,
  57213     },
  57214 #endif /* chips */
  57215 
  57216 #if defined(BCM_88650_B0)
  57217     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88650_B0r */
  57218         soc_block_list[42],
  57219         soc_genreg,
  57220         1,
  57221         0,
  57222         0x127,
  57223         SOC_REG_FLAG_RO,
  57224         0,
  57225         2,
  57226         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88650_B0r_fields,
  57227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57228         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57229         -1,
  57230         -1,
  57231     },
  57232 #endif /* chips */
  57233 
  57234 #if defined(BCM_88660_A0)
  57235     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88660_A0r */
  57236         soc_block_list[42],
  57237         soc_genreg,
  57238         1,
  57239         0,
  57240         0x127,
  57241         SOC_REG_FLAG_RO,
  57242         0,
  57243         2,
  57244         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88660_A0r_fields,
  57245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57246         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57247         -1,
  57248         -1,
  57249     },
  57250 #endif /* chips */
  57251 
  57252 #if defined(BCM_88675_A0)
  57253     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88675_A0r */
  57254         soc_block_list[42],
  57255         soc_genreg,
  57256         1,
  57257         0,
  57258         0x12e,
  57259         SOC_REG_FLAG_RO,
  57260         0,
  57261         2,
  57262         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88675_A0r_fields,
  57263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57264         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57265         -1,
  57266         -1,
  57267     },
  57268 #endif /* chips */
  57269 
  57270 #if defined(BCM_88675_B0)
  57271     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88675_B0r */
  57272         soc_block_list[42],
  57273         soc_genreg,
  57274         1,
  57275         0,
  57276         0x12e,
  57277         SOC_REG_FLAG_RO,
  57278         0,
  57279         2,
  57280         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88675_B0r_fields,
  57281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57282         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57283         -1,
  57284         -1,
  57285     },
  57286 #endif /* chips */
  57287 
  57288 #if defined(BCM_88680_A0)
  57289     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88680_A0r */
  57290         soc_block_list[42],
  57291         soc_genreg,
  57292         1,
  57293         0,
  57294         0x12e,
  57295         SOC_REG_FLAG_RO,
  57296         0,
  57297         2,
  57298         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88680_A0r_fields,
  57299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57300         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57301         -1,
  57302         -1,
  57303     },
  57304 #endif /* chips */
  57305 
  57306 #if defined(BCM_88690_A0)
  57307     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88690_A0r */
  57308         soc_block_list[42],
  57309         soc_genreg,
  57310         1,
  57311         0,
  57312         0x150,
  57313         SOC_REG_FLAG_RO,
  57314         SOC_REG_FLAG_COUNTER_FEILDS,
  57315         2,
  57316         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88690_A0r_fields,
  57317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57318         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57319         -1,
  57320         -1,
  57321     },
  57322 #endif /* chips */
  57323 
  57324 #if defined(BCM_88690_B0)
  57325     { /* SOC_REG_INT_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88690_B0r */
  57326         soc_block_list[42],
  57327         soc_genreg,
  57328         1,
  57329         0,
  57330         0x150,
  57331         SOC_REG_FLAG_RO,
  57332         SOC_REG_FLAG_COUNTER_FEILDS,
  57333         2,
  57334         soc_OLP_INCOMING_BAD_PACKET_COUNTER_BCM88690_B0r_fields,
  57335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57336         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57337         -1,
  57338         -1,
  57339     },
  57340 #endif /* chips */
  57341 
  57342 #if defined(BCM_88650_A0)
  57343     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTERr */
  57344         soc_block_list[42],
  57345         soc_genreg,
  57346         1,
  57347         0,
  57348         0x11f,
  57349         SOC_REG_FLAG_RO,
  57350         0,
  57351         1,
  57352         soc_OLP_INCOMING_EVENT_COUNTERr_fields,
  57353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57354         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57355         -1,
  57356         -1,
  57357     },
  57358 #endif /* chips */
  57359 
  57360 #if defined(BCM_88270_A0)
  57361     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88270_A0r */
  57362         soc_block_list[42],
  57363         soc_genreg,
  57364         1,
  57365         0,
  57366         0x125,
  57367         SOC_REG_FLAG_RO |
  57368                           SOC_REG_FLAG_SIGNAL,
  57369         0,
  57370         1,
  57371         soc_OLP_INCOMING_EVENT_COUNTER_BCM88270_A0r_fields,
  57372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57373         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57374         -1,
  57375         -1,
  57376     },
  57377 #endif /* chips */
  57378 
  57379 #if defined(BCM_88375_A0)
  57380     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88375_A0r */
  57381         soc_block_list[42],
  57382         soc_genreg,
  57383         1,
  57384         0,
  57385         0x125,
  57386         SOC_REG_FLAG_RO |
  57387                           SOC_REG_FLAG_SIGNAL,
  57388         0,
  57389         1,
  57390         soc_OLP_INCOMING_EVENT_COUNTER_BCM88375_A0r_fields,
  57391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57392         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57393         -1,
  57394         -1,
  57395     },
  57396 #endif /* chips */
  57397 
  57398 #if defined(BCM_88375_B0)
  57399     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88375_B0r */
  57400         soc_block_list[42],
  57401         soc_genreg,
  57402         1,
  57403         0,
  57404         0x125,
  57405         SOC_REG_FLAG_RO |
  57406                           SOC_REG_FLAG_SIGNAL,
  57407         0,
  57408         1,
  57409         soc_OLP_INCOMING_EVENT_COUNTER_BCM88375_B0r_fields,
  57410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57411         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57412         -1,
  57413         -1,
  57414     },
  57415 #endif /* chips */
  57416 
  57417 #if defined(BCM_88470_A0)
  57418     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88470_A0r */
  57419         soc_block_list[42],
  57420         soc_genreg,
  57421         1,
  57422         0,
  57423         0x125,
  57424         SOC_REG_FLAG_RO |
  57425                           SOC_REG_FLAG_SIGNAL,
  57426         0,
  57427         1,
  57428         soc_OLP_INCOMING_EVENT_COUNTER_BCM88470_A0r_fields,
  57429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57430         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57431         -1,
  57432         -1,
  57433     },
  57434 #endif /* chips */
  57435 
  57436 #if defined(BCM_88470_B0)
  57437     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88470_B0r */
  57438         soc_block_list[42],
  57439         soc_genreg,
  57440         1,
  57441         0,
  57442         0x125,
  57443         SOC_REG_FLAG_RO |
  57444                           SOC_REG_FLAG_SIGNAL,
  57445         0,
  57446         1,
  57447         soc_OLP_INCOMING_EVENT_COUNTER_BCM88470_B0r_fields,
  57448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57449         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57450         -1,
  57451         -1,
  57452     },
  57453 #endif /* chips */
  57454 
  57455 #if defined(BCM_88650_B0)
  57456     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88650_B0r */
  57457         soc_block_list[42],
  57458         soc_genreg,
  57459         1,
  57460         0,
  57461         0x11f,
  57462         SOC_REG_FLAG_RO,
  57463         0,
  57464         1,
  57465         soc_OLP_INCOMING_EVENT_COUNTER_BCM88650_B0r_fields,
  57466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57467         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57468         -1,
  57469         -1,
  57470     },
  57471 #endif /* chips */
  57472 
  57473 #if defined(BCM_88660_A0)
  57474     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88660_A0r */
  57475         soc_block_list[42],
  57476         soc_genreg,
  57477         1,
  57478         0,
  57479         0x11f,
  57480         SOC_REG_FLAG_RO,
  57481         0,
  57482         1,
  57483         soc_OLP_INCOMING_EVENT_COUNTER_BCM88660_A0r_fields,
  57484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57485         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57486         -1,
  57487         -1,
  57488     },
  57489 #endif /* chips */
  57490 
  57491 #if defined(BCM_88675_A0)
  57492     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88675_A0r */
  57493         soc_block_list[42],
  57494         soc_genreg,
  57495         1,
  57496         0,
  57497         0x125,
  57498         SOC_REG_FLAG_RO |
  57499                           SOC_REG_FLAG_SIGNAL,
  57500         0,
  57501         1,
  57502         soc_OLP_INCOMING_EVENT_COUNTER_BCM88675_A0r_fields,
  57503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57504         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57505         -1,
  57506         -1,
  57507     },
  57508 #endif /* chips */
  57509 
  57510 #if defined(BCM_88675_B0)
  57511     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88675_B0r */
  57512         soc_block_list[42],
  57513         soc_genreg,
  57514         1,
  57515         0,
  57516         0x125,
  57517         SOC_REG_FLAG_RO |
  57518                           SOC_REG_FLAG_SIGNAL,
  57519         0,
  57520         1,
  57521         soc_OLP_INCOMING_EVENT_COUNTER_BCM88675_B0r_fields,
  57522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57523         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57524         -1,
  57525         -1,
  57526     },
  57527 #endif /* chips */
  57528 
  57529 #if defined(BCM_88680_A0)
  57530     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88680_A0r */
  57531         soc_block_list[42],
  57532         soc_genreg,
  57533         1,
  57534         0,
  57535         0x125,
  57536         SOC_REG_FLAG_RO |
  57537                           SOC_REG_FLAG_SIGNAL,
  57538         0,
  57539         1,
  57540         soc_OLP_INCOMING_EVENT_COUNTER_BCM88680_A0r_fields,
  57541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57542         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57543         -1,
  57544         -1,
  57545     },
  57546 #endif /* chips */
  57547 
  57548 #if defined(BCM_88690_A0)
  57549     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88690_A0r */
  57550         soc_block_list[42],
  57551         soc_genreg,
  57552         1,
  57553         0,
  57554         0x147,
  57555         SOC_REG_FLAG_RO,
  57556         SOC_REG_FLAG_COUNTER_FEILDS,
  57557         1,
  57558         soc_OLP_INCOMING_EVENT_COUNTER_BCM88690_A0r_fields,
  57559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57560         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57561         -1,
  57562         -1,
  57563     },
  57564 #endif /* chips */
  57565 
  57566 #if defined(BCM_88690_B0)
  57567     { /* SOC_REG_INT_OLP_INCOMING_EVENT_COUNTER_BCM88690_B0r */
  57568         soc_block_list[42],
  57569         soc_genreg,
  57570         1,
  57571         0,
  57572         0x147,
  57573         SOC_REG_FLAG_RO,
  57574         SOC_REG_FLAG_COUNTER_FEILDS,
  57575         1,
  57576         soc_OLP_INCOMING_EVENT_COUNTER_BCM88690_B0r_fields,
  57577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57578         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57579         -1,
  57580         -1,
  57581     },
  57582 #endif /* chips */
  57583 
  57584 #if defined(BCM_88650_A0)
  57585     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTERr */
  57586         soc_block_list[42],
  57587         soc_genreg,
  57588         1,
  57589         0,
  57590         0x128,
  57591         SOC_REG_FLAG_RO,
  57592         0,
  57593         1,
  57594         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTERr_fields,
  57595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57596         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57597         -1,
  57598         -1,
  57599     },
  57600 #endif /* chips */
  57601 
  57602 #if defined(BCM_88270_A0)
  57603     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88270_A0r */
  57604         soc_block_list[42],
  57605         soc_genreg,
  57606         1,
  57607         0,
  57608         0x12f,
  57609         SOC_REG_FLAG_RO |
  57610                           SOC_REG_FLAG_SIGNAL,
  57611         0,
  57612         1,
  57613         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88270_A0r_fields,
  57614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57615         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57616         -1,
  57617         -1,
  57618     },
  57619 #endif /* chips */
  57620 
  57621 #if defined(BCM_88375_A0)
  57622     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88375_A0r */
  57623         soc_block_list[42],
  57624         soc_genreg,
  57625         1,
  57626         0,
  57627         0x12f,
  57628         SOC_REG_FLAG_RO |
  57629                           SOC_REG_FLAG_SIGNAL,
  57630         0,
  57631         1,
  57632         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88375_A0r_fields,
  57633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57634         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57635         -1,
  57636         -1,
  57637     },
  57638 #endif /* chips */
  57639 
  57640 #if defined(BCM_88375_B0)
  57641     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88375_B0r */
  57642         soc_block_list[42],
  57643         soc_genreg,
  57644         1,
  57645         0,
  57646         0x12f,
  57647         SOC_REG_FLAG_RO |
  57648                           SOC_REG_FLAG_SIGNAL,
  57649         0,
  57650         1,
  57651         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88375_B0r_fields,
  57652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57653         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57654         -1,
  57655         -1,
  57656     },
  57657 #endif /* chips */
  57658 
  57659 #if defined(BCM_88470_A0)
  57660     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88470_A0r */
  57661         soc_block_list[42],
  57662         soc_genreg,
  57663         1,
  57664         0,
  57665         0x12f,
  57666         SOC_REG_FLAG_RO |
  57667                           SOC_REG_FLAG_SIGNAL,
  57668         0,
  57669         1,
  57670         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88470_A0r_fields,
  57671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57672         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57673         -1,
  57674         -1,
  57675     },
  57676 #endif /* chips */
  57677 
  57678 #if defined(BCM_88470_B0)
  57679     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88470_B0r */
  57680         soc_block_list[42],
  57681         soc_genreg,
  57682         1,
  57683         0,
  57684         0x12f,
  57685         SOC_REG_FLAG_RO |
  57686                           SOC_REG_FLAG_SIGNAL,
  57687         0,
  57688         1,
  57689         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88470_B0r_fields,
  57690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57691         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57692         -1,
  57693         -1,
  57694     },
  57695 #endif /* chips */
  57696 
  57697 #if defined(BCM_88650_B0)
  57698     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88650_B0r */
  57699         soc_block_list[42],
  57700         soc_genreg,
  57701         1,
  57702         0,
  57703         0x128,
  57704         SOC_REG_FLAG_RO,
  57705         0,
  57706         1,
  57707         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88650_B0r_fields,
  57708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57709         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57710         -1,
  57711         -1,
  57712     },
  57713 #endif /* chips */
  57714 
  57715 #if defined(BCM_88660_A0)
  57716     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88660_A0r */
  57717         soc_block_list[42],
  57718         soc_genreg,
  57719         1,
  57720         0,
  57721         0x128,
  57722         SOC_REG_FLAG_RO,
  57723         0,
  57724         1,
  57725         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88660_A0r_fields,
  57726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57727         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57728         -1,
  57729         -1,
  57730     },
  57731 #endif /* chips */
  57732 
  57733 #if defined(BCM_88675_A0)
  57734     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88675_A0r */
  57735         soc_block_list[42],
  57736         soc_genreg,
  57737         1,
  57738         0,
  57739         0x12f,
  57740         SOC_REG_FLAG_RO |
  57741                           SOC_REG_FLAG_SIGNAL,
  57742         0,
  57743         1,
  57744         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88675_A0r_fields,
  57745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57746         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57747         -1,
  57748         -1,
  57749     },
  57750 #endif /* chips */
  57751 
  57752 #if defined(BCM_88675_B0)
  57753     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88675_B0r */
  57754         soc_block_list[42],
  57755         soc_genreg,
  57756         1,
  57757         0,
  57758         0x12f,
  57759         SOC_REG_FLAG_RO |
  57760                           SOC_REG_FLAG_SIGNAL,
  57761         0,
  57762         1,
  57763         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88675_B0r_fields,
  57764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57765         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57766         -1,
  57767         -1,
  57768     },
  57769 #endif /* chips */
  57770 
  57771 #if defined(BCM_88680_A0)
  57772     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88680_A0r */
  57773         soc_block_list[42],
  57774         soc_genreg,
  57775         1,
  57776         0,
  57777         0x12f,
  57778         SOC_REG_FLAG_RO |
  57779                           SOC_REG_FLAG_SIGNAL,
  57780         0,
  57781         1,
  57782         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88680_A0r_fields,
  57783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57784         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57785         -1,
  57786         -1,
  57787     },
  57788 #endif /* chips */
  57789 
  57790 #if defined(BCM_88690_A0)
  57791     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88690_A0r */
  57792         soc_block_list[42],
  57793         soc_genreg,
  57794         1,
  57795         0,
  57796         0x151,
  57797         SOC_REG_FLAG_RO,
  57798         SOC_REG_FLAG_COUNTER_FEILDS,
  57799         1,
  57800         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88690_A0r_fields,
  57801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57802         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57803         -1,
  57804         -1,
  57805     },
  57806 #endif /* chips */
  57807 
  57808 #if defined(BCM_88690_B0)
  57809     { /* SOC_REG_INT_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88690_B0r */
  57810         soc_block_list[42],
  57811         soc_genreg,
  57812         1,
  57813         0,
  57814         0x151,
  57815         SOC_REG_FLAG_RO,
  57816         SOC_REG_FLAG_COUNTER_FEILDS,
  57817         1,
  57818         soc_OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER_BCM88690_B0r_fields,
  57819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57820         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57821         -1,
  57822         -1,
  57823     },
  57824 #endif /* chips */
  57825 
  57826 #if defined(BCM_88650_A0)
  57827     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTERr */
  57828         soc_block_list[42],
  57829         soc_genreg,
  57830         1,
  57831         0,
  57832         0x126,
  57833         SOC_REG_FLAG_RO,
  57834         0,
  57835         1,
  57836         soc_OLP_INCOMING_VALID_PACKET_COUNTERr_fields,
  57837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57838         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57839         -1,
  57840         -1,
  57841     },
  57842 #endif /* chips */
  57843 
  57844 #if defined(BCM_88270_A0)
  57845     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88270_A0r */
  57846         soc_block_list[42],
  57847         soc_genreg,
  57848         1,
  57849         0,
  57850         0x12d,
  57851         SOC_REG_FLAG_RO |
  57852                           SOC_REG_FLAG_SIGNAL,
  57853         0,
  57854         1,
  57855         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88270_A0r_fields,
  57856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57857         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57858         -1,
  57859         -1,
  57860     },
  57861 #endif /* chips */
  57862 
  57863 #if defined(BCM_88375_A0)
  57864     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88375_A0r */
  57865         soc_block_list[42],
  57866         soc_genreg,
  57867         1,
  57868         0,
  57869         0x12d,
  57870         SOC_REG_FLAG_RO |
  57871                           SOC_REG_FLAG_SIGNAL,
  57872         0,
  57873         1,
  57874         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88375_A0r_fields,
  57875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57876         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57877         -1,
  57878         -1,
  57879     },
  57880 #endif /* chips */
  57881 
  57882 #if defined(BCM_88375_B0)
  57883     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88375_B0r */
  57884         soc_block_list[42],
  57885         soc_genreg,
  57886         1,
  57887         0,
  57888         0x12d,
  57889         SOC_REG_FLAG_RO |
  57890                           SOC_REG_FLAG_SIGNAL,
  57891         0,
  57892         1,
  57893         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88375_B0r_fields,
  57894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57895         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57896         -1,
  57897         -1,
  57898     },
  57899 #endif /* chips */
  57900 
  57901 #if defined(BCM_88470_A0)
  57902     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88470_A0r */
  57903         soc_block_list[42],
  57904         soc_genreg,
  57905         1,
  57906         0,
  57907         0x12d,
  57908         SOC_REG_FLAG_RO |
  57909                           SOC_REG_FLAG_SIGNAL,
  57910         0,
  57911         1,
  57912         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88470_A0r_fields,
  57913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57914         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57915         -1,
  57916         -1,
  57917     },
  57918 #endif /* chips */
  57919 
  57920 #if defined(BCM_88470_B0)
  57921     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88470_B0r */
  57922         soc_block_list[42],
  57923         soc_genreg,
  57924         1,
  57925         0,
  57926         0x12d,
  57927         SOC_REG_FLAG_RO |
  57928                           SOC_REG_FLAG_SIGNAL,
  57929         0,
  57930         1,
  57931         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88470_B0r_fields,
  57932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57933         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57934         -1,
  57935         -1,
  57936     },
  57937 #endif /* chips */
  57938 
  57939 #if defined(BCM_88650_B0)
  57940     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88650_B0r */
  57941         soc_block_list[42],
  57942         soc_genreg,
  57943         1,
  57944         0,
  57945         0x126,
  57946         SOC_REG_FLAG_RO,
  57947         0,
  57948         1,
  57949         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88650_B0r_fields,
  57950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57951         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57952         -1,
  57953         -1,
  57954     },
  57955 #endif /* chips */
  57956 
  57957 #if defined(BCM_88660_A0)
  57958     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88660_A0r */
  57959         soc_block_list[42],
  57960         soc_genreg,
  57961         1,
  57962         0,
  57963         0x126,
  57964         SOC_REG_FLAG_RO,
  57965         0,
  57966         1,
  57967         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88660_A0r_fields,
  57968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57969         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57970         -1,
  57971         -1,
  57972     },
  57973 #endif /* chips */
  57974 
  57975 #if defined(BCM_88675_A0)
  57976     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88675_A0r */
  57977         soc_block_list[42],
  57978         soc_genreg,
  57979         1,
  57980         0,
  57981         0x12d,
  57982         SOC_REG_FLAG_RO |
  57983                           SOC_REG_FLAG_SIGNAL,
  57984         0,
  57985         1,
  57986         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88675_A0r_fields,
  57987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57988         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  57989         -1,
  57990         -1,
  57991     },
  57992 #endif /* chips */
  57993 
  57994 #if defined(BCM_88675_B0)
  57995     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88675_B0r */
  57996         soc_block_list[42],
  57997         soc_genreg,
  57998         1,
  57999         0,
  58000         0x12d,
  58001         SOC_REG_FLAG_RO |
  58002                           SOC_REG_FLAG_SIGNAL,
  58003         0,
  58004         1,
  58005         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88675_B0r_fields,
  58006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58007         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  58008         -1,
  58009         -1,
  58010     },
  58011 #endif /* chips */
  58012 
  58013 #if defined(BCM_88680_A0)
  58014     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88680_A0r */
  58015         soc_block_list[42],
  58016         soc_genreg,
  58017         1,
  58018         0,
  58019         0x12d,
  58020         SOC_REG_FLAG_RO |
  58021                           SOC_REG_FLAG_SIGNAL,
  58022         0,
  58023         1,
  58024         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88680_A0r_fields,
  58025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58026         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  58027         -1,
  58028         -1,
  58029     },
  58030 #endif /* chips */
  58031 
  58032 #if defined(BCM_88690_A0)
  58033     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88690_A0r */
  58034         soc_block_list[42],
  58035         soc_genreg,
  58036         1,
  58037         0,
  58038         0x14f,
  58039         SOC_REG_FLAG_RO,
  58040         SOC_REG_FLAG_COUNTER_FEILDS,
  58041         1,
  58042         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88690_A0r_fields,
  58043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58044         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  58045         -1,
  58046         -1,
  58047     },
  58048 #endif /* chips */
  58049 
  58050 #if defined(BCM_88690_B0)
  58051     { /* SOC_REG_INT_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88690_B0r */
  58052         soc_block_list[42],
  58053         soc_genreg,
  58054         1,
  58055         0,
  58056         0x14f,
  58057         SOC_REG_FLAG_RO,
  58058         SOC_REG_FLAG_COUNTER_FEILDS,
  58059         1,
  58060         soc_OLP_INCOMING_VALID_PACKET_COUNTER_BCM88690_B0r_fields,
  58061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58062         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  58063         -1,
  58064         -1,
  58065     },
  58066 #endif /* chips */
  58067 
  58068 #if defined(BCM_88650_A0)
  58069     { /* SOC_REG_INT_OLP_INDIRECT_COMMANDr */
  58070         soc_block_list[42],
  58071         soc_genreg,
  58072         1,
  58073         0,
  58074         0x80,
  58075         0,
  58076         0,
  58077         5,
  58078         soc_OLP_INDIRECT_COMMANDr_fields,
  58079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58080         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58081         -1,
  58082         -1,
  58083     },
  58084 #endif /* chips */
  58085 
  58086 #if defined(BCM_88650_A0)
  58087     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESSr */
  58088         soc_block_list[42],
  58089         soc_genreg,
  58090         1,
  58091         0,
  58092         0x81,
  58093         0,
  58094         0,
  58095         2,
  58096         soc_OLP_INDIRECT_COMMAND_ADDRESSr_fields,
  58097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58098         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58099         -1,
  58100         -1,
  58101     },
  58102 #endif /* chips */
  58103 
  58104 #if defined(BCM_88270_A0)
  58105     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88270_A0r */
  58106         soc_block_list[42],
  58107         soc_genreg,
  58108         1,
  58109         0,
  58110         0x81,
  58111         0,
  58112         0,
  58113         2,
  58114         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88270_A0r_fields,
  58115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58116         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58117         -1,
  58118         -1,
  58119     },
  58120 #endif /* chips */
  58121 
  58122 #if defined(BCM_88375_A0)
  58123     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88375_A0r */
  58124         soc_block_list[42],
  58125         soc_genreg,
  58126         1,
  58127         0,
  58128         0x81,
  58129         0,
  58130         0,
  58131         2,
  58132         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88375_A0r_fields,
  58133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58134         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58135         -1,
  58136         -1,
  58137     },
  58138 #endif /* chips */
  58139 
  58140 #if defined(BCM_88375_B0)
  58141     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88375_B0r */
  58142         soc_block_list[42],
  58143         soc_genreg,
  58144         1,
  58145         0,
  58146         0x81,
  58147         0,
  58148         0,
  58149         2,
  58150         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88375_B0r_fields,
  58151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58152         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58153         -1,
  58154         -1,
  58155     },
  58156 #endif /* chips */
  58157 
  58158 #if defined(BCM_88470_A0)
  58159     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88470_A0r */
  58160         soc_block_list[42],
  58161         soc_genreg,
  58162         1,
  58163         0,
  58164         0x81,
  58165         0,
  58166         0,
  58167         2,
  58168         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88470_A0r_fields,
  58169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58170         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58171         -1,
  58172         -1,
  58173     },
  58174 #endif /* chips */
  58175 
  58176 #if defined(BCM_88470_B0)
  58177     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88470_B0r */
  58178         soc_block_list[42],
  58179         soc_genreg,
  58180         1,
  58181         0,
  58182         0x81,
  58183         0,
  58184         0,
  58185         2,
  58186         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88470_B0r_fields,
  58187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58188         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58189         -1,
  58190         -1,
  58191     },
  58192 #endif /* chips */
  58193 
  58194 #if defined(BCM_88650_B0)
  58195     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88650_B0r */
  58196         soc_block_list[42],
  58197         soc_genreg,
  58198         1,
  58199         0,
  58200         0x81,
  58201         0,
  58202         0,
  58203         2,
  58204         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88650_B0r_fields,
  58205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58206         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58207         -1,
  58208         -1,
  58209     },
  58210 #endif /* chips */
  58211 
  58212 #if defined(BCM_88660_A0)
  58213     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88660_A0r */
  58214         soc_block_list[42],
  58215         soc_genreg,
  58216         1,
  58217         0,
  58218         0x81,
  58219         0,
  58220         0,
  58221         2,
  58222         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88660_A0r_fields,
  58223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58224         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58225         -1,
  58226         -1,
  58227     },
  58228 #endif /* chips */
  58229 
  58230 #if defined(BCM_88675_A0)
  58231     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88675_A0r */
  58232         soc_block_list[42],
  58233         soc_genreg,
  58234         1,
  58235         0,
  58236         0x81,
  58237         0,
  58238         0,
  58239         2,
  58240         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88675_A0r_fields,
  58241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58242         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58243         -1,
  58244         -1,
  58245     },
  58246 #endif /* chips */
  58247 
  58248 #if defined(BCM_88675_B0)
  58249     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88675_B0r */
  58250         soc_block_list[42],
  58251         soc_genreg,
  58252         1,
  58253         0,
  58254         0x81,
  58255         0,
  58256         0,
  58257         2,
  58258         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88675_B0r_fields,
  58259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58260         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58261         -1,
  58262         -1,
  58263     },
  58264 #endif /* chips */
  58265 
  58266 #if defined(BCM_88680_A0)
  58267     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r */
  58268         soc_block_list[42],
  58269         soc_genreg,
  58270         1,
  58271         0,
  58272         0x81,
  58273         0,
  58274         0,
  58275         2,
  58276         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r_fields,
  58277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58278         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58279         -1,
  58280         -1,
  58281     },
  58282 #endif /* chips */
  58283 
  58284 #if defined(BCM_88690_A0)
  58285     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r */
  58286         soc_block_list[42],
  58287         soc_genreg,
  58288         1,
  58289         0,
  58290         0x81,
  58291         0,
  58292         0,
  58293         2,
  58294         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r_fields,
  58295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58296         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58297         -1,
  58298         -1,
  58299     },
  58300 #endif /* chips */
  58301 
  58302 #if defined(BCM_88690_B0)
  58303     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r */
  58304         soc_block_list[42],
  58305         soc_genreg,
  58306         1,
  58307         0,
  58308         0x81,
  58309         0,
  58310         0,
  58311         2,
  58312         soc_OLP_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r_fields,
  58313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58314         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58315         -1,
  58316         -1,
  58317     },
  58318 #endif /* chips */
  58319 
  58320 #if defined(BCM_88270_A0)
  58321     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88270_A0r */
  58322         soc_block_list[42],
  58323         soc_genreg,
  58324         1,
  58325         0,
  58326         0x80,
  58327         0,
  58328         0,
  58329         5,
  58330         soc_OLP_INDIRECT_COMMAND_BCM88270_A0r_fields,
  58331         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  58332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58333         -1,
  58334         -1,
  58335     },
  58336 #endif /* chips */
  58337 
  58338 #if defined(BCM_88375_A0)
  58339     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88375_A0r */
  58340         soc_block_list[42],
  58341         soc_genreg,
  58342         1,
  58343         0,
  58344         0x80,
  58345         0,
  58346         0,
  58347         5,
  58348         soc_OLP_INDIRECT_COMMAND_BCM88375_A0r_fields,
  58349         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  58350         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58351         -1,
  58352         -1,
  58353     },
  58354 #endif /* chips */
  58355 
  58356 #if defined(BCM_88375_B0)
  58357     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88375_B0r */
  58358         soc_block_list[42],
  58359         soc_genreg,
  58360         1,
  58361         0,
  58362         0x80,
  58363         0,
  58364         0,
  58365         5,
  58366         soc_OLP_INDIRECT_COMMAND_BCM88375_B0r_fields,
  58367         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  58368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58369         -1,
  58370         -1,
  58371     },
  58372 #endif /* chips */
  58373 
  58374 #if defined(BCM_88470_A0)
  58375     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88470_A0r */
  58376         soc_block_list[42],
  58377         soc_genreg,
  58378         1,
  58379         0,
  58380         0x80,
  58381         0,
  58382         0,
  58383         5,
  58384         soc_OLP_INDIRECT_COMMAND_BCM88470_A0r_fields,
  58385         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  58386         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58387         -1,
  58388         -1,
  58389     },
  58390 #endif /* chips */
  58391 
  58392 #if defined(BCM_88470_B0)
  58393     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88470_B0r */
  58394         soc_block_list[42],
  58395         soc_genreg,
  58396         1,
  58397         0,
  58398         0x80,
  58399         0,
  58400         0,
  58401         5,
  58402         soc_OLP_INDIRECT_COMMAND_BCM88470_B0r_fields,
  58403         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  58404         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58405         -1,
  58406         -1,
  58407     },
  58408 #endif /* chips */
  58409 
  58410 #if defined(BCM_88650_B0)
  58411     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88650_B0r */
  58412         soc_block_list[42],
  58413         soc_genreg,
  58414         1,
  58415         0,
  58416         0x80,
  58417         0,
  58418         0,
  58419         5,
  58420         soc_OLP_INDIRECT_COMMAND_BCM88650_B0r_fields,
  58421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58422         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58423         -1,
  58424         -1,
  58425     },
  58426 #endif /* chips */
  58427 
  58428 #if defined(BCM_88660_A0)
  58429     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88660_A0r */
  58430         soc_block_list[42],
  58431         soc_genreg,
  58432         1,
  58433         0,
  58434         0x80,
  58435         0,
  58436         0,
  58437         5,
  58438         soc_OLP_INDIRECT_COMMAND_BCM88660_A0r_fields,
  58439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58440         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58441         -1,
  58442         -1,
  58443     },
  58444 #endif /* chips */
  58445 
  58446 #if defined(BCM_88675_A0)
  58447     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88675_A0r */
  58448         soc_block_list[42],
  58449         soc_genreg,
  58450         1,
  58451         0,
  58452         0x80,
  58453         0,
  58454         0,
  58455         5,
  58456         soc_OLP_INDIRECT_COMMAND_BCM88675_A0r_fields,
  58457         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  58458         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58459         -1,
  58460         -1,
  58461     },
  58462 #endif /* chips */
  58463 
  58464 #if defined(BCM_88675_B0)
  58465     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88675_B0r */
  58466         soc_block_list[42],
  58467         soc_genreg,
  58468         1,
  58469         0,
  58470         0x80,
  58471         0,
  58472         0,
  58473         5,
  58474         soc_OLP_INDIRECT_COMMAND_BCM88675_B0r_fields,
  58475         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  58476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58477         -1,
  58478         -1,
  58479     },
  58480 #endif /* chips */
  58481 
  58482 #if defined(BCM_88680_A0)
  58483     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88680_A0r */
  58484         soc_block_list[42],
  58485         soc_genreg,
  58486         1,
  58487         0,
  58488         0x80,
  58489         0,
  58490         0,
  58491         5,
  58492         soc_OLP_INDIRECT_COMMAND_BCM88680_A0r_fields,
  58493         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  58494         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58495         -1,
  58496         -1,
  58497     },
  58498 #endif /* chips */
  58499 
  58500 #if defined(BCM_88690_A0)
  58501     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88690_A0r */
  58502         soc_block_list[42],
  58503         soc_genreg,
  58504         1,
  58505         0,
  58506         0x80,
  58507         0,
  58508         0,
  58509         5,
  58510         soc_OLP_INDIRECT_COMMAND_BCM88690_A0r_fields,
  58511         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
  58512         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58513         -1,
  58514         -1,
  58515     },
  58516 #endif /* chips */
  58517 
  58518 #if defined(BCM_88690_B0)
  58519     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_BCM88690_B0r */
  58520         soc_block_list[42],
  58521         soc_genreg,
  58522         1,
  58523         0,
  58524         0x80,
  58525         0,
  58526         0,
  58527         5,
  58528         soc_OLP_INDIRECT_COMMAND_BCM88690_B0r_fields,
  58529         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
  58530         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58531         -1,
  58532         -1,
  58533     },
  58534 #endif /* chips */
  58535 
  58536 #if defined(BCM_88650_A0)
  58537     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENTr */
  58538         soc_block_list[42],
  58539         soc_genreg,
  58540         1,
  58541         0,
  58542         0x82,
  58543         SOC_REG_FLAG_64_BITS |
  58544                           SOC_REG_FLAG_SIGNAL,
  58545         0,
  58546         1,
  58547         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
  58548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58549         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58550         -1,
  58551         -1,
  58552     },
  58553 #endif /* chips */
  58554 
  58555 #if defined(BCM_88270_A0)
  58556     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88270_A0r */
  58557         soc_block_list[42],
  58558         soc_genreg,
  58559         1,
  58560         0,
  58561         0x82,
  58562         SOC_REG_FLAG_64_BITS,
  58563         0,
  58564         1,
  58565         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88270_A0r_fields,
  58566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58567         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58568         -1,
  58569         -1,
  58570     },
  58571 #endif /* chips */
  58572 
  58573 #if defined(BCM_88375_A0)
  58574     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_A0r */
  58575         soc_block_list[42],
  58576         soc_genreg,
  58577         1,
  58578         0,
  58579         0x82,
  58580         SOC_REG_FLAG_64_BITS,
  58581         0,
  58582         1,
  58583         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_A0r_fields,
  58584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58585         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58586         -1,
  58587         -1,
  58588     },
  58589 #endif /* chips */
  58590 
  58591 #if defined(BCM_88375_B0)
  58592     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_B0r */
  58593         soc_block_list[42],
  58594         soc_genreg,
  58595         1,
  58596         0,
  58597         0x82,
  58598         SOC_REG_FLAG_64_BITS,
  58599         0,
  58600         1,
  58601         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_B0r_fields,
  58602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58603         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58604         -1,
  58605         -1,
  58606     },
  58607 #endif /* chips */
  58608 
  58609 #if defined(BCM_88470_A0)
  58610     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_A0r */
  58611         soc_block_list[42],
  58612         soc_genreg,
  58613         1,
  58614         0,
  58615         0x82,
  58616         SOC_REG_FLAG_64_BITS,
  58617         0,
  58618         1,
  58619         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_A0r_fields,
  58620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58621         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58622         -1,
  58623         -1,
  58624     },
  58625 #endif /* chips */
  58626 
  58627 #if defined(BCM_88470_B0)
  58628     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_B0r */
  58629         soc_block_list[42],
  58630         soc_genreg,
  58631         1,
  58632         0,
  58633         0x82,
  58634         SOC_REG_FLAG_64_BITS,
  58635         0,
  58636         1,
  58637         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_B0r_fields,
  58638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58639         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58640         -1,
  58641         -1,
  58642     },
  58643 #endif /* chips */
  58644 
  58645 #if defined(BCM_88650_B0)
  58646     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88650_B0r */
  58647         soc_block_list[42],
  58648         soc_genreg,
  58649         1,
  58650         0,
  58651         0x82,
  58652         SOC_REG_FLAG_64_BITS |
  58653                           SOC_REG_FLAG_SIGNAL,
  58654         0,
  58655         1,
  58656         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88650_B0r_fields,
  58657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58658         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58659         -1,
  58660         -1,
  58661     },
  58662 #endif /* chips */
  58663 
  58664 #if defined(BCM_88660_A0)
  58665     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88660_A0r */
  58666         soc_block_list[42],
  58667         soc_genreg,
  58668         1,
  58669         0,
  58670         0x82,
  58671         SOC_REG_FLAG_64_BITS |
  58672                           SOC_REG_FLAG_SIGNAL,
  58673         0,
  58674         1,
  58675         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88660_A0r_fields,
  58676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58677         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58678         -1,
  58679         -1,
  58680     },
  58681 #endif /* chips */
  58682 
  58683 #if defined(BCM_88675_A0)
  58684     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_A0r */
  58685         soc_block_list[42],
  58686         soc_genreg,
  58687         1,
  58688         0,
  58689         0x82,
  58690         SOC_REG_FLAG_64_BITS,
  58691         0,
  58692         1,
  58693         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_A0r_fields,
  58694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58695         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58696         -1,
  58697         -1,
  58698     },
  58699 #endif /* chips */
  58700 
  58701 #if defined(BCM_88675_B0)
  58702     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_B0r */
  58703         soc_block_list[42],
  58704         soc_genreg,
  58705         1,
  58706         0,
  58707         0x82,
  58708         SOC_REG_FLAG_64_BITS,
  58709         0,
  58710         1,
  58711         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_B0r_fields,
  58712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58713         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58714         -1,
  58715         -1,
  58716     },
  58717 #endif /* chips */
  58718 
  58719 #if defined(BCM_88680_A0)
  58720     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r */
  58721         soc_block_list[42],
  58722         soc_genreg,
  58723         1,
  58724         0,
  58725         0x82,
  58726         SOC_REG_FLAG_64_BITS,
  58727         0,
  58728         1,
  58729         soc_OLP_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r_fields,
  58730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58731         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  58732         -1,
  58733         -1,
  58734     },
  58735 #endif /* chips */
  58736 
  58737 #if defined(BCM_88650_A0)
  58738     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATAr */
  58739         soc_block_list[42],
  58740         soc_genreg,
  58741         1,
  58742         0,
  58743         0x60,
  58744         SOC_REG_FLAG_ABOVE_64_BITS |
  58745                           SOC_REG_FLAG_RO,
  58746         0,
  58747         1,
  58748         soc_OLP_INDIRECT_COMMAND_RD_DATAr_fields,
  58749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58750         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58751         -1,
  58752         -1,
  58753     },
  58754 #endif /* chips */
  58755 
  58756 #if defined(BCM_88270_A0)
  58757     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88270_A0r */
  58758         soc_block_list[42],
  58759         soc_genreg,
  58760         1,
  58761         0,
  58762         0x60,
  58763         SOC_REG_FLAG_ABOVE_64_BITS |
  58764                           SOC_REG_FLAG_RO |
  58765                           SOC_REG_FLAG_SIGNAL,
  58766         0,
  58767         1,
  58768         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88270_A0r_fields,
  58769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58770         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58771         -1,
  58772         -1,
  58773     },
  58774 #endif /* chips */
  58775 
  58776 #if defined(BCM_88375_A0)
  58777     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88375_A0r */
  58778         soc_block_list[42],
  58779         soc_genreg,
  58780         1,
  58781         0,
  58782         0x60,
  58783         SOC_REG_FLAG_ABOVE_64_BITS |
  58784                           SOC_REG_FLAG_RO |
  58785                           SOC_REG_FLAG_SIGNAL,
  58786         0,
  58787         1,
  58788         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88375_A0r_fields,
  58789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58791         -1,
  58792         -1,
  58793     },
  58794 #endif /* chips */
  58795 
  58796 #if defined(BCM_88375_B0)
  58797     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88375_B0r */
  58798         soc_block_list[42],
  58799         soc_genreg,
  58800         1,
  58801         0,
  58802         0x60,
  58803         SOC_REG_FLAG_ABOVE_64_BITS |
  58804                           SOC_REG_FLAG_RO |
  58805                           SOC_REG_FLAG_SIGNAL,
  58806         0,
  58807         1,
  58808         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88375_B0r_fields,
  58809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58810         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58811         -1,
  58812         -1,
  58813     },
  58814 #endif /* chips */
  58815 
  58816 #if defined(BCM_88470_A0)
  58817     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88470_A0r */
  58818         soc_block_list[42],
  58819         soc_genreg,
  58820         1,
  58821         0,
  58822         0x60,
  58823         SOC_REG_FLAG_ABOVE_64_BITS |
  58824                           SOC_REG_FLAG_RO |
  58825                           SOC_REG_FLAG_SIGNAL,
  58826         0,
  58827         1,
  58828         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88470_A0r_fields,
  58829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58830         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58831         -1,
  58832         -1,
  58833     },
  58834 #endif /* chips */
  58835 
  58836 #if defined(BCM_88470_B0)
  58837     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88470_B0r */
  58838         soc_block_list[42],
  58839         soc_genreg,
  58840         1,
  58841         0,
  58842         0x60,
  58843         SOC_REG_FLAG_ABOVE_64_BITS |
  58844                           SOC_REG_FLAG_RO |
  58845                           SOC_REG_FLAG_SIGNAL,
  58846         0,
  58847         1,
  58848         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88470_B0r_fields,
  58849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58851         -1,
  58852         -1,
  58853     },
  58854 #endif /* chips */
  58855 
  58856 #if defined(BCM_88650_B0)
  58857     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88650_B0r */
  58858         soc_block_list[42],
  58859         soc_genreg,
  58860         1,
  58861         0,
  58862         0x60,
  58863         SOC_REG_FLAG_ABOVE_64_BITS |
  58864                           SOC_REG_FLAG_RO,
  58865         0,
  58866         1,
  58867         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88650_B0r_fields,
  58868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58870         -1,
  58871         -1,
  58872     },
  58873 #endif /* chips */
  58874 
  58875 #if defined(BCM_88660_A0)
  58876     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88660_A0r */
  58877         soc_block_list[42],
  58878         soc_genreg,
  58879         1,
  58880         0,
  58881         0x60,
  58882         SOC_REG_FLAG_ABOVE_64_BITS |
  58883                           SOC_REG_FLAG_RO,
  58884         0,
  58885         1,
  58886         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88660_A0r_fields,
  58887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58888         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58889         -1,
  58890         -1,
  58891     },
  58892 #endif /* chips */
  58893 
  58894 #if defined(BCM_88675_A0)
  58895     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88675_A0r */
  58896         soc_block_list[42],
  58897         soc_genreg,
  58898         1,
  58899         0,
  58900         0x60,
  58901         SOC_REG_FLAG_ABOVE_64_BITS |
  58902                           SOC_REG_FLAG_RO |
  58903                           SOC_REG_FLAG_SIGNAL,
  58904         0,
  58905         1,
  58906         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88675_A0r_fields,
  58907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58908         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58909         -1,
  58910         -1,
  58911     },
  58912 #endif /* chips */
  58913 
  58914 #if defined(BCM_88675_B0)
  58915     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88675_B0r */
  58916         soc_block_list[42],
  58917         soc_genreg,
  58918         1,
  58919         0,
  58920         0x60,
  58921         SOC_REG_FLAG_ABOVE_64_BITS |
  58922                           SOC_REG_FLAG_RO |
  58923                           SOC_REG_FLAG_SIGNAL,
  58924         0,
  58925         1,
  58926         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88675_B0r_fields,
  58927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58928         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58929         -1,
  58930         -1,
  58931     },
  58932 #endif /* chips */
  58933 
  58934 #if defined(BCM_88680_A0)
  58935     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88680_A0r */
  58936         soc_block_list[42],
  58937         soc_genreg,
  58938         1,
  58939         0,
  58940         0x60,
  58941         SOC_REG_FLAG_ABOVE_64_BITS |
  58942                           SOC_REG_FLAG_RO |
  58943                           SOC_REG_FLAG_SIGNAL,
  58944         0,
  58945         1,
  58946         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88680_A0r_fields,
  58947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58948         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58949         -1,
  58950         -1,
  58951     },
  58952 #endif /* chips */
  58953 
  58954 #if defined(BCM_88690_A0)
  58955     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88690_A0r */
  58956         soc_block_list[42],
  58957         soc_genreg,
  58958         1,
  58959         0,
  58960         0x60,
  58961         SOC_REG_FLAG_ABOVE_64_BITS |
  58962                           SOC_REG_FLAG_RO |
  58963                           SOC_REG_FLAG_SIGNAL,
  58964         0,
  58965         1,
  58966         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88690_A0r_fields,
  58967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58968         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58969         -1,
  58970         -1,
  58971     },
  58972 #endif /* chips */
  58973 
  58974 #if defined(BCM_88690_B0)
  58975     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r */
  58976         soc_block_list[42],
  58977         soc_genreg,
  58978         1,
  58979         0,
  58980         0x60,
  58981         SOC_REG_FLAG_ABOVE_64_BITS |
  58982                           SOC_REG_FLAG_RO |
  58983                           SOC_REG_FLAG_SIGNAL,
  58984         0,
  58985         1,
  58986         soc_OLP_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r_fields,
  58987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58988         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58989         -1,
  58990         -1,
  58991     },
  58992 #endif /* chips */
  58993 
  58994 #if defined(BCM_88675_A0)
  58995     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WIDE_MEMr */
  58996         soc_block_list[42],
  58997         soc_genreg,
  58998         1,
  58999         0,
  59000         0x41,
  59001         0,
  59002         0,
  59003         1,
  59004         soc_OLP_INDIRECT_COMMAND_WIDE_MEMr_fields,
  59005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59006         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59007         -1,
  59008         -1,
  59009     },
  59010 #endif /* chips */
  59011 
  59012 #if defined(BCM_88270_A0)
  59013     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88270_A0r */
  59014         soc_block_list[42],
  59015         soc_genreg,
  59016         1,
  59017         0,
  59018         0x41,
  59019         0,
  59020         0,
  59021         1,
  59022         soc_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88270_A0r_fields,
  59023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59024         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59025         -1,
  59026         -1,
  59027     },
  59028 #endif /* chips */
  59029 
  59030 #if defined(BCM_88375_A0)
  59031     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88375_A0r */
  59032         soc_block_list[42],
  59033         soc_genreg,
  59034         1,
  59035         0,
  59036         0x41,
  59037         0,
  59038         0,
  59039         1,
  59040         soc_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88375_A0r_fields,
  59041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59042         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59043         -1,
  59044         -1,
  59045     },
  59046 #endif /* chips */
  59047 
  59048 #if defined(BCM_88375_B0)
  59049     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88375_B0r */
  59050         soc_block_list[42],
  59051         soc_genreg,
  59052         1,
  59053         0,
  59054         0x41,
  59055         0,
  59056         0,
  59057         1,
  59058         soc_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88375_B0r_fields,
  59059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59060         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59061         -1,
  59062         -1,
  59063     },
  59064 #endif /* chips */
  59065 
  59066 #if defined(BCM_88470_A0)
  59067     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88470_A0r */
  59068         soc_block_list[42],
  59069         soc_genreg,
  59070         1,
  59071         0,
  59072         0x41,
  59073         0,
  59074         0,
  59075         1,
  59076         soc_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88470_A0r_fields,
  59077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59078         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59079         -1,
  59080         -1,
  59081     },
  59082 #endif /* chips */
  59083 
  59084 #if defined(BCM_88470_B0)
  59085     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88470_B0r */
  59086         soc_block_list[42],
  59087         soc_genreg,
  59088         1,
  59089         0,
  59090         0x41,
  59091         0,
  59092         0,
  59093         1,
  59094         soc_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88470_B0r_fields,
  59095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59096         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59097         -1,
  59098         -1,
  59099     },
  59100 #endif /* chips */
  59101 
  59102 #if defined(BCM_88675_B0)
  59103     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88675_B0r */
  59104         soc_block_list[42],
  59105         soc_genreg,
  59106         1,
  59107         0,
  59108         0x41,
  59109         0,
  59110         0,
  59111         1,
  59112         soc_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88675_B0r_fields,
  59113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59114         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59115         -1,
  59116         -1,
  59117     },
  59118 #endif /* chips */
  59119 
  59120 #if defined(BCM_88680_A0)
  59121     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r */
  59122         soc_block_list[42],
  59123         soc_genreg,
  59124         1,
  59125         0,
  59126         0x41,
  59127         0,
  59128         0,
  59129         1,
  59130         soc_OLP_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r_fields,
  59131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59132         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59133         -1,
  59134         -1,
  59135     },
  59136 #endif /* chips */
  59137 
  59138 #if defined(BCM_88650_A0)
  59139     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATAr */
  59140         soc_block_list[42],
  59141         soc_genreg,
  59142         1,
  59143         0,
  59144         0x20,
  59145         SOC_REG_FLAG_ABOVE_64_BITS,
  59146         0,
  59147         1,
  59148         soc_OLP_INDIRECT_COMMAND_WR_DATAr_fields,
  59149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59150         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59151         -1,
  59152         -1,
  59153     },
  59154 #endif /* chips */
  59155 
  59156 #if defined(BCM_88270_A0)
  59157     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88270_A0r */
  59158         soc_block_list[42],
  59159         soc_genreg,
  59160         1,
  59161         0,
  59162         0x20,
  59163         SOC_REG_FLAG_ABOVE_64_BITS,
  59164         0,
  59165         1,
  59166         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88270_A0r_fields,
  59167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59169         -1,
  59170         -1,
  59171     },
  59172 #endif /* chips */
  59173 
  59174 #if defined(BCM_88375_A0)
  59175     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88375_A0r */
  59176         soc_block_list[42],
  59177         soc_genreg,
  59178         1,
  59179         0,
  59180         0x20,
  59181         SOC_REG_FLAG_ABOVE_64_BITS,
  59182         0,
  59183         1,
  59184         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88375_A0r_fields,
  59185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59187         -1,
  59188         -1,
  59189     },
  59190 #endif /* chips */
  59191 
  59192 #if defined(BCM_88375_B0)
  59193     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88375_B0r */
  59194         soc_block_list[42],
  59195         soc_genreg,
  59196         1,
  59197         0,
  59198         0x20,
  59199         SOC_REG_FLAG_ABOVE_64_BITS,
  59200         0,
  59201         1,
  59202         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88375_B0r_fields,
  59203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59205         -1,
  59206         -1,
  59207     },
  59208 #endif /* chips */
  59209 
  59210 #if defined(BCM_88470_A0)
  59211     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88470_A0r */
  59212         soc_block_list[42],
  59213         soc_genreg,
  59214         1,
  59215         0,
  59216         0x20,
  59217         SOC_REG_FLAG_ABOVE_64_BITS,
  59218         0,
  59219         1,
  59220         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88470_A0r_fields,
  59221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59222         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59223         -1,
  59224         -1,
  59225     },
  59226 #endif /* chips */
  59227 
  59228 #if defined(BCM_88470_B0)
  59229     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88470_B0r */
  59230         soc_block_list[42],
  59231         soc_genreg,
  59232         1,
  59233         0,
  59234         0x20,
  59235         SOC_REG_FLAG_ABOVE_64_BITS,
  59236         0,
  59237         1,
  59238         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88470_B0r_fields,
  59239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59240         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59241         -1,
  59242         -1,
  59243     },
  59244 #endif /* chips */
  59245 
  59246 #if defined(BCM_88650_B0)
  59247     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88650_B0r */
  59248         soc_block_list[42],
  59249         soc_genreg,
  59250         1,
  59251         0,
  59252         0x20,
  59253         SOC_REG_FLAG_ABOVE_64_BITS,
  59254         0,
  59255         1,
  59256         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88650_B0r_fields,
  59257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59258         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59259         -1,
  59260         -1,
  59261     },
  59262 #endif /* chips */
  59263 
  59264 #if defined(BCM_88660_A0)
  59265     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88660_A0r */
  59266         soc_block_list[42],
  59267         soc_genreg,
  59268         1,
  59269         0,
  59270         0x20,
  59271         SOC_REG_FLAG_ABOVE_64_BITS,
  59272         0,
  59273         1,
  59274         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88660_A0r_fields,
  59275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59276         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59277         -1,
  59278         -1,
  59279     },
  59280 #endif /* chips */
  59281 
  59282 #if defined(BCM_88675_A0)
  59283     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88675_A0r */
  59284         soc_block_list[42],
  59285         soc_genreg,
  59286         1,
  59287         0,
  59288         0x20,
  59289         SOC_REG_FLAG_ABOVE_64_BITS,
  59290         0,
  59291         1,
  59292         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88675_A0r_fields,
  59293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59294         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59295         -1,
  59296         -1,
  59297     },
  59298 #endif /* chips */
  59299 
  59300 #if defined(BCM_88675_B0)
  59301     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88675_B0r */
  59302         soc_block_list[42],
  59303         soc_genreg,
  59304         1,
  59305         0,
  59306         0x20,
  59307         SOC_REG_FLAG_ABOVE_64_BITS,
  59308         0,
  59309         1,
  59310         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88675_B0r_fields,
  59311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59312         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59313         -1,
  59314         -1,
  59315     },
  59316 #endif /* chips */
  59317 
  59318 #if defined(BCM_88680_A0)
  59319     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r */
  59320         soc_block_list[42],
  59321         soc_genreg,
  59322         1,
  59323         0,
  59324         0x20,
  59325         SOC_REG_FLAG_ABOVE_64_BITS,
  59326         0,
  59327         1,
  59328         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r_fields,
  59329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59331         -1,
  59332         -1,
  59333     },
  59334 #endif /* chips */
  59335 
  59336 #if defined(BCM_88690_A0)
  59337     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r */
  59338         soc_block_list[42],
  59339         soc_genreg,
  59340         1,
  59341         0,
  59342         0x20,
  59343         SOC_REG_FLAG_ABOVE_64_BITS,
  59344         0,
  59345         1,
  59346         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r_fields,
  59347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59348         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59349         -1,
  59350         -1,
  59351     },
  59352 #endif /* chips */
  59353 
  59354 #if defined(BCM_88690_B0)
  59355     { /* SOC_REG_INT_OLP_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r */
  59356         soc_block_list[42],
  59357         soc_genreg,
  59358         1,
  59359         0,
  59360         0x20,
  59361         SOC_REG_FLAG_ABOVE_64_BITS,
  59362         0,
  59363         1,
  59364         soc_OLP_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r_fields,
  59365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59366         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59367         -1,
  59368         -1,
  59369     },
  59370 #endif /* chips */
  59371 
  59372 #if defined(BCM_88675_A0)
  59373     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLEr */
  59374         soc_block_list[42],
  59375         soc_genreg,
  59376         1,
  59377         0,
  59378         0x83,
  59379         0,
  59380         0,
  59381         4,
  59382         soc_OLP_INDIRECT_FORCE_BUBBLEr_fields,
  59383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59384         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  59385         -1,
  59386         -1,
  59387     },
  59388 #endif /* chips */
  59389 
  59390 #if defined(BCM_88270_A0)
  59391     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLE_BCM88270_A0r */
  59392         soc_block_list[42],
  59393         soc_genreg,
  59394         1,
  59395         0,
  59396         0x83,
  59397         0,
  59398         0,
  59399         4,
  59400         soc_OLP_INDIRECT_FORCE_BUBBLE_BCM88270_A0r_fields,
  59401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59402         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  59403         -1,
  59404         -1,
  59405     },
  59406 #endif /* chips */
  59407 
  59408 #if defined(BCM_88375_A0)
  59409     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLE_BCM88375_A0r */
  59410         soc_block_list[42],
  59411         soc_genreg,
  59412         1,
  59413         0,
  59414         0x83,
  59415         0,
  59416         0,
  59417         4,
  59418         soc_OLP_INDIRECT_FORCE_BUBBLE_BCM88375_A0r_fields,
  59419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59420         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  59421         -1,
  59422         -1,
  59423     },
  59424 #endif /* chips */
  59425 
  59426 #if defined(BCM_88375_B0)
  59427     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLE_BCM88375_B0r */
  59428         soc_block_list[42],
  59429         soc_genreg,
  59430         1,
  59431         0,
  59432         0x83,
  59433         0,
  59434         0,
  59435         4,
  59436         soc_OLP_INDIRECT_FORCE_BUBBLE_BCM88375_B0r_fields,
  59437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59438         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  59439         -1,
  59440         -1,
  59441     },
  59442 #endif /* chips */
  59443 
  59444 #if defined(BCM_88470_A0)
  59445     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLE_BCM88470_A0r */
  59446         soc_block_list[42],
  59447         soc_genreg,
  59448         1,
  59449         0,
  59450         0x83,
  59451         0,
  59452         0,
  59453         4,
  59454         soc_OLP_INDIRECT_FORCE_BUBBLE_BCM88470_A0r_fields,
  59455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59456         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  59457         -1,
  59458         -1,
  59459     },
  59460 #endif /* chips */
  59461 
  59462 #if defined(BCM_88470_B0)
  59463     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLE_BCM88470_B0r */
  59464         soc_block_list[42],
  59465         soc_genreg,
  59466         1,
  59467         0,
  59468         0x83,
  59469         0,
  59470         0,
  59471         4,
  59472         soc_OLP_INDIRECT_FORCE_BUBBLE_BCM88470_B0r_fields,
  59473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59474         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  59475         -1,
  59476         -1,
  59477     },
  59478 #endif /* chips */
  59479 
  59480 #if defined(BCM_88675_B0)
  59481     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLE_BCM88675_B0r */
  59482         soc_block_list[42],
  59483         soc_genreg,
  59484         1,
  59485         0,
  59486         0x83,
  59487         0,
  59488         0,
  59489         4,
  59490         soc_OLP_INDIRECT_FORCE_BUBBLE_BCM88675_B0r_fields,
  59491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59492         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  59493         -1,
  59494         -1,
  59495     },
  59496 #endif /* chips */
  59497 
  59498 #if defined(BCM_88680_A0)
  59499     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLE_BCM88680_A0r */
  59500         soc_block_list[42],
  59501         soc_genreg,
  59502         1,
  59503         0,
  59504         0x83,
  59505         0,
  59506         0,
  59507         4,
  59508         soc_OLP_INDIRECT_FORCE_BUBBLE_BCM88680_A0r_fields,
  59509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59510         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  59511         -1,
  59512         -1,
  59513     },
  59514 #endif /* chips */
  59515 
  59516 #if defined(BCM_88690_A0)
  59517     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLE_BCM88690_A0r */
  59518         soc_block_list[42],
  59519         soc_genreg,
  59520         1,
  59521         0,
  59522         0x83,
  59523         0,
  59524         0,
  59525         4,
  59526         soc_OLP_INDIRECT_FORCE_BUBBLE_BCM88690_A0r_fields,
  59527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59528         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  59529         -1,
  59530         -1,
  59531     },
  59532 #endif /* chips */
  59533 
  59534 #if defined(BCM_88690_B0)
  59535     { /* SOC_REG_INT_OLP_INDIRECT_FORCE_BUBBLE_BCM88690_B0r */
  59536         soc_block_list[42],
  59537         soc_genreg,
  59538         1,
  59539         0,
  59540         0x83,
  59541         0,
  59542         0,
  59543         4,
  59544         soc_OLP_INDIRECT_FORCE_BUBBLE_BCM88690_B0r_fields,
  59545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59546         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  59547         -1,
  59548         -1,
  59549     },
  59550 #endif /* chips */
  59551 
  59552 #if defined(BCM_88650_A0)
  59553     { /* SOC_REG_INT_OLP_INDIRECT_WR_MASKr */
  59554         soc_block_list[42],
  59555         soc_genreg,
  59556         1,
  59557         0,
  59558         0x40,
  59559         SOC_REG_FLAG_ABOVE_64_BITS,
  59560         0,
  59561         1,
  59562         soc_OLP_INDIRECT_WR_MASKr_fields,
  59563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59564         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59565         -1,
  59566         -1,
  59567     },
  59568 #endif /* chips */
  59569 
  59570 #if defined(BCM_88650_B0)
  59571     { /* SOC_REG_INT_OLP_INDIRECT_WR_MASK_BCM88650_B0r */
  59572         soc_block_list[42],
  59573         soc_genreg,
  59574         1,
  59575         0,
  59576         0x40,
  59577         SOC_REG_FLAG_ABOVE_64_BITS,
  59578         0,
  59579         1,
  59580         soc_OLP_INDIRECT_WR_MASK_BCM88650_B0r_fields,
  59581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59582         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59583         -1,
  59584         -1,
  59585     },
  59586 #endif /* chips */
  59587 
  59588 #if defined(BCM_88660_A0)
  59589     { /* SOC_REG_INT_OLP_INDIRECT_WR_MASK_BCM88660_A0r */
  59590         soc_block_list[42],
  59591         soc_genreg,
  59592         1,
  59593         0,
  59594         0x40,
  59595         SOC_REG_FLAG_ABOVE_64_BITS,
  59596         0,
  59597         1,
  59598         soc_OLP_INDIRECT_WR_MASK_BCM88660_A0r_fields,
  59599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59600         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59601         -1,
  59602         -1,
  59603     },
  59604 #endif /* chips */
  59605 
  59606 #if defined(BCM_88650_A0)
  59607     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTERr */
  59608         soc_block_list[42],
  59609         soc_genreg,
  59610         1,
  59611         0,
  59612         0x10,
  59613         SOC_REG_FLAG_SIGNAL,
  59614         0,
  59615         1,
  59616         soc_OLP_INTERRUPT_MASK_REGISTERr_fields,
  59617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59618         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59619         -1,
  59620         -1,
  59621     },
  59622 #endif /* chips */
  59623 
  59624 #if defined(BCM_88270_A0)
  59625     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88270_A0r */
  59626         soc_block_list[42],
  59627         soc_genreg,
  59628         1,
  59629         0,
  59630         0x10,
  59631         0,
  59632         0,
  59633         2,
  59634         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88270_A0r_fields,
  59635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59636         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59637         -1,
  59638         -1,
  59639     },
  59640 #endif /* chips */
  59641 
  59642 #if defined(BCM_88375_A0)
  59643     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88375_A0r */
  59644         soc_block_list[42],
  59645         soc_genreg,
  59646         1,
  59647         0,
  59648         0x10,
  59649         0,
  59650         0,
  59651         2,
  59652         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88375_A0r_fields,
  59653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59654         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59655         -1,
  59656         -1,
  59657     },
  59658 #endif /* chips */
  59659 
  59660 #if defined(BCM_88375_B0)
  59661     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88375_B0r */
  59662         soc_block_list[42],
  59663         soc_genreg,
  59664         1,
  59665         0,
  59666         0x10,
  59667         0,
  59668         0,
  59669         2,
  59670         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88375_B0r_fields,
  59671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59672         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59673         -1,
  59674         -1,
  59675     },
  59676 #endif /* chips */
  59677 
  59678 #if defined(BCM_88470_A0)
  59679     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88470_A0r */
  59680         soc_block_list[42],
  59681         soc_genreg,
  59682         1,
  59683         0,
  59684         0x10,
  59685         0,
  59686         0,
  59687         2,
  59688         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88470_A0r_fields,
  59689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59690         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59691         -1,
  59692         -1,
  59693     },
  59694 #endif /* chips */
  59695 
  59696 #if defined(BCM_88470_B0)
  59697     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88470_B0r */
  59698         soc_block_list[42],
  59699         soc_genreg,
  59700         1,
  59701         0,
  59702         0x10,
  59703         0,
  59704         0,
  59705         2,
  59706         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88470_B0r_fields,
  59707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59708         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59709         -1,
  59710         -1,
  59711     },
  59712 #endif /* chips */
  59713 
  59714 #if defined(BCM_88650_B0)
  59715     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88650_B0r */
  59716         soc_block_list[42],
  59717         soc_genreg,
  59718         1,
  59719         0,
  59720         0x10,
  59721         SOC_REG_FLAG_SIGNAL,
  59722         0,
  59723         1,
  59724         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88650_B0r_fields,
  59725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59726         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59727         -1,
  59728         -1,
  59729     },
  59730 #endif /* chips */
  59731 
  59732 #if defined(BCM_88660_A0)
  59733     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88660_A0r */
  59734         soc_block_list[42],
  59735         soc_genreg,
  59736         1,
  59737         0,
  59738         0x10,
  59739         SOC_REG_FLAG_SIGNAL,
  59740         0,
  59741         1,
  59742         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88660_A0r_fields,
  59743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59744         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59745         -1,
  59746         -1,
  59747     },
  59748 #endif /* chips */
  59749 
  59750 #if defined(BCM_88675_A0)
  59751     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88675_A0r */
  59752         soc_block_list[42],
  59753         soc_genreg,
  59754         1,
  59755         0,
  59756         0x10,
  59757         0,
  59758         0,
  59759         2,
  59760         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88675_A0r_fields,
  59761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59762         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59763         -1,
  59764         -1,
  59765     },
  59766 #endif /* chips */
  59767 
  59768 #if defined(BCM_88675_B0)
  59769     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88675_B0r */
  59770         soc_block_list[42],
  59771         soc_genreg,
  59772         1,
  59773         0,
  59774         0x10,
  59775         0,
  59776         0,
  59777         2,
  59778         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88675_B0r_fields,
  59779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59780         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59781         -1,
  59782         -1,
  59783     },
  59784 #endif /* chips */
  59785 
  59786 #if defined(BCM_88680_A0)
  59787     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88680_A0r */
  59788         soc_block_list[42],
  59789         soc_genreg,
  59790         1,
  59791         0,
  59792         0x10,
  59793         0,
  59794         0,
  59795         2,
  59796         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88680_A0r_fields,
  59797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59798         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59799         -1,
  59800         -1,
  59801     },
  59802 #endif /* chips */
  59803 
  59804 #if defined(BCM_88690_A0)
  59805     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88690_A0r */
  59806         soc_block_list[42],
  59807         soc_genreg,
  59808         1,
  59809         0,
  59810         0x10,
  59811         0,
  59812         0,
  59813         2,
  59814         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88690_A0r_fields,
  59815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59816         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59817         -1,
  59818         -1,
  59819     },
  59820 #endif /* chips */
  59821 
  59822 #if defined(BCM_88690_B0)
  59823     { /* SOC_REG_INT_OLP_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  59824         soc_block_list[42],
  59825         soc_genreg,
  59826         1,
  59827         0,
  59828         0x10,
  59829         0,
  59830         0,
  59831         2,
  59832         soc_OLP_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  59833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59834         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59835         -1,
  59836         -1,
  59837     },
  59838 #endif /* chips */
  59839 
  59840 #if defined(BCM_88650_A0)
  59841     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTERr */
  59842         soc_block_list[42],
  59843         soc_genreg,
  59844         1,
  59845         0,
  59846         0,
  59847         SOC_REG_FLAG_INTERRUPT,
  59848         0,
  59849         1,
  59850         soc_OLP_INTERRUPT_REGISTERr_fields,
  59851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59852         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59853         -1,
  59854         -1,
  59855     },
  59856 #endif /* chips */
  59857 
  59858 #if defined(BCM_88270_A0)
  59859     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88270_A0r */
  59860         soc_block_list[42],
  59861         soc_genreg,
  59862         1,
  59863         0,
  59864         0,
  59865         SOC_REG_FLAG_INTERRUPT |
  59866                           SOC_REG_FLAG_SIGNAL,
  59867         0,
  59868         2,
  59869         soc_OLP_INTERRUPT_REGISTER_BCM88270_A0r_fields,
  59870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59871         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59872         -1,
  59873         -1,
  59874     },
  59875 #endif /* chips */
  59876 
  59877 #if defined(BCM_88375_A0)
  59878     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88375_A0r */
  59879         soc_block_list[42],
  59880         soc_genreg,
  59881         1,
  59882         0,
  59883         0,
  59884         SOC_REG_FLAG_INTERRUPT,
  59885         0,
  59886         2,
  59887         soc_OLP_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  59888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59889         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59890         -1,
  59891         -1,
  59892     },
  59893 #endif /* chips */
  59894 
  59895 #if defined(BCM_88375_B0)
  59896     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88375_B0r */
  59897         soc_block_list[42],
  59898         soc_genreg,
  59899         1,
  59900         0,
  59901         0,
  59902         SOC_REG_FLAG_INTERRUPT,
  59903         0,
  59904         2,
  59905         soc_OLP_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  59906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59907         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59908         -1,
  59909         -1,
  59910     },
  59911 #endif /* chips */
  59912 
  59913 #if defined(BCM_88470_A0)
  59914     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88470_A0r */
  59915         soc_block_list[42],
  59916         soc_genreg,
  59917         1,
  59918         0,
  59919         0,
  59920         SOC_REG_FLAG_INTERRUPT |
  59921                           SOC_REG_FLAG_SIGNAL,
  59922         0,
  59923         2,
  59924         soc_OLP_INTERRUPT_REGISTER_BCM88470_A0r_fields,
  59925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59926         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59927         -1,
  59928         -1,
  59929     },
  59930 #endif /* chips */
  59931 
  59932 #if defined(BCM_88470_B0)
  59933     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88470_B0r */
  59934         soc_block_list[42],
  59935         soc_genreg,
  59936         1,
  59937         0,
  59938         0,
  59939         SOC_REG_FLAG_INTERRUPT |
  59940                           SOC_REG_FLAG_SIGNAL,
  59941         0,
  59942         2,
  59943         soc_OLP_INTERRUPT_REGISTER_BCM88470_B0r_fields,
  59944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59945         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  59946         -1,
  59947         -1,
  59948     },
  59949 #endif /* chips */
  59950 
  59951 #if defined(BCM_88650_B0)
  59952     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88650_B0r */
  59953         soc_block_list[42],
  59954         soc_genreg,
  59955         1,
  59956         0,
  59957         0,
  59958         SOC_REG_FLAG_INTERRUPT,
  59959         0,
  59960         1,
  59961         soc_OLP_INTERRUPT_REGISTER_BCM88650_B0r_fields,
  59962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59963         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59964         -1,
  59965         -1,
  59966     },
  59967 #endif /* chips */
  59968 
  59969 #if defined(BCM_88660_A0)
  59970     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88660_A0r */
  59971         soc_block_list[42],
  59972         soc_genreg,
  59973         1,
  59974         0,
  59975         0,
  59976         SOC_REG_FLAG_INTERRUPT,
  59977         0,
  59978         1,
  59979         soc_OLP_INTERRUPT_REGISTER_BCM88660_A0r_fields,
  59980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59981         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59982         -1,
  59983         -1,
  59984     },
  59985 #endif /* chips */
  59986 
  59987 #if defined(BCM_88675_A0)
  59988     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88675_A0r */
  59989         soc_block_list[42],
  59990         soc_genreg,
  59991         1,
  59992         0,
  59993         0,
  59994         SOC_REG_FLAG_INTERRUPT,
  59995         0,
  59996         2,
  59997         soc_OLP_INTERRUPT_REGISTER_BCM88675_A0r_fields,
  59998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59999         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60000         -1,
  60001         -1,
  60002     },
  60003 #endif /* chips */
  60004 
  60005 #if defined(BCM_88675_B0)
  60006     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88675_B0r */
  60007         soc_block_list[42],
  60008         soc_genreg,
  60009         1,
  60010         0,
  60011         0,
  60012         SOC_REG_FLAG_INTERRUPT,
  60013         0,
  60014         2,
  60015         soc_OLP_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  60016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60017         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60018         -1,
  60019         -1,
  60020     },
  60021 #endif /* chips */
  60022 
  60023 #if defined(BCM_88680_A0)
  60024     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88680_A0r */
  60025         soc_block_list[42],
  60026         soc_genreg,
  60027         1,
  60028         0,
  60029         0,
  60030         SOC_REG_FLAG_INTERRUPT,
  60031         0,
  60032         2,
  60033         soc_OLP_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  60034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60035         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60036         -1,
  60037         -1,
  60038     },
  60039 #endif /* chips */
  60040 
  60041 #if defined(BCM_88690_A0)
  60042     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88690_A0r */
  60043         soc_block_list[42],
  60044         soc_genreg,
  60045         1,
  60046         0,
  60047         0,
  60048         SOC_REG_FLAG_INTERRUPT |
  60049                           SOC_REG_FLAG_SIGNAL,
  60050         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  60051         2,
  60052         soc_OLP_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  60053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60054         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60055         -1,
  60056         -1,
  60057     },
  60058 #endif /* chips */
  60059 
  60060 #if defined(BCM_88690_B0)
  60061     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_BCM88690_B0r */
  60062         soc_block_list[42],
  60063         soc_genreg,
  60064         1,
  60065         0,
  60066         0,
  60067         SOC_REG_FLAG_INTERRUPT |
  60068                           SOC_REG_FLAG_SIGNAL,
  60069         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  60070         2,
  60071         soc_OLP_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  60072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60073         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60074         -1,
  60075         -1,
  60076     },
  60077 #endif /* chips */
  60078 
  60079 #if defined(BCM_88650_A0)
  60080     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TESTr */
  60081         soc_block_list[42],
  60082         soc_genreg,
  60083         1,
  60084         0,
  60085         0x18,
  60086         SOC_REG_FLAG_INTERRUPT |
  60087                           SOC_REG_FLAG_SIGNAL,
  60088         0,
  60089         1,
  60090         soc_OLP_INTERRUPT_REGISTER_TESTr_fields,
  60091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60092         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60093         -1,
  60094         -1,
  60095     },
  60096 #endif /* chips */
  60097 
  60098 #if defined(BCM_88270_A0)
  60099     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88270_A0r */
  60100         soc_block_list[42],
  60101         soc_genreg,
  60102         1,
  60103         0,
  60104         0x18,
  60105         0,
  60106         0,
  60107         1,
  60108         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88270_A0r_fields,
  60109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60110         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60111         -1,
  60112         -1,
  60113     },
  60114 #endif /* chips */
  60115 
  60116 #if defined(BCM_88375_A0)
  60117     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  60118         soc_block_list[42],
  60119         soc_genreg,
  60120         1,
  60121         0,
  60122         0x18,
  60123         0,
  60124         0,
  60125         1,
  60126         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  60127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60128         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60129         -1,
  60130         -1,
  60131     },
  60132 #endif /* chips */
  60133 
  60134 #if defined(BCM_88375_B0)
  60135     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  60136         soc_block_list[42],
  60137         soc_genreg,
  60138         1,
  60139         0,
  60140         0x18,
  60141         0,
  60142         0,
  60143         1,
  60144         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  60145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60146         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60147         -1,
  60148         -1,
  60149     },
  60150 #endif /* chips */
  60151 
  60152 #if defined(BCM_88470_A0)
  60153     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88470_A0r */
  60154         soc_block_list[42],
  60155         soc_genreg,
  60156         1,
  60157         0,
  60158         0x18,
  60159         0,
  60160         0,
  60161         1,
  60162         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88470_A0r_fields,
  60163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60164         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60165         -1,
  60166         -1,
  60167     },
  60168 #endif /* chips */
  60169 
  60170 #if defined(BCM_88470_B0)
  60171     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88470_B0r */
  60172         soc_block_list[42],
  60173         soc_genreg,
  60174         1,
  60175         0,
  60176         0x18,
  60177         0,
  60178         0,
  60179         1,
  60180         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88470_B0r_fields,
  60181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60182         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60183         -1,
  60184         -1,
  60185     },
  60186 #endif /* chips */
  60187 
  60188 #if defined(BCM_88650_B0)
  60189     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88650_B0r */
  60190         soc_block_list[42],
  60191         soc_genreg,
  60192         1,
  60193         0,
  60194         0x18,
  60195         SOC_REG_FLAG_INTERRUPT |
  60196                           SOC_REG_FLAG_SIGNAL,
  60197         0,
  60198         1,
  60199         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88650_B0r_fields,
  60200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60201         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60202         -1,
  60203         -1,
  60204     },
  60205 #endif /* chips */
  60206 
  60207 #if defined(BCM_88660_A0)
  60208     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88660_A0r */
  60209         soc_block_list[42],
  60210         soc_genreg,
  60211         1,
  60212         0,
  60213         0x18,
  60214         SOC_REG_FLAG_INTERRUPT |
  60215                           SOC_REG_FLAG_SIGNAL,
  60216         0,
  60217         1,
  60218         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88660_A0r_fields,
  60219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60220         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60221         -1,
  60222         -1,
  60223     },
  60224 #endif /* chips */
  60225 
  60226 #if defined(BCM_88675_A0)
  60227     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88675_A0r */
  60228         soc_block_list[42],
  60229         soc_genreg,
  60230         1,
  60231         0,
  60232         0x18,
  60233         0,
  60234         0,
  60235         1,
  60236         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88675_A0r_fields,
  60237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60238         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60239         -1,
  60240         -1,
  60241     },
  60242 #endif /* chips */
  60243 
  60244 #if defined(BCM_88675_B0)
  60245     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  60246         soc_block_list[42],
  60247         soc_genreg,
  60248         1,
  60249         0,
  60250         0x18,
  60251         0,
  60252         0,
  60253         1,
  60254         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  60255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60256         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60257         -1,
  60258         -1,
  60259     },
  60260 #endif /* chips */
  60261 
  60262 #if defined(BCM_88680_A0)
  60263     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  60264         soc_block_list[42],
  60265         soc_genreg,
  60266         1,
  60267         0,
  60268         0x18,
  60269         0,
  60270         0,
  60271         1,
  60272         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  60273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60274         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60275         -1,
  60276         -1,
  60277     },
  60278 #endif /* chips */
  60279 
  60280 #if defined(BCM_88690_A0)
  60281     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  60282         soc_block_list[42],
  60283         soc_genreg,
  60284         1,
  60285         0,
  60286         0x18,
  60287         0,
  60288         0,
  60289         1,
  60290         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  60291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60292         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60293         -1,
  60294         -1,
  60295     },
  60296 #endif /* chips */
  60297 
  60298 #if defined(BCM_88690_B0)
  60299     { /* SOC_REG_INT_OLP_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  60300         soc_block_list[42],
  60301         soc_genreg,
  60302         1,
  60303         0,
  60304         0x18,
  60305         0,
  60306         0,
  60307         1,
  60308         soc_OLP_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  60309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60310         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60311         -1,
  60312         -1,
  60313     },
  60314 #endif /* chips */
  60315 
  60316 #if defined(BCM_88650_A0)
  60317     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTERr */
  60318         soc_block_list[42],
  60319         soc_genreg,
  60320         1,
  60321         0,
  60322         0x124,
  60323         SOC_REG_FLAG_RO,
  60324         0,
  60325         1,
  60326         soc_OLP_IP_TRANSACTION_COUNTERr_fields,
  60327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60328         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60329         -1,
  60330         -1,
  60331     },
  60332 #endif /* chips */
  60333 
  60334 #if defined(BCM_88270_A0)
  60335     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88270_A0r */
  60336         soc_block_list[42],
  60337         soc_genreg,
  60338         1,
  60339         0,
  60340         0x12b,
  60341         SOC_REG_FLAG_RO |
  60342                           SOC_REG_FLAG_SIGNAL,
  60343         0,
  60344         1,
  60345         soc_OLP_IP_TRANSACTION_COUNTER_BCM88270_A0r_fields,
  60346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60347         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60348         -1,
  60349         -1,
  60350     },
  60351 #endif /* chips */
  60352 
  60353 #if defined(BCM_88375_A0)
  60354     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88375_A0r */
  60355         soc_block_list[42],
  60356         soc_genreg,
  60357         1,
  60358         0,
  60359         0x12b,
  60360         SOC_REG_FLAG_RO |
  60361                           SOC_REG_FLAG_SIGNAL,
  60362         0,
  60363         1,
  60364         soc_OLP_IP_TRANSACTION_COUNTER_BCM88375_A0r_fields,
  60365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60366         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60367         -1,
  60368         -1,
  60369     },
  60370 #endif /* chips */
  60371 
  60372 #if defined(BCM_88375_B0)
  60373     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88375_B0r */
  60374         soc_block_list[42],
  60375         soc_genreg,
  60376         1,
  60377         0,
  60378         0x12b,
  60379         SOC_REG_FLAG_RO |
  60380                           SOC_REG_FLAG_SIGNAL,
  60381         0,
  60382         1,
  60383         soc_OLP_IP_TRANSACTION_COUNTER_BCM88375_B0r_fields,
  60384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60385         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60386         -1,
  60387         -1,
  60388     },
  60389 #endif /* chips */
  60390 
  60391 #if defined(BCM_88470_A0)
  60392     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88470_A0r */
  60393         soc_block_list[42],
  60394         soc_genreg,
  60395         1,
  60396         0,
  60397         0x12b,
  60398         SOC_REG_FLAG_RO |
  60399                           SOC_REG_FLAG_SIGNAL,
  60400         0,
  60401         1,
  60402         soc_OLP_IP_TRANSACTION_COUNTER_BCM88470_A0r_fields,
  60403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60404         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60405         -1,
  60406         -1,
  60407     },
  60408 #endif /* chips */
  60409 
  60410 #if defined(BCM_88470_B0)
  60411     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88470_B0r */
  60412         soc_block_list[42],
  60413         soc_genreg,
  60414         1,
  60415         0,
  60416         0x12b,
  60417         SOC_REG_FLAG_RO |
  60418                           SOC_REG_FLAG_SIGNAL,
  60419         0,
  60420         1,
  60421         soc_OLP_IP_TRANSACTION_COUNTER_BCM88470_B0r_fields,
  60422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60423         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60424         -1,
  60425         -1,
  60426     },
  60427 #endif /* chips */
  60428 
  60429 #if defined(BCM_88650_B0)
  60430     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88650_B0r */
  60431         soc_block_list[42],
  60432         soc_genreg,
  60433         1,
  60434         0,
  60435         0x124,
  60436         SOC_REG_FLAG_RO,
  60437         0,
  60438         1,
  60439         soc_OLP_IP_TRANSACTION_COUNTER_BCM88650_B0r_fields,
  60440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60441         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60442         -1,
  60443         -1,
  60444     },
  60445 #endif /* chips */
  60446 
  60447 #if defined(BCM_88660_A0)
  60448     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88660_A0r */
  60449         soc_block_list[42],
  60450         soc_genreg,
  60451         1,
  60452         0,
  60453         0x124,
  60454         SOC_REG_FLAG_RO,
  60455         0,
  60456         1,
  60457         soc_OLP_IP_TRANSACTION_COUNTER_BCM88660_A0r_fields,
  60458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60459         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60460         -1,
  60461         -1,
  60462     },
  60463 #endif /* chips */
  60464 
  60465 #if defined(BCM_88675_A0)
  60466     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88675_A0r */
  60467         soc_block_list[42],
  60468         soc_genreg,
  60469         1,
  60470         0,
  60471         0x12b,
  60472         SOC_REG_FLAG_RO |
  60473                           SOC_REG_FLAG_SIGNAL,
  60474         0,
  60475         1,
  60476         soc_OLP_IP_TRANSACTION_COUNTER_BCM88675_A0r_fields,
  60477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60478         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60479         -1,
  60480         -1,
  60481     },
  60482 #endif /* chips */
  60483 
  60484 #if defined(BCM_88675_B0)
  60485     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88675_B0r */
  60486         soc_block_list[42],
  60487         soc_genreg,
  60488         1,
  60489         0,
  60490         0x12b,
  60491         SOC_REG_FLAG_RO |
  60492                           SOC_REG_FLAG_SIGNAL,
  60493         0,
  60494         1,
  60495         soc_OLP_IP_TRANSACTION_COUNTER_BCM88675_B0r_fields,
  60496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60497         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60498         -1,
  60499         -1,
  60500     },
  60501 #endif /* chips */
  60502 
  60503 #if defined(BCM_88680_A0)
  60504     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88680_A0r */
  60505         soc_block_list[42],
  60506         soc_genreg,
  60507         1,
  60508         0,
  60509         0x12b,
  60510         SOC_REG_FLAG_RO |
  60511                           SOC_REG_FLAG_SIGNAL,
  60512         0,
  60513         1,
  60514         soc_OLP_IP_TRANSACTION_COUNTER_BCM88680_A0r_fields,
  60515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60516         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60517         -1,
  60518         -1,
  60519     },
  60520 #endif /* chips */
  60521 
  60522 #if defined(BCM_88690_A0)
  60523     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88690_A0r */
  60524         soc_block_list[42],
  60525         soc_genreg,
  60526         1,
  60527         0,
  60528         0x14d,
  60529         SOC_REG_FLAG_RO,
  60530         SOC_REG_FLAG_COUNTER_FEILDS,
  60531         1,
  60532         soc_OLP_IP_TRANSACTION_COUNTER_BCM88690_A0r_fields,
  60533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60534         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60535         -1,
  60536         -1,
  60537     },
  60538 #endif /* chips */
  60539 
  60540 #if defined(BCM_88690_B0)
  60541     { /* SOC_REG_INT_OLP_IP_TRANSACTION_COUNTER_BCM88690_B0r */
  60542         soc_block_list[42],
  60543         soc_genreg,
  60544         1,
  60545         0,
  60546         0x14d,
  60547         SOC_REG_FLAG_RO,
  60548         SOC_REG_FLAG_COUNTER_FEILDS,
  60549         1,
  60550         soc_OLP_IP_TRANSACTION_COUNTER_BCM88690_B0r_fields,
  60551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60552         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60553         -1,
  60554         -1,
  60555     },
  60556 #endif /* chips */
  60557 
  60558 #if defined(BCM_88690_A0)
  60559     { /* SOC_REG_INT_OLP_LARGE_EM_MRQ_CONFIGURATIONr */
  60560         soc_block_list[42],
  60561         soc_genreg,
  60562         1,
  60563         0,
  60564         0x123,
  60565         0,
  60566         0,
  60567         1,
  60568         soc_OLP_LARGE_EM_MRQ_CONFIGURATIONr_fields,
  60569         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  60570         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60571         -1,
  60572         -1,
  60573     },
  60574 #endif /* chips */
  60575 
  60576 #if defined(BCM_88690_B0)
  60577     { /* SOC_REG_INT_OLP_LARGE_EM_MRQ_CONFIGURATION_BCM88690_B0r */
  60578         soc_block_list[42],
  60579         soc_genreg,
  60580         1,
  60581         0,
  60582         0x123,
  60583         0,
  60584         0,
  60585         1,
  60586         soc_OLP_LARGE_EM_MRQ_CONFIGURATION_BCM88690_B0r_fields,
  60587         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  60588         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60589         -1,
  60590         -1,
  60591     },
  60592 #endif /* chips */
  60593 
  60594 #if defined(BCM_88690_A0)
  60595     { /* SOC_REG_INT_OLP_LEARN_CMD_DESTINATION_OFFSETr */
  60596         soc_block_list[42],
  60597         soc_genreg,
  60598         1,
  60599         0,
  60600         0x11b,
  60601         0,
  60602         0,
  60603         1,
  60604         soc_OLP_LEARN_CMD_DESTINATION_OFFSETr_fields,
  60605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60606         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60607         -1,
  60608         -1,
  60609     },
  60610 #endif /* chips */
  60611 
  60612 #if defined(BCM_88690_B0)
  60613     { /* SOC_REG_INT_OLP_LEARN_CMD_DESTINATION_OFFSET_BCM88690_B0r */
  60614         soc_block_list[42],
  60615         soc_genreg,
  60616         1,
  60617         0,
  60618         0x11b,
  60619         0,
  60620         0,
  60621         1,
  60622         soc_OLP_LEARN_CMD_DESTINATION_OFFSET_BCM88690_B0r_fields,
  60623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60624         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60625         -1,
  60626         -1,
  60627     },
  60628 #endif /* chips */
  60629 
  60630 #if defined(BCM_88690_A0)
  60631     { /* SOC_REG_INT_OLP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_INITIAL_VALUEr */
  60632         soc_block_list[42],
  60633         soc_genreg,
  60634         1,
  60635         0,
  60636         0x117,
  60637         SOC_REG_FLAG_64_BITS,
  60638         0,
  60639         1,
  60640         soc_OLP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_INITIAL_VALUEr_fields,
  60641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60642         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  60643         -1,
  60644         -1,
  60645     },
  60646 #endif /* chips */
  60647 
  60648 #if defined(BCM_88690_B0)
  60649     { /* SOC_REG_INT_OLP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_INITIAL_VALUE_BCM88690_B0r */
  60650         soc_block_list[42],
  60651         soc_genreg,
  60652         1,
  60653         0,
  60654         0x117,
  60655         SOC_REG_FLAG_64_BITS,
  60656         0,
  60657         1,
  60658         soc_OLP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_INITIAL_VALUE_BCM88690_B0r_fields,
  60659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60660         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  60661         -1,
  60662         -1,
  60663     },
  60664 #endif /* chips */
  60665 
  60666 #if defined(BCM_88690_A0)
  60667     { /* SOC_REG_INT_OLP_LEARN_CMD_EEI_OFFSETr */
  60668         soc_block_list[42],
  60669         soc_genreg,
  60670         1,
  60671         0,
  60672         0x11d,
  60673         0,
  60674         0,
  60675         1,
  60676         soc_OLP_LEARN_CMD_EEI_OFFSETr_fields,
  60677         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  60678         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60679         -1,
  60680         -1,
  60681     },
  60682 #endif /* chips */
  60683 
  60684 #if defined(BCM_88690_B0)
  60685     { /* SOC_REG_INT_OLP_LEARN_CMD_EEI_OFFSET_BCM88690_B0r */
  60686         soc_block_list[42],
  60687         soc_genreg,
  60688         1,
  60689         0,
  60690         0x11d,
  60691         0,
  60692         0,
  60693         1,
  60694         soc_OLP_LEARN_CMD_EEI_OFFSET_BCM88690_B0r_fields,
  60695         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  60696         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60697         -1,
  60698         -1,
  60699     },
  60700 #endif /* chips */
  60701 
  60702 #if defined(BCM_88690_A0)
  60703     { /* SOC_REG_INT_OLP_LEARN_CMD_FEC_OFFSETr */
  60704         soc_block_list[42],
  60705         soc_genreg,
  60706         1,
  60707         0,
  60708         0x11e,
  60709         0,
  60710         0,
  60711         1,
  60712         soc_OLP_LEARN_CMD_FEC_OFFSETr_fields,
  60713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60714         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60715         -1,
  60716         -1,
  60717     },
  60718 #endif /* chips */
  60719 
  60720 #if defined(BCM_88690_B0)
  60721     { /* SOC_REG_INT_OLP_LEARN_CMD_FEC_OFFSET_BCM88690_B0r */
  60722         soc_block_list[42],
  60723         soc_genreg,
  60724         1,
  60725         0,
  60726         0x11e,
  60727         0,
  60728         0,
  60729         1,
  60730         soc_OLP_LEARN_CMD_FEC_OFFSET_BCM88690_B0r_fields,
  60731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60732         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60733         -1,
  60734         -1,
  60735     },
  60736 #endif /* chips */
  60737 
  60738 #if defined(BCM_88690_A0)
  60739     { /* SOC_REG_INT_OLP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_INFO_DATA_INITIAL_VALUEr */
  60740         soc_block_list[42],
  60741         soc_genreg,
  60742         1,
  60743         0,
  60744         0x119,
  60745         SOC_REG_FLAG_64_BITS,
  60746         0,
  60747         1,
  60748         soc_OLP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_INFO_DATA_INITIAL_VALUEr_fields,
  60749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60750         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  60751         -1,
  60752         -1,
  60753     },
  60754 #endif /* chips */
  60755 
  60756 #if defined(BCM_88690_B0)
  60757     { /* SOC_REG_INT_OLP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_INFO_DATA_INITIAL_VALUE_BCM88690_B0r */
  60758         soc_block_list[42],
  60759         soc_genreg,
  60760         1,
  60761         0,
  60762         0x119,
  60763         SOC_REG_FLAG_64_BITS,
  60764         0,
  60765         1,
  60766         soc_OLP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_INFO_DATA_INITIAL_VALUE_BCM88690_B0r_fields,
  60767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60768         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  60769         -1,
  60770         -1,
  60771     },
  60772 #endif /* chips */
  60773 
  60774 #if defined(BCM_88690_A0)
  60775     { /* SOC_REG_INT_OLP_LEARN_CMD_OUT_LIF_OFFSETr */
  60776         soc_block_list[42],
  60777         soc_genreg,
  60778         1,
  60779         0,
  60780         0x11c,
  60781         0,
  60782         0,
  60783         1,
  60784         soc_OLP_LEARN_CMD_OUT_LIF_OFFSETr_fields,
  60785         SOC_RESET_VAL_DEC(0x00000015, 0x00000000)
  60786         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60787         -1,
  60788         -1,
  60789     },
  60790 #endif /* chips */
  60791 
  60792 #if defined(BCM_88690_B0)
  60793     { /* SOC_REG_INT_OLP_LEARN_CMD_OUT_LIF_OFFSET_BCM88690_B0r */
  60794         soc_block_list[42],
  60795         soc_genreg,
  60796         1,
  60797         0,
  60798         0x11c,
  60799         0,
  60800         0,
  60801         1,
  60802         soc_OLP_LEARN_CMD_OUT_LIF_OFFSET_BCM88690_B0r_fields,
  60803         SOC_RESET_VAL_DEC(0x00000015, 0x00000000)
  60804         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60805         -1,
  60806         -1,
  60807     },
  60808 #endif /* chips */
  60809 
  60810 #if defined(BCM_88650_A0)
  60811     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTERr */
  60812         soc_block_list[42],
  60813         soc_genreg,
  60814         1,
  60815         0,
  60816         0x120,
  60817         SOC_REG_FLAG_RO,
  60818         0,
  60819         1,
  60820         soc_OLP_LPBK_EVENT_COUNTERr_fields,
  60821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60822         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60823         -1,
  60824         -1,
  60825     },
  60826 #endif /* chips */
  60827 
  60828 #if defined(BCM_88270_A0)
  60829     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88270_A0r */
  60830         soc_block_list[42],
  60831         soc_genreg,
  60832         1,
  60833         0,
  60834         0x126,
  60835         SOC_REG_FLAG_RO |
  60836                           SOC_REG_FLAG_SIGNAL,
  60837         0,
  60838         1,
  60839         soc_OLP_LPBK_EVENT_COUNTER_BCM88270_A0r_fields,
  60840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60841         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60842         -1,
  60843         -1,
  60844     },
  60845 #endif /* chips */
  60846 
  60847 #if defined(BCM_88375_A0)
  60848     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88375_A0r */
  60849         soc_block_list[42],
  60850         soc_genreg,
  60851         1,
  60852         0,
  60853         0x126,
  60854         SOC_REG_FLAG_RO |
  60855                           SOC_REG_FLAG_SIGNAL,
  60856         0,
  60857         1,
  60858         soc_OLP_LPBK_EVENT_COUNTER_BCM88375_A0r_fields,
  60859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60860         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60861         -1,
  60862         -1,
  60863     },
  60864 #endif /* chips */
  60865 
  60866 #if defined(BCM_88375_B0)
  60867     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88375_B0r */
  60868         soc_block_list[42],
  60869         soc_genreg,
  60870         1,
  60871         0,
  60872         0x126,
  60873         SOC_REG_FLAG_RO |
  60874                           SOC_REG_FLAG_SIGNAL,
  60875         0,
  60876         1,
  60877         soc_OLP_LPBK_EVENT_COUNTER_BCM88375_B0r_fields,
  60878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60879         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60880         -1,
  60881         -1,
  60882     },
  60883 #endif /* chips */
  60884 
  60885 #if defined(BCM_88470_A0)
  60886     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88470_A0r */
  60887         soc_block_list[42],
  60888         soc_genreg,
  60889         1,
  60890         0,
  60891         0x126,
  60892         SOC_REG_FLAG_RO |
  60893                           SOC_REG_FLAG_SIGNAL,
  60894         0,
  60895         1,
  60896         soc_OLP_LPBK_EVENT_COUNTER_BCM88470_A0r_fields,
  60897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60898         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60899         -1,
  60900         -1,
  60901     },
  60902 #endif /* chips */
  60903 
  60904 #if defined(BCM_88470_B0)
  60905     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88470_B0r */
  60906         soc_block_list[42],
  60907         soc_genreg,
  60908         1,
  60909         0,
  60910         0x126,
  60911         SOC_REG_FLAG_RO |
  60912                           SOC_REG_FLAG_SIGNAL,
  60913         0,
  60914         1,
  60915         soc_OLP_LPBK_EVENT_COUNTER_BCM88470_B0r_fields,
  60916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60917         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60918         -1,
  60919         -1,
  60920     },
  60921 #endif /* chips */
  60922 
  60923 #if defined(BCM_88650_B0)
  60924     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88650_B0r */
  60925         soc_block_list[42],
  60926         soc_genreg,
  60927         1,
  60928         0,
  60929         0x120,
  60930         SOC_REG_FLAG_RO,
  60931         0,
  60932         1,
  60933         soc_OLP_LPBK_EVENT_COUNTER_BCM88650_B0r_fields,
  60934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60935         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60936         -1,
  60937         -1,
  60938     },
  60939 #endif /* chips */
  60940 
  60941 #if defined(BCM_88660_A0)
  60942     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88660_A0r */
  60943         soc_block_list[42],
  60944         soc_genreg,
  60945         1,
  60946         0,
  60947         0x120,
  60948         SOC_REG_FLAG_RO,
  60949         0,
  60950         1,
  60951         soc_OLP_LPBK_EVENT_COUNTER_BCM88660_A0r_fields,
  60952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60953         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60954         -1,
  60955         -1,
  60956     },
  60957 #endif /* chips */
  60958 
  60959 #if defined(BCM_88675_A0)
  60960     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88675_A0r */
  60961         soc_block_list[42],
  60962         soc_genreg,
  60963         1,
  60964         0,
  60965         0x126,
  60966         SOC_REG_FLAG_RO |
  60967                           SOC_REG_FLAG_SIGNAL,
  60968         0,
  60969         1,
  60970         soc_OLP_LPBK_EVENT_COUNTER_BCM88675_A0r_fields,
  60971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60972         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60973         -1,
  60974         -1,
  60975     },
  60976 #endif /* chips */
  60977 
  60978 #if defined(BCM_88675_B0)
  60979     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88675_B0r */
  60980         soc_block_list[42],
  60981         soc_genreg,
  60982         1,
  60983         0,
  60984         0x126,
  60985         SOC_REG_FLAG_RO |
  60986                           SOC_REG_FLAG_SIGNAL,
  60987         0,
  60988         1,
  60989         soc_OLP_LPBK_EVENT_COUNTER_BCM88675_B0r_fields,
  60990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60991         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60992         -1,
  60993         -1,
  60994     },
  60995 #endif /* chips */
  60996 
  60997 #if defined(BCM_88680_A0)
  60998     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88680_A0r */
  60999         soc_block_list[42],
  61000         soc_genreg,
  61001         1,
  61002         0,
  61003         0x126,
  61004         SOC_REG_FLAG_RO |
  61005                           SOC_REG_FLAG_SIGNAL,
  61006         0,
  61007         1,
  61008         soc_OLP_LPBK_EVENT_COUNTER_BCM88680_A0r_fields,
  61009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61010         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61011         -1,
  61012         -1,
  61013     },
  61014 #endif /* chips */
  61015 
  61016 #if defined(BCM_88690_A0)
  61017     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88690_A0r */
  61018         soc_block_list[42],
  61019         soc_genreg,
  61020         1,
  61021         0,
  61022         0x148,
  61023         SOC_REG_FLAG_RO,
  61024         SOC_REG_FLAG_COUNTER_FEILDS,
  61025         1,
  61026         soc_OLP_LPBK_EVENT_COUNTER_BCM88690_A0r_fields,
  61027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61028         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61029         -1,
  61030         -1,
  61031     },
  61032 #endif /* chips */
  61033 
  61034 #if defined(BCM_88690_B0)
  61035     { /* SOC_REG_INT_OLP_LPBK_EVENT_COUNTER_BCM88690_B0r */
  61036         soc_block_list[42],
  61037         soc_genreg,
  61038         1,
  61039         0,
  61040         0x148,
  61041         SOC_REG_FLAG_RO,
  61042         SOC_REG_FLAG_COUNTER_FEILDS,
  61043         1,
  61044         soc_OLP_LPBK_EVENT_COUNTER_BCM88690_B0r_fields,
  61045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61046         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61047         -1,
  61048         -1,
  61049     },
  61050 #endif /* chips */
  61051 
  61052 #if defined(BCM_88650_B0)
  61053     { /* SOC_REG_INT_OLP_OLP_GLOBAL_REGISTERS_0r */
  61054         soc_block_list[42],
  61055         soc_genreg,
  61056         1,
  61057         0,
  61058         0xf0,
  61059         SOC_REG_FLAG_SIGNAL,
  61060         0,
  61061         3,
  61062         soc_OLP_OLP_GLOBAL_REGISTERS_0r_fields,
  61063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61064         SOC_RESET_MASK_DEC(0x0001c000, 0x00000000)
  61065         -1,
  61066         -1,
  61067     },
  61068 #endif /* chips */
  61069 
  61070 #if defined(BCM_88660_A0)
  61071     { /* SOC_REG_INT_OLP_OLP_GLOBAL_REGISTERS_0_BCM88660_A0r */
  61072         soc_block_list[42],
  61073         soc_genreg,
  61074         1,
  61075         0,
  61076         0xf0,
  61077         SOC_REG_FLAG_SIGNAL,
  61078         0,
  61079         3,
  61080         soc_OLP_OLP_GLOBAL_REGISTERS_0_BCM88660_A0r_fields,
  61081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61082         SOC_RESET_MASK_DEC(0x0001c000, 0x00000000)
  61083         -1,
  61084         -1,
  61085     },
  61086 #endif /* chips */
  61087 
  61088 #if defined(BCM_88690_B0)
  61089     { /* SOC_REG_INT_OLP_OLP_LEARN_PAYLOAD_STRENGTH_SIZEr */
  61090         soc_block_list[42],
  61091         soc_genreg,
  61092         1,
  61093         0,
  61094         0x15d,
  61095         0,
  61096         0,
  61097         1,
  61098         soc_OLP_OLP_LEARN_PAYLOAD_STRENGTH_SIZEr_fields,
  61099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61100         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  61101         -1,
  61102         -1,
  61103     },
  61104 #endif /* chips */
  61105 
  61106 #if defined(BCM_88650_A0)
  61107     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTERr */
  61108         soc_block_list[42],
  61109         soc_genreg,
  61110         1,
  61111         0,
  61112         0x123,
  61113         SOC_REG_FLAG_RO,
  61114         0,
  61115         1,
  61116         soc_OLP_OUTGOING_PACKET_COUNTERr_fields,
  61117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61118         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61119         -1,
  61120         -1,
  61121     },
  61122 #endif /* chips */
  61123 
  61124 #if defined(BCM_88270_A0)
  61125     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88270_A0r */
  61126         soc_block_list[42],
  61127         soc_genreg,
  61128         1,
  61129         0,
  61130         0x12a,
  61131         SOC_REG_FLAG_RO |
  61132                           SOC_REG_FLAG_SIGNAL,
  61133         0,
  61134         1,
  61135         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88270_A0r_fields,
  61136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61137         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61138         -1,
  61139         -1,
  61140     },
  61141 #endif /* chips */
  61142 
  61143 #if defined(BCM_88375_A0)
  61144     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88375_A0r */
  61145         soc_block_list[42],
  61146         soc_genreg,
  61147         1,
  61148         0,
  61149         0x12a,
  61150         SOC_REG_FLAG_RO |
  61151                           SOC_REG_FLAG_SIGNAL,
  61152         0,
  61153         1,
  61154         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88375_A0r_fields,
  61155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61156         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61157         -1,
  61158         -1,
  61159     },
  61160 #endif /* chips */
  61161 
  61162 #if defined(BCM_88375_B0)
  61163     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88375_B0r */
  61164         soc_block_list[42],
  61165         soc_genreg,
  61166         1,
  61167         0,
  61168         0x12a,
  61169         SOC_REG_FLAG_RO |
  61170                           SOC_REG_FLAG_SIGNAL,
  61171         0,
  61172         1,
  61173         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88375_B0r_fields,
  61174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61175         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61176         -1,
  61177         -1,
  61178     },
  61179 #endif /* chips */
  61180 
  61181 #if defined(BCM_88470_A0)
  61182     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88470_A0r */
  61183         soc_block_list[42],
  61184         soc_genreg,
  61185         1,
  61186         0,
  61187         0x12a,
  61188         SOC_REG_FLAG_RO |
  61189                           SOC_REG_FLAG_SIGNAL,
  61190         0,
  61191         1,
  61192         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88470_A0r_fields,
  61193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61194         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61195         -1,
  61196         -1,
  61197     },
  61198 #endif /* chips */
  61199 
  61200 #if defined(BCM_88470_B0)
  61201     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88470_B0r */
  61202         soc_block_list[42],
  61203         soc_genreg,
  61204         1,
  61205         0,
  61206         0x12a,
  61207         SOC_REG_FLAG_RO |
  61208                           SOC_REG_FLAG_SIGNAL,
  61209         0,
  61210         1,
  61211         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88470_B0r_fields,
  61212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61213         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61214         -1,
  61215         -1,
  61216     },
  61217 #endif /* chips */
  61218 
  61219 #if defined(BCM_88650_B0)
  61220     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88650_B0r */
  61221         soc_block_list[42],
  61222         soc_genreg,
  61223         1,
  61224         0,
  61225         0x123,
  61226         SOC_REG_FLAG_RO,
  61227         0,
  61228         1,
  61229         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88650_B0r_fields,
  61230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61231         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61232         -1,
  61233         -1,
  61234     },
  61235 #endif /* chips */
  61236 
  61237 #if defined(BCM_88660_A0)
  61238     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88660_A0r */
  61239         soc_block_list[42],
  61240         soc_genreg,
  61241         1,
  61242         0,
  61243         0x123,
  61244         SOC_REG_FLAG_RO,
  61245         0,
  61246         1,
  61247         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88660_A0r_fields,
  61248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61249         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61250         -1,
  61251         -1,
  61252     },
  61253 #endif /* chips */
  61254 
  61255 #if defined(BCM_88675_A0)
  61256     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88675_A0r */
  61257         soc_block_list[42],
  61258         soc_genreg,
  61259         1,
  61260         0,
  61261         0x12a,
  61262         SOC_REG_FLAG_RO |
  61263                           SOC_REG_FLAG_SIGNAL,
  61264         0,
  61265         1,
  61266         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88675_A0r_fields,
  61267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61268         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61269         -1,
  61270         -1,
  61271     },
  61272 #endif /* chips */
  61273 
  61274 #if defined(BCM_88675_B0)
  61275     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88675_B0r */
  61276         soc_block_list[42],
  61277         soc_genreg,
  61278         1,
  61279         0,
  61280         0x12a,
  61281         SOC_REG_FLAG_RO |
  61282                           SOC_REG_FLAG_SIGNAL,
  61283         0,
  61284         1,
  61285         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88675_B0r_fields,
  61286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61287         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61288         -1,
  61289         -1,
  61290     },
  61291 #endif /* chips */
  61292 
  61293 #if defined(BCM_88680_A0)
  61294     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88680_A0r */
  61295         soc_block_list[42],
  61296         soc_genreg,
  61297         1,
  61298         0,
  61299         0x12a,
  61300         SOC_REG_FLAG_RO |
  61301                           SOC_REG_FLAG_SIGNAL,
  61302         0,
  61303         1,
  61304         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88680_A0r_fields,
  61305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61306         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61307         -1,
  61308         -1,
  61309     },
  61310 #endif /* chips */
  61311 
  61312 #if defined(BCM_88690_A0)
  61313     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88690_A0r */
  61314         soc_block_list[42],
  61315         soc_genreg,
  61316         1,
  61317         0,
  61318         0x14c,
  61319         SOC_REG_FLAG_RO,
  61320         SOC_REG_FLAG_COUNTER_FEILDS,
  61321         1,
  61322         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88690_A0r_fields,
  61323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61324         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61325         -1,
  61326         -1,
  61327     },
  61328 #endif /* chips */
  61329 
  61330 #if defined(BCM_88690_B0)
  61331     { /* SOC_REG_INT_OLP_OUTGOING_PACKET_COUNTER_BCM88690_B0r */
  61332         soc_block_list[42],
  61333         soc_genreg,
  61334         1,
  61335         0,
  61336         0x14c,
  61337         SOC_REG_FLAG_RO,
  61338         SOC_REG_FLAG_COUNTER_FEILDS,
  61339         1,
  61340         soc_OLP_OUTGOING_PACKET_COUNTER_BCM88690_B0r_fields,
  61341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61342         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61343         -1,
  61344         -1,
  61345     },
  61346 #endif /* chips */
  61347 
  61348 #if defined(BCM_88650_A0)
  61349     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTERr */
  61350         soc_block_list[42],
  61351         soc_genreg,
  61352         1,
  61353         0,
  61354         0x129,
  61355         SOC_REG_FLAG_RO,
  61356         0,
  61357         1,
  61358         soc_OLP_OUTGOING_REQUEST_COUNTERr_fields,
  61359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61360         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61361         -1,
  61362         -1,
  61363     },
  61364 #endif /* chips */
  61365 
  61366 #if defined(BCM_88270_A0)
  61367     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88270_A0r */
  61368         soc_block_list[42],
  61369         soc_genreg,
  61370         1,
  61371         0,
  61372         0x130,
  61373         SOC_REG_FLAG_RO |
  61374                           SOC_REG_FLAG_SIGNAL,
  61375         0,
  61376         1,
  61377         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88270_A0r_fields,
  61378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61379         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61380         -1,
  61381         -1,
  61382     },
  61383 #endif /* chips */
  61384 
  61385 #if defined(BCM_88375_A0)
  61386     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88375_A0r */
  61387         soc_block_list[42],
  61388         soc_genreg,
  61389         1,
  61390         0,
  61391         0x130,
  61392         SOC_REG_FLAG_RO |
  61393                           SOC_REG_FLAG_SIGNAL,
  61394         0,
  61395         1,
  61396         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88375_A0r_fields,
  61397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61398         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61399         -1,
  61400         -1,
  61401     },
  61402 #endif /* chips */
  61403 
  61404 #if defined(BCM_88375_B0)
  61405     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88375_B0r */
  61406         soc_block_list[42],
  61407         soc_genreg,
  61408         1,
  61409         0,
  61410         0x130,
  61411         SOC_REG_FLAG_RO |
  61412                           SOC_REG_FLAG_SIGNAL,
  61413         0,
  61414         1,
  61415         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88375_B0r_fields,
  61416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61417         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61418         -1,
  61419         -1,
  61420     },
  61421 #endif /* chips */
  61422 
  61423 #if defined(BCM_88470_A0)
  61424     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88470_A0r */
  61425         soc_block_list[42],
  61426         soc_genreg,
  61427         1,
  61428         0,
  61429         0x130,
  61430         SOC_REG_FLAG_RO |
  61431                           SOC_REG_FLAG_SIGNAL,
  61432         0,
  61433         1,
  61434         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88470_A0r_fields,
  61435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61436         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61437         -1,
  61438         -1,
  61439     },
  61440 #endif /* chips */
  61441 
  61442 #if defined(BCM_88470_B0)
  61443     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88470_B0r */
  61444         soc_block_list[42],
  61445         soc_genreg,
  61446         1,
  61447         0,
  61448         0x130,
  61449         SOC_REG_FLAG_RO |
  61450                           SOC_REG_FLAG_SIGNAL,
  61451         0,
  61452         1,
  61453         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88470_B0r_fields,
  61454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61455         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61456         -1,
  61457         -1,
  61458     },
  61459 #endif /* chips */
  61460 
  61461 #if defined(BCM_88650_B0)
  61462     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88650_B0r */
  61463         soc_block_list[42],
  61464         soc_genreg,
  61465         1,
  61466         0,
  61467         0x129,
  61468         SOC_REG_FLAG_RO,
  61469         0,
  61470         1,
  61471         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88650_B0r_fields,
  61472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61473         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61474         -1,
  61475         -1,
  61476     },
  61477 #endif /* chips */
  61478 
  61479 #if defined(BCM_88660_A0)
  61480     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88660_A0r */
  61481         soc_block_list[42],
  61482         soc_genreg,
  61483         1,
  61484         0,
  61485         0x129,
  61486         SOC_REG_FLAG_RO,
  61487         0,
  61488         1,
  61489         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88660_A0r_fields,
  61490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61491         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61492         -1,
  61493         -1,
  61494     },
  61495 #endif /* chips */
  61496 
  61497 #if defined(BCM_88675_A0)
  61498     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88675_A0r */
  61499         soc_block_list[42],
  61500         soc_genreg,
  61501         1,
  61502         0,
  61503         0x130,
  61504         SOC_REG_FLAG_RO |
  61505                           SOC_REG_FLAG_SIGNAL,
  61506         0,
  61507         1,
  61508         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88675_A0r_fields,
  61509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61510         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61511         -1,
  61512         -1,
  61513     },
  61514 #endif /* chips */
  61515 
  61516 #if defined(BCM_88675_B0)
  61517     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88675_B0r */
  61518         soc_block_list[42],
  61519         soc_genreg,
  61520         1,
  61521         0,
  61522         0x130,
  61523         SOC_REG_FLAG_RO |
  61524                           SOC_REG_FLAG_SIGNAL,
  61525         0,
  61526         1,
  61527         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88675_B0r_fields,
  61528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61529         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61530         -1,
  61531         -1,
  61532     },
  61533 #endif /* chips */
  61534 
  61535 #if defined(BCM_88680_A0)
  61536     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88680_A0r */
  61537         soc_block_list[42],
  61538         soc_genreg,
  61539         1,
  61540         0,
  61541         0x130,
  61542         SOC_REG_FLAG_RO |
  61543                           SOC_REG_FLAG_SIGNAL,
  61544         0,
  61545         1,
  61546         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88680_A0r_fields,
  61547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61548         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61549         -1,
  61550         -1,
  61551     },
  61552 #endif /* chips */
  61553 
  61554 #if defined(BCM_88690_A0)
  61555     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88690_A0r */
  61556         soc_block_list[42],
  61557         soc_genreg,
  61558         1,
  61559         0,
  61560         0x152,
  61561         SOC_REG_FLAG_RO,
  61562         SOC_REG_FLAG_COUNTER_FEILDS,
  61563         1,
  61564         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88690_A0r_fields,
  61565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61566         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61567         -1,
  61568         -1,
  61569     },
  61570 #endif /* chips */
  61571 
  61572 #if defined(BCM_88690_B0)
  61573     { /* SOC_REG_INT_OLP_OUTGOING_REQUEST_COUNTER_BCM88690_B0r */
  61574         soc_block_list[42],
  61575         soc_genreg,
  61576         1,
  61577         0,
  61578         0x152,
  61579         SOC_REG_FLAG_RO,
  61580         SOC_REG_FLAG_COUNTER_FEILDS,
  61581         1,
  61582         soc_OLP_OUTGOING_REQUEST_COUNTER_BCM88690_B0r_fields,
  61583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61584         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61585         -1,
  61586         -1,
  61587     },
  61588 #endif /* chips */
  61589 
  61590 #if defined(BCM_88650_A0)
  61591     { /* SOC_REG_INT_OLP_PARITY_ERR_CNTr */
  61592         soc_block_list[42],
  61593         soc_genreg,
  61594         1,
  61595         0,
  61596         0x98,
  61597         SOC_REG_FLAG_64_BITS |
  61598                           SOC_REG_FLAG_RO,
  61599         0,
  61600         4,
  61601         soc_OLP_PARITY_ERR_CNTr_fields,
  61602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61603         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61604         -1,
  61605         -1,
  61606     },
  61607 #endif /* chips */
  61608 
  61609 #if defined(BCM_88270_A0)
  61610     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88270_A0r */
  61611         soc_block_list[42],
  61612         soc_genreg,
  61613         1,
  61614         0,
  61615         0x98,
  61616         SOC_REG_FLAG_64_BITS |
  61617                           SOC_REG_FLAG_RO,
  61618         0,
  61619         4,
  61620         soc_OLP_PARITY_ERR_CNT_BCM88270_A0r_fields,
  61621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61622         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61623         -1,
  61624         -1,
  61625     },
  61626 #endif /* chips */
  61627 
  61628 #if defined(BCM_88375_A0)
  61629     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88375_A0r */
  61630         soc_block_list[42],
  61631         soc_genreg,
  61632         1,
  61633         0,
  61634         0x98,
  61635         SOC_REG_FLAG_64_BITS |
  61636                           SOC_REG_FLAG_RO,
  61637         0,
  61638         4,
  61639         soc_OLP_PARITY_ERR_CNT_BCM88375_A0r_fields,
  61640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61641         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61642         -1,
  61643         -1,
  61644     },
  61645 #endif /* chips */
  61646 
  61647 #if defined(BCM_88375_B0)
  61648     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88375_B0r */
  61649         soc_block_list[42],
  61650         soc_genreg,
  61651         1,
  61652         0,
  61653         0x98,
  61654         SOC_REG_FLAG_64_BITS |
  61655                           SOC_REG_FLAG_RO,
  61656         0,
  61657         4,
  61658         soc_OLP_PARITY_ERR_CNT_BCM88375_B0r_fields,
  61659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61660         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61661         -1,
  61662         -1,
  61663     },
  61664 #endif /* chips */
  61665 
  61666 #if defined(BCM_88470_A0)
  61667     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88470_A0r */
  61668         soc_block_list[42],
  61669         soc_genreg,
  61670         1,
  61671         0,
  61672         0x98,
  61673         SOC_REG_FLAG_64_BITS |
  61674                           SOC_REG_FLAG_RO,
  61675         0,
  61676         4,
  61677         soc_OLP_PARITY_ERR_CNT_BCM88470_A0r_fields,
  61678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61679         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61680         -1,
  61681         -1,
  61682     },
  61683 #endif /* chips */
  61684 
  61685 #if defined(BCM_88470_B0)
  61686     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88470_B0r */
  61687         soc_block_list[42],
  61688         soc_genreg,
  61689         1,
  61690         0,
  61691         0x98,
  61692         SOC_REG_FLAG_64_BITS |
  61693                           SOC_REG_FLAG_RO,
  61694         0,
  61695         4,
  61696         soc_OLP_PARITY_ERR_CNT_BCM88470_B0r_fields,
  61697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61698         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61699         -1,
  61700         -1,
  61701     },
  61702 #endif /* chips */
  61703 
  61704 #if defined(BCM_88650_B0)
  61705     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88650_B0r */
  61706         soc_block_list[42],
  61707         soc_genreg,
  61708         1,
  61709         0,
  61710         0x98,
  61711         SOC_REG_FLAG_64_BITS |
  61712                           SOC_REG_FLAG_RO,
  61713         0,
  61714         4,
  61715         soc_OLP_PARITY_ERR_CNT_BCM88650_B0r_fields,
  61716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61717         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61718         -1,
  61719         -1,
  61720     },
  61721 #endif /* chips */
  61722 
  61723 #if defined(BCM_88660_A0)
  61724     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88660_A0r */
  61725         soc_block_list[42],
  61726         soc_genreg,
  61727         1,
  61728         0,
  61729         0x98,
  61730         SOC_REG_FLAG_64_BITS |
  61731                           SOC_REG_FLAG_RO,
  61732         0,
  61733         4,
  61734         soc_OLP_PARITY_ERR_CNT_BCM88660_A0r_fields,
  61735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61736         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61737         -1,
  61738         -1,
  61739     },
  61740 #endif /* chips */
  61741 
  61742 #if defined(BCM_88675_A0)
  61743     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88675_A0r */
  61744         soc_block_list[42],
  61745         soc_genreg,
  61746         1,
  61747         0,
  61748         0x98,
  61749         SOC_REG_FLAG_64_BITS |
  61750                           SOC_REG_FLAG_RO,
  61751         0,
  61752         4,
  61753         soc_OLP_PARITY_ERR_CNT_BCM88675_A0r_fields,
  61754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61755         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61756         -1,
  61757         -1,
  61758     },
  61759 #endif /* chips */
  61760 
  61761 #if defined(BCM_88675_B0)
  61762     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88675_B0r */
  61763         soc_block_list[42],
  61764         soc_genreg,
  61765         1,
  61766         0,
  61767         0x98,
  61768         SOC_REG_FLAG_64_BITS |
  61769                           SOC_REG_FLAG_RO,
  61770         0,
  61771         4,
  61772         soc_OLP_PARITY_ERR_CNT_BCM88675_B0r_fields,
  61773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61774         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61775         -1,
  61776         -1,
  61777     },
  61778 #endif /* chips */
  61779 
  61780 #if defined(BCM_88680_A0)
  61781     { /* SOC_REG_INT_OLP_PARITY_ERR_CNT_BCM88680_A0r */
  61782         soc_block_list[42],
  61783         soc_genreg,
  61784         1,
  61785         0,
  61786         0x98,
  61787         SOC_REG_FLAG_64_BITS |
  61788                           SOC_REG_FLAG_RO,
  61789         0,
  61790         4,
  61791         soc_OLP_PARITY_ERR_CNT_BCM88680_A0r_fields,
  61792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61793         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  61794         -1,
  61795         -1,
  61796     },
  61797 #endif /* chips */
  61798 
  61799 #if defined(BCM_88650_A0)
  61800     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATEr */
  61801         soc_block_list[42],
  61802         soc_genreg,
  61803         1,
  61804         0,
  61805         0xaa,
  61806         SOC_REG_FLAG_SIGNAL,
  61807         0,
  61808         3,
  61809         soc_OLP_PAR_ERR_INITIATEr_fields,
  61810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61811         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  61812         -1,
  61813         -1,
  61814     },
  61815 #endif /* chips */
  61816 
  61817 #if defined(BCM_88270_A0)
  61818     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88270_A0r */
  61819         soc_block_list[42],
  61820         soc_genreg,
  61821         1,
  61822         0,
  61823         0xaa,
  61824         0,
  61825         0,
  61826         1,
  61827         soc_OLP_PAR_ERR_INITIATE_BCM88270_A0r_fields,
  61828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61829         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61830         -1,
  61831         -1,
  61832     },
  61833 #endif /* chips */
  61834 
  61835 #if defined(BCM_88375_A0)
  61836     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88375_A0r */
  61837         soc_block_list[42],
  61838         soc_genreg,
  61839         1,
  61840         0,
  61841         0xaa,
  61842         0,
  61843         0,
  61844         1,
  61845         soc_OLP_PAR_ERR_INITIATE_BCM88375_A0r_fields,
  61846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61847         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61848         -1,
  61849         -1,
  61850     },
  61851 #endif /* chips */
  61852 
  61853 #if defined(BCM_88375_B0)
  61854     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88375_B0r */
  61855         soc_block_list[42],
  61856         soc_genreg,
  61857         1,
  61858         0,
  61859         0xaa,
  61860         0,
  61861         0,
  61862         1,
  61863         soc_OLP_PAR_ERR_INITIATE_BCM88375_B0r_fields,
  61864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61865         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61866         -1,
  61867         -1,
  61868     },
  61869 #endif /* chips */
  61870 
  61871 #if defined(BCM_88470_A0)
  61872     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88470_A0r */
  61873         soc_block_list[42],
  61874         soc_genreg,
  61875         1,
  61876         0,
  61877         0xaa,
  61878         0,
  61879         0,
  61880         1,
  61881         soc_OLP_PAR_ERR_INITIATE_BCM88470_A0r_fields,
  61882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61883         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61884         -1,
  61885         -1,
  61886     },
  61887 #endif /* chips */
  61888 
  61889 #if defined(BCM_88470_B0)
  61890     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88470_B0r */
  61891         soc_block_list[42],
  61892         soc_genreg,
  61893         1,
  61894         0,
  61895         0xaa,
  61896         0,
  61897         0,
  61898         1,
  61899         soc_OLP_PAR_ERR_INITIATE_BCM88470_B0r_fields,
  61900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61901         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61902         -1,
  61903         -1,
  61904     },
  61905 #endif /* chips */
  61906 
  61907 #if defined(BCM_88650_B0)
  61908     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88650_B0r */
  61909         soc_block_list[42],
  61910         soc_genreg,
  61911         1,
  61912         0,
  61913         0xaa,
  61914         SOC_REG_FLAG_SIGNAL,
  61915         0,
  61916         3,
  61917         soc_OLP_PAR_ERR_INITIATE_BCM88650_B0r_fields,
  61918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61919         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  61920         -1,
  61921         -1,
  61922     },
  61923 #endif /* chips */
  61924 
  61925 #if defined(BCM_88660_A0)
  61926     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88660_A0r */
  61927         soc_block_list[42],
  61928         soc_genreg,
  61929         1,
  61930         0,
  61931         0xaa,
  61932         SOC_REG_FLAG_SIGNAL,
  61933         0,
  61934         3,
  61935         soc_OLP_PAR_ERR_INITIATE_BCM88660_A0r_fields,
  61936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61937         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  61938         -1,
  61939         -1,
  61940     },
  61941 #endif /* chips */
  61942 
  61943 #if defined(BCM_88675_A0)
  61944     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88675_A0r */
  61945         soc_block_list[42],
  61946         soc_genreg,
  61947         1,
  61948         0,
  61949         0xaa,
  61950         0,
  61951         0,
  61952         1,
  61953         soc_OLP_PAR_ERR_INITIATE_BCM88675_A0r_fields,
  61954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61955         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61956         -1,
  61957         -1,
  61958     },
  61959 #endif /* chips */
  61960 
  61961 #if defined(BCM_88675_B0)
  61962     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88675_B0r */
  61963         soc_block_list[42],
  61964         soc_genreg,
  61965         1,
  61966         0,
  61967         0xaa,
  61968         0,
  61969         0,
  61970         1,
  61971         soc_OLP_PAR_ERR_INITIATE_BCM88675_B0r_fields,
  61972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61973         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61974         -1,
  61975         -1,
  61976     },
  61977 #endif /* chips */
  61978 
  61979 #if defined(BCM_88680_A0)
  61980     { /* SOC_REG_INT_OLP_PAR_ERR_INITIATE_BCM88680_A0r */
  61981         soc_block_list[42],
  61982         soc_genreg,
  61983         1,
  61984         0,
  61985         0xaa,
  61986         0,
  61987         0,
  61988         1,
  61989         soc_OLP_PAR_ERR_INITIATE_BCM88680_A0r_fields,
  61990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61991         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61992         -1,
  61993         -1,
  61994     },
  61995 #endif /* chips */
  61996 
  61997 #if defined(BCM_88650_A0)
  61998     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASKr */
  61999         soc_block_list[42],
  62000         soc_genreg,
  62001         1,
  62002         0,
  62003         0xa0,
  62004         SOC_REG_FLAG_SIGNAL,
  62005         0,
  62006         3,
  62007         soc_OLP_PAR_ERR_MEM_MASKr_fields,
  62008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62009         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62010         -1,
  62011         -1,
  62012     },
  62013 #endif /* chips */
  62014 
  62015 #if defined(BCM_88270_A0)
  62016     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88270_A0r */
  62017         soc_block_list[42],
  62018         soc_genreg,
  62019         1,
  62020         0,
  62021         0xa0,
  62022         0,
  62023         0,
  62024         1,
  62025         soc_OLP_PAR_ERR_MEM_MASK_BCM88270_A0r_fields,
  62026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62027         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62028         -1,
  62029         -1,
  62030     },
  62031 #endif /* chips */
  62032 
  62033 #if defined(BCM_88375_A0)
  62034     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88375_A0r */
  62035         soc_block_list[42],
  62036         soc_genreg,
  62037         1,
  62038         0,
  62039         0xa0,
  62040         0,
  62041         0,
  62042         1,
  62043         soc_OLP_PAR_ERR_MEM_MASK_BCM88375_A0r_fields,
  62044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62045         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62046         -1,
  62047         -1,
  62048     },
  62049 #endif /* chips */
  62050 
  62051 #if defined(BCM_88375_B0)
  62052     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88375_B0r */
  62053         soc_block_list[42],
  62054         soc_genreg,
  62055         1,
  62056         0,
  62057         0xa0,
  62058         0,
  62059         0,
  62060         1,
  62061         soc_OLP_PAR_ERR_MEM_MASK_BCM88375_B0r_fields,
  62062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62063         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62064         -1,
  62065         -1,
  62066     },
  62067 #endif /* chips */
  62068 
  62069 #if defined(BCM_88470_A0)
  62070     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88470_A0r */
  62071         soc_block_list[42],
  62072         soc_genreg,
  62073         1,
  62074         0,
  62075         0xa0,
  62076         0,
  62077         0,
  62078         1,
  62079         soc_OLP_PAR_ERR_MEM_MASK_BCM88470_A0r_fields,
  62080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62081         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62082         -1,
  62083         -1,
  62084     },
  62085 #endif /* chips */
  62086 
  62087 #if defined(BCM_88470_B0)
  62088     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88470_B0r */
  62089         soc_block_list[42],
  62090         soc_genreg,
  62091         1,
  62092         0,
  62093         0xa0,
  62094         0,
  62095         0,
  62096         1,
  62097         soc_OLP_PAR_ERR_MEM_MASK_BCM88470_B0r_fields,
  62098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62099         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62100         -1,
  62101         -1,
  62102     },
  62103 #endif /* chips */
  62104 
  62105 #if defined(BCM_88650_B0)
  62106     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88650_B0r */
  62107         soc_block_list[42],
  62108         soc_genreg,
  62109         1,
  62110         0,
  62111         0xa0,
  62112         SOC_REG_FLAG_SIGNAL,
  62113         0,
  62114         3,
  62115         soc_OLP_PAR_ERR_MEM_MASK_BCM88650_B0r_fields,
  62116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62117         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62118         -1,
  62119         -1,
  62120     },
  62121 #endif /* chips */
  62122 
  62123 #if defined(BCM_88660_A0)
  62124     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88660_A0r */
  62125         soc_block_list[42],
  62126         soc_genreg,
  62127         1,
  62128         0,
  62129         0xa0,
  62130         SOC_REG_FLAG_SIGNAL,
  62131         0,
  62132         3,
  62133         soc_OLP_PAR_ERR_MEM_MASK_BCM88660_A0r_fields,
  62134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62135         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62136         -1,
  62137         -1,
  62138     },
  62139 #endif /* chips */
  62140 
  62141 #if defined(BCM_88675_A0)
  62142     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88675_A0r */
  62143         soc_block_list[42],
  62144         soc_genreg,
  62145         1,
  62146         0,
  62147         0xa0,
  62148         0,
  62149         0,
  62150         1,
  62151         soc_OLP_PAR_ERR_MEM_MASK_BCM88675_A0r_fields,
  62152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62153         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62154         -1,
  62155         -1,
  62156     },
  62157 #endif /* chips */
  62158 
  62159 #if defined(BCM_88675_B0)
  62160     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88675_B0r */
  62161         soc_block_list[42],
  62162         soc_genreg,
  62163         1,
  62164         0,
  62165         0xa0,
  62166         0,
  62167         0,
  62168         1,
  62169         soc_OLP_PAR_ERR_MEM_MASK_BCM88675_B0r_fields,
  62170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62171         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62172         -1,
  62173         -1,
  62174     },
  62175 #endif /* chips */
  62176 
  62177 #if defined(BCM_88680_A0)
  62178     { /* SOC_REG_INT_OLP_PAR_ERR_MEM_MASK_BCM88680_A0r */
  62179         soc_block_list[42],
  62180         soc_genreg,
  62181         1,
  62182         0,
  62183         0xa0,
  62184         0,
  62185         0,
  62186         1,
  62187         soc_OLP_PAR_ERR_MEM_MASK_BCM88680_A0r_fields,
  62188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62189         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62190         -1,
  62191         -1,
  62192     },
  62193 #endif /* chips */
  62194 
  62195 #if defined(BCM_88675_A0)
  62196     { /* SOC_REG_INT_OLP_PIPE_SELECTr */
  62197         soc_block_list[42],
  62198         soc_genreg,
  62199         1,
  62200         0,
  62201         0x101,
  62202         0,
  62203         0,
  62204         3,
  62205         soc_OLP_PIPE_SELECTr_fields,
  62206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62207         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62208         -1,
  62209         -1,
  62210     },
  62211 #endif /* chips */
  62212 
  62213 #if defined(BCM_88270_A0)
  62214     { /* SOC_REG_INT_OLP_PIPE_SELECT_BCM88270_A0r */
  62215         soc_block_list[42],
  62216         soc_genreg,
  62217         1,
  62218         0,
  62219         0x101,
  62220         0,
  62221         0,
  62222         3,
  62223         soc_OLP_PIPE_SELECT_BCM88270_A0r_fields,
  62224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62225         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62226         -1,
  62227         -1,
  62228     },
  62229 #endif /* chips */
  62230 
  62231 #if defined(BCM_88375_A0)
  62232     { /* SOC_REG_INT_OLP_PIPE_SELECT_BCM88375_A0r */
  62233         soc_block_list[42],
  62234         soc_genreg,
  62235         1,
  62236         0,
  62237         0x101,
  62238         0,
  62239         0,
  62240         3,
  62241         soc_OLP_PIPE_SELECT_BCM88375_A0r_fields,
  62242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62243         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62244         -1,
  62245         -1,
  62246     },
  62247 #endif /* chips */
  62248 
  62249 #if defined(BCM_88375_B0)
  62250     { /* SOC_REG_INT_OLP_PIPE_SELECT_BCM88375_B0r */
  62251         soc_block_list[42],
  62252         soc_genreg,
  62253         1,
  62254         0,
  62255         0x101,
  62256         0,
  62257         0,
  62258         3,
  62259         soc_OLP_PIPE_SELECT_BCM88375_B0r_fields,
  62260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62261         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62262         -1,
  62263         -1,
  62264     },
  62265 #endif /* chips */
  62266 
  62267 #if defined(BCM_88470_A0)
  62268     { /* SOC_REG_INT_OLP_PIPE_SELECT_BCM88470_A0r */
  62269         soc_block_list[42],
  62270         soc_genreg,
  62271         1,
  62272         0,
  62273         0x101,
  62274         0,
  62275         0,
  62276         3,
  62277         soc_OLP_PIPE_SELECT_BCM88470_A0r_fields,
  62278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62279         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62280         -1,
  62281         -1,
  62282     },
  62283 #endif /* chips */
  62284 
  62285 #if defined(BCM_88470_B0)
  62286     { /* SOC_REG_INT_OLP_PIPE_SELECT_BCM88470_B0r */
  62287         soc_block_list[42],
  62288         soc_genreg,
  62289         1,
  62290         0,
  62291         0x101,
  62292         0,
  62293         0,
  62294         3,
  62295         soc_OLP_PIPE_SELECT_BCM88470_B0r_fields,
  62296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62297         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62298         -1,
  62299         -1,
  62300     },
  62301 #endif /* chips */
  62302 
  62303 #if defined(BCM_88675_B0)
  62304     { /* SOC_REG_INT_OLP_PIPE_SELECT_BCM88675_B0r */
  62305         soc_block_list[42],
  62306         soc_genreg,
  62307         1,
  62308         0,
  62309         0x101,
  62310         0,
  62311         0,
  62312         3,
  62313         soc_OLP_PIPE_SELECT_BCM88675_B0r_fields,
  62314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62315         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62316         -1,
  62317         -1,
  62318     },
  62319 #endif /* chips */
  62320 
  62321 #if defined(BCM_88680_A0)
  62322     { /* SOC_REG_INT_OLP_PIPE_SELECT_BCM88680_A0r */
  62323         soc_block_list[42],
  62324         soc_genreg,
  62325         1,
  62326         0,
  62327         0x101,
  62328         0,
  62329         0,
  62330         3,
  62331         soc_OLP_PIPE_SELECT_BCM88680_A0r_fields,
  62332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62333         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62334         -1,
  62335         -1,
  62336     },
  62337 #endif /* chips */
  62338 
  62339 #if defined(BCM_88690_A0)
  62340     { /* SOC_REG_INT_OLP_PIPE_SELECT_BCM88690_A0r */
  62341         soc_block_list[42],
  62342         soc_genreg,
  62343         1,
  62344         0,
  62345         0x10f,
  62346         0,
  62347         0,
  62348         3,
  62349         soc_OLP_PIPE_SELECT_BCM88690_A0r_fields,
  62350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62351         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62352         -1,
  62353         -1,
  62354     },
  62355 #endif /* chips */
  62356 
  62357 #if defined(BCM_88690_B0)
  62358     { /* SOC_REG_INT_OLP_PIPE_SELECT_BCM88690_B0r */
  62359         soc_block_list[42],
  62360         soc_genreg,
  62361         1,
  62362         0,
  62363         0x10f,
  62364         0,
  62365         0,
  62366         3,
  62367         soc_OLP_PIPE_SELECT_BCM88690_B0r_fields,
  62368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62369         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62370         -1,
  62371         -1,
  62372     },
  62373 #endif /* chips */
  62374 
  62375 #if defined(BCM_88690_A0)
  62376     { /* SOC_REG_INT_OLP_REG_0041r */
  62377         soc_block_list[42],
  62378         soc_genreg,
  62379         1,
  62380         0,
  62381         0x41,
  62382         0,
  62383         0,
  62384         1,
  62385         soc_OLP_REG_0041r_fields,
  62386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62387         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62388         -1,
  62389         -1,
  62390     },
  62391 #endif /* chips */
  62392 
  62393 #if defined(BCM_88650_A0)
  62394     { /* SOC_REG_INT_OLP_REG_0085r */
  62395         soc_block_list[42],
  62396         soc_genreg,
  62397         1,
  62398         0,
  62399         0x85,
  62400         0,
  62401         0,
  62402         2,
  62403         soc_OLP_REG_0085r_fields,
  62404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62405         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  62406         -1,
  62407         -1,
  62408     },
  62409 #endif /* chips */
  62410 
  62411 #if defined(BCM_88650_A0)
  62412     { /* SOC_REG_INT_OLP_REG_0090r */
  62413         soc_block_list[42],
  62414         soc_genreg,
  62415         1,
  62416         0,
  62417         0x90,
  62418         SOC_REG_FLAG_SIGNAL,
  62419         0,
  62420         1,
  62421         soc_OLP_REG_0090r_fields,
  62422         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  62423         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62424         -1,
  62425         -1,
  62426     },
  62427 #endif /* chips */
  62428 
  62429 #if defined(BCM_88650_A0)
  62430     { /* SOC_REG_INT_OLP_REG_0091r */
  62431         soc_block_list[42],
  62432         soc_genreg,
  62433         1,
  62434         0,
  62435         0x91,
  62436         SOC_REG_FLAG_SIGNAL,
  62437         0,
  62438         1,
  62439         soc_OLP_REG_0091r_fields,
  62440         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  62441         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62442         -1,
  62443         -1,
  62444     },
  62445 #endif /* chips */
  62446 
  62447 #if defined(BCM_88650_A0)
  62448     { /* SOC_REG_INT_OLP_REG_0092r */
  62449         soc_block_list[42],
  62450         soc_genreg,
  62451         1,
  62452         0,
  62453         0x92,
  62454         SOC_REG_FLAG_SIGNAL,
  62455         0,
  62456         1,
  62457         soc_OLP_REG_0092r_fields,
  62458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62459         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62460         -1,
  62461         -1,
  62462     },
  62463 #endif /* chips */
  62464 
  62465 #if defined(BCM_88650_A0)
  62466     { /* SOC_REG_INT_OLP_REG_0093r */
  62467         soc_block_list[42],
  62468         soc_genreg,
  62469         1,
  62470         0,
  62471         0x93,
  62472         SOC_REG_FLAG_SIGNAL,
  62473         0,
  62474         1,
  62475         soc_OLP_REG_0093r_fields,
  62476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62478         -1,
  62479         -1,
  62480     },
  62481 #endif /* chips */
  62482 
  62483 #if defined(BCM_88690_A0)
  62484     { /* SOC_REG_INT_OLP_REG_0098r */
  62485         soc_block_list[42],
  62486         soc_genreg,
  62487         1,
  62488         0,
  62489         0x98,
  62490         SOC_REG_FLAG_64_BITS |
  62491                           SOC_REG_FLAG_RO,
  62492         SOC_REG_FLAG_COUNTER_FEILDS |
  62493                           SOC_REG_FLAG_INIT_ON_READ,
  62494         4,
  62495         soc_OLP_REG_0098r_fields,
  62496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62497         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62498         -1,
  62499         -1,
  62500     },
  62501 #endif /* chips */
  62502 
  62503 #if defined(BCM_88650_A0)
  62504     { /* SOC_REG_INT_OLP_REG_0100r */
  62505         soc_block_list[42],
  62506         soc_genreg,
  62507         1,
  62508         0,
  62509         0x100,
  62510         SOC_REG_FLAG_SIGNAL,
  62511         0,
  62512         6,
  62513         soc_OLP_REG_0100r_fields,
  62514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62515         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  62516         -1,
  62517         -1,
  62518     },
  62519 #endif /* chips */
  62520 
  62521 #if defined(BCM_88650_A0)
  62522     { /* SOC_REG_INT_OLP_REG_0109r */
  62523         soc_block_list[42],
  62524         soc_genreg,
  62525         2,
  62526         0,
  62527         0x109,
  62528         SOC_REG_FLAG_ARRAY |
  62529                           SOC_REG_FLAG_RO |
  62530                           SOC_REG_FLAG_REG_ARRAY,
  62531         0,
  62532         1,
  62533         soc_OLP_REG_0109r_fields,
  62534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62535         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  62536         -1,
  62537         -1,
  62538     },
  62539 #endif /* chips */
  62540 
  62541 #if defined(BCM_88675_A0)
  62542     { /* SOC_REG_INT_OLP_REG_0111r */
  62543         soc_block_list[42],
  62544         soc_genreg,
  62545         1,
  62546         0,
  62547         0x111,
  62548         SOC_REG_FLAG_RO |
  62549                           SOC_REG_FLAG_SIGNAL,
  62550         0,
  62551         1,
  62552         soc_OLP_REG_0111r_fields,
  62553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62554         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  62555         -1,
  62556         -1,
  62557     },
  62558 #endif /* chips */
  62559 
  62560 #if defined(BCM_88675_A0)
  62561     { /* SOC_REG_INT_OLP_REG_0112r */
  62562         soc_block_list[42],
  62563         soc_genreg,
  62564         1,
  62565         0,
  62566         0x112,
  62567         SOC_REG_FLAG_RO |
  62568                           SOC_REG_FLAG_SIGNAL,
  62569         0,
  62570         1,
  62571         soc_OLP_REG_0112r_fields,
  62572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62573         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  62574         -1,
  62575         -1,
  62576     },
  62577 #endif /* chips */
  62578 
  62579 #if defined(BCM_88690_B0)
  62580     { /* SOC_REG_INT_OLP_REG_0041_BCM88690_B0r */
  62581         soc_block_list[42],
  62582         soc_genreg,
  62583         1,
  62584         0,
  62585         0x41,
  62586         0,
  62587         0,
  62588         1,
  62589         soc_OLP_REG_0041_BCM88690_B0r_fields,
  62590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62591         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62592         -1,
  62593         -1,
  62594     },
  62595 #endif /* chips */
  62596 
  62597 #if defined(BCM_88650_B0)
  62598     { /* SOC_REG_INT_OLP_REG_0085_BCM88650_B0r */
  62599         soc_block_list[42],
  62600         soc_genreg,
  62601         1,
  62602         0,
  62603         0x85,
  62604         0,
  62605         0,
  62606         2,
  62607         soc_OLP_REG_0085_BCM88650_B0r_fields,
  62608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62609         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  62610         -1,
  62611         -1,
  62612     },
  62613 #endif /* chips */
  62614 
  62615 #if defined(BCM_88660_A0)
  62616     { /* SOC_REG_INT_OLP_REG_0085_BCM88660_A0r */
  62617         soc_block_list[42],
  62618         soc_genreg,
  62619         1,
  62620         0,
  62621         0x85,
  62622         0,
  62623         0,
  62624         2,
  62625         soc_OLP_REG_0085_BCM88660_A0r_fields,
  62626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62627         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  62628         -1,
  62629         -1,
  62630     },
  62631 #endif /* chips */
  62632 
  62633 #if defined(BCM_88650_B0)
  62634     { /* SOC_REG_INT_OLP_REG_0090_BCM88650_B0r */
  62635         soc_block_list[42],
  62636         soc_genreg,
  62637         1,
  62638         0,
  62639         0x90,
  62640         SOC_REG_FLAG_SIGNAL,
  62641         0,
  62642         1,
  62643         soc_OLP_REG_0090_BCM88650_B0r_fields,
  62644         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  62645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62646         -1,
  62647         -1,
  62648     },
  62649 #endif /* chips */
  62650 
  62651 #if defined(BCM_88660_A0)
  62652     { /* SOC_REG_INT_OLP_REG_0090_BCM88660_A0r */
  62653         soc_block_list[42],
  62654         soc_genreg,
  62655         1,
  62656         0,
  62657         0x90,
  62658         SOC_REG_FLAG_SIGNAL,
  62659         0,
  62660         1,
  62661         soc_OLP_REG_0090_BCM88660_A0r_fields,
  62662         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  62663         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62664         -1,
  62665         -1,
  62666     },
  62667 #endif /* chips */
  62668 
  62669 #if defined(BCM_88650_B0)
  62670     { /* SOC_REG_INT_OLP_REG_0091_BCM88650_B0r */
  62671         soc_block_list[42],
  62672         soc_genreg,
  62673         1,
  62674         0,
  62675         0x91,
  62676         SOC_REG_FLAG_SIGNAL,
  62677         0,
  62678         1,
  62679         soc_OLP_REG_0091_BCM88650_B0r_fields,
  62680         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  62681         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62682         -1,
  62683         -1,
  62684     },
  62685 #endif /* chips */
  62686 
  62687 #if defined(BCM_88660_A0)
  62688     { /* SOC_REG_INT_OLP_REG_0091_BCM88660_A0r */
  62689         soc_block_list[42],
  62690         soc_genreg,
  62691         1,
  62692         0,
  62693         0x91,
  62694         SOC_REG_FLAG_SIGNAL,
  62695         0,
  62696         1,
  62697         soc_OLP_REG_0091_BCM88660_A0r_fields,
  62698         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  62699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62700         -1,
  62701         -1,
  62702     },
  62703 #endif /* chips */
  62704 
  62705 #if defined(BCM_88650_B0)
  62706     { /* SOC_REG_INT_OLP_REG_0092_BCM88650_B0r */
  62707         soc_block_list[42],
  62708         soc_genreg,
  62709         1,
  62710         0,
  62711         0x92,
  62712         SOC_REG_FLAG_SIGNAL,
  62713         0,
  62714         1,
  62715         soc_OLP_REG_0092_BCM88650_B0r_fields,
  62716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62718         -1,
  62719         -1,
  62720     },
  62721 #endif /* chips */
  62722 
  62723 #if defined(BCM_88660_A0)
  62724     { /* SOC_REG_INT_OLP_REG_0092_BCM88660_A0r */
  62725         soc_block_list[42],
  62726         soc_genreg,
  62727         1,
  62728         0,
  62729         0x92,
  62730         SOC_REG_FLAG_SIGNAL,
  62731         0,
  62732         1,
  62733         soc_OLP_REG_0092_BCM88660_A0r_fields,
  62734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62736         -1,
  62737         -1,
  62738     },
  62739 #endif /* chips */
  62740 
  62741 #if defined(BCM_88650_B0)
  62742     { /* SOC_REG_INT_OLP_REG_0093_BCM88650_B0r */
  62743         soc_block_list[42],
  62744         soc_genreg,
  62745         1,
  62746         0,
  62747         0x93,
  62748         SOC_REG_FLAG_SIGNAL,
  62749         0,
  62750         1,
  62751         soc_OLP_REG_0093_BCM88650_B0r_fields,
  62752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62754         -1,
  62755         -1,
  62756     },
  62757 #endif /* chips */
  62758 
  62759 #if defined(BCM_88660_A0)
  62760     { /* SOC_REG_INT_OLP_REG_0093_BCM88660_A0r */
  62761         soc_block_list[42],
  62762         soc_genreg,
  62763         1,
  62764         0,
  62765         0x93,
  62766         SOC_REG_FLAG_SIGNAL,
  62767         0,
  62768         1,
  62769         soc_OLP_REG_0093_BCM88660_A0r_fields,
  62770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62772         -1,
  62773         -1,
  62774     },
  62775 #endif /* chips */
  62776 
  62777 #if defined(BCM_88690_B0)
  62778     { /* SOC_REG_INT_OLP_REG_0098_BCM88690_B0r */
  62779         soc_block_list[42],
  62780         soc_genreg,
  62781         1,
  62782         0,
  62783         0x98,
  62784         SOC_REG_FLAG_64_BITS |
  62785                           SOC_REG_FLAG_RO,
  62786         SOC_REG_FLAG_COUNTER_FEILDS |
  62787                           SOC_REG_FLAG_INIT_ON_READ,
  62788         4,
  62789         soc_OLP_REG_0098_BCM88690_B0r_fields,
  62790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62791         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62792         -1,
  62793         -1,
  62794     },
  62795 #endif /* chips */
  62796 
  62797 #if defined(BCM_88690_A0)
  62798     { /* SOC_REG_INT_OLP_REG_00A0r */
  62799         soc_block_list[42],
  62800         soc_genreg,
  62801         1,
  62802         0,
  62803         0xa0,
  62804         0,
  62805         0,
  62806         1,
  62807         soc_OLP_REG_00A0r_fields,
  62808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62809         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62810         -1,
  62811         -1,
  62812     },
  62813 #endif /* chips */
  62814 
  62815 #if defined(BCM_88690_A0)
  62816     { /* SOC_REG_INT_OLP_REG_00A4r */
  62817         soc_block_list[42],
  62818         soc_genreg,
  62819         1,
  62820         0,
  62821         0xa4,
  62822         0,
  62823         0,
  62824         6,
  62825         soc_OLP_REG_00A4r_fields,
  62826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62827         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  62828         -1,
  62829         -1,
  62830     },
  62831 #endif /* chips */
  62832 
  62833 #if defined(BCM_88690_A0)
  62834     { /* SOC_REG_INT_OLP_REG_00A6r */
  62835         soc_block_list[42],
  62836         soc_genreg,
  62837         1,
  62838         0,
  62839         0xa6,
  62840         0,
  62841         0,
  62842         6,
  62843         soc_OLP_REG_00A6r_fields,
  62844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62845         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  62846         -1,
  62847         -1,
  62848     },
  62849 #endif /* chips */
  62850 
  62851 #if defined(BCM_88690_B0)
  62852     { /* SOC_REG_INT_OLP_REG_00A0_BCM88690_B0r */
  62853         soc_block_list[42],
  62854         soc_genreg,
  62855         1,
  62856         0,
  62857         0xa0,
  62858         0,
  62859         0,
  62860         1,
  62861         soc_OLP_REG_00A0_BCM88690_B0r_fields,
  62862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62863         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62864         -1,
  62865         -1,
  62866     },
  62867 #endif /* chips */
  62868 
  62869 #if defined(BCM_88690_A0)
  62870     { /* SOC_REG_INT_OLP_REG_00AAr */
  62871         soc_block_list[42],
  62872         soc_genreg,
  62873         1,
  62874         0,
  62875         0xaa,
  62876         0,
  62877         0,
  62878         1,
  62879         soc_OLP_REG_00AAr_fields,
  62880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62881         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62882         -1,
  62883         -1,
  62884     },
  62885 #endif /* chips */
  62886 
  62887 #if defined(BCM_88650_A0)
  62888     { /* SOC_REG_INT_OLP_REG_00BFr */
  62889         soc_block_list[42],
  62890         soc_genreg,
  62891         1,
  62892         0,
  62893         0xbf,
  62894         SOC_REG_FLAG_SIGNAL,
  62895         0,
  62896         6,
  62897         soc_OLP_REG_00BFr_fields,
  62898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62899         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  62900         -1,
  62901         -1,
  62902     },
  62903 #endif /* chips */
  62904 
  62905 #if defined(BCM_88650_B0)
  62906     { /* SOC_REG_INT_OLP_REG_00BF_BCM88650_B0r */
  62907         soc_block_list[42],
  62908         soc_genreg,
  62909         1,
  62910         0,
  62911         0xbf,
  62912         SOC_REG_FLAG_SIGNAL,
  62913         0,
  62914         6,
  62915         soc_OLP_REG_00BF_BCM88650_B0r_fields,
  62916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62917         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  62918         -1,
  62919         -1,
  62920     },
  62921 #endif /* chips */
  62922 
  62923 #if defined(BCM_88660_A0)
  62924     { /* SOC_REG_INT_OLP_REG_00BF_BCM88660_A0r */
  62925         soc_block_list[42],
  62926         soc_genreg,
  62927         1,
  62928         0,
  62929         0xbf,
  62930         SOC_REG_FLAG_SIGNAL,
  62931         0,
  62932         6,
  62933         soc_OLP_REG_00BF_BCM88660_A0r_fields,
  62934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62935         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  62936         -1,
  62937         -1,
  62938     },
  62939 #endif /* chips */
  62940 
  62941 #if defined(BCM_88690_A0)
  62942     { /* SOC_REG_INT_OLP_REG_00C2r */
  62943         soc_block_list[42],
  62944         soc_genreg,
  62945         1,
  62946         0,
  62947         0xc2,
  62948         0,
  62949         0,
  62950         6,
  62951         soc_OLP_REG_00C2r_fields,
  62952         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  62953         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  62954         -1,
  62955         -1,
  62956     },
  62957 #endif /* chips */
  62958 
  62959 #if defined(BCM_88690_A0)
  62960     { /* SOC_REG_INT_OLP_REG_00C3r */
  62961         soc_block_list[42],
  62962         soc_genreg,
  62963         1,
  62964         0,
  62965         0xc3,
  62966         0,
  62967         0,
  62968         3,
  62969         soc_OLP_REG_00C3r_fields,
  62970         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62971         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62972         -1,
  62973         -1,
  62974     },
  62975 #endif /* chips */
  62976 
  62977 #if defined(BCM_88690_B0)
  62978     { /* SOC_REG_INT_OLP_REG_00C2_BCM88690_B0r */
  62979         soc_block_list[42],
  62980         soc_genreg,
  62981         1,
  62982         0,
  62983         0xc2,
  62984         0,
  62985         0,
  62986         6,
  62987         soc_OLP_REG_00C2_BCM88690_B0r_fields,
  62988         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  62989         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  62990         -1,
  62991         -1,
  62992     },
  62993 #endif /* chips */
  62994 
  62995 #if defined(BCM_88690_B0)
  62996     { /* SOC_REG_INT_OLP_REG_00C3_BCM88690_B0r */
  62997         soc_block_list[42],
  62998         soc_genreg,
  62999         1,
  63000         0,
  63001         0xc3,
  63002         0,
  63003         0,
  63004         3,
  63005         soc_OLP_REG_00C3_BCM88690_B0r_fields,
  63006         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  63007         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63008         -1,
  63009         -1,
  63010     },
  63011 #endif /* chips */
  63012 
  63013 #if defined(BCM_88690_A0)
  63014     { /* SOC_REG_INT_OLP_REG_00E7r */
  63015         soc_block_list[42],
  63016         soc_genreg,
  63017         1,
  63018         0,
  63019         0xe7,
  63020         0,
  63021         0,
  63022         6,
  63023         soc_OLP_REG_00E7r_fields,
  63024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63025         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  63026         -1,
  63027         -1,
  63028     },
  63029 #endif /* chips */
  63030 
  63031 #if defined(BCM_88650_A0)
  63032     { /* SOC_REG_INT_OLP_REG_00F0r */
  63033         soc_block_list[42],
  63034         soc_genreg,
  63035         1,
  63036         0,
  63037         0xf0,
  63038         SOC_REG_FLAG_SIGNAL,
  63039         0,
  63040         3,
  63041         soc_OLP_REG_00F0r_fields,
  63042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63043         SOC_RESET_MASK_DEC(0x0001c000, 0x00000000)
  63044         -1,
  63045         -1,
  63046     },
  63047 #endif /* chips */
  63048 
  63049 #if defined(BCM_88270_A0)
  63050     { /* SOC_REG_INT_OLP_REG_0109_BCM88270_A0r */
  63051         soc_block_list[42],
  63052         soc_genreg,
  63053         2,
  63054         0,
  63055         0x109,
  63056         SOC_REG_FLAG_ARRAY |
  63057                           SOC_REG_FLAG_RO |
  63058                           SOC_REG_FLAG_REG_ARRAY |
  63059                           SOC_REG_FLAG_SIGNAL,
  63060         0,
  63061         1,
  63062         soc_OLP_REG_0109_BCM88270_A0r_fields,
  63063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63064         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63065         -1,
  63066         -1,
  63067     },
  63068 #endif /* chips */
  63069 
  63070 #if defined(BCM_88375_A0)
  63071     { /* SOC_REG_INT_OLP_REG_0109_BCM88375_A0r */
  63072         soc_block_list[42],
  63073         soc_genreg,
  63074         2,
  63075         0,
  63076         0x109,
  63077         SOC_REG_FLAG_ARRAY |
  63078                           SOC_REG_FLAG_RO |
  63079                           SOC_REG_FLAG_REG_ARRAY |
  63080                           SOC_REG_FLAG_SIGNAL,
  63081         0,
  63082         1,
  63083         soc_OLP_REG_0109_BCM88375_A0r_fields,
  63084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63085         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63086         -1,
  63087         -1,
  63088     },
  63089 #endif /* chips */
  63090 
  63091 #if defined(BCM_88375_B0)
  63092     { /* SOC_REG_INT_OLP_REG_0109_BCM88375_B0r */
  63093         soc_block_list[42],
  63094         soc_genreg,
  63095         2,
  63096         0,
  63097         0x109,
  63098         SOC_REG_FLAG_ARRAY |
  63099                           SOC_REG_FLAG_RO |
  63100                           SOC_REG_FLAG_REG_ARRAY |
  63101                           SOC_REG_FLAG_SIGNAL,
  63102         0,
  63103         1,
  63104         soc_OLP_REG_0109_BCM88375_B0r_fields,
  63105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63106         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63107         -1,
  63108         -1,
  63109     },
  63110 #endif /* chips */
  63111 
  63112 #if defined(BCM_88470_A0)
  63113     { /* SOC_REG_INT_OLP_REG_0109_BCM88470_A0r */
  63114         soc_block_list[42],
  63115         soc_genreg,
  63116         2,
  63117         0,
  63118         0x109,
  63119         SOC_REG_FLAG_ARRAY |
  63120                           SOC_REG_FLAG_RO |
  63121                           SOC_REG_FLAG_REG_ARRAY |
  63122                           SOC_REG_FLAG_SIGNAL,
  63123         0,
  63124         1,
  63125         soc_OLP_REG_0109_BCM88470_A0r_fields,
  63126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63127         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63128         -1,
  63129         -1,
  63130     },
  63131 #endif /* chips */
  63132 
  63133 #if defined(BCM_88470_B0)
  63134     { /* SOC_REG_INT_OLP_REG_0109_BCM88470_B0r */
  63135         soc_block_list[42],
  63136         soc_genreg,
  63137         2,
  63138         0,
  63139         0x109,
  63140         SOC_REG_FLAG_ARRAY |
  63141                           SOC_REG_FLAG_RO |
  63142                           SOC_REG_FLAG_REG_ARRAY |
  63143                           SOC_REG_FLAG_SIGNAL,
  63144         0,
  63145         1,
  63146         soc_OLP_REG_0109_BCM88470_B0r_fields,
  63147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63148         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63149         -1,
  63150         -1,
  63151     },
  63152 #endif /* chips */
  63153 
  63154 #if defined(BCM_88650_B0)
  63155     { /* SOC_REG_INT_OLP_REG_0109_BCM88650_B0r */
  63156         soc_block_list[42],
  63157         soc_genreg,
  63158         2,
  63159         0,
  63160         0x109,
  63161         SOC_REG_FLAG_ARRAY |
  63162                           SOC_REG_FLAG_RO |
  63163                           SOC_REG_FLAG_REG_ARRAY,
  63164         0,
  63165         1,
  63166         soc_OLP_REG_0109_BCM88650_B0r_fields,
  63167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63168         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63169         -1,
  63170         -1,
  63171     },
  63172 #endif /* chips */
  63173 
  63174 #if defined(BCM_88660_A0)
  63175     { /* SOC_REG_INT_OLP_REG_0109_BCM88660_A0r */
  63176         soc_block_list[42],
  63177         soc_genreg,
  63178         2,
  63179         0,
  63180         0x109,
  63181         SOC_REG_FLAG_ARRAY |
  63182                           SOC_REG_FLAG_RO |
  63183                           SOC_REG_FLAG_REG_ARRAY,
  63184         0,
  63185         1,
  63186         soc_OLP_REG_0109_BCM88660_A0r_fields,
  63187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63188         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63189         -1,
  63190         -1,
  63191     },
  63192 #endif /* chips */
  63193 
  63194 #if defined(BCM_88675_A0)
  63195     { /* SOC_REG_INT_OLP_REG_0109_BCM88675_A0r */
  63196         soc_block_list[42],
  63197         soc_genreg,
  63198         2,
  63199         0,
  63200         0x109,
  63201         SOC_REG_FLAG_ARRAY |
  63202                           SOC_REG_FLAG_RO |
  63203                           SOC_REG_FLAG_REG_ARRAY |
  63204                           SOC_REG_FLAG_SIGNAL,
  63205         0,
  63206         1,
  63207         soc_OLP_REG_0109_BCM88675_A0r_fields,
  63208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63209         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63210         -1,
  63211         -1,
  63212     },
  63213 #endif /* chips */
  63214 
  63215 #if defined(BCM_88675_B0)
  63216     { /* SOC_REG_INT_OLP_REG_0109_BCM88675_B0r */
  63217         soc_block_list[42],
  63218         soc_genreg,
  63219         2,
  63220         0,
  63221         0x109,
  63222         SOC_REG_FLAG_ARRAY |
  63223                           SOC_REG_FLAG_RO |
  63224                           SOC_REG_FLAG_REG_ARRAY |
  63225                           SOC_REG_FLAG_SIGNAL,
  63226         0,
  63227         1,
  63228         soc_OLP_REG_0109_BCM88675_B0r_fields,
  63229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63230         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63231         -1,
  63232         -1,
  63233     },
  63234 #endif /* chips */
  63235 
  63236 #if defined(BCM_88680_A0)
  63237     { /* SOC_REG_INT_OLP_REG_0109_BCM88680_A0r */
  63238         soc_block_list[42],
  63239         soc_genreg,
  63240         2,
  63241         0,
  63242         0x109,
  63243         SOC_REG_FLAG_ARRAY |
  63244                           SOC_REG_FLAG_RO |
  63245                           SOC_REG_FLAG_REG_ARRAY |
  63246                           SOC_REG_FLAG_SIGNAL,
  63247         0,
  63248         1,
  63249         soc_OLP_REG_0109_BCM88680_A0r_fields,
  63250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63251         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63252         -1,
  63253         -1,
  63254     },
  63255 #endif /* chips */
  63256 
  63257 #if defined(BCM_88650_A0)
  63258     { /* SOC_REG_INT_OLP_REG_010Br */
  63259         soc_block_list[42],
  63260         soc_genreg,
  63261         2,
  63262         0,
  63263         0x10b,
  63264         SOC_REG_FLAG_ARRAY |
  63265                           SOC_REG_FLAG_RO |
  63266                           SOC_REG_FLAG_REG_ARRAY,
  63267         0,
  63268         1,
  63269         soc_OLP_REG_010Br_fields,
  63270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63271         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63272         -1,
  63273         -1,
  63274     },
  63275 #endif /* chips */
  63276 
  63277 #if defined(BCM_88650_B0)
  63278     { /* SOC_REG_INT_OLP_REG_010B_BCM88650_B0r */
  63279         soc_block_list[42],
  63280         soc_genreg,
  63281         2,
  63282         0,
  63283         0x10b,
  63284         SOC_REG_FLAG_ARRAY |
  63285                           SOC_REG_FLAG_RO |
  63286                           SOC_REG_FLAG_REG_ARRAY,
  63287         0,
  63288         1,
  63289         soc_OLP_REG_010B_BCM88650_B0r_fields,
  63290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63291         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63292         -1,
  63293         -1,
  63294     },
  63295 #endif /* chips */
  63296 
  63297 #if defined(BCM_88660_A0)
  63298     { /* SOC_REG_INT_OLP_REG_010B_BCM88660_A0r */
  63299         soc_block_list[42],
  63300         soc_genreg,
  63301         2,
  63302         0,
  63303         0x10b,
  63304         SOC_REG_FLAG_ARRAY |
  63305                           SOC_REG_FLAG_RO |
  63306                           SOC_REG_FLAG_REG_ARRAY,
  63307         0,
  63308         1,
  63309         soc_OLP_REG_010B_BCM88660_A0r_fields,
  63310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63311         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63312         -1,
  63313         -1,
  63314     },
  63315 #endif /* chips */
  63316 
  63317 #if defined(BCM_88675_A0)
  63318     { /* SOC_REG_INT_OLP_REG_010Dr */
  63319         soc_block_list[42],
  63320         soc_genreg,
  63321         2,
  63322         0,
  63323         0x10d,
  63324         SOC_REG_FLAG_ARRAY |
  63325                           SOC_REG_FLAG_RO |
  63326                           SOC_REG_FLAG_REG_ARRAY |
  63327                           SOC_REG_FLAG_SIGNAL,
  63328         0,
  63329         1,
  63330         soc_OLP_REG_010Dr_fields,
  63331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63332         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63333         -1,
  63334         -1,
  63335     },
  63336 #endif /* chips */
  63337 
  63338 #if defined(BCM_88270_A0)
  63339     { /* SOC_REG_INT_OLP_REG_010D_BCM88270_A0r */
  63340         soc_block_list[42],
  63341         soc_genreg,
  63342         2,
  63343         0,
  63344         0x10d,
  63345         SOC_REG_FLAG_ARRAY |
  63346                           SOC_REG_FLAG_RO |
  63347                           SOC_REG_FLAG_REG_ARRAY |
  63348                           SOC_REG_FLAG_SIGNAL,
  63349         0,
  63350         1,
  63351         soc_OLP_REG_010D_BCM88270_A0r_fields,
  63352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63353         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63354         -1,
  63355         -1,
  63356     },
  63357 #endif /* chips */
  63358 
  63359 #if defined(BCM_88375_A0)
  63360     { /* SOC_REG_INT_OLP_REG_010D_BCM88375_A0r */
  63361         soc_block_list[42],
  63362         soc_genreg,
  63363         2,
  63364         0,
  63365         0x10d,
  63366         SOC_REG_FLAG_ARRAY |
  63367                           SOC_REG_FLAG_RO |
  63368                           SOC_REG_FLAG_REG_ARRAY |
  63369                           SOC_REG_FLAG_SIGNAL,
  63370         0,
  63371         1,
  63372         soc_OLP_REG_010D_BCM88375_A0r_fields,
  63373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63374         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63375         -1,
  63376         -1,
  63377     },
  63378 #endif /* chips */
  63379 
  63380 #if defined(BCM_88375_B0)
  63381     { /* SOC_REG_INT_OLP_REG_010D_BCM88375_B0r */
  63382         soc_block_list[42],
  63383         soc_genreg,
  63384         2,
  63385         0,
  63386         0x10d,
  63387         SOC_REG_FLAG_ARRAY |
  63388                           SOC_REG_FLAG_RO |
  63389                           SOC_REG_FLAG_REG_ARRAY |
  63390                           SOC_REG_FLAG_SIGNAL,
  63391         0,
  63392         1,
  63393         soc_OLP_REG_010D_BCM88375_B0r_fields,
  63394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63395         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63396         -1,
  63397         -1,
  63398     },
  63399 #endif /* chips */
  63400 
  63401 #if defined(BCM_88470_A0)
  63402     { /* SOC_REG_INT_OLP_REG_010D_BCM88470_A0r */
  63403         soc_block_list[42],
  63404         soc_genreg,
  63405         2,
  63406         0,
  63407         0x10d,
  63408         SOC_REG_FLAG_ARRAY |
  63409                           SOC_REG_FLAG_RO |
  63410                           SOC_REG_FLAG_REG_ARRAY |
  63411                           SOC_REG_FLAG_SIGNAL,
  63412         0,
  63413         1,
  63414         soc_OLP_REG_010D_BCM88470_A0r_fields,
  63415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63416         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63417         -1,
  63418         -1,
  63419     },
  63420 #endif /* chips */
  63421 
  63422 #if defined(BCM_88470_B0)
  63423     { /* SOC_REG_INT_OLP_REG_010D_BCM88470_B0r */
  63424         soc_block_list[42],
  63425         soc_genreg,
  63426         2,
  63427         0,
  63428         0x10d,
  63429         SOC_REG_FLAG_ARRAY |
  63430                           SOC_REG_FLAG_RO |
  63431                           SOC_REG_FLAG_REG_ARRAY |
  63432                           SOC_REG_FLAG_SIGNAL,
  63433         0,
  63434         1,
  63435         soc_OLP_REG_010D_BCM88470_B0r_fields,
  63436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63437         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63438         -1,
  63439         -1,
  63440     },
  63441 #endif /* chips */
  63442 
  63443 #if defined(BCM_88675_B0)
  63444     { /* SOC_REG_INT_OLP_REG_010D_BCM88675_B0r */
  63445         soc_block_list[42],
  63446         soc_genreg,
  63447         2,
  63448         0,
  63449         0x10d,
  63450         SOC_REG_FLAG_ARRAY |
  63451                           SOC_REG_FLAG_RO |
  63452                           SOC_REG_FLAG_REG_ARRAY |
  63453                           SOC_REG_FLAG_SIGNAL,
  63454         0,
  63455         1,
  63456         soc_OLP_REG_010D_BCM88675_B0r_fields,
  63457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63458         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63459         -1,
  63460         -1,
  63461     },
  63462 #endif /* chips */
  63463 
  63464 #if defined(BCM_88680_A0)
  63465     { /* SOC_REG_INT_OLP_REG_010D_BCM88680_A0r */
  63466         soc_block_list[42],
  63467         soc_genreg,
  63468         2,
  63469         0,
  63470         0x10d,
  63471         SOC_REG_FLAG_ARRAY |
  63472                           SOC_REG_FLAG_RO |
  63473                           SOC_REG_FLAG_REG_ARRAY |
  63474                           SOC_REG_FLAG_SIGNAL,
  63475         0,
  63476         1,
  63477         soc_OLP_REG_010D_BCM88680_A0r_fields,
  63478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63479         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63480         -1,
  63481         -1,
  63482     },
  63483 #endif /* chips */
  63484 
  63485 #if defined(BCM_88270_A0)
  63486     { /* SOC_REG_INT_OLP_REG_0111_BCM88270_A0r */
  63487         soc_block_list[42],
  63488         soc_genreg,
  63489         1,
  63490         0,
  63491         0x111,
  63492         SOC_REG_FLAG_RO |
  63493                           SOC_REG_FLAG_SIGNAL,
  63494         0,
  63495         1,
  63496         soc_OLP_REG_0111_BCM88270_A0r_fields,
  63497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63498         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63499         -1,
  63500         -1,
  63501     },
  63502 #endif /* chips */
  63503 
  63504 #if defined(BCM_88375_A0)
  63505     { /* SOC_REG_INT_OLP_REG_0111_BCM88375_A0r */
  63506         soc_block_list[42],
  63507         soc_genreg,
  63508         1,
  63509         0,
  63510         0x111,
  63511         SOC_REG_FLAG_RO |
  63512                           SOC_REG_FLAG_SIGNAL,
  63513         0,
  63514         1,
  63515         soc_OLP_REG_0111_BCM88375_A0r_fields,
  63516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63517         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63518         -1,
  63519         -1,
  63520     },
  63521 #endif /* chips */
  63522 
  63523 #if defined(BCM_88375_B0)
  63524     { /* SOC_REG_INT_OLP_REG_0111_BCM88375_B0r */
  63525         soc_block_list[42],
  63526         soc_genreg,
  63527         1,
  63528         0,
  63529         0x111,
  63530         SOC_REG_FLAG_RO |
  63531                           SOC_REG_FLAG_SIGNAL,
  63532         0,
  63533         1,
  63534         soc_OLP_REG_0111_BCM88375_B0r_fields,
  63535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63536         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63537         -1,
  63538         -1,
  63539     },
  63540 #endif /* chips */
  63541 
  63542 #if defined(BCM_88470_A0)
  63543     { /* SOC_REG_INT_OLP_REG_0111_BCM88470_A0r */
  63544         soc_block_list[42],
  63545         soc_genreg,
  63546         1,
  63547         0,
  63548         0x111,
  63549         SOC_REG_FLAG_RO |
  63550                           SOC_REG_FLAG_SIGNAL,
  63551         0,
  63552         1,
  63553         soc_OLP_REG_0111_BCM88470_A0r_fields,
  63554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63555         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63556         -1,
  63557         -1,
  63558     },
  63559 #endif /* chips */
  63560 
  63561 #if defined(BCM_88470_B0)
  63562     { /* SOC_REG_INT_OLP_REG_0111_BCM88470_B0r */
  63563         soc_block_list[42],
  63564         soc_genreg,
  63565         1,
  63566         0,
  63567         0x111,
  63568         SOC_REG_FLAG_RO |
  63569                           SOC_REG_FLAG_SIGNAL,
  63570         0,
  63571         1,
  63572         soc_OLP_REG_0111_BCM88470_B0r_fields,
  63573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63574         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63575         -1,
  63576         -1,
  63577     },
  63578 #endif /* chips */
  63579 
  63580 #if defined(BCM_88675_B0)
  63581     { /* SOC_REG_INT_OLP_REG_0111_BCM88675_B0r */
  63582         soc_block_list[42],
  63583         soc_genreg,
  63584         1,
  63585         0,
  63586         0x111,
  63587         SOC_REG_FLAG_RO |
  63588                           SOC_REG_FLAG_SIGNAL,
  63589         0,
  63590         1,
  63591         soc_OLP_REG_0111_BCM88675_B0r_fields,
  63592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63593         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63594         -1,
  63595         -1,
  63596     },
  63597 #endif /* chips */
  63598 
  63599 #if defined(BCM_88680_A0)
  63600     { /* SOC_REG_INT_OLP_REG_0111_BCM88680_A0r */
  63601         soc_block_list[42],
  63602         soc_genreg,
  63603         1,
  63604         0,
  63605         0x111,
  63606         SOC_REG_FLAG_RO |
  63607                           SOC_REG_FLAG_SIGNAL,
  63608         0,
  63609         1,
  63610         soc_OLP_REG_0111_BCM88680_A0r_fields,
  63611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63612         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63613         -1,
  63614         -1,
  63615     },
  63616 #endif /* chips */
  63617 
  63618 #if defined(BCM_88270_A0)
  63619     { /* SOC_REG_INT_OLP_REG_0112_BCM88270_A0r */
  63620         soc_block_list[42],
  63621         soc_genreg,
  63622         1,
  63623         0,
  63624         0x112,
  63625         SOC_REG_FLAG_RO |
  63626                           SOC_REG_FLAG_SIGNAL,
  63627         0,
  63628         1,
  63629         soc_OLP_REG_0112_BCM88270_A0r_fields,
  63630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63631         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63632         -1,
  63633         -1,
  63634     },
  63635 #endif /* chips */
  63636 
  63637 #if defined(BCM_88375_A0)
  63638     { /* SOC_REG_INT_OLP_REG_0112_BCM88375_A0r */
  63639         soc_block_list[42],
  63640         soc_genreg,
  63641         1,
  63642         0,
  63643         0x112,
  63644         SOC_REG_FLAG_RO |
  63645                           SOC_REG_FLAG_SIGNAL,
  63646         0,
  63647         1,
  63648         soc_OLP_REG_0112_BCM88375_A0r_fields,
  63649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63650         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63651         -1,
  63652         -1,
  63653     },
  63654 #endif /* chips */
  63655 
  63656 #if defined(BCM_88375_B0)
  63657     { /* SOC_REG_INT_OLP_REG_0112_BCM88375_B0r */
  63658         soc_block_list[42],
  63659         soc_genreg,
  63660         1,
  63661         0,
  63662         0x112,
  63663         SOC_REG_FLAG_RO |
  63664                           SOC_REG_FLAG_SIGNAL,
  63665         0,
  63666         1,
  63667         soc_OLP_REG_0112_BCM88375_B0r_fields,
  63668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63669         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63670         -1,
  63671         -1,
  63672     },
  63673 #endif /* chips */
  63674 
  63675 #if defined(BCM_88470_A0)
  63676     { /* SOC_REG_INT_OLP_REG_0112_BCM88470_A0r */
  63677         soc_block_list[42],
  63678         soc_genreg,
  63679         1,
  63680         0,
  63681         0x112,
  63682         SOC_REG_FLAG_RO |
  63683                           SOC_REG_FLAG_SIGNAL,
  63684         0,
  63685         1,
  63686         soc_OLP_REG_0112_BCM88470_A0r_fields,
  63687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63688         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63689         -1,
  63690         -1,
  63691     },
  63692 #endif /* chips */
  63693 
  63694 #if defined(BCM_88470_B0)
  63695     { /* SOC_REG_INT_OLP_REG_0112_BCM88470_B0r */
  63696         soc_block_list[42],
  63697         soc_genreg,
  63698         1,
  63699         0,
  63700         0x112,
  63701         SOC_REG_FLAG_RO |
  63702                           SOC_REG_FLAG_SIGNAL,
  63703         0,
  63704         1,
  63705         soc_OLP_REG_0112_BCM88470_B0r_fields,
  63706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63707         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63708         -1,
  63709         -1,
  63710     },
  63711 #endif /* chips */
  63712 
  63713 #if defined(BCM_88675_B0)
  63714     { /* SOC_REG_INT_OLP_REG_0112_BCM88675_B0r */
  63715         soc_block_list[42],
  63716         soc_genreg,
  63717         1,
  63718         0,
  63719         0x112,
  63720         SOC_REG_FLAG_RO |
  63721                           SOC_REG_FLAG_SIGNAL,
  63722         0,
  63723         1,
  63724         soc_OLP_REG_0112_BCM88675_B0r_fields,
  63725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63726         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63727         -1,
  63728         -1,
  63729     },
  63730 #endif /* chips */
  63731 
  63732 #if defined(BCM_88680_A0)
  63733     { /* SOC_REG_INT_OLP_REG_0112_BCM88680_A0r */
  63734         soc_block_list[42],
  63735         soc_genreg,
  63736         1,
  63737         0,
  63738         0x112,
  63739         SOC_REG_FLAG_RO |
  63740                           SOC_REG_FLAG_SIGNAL,
  63741         0,
  63742         1,
  63743         soc_OLP_REG_0112_BCM88680_A0r_fields,
  63744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63745         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63746         -1,
  63747         -1,
  63748     },
  63749 #endif /* chips */
  63750 
  63751 #if defined(BCM_88675_A0)
  63752     { /* SOC_REG_INT_OLP_RESERVED_MIRROR_ADDRr */
  63753         soc_block_list[42],
  63754         soc_genreg,
  63755         1,
  63756         0,
  63757         0x85,
  63758         0,
  63759         0,
  63760         2,
  63761         soc_OLP_RESERVED_MIRROR_ADDRr_fields,
  63762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63763         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  63764         -1,
  63765         -1,
  63766     },
  63767 #endif /* chips */
  63768 
  63769 #if defined(BCM_88270_A0)
  63770     { /* SOC_REG_INT_OLP_RESERVED_MIRROR_ADDR_BCM88270_A0r */
  63771         soc_block_list[42],
  63772         soc_genreg,
  63773         1,
  63774         0,
  63775         0x85,
  63776         0,
  63777         0,
  63778         2,
  63779         soc_OLP_RESERVED_MIRROR_ADDR_BCM88270_A0r_fields,
  63780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63781         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  63782         -1,
  63783         -1,
  63784     },
  63785 #endif /* chips */
  63786 
  63787 #if defined(BCM_88375_A0)
  63788     { /* SOC_REG_INT_OLP_RESERVED_MIRROR_ADDR_BCM88375_A0r */
  63789         soc_block_list[42],
  63790         soc_genreg,
  63791         1,
  63792         0,
  63793         0x85,
  63794         0,
  63795         0,
  63796         2,
  63797         soc_OLP_RESERVED_MIRROR_ADDR_BCM88375_A0r_fields,
  63798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63799         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  63800         -1,
  63801         -1,
  63802     },
  63803 #endif /* chips */
  63804 
  63805 #if defined(BCM_88375_B0)
  63806     { /* SOC_REG_INT_OLP_RESERVED_MIRROR_ADDR_BCM88375_B0r */
  63807         soc_block_list[42],
  63808         soc_genreg,
  63809         1,
  63810         0,
  63811         0x85,
  63812         0,
  63813         0,
  63814         2,
  63815         soc_OLP_RESERVED_MIRROR_ADDR_BCM88375_B0r_fields,
  63816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63817         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  63818         -1,
  63819         -1,
  63820     },
  63821 #endif /* chips */
  63822 
  63823 #if defined(BCM_88470_A0)
  63824     { /* SOC_REG_INT_OLP_RESERVED_MIRROR_ADDR_BCM88470_A0r */
  63825         soc_block_list[42],
  63826         soc_genreg,
  63827         1,
  63828         0,
  63829         0x85,
  63830         0,
  63831         0,
  63832         2,
  63833         soc_OLP_RESERVED_MIRROR_ADDR_BCM88470_A0r_fields,
  63834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63835         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  63836         -1,
  63837         -1,
  63838     },
  63839 #endif /* chips */
  63840 
  63841 #if defined(BCM_88470_B0)
  63842     { /* SOC_REG_INT_OLP_RESERVED_MIRROR_ADDR_BCM88470_B0r */
  63843         soc_block_list[42],
  63844         soc_genreg,
  63845         1,
  63846         0,
  63847         0x85,
  63848         0,
  63849         0,
  63850         2,
  63851         soc_OLP_RESERVED_MIRROR_ADDR_BCM88470_B0r_fields,
  63852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63853         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  63854         -1,
  63855         -1,
  63856     },
  63857 #endif /* chips */
  63858 
  63859 #if defined(BCM_88675_B0)
  63860     { /* SOC_REG_INT_OLP_RESERVED_MIRROR_ADDR_BCM88675_B0r */
  63861         soc_block_list[42],
  63862         soc_genreg,
  63863         1,
  63864         0,
  63865         0x85,
  63866         0,
  63867         0,
  63868         2,
  63869         soc_OLP_RESERVED_MIRROR_ADDR_BCM88675_B0r_fields,
  63870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63871         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  63872         -1,
  63873         -1,
  63874     },
  63875 #endif /* chips */
  63876 
  63877 #if defined(BCM_88680_A0)
  63878     { /* SOC_REG_INT_OLP_RESERVED_MIRROR_ADDR_BCM88680_A0r */
  63879         soc_block_list[42],
  63880         soc_genreg,
  63881         1,
  63882         0,
  63883         0x85,
  63884         0,
  63885         0,
  63886         2,
  63887         soc_OLP_RESERVED_MIRROR_ADDR_BCM88680_A0r_fields,
  63888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63889         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  63890         -1,
  63891         -1,
  63892     },
  63893 #endif /* chips */
  63894 
  63895 #if defined(BCM_88690_A0)
  63896     { /* SOC_REG_INT_OLP_RESERVED_MIRROR_ADDR_BCM88690_A0r */
  63897         soc_block_list[42],
  63898         soc_genreg,
  63899         1,
  63900         0,
  63901         0x85,
  63902         0,
  63903         0,
  63904         2,
  63905         soc_OLP_RESERVED_MIRROR_ADDR_BCM88690_A0r_fields,
  63906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63907         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  63908         -1,
  63909         -1,
  63910     },
  63911 #endif /* chips */
  63912 
  63913 #if defined(BCM_88675_A0)
  63914     { /* SOC_REG_INT_OLP_RESERVED_MTCDr */
  63915         soc_block_list[42],
  63916         soc_genreg,
  63917         1,
  63918         0,
  63919         0xae,
  63920         0,
  63921         0,
  63922         6,
  63923         soc_OLP_RESERVED_MTCDr_fields,
  63924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63925         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63926         -1,
  63927         -1,
  63928     },
  63929 #endif /* chips */
  63930 
  63931 #if defined(BCM_88270_A0)
  63932     { /* SOC_REG_INT_OLP_RESERVED_MTCD_BCM88270_A0r */
  63933         soc_block_list[42],
  63934         soc_genreg,
  63935         1,
  63936         0,
  63937         0xae,
  63938         0,
  63939         0,
  63940         6,
  63941         soc_OLP_RESERVED_MTCD_BCM88270_A0r_fields,
  63942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63943         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63944         -1,
  63945         -1,
  63946     },
  63947 #endif /* chips */
  63948 
  63949 #if defined(BCM_88375_A0)
  63950     { /* SOC_REG_INT_OLP_RESERVED_MTCD_BCM88375_A0r */
  63951         soc_block_list[42],
  63952         soc_genreg,
  63953         1,
  63954         0,
  63955         0xae,
  63956         0,
  63957         0,
  63958         6,
  63959         soc_OLP_RESERVED_MTCD_BCM88375_A0r_fields,
  63960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63961         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63962         -1,
  63963         -1,
  63964     },
  63965 #endif /* chips */
  63966 
  63967 #if defined(BCM_88375_B0)
  63968     { /* SOC_REG_INT_OLP_RESERVED_MTCD_BCM88375_B0r */
  63969         soc_block_list[42],
  63970         soc_genreg,
  63971         1,
  63972         0,
  63973         0xae,
  63974         0,
  63975         0,
  63976         6,
  63977         soc_OLP_RESERVED_MTCD_BCM88375_B0r_fields,
  63978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63979         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63980         -1,
  63981         -1,
  63982     },
  63983 #endif /* chips */
  63984 
  63985 #if defined(BCM_88470_A0)
  63986     { /* SOC_REG_INT_OLP_RESERVED_MTCD_BCM88470_A0r */
  63987         soc_block_list[42],
  63988         soc_genreg,
  63989         1,
  63990         0,
  63991         0xae,
  63992         0,
  63993         0,
  63994         6,
  63995         soc_OLP_RESERVED_MTCD_BCM88470_A0r_fields,
  63996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63997         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63998         -1,
  63999         -1,
  64000     },
  64001 #endif /* chips */
  64002 
  64003 #if defined(BCM_88470_B0)
  64004     { /* SOC_REG_INT_OLP_RESERVED_MTCD_BCM88470_B0r */
  64005         soc_block_list[42],
  64006         soc_genreg,
  64007         1,
  64008         0,
  64009         0xae,
  64010         0,
  64011         0,
  64012         6,
  64013         soc_OLP_RESERVED_MTCD_BCM88470_B0r_fields,
  64014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64015         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64016         -1,
  64017         -1,
  64018     },
  64019 #endif /* chips */
  64020 
  64021 #if defined(BCM_88675_B0)
  64022     { /* SOC_REG_INT_OLP_RESERVED_MTCD_BCM88675_B0r */
  64023         soc_block_list[42],
  64024         soc_genreg,
  64025         1,
  64026         0,
  64027         0xae,
  64028         0,
  64029         0,
  64030         6,
  64031         soc_OLP_RESERVED_MTCD_BCM88675_B0r_fields,
  64032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64033         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64034         -1,
  64035         -1,
  64036     },
  64037 #endif /* chips */
  64038 
  64039 #if defined(BCM_88680_A0)
  64040     { /* SOC_REG_INT_OLP_RESERVED_MTCD_BCM88680_A0r */
  64041         soc_block_list[42],
  64042         soc_genreg,
  64043         1,
  64044         0,
  64045         0xae,
  64046         0,
  64047         0,
  64048         6,
  64049         soc_OLP_RESERVED_MTCD_BCM88680_A0r_fields,
  64050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64051         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64052         -1,
  64053         -1,
  64054     },
  64055 #endif /* chips */
  64056 
  64057 #if defined(BCM_88690_A0)
  64058     { /* SOC_REG_INT_OLP_RESERVED_MTCD_BCM88690_A0r */
  64059         soc_block_list[42],
  64060         soc_genreg,
  64061         1,
  64062         0,
  64063         0xae,
  64064         0,
  64065         0,
  64066         6,
  64067         soc_OLP_RESERVED_MTCD_BCM88690_A0r_fields,
  64068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64069         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64070         -1,
  64071         -1,
  64072     },
  64073 #endif /* chips */
  64074 
  64075 #if defined(BCM_88690_B0)
  64076     { /* SOC_REG_INT_OLP_RESERVED_MTCD_BCM88690_B0r */
  64077         soc_block_list[42],
  64078         soc_genreg,
  64079         1,
  64080         0,
  64081         0xae,
  64082         0,
  64083         0,
  64084         6,
  64085         soc_OLP_RESERVED_MTCD_BCM88690_B0r_fields,
  64086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64087         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64088         -1,
  64089         -1,
  64090     },
  64091 #endif /* chips */
  64092 
  64093 #if defined(BCM_88675_A0)
  64094     { /* SOC_REG_INT_OLP_RESERVED_MTCPr */
  64095         soc_block_list[42],
  64096         soc_genreg,
  64097         1,
  64098         0,
  64099         0xad,
  64100         SOC_REG_FLAG_64_BITS,
  64101         0,
  64102         17,
  64103         soc_OLP_RESERVED_MTCPr_fields,
  64104         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64105         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64106         -1,
  64107         -1,
  64108     },
  64109 #endif /* chips */
  64110 
  64111 #if defined(BCM_88270_A0)
  64112     { /* SOC_REG_INT_OLP_RESERVED_MTCP_BCM88270_A0r */
  64113         soc_block_list[42],
  64114         soc_genreg,
  64115         1,
  64116         0,
  64117         0xad,
  64118         SOC_REG_FLAG_64_BITS,
  64119         0,
  64120         17,
  64121         soc_OLP_RESERVED_MTCP_BCM88270_A0r_fields,
  64122         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64123         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64124         -1,
  64125         -1,
  64126     },
  64127 #endif /* chips */
  64128 
  64129 #if defined(BCM_88375_A0)
  64130     { /* SOC_REG_INT_OLP_RESERVED_MTCP_BCM88375_A0r */
  64131         soc_block_list[42],
  64132         soc_genreg,
  64133         1,
  64134         0,
  64135         0xad,
  64136         SOC_REG_FLAG_64_BITS,
  64137         0,
  64138         17,
  64139         soc_OLP_RESERVED_MTCP_BCM88375_A0r_fields,
  64140         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64141         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64142         -1,
  64143         -1,
  64144     },
  64145 #endif /* chips */
  64146 
  64147 #if defined(BCM_88375_B0)
  64148     { /* SOC_REG_INT_OLP_RESERVED_MTCP_BCM88375_B0r */
  64149         soc_block_list[42],
  64150         soc_genreg,
  64151         1,
  64152         0,
  64153         0xad,
  64154         SOC_REG_FLAG_64_BITS,
  64155         0,
  64156         17,
  64157         soc_OLP_RESERVED_MTCP_BCM88375_B0r_fields,
  64158         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64159         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64160         -1,
  64161         -1,
  64162     },
  64163 #endif /* chips */
  64164 
  64165 #if defined(BCM_88470_A0)
  64166     { /* SOC_REG_INT_OLP_RESERVED_MTCP_BCM88470_A0r */
  64167         soc_block_list[42],
  64168         soc_genreg,
  64169         1,
  64170         0,
  64171         0xad,
  64172         SOC_REG_FLAG_64_BITS,
  64173         0,
  64174         17,
  64175         soc_OLP_RESERVED_MTCP_BCM88470_A0r_fields,
  64176         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64177         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64178         -1,
  64179         -1,
  64180     },
  64181 #endif /* chips */
  64182 
  64183 #if defined(BCM_88470_B0)
  64184     { /* SOC_REG_INT_OLP_RESERVED_MTCP_BCM88470_B0r */
  64185         soc_block_list[42],
  64186         soc_genreg,
  64187         1,
  64188         0,
  64189         0xad,
  64190         SOC_REG_FLAG_64_BITS,
  64191         0,
  64192         17,
  64193         soc_OLP_RESERVED_MTCP_BCM88470_B0r_fields,
  64194         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64195         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64196         -1,
  64197         -1,
  64198     },
  64199 #endif /* chips */
  64200 
  64201 #if defined(BCM_88675_B0)
  64202     { /* SOC_REG_INT_OLP_RESERVED_MTCP_BCM88675_B0r */
  64203         soc_block_list[42],
  64204         soc_genreg,
  64205         1,
  64206         0,
  64207         0xad,
  64208         SOC_REG_FLAG_64_BITS,
  64209         0,
  64210         17,
  64211         soc_OLP_RESERVED_MTCP_BCM88675_B0r_fields,
  64212         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64213         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64214         -1,
  64215         -1,
  64216     },
  64217 #endif /* chips */
  64218 
  64219 #if defined(BCM_88680_A0)
  64220     { /* SOC_REG_INT_OLP_RESERVED_MTCP_BCM88680_A0r */
  64221         soc_block_list[42],
  64222         soc_genreg,
  64223         1,
  64224         0,
  64225         0xad,
  64226         SOC_REG_FLAG_64_BITS,
  64227         0,
  64228         17,
  64229         soc_OLP_RESERVED_MTCP_BCM88680_A0r_fields,
  64230         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64231         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64232         -1,
  64233         -1,
  64234     },
  64235 #endif /* chips */
  64236 
  64237 #if defined(BCM_88690_A0)
  64238     { /* SOC_REG_INT_OLP_RESERVED_MTCP_BCM88690_A0r */
  64239         soc_block_list[42],
  64240         soc_genreg,
  64241         1,
  64242         0,
  64243         0xad,
  64244         SOC_REG_FLAG_64_BITS,
  64245         0,
  64246         17,
  64247         soc_OLP_RESERVED_MTCP_BCM88690_A0r_fields,
  64248         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64249         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64250         -1,
  64251         -1,
  64252     },
  64253 #endif /* chips */
  64254 
  64255 #if defined(BCM_88690_B0)
  64256     { /* SOC_REG_INT_OLP_RESERVED_MTCP_BCM88690_B0r */
  64257         soc_block_list[42],
  64258         soc_genreg,
  64259         1,
  64260         0,
  64261         0xad,
  64262         SOC_REG_FLAG_64_BITS,
  64263         0,
  64264         17,
  64265         soc_OLP_RESERVED_MTCP_BCM88690_B0r_fields,
  64266         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  64267         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  64268         -1,
  64269         -1,
  64270     },
  64271 #endif /* chips */
  64272 
  64273 #if defined(BCM_88675_A0)
  64274     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0r */
  64275         soc_block_list[42],
  64276         soc_genreg,
  64277         1,
  64278         0,
  64279         0x90,
  64280         0,
  64281         0,
  64282         1,
  64283         soc_OLP_RESERVED_SPARE_0r_fields,
  64284         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64285         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64286         -1,
  64287         -1,
  64288     },
  64289 #endif /* chips */
  64290 
  64291 #if defined(BCM_88675_A0)
  64292     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1r */
  64293         soc_block_list[42],
  64294         soc_genreg,
  64295         1,
  64296         0,
  64297         0x91,
  64298         0,
  64299         0,
  64300         1,
  64301         soc_OLP_RESERVED_SPARE_1r_fields,
  64302         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64303         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64304         -1,
  64305         -1,
  64306     },
  64307 #endif /* chips */
  64308 
  64309 #if defined(BCM_88675_A0)
  64310     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2r */
  64311         soc_block_list[42],
  64312         soc_genreg,
  64313         1,
  64314         0,
  64315         0x92,
  64316         0,
  64317         0,
  64318         1,
  64319         soc_OLP_RESERVED_SPARE_2r_fields,
  64320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64321         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64322         -1,
  64323         -1,
  64324     },
  64325 #endif /* chips */
  64326 
  64327 #if defined(BCM_88675_A0)
  64328     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3r */
  64329         soc_block_list[42],
  64330         soc_genreg,
  64331         1,
  64332         0,
  64333         0x93,
  64334         0,
  64335         0,
  64336         1,
  64337         soc_OLP_RESERVED_SPARE_3r_fields,
  64338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64339         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64340         -1,
  64341         -1,
  64342     },
  64343 #endif /* chips */
  64344 
  64345 #if defined(BCM_88270_A0)
  64346     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0_BCM88270_A0r */
  64347         soc_block_list[42],
  64348         soc_genreg,
  64349         1,
  64350         0,
  64351         0x90,
  64352         0,
  64353         0,
  64354         1,
  64355         soc_OLP_RESERVED_SPARE_0_BCM88270_A0r_fields,
  64356         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64357         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64358         -1,
  64359         -1,
  64360     },
  64361 #endif /* chips */
  64362 
  64363 #if defined(BCM_88375_A0)
  64364     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0_BCM88375_A0r */
  64365         soc_block_list[42],
  64366         soc_genreg,
  64367         1,
  64368         0,
  64369         0x90,
  64370         0,
  64371         0,
  64372         1,
  64373         soc_OLP_RESERVED_SPARE_0_BCM88375_A0r_fields,
  64374         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64375         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64376         -1,
  64377         -1,
  64378     },
  64379 #endif /* chips */
  64380 
  64381 #if defined(BCM_88375_B0)
  64382     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0_BCM88375_B0r */
  64383         soc_block_list[42],
  64384         soc_genreg,
  64385         1,
  64386         0,
  64387         0x90,
  64388         0,
  64389         0,
  64390         1,
  64391         soc_OLP_RESERVED_SPARE_0_BCM88375_B0r_fields,
  64392         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64393         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64394         -1,
  64395         -1,
  64396     },
  64397 #endif /* chips */
  64398 
  64399 #if defined(BCM_88470_A0)
  64400     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0_BCM88470_A0r */
  64401         soc_block_list[42],
  64402         soc_genreg,
  64403         1,
  64404         0,
  64405         0x90,
  64406         0,
  64407         0,
  64408         1,
  64409         soc_OLP_RESERVED_SPARE_0_BCM88470_A0r_fields,
  64410         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64411         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64412         -1,
  64413         -1,
  64414     },
  64415 #endif /* chips */
  64416 
  64417 #if defined(BCM_88470_B0)
  64418     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0_BCM88470_B0r */
  64419         soc_block_list[42],
  64420         soc_genreg,
  64421         1,
  64422         0,
  64423         0x90,
  64424         0,
  64425         0,
  64426         1,
  64427         soc_OLP_RESERVED_SPARE_0_BCM88470_B0r_fields,
  64428         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64429         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64430         -1,
  64431         -1,
  64432     },
  64433 #endif /* chips */
  64434 
  64435 #if defined(BCM_88675_B0)
  64436     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0_BCM88675_B0r */
  64437         soc_block_list[42],
  64438         soc_genreg,
  64439         1,
  64440         0,
  64441         0x90,
  64442         0,
  64443         0,
  64444         1,
  64445         soc_OLP_RESERVED_SPARE_0_BCM88675_B0r_fields,
  64446         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64447         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64448         -1,
  64449         -1,
  64450     },
  64451 #endif /* chips */
  64452 
  64453 #if defined(BCM_88680_A0)
  64454     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0_BCM88680_A0r */
  64455         soc_block_list[42],
  64456         soc_genreg,
  64457         1,
  64458         0,
  64459         0x90,
  64460         0,
  64461         0,
  64462         1,
  64463         soc_OLP_RESERVED_SPARE_0_BCM88680_A0r_fields,
  64464         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64465         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64466         -1,
  64467         -1,
  64468     },
  64469 #endif /* chips */
  64470 
  64471 #if defined(BCM_88690_A0)
  64472     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0_BCM88690_A0r */
  64473         soc_block_list[42],
  64474         soc_genreg,
  64475         1,
  64476         0,
  64477         0x90,
  64478         0,
  64479         0,
  64480         1,
  64481         soc_OLP_RESERVED_SPARE_0_BCM88690_A0r_fields,
  64482         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64483         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64484         -1,
  64485         -1,
  64486     },
  64487 #endif /* chips */
  64488 
  64489 #if defined(BCM_88690_B0)
  64490     { /* SOC_REG_INT_OLP_RESERVED_SPARE_0_BCM88690_B0r */
  64491         soc_block_list[42],
  64492         soc_genreg,
  64493         1,
  64494         0,
  64495         0x90,
  64496         0,
  64497         0,
  64498         1,
  64499         soc_OLP_RESERVED_SPARE_0_BCM88690_B0r_fields,
  64500         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64501         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64502         -1,
  64503         -1,
  64504     },
  64505 #endif /* chips */
  64506 
  64507 #if defined(BCM_88270_A0)
  64508     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1_BCM88270_A0r */
  64509         soc_block_list[42],
  64510         soc_genreg,
  64511         1,
  64512         0,
  64513         0x91,
  64514         0,
  64515         0,
  64516         1,
  64517         soc_OLP_RESERVED_SPARE_1_BCM88270_A0r_fields,
  64518         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64519         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64520         -1,
  64521         -1,
  64522     },
  64523 #endif /* chips */
  64524 
  64525 #if defined(BCM_88375_A0)
  64526     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1_BCM88375_A0r */
  64527         soc_block_list[42],
  64528         soc_genreg,
  64529         1,
  64530         0,
  64531         0x91,
  64532         0,
  64533         0,
  64534         1,
  64535         soc_OLP_RESERVED_SPARE_1_BCM88375_A0r_fields,
  64536         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64538         -1,
  64539         -1,
  64540     },
  64541 #endif /* chips */
  64542 
  64543 #if defined(BCM_88375_B0)
  64544     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1_BCM88375_B0r */
  64545         soc_block_list[42],
  64546         soc_genreg,
  64547         1,
  64548         0,
  64549         0x91,
  64550         0,
  64551         0,
  64552         1,
  64553         soc_OLP_RESERVED_SPARE_1_BCM88375_B0r_fields,
  64554         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64555         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64556         -1,
  64557         -1,
  64558     },
  64559 #endif /* chips */
  64560 
  64561 #if defined(BCM_88470_A0)
  64562     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1_BCM88470_A0r */
  64563         soc_block_list[42],
  64564         soc_genreg,
  64565         1,
  64566         0,
  64567         0x91,
  64568         0,
  64569         0,
  64570         1,
  64571         soc_OLP_RESERVED_SPARE_1_BCM88470_A0r_fields,
  64572         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64573         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64574         -1,
  64575         -1,
  64576     },
  64577 #endif /* chips */
  64578 
  64579 #if defined(BCM_88470_B0)
  64580     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1_BCM88470_B0r */
  64581         soc_block_list[42],
  64582         soc_genreg,
  64583         1,
  64584         0,
  64585         0x91,
  64586         0,
  64587         0,
  64588         1,
  64589         soc_OLP_RESERVED_SPARE_1_BCM88470_B0r_fields,
  64590         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64591         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64592         -1,
  64593         -1,
  64594     },
  64595 #endif /* chips */
  64596 
  64597 #if defined(BCM_88675_B0)
  64598     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1_BCM88675_B0r */
  64599         soc_block_list[42],
  64600         soc_genreg,
  64601         1,
  64602         0,
  64603         0x91,
  64604         0,
  64605         0,
  64606         1,
  64607         soc_OLP_RESERVED_SPARE_1_BCM88675_B0r_fields,
  64608         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64609         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64610         -1,
  64611         -1,
  64612     },
  64613 #endif /* chips */
  64614 
  64615 #if defined(BCM_88680_A0)
  64616     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1_BCM88680_A0r */
  64617         soc_block_list[42],
  64618         soc_genreg,
  64619         1,
  64620         0,
  64621         0x91,
  64622         0,
  64623         0,
  64624         1,
  64625         soc_OLP_RESERVED_SPARE_1_BCM88680_A0r_fields,
  64626         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64627         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64628         -1,
  64629         -1,
  64630     },
  64631 #endif /* chips */
  64632 
  64633 #if defined(BCM_88690_A0)
  64634     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1_BCM88690_A0r */
  64635         soc_block_list[42],
  64636         soc_genreg,
  64637         1,
  64638         0,
  64639         0x91,
  64640         0,
  64641         0,
  64642         1,
  64643         soc_OLP_RESERVED_SPARE_1_BCM88690_A0r_fields,
  64644         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64646         -1,
  64647         -1,
  64648     },
  64649 #endif /* chips */
  64650 
  64651 #if defined(BCM_88690_B0)
  64652     { /* SOC_REG_INT_OLP_RESERVED_SPARE_1_BCM88690_B0r */
  64653         soc_block_list[42],
  64654         soc_genreg,
  64655         1,
  64656         0,
  64657         0x91,
  64658         0,
  64659         0,
  64660         1,
  64661         soc_OLP_RESERVED_SPARE_1_BCM88690_B0r_fields,
  64662         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  64663         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64664         -1,
  64665         -1,
  64666     },
  64667 #endif /* chips */
  64668 
  64669 #if defined(BCM_88270_A0)
  64670     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2_BCM88270_A0r */
  64671         soc_block_list[42],
  64672         soc_genreg,
  64673         1,
  64674         0,
  64675         0x92,
  64676         0,
  64677         0,
  64678         1,
  64679         soc_OLP_RESERVED_SPARE_2_BCM88270_A0r_fields,
  64680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64681         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64682         -1,
  64683         -1,
  64684     },
  64685 #endif /* chips */
  64686 
  64687 #if defined(BCM_88375_A0)
  64688     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2_BCM88375_A0r */
  64689         soc_block_list[42],
  64690         soc_genreg,
  64691         1,
  64692         0,
  64693         0x92,
  64694         0,
  64695         0,
  64696         1,
  64697         soc_OLP_RESERVED_SPARE_2_BCM88375_A0r_fields,
  64698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64700         -1,
  64701         -1,
  64702     },
  64703 #endif /* chips */
  64704 
  64705 #if defined(BCM_88375_B0)
  64706     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2_BCM88375_B0r */
  64707         soc_block_list[42],
  64708         soc_genreg,
  64709         1,
  64710         0,
  64711         0x92,
  64712         0,
  64713         0,
  64714         1,
  64715         soc_OLP_RESERVED_SPARE_2_BCM88375_B0r_fields,
  64716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64718         -1,
  64719         -1,
  64720     },
  64721 #endif /* chips */
  64722 
  64723 #if defined(BCM_88470_A0)
  64724     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2_BCM88470_A0r */
  64725         soc_block_list[42],
  64726         soc_genreg,
  64727         1,
  64728         0,
  64729         0x92,
  64730         0,
  64731         0,
  64732         1,
  64733         soc_OLP_RESERVED_SPARE_2_BCM88470_A0r_fields,
  64734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64736         -1,
  64737         -1,
  64738     },
  64739 #endif /* chips */
  64740 
  64741 #if defined(BCM_88470_B0)
  64742     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2_BCM88470_B0r */
  64743         soc_block_list[42],
  64744         soc_genreg,
  64745         1,
  64746         0,
  64747         0x92,
  64748         0,
  64749         0,
  64750         1,
  64751         soc_OLP_RESERVED_SPARE_2_BCM88470_B0r_fields,
  64752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64754         -1,
  64755         -1,
  64756     },
  64757 #endif /* chips */
  64758 
  64759 #if defined(BCM_88675_B0)
  64760     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2_BCM88675_B0r */
  64761         soc_block_list[42],
  64762         soc_genreg,
  64763         1,
  64764         0,
  64765         0x92,
  64766         0,
  64767         0,
  64768         1,
  64769         soc_OLP_RESERVED_SPARE_2_BCM88675_B0r_fields,
  64770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64772         -1,
  64773         -1,
  64774     },
  64775 #endif /* chips */
  64776 
  64777 #if defined(BCM_88680_A0)
  64778     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2_BCM88680_A0r */
  64779         soc_block_list[42],
  64780         soc_genreg,
  64781         1,
  64782         0,
  64783         0x92,
  64784         0,
  64785         0,
  64786         1,
  64787         soc_OLP_RESERVED_SPARE_2_BCM88680_A0r_fields,
  64788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64789         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64790         -1,
  64791         -1,
  64792     },
  64793 #endif /* chips */
  64794 
  64795 #if defined(BCM_88690_A0)
  64796     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2_BCM88690_A0r */
  64797         soc_block_list[42],
  64798         soc_genreg,
  64799         1,
  64800         0,
  64801         0x92,
  64802         0,
  64803         0,
  64804         1,
  64805         soc_OLP_RESERVED_SPARE_2_BCM88690_A0r_fields,
  64806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64807         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64808         -1,
  64809         -1,
  64810     },
  64811 #endif /* chips */
  64812 
  64813 #if defined(BCM_88690_B0)
  64814     { /* SOC_REG_INT_OLP_RESERVED_SPARE_2_BCM88690_B0r */
  64815         soc_block_list[42],
  64816         soc_genreg,
  64817         1,
  64818         0,
  64819         0x92,
  64820         0,
  64821         0,
  64822         1,
  64823         soc_OLP_RESERVED_SPARE_2_BCM88690_B0r_fields,
  64824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64825         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64826         -1,
  64827         -1,
  64828     },
  64829 #endif /* chips */
  64830 
  64831 #if defined(BCM_88270_A0)
  64832     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3_BCM88270_A0r */
  64833         soc_block_list[42],
  64834         soc_genreg,
  64835         1,
  64836         0,
  64837         0x93,
  64838         0,
  64839         0,
  64840         1,
  64841         soc_OLP_RESERVED_SPARE_3_BCM88270_A0r_fields,
  64842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64843         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64844         -1,
  64845         -1,
  64846     },
  64847 #endif /* chips */
  64848 
  64849 #if defined(BCM_88375_A0)
  64850     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3_BCM88375_A0r */
  64851         soc_block_list[42],
  64852         soc_genreg,
  64853         1,
  64854         0,
  64855         0x93,
  64856         0,
  64857         0,
  64858         1,
  64859         soc_OLP_RESERVED_SPARE_3_BCM88375_A0r_fields,
  64860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64861         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64862         -1,
  64863         -1,
  64864     },
  64865 #endif /* chips */
  64866 
  64867 #if defined(BCM_88375_B0)
  64868     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3_BCM88375_B0r */
  64869         soc_block_list[42],
  64870         soc_genreg,
  64871         1,
  64872         0,
  64873         0x93,
  64874         0,
  64875         0,
  64876         1,
  64877         soc_OLP_RESERVED_SPARE_3_BCM88375_B0r_fields,
  64878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64879         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64880         -1,
  64881         -1,
  64882     },
  64883 #endif /* chips */
  64884 
  64885 #if defined(BCM_88470_A0)
  64886     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3_BCM88470_A0r */
  64887         soc_block_list[42],
  64888         soc_genreg,
  64889         1,
  64890         0,
  64891         0x93,
  64892         0,
  64893         0,
  64894         1,
  64895         soc_OLP_RESERVED_SPARE_3_BCM88470_A0r_fields,
  64896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64898         -1,
  64899         -1,
  64900     },
  64901 #endif /* chips */
  64902 
  64903 #if defined(BCM_88470_B0)
  64904     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3_BCM88470_B0r */
  64905         soc_block_list[42],
  64906         soc_genreg,
  64907         1,
  64908         0,
  64909         0x93,
  64910         0,
  64911         0,
  64912         1,
  64913         soc_OLP_RESERVED_SPARE_3_BCM88470_B0r_fields,
  64914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64916         -1,
  64917         -1,
  64918     },
  64919 #endif /* chips */
  64920 
  64921 #if defined(BCM_88675_B0)
  64922     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3_BCM88675_B0r */
  64923         soc_block_list[42],
  64924         soc_genreg,
  64925         1,
  64926         0,
  64927         0x93,
  64928         0,
  64929         0,
  64930         1,
  64931         soc_OLP_RESERVED_SPARE_3_BCM88675_B0r_fields,
  64932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64933         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64934         -1,
  64935         -1,
  64936     },
  64937 #endif /* chips */
  64938 
  64939 #if defined(BCM_88680_A0)
  64940     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3_BCM88680_A0r */
  64941         soc_block_list[42],
  64942         soc_genreg,
  64943         1,
  64944         0,
  64945         0x93,
  64946         0,
  64947         0,
  64948         1,
  64949         soc_OLP_RESERVED_SPARE_3_BCM88680_A0r_fields,
  64950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64952         -1,
  64953         -1,
  64954     },
  64955 #endif /* chips */
  64956 
  64957 #if defined(BCM_88690_A0)
  64958     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3_BCM88690_A0r */
  64959         soc_block_list[42],
  64960         soc_genreg,
  64961         1,
  64962         0,
  64963         0x93,
  64964         0,
  64965         0,
  64966         1,
  64967         soc_OLP_RESERVED_SPARE_3_BCM88690_A0r_fields,
  64968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64969         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64970         -1,
  64971         -1,
  64972     },
  64973 #endif /* chips */
  64974 
  64975 #if defined(BCM_88690_B0)
  64976     { /* SOC_REG_INT_OLP_RESERVED_SPARE_3_BCM88690_B0r */
  64977         soc_block_list[42],
  64978         soc_genreg,
  64979         1,
  64980         0,
  64981         0x93,
  64982         0,
  64983         0,
  64984         1,
  64985         soc_OLP_RESERVED_SPARE_3_BCM88690_B0r_fields,
  64986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64987         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64988         -1,
  64989         -1,
  64990     },
  64991 #endif /* chips */
  64992 
  64993 #if defined(BCM_88650_A0)
  64994     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICEr */
  64995         soc_block_list[42],
  64996         soc_genreg,
  64997         1,
  64998         0,
  64999         0x103,
  65000         SOC_REG_FLAG_64_BITS |
  65001                           SOC_REG_FLAG_SIGNAL,
  65002         0,
  65003         4,
  65004         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICEr_fields,
  65005         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65006         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65007         -1,
  65008         -1,
  65009     },
  65010 #endif /* chips */
  65011 
  65012 #if defined(BCM_88270_A0)
  65013     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88270_A0r */
  65014         soc_block_list[42],
  65015         soc_genreg,
  65016         1,
  65017         0,
  65018         0x104,
  65019         SOC_REG_FLAG_64_BITS,
  65020         0,
  65021         4,
  65022         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88270_A0r_fields,
  65023         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65024         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65025         -1,
  65026         -1,
  65027     },
  65028 #endif /* chips */
  65029 
  65030 #if defined(BCM_88375_A0)
  65031     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88375_A0r */
  65032         soc_block_list[42],
  65033         soc_genreg,
  65034         1,
  65035         0,
  65036         0x104,
  65037         SOC_REG_FLAG_64_BITS,
  65038         0,
  65039         4,
  65040         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88375_A0r_fields,
  65041         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65042         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65043         -1,
  65044         -1,
  65045     },
  65046 #endif /* chips */
  65047 
  65048 #if defined(BCM_88375_B0)
  65049     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88375_B0r */
  65050         soc_block_list[42],
  65051         soc_genreg,
  65052         1,
  65053         0,
  65054         0x104,
  65055         SOC_REG_FLAG_64_BITS,
  65056         0,
  65057         4,
  65058         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88375_B0r_fields,
  65059         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65060         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65061         -1,
  65062         -1,
  65063     },
  65064 #endif /* chips */
  65065 
  65066 #if defined(BCM_88470_A0)
  65067     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88470_A0r */
  65068         soc_block_list[42],
  65069         soc_genreg,
  65070         1,
  65071         0,
  65072         0x104,
  65073         SOC_REG_FLAG_64_BITS,
  65074         0,
  65075         4,
  65076         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88470_A0r_fields,
  65077         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65078         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65079         -1,
  65080         -1,
  65081     },
  65082 #endif /* chips */
  65083 
  65084 #if defined(BCM_88470_B0)
  65085     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88470_B0r */
  65086         soc_block_list[42],
  65087         soc_genreg,
  65088         1,
  65089         0,
  65090         0x104,
  65091         SOC_REG_FLAG_64_BITS,
  65092         0,
  65093         4,
  65094         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88470_B0r_fields,
  65095         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65096         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65097         -1,
  65098         -1,
  65099     },
  65100 #endif /* chips */
  65101 
  65102 #if defined(BCM_88650_B0)
  65103     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88650_B0r */
  65104         soc_block_list[42],
  65105         soc_genreg,
  65106         1,
  65107         0,
  65108         0x103,
  65109         SOC_REG_FLAG_64_BITS |
  65110                           SOC_REG_FLAG_SIGNAL,
  65111         0,
  65112         4,
  65113         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88650_B0r_fields,
  65114         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65115         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65116         -1,
  65117         -1,
  65118     },
  65119 #endif /* chips */
  65120 
  65121 #if defined(BCM_88660_A0)
  65122     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88660_A0r */
  65123         soc_block_list[42],
  65124         soc_genreg,
  65125         1,
  65126         0,
  65127         0x103,
  65128         SOC_REG_FLAG_64_BITS |
  65129                           SOC_REG_FLAG_SIGNAL,
  65130         0,
  65131         4,
  65132         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88660_A0r_fields,
  65133         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65134         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65135         -1,
  65136         -1,
  65137     },
  65138 #endif /* chips */
  65139 
  65140 #if defined(BCM_88675_A0)
  65141     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88675_A0r */
  65142         soc_block_list[42],
  65143         soc_genreg,
  65144         1,
  65145         0,
  65146         0x104,
  65147         SOC_REG_FLAG_64_BITS,
  65148         0,
  65149         4,
  65150         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88675_A0r_fields,
  65151         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65152         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65153         -1,
  65154         -1,
  65155     },
  65156 #endif /* chips */
  65157 
  65158 #if defined(BCM_88675_B0)
  65159     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88675_B0r */
  65160         soc_block_list[42],
  65161         soc_genreg,
  65162         1,
  65163         0,
  65164         0x104,
  65165         SOC_REG_FLAG_64_BITS,
  65166         0,
  65167         4,
  65168         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88675_B0r_fields,
  65169         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65170         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65171         -1,
  65172         -1,
  65173     },
  65174 #endif /* chips */
  65175 
  65176 #if defined(BCM_88680_A0)
  65177     { /* SOC_REG_INT_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88680_A0r */
  65178         soc_block_list[42],
  65179         soc_genreg,
  65180         1,
  65181         0,
  65182         0x104,
  65183         SOC_REG_FLAG_64_BITS,
  65184         0,
  65185         4,
  65186         soc_OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE_BCM88680_A0r_fields,
  65187         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65188         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65189         -1,
  65190         -1,
  65191     },
  65192 #endif /* chips */
  65193 
  65194 #if defined(BCM_88690_A0)
  65195     { /* SOC_REG_INT_OLP_RX_CONFIGS_BCM_86650_DSP_SOURCE_DEVICEr */
  65196         soc_block_list[42],
  65197         soc_genreg,
  65198         1,
  65199         0,
  65200         0x112,
  65201         SOC_REG_FLAG_64_BITS,
  65202         0,
  65203         4,
  65204         soc_OLP_RX_CONFIGS_BCM_86650_DSP_SOURCE_DEVICEr_fields,
  65205         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65206         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65207         -1,
  65208         -1,
  65209     },
  65210 #endif /* chips */
  65211 
  65212 #if defined(BCM_88690_B0)
  65213     { /* SOC_REG_INT_OLP_RX_CONFIGS_BCM_86650_DSP_SOURCE_DEVICE_BCM88690_B0r */
  65214         soc_block_list[42],
  65215         soc_genreg,
  65216         1,
  65217         0,
  65218         0x112,
  65219         SOC_REG_FLAG_64_BITS,
  65220         0,
  65221         4,
  65222         soc_OLP_RX_CONFIGS_BCM_86650_DSP_SOURCE_DEVICE_BCM88690_B0r_fields,
  65223         SOC_RESET_VAL_DEC(0x0000000e, 0x00000000)
  65224         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65225         -1,
  65226         -1,
  65227     },
  65228 #endif /* chips */
  65229 
  65230 #if defined(BCM_88650_A0)
  65231     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIERr */
  65232         soc_block_list[42],
  65233         soc_genreg,
  65234         1,
  65235         0,
  65236         0x101,
  65237         SOC_REG_FLAG_64_BITS |
  65238                           SOC_REG_FLAG_SIGNAL,
  65239         0,
  65240         4,
  65241         soc_OLP_RX_CONFIGS_DSP_IDENTIFIERr_fields,
  65242         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65243         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65244         -1,
  65245         -1,
  65246     },
  65247 #endif /* chips */
  65248 
  65249 #if defined(BCM_88270_A0)
  65250     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88270_A0r */
  65251         soc_block_list[42],
  65252         soc_genreg,
  65253         1,
  65254         0,
  65255         0x102,
  65256         SOC_REG_FLAG_64_BITS,
  65257         0,
  65258         4,
  65259         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88270_A0r_fields,
  65260         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65261         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65262         -1,
  65263         -1,
  65264     },
  65265 #endif /* chips */
  65266 
  65267 #if defined(BCM_88375_A0)
  65268     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88375_A0r */
  65269         soc_block_list[42],
  65270         soc_genreg,
  65271         1,
  65272         0,
  65273         0x102,
  65274         SOC_REG_FLAG_64_BITS,
  65275         0,
  65276         4,
  65277         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88375_A0r_fields,
  65278         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65279         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65280         -1,
  65281         -1,
  65282     },
  65283 #endif /* chips */
  65284 
  65285 #if defined(BCM_88375_B0)
  65286     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88375_B0r */
  65287         soc_block_list[42],
  65288         soc_genreg,
  65289         1,
  65290         0,
  65291         0x102,
  65292         SOC_REG_FLAG_64_BITS,
  65293         0,
  65294         4,
  65295         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88375_B0r_fields,
  65296         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65297         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65298         -1,
  65299         -1,
  65300     },
  65301 #endif /* chips */
  65302 
  65303 #if defined(BCM_88470_A0)
  65304     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88470_A0r */
  65305         soc_block_list[42],
  65306         soc_genreg,
  65307         1,
  65308         0,
  65309         0x102,
  65310         SOC_REG_FLAG_64_BITS,
  65311         0,
  65312         4,
  65313         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88470_A0r_fields,
  65314         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65315         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65316         -1,
  65317         -1,
  65318     },
  65319 #endif /* chips */
  65320 
  65321 #if defined(BCM_88470_B0)
  65322     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88470_B0r */
  65323         soc_block_list[42],
  65324         soc_genreg,
  65325         1,
  65326         0,
  65327         0x102,
  65328         SOC_REG_FLAG_64_BITS,
  65329         0,
  65330         4,
  65331         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88470_B0r_fields,
  65332         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65333         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65334         -1,
  65335         -1,
  65336     },
  65337 #endif /* chips */
  65338 
  65339 #if defined(BCM_88650_B0)
  65340     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88650_B0r */
  65341         soc_block_list[42],
  65342         soc_genreg,
  65343         1,
  65344         0,
  65345         0x101,
  65346         SOC_REG_FLAG_64_BITS |
  65347                           SOC_REG_FLAG_SIGNAL,
  65348         0,
  65349         4,
  65350         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88650_B0r_fields,
  65351         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65352         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65353         -1,
  65354         -1,
  65355     },
  65356 #endif /* chips */
  65357 
  65358 #if defined(BCM_88660_A0)
  65359     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88660_A0r */
  65360         soc_block_list[42],
  65361         soc_genreg,
  65362         1,
  65363         0,
  65364         0x101,
  65365         SOC_REG_FLAG_64_BITS |
  65366                           SOC_REG_FLAG_SIGNAL,
  65367         0,
  65368         4,
  65369         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88660_A0r_fields,
  65370         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65371         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65372         -1,
  65373         -1,
  65374     },
  65375 #endif /* chips */
  65376 
  65377 #if defined(BCM_88675_A0)
  65378     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88675_A0r */
  65379         soc_block_list[42],
  65380         soc_genreg,
  65381         1,
  65382         0,
  65383         0x102,
  65384         SOC_REG_FLAG_64_BITS,
  65385         0,
  65386         4,
  65387         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88675_A0r_fields,
  65388         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65389         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65390         -1,
  65391         -1,
  65392     },
  65393 #endif /* chips */
  65394 
  65395 #if defined(BCM_88675_B0)
  65396     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88675_B0r */
  65397         soc_block_list[42],
  65398         soc_genreg,
  65399         1,
  65400         0,
  65401         0x102,
  65402         SOC_REG_FLAG_64_BITS,
  65403         0,
  65404         4,
  65405         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88675_B0r_fields,
  65406         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65407         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65408         -1,
  65409         -1,
  65410     },
  65411 #endif /* chips */
  65412 
  65413 #if defined(BCM_88680_A0)
  65414     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88680_A0r */
  65415         soc_block_list[42],
  65416         soc_genreg,
  65417         1,
  65418         0,
  65419         0x102,
  65420         SOC_REG_FLAG_64_BITS,
  65421         0,
  65422         4,
  65423         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88680_A0r_fields,
  65424         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65425         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65426         -1,
  65427         -1,
  65428     },
  65429 #endif /* chips */
  65430 
  65431 #if defined(BCM_88690_A0)
  65432     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88690_A0r */
  65433         soc_block_list[42],
  65434         soc_genreg,
  65435         1,
  65436         0,
  65437         0x110,
  65438         SOC_REG_FLAG_64_BITS,
  65439         0,
  65440         4,
  65441         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88690_A0r_fields,
  65442         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65443         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65444         -1,
  65445         -1,
  65446     },
  65447 #endif /* chips */
  65448 
  65449 #if defined(BCM_88690_B0)
  65450     { /* SOC_REG_INT_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88690_B0r */
  65451         soc_block_list[42],
  65452         soc_genreg,
  65453         1,
  65454         0,
  65455         0x110,
  65456         SOC_REG_FLAG_64_BITS,
  65457         0,
  65458         4,
  65459         soc_OLP_RX_CONFIGS_DSP_IDENTIFIER_BCM88690_B0r_fields,
  65460         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  65461         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  65462         -1,
  65463         -1,
  65464     },
  65465 #endif /* chips */
  65466 
  65467 #if defined(BCM_88650_A0)
  65468     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERALr */
  65469         soc_block_list[42],
  65470         soc_genreg,
  65471         1,
  65472         0,
  65473         0x105,
  65474         SOC_REG_FLAG_SIGNAL,
  65475         0,
  65476         2,
  65477         soc_OLP_RX_CONFIGS_GENERALr_fields,
  65478         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65479         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65480         -1,
  65481         -1,
  65482     },
  65483 #endif /* chips */
  65484 
  65485 #if defined(BCM_88270_A0)
  65486     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88270_A0r */
  65487         soc_block_list[42],
  65488         soc_genreg,
  65489         1,
  65490         0,
  65491         0x106,
  65492         0,
  65493         0,
  65494         1,
  65495         soc_OLP_RX_CONFIGS_GENERAL_BCM88270_A0r_fields,
  65496         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65497         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65498         -1,
  65499         -1,
  65500     },
  65501 #endif /* chips */
  65502 
  65503 #if defined(BCM_88375_A0)
  65504     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88375_A0r */
  65505         soc_block_list[42],
  65506         soc_genreg,
  65507         1,
  65508         0,
  65509         0x106,
  65510         0,
  65511         0,
  65512         1,
  65513         soc_OLP_RX_CONFIGS_GENERAL_BCM88375_A0r_fields,
  65514         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65515         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65516         -1,
  65517         -1,
  65518     },
  65519 #endif /* chips */
  65520 
  65521 #if defined(BCM_88375_B0)
  65522     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88375_B0r */
  65523         soc_block_list[42],
  65524         soc_genreg,
  65525         1,
  65526         0,
  65527         0x106,
  65528         0,
  65529         0,
  65530         1,
  65531         soc_OLP_RX_CONFIGS_GENERAL_BCM88375_B0r_fields,
  65532         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65533         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65534         -1,
  65535         -1,
  65536     },
  65537 #endif /* chips */
  65538 
  65539 #if defined(BCM_88470_A0)
  65540     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88470_A0r */
  65541         soc_block_list[42],
  65542         soc_genreg,
  65543         1,
  65544         0,
  65545         0x106,
  65546         0,
  65547         0,
  65548         1,
  65549         soc_OLP_RX_CONFIGS_GENERAL_BCM88470_A0r_fields,
  65550         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65551         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65552         -1,
  65553         -1,
  65554     },
  65555 #endif /* chips */
  65556 
  65557 #if defined(BCM_88470_B0)
  65558     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88470_B0r */
  65559         soc_block_list[42],
  65560         soc_genreg,
  65561         1,
  65562         0,
  65563         0x106,
  65564         0,
  65565         0,
  65566         1,
  65567         soc_OLP_RX_CONFIGS_GENERAL_BCM88470_B0r_fields,
  65568         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65569         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65570         -1,
  65571         -1,
  65572     },
  65573 #endif /* chips */
  65574 
  65575 #if defined(BCM_88650_B0)
  65576     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88650_B0r */
  65577         soc_block_list[42],
  65578         soc_genreg,
  65579         1,
  65580         0,
  65581         0x105,
  65582         SOC_REG_FLAG_SIGNAL,
  65583         0,
  65584         2,
  65585         soc_OLP_RX_CONFIGS_GENERAL_BCM88650_B0r_fields,
  65586         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65587         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65588         -1,
  65589         -1,
  65590     },
  65591 #endif /* chips */
  65592 
  65593 #if defined(BCM_88660_A0)
  65594     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88660_A0r */
  65595         soc_block_list[42],
  65596         soc_genreg,
  65597         1,
  65598         0,
  65599         0x105,
  65600         SOC_REG_FLAG_SIGNAL,
  65601         0,
  65602         2,
  65603         soc_OLP_RX_CONFIGS_GENERAL_BCM88660_A0r_fields,
  65604         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65605         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65606         -1,
  65607         -1,
  65608     },
  65609 #endif /* chips */
  65610 
  65611 #if defined(BCM_88675_A0)
  65612     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88675_A0r */
  65613         soc_block_list[42],
  65614         soc_genreg,
  65615         1,
  65616         0,
  65617         0x106,
  65618         0,
  65619         0,
  65620         1,
  65621         soc_OLP_RX_CONFIGS_GENERAL_BCM88675_A0r_fields,
  65622         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65623         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65624         -1,
  65625         -1,
  65626     },
  65627 #endif /* chips */
  65628 
  65629 #if defined(BCM_88675_B0)
  65630     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88675_B0r */
  65631         soc_block_list[42],
  65632         soc_genreg,
  65633         1,
  65634         0,
  65635         0x106,
  65636         0,
  65637         0,
  65638         1,
  65639         soc_OLP_RX_CONFIGS_GENERAL_BCM88675_B0r_fields,
  65640         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65641         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65642         -1,
  65643         -1,
  65644     },
  65645 #endif /* chips */
  65646 
  65647 #if defined(BCM_88680_A0)
  65648     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88680_A0r */
  65649         soc_block_list[42],
  65650         soc_genreg,
  65651         1,
  65652         0,
  65653         0x106,
  65654         0,
  65655         0,
  65656         1,
  65657         soc_OLP_RX_CONFIGS_GENERAL_BCM88680_A0r_fields,
  65658         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65659         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65660         -1,
  65661         -1,
  65662     },
  65663 #endif /* chips */
  65664 
  65665 #if defined(BCM_88690_A0)
  65666     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88690_A0r */
  65667         soc_block_list[42],
  65668         soc_genreg,
  65669         1,
  65670         0,
  65671         0x114,
  65672         0,
  65673         0,
  65674         1,
  65675         soc_OLP_RX_CONFIGS_GENERAL_BCM88690_A0r_fields,
  65676         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65677         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65678         -1,
  65679         -1,
  65680     },
  65681 #endif /* chips */
  65682 
  65683 #if defined(BCM_88690_B0)
  65684     { /* SOC_REG_INT_OLP_RX_CONFIGS_GENERAL_BCM88690_B0r */
  65685         soc_block_list[42],
  65686         soc_genreg,
  65687         1,
  65688         0,
  65689         0x114,
  65690         0,
  65691         0,
  65692         1,
  65693         soc_OLP_RX_CONFIGS_GENERAL_BCM88690_B0r_fields,
  65694         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  65695         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65696         -1,
  65697         -1,
  65698     },
  65699 #endif /* chips */
  65700 
  65701 #if defined(BCM_88650_A0)
  65702     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_IDr */
  65703         soc_block_list[42],
  65704         soc_genreg,
  65705         1,
  65706         0,
  65707         0x86,
  65708         SOC_REG_FLAG_SIGNAL,
  65709         0,
  65710         1,
  65711         soc_OLP_SBUS_BROADCAST_IDr_fields,
  65712         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  65713         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65714         -1,
  65715         -1,
  65716     },
  65717 #endif /* chips */
  65718 
  65719 #if defined(BCM_88270_A0)
  65720     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88270_A0r */
  65721         soc_block_list[42],
  65722         soc_genreg,
  65723         1,
  65724         0,
  65725         0x86,
  65726         0,
  65727         0,
  65728         1,
  65729         soc_OLP_SBUS_BROADCAST_ID_BCM88270_A0r_fields,
  65730         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  65731         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65732         -1,
  65733         -1,
  65734     },
  65735 #endif /* chips */
  65736 
  65737 #if defined(BCM_88375_A0)
  65738     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88375_A0r */
  65739         soc_block_list[42],
  65740         soc_genreg,
  65741         1,
  65742         0,
  65743         0x86,
  65744         0,
  65745         0,
  65746         1,
  65747         soc_OLP_SBUS_BROADCAST_ID_BCM88375_A0r_fields,
  65748         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  65749         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65750         -1,
  65751         -1,
  65752     },
  65753 #endif /* chips */
  65754 
  65755 #if defined(BCM_88375_B0)
  65756     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88375_B0r */
  65757         soc_block_list[42],
  65758         soc_genreg,
  65759         1,
  65760         0,
  65761         0x86,
  65762         0,
  65763         0,
  65764         1,
  65765         soc_OLP_SBUS_BROADCAST_ID_BCM88375_B0r_fields,
  65766         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  65767         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65768         -1,
  65769         -1,
  65770     },
  65771 #endif /* chips */
  65772 
  65773 #if defined(BCM_88470_A0)
  65774     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88470_A0r */
  65775         soc_block_list[42],
  65776         soc_genreg,
  65777         1,
  65778         0,
  65779         0x86,
  65780         0,
  65781         0,
  65782         1,
  65783         soc_OLP_SBUS_BROADCAST_ID_BCM88470_A0r_fields,
  65784         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  65785         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65786         -1,
  65787         -1,
  65788     },
  65789 #endif /* chips */
  65790 
  65791 #if defined(BCM_88470_B0)
  65792     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88470_B0r */
  65793         soc_block_list[42],
  65794         soc_genreg,
  65795         1,
  65796         0,
  65797         0x86,
  65798         0,
  65799         0,
  65800         1,
  65801         soc_OLP_SBUS_BROADCAST_ID_BCM88470_B0r_fields,
  65802         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  65803         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65804         -1,
  65805         -1,
  65806     },
  65807 #endif /* chips */
  65808 
  65809 #if defined(BCM_88650_B0)
  65810     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88650_B0r */
  65811         soc_block_list[42],
  65812         soc_genreg,
  65813         1,
  65814         0,
  65815         0x86,
  65816         SOC_REG_FLAG_SIGNAL,
  65817         0,
  65818         1,
  65819         soc_OLP_SBUS_BROADCAST_ID_BCM88650_B0r_fields,
  65820         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  65821         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65822         -1,
  65823         -1,
  65824     },
  65825 #endif /* chips */
  65826 
  65827 #if defined(BCM_88660_A0)
  65828     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88660_A0r */
  65829         soc_block_list[42],
  65830         soc_genreg,
  65831         1,
  65832         0,
  65833         0x86,
  65834         SOC_REG_FLAG_SIGNAL,
  65835         0,
  65836         1,
  65837         soc_OLP_SBUS_BROADCAST_ID_BCM88660_A0r_fields,
  65838         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  65839         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65840         -1,
  65841         -1,
  65842     },
  65843 #endif /* chips */
  65844 
  65845 #if defined(BCM_88675_A0)
  65846     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88675_A0r */
  65847         soc_block_list[42],
  65848         soc_genreg,
  65849         1,
  65850         0,
  65851         0x86,
  65852         0,
  65853         0,
  65854         1,
  65855         soc_OLP_SBUS_BROADCAST_ID_BCM88675_A0r_fields,
  65856         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  65857         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65858         -1,
  65859         -1,
  65860     },
  65861 #endif /* chips */
  65862 
  65863 #if defined(BCM_88675_B0)
  65864     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88675_B0r */
  65865         soc_block_list[42],
  65866         soc_genreg,
  65867         1,
  65868         0,
  65869         0x86,
  65870         0,
  65871         0,
  65872         1,
  65873         soc_OLP_SBUS_BROADCAST_ID_BCM88675_B0r_fields,
  65874         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  65875         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65876         -1,
  65877         -1,
  65878     },
  65879 #endif /* chips */
  65880 
  65881 #if defined(BCM_88680_A0)
  65882     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88680_A0r */
  65883         soc_block_list[42],
  65884         soc_genreg,
  65885         1,
  65886         0,
  65887         0x86,
  65888         0,
  65889         0,
  65890         1,
  65891         soc_OLP_SBUS_BROADCAST_ID_BCM88680_A0r_fields,
  65892         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  65893         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  65894         -1,
  65895         -1,
  65896     },
  65897 #endif /* chips */
  65898 
  65899 #if defined(BCM_88690_A0)
  65900     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88690_A0r */
  65901         soc_block_list[42],
  65902         soc_genreg,
  65903         1,
  65904         0,
  65905         0x86,
  65906         0,
  65907         0,
  65908         1,
  65909         soc_OLP_SBUS_BROADCAST_ID_BCM88690_A0r_fields,
  65910         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  65911         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  65912         -1,
  65913         -1,
  65914     },
  65915 #endif /* chips */
  65916 
  65917 #if defined(BCM_88690_B0)
  65918     { /* SOC_REG_INT_OLP_SBUS_BROADCAST_ID_BCM88690_B0r */
  65919         soc_block_list[42],
  65920         soc_genreg,
  65921         1,
  65922         0,
  65923         0x86,
  65924         0,
  65925         0,
  65926         1,
  65927         soc_OLP_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
  65928         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  65929         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  65930         -1,
  65931         -1,
  65932     },
  65933 #endif /* chips */
  65934 
  65935 #if defined(BCM_88650_A0)
  65936     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAINr */
  65937         soc_block_list[42],
  65938         soc_genreg,
  65939         1,
  65940         0,
  65941         0x87,
  65942         SOC_REG_FLAG_SIGNAL,
  65943         0,
  65944         1,
  65945         soc_OLP_SBUS_LAST_IN_CHAINr_fields,
  65946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65947         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65948         -1,
  65949         -1,
  65950     },
  65951 #endif /* chips */
  65952 
  65953 #if defined(BCM_88270_A0)
  65954     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88270_A0r */
  65955         soc_block_list[42],
  65956         soc_genreg,
  65957         1,
  65958         0,
  65959         0x87,
  65960         0,
  65961         0,
  65962         1,
  65963         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88270_A0r_fields,
  65964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65965         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65966         -1,
  65967         -1,
  65968     },
  65969 #endif /* chips */
  65970 
  65971 #if defined(BCM_88375_A0)
  65972     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88375_A0r */
  65973         soc_block_list[42],
  65974         soc_genreg,
  65975         1,
  65976         0,
  65977         0x87,
  65978         0,
  65979         0,
  65980         1,
  65981         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88375_A0r_fields,
  65982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65983         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65984         -1,
  65985         -1,
  65986     },
  65987 #endif /* chips */
  65988 
  65989 #if defined(BCM_88375_B0)
  65990     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88375_B0r */
  65991         soc_block_list[42],
  65992         soc_genreg,
  65993         1,
  65994         0,
  65995         0x87,
  65996         0,
  65997         0,
  65998         1,
  65999         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88375_B0r_fields,
  66000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66001         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66002         -1,
  66003         -1,
  66004     },
  66005 #endif /* chips */
  66006 
  66007 #if defined(BCM_88470_A0)
  66008     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88470_A0r */
  66009         soc_block_list[42],
  66010         soc_genreg,
  66011         1,
  66012         0,
  66013         0x87,
  66014         0,
  66015         0,
  66016         1,
  66017         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88470_A0r_fields,
  66018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66019         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66020         -1,
  66021         -1,
  66022     },
  66023 #endif /* chips */
  66024 
  66025 #if defined(BCM_88470_B0)
  66026     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88470_B0r */
  66027         soc_block_list[42],
  66028         soc_genreg,
  66029         1,
  66030         0,
  66031         0x87,
  66032         0,
  66033         0,
  66034         1,
  66035         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88470_B0r_fields,
  66036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66037         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66038         -1,
  66039         -1,
  66040     },
  66041 #endif /* chips */
  66042 
  66043 #if defined(BCM_88650_B0)
  66044     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88650_B0r */
  66045         soc_block_list[42],
  66046         soc_genreg,
  66047         1,
  66048         0,
  66049         0x87,
  66050         SOC_REG_FLAG_SIGNAL,
  66051         0,
  66052         1,
  66053         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88650_B0r_fields,
  66054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66055         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66056         -1,
  66057         -1,
  66058     },
  66059 #endif /* chips */
  66060 
  66061 #if defined(BCM_88660_A0)
  66062     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88660_A0r */
  66063         soc_block_list[42],
  66064         soc_genreg,
  66065         1,
  66066         0,
  66067         0x87,
  66068         SOC_REG_FLAG_SIGNAL,
  66069         0,
  66070         1,
  66071         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88660_A0r_fields,
  66072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66073         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66074         -1,
  66075         -1,
  66076     },
  66077 #endif /* chips */
  66078 
  66079 #if defined(BCM_88675_A0)
  66080     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88675_A0r */
  66081         soc_block_list[42],
  66082         soc_genreg,
  66083         1,
  66084         0,
  66085         0x87,
  66086         0,
  66087         0,
  66088         1,
  66089         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88675_A0r_fields,
  66090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66091         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66092         -1,
  66093         -1,
  66094     },
  66095 #endif /* chips */
  66096 
  66097 #if defined(BCM_88675_B0)
  66098     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88675_B0r */
  66099         soc_block_list[42],
  66100         soc_genreg,
  66101         1,
  66102         0,
  66103         0x87,
  66104         0,
  66105         0,
  66106         1,
  66107         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88675_B0r_fields,
  66108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66109         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66110         -1,
  66111         -1,
  66112     },
  66113 #endif /* chips */
  66114 
  66115 #if defined(BCM_88680_A0)
  66116     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88680_A0r */
  66117         soc_block_list[42],
  66118         soc_genreg,
  66119         1,
  66120         0,
  66121         0x87,
  66122         0,
  66123         0,
  66124         1,
  66125         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88680_A0r_fields,
  66126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66127         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66128         -1,
  66129         -1,
  66130     },
  66131 #endif /* chips */
  66132 
  66133 #if defined(BCM_88690_A0)
  66134     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88690_A0r */
  66135         soc_block_list[42],
  66136         soc_genreg,
  66137         1,
  66138         0,
  66139         0x87,
  66140         0,
  66141         0,
  66142         1,
  66143         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88690_A0r_fields,
  66144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66145         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66146         -1,
  66147         -1,
  66148     },
  66149 #endif /* chips */
  66150 
  66151 #if defined(BCM_88690_B0)
  66152     { /* SOC_REG_INT_OLP_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
  66153         soc_block_list[42],
  66154         soc_genreg,
  66155         1,
  66156         0,
  66157         0x87,
  66158         0,
  66159         0,
  66160         1,
  66161         soc_OLP_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
  66162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66163         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66164         -1,
  66165         -1,
  66166     },
  66167 #endif /* chips */
  66168 
  66169 #if defined(BCM_88690_B0)
  66170     { /* SOC_REG_INT_OLP_SPECIAL_CLOCK_CONTROLSr */
  66171         soc_block_list[42],
  66172         soc_genreg,
  66173         1,
  66174         0,
  66175         0xc1,
  66176         0,
  66177         0,
  66178         1,
  66179         soc_OLP_SPECIAL_CLOCK_CONTROLSr_fields,
  66180         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  66181         SOC_RESET_MASK_DEC(0x00000002, 0x00000000)
  66182         -1,
  66183         -1,
  66184     },
  66185 #endif /* chips */
  66186 
  66187 #if defined(BCM_88675_A0)
  66188     { /* SOC_REG_INT_OLP_TX_CONFIGSr */
  66189         soc_block_list[42],
  66190         soc_genreg,
  66191         1,
  66192         0,
  66193         0x108,
  66194         0,
  66195         0,
  66196         1,
  66197         soc_OLP_TX_CONFIGSr_fields,
  66198         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66199         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66200         -1,
  66201         -1,
  66202     },
  66203 #endif /* chips */
  66204 
  66205 #if defined(BCM_88650_A0)
  66206     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARADr */
  66207         soc_block_list[42],
  66208         soc_genreg,
  66209         1,
  66210         0,
  66211         0x106,
  66212         SOC_REG_FLAG_SIGNAL,
  66213         0,
  66214         3,
  66215         soc_OLP_TX_CONFIGS_ARADr_fields,
  66216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66217         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66218         -1,
  66219         -1,
  66220     },
  66221 #endif /* chips */
  66222 
  66223 #if defined(BCM_88270_A0)
  66224     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88270_A0r */
  66225         soc_block_list[42],
  66226         soc_genreg,
  66227         1,
  66228         0,
  66229         0x107,
  66230         0,
  66231         0,
  66232         3,
  66233         soc_OLP_TX_CONFIGS_ARAD_BCM88270_A0r_fields,
  66234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66235         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66236         -1,
  66237         -1,
  66238     },
  66239 #endif /* chips */
  66240 
  66241 #if defined(BCM_88375_A0)
  66242     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88375_A0r */
  66243         soc_block_list[42],
  66244         soc_genreg,
  66245         1,
  66246         0,
  66247         0x107,
  66248         0,
  66249         0,
  66250         3,
  66251         soc_OLP_TX_CONFIGS_ARAD_BCM88375_A0r_fields,
  66252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66253         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66254         -1,
  66255         -1,
  66256     },
  66257 #endif /* chips */
  66258 
  66259 #if defined(BCM_88375_B0)
  66260     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88375_B0r */
  66261         soc_block_list[42],
  66262         soc_genreg,
  66263         1,
  66264         0,
  66265         0x107,
  66266         0,
  66267         0,
  66268         3,
  66269         soc_OLP_TX_CONFIGS_ARAD_BCM88375_B0r_fields,
  66270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66271         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66272         -1,
  66273         -1,
  66274     },
  66275 #endif /* chips */
  66276 
  66277 #if defined(BCM_88470_A0)
  66278     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88470_A0r */
  66279         soc_block_list[42],
  66280         soc_genreg,
  66281         1,
  66282         0,
  66283         0x107,
  66284         0,
  66285         0,
  66286         3,
  66287         soc_OLP_TX_CONFIGS_ARAD_BCM88470_A0r_fields,
  66288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66289         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66290         -1,
  66291         -1,
  66292     },
  66293 #endif /* chips */
  66294 
  66295 #if defined(BCM_88470_B0)
  66296     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88470_B0r */
  66297         soc_block_list[42],
  66298         soc_genreg,
  66299         1,
  66300         0,
  66301         0x107,
  66302         0,
  66303         0,
  66304         3,
  66305         soc_OLP_TX_CONFIGS_ARAD_BCM88470_B0r_fields,
  66306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66307         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66308         -1,
  66309         -1,
  66310     },
  66311 #endif /* chips */
  66312 
  66313 #if defined(BCM_88650_B0)
  66314     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88650_B0r */
  66315         soc_block_list[42],
  66316         soc_genreg,
  66317         1,
  66318         0,
  66319         0x106,
  66320         SOC_REG_FLAG_SIGNAL,
  66321         0,
  66322         3,
  66323         soc_OLP_TX_CONFIGS_ARAD_BCM88650_B0r_fields,
  66324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66325         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66326         -1,
  66327         -1,
  66328     },
  66329 #endif /* chips */
  66330 
  66331 #if defined(BCM_88660_A0)
  66332     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88660_A0r */
  66333         soc_block_list[42],
  66334         soc_genreg,
  66335         1,
  66336         0,
  66337         0x106,
  66338         SOC_REG_FLAG_SIGNAL,
  66339         0,
  66340         3,
  66341         soc_OLP_TX_CONFIGS_ARAD_BCM88660_A0r_fields,
  66342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66343         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66344         -1,
  66345         -1,
  66346     },
  66347 #endif /* chips */
  66348 
  66349 #if defined(BCM_88675_A0)
  66350     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88675_A0r */
  66351         soc_block_list[42],
  66352         soc_genreg,
  66353         1,
  66354         0,
  66355         0x107,
  66356         0,
  66357         0,
  66358         3,
  66359         soc_OLP_TX_CONFIGS_ARAD_BCM88675_A0r_fields,
  66360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66361         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66362         -1,
  66363         -1,
  66364     },
  66365 #endif /* chips */
  66366 
  66367 #if defined(BCM_88675_B0)
  66368     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88675_B0r */
  66369         soc_block_list[42],
  66370         soc_genreg,
  66371         1,
  66372         0,
  66373         0x107,
  66374         0,
  66375         0,
  66376         3,
  66377         soc_OLP_TX_CONFIGS_ARAD_BCM88675_B0r_fields,
  66378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66379         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66380         -1,
  66381         -1,
  66382     },
  66383 #endif /* chips */
  66384 
  66385 #if defined(BCM_88680_A0)
  66386     { /* SOC_REG_INT_OLP_TX_CONFIGS_ARAD_BCM88680_A0r */
  66387         soc_block_list[42],
  66388         soc_genreg,
  66389         1,
  66390         0,
  66391         0x107,
  66392         0,
  66393         0,
  66394         3,
  66395         soc_OLP_TX_CONFIGS_ARAD_BCM88680_A0r_fields,
  66396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66397         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66398         -1,
  66399         -1,
  66400     },
  66401 #endif /* chips */
  66402 
  66403 #if defined(BCM_88270_A0)
  66404     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM88270_A0r */
  66405         soc_block_list[42],
  66406         soc_genreg,
  66407         1,
  66408         0,
  66409         0x108,
  66410         0,
  66411         0,
  66412         1,
  66413         soc_OLP_TX_CONFIGS_BCM88270_A0r_fields,
  66414         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66415         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66416         -1,
  66417         -1,
  66418     },
  66419 #endif /* chips */
  66420 
  66421 #if defined(BCM_88375_A0)
  66422     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM88375_A0r */
  66423         soc_block_list[42],
  66424         soc_genreg,
  66425         1,
  66426         0,
  66427         0x108,
  66428         0,
  66429         0,
  66430         1,
  66431         soc_OLP_TX_CONFIGS_BCM88375_A0r_fields,
  66432         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66433         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66434         -1,
  66435         -1,
  66436     },
  66437 #endif /* chips */
  66438 
  66439 #if defined(BCM_88375_B0)
  66440     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM88375_B0r */
  66441         soc_block_list[42],
  66442         soc_genreg,
  66443         1,
  66444         0,
  66445         0x108,
  66446         0,
  66447         0,
  66448         1,
  66449         soc_OLP_TX_CONFIGS_BCM88375_B0r_fields,
  66450         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66451         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66452         -1,
  66453         -1,
  66454     },
  66455 #endif /* chips */
  66456 
  66457 #if defined(BCM_88470_A0)
  66458     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM88470_A0r */
  66459         soc_block_list[42],
  66460         soc_genreg,
  66461         1,
  66462         0,
  66463         0x108,
  66464         0,
  66465         0,
  66466         1,
  66467         soc_OLP_TX_CONFIGS_BCM88470_A0r_fields,
  66468         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66469         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66470         -1,
  66471         -1,
  66472     },
  66473 #endif /* chips */
  66474 
  66475 #if defined(BCM_88470_B0)
  66476     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM88470_B0r */
  66477         soc_block_list[42],
  66478         soc_genreg,
  66479         1,
  66480         0,
  66481         0x108,
  66482         0,
  66483         0,
  66484         1,
  66485         soc_OLP_TX_CONFIGS_BCM88470_B0r_fields,
  66486         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66487         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66488         -1,
  66489         -1,
  66490     },
  66491 #endif /* chips */
  66492 
  66493 #if defined(BCM_88675_B0)
  66494     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM88675_B0r */
  66495         soc_block_list[42],
  66496         soc_genreg,
  66497         1,
  66498         0,
  66499         0x108,
  66500         0,
  66501         0,
  66502         1,
  66503         soc_OLP_TX_CONFIGS_BCM88675_B0r_fields,
  66504         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66505         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66506         -1,
  66507         -1,
  66508     },
  66509 #endif /* chips */
  66510 
  66511 #if defined(BCM_88680_A0)
  66512     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM88680_A0r */
  66513         soc_block_list[42],
  66514         soc_genreg,
  66515         1,
  66516         0,
  66517         0x108,
  66518         0,
  66519         0,
  66520         1,
  66521         soc_OLP_TX_CONFIGS_BCM88680_A0r_fields,
  66522         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66523         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66524         -1,
  66525         -1,
  66526     },
  66527 #endif /* chips */
  66528 
  66529 #if defined(BCM_88690_A0)
  66530     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM88690_A0r */
  66531         soc_block_list[42],
  66532         soc_genreg,
  66533         1,
  66534         0,
  66535         0x116,
  66536         0,
  66537         0,
  66538         1,
  66539         soc_OLP_TX_CONFIGS_BCM88690_A0r_fields,
  66540         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66541         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66542         -1,
  66543         -1,
  66544     },
  66545 #endif /* chips */
  66546 
  66547 #if defined(BCM_88690_B0)
  66548     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM88690_B0r */
  66549         soc_block_list[42],
  66550         soc_genreg,
  66551         1,
  66552         0,
  66553         0x116,
  66554         0,
  66555         0,
  66556         1,
  66557         soc_OLP_TX_CONFIGS_BCM88690_B0r_fields,
  66558         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  66559         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66560         -1,
  66561         -1,
  66562     },
  66563 #endif /* chips */
  66564 
  66565 #if defined(BCM_88690_A0)
  66566     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM_86650r */
  66567         soc_block_list[42],
  66568         soc_genreg,
  66569         1,
  66570         0,
  66571         0x115,
  66572         0,
  66573         0,
  66574         3,
  66575         soc_OLP_TX_CONFIGS_BCM_86650r_fields,
  66576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66577         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66578         -1,
  66579         -1,
  66580     },
  66581 #endif /* chips */
  66582 
  66583 #if defined(BCM_88690_B0)
  66584     { /* SOC_REG_INT_OLP_TX_CONFIGS_BCM_86650_BCM88690_B0r */
  66585         soc_block_list[42],
  66586         soc_genreg,
  66587         1,
  66588         0,
  66589         0x115,
  66590         0,
  66591         0,
  66592         3,
  66593         soc_OLP_TX_CONFIGS_BCM_86650_BCM88690_B0r_fields,
  66594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66595         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66596         -1,
  66597         -1,
  66598     },
  66599 #endif /* chips */
  66600 
  66601 #if defined(BCM_88650_A0)
  66602     { /* SOC_REG_INT_OLP_TX_CONFIGS_PETRA_Br */
  66603         soc_block_list[42],
  66604         soc_genreg,
  66605         1,
  66606         0,
  66607         0x107,
  66608         SOC_REG_FLAG_SIGNAL,
  66609         0,
  66610         4,
  66611         soc_OLP_TX_CONFIGS_PETRA_Br_fields,
  66612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66613         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  66614         -1,
  66615         -1,
  66616     },
  66617 #endif /* chips */
  66618 
  66619 #if defined(BCM_88650_B0)
  66620     { /* SOC_REG_INT_OLP_TX_CONFIGS_PETRA_B_BCM88650_B0r */
  66621         soc_block_list[42],
  66622         soc_genreg,
  66623         1,
  66624         0,
  66625         0x107,
  66626         SOC_REG_FLAG_SIGNAL,
  66627         0,
  66628         4,
  66629         soc_OLP_TX_CONFIGS_PETRA_B_BCM88650_B0r_fields,
  66630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66631         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  66632         -1,
  66633         -1,
  66634     },
  66635 #endif /* chips */
  66636 
  66637 #if defined(BCM_88660_A0)
  66638     { /* SOC_REG_INT_OLP_TX_CONFIGS_PETRA_B_BCM88660_A0r */
  66639         soc_block_list[42],
  66640         soc_genreg,
  66641         1,
  66642         0,
  66643         0x107,
  66644         SOC_REG_FLAG_SIGNAL,
  66645         0,
  66646         4,
  66647         soc_OLP_TX_CONFIGS_PETRA_B_BCM88660_A0r_fields,
  66648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66649         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  66650         -1,
  66651         -1,
  66652     },
  66653 #endif /* chips */
  66654 
  66655 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  66656     { /* SOC_REG_INT_OOBFC_CHANNEL_BASE_64r */
  66657         soc_block_list[4],
  66658         soc_genreg,
  66659         1,
  66660         0,
  66661         0x16080540,
  66662         SOC_REG_FLAG_64_BITS,
  66663         0,
  66664         10,
  66665         soc_OOBFC_CHANNEL_BASE_64r_fields,
  66666         SOC_RESET_VAL_DEC(0x0f030840, 0x00000070)
  66667         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  66668         -1,
  66669         -1,
  66670     },
  66671 #endif /* chips */
  66672 
  66673 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  66674     defined(BCM_56270_A0)
  66675     { /* SOC_REG_INT_OOBFC_CHANNEL_BASE_64_BCM56260_A0r */
  66676         soc_block_list[4],
  66677         soc_genreg,
  66678         1,
  66679         0,
  66680         0x5a006000,
  66681         SOC_REG_FLAG_64_BITS,
  66682         0,
  66683         10,
  66684         soc_OOBFC_CHANNEL_BASE_64_BCM56260_A0r_fields,
  66685         SOC_RESET_VAL_DEC(0x0f030840, 0x00000070)
  66686         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  66687         -1,
  66688         -1,
  66689     },
  66690 #endif /* chips */
  66691 
  66692 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  66693     { /* SOC_REG_INT_OOBFC_CHANNEL_BASE_64_BCM56440_A0r */
  66694         soc_block_list[4],
  66695         soc_genreg,
  66696         1,
  66697         0,
  66698         0x16080540,
  66699         SOC_REG_FLAG_64_BITS,
  66700         0,
  66701         10,
  66702         soc_OOBFC_CHANNEL_BASE_64_BCM56440_A0r_fields,
  66703         SOC_RESET_VAL_DEC(0x0c000000, 0x00000000)
  66704         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  66705         -1,
  66706         -1,
  66707     },
  66708 #endif /* chips */
  66709 
  66710 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66711     defined(BCM_56450_B1)
  66712     { /* SOC_REG_INT_OOBFC_CHANNEL_BASE_64_BCM56450_A0r */
  66713         soc_block_list[4],
  66714         soc_genreg,
  66715         1,
  66716         0,
  66717         0x5a006000,
  66718         SOC_REG_FLAG_64_BITS,
  66719         0,
  66720         10,
  66721         soc_OOBFC_CHANNEL_BASE_64_BCM56640_A0r_fields,
  66722         SOC_RESET_VAL_DEC(0x0f030840, 0x00000070)
  66723         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  66724         -1,
  66725         -1,
  66726     },
  66727 #endif /* chips */
  66728 
  66729 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66730     { /* SOC_REG_INT_OOBFC_CHANNEL_BASE_64_BCM56560_A0r */
  66731         soc_block_list[4],
  66732         soc_genreg,
  66733         1,
  66734         0,
  66735         0x5a006000,
  66736         SOC_REG_FLAG_64_BITS,
  66737         0,
  66738         10,
  66739         soc_OOBFC_CHANNEL_BASE_64_BCM56560_A0r_fields,
  66740         SOC_RESET_VAL_DEC(0x0d02a580, 0x00000030)
  66741         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  66742         -1,
  66743         -1,
  66744     },
  66745 #endif /* chips */
  66746 
  66747 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  66748     { /* SOC_REG_INT_OOBFC_CHANNEL_BASE_64_BCM56640_A0r */
  66749         soc_block_list[4],
  66750         soc_genreg,
  66751         1,
  66752         0,
  66753         0x96006000,
  66754         SOC_REG_FLAG_64_BITS,
  66755         0,
  66756         10,
  66757         soc_OOBFC_CHANNEL_BASE_64_BCM56640_A0r_fields,
  66758         SOC_RESET_VAL_DEC(0x0f030840, 0x00000070)
  66759         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  66760         -1,
  66761         -1,
  66762     },
  66763 #endif /* chips */
  66764 
  66765 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  66766     { /* SOC_REG_INT_OOBFC_CHANNEL_BASE_64_BCM56850_A0r */
  66767         soc_block_list[4],
  66768         soc_genreg,
  66769         1,
  66770         0,
  66771         0x5a006000,
  66772         SOC_REG_FLAG_64_BITS,
  66773         0,
  66774         10,
  66775         soc_OOBFC_CHANNEL_BASE_64_BCM56850_A0r_fields,
  66776         SOC_RESET_VAL_DEC(0x0d02a580, 0x00000030)
  66777         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  66778         -1,
  66779         -1,
  66780     },
  66781 #endif /* chips */
  66782 
  66783 #if defined(BCM_56960_A0)
  66784     { /* SOC_REG_INT_OOBFC_CHANNEL_BASE_64_BCM56960_A0r */
  66785         soc_block_list[126],
  66786         soc_genreg,
  66787         1,
  66788         0,
  66789         0x6006000,
  66790         SOC_REG_FLAG_64_BITS |
  66791                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  66792         0,
  66793         12,
  66794         soc_OOBFC_CHANNEL_BASE_64_BCM56960_A0r_fields,
  66795         SOC_RESET_VAL_DEC(0x0d230600, 0x00000030)
  66796         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  66797         -1,
  66798         -1,
  66799         3,
  66800     },
  66801 #endif /* chips */
  66802 
  66803 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  66804     defined(BCM_56965_A0) || defined(BCM_56970_A0)
  66805     { /* SOC_REG_INT_OOBFC_CHANNEL_BASE_64_BCM56965_A0r */
  66806         soc_block_list[126],
  66807         soc_genreg,
  66808         1,
  66809         0,
  66810         0x6006000,
  66811         SOC_REG_FLAG_64_BITS |
  66812                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  66813         0,
  66814         10,
  66815         soc_OOBFC_CHANNEL_BASE_64_BCM56965_A0r_fields,
  66816         SOC_RESET_VAL_DEC(0x0d230600, 0x00000030)
  66817         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  66818         -1,
  66819         -1,
  66820         3,
  66821     },
  66822 #endif /* chips */
  66823 
  66824 #if defined(BCM_56840_B0)
  66825     { /* SOC_REG_INT_OOBFC_CHIF_CFGr */
  66826         soc_block_list[4],
  66827         soc_genreg,
  66828         1,
  66829         0,
  66830         0x22080050,
  66831         SOC_REG_FLAG_64_BITS,
  66832         0,
  66833         15,
  66834         soc_OOBFC_CHIF_CFGr_fields,
  66835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66836         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  66837         -1,
  66838         -1,
  66839     },
  66840 #endif /* chips */
  66841 
  66842 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  66843     { /* SOC_REG_INT_OOBFC_CHIF_CFG0r */
  66844         soc_block_list[4],
  66845         soc_genreg,
  66846         1,
  66847         0,
  66848         0x5e00a000,
  66849         0,
  66850         0,
  66851         7,
  66852         soc_OOBFC_CHIF_CFG0r_fields,
  66853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66854         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  66855         -1,
  66856         -1,
  66857     },
  66858 #endif /* chips */
  66859 
  66860 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  66861     { /* SOC_REG_INT_OOBFC_CHIF_CFG1r */
  66862         soc_block_list[4],
  66863         soc_genreg,
  66864         1,
  66865         0,
  66866         0x5e00a100,
  66867         0,
  66868         0,
  66869         7,
  66870         soc_OOBFC_CHIF_CFG0r_fields,
  66871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66872         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  66873         -1,
  66874         -1,
  66875     },
  66876 #endif /* chips */
  66877 
  66878 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  66879     { /* SOC_REG_INT_OOBFC_CHIF_CFG2r */
  66880         soc_block_list[4],
  66881         soc_genreg,
  66882         1,
  66883         0,
  66884         0x5e00a200,
  66885         0,
  66886         0,
  66887         7,
  66888         soc_OOBFC_CHIF_CFG0r_fields,
  66889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66890         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  66891         -1,
  66892         -1,
  66893     },
  66894 #endif /* chips */
  66895 
  66896 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  66897     { /* SOC_REG_INT_OOBFC_CHIF_CFG3r */
  66898         soc_block_list[4],
  66899         soc_genreg,
  66900         1,
  66901         0,
  66902         0x5e00a300,
  66903         0,
  66904         0,
  66905         7,
  66906         soc_OOBFC_CHIF_CFG0r_fields,
  66907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66908         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  66909         -1,
  66910         -1,
  66911     },
  66912 #endif /* chips */
  66913 
  66914 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66915     { /* SOC_REG_INT_OOBFC_CHIF_CFG0_BCM56560_A0r */
  66916         soc_block_list[4],
  66917         soc_genreg,
  66918         1,
  66919         0,
  66920         0x5e00a000,
  66921         0,
  66922         0,
  66923         7,
  66924         soc_OOBFC_CHIF_CFG0_BCM56960_A0r_fields,
  66925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66926         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  66927         -1,
  66928         -1,
  66929     },
  66930 #endif /* chips */
  66931 
  66932 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  66933     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  66934     defined(BCM_56970_A0)
  66935     { /* SOC_REG_INT_OOBFC_CHIF_CFG0_BCM56960_A0r */
  66936         soc_block_list[126],
  66937         soc_genreg,
  66938         1,
  66939         0,
  66940         0x601a000,
  66941         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  66942         0,
  66943         7,
  66944         soc_OOBFC_CHIF_CFG0_BCM56960_A0r_fields,
  66945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66946         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  66947         -1,
  66948         -1,
  66949         3,
  66950     },
  66951 #endif /* chips */
  66952 
  66953 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66954     { /* SOC_REG_INT_OOBFC_CHIF_CFG1_BCM56560_A0r */
  66955         soc_block_list[4],
  66956         soc_genreg,
  66957         1,
  66958         0,
  66959         0x5e00a100,
  66960         0,
  66961         0,
  66962         7,
  66963         soc_OOBFC_CHIF_CFG0_BCM56960_A0r_fields,
  66964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66965         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  66966         -1,
  66967         -1,
  66968     },
  66969 #endif /* chips */
  66970 
  66971 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  66972     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  66973     defined(BCM_56970_A0)
  66974     { /* SOC_REG_INT_OOBFC_CHIF_CFG1_BCM56960_A0r */
  66975         soc_block_list[126],
  66976         soc_genreg,
  66977         1,
  66978         0,
  66979         0x601a100,
  66980         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  66981         0,
  66982         7,
  66983         soc_OOBFC_CHIF_CFG0_BCM56960_A0r_fields,
  66984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66985         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  66986         -1,
  66987         -1,
  66988         3,
  66989     },
  66990 #endif /* chips */
  66991 
  66992 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66993     { /* SOC_REG_INT_OOBFC_CHIF_CFG2_BCM56560_A0r */
  66994         soc_block_list[4],
  66995         soc_genreg,
  66996         1,
  66997         0,
  66998         0x5e00a200,
  66999         0,
  67000         0,
  67001         7,
  67002         soc_OOBFC_CHIF_CFG0_BCM56960_A0r_fields,
  67003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67004         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67005         -1,
  67006         -1,
  67007     },
  67008 #endif /* chips */
  67009 
  67010 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  67011     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67012     defined(BCM_56970_A0)
  67013     { /* SOC_REG_INT_OOBFC_CHIF_CFG2_BCM56960_A0r */
  67014         soc_block_list[126],
  67015         soc_genreg,
  67016         1,
  67017         0,
  67018         0x601a200,
  67019         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67020         0,
  67021         7,
  67022         soc_OOBFC_CHIF_CFG0_BCM56960_A0r_fields,
  67023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67024         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67025         -1,
  67026         -1,
  67027         3,
  67028     },
  67029 #endif /* chips */
  67030 
  67031 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67032     { /* SOC_REG_INT_OOBFC_CHIF_CFG3_BCM56560_A0r */
  67033         soc_block_list[4],
  67034         soc_genreg,
  67035         1,
  67036         0,
  67037         0x5e00a300,
  67038         0,
  67039         0,
  67040         7,
  67041         soc_OOBFC_CHIF_CFG0_BCM56960_A0r_fields,
  67042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67043         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67044         -1,
  67045         -1,
  67046     },
  67047 #endif /* chips */
  67048 
  67049 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  67050     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67051     defined(BCM_56970_A0)
  67052     { /* SOC_REG_INT_OOBFC_CHIF_CFG3_BCM56960_A0r */
  67053         soc_block_list[126],
  67054         soc_genreg,
  67055         1,
  67056         0,
  67057         0x601a300,
  67058         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67059         0,
  67060         7,
  67061         soc_OOBFC_CHIF_CFG0_BCM56960_A0r_fields,
  67062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67063         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67064         -1,
  67065         -1,
  67066         3,
  67067     },
  67068 #endif /* chips */
  67069 
  67070 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  67071     { /* SOC_REG_INT_OOBFC_CHIF_CFG_BCM56260_A0r */
  67072         soc_block_list[4],
  67073         soc_genreg,
  67074         1,
  67075         0,
  67076         0xce002100,
  67077         0,
  67078         0,
  67079         5,
  67080         soc_OOBFC_CHIF_CFG_BCM56260_A0r_fields,
  67081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67082         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  67083         -1,
  67084         -1,
  67085     },
  67086 #endif /* chips */
  67087 
  67088 #if defined(BCM_56270_A0)
  67089     { /* SOC_REG_INT_OOBFC_CHIF_CFG_BCM56270_A0r */
  67090         soc_block_list[4],
  67091         soc_genreg,
  67092         1,
  67093         0,
  67094         0xce002100,
  67095         0,
  67096         0,
  67097         5,
  67098         soc_OOBFC_CHIF_CFG_BCM56270_A0r_fields,
  67099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67100         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  67101         -1,
  67102         -1,
  67103     },
  67104 #endif /* chips */
  67105 
  67106 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67107     defined(BCM_56450_B1)
  67108     { /* SOC_REG_INT_OOBFC_CHIF_CFG_BCM56450_A0r */
  67109         soc_block_list[4],
  67110         soc_genreg,
  67111         1,
  67112         0,
  67113         0xce002100,
  67114         0,
  67115         0,
  67116         5,
  67117         soc_OOBFC_CHIF_CFG_BCM56450_A0r_fields,
  67118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67119         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67120         -1,
  67121         -1,
  67122     },
  67123 #endif /* chips */
  67124 
  67125 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67126     { /* SOC_REG_INT_OOBFC_CHIF_CFG_BCM56640_A0r */
  67127         soc_block_list[4],
  67128         soc_genreg,
  67129         1,
  67130         0,
  67131         0x9a002100,
  67132         0,
  67133         0,
  67134         5,
  67135         soc_OOBFC_CHIF_CFG_BCM56640_A0r_fields,
  67136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67137         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  67138         -1,
  67139         -1,
  67140     },
  67141 #endif /* chips */
  67142 
  67143 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67144     defined(BCM_56970_A0)
  67145     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN2r */
  67146         soc_block_list[126],
  67147         soc_genreg,
  67148         1,
  67149         0,
  67150         0x6006600,
  67151         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67152         0,
  67153         1,
  67154         soc_OOBFC_ENG_PORT_EN2r_fields,
  67155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67156         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  67157         -1,
  67158         -1,
  67159         3,
  67160     },
  67161 #endif /* chips */
  67162 
  67163 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  67164     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN0_64r */
  67165         soc_block_list[4],
  67166         soc_genreg,
  67167         1,
  67168         0,
  67169         0x5a006300,
  67170         SOC_REG_FLAG_64_BITS,
  67171         0,
  67172         1,
  67173         soc_OOBFC_ENG_PORT_EN0_64r_fields,
  67174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67175         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67176         -1,
  67177         -1,
  67178     },
  67179 #endif /* chips */
  67180 
  67181 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67182     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN0_64_BCM56560_A0r */
  67183         soc_block_list[4],
  67184         soc_genreg,
  67185         1,
  67186         0,
  67187         0x5a006300,
  67188         SOC_REG_FLAG_64_BITS,
  67189         0,
  67190         1,
  67191         soc_OOBFC_ENG_PORT_EN0_64_BCM56960_A0r_fields,
  67192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67193         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67194         -1,
  67195         -1,
  67196     },
  67197 #endif /* chips */
  67198 
  67199 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  67200     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67201     defined(BCM_56970_A0)
  67202     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN0_64_BCM56960_A0r */
  67203         soc_block_list[126],
  67204         soc_genreg,
  67205         1,
  67206         0,
  67207         0x6006400,
  67208         SOC_REG_FLAG_64_BITS |
  67209                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67210         0,
  67211         1,
  67212         soc_OOBFC_ENG_PORT_EN0_64_BCM56960_A0r_fields,
  67213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67214         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67215         -1,
  67216         -1,
  67217         3,
  67218     },
  67219 #endif /* chips */
  67220 
  67221 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  67222     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN1_64r */
  67223         soc_block_list[4],
  67224         soc_genreg,
  67225         1,
  67226         0,
  67227         0x5a006400,
  67228         SOC_REG_FLAG_64_BITS,
  67229         0,
  67230         1,
  67231         soc_OOBFC_ENG_PORT_EN1_64r_fields,
  67232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67233         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  67234         -1,
  67235         -1,
  67236     },
  67237 #endif /* chips */
  67238 
  67239 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67240     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN1_64_BCM56560_A0r */
  67241         soc_block_list[4],
  67242         soc_genreg,
  67243         1,
  67244         0,
  67245         0x5a006400,
  67246         SOC_REG_FLAG_64_BITS,
  67247         0,
  67248         1,
  67249         soc_OOBFC_ENG_PORT_EN1_64_BCM56560_A0r_fields,
  67250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67251         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  67252         -1,
  67253         -1,
  67254     },
  67255 #endif /* chips */
  67256 
  67257 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  67258     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67259     defined(BCM_56970_A0)
  67260     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN1_64_BCM56960_A0r */
  67261         soc_block_list[126],
  67262         soc_genreg,
  67263         1,
  67264         0,
  67265         0x6006500,
  67266         SOC_REG_FLAG_64_BITS |
  67267                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67268         0,
  67269         1,
  67270         soc_OOBFC_ENG_PORT_EN0_64_BCM56960_A0r_fields,
  67271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67272         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67273         -1,
  67274         -1,
  67275         3,
  67276     },
  67277 #endif /* chips */
  67278 
  67279 #if defined(BCM_56870_A0)
  67280     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN2_BCM56870_A0r */
  67281         soc_block_list[126],
  67282         soc_genreg,
  67283         1,
  67284         0,
  67285         0x6006600,
  67286         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67287         0,
  67288         1,
  67289         soc_OOBFC_ENG_PORT_EN2_BCM56870_A0r_fields,
  67290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67291         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  67292         -1,
  67293         -1,
  67294         3,
  67295     },
  67296 #endif /* chips */
  67297 
  67298 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  67299     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN_29r */
  67300         soc_block_list[4],
  67301         soc_genreg,
  67302         1,
  67303         0,
  67304         0x5a006200,
  67305         SOC_REG_FLAG_64_BITS,
  67306         0,
  67307         1,
  67308         soc_OOBFC_ENG_PORT_EN_29r_fields,
  67309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67310         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  67311         -1,
  67312         -1,
  67313     },
  67314 #endif /* chips */
  67315 
  67316 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67317     defined(BCM_56450_B1)
  67318     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN_41r */
  67319         soc_block_list[4],
  67320         soc_genreg,
  67321         1,
  67322         0,
  67323         0x5a006200,
  67324         SOC_REG_FLAG_64_BITS,
  67325         0,
  67326         1,
  67327         soc_OOBFC_ENG_PORT_EN_41r_fields,
  67328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67329         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  67330         -1,
  67331         -1,
  67332     },
  67333 #endif /* chips */
  67334 
  67335 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67336     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN_64r */
  67337         soc_block_list[4],
  67338         soc_genreg,
  67339         1,
  67340         0,
  67341         0x96006200,
  67342         SOC_REG_FLAG_64_BITS,
  67343         0,
  67344         1,
  67345         soc_OOBFC_ENG_PORT_EN_64r_fields,
  67346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67347         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  67348         -1,
  67349         -1,
  67350     },
  67351 #endif /* chips */
  67352 
  67353 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  67354     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN_0_64r */
  67355         soc_block_list[4],
  67356         soc_genreg,
  67357         1,
  67358         0,
  67359         0x16080570,
  67360         SOC_REG_FLAG_64_BITS,
  67361         0,
  67362         1,
  67363         soc_OOBFC_ENG_PORT_EN_0_64r_fields,
  67364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67365         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  67366         -1,
  67367         -1,
  67368     },
  67369 #endif /* chips */
  67370 
  67371 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67372     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN_0_64_BCM56440_A0r */
  67373         soc_block_list[4],
  67374         soc_genreg,
  67375         1,
  67376         0,
  67377         0x16080570,
  67378         SOC_REG_FLAG_64_BITS,
  67379         0,
  67380         1,
  67381         soc_OOBFC_ENG_PORT_EN_0_64_BCM56440_A0r_fields,
  67382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67383         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  67384         -1,
  67385         -1,
  67386     },
  67387 #endif /* chips */
  67388 
  67389 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  67390     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  67391     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN_1_64r */
  67392         soc_block_list[4],
  67393         soc_genreg,
  67394         1,
  67395         0,
  67396         0x16080580,
  67397         SOC_REG_FLAG_64_BITS,
  67398         0,
  67399         1,
  67400         soc_OOBFC_ENG_PORT_EN_0_64r_fields,
  67401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67402         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  67403         -1,
  67404         -1,
  67405     },
  67406 #endif /* chips */
  67407 
  67408 #if defined(BCM_56270_A0)
  67409     { /* SOC_REG_INT_OOBFC_ENG_PORT_EN_29_BCM56270_A0r */
  67410         soc_block_list[4],
  67411         soc_genreg,
  67412         1,
  67413         0,
  67414         0x5a006200,
  67415         SOC_REG_FLAG_64_BITS,
  67416         0,
  67417         1,
  67418         soc_OOBFC_ENG_PORT_EN_29_BCM56270_A0r_fields,
  67419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67420         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67421         -1,
  67422         -1,
  67423     },
  67424 #endif /* chips */
  67425 
  67426 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67427     defined(BCM_56970_A0)
  67428     { /* SOC_REG_INT_OOBFC_ENG_PORT_QSEL2r */
  67429         soc_block_list[126],
  67430         soc_genreg,
  67431         1,
  67432         0,
  67433         0x6006900,
  67434         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67435         0,
  67436         1,
  67437         soc_OOBFC_ENG_PORT_QSEL2r_fields,
  67438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67439         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  67440         -1,
  67441         -1,
  67442         3,
  67443     },
  67444 #endif /* chips */
  67445 
  67446 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  67447     { /* SOC_REG_INT_OOBFC_ENG_PORT_QSEL0_64r */
  67448         soc_block_list[4],
  67449         soc_genreg,
  67450         1,
  67451         0,
  67452         0x5a006500,
  67453         SOC_REG_FLAG_64_BITS,
  67454         0,
  67455         1,
  67456         soc_OOBFC_ENG_PORT_QSEL0_64r_fields,
  67457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67458         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67459         -1,
  67460         -1,
  67461     },
  67462 #endif /* chips */
  67463 
  67464 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67465     { /* SOC_REG_INT_OOBFC_ENG_PORT_QSEL0_64_BCM56560_A0r */
  67466         soc_block_list[4],
  67467         soc_genreg,
  67468         1,
  67469         0,
  67470         0x5a006500,
  67471         SOC_REG_FLAG_64_BITS,
  67472         0,
  67473         1,
  67474         soc_OOBFC_ENG_PORT_QSEL0_64_BCM56960_A0r_fields,
  67475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67476         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67477         -1,
  67478         -1,
  67479     },
  67480 #endif /* chips */
  67481 
  67482 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  67483     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67484     defined(BCM_56970_A0)
  67485     { /* SOC_REG_INT_OOBFC_ENG_PORT_QSEL0_64_BCM56960_A0r */
  67486         soc_block_list[126],
  67487         soc_genreg,
  67488         1,
  67489         0,
  67490         0x6006700,
  67491         SOC_REG_FLAG_64_BITS |
  67492                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67493         0,
  67494         1,
  67495         soc_OOBFC_ENG_PORT_QSEL0_64_BCM56960_A0r_fields,
  67496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67497         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67498         -1,
  67499         -1,
  67500         3,
  67501     },
  67502 #endif /* chips */
  67503 
  67504 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  67505     { /* SOC_REG_INT_OOBFC_ENG_PORT_QSEL1_64r */
  67506         soc_block_list[4],
  67507         soc_genreg,
  67508         1,
  67509         0,
  67510         0x5a006a00,
  67511         SOC_REG_FLAG_64_BITS,
  67512         0,
  67513         1,
  67514         soc_OOBFC_ENG_PORT_QSEL1_64r_fields,
  67515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67516         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  67517         -1,
  67518         -1,
  67519     },
  67520 #endif /* chips */
  67521 
  67522 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67523     { /* SOC_REG_INT_OOBFC_ENG_PORT_QSEL1_64_BCM56560_A0r */
  67524         soc_block_list[4],
  67525         soc_genreg,
  67526         1,
  67527         0,
  67528         0x5a006a00,
  67529         SOC_REG_FLAG_64_BITS,
  67530         0,
  67531         1,
  67532         soc_OOBFC_ENG_PORT_QSEL1_64_BCM56560_A0r_fields,
  67533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67534         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  67535         -1,
  67536         -1,
  67537     },
  67538 #endif /* chips */
  67539 
  67540 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  67541     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67542     defined(BCM_56970_A0)
  67543     { /* SOC_REG_INT_OOBFC_ENG_PORT_QSEL1_64_BCM56960_A0r */
  67544         soc_block_list[126],
  67545         soc_genreg,
  67546         1,
  67547         0,
  67548         0x6006800,
  67549         SOC_REG_FLAG_64_BITS |
  67550                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67551         0,
  67552         1,
  67553         soc_OOBFC_ENG_PORT_QSEL0_64_BCM56960_A0r_fields,
  67554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67555         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67556         -1,
  67557         -1,
  67558         3,
  67559     },
  67560 #endif /* chips */
  67561 
  67562 #if defined(BCM_56870_A0)
  67563     { /* SOC_REG_INT_OOBFC_ENG_PORT_QSEL2_BCM56870_A0r */
  67564         soc_block_list[126],
  67565         soc_genreg,
  67566         1,
  67567         0,
  67568         0x6006900,
  67569         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67570         0,
  67571         1,
  67572         soc_OOBFC_ENG_PORT_QSEL2_BCM56870_A0r_fields,
  67573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67574         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  67575         -1,
  67576         -1,
  67577         3,
  67578     },
  67579 #endif /* chips */
  67580 
  67581 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67582     { /* SOC_REG_INT_OOBFC_ENG_PORT_QSEL_64r */
  67583         soc_block_list[4],
  67584         soc_genreg,
  67585         1,
  67586         0,
  67587         0x96006300,
  67588         SOC_REG_FLAG_64_BITS,
  67589         0,
  67590         1,
  67591         soc_OOBFC_ENG_PORT_QSEL_64r_fields,
  67592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67593         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  67594         -1,
  67595         -1,
  67596     },
  67597 #endif /* chips */
  67598 
  67599 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  67600     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  67601     { /* SOC_REG_INT_OOBFC_GCSr */
  67602         soc_block_list[4],
  67603         soc_genreg,
  67604         1,
  67605         0,
  67606         0x16080590,
  67607         0,
  67608         0,
  67609         2,
  67610         soc_OOBFC_GCSr_fields,
  67611         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  67612         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67613         -1,
  67614         -1,
  67615     },
  67616 #endif /* chips */
  67617 
  67618 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  67619     defined(BCM_56270_A0)
  67620     { /* SOC_REG_INT_OOBFC_GCS_BCM56260_A0r */
  67621         soc_block_list[4],
  67622         soc_genreg,
  67623         1,
  67624         0,
  67625         0x5a006400,
  67626         0,
  67627         0,
  67628         2,
  67629         soc_OOBFC_GCS_BCM56960_A0r_fields,
  67630         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  67631         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67632         -1,
  67633         -1,
  67634     },
  67635 #endif /* chips */
  67636 
  67637 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67638     defined(BCM_56450_B1)
  67639     { /* SOC_REG_INT_OOBFC_GCS_BCM56450_A0r */
  67640         soc_block_list[4],
  67641         soc_genreg,
  67642         1,
  67643         0,
  67644         0x5a006400,
  67645         0,
  67646         0,
  67647         2,
  67648         soc_OOBFC_GCS_BCM56640_A0r_fields,
  67649         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  67650         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67651         -1,
  67652         -1,
  67653     },
  67654 #endif /* chips */
  67655 
  67656 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67657     { /* SOC_REG_INT_OOBFC_GCS_BCM56560_A0r */
  67658         soc_block_list[4],
  67659         soc_genreg,
  67660         1,
  67661         0,
  67662         0x5a006600,
  67663         0,
  67664         0,
  67665         2,
  67666         soc_OOBFC_GCS_BCM56960_A0r_fields,
  67667         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  67668         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67669         -1,
  67670         -1,
  67671     },
  67672 #endif /* chips */
  67673 
  67674 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67675     { /* SOC_REG_INT_OOBFC_GCS_BCM56640_A0r */
  67676         soc_block_list[4],
  67677         soc_genreg,
  67678         1,
  67679         0,
  67680         0x96006400,
  67681         0,
  67682         0,
  67683         2,
  67684         soc_OOBFC_GCS_BCM56640_A0r_fields,
  67685         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  67686         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67687         -1,
  67688         -1,
  67689     },
  67690 #endif /* chips */
  67691 
  67692 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  67693     { /* SOC_REG_INT_OOBFC_GCS_BCM56850_A0r */
  67694         soc_block_list[4],
  67695         soc_genreg,
  67696         1,
  67697         0,
  67698         0x5a006600,
  67699         0,
  67700         0,
  67701         2,
  67702         soc_OOBFC_GCS_BCM56640_A0r_fields,
  67703         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  67704         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67705         -1,
  67706         -1,
  67707     },
  67708 #endif /* chips */
  67709 
  67710 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  67711     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67712     defined(BCM_56970_A0)
  67713     { /* SOC_REG_INT_OOBFC_GCS_BCM56960_A0r */
  67714         soc_block_list[126],
  67715         soc_genreg,
  67716         1,
  67717         0,
  67718         0x6006a00,
  67719         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67720         0,
  67721         2,
  67722         soc_OOBFC_GCS_BCM56960_A0r_fields,
  67723         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  67724         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67725         -1,
  67726         -1,
  67727         3,
  67728     },
  67729 #endif /* chips */
  67730 
  67731 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67732     { /* SOC_REG_INT_OOBFC_INGRES_PORT_PG_PORT_ENA_64r */
  67733         soc_block_list[4],
  67734         soc_genreg,
  67735         1,
  67736         0,
  67737         0x16080550,
  67738         SOC_REG_FLAG_64_BITS,
  67739         0,
  67740         1,
  67741         soc_OOBFC_INGRES_PORT_PG_PORT_ENA_64r_fields,
  67742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67743         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  67744         -1,
  67745         -1,
  67746     },
  67747 #endif /* chips */
  67748 
  67749 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67750     defined(BCM_56970_A0)
  67751     { /* SOC_REG_INT_OOBFC_ING_PORT_EN2r */
  67752         soc_block_list[126],
  67753         soc_genreg,
  67754         1,
  67755         0,
  67756         0x6006300,
  67757         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67758         0,
  67759         1,
  67760         soc_OOBFC_ING_PORT_EN2r_fields,
  67761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67762         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  67763         -1,
  67764         -1,
  67765         3,
  67766     },
  67767 #endif /* chips */
  67768 
  67769 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  67770     { /* SOC_REG_INT_OOBFC_ING_PORT_EN0_64r */
  67771         soc_block_list[4],
  67772         soc_genreg,
  67773         1,
  67774         0,
  67775         0x5a006100,
  67776         SOC_REG_FLAG_64_BITS,
  67777         0,
  67778         1,
  67779         soc_OOBFC_ING_PORT_EN0_64r_fields,
  67780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67781         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67782         -1,
  67783         -1,
  67784     },
  67785 #endif /* chips */
  67786 
  67787 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67788     { /* SOC_REG_INT_OOBFC_ING_PORT_EN0_64_BCM56560_A0r */
  67789         soc_block_list[4],
  67790         soc_genreg,
  67791         1,
  67792         0,
  67793         0x5a006100,
  67794         SOC_REG_FLAG_64_BITS,
  67795         0,
  67796         1,
  67797         soc_OOBFC_ING_PORT_EN0_64_BCM56960_A0r_fields,
  67798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67799         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67800         -1,
  67801         -1,
  67802     },
  67803 #endif /* chips */
  67804 
  67805 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  67806     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67807     defined(BCM_56970_A0)
  67808     { /* SOC_REG_INT_OOBFC_ING_PORT_EN0_64_BCM56960_A0r */
  67809         soc_block_list[126],
  67810         soc_genreg,
  67811         1,
  67812         0,
  67813         0x6006100,
  67814         SOC_REG_FLAG_64_BITS |
  67815                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67816         0,
  67817         1,
  67818         soc_OOBFC_ING_PORT_EN0_64_BCM56960_A0r_fields,
  67819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67820         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67821         -1,
  67822         -1,
  67823         3,
  67824     },
  67825 #endif /* chips */
  67826 
  67827 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  67828     { /* SOC_REG_INT_OOBFC_ING_PORT_EN1_64r */
  67829         soc_block_list[4],
  67830         soc_genreg,
  67831         1,
  67832         0,
  67833         0x5a006200,
  67834         SOC_REG_FLAG_64_BITS,
  67835         0,
  67836         1,
  67837         soc_OOBFC_ING_PORT_EN1_64r_fields,
  67838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67839         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  67840         -1,
  67841         -1,
  67842     },
  67843 #endif /* chips */
  67844 
  67845 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67846     { /* SOC_REG_INT_OOBFC_ING_PORT_EN1_64_BCM56560_A0r */
  67847         soc_block_list[4],
  67848         soc_genreg,
  67849         1,
  67850         0,
  67851         0x5a006200,
  67852         SOC_REG_FLAG_64_BITS,
  67853         0,
  67854         1,
  67855         soc_OOBFC_ING_PORT_EN1_64_BCM56560_A0r_fields,
  67856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67857         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  67858         -1,
  67859         -1,
  67860     },
  67861 #endif /* chips */
  67862 
  67863 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  67864     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  67865     defined(BCM_56970_A0)
  67866     { /* SOC_REG_INT_OOBFC_ING_PORT_EN1_64_BCM56960_A0r */
  67867         soc_block_list[126],
  67868         soc_genreg,
  67869         1,
  67870         0,
  67871         0x6006200,
  67872         SOC_REG_FLAG_64_BITS |
  67873                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67874         0,
  67875         1,
  67876         soc_OOBFC_ING_PORT_EN0_64_BCM56960_A0r_fields,
  67877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67878         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67879         -1,
  67880         -1,
  67881         3,
  67882     },
  67883 #endif /* chips */
  67884 
  67885 #if defined(BCM_56870_A0)
  67886     { /* SOC_REG_INT_OOBFC_ING_PORT_EN2_BCM56870_A0r */
  67887         soc_block_list[126],
  67888         soc_genreg,
  67889         1,
  67890         0,
  67891         0x6006300,
  67892         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67893         0,
  67894         1,
  67895         soc_OOBFC_ING_PORT_EN2_BCM56870_A0r_fields,
  67896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67897         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  67898         -1,
  67899         -1,
  67900         3,
  67901     },
  67902 #endif /* chips */
  67903 
  67904 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  67905     { /* SOC_REG_INT_OOBFC_ING_PORT_EN_29r */
  67906         soc_block_list[4],
  67907         soc_genreg,
  67908         1,
  67909         0,
  67910         0x5a006100,
  67911         SOC_REG_FLAG_64_BITS,
  67912         0,
  67913         1,
  67914         soc_OOBFC_ING_PORT_EN_29r_fields,
  67915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67916         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  67917         -1,
  67918         -1,
  67919     },
  67920 #endif /* chips */
  67921 
  67922 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67923     defined(BCM_56450_B1)
  67924     { /* SOC_REG_INT_OOBFC_ING_PORT_EN_41r */
  67925         soc_block_list[4],
  67926         soc_genreg,
  67927         1,
  67928         0,
  67929         0x5a006100,
  67930         SOC_REG_FLAG_64_BITS,
  67931         0,
  67932         1,
  67933         soc_OOBFC_ING_PORT_EN_41r_fields,
  67934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67935         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  67936         -1,
  67937         -1,
  67938     },
  67939 #endif /* chips */
  67940 
  67941 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67942     { /* SOC_REG_INT_OOBFC_ING_PORT_EN_64r */
  67943         soc_block_list[4],
  67944         soc_genreg,
  67945         1,
  67946         0,
  67947         0x96006100,
  67948         SOC_REG_FLAG_64_BITS,
  67949         0,
  67950         1,
  67951         soc_OOBFC_ING_PORT_EN_64r_fields,
  67952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67953         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  67954         -1,
  67955         -1,
  67956     },
  67957 #endif /* chips */
  67958 
  67959 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  67960     { /* SOC_REG_INT_OOBFC_ING_PORT_EN_0_64r */
  67961         soc_block_list[4],
  67962         soc_genreg,
  67963         1,
  67964         0,
  67965         0x16080550,
  67966         SOC_REG_FLAG_64_BITS,
  67967         0,
  67968         1,
  67969         soc_OOBFC_ING_PORT_EN_0_64r_fields,
  67970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67971         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  67972         -1,
  67973         -1,
  67974     },
  67975 #endif /* chips */
  67976 
  67977 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  67978     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  67979     { /* SOC_REG_INT_OOBFC_ING_PORT_EN_1_64r */
  67980         soc_block_list[4],
  67981         soc_genreg,
  67982         1,
  67983         0,
  67984         0x16080560,
  67985         SOC_REG_FLAG_64_BITS,
  67986         0,
  67987         1,
  67988         soc_OOBFC_ING_PORT_EN_0_64r_fields,
  67989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67990         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  67991         -1,
  67992         -1,
  67993     },
  67994 #endif /* chips */
  67995 
  67996 #if defined(BCM_56270_A0)
  67997     { /* SOC_REG_INT_OOBFC_ING_PORT_EN_29_BCM56270_A0r */
  67998         soc_block_list[4],
  67999         soc_genreg,
  68000         1,
  68001         0,
  68002         0x5a006100,
  68003         SOC_REG_FLAG_64_BITS,
  68004         0,
  68005         1,
  68006         soc_OOBFC_ING_PORT_EN_29_BCM56270_A0r_fields,
  68007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68008         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  68009         -1,
  68010         -1,
  68011     },
  68012 #endif /* chips */
  68013 
  68014 #if defined(BCM_56840_B0)
  68015     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNTr */
  68016         soc_block_list[4],
  68017         soc_genreg,
  68018         1,
  68019         0,
  68020         0x22080080,
  68021         SOC_REG_FLAG_64_BITS,
  68022         0,
  68023         3,
  68024         soc_OOBFC_MSG_CRC_CNTr_fields,
  68025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68026         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  68027         -1,
  68028         -1,
  68029     },
  68030 #endif /* chips */
  68031 
  68032 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68033     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT0r */
  68034         soc_block_list[4],
  68035         soc_genreg,
  68036         1,
  68037         0,
  68038         0x5e00a800,
  68039         0,
  68040         0,
  68041         1,
  68042         soc_OOBFC_MSG_CRC_CNT_BCM56640_A0r_fields,
  68043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68044         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68045         -1,
  68046         -1,
  68047     },
  68048 #endif /* chips */
  68049 
  68050 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68051     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT1r */
  68052         soc_block_list[4],
  68053         soc_genreg,
  68054         1,
  68055         0,
  68056         0x5e00a900,
  68057         0,
  68058         0,
  68059         1,
  68060         soc_OOBFC_MSG_CRC_CNT_BCM56640_A0r_fields,
  68061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68062         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68063         -1,
  68064         -1,
  68065     },
  68066 #endif /* chips */
  68067 
  68068 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68069     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT2r */
  68070         soc_block_list[4],
  68071         soc_genreg,
  68072         1,
  68073         0,
  68074         0x5e00aa00,
  68075         0,
  68076         0,
  68077         1,
  68078         soc_OOBFC_MSG_CRC_CNT_BCM56640_A0r_fields,
  68079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68080         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68081         -1,
  68082         -1,
  68083     },
  68084 #endif /* chips */
  68085 
  68086 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68087     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT3r */
  68088         soc_block_list[4],
  68089         soc_genreg,
  68090         1,
  68091         0,
  68092         0x5e00ab00,
  68093         0,
  68094         0,
  68095         1,
  68096         soc_OOBFC_MSG_CRC_CNT_BCM56640_A0r_fields,
  68097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68098         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68099         -1,
  68100         -1,
  68101     },
  68102 #endif /* chips */
  68103 
  68104 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68105     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT0_BCM56560_A0r */
  68106         soc_block_list[4],
  68107         soc_genreg,
  68108         1,
  68109         0,
  68110         0x5e00a800,
  68111         0,
  68112         0,
  68113         1,
  68114         soc_OOBFC_MSG_CRC_CNT0r_fields,
  68115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68116         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68117         -1,
  68118         -1,
  68119     },
  68120 #endif /* chips */
  68121 
  68122 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68123     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68124     defined(BCM_56970_A0)
  68125     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT0_BCM56960_A0r */
  68126         soc_block_list[126],
  68127         soc_genreg,
  68128         1,
  68129         0,
  68130         0x601a800,
  68131         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68132         0,
  68133         1,
  68134         soc_OOBFC_MSG_CRC_CNT0r_fields,
  68135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68136         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68137         -1,
  68138         -1,
  68139         3,
  68140     },
  68141 #endif /* chips */
  68142 
  68143 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68144     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT1_BCM56560_A0r */
  68145         soc_block_list[4],
  68146         soc_genreg,
  68147         1,
  68148         0,
  68149         0x5e00a900,
  68150         0,
  68151         0,
  68152         1,
  68153         soc_OOBFC_MSG_CRC_CNT0r_fields,
  68154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68155         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68156         -1,
  68157         -1,
  68158     },
  68159 #endif /* chips */
  68160 
  68161 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68162     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68163     defined(BCM_56970_A0)
  68164     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT1_BCM56960_A0r */
  68165         soc_block_list[126],
  68166         soc_genreg,
  68167         1,
  68168         0,
  68169         0x601a900,
  68170         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68171         0,
  68172         1,
  68173         soc_OOBFC_MSG_CRC_CNT0r_fields,
  68174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68175         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68176         -1,
  68177         -1,
  68178         3,
  68179     },
  68180 #endif /* chips */
  68181 
  68182 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68183     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT2_BCM56560_A0r */
  68184         soc_block_list[4],
  68185         soc_genreg,
  68186         1,
  68187         0,
  68188         0x5e00aa00,
  68189         0,
  68190         0,
  68191         1,
  68192         soc_OOBFC_MSG_CRC_CNT0r_fields,
  68193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68194         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68195         -1,
  68196         -1,
  68197     },
  68198 #endif /* chips */
  68199 
  68200 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68201     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68202     defined(BCM_56970_A0)
  68203     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT2_BCM56960_A0r */
  68204         soc_block_list[126],
  68205         soc_genreg,
  68206         1,
  68207         0,
  68208         0x601aa00,
  68209         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68210         0,
  68211         1,
  68212         soc_OOBFC_MSG_CRC_CNT0r_fields,
  68213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68214         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68215         -1,
  68216         -1,
  68217         3,
  68218     },
  68219 #endif /* chips */
  68220 
  68221 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68222     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT3_BCM56560_A0r */
  68223         soc_block_list[4],
  68224         soc_genreg,
  68225         1,
  68226         0,
  68227         0x5e00ab00,
  68228         0,
  68229         0,
  68230         1,
  68231         soc_OOBFC_MSG_CRC_CNT0r_fields,
  68232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68233         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68234         -1,
  68235         -1,
  68236     },
  68237 #endif /* chips */
  68238 
  68239 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68240     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68241     defined(BCM_56970_A0)
  68242     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT3_BCM56960_A0r */
  68243         soc_block_list[126],
  68244         soc_genreg,
  68245         1,
  68246         0,
  68247         0x601ab00,
  68248         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68249         0,
  68250         1,
  68251         soc_OOBFC_MSG_CRC_CNT0r_fields,
  68252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68253         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68254         -1,
  68255         -1,
  68256         3,
  68257     },
  68258 #endif /* chips */
  68259 
  68260 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  68261     defined(BCM_56270_A0)
  68262     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT_BCM56260_A0r */
  68263         soc_block_list[4],
  68264         soc_genreg,
  68265         1,
  68266         0,
  68267         0xce002200,
  68268         0,
  68269         0,
  68270         1,
  68271         soc_OOBFC_MSG_CRC_CNT0r_fields,
  68272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68273         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68274         -1,
  68275         -1,
  68276     },
  68277 #endif /* chips */
  68278 
  68279 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68280     defined(BCM_56450_B1)
  68281     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT_BCM56450_A0r */
  68282         soc_block_list[4],
  68283         soc_genreg,
  68284         1,
  68285         0,
  68286         0xce002200,
  68287         0,
  68288         0,
  68289         1,
  68290         soc_OOBFC_MSG_CRC_CNT_BCM56640_A0r_fields,
  68291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68292         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68293         -1,
  68294         -1,
  68295     },
  68296 #endif /* chips */
  68297 
  68298 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  68299     { /* SOC_REG_INT_OOBFC_MSG_CRC_CNT_BCM56640_A0r */
  68300         soc_block_list[4],
  68301         soc_genreg,
  68302         1,
  68303         0,
  68304         0x9a002200,
  68305         0,
  68306         0,
  68307         1,
  68308         soc_OOBFC_MSG_CRC_CNT_BCM56640_A0r_fields,
  68309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68310         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68311         -1,
  68312         -1,
  68313     },
  68314 #endif /* chips */
  68315 
  68316 #if defined(BCM_56840_B0)
  68317     { /* SOC_REG_INT_OOBFC_MSG_REG0r */
  68318         soc_block_list[4],
  68319         soc_genreg,
  68320         1,
  68321         0,
  68322         0x22080090,
  68323         SOC_REG_FLAG_64_BITS,
  68324         0,
  68325         1,
  68326         soc_OOBFC_MSG_REG0r_fields,
  68327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68328         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68329         -1,
  68330         -1,
  68331     },
  68332 #endif /* chips */
  68333 
  68334 #if defined(BCM_56840_B0)
  68335     { /* SOC_REG_INT_OOBFC_MSG_REG1r */
  68336         soc_block_list[4],
  68337         soc_genreg,
  68338         1,
  68339         0,
  68340         0x220800a0,
  68341         SOC_REG_FLAG_64_BITS,
  68342         0,
  68343         1,
  68344         soc_OOBFC_MSG_REG0r_fields,
  68345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68346         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68347         -1,
  68348         -1,
  68349     },
  68350 #endif /* chips */
  68351 
  68352 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  68353     defined(BCM_56270_A0)
  68354     { /* SOC_REG_INT_OOBFC_MSG_REG0_BCM56260_A0r */
  68355         soc_block_list[4],
  68356         soc_genreg,
  68357         1,
  68358         0,
  68359         0xce002300,
  68360         SOC_REG_FLAG_64_BITS,
  68361         0,
  68362         1,
  68363         soc_OOBFC_MSG_REG0_BCM56960_A0r_fields,
  68364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68365         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68366         -1,
  68367         -1,
  68368     },
  68369 #endif /* chips */
  68370 
  68371 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68372     defined(BCM_56450_B1)
  68373     { /* SOC_REG_INT_OOBFC_MSG_REG0_BCM56450_A0r */
  68374         soc_block_list[4],
  68375         soc_genreg,
  68376         1,
  68377         0,
  68378         0xce002300,
  68379         SOC_REG_FLAG_64_BITS,
  68380         0,
  68381         1,
  68382         soc_OOBFC_MSG_REG0_BCM56640_A0r_fields,
  68383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68384         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68385         -1,
  68386         -1,
  68387     },
  68388 #endif /* chips */
  68389 
  68390 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68391     { /* SOC_REG_INT_OOBFC_MSG_REG0_BCM56560_A0r */
  68392         soc_block_list[4],
  68393         soc_genreg,
  68394         1,
  68395         0,
  68396         0x5e002300,
  68397         SOC_REG_FLAG_64_BITS,
  68398         0,
  68399         1,
  68400         soc_OOBFC_MSG_REG0_BCM56960_A0r_fields,
  68401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68402         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68403         -1,
  68404         -1,
  68405     },
  68406 #endif /* chips */
  68407 
  68408 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  68409     { /* SOC_REG_INT_OOBFC_MSG_REG0_BCM56640_A0r */
  68410         soc_block_list[4],
  68411         soc_genreg,
  68412         1,
  68413         0,
  68414         0x9a002300,
  68415         SOC_REG_FLAG_64_BITS,
  68416         0,
  68417         1,
  68418         soc_OOBFC_MSG_REG0_BCM56640_A0r_fields,
  68419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68420         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68421         -1,
  68422         -1,
  68423     },
  68424 #endif /* chips */
  68425 
  68426 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68427     { /* SOC_REG_INT_OOBFC_MSG_REG0_BCM56850_A0r */
  68428         soc_block_list[4],
  68429         soc_genreg,
  68430         1,
  68431         0,
  68432         0x5e002300,
  68433         SOC_REG_FLAG_64_BITS,
  68434         0,
  68435         1,
  68436         soc_OOBFC_MSG_REG0_BCM56640_A0r_fields,
  68437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68438         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68439         -1,
  68440         -1,
  68441     },
  68442 #endif /* chips */
  68443 
  68444 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68445     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68446     defined(BCM_56970_A0)
  68447     { /* SOC_REG_INT_OOBFC_MSG_REG0_BCM56960_A0r */
  68448         soc_block_list[126],
  68449         soc_genreg,
  68450         1,
  68451         0,
  68452         0x6012300,
  68453         SOC_REG_FLAG_64_BITS |
  68454                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68455         0,
  68456         1,
  68457         soc_OOBFC_MSG_REG0_BCM56960_A0r_fields,
  68458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68459         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68460         -1,
  68461         -1,
  68462         3,
  68463     },
  68464 #endif /* chips */
  68465 
  68466 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  68467     defined(BCM_56270_A0)
  68468     { /* SOC_REG_INT_OOBFC_MSG_REG1_BCM56260_A0r */
  68469         soc_block_list[4],
  68470         soc_genreg,
  68471         1,
  68472         0,
  68473         0xce002400,
  68474         SOC_REG_FLAG_64_BITS,
  68475         0,
  68476         1,
  68477         soc_OOBFC_MSG_REG0_BCM56960_A0r_fields,
  68478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68479         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68480         -1,
  68481         -1,
  68482     },
  68483 #endif /* chips */
  68484 
  68485 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68486     defined(BCM_56450_B1)
  68487     { /* SOC_REG_INT_OOBFC_MSG_REG1_BCM56450_A0r */
  68488         soc_block_list[4],
  68489         soc_genreg,
  68490         1,
  68491         0,
  68492         0xce002400,
  68493         SOC_REG_FLAG_64_BITS,
  68494         0,
  68495         1,
  68496         soc_OOBFC_MSG_REG0_BCM56640_A0r_fields,
  68497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68498         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68499         -1,
  68500         -1,
  68501     },
  68502 #endif /* chips */
  68503 
  68504 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68505     { /* SOC_REG_INT_OOBFC_MSG_REG1_BCM56560_A0r */
  68506         soc_block_list[4],
  68507         soc_genreg,
  68508         1,
  68509         0,
  68510         0x5e002400,
  68511         SOC_REG_FLAG_64_BITS,
  68512         0,
  68513         1,
  68514         soc_OOBFC_MSG_REG0_BCM56960_A0r_fields,
  68515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68516         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68517         -1,
  68518         -1,
  68519     },
  68520 #endif /* chips */
  68521 
  68522 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  68523     { /* SOC_REG_INT_OOBFC_MSG_REG1_BCM56640_A0r */
  68524         soc_block_list[4],
  68525         soc_genreg,
  68526         1,
  68527         0,
  68528         0x9a002400,
  68529         SOC_REG_FLAG_64_BITS,
  68530         0,
  68531         1,
  68532         soc_OOBFC_MSG_REG0_BCM56640_A0r_fields,
  68533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68534         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68535         -1,
  68536         -1,
  68537     },
  68538 #endif /* chips */
  68539 
  68540 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68541     { /* SOC_REG_INT_OOBFC_MSG_REG1_BCM56850_A0r */
  68542         soc_block_list[4],
  68543         soc_genreg,
  68544         1,
  68545         0,
  68546         0x5e002400,
  68547         SOC_REG_FLAG_64_BITS,
  68548         0,
  68549         1,
  68550         soc_OOBFC_MSG_REG0_BCM56640_A0r_fields,
  68551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68552         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68553         -1,
  68554         -1,
  68555     },
  68556 #endif /* chips */
  68557 
  68558 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68559     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68560     defined(BCM_56970_A0)
  68561     { /* SOC_REG_INT_OOBFC_MSG_REG1_BCM56960_A0r */
  68562         soc_block_list[126],
  68563         soc_genreg,
  68564         1,
  68565         0,
  68566         0x6012400,
  68567         SOC_REG_FLAG_64_BITS |
  68568                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68569         0,
  68570         1,
  68571         soc_OOBFC_MSG_REG0_BCM56960_A0r_fields,
  68572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68573         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68574         -1,
  68575         -1,
  68576         3,
  68577     },
  68578 #endif /* chips */
  68579 
  68580 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  68581     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNTr */
  68582         soc_block_list[4],
  68583         soc_genreg,
  68584         1,
  68585         0,
  68586         0x9a002600,
  68587         0,
  68588         0,
  68589         1,
  68590         soc_OOBFC_MSG_RX_TOT_CNTr_fields,
  68591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68592         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68593         -1,
  68594         -1,
  68595     },
  68596 #endif /* chips */
  68597 
  68598 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68599     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT0r */
  68600         soc_block_list[4],
  68601         soc_genreg,
  68602         1,
  68603         0,
  68604         0x5e00b000,
  68605         0,
  68606         0,
  68607         1,
  68608         soc_ETU_RRFE_WAIT_TIMERr_fields,
  68609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68610         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68611         -1,
  68612         -1,
  68613     },
  68614 #endif /* chips */
  68615 
  68616 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68617     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT1r */
  68618         soc_block_list[4],
  68619         soc_genreg,
  68620         1,
  68621         0,
  68622         0x5e00b100,
  68623         0,
  68624         0,
  68625         1,
  68626         soc_ETU_RRFE_WAIT_TIMERr_fields,
  68627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68628         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68629         -1,
  68630         -1,
  68631     },
  68632 #endif /* chips */
  68633 
  68634 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68635     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT2r */
  68636         soc_block_list[4],
  68637         soc_genreg,
  68638         1,
  68639         0,
  68640         0x5e00b200,
  68641         0,
  68642         0,
  68643         1,
  68644         soc_ETU_RRFE_WAIT_TIMERr_fields,
  68645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68646         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68647         -1,
  68648         -1,
  68649     },
  68650 #endif /* chips */
  68651 
  68652 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68653     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT3r */
  68654         soc_block_list[4],
  68655         soc_genreg,
  68656         1,
  68657         0,
  68658         0x5e00b300,
  68659         0,
  68660         0,
  68661         1,
  68662         soc_ETU_RRFE_WAIT_TIMERr_fields,
  68663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68664         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68665         -1,
  68666         -1,
  68667     },
  68668 #endif /* chips */
  68669 
  68670 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68671     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT0_BCM56560_A0r */
  68672         soc_block_list[4],
  68673         soc_genreg,
  68674         1,
  68675         0,
  68676         0x5e00b000,
  68677         0,
  68678         0,
  68679         1,
  68680         soc_INTFO_OOBFC_MSG_RX_FAILED_CNT0r_fields,
  68681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68682         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68683         -1,
  68684         -1,
  68685     },
  68686 #endif /* chips */
  68687 
  68688 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68689     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68690     defined(BCM_56970_A0)
  68691     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT0_BCM56960_A0r */
  68692         soc_block_list[126],
  68693         soc_genreg,
  68694         1,
  68695         0,
  68696         0x601b000,
  68697         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68698         0,
  68699         1,
  68700         soc_INTFO_OOBFC_MSG_RX_FAILED_CNT0r_fields,
  68701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68702         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68703         -1,
  68704         -1,
  68705         3,
  68706     },
  68707 #endif /* chips */
  68708 
  68709 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68710     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT1_BCM56560_A0r */
  68711         soc_block_list[4],
  68712         soc_genreg,
  68713         1,
  68714         0,
  68715         0x5e00b100,
  68716         0,
  68717         0,
  68718         1,
  68719         soc_INTFO_OOBFC_MSG_RX_FAILED_CNT0r_fields,
  68720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68721         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68722         -1,
  68723         -1,
  68724     },
  68725 #endif /* chips */
  68726 
  68727 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68728     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68729     defined(BCM_56970_A0)
  68730     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT1_BCM56960_A0r */
  68731         soc_block_list[126],
  68732         soc_genreg,
  68733         1,
  68734         0,
  68735         0x601b100,
  68736         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68737         0,
  68738         1,
  68739         soc_INTFO_OOBFC_MSG_RX_FAILED_CNT0r_fields,
  68740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68741         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68742         -1,
  68743         -1,
  68744         3,
  68745     },
  68746 #endif /* chips */
  68747 
  68748 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68749     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT2_BCM56560_A0r */
  68750         soc_block_list[4],
  68751         soc_genreg,
  68752         1,
  68753         0,
  68754         0x5e00b200,
  68755         0,
  68756         0,
  68757         1,
  68758         soc_INTFO_OOBFC_MSG_RX_FAILED_CNT0r_fields,
  68759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68760         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68761         -1,
  68762         -1,
  68763     },
  68764 #endif /* chips */
  68765 
  68766 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68767     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68768     defined(BCM_56970_A0)
  68769     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT2_BCM56960_A0r */
  68770         soc_block_list[126],
  68771         soc_genreg,
  68772         1,
  68773         0,
  68774         0x601b200,
  68775         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68776         0,
  68777         1,
  68778         soc_INTFO_OOBFC_MSG_RX_FAILED_CNT0r_fields,
  68779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68780         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68781         -1,
  68782         -1,
  68783         3,
  68784     },
  68785 #endif /* chips */
  68786 
  68787 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68788     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT3_BCM56560_A0r */
  68789         soc_block_list[4],
  68790         soc_genreg,
  68791         1,
  68792         0,
  68793         0x5e00b300,
  68794         0,
  68795         0,
  68796         1,
  68797         soc_INTFO_OOBFC_MSG_RX_FAILED_CNT0r_fields,
  68798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68799         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68800         -1,
  68801         -1,
  68802     },
  68803 #endif /* chips */
  68804 
  68805 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68806     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68807     defined(BCM_56970_A0)
  68808     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT3_BCM56960_A0r */
  68809         soc_block_list[126],
  68810         soc_genreg,
  68811         1,
  68812         0,
  68813         0x601b300,
  68814         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68815         0,
  68816         1,
  68817         soc_INTFO_OOBFC_MSG_RX_FAILED_CNT0r_fields,
  68818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68819         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68820         -1,
  68821         -1,
  68822         3,
  68823     },
  68824 #endif /* chips */
  68825 
  68826 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  68827     defined(BCM_56270_A0)
  68828     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT_BCM56260_A0r */
  68829         soc_block_list[4],
  68830         soc_genreg,
  68831         1,
  68832         0,
  68833         0xce002600,
  68834         0,
  68835         0,
  68836         1,
  68837         soc_OOBFC_MSG_TX_CNTr_fields,
  68838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68840         -1,
  68841         -1,
  68842     },
  68843 #endif /* chips */
  68844 
  68845 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68846     defined(BCM_56450_B1)
  68847     { /* SOC_REG_INT_OOBFC_MSG_RX_TOT_CNT_BCM56450_A0r */
  68848         soc_block_list[4],
  68849         soc_genreg,
  68850         1,
  68851         0,
  68852         0xce002600,
  68853         0,
  68854         0,
  68855         1,
  68856         soc_OOBFC_MSG_RX_TOT_CNTr_fields,
  68857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68858         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68859         -1,
  68860         -1,
  68861     },
  68862 #endif /* chips */
  68863 
  68864 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  68865     { /* SOC_REG_INT_OOBFC_MSG_TX_CNTr */
  68866         soc_block_list[4],
  68867         soc_genreg,
  68868         1,
  68869         0,
  68870         0x96006600,
  68871         0,
  68872         0,
  68873         1,
  68874         soc_OOBFC_MSG_RX_TOT_CNTr_fields,
  68875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68877         -1,
  68878         -1,
  68879     },
  68880 #endif /* chips */
  68881 
  68882 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  68883     defined(BCM_56270_A0)
  68884     { /* SOC_REG_INT_OOBFC_MSG_TX_CNT_BCM56260_A0r */
  68885         soc_block_list[4],
  68886         soc_genreg,
  68887         1,
  68888         0,
  68889         0x5a006600,
  68890         0,
  68891         0,
  68892         1,
  68893         soc_OOBFC_MSG_TX_CNTr_fields,
  68894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68895         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68896         -1,
  68897         -1,
  68898     },
  68899 #endif /* chips */
  68900 
  68901 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68902     defined(BCM_56450_B1)
  68903     { /* SOC_REG_INT_OOBFC_MSG_TX_CNT_BCM56450_A0r */
  68904         soc_block_list[4],
  68905         soc_genreg,
  68906         1,
  68907         0,
  68908         0x5a006600,
  68909         0,
  68910         0,
  68911         1,
  68912         soc_OOBFC_MSG_RX_TOT_CNTr_fields,
  68913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68914         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68915         -1,
  68916         -1,
  68917     },
  68918 #endif /* chips */
  68919 
  68920 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  68921     { /* SOC_REG_INT_OOBFC_MSG_TX_CNT_BCM56560_A0r */
  68922         soc_block_list[4],
  68923         soc_genreg,
  68924         1,
  68925         0,
  68926         0x5a006800,
  68927         0,
  68928         0,
  68929         1,
  68930         soc_OOBFC_MSG_TX_CNTr_fields,
  68931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68932         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68933         -1,
  68934         -1,
  68935     },
  68936 #endif /* chips */
  68937 
  68938 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  68939     { /* SOC_REG_INT_OOBFC_MSG_TX_CNT_BCM56850_A0r */
  68940         soc_block_list[4],
  68941         soc_genreg,
  68942         1,
  68943         0,
  68944         0x5a006800,
  68945         0,
  68946         0,
  68947         1,
  68948         soc_OOBFC_MSG_RX_TOT_CNTr_fields,
  68949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68950         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68951         -1,
  68952         -1,
  68953     },
  68954 #endif /* chips */
  68955 
  68956 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  68957     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  68958     defined(BCM_56970_A0)
  68959     { /* SOC_REG_INT_OOBFC_MSG_TX_CNT_BCM56960_A0r */
  68960         soc_block_list[126],
  68961         soc_genreg,
  68962         1,
  68963         0,
  68964         0x6006c00,
  68965         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68966         0,
  68967         1,
  68968         soc_OOBFC_MSG_TX_CNTr_fields,
  68969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68971         -1,
  68972         -1,
  68973         3,
  68974     },
  68975 #endif /* chips */
  68976 
  68977 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  68978     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  68979     { /* SOC_REG_INT_OOBFC_STSr */
  68980         soc_block_list[4],
  68981         soc_genreg,
  68982         1,
  68983         0,
  68984         0x160805a0,
  68985         SOC_REG_FLAG_RO,
  68986         0,
  68987         2,
  68988         soc_OOBFC_STSr_fields,
  68989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68990         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  68991         -1,
  68992         -1,
  68993     },
  68994 #endif /* chips */
  68995 
  68996 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  68997     defined(BCM_56270_A0)
  68998     { /* SOC_REG_INT_OOBFC_STS_BCM56260_A0r */
  68999         soc_block_list[4],
  69000         soc_genreg,
  69001         1,
  69002         0,
  69003         0x5a006500,
  69004         SOC_REG_FLAG_RO,
  69005         0,
  69006         2,
  69007         soc_OOBFC_STS_BCM56960_A0r_fields,
  69008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69009         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69010         -1,
  69011         -1,
  69012     },
  69013 #endif /* chips */
  69014 
  69015 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69016     defined(BCM_56450_B1)
  69017     { /* SOC_REG_INT_OOBFC_STS_BCM56450_A0r */
  69018         soc_block_list[4],
  69019         soc_genreg,
  69020         1,
  69021         0,
  69022         0x5a006500,
  69023         SOC_REG_FLAG_RO,
  69024         0,
  69025         2,
  69026         soc_OOBFC_STS_BCM56640_A0r_fields,
  69027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69028         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69029         -1,
  69030         -1,
  69031     },
  69032 #endif /* chips */
  69033 
  69034 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  69035     { /* SOC_REG_INT_OOBFC_STS_BCM56560_A0r */
  69036         soc_block_list[4],
  69037         soc_genreg,
  69038         1,
  69039         0,
  69040         0x5a006700,
  69041         SOC_REG_FLAG_RO,
  69042         0,
  69043         2,
  69044         soc_OOBFC_STS_BCM56960_A0r_fields,
  69045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69046         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69047         -1,
  69048         -1,
  69049     },
  69050 #endif /* chips */
  69051 
  69052 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  69053     { /* SOC_REG_INT_OOBFC_STS_BCM56640_A0r */
  69054         soc_block_list[4],
  69055         soc_genreg,
  69056         1,
  69057         0,
  69058         0x96006500,
  69059         SOC_REG_FLAG_RO,
  69060         0,
  69061         2,
  69062         soc_OOBFC_STS_BCM56640_A0r_fields,
  69063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69064         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69065         -1,
  69066         -1,
  69067     },
  69068 #endif /* chips */
  69069 
  69070 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  69071     { /* SOC_REG_INT_OOBFC_STS_BCM56850_A0r */
  69072         soc_block_list[4],
  69073         soc_genreg,
  69074         1,
  69075         0,
  69076         0x5a006700,
  69077         SOC_REG_FLAG_RO,
  69078         0,
  69079         2,
  69080         soc_OOBFC_STS_BCM56640_A0r_fields,
  69081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69082         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69083         -1,
  69084         -1,
  69085     },
  69086 #endif /* chips */
  69087 
  69088 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  69089     { /* SOC_REG_INT_OOBFC_STS_BCM56960_A0r */
  69090         soc_block_list[126],
  69091         soc_genreg,
  69092         1,
  69093         0,
  69094         0x6006b00,
  69095         SOC_REG_FLAG_RO |
  69096                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69097         0,
  69098         2,
  69099         soc_OOBFC_STS_BCM56960_A0r_fields,
  69100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69101         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69102         -1,
  69103         -1,
  69104         3,
  69105     },
  69106 #endif /* chips */
  69107 
  69108 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  69109     defined(BCM_56970_A0)
  69110     { /* SOC_REG_INT_OOBFC_STS_BCM56970_A0r */
  69111         soc_block_list[126],
  69112         soc_genreg,
  69113         1,
  69114         0,
  69115         0x6006b00,
  69116         SOC_REG_FLAG_RO |
  69117                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69118         0,
  69119         2,
  69120         soc_OOBFC_STS_BCM56960_A0r_fields,
  69121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69122         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69123         -1,
  69124         -1,
  69125         3,
  69126     },
  69127 #endif /* chips */
  69128 
  69129 #if defined(BCM_56840_B0)
  69130     { /* SOC_REG_INT_OOBFC_TX_IDLEr */
  69131         soc_block_list[4],
  69132         soc_genreg,
  69133         1,
  69134         0,
  69135         0x160805b0,
  69136         0,
  69137         0,
  69138         1,
  69139         soc_OOBFC_TX_IDLEr_fields,
  69140         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  69141         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69142         -1,
  69143         -1,
  69144     },
  69145 #endif /* chips */
  69146 
  69147 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  69148     defined(BCM_56270_A0)
  69149     { /* SOC_REG_INT_OOBFC_TX_IDLE_BCM56260_A0r */
  69150         soc_block_list[4],
  69151         soc_genreg,
  69152         1,
  69153         0,
  69154         0x5a006700,
  69155         0,
  69156         0,
  69157         1,
  69158         soc_OOBFC_TX_IDLE_BCM56260_A0r_fields,
  69159         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  69160         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  69161         -1,
  69162         -1,
  69163     },
  69164 #endif /* chips */
  69165 
  69166 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69167     defined(BCM_56450_B1)
  69168     { /* SOC_REG_INT_OOBFC_TX_IDLE_BCM56450_A0r */
  69169         soc_block_list[4],
  69170         soc_genreg,
  69171         1,
  69172         0,
  69173         0x5a006700,
  69174         0,
  69175         0,
  69176         1,
  69177         soc_OOBFC_TX_IDLE_BCM56450_A0r_fields,
  69178         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  69179         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  69180         -1,
  69181         -1,
  69182     },
  69183 #endif /* chips */
  69184 
  69185 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  69186     { /* SOC_REG_INT_OOBFC_TX_IDLE_BCM56560_A0r */
  69187         soc_block_list[4],
  69188         soc_genreg,
  69189         1,
  69190         0,
  69191         0x5a006900,
  69192         0,
  69193         0,
  69194         1,
  69195         soc_OOBFC_TX_IDLE_BCM56560_A0r_fields,
  69196         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  69197         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  69198         -1,
  69199         -1,
  69200     },
  69201 #endif /* chips */
  69202 
  69203 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  69204     { /* SOC_REG_INT_OOBFC_TX_IDLE_BCM56640_A0r */
  69205         soc_block_list[4],
  69206         soc_genreg,
  69207         1,
  69208         0,
  69209         0x96006700,
  69210         0,
  69211         0,
  69212         1,
  69213         soc_OOBFC_TX_IDLE_BCM56640_A0r_fields,
  69214         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  69215         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69216         -1,
  69217         -1,
  69218     },
  69219 #endif /* chips */
  69220 
  69221 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  69222     { /* SOC_REG_INT_OOBFC_TX_IDLE_BCM56850_A0r */
  69223         soc_block_list[4],
  69224         soc_genreg,
  69225         1,
  69226         0,
  69227         0x5a006900,
  69228         0,
  69229         0,
  69230         1,
  69231         soc_OOBFC_TX_IDLE_BCM56640_A0r_fields,
  69232         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  69233         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69234         -1,
  69235         -1,
  69236     },
  69237 #endif /* chips */
  69238 
  69239 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  69240     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  69241     defined(BCM_56970_A0)
  69242     { /* SOC_REG_INT_OOBFC_TX_IDLE_BCM56960_A0r */
  69243         soc_block_list[126],
  69244         soc_genreg,
  69245         1,
  69246         0,
  69247         0x6006d00,
  69248         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69249         0,
  69250         1,
  69251         soc_OOBFC_TX_IDLE_BCM56960_A0r_fields,
  69252         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  69253         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69254         -1,
  69255         -1,
  69256         3,
  69257     },
  69258 #endif /* chips */
  69259 
  69260 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69261     { /* SOC_REG_INT_OOBFC_TX_MESSAGE_GAPr */
  69262         soc_block_list[4],
  69263         soc_genreg,
  69264         1,
  69265         0,
  69266         0x160805b0,
  69267         0,
  69268         0,
  69269         1,
  69270         soc_OOBFC_TX_MESSAGE_GAPr_fields,
  69271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69272         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69273         -1,
  69274         -1,
  69275     },
  69276 #endif /* chips */
  69277 
  69278 #if defined(BCM_56840_B0)
  69279     { /* SOC_REG_INT_OOBIF_DEBUGr */
  69280         soc_block_list[4],
  69281         soc_genreg,
  69282         1,
  69283         0,
  69284         0x220800b0,
  69285         0,
  69286         0,
  69287         6,
  69288         soc_OOBIF_DEBUGr_fields,
  69289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69290         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  69291         -1,
  69292         -1,
  69293     },
  69294 #endif /* chips */
  69295 
  69296 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  69297     defined(BCM_56270_A0)
  69298     { /* SOC_REG_INT_OOBIF_DEBUG_BCM56260_A0r */
  69299         soc_block_list[4],
  69300         soc_genreg,
  69301         1,
  69302         0,
  69303         0xce002500,
  69304         0,
  69305         0,
  69306         4,
  69307         soc_OOBIF_DEBUG_BCM56260_A0r_fields,
  69308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69309         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  69310         -1,
  69311         -1,
  69312     },
  69313 #endif /* chips */
  69314 
  69315 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69316     defined(BCM_56450_B1)
  69317     { /* SOC_REG_INT_OOBIF_DEBUG_BCM56450_A0r */
  69318         soc_block_list[4],
  69319         soc_genreg,
  69320         1,
  69321         0,
  69322         0xce002500,
  69323         0,
  69324         0,
  69325         4,
  69326         soc_OOBIF_DEBUG_BCM56640_A0r_fields,
  69327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69328         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  69329         -1,
  69330         -1,
  69331     },
  69332 #endif /* chips */
  69333 
  69334 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  69335     { /* SOC_REG_INT_OOBIF_DEBUG_BCM56560_A0r */
  69336         soc_block_list[4],
  69337         soc_genreg,
  69338         1,
  69339         0,
  69340         0x5e002500,
  69341         0,
  69342         0,
  69343         3,
  69344         soc_OOBIF_DEBUG_BCM56960_A0r_fields,
  69345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69346         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69347         -1,
  69348         -1,
  69349     },
  69350 #endif /* chips */
  69351 
  69352 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  69353     { /* SOC_REG_INT_OOBIF_DEBUG_BCM56640_A0r */
  69354         soc_block_list[4],
  69355         soc_genreg,
  69356         1,
  69357         0,
  69358         0x9a002500,
  69359         0,
  69360         0,
  69361         4,
  69362         soc_OOBIF_DEBUG_BCM56640_A0r_fields,
  69363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69364         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  69365         -1,
  69366         -1,
  69367     },
  69368 #endif /* chips */
  69369 
  69370 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  69371     { /* SOC_REG_INT_OOBIF_DEBUG_BCM56850_A0r */
  69372         soc_block_list[4],
  69373         soc_genreg,
  69374         1,
  69375         0,
  69376         0x5e002500,
  69377         0,
  69378         0,
  69379         3,
  69380         soc_OOBIF_DEBUG_BCM56850_A0r_fields,
  69381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69382         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69383         -1,
  69384         -1,
  69385     },
  69386 #endif /* chips */
  69387 
  69388 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  69389     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  69390     defined(BCM_56970_A0)
  69391     { /* SOC_REG_INT_OOBIF_DEBUG_BCM56960_A0r */
  69392         soc_block_list[126],
  69393         soc_genreg,
  69394         1,
  69395         0,
  69396         0x6012500,
  69397         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69398         0,
  69399         3,
  69400         soc_OOBIF_DEBUG_BCM56960_A0r_fields,
  69401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69402         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69403         -1,
  69404         -1,
  69405         3,
  69406     },
  69407 #endif /* chips */
  69408 
  69409 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  69410     { /* SOC_REG_INT_OOBIF_RX_TESTr */
  69411         soc_block_list[4],
  69412         soc_genreg,
  69413         1,
  69414         0,
  69415         0x5e005000,
  69416         0,
  69417         0,
  69418         4,
  69419         soc_OOBIF_RX_TESTr_fields,
  69420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69421         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69422         -1,
  69423         -1,
  69424     },
  69425 #endif /* chips */
  69426 
  69427 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  69428     { /* SOC_REG_INT_OOBIF_RX_TEST_BCM56560_A0r */
  69429         soc_block_list[4],
  69430         soc_genreg,
  69431         1,
  69432         0,
  69433         0x5e005000,
  69434         0,
  69435         0,
  69436         4,
  69437         soc_OOBIF_RX_TEST_BCM56960_A0r_fields,
  69438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69439         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69440         -1,
  69441         -1,
  69442     },
  69443 #endif /* chips */
  69444 
  69445 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  69446     { /* SOC_REG_INT_OOBIF_RX_TEST_BCM56960_A0r */
  69447         soc_block_list[126],
  69448         soc_genreg,
  69449         1,
  69450         0,
  69451         0x6015000,
  69452         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69453         0,
  69454         4,
  69455         soc_OOBIF_RX_TEST_BCM56960_A0r_fields,
  69456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69457         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69458         -1,
  69459         -1,
  69460         3,
  69461     },
  69462 #endif /* chips */
  69463 
  69464 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  69465     defined(BCM_56970_A0)
  69466     { /* SOC_REG_INT_OOBIF_RX_TEST_BCM56970_A0r */
  69467         soc_block_list[126],
  69468         soc_genreg,
  69469         1,
  69470         0,
  69471         0x6015000,
  69472         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69473         0,
  69474         4,
  69475         soc_OOBIF_RX_TEST_BCM56960_A0r_fields,
  69476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69478         -1,
  69479         -1,
  69480         3,
  69481     },
  69482 #endif /* chips */
  69483 
  69484 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  69485     { /* SOC_REG_INT_OOBIF_TX_TESTr */
  69486         soc_block_list[4],
  69487         soc_genreg,
  69488         1,
  69489         0,
  69490         0x5a00a600,
  69491         0,
  69492         0,
  69493         2,
  69494         soc_OOBIF_TX_TESTr_fields,
  69495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69496         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69497         -1,
  69498         -1,
  69499     },
  69500 #endif /* chips */
  69501 
  69502 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  69503     { /* SOC_REG_INT_OOBIF_TX_TEST_BCM56560_A0r */
  69504         soc_block_list[4],
  69505         soc_genreg,
  69506         1,
  69507         0,
  69508         0x5a00a600,
  69509         0,
  69510         0,
  69511         2,
  69512         soc_OOBIF_TX_TEST_BCM56960_A0r_fields,
  69513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69514         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69515         -1,
  69516         -1,
  69517     },
  69518 #endif /* chips */
  69519 
  69520 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  69521     { /* SOC_REG_INT_OOBIF_TX_TEST_BCM56960_A0r */
  69522         soc_block_list[126],
  69523         soc_genreg,
  69524         1,
  69525         0,
  69526         0x600a600,
  69527         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69528         0,
  69529         2,
  69530         soc_OOBIF_TX_TEST_BCM56960_A0r_fields,
  69531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69532         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69533         -1,
  69534         -1,
  69535         3,
  69536     },
  69537 #endif /* chips */
  69538 
  69539 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  69540     defined(BCM_56970_A0)
  69541     { /* SOC_REG_INT_OOBIF_TX_TEST_BCM56970_A0r */
  69542         soc_block_list[126],
  69543         soc_genreg,
  69544         1,
  69545         0,
  69546         0x600a600,
  69547         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69548         0,
  69549         2,
  69550         soc_OOBIF_TX_TEST_BCM56960_A0r_fields,
  69551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69552         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69553         -1,
  69554         -1,
  69555         3,
  69556     },
  69557 #endif /* chips */
  69558 
  69559 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  69560     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  69561     defined(BCM_56970_A0)
  69562     { /* SOC_REG_INT_OOB_STATS_MSG_TX_CNTr */
  69563         soc_block_list[126],
  69564         soc_genreg,
  69565         1,
  69566         0,
  69567         0x600ac00,
  69568         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69569         0,
  69570         1,
  69571         soc_OOB_STATS_MSG_TX_CNTr_fields,
  69572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69574         -1,
  69575         -1,
  69576         3,
  69577     },
  69578 #endif /* chips */
  69579 
  69580 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  69581     { /* SOC_REG_INT_OOB_STATS_STSr */
  69582         soc_block_list[126],
  69583         soc_genreg,
  69584         1,
  69585         0,
  69586         0x600ab00,
  69587         SOC_REG_FLAG_RO |
  69588                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69589         0,
  69590         2,
  69591         soc_OOBFC_STS_BCM56960_A0r_fields,
  69592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69593         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69594         -1,
  69595         -1,
  69596         3,
  69597     },
  69598 #endif /* chips */
  69599 
  69600 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  69601     defined(BCM_56970_A0)
  69602     { /* SOC_REG_INT_OOB_STATS_STS_BCM56970_A0r */
  69603         soc_block_list[126],
  69604         soc_genreg,
  69605         1,
  69606         0,
  69607         0x600ab00,
  69608         SOC_REG_FLAG_RO |
  69609                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69610         0,
  69611         2,
  69612         soc_OOBFC_STS_BCM56960_A0r_fields,
  69613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69614         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69615         -1,
  69616         -1,
  69617         3,
  69618     },
  69619 #endif /* chips */
  69620 
  69621 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  69622     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  69623     defined(BCM_56970_A0)
  69624     { /* SOC_REG_INT_OOB_STATS_TX_IDLEr */
  69625         soc_block_list[126],
  69626         soc_genreg,
  69627         1,
  69628         0,
  69629         0x600ad00,
  69630         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69631         0,
  69632         1,
  69633         soc_OOBFC_TX_IDLE_BCM56960_A0r_fields,
  69634         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  69635         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69636         -1,
  69637         -1,
  69638         3,
  69639     },
  69640 #endif /* chips */
  69641 
  69642 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  69643     defined(BCM_56960_A0) || defined(BCM_56965_A0)
  69644     { /* SOC_REG_INT_OOB_STATS_TX_TESTr */
  69645         soc_block_list[126],
  69646         soc_genreg,
  69647         1,
  69648         0,
  69649         0x600a800,
  69650         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69651         0,
  69652         2,
  69653         soc_OOBIF_TX_TEST_BCM56960_A0r_fields,
  69654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69655         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69656         -1,
  69657         -1,
  69658         3,
  69659     },
  69660 #endif /* chips */
  69661 
  69662 #if defined(BCM_56970_A0)
  69663     { /* SOC_REG_INT_OOB_STATS_TX_TEST_BCM56970_A0r */
  69664         soc_block_list[126],
  69665         soc_genreg,
  69666         1,
  69667         0,
  69668         0x600a800,
  69669         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69670         0,
  69671         2,
  69672         soc_OOBIF_TX_TEST_BCM56960_A0r_fields,
  69673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69674         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69675         -1,
  69676         -1,
  69677         3,
  69678     },
  69679 #endif /* chips */
  69680 
  69681 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  69682     { /* SOC_REG_INT_OPAQUE_TAG_CONFIG_0r */
  69683         soc_block_list[5],
  69684         soc_genreg,
  69685         1,
  69686         0,
  69687         0x6001e00,
  69688         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69689         0,
  69690         4,
  69691         soc_OPAQUE_TAG_CONFIG_0r_fields,
  69692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69693         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69694         -1,
  69695         -1,
  69696         3,
  69697     },
  69698 #endif /* chips */
  69699 
  69700 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  69701     { /* SOC_REG_INT_OPAQUE_TAG_CONFIG_1r */
  69702         soc_block_list[5],
  69703         soc_genreg,
  69704         1,
  69705         0,
  69706         0x6001f00,
  69707         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69708         0,
  69709         4,
  69710         soc_OPAQUE_TAG_CONFIG_0r_fields,
  69711         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69712         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69713         -1,
  69714         -1,
  69715         3,
  69716     },
  69717 #endif /* chips */
  69718 
  69719 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  69720     { /* SOC_REG_INT_OPP_SCHED_CFGr */
  69721         soc_block_list[125],
  69722         soc_pipereg,
  69723         1,
  69724         0,
  69725         0x39840300,
  69726         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69727         0,
  69728         7,
  69729         soc_IS_OPP_SCHED_CFGr_fields,
  69730         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
  69731         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  69732         -1,
  69733         -1,
  69734         3,
  69735     },
  69736 #endif /* chips */
  69737 
  69738 #if defined(BCM_56370_A0)
  69739     { /* SOC_REG_INT_OPP_SCHED_CFG_BCM56370_A0r */
  69740         soc_block_list[125],
  69741         soc_pipereg,
  69742         1,
  69743         0,
  69744         0x15840500,
  69745         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69746         0,
  69747         9,
  69748         soc_IS_OPP_SCHED_CFG_BCM56370_A0r_fields,
  69749         SOC_RESET_VAL_DEC(0x09200000, 0x00000000)
  69750         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  69751         -1,
  69752         -1,
  69753         3,
  69754     },
  69755 #endif /* chips */
  69756 
  69757 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  69758     { /* SOC_REG_INT_OPP_SCHED_CFG_BCM56870_A0r */
  69759         soc_block_list[125],
  69760         soc_pipereg,
  69761         1,
  69762         0,
  69763         0x15840400,
  69764         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69765         0,
  69766         7,
  69767         soc_IS_OPP_SCHED_CFG_BCM56870_A0r_fields,
  69768         SOC_RESET_VAL_DEC(0x0010c000, 0x00000000)
  69769         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69770         -1,
  69771         -1,
  69772         3,
  69773     },
  69774 #endif /* chips */
  69775 
  69776 #if defined(BCM_56970_A0)
  69777     { /* SOC_REG_INT_OPP_SCHED_CFG_BCM56970_A0r */
  69778         soc_block_list[125],
  69779         soc_pipereg,
  69780         1,
  69781         0,
  69782         0x15840300,
  69783         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  69784         0,
  69785         7,
  69786         soc_IS_OPP_SCHED_CFG_BCM56970_A0r_fields,
  69787         SOC_RESET_VAL_DEC(0x0008c000, 0x00000000)
  69788         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  69789         -1,
  69790         -1,
  69791         3,
  69792     },
  69793 #endif /* chips */
  69794 
  69795 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  69796     { /* SOC_REG_INT_OP_BUFFER_DROP_STATESr */
  69797         soc_block_list[4],
  69798         soc_genreg,
  69799         1,
  69800         0,
  69801         0xe006c00,
  69802         SOC_REG_FLAG_RO,
  69803         0,
  69804         12,
  69805         soc_OP_BUFFER_DROP_STATESr_fields,
  69806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69807         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  69808         -1,
  69809         -1,
  69810     },
  69811 #endif /* chips */
  69812 
  69813 #if defined(BCM_88732_A0)
  69814     { /* SOC_REG_INT_OP_BUFFER_LIMIT_PRI0r */
  69815         soc_block_list[4],
  69816         soc_genreg,
  69817         1,
  69818         0,
  69819         0x308000a,
  69820         0,
  69821         0,
  69822         1,
  69823         soc_OP_BUFFER_LIMIT_PRI0r_fields,
  69824         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  69825         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  69826         -1,
  69827         -1,
  69828     },
  69829 #endif /* chips */
  69830 
  69831 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  69832     { /* SOC_REG_INT_OP_BUFFER_LIMIT_REDr */
  69833         soc_block_list[4],
  69834         soc_genreg,
  69835         1,
  69836         0,
  69837         0x3080009,
  69838         0,
  69839         0,
  69840         1,
  69841         soc_OP_BUFFER_LIMIT_REDr_fields,
  69842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69843         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  69844         -1,
  69845         -1,
  69846     },
  69847 #endif /* chips */
  69848 
  69849 #if defined(BCM_88732_A0)
  69850     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_BCM88732_A0r */
  69851         soc_block_list[4],
  69852         soc_genreg,
  69853         1,
  69854         0,
  69855         0x3080009,
  69856         0,
  69857         0,
  69858         1,
  69859         soc_OP_BUFFER_LIMIT_RED_BCM88732_A0r_fields,
  69860         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  69861         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  69862         -1,
  69863         -1,
  69864     },
  69865 #endif /* chips */
  69866 
  69867 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  69868     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  69869     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELLr */
  69870         soc_block_list[4],
  69871         soc_genreg,
  69872         1,
  69873         0,
  69874         0x3080004,
  69875         0,
  69876         0,
  69877         1,
  69878         soc_OP_BUFFER_LIMIT_RED_CELLr_fields,
  69879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69880         SOC_RESET_MASK_DEC(0x00007ff8, 0x00000000)
  69881         -1,
  69882         -1,
  69883     },
  69884 #endif /* chips */
  69885 
  69886 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69887     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELLEr */
  69888         soc_block_list[4],
  69889         soc_genreg,
  69890         1,
  69891         0,
  69892         0x3080009,
  69893         0,
  69894         0,
  69895         1,
  69896         soc_OP_BUFFER_LIMIT_RED_CELLEr_fields,
  69897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69898         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  69899         -1,
  69900         -1,
  69901     },
  69902 #endif /* chips */
  69903 
  69904 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69905     defined(BCM_56450_B1)
  69906     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELLE_POOL0r */
  69907         soc_block_list[4],
  69908         soc_genreg,
  69909         1,
  69910         0,
  69911         0xe000b00,
  69912         0,
  69913         0,
  69914         1,
  69915         soc_OP_BUFFER_LIMIT_RED_CELLE_POOL0r_fields,
  69916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69917         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  69918         -1,
  69919         -1,
  69920     },
  69921 #endif /* chips */
  69922 
  69923 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69924     defined(BCM_56450_B1)
  69925     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELLE_POOL1r */
  69926         soc_block_list[4],
  69927         soc_genreg,
  69928         1,
  69929         0,
  69930         0xe000d00,
  69931         0,
  69932         0,
  69933         1,
  69934         soc_OP_BUFFER_LIMIT_RED_CELLE_POOL0r_fields,
  69935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69936         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  69937         -1,
  69938         -1,
  69939     },
  69940 #endif /* chips */
  69941 
  69942 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  69943     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELLE_POOL0_BCM56260_A0r */
  69944         soc_block_list[4],
  69945         soc_genreg,
  69946         1,
  69947         0,
  69948         0xe000b00,
  69949         0,
  69950         0,
  69951         1,
  69952         soc_OP_BUFFER_LIMIT_RED_CELLE_POOL0_BCM56260_A0r_fields,
  69953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69954         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  69955         -1,
  69956         -1,
  69957     },
  69958 #endif /* chips */
  69959 
  69960 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  69961     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELLE_POOL1_BCM56260_A0r */
  69962         soc_block_list[4],
  69963         soc_genreg,
  69964         1,
  69965         0,
  69966         0xe000d00,
  69967         0,
  69968         0,
  69969         1,
  69970         soc_OP_BUFFER_LIMIT_RED_CELLE_POOL0_BCM56260_A0r_fields,
  69971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69972         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  69973         -1,
  69974         -1,
  69975     },
  69976 #endif /* chips */
  69977 
  69978 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69979     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELLIr */
  69980         soc_block_list[4],
  69981         soc_genreg,
  69982         1,
  69983         0,
  69984         0x3080008,
  69985         0,
  69986         0,
  69987         1,
  69988         soc_OP_BUFFER_LIMIT_RED_CELLIr_fields,
  69989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69990         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  69991         -1,
  69992         -1,
  69993     },
  69994 #endif /* chips */
  69995 
  69996 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  69997     defined(BCM_56270_A0)
  69998     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELLI_BCM56260_A0r */
  69999         soc_block_list[4],
  70000         soc_genreg,
  70001         1,
  70002         0,
  70003         0xe000a00,
  70004         0,
  70005         0,
  70006         1,
  70007         soc_OP_BUFFER_LIMIT_RED_CELLI_BCM56260_A0r_fields,
  70008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70009         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70010         -1,
  70011         -1,
  70012     },
  70013 #endif /* chips */
  70014 
  70015 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70016     defined(BCM_56450_B1)
  70017     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELLI_BCM56450_A0r */
  70018         soc_block_list[4],
  70019         soc_genreg,
  70020         1,
  70021         0,
  70022         0xe000a00,
  70023         0,
  70024         0,
  70025         1,
  70026         soc_OP_BUFFER_LIMIT_RED_CELLI_BCM56450_A0r_fields,
  70027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70028         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70029         -1,
  70030         -1,
  70031     },
  70032 #endif /* chips */
  70033 
  70034 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  70035     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELL_BCM56334_A0r */
  70036         soc_block_list[4],
  70037         soc_genreg,
  70038         1,
  70039         0,
  70040         0x3080004,
  70041         0,
  70042         0,
  70043         1,
  70044         soc_OP_BUFFER_LIMIT_RED_CELL_BCM56334_A0r_fields,
  70045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70046         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  70047         -1,
  70048         -1,
  70049     },
  70050 #endif /* chips */
  70051 
  70052 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  70053     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  70054     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  70055     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELL_BCM56634_A0r */
  70056         soc_block_list[4],
  70057         soc_genreg,
  70058         1,
  70059         0,
  70060         0x3080004,
  70061         0,
  70062         0,
  70063         1,
  70064         soc_OP_BUFFER_LIMIT_RED_CELL_BCM56634_A0r_fields,
  70065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70066         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  70067         -1,
  70068         -1,
  70069     },
  70070 #endif /* chips */
  70071 
  70072 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  70073     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELL_BCM56640_A0r */
  70074         soc_block_list[4],
  70075         soc_genreg,
  70076         4,
  70077         0,
  70078         0xe000c00,
  70079         SOC_REG_FLAG_ARRAY,
  70080         0,
  70081         1,
  70082         soc_OP_BUFFER_LIMIT_RED_CELL_BCM56640_A0r_fields,
  70083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70084         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  70085         -1,
  70086         -1,
  70087     },
  70088 #endif /* chips */
  70089 
  70090 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  70091     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_CELL_BCM56840_A0r */
  70092         soc_block_list[4],
  70093         soc_genreg,
  70094         4,
  70095         0,
  70096         0x308000c,
  70097         SOC_REG_FLAG_ARRAY,
  70098         0,
  70099         1,
  70100         soc_OP_BUFFER_LIMIT_RED_CELL_BCM56840_A0r_fields,
  70101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70102         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70103         -1,
  70104         -1,
  70105     },
  70106 #endif /* chips */
  70107 
  70108 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  70109     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  70110     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_PACKETr */
  70111         soc_block_list[4],
  70112         soc_genreg,
  70113         1,
  70114         0,
  70115         0x3080005,
  70116         0,
  70117         0,
  70118         1,
  70119         soc_OP_BUFFER_LIMIT_RED_PACKETr_fields,
  70120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70121         SOC_RESET_MASK_DEC(0x00003ffc, 0x00000000)
  70122         -1,
  70123         -1,
  70124     },
  70125 #endif /* chips */
  70126 
  70127 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  70128     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_PACKET_BCM56334_A0r */
  70129         soc_block_list[4],
  70130         soc_genreg,
  70131         1,
  70132         0,
  70133         0x3080005,
  70134         0,
  70135         0,
  70136         1,
  70137         soc_OP_BUFFER_LIMIT_RED_PACKET_BCM56334_A0r_fields,
  70138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70139         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  70140         -1,
  70141         -1,
  70142     },
  70143 #endif /* chips */
  70144 
  70145 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  70146     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  70147     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  70148     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_PACKET_BCM56634_A0r */
  70149         soc_block_list[4],
  70150         soc_genreg,
  70151         1,
  70152         0,
  70153         0x3080005,
  70154         0,
  70155         0,
  70156         1,
  70157         soc_OP_BUFFER_LIMIT_RED_PACKET_BCM56634_A0r_fields,
  70158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70159         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  70160         -1,
  70161         -1,
  70162     },
  70163 #endif /* chips */
  70164 
  70165 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70166     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_QENTRYr */
  70167         soc_block_list[4],
  70168         soc_genreg,
  70169         1,
  70170         0,
  70171         0x308000a,
  70172         0,
  70173         0,
  70174         1,
  70175         soc_OP_BUFFER_LIMIT_RED_QENTRYr_fields,
  70176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70177         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  70178         -1,
  70179         -1,
  70180     },
  70181 #endif /* chips */
  70182 
  70183 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  70184     defined(BCM_56270_A0)
  70185     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_QENTRY_BCM56260_A0r */
  70186         soc_block_list[4],
  70187         soc_genreg,
  70188         1,
  70189         0,
  70190         0xe000e00,
  70191         0,
  70192         0,
  70193         1,
  70194         soc_OP_BUFFER_LIMIT_RED_QENTRY_BCM56260_A0r_fields,
  70195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70196         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70197         -1,
  70198         -1,
  70199     },
  70200 #endif /* chips */
  70201 
  70202 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70203     defined(BCM_56450_B1)
  70204     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_QENTRY_BCM56450_A0r */
  70205         soc_block_list[4],
  70206         soc_genreg,
  70207         1,
  70208         0,
  70209         0xe000e00,
  70210         0,
  70211         0,
  70212         1,
  70213         soc_OP_BUFFER_LIMIT_RED_QENTRY_BCM56450_A0r_fields,
  70214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70215         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  70216         -1,
  70217         -1,
  70218     },
  70219 #endif /* chips */
  70220 
  70221 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70222     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_THDOEMAr */
  70223         soc_block_list[4],
  70224         soc_genreg,
  70225         1,
  70226         0,
  70227         0x2e080002,
  70228         0,
  70229         0,
  70230         1,
  70231         soc_OP_BUFFER_LIMIT_RED_THDOEMAr_fields,
  70232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70233         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70234         -1,
  70235         -1,
  70236     },
  70237 #endif /* chips */
  70238 
  70239 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  70240     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_THDOEMA_BCM56260_A0r */
  70241         soc_block_list[4],
  70242         soc_genreg,
  70243         1,
  70244         0,
  70245         0xba000200,
  70246         0,
  70247         0,
  70248         1,
  70249         soc_OP_BUFFER_LIMIT_RED_THDOEMA_BCM56260_A0r_fields,
  70250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70251         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  70252         -1,
  70253         -1,
  70254     },
  70255 #endif /* chips */
  70256 
  70257 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70258     defined(BCM_56450_B1)
  70259     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_THDOEMA_BCM56450_A0r */
  70260         soc_block_list[4],
  70261         soc_genreg,
  70262         1,
  70263         0,
  70264         0xba000200,
  70265         0,
  70266         0,
  70267         1,
  70268         soc_OP_BUFFER_LIMIT_RED_THDOEMA_BCM56450_A0r_fields,
  70269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70270         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70271         -1,
  70272         -1,
  70273     },
  70274 #endif /* chips */
  70275 
  70276 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70277     defined(BCM_56450_B1)
  70278     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_THDORDEQr */
  70279         soc_block_list[4],
  70280         soc_genreg,
  70281         1,
  70282         0,
  70283         0xca000200,
  70284         0,
  70285         0,
  70286         1,
  70287         soc_OP_BUFFER_LIMIT_RED_THDORDEQr_fields,
  70288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70289         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  70290         -1,
  70291         -1,
  70292     },
  70293 #endif /* chips */
  70294 
  70295 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  70296     defined(BCM_56270_A0)
  70297     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_THDORDEQ_BCM56260_A0r */
  70298         soc_block_list[4],
  70299         soc_genreg,
  70300         1,
  70301         0,
  70302         0xca000200,
  70303         0,
  70304         0,
  70305         1,
  70306         soc_OP_BUFFER_LIMIT_RED_THDORDEQ_BCM56260_A0r_fields,
  70307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70308         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70309         -1,
  70310         -1,
  70311     },
  70312 #endif /* chips */
  70313 
  70314 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70315     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_THDORQEQr */
  70316         soc_block_list[4],
  70317         soc_genreg,
  70318         1,
  70319         0,
  70320         0x2d080002,
  70321         0,
  70322         0,
  70323         1,
  70324         soc_OP_BUFFER_LIMIT_RED_THDORQEQr_fields,
  70325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70326         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  70327         -1,
  70328         -1,
  70329     },
  70330 #endif /* chips */
  70331 
  70332 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  70333     defined(BCM_56270_A0)
  70334     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_THDORQEQ_BCM56260_A0r */
  70335         soc_block_list[4],
  70336         soc_genreg,
  70337         1,
  70338         0,
  70339         0xb6000200,
  70340         0,
  70341         0,
  70342         1,
  70343         soc_OP_BUFFER_LIMIT_RED_THDORQEQ_BCM56260_A0r_fields,
  70344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70345         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  70346         -1,
  70347         -1,
  70348     },
  70349 #endif /* chips */
  70350 
  70351 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70352     defined(BCM_56450_B1)
  70353     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RED_THDORQEQ_BCM56450_A0r */
  70354         soc_block_list[4],
  70355         soc_genreg,
  70356         1,
  70357         0,
  70358         0xb6000200,
  70359         0,
  70360         0,
  70361         1,
  70362         soc_OP_BUFFER_LIMIT_RED_THDORQEQ_BCM56450_A0r_fields,
  70363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70364         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  70365         -1,
  70366         -1,
  70367     },
  70368 #endif /* chips */
  70369 
  70370 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  70371     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_REDr */
  70372         soc_block_list[4],
  70373         soc_genreg,
  70374         1,
  70375         0,
  70376         0x308000d,
  70377         0,
  70378         0,
  70379         1,
  70380         soc_OP_BUFFER_LIMIT_RESUME_REDr_fields,
  70381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70382         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  70383         -1,
  70384         -1,
  70385     },
  70386 #endif /* chips */
  70387 
  70388 #if defined(BCM_88732_A0)
  70389     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_BCM88732_A0r */
  70390         soc_block_list[4],
  70391         soc_genreg,
  70392         1,
  70393         0,
  70394         0x308000e,
  70395         0,
  70396         0,
  70397         1,
  70398         soc_OP_BUFFER_LIMIT_RESUME_RED_BCM88732_A0r_fields,
  70399         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  70400         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  70401         -1,
  70402         -1,
  70403     },
  70404 #endif /* chips */
  70405 
  70406 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  70407     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  70408     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELLr */
  70409         soc_block_list[4],
  70410         soc_genreg,
  70411         1,
  70412         0,
  70413         0x3080024,
  70414         0,
  70415         0,
  70416         1,
  70417         soc_OP_BUFFER_LIMIT_RESUME_RED_CELLr_fields,
  70418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70419         SOC_RESET_MASK_DEC(0x00007ff8, 0x00000000)
  70420         -1,
  70421         -1,
  70422     },
  70423 #endif /* chips */
  70424 
  70425 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70426     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELLEr */
  70427         soc_block_list[4],
  70428         soc_genreg,
  70429         1,
  70430         0,
  70431         0x3080089,
  70432         0,
  70433         0,
  70434         1,
  70435         soc_OP_BUFFER_LIMIT_RESUME_RED_CELLEr_fields,
  70436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70437         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  70438         -1,
  70439         -1,
  70440     },
  70441 #endif /* chips */
  70442 
  70443 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70444     defined(BCM_56450_B1)
  70445     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0r */
  70446         soc_block_list[4],
  70447         soc_genreg,
  70448         1,
  70449         0,
  70450         0xe008b00,
  70451         0,
  70452         0,
  70453         1,
  70454         soc_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0r_fields,
  70455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70456         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  70457         -1,
  70458         -1,
  70459     },
  70460 #endif /* chips */
  70461 
  70462 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70463     defined(BCM_56450_B1)
  70464     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL1r */
  70465         soc_block_list[4],
  70466         soc_genreg,
  70467         1,
  70468         0,
  70469         0xe008d00,
  70470         0,
  70471         0,
  70472         1,
  70473         soc_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0r_fields,
  70474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70475         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  70476         -1,
  70477         -1,
  70478     },
  70479 #endif /* chips */
  70480 
  70481 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  70482     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0_BCM56260_A0r */
  70483         soc_block_list[4],
  70484         soc_genreg,
  70485         1,
  70486         0,
  70487         0xe008b00,
  70488         0,
  70489         0,
  70490         1,
  70491         soc_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0_BCM56260_A0r_fields,
  70492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70493         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70494         -1,
  70495         -1,
  70496     },
  70497 #endif /* chips */
  70498 
  70499 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  70500     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL1_BCM56260_A0r */
  70501         soc_block_list[4],
  70502         soc_genreg,
  70503         1,
  70504         0,
  70505         0xe008d00,
  70506         0,
  70507         0,
  70508         1,
  70509         soc_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0_BCM56260_A0r_fields,
  70510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70511         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70512         -1,
  70513         -1,
  70514     },
  70515 #endif /* chips */
  70516 
  70517 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70518     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELLIr */
  70519         soc_block_list[4],
  70520         soc_genreg,
  70521         1,
  70522         0,
  70523         0x3080088,
  70524         0,
  70525         0,
  70526         1,
  70527         soc_OP_BUFFER_LIMIT_RESUME_RED_CELLIr_fields,
  70528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70529         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70530         -1,
  70531         -1,
  70532     },
  70533 #endif /* chips */
  70534 
  70535 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  70536     defined(BCM_56270_A0)
  70537     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELLI_BCM56260_A0r */
  70538         soc_block_list[4],
  70539         soc_genreg,
  70540         1,
  70541         0,
  70542         0xe008a00,
  70543         0,
  70544         0,
  70545         1,
  70546         soc_OP_BUFFER_LIMIT_RESUME_RED_CELLI_BCM56260_A0r_fields,
  70547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70548         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70549         -1,
  70550         -1,
  70551     },
  70552 #endif /* chips */
  70553 
  70554 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70555     defined(BCM_56450_B1)
  70556     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELLI_BCM56450_A0r */
  70557         soc_block_list[4],
  70558         soc_genreg,
  70559         1,
  70560         0,
  70561         0xe008a00,
  70562         0,
  70563         0,
  70564         1,
  70565         soc_OP_BUFFER_LIMIT_RESUME_RED_CELLI_BCM56450_A0r_fields,
  70566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70567         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70568         -1,
  70569         -1,
  70570     },
  70571 #endif /* chips */
  70572 
  70573 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  70574     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELL_BCM56334_A0r */
  70575         soc_block_list[4],
  70576         soc_genreg,
  70577         1,
  70578         0,
  70579         0x3080024,
  70580         0,
  70581         0,
  70582         1,
  70583         soc_OP_BUFFER_LIMIT_RESUME_RED_CELL_BCM56334_A0r_fields,
  70584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70585         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  70586         -1,
  70587         -1,
  70588     },
  70589 #endif /* chips */
  70590 
  70591 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  70592     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  70593     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  70594     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELL_BCM56634_A0r */
  70595         soc_block_list[4],
  70596         soc_genreg,
  70597         1,
  70598         0,
  70599         0x3080024,
  70600         0,
  70601         0,
  70602         1,
  70603         soc_OP_BUFFER_LIMIT_RESUME_RED_CELL_BCM56634_A0r_fields,
  70604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70605         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  70606         -1,
  70607         -1,
  70608     },
  70609 #endif /* chips */
  70610 
  70611 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  70612     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELL_BCM56640_A0r */
  70613         soc_block_list[4],
  70614         soc_genreg,
  70615         4,
  70616         0,
  70617         0xe008800,
  70618         SOC_REG_FLAG_ARRAY,
  70619         0,
  70620         1,
  70621         soc_OP_BUFFER_LIMIT_RESUME_RED_CELL_BCM56640_A0r_fields,
  70622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70623         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  70624         -1,
  70625         -1,
  70626     },
  70627 #endif /* chips */
  70628 
  70629 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  70630     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_CELL_BCM56840_A0r */
  70631         soc_block_list[4],
  70632         soc_genreg,
  70633         4,
  70634         0,
  70635         0x3080088,
  70636         SOC_REG_FLAG_ARRAY,
  70637         0,
  70638         1,
  70639         soc_OP_BUFFER_LIMIT_RESUME_RED_CELL_BCM56840_A0r_fields,
  70640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70641         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70642         -1,
  70643         -1,
  70644     },
  70645 #endif /* chips */
  70646 
  70647 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  70648     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  70649     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_PACKETr */
  70650         soc_block_list[4],
  70651         soc_genreg,
  70652         1,
  70653         0,
  70654         0x3080025,
  70655         0,
  70656         0,
  70657         1,
  70658         soc_OP_BUFFER_LIMIT_RESUME_RED_PACKETr_fields,
  70659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70660         SOC_RESET_MASK_DEC(0x00003ffc, 0x00000000)
  70661         -1,
  70662         -1,
  70663     },
  70664 #endif /* chips */
  70665 
  70666 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  70667     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_PACKET_BCM56334_A0r */
  70668         soc_block_list[4],
  70669         soc_genreg,
  70670         1,
  70671         0,
  70672         0x3080025,
  70673         0,
  70674         0,
  70675         1,
  70676         soc_OP_BUFFER_LIMIT_RESUME_RED_PACKET_BCM56334_A0r_fields,
  70677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70678         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  70679         -1,
  70680         -1,
  70681     },
  70682 #endif /* chips */
  70683 
  70684 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  70685     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  70686     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  70687     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_PACKET_BCM56634_A0r */
  70688         soc_block_list[4],
  70689         soc_genreg,
  70690         1,
  70691         0,
  70692         0x3080025,
  70693         0,
  70694         0,
  70695         1,
  70696         soc_OP_BUFFER_LIMIT_RESUME_RED_PACKET_BCM56634_A0r_fields,
  70697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70698         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  70699         -1,
  70700         -1,
  70701     },
  70702 #endif /* chips */
  70703 
  70704 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70705     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr */
  70706         soc_block_list[4],
  70707         soc_genreg,
  70708         1,
  70709         0,
  70710         0x308008a,
  70711         0,
  70712         0,
  70713         1,
  70714         soc_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr_fields,
  70715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70716         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  70717         -1,
  70718         -1,
  70719     },
  70720 #endif /* chips */
  70721 
  70722 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  70723     defined(BCM_56270_A0)
  70724     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_QENTRY_BCM56260_A0r */
  70725         soc_block_list[4],
  70726         soc_genreg,
  70727         1,
  70728         0,
  70729         0xe008e00,
  70730         0,
  70731         0,
  70732         1,
  70733         soc_OP_BUFFER_LIMIT_RESUME_RED_QENTRY_BCM56260_A0r_fields,
  70734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70735         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70736         -1,
  70737         -1,
  70738     },
  70739 #endif /* chips */
  70740 
  70741 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70742     defined(BCM_56450_B1)
  70743     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_QENTRY_BCM56450_A0r */
  70744         soc_block_list[4],
  70745         soc_genreg,
  70746         1,
  70747         0,
  70748         0xe008e00,
  70749         0,
  70750         0,
  70751         1,
  70752         soc_OP_BUFFER_LIMIT_RESUME_RED_QENTRY_BCM56450_A0r_fields,
  70753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70754         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  70755         -1,
  70756         -1,
  70757     },
  70758 #endif /* chips */
  70759 
  70760 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70761     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr */
  70762         soc_block_list[4],
  70763         soc_genreg,
  70764         1,
  70765         0,
  70766         0x2e080006,
  70767         0,
  70768         0,
  70769         1,
  70770         soc_OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr_fields,
  70771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70772         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70773         -1,
  70774         -1,
  70775     },
  70776 #endif /* chips */
  70777 
  70778 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  70779     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_THDOEMA_BCM56260_A0r */
  70780         soc_block_list[4],
  70781         soc_genreg,
  70782         1,
  70783         0,
  70784         0xba000600,
  70785         0,
  70786         0,
  70787         1,
  70788         soc_OP_BUFFER_LIMIT_RESUME_RED_THDOEMA_BCM56260_A0r_fields,
  70789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70790         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  70791         -1,
  70792         -1,
  70793     },
  70794 #endif /* chips */
  70795 
  70796 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70797     defined(BCM_56450_B1)
  70798     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_THDOEMA_BCM56450_A0r */
  70799         soc_block_list[4],
  70800         soc_genreg,
  70801         1,
  70802         0,
  70803         0xba000600,
  70804         0,
  70805         0,
  70806         1,
  70807         soc_OP_BUFFER_LIMIT_RESUME_RED_THDOEMA_BCM56450_A0r_fields,
  70808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70809         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70810         -1,
  70811         -1,
  70812     },
  70813 #endif /* chips */
  70814 
  70815 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70816     defined(BCM_56450_B1)
  70817     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr */
  70818         soc_block_list[4],
  70819         soc_genreg,
  70820         1,
  70821         0,
  70822         0xca000600,
  70823         0,
  70824         0,
  70825         1,
  70826         soc_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr_fields,
  70827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70828         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  70829         -1,
  70830         -1,
  70831     },
  70832 #endif /* chips */
  70833 
  70834 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  70835     defined(BCM_56270_A0)
  70836     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQ_BCM56260_A0r */
  70837         soc_block_list[4],
  70838         soc_genreg,
  70839         1,
  70840         0,
  70841         0xca000600,
  70842         0,
  70843         0,
  70844         1,
  70845         soc_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQ_BCM56260_A0r_fields,
  70846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70847         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70848         -1,
  70849         -1,
  70850     },
  70851 #endif /* chips */
  70852 
  70853 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70854     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr */
  70855         soc_block_list[4],
  70856         soc_genreg,
  70857         1,
  70858         0,
  70859         0x2d080006,
  70860         0,
  70861         0,
  70862         1,
  70863         soc_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr_fields,
  70864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70865         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  70866         -1,
  70867         -1,
  70868     },
  70869 #endif /* chips */
  70870 
  70871 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  70872     defined(BCM_56270_A0)
  70873     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQ_BCM56260_A0r */
  70874         soc_block_list[4],
  70875         soc_genreg,
  70876         1,
  70877         0,
  70878         0xb6000600,
  70879         0,
  70880         0,
  70881         1,
  70882         soc_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQ_BCM56260_A0r_fields,
  70883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70884         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  70885         -1,
  70886         -1,
  70887     },
  70888 #endif /* chips */
  70889 
  70890 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70891     defined(BCM_56450_B1)
  70892     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQ_BCM56450_A0r */
  70893         soc_block_list[4],
  70894         soc_genreg,
  70895         1,
  70896         0,
  70897         0xb6000600,
  70898         0,
  70899         0,
  70900         1,
  70901         soc_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQ_BCM56450_A0r_fields,
  70902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70903         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  70904         -1,
  70905         -1,
  70906     },
  70907 #endif /* chips */
  70908 
  70909 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  70910     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOWr */
  70911         soc_block_list[4],
  70912         soc_genreg,
  70913         1,
  70914         0,
  70915         0x308000c,
  70916         0,
  70917         0,
  70918         1,
  70919         soc_OP_BUFFER_LIMIT_RESUME_YELLOWr_fields,
  70920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70921         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  70922         -1,
  70923         -1,
  70924     },
  70925 #endif /* chips */
  70926 
  70927 #if defined(BCM_88732_A0)
  70928     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_BCM88732_A0r */
  70929         soc_block_list[4],
  70930         soc_genreg,
  70931         1,
  70932         0,
  70933         0x308000d,
  70934         0,
  70935         0,
  70936         1,
  70937         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_BCM88732_A0r_fields,
  70938         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  70939         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  70940         -1,
  70941         -1,
  70942     },
  70943 #endif /* chips */
  70944 
  70945 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  70946     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  70947     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLr */
  70948         soc_block_list[4],
  70949         soc_genreg,
  70950         1,
  70951         0,
  70952         0x3080022,
  70953         0,
  70954         0,
  70955         1,
  70956         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLr_fields,
  70957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70958         SOC_RESET_MASK_DEC(0x00007ff8, 0x00000000)
  70959         -1,
  70960         -1,
  70961     },
  70962 #endif /* chips */
  70963 
  70964 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70965     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEr */
  70966         soc_block_list[4],
  70967         soc_genreg,
  70968         1,
  70969         0,
  70970         0x3080085,
  70971         0,
  70972         0,
  70973         1,
  70974         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEr_fields,
  70975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70976         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  70977         -1,
  70978         -1,
  70979     },
  70980 #endif /* chips */
  70981 
  70982 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70983     defined(BCM_56450_B1)
  70984     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0r */
  70985         soc_block_list[4],
  70986         soc_genreg,
  70987         1,
  70988         0,
  70989         0xe008600,
  70990         0,
  70991         0,
  70992         1,
  70993         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0r_fields,
  70994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70995         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  70996         -1,
  70997         -1,
  70998     },
  70999 #endif /* chips */
  71000 
  71001 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71002     defined(BCM_56450_B1)
  71003     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL1r */
  71004         soc_block_list[4],
  71005         soc_genreg,
  71006         1,
  71007         0,
  71008         0xe008800,
  71009         0,
  71010         0,
  71011         1,
  71012         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0r_fields,
  71013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71014         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  71015         -1,
  71016         -1,
  71017     },
  71018 #endif /* chips */
  71019 
  71020 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  71021     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0_BCM56260_A0r */
  71022         soc_block_list[4],
  71023         soc_genreg,
  71024         1,
  71025         0,
  71026         0xe008600,
  71027         0,
  71028         0,
  71029         1,
  71030         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0_BCM56260_A0r_fields,
  71031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71032         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  71033         -1,
  71034         -1,
  71035     },
  71036 #endif /* chips */
  71037 
  71038 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  71039     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL1_BCM56260_A0r */
  71040         soc_block_list[4],
  71041         soc_genreg,
  71042         1,
  71043         0,
  71044         0xe008800,
  71045         0,
  71046         0,
  71047         1,
  71048         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0_BCM56260_A0r_fields,
  71049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71050         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  71051         -1,
  71052         -1,
  71053     },
  71054 #endif /* chips */
  71055 
  71056 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71057     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr */
  71058         soc_block_list[4],
  71059         soc_genreg,
  71060         1,
  71061         0,
  71062         0x3080084,
  71063         0,
  71064         0,
  71065         1,
  71066         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr_fields,
  71067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71068         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71069         -1,
  71070         -1,
  71071     },
  71072 #endif /* chips */
  71073 
  71074 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  71075     defined(BCM_56270_A0)
  71076     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI_BCM56260_A0r */
  71077         soc_block_list[4],
  71078         soc_genreg,
  71079         1,
  71080         0,
  71081         0xe008500,
  71082         0,
  71083         0,
  71084         1,
  71085         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI_BCM56260_A0r_fields,
  71086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71087         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71088         -1,
  71089         -1,
  71090     },
  71091 #endif /* chips */
  71092 
  71093 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71094     defined(BCM_56450_B1)
  71095     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI_BCM56450_A0r */
  71096         soc_block_list[4],
  71097         soc_genreg,
  71098         1,
  71099         0,
  71100         0xe008500,
  71101         0,
  71102         0,
  71103         1,
  71104         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI_BCM56450_A0r_fields,
  71105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71106         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71107         -1,
  71108         -1,
  71109     },
  71110 #endif /* chips */
  71111 
  71112 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  71113     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELL_BCM56334_A0r */
  71114         soc_block_list[4],
  71115         soc_genreg,
  71116         1,
  71117         0,
  71118         0x3080022,
  71119         0,
  71120         0,
  71121         1,
  71122         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELL_BCM56334_A0r_fields,
  71123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71124         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  71125         -1,
  71126         -1,
  71127     },
  71128 #endif /* chips */
  71129 
  71130 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  71131     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  71132     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  71133     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELL_BCM56634_A0r */
  71134         soc_block_list[4],
  71135         soc_genreg,
  71136         1,
  71137         0,
  71138         0x3080022,
  71139         0,
  71140         0,
  71141         1,
  71142         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELL_BCM56634_A0r_fields,
  71143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71144         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  71145         -1,
  71146         -1,
  71147     },
  71148 #endif /* chips */
  71149 
  71150 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  71151     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELL_BCM56640_A0r */
  71152         soc_block_list[4],
  71153         soc_genreg,
  71154         4,
  71155         0,
  71156         0xe008400,
  71157         SOC_REG_FLAG_ARRAY,
  71158         0,
  71159         1,
  71160         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELL_BCM56640_A0r_fields,
  71161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71162         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  71163         -1,
  71164         -1,
  71165     },
  71166 #endif /* chips */
  71167 
  71168 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  71169     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_CELL_BCM56840_A0r */
  71170         soc_block_list[4],
  71171         soc_genreg,
  71172         4,
  71173         0,
  71174         0x3080084,
  71175         SOC_REG_FLAG_ARRAY,
  71176         0,
  71177         1,
  71178         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_CELL_BCM56840_A0r_fields,
  71179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71180         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  71181         -1,
  71182         -1,
  71183     },
  71184 #endif /* chips */
  71185 
  71186 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  71187     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  71188     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_PACKETr */
  71189         soc_block_list[4],
  71190         soc_genreg,
  71191         1,
  71192         0,
  71193         0x3080023,
  71194         0,
  71195         0,
  71196         1,
  71197         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_PACKETr_fields,
  71198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71199         SOC_RESET_MASK_DEC(0x00003ffc, 0x00000000)
  71200         -1,
  71201         -1,
  71202     },
  71203 #endif /* chips */
  71204 
  71205 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  71206     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_PACKET_BCM56334_A0r */
  71207         soc_block_list[4],
  71208         soc_genreg,
  71209         1,
  71210         0,
  71211         0x3080023,
  71212         0,
  71213         0,
  71214         1,
  71215         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_PACKET_BCM56334_A0r_fields,
  71216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71217         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  71218         -1,
  71219         -1,
  71220     },
  71221 #endif /* chips */
  71222 
  71223 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  71224     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  71225     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  71226     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_PACKET_BCM56634_A0r */
  71227         soc_block_list[4],
  71228         soc_genreg,
  71229         1,
  71230         0,
  71231         0x3080023,
  71232         0,
  71233         0,
  71234         1,
  71235         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_PACKET_BCM56634_A0r_fields,
  71236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71237         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  71238         -1,
  71239         -1,
  71240     },
  71241 #endif /* chips */
  71242 
  71243 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71244     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr */
  71245         soc_block_list[4],
  71246         soc_genreg,
  71247         1,
  71248         0,
  71249         0x3080086,
  71250         0,
  71251         0,
  71252         1,
  71253         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr_fields,
  71254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71255         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  71256         -1,
  71257         -1,
  71258     },
  71259 #endif /* chips */
  71260 
  71261 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  71262     defined(BCM_56270_A0)
  71263     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY_BCM56260_A0r */
  71264         soc_block_list[4],
  71265         soc_genreg,
  71266         1,
  71267         0,
  71268         0xe008900,
  71269         0,
  71270         0,
  71271         1,
  71272         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY_BCM56260_A0r_fields,
  71273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71274         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  71275         -1,
  71276         -1,
  71277     },
  71278 #endif /* chips */
  71279 
  71280 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71281     defined(BCM_56450_B1)
  71282     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY_BCM56450_A0r */
  71283         soc_block_list[4],
  71284         soc_genreg,
  71285         1,
  71286         0,
  71287         0xe008900,
  71288         0,
  71289         0,
  71290         1,
  71291         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY_BCM56450_A0r_fields,
  71292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71293         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  71294         -1,
  71295         -1,
  71296     },
  71297 #endif /* chips */
  71298 
  71299 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71300     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr */
  71301         soc_block_list[4],
  71302         soc_genreg,
  71303         1,
  71304         0,
  71305         0x2e080005,
  71306         0,
  71307         0,
  71308         1,
  71309         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr_fields,
  71310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71311         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71312         -1,
  71313         -1,
  71314     },
  71315 #endif /* chips */
  71316 
  71317 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  71318     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMA_BCM56260_A0r */
  71319         soc_block_list[4],
  71320         soc_genreg,
  71321         1,
  71322         0,
  71323         0xba000500,
  71324         0,
  71325         0,
  71326         1,
  71327         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMA_BCM56260_A0r_fields,
  71328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71329         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  71330         -1,
  71331         -1,
  71332     },
  71333 #endif /* chips */
  71334 
  71335 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71336     defined(BCM_56450_B1)
  71337     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMA_BCM56450_A0r */
  71338         soc_block_list[4],
  71339         soc_genreg,
  71340         1,
  71341         0,
  71342         0xba000500,
  71343         0,
  71344         0,
  71345         1,
  71346         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMA_BCM56450_A0r_fields,
  71347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71348         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71349         -1,
  71350         -1,
  71351     },
  71352 #endif /* chips */
  71353 
  71354 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71355     defined(BCM_56450_B1)
  71356     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr */
  71357         soc_block_list[4],
  71358         soc_genreg,
  71359         1,
  71360         0,
  71361         0xca000500,
  71362         0,
  71363         0,
  71364         1,
  71365         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr_fields,
  71366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71367         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  71368         -1,
  71369         -1,
  71370     },
  71371 #endif /* chips */
  71372 
  71373 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  71374     defined(BCM_56270_A0)
  71375     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQ_BCM56260_A0r */
  71376         soc_block_list[4],
  71377         soc_genreg,
  71378         1,
  71379         0,
  71380         0xca000500,
  71381         0,
  71382         0,
  71383         1,
  71384         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQ_BCM56260_A0r_fields,
  71385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71386         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  71387         -1,
  71388         -1,
  71389     },
  71390 #endif /* chips */
  71391 
  71392 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71393     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr */
  71394         soc_block_list[4],
  71395         soc_genreg,
  71396         1,
  71397         0,
  71398         0x2d080005,
  71399         0,
  71400         0,
  71401         1,
  71402         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr_fields,
  71403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71404         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  71405         -1,
  71406         -1,
  71407     },
  71408 #endif /* chips */
  71409 
  71410 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  71411     defined(BCM_56270_A0)
  71412     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQ_BCM56260_A0r */
  71413         soc_block_list[4],
  71414         soc_genreg,
  71415         1,
  71416         0,
  71417         0xb6000500,
  71418         0,
  71419         0,
  71420         1,
  71421         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQ_BCM56260_A0r_fields,
  71422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71423         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  71424         -1,
  71425         -1,
  71426     },
  71427 #endif /* chips */
  71428 
  71429 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71430     defined(BCM_56450_B1)
  71431     { /* SOC_REG_INT_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQ_BCM56450_A0r */
  71432         soc_block_list[4],
  71433         soc_genreg,
  71434         1,
  71435         0,
  71436         0xb6000500,
  71437         0,
  71438         0,
  71439         1,
  71440         soc_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQ_BCM56450_A0r_fields,
  71441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71442         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  71443         -1,
  71444         -1,
  71445     },
  71446 #endif /* chips */
  71447 
  71448 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  71449     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOWr */
  71450         soc_block_list[4],
  71451         soc_genreg,
  71452         1,
  71453         0,
  71454         0x3080008,
  71455         0,
  71456         0,
  71457         1,
  71458         soc_OP_BUFFER_LIMIT_YELLOWr_fields,
  71459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71460         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  71461         -1,
  71462         -1,
  71463     },
  71464 #endif /* chips */
  71465 
  71466 #if defined(BCM_88732_A0)
  71467     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_BCM88732_A0r */
  71468         soc_block_list[4],
  71469         soc_genreg,
  71470         1,
  71471         0,
  71472         0x3080008,
  71473         0,
  71474         0,
  71475         1,
  71476         soc_OP_BUFFER_LIMIT_YELLOW_BCM88732_A0r_fields,
  71477         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  71478         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  71479         -1,
  71480         -1,
  71481     },
  71482 #endif /* chips */
  71483 
  71484 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  71485     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  71486     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELLr */
  71487         soc_block_list[4],
  71488         soc_genreg,
  71489         1,
  71490         0,
  71491         0x3080002,
  71492         0,
  71493         0,
  71494         1,
  71495         soc_OP_BUFFER_LIMIT_YELLOW_CELLr_fields,
  71496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71497         SOC_RESET_MASK_DEC(0x00007ff8, 0x00000000)
  71498         -1,
  71499         -1,
  71500     },
  71501 #endif /* chips */
  71502 
  71503 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71504     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELLEr */
  71505         soc_block_list[4],
  71506         soc_genreg,
  71507         1,
  71508         0,
  71509         0x3080005,
  71510         0,
  71511         0,
  71512         1,
  71513         soc_OP_BUFFER_LIMIT_YELLOW_CELLEr_fields,
  71514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71515         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  71516         -1,
  71517         -1,
  71518     },
  71519 #endif /* chips */
  71520 
  71521 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71522     defined(BCM_56450_B1)
  71523     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0r */
  71524         soc_block_list[4],
  71525         soc_genreg,
  71526         1,
  71527         0,
  71528         0xe000600,
  71529         0,
  71530         0,
  71531         1,
  71532         soc_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0r_fields,
  71533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71534         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  71535         -1,
  71536         -1,
  71537     },
  71538 #endif /* chips */
  71539 
  71540 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71541     defined(BCM_56450_B1)
  71542     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL1r */
  71543         soc_block_list[4],
  71544         soc_genreg,
  71545         1,
  71546         0,
  71547         0xe000800,
  71548         0,
  71549         0,
  71550         1,
  71551         soc_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0r_fields,
  71552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71553         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  71554         -1,
  71555         -1,
  71556     },
  71557 #endif /* chips */
  71558 
  71559 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  71560     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0_BCM56260_A0r */
  71561         soc_block_list[4],
  71562         soc_genreg,
  71563         1,
  71564         0,
  71565         0xe000600,
  71566         0,
  71567         0,
  71568         1,
  71569         soc_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0_BCM56260_A0r_fields,
  71570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71571         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  71572         -1,
  71573         -1,
  71574     },
  71575 #endif /* chips */
  71576 
  71577 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  71578     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL1_BCM56260_A0r */
  71579         soc_block_list[4],
  71580         soc_genreg,
  71581         1,
  71582         0,
  71583         0xe000800,
  71584         0,
  71585         0,
  71586         1,
  71587         soc_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0_BCM56260_A0r_fields,
  71588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71589         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  71590         -1,
  71591         -1,
  71592     },
  71593 #endif /* chips */
  71594 
  71595 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71596     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELLIr */
  71597         soc_block_list[4],
  71598         soc_genreg,
  71599         1,
  71600         0,
  71601         0x3080004,
  71602         0,
  71603         0,
  71604         1,
  71605         soc_OP_BUFFER_LIMIT_YELLOW_CELLIr_fields,
  71606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71607         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71608         -1,
  71609         -1,
  71610     },
  71611 #endif /* chips */
  71612 
  71613 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  71614     defined(BCM_56270_A0)
  71615     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELLI_BCM56260_A0r */
  71616         soc_block_list[4],
  71617         soc_genreg,
  71618         1,
  71619         0,
  71620         0xe000500,
  71621         0,
  71622         0,
  71623         1,
  71624         soc_OP_BUFFER_LIMIT_YELLOW_CELLI_BCM56260_A0r_fields,
  71625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71626         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71627         -1,
  71628         -1,
  71629     },
  71630 #endif /* chips */
  71631 
  71632 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71633     defined(BCM_56450_B1)
  71634     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELLI_BCM56450_A0r */
  71635         soc_block_list[4],
  71636         soc_genreg,
  71637         1,
  71638         0,
  71639         0xe000500,
  71640         0,
  71641         0,
  71642         1,
  71643         soc_OP_BUFFER_LIMIT_YELLOW_CELLI_BCM56450_A0r_fields,
  71644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71645         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71646         -1,
  71647         -1,
  71648     },
  71649 #endif /* chips */
  71650 
  71651 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  71652     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELL_BCM56334_A0r */
  71653         soc_block_list[4],
  71654         soc_genreg,
  71655         1,
  71656         0,
  71657         0x3080002,
  71658         0,
  71659         0,
  71660         1,
  71661         soc_OP_BUFFER_LIMIT_YELLOW_CELL_BCM56334_A0r_fields,
  71662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71663         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  71664         -1,
  71665         -1,
  71666     },
  71667 #endif /* chips */
  71668 
  71669 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  71670     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  71671     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  71672     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELL_BCM56634_A0r */
  71673         soc_block_list[4],
  71674         soc_genreg,
  71675         1,
  71676         0,
  71677         0x3080002,
  71678         0,
  71679         0,
  71680         1,
  71681         soc_OP_BUFFER_LIMIT_YELLOW_CELL_BCM56634_A0r_fields,
  71682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71683         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  71684         -1,
  71685         -1,
  71686     },
  71687 #endif /* chips */
  71688 
  71689 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  71690     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELL_BCM56640_A0r */
  71691         soc_block_list[4],
  71692         soc_genreg,
  71693         4,
  71694         0,
  71695         0xe000800,
  71696         SOC_REG_FLAG_ARRAY,
  71697         0,
  71698         1,
  71699         soc_OP_BUFFER_LIMIT_YELLOW_CELL_BCM56640_A0r_fields,
  71700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71701         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  71702         -1,
  71703         -1,
  71704     },
  71705 #endif /* chips */
  71706 
  71707 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  71708     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_CELL_BCM56840_A0r */
  71709         soc_block_list[4],
  71710         soc_genreg,
  71711         4,
  71712         0,
  71713         0x3080008,
  71714         SOC_REG_FLAG_ARRAY,
  71715         0,
  71716         1,
  71717         soc_OP_BUFFER_LIMIT_YELLOW_CELL_BCM56840_A0r_fields,
  71718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71719         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  71720         -1,
  71721         -1,
  71722     },
  71723 #endif /* chips */
  71724 
  71725 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  71726     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  71727     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_PACKETr */
  71728         soc_block_list[4],
  71729         soc_genreg,
  71730         1,
  71731         0,
  71732         0x3080003,
  71733         0,
  71734         0,
  71735         1,
  71736         soc_OP_BUFFER_LIMIT_YELLOW_PACKETr_fields,
  71737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71738         SOC_RESET_MASK_DEC(0x00003ffc, 0x00000000)
  71739         -1,
  71740         -1,
  71741     },
  71742 #endif /* chips */
  71743 
  71744 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  71745     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_PACKET_BCM56334_A0r */
  71746         soc_block_list[4],
  71747         soc_genreg,
  71748         1,
  71749         0,
  71750         0x3080003,
  71751         0,
  71752         0,
  71753         1,
  71754         soc_OP_BUFFER_LIMIT_YELLOW_PACKET_BCM56334_A0r_fields,
  71755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71756         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  71757         -1,
  71758         -1,
  71759     },
  71760 #endif /* chips */
  71761 
  71762 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  71763     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  71764     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  71765     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_PACKET_BCM56634_A0r */
  71766         soc_block_list[4],
  71767         soc_genreg,
  71768         1,
  71769         0,
  71770         0x3080003,
  71771         0,
  71772         0,
  71773         1,
  71774         soc_OP_BUFFER_LIMIT_YELLOW_PACKET_BCM56634_A0r_fields,
  71775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71776         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  71777         -1,
  71778         -1,
  71779     },
  71780 #endif /* chips */
  71781 
  71782 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71783     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_QENTRYr */
  71784         soc_block_list[4],
  71785         soc_genreg,
  71786         1,
  71787         0,
  71788         0x3080006,
  71789         0,
  71790         0,
  71791         1,
  71792         soc_OP_BUFFER_LIMIT_YELLOW_QENTRYr_fields,
  71793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71794         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  71795         -1,
  71796         -1,
  71797     },
  71798 #endif /* chips */
  71799 
  71800 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  71801     defined(BCM_56270_A0)
  71802     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_QENTRY_BCM56260_A0r */
  71803         soc_block_list[4],
  71804         soc_genreg,
  71805         1,
  71806         0,
  71807         0xe000900,
  71808         0,
  71809         0,
  71810         1,
  71811         soc_OP_BUFFER_LIMIT_YELLOW_QENTRY_BCM56260_A0r_fields,
  71812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71813         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  71814         -1,
  71815         -1,
  71816     },
  71817 #endif /* chips */
  71818 
  71819 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71820     defined(BCM_56450_B1)
  71821     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_QENTRY_BCM56450_A0r */
  71822         soc_block_list[4],
  71823         soc_genreg,
  71824         1,
  71825         0,
  71826         0xe000900,
  71827         0,
  71828         0,
  71829         1,
  71830         soc_OP_BUFFER_LIMIT_YELLOW_QENTRY_BCM56450_A0r_fields,
  71831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71832         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  71833         -1,
  71834         -1,
  71835     },
  71836 #endif /* chips */
  71837 
  71838 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71839     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_THDOEMAr */
  71840         soc_block_list[4],
  71841         soc_genreg,
  71842         1,
  71843         0,
  71844         0x2e080001,
  71845         0,
  71846         0,
  71847         1,
  71848         soc_OP_BUFFER_LIMIT_YELLOW_THDOEMAr_fields,
  71849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71850         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71851         -1,
  71852         -1,
  71853     },
  71854 #endif /* chips */
  71855 
  71856 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  71857     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_THDOEMA_BCM56260_A0r */
  71858         soc_block_list[4],
  71859         soc_genreg,
  71860         1,
  71861         0,
  71862         0xba000100,
  71863         0,
  71864         0,
  71865         1,
  71866         soc_OP_BUFFER_LIMIT_YELLOW_THDOEMA_BCM56260_A0r_fields,
  71867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71868         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  71869         -1,
  71870         -1,
  71871     },
  71872 #endif /* chips */
  71873 
  71874 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71875     defined(BCM_56450_B1)
  71876     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_THDOEMA_BCM56450_A0r */
  71877         soc_block_list[4],
  71878         soc_genreg,
  71879         1,
  71880         0,
  71881         0xba000100,
  71882         0,
  71883         0,
  71884         1,
  71885         soc_OP_BUFFER_LIMIT_YELLOW_THDOEMA_BCM56450_A0r_fields,
  71886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71887         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  71888         -1,
  71889         -1,
  71890     },
  71891 #endif /* chips */
  71892 
  71893 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71894     defined(BCM_56450_B1)
  71895     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_THDORDEQr */
  71896         soc_block_list[4],
  71897         soc_genreg,
  71898         1,
  71899         0,
  71900         0xca000100,
  71901         0,
  71902         0,
  71903         1,
  71904         soc_OP_BUFFER_LIMIT_YELLOW_THDORDEQr_fields,
  71905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71906         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  71907         -1,
  71908         -1,
  71909     },
  71910 #endif /* chips */
  71911 
  71912 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  71913     defined(BCM_56270_A0)
  71914     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_THDORDEQ_BCM56260_A0r */
  71915         soc_block_list[4],
  71916         soc_genreg,
  71917         1,
  71918         0,
  71919         0xca000100,
  71920         0,
  71921         0,
  71922         1,
  71923         soc_OP_BUFFER_LIMIT_YELLOW_THDORDEQ_BCM56260_A0r_fields,
  71924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71925         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  71926         -1,
  71927         -1,
  71928     },
  71929 #endif /* chips */
  71930 
  71931 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71932     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_THDORQEQr */
  71933         soc_block_list[4],
  71934         soc_genreg,
  71935         1,
  71936         0,
  71937         0x2d080001,
  71938         0,
  71939         0,
  71940         1,
  71941         soc_OP_BUFFER_LIMIT_YELLOW_THDORQEQr_fields,
  71942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71943         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  71944         -1,
  71945         -1,
  71946     },
  71947 #endif /* chips */
  71948 
  71949 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  71950     defined(BCM_56270_A0)
  71951     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_THDORQEQ_BCM56260_A0r */
  71952         soc_block_list[4],
  71953         soc_genreg,
  71954         1,
  71955         0,
  71956         0xb6000100,
  71957         0,
  71958         0,
  71959         1,
  71960         soc_OP_BUFFER_LIMIT_YELLOW_THDORQEQ_BCM56260_A0r_fields,
  71961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71962         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  71963         -1,
  71964         -1,
  71965     },
  71966 #endif /* chips */
  71967 
  71968 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71969     defined(BCM_56450_B1)
  71970     { /* SOC_REG_INT_OP_BUFFER_LIMIT_YELLOW_THDORQEQ_BCM56450_A0r */
  71971         soc_block_list[4],
  71972         soc_genreg,
  71973         1,
  71974         0,
  71975         0xb6000100,
  71976         0,
  71977         0,
  71978         1,
  71979         soc_OP_BUFFER_LIMIT_YELLOW_THDORQEQ_BCM56450_A0r_fields,
  71980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71981         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  71982         -1,
  71983         -1,
  71984     },
  71985 #endif /* chips */
  71986 
  71987 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  71988     { /* SOC_REG_INT_OP_BUFFER_MAX_TOTAL_COUNT_CELLr */
  71989         soc_block_list[4],
  71990         soc_genreg,
  71991         4,
  71992         0,
  71993         0x3080048,
  71994         SOC_REG_FLAG_ARRAY,
  71995         0,
  71996         1,
  71997         soc_OP_BUFFER_MAX_TOTAL_COUNT_CELLr_fields,
  71998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71999         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72000         -1,
  72001         -1,
  72002     },
  72003 #endif /* chips */
  72004 
  72005 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  72006     { /* SOC_REG_INT_OP_BUFFER_MAX_TOTAL_COUNT_CELL_BCM56640_A0r */
  72007         soc_block_list[4],
  72008         soc_genreg,
  72009         4,
  72010         0,
  72011         0xe004800,
  72012         SOC_REG_FLAG_ARRAY,
  72013         0,
  72014         1,
  72015         soc_OP_BUFFER_MAX_TOTAL_COUNT_CELL_BCM56640_A0r_fields,
  72016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72017         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  72018         -1,
  72019         -1,
  72020     },
  72021 #endif /* chips */
  72022 
  72023 #if defined(BCM_56800_A0)
  72024     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNTr */
  72025         soc_block_list[4],
  72026         soc_genreg,
  72027         1,
  72028         0,
  72029         0x3080020,
  72030         SOC_REG_FLAG_RO,
  72031         0,
  72032         1,
  72033         soc_OP_BUFFER_SHARED_COUNTr_fields,
  72034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72035         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72036         -1,
  72037         -1,
  72038     },
  72039 #endif /* chips */
  72040 
  72041 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  72042     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_BCM56820_A0r */
  72043         soc_block_list[4],
  72044         soc_genreg,
  72045         1,
  72046         0,
  72047         0x3080005,
  72048         SOC_REG_FLAG_RO,
  72049         0,
  72050         1,
  72051         soc_OP_BUFFER_SHARED_COUNTr_fields,
  72052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72053         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72054         -1,
  72055         -1,
  72056     },
  72057 #endif /* chips */
  72058 
  72059 #if defined(BCM_88732_A0)
  72060     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_BCM88732_A0r */
  72061         soc_block_list[4],
  72062         soc_genreg,
  72063         1,
  72064         0,
  72065         0x3080005,
  72066         SOC_REG_FLAG_RO,
  72067         0,
  72068         1,
  72069         soc_OP_BUFFER_SHARED_COUNT_BCM88732_A0r_fields,
  72070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72071         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  72072         -1,
  72073         -1,
  72074     },
  72075 #endif /* chips */
  72076 
  72077 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  72078     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  72079     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  72080     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  72081     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  72082     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELLr */
  72083         soc_block_list[4],
  72084         soc_genreg,
  72085         1,
  72086         0,
  72087         0x308000e,
  72088         SOC_REG_FLAG_RO,
  72089         0,
  72090         1,
  72091         soc_OP_BUFFER_SHARED_COUNT_CELLr_fields,
  72092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72093         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  72094         -1,
  72095         -1,
  72096     },
  72097 #endif /* chips */
  72098 
  72099 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72100     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELLEr */
  72101         soc_block_list[4],
  72102         soc_genreg,
  72103         1,
  72104         0,
  72105         0x3080041,
  72106         SOC_REG_FLAG_RO,
  72107         0,
  72108         1,
  72109         soc_OP_BUFFER_SHARED_COUNT_CELLEr_fields,
  72110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72111         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72112         -1,
  72113         -1,
  72114     },
  72115 #endif /* chips */
  72116 
  72117 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72118     defined(BCM_56450_B1)
  72119     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELLE_POOL0r */
  72120         soc_block_list[4],
  72121         soc_genreg,
  72122         1,
  72123         0,
  72124         0xe004100,
  72125         SOC_REG_FLAG_RO,
  72126         0,
  72127         1,
  72128         soc_OP_BUFFER_SHARED_COUNT_CELLE_POOL0r_fields,
  72129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72130         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72131         -1,
  72132         -1,
  72133     },
  72134 #endif /* chips */
  72135 
  72136 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72137     defined(BCM_56450_B1)
  72138     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELLE_POOL1r */
  72139         soc_block_list[4],
  72140         soc_genreg,
  72141         1,
  72142         0,
  72143         0xe004300,
  72144         SOC_REG_FLAG_RO,
  72145         0,
  72146         1,
  72147         soc_OP_BUFFER_SHARED_COUNT_CELLE_POOL0r_fields,
  72148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72149         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72150         -1,
  72151         -1,
  72152     },
  72153 #endif /* chips */
  72154 
  72155 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  72156     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELLE_POOL0_BCM56260_A0r */
  72157         soc_block_list[4],
  72158         soc_genreg,
  72159         1,
  72160         0,
  72161         0xe004100,
  72162         SOC_REG_FLAG_RO,
  72163         0,
  72164         1,
  72165         soc_OP_BUFFER_SHARED_COUNT_CELLE_POOL0_BCM56260_A0r_fields,
  72166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72167         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72168         -1,
  72169         -1,
  72170     },
  72171 #endif /* chips */
  72172 
  72173 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  72174     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELLE_POOL1_BCM56260_A0r */
  72175         soc_block_list[4],
  72176         soc_genreg,
  72177         1,
  72178         0,
  72179         0xe004300,
  72180         SOC_REG_FLAG_RO,
  72181         0,
  72182         1,
  72183         soc_OP_BUFFER_SHARED_COUNT_CELLE_POOL0_BCM56260_A0r_fields,
  72184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72185         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72186         -1,
  72187         -1,
  72188     },
  72189 #endif /* chips */
  72190 
  72191 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72192     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELLIr */
  72193         soc_block_list[4],
  72194         soc_genreg,
  72195         1,
  72196         0,
  72197         0x3080040,
  72198         SOC_REG_FLAG_RO,
  72199         0,
  72200         1,
  72201         soc_OP_BUFFER_SHARED_COUNT_CELLIr_fields,
  72202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72203         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72204         -1,
  72205         -1,
  72206     },
  72207 #endif /* chips */
  72208 
  72209 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  72210     defined(BCM_56270_A0)
  72211     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELLI_BCM56260_A0r */
  72212         soc_block_list[4],
  72213         soc_genreg,
  72214         1,
  72215         0,
  72216         0xe004000,
  72217         SOC_REG_FLAG_RO,
  72218         0,
  72219         1,
  72220         soc_OP_BUFFER_SHARED_COUNT_CELLI_BCM56260_A0r_fields,
  72221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72222         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72223         -1,
  72224         -1,
  72225     },
  72226 #endif /* chips */
  72227 
  72228 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72229     defined(BCM_56450_B1)
  72230     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELLI_BCM56450_A0r */
  72231         soc_block_list[4],
  72232         soc_genreg,
  72233         1,
  72234         0,
  72235         0xe004000,
  72236         SOC_REG_FLAG_RO,
  72237         0,
  72238         1,
  72239         soc_OP_BUFFER_SHARED_COUNT_CELLI_BCM56450_A0r_fields,
  72240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72241         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72242         -1,
  72243         -1,
  72244     },
  72245 #endif /* chips */
  72246 
  72247 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  72248     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELL_BCM56334_A0r */
  72249         soc_block_list[4],
  72250         soc_genreg,
  72251         1,
  72252         0,
  72253         0x308000e,
  72254         SOC_REG_FLAG_RO,
  72255         0,
  72256         1,
  72257         soc_OP_BUFFER_SHARED_COUNT_CELL_BCM56334_A0r_fields,
  72258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72259         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72260         -1,
  72261         -1,
  72262     },
  72263 #endif /* chips */
  72264 
  72265 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  72266     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELL_BCM56640_A0r */
  72267         soc_block_list[4],
  72268         soc_genreg,
  72269         4,
  72270         0,
  72271         0xe004000,
  72272         SOC_REG_FLAG_ARRAY |
  72273                           SOC_REG_FLAG_RO,
  72274         0,
  72275         1,
  72276         soc_OP_BUFFER_SHARED_COUNT_CELL_BCM56640_A0r_fields,
  72277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72278         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  72279         -1,
  72280         -1,
  72281     },
  72282 #endif /* chips */
  72283 
  72284 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  72285     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_CELL_BCM56840_A0r */
  72286         soc_block_list[4],
  72287         soc_genreg,
  72288         4,
  72289         0,
  72290         0x3080040,
  72291         SOC_REG_FLAG_ARRAY |
  72292                           SOC_REG_FLAG_RO,
  72293         0,
  72294         1,
  72295         soc_OP_BUFFER_SHARED_COUNT_CELL_BCM56840_A0r_fields,
  72296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72297         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72298         -1,
  72299         -1,
  72300     },
  72301 #endif /* chips */
  72302 
  72303 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  72304     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  72305     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  72306     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  72307     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  72308     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_PACKETr */
  72309         soc_block_list[4],
  72310         soc_genreg,
  72311         1,
  72312         0,
  72313         0x308000f,
  72314         SOC_REG_FLAG_RO,
  72315         0,
  72316         1,
  72317         soc_OP_BUFFER_SHARED_COUNT_PACKETr_fields,
  72318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72319         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72320         -1,
  72321         -1,
  72322     },
  72323 #endif /* chips */
  72324 
  72325 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  72326     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_PACKET_BCM56334_A0r */
  72327         soc_block_list[4],
  72328         soc_genreg,
  72329         1,
  72330         0,
  72331         0x308000f,
  72332         SOC_REG_FLAG_RO,
  72333         0,
  72334         1,
  72335         soc_OP_BUFFER_SHARED_COUNT_PACKET_BCM56334_A0r_fields,
  72336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72337         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  72338         -1,
  72339         -1,
  72340     },
  72341 #endif /* chips */
  72342 
  72343 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72344     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_QENTRYr */
  72345         soc_block_list[4],
  72346         soc_genreg,
  72347         1,
  72348         0,
  72349         0x3080048,
  72350         SOC_REG_FLAG_RO,
  72351         0,
  72352         1,
  72353         soc_OP_BUFFER_SHARED_COUNT_QENTRYr_fields,
  72354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72355         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72356         -1,
  72357         -1,
  72358     },
  72359 #endif /* chips */
  72360 
  72361 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  72362     defined(BCM_56270_A0)
  72363     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_QENTRY_BCM56260_A0r */
  72364         soc_block_list[4],
  72365         soc_genreg,
  72366         1,
  72367         0,
  72368         0xe004800,
  72369         SOC_REG_FLAG_RO,
  72370         0,
  72371         1,
  72372         soc_OP_BUFFER_SHARED_COUNT_QENTRY_BCM56260_A0r_fields,
  72373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72374         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72375         -1,
  72376         -1,
  72377     },
  72378 #endif /* chips */
  72379 
  72380 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72381     defined(BCM_56450_B1)
  72382     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_QENTRY_BCM56450_A0r */
  72383         soc_block_list[4],
  72384         soc_genreg,
  72385         1,
  72386         0,
  72387         0xe004800,
  72388         SOC_REG_FLAG_RO,
  72389         0,
  72390         1,
  72391         soc_OP_BUFFER_SHARED_COUNT_QENTRY_BCM56450_A0r_fields,
  72392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72393         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72394         -1,
  72395         -1,
  72396     },
  72397 #endif /* chips */
  72398 
  72399 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72400     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_THDOEMAr */
  72401         soc_block_list[4],
  72402         soc_genreg,
  72403         1,
  72404         0,
  72405         0x2e080003,
  72406         SOC_REG_FLAG_RO,
  72407         0,
  72408         1,
  72409         soc_OP_BUFFER_SHARED_COUNTr_fields,
  72410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72411         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72412         -1,
  72413         -1,
  72414     },
  72415 #endif /* chips */
  72416 
  72417 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  72418     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_THDOEMA_BCM56260_A0r */
  72419         soc_block_list[4],
  72420         soc_genreg,
  72421         1,
  72422         0,
  72423         0xba000300,
  72424         SOC_REG_FLAG_RO,
  72425         0,
  72426         1,
  72427         soc_OP_BUFFER_SHARED_COUNT_THDOEMA_BCM56260_A0r_fields,
  72428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72429         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  72430         -1,
  72431         -1,
  72432     },
  72433 #endif /* chips */
  72434 
  72435 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72436     defined(BCM_56450_B1)
  72437     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_THDOEMA_BCM56450_A0r */
  72438         soc_block_list[4],
  72439         soc_genreg,
  72440         1,
  72441         0,
  72442         0xba000300,
  72443         SOC_REG_FLAG_RO,
  72444         0,
  72445         1,
  72446         soc_OP_BUFFER_SHARED_COUNT_THDOEMAr_fields,
  72447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72448         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72449         -1,
  72450         -1,
  72451     },
  72452 #endif /* chips */
  72453 
  72454 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72455     defined(BCM_56450_B1)
  72456     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_THDORDEQr */
  72457         soc_block_list[4],
  72458         soc_genreg,
  72459         1,
  72460         0,
  72461         0xca000300,
  72462         SOC_REG_FLAG_RO,
  72463         0,
  72464         1,
  72465         soc_OP_BUFFER_SHARED_COUNT_THDORDEQr_fields,
  72466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72467         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  72468         -1,
  72469         -1,
  72470     },
  72471 #endif /* chips */
  72472 
  72473 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  72474     defined(BCM_56270_A0)
  72475     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_THDORDEQ_BCM56260_A0r */
  72476         soc_block_list[4],
  72477         soc_genreg,
  72478         1,
  72479         0,
  72480         0xca000300,
  72481         SOC_REG_FLAG_RO,
  72482         0,
  72483         1,
  72484         soc_OP_BUFFER_SHARED_COUNT_THDORDEQ_BCM56260_A0r_fields,
  72485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72486         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  72487         -1,
  72488         -1,
  72489     },
  72490 #endif /* chips */
  72491 
  72492 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72493     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_THDORQEQr */
  72494         soc_block_list[4],
  72495         soc_genreg,
  72496         1,
  72497         0,
  72498         0x2d080003,
  72499         SOC_REG_FLAG_RO,
  72500         0,
  72501         1,
  72502         soc_OP_BUFFER_SHARED_COUNT_THDORQEQr_fields,
  72503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72504         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  72505         -1,
  72506         -1,
  72507     },
  72508 #endif /* chips */
  72509 
  72510 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  72511     defined(BCM_56270_A0)
  72512     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_THDORQEQ_BCM56260_A0r */
  72513         soc_block_list[4],
  72514         soc_genreg,
  72515         1,
  72516         0,
  72517         0xb6000300,
  72518         SOC_REG_FLAG_RO,
  72519         0,
  72520         1,
  72521         soc_OP_BUFFER_SHARED_COUNT_THDORQEQ_BCM56260_A0r_fields,
  72522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72523         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  72524         -1,
  72525         -1,
  72526     },
  72527 #endif /* chips */
  72528 
  72529 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72530     defined(BCM_56450_B1)
  72531     { /* SOC_REG_INT_OP_BUFFER_SHARED_COUNT_THDORQEQ_BCM56450_A0r */
  72532         soc_block_list[4],
  72533         soc_genreg,
  72534         1,
  72535         0,
  72536         0xb6000300,
  72537         SOC_REG_FLAG_RO,
  72538         0,
  72539         1,
  72540         soc_OP_BUFFER_SHARED_COUNT_THDORQEQ_BCM56450_A0r_fields,
  72541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72542         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  72543         -1,
  72544         -1,
  72545     },
  72546 #endif /* chips */
  72547 
  72548 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  72549     defined(BCM_56820_A0)
  72550     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMITr */
  72551         soc_block_list[4],
  72552         soc_genreg,
  72553         1,
  72554         0,
  72555         0x3080000,
  72556         0,
  72557         0,
  72558         1,
  72559         soc_OP_BUFFER_SHARED_LIMITr_fields,
  72560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72561         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72562         -1,
  72563         -1,
  72564     },
  72565 #endif /* chips */
  72566 
  72567 #if defined(BCM_88732_A0)
  72568     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_BCM88732_A0r */
  72569         soc_block_list[4],
  72570         soc_genreg,
  72571         1,
  72572         0,
  72573         0x3080000,
  72574         0,
  72575         0,
  72576         1,
  72577         soc_OP_BUFFER_SHARED_LIMIT_BCM88732_A0r_fields,
  72578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72579         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  72580         -1,
  72581         -1,
  72582     },
  72583 #endif /* chips */
  72584 
  72585 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  72586     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  72587     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  72588     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  72589     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  72590     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELLr */
  72591         soc_block_list[4],
  72592         soc_genreg,
  72593         1,
  72594         0,
  72595         0x3080000,
  72596         0,
  72597         0,
  72598         1,
  72599         soc_OP_BUFFER_SHARED_LIMIT_CELLr_fields,
  72600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72601         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  72602         -1,
  72603         -1,
  72604     },
  72605 #endif /* chips */
  72606 
  72607 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72608     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELLEr */
  72609         soc_block_list[4],
  72610         soc_genreg,
  72611         1,
  72612         0,
  72613         0x3080001,
  72614         0,
  72615         0,
  72616         1,
  72617         soc_OP_BUFFER_SHARED_LIMIT_CELLEr_fields,
  72618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72619         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72620         -1,
  72621         -1,
  72622     },
  72623 #endif /* chips */
  72624 
  72625 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72626     defined(BCM_56450_B1)
  72627     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r */
  72628         soc_block_list[4],
  72629         soc_genreg,
  72630         1,
  72631         0,
  72632         0xe000100,
  72633         0,
  72634         0,
  72635         1,
  72636         soc_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r_fields,
  72637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72638         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72639         -1,
  72640         -1,
  72641     },
  72642 #endif /* chips */
  72643 
  72644 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72645     defined(BCM_56450_B1)
  72646     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELLE_POOL1r */
  72647         soc_block_list[4],
  72648         soc_genreg,
  72649         1,
  72650         0,
  72651         0xe000300,
  72652         0,
  72653         0,
  72654         1,
  72655         soc_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r_fields,
  72656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72657         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72658         -1,
  72659         -1,
  72660     },
  72661 #endif /* chips */
  72662 
  72663 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  72664     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0_BCM56260_A0r */
  72665         soc_block_list[4],
  72666         soc_genreg,
  72667         1,
  72668         0,
  72669         0xe000100,
  72670         0,
  72671         0,
  72672         1,
  72673         soc_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0_BCM56260_A0r_fields,
  72674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72675         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72676         -1,
  72677         -1,
  72678     },
  72679 #endif /* chips */
  72680 
  72681 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  72682     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELLE_POOL1_BCM56260_A0r */
  72683         soc_block_list[4],
  72684         soc_genreg,
  72685         1,
  72686         0,
  72687         0xe000300,
  72688         0,
  72689         0,
  72690         1,
  72691         soc_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0_BCM56260_A0r_fields,
  72692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72693         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72694         -1,
  72695         -1,
  72696     },
  72697 #endif /* chips */
  72698 
  72699 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72700     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELLIr */
  72701         soc_block_list[4],
  72702         soc_genreg,
  72703         1,
  72704         0,
  72705         0x3080000,
  72706         0,
  72707         0,
  72708         1,
  72709         soc_OP_BUFFER_SHARED_LIMIT_CELLIr_fields,
  72710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72711         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72712         -1,
  72713         -1,
  72714     },
  72715 #endif /* chips */
  72716 
  72717 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  72718     defined(BCM_56270_A0)
  72719     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELLI_BCM56260_A0r */
  72720         soc_block_list[4],
  72721         soc_genreg,
  72722         1,
  72723         0,
  72724         0xe000000,
  72725         0,
  72726         0,
  72727         1,
  72728         soc_OP_BUFFER_SHARED_LIMIT_CELLI_BCM56260_A0r_fields,
  72729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72730         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72731         -1,
  72732         -1,
  72733     },
  72734 #endif /* chips */
  72735 
  72736 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72737     defined(BCM_56450_B1)
  72738     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELLI_BCM56450_A0r */
  72739         soc_block_list[4],
  72740         soc_genreg,
  72741         1,
  72742         0,
  72743         0xe000000,
  72744         0,
  72745         0,
  72746         1,
  72747         soc_OP_BUFFER_SHARED_LIMIT_CELLI_BCM56450_A0r_fields,
  72748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72749         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72750         -1,
  72751         -1,
  72752     },
  72753 #endif /* chips */
  72754 
  72755 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  72756     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELL_BCM56334_A0r */
  72757         soc_block_list[4],
  72758         soc_genreg,
  72759         1,
  72760         0,
  72761         0x3080000,
  72762         0,
  72763         0,
  72764         1,
  72765         soc_OP_BUFFER_SHARED_LIMIT_CELL_BCM56334_A0r_fields,
  72766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72767         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72768         -1,
  72769         -1,
  72770     },
  72771 #endif /* chips */
  72772 
  72773 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  72774     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELL_BCM56640_A0r */
  72775         soc_block_list[4],
  72776         soc_genreg,
  72777         4,
  72778         0,
  72779         0xe000400,
  72780         SOC_REG_FLAG_ARRAY,
  72781         0,
  72782         1,
  72783         soc_OP_BUFFER_SHARED_LIMIT_CELL_BCM56640_A0r_fields,
  72784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72785         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  72786         -1,
  72787         -1,
  72788     },
  72789 #endif /* chips */
  72790 
  72791 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  72792     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_CELL_BCM56840_A0r */
  72793         soc_block_list[4],
  72794         soc_genreg,
  72795         4,
  72796         0,
  72797         0x3080004,
  72798         SOC_REG_FLAG_ARRAY,
  72799         0,
  72800         1,
  72801         soc_OP_BUFFER_SHARED_LIMIT_CELL_BCM56840_A0r_fields,
  72802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72803         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72804         -1,
  72805         -1,
  72806     },
  72807 #endif /* chips */
  72808 
  72809 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  72810     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  72811     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  72812     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  72813     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  72814     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_PACKETr */
  72815         soc_block_list[4],
  72816         soc_genreg,
  72817         1,
  72818         0,
  72819         0x3080001,
  72820         0,
  72821         0,
  72822         1,
  72823         soc_OP_BUFFER_SHARED_LIMIT_PACKETr_fields,
  72824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72825         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72826         -1,
  72827         -1,
  72828     },
  72829 #endif /* chips */
  72830 
  72831 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  72832     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_PACKET_BCM56334_A0r */
  72833         soc_block_list[4],
  72834         soc_genreg,
  72835         1,
  72836         0,
  72837         0x3080001,
  72838         0,
  72839         0,
  72840         1,
  72841         soc_OP_BUFFER_SHARED_LIMIT_PACKET_BCM56334_A0r_fields,
  72842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72843         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  72844         -1,
  72845         -1,
  72846     },
  72847 #endif /* chips */
  72848 
  72849 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72850     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_QENTRYr */
  72851         soc_block_list[4],
  72852         soc_genreg,
  72853         1,
  72854         0,
  72855         0x3080002,
  72856         0,
  72857         0,
  72858         1,
  72859         soc_OP_BUFFER_SHARED_LIMIT_QENTRYr_fields,
  72860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72861         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72862         -1,
  72863         -1,
  72864     },
  72865 #endif /* chips */
  72866 
  72867 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  72868     defined(BCM_56270_A0)
  72869     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_QENTRY_BCM56260_A0r */
  72870         soc_block_list[4],
  72871         soc_genreg,
  72872         1,
  72873         0,
  72874         0xe000400,
  72875         0,
  72876         0,
  72877         1,
  72878         soc_OP_BUFFER_SHARED_LIMIT_QENTRY_BCM56260_A0r_fields,
  72879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72880         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72881         -1,
  72882         -1,
  72883     },
  72884 #endif /* chips */
  72885 
  72886 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72887     defined(BCM_56450_B1)
  72888     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_QENTRY_BCM56450_A0r */
  72889         soc_block_list[4],
  72890         soc_genreg,
  72891         1,
  72892         0,
  72893         0xe000400,
  72894         0,
  72895         0,
  72896         1,
  72897         soc_OP_BUFFER_SHARED_LIMIT_QENTRY_BCM56450_A0r_fields,
  72898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72899         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72900         -1,
  72901         -1,
  72902     },
  72903 #endif /* chips */
  72904 
  72905 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  72906     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUMEr */
  72907         soc_block_list[4],
  72908         soc_genreg,
  72909         1,
  72910         0,
  72911         0x308000b,
  72912         0,
  72913         0,
  72914         1,
  72915         soc_OP_BUFFER_SHARED_LIMIT_RESUMEr_fields,
  72916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72917         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  72918         -1,
  72919         -1,
  72920     },
  72921 #endif /* chips */
  72922 
  72923 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  72924     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  72925     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  72926     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  72927     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  72928     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELLr */
  72929         soc_block_list[4],
  72930         soc_genreg,
  72931         1,
  72932         0,
  72933         0x3080020,
  72934         0,
  72935         0,
  72936         1,
  72937         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELLr_fields,
  72938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72939         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  72940         -1,
  72941         -1,
  72942     },
  72943 #endif /* chips */
  72944 
  72945 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72946     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELLEr */
  72947         soc_block_list[4],
  72948         soc_genreg,
  72949         1,
  72950         0,
  72951         0x3080081,
  72952         0,
  72953         0,
  72954         1,
  72955         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELLEr_fields,
  72956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72957         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72958         -1,
  72959         -1,
  72960     },
  72961 #endif /* chips */
  72962 
  72963 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72964     defined(BCM_56450_B1)
  72965     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r */
  72966         soc_block_list[4],
  72967         soc_genreg,
  72968         1,
  72969         0,
  72970         0xe008100,
  72971         0,
  72972         0,
  72973         1,
  72974         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r_fields,
  72975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72976         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72977         -1,
  72978         -1,
  72979     },
  72980 #endif /* chips */
  72981 
  72982 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72983     defined(BCM_56450_B1)
  72984     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL1r */
  72985         soc_block_list[4],
  72986         soc_genreg,
  72987         1,
  72988         0,
  72989         0xe008300,
  72990         0,
  72991         0,
  72992         1,
  72993         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r_fields,
  72994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72995         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72996         -1,
  72997         -1,
  72998     },
  72999 #endif /* chips */
  73000 
  73001 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  73002     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0_BCM56260_A0r */
  73003         soc_block_list[4],
  73004         soc_genreg,
  73005         1,
  73006         0,
  73007         0xe008100,
  73008         0,
  73009         0,
  73010         1,
  73011         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0_BCM56260_A0r_fields,
  73012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73013         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  73014         -1,
  73015         -1,
  73016     },
  73017 #endif /* chips */
  73018 
  73019 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  73020     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL1_BCM56260_A0r */
  73021         soc_block_list[4],
  73022         soc_genreg,
  73023         1,
  73024         0,
  73025         0xe008300,
  73026         0,
  73027         0,
  73028         1,
  73029         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0_BCM56260_A0r_fields,
  73030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73031         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  73032         -1,
  73033         -1,
  73034     },
  73035 #endif /* chips */
  73036 
  73037 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73038     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr */
  73039         soc_block_list[4],
  73040         soc_genreg,
  73041         1,
  73042         0,
  73043         0x3080080,
  73044         0,
  73045         0,
  73046         1,
  73047         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr_fields,
  73048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73049         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73050         -1,
  73051         -1,
  73052     },
  73053 #endif /* chips */
  73054 
  73055 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  73056     defined(BCM_56270_A0)
  73057     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELLI_BCM56260_A0r */
  73058         soc_block_list[4],
  73059         soc_genreg,
  73060         1,
  73061         0,
  73062         0xe008000,
  73063         0,
  73064         0,
  73065         1,
  73066         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELLI_BCM56260_A0r_fields,
  73067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73068         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73069         -1,
  73070         -1,
  73071     },
  73072 #endif /* chips */
  73073 
  73074 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73075     defined(BCM_56450_B1)
  73076     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELLI_BCM56450_A0r */
  73077         soc_block_list[4],
  73078         soc_genreg,
  73079         1,
  73080         0,
  73081         0xe008000,
  73082         0,
  73083         0,
  73084         1,
  73085         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELLI_BCM56450_A0r_fields,
  73086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73087         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73088         -1,
  73089         -1,
  73090     },
  73091 #endif /* chips */
  73092 
  73093 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  73094     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELL_BCM56334_A0r */
  73095         soc_block_list[4],
  73096         soc_genreg,
  73097         1,
  73098         0,
  73099         0x3080020,
  73100         0,
  73101         0,
  73102         1,
  73103         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELL_BCM56334_A0r_fields,
  73104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73105         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73106         -1,
  73107         -1,
  73108     },
  73109 #endif /* chips */
  73110 
  73111 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  73112     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELL_BCM56640_A0r */
  73113         soc_block_list[4],
  73114         soc_genreg,
  73115         4,
  73116         0,
  73117         0xe008000,
  73118         SOC_REG_FLAG_ARRAY,
  73119         0,
  73120         1,
  73121         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELL_BCM56640_A0r_fields,
  73122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73123         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  73124         -1,
  73125         -1,
  73126     },
  73127 #endif /* chips */
  73128 
  73129 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  73130     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_CELL_BCM56840_A0r */
  73131         soc_block_list[4],
  73132         soc_genreg,
  73133         4,
  73134         0,
  73135         0x3080080,
  73136         SOC_REG_FLAG_ARRAY,
  73137         0,
  73138         1,
  73139         soc_OP_BUFFER_SHARED_LIMIT_RESUME_CELL_BCM56840_A0r_fields,
  73140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73141         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  73142         -1,
  73143         -1,
  73144     },
  73145 #endif /* chips */
  73146 
  73147 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  73148     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  73149     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  73150     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  73151     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  73152     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_PACKETr */
  73153         soc_block_list[4],
  73154         soc_genreg,
  73155         1,
  73156         0,
  73157         0x3080021,
  73158         0,
  73159         0,
  73160         1,
  73161         soc_OP_BUFFER_SHARED_LIMIT_RESUME_PACKETr_fields,
  73162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73163         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73164         -1,
  73165         -1,
  73166     },
  73167 #endif /* chips */
  73168 
  73169 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  73170     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_PACKET_BCM56334_A0r */
  73171         soc_block_list[4],
  73172         soc_genreg,
  73173         1,
  73174         0,
  73175         0x3080021,
  73176         0,
  73177         0,
  73178         1,
  73179         soc_OP_BUFFER_SHARED_LIMIT_RESUME_PACKET_BCM56334_A0r_fields,
  73180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73181         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  73182         -1,
  73183         -1,
  73184     },
  73185 #endif /* chips */
  73186 
  73187 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73188     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr */
  73189         soc_block_list[4],
  73190         soc_genreg,
  73191         1,
  73192         0,
  73193         0x3080082,
  73194         0,
  73195         0,
  73196         1,
  73197         soc_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr_fields,
  73198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73199         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  73200         -1,
  73201         -1,
  73202     },
  73203 #endif /* chips */
  73204 
  73205 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  73206     defined(BCM_56270_A0)
  73207     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY_BCM56260_A0r */
  73208         soc_block_list[4],
  73209         soc_genreg,
  73210         1,
  73211         0,
  73212         0xe008400,
  73213         0,
  73214         0,
  73215         1,
  73216         soc_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY_BCM56260_A0r_fields,
  73217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73218         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  73219         -1,
  73220         -1,
  73221     },
  73222 #endif /* chips */
  73223 
  73224 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73225     defined(BCM_56450_B1)
  73226     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY_BCM56450_A0r */
  73227         soc_block_list[4],
  73228         soc_genreg,
  73229         1,
  73230         0,
  73231         0xe008400,
  73232         0,
  73233         0,
  73234         1,
  73235         soc_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY_BCM56450_A0r_fields,
  73236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73237         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  73238         -1,
  73239         -1,
  73240     },
  73241 #endif /* chips */
  73242 
  73243 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73244     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr */
  73245         soc_block_list[4],
  73246         soc_genreg,
  73247         1,
  73248         0,
  73249         0x2e080004,
  73250         0,
  73251         0,
  73252         1,
  73253         soc_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr_fields,
  73254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73255         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73256         -1,
  73257         -1,
  73258     },
  73259 #endif /* chips */
  73260 
  73261 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  73262     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMA_BCM56260_A0r */
  73263         soc_block_list[4],
  73264         soc_genreg,
  73265         1,
  73266         0,
  73267         0xba000400,
  73268         0,
  73269         0,
  73270         1,
  73271         soc_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMA_BCM56260_A0r_fields,
  73272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73273         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  73274         -1,
  73275         -1,
  73276     },
  73277 #endif /* chips */
  73278 
  73279 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73280     defined(BCM_56450_B1)
  73281     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMA_BCM56450_A0r */
  73282         soc_block_list[4],
  73283         soc_genreg,
  73284         1,
  73285         0,
  73286         0xba000400,
  73287         0,
  73288         0,
  73289         1,
  73290         soc_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMA_BCM56450_A0r_fields,
  73291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73292         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73293         -1,
  73294         -1,
  73295     },
  73296 #endif /* chips */
  73297 
  73298 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73299     defined(BCM_56450_B1)
  73300     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr */
  73301         soc_block_list[4],
  73302         soc_genreg,
  73303         1,
  73304         0,
  73305         0xca000400,
  73306         0,
  73307         0,
  73308         1,
  73309         soc_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr_fields,
  73310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73311         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  73312         -1,
  73313         -1,
  73314     },
  73315 #endif /* chips */
  73316 
  73317 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  73318     defined(BCM_56270_A0)
  73319     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQ_BCM56260_A0r */
  73320         soc_block_list[4],
  73321         soc_genreg,
  73322         1,
  73323         0,
  73324         0xca000400,
  73325         0,
  73326         0,
  73327         1,
  73328         soc_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQ_BCM56260_A0r_fields,
  73329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73330         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  73331         -1,
  73332         -1,
  73333     },
  73334 #endif /* chips */
  73335 
  73336 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73337     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr */
  73338         soc_block_list[4],
  73339         soc_genreg,
  73340         1,
  73341         0,
  73342         0x2d080004,
  73343         0,
  73344         0,
  73345         1,
  73346         soc_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr_fields,
  73347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73348         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  73349         -1,
  73350         -1,
  73351     },
  73352 #endif /* chips */
  73353 
  73354 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  73355     defined(BCM_56270_A0)
  73356     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQ_BCM56260_A0r */
  73357         soc_block_list[4],
  73358         soc_genreg,
  73359         1,
  73360         0,
  73361         0xb6000400,
  73362         0,
  73363         0,
  73364         1,
  73365         soc_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQ_BCM56260_A0r_fields,
  73366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73367         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  73368         -1,
  73369         -1,
  73370     },
  73371 #endif /* chips */
  73372 
  73373 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73374     defined(BCM_56450_B1)
  73375     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQ_BCM56450_A0r */
  73376         soc_block_list[4],
  73377         soc_genreg,
  73378         1,
  73379         0,
  73380         0xb6000400,
  73381         0,
  73382         0,
  73383         1,
  73384         soc_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQ_BCM56450_A0r_fields,
  73385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73386         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  73387         -1,
  73388         -1,
  73389     },
  73390 #endif /* chips */
  73391 
  73392 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73393     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_THDOEMAr */
  73394         soc_block_list[4],
  73395         soc_genreg,
  73396         1,
  73397         0,
  73398         0x2e080000,
  73399         0,
  73400         0,
  73401         1,
  73402         soc_OP_BUFFER_SHARED_LIMITr_fields,
  73403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73404         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73405         -1,
  73406         -1,
  73407     },
  73408 #endif /* chips */
  73409 
  73410 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  73411     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_THDOEMA_BCM56260_A0r */
  73412         soc_block_list[4],
  73413         soc_genreg,
  73414         1,
  73415         0,
  73416         0xba000000,
  73417         0,
  73418         0,
  73419         1,
  73420         soc_OP_BUFFER_SHARED_LIMIT_THDOEMA_BCM56260_A0r_fields,
  73421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73422         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  73423         -1,
  73424         -1,
  73425     },
  73426 #endif /* chips */
  73427 
  73428 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73429     defined(BCM_56450_B1)
  73430     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_THDOEMA_BCM56450_A0r */
  73431         soc_block_list[4],
  73432         soc_genreg,
  73433         1,
  73434         0,
  73435         0xba000000,
  73436         0,
  73437         0,
  73438         1,
  73439         soc_OP_BUFFER_SHARED_LIMIT_THDOEMAr_fields,
  73440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73441         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73442         -1,
  73443         -1,
  73444     },
  73445 #endif /* chips */
  73446 
  73447 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73448     defined(BCM_56450_B1)
  73449     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_THDORDEQr */
  73450         soc_block_list[4],
  73451         soc_genreg,
  73452         1,
  73453         0,
  73454         0xca000000,
  73455         0,
  73456         0,
  73457         1,
  73458         soc_OP_BUFFER_SHARED_LIMIT_THDORDEQr_fields,
  73459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73460         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  73461         -1,
  73462         -1,
  73463     },
  73464 #endif /* chips */
  73465 
  73466 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  73467     defined(BCM_56270_A0)
  73468     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_THDORDEQ_BCM56260_A0r */
  73469         soc_block_list[4],
  73470         soc_genreg,
  73471         1,
  73472         0,
  73473         0xca000000,
  73474         0,
  73475         0,
  73476         1,
  73477         soc_OP_BUFFER_SHARED_LIMIT_THDORDEQ_BCM56260_A0r_fields,
  73478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73479         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  73480         -1,
  73481         -1,
  73482     },
  73483 #endif /* chips */
  73484 
  73485 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73486     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_THDORQEQr */
  73487         soc_block_list[4],
  73488         soc_genreg,
  73489         1,
  73490         0,
  73491         0x2d080000,
  73492         0,
  73493         0,
  73494         1,
  73495         soc_OP_BUFFER_SHARED_LIMIT_THDORQEQr_fields,
  73496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73497         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  73498         -1,
  73499         -1,
  73500     },
  73501 #endif /* chips */
  73502 
  73503 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  73504     defined(BCM_56270_A0)
  73505     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_THDORQEQ_BCM56260_A0r */
  73506         soc_block_list[4],
  73507         soc_genreg,
  73508         1,
  73509         0,
  73510         0xb6000000,
  73511         0,
  73512         0,
  73513         1,
  73514         soc_OP_BUFFER_SHARED_LIMIT_THDORQEQ_BCM56260_A0r_fields,
  73515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73516         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  73517         -1,
  73518         -1,
  73519     },
  73520 #endif /* chips */
  73521 
  73522 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73523     defined(BCM_56450_B1)
  73524     { /* SOC_REG_INT_OP_BUFFER_SHARED_LIMIT_THDORQEQ_BCM56450_A0r */
  73525         soc_block_list[4],
  73526         soc_genreg,
  73527         1,
  73528         0,
  73529         0xb6000000,
  73530         0,
  73531         0,
  73532         1,
  73533         soc_OP_BUFFER_SHARED_LIMIT_THDORQEQ_BCM56450_A0r_fields,
  73534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73535         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  73536         -1,
  73537         -1,
  73538     },
  73539 #endif /* chips */
  73540 
  73541 #if defined(BCM_56800_A0)
  73542     { /* SOC_REG_INT_OP_BUFFER_TOTAL_COUNTr */
  73543         soc_block_list[4],
  73544         soc_genreg,
  73545         1,
  73546         0,
  73547         0x3080021,
  73548         SOC_REG_FLAG_RO,
  73549         0,
  73550         1,
  73551         soc_OP_BUFFER_TOTAL_COUNTr_fields,
  73552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73553         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73554         -1,
  73555         -1,
  73556     },
  73557 #endif /* chips */
  73558 
  73559 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  73560     { /* SOC_REG_INT_OP_BUFFER_TOTAL_COUNT_BCM56820_A0r */
  73561         soc_block_list[4],
  73562         soc_genreg,
  73563         1,
  73564         0,
  73565         0x3080006,
  73566         SOC_REG_FLAG_RO,
  73567         0,
  73568         1,
  73569         soc_OP_BUFFER_TOTAL_COUNTr_fields,
  73570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73571         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73572         -1,
  73573         -1,
  73574     },
  73575 #endif /* chips */
  73576 
  73577 #if defined(BCM_88732_A0)
  73578     { /* SOC_REG_INT_OP_BUFFER_TOTAL_COUNT_BCM88732_A0r */
  73579         soc_block_list[4],
  73580         soc_genreg,
  73581         1,
  73582         0,
  73583         0x3080006,
  73584         SOC_REG_FLAG_RO,
  73585         0,
  73586         1,
  73587         soc_OP_BUFFER_TOTAL_COUNT_BCM88732_A0r_fields,
  73588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73589         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  73590         -1,
  73591         -1,
  73592     },
  73593 #endif /* chips */
  73594 
  73595 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  73596     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  73597     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  73598     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  73599     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  73600     { /* SOC_REG_INT_OP_BUFFER_TOTAL_COUNT_CELLr */
  73601         soc_block_list[4],
  73602         soc_genreg,
  73603         1,
  73604         0,
  73605         0x3080010,
  73606         SOC_REG_FLAG_RO,
  73607         0,
  73608         1,
  73609         soc_OP_BUFFER_TOTAL_COUNT_CELLr_fields,
  73610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73611         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  73612         -1,
  73613         -1,
  73614     },
  73615 #endif /* chips */
  73616 
  73617 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  73618     { /* SOC_REG_INT_OP_BUFFER_TOTAL_COUNT_CELL_BCM56334_A0r */
  73619         soc_block_list[4],
  73620         soc_genreg,
  73621         1,
  73622         0,
  73623         0x3080010,
  73624         SOC_REG_FLAG_RO,
  73625         0,
  73626         1,
  73627         soc_OP_BUFFER_TOTAL_COUNT_CELL_BCM56334_A0r_fields,
  73628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73629         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73630         -1,
  73631         -1,
  73632     },
  73633 #endif /* chips */
  73634 
  73635 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  73636     { /* SOC_REG_INT_OP_BUFFER_TOTAL_COUNT_CELL_BCM56640_A0r */
  73637         soc_block_list[4],
  73638         soc_genreg,
  73639         4,
  73640         0,
  73641         0xe004400,
  73642         SOC_REG_FLAG_ARRAY |
  73643                           SOC_REG_FLAG_RO,
  73644         0,
  73645         1,
  73646         soc_OP_BUFFER_TOTAL_COUNT_CELL_BCM56640_A0r_fields,
  73647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73648         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  73649         -1,
  73650         -1,
  73651     },
  73652 #endif /* chips */
  73653 
  73654 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  73655     { /* SOC_REG_INT_OP_BUFFER_TOTAL_COUNT_CELL_BCM56840_A0r */
  73656         soc_block_list[4],
  73657         soc_genreg,
  73658         4,
  73659         0,
  73660         0x3080044,
  73661         SOC_REG_FLAG_ARRAY |
  73662                           SOC_REG_FLAG_RO,
  73663         0,
  73664         1,
  73665         soc_OP_BUFFER_TOTAL_COUNT_CELL_BCM56840_A0r_fields,
  73666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73667         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  73668         -1,
  73669         -1,
  73670     },
  73671 #endif /* chips */
  73672 
  73673 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  73674     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  73675     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  73676     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  73677     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  73678     { /* SOC_REG_INT_OP_BUFFER_TOTAL_COUNT_PACKETr */
  73679         soc_block_list[4],
  73680         soc_genreg,
  73681         1,
  73682         0,
  73683         0x3080011,
  73684         SOC_REG_FLAG_RO,
  73685         0,
  73686         1,
  73687         soc_OP_BUFFER_TOTAL_COUNT_PACKETr_fields,
  73688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73689         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  73690         -1,
  73691         -1,
  73692     },
  73693 #endif /* chips */
  73694 
  73695 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  73696     { /* SOC_REG_INT_OP_BUFFER_TOTAL_COUNT_PACKET_BCM56334_A0r */
  73697         soc_block_list[4],
  73698         soc_genreg,
  73699         1,
  73700         0,
  73701         0x3080011,
  73702         SOC_REG_FLAG_RO,
  73703         0,
  73704         1,
  73705         soc_OP_BUFFER_TOTAL_COUNT_PACKET_BCM56334_A0r_fields,
  73706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73707         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  73708         -1,
  73709         -1,
  73710     },
  73711 #endif /* chips */
  73712 
  73713 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  73714     { /* SOC_REG_INT_OP_CPU_QUEUE_BST_STATr */
  73715         soc_block_list[4],
  73716         soc_portreg,
  73717         48,
  73718         0,
  73719         0xc048000,
  73720         SOC_REG_FLAG_ARRAY,
  73721         0,
  73722         1,
  73723         soc_OP_CPU_QUEUE_BST_STATr_fields,
  73724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73725         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  73726         -1,
  73727         66,
  73728     },
  73729 #endif /* chips */
  73730 
  73731 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  73732     { /* SOC_REG_INT_OP_CPU_QUEUE_BST_THRESHOLDr */
  73733         soc_block_list[4],
  73734         soc_portreg,
  73735         48,
  73736         0,
  73737         0xc04c000,
  73738         SOC_REG_FLAG_ARRAY,
  73739         0,
  73740         2,
  73741         soc_OP_CPU_QUEUE_BST_THRESHOLDr_fields,
  73742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73743         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  73744         -1,
  73745         66,
  73746     },
  73747 #endif /* chips */
  73748 
  73749 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  73750     { /* SOC_REG_INT_OP_CPU_QUEUE_BST_THRESHOLD_PROFILEr */
  73751         soc_block_list[4],
  73752         soc_genreg,
  73753         8,
  73754         0,
  73755         0xe050000,
  73756         SOC_REG_FLAG_ARRAY,
  73757         0,
  73758         2,
  73759         soc_OP_CPU_QUEUE_BST_THRESHOLD_PROFILEr_fields,
  73760         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  73761         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  73762         -1,
  73763         -1,
  73764     },
  73765 #endif /* chips */
  73766 
  73767 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  73768     { /* SOC_REG_INT_OP_CPU_QUEUE_BST_TRIGGERr */
  73769         soc_block_list[4],
  73770         soc_genreg,
  73771         1,
  73772         0,
  73773         0xe052000,
  73774         0,
  73775         0,
  73776         1,
  73777         soc_OP_CPU_QUEUE_BST_TRIGGERr_fields,
  73778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73779         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  73780         -1,
  73781         -1,
  73782     },
  73783 #endif /* chips */
  73784 
  73785 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73786     { /* SOC_REG_INT_OP_E2ECC_PORT_CONFIGr */
  73787         soc_block_list[4],
  73788         soc_portreg,
  73789         1,
  73790         0,
  73791         0x3000090,
  73792         0,
  73793         0,
  73794         4,
  73795         soc_OP_E2ECC_PORT_CONFIGr_fields,
  73796         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  73797         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  73798         -1,
  73799         55,
  73800     },
  73801 #endif /* chips */
  73802 
  73803 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  73804     { /* SOC_REG_INT_OP_E2ECC_PORT_CONFIG_BCM56260_A0r */
  73805         soc_block_list[4],
  73806         soc_portreg,
  73807         1,
  73808         0,
  73809         0xc009000,
  73810         0,
  73811         0,
  73812         4,
  73813         soc_OP_E2ECC_PORT_CONFIG_BCM56260_A0r_fields,
  73814         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  73815         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  73816         -1,
  73817         89,
  73818     },
  73819 #endif /* chips */
  73820 
  73821 #if defined(BCM_56270_A0)
  73822     { /* SOC_REG_INT_OP_E2ECC_PORT_CONFIG_BCM56270_A0r */
  73823         soc_block_list[4],
  73824         soc_portreg,
  73825         1,
  73826         0,
  73827         0xc009000,
  73828         0,
  73829         0,
  73830         4,
  73831         soc_OP_E2ECC_PORT_CONFIG_BCM56270_A0r_fields,
  73832         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  73833         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  73834         -1,
  73835         96,
  73836     },
  73837 #endif /* chips */
  73838 
  73839 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73840     defined(BCM_56450_B1)
  73841     { /* SOC_REG_INT_OP_E2ECC_PORT_CONFIG_BCM56450_A0r */
  73842         soc_block_list[4],
  73843         soc_portreg,
  73844         1,
  73845         0,
  73846         0xc009000,
  73847         0,
  73848         0,
  73849         4,
  73850         soc_OP_E2ECC_PORT_CONFIG_BCM56450_A0r_fields,
  73851         SOC_RESET_VAL_DEC(0x00001000, 0x00000000)
  73852         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  73853         -1,
  73854         78,
  73855     },
  73856 #endif /* chips */
  73857 
  73858 #if defined(BCM_88732_A0)
  73859     { /* SOC_REG_INT_OP_EP_PORT_MAPPING_TABLE_0r */
  73860         soc_block_list[4],
  73861         soc_genreg,
  73862         1,
  73863         0,
  73864         0xe080042,
  73865         0,
  73866         0,
  73867         6,
  73868         soc_FC_DST_PORT_MAPPING_TABLE_0r_fields,
  73869         SOC_RESET_VAL_DEC(0x0c520c41, 0x00000000)
  73870         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  73871         -1,
  73872         -1,
  73873     },
  73874 #endif /* chips */
  73875 
  73876 #if defined(BCM_88732_A0)
  73877     { /* SOC_REG_INT_OP_EP_PORT_MAPPING_TABLE_1r */
  73878         soc_block_list[4],
  73879         soc_genreg,
  73880         1,
  73881         0,
  73882         0xe080043,
  73883         0,
  73884         0,
  73885         6,
  73886         soc_FC_DST_PORT_MAPPING_TABLE_1r_fields,
  73887         SOC_RESET_VAL_DEC(0x18b52507, 0x00000000)
  73888         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  73889         -1,
  73890         -1,
  73891     },
  73892 #endif /* chips */
  73893 
  73894 #if defined(BCM_88732_A0)
  73895     { /* SOC_REG_INT_OP_EP_PORT_MAPPING_TABLE_2r */
  73896         soc_block_list[4],
  73897         soc_genreg,
  73898         1,
  73899         0,
  73900         0xe080044,
  73901         0,
  73902         0,
  73903         4,
  73904         soc_FC_DST_PORT_MAPPING_TABLE_2r_fields,
  73905         SOC_RESET_VAL_DEC(0x00083dcd, 0x00000000)
  73906         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  73907         -1,
  73908         -1,
  73909     },
  73910 #endif /* chips */
  73911 
  73912 #if defined(BCM_56840_B0)
  73913     { /* SOC_REG_INT_OP_EX_PORT_CONFIG_COS_MIN_0r */
  73914         soc_block_list[4],
  73915         soc_portreg,
  73916         1,
  73917         0,
  73918         0x3000035,
  73919         0,
  73920         0,
  73921         32,
  73922         soc_OP_EX_PORT_CONFIG_COS_MIN_0r_fields,
  73923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73925         -1,
  73926         36,
  73927     },
  73928 #endif /* chips */
  73929 
  73930 #if defined(BCM_56840_B0)
  73931     { /* SOC_REG_INT_OP_EX_PORT_CONFIG_COS_MIN_1r */
  73932         soc_block_list[4],
  73933         soc_portreg,
  73934         1,
  73935         0,
  73936         0x3000036,
  73937         0,
  73938         0,
  73939         32,
  73940         soc_OP_EX_PORT_CONFIG_COS_MIN_1r_fields,
  73941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73943         -1,
  73944         36,
  73945     },
  73946 #endif /* chips */
  73947 
  73948 #if defined(BCM_56840_B0)
  73949     { /* SOC_REG_INT_OP_EX_PORT_CONFIG_COS_MIN_2r */
  73950         soc_block_list[4],
  73951         soc_portreg,
  73952         1,
  73953         0,
  73954         0x3000037,
  73955         0,
  73956         0,
  73957         10,
  73958         soc_OP_EX_PORT_CONFIG_COS_MIN_2r_fields,
  73959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73960         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  73961         -1,
  73962         36,
  73963     },
  73964 #endif /* chips */
  73965 
  73966 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  73967     { /* SOC_REG_INT_OP_EX_PORT_CONFIG_SPID_0r */
  73968         soc_block_list[4],
  73969         soc_portreg,
  73970         1,
  73971         0,
  73972         0x300002c,
  73973         0,
  73974         0,
  73975         16,
  73976         soc_OP_EX_PORT_CONFIG_SPID_0r_fields,
  73977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73978         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73979         -1,
  73980         36,
  73981     },
  73982 #endif /* chips */
  73983 
  73984 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  73985     { /* SOC_REG_INT_OP_EX_PORT_CONFIG_SPID_1r */
  73986         soc_block_list[4],
  73987         soc_portreg,
  73988         1,
  73989         0,
  73990         0x300002d,
  73991         0,
  73992         0,
  73993         16,
  73994         soc_OP_EX_PORT_CONFIG_SPID_1r_fields,
  73995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73997         -1,
  73998         36,
  73999     },
  74000 #endif /* chips */
  74001 
  74002 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74003     { /* SOC_REG_INT_OP_EX_PORT_CONFIG_SPID_2r */
  74004         soc_block_list[4],
  74005         soc_portreg,
  74006         1,
  74007         0,
  74008         0x3000030,
  74009         0,
  74010         0,
  74011         16,
  74012         soc_OP_EX_PORT_CONFIG_SPID_2r_fields,
  74013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74014         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74015         -1,
  74016         36,
  74017     },
  74018 #endif /* chips */
  74019 
  74020 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74021     { /* SOC_REG_INT_OP_EX_PORT_CONFIG_SPID_3r */
  74022         soc_block_list[4],
  74023         soc_portreg,
  74024         1,
  74025         0,
  74026         0x3000032,
  74027         0,
  74028         0,
  74029         16,
  74030         soc_OP_EX_PORT_CONFIG_SPID_3r_fields,
  74031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74032         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74033         -1,
  74034         36,
  74035     },
  74036 #endif /* chips */
  74037 
  74038 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74039     { /* SOC_REG_INT_OP_EX_PORT_CONFIG_SPID_4r */
  74040         soc_block_list[4],
  74041         soc_portreg,
  74042         1,
  74043         0,
  74044         0x3000034,
  74045         0,
  74046         0,
  74047         10,
  74048         soc_OP_EX_PORT_CONFIG_SPID_4r_fields,
  74049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74050         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  74051         -1,
  74052         36,
  74053     },
  74054 #endif /* chips */
  74055 
  74056 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74057     { /* SOC_REG_INT_OP_EX_QUEUE_MIN_COUNT_CELLr */
  74058         soc_block_list[4],
  74059         soc_portreg,
  74060         74,
  74061         0,
  74062         0x3000800,
  74063         SOC_REG_FLAG_ARRAY |
  74064                           SOC_REG_FLAG_RO,
  74065         0,
  74066         1,
  74067         soc_OP_EX_QUEUE_MIN_COUNT_CELLr_fields,
  74068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74069         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74070         -1,
  74071         43,
  74072     },
  74073 #endif /* chips */
  74074 
  74075 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74076     { /* SOC_REG_INT_OP_EX_QUEUE_RESET_VALUE_CELLr */
  74077         soc_block_list[4],
  74078         soc_portreg,
  74079         74,
  74080         0,
  74081         0x3000b00,
  74082         SOC_REG_FLAG_ARRAY |
  74083                           SOC_REG_FLAG_RO,
  74084         0,
  74085         4,
  74086         soc_OP_EX_QUEUE_RESET_VALUE_CELLr_fields,
  74087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74088         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  74089         -1,
  74090         43,
  74091     },
  74092 #endif /* chips */
  74093 
  74094 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74095     { /* SOC_REG_INT_OP_EX_QUEUE_SHARED_COUNT_CELLr */
  74096         soc_block_list[4],
  74097         soc_portreg,
  74098         74,
  74099         0,
  74100         0x3000900,
  74101         SOC_REG_FLAG_ARRAY |
  74102                           SOC_REG_FLAG_RO,
  74103         0,
  74104         1,
  74105         soc_OP_EX_QUEUE_SHARED_COUNT_CELLr_fields,
  74106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74107         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74108         -1,
  74109         43,
  74110     },
  74111 #endif /* chips */
  74112 
  74113 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74114     { /* SOC_REG_INT_OP_EX_QUEUE_TOTAL_COUNT_CELLr */
  74115         soc_block_list[4],
  74116         soc_portreg,
  74117         74,
  74118         0,
  74119         0x3000a00,
  74120         SOC_REG_FLAG_ARRAY |
  74121                           SOC_REG_FLAG_RO,
  74122         0,
  74123         1,
  74124         soc_OP_EX_QUEUE_TOTAL_COUNT_CELLr_fields,
  74125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74126         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74127         -1,
  74128         43,
  74129     },
  74130 #endif /* chips */
  74131 
  74132 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  74133     { /* SOC_REG_INT_OP_MCUC_SP_BST_STATr */
  74134         soc_block_list[4],
  74135         soc_genreg,
  74136         4,
  74137         0,
  74138         0xe063c00,
  74139         SOC_REG_FLAG_ARRAY,
  74140         0,
  74141         1,
  74142         soc_OP_CPU_QUEUE_BST_STATr_fields,
  74143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74144         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  74145         -1,
  74146         -1,
  74147     },
  74148 #endif /* chips */
  74149 
  74150 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  74151     { /* SOC_REG_INT_OP_MCUC_SP_BST_THRESHOLDr */
  74152         soc_block_list[4],
  74153         soc_genreg,
  74154         4,
  74155         0,
  74156         0xe063800,
  74157         SOC_REG_FLAG_ARRAY,
  74158         0,
  74159         2,
  74160         soc_OP_MCUC_SP_BST_THRESHOLDr_fields,
  74161         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  74162         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  74163         -1,
  74164         -1,
  74165     },
  74166 #endif /* chips */
  74167 
  74168 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  74169     { /* SOC_REG_INT_OP_MC_SP_BST_STATr */
  74170         soc_block_list[4],
  74171         soc_genreg,
  74172         4,
  74173         0,
  74174         0xe064400,
  74175         SOC_REG_FLAG_ARRAY,
  74176         0,
  74177         1,
  74178         soc_OP_CPU_QUEUE_BST_STATr_fields,
  74179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74180         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  74181         -1,
  74182         -1,
  74183     },
  74184 #endif /* chips */
  74185 
  74186 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  74187     { /* SOC_REG_INT_OP_MC_SP_BST_THRESHOLDr */
  74188         soc_block_list[4],
  74189         soc_genreg,
  74190         4,
  74191         0,
  74192         0xe064000,
  74193         SOC_REG_FLAG_ARRAY,
  74194         0,
  74195         2,
  74196         soc_OP_MCUC_SP_BST_THRESHOLDr_fields,
  74197         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  74198         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  74199         -1,
  74200         -1,
  74201     },
  74202 #endif /* chips */
  74203 
  74204 #if defined(BCM_56800_A0)
  74205     { /* SOC_REG_INT_OP_PORT_CONFIGr */
  74206         soc_block_list[4],
  74207         soc_portreg,
  74208         1,
  74209         0,
  74210         0x3000003,
  74211         0,
  74212         0,
  74213         3,
  74214         soc_OP_PORT_CONFIGr_fields,
  74215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74216         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  74217         -1,
  74218         -1,
  74219     },
  74220 #endif /* chips */
  74221 
  74222 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74223     { /* SOC_REG_INT_OP_PORT_CONFIG1_CELLr */
  74224         soc_block_list[4],
  74225         soc_portreg,
  74226         1,
  74227         0,
  74228         0x3000028,
  74229         0,
  74230         0,
  74231         1,
  74232         soc_OP_PORT_CONFIG1_CELLr_fields,
  74233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74234         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  74235         -1,
  74236         -1,
  74237     },
  74238 #endif /* chips */
  74239 
  74240 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  74241     { /* SOC_REG_INT_OP_PORT_CONFIG1_CELL_BCM56640_A0r */
  74242         soc_block_list[4],
  74243         soc_portreg,
  74244         1,
  74245         0,
  74246         0xc003000,
  74247         0,
  74248         0,
  74249         1,
  74250         soc_OP_PORT_CONFIG1_CELL_BCM56640_A0r_fields,
  74251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74252         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  74253         -1,
  74254         57,
  74255     },
  74256 #endif /* chips */
  74257 
  74258 #if defined(BCM_88732_A0)
  74259     { /* SOC_REG_INT_OP_PORT_CONFIGLr */
  74260         soc_block_list[4],
  74261         soc_portreg,
  74262         1,
  74263         0,
  74264         0x3000004,
  74265         0,
  74266         0,
  74267         4,
  74268         soc_OP_PORT_CONFIGLr_fields,
  74269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74270         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  74271         -1,
  74272         -1,
  74273     },
  74274 #endif /* chips */
  74275 
  74276 #if defined(BCM_88732_A0)
  74277     { /* SOC_REG_INT_OP_PORT_CONFIGUr */
  74278         soc_block_list[4],
  74279         soc_portreg,
  74280         1,
  74281         0,
  74282         0x3000003,
  74283         0,
  74284         0,
  74285         1,
  74286         soc_OP_PORT_CONFIGUr_fields,
  74287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74288         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  74289         -1,
  74290         -1,
  74291     },
  74292 #endif /* chips */
  74293 
  74294 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  74295     { /* SOC_REG_INT_OP_PORT_CONFIG_BCM56820_A0r */
  74296         soc_block_list[4],
  74297         soc_portreg,
  74298         1,
  74299         0,
  74300         0x3000003,
  74301         0,
  74302         0,
  74303         4,
  74304         soc_OP_PORT_CONFIG_BCM56820_A0r_fields,
  74305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74306         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  74307         -1,
  74308         -1,
  74309     },
  74310 #endif /* chips */
  74311 
  74312 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74313     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74314     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74315     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  74316     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74317     { /* SOC_REG_INT_OP_PORT_CONFIG_CELLr */
  74318         soc_block_list[4],
  74319         soc_portreg,
  74320         1,
  74321         0,
  74322         0x3000008,
  74323         0,
  74324         0,
  74325         4,
  74326         soc_OP_PORT_CONFIG_CELLr_fields,
  74327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74328         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74329         -1,
  74330         -1,
  74331     },
  74332 #endif /* chips */
  74333 
  74334 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  74335     { /* SOC_REG_INT_OP_PORT_CONFIG_CELL_BCM56334_A0r */
  74336         soc_block_list[4],
  74337         soc_portreg,
  74338         1,
  74339         0,
  74340         0x3000008,
  74341         0,
  74342         0,
  74343         4,
  74344         soc_OP_PORT_CONFIG_CELL_BCM56334_A0r_fields,
  74345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74346         SOC_RESET_MASK_DEC(0xdfffbfff, 0x00000000)
  74347         -1,
  74348         -1,
  74349     },
  74350 #endif /* chips */
  74351 
  74352 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  74353     { /* SOC_REG_INT_OP_PORT_CONFIG_CELL_BCM56640_A0r */
  74354         soc_block_list[4],
  74355         soc_portreg,
  74356         4,
  74357         0,
  74358         0xc002800,
  74359         SOC_REG_FLAG_ARRAY,
  74360         0,
  74361         2,
  74362         soc_OP_PORT_CONFIG_CELL_BCM56640_A0r_fields,
  74363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74364         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  74365         -1,
  74366         57,
  74367     },
  74368 #endif /* chips */
  74369 
  74370 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74371     { /* SOC_REG_INT_OP_PORT_CONFIG_CELL_BCM56840_A0r */
  74372         soc_block_list[4],
  74373         soc_portreg,
  74374         4,
  74375         0,
  74376         0x3000020,
  74377         SOC_REG_FLAG_ARRAY,
  74378         0,
  74379         2,
  74380         soc_OP_PORT_CONFIG_CELL_BCM56840_A0r_fields,
  74381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74383         -1,
  74384         -1,
  74385     },
  74386 #endif /* chips */
  74387 
  74388 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74389     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74390     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74391     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  74392     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74393     { /* SOC_REG_INT_OP_PORT_CONFIG_PACKETr */
  74394         soc_block_list[4],
  74395         soc_portreg,
  74396         1,
  74397         0,
  74398         0x3000009,
  74399         0,
  74400         0,
  74401         4,
  74402         soc_OP_PORT_CONFIG_PACKETr_fields,
  74403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74404         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  74405         -1,
  74406         -1,
  74407     },
  74408 #endif /* chips */
  74409 
  74410 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  74411     { /* SOC_REG_INT_OP_PORT_CONFIG_PACKET_BCM56334_A0r */
  74412         soc_block_list[4],
  74413         soc_portreg,
  74414         1,
  74415         0,
  74416         0x3000009,
  74417         0,
  74418         0,
  74419         4,
  74420         soc_OP_PORT_CONFIG_PACKET_BCM56334_A0r_fields,
  74421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74422         SOC_RESET_MASK_DEC(0x37ffdfff, 0x00000000)
  74423         -1,
  74424         -1,
  74425     },
  74426 #endif /* chips */
  74427 
  74428 #if defined(BCM_56800_A0)
  74429     { /* SOC_REG_INT_OP_PORT_DROP_STATE_BMPr */
  74430         soc_block_list[4],
  74431         soc_genreg,
  74432         1,
  74433         0,
  74434         0x3080060,
  74435         SOC_REG_FLAG_RO,
  74436         0,
  74437         1,
  74438         soc_OP_PORT_DROP_STATE_BMPr_fields,
  74439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74440         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  74441         -1,
  74442         -1,
  74443     },
  74444 #endif /* chips */
  74445 
  74446 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  74447     { /* SOC_REG_INT_OP_PORT_DROP_STATE_BMP_BCM56820_A0r */
  74448         soc_block_list[4],
  74449         soc_genreg,
  74450         1,
  74451         0,
  74452         0x3080007,
  74453         SOC_REG_FLAG_RO,
  74454         0,
  74455         1,
  74456         soc_OP_PORT_DROP_STATE_BMP_BCM56820_A0r_fields,
  74457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74458         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  74459         -1,
  74460         -1,
  74461     },
  74462 #endif /* chips */
  74463 
  74464 #if defined(BCM_88732_A0)
  74465     { /* SOC_REG_INT_OP_PORT_DROP_STATE_BMP_BCM88732_A0r */
  74466         soc_block_list[4],
  74467         soc_genreg,
  74468         1,
  74469         0,
  74470         0x3080007,
  74471         SOC_REG_FLAG_RO,
  74472         0,
  74473         1,
  74474         soc_OP_PORT_DROP_STATE_BMP_BCM88732_A0r_fields,
  74475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74476         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  74477         -1,
  74478         -1,
  74479     },
  74480 #endif /* chips */
  74481 
  74482 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74483     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74484     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74485     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  74486     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74487     { /* SOC_REG_INT_OP_PORT_DROP_STATE_CELL_BMP0r */
  74488         soc_block_list[4],
  74489         soc_genreg,
  74490         1,
  74491         0,
  74492         0x3080016,
  74493         SOC_REG_FLAG_RO,
  74494         0,
  74495         1,
  74496         soc_OP_PORT_DROP_STATE_CELL_BMP0r_fields,
  74497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74498         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74499         -1,
  74500         -1,
  74501     },
  74502 #endif /* chips */
  74503 
  74504 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74505     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  74506     { /* SOC_REG_INT_OP_PORT_DROP_STATE_CELL_BMP1r */
  74507         soc_block_list[4],
  74508         soc_genreg,
  74509         1,
  74510         0,
  74511         0x3080017,
  74512         SOC_REG_FLAG_RO,
  74513         0,
  74514         1,
  74515         soc_OP_PORT_DROP_STATE_CELL_BMP1r_fields,
  74516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74517         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  74518         -1,
  74519         -1,
  74520     },
  74521 #endif /* chips */
  74522 
  74523 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74524     { /* SOC_REG_INT_OP_PORT_DROP_STATE_CELL_BMP0_64r */
  74525         soc_block_list[4],
  74526         soc_genreg,
  74527         4,
  74528         0,
  74529         0x3080060,
  74530         SOC_REG_FLAG_64_BITS |
  74531                           SOC_REG_FLAG_ARRAY |
  74532                           SOC_REG_FLAG_RO,
  74533         0,
  74534         1,
  74535         soc_OP_PORT_DROP_STATE_CELL_BMP0_64r_fields,
  74536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  74538         -1,
  74539         -1,
  74540     },
  74541 #endif /* chips */
  74542 
  74543 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  74544     { /* SOC_REG_INT_OP_PORT_DROP_STATE_CELL_BMP0_64_BCM56640_A0r */
  74545         soc_block_list[4],
  74546         soc_genreg,
  74547         4,
  74548         0,
  74549         0xe006000,
  74550         SOC_REG_FLAG_64_BITS |
  74551                           SOC_REG_FLAG_ARRAY |
  74552                           SOC_REG_FLAG_RO,
  74553         0,
  74554         1,
  74555         soc_OP_PORT_DROP_STATE_CELL_BMP0_64_BCM56640_A0r_fields,
  74556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74557         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  74558         -1,
  74559         -1,
  74560     },
  74561 #endif /* chips */
  74562 
  74563 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  74564     { /* SOC_REG_INT_OP_PORT_DROP_STATE_CELL_BMP0_BCM56334_A0r */
  74565         soc_block_list[4],
  74566         soc_genreg,
  74567         1,
  74568         0,
  74569         0x3080016,
  74570         SOC_REG_FLAG_RO,
  74571         0,
  74572         1,
  74573         soc_OP_PORT_DROP_STATE_CELL_BMP0_BCM56334_A0r_fields,
  74574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74575         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  74576         -1,
  74577         -1,
  74578     },
  74579 #endif /* chips */
  74580 
  74581 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74582     { /* SOC_REG_INT_OP_PORT_DROP_STATE_CELL_BMP1_64r */
  74583         soc_block_list[4],
  74584         soc_genreg,
  74585         4,
  74586         0,
  74587         0x3080064,
  74588         SOC_REG_FLAG_64_BITS |
  74589                           SOC_REG_FLAG_ARRAY |
  74590                           SOC_REG_FLAG_RO,
  74591         0,
  74592         1,
  74593         soc_OP_PORT_DROP_STATE_CELL_BMP1_64r_fields,
  74594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  74596         -1,
  74597         -1,
  74598     },
  74599 #endif /* chips */
  74600 
  74601 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74602     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74603     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74604     { /* SOC_REG_INT_OP_PORT_DROP_STATE_CELL_BMP1_BCM56634_A0r */
  74605         soc_block_list[4],
  74606         soc_genreg,
  74607         1,
  74608         0,
  74609         0x3080017,
  74610         SOC_REG_FLAG_RO,
  74611         0,
  74612         1,
  74613         soc_OP_PORT_DROP_STATE_CELL_BMP1_BCM56634_A0r_fields,
  74614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74615         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  74616         -1,
  74617         -1,
  74618     },
  74619 #endif /* chips */
  74620 
  74621 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74622     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74623     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74624     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  74625     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74626     { /* SOC_REG_INT_OP_PORT_DROP_STATE_PACKET_BMP0r */
  74627         soc_block_list[4],
  74628         soc_genreg,
  74629         1,
  74630         0,
  74631         0x3080018,
  74632         SOC_REG_FLAG_RO,
  74633         0,
  74634         1,
  74635         soc_OP_PORT_DROP_STATE_PACKET_BMP0r_fields,
  74636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74637         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74638         -1,
  74639         -1,
  74640     },
  74641 #endif /* chips */
  74642 
  74643 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74644     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  74645     { /* SOC_REG_INT_OP_PORT_DROP_STATE_PACKET_BMP1r */
  74646         soc_block_list[4],
  74647         soc_genreg,
  74648         1,
  74649         0,
  74650         0x3080019,
  74651         SOC_REG_FLAG_RO,
  74652         0,
  74653         1,
  74654         soc_OP_PORT_DROP_STATE_PACKET_BMP1r_fields,
  74655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74656         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  74657         -1,
  74658         -1,
  74659     },
  74660 #endif /* chips */
  74661 
  74662 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  74663     { /* SOC_REG_INT_OP_PORT_DROP_STATE_PACKET_BMP0_BCM56334_A0r */
  74664         soc_block_list[4],
  74665         soc_genreg,
  74666         1,
  74667         0,
  74668         0x3080018,
  74669         SOC_REG_FLAG_RO,
  74670         0,
  74671         1,
  74672         soc_OP_PORT_DROP_STATE_PACKET_BMP0_BCM56334_A0r_fields,
  74673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74674         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  74675         -1,
  74676         -1,
  74677     },
  74678 #endif /* chips */
  74679 
  74680 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74681     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74682     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74683     { /* SOC_REG_INT_OP_PORT_DROP_STATE_PACKET_BMP1_BCM56634_A0r */
  74684         soc_block_list[4],
  74685         soc_genreg,
  74686         1,
  74687         0,
  74688         0x3080019,
  74689         SOC_REG_FLAG_RO,
  74690         0,
  74691         1,
  74692         soc_OP_PORT_DROP_STATE_PACKET_BMP1_BCM56634_A0r_fields,
  74693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74694         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  74695         -1,
  74696         -1,
  74697     },
  74698 #endif /* chips */
  74699 
  74700 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74701     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74702     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74703     { /* SOC_REG_INT_OP_PORT_FIRST_FRAGMENT_COUNT_CELLr */
  74704         soc_block_list[4],
  74705         soc_portreg,
  74706         1,
  74707         0,
  74708         0x30005b4,
  74709         SOC_REG_FLAG_RO,
  74710         0,
  74711         1,
  74712         soc_OP_PORT_FIRST_FRAGMENT_COUNT_CELLr_fields,
  74713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74714         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  74715         -1,
  74716         20,
  74717     },
  74718 #endif /* chips */
  74719 
  74720 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74721     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74722     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74723     { /* SOC_REG_INT_OP_PORT_FIRST_FRAGMENT_COUNT_PACKETr */
  74724         soc_block_list[4],
  74725         soc_portreg,
  74726         1,
  74727         0,
  74728         0x30005b5,
  74729         SOC_REG_FLAG_RO,
  74730         0,
  74731         1,
  74732         soc_OP_PORT_FIRST_FRAGMENT_COUNT_PACKETr_fields,
  74733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74734         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  74735         -1,
  74736         20,
  74737     },
  74738 #endif /* chips */
  74739 
  74740 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74741     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74742     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74743     { /* SOC_REG_INT_OP_PORT_FIRST_FRAGMENT_DISC_RESUME_THD_CELLr */
  74744         soc_block_list[4],
  74745         soc_portreg,
  74746         1,
  74747         0,
  74748         0x30005b1,
  74749         0,
  74750         0,
  74751         1,
  74752         soc_OP_PORT_FIRST_FRAGMENT_DISC_RESUME_THD_CELLr_fields,
  74753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74754         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  74755         -1,
  74756         20,
  74757     },
  74758 #endif /* chips */
  74759 
  74760 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74761     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74762     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74763     { /* SOC_REG_INT_OP_PORT_FIRST_FRAGMENT_DISC_RESUME_THD_PACKETr */
  74764         soc_block_list[4],
  74765         soc_portreg,
  74766         1,
  74767         0,
  74768         0x30005b3,
  74769         0,
  74770         0,
  74771         1,
  74772         soc_OP_PORT_FIRST_FRAGMENT_DISC_RESUME_THD_PACKETr_fields,
  74773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74774         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  74775         -1,
  74776         20,
  74777     },
  74778 #endif /* chips */
  74779 
  74780 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74781     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74782     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74783     { /* SOC_REG_INT_OP_PORT_FIRST_FRAGMENT_DISC_SET_THD_CELLr */
  74784         soc_block_list[4],
  74785         soc_portreg,
  74786         1,
  74787         0,
  74788         0x30005b0,
  74789         0,
  74790         0,
  74791         1,
  74792         soc_OP_PORT_FIRST_FRAGMENT_DISC_SET_THD_CELLr_fields,
  74793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74794         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  74795         -1,
  74796         20,
  74797     },
  74798 #endif /* chips */
  74799 
  74800 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74801     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74802     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74803     { /* SOC_REG_INT_OP_PORT_FIRST_FRAGMENT_DISC_SET_THD_PACKETr */
  74804         soc_block_list[4],
  74805         soc_portreg,
  74806         1,
  74807         0,
  74808         0x30005b2,
  74809         0,
  74810         0,
  74811         1,
  74812         soc_OP_PORT_FIRST_FRAGMENT_DISC_SET_THD_PACKETr_fields,
  74813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74814         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  74815         -1,
  74816         20,
  74817     },
  74818 #endif /* chips */
  74819 
  74820 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  74821     { /* SOC_REG_INT_OP_PORT_LIMIT_COLOR_CELLr */
  74822         soc_block_list[4],
  74823         soc_portreg,
  74824         4,
  74825         0,
  74826         0x3000038,
  74827         SOC_REG_FLAG_ARRAY,
  74828         0,
  74829         1,
  74830         soc_OP_PORT_LIMIT_COLOR_CELLr_fields,
  74831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74832         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74833         -1,
  74834         -1,
  74835     },
  74836 #endif /* chips */
  74837 
  74838 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  74839     { /* SOC_REG_INT_OP_PORT_LIMIT_COLOR_CELL_BCM56640_A0r */
  74840         soc_block_list[4],
  74841         soc_portreg,
  74842         4,
  74843         0,
  74844         0xc003800,
  74845         SOC_REG_FLAG_ARRAY,
  74846         0,
  74847         1,
  74848         soc_OP_PORT_LIMIT_COLOR_CELL_BCM56640_A0r_fields,
  74849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74850         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  74851         -1,
  74852         57,
  74853     },
  74854 #endif /* chips */
  74855 
  74856 #if defined(BCM_88732_A0)
  74857     { /* SOC_REG_INT_OP_PORT_LIMIT_PRI0r */
  74858         soc_block_list[4],
  74859         soc_portreg,
  74860         1,
  74861         0,
  74862         0x30000c4,
  74863         0,
  74864         0,
  74865         1,
  74866         soc_OP_PORT_LIMIT_PRI0r_fields,
  74867         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  74868         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  74869         -1,
  74870         -1,
  74871     },
  74872 #endif /* chips */
  74873 
  74874 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  74875     { /* SOC_REG_INT_OP_PORT_LIMIT_REDr */
  74876         soc_block_list[4],
  74877         soc_portreg,
  74878         1,
  74879         0,
  74880         0x30000c3,
  74881         0,
  74882         0,
  74883         1,
  74884         soc_OP_PORT_LIMIT_REDr_fields,
  74885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74886         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  74887         -1,
  74888         -1,
  74889     },
  74890 #endif /* chips */
  74891 
  74892 #if defined(BCM_88732_A0)
  74893     { /* SOC_REG_INT_OP_PORT_LIMIT_RED_BCM88732_A0r */
  74894         soc_block_list[4],
  74895         soc_portreg,
  74896         1,
  74897         0,
  74898         0x30000c3,
  74899         0,
  74900         0,
  74901         1,
  74902         soc_OP_PORT_LIMIT_RED_BCM88732_A0r_fields,
  74903         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  74904         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  74905         -1,
  74906         -1,
  74907     },
  74908 #endif /* chips */
  74909 
  74910 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74911     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  74912     { /* SOC_REG_INT_OP_PORT_LIMIT_RED_CELLr */
  74913         soc_block_list[4],
  74914         soc_portreg,
  74915         1,
  74916         0,
  74917         0x300000c,
  74918         0,
  74919         0,
  74920         1,
  74921         soc_OP_PORT_LIMIT_RED_CELLr_fields,
  74922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74923         SOC_RESET_MASK_DEC(0x00007ff8, 0x00000000)
  74924         -1,
  74925         -1,
  74926     },
  74927 #endif /* chips */
  74928 
  74929 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  74930     { /* SOC_REG_INT_OP_PORT_LIMIT_RED_CELL_BCM56334_A0r */
  74931         soc_block_list[4],
  74932         soc_portreg,
  74933         1,
  74934         0,
  74935         0x300000c,
  74936         0,
  74937         0,
  74938         1,
  74939         soc_OP_PORT_LIMIT_RED_CELL_BCM56334_A0r_fields,
  74940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74941         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  74942         -1,
  74943         -1,
  74944     },
  74945 #endif /* chips */
  74946 
  74947 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74948     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74949     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74950     { /* SOC_REG_INT_OP_PORT_LIMIT_RED_CELL_BCM56634_A0r */
  74951         soc_block_list[4],
  74952         soc_portreg,
  74953         1,
  74954         0,
  74955         0x300000c,
  74956         0,
  74957         0,
  74958         1,
  74959         soc_OP_PORT_LIMIT_RED_CELL_BCM56634_A0r_fields,
  74960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74961         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  74962         -1,
  74963         -1,
  74964     },
  74965 #endif /* chips */
  74966 
  74967 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74968     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  74969     { /* SOC_REG_INT_OP_PORT_LIMIT_RED_PACKETr */
  74970         soc_block_list[4],
  74971         soc_portreg,
  74972         1,
  74973         0,
  74974         0x300000d,
  74975         0,
  74976         0,
  74977         1,
  74978         soc_OP_PORT_LIMIT_RED_PACKETr_fields,
  74979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74980         SOC_RESET_MASK_DEC(0x00003ffc, 0x00000000)
  74981         -1,
  74982         -1,
  74983     },
  74984 #endif /* chips */
  74985 
  74986 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  74987     { /* SOC_REG_INT_OP_PORT_LIMIT_RED_PACKET_BCM56334_A0r */
  74988         soc_block_list[4],
  74989         soc_portreg,
  74990         1,
  74991         0,
  74992         0x300000d,
  74993         0,
  74994         0,
  74995         1,
  74996         soc_OP_PORT_LIMIT_RED_PACKET_BCM56334_A0r_fields,
  74997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74998         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  74999         -1,
  75000         -1,
  75001     },
  75002 #endif /* chips */
  75003 
  75004 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75005     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75006     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75007     { /* SOC_REG_INT_OP_PORT_LIMIT_RED_PACKET_BCM56634_A0r */
  75008         soc_block_list[4],
  75009         soc_portreg,
  75010         1,
  75011         0,
  75012         0x300000d,
  75013         0,
  75014         0,
  75015         1,
  75016         soc_OP_PORT_LIMIT_RED_PACKET_BCM56634_A0r_fields,
  75017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75018         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  75019         -1,
  75020         -1,
  75021     },
  75022 #endif /* chips */
  75023 
  75024 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  75025     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_COLOR_CELLr */
  75026         soc_block_list[4],
  75027         soc_portreg,
  75028         4,
  75029         0,
  75030         0x3000090,
  75031         SOC_REG_FLAG_ARRAY,
  75032         0,
  75033         1,
  75034         soc_OP_PORT_LIMIT_COLOR_CELLr_fields,
  75035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75036         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  75037         -1,
  75038         -1,
  75039     },
  75040 #endif /* chips */
  75041 
  75042 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  75043     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_COLOR_CELL_BCM56640_A0r */
  75044         soc_block_list[4],
  75045         soc_portreg,
  75046         4,
  75047         0,
  75048         0xc009000,
  75049         SOC_REG_FLAG_ARRAY,
  75050         0,
  75051         1,
  75052         soc_OP_PORT_LIMIT_COLOR_CELL_BCM56640_A0r_fields,
  75053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75054         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  75055         -1,
  75056         57,
  75057     },
  75058 #endif /* chips */
  75059 
  75060 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75061     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75062     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75063     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_RED_CELLr */
  75064         soc_block_list[4],
  75065         soc_portreg,
  75066         1,
  75067         0,
  75068         0x3000028,
  75069         0,
  75070         0,
  75071         1,
  75072         soc_OP_PORT_LIMIT_RESUME_RED_CELLr_fields,
  75073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75074         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  75075         -1,
  75076         -1,
  75077     },
  75078 #endif /* chips */
  75079 
  75080 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75081     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_RED_CELL_BCM56334_A0r */
  75082         soc_block_list[4],
  75083         soc_portreg,
  75084         1,
  75085         0,
  75086         0x3000562,
  75087         0,
  75088         0,
  75089         1,
  75090         soc_OP_PORT_LIMIT_RESUME_RED_CELL_BCM56334_A0r_fields,
  75091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75092         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  75093         -1,
  75094         -1,
  75095     },
  75096 #endif /* chips */
  75097 
  75098 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75099     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75100     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75101     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_RED_PACKETr */
  75102         soc_block_list[4],
  75103         soc_portreg,
  75104         1,
  75105         0,
  75106         0x3000029,
  75107         0,
  75108         0,
  75109         1,
  75110         soc_OP_PORT_LIMIT_RESUME_RED_PACKETr_fields,
  75111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75112         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  75113         -1,
  75114         -1,
  75115     },
  75116 #endif /* chips */
  75117 
  75118 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75119     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_RED_PACKET_BCM56334_A0r */
  75120         soc_block_list[4],
  75121         soc_portreg,
  75122         1,
  75123         0,
  75124         0x3000563,
  75125         0,
  75126         0,
  75127         1,
  75128         soc_OP_PORT_LIMIT_RESUME_RED_PACKET_BCM56334_A0r_fields,
  75129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75130         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  75131         -1,
  75132         -1,
  75133     },
  75134 #endif /* chips */
  75135 
  75136 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75137     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75138     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75139     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_YELLOW_CELLr */
  75140         soc_block_list[4],
  75141         soc_portreg,
  75142         1,
  75143         0,
  75144         0x3000026,
  75145         0,
  75146         0,
  75147         1,
  75148         soc_OP_PORT_LIMIT_RESUME_YELLOW_CELLr_fields,
  75149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75150         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  75151         -1,
  75152         -1,
  75153     },
  75154 #endif /* chips */
  75155 
  75156 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75157     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_YELLOW_CELL_BCM56334_A0r */
  75158         soc_block_list[4],
  75159         soc_portreg,
  75160         1,
  75161         0,
  75162         0x3000560,
  75163         0,
  75164         0,
  75165         1,
  75166         soc_OP_PORT_LIMIT_RESUME_YELLOW_CELL_BCM56334_A0r_fields,
  75167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75168         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  75169         -1,
  75170         -1,
  75171     },
  75172 #endif /* chips */
  75173 
  75174 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75175     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75176     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75177     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_YELLOW_PACKETr */
  75178         soc_block_list[4],
  75179         soc_portreg,
  75180         1,
  75181         0,
  75182         0x3000027,
  75183         0,
  75184         0,
  75185         1,
  75186         soc_OP_PORT_LIMIT_RESUME_YELLOW_PACKETr_fields,
  75187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75188         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  75189         -1,
  75190         -1,
  75191     },
  75192 #endif /* chips */
  75193 
  75194 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75195     { /* SOC_REG_INT_OP_PORT_LIMIT_RESUME_YELLOW_PACKET_BCM56334_A0r */
  75196         soc_block_list[4],
  75197         soc_portreg,
  75198         1,
  75199         0,
  75200         0x3000561,
  75201         0,
  75202         0,
  75203         1,
  75204         soc_OP_PORT_LIMIT_RESUME_YELLOW_PACKET_BCM56334_A0r_fields,
  75205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75206         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  75207         -1,
  75208         -1,
  75209     },
  75210 #endif /* chips */
  75211 
  75212 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  75213     { /* SOC_REG_INT_OP_PORT_LIMIT_YELLOWr */
  75214         soc_block_list[4],
  75215         soc_portreg,
  75216         1,
  75217         0,
  75218         0x30000c2,
  75219         0,
  75220         0,
  75221         1,
  75222         soc_OP_PORT_LIMIT_YELLOWr_fields,
  75223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75224         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  75225         -1,
  75226         -1,
  75227     },
  75228 #endif /* chips */
  75229 
  75230 #if defined(BCM_88732_A0)
  75231     { /* SOC_REG_INT_OP_PORT_LIMIT_YELLOW_BCM88732_A0r */
  75232         soc_block_list[4],
  75233         soc_portreg,
  75234         1,
  75235         0,
  75236         0x30000c2,
  75237         0,
  75238         0,
  75239         1,
  75240         soc_OP_PORT_LIMIT_YELLOW_BCM88732_A0r_fields,
  75241         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  75242         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  75243         -1,
  75244         -1,
  75245     },
  75246 #endif /* chips */
  75247 
  75248 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75249     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  75250     { /* SOC_REG_INT_OP_PORT_LIMIT_YELLOW_CELLr */
  75251         soc_block_list[4],
  75252         soc_portreg,
  75253         1,
  75254         0,
  75255         0x300000a,
  75256         0,
  75257         0,
  75258         1,
  75259         soc_OP_PORT_LIMIT_YELLOW_CELLr_fields,
  75260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75261         SOC_RESET_MASK_DEC(0x00007ff8, 0x00000000)
  75262         -1,
  75263         -1,
  75264     },
  75265 #endif /* chips */
  75266 
  75267 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75268     { /* SOC_REG_INT_OP_PORT_LIMIT_YELLOW_CELL_BCM56334_A0r */
  75269         soc_block_list[4],
  75270         soc_portreg,
  75271         1,
  75272         0,
  75273         0x300000a,
  75274         0,
  75275         0,
  75276         1,
  75277         soc_OP_PORT_LIMIT_YELLOW_CELL_BCM56334_A0r_fields,
  75278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75279         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  75280         -1,
  75281         -1,
  75282     },
  75283 #endif /* chips */
  75284 
  75285 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75286     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75287     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75288     { /* SOC_REG_INT_OP_PORT_LIMIT_YELLOW_CELL_BCM56634_A0r */
  75289         soc_block_list[4],
  75290         soc_portreg,
  75291         1,
  75292         0,
  75293         0x300000a,
  75294         0,
  75295         0,
  75296         1,
  75297         soc_OP_PORT_LIMIT_YELLOW_CELL_BCM56634_A0r_fields,
  75298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75299         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  75300         -1,
  75301         -1,
  75302     },
  75303 #endif /* chips */
  75304 
  75305 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75306     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  75307     { /* SOC_REG_INT_OP_PORT_LIMIT_YELLOW_PACKETr */
  75308         soc_block_list[4],
  75309         soc_portreg,
  75310         1,
  75311         0,
  75312         0x300000b,
  75313         0,
  75314         0,
  75315         1,
  75316         soc_OP_PORT_LIMIT_YELLOW_PACKETr_fields,
  75317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75318         SOC_RESET_MASK_DEC(0x00003ffc, 0x00000000)
  75319         -1,
  75320         -1,
  75321     },
  75322 #endif /* chips */
  75323 
  75324 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75325     { /* SOC_REG_INT_OP_PORT_LIMIT_YELLOW_PACKET_BCM56334_A0r */
  75326         soc_block_list[4],
  75327         soc_portreg,
  75328         1,
  75329         0,
  75330         0x300000b,
  75331         0,
  75332         0,
  75333         1,
  75334         soc_OP_PORT_LIMIT_YELLOW_PACKET_BCM56334_A0r_fields,
  75335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75336         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  75337         -1,
  75338         -1,
  75339     },
  75340 #endif /* chips */
  75341 
  75342 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75343     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75344     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75345     { /* SOC_REG_INT_OP_PORT_LIMIT_YELLOW_PACKET_BCM56634_A0r */
  75346         soc_block_list[4],
  75347         soc_portreg,
  75348         1,
  75349         0,
  75350         0x300000b,
  75351         0,
  75352         0,
  75353         1,
  75354         soc_OP_PORT_LIMIT_YELLOW_PACKET_BCM56634_A0r_fields,
  75355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75356         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  75357         -1,
  75358         -1,
  75359     },
  75360 #endif /* chips */
  75361 
  75362 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  75363     { /* SOC_REG_INT_OP_PORT_MC_RED_DROP_STATE_CELL_BMP0_64r */
  75364         soc_block_list[4],
  75365         soc_genreg,
  75366         4,
  75367         0,
  75368         0xe006800,
  75369         SOC_REG_FLAG_64_BITS |
  75370                           SOC_REG_FLAG_ARRAY |
  75371                           SOC_REG_FLAG_RO,
  75372         0,
  75373         1,
  75374         soc_OP_PORT_MC_RED_DROP_STATE_CELL_BMP0_64r_fields,
  75375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75376         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  75377         -1,
  75378         -1,
  75379     },
  75380 #endif /* chips */
  75381 
  75382 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  75383     { /* SOC_REG_INT_OP_PORT_MC_YELLOW_DROP_STATE_CELL_BMP0_64r */
  75384         soc_block_list[4],
  75385         soc_genreg,
  75386         4,
  75387         0,
  75388         0xe006400,
  75389         SOC_REG_FLAG_64_BITS |
  75390                           SOC_REG_FLAG_ARRAY |
  75391                           SOC_REG_FLAG_RO,
  75392         0,
  75393         1,
  75394         soc_OP_PORT_MC_YELLOW_DROP_STATE_CELL_BMP0_64r_fields,
  75395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75396         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  75397         -1,
  75398         -1,
  75399     },
  75400 #endif /* chips */
  75401 
  75402 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75403     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75404     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75405     { /* SOC_REG_INT_OP_PORT_REDIRECT_COUNT_CELLr */
  75406         soc_block_list[4],
  75407         soc_portreg,
  75408         1,
  75409         0,
  75410         0x30005f4,
  75411         SOC_REG_FLAG_RO,
  75412         0,
  75413         1,
  75414         soc_OP_PORT_FIRST_FRAGMENT_COUNT_CELLr_fields,
  75415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75416         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  75417         -1,
  75418         20,
  75419     },
  75420 #endif /* chips */
  75421 
  75422 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75423     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75424     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75425     { /* SOC_REG_INT_OP_PORT_REDIRECT_COUNT_PACKETr */
  75426         soc_block_list[4],
  75427         soc_portreg,
  75428         1,
  75429         0,
  75430         0x30005f5,
  75431         SOC_REG_FLAG_RO,
  75432         0,
  75433         1,
  75434         soc_OP_PORT_REDIRECT_COUNT_PACKETr_fields,
  75435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75436         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75437         -1,
  75438         20,
  75439     },
  75440 #endif /* chips */
  75441 
  75442 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75443     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75444     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75445     { /* SOC_REG_INT_OP_PORT_REDIRECT_DISC_RESUME_THD_CELLr */
  75446         soc_block_list[4],
  75447         soc_portreg,
  75448         1,
  75449         0,
  75450         0x30005f1,
  75451         0,
  75452         0,
  75453         1,
  75454         soc_OP_PORT_FIRST_FRAGMENT_DISC_RESUME_THD_CELLr_fields,
  75455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75456         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  75457         -1,
  75458         20,
  75459     },
  75460 #endif /* chips */
  75461 
  75462 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75463     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75464     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75465     { /* SOC_REG_INT_OP_PORT_REDIRECT_DISC_RESUME_THD_PACKETr */
  75466         soc_block_list[4],
  75467         soc_portreg,
  75468         1,
  75469         0,
  75470         0x30005f3,
  75471         0,
  75472         0,
  75473         1,
  75474         soc_OP_PORT_REDIRECT_DISC_RESUME_THD_PACKETr_fields,
  75475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75476         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75477         -1,
  75478         20,
  75479     },
  75480 #endif /* chips */
  75481 
  75482 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75483     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75484     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75485     { /* SOC_REG_INT_OP_PORT_REDIRECT_DISC_SET_THD_CELLr */
  75486         soc_block_list[4],
  75487         soc_portreg,
  75488         1,
  75489         0,
  75490         0x30005f0,
  75491         0,
  75492         0,
  75493         1,
  75494         soc_OP_PORT_FIRST_FRAGMENT_DISC_SET_THD_CELLr_fields,
  75495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75496         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  75497         -1,
  75498         20,
  75499     },
  75500 #endif /* chips */
  75501 
  75502 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75503     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75504     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75505     { /* SOC_REG_INT_OP_PORT_REDIRECT_DISC_SET_THD_PACKETr */
  75506         soc_block_list[4],
  75507         soc_portreg,
  75508         1,
  75509         0,
  75510         0x30005f2,
  75511         0,
  75512         0,
  75513         1,
  75514         soc_OP_PORT_REDIRECT_DISC_SET_THD_PACKETr_fields,
  75515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75516         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75517         -1,
  75518         20,
  75519     },
  75520 #endif /* chips */
  75521 
  75522 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75523     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75524     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75525     { /* SOC_REG_INT_OP_PORT_REDIRECT_XQ_COUNT_PACKETr */
  75526         soc_block_list[4],
  75527         soc_portreg,
  75528         1,
  75529         0,
  75530         0x300061a,
  75531         SOC_REG_FLAG_RO,
  75532         0,
  75533         1,
  75534         soc_OP_PORT_REDIRECT_COUNT_PACKETr_fields,
  75535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75536         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75537         -1,
  75538         20,
  75539     },
  75540 #endif /* chips */
  75541 
  75542 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75543     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75544     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75545     { /* SOC_REG_INT_OP_PORT_REDIRECT_XQ_DISC_RESUME_THD_PACKETr */
  75546         soc_block_list[4],
  75547         soc_portreg,
  75548         1,
  75549         0,
  75550         0x3000619,
  75551         0,
  75552         0,
  75553         1,
  75554         soc_OP_PORT_REDIRECT_DISC_RESUME_THD_PACKETr_fields,
  75555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75556         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75557         -1,
  75558         20,
  75559     },
  75560 #endif /* chips */
  75561 
  75562 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75563     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75564     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75565     { /* SOC_REG_INT_OP_PORT_REDIRECT_XQ_DISC_SET_THD_PACKETr */
  75566         soc_block_list[4],
  75567         soc_portreg,
  75568         1,
  75569         0,
  75570         0x3000618,
  75571         0,
  75572         0,
  75573         1,
  75574         soc_OP_PORT_REDIRECT_DISC_SET_THD_PACKETr_fields,
  75575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75576         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75577         -1,
  75578         20,
  75579     },
  75580 #endif /* chips */
  75581 
  75582 #if defined(BCM_56800_A0)
  75583     { /* SOC_REG_INT_OP_PORT_SHARED_COUNTr */
  75584         soc_block_list[4],
  75585         soc_portreg,
  75586         1,
  75587         0,
  75588         0x3000022,
  75589         SOC_REG_FLAG_RO,
  75590         0,
  75591         1,
  75592         soc_OP_PORT_SHARED_COUNTr_fields,
  75593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75594         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  75595         -1,
  75596         -1,
  75597     },
  75598 #endif /* chips */
  75599 
  75600 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  75601     { /* SOC_REG_INT_OP_PORT_SHARED_COUNT_BCM56820_A0r */
  75602         soc_block_list[4],
  75603         soc_portreg,
  75604         1,
  75605         0,
  75606         0x30000c0,
  75607         SOC_REG_FLAG_RO,
  75608         0,
  75609         1,
  75610         soc_OP_PORT_SHARED_COUNTr_fields,
  75611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75612         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  75613         -1,
  75614         -1,
  75615     },
  75616 #endif /* chips */
  75617 
  75618 #if defined(BCM_88732_A0)
  75619     { /* SOC_REG_INT_OP_PORT_SHARED_COUNT_BCM88732_A0r */
  75620         soc_block_list[4],
  75621         soc_portreg,
  75622         1,
  75623         0,
  75624         0x30000c0,
  75625         SOC_REG_FLAG_RO,
  75626         0,
  75627         1,
  75628         soc_OP_PORT_SHARED_COUNT_BCM88732_A0r_fields,
  75629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75630         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  75631         -1,
  75632         -1,
  75633     },
  75634 #endif /* chips */
  75635 
  75636 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75637     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75638     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75639     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  75640     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75641     { /* SOC_REG_INT_OP_PORT_SHARED_COUNT_CELLr */
  75642         soc_block_list[4],
  75643         soc_portreg,
  75644         1,
  75645         0,
  75646         0x3000012,
  75647         SOC_REG_FLAG_RO,
  75648         0,
  75649         1,
  75650         soc_OP_PORT_SHARED_COUNT_CELLr_fields,
  75651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75652         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  75653         -1,
  75654         -1,
  75655     },
  75656 #endif /* chips */
  75657 
  75658 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75659     { /* SOC_REG_INT_OP_PORT_SHARED_COUNT_CELL_BCM56334_A0r */
  75660         soc_block_list[4],
  75661         soc_portreg,
  75662         1,
  75663         0,
  75664         0x3000012,
  75665         SOC_REG_FLAG_RO,
  75666         0,
  75667         1,
  75668         soc_OP_PORT_SHARED_COUNT_CELL_BCM56334_A0r_fields,
  75669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75670         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  75671         -1,
  75672         -1,
  75673     },
  75674 #endif /* chips */
  75675 
  75676 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  75677     { /* SOC_REG_INT_OP_PORT_SHARED_COUNT_CELL_BCM56640_A0r */
  75678         soc_block_list[4],
  75679         soc_portreg,
  75680         4,
  75681         0,
  75682         0xc005000,
  75683         SOC_REG_FLAG_ARRAY |
  75684                           SOC_REG_FLAG_RO,
  75685         0,
  75686         1,
  75687         soc_OP_PORT_SHARED_COUNT_CELL_BCM56640_A0r_fields,
  75688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75689         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  75690         -1,
  75691         57,
  75692     },
  75693 #endif /* chips */
  75694 
  75695 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  75696     { /* SOC_REG_INT_OP_PORT_SHARED_COUNT_CELL_BCM56840_A0r */
  75697         soc_block_list[4],
  75698         soc_portreg,
  75699         4,
  75700         0,
  75701         0x3000050,
  75702         SOC_REG_FLAG_ARRAY |
  75703                           SOC_REG_FLAG_RO,
  75704         0,
  75705         1,
  75706         soc_OP_PORT_SHARED_COUNT_CELL_BCM56840_A0r_fields,
  75707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75708         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75709         -1,
  75710         -1,
  75711     },
  75712 #endif /* chips */
  75713 
  75714 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75715     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75716     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75717     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  75718     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75719     { /* SOC_REG_INT_OP_PORT_SHARED_COUNT_PACKETr */
  75720         soc_block_list[4],
  75721         soc_portreg,
  75722         1,
  75723         0,
  75724         0x3000013,
  75725         SOC_REG_FLAG_RO,
  75726         0,
  75727         1,
  75728         soc_OP_PORT_SHARED_COUNT_PACKETr_fields,
  75729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75730         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  75731         -1,
  75732         -1,
  75733     },
  75734 #endif /* chips */
  75735 
  75736 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75737     { /* SOC_REG_INT_OP_PORT_SHARED_COUNT_PACKET_BCM56334_A0r */
  75738         soc_block_list[4],
  75739         soc_portreg,
  75740         1,
  75741         0,
  75742         0x3000013,
  75743         SOC_REG_FLAG_RO,
  75744         0,
  75745         1,
  75746         soc_OP_PORT_SHARED_COUNT_PACKET_BCM56334_A0r_fields,
  75747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75748         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  75749         -1,
  75750         -1,
  75751     },
  75752 #endif /* chips */
  75753 
  75754 #if defined(BCM_56800_A0)
  75755     { /* SOC_REG_INT_OP_PORT_TOTAL_COUNTr */
  75756         soc_block_list[4],
  75757         soc_portreg,
  75758         1,
  75759         0,
  75760         0x3000023,
  75761         SOC_REG_FLAG_RO,
  75762         0,
  75763         1,
  75764         soc_OP_PORT_TOTAL_COUNTr_fields,
  75765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75766         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  75767         -1,
  75768         -1,
  75769     },
  75770 #endif /* chips */
  75771 
  75772 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  75773     { /* SOC_REG_INT_OP_PORT_TOTAL_COUNT_BCM56820_A0r */
  75774         soc_block_list[4],
  75775         soc_portreg,
  75776         1,
  75777         0,
  75778         0x30000c1,
  75779         SOC_REG_FLAG_RO,
  75780         0,
  75781         1,
  75782         soc_OP_PORT_TOTAL_COUNTr_fields,
  75783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75784         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  75785         -1,
  75786         -1,
  75787     },
  75788 #endif /* chips */
  75789 
  75790 #if defined(BCM_88732_A0)
  75791     { /* SOC_REG_INT_OP_PORT_TOTAL_COUNT_BCM88732_A0r */
  75792         soc_block_list[4],
  75793         soc_portreg,
  75794         1,
  75795         0,
  75796         0x30000c1,
  75797         SOC_REG_FLAG_RO,
  75798         0,
  75799         1,
  75800         soc_OP_PORT_TOTAL_COUNT_BCM88732_A0r_fields,
  75801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75802         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  75803         -1,
  75804         -1,
  75805     },
  75806 #endif /* chips */
  75807 
  75808 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75809     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75810     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75811     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  75812     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75813     { /* SOC_REG_INT_OP_PORT_TOTAL_COUNT_CELLr */
  75814         soc_block_list[4],
  75815         soc_portreg,
  75816         1,
  75817         0,
  75818         0x3000014,
  75819         SOC_REG_FLAG_RO,
  75820         0,
  75821         1,
  75822         soc_OP_PORT_TOTAL_COUNT_CELLr_fields,
  75823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75824         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  75825         -1,
  75826         -1,
  75827     },
  75828 #endif /* chips */
  75829 
  75830 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75831     { /* SOC_REG_INT_OP_PORT_TOTAL_COUNT_CELL_BCM56334_A0r */
  75832         soc_block_list[4],
  75833         soc_portreg,
  75834         1,
  75835         0,
  75836         0x3000014,
  75837         SOC_REG_FLAG_RO,
  75838         0,
  75839         1,
  75840         soc_OP_PORT_TOTAL_COUNT_CELL_BCM56334_A0r_fields,
  75841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75842         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  75843         -1,
  75844         -1,
  75845     },
  75846 #endif /* chips */
  75847 
  75848 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  75849     { /* SOC_REG_INT_OP_PORT_TOTAL_COUNT_CELL_BCM56640_A0r */
  75850         soc_block_list[4],
  75851         soc_portreg,
  75852         1,
  75853         0,
  75854         0xc005800,
  75855         SOC_REG_FLAG_RO,
  75856         0,
  75857         1,
  75858         soc_OP_PORT_TOTAL_COUNT_CELL_BCM56640_A0r_fields,
  75859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75860         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  75861         -1,
  75862         57,
  75863     },
  75864 #endif /* chips */
  75865 
  75866 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75867     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75868     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75869     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  75870     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75871     { /* SOC_REG_INT_OP_PORT_TOTAL_COUNT_PACKETr */
  75872         soc_block_list[4],
  75873         soc_portreg,
  75874         1,
  75875         0,
  75876         0x3000015,
  75877         SOC_REG_FLAG_RO,
  75878         0,
  75879         1,
  75880         soc_OP_PORT_TOTAL_COUNT_PACKETr_fields,
  75881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75882         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  75883         -1,
  75884         -1,
  75885     },
  75886 #endif /* chips */
  75887 
  75888 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75889     { /* SOC_REG_INT_OP_PORT_TOTAL_COUNT_PACKET_BCM56334_A0r */
  75890         soc_block_list[4],
  75891         soc_portreg,
  75892         1,
  75893         0,
  75894         0x3000015,
  75895         SOC_REG_FLAG_RO,
  75896         0,
  75897         1,
  75898         soc_OP_PORT_TOTAL_COUNT_PACKET_BCM56334_A0r_fields,
  75899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75900         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  75901         -1,
  75902         -1,
  75903     },
  75904 #endif /* chips */
  75905 
  75906 #if defined(BCM_56800_A0)
  75907     { /* SOC_REG_INT_OP_QUEUE_CONFIGr */
  75908         soc_block_list[4],
  75909         soc_portreg,
  75910         10,
  75911         0,
  75912         0x3000010,
  75913         SOC_REG_FLAG_ARRAY,
  75914         0,
  75915         5,
  75916         soc_OP_QUEUE_CONFIGr_fields,
  75917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75918         SOC_RESET_MASK_DEC(0xffff3fff, 0x00000000)
  75919         -1,
  75920         -1,
  75921     },
  75922 #endif /* chips */
  75923 
  75924 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75925     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  75926     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_CELLr */
  75927         soc_block_list[4],
  75928         soc_portreg,
  75929         48,
  75930         0,
  75931         0x3000080,
  75932         SOC_REG_FLAG_ARRAY,
  75933         0,
  75934         2,
  75935         soc_OP_QUEUE_CONFIG1_CELLr_fields,
  75936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75937         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  75938         -1,
  75939         0,
  75940     },
  75941 #endif /* chips */
  75942 
  75943 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  75944     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_CELL_BCM56334_A0r */
  75945         soc_block_list[4],
  75946         soc_portreg,
  75947         48,
  75948         0,
  75949         0x3000080,
  75950         SOC_REG_FLAG_ARRAY,
  75951         0,
  75952         3,
  75953         soc_OP_QUEUE_CONFIG1_CELL_BCM56334_A0r_fields,
  75954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75955         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75956         -1,
  75957         28,
  75958     },
  75959 #endif /* chips */
  75960 
  75961 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \
  75962     defined(BCM_56685_A0)
  75963     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_CELL_BCM56634_A0r */
  75964         soc_block_list[4],
  75965         soc_portreg,
  75966         48,
  75967         0,
  75968         0x3000080,
  75969         SOC_REG_FLAG_ARRAY,
  75970         0,
  75971         2,
  75972         soc_OP_QUEUE_CONFIG1_CELLr_fields,
  75973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75974         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  75975         -1,
  75976         12,
  75977     },
  75978 #endif /* chips */
  75979 
  75980 #if defined(BCM_56524_B0) || defined(BCM_56634_B0) || \
  75981     defined(BCM_56685_B0)
  75982     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_CELL_BCM56634_B0r */
  75983         soc_block_list[4],
  75984         soc_portreg,
  75985         48,
  75986         0,
  75987         0x3000080,
  75988         SOC_REG_FLAG_ARRAY,
  75989         0,
  75990         3,
  75991         soc_OP_QUEUE_CONFIG1_CELL_BCM56634_B0r_fields,
  75992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75993         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75994         -1,
  75995         12,
  75996     },
  75997 #endif /* chips */
  75998 
  75999 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  76000     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_CELL_BCM56640_A0r */
  76001         soc_block_list[4],
  76002         soc_portreg,
  76003         48,
  76004         0,
  76005         0xc014000,
  76006         SOC_REG_FLAG_ARRAY,
  76007         0,
  76008         7,
  76009         soc_OP_QUEUE_CONFIG1_CELL_BCM56640_A0r_fields,
  76010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76011         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  76012         -1,
  76013         62,
  76014     },
  76015 #endif /* chips */
  76016 
  76017 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  76018     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_CELL_BCM56840_A0r */
  76019         soc_block_list[4],
  76020         soc_portreg,
  76021         48,
  76022         0,
  76023         0x3000140,
  76024         SOC_REG_FLAG_ARRAY,
  76025         0,
  76026         7,
  76027         soc_OP_QUEUE_CONFIG1_CELL_BCM56840_A0r_fields,
  76028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76029         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  76030         -1,
  76031         38,
  76032     },
  76033 #endif /* chips */
  76034 
  76035 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  76036     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  76037     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_PACKETr */
  76038         soc_block_list[4],
  76039         soc_portreg,
  76040         48,
  76041         0,
  76042         0x3000100,
  76043         SOC_REG_FLAG_ARRAY,
  76044         0,
  76045         2,
  76046         soc_OP_QUEUE_CONFIG1_PACKETr_fields,
  76047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76048         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  76049         -1,
  76050         0,
  76051     },
  76052 #endif /* chips */
  76053 
  76054 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  76055     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_PACKET_BCM56334_A0r */
  76056         soc_block_list[4],
  76057         soc_portreg,
  76058         48,
  76059         0,
  76060         0x3000100,
  76061         SOC_REG_FLAG_ARRAY,
  76062         0,
  76063         3,
  76064         soc_OP_QUEUE_CONFIG1_PACKET_BCM56334_A0r_fields,
  76065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76066         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  76067         -1,
  76068         28,
  76069     },
  76070 #endif /* chips */
  76071 
  76072 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \
  76073     defined(BCM_56685_A0)
  76074     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_PACKET_BCM56634_A0r */
  76075         soc_block_list[4],
  76076         soc_portreg,
  76077         48,
  76078         0,
  76079         0x3000100,
  76080         SOC_REG_FLAG_ARRAY,
  76081         0,
  76082         2,
  76083         soc_OP_QUEUE_CONFIG1_PACKETr_fields,
  76084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76085         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  76086         -1,
  76087         12,
  76088     },
  76089 #endif /* chips */
  76090 
  76091 #if defined(BCM_56524_B0) || defined(BCM_56634_B0) || \
  76092     defined(BCM_56685_B0)
  76093     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_PACKET_BCM56634_B0r */
  76094         soc_block_list[4],
  76095         soc_portreg,
  76096         48,
  76097         0,
  76098         0x3000100,
  76099         SOC_REG_FLAG_ARRAY,
  76100         0,
  76101         3,
  76102         soc_OP_QUEUE_CONFIG1_PACKET_BCM56634_B0r_fields,
  76103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76104         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  76105         -1,
  76106         12,
  76107     },
  76108 #endif /* chips */
  76109 
  76110 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76111     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDOEMAr */
  76112         soc_block_list[4],
  76113         soc_genreg,
  76114         8,
  76115         0,
  76116         0x2e080017,
  76117         SOC_REG_FLAG_ARRAY,
  76118         0,
  76119         3,
  76120         soc_OP_QUEUE_CONFIG1_THDOEMAr_fields,
  76121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76122         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76123         -1,
  76124         -1,
  76125     },
  76126 #endif /* chips */
  76127 
  76128 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  76129     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDOEMA_BCM56260_A0r */
  76130         soc_block_list[4],
  76131         soc_genreg,
  76132         8,
  76133         0,
  76134         0xba001700,
  76135         SOC_REG_FLAG_ARRAY,
  76136         0,
  76137         3,
  76138         soc_OP_QUEUE_CONFIG1_THDOEMA_BCM56260_A0r_fields,
  76139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76140         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  76141         -1,
  76142         -1,
  76143     },
  76144 #endif /* chips */
  76145 
  76146 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76147     defined(BCM_56450_B1)
  76148     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDOEMA_BCM56450_A0r */
  76149         soc_block_list[4],
  76150         soc_genreg,
  76151         8,
  76152         0,
  76153         0xba001700,
  76154         SOC_REG_FLAG_ARRAY,
  76155         0,
  76156         3,
  76157         soc_OP_QUEUE_CONFIG1_THDOEMA_BCM56450_A0r_fields,
  76158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76159         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76160         -1,
  76161         -1,
  76162     },
  76163 #endif /* chips */
  76164 
  76165 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76166     defined(BCM_56450_B1)
  76167     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORDEEr */
  76168         soc_block_list[4],
  76169         soc_genreg,
  76170         8,
  76171         0,
  76172         0xc6001700,
  76173         SOC_REG_FLAG_ARRAY,
  76174         0,
  76175         3,
  76176         soc_OP_QUEUE_CONFIG1_THDORDEEr_fields,
  76177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76178         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  76179         -1,
  76180         -1,
  76181     },
  76182 #endif /* chips */
  76183 
  76184 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  76185     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORDEE_BCM56260_A0r */
  76186         soc_block_list[4],
  76187         soc_genreg,
  76188         8,
  76189         0,
  76190         0xc6001700,
  76191         SOC_REG_FLAG_ARRAY,
  76192         0,
  76193         3,
  76194         soc_OP_QUEUE_CONFIG1_THDORDEE_BCM56260_A0r_fields,
  76195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76196         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  76197         -1,
  76198         -1,
  76199     },
  76200 #endif /* chips */
  76201 
  76202 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76203     defined(BCM_56450_B1)
  76204     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORDEIr */
  76205         soc_block_list[4],
  76206         soc_genreg,
  76207         8,
  76208         0,
  76209         0xc2001700,
  76210         SOC_REG_FLAG_ARRAY,
  76211         0,
  76212         3,
  76213         soc_OP_QUEUE_CONFIG1_THDOEMA_BCM56450_A0r_fields,
  76214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76215         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76216         -1,
  76217         -1,
  76218     },
  76219 #endif /* chips */
  76220 
  76221 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  76222     defined(BCM_56270_A0)
  76223     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORDEI_BCM56260_A0r */
  76224         soc_block_list[4],
  76225         soc_genreg,
  76226         8,
  76227         0,
  76228         0xc2001700,
  76229         SOC_REG_FLAG_ARRAY,
  76230         0,
  76231         3,
  76232         soc_OP_QUEUE_CONFIG1_THDORDEIr_fields,
  76233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76234         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76235         -1,
  76236         -1,
  76237     },
  76238 #endif /* chips */
  76239 
  76240 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76241     defined(BCM_56450_B1)
  76242     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORDEQr */
  76243         soc_block_list[4],
  76244         soc_genreg,
  76245         16,
  76246         0,
  76247         0xca002700,
  76248         SOC_REG_FLAG_ARRAY,
  76249         0,
  76250         3,
  76251         soc_OP_QUEUE_CONFIG1_THDORDEQr_fields,
  76252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76253         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  76254         -1,
  76255         -1,
  76256     },
  76257 #endif /* chips */
  76258 
  76259 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  76260     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORDEQ_BCM56260_A0r */
  76261         soc_block_list[4],
  76262         soc_genreg,
  76263         16,
  76264         0,
  76265         0xca002700,
  76266         SOC_REG_FLAG_ARRAY,
  76267         0,
  76268         3,
  76269         soc_OP_QUEUE_CONFIG1_THDORDEQ_BCM56260_A0r_fields,
  76270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76271         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  76272         -1,
  76273         -1,
  76274     },
  76275 #endif /* chips */
  76276 
  76277 #if defined(BCM_56270_A0)
  76278     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORDEQ_BCM56270_A0r */
  76279         soc_block_list[4],
  76280         soc_genreg,
  76281         8,
  76282         0,
  76283         0xca001700,
  76284         SOC_REG_FLAG_ARRAY,
  76285         0,
  76286         3,
  76287         soc_OP_QUEUE_CONFIG1_THDORDEQ_BCM56260_A0r_fields,
  76288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76289         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  76290         -1,
  76291         -1,
  76292     },
  76293 #endif /* chips */
  76294 
  76295 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76296     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORQEEr */
  76297         soc_block_list[4],
  76298         soc_genreg,
  76299         12,
  76300         0,
  76301         0x2c08001f,
  76302         SOC_REG_FLAG_ARRAY,
  76303         0,
  76304         3,
  76305         soc_OP_QUEUE_CONFIG1_THDORQEEr_fields,
  76306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76307         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  76308         -1,
  76309         -1,
  76310     },
  76311 #endif /* chips */
  76312 
  76313 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  76314     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORQEE_BCM56260_A0r */
  76315         soc_block_list[4],
  76316         soc_genreg,
  76317         12,
  76318         0,
  76319         0xb2001f00,
  76320         SOC_REG_FLAG_ARRAY,
  76321         0,
  76322         3,
  76323         soc_OP_QUEUE_CONFIG1_THDORDEE_BCM56260_A0r_fields,
  76324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76325         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  76326         -1,
  76327         -1,
  76328     },
  76329 #endif /* chips */
  76330 
  76331 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76332     defined(BCM_56450_B1)
  76333     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORQEE_BCM56450_A0r */
  76334         soc_block_list[4],
  76335         soc_genreg,
  76336         12,
  76337         0,
  76338         0xb2001f00,
  76339         SOC_REG_FLAG_ARRAY,
  76340         0,
  76341         3,
  76342         soc_OP_QUEUE_CONFIG1_THDORDEEr_fields,
  76343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76344         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  76345         -1,
  76346         -1,
  76347     },
  76348 #endif /* chips */
  76349 
  76350 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76351     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORQEIr */
  76352         soc_block_list[4],
  76353         soc_genreg,
  76354         12,
  76355         0,
  76356         0x2b08001f,
  76357         SOC_REG_FLAG_ARRAY,
  76358         0,
  76359         3,
  76360         soc_OP_QUEUE_CONFIG1_THDOEMAr_fields,
  76361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76362         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76363         -1,
  76364         -1,
  76365     },
  76366 #endif /* chips */
  76367 
  76368 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  76369     defined(BCM_56270_A0)
  76370     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORQEI_BCM56260_A0r */
  76371         soc_block_list[4],
  76372         soc_genreg,
  76373         12,
  76374         0,
  76375         0xae001f00,
  76376         SOC_REG_FLAG_ARRAY,
  76377         0,
  76378         3,
  76379         soc_OP_QUEUE_CONFIG1_THDORDEIr_fields,
  76380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76381         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76382         -1,
  76383         -1,
  76384     },
  76385 #endif /* chips */
  76386 
  76387 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76388     defined(BCM_56450_B1)
  76389     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORQEI_BCM56450_A0r */
  76390         soc_block_list[4],
  76391         soc_genreg,
  76392         12,
  76393         0,
  76394         0xae001f00,
  76395         SOC_REG_FLAG_ARRAY,
  76396         0,
  76397         3,
  76398         soc_OP_QUEUE_CONFIG1_THDOEMA_BCM56450_A0r_fields,
  76399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76400         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76401         -1,
  76402         -1,
  76403     },
  76404 #endif /* chips */
  76405 
  76406 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76407     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORQEQr */
  76408         soc_block_list[4],
  76409         soc_genreg,
  76410         12,
  76411         0,
  76412         0x2d08001f,
  76413         SOC_REG_FLAG_ARRAY,
  76414         0,
  76415         3,
  76416         soc_OP_QUEUE_CONFIG1_THDORQEQr_fields,
  76417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76418         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  76419         -1,
  76420         -1,
  76421     },
  76422 #endif /* chips */
  76423 
  76424 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  76425     defined(BCM_56270_A0)
  76426     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORQEQ_BCM56260_A0r */
  76427         soc_block_list[4],
  76428         soc_genreg,
  76429         12,
  76430         0,
  76431         0xb6001f00,
  76432         SOC_REG_FLAG_ARRAY,
  76433         0,
  76434         3,
  76435         soc_OP_QUEUE_CONFIG1_THDORQEQ_BCM56260_A0r_fields,
  76436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76437         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  76438         -1,
  76439         -1,
  76440     },
  76441 #endif /* chips */
  76442 
  76443 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76444     defined(BCM_56450_B1)
  76445     { /* SOC_REG_INT_OP_QUEUE_CONFIG1_THDORQEQ_BCM56450_A0r */
  76446         soc_block_list[4],
  76447         soc_genreg,
  76448         12,
  76449         0,
  76450         0xb6001f00,
  76451         SOC_REG_FLAG_ARRAY,
  76452         0,
  76453         3,
  76454         soc_OP_QUEUE_CONFIG1_THDORQEQ_BCM56450_A0r_fields,
  76455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76456         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  76457         -1,
  76458         -1,
  76459     },
  76460 #endif /* chips */
  76461 
  76462 #if defined(BCM_88732_A0)
  76463     { /* SOC_REG_INT_OP_QUEUE_CONFIGLr */
  76464         soc_block_list[4],
  76465         soc_portreg,
  76466         10,
  76467         0,
  76468         0x3000060,
  76469         SOC_REG_FLAG_ARRAY,
  76470         0,
  76471         7,
  76472         soc_OP_QUEUE_CONFIGLr_fields,
  76473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76474         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  76475         -1,
  76476         49,
  76477     },
  76478 #endif /* chips */
  76479 
  76480 #if defined(BCM_88732_A0)
  76481     { /* SOC_REG_INT_OP_QUEUE_CONFIGUr */
  76482         soc_block_list[4],
  76483         soc_portreg,
  76484         10,
  76485         0,
  76486         0x3000040,
  76487         SOC_REG_FLAG_ARRAY,
  76488         0,
  76489         1,
  76490         soc_OP_QUEUE_CONFIGUr_fields,
  76491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76492         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  76493         -1,
  76494         49,
  76495     },
  76496 #endif /* chips */
  76497 
  76498 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  76499     { /* SOC_REG_INT_OP_QUEUE_CONFIG_BCM56820_A0r */
  76500         soc_block_list[4],
  76501         soc_portreg,
  76502         32,
  76503         0,
  76504         0x3000040,
  76505         SOC_REG_FLAG_ARRAY,
  76506         0,
  76507         7,
  76508         soc_OP_QUEUE_CONFIG_BCM56820_A0r_fields,
  76509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76510         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  76511         -1,
  76512         9,
  76513     },
  76514 #endif /* chips */
  76515 
  76516 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  76517     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  76518     { /* SOC_REG_INT_OP_QUEUE_CONFIG_CELLr */
  76519         soc_block_list[4],
  76520         soc_portreg,
  76521         48,
  76522         0,
  76523         0x3000040,
  76524         SOC_REG_FLAG_ARRAY,
  76525         0,
  76526         4,
  76527         soc_OP_QUEUE_CONFIG_CELLr_fields,
  76528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76529         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  76530         -1,
  76531         0,
  76532     },
  76533 #endif /* chips */
  76534 
  76535 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  76536     { /* SOC_REG_INT_OP_QUEUE_CONFIG_CELL_BCM56334_A0r */
  76537         soc_block_list[4],
  76538         soc_portreg,
  76539         48,
  76540         0,
  76541         0x3000040,
  76542         SOC_REG_FLAG_ARRAY,
  76543         0,
  76544         4,
  76545         soc_OP_QUEUE_CONFIG_CELL_BCM56334_A0r_fields,
  76546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76547         SOC_RESET_MASK_DEC(0xdfffbfff, 0x00000000)
  76548         -1,
  76549         28,
  76550     },
  76551 #endif /* chips */
  76552 
  76553 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  76554     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  76555     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  76556     { /* SOC_REG_INT_OP_QUEUE_CONFIG_CELL_BCM56634_A0r */
  76557         soc_block_list[4],
  76558         soc_portreg,
  76559         48,
  76560         0,
  76561         0x3000040,
  76562         SOC_REG_FLAG_ARRAY,
  76563         0,
  76564         5,
  76565         soc_OP_QUEUE_CONFIG_CELL_BCM56634_A0r_fields,
  76566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76567         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  76568         -1,
  76569         12,
  76570     },
  76571 #endif /* chips */
  76572 
  76573 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  76574     { /* SOC_REG_INT_OP_QUEUE_CONFIG_CELL_BCM56640_A0r */
  76575         soc_block_list[4],
  76576         soc_portreg,
  76577         48,
  76578         0,
  76579         0xc010000,
  76580         SOC_REG_FLAG_ARRAY,
  76581         0,
  76582         3,
  76583         soc_OP_QUEUE_CONFIG_CELL_BCM56640_A0r_fields,
  76584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76585         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  76586         -1,
  76587         62,
  76588     },
  76589 #endif /* chips */
  76590 
  76591 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  76592     { /* SOC_REG_INT_OP_QUEUE_CONFIG_CELL_BCM56840_A0r */
  76593         soc_block_list[4],
  76594         soc_portreg,
  76595         48,
  76596         0,
  76597         0x3000100,
  76598         SOC_REG_FLAG_ARRAY,
  76599         0,
  76600         3,
  76601         soc_OP_QUEUE_CONFIG_CELL_BCM56840_A0r_fields,
  76602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76603         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  76604         -1,
  76605         38,
  76606     },
  76607 #endif /* chips */
  76608 
  76609 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  76610     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  76611     { /* SOC_REG_INT_OP_QUEUE_CONFIG_PACKETr */
  76612         soc_block_list[4],
  76613         soc_portreg,
  76614         48,
  76615         0,
  76616         0x30000c0,
  76617         SOC_REG_FLAG_ARRAY,
  76618         0,
  76619         4,
  76620         soc_OP_QUEUE_CONFIG_PACKETr_fields,
  76621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76622         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  76623         -1,
  76624         0,
  76625     },
  76626 #endif /* chips */
  76627 
  76628 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  76629     { /* SOC_REG_INT_OP_QUEUE_CONFIG_PACKET_BCM56334_A0r */
  76630         soc_block_list[4],
  76631         soc_portreg,
  76632         48,
  76633         0,
  76634         0x30000c0,
  76635         SOC_REG_FLAG_ARRAY,
  76636         0,
  76637         4,
  76638         soc_OP_QUEUE_CONFIG_PACKET_BCM56334_A0r_fields,
  76639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76640         SOC_RESET_MASK_DEC(0x37ffdfff, 0x00000000)
  76641         -1,
  76642         28,
  76643     },
  76644 #endif /* chips */
  76645 
  76646 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  76647     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  76648     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  76649     { /* SOC_REG_INT_OP_QUEUE_CONFIG_PACKET_BCM56634_A0r */
  76650         soc_block_list[4],
  76651         soc_portreg,
  76652         48,
  76653         0,
  76654         0x30000c0,
  76655         SOC_REG_FLAG_ARRAY,
  76656         0,
  76657         5,
  76658         soc_OP_QUEUE_CONFIG_PACKET_BCM56634_A0r_fields,
  76659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76660         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  76661         -1,
  76662         12,
  76663     },
  76664 #endif /* chips */
  76665 
  76666 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76667     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDOEMAr */
  76668         soc_block_list[4],
  76669         soc_genreg,
  76670         8,
  76671         0,
  76672         0x2e08000f,
  76673         SOC_REG_FLAG_ARRAY,
  76674         0,
  76675         3,
  76676         soc_OP_QUEUE_CONFIG_THDOEMAr_fields,
  76677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76678         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76679         -1,
  76680         -1,
  76681     },
  76682 #endif /* chips */
  76683 
  76684 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  76685     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDOEMA_BCM56260_A0r */
  76686         soc_block_list[4],
  76687         soc_genreg,
  76688         8,
  76689         0,
  76690         0xba000f00,
  76691         SOC_REG_FLAG_ARRAY,
  76692         0,
  76693         3,
  76694         soc_OP_QUEUE_CONFIG_THDOEMA_BCM56260_A0r_fields,
  76695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76696         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  76697         -1,
  76698         -1,
  76699     },
  76700 #endif /* chips */
  76701 
  76702 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76703     defined(BCM_56450_B1)
  76704     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDOEMA_BCM56450_A0r */
  76705         soc_block_list[4],
  76706         soc_genreg,
  76707         8,
  76708         0,
  76709         0xba000f00,
  76710         SOC_REG_FLAG_ARRAY,
  76711         0,
  76712         3,
  76713         soc_OP_QUEUE_CONFIG_THDOEMA_BCM56450_A0r_fields,
  76714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76715         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76716         -1,
  76717         -1,
  76718     },
  76719 #endif /* chips */
  76720 
  76721 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76722     defined(BCM_56450_B1)
  76723     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORDEEr */
  76724         soc_block_list[4],
  76725         soc_genreg,
  76726         8,
  76727         0,
  76728         0xc6000f00,
  76729         SOC_REG_FLAG_ARRAY,
  76730         0,
  76731         3,
  76732         soc_OP_QUEUE_CONFIG_THDORDEEr_fields,
  76733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76734         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  76735         -1,
  76736         -1,
  76737     },
  76738 #endif /* chips */
  76739 
  76740 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  76741     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORDEE_BCM56260_A0r */
  76742         soc_block_list[4],
  76743         soc_genreg,
  76744         8,
  76745         0,
  76746         0xc6000f00,
  76747         SOC_REG_FLAG_ARRAY,
  76748         0,
  76749         3,
  76750         soc_OP_QUEUE_CONFIG_THDORDEE_BCM56260_A0r_fields,
  76751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76752         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  76753         -1,
  76754         -1,
  76755     },
  76756 #endif /* chips */
  76757 
  76758 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76759     defined(BCM_56450_B1)
  76760     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORDEIr */
  76761         soc_block_list[4],
  76762         soc_genreg,
  76763         8,
  76764         0,
  76765         0xc2000f00,
  76766         SOC_REG_FLAG_ARRAY,
  76767         0,
  76768         3,
  76769         soc_OP_QUEUE_CONFIG_THDOEMA_BCM56450_A0r_fields,
  76770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76771         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76772         -1,
  76773         -1,
  76774     },
  76775 #endif /* chips */
  76776 
  76777 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  76778     defined(BCM_56270_A0)
  76779     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORDEI_BCM56260_A0r */
  76780         soc_block_list[4],
  76781         soc_genreg,
  76782         8,
  76783         0,
  76784         0xc2000f00,
  76785         SOC_REG_FLAG_ARRAY,
  76786         0,
  76787         3,
  76788         soc_OP_QUEUE_CONFIG_THDORDEIr_fields,
  76789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76790         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76791         -1,
  76792         -1,
  76793     },
  76794 #endif /* chips */
  76795 
  76796 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76797     defined(BCM_56450_B1)
  76798     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORDEQr */
  76799         soc_block_list[4],
  76800         soc_genreg,
  76801         16,
  76802         0,
  76803         0xca001700,
  76804         SOC_REG_FLAG_ARRAY,
  76805         0,
  76806         3,
  76807         soc_OP_QUEUE_CONFIG_THDORDEQr_fields,
  76808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76809         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  76810         -1,
  76811         -1,
  76812     },
  76813 #endif /* chips */
  76814 
  76815 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  76816     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORDEQ_BCM56260_A0r */
  76817         soc_block_list[4],
  76818         soc_genreg,
  76819         16,
  76820         0,
  76821         0xca001700,
  76822         SOC_REG_FLAG_ARRAY,
  76823         0,
  76824         3,
  76825         soc_OP_QUEUE_CONFIG_THDORDEQ_BCM56260_A0r_fields,
  76826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76827         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  76828         -1,
  76829         -1,
  76830     },
  76831 #endif /* chips */
  76832 
  76833 #if defined(BCM_56270_A0)
  76834     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORDEQ_BCM56270_A0r */
  76835         soc_block_list[4],
  76836         soc_genreg,
  76837         8,
  76838         0,
  76839         0xca000f00,
  76840         SOC_REG_FLAG_ARRAY,
  76841         0,
  76842         3,
  76843         soc_OP_QUEUE_CONFIG_THDORDEQ_BCM56260_A0r_fields,
  76844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76845         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  76846         -1,
  76847         -1,
  76848     },
  76849 #endif /* chips */
  76850 
  76851 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76852     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORQEEr */
  76853         soc_block_list[4],
  76854         soc_genreg,
  76855         12,
  76856         0,
  76857         0x2c080013,
  76858         SOC_REG_FLAG_ARRAY,
  76859         0,
  76860         3,
  76861         soc_OP_QUEUE_CONFIG_THDORQEEr_fields,
  76862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76863         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  76864         -1,
  76865         -1,
  76866     },
  76867 #endif /* chips */
  76868 
  76869 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  76870     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORQEE_BCM56260_A0r */
  76871         soc_block_list[4],
  76872         soc_genreg,
  76873         12,
  76874         0,
  76875         0xb2001300,
  76876         SOC_REG_FLAG_ARRAY,
  76877         0,
  76878         3,
  76879         soc_OP_QUEUE_CONFIG_THDORDEE_BCM56260_A0r_fields,
  76880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76881         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  76882         -1,
  76883         -1,
  76884     },
  76885 #endif /* chips */
  76886 
  76887 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76888     defined(BCM_56450_B1)
  76889     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORQEE_BCM56450_A0r */
  76890         soc_block_list[4],
  76891         soc_genreg,
  76892         12,
  76893         0,
  76894         0xb2001300,
  76895         SOC_REG_FLAG_ARRAY,
  76896         0,
  76897         3,
  76898         soc_OP_QUEUE_CONFIG_THDORDEEr_fields,
  76899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76900         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  76901         -1,
  76902         -1,
  76903     },
  76904 #endif /* chips */
  76905 
  76906 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76907     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORQEIr */
  76908         soc_block_list[4],
  76909         soc_genreg,
  76910         12,
  76911         0,
  76912         0x2b080013,
  76913         SOC_REG_FLAG_ARRAY,
  76914         0,
  76915         3,
  76916         soc_OP_QUEUE_CONFIG_THDOEMAr_fields,
  76917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76918         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76919         -1,
  76920         -1,
  76921     },
  76922 #endif /* chips */
  76923 
  76924 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  76925     defined(BCM_56270_A0)
  76926     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORQEI_BCM56260_A0r */
  76927         soc_block_list[4],
  76928         soc_genreg,
  76929         12,
  76930         0,
  76931         0xae001300,
  76932         SOC_REG_FLAG_ARRAY,
  76933         0,
  76934         3,
  76935         soc_OP_QUEUE_CONFIG_THDORDEIr_fields,
  76936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76937         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76938         -1,
  76939         -1,
  76940     },
  76941 #endif /* chips */
  76942 
  76943 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76944     defined(BCM_56450_B1)
  76945     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORQEI_BCM56450_A0r */
  76946         soc_block_list[4],
  76947         soc_genreg,
  76948         12,
  76949         0,
  76950         0xae001300,
  76951         SOC_REG_FLAG_ARRAY,
  76952         0,
  76953         3,
  76954         soc_OP_QUEUE_CONFIG_THDOEMA_BCM56450_A0r_fields,
  76955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76956         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76957         -1,
  76958         -1,
  76959     },
  76960 #endif /* chips */
  76961 
  76962 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76963     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORQEQr */
  76964         soc_block_list[4],
  76965         soc_genreg,
  76966         12,
  76967         0,
  76968         0x2d080013,
  76969         SOC_REG_FLAG_ARRAY,
  76970         0,
  76971         3,
  76972         soc_OP_QUEUE_CONFIG_THDORQEQr_fields,
  76973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76974         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  76975         -1,
  76976         -1,
  76977     },
  76978 #endif /* chips */
  76979 
  76980 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  76981     defined(BCM_56270_A0)
  76982     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORQEQ_BCM56260_A0r */
  76983         soc_block_list[4],
  76984         soc_genreg,
  76985         12,
  76986         0,
  76987         0xb6001300,
  76988         SOC_REG_FLAG_ARRAY,
  76989         0,
  76990         3,
  76991         soc_OP_QUEUE_CONFIG_THDORQEQ_BCM56260_A0r_fields,
  76992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76993         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  76994         -1,
  76995         -1,
  76996     },
  76997 #endif /* chips */
  76998 
  76999 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77000     defined(BCM_56450_B1)
  77001     { /* SOC_REG_INT_OP_QUEUE_CONFIG_THDORQEQ_BCM56450_A0r */
  77002         soc_block_list[4],
  77003         soc_genreg,
  77004         12,
  77005         0,
  77006         0xb6001300,
  77007         SOC_REG_FLAG_ARRAY,
  77008         0,
  77009         3,
  77010         soc_OP_QUEUE_CONFIG_THDORQEQ_BCM56450_A0r_fields,
  77011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77012         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77013         -1,
  77014         -1,
  77015     },
  77016 #endif /* chips */
  77017 
  77018 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77019     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77020     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77021     { /* SOC_REG_INT_OP_QUEUE_FIRST_FRAGMENT_CONFIG_CELLr */
  77022         soc_block_list[4],
  77023         soc_portreg,
  77024         8,
  77025         0,
  77026         0x3000580,
  77027         SOC_REG_FLAG_ARRAY,
  77028         0,
  77029         4,
  77030         soc_OP_QUEUE_FIRST_FRAGMENT_CONFIG_CELLr_fields,
  77031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77032         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  77033         -1,
  77034         14,
  77035     },
  77036 #endif /* chips */
  77037 
  77038 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77039     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77040     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77041     { /* SOC_REG_INT_OP_QUEUE_FIRST_FRAGMENT_CONFIG_PACKETr */
  77042         soc_block_list[4],
  77043         soc_portreg,
  77044         8,
  77045         0,
  77046         0x3000590,
  77047         SOC_REG_FLAG_ARRAY,
  77048         0,
  77049         4,
  77050         soc_OP_QUEUE_FIRST_FRAGMENT_CONFIG_PACKETr_fields,
  77051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77052         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  77053         -1,
  77054         14,
  77055     },
  77056 #endif /* chips */
  77057 
  77058 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77059     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77060     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77061     { /* SOC_REG_INT_OP_QUEUE_FIRST_FRAGMENT_COUNT_CELLr */
  77062         soc_block_list[4],
  77063         soc_portreg,
  77064         8,
  77065         0,
  77066         0x30005a0,
  77067         SOC_REG_FLAG_ARRAY |
  77068                           SOC_REG_FLAG_RO,
  77069         0,
  77070         1,
  77071         soc_OP_PORT_FIRST_FRAGMENT_COUNT_CELLr_fields,
  77072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77073         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77074         -1,
  77075         14,
  77076     },
  77077 #endif /* chips */
  77078 
  77079 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77080     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77081     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77082     { /* SOC_REG_INT_OP_QUEUE_FIRST_FRAGMENT_COUNT_PACKETr */
  77083         soc_block_list[4],
  77084         soc_portreg,
  77085         8,
  77086         0,
  77087         0x30005a8,
  77088         SOC_REG_FLAG_ARRAY |
  77089                           SOC_REG_FLAG_RO,
  77090         0,
  77091         1,
  77092         soc_OP_PORT_FIRST_FRAGMENT_COUNT_PACKETr_fields,
  77093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77094         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  77095         -1,
  77096         14,
  77097     },
  77098 #endif /* chips */
  77099 
  77100 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77101     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77102     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77103     { /* SOC_REG_INT_OP_QUEUE_FIRST_FRAGMENT_RESET_OFFSET_CELLr */
  77104         soc_block_list[4],
  77105         soc_portreg,
  77106         8,
  77107         0,
  77108         0x3000588,
  77109         SOC_REG_FLAG_ARRAY,
  77110         0,
  77111         1,
  77112         soc_OP_QUEUE_FIRST_FRAGMENT_RESET_OFFSET_CELLr_fields,
  77113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77114         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77115         -1,
  77116         14,
  77117     },
  77118 #endif /* chips */
  77119 
  77120 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77121     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77122     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77123     { /* SOC_REG_INT_OP_QUEUE_FIRST_FRAGMENT_RESET_OFFSET_PACKETr */
  77124         soc_block_list[4],
  77125         soc_portreg,
  77126         8,
  77127         0,
  77128         0x3000598,
  77129         SOC_REG_FLAG_ARRAY,
  77130         0,
  77131         1,
  77132         soc_OP_QUEUE_FIRST_FRAGMENT_RESET_OFFSET_PACKETr_fields,
  77133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77134         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  77135         -1,
  77136         14,
  77137     },
  77138 #endif /* chips */
  77139 
  77140 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  77141     { /* SOC_REG_INT_OP_QUEUE_LIMIT_COLOR_CELLr */
  77142         soc_block_list[4],
  77143         soc_portreg,
  77144         48,
  77145         0,
  77146         0x3000180,
  77147         SOC_REG_FLAG_ARRAY,
  77148         0,
  77149         1,
  77150         soc_OP_PORT_LIMIT_COLOR_CELLr_fields,
  77151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77152         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  77153         -1,
  77154         38,
  77155     },
  77156 #endif /* chips */
  77157 
  77158 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  77159     { /* SOC_REG_INT_OP_QUEUE_LIMIT_COLOR_CELL_BCM56640_A0r */
  77160         soc_block_list[4],
  77161         soc_portreg,
  77162         48,
  77163         0,
  77164         0xc018000,
  77165         SOC_REG_FLAG_ARRAY,
  77166         0,
  77167         1,
  77168         soc_OP_PORT_LIMIT_COLOR_CELL_BCM56640_A0r_fields,
  77169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77170         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  77171         -1,
  77172         62,
  77173     },
  77174 #endif /* chips */
  77175 
  77176 #if defined(BCM_88732_A0)
  77177     { /* SOC_REG_INT_OP_QUEUE_LIMIT_PRI0r */
  77178         soc_block_list[4],
  77179         soc_portreg,
  77180         10,
  77181         0,
  77182         0x3000280,
  77183         SOC_REG_FLAG_ARRAY,
  77184         0,
  77185         1,
  77186         soc_OP_QUEUE_LIMIT_PRI0r_fields,
  77187         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  77188         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  77189         -1,
  77190         49,
  77191     },
  77192 #endif /* chips */
  77193 
  77194 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  77195     { /* SOC_REG_INT_OP_QUEUE_LIMIT_REDr */
  77196         soc_block_list[4],
  77197         soc_portreg,
  77198         32,
  77199         0,
  77200         0x3000240,
  77201         SOC_REG_FLAG_ARRAY,
  77202         0,
  77203         1,
  77204         soc_OP_QUEUE_LIMIT_REDr_fields,
  77205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77206         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  77207         -1,
  77208         9,
  77209     },
  77210 #endif /* chips */
  77211 
  77212 #if defined(BCM_88732_A0)
  77213     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_BCM88732_A0r */
  77214         soc_block_list[4],
  77215         soc_portreg,
  77216         10,
  77217         0,
  77218         0x3000240,
  77219         SOC_REG_FLAG_ARRAY,
  77220         0,
  77221         1,
  77222         soc_OP_QUEUE_LIMIT_RED_BCM88732_A0r_fields,
  77223         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  77224         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  77225         -1,
  77226         49,
  77227     },
  77228 #endif /* chips */
  77229 
  77230 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  77231     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  77232     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_CELLr */
  77233         soc_block_list[4],
  77234         soc_portreg,
  77235         48,
  77236         0,
  77237         0x30001c0,
  77238         SOC_REG_FLAG_ARRAY,
  77239         0,
  77240         1,
  77241         soc_OP_QUEUE_LIMIT_RED_CELLr_fields,
  77242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77243         SOC_RESET_MASK_DEC(0x00007ff8, 0x00000000)
  77244         -1,
  77245         0,
  77246     },
  77247 #endif /* chips */
  77248 
  77249 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  77250     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_CELL_BCM56334_A0r */
  77251         soc_block_list[4],
  77252         soc_portreg,
  77253         48,
  77254         0,
  77255         0x30001c0,
  77256         SOC_REG_FLAG_ARRAY,
  77257         0,
  77258         1,
  77259         soc_OP_QUEUE_LIMIT_RED_CELL_BCM56334_A0r_fields,
  77260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77261         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  77262         -1,
  77263         28,
  77264     },
  77265 #endif /* chips */
  77266 
  77267 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77268     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77269     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77270     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_CELL_BCM56634_A0r */
  77271         soc_block_list[4],
  77272         soc_portreg,
  77273         48,
  77274         0,
  77275         0x30001c0,
  77276         SOC_REG_FLAG_ARRAY,
  77277         0,
  77278         1,
  77279         soc_OP_QUEUE_LIMIT_RED_CELL_BCM56634_A0r_fields,
  77280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77281         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  77282         -1,
  77283         12,
  77284     },
  77285 #endif /* chips */
  77286 
  77287 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  77288     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  77289     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_PACKETr */
  77290         soc_block_list[4],
  77291         soc_portreg,
  77292         48,
  77293         0,
  77294         0x3000200,
  77295         SOC_REG_FLAG_ARRAY,
  77296         0,
  77297         1,
  77298         soc_OP_QUEUE_LIMIT_RED_PACKETr_fields,
  77299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77300         SOC_RESET_MASK_DEC(0x00003ffc, 0x00000000)
  77301         -1,
  77302         0,
  77303     },
  77304 #endif /* chips */
  77305 
  77306 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  77307     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_PACKET_BCM56334_A0r */
  77308         soc_block_list[4],
  77309         soc_portreg,
  77310         48,
  77311         0,
  77312         0x3000200,
  77313         SOC_REG_FLAG_ARRAY,
  77314         0,
  77315         1,
  77316         soc_OP_QUEUE_LIMIT_RED_PACKET_BCM56334_A0r_fields,
  77317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77318         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  77319         -1,
  77320         28,
  77321     },
  77322 #endif /* chips */
  77323 
  77324 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77325     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77326     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77327     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_PACKET_BCM56634_A0r */
  77328         soc_block_list[4],
  77329         soc_portreg,
  77330         48,
  77331         0,
  77332         0x3000200,
  77333         SOC_REG_FLAG_ARRAY,
  77334         0,
  77335         1,
  77336         soc_OP_QUEUE_LIMIT_RED_PACKET_BCM56634_A0r_fields,
  77337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77338         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  77339         -1,
  77340         12,
  77341     },
  77342 #endif /* chips */
  77343 
  77344 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77345     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDOEMAr */
  77346         soc_block_list[4],
  77347         soc_genreg,
  77348         8,
  77349         0,
  77350         0x2e080027,
  77351         SOC_REG_FLAG_ARRAY,
  77352         0,
  77353         1,
  77354         soc_OP_QUEUE_LIMIT_RED_THDOEMAr_fields,
  77355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77356         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77357         -1,
  77358         -1,
  77359     },
  77360 #endif /* chips */
  77361 
  77362 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  77363     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDOEMA_BCM56260_A0r */
  77364         soc_block_list[4],
  77365         soc_genreg,
  77366         8,
  77367         0,
  77368         0xba002700,
  77369         SOC_REG_FLAG_ARRAY,
  77370         0,
  77371         1,
  77372         soc_OP_QUEUE_LIMIT_RED_THDOEMA_BCM56260_A0r_fields,
  77373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77374         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  77375         -1,
  77376         -1,
  77377     },
  77378 #endif /* chips */
  77379 
  77380 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77381     defined(BCM_56450_B1)
  77382     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDOEMA_BCM56450_A0r */
  77383         soc_block_list[4],
  77384         soc_genreg,
  77385         8,
  77386         0,
  77387         0xba002700,
  77388         SOC_REG_FLAG_ARRAY,
  77389         0,
  77390         1,
  77391         soc_OP_QUEUE_LIMIT_RED_THDOEMA_BCM56450_A0r_fields,
  77392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77393         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77394         -1,
  77395         -1,
  77396     },
  77397 #endif /* chips */
  77398 
  77399 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77400     defined(BCM_56450_B1)
  77401     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORDEEr */
  77402         soc_block_list[4],
  77403         soc_genreg,
  77404         8,
  77405         0,
  77406         0xc6002700,
  77407         SOC_REG_FLAG_ARRAY,
  77408         0,
  77409         1,
  77410         soc_OP_QUEUE_LIMIT_RED_THDORDEEr_fields,
  77411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77412         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77413         -1,
  77414         -1,
  77415     },
  77416 #endif /* chips */
  77417 
  77418 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  77419     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORDEE_BCM56260_A0r */
  77420         soc_block_list[4],
  77421         soc_genreg,
  77422         8,
  77423         0,
  77424         0xc6002700,
  77425         SOC_REG_FLAG_ARRAY,
  77426         0,
  77427         1,
  77428         soc_OP_QUEUE_LIMIT_RED_THDORDEE_BCM56260_A0r_fields,
  77429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77430         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  77431         -1,
  77432         -1,
  77433     },
  77434 #endif /* chips */
  77435 
  77436 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77437     defined(BCM_56450_B1)
  77438     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORDEIr */
  77439         soc_block_list[4],
  77440         soc_genreg,
  77441         8,
  77442         0,
  77443         0xc2002700,
  77444         SOC_REG_FLAG_ARRAY,
  77445         0,
  77446         1,
  77447         soc_OP_QUEUE_LIMIT_RED_THDOEMA_BCM56450_A0r_fields,
  77448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77449         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77450         -1,
  77451         -1,
  77452     },
  77453 #endif /* chips */
  77454 
  77455 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  77456     defined(BCM_56270_A0)
  77457     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORDEI_BCM56260_A0r */
  77458         soc_block_list[4],
  77459         soc_genreg,
  77460         8,
  77461         0,
  77462         0xc2002700,
  77463         SOC_REG_FLAG_ARRAY,
  77464         0,
  77465         1,
  77466         soc_OP_QUEUE_LIMIT_RED_THDORDEIr_fields,
  77467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77468         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77469         -1,
  77470         -1,
  77471     },
  77472 #endif /* chips */
  77473 
  77474 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77475     defined(BCM_56450_B1)
  77476     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORDEQr */
  77477         soc_block_list[4],
  77478         soc_genreg,
  77479         16,
  77480         0,
  77481         0xca004700,
  77482         SOC_REG_FLAG_ARRAY,
  77483         0,
  77484         1,
  77485         soc_OP_QUEUE_LIMIT_RED_THDORDEQr_fields,
  77486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77487         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  77488         -1,
  77489         -1,
  77490     },
  77491 #endif /* chips */
  77492 
  77493 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  77494     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORDEQ_BCM56260_A0r */
  77495         soc_block_list[4],
  77496         soc_genreg,
  77497         16,
  77498         0,
  77499         0xca004700,
  77500         SOC_REG_FLAG_ARRAY,
  77501         0,
  77502         1,
  77503         soc_OP_QUEUE_LIMIT_RED_THDORDEQ_BCM56260_A0r_fields,
  77504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77505         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  77506         -1,
  77507         -1,
  77508     },
  77509 #endif /* chips */
  77510 
  77511 #if defined(BCM_56270_A0)
  77512     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORDEQ_BCM56270_A0r */
  77513         soc_block_list[4],
  77514         soc_genreg,
  77515         8,
  77516         0,
  77517         0xca002700,
  77518         SOC_REG_FLAG_ARRAY,
  77519         0,
  77520         1,
  77521         soc_OP_QUEUE_LIMIT_RED_THDORDEQ_BCM56260_A0r_fields,
  77522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77523         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  77524         -1,
  77525         -1,
  77526     },
  77527 #endif /* chips */
  77528 
  77529 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77530     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORQEEr */
  77531         soc_block_list[4],
  77532         soc_genreg,
  77533         12,
  77534         0,
  77535         0x2c080037,
  77536         SOC_REG_FLAG_ARRAY,
  77537         0,
  77538         1,
  77539         soc_OP_QUEUE_LIMIT_RED_THDORQEEr_fields,
  77540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77541         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77542         -1,
  77543         -1,
  77544     },
  77545 #endif /* chips */
  77546 
  77547 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  77548     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORQEE_BCM56260_A0r */
  77549         soc_block_list[4],
  77550         soc_genreg,
  77551         12,
  77552         0,
  77553         0xb2003700,
  77554         SOC_REG_FLAG_ARRAY,
  77555         0,
  77556         1,
  77557         soc_OP_QUEUE_LIMIT_RED_THDORDEE_BCM56260_A0r_fields,
  77558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77559         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  77560         -1,
  77561         -1,
  77562     },
  77563 #endif /* chips */
  77564 
  77565 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77566     defined(BCM_56450_B1)
  77567     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORQEE_BCM56450_A0r */
  77568         soc_block_list[4],
  77569         soc_genreg,
  77570         12,
  77571         0,
  77572         0xb2003700,
  77573         SOC_REG_FLAG_ARRAY,
  77574         0,
  77575         1,
  77576         soc_OP_QUEUE_LIMIT_RED_THDORDEEr_fields,
  77577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77578         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77579         -1,
  77580         -1,
  77581     },
  77582 #endif /* chips */
  77583 
  77584 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77585     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORQEIr */
  77586         soc_block_list[4],
  77587         soc_genreg,
  77588         12,
  77589         0,
  77590         0x2b080037,
  77591         SOC_REG_FLAG_ARRAY,
  77592         0,
  77593         1,
  77594         soc_OP_QUEUE_LIMIT_RED_THDOEMAr_fields,
  77595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77596         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77597         -1,
  77598         -1,
  77599     },
  77600 #endif /* chips */
  77601 
  77602 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  77603     defined(BCM_56270_A0)
  77604     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORQEI_BCM56260_A0r */
  77605         soc_block_list[4],
  77606         soc_genreg,
  77607         12,
  77608         0,
  77609         0xae003700,
  77610         SOC_REG_FLAG_ARRAY,
  77611         0,
  77612         1,
  77613         soc_OP_QUEUE_LIMIT_RED_THDORDEIr_fields,
  77614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77615         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77616         -1,
  77617         -1,
  77618     },
  77619 #endif /* chips */
  77620 
  77621 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77622     defined(BCM_56450_B1)
  77623     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORQEI_BCM56450_A0r */
  77624         soc_block_list[4],
  77625         soc_genreg,
  77626         12,
  77627         0,
  77628         0xae003700,
  77629         SOC_REG_FLAG_ARRAY,
  77630         0,
  77631         1,
  77632         soc_OP_QUEUE_LIMIT_RED_THDOEMA_BCM56450_A0r_fields,
  77633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77634         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77635         -1,
  77636         -1,
  77637     },
  77638 #endif /* chips */
  77639 
  77640 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77641     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORQEQr */
  77642         soc_block_list[4],
  77643         soc_genreg,
  77644         12,
  77645         0,
  77646         0x2d080037,
  77647         SOC_REG_FLAG_ARRAY,
  77648         0,
  77649         1,
  77650         soc_OP_QUEUE_LIMIT_RED_THDORQEQr_fields,
  77651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77652         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  77653         -1,
  77654         -1,
  77655     },
  77656 #endif /* chips */
  77657 
  77658 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  77659     defined(BCM_56270_A0)
  77660     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORQEQ_BCM56260_A0r */
  77661         soc_block_list[4],
  77662         soc_genreg,
  77663         12,
  77664         0,
  77665         0xb6003700,
  77666         SOC_REG_FLAG_ARRAY,
  77667         0,
  77668         1,
  77669         soc_OP_QUEUE_LIMIT_RED_THDORQEQ_BCM56260_A0r_fields,
  77670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77671         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  77672         -1,
  77673         -1,
  77674     },
  77675 #endif /* chips */
  77676 
  77677 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77678     defined(BCM_56450_B1)
  77679     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RED_THDORQEQ_BCM56450_A0r */
  77680         soc_block_list[4],
  77681         soc_genreg,
  77682         12,
  77683         0,
  77684         0xb6003700,
  77685         SOC_REG_FLAG_ARRAY,
  77686         0,
  77687         1,
  77688         soc_OP_QUEUE_LIMIT_RED_THDORQEQ_BCM56450_A0r_fields,
  77689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77690         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  77691         -1,
  77692         -1,
  77693     },
  77694 #endif /* chips */
  77695 
  77696 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77697     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77698     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77699     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RESUME_COLOR_CELLr */
  77700         soc_block_list[4],
  77701         soc_portreg,
  77702         48,
  77703         0,
  77704         0x3000500,
  77705         SOC_REG_FLAG_ARRAY,
  77706         0,
  77707         1,
  77708         soc_OP_QUEUE_LIMIT_RESUME_COLOR_CELLr_fields,
  77709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77710         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  77711         -1,
  77712         12,
  77713     },
  77714 #endif /* chips */
  77715 
  77716 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  77717     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RESUME_COLOR_CELL_BCM56334_A0r */
  77718         soc_block_list[4],
  77719         soc_portreg,
  77720         48,
  77721         0,
  77722         0x30004c0,
  77723         SOC_REG_FLAG_ARRAY,
  77724         0,
  77725         1,
  77726         soc_OP_QUEUE_LIMIT_RESUME_COLOR_CELLr_fields,
  77727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77728         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  77729         -1,
  77730         28,
  77731     },
  77732 #endif /* chips */
  77733 
  77734 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  77735     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RESUME_COLOR_CELL_BCM56640_A0r */
  77736         soc_block_list[4],
  77737         soc_portreg,
  77738         48,
  77739         0,
  77740         0xc044000,
  77741         SOC_REG_FLAG_ARRAY,
  77742         0,
  77743         1,
  77744         soc_OP_QUEUE_LIMIT_RESUME_COLOR_CELL_BCM56640_A0r_fields,
  77745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77746         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  77747         -1,
  77748         62,
  77749     },
  77750 #endif /* chips */
  77751 
  77752 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  77753     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RESUME_COLOR_CELL_BCM56840_A0r */
  77754         soc_block_list[4],
  77755         soc_portreg,
  77756         48,
  77757         0,
  77758         0x3000440,
  77759         SOC_REG_FLAG_ARRAY,
  77760         0,
  77761         1,
  77762         soc_OP_QUEUE_LIMIT_RESUME_COLOR_CELLr_fields,
  77763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77764         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  77765         -1,
  77766         38,
  77767     },
  77768 #endif /* chips */
  77769 
  77770 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77771     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77772     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77773     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RESUME_COLOR_PACKETr */
  77774         soc_block_list[4],
  77775         soc_portreg,
  77776         48,
  77777         0,
  77778         0x3000540,
  77779         SOC_REG_FLAG_ARRAY,
  77780         0,
  77781         1,
  77782         soc_OP_QUEUE_LIMIT_RESUME_COLOR_PACKETr_fields,
  77783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77784         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  77785         -1,
  77786         12,
  77787     },
  77788 #endif /* chips */
  77789 
  77790 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  77791     { /* SOC_REG_INT_OP_QUEUE_LIMIT_RESUME_COLOR_PACKET_BCM56334_A0r */
  77792         soc_block_list[4],
  77793         soc_portreg,
  77794         48,
  77795         0,
  77796         0x3000500,
  77797         SOC_REG_FLAG_ARRAY,
  77798         0,
  77799         1,
  77800         soc_OP_QUEUE_LIMIT_RESUME_COLOR_PACKETr_fields,
  77801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77802         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  77803         -1,
  77804         28,
  77805     },
  77806 #endif /* chips */
  77807 
  77808 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  77809     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOWr */
  77810         soc_block_list[4],
  77811         soc_portreg,
  77812         32,
  77813         0,
  77814         0x3000200,
  77815         SOC_REG_FLAG_ARRAY,
  77816         0,
  77817         1,
  77818         soc_OP_QUEUE_LIMIT_YELLOWr_fields,
  77819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77820         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  77821         -1,
  77822         9,
  77823     },
  77824 #endif /* chips */
  77825 
  77826 #if defined(BCM_88732_A0)
  77827     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_BCM88732_A0r */
  77828         soc_block_list[4],
  77829         soc_portreg,
  77830         10,
  77831         0,
  77832         0x3000200,
  77833         SOC_REG_FLAG_ARRAY,
  77834         0,
  77835         1,
  77836         soc_OP_QUEUE_LIMIT_YELLOW_BCM88732_A0r_fields,
  77837         SOC_RESET_VAL_DEC(0x00018000, 0x00000000)
  77838         SOC_RESET_MASK_DEC(0x0001fff8, 0x00000000)
  77839         -1,
  77840         49,
  77841     },
  77842 #endif /* chips */
  77843 
  77844 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  77845     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  77846     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_CELLr */
  77847         soc_block_list[4],
  77848         soc_portreg,
  77849         48,
  77850         0,
  77851         0x3000140,
  77852         SOC_REG_FLAG_ARRAY,
  77853         0,
  77854         1,
  77855         soc_OP_QUEUE_LIMIT_YELLOW_CELLr_fields,
  77856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77857         SOC_RESET_MASK_DEC(0x00007ff8, 0x00000000)
  77858         -1,
  77859         0,
  77860     },
  77861 #endif /* chips */
  77862 
  77863 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  77864     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_CELL_BCM56334_A0r */
  77865         soc_block_list[4],
  77866         soc_portreg,
  77867         48,
  77868         0,
  77869         0x3000140,
  77870         SOC_REG_FLAG_ARRAY,
  77871         0,
  77872         1,
  77873         soc_OP_QUEUE_LIMIT_YELLOW_CELL_BCM56334_A0r_fields,
  77874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77875         SOC_RESET_MASK_DEC(0x00003ff8, 0x00000000)
  77876         -1,
  77877         28,
  77878     },
  77879 #endif /* chips */
  77880 
  77881 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77882     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77883     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77884     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_CELL_BCM56634_A0r */
  77885         soc_block_list[4],
  77886         soc_portreg,
  77887         48,
  77888         0,
  77889         0x3000140,
  77890         SOC_REG_FLAG_ARRAY,
  77891         0,
  77892         1,
  77893         soc_OP_QUEUE_LIMIT_YELLOW_CELL_BCM56634_A0r_fields,
  77894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77895         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  77896         -1,
  77897         12,
  77898     },
  77899 #endif /* chips */
  77900 
  77901 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  77902     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  77903     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_PACKETr */
  77904         soc_block_list[4],
  77905         soc_portreg,
  77906         48,
  77907         0,
  77908         0x3000180,
  77909         SOC_REG_FLAG_ARRAY,
  77910         0,
  77911         1,
  77912         soc_OP_QUEUE_LIMIT_YELLOW_PACKETr_fields,
  77913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77914         SOC_RESET_MASK_DEC(0x00003ffc, 0x00000000)
  77915         -1,
  77916         0,
  77917     },
  77918 #endif /* chips */
  77919 
  77920 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  77921     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_PACKET_BCM56334_A0r */
  77922         soc_block_list[4],
  77923         soc_portreg,
  77924         48,
  77925         0,
  77926         0x3000180,
  77927         SOC_REG_FLAG_ARRAY,
  77928         0,
  77929         1,
  77930         soc_OP_QUEUE_LIMIT_YELLOW_PACKET_BCM56334_A0r_fields,
  77931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77932         SOC_RESET_MASK_DEC(0x00001ffc, 0x00000000)
  77933         -1,
  77934         28,
  77935     },
  77936 #endif /* chips */
  77937 
  77938 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77939     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77940     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77941     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_PACKET_BCM56634_A0r */
  77942         soc_block_list[4],
  77943         soc_portreg,
  77944         48,
  77945         0,
  77946         0x3000180,
  77947         SOC_REG_FLAG_ARRAY,
  77948         0,
  77949         1,
  77950         soc_OP_QUEUE_LIMIT_YELLOW_PACKET_BCM56634_A0r_fields,
  77951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77952         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  77953         -1,
  77954         12,
  77955     },
  77956 #endif /* chips */
  77957 
  77958 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77959     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDOEMAr */
  77960         soc_block_list[4],
  77961         soc_genreg,
  77962         8,
  77963         0,
  77964         0x2e08001f,
  77965         SOC_REG_FLAG_ARRAY,
  77966         0,
  77967         1,
  77968         soc_OP_QUEUE_LIMIT_YELLOW_THDOEMAr_fields,
  77969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77970         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77971         -1,
  77972         -1,
  77973     },
  77974 #endif /* chips */
  77975 
  77976 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  77977     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDOEMA_BCM56260_A0r */
  77978         soc_block_list[4],
  77979         soc_genreg,
  77980         8,
  77981         0,
  77982         0xba001f00,
  77983         SOC_REG_FLAG_ARRAY,
  77984         0,
  77985         1,
  77986         soc_OP_QUEUE_LIMIT_YELLOW_THDOEMA_BCM56260_A0r_fields,
  77987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77988         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  77989         -1,
  77990         -1,
  77991     },
  77992 #endif /* chips */
  77993 
  77994 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77995     defined(BCM_56450_B1)
  77996     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDOEMA_BCM56450_A0r */
  77997         soc_block_list[4],
  77998         soc_genreg,
  77999         8,
  78000         0,
  78001         0xba001f00,
  78002         SOC_REG_FLAG_ARRAY,
  78003         0,
  78004         1,
  78005         soc_OP_QUEUE_LIMIT_YELLOW_THDOEMA_BCM56450_A0r_fields,
  78006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78007         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78008         -1,
  78009         -1,
  78010     },
  78011 #endif /* chips */
  78012 
  78013 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78014     defined(BCM_56450_B1)
  78015     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORDEEr */
  78016         soc_block_list[4],
  78017         soc_genreg,
  78018         8,
  78019         0,
  78020         0xc6001f00,
  78021         SOC_REG_FLAG_ARRAY,
  78022         0,
  78023         1,
  78024         soc_OP_QUEUE_LIMIT_YELLOW_THDORDEEr_fields,
  78025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78026         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  78027         -1,
  78028         -1,
  78029     },
  78030 #endif /* chips */
  78031 
  78032 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78033     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORDEE_BCM56260_A0r */
  78034         soc_block_list[4],
  78035         soc_genreg,
  78036         8,
  78037         0,
  78038         0xc6001f00,
  78039         SOC_REG_FLAG_ARRAY,
  78040         0,
  78041         1,
  78042         soc_OP_QUEUE_LIMIT_YELLOW_THDORDEE_BCM56260_A0r_fields,
  78043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78044         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  78045         -1,
  78046         -1,
  78047     },
  78048 #endif /* chips */
  78049 
  78050 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78051     defined(BCM_56450_B1)
  78052     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORDEIr */
  78053         soc_block_list[4],
  78054         soc_genreg,
  78055         8,
  78056         0,
  78057         0xc2001f00,
  78058         SOC_REG_FLAG_ARRAY,
  78059         0,
  78060         1,
  78061         soc_OP_QUEUE_LIMIT_YELLOW_THDOEMA_BCM56450_A0r_fields,
  78062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78063         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78064         -1,
  78065         -1,
  78066     },
  78067 #endif /* chips */
  78068 
  78069 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  78070     defined(BCM_56270_A0)
  78071     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORDEI_BCM56260_A0r */
  78072         soc_block_list[4],
  78073         soc_genreg,
  78074         8,
  78075         0,
  78076         0xc2001f00,
  78077         SOC_REG_FLAG_ARRAY,
  78078         0,
  78079         1,
  78080         soc_OP_QUEUE_LIMIT_YELLOW_THDORDEIr_fields,
  78081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78082         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78083         -1,
  78084         -1,
  78085     },
  78086 #endif /* chips */
  78087 
  78088 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78089     defined(BCM_56450_B1)
  78090     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORDEQr */
  78091         soc_block_list[4],
  78092         soc_genreg,
  78093         16,
  78094         0,
  78095         0xca003700,
  78096         SOC_REG_FLAG_ARRAY,
  78097         0,
  78098         1,
  78099         soc_OP_QUEUE_LIMIT_YELLOW_THDORDEQr_fields,
  78100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78101         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78102         -1,
  78103         -1,
  78104     },
  78105 #endif /* chips */
  78106 
  78107 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78108     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORDEQ_BCM56260_A0r */
  78109         soc_block_list[4],
  78110         soc_genreg,
  78111         16,
  78112         0,
  78113         0xca003700,
  78114         SOC_REG_FLAG_ARRAY,
  78115         0,
  78116         1,
  78117         soc_OP_QUEUE_LIMIT_YELLOW_THDORDEQ_BCM56260_A0r_fields,
  78118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78119         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  78120         -1,
  78121         -1,
  78122     },
  78123 #endif /* chips */
  78124 
  78125 #if defined(BCM_56270_A0)
  78126     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORDEQ_BCM56270_A0r */
  78127         soc_block_list[4],
  78128         soc_genreg,
  78129         8,
  78130         0,
  78131         0xca001f00,
  78132         SOC_REG_FLAG_ARRAY,
  78133         0,
  78134         1,
  78135         soc_OP_QUEUE_LIMIT_YELLOW_THDORDEQ_BCM56260_A0r_fields,
  78136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78137         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  78138         -1,
  78139         -1,
  78140     },
  78141 #endif /* chips */
  78142 
  78143 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78144     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORQEEr */
  78145         soc_block_list[4],
  78146         soc_genreg,
  78147         12,
  78148         0,
  78149         0x2c08002b,
  78150         SOC_REG_FLAG_ARRAY,
  78151         0,
  78152         1,
  78153         soc_OP_QUEUE_LIMIT_YELLOW_THDORQEEr_fields,
  78154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78155         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  78156         -1,
  78157         -1,
  78158     },
  78159 #endif /* chips */
  78160 
  78161 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78162     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORQEE_BCM56260_A0r */
  78163         soc_block_list[4],
  78164         soc_genreg,
  78165         12,
  78166         0,
  78167         0xb2002b00,
  78168         SOC_REG_FLAG_ARRAY,
  78169         0,
  78170         1,
  78171         soc_OP_QUEUE_LIMIT_YELLOW_THDORDEE_BCM56260_A0r_fields,
  78172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78173         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  78174         -1,
  78175         -1,
  78176     },
  78177 #endif /* chips */
  78178 
  78179 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78180     defined(BCM_56450_B1)
  78181     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORQEE_BCM56450_A0r */
  78182         soc_block_list[4],
  78183         soc_genreg,
  78184         12,
  78185         0,
  78186         0xb2002b00,
  78187         SOC_REG_FLAG_ARRAY,
  78188         0,
  78189         1,
  78190         soc_OP_QUEUE_LIMIT_YELLOW_THDORDEEr_fields,
  78191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78192         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  78193         -1,
  78194         -1,
  78195     },
  78196 #endif /* chips */
  78197 
  78198 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78199     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORQEIr */
  78200         soc_block_list[4],
  78201         soc_genreg,
  78202         12,
  78203         0,
  78204         0x2b08002b,
  78205         SOC_REG_FLAG_ARRAY,
  78206         0,
  78207         1,
  78208         soc_OP_QUEUE_LIMIT_YELLOW_THDOEMAr_fields,
  78209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78210         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78211         -1,
  78212         -1,
  78213     },
  78214 #endif /* chips */
  78215 
  78216 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  78217     defined(BCM_56270_A0)
  78218     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORQEI_BCM56260_A0r */
  78219         soc_block_list[4],
  78220         soc_genreg,
  78221         12,
  78222         0,
  78223         0xae002b00,
  78224         SOC_REG_FLAG_ARRAY,
  78225         0,
  78226         1,
  78227         soc_OP_QUEUE_LIMIT_YELLOW_THDORDEIr_fields,
  78228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78229         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78230         -1,
  78231         -1,
  78232     },
  78233 #endif /* chips */
  78234 
  78235 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78236     defined(BCM_56450_B1)
  78237     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORQEI_BCM56450_A0r */
  78238         soc_block_list[4],
  78239         soc_genreg,
  78240         12,
  78241         0,
  78242         0xae002b00,
  78243         SOC_REG_FLAG_ARRAY,
  78244         0,
  78245         1,
  78246         soc_OP_QUEUE_LIMIT_YELLOW_THDOEMA_BCM56450_A0r_fields,
  78247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78248         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78249         -1,
  78250         -1,
  78251     },
  78252 #endif /* chips */
  78253 
  78254 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78255     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORQEQr */
  78256         soc_block_list[4],
  78257         soc_genreg,
  78258         12,
  78259         0,
  78260         0x2d08002b,
  78261         SOC_REG_FLAG_ARRAY,
  78262         0,
  78263         1,
  78264         soc_OP_QUEUE_LIMIT_YELLOW_THDORQEQr_fields,
  78265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78266         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  78267         -1,
  78268         -1,
  78269     },
  78270 #endif /* chips */
  78271 
  78272 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  78273     defined(BCM_56270_A0)
  78274     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORQEQ_BCM56260_A0r */
  78275         soc_block_list[4],
  78276         soc_genreg,
  78277         12,
  78278         0,
  78279         0xb6002b00,
  78280         SOC_REG_FLAG_ARRAY,
  78281         0,
  78282         1,
  78283         soc_OP_QUEUE_LIMIT_YELLOW_THDORQEQ_BCM56260_A0r_fields,
  78284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78285         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  78286         -1,
  78287         -1,
  78288     },
  78289 #endif /* chips */
  78290 
  78291 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78292     defined(BCM_56450_B1)
  78293     { /* SOC_REG_INT_OP_QUEUE_LIMIT_YELLOW_THDORQEQ_BCM56450_A0r */
  78294         soc_block_list[4],
  78295         soc_genreg,
  78296         12,
  78297         0,
  78298         0xb6002b00,
  78299         SOC_REG_FLAG_ARRAY,
  78300         0,
  78301         1,
  78302         soc_OP_QUEUE_LIMIT_YELLOW_THDORQEQ_BCM56450_A0r_fields,
  78303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78304         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  78305         -1,
  78306         -1,
  78307     },
  78308 #endif /* chips */
  78309 
  78310 #if defined(BCM_56800_A0)
  78311     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNTr */
  78312         soc_block_list[4],
  78313         soc_portreg,
  78314         10,
  78315         0,
  78316         0x3000030,
  78317         SOC_REG_FLAG_ARRAY |
  78318                           SOC_REG_FLAG_RO,
  78319         0,
  78320         1,
  78321         soc_OP_QUEUE_MIN_COUNTr_fields,
  78322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78323         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  78324         -1,
  78325         -1,
  78326     },
  78327 #endif /* chips */
  78328 
  78329 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  78330     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_BCM56820_A0r */
  78331         soc_block_list[4],
  78332         soc_portreg,
  78333         32,
  78334         0,
  78335         0x3000100,
  78336         SOC_REG_FLAG_ARRAY |
  78337                           SOC_REG_FLAG_RO,
  78338         0,
  78339         1,
  78340         soc_OP_QUEUE_MIN_COUNT_BCM56820_A0r_fields,
  78341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78342         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78343         -1,
  78344         9,
  78345     },
  78346 #endif /* chips */
  78347 
  78348 #if defined(BCM_88732_A0)
  78349     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_BCM88732_A0r */
  78350         soc_block_list[4],
  78351         soc_portreg,
  78352         10,
  78353         0,
  78354         0x3000100,
  78355         SOC_REG_FLAG_ARRAY |
  78356                           SOC_REG_FLAG_RO,
  78357         0,
  78358         3,
  78359         soc_OP_QUEUE_MIN_COUNT_BCM88732_A0r_fields,
  78360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78361         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  78362         -1,
  78363         49,
  78364     },
  78365 #endif /* chips */
  78366 
  78367 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  78368     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  78369     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_CELLr */
  78370         soc_block_list[4],
  78371         soc_portreg,
  78372         48,
  78373         0,
  78374         0x30002c0,
  78375         SOC_REG_FLAG_ARRAY |
  78376                           SOC_REG_FLAG_RO,
  78377         0,
  78378         1,
  78379         soc_OP_QUEUE_MIN_COUNT_CELLr_fields,
  78380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78381         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  78382         -1,
  78383         0,
  78384     },
  78385 #endif /* chips */
  78386 
  78387 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  78388     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_CELL_BCM56334_A0r */
  78389         soc_block_list[4],
  78390         soc_portreg,
  78391         48,
  78392         0,
  78393         0x30002c0,
  78394         SOC_REG_FLAG_ARRAY |
  78395                           SOC_REG_FLAG_RO,
  78396         0,
  78397         1,
  78398         soc_OP_QUEUE_MIN_COUNT_CELL_BCM56334_A0r_fields,
  78399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78400         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78401         -1,
  78402         28,
  78403     },
  78404 #endif /* chips */
  78405 
  78406 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  78407     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  78408     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  78409     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_CELL_BCM56634_A0r */
  78410         soc_block_list[4],
  78411         soc_portreg,
  78412         48,
  78413         0,
  78414         0x30002c0,
  78415         SOC_REG_FLAG_ARRAY |
  78416                           SOC_REG_FLAG_RO,
  78417         0,
  78418         1,
  78419         soc_OP_QUEUE_MIN_COUNT_CELLr_fields,
  78420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78421         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  78422         -1,
  78423         12,
  78424     },
  78425 #endif /* chips */
  78426 
  78427 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  78428     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_CELL_BCM56640_A0r */
  78429         soc_block_list[4],
  78430         soc_portreg,
  78431         48,
  78432         0,
  78433         0xc024000,
  78434         SOC_REG_FLAG_ARRAY |
  78435                           SOC_REG_FLAG_RO,
  78436         0,
  78437         1,
  78438         soc_OP_QUEUE_MIN_COUNT_CELL_BCM56640_A0r_fields,
  78439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78440         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  78441         -1,
  78442         62,
  78443     },
  78444 #endif /* chips */
  78445 
  78446 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  78447     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_CELL_BCM56840_A0r */
  78448         soc_block_list[4],
  78449         soc_portreg,
  78450         48,
  78451         0,
  78452         0x3000240,
  78453         SOC_REG_FLAG_ARRAY |
  78454                           SOC_REG_FLAG_RO,
  78455         0,
  78456         1,
  78457         soc_OP_EX_QUEUE_MIN_COUNT_CELLr_fields,
  78458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78459         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78460         -1,
  78461         38,
  78462     },
  78463 #endif /* chips */
  78464 
  78465 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  78466     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  78467     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_PACKETr */
  78468         soc_block_list[4],
  78469         soc_portreg,
  78470         48,
  78471         0,
  78472         0x3000300,
  78473         SOC_REG_FLAG_ARRAY |
  78474                           SOC_REG_FLAG_RO,
  78475         0,
  78476         1,
  78477         soc_OP_QUEUE_MIN_COUNT_PACKETr_fields,
  78478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78479         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78480         -1,
  78481         0,
  78482     },
  78483 #endif /* chips */
  78484 
  78485 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  78486     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_PACKET_BCM56334_A0r */
  78487         soc_block_list[4],
  78488         soc_portreg,
  78489         48,
  78490         0,
  78491         0x3000300,
  78492         SOC_REG_FLAG_ARRAY |
  78493                           SOC_REG_FLAG_RO,
  78494         0,
  78495         1,
  78496         soc_OP_QUEUE_MIN_COUNT_PACKET_BCM56334_A0r_fields,
  78497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78498         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  78499         -1,
  78500         28,
  78501     },
  78502 #endif /* chips */
  78503 
  78504 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  78505     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  78506     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  78507     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_PACKET_BCM56634_A0r */
  78508         soc_block_list[4],
  78509         soc_portreg,
  78510         48,
  78511         0,
  78512         0x3000300,
  78513         SOC_REG_FLAG_ARRAY |
  78514                           SOC_REG_FLAG_RO,
  78515         0,
  78516         1,
  78517         soc_OP_QUEUE_MIN_COUNT_PACKETr_fields,
  78518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78519         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78520         -1,
  78521         12,
  78522     },
  78523 #endif /* chips */
  78524 
  78525 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78526     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDOEMAr */
  78527         soc_block_list[4],
  78528         soc_genreg,
  78529         8,
  78530         0,
  78531         0x2e080047,
  78532         SOC_REG_FLAG_ARRAY |
  78533                           SOC_REG_FLAG_RO,
  78534         0,
  78535         1,
  78536         soc_OP_QUEUE_MIN_COUNT_BCM56820_A0r_fields,
  78537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78538         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78539         -1,
  78540         -1,
  78541     },
  78542 #endif /* chips */
  78543 
  78544 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78545     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDOEMA_BCM56260_A0r */
  78546         soc_block_list[4],
  78547         soc_genreg,
  78548         8,
  78549         0,
  78550         0xba004700,
  78551         SOC_REG_FLAG_ARRAY |
  78552                           SOC_REG_FLAG_RO,
  78553         0,
  78554         1,
  78555         soc_OP_QUEUE_MIN_COUNT_THDOEMA_BCM56260_A0r_fields,
  78556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78557         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  78558         -1,
  78559         -1,
  78560     },
  78561 #endif /* chips */
  78562 
  78563 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78564     defined(BCM_56450_B1)
  78565     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDOEMA_BCM56450_A0r */
  78566         soc_block_list[4],
  78567         soc_genreg,
  78568         8,
  78569         0,
  78570         0xba004700,
  78571         SOC_REG_FLAG_ARRAY |
  78572                           SOC_REG_FLAG_RO,
  78573         0,
  78574         1,
  78575         soc_OP_QUEUE_MIN_COUNT_THDOEMAr_fields,
  78576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78577         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78578         -1,
  78579         -1,
  78580     },
  78581 #endif /* chips */
  78582 
  78583 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78584     defined(BCM_56450_B1)
  78585     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORDEEr */
  78586         soc_block_list[4],
  78587         soc_genreg,
  78588         8,
  78589         0,
  78590         0xc6004700,
  78591         SOC_REG_FLAG_ARRAY |
  78592                           SOC_REG_FLAG_RO,
  78593         0,
  78594         1,
  78595         soc_OP_QUEUE_MIN_COUNT_THDORDEEr_fields,
  78596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78597         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  78598         -1,
  78599         -1,
  78600     },
  78601 #endif /* chips */
  78602 
  78603 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78604     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORDEE_BCM56260_A0r */
  78605         soc_block_list[4],
  78606         soc_genreg,
  78607         8,
  78608         0,
  78609         0xc6004700,
  78610         SOC_REG_FLAG_ARRAY |
  78611                           SOC_REG_FLAG_RO,
  78612         0,
  78613         1,
  78614         soc_OP_QUEUE_MIN_COUNT_THDORDEE_BCM56260_A0r_fields,
  78615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78616         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78617         -1,
  78618         -1,
  78619     },
  78620 #endif /* chips */
  78621 
  78622 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78623     defined(BCM_56450_B1)
  78624     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORDEIr */
  78625         soc_block_list[4],
  78626         soc_genreg,
  78627         8,
  78628         0,
  78629         0xc2004700,
  78630         SOC_REG_FLAG_ARRAY |
  78631                           SOC_REG_FLAG_RO,
  78632         0,
  78633         1,
  78634         soc_OP_QUEUE_MIN_COUNT_THDOEMAr_fields,
  78635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78636         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78637         -1,
  78638         -1,
  78639     },
  78640 #endif /* chips */
  78641 
  78642 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  78643     defined(BCM_56270_A0)
  78644     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORDEI_BCM56260_A0r */
  78645         soc_block_list[4],
  78646         soc_genreg,
  78647         8,
  78648         0,
  78649         0xc2004700,
  78650         SOC_REG_FLAG_ARRAY |
  78651                           SOC_REG_FLAG_RO,
  78652         0,
  78653         1,
  78654         soc_OP_QUEUE_MIN_COUNT_THDORDEIr_fields,
  78655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78656         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78657         -1,
  78658         -1,
  78659     },
  78660 #endif /* chips */
  78661 
  78662 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78663     defined(BCM_56450_B1)
  78664     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORDEQr */
  78665         soc_block_list[4],
  78666         soc_genreg,
  78667         16,
  78668         0,
  78669         0xca008700,
  78670         SOC_REG_FLAG_ARRAY |
  78671                           SOC_REG_FLAG_RO,
  78672         0,
  78673         1,
  78674         soc_OP_QUEUE_MIN_COUNT_THDORDEQr_fields,
  78675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78676         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  78677         -1,
  78678         -1,
  78679     },
  78680 #endif /* chips */
  78681 
  78682 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78683     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORDEQ_BCM56260_A0r */
  78684         soc_block_list[4],
  78685         soc_genreg,
  78686         16,
  78687         0,
  78688         0xca008700,
  78689         SOC_REG_FLAG_ARRAY |
  78690                           SOC_REG_FLAG_RO,
  78691         0,
  78692         1,
  78693         soc_OP_QUEUE_MIN_COUNT_THDORDEQ_BCM56260_A0r_fields,
  78694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78695         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  78696         -1,
  78697         -1,
  78698     },
  78699 #endif /* chips */
  78700 
  78701 #if defined(BCM_56270_A0)
  78702     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORDEQ_BCM56270_A0r */
  78703         soc_block_list[4],
  78704         soc_genreg,
  78705         8,
  78706         0,
  78707         0xca004700,
  78708         SOC_REG_FLAG_ARRAY |
  78709                           SOC_REG_FLAG_RO,
  78710         0,
  78711         1,
  78712         soc_OP_QUEUE_MIN_COUNT_THDORDEQ_BCM56260_A0r_fields,
  78713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78714         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  78715         -1,
  78716         -1,
  78717     },
  78718 #endif /* chips */
  78719 
  78720 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78721     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORQEEr */
  78722         soc_block_list[4],
  78723         soc_genreg,
  78724         12,
  78725         0,
  78726         0x2c080067,
  78727         SOC_REG_FLAG_ARRAY |
  78728                           SOC_REG_FLAG_RO,
  78729         0,
  78730         1,
  78731         soc_OP_QUEUE_MIN_COUNT_THDORQEEr_fields,
  78732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78733         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  78734         -1,
  78735         -1,
  78736     },
  78737 #endif /* chips */
  78738 
  78739 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78740     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORQEE_BCM56260_A0r */
  78741         soc_block_list[4],
  78742         soc_genreg,
  78743         12,
  78744         0,
  78745         0xb2006700,
  78746         SOC_REG_FLAG_ARRAY |
  78747                           SOC_REG_FLAG_RO,
  78748         0,
  78749         1,
  78750         soc_OP_QUEUE_MIN_COUNT_THDORDEE_BCM56260_A0r_fields,
  78751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78752         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78753         -1,
  78754         -1,
  78755     },
  78756 #endif /* chips */
  78757 
  78758 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78759     defined(BCM_56450_B1)
  78760     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORQEE_BCM56450_A0r */
  78761         soc_block_list[4],
  78762         soc_genreg,
  78763         12,
  78764         0,
  78765         0xb2006700,
  78766         SOC_REG_FLAG_ARRAY |
  78767                           SOC_REG_FLAG_RO,
  78768         0,
  78769         1,
  78770         soc_OP_QUEUE_MIN_COUNT_THDORDEEr_fields,
  78771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78772         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  78773         -1,
  78774         -1,
  78775     },
  78776 #endif /* chips */
  78777 
  78778 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78779     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORQEIr */
  78780         soc_block_list[4],
  78781         soc_genreg,
  78782         12,
  78783         0,
  78784         0x2b080067,
  78785         SOC_REG_FLAG_ARRAY |
  78786                           SOC_REG_FLAG_RO,
  78787         0,
  78788         1,
  78789         soc_OP_QUEUE_MIN_COUNT_BCM56820_A0r_fields,
  78790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78791         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78792         -1,
  78793         -1,
  78794     },
  78795 #endif /* chips */
  78796 
  78797 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  78798     defined(BCM_56270_A0)
  78799     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORQEI_BCM56260_A0r */
  78800         soc_block_list[4],
  78801         soc_genreg,
  78802         12,
  78803         0,
  78804         0xae006700,
  78805         SOC_REG_FLAG_ARRAY |
  78806                           SOC_REG_FLAG_RO,
  78807         0,
  78808         1,
  78809         soc_OP_QUEUE_MIN_COUNT_THDORDEIr_fields,
  78810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78811         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78812         -1,
  78813         -1,
  78814     },
  78815 #endif /* chips */
  78816 
  78817 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78818     defined(BCM_56450_B1)
  78819     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORQEI_BCM56450_A0r */
  78820         soc_block_list[4],
  78821         soc_genreg,
  78822         12,
  78823         0,
  78824         0xae006700,
  78825         SOC_REG_FLAG_ARRAY |
  78826                           SOC_REG_FLAG_RO,
  78827         0,
  78828         1,
  78829         soc_OP_QUEUE_MIN_COUNT_THDOEMAr_fields,
  78830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78831         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  78832         -1,
  78833         -1,
  78834     },
  78835 #endif /* chips */
  78836 
  78837 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78838     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORQEQr */
  78839         soc_block_list[4],
  78840         soc_genreg,
  78841         12,
  78842         0,
  78843         0x2d080067,
  78844         SOC_REG_FLAG_ARRAY |
  78845                           SOC_REG_FLAG_RO,
  78846         0,
  78847         1,
  78848         soc_OP_QUEUE_MIN_COUNT_THDORQEQr_fields,
  78849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78850         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  78851         -1,
  78852         -1,
  78853     },
  78854 #endif /* chips */
  78855 
  78856 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  78857     defined(BCM_56270_A0)
  78858     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORQEQ_BCM56260_A0r */
  78859         soc_block_list[4],
  78860         soc_genreg,
  78861         12,
  78862         0,
  78863         0xb6006700,
  78864         SOC_REG_FLAG_ARRAY |
  78865                           SOC_REG_FLAG_RO,
  78866         0,
  78867         1,
  78868         soc_OP_QUEUE_MIN_COUNT_THDORQEQ_BCM56260_A0r_fields,
  78869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78870         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  78871         -1,
  78872         -1,
  78873     },
  78874 #endif /* chips */
  78875 
  78876 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78877     defined(BCM_56450_B1)
  78878     { /* SOC_REG_INT_OP_QUEUE_MIN_COUNT_THDORQEQ_BCM56450_A0r */
  78879         soc_block_list[4],
  78880         soc_genreg,
  78881         12,
  78882         0,
  78883         0xb6006700,
  78884         SOC_REG_FLAG_ARRAY |
  78885                           SOC_REG_FLAG_RO,
  78886         0,
  78887         1,
  78888         soc_OP_QUEUE_MIN_COUNT_THDORQEQ_BCM56450_A0r_fields,
  78889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78890         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  78891         -1,
  78892         -1,
  78893     },
  78894 #endif /* chips */
  78895 
  78896 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  78897     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  78898     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  78899     { /* SOC_REG_INT_OP_QUEUE_REDIRECT_CONFIG_CELLr */
  78900         soc_block_list[4],
  78901         soc_portreg,
  78902         8,
  78903         0,
  78904         0x30005c0,
  78905         SOC_REG_FLAG_ARRAY,
  78906         0,
  78907         4,
  78908         soc_OP_QUEUE_FIRST_FRAGMENT_CONFIG_CELLr_fields,
  78909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78910         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  78911         -1,
  78912         14,
  78913     },
  78914 #endif /* chips */
  78915 
  78916 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  78917     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  78918     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  78919     { /* SOC_REG_INT_OP_QUEUE_REDIRECT_CONFIG_PACKETr */
  78920         soc_block_list[4],
  78921         soc_portreg,
  78922         8,
  78923         0,
  78924         0x30005d0,
  78925         SOC_REG_FLAG_ARRAY,
  78926         0,
  78927         4,
  78928         soc_OP_QUEUE_REDIRECT_CONFIG_PACKETr_fields,
  78929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78930         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  78931         -1,
  78932         14,
  78933     },
  78934 #endif /* chips */
  78935 
  78936 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  78937     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  78938     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  78939     { /* SOC_REG_INT_OP_QUEUE_REDIRECT_COUNT_CELLr */
  78940         soc_block_list[4],
  78941         soc_portreg,
  78942         8,
  78943         0,
  78944         0x30005e0,
  78945         SOC_REG_FLAG_ARRAY |
  78946                           SOC_REG_FLAG_RO,
  78947         0,
  78948         1,
  78949         soc_OP_PORT_FIRST_FRAGMENT_COUNT_CELLr_fields,
  78950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78951         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  78952         -1,
  78953         14,
  78954     },
  78955 #endif /* chips */
  78956 
  78957 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  78958     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  78959     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  78960     { /* SOC_REG_INT_OP_QUEUE_REDIRECT_COUNT_PACKETr */
  78961         soc_block_list[4],
  78962         soc_portreg,
  78963         8,
  78964         0,
  78965         0x30005e8,
  78966         SOC_REG_FLAG_ARRAY |
  78967                           SOC_REG_FLAG_RO,
  78968         0,
  78969         1,
  78970         soc_OP_PORT_REDIRECT_COUNT_PACKETr_fields,
  78971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78972         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78973         -1,
  78974         14,
  78975     },
  78976 #endif /* chips */
  78977 
  78978 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  78979     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  78980     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  78981     { /* SOC_REG_INT_OP_QUEUE_REDIRECT_RESET_OFFSET_CELLr */
  78982         soc_block_list[4],
  78983         soc_portreg,
  78984         8,
  78985         0,
  78986         0x30005c8,
  78987         SOC_REG_FLAG_ARRAY,
  78988         0,
  78989         1,
  78990         soc_OP_QUEUE_FIRST_FRAGMENT_RESET_OFFSET_CELLr_fields,
  78991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78992         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  78993         -1,
  78994         14,
  78995     },
  78996 #endif /* chips */
  78997 
  78998 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  78999     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  79000     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  79001     { /* SOC_REG_INT_OP_QUEUE_REDIRECT_RESET_OFFSET_PACKETr */
  79002         soc_block_list[4],
  79003         soc_portreg,
  79004         8,
  79005         0,
  79006         0x30005d8,
  79007         SOC_REG_FLAG_ARRAY,
  79008         0,
  79009         1,
  79010         soc_OP_QUEUE_REDIRECT_RESET_OFFSET_PACKETr_fields,
  79011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79012         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79013         -1,
  79014         14,
  79015     },
  79016 #endif /* chips */
  79017 
  79018 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  79019     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  79020     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  79021     { /* SOC_REG_INT_OP_QUEUE_REDIRECT_XQ_CONFIG_PACKETr */
  79022         soc_block_list[4],
  79023         soc_portreg,
  79024         8,
  79025         0,
  79026         0x3000600,
  79027         SOC_REG_FLAG_ARRAY,
  79028         0,
  79029         4,
  79030         soc_OP_QUEUE_REDIRECT_CONFIG_PACKETr_fields,
  79031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79032         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  79033         -1,
  79034         14,
  79035     },
  79036 #endif /* chips */
  79037 
  79038 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  79039     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  79040     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  79041     { /* SOC_REG_INT_OP_QUEUE_REDIRECT_XQ_COUNT_PACKETr */
  79042         soc_block_list[4],
  79043         soc_portreg,
  79044         8,
  79045         0,
  79046         0x3000610,
  79047         SOC_REG_FLAG_ARRAY |
  79048                           SOC_REG_FLAG_RO,
  79049         0,
  79050         1,
  79051         soc_OP_PORT_REDIRECT_COUNT_PACKETr_fields,
  79052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79053         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79054         -1,
  79055         14,
  79056     },
  79057 #endif /* chips */
  79058 
  79059 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  79060     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  79061     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  79062     { /* SOC_REG_INT_OP_QUEUE_REDIRECT_XQ_RESET_OFFSET_PACKETr */
  79063         soc_block_list[4],
  79064         soc_portreg,
  79065         8,
  79066         0,
  79067         0x3000608,
  79068         SOC_REG_FLAG_ARRAY,
  79069         0,
  79070         1,
  79071         soc_OP_QUEUE_REDIRECT_RESET_OFFSET_PACKETr_fields,
  79072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79073         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79074         -1,
  79075         14,
  79076     },
  79077 #endif /* chips */
  79078 
  79079 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  79080     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSETr */
  79081         soc_block_list[4],
  79082         soc_portreg,
  79083         32,
  79084         0,
  79085         0x3000080,
  79086         SOC_REG_FLAG_ARRAY,
  79087         0,
  79088         1,
  79089         soc_OP_QUEUE_RESET_OFFSETr_fields,
  79090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79091         SOC_RESET_MASK_DEC(0x00003ff0, 0x00000000)
  79092         -1,
  79093         9,
  79094     },
  79095 #endif /* chips */
  79096 
  79097 #if defined(BCM_88732_A0)
  79098     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_BCM88732_A0r */
  79099         soc_block_list[4],
  79100         soc_portreg,
  79101         10,
  79102         0,
  79103         0x3000080,
  79104         SOC_REG_FLAG_ARRAY,
  79105         0,
  79106         1,
  79107         soc_OP_QUEUE_RESET_OFFSET_BCM88732_A0r_fields,
  79108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79109         SOC_RESET_MASK_DEC(0x0001fff0, 0x00000000)
  79110         -1,
  79111         49,
  79112     },
  79113 #endif /* chips */
  79114 
  79115 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  79116     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  79117     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_CELLr */
  79118         soc_block_list[4],
  79119         soc_portreg,
  79120         48,
  79121         0,
  79122         0x3000240,
  79123         SOC_REG_FLAG_ARRAY,
  79124         0,
  79125         1,
  79126         soc_OP_QUEUE_RESET_OFFSET_CELLr_fields,
  79127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79128         SOC_RESET_MASK_DEC(0x00007ff0, 0x00000000)
  79129         -1,
  79130         0,
  79131     },
  79132 #endif /* chips */
  79133 
  79134 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  79135     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_CELL_BCM56334_A0r */
  79136         soc_block_list[4],
  79137         soc_portreg,
  79138         48,
  79139         0,
  79140         0x3000240,
  79141         SOC_REG_FLAG_ARRAY,
  79142         0,
  79143         1,
  79144         soc_OP_QUEUE_RESET_OFFSET_CELL_BCM56334_A0r_fields,
  79145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79146         SOC_RESET_MASK_DEC(0x00003ff0, 0x00000000)
  79147         -1,
  79148         28,
  79149     },
  79150 #endif /* chips */
  79151 
  79152 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  79153     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  79154     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  79155     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_CELL_BCM56634_A0r */
  79156         soc_block_list[4],
  79157         soc_portreg,
  79158         48,
  79159         0,
  79160         0x3000240,
  79161         SOC_REG_FLAG_ARRAY,
  79162         0,
  79163         1,
  79164         soc_OP_QUEUE_RESET_OFFSET_CELL_BCM56634_A0r_fields,
  79165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79166         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79167         -1,
  79168         12,
  79169     },
  79170 #endif /* chips */
  79171 
  79172 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  79173     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_CELL_BCM56640_A0r */
  79174         soc_block_list[4],
  79175         soc_portreg,
  79176         48,
  79177         0,
  79178         0xc020000,
  79179         SOC_REG_FLAG_ARRAY,
  79180         0,
  79181         1,
  79182         soc_OP_QUEUE_RESET_OFFSET_CELL_BCM56640_A0r_fields,
  79183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79184         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  79185         -1,
  79186         62,
  79187     },
  79188 #endif /* chips */
  79189 
  79190 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  79191     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_CELL_BCM56840_A0r */
  79192         soc_block_list[4],
  79193         soc_portreg,
  79194         48,
  79195         0,
  79196         0x3000200,
  79197         SOC_REG_FLAG_ARRAY,
  79198         0,
  79199         1,
  79200         soc_OP_QUEUE_RESET_OFFSET_CELL_BCM56840_A0r_fields,
  79201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79202         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  79203         -1,
  79204         38,
  79205     },
  79206 #endif /* chips */
  79207 
  79208 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  79209     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  79210     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_PACKETr */
  79211         soc_block_list[4],
  79212         soc_portreg,
  79213         48,
  79214         0,
  79215         0x3000280,
  79216         SOC_REG_FLAG_ARRAY,
  79217         0,
  79218         1,
  79219         soc_OP_QUEUE_RESET_OFFSET_PACKETr_fields,
  79220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79221         SOC_RESET_MASK_DEC(0x00000ffc, 0x00000000)
  79222         -1,
  79223         0,
  79224     },
  79225 #endif /* chips */
  79226 
  79227 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  79228     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_PACKET_BCM56334_A0r */
  79229         soc_block_list[4],
  79230         soc_portreg,
  79231         48,
  79232         0,
  79233         0x3000280,
  79234         SOC_REG_FLAG_ARRAY,
  79235         0,
  79236         1,
  79237         soc_OP_QUEUE_RESET_OFFSET_PACKETr_fields,
  79238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79239         SOC_RESET_MASK_DEC(0x00000ffc, 0x00000000)
  79240         -1,
  79241         28,
  79242     },
  79243 #endif /* chips */
  79244 
  79245 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  79246     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  79247     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  79248     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_PACKET_BCM56634_A0r */
  79249         soc_block_list[4],
  79250         soc_portreg,
  79251         48,
  79252         0,
  79253         0x3000280,
  79254         SOC_REG_FLAG_ARRAY,
  79255         0,
  79256         1,
  79257         soc_OP_QUEUE_RESET_OFFSET_PACKET_BCM56634_A0r_fields,
  79258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79259         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  79260         -1,
  79261         12,
  79262     },
  79263 #endif /* chips */
  79264 
  79265 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79266     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDOEMAr */
  79267         soc_block_list[4],
  79268         soc_genreg,
  79269         8,
  79270         0,
  79271         0x2e08003f,
  79272         SOC_REG_FLAG_ARRAY,
  79273         0,
  79274         1,
  79275         soc_OP_QUEUE_RESET_OFFSET_RED_THDOEMAr_fields,
  79276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79277         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79278         -1,
  79279         -1,
  79280     },
  79281 #endif /* chips */
  79282 
  79283 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79284     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDOEMA_BCM56260_A0r */
  79285         soc_block_list[4],
  79286         soc_genreg,
  79287         8,
  79288         0,
  79289         0xba003f00,
  79290         SOC_REG_FLAG_ARRAY,
  79291         0,
  79292         1,
  79293         soc_OP_QUEUE_RESET_OFFSET_RED_THDOEMA_BCM56260_A0r_fields,
  79294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79295         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  79296         -1,
  79297         -1,
  79298     },
  79299 #endif /* chips */
  79300 
  79301 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79302     defined(BCM_56450_B1)
  79303     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDOEMA_BCM56450_A0r */
  79304         soc_block_list[4],
  79305         soc_genreg,
  79306         8,
  79307         0,
  79308         0xba003f00,
  79309         SOC_REG_FLAG_ARRAY,
  79310         0,
  79311         1,
  79312         soc_OP_QUEUE_RESET_OFFSET_RED_THDOEMA_BCM56450_A0r_fields,
  79313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79314         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79315         -1,
  79316         -1,
  79317     },
  79318 #endif /* chips */
  79319 
  79320 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79321     defined(BCM_56450_B1)
  79322     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORDEEr */
  79323         soc_block_list[4],
  79324         soc_genreg,
  79325         8,
  79326         0,
  79327         0xc6003f00,
  79328         SOC_REG_FLAG_ARRAY,
  79329         0,
  79330         1,
  79331         soc_OP_QUEUE_RESET_OFFSET_RED_THDORDEEr_fields,
  79332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79333         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  79334         -1,
  79335         -1,
  79336     },
  79337 #endif /* chips */
  79338 
  79339 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79340     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORDEE_BCM56260_A0r */
  79341         soc_block_list[4],
  79342         soc_genreg,
  79343         8,
  79344         0,
  79345         0xc6003f00,
  79346         SOC_REG_FLAG_ARRAY,
  79347         0,
  79348         1,
  79349         soc_OP_QUEUE_RESET_OFFSET_RED_THDORDEE_BCM56260_A0r_fields,
  79350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79351         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  79352         -1,
  79353         -1,
  79354     },
  79355 #endif /* chips */
  79356 
  79357 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79358     defined(BCM_56450_B1)
  79359     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORDEIr */
  79360         soc_block_list[4],
  79361         soc_genreg,
  79362         8,
  79363         0,
  79364         0xc2003f00,
  79365         SOC_REG_FLAG_ARRAY,
  79366         0,
  79367         1,
  79368         soc_OP_QUEUE_RESET_OFFSET_RED_THDOEMA_BCM56450_A0r_fields,
  79369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79370         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79371         -1,
  79372         -1,
  79373     },
  79374 #endif /* chips */
  79375 
  79376 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  79377     defined(BCM_56270_A0)
  79378     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORDEI_BCM56260_A0r */
  79379         soc_block_list[4],
  79380         soc_genreg,
  79381         8,
  79382         0,
  79383         0xc2003f00,
  79384         SOC_REG_FLAG_ARRAY,
  79385         0,
  79386         1,
  79387         soc_OP_QUEUE_RESET_OFFSET_RED_THDORDEIr_fields,
  79388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79389         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79390         -1,
  79391         -1,
  79392     },
  79393 #endif /* chips */
  79394 
  79395 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79396     defined(BCM_56450_B1)
  79397     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORDEQr */
  79398         soc_block_list[4],
  79399         soc_genreg,
  79400         16,
  79401         0,
  79402         0xca007700,
  79403         SOC_REG_FLAG_ARRAY,
  79404         0,
  79405         1,
  79406         soc_OP_QUEUE_RESET_OFFSET_RED_THDORDEQr_fields,
  79407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79408         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  79409         -1,
  79410         -1,
  79411     },
  79412 #endif /* chips */
  79413 
  79414 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79415     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORDEQ_BCM56260_A0r */
  79416         soc_block_list[4],
  79417         soc_genreg,
  79418         16,
  79419         0,
  79420         0xca007700,
  79421         SOC_REG_FLAG_ARRAY,
  79422         0,
  79423         1,
  79424         soc_OP_QUEUE_RESET_OFFSET_RED_THDORDEQ_BCM56260_A0r_fields,
  79425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79426         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  79427         -1,
  79428         -1,
  79429     },
  79430 #endif /* chips */
  79431 
  79432 #if defined(BCM_56270_A0)
  79433     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORDEQ_BCM56270_A0r */
  79434         soc_block_list[4],
  79435         soc_genreg,
  79436         8,
  79437         0,
  79438         0xca003f00,
  79439         SOC_REG_FLAG_ARRAY,
  79440         0,
  79441         1,
  79442         soc_OP_QUEUE_RESET_OFFSET_RED_THDORDEQ_BCM56260_A0r_fields,
  79443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79444         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  79445         -1,
  79446         -1,
  79447     },
  79448 #endif /* chips */
  79449 
  79450 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79451     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORQEEr */
  79452         soc_block_list[4],
  79453         soc_genreg,
  79454         12,
  79455         0,
  79456         0x2c08005b,
  79457         SOC_REG_FLAG_ARRAY,
  79458         0,
  79459         1,
  79460         soc_OP_QUEUE_RESET_OFFSET_RED_THDORQEEr_fields,
  79461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79462         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  79463         -1,
  79464         -1,
  79465     },
  79466 #endif /* chips */
  79467 
  79468 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79469     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORQEE_BCM56260_A0r */
  79470         soc_block_list[4],
  79471         soc_genreg,
  79472         12,
  79473         0,
  79474         0xb2005b00,
  79475         SOC_REG_FLAG_ARRAY,
  79476         0,
  79477         1,
  79478         soc_OP_QUEUE_RESET_OFFSET_RED_THDORDEE_BCM56260_A0r_fields,
  79479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79480         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  79481         -1,
  79482         -1,
  79483     },
  79484 #endif /* chips */
  79485 
  79486 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79487     defined(BCM_56450_B1)
  79488     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORQEE_BCM56450_A0r */
  79489         soc_block_list[4],
  79490         soc_genreg,
  79491         12,
  79492         0,
  79493         0xb2005b00,
  79494         SOC_REG_FLAG_ARRAY,
  79495         0,
  79496         1,
  79497         soc_OP_QUEUE_RESET_OFFSET_RED_THDORDEEr_fields,
  79498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79499         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  79500         -1,
  79501         -1,
  79502     },
  79503 #endif /* chips */
  79504 
  79505 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79506     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORQEIr */
  79507         soc_block_list[4],
  79508         soc_genreg,
  79509         12,
  79510         0,
  79511         0x2b08005b,
  79512         SOC_REG_FLAG_ARRAY,
  79513         0,
  79514         1,
  79515         soc_OP_QUEUE_RESET_OFFSET_RED_THDOEMAr_fields,
  79516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79517         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79518         -1,
  79519         -1,
  79520     },
  79521 #endif /* chips */
  79522 
  79523 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  79524     defined(BCM_56270_A0)
  79525     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORQEI_BCM56260_A0r */
  79526         soc_block_list[4],
  79527         soc_genreg,
  79528         12,
  79529         0,
  79530         0xae005b00,
  79531         SOC_REG_FLAG_ARRAY,
  79532         0,
  79533         1,
  79534         soc_OP_QUEUE_RESET_OFFSET_RED_THDORDEIr_fields,
  79535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79536         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79537         -1,
  79538         -1,
  79539     },
  79540 #endif /* chips */
  79541 
  79542 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79543     defined(BCM_56450_B1)
  79544     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORQEI_BCM56450_A0r */
  79545         soc_block_list[4],
  79546         soc_genreg,
  79547         12,
  79548         0,
  79549         0xae005b00,
  79550         SOC_REG_FLAG_ARRAY,
  79551         0,
  79552         1,
  79553         soc_OP_QUEUE_RESET_OFFSET_RED_THDOEMA_BCM56450_A0r_fields,
  79554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79555         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79556         -1,
  79557         -1,
  79558     },
  79559 #endif /* chips */
  79560 
  79561 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79562     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr */
  79563         soc_block_list[4],
  79564         soc_genreg,
  79565         12,
  79566         0,
  79567         0x2d08005b,
  79568         SOC_REG_FLAG_ARRAY,
  79569         0,
  79570         1,
  79571         soc_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr_fields,
  79572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79573         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  79574         -1,
  79575         -1,
  79576     },
  79577 #endif /* chips */
  79578 
  79579 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  79580     defined(BCM_56270_A0)
  79581     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORQEQ_BCM56260_A0r */
  79582         soc_block_list[4],
  79583         soc_genreg,
  79584         12,
  79585         0,
  79586         0xb6005b00,
  79587         SOC_REG_FLAG_ARRAY,
  79588         0,
  79589         1,
  79590         soc_OP_QUEUE_RESET_OFFSET_RED_THDORQEQ_BCM56260_A0r_fields,
  79591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79592         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  79593         -1,
  79594         -1,
  79595     },
  79596 #endif /* chips */
  79597 
  79598 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79599     defined(BCM_56450_B1)
  79600     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_RED_THDORQEQ_BCM56450_A0r */
  79601         soc_block_list[4],
  79602         soc_genreg,
  79603         12,
  79604         0,
  79605         0xb6005b00,
  79606         SOC_REG_FLAG_ARRAY,
  79607         0,
  79608         1,
  79609         soc_OP_QUEUE_RESET_OFFSET_RED_THDORQEQ_BCM56450_A0r_fields,
  79610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79611         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  79612         -1,
  79613         -1,
  79614     },
  79615 #endif /* chips */
  79616 
  79617 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79618     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDOEMAr */
  79619         soc_block_list[4],
  79620         soc_genreg,
  79621         8,
  79622         0,
  79623         0x2e08002f,
  79624         SOC_REG_FLAG_ARRAY,
  79625         0,
  79626         1,
  79627         soc_OP_QUEUE_RESET_OFFSET_THDOEMAr_fields,
  79628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79629         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  79630         -1,
  79631         -1,
  79632     },
  79633 #endif /* chips */
  79634 
  79635 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79636     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDOEMA_BCM56260_A0r */
  79637         soc_block_list[4],
  79638         soc_genreg,
  79639         8,
  79640         0,
  79641         0xba002f00,
  79642         SOC_REG_FLAG_ARRAY,
  79643         0,
  79644         1,
  79645         soc_OP_QUEUE_RESET_OFFSET_THDOEMA_BCM56260_A0r_fields,
  79646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79647         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  79648         -1,
  79649         -1,
  79650     },
  79651 #endif /* chips */
  79652 
  79653 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79654     defined(BCM_56450_B1)
  79655     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDOEMA_BCM56450_A0r */
  79656         soc_block_list[4],
  79657         soc_genreg,
  79658         8,
  79659         0,
  79660         0xba002f00,
  79661         SOC_REG_FLAG_ARRAY,
  79662         0,
  79663         1,
  79664         soc_OP_QUEUE_RESET_OFFSET_THDOEMA_BCM56450_A0r_fields,
  79665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79666         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  79667         -1,
  79668         -1,
  79669     },
  79670 #endif /* chips */
  79671 
  79672 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79673     defined(BCM_56450_B1)
  79674     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORDEEr */
  79675         soc_block_list[4],
  79676         soc_genreg,
  79677         8,
  79678         0,
  79679         0xc6002f00,
  79680         SOC_REG_FLAG_ARRAY,
  79681         0,
  79682         1,
  79683         soc_OP_QUEUE_RESET_OFFSET_THDORDEEr_fields,
  79684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79685         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  79686         -1,
  79687         -1,
  79688     },
  79689 #endif /* chips */
  79690 
  79691 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79692     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORDEE_BCM56260_A0r */
  79693         soc_block_list[4],
  79694         soc_genreg,
  79695         8,
  79696         0,
  79697         0xc6002f00,
  79698         SOC_REG_FLAG_ARRAY,
  79699         0,
  79700         1,
  79701         soc_OP_QUEUE_RESET_OFFSET_THDORDEE_BCM56260_A0r_fields,
  79702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79703         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79704         -1,
  79705         -1,
  79706     },
  79707 #endif /* chips */
  79708 
  79709 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79710     defined(BCM_56450_B1)
  79711     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORDEIr */
  79712         soc_block_list[4],
  79713         soc_genreg,
  79714         8,
  79715         0,
  79716         0xc2002f00,
  79717         SOC_REG_FLAG_ARRAY,
  79718         0,
  79719         1,
  79720         soc_OP_QUEUE_RESET_OFFSET_THDOEMA_BCM56450_A0r_fields,
  79721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79722         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  79723         -1,
  79724         -1,
  79725     },
  79726 #endif /* chips */
  79727 
  79728 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  79729     defined(BCM_56270_A0)
  79730     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORDEI_BCM56260_A0r */
  79731         soc_block_list[4],
  79732         soc_genreg,
  79733         8,
  79734         0,
  79735         0xc2002f00,
  79736         SOC_REG_FLAG_ARRAY,
  79737         0,
  79738         1,
  79739         soc_OP_QUEUE_RESET_OFFSET_THDORDEIr_fields,
  79740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79741         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  79742         -1,
  79743         -1,
  79744     },
  79745 #endif /* chips */
  79746 
  79747 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79748     defined(BCM_56450_B1)
  79749     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORDEQr */
  79750         soc_block_list[4],
  79751         soc_genreg,
  79752         16,
  79753         0,
  79754         0xca005700,
  79755         SOC_REG_FLAG_ARRAY,
  79756         0,
  79757         1,
  79758         soc_OP_QUEUE_RESET_OFFSET_THDORDEQr_fields,
  79759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79760         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  79761         -1,
  79762         -1,
  79763     },
  79764 #endif /* chips */
  79765 
  79766 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79767     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORDEQ_BCM56260_A0r */
  79768         soc_block_list[4],
  79769         soc_genreg,
  79770         16,
  79771         0,
  79772         0xca005700,
  79773         SOC_REG_FLAG_ARRAY,
  79774         0,
  79775         1,
  79776         soc_OP_QUEUE_RESET_OFFSET_THDORDEQ_BCM56260_A0r_fields,
  79777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79778         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  79779         -1,
  79780         -1,
  79781     },
  79782 #endif /* chips */
  79783 
  79784 #if defined(BCM_56270_A0)
  79785     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORDEQ_BCM56270_A0r */
  79786         soc_block_list[4],
  79787         soc_genreg,
  79788         8,
  79789         0,
  79790         0xca002f00,
  79791         SOC_REG_FLAG_ARRAY,
  79792         0,
  79793         1,
  79794         soc_OP_QUEUE_RESET_OFFSET_THDORDEQ_BCM56260_A0r_fields,
  79795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79796         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  79797         -1,
  79798         -1,
  79799     },
  79800 #endif /* chips */
  79801 
  79802 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79803     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORQEEr */
  79804         soc_block_list[4],
  79805         soc_genreg,
  79806         12,
  79807         0,
  79808         0x2c080043,
  79809         SOC_REG_FLAG_ARRAY,
  79810         0,
  79811         1,
  79812         soc_OP_QUEUE_RESET_OFFSET_THDORQEEr_fields,
  79813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79814         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  79815         -1,
  79816         -1,
  79817     },
  79818 #endif /* chips */
  79819 
  79820 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79821     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORQEE_BCM56260_A0r */
  79822         soc_block_list[4],
  79823         soc_genreg,
  79824         12,
  79825         0,
  79826         0xb2004300,
  79827         SOC_REG_FLAG_ARRAY,
  79828         0,
  79829         1,
  79830         soc_OP_QUEUE_RESET_OFFSET_THDORDEE_BCM56260_A0r_fields,
  79831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79832         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79833         -1,
  79834         -1,
  79835     },
  79836 #endif /* chips */
  79837 
  79838 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79839     defined(BCM_56450_B1)
  79840     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORQEE_BCM56450_A0r */
  79841         soc_block_list[4],
  79842         soc_genreg,
  79843         12,
  79844         0,
  79845         0xb2004300,
  79846         SOC_REG_FLAG_ARRAY,
  79847         0,
  79848         1,
  79849         soc_OP_QUEUE_RESET_OFFSET_THDORDEEr_fields,
  79850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79851         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  79852         -1,
  79853         -1,
  79854     },
  79855 #endif /* chips */
  79856 
  79857 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79858     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORQEIr */
  79859         soc_block_list[4],
  79860         soc_genreg,
  79861         12,
  79862         0,
  79863         0x2b080043,
  79864         SOC_REG_FLAG_ARRAY,
  79865         0,
  79866         1,
  79867         soc_OP_QUEUE_RESET_OFFSET_THDOEMAr_fields,
  79868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79869         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  79870         -1,
  79871         -1,
  79872     },
  79873 #endif /* chips */
  79874 
  79875 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  79876     defined(BCM_56270_A0)
  79877     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORQEI_BCM56260_A0r */
  79878         soc_block_list[4],
  79879         soc_genreg,
  79880         12,
  79881         0,
  79882         0xae004300,
  79883         SOC_REG_FLAG_ARRAY,
  79884         0,
  79885         1,
  79886         soc_OP_QUEUE_RESET_OFFSET_THDORDEIr_fields,
  79887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79888         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  79889         -1,
  79890         -1,
  79891     },
  79892 #endif /* chips */
  79893 
  79894 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79895     defined(BCM_56450_B1)
  79896     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORQEI_BCM56450_A0r */
  79897         soc_block_list[4],
  79898         soc_genreg,
  79899         12,
  79900         0,
  79901         0xae004300,
  79902         SOC_REG_FLAG_ARRAY,
  79903         0,
  79904         1,
  79905         soc_OP_QUEUE_RESET_OFFSET_THDOEMA_BCM56450_A0r_fields,
  79906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79907         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  79908         -1,
  79909         -1,
  79910     },
  79911 #endif /* chips */
  79912 
  79913 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79914     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORQEQr */
  79915         soc_block_list[4],
  79916         soc_genreg,
  79917         12,
  79918         0,
  79919         0x2d080043,
  79920         SOC_REG_FLAG_ARRAY,
  79921         0,
  79922         1,
  79923         soc_OP_QUEUE_RESET_OFFSET_THDORQEQr_fields,
  79924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79925         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  79926         -1,
  79927         -1,
  79928     },
  79929 #endif /* chips */
  79930 
  79931 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  79932     defined(BCM_56270_A0)
  79933     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORQEQ_BCM56260_A0r */
  79934         soc_block_list[4],
  79935         soc_genreg,
  79936         12,
  79937         0,
  79938         0xb6004300,
  79939         SOC_REG_FLAG_ARRAY,
  79940         0,
  79941         1,
  79942         soc_OP_QUEUE_RESET_OFFSET_THDORQEQ_BCM56260_A0r_fields,
  79943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79944         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  79945         -1,
  79946         -1,
  79947     },
  79948 #endif /* chips */
  79949 
  79950 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79951     defined(BCM_56450_B1)
  79952     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_THDORQEQ_BCM56450_A0r */
  79953         soc_block_list[4],
  79954         soc_genreg,
  79955         12,
  79956         0,
  79957         0xb6004300,
  79958         SOC_REG_FLAG_ARRAY,
  79959         0,
  79960         1,
  79961         soc_OP_QUEUE_RESET_OFFSET_THDORQEQ_BCM56450_A0r_fields,
  79962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79963         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  79964         -1,
  79965         -1,
  79966     },
  79967 #endif /* chips */
  79968 
  79969 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79970     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr */
  79971         soc_block_list[4],
  79972         soc_genreg,
  79973         8,
  79974         0,
  79975         0x2e080037,
  79976         SOC_REG_FLAG_ARRAY,
  79977         0,
  79978         1,
  79979         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr_fields,
  79980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79981         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  79982         -1,
  79983         -1,
  79984     },
  79985 #endif /* chips */
  79986 
  79987 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79988     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMA_BCM56260_A0r */
  79989         soc_block_list[4],
  79990         soc_genreg,
  79991         8,
  79992         0,
  79993         0xba003700,
  79994         SOC_REG_FLAG_ARRAY,
  79995         0,
  79996         1,
  79997         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMA_BCM56260_A0r_fields,
  79998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79999         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  80000         -1,
  80001         -1,
  80002     },
  80003 #endif /* chips */
  80004 
  80005 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80006     defined(BCM_56450_B1)
  80007     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMA_BCM56450_A0r */
  80008         soc_block_list[4],
  80009         soc_genreg,
  80010         8,
  80011         0,
  80012         0xba003700,
  80013         SOC_REG_FLAG_ARRAY,
  80014         0,
  80015         1,
  80016         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMA_BCM56450_A0r_fields,
  80017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80018         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  80019         -1,
  80020         -1,
  80021     },
  80022 #endif /* chips */
  80023 
  80024 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80025     defined(BCM_56450_B1)
  80026     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr */
  80027         soc_block_list[4],
  80028         soc_genreg,
  80029         8,
  80030         0,
  80031         0xc6003700,
  80032         SOC_REG_FLAG_ARRAY,
  80033         0,
  80034         1,
  80035         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr_fields,
  80036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80037         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  80038         -1,
  80039         -1,
  80040     },
  80041 #endif /* chips */
  80042 
  80043 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  80044     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEE_BCM56260_A0r */
  80045         soc_block_list[4],
  80046         soc_genreg,
  80047         8,
  80048         0,
  80049         0xc6003700,
  80050         SOC_REG_FLAG_ARRAY,
  80051         0,
  80052         1,
  80053         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEE_BCM56260_A0r_fields,
  80054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80055         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  80056         -1,
  80057         -1,
  80058     },
  80059 #endif /* chips */
  80060 
  80061 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80062     defined(BCM_56450_B1)
  80063     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr */
  80064         soc_block_list[4],
  80065         soc_genreg,
  80066         8,
  80067         0,
  80068         0xc2003700,
  80069         SOC_REG_FLAG_ARRAY,
  80070         0,
  80071         1,
  80072         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMA_BCM56450_A0r_fields,
  80073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80074         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  80075         -1,
  80076         -1,
  80077     },
  80078 #endif /* chips */
  80079 
  80080 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  80081     defined(BCM_56270_A0)
  80082     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEI_BCM56260_A0r */
  80083         soc_block_list[4],
  80084         soc_genreg,
  80085         8,
  80086         0,
  80087         0xc2003700,
  80088         SOC_REG_FLAG_ARRAY,
  80089         0,
  80090         1,
  80091         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr_fields,
  80092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80093         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  80094         -1,
  80095         -1,
  80096     },
  80097 #endif /* chips */
  80098 
  80099 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80100     defined(BCM_56450_B1)
  80101     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr */
  80102         soc_block_list[4],
  80103         soc_genreg,
  80104         16,
  80105         0,
  80106         0xca006700,
  80107         SOC_REG_FLAG_ARRAY,
  80108         0,
  80109         1,
  80110         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr_fields,
  80111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80112         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  80113         -1,
  80114         -1,
  80115     },
  80116 #endif /* chips */
  80117 
  80118 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  80119     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQ_BCM56260_A0r */
  80120         soc_block_list[4],
  80121         soc_genreg,
  80122         16,
  80123         0,
  80124         0xca006700,
  80125         SOC_REG_FLAG_ARRAY,
  80126         0,
  80127         1,
  80128         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQ_BCM56260_A0r_fields,
  80129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80130         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  80131         -1,
  80132         -1,
  80133     },
  80134 #endif /* chips */
  80135 
  80136 #if defined(BCM_56270_A0)
  80137     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQ_BCM56270_A0r */
  80138         soc_block_list[4],
  80139         soc_genreg,
  80140         8,
  80141         0,
  80142         0xca003700,
  80143         SOC_REG_FLAG_ARRAY,
  80144         0,
  80145         1,
  80146         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQ_BCM56260_A0r_fields,
  80147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80148         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  80149         -1,
  80150         -1,
  80151     },
  80152 #endif /* chips */
  80153 
  80154 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80155     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr */
  80156         soc_block_list[4],
  80157         soc_genreg,
  80158         12,
  80159         0,
  80160         0x2c08004f,
  80161         SOC_REG_FLAG_ARRAY,
  80162         0,
  80163         1,
  80164         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr_fields,
  80165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80166         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  80167         -1,
  80168         -1,
  80169     },
  80170 #endif /* chips */
  80171 
  80172 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  80173     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEE_BCM56260_A0r */
  80174         soc_block_list[4],
  80175         soc_genreg,
  80176         12,
  80177         0,
  80178         0xb2004f00,
  80179         SOC_REG_FLAG_ARRAY,
  80180         0,
  80181         1,
  80182         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEE_BCM56260_A0r_fields,
  80183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80184         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  80185         -1,
  80186         -1,
  80187     },
  80188 #endif /* chips */
  80189 
  80190 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80191     defined(BCM_56450_B1)
  80192     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEE_BCM56450_A0r */
  80193         soc_block_list[4],
  80194         soc_genreg,
  80195         12,
  80196         0,
  80197         0xb2004f00,
  80198         SOC_REG_FLAG_ARRAY,
  80199         0,
  80200         1,
  80201         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr_fields,
  80202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80203         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  80204         -1,
  80205         -1,
  80206     },
  80207 #endif /* chips */
  80208 
  80209 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80210     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr */
  80211         soc_block_list[4],
  80212         soc_genreg,
  80213         12,
  80214         0,
  80215         0x2b08004f,
  80216         SOC_REG_FLAG_ARRAY,
  80217         0,
  80218         1,
  80219         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr_fields,
  80220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80221         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  80222         -1,
  80223         -1,
  80224     },
  80225 #endif /* chips */
  80226 
  80227 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  80228     defined(BCM_56270_A0)
  80229     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEI_BCM56260_A0r */
  80230         soc_block_list[4],
  80231         soc_genreg,
  80232         12,
  80233         0,
  80234         0xae004f00,
  80235         SOC_REG_FLAG_ARRAY,
  80236         0,
  80237         1,
  80238         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr_fields,
  80239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80240         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  80241         -1,
  80242         -1,
  80243     },
  80244 #endif /* chips */
  80245 
  80246 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80247     defined(BCM_56450_B1)
  80248     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEI_BCM56450_A0r */
  80249         soc_block_list[4],
  80250         soc_genreg,
  80251         12,
  80252         0,
  80253         0xae004f00,
  80254         SOC_REG_FLAG_ARRAY,
  80255         0,
  80256         1,
  80257         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMA_BCM56450_A0r_fields,
  80258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80259         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  80260         -1,
  80261         -1,
  80262     },
  80263 #endif /* chips */
  80264 
  80265 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80266     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr */
  80267         soc_block_list[4],
  80268         soc_genreg,
  80269         12,
  80270         0,
  80271         0x2d08004f,
  80272         SOC_REG_FLAG_ARRAY,
  80273         0,
  80274         1,
  80275         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr_fields,
  80276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80277         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  80278         -1,
  80279         -1,
  80280     },
  80281 #endif /* chips */
  80282 
  80283 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  80284     defined(BCM_56270_A0)
  80285     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQ_BCM56260_A0r */
  80286         soc_block_list[4],
  80287         soc_genreg,
  80288         12,
  80289         0,
  80290         0xb6004f00,
  80291         SOC_REG_FLAG_ARRAY,
  80292         0,
  80293         1,
  80294         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQ_BCM56260_A0r_fields,
  80295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80296         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  80297         -1,
  80298         -1,
  80299     },
  80300 #endif /* chips */
  80301 
  80302 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80303     defined(BCM_56450_B1)
  80304     { /* SOC_REG_INT_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQ_BCM56450_A0r */
  80305         soc_block_list[4],
  80306         soc_genreg,
  80307         12,
  80308         0,
  80309         0xb6004f00,
  80310         SOC_REG_FLAG_ARRAY,
  80311         0,
  80312         1,
  80313         soc_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQ_BCM56450_A0r_fields,
  80314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80315         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  80316         -1,
  80317         -1,
  80318     },
  80319 #endif /* chips */
  80320 
  80321 #if defined(BCM_56800_A0)
  80322     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUEr */
  80323         soc_block_list[4],
  80324         soc_portreg,
  80325         10,
  80326         0,
  80327         0x3000070,
  80328         SOC_REG_FLAG_ARRAY |
  80329                           SOC_REG_FLAG_RO,
  80330         0,
  80331         2,
  80332         soc_OP_QUEUE_RESET_VALUEr_fields,
  80333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80334         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  80335         -1,
  80336         -1,
  80337     },
  80338 #endif /* chips */
  80339 
  80340 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  80341     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_BCM56820_A0r */
  80342         soc_block_list[4],
  80343         soc_portreg,
  80344         32,
  80345         0,
  80346         0x30001c0,
  80347         SOC_REG_FLAG_ARRAY |
  80348                           SOC_REG_FLAG_RO,
  80349         0,
  80350         5,
  80351         soc_OP_QUEUE_RESET_VALUE_BCM56820_A0r_fields,
  80352         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  80353         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  80354         -1,
  80355         9,
  80356     },
  80357 #endif /* chips */
  80358 
  80359 #if defined(BCM_88732_A0)
  80360     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_BCM88732_A0r */
  80361         soc_block_list[4],
  80362         soc_portreg,
  80363         10,
  80364         0,
  80365         0x30001c0,
  80366         SOC_REG_FLAG_ARRAY |
  80367                           SOC_REG_FLAG_RO,
  80368         0,
  80369         5,
  80370         soc_OP_QUEUE_RESET_VALUE_BCM88732_A0r_fields,
  80371         SOC_RESET_VAL_DEC(0x00080000, 0x00000000)
  80372         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  80373         -1,
  80374         49,
  80375     },
  80376 #endif /* chips */
  80377 
  80378 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  80379     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  80380     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_CELLr */
  80381         soc_block_list[4],
  80382         soc_portreg,
  80383         48,
  80384         0,
  80385         0x3000440,
  80386         SOC_REG_FLAG_ARRAY |
  80387                           SOC_REG_FLAG_RO,
  80388         0,
  80389         5,
  80390         soc_OP_QUEUE_RESET_VALUE_CELLr_fields,
  80391         SOC_RESET_VAL_DEC(0x00020000, 0x00000000)
  80392         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  80393         -1,
  80394         0,
  80395     },
  80396 #endif /* chips */
  80397 
  80398 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  80399     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_CELL_BCM56334_A0r */
  80400         soc_block_list[4],
  80401         soc_portreg,
  80402         48,
  80403         0,
  80404         0x3000440,
  80405         SOC_REG_FLAG_ARRAY |
  80406                           SOC_REG_FLAG_RO,
  80407         0,
  80408         5,
  80409         soc_OP_QUEUE_RESET_VALUE_CELL_BCM56334_A0r_fields,
  80410         SOC_RESET_VAL_DEC(0x00020000, 0x00000000)
  80411         SOC_RESET_MASK_DEC(0x0007bfff, 0x00000000)
  80412         -1,
  80413         28,
  80414     },
  80415 #endif /* chips */
  80416 
  80417 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  80418     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  80419     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  80420     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_CELL_BCM56634_A0r */
  80421         soc_block_list[4],
  80422         soc_portreg,
  80423         48,
  80424         0,
  80425         0x3000440,
  80426         SOC_REG_FLAG_ARRAY |
  80427                           SOC_REG_FLAG_RO,
  80428         0,
  80429         5,
  80430         soc_OP_QUEUE_RESET_VALUE_CELLr_fields,
  80431         SOC_RESET_VAL_DEC(0x00020000, 0x00000000)
  80432         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  80433         -1,
  80434         12,
  80435     },
  80436 #endif /* chips */
  80437 
  80438 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  80439     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_CELL_BCM56640_A0r */
  80440         soc_block_list[4],
  80441         soc_portreg,
  80442         48,
  80443         0,
  80444         0xc03c000,
  80445         SOC_REG_FLAG_ARRAY |
  80446                           SOC_REG_FLAG_RO,
  80447         0,
  80448         4,
  80449         soc_OP_QUEUE_RESET_VALUE_CELL_BCM56640_A0r_fields,
  80450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80451         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  80452         -1,
  80453         62,
  80454     },
  80455 #endif /* chips */
  80456 
  80457 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  80458     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_CELL_BCM56840_A0r */
  80459         soc_block_list[4],
  80460         soc_portreg,
  80461         48,
  80462         0,
  80463         0x30003c0,
  80464         SOC_REG_FLAG_ARRAY |
  80465                           SOC_REG_FLAG_RO,
  80466         0,
  80467         4,
  80468         soc_OP_QUEUE_RESET_VALUE_CELL_BCM56840_A0r_fields,
  80469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80470         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  80471         -1,
  80472         38,
  80473     },
  80474 #endif /* chips */
  80475 
  80476 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  80477     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  80478     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_PACKETr */
  80479         soc_block_list[4],
  80480         soc_portreg,
  80481         48,
  80482         0,
  80483         0x3000480,
  80484         SOC_REG_FLAG_ARRAY |
  80485                           SOC_REG_FLAG_RO,
  80486         0,
  80487         5,
  80488         soc_OP_QUEUE_RESET_VALUE_PACKETr_fields,
  80489         SOC_RESET_VAL_DEC(0x00020000, 0x00000000)
  80490         SOC_RESET_MASK_DEC(0x0007bfff, 0x00000000)
  80491         -1,
  80492         0,
  80493     },
  80494 #endif /* chips */
  80495 
  80496 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  80497     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_PACKET_BCM56334_A0r */
  80498         soc_block_list[4],
  80499         soc_portreg,
  80500         48,
  80501         0,
  80502         0x3000480,
  80503         SOC_REG_FLAG_ARRAY |
  80504                           SOC_REG_FLAG_RO,
  80505         0,
  80506         5,
  80507         soc_OP_QUEUE_RESET_VALUE_PACKET_BCM56334_A0r_fields,
  80508         SOC_RESET_VAL_DEC(0x00020000, 0x00000000)
  80509         SOC_RESET_MASK_DEC(0x00079fff, 0x00000000)
  80510         -1,
  80511         28,
  80512     },
  80513 #endif /* chips */
  80514 
  80515 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  80516     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  80517     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  80518     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_PACKET_BCM56634_A0r */
  80519         soc_block_list[4],
  80520         soc_portreg,
  80521         48,
  80522         0,
  80523         0x3000480,
  80524         SOC_REG_FLAG_ARRAY |
  80525                           SOC_REG_FLAG_RO,
  80526         0,
  80527         5,
  80528         soc_OP_QUEUE_RESET_VALUE_PACKETr_fields,
  80529         SOC_RESET_VAL_DEC(0x00020000, 0x00000000)
  80530         SOC_RESET_MASK_DEC(0x0007bfff, 0x00000000)
  80531         -1,
  80532         12,
  80533     },
  80534 #endif /* chips */
  80535 
  80536 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80537     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDOEMAr */
  80538         soc_block_list[4],
  80539         soc_genreg,
  80540         8,
  80541         0,
  80542         0x2e08005f,
  80543         SOC_REG_FLAG_ARRAY |
  80544                           SOC_REG_FLAG_RO,
  80545         0,
  80546         5,
  80547         soc_OP_QUEUE_RESET_VALUE_THDOEMAr_fields,
  80548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80549         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  80550         -1,
  80551         -1,
  80552     },
  80553 #endif /* chips */
  80554 
  80555 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  80556     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDOEMA_BCM56260_A0r */
  80557         soc_block_list[4],
  80558         soc_genreg,
  80559         8,
  80560         0,
  80561         0xba005f00,
  80562         SOC_REG_FLAG_ARRAY |
  80563                           SOC_REG_FLAG_RO,
  80564         0,
  80565         5,
  80566         soc_OP_QUEUE_RESET_VALUE_THDOEMA_BCM56260_A0r_fields,
  80567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80568         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  80569         -1,
  80570         -1,
  80571     },
  80572 #endif /* chips */
  80573 
  80574 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80575     defined(BCM_56450_B1)
  80576     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDOEMA_BCM56450_A0r */
  80577         soc_block_list[4],
  80578         soc_genreg,
  80579         8,
  80580         0,
  80581         0xba005f00,
  80582         SOC_REG_FLAG_ARRAY |
  80583                           SOC_REG_FLAG_RO,
  80584         0,
  80585         5,
  80586         soc_OP_QUEUE_RESET_VALUE_THDOEMA_BCM56450_A0r_fields,
  80587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80588         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  80589         -1,
  80590         -1,
  80591     },
  80592 #endif /* chips */
  80593 
  80594 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80595     defined(BCM_56450_B1)
  80596     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORDEEr */
  80597         soc_block_list[4],
  80598         soc_genreg,
  80599         8,
  80600         0,
  80601         0xc6005f00,
  80602         SOC_REG_FLAG_ARRAY |
  80603                           SOC_REG_FLAG_RO,
  80604         0,
  80605         5,
  80606         soc_OP_QUEUE_RESET_VALUE_THDORDEEr_fields,
  80607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80608         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  80609         -1,
  80610         -1,
  80611     },
  80612 #endif /* chips */
  80613 
  80614 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  80615     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORDEE_BCM56260_A0r */
  80616         soc_block_list[4],
  80617         soc_genreg,
  80618         8,
  80619         0,
  80620         0xc6005f00,
  80621         SOC_REG_FLAG_ARRAY |
  80622                           SOC_REG_FLAG_RO,
  80623         0,
  80624         5,
  80625         soc_OP_QUEUE_RESET_VALUE_THDORDEE_BCM56260_A0r_fields,
  80626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80627         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  80628         -1,
  80629         -1,
  80630     },
  80631 #endif /* chips */
  80632 
  80633 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80634     defined(BCM_56450_B1)
  80635     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORDEIr */
  80636         soc_block_list[4],
  80637         soc_genreg,
  80638         8,
  80639         0,
  80640         0xc2005f00,
  80641         SOC_REG_FLAG_ARRAY |
  80642                           SOC_REG_FLAG_RO,
  80643         0,
  80644         5,
  80645         soc_OP_QUEUE_RESET_VALUE_THDOEMA_BCM56450_A0r_fields,
  80646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80647         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  80648         -1,
  80649         -1,
  80650     },
  80651 #endif /* chips */
  80652 
  80653 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  80654     defined(BCM_56270_A0)
  80655     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORDEI_BCM56260_A0r */
  80656         soc_block_list[4],
  80657         soc_genreg,
  80658         8,
  80659         0,
  80660         0xc2005f00,
  80661         SOC_REG_FLAG_ARRAY |
  80662                           SOC_REG_FLAG_RO,
  80663         0,
  80664         5,
  80665         soc_OP_QUEUE_RESET_VALUE_THDORDEIr_fields,
  80666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80667         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  80668         -1,
  80669         -1,
  80670     },
  80671 #endif /* chips */
  80672 
  80673 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80674     defined(BCM_56450_B1)
  80675     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORDEQr */
  80676         soc_block_list[4],
  80677         soc_genreg,
  80678         16,
  80679         0,
  80680         0xca00b700,
  80681         SOC_REG_FLAG_ARRAY |
  80682                           SOC_REG_FLAG_RO,
  80683         0,
  80684         5,
  80685         soc_OP_QUEUE_RESET_VALUE_THDORDEQr_fields,
  80686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80687         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  80688         -1,
  80689         -1,
  80690     },
  80691 #endif /* chips */
  80692 
  80693 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  80694     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORDEQ_BCM56260_A0r */
  80695         soc_block_list[4],
  80696         soc_genreg,
  80697         16,
  80698         0,
  80699         0xca00b700,
  80700         SOC_REG_FLAG_ARRAY |
  80701                           SOC_REG_FLAG_RO,
  80702         0,
  80703         5,
  80704         soc_OP_QUEUE_RESET_VALUE_THDORDEQ_BCM56260_A0r_fields,
  80705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80706         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  80707         -1,
  80708         -1,
  80709     },
  80710 #endif /* chips */
  80711 
  80712 #if defined(BCM_56270_A0)
  80713     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORDEQ_BCM56270_A0r */
  80714         soc_block_list[4],
  80715         soc_genreg,
  80716         8,
  80717         0,
  80718         0xca005f00,
  80719         SOC_REG_FLAG_ARRAY |
  80720                           SOC_REG_FLAG_RO,
  80721         0,
  80722         5,
  80723         soc_OP_QUEUE_RESET_VALUE_THDORDEQ_BCM56260_A0r_fields,
  80724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80725         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  80726         -1,
  80727         -1,
  80728     },
  80729 #endif /* chips */
  80730 
  80731 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80732     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORQEEr */
  80733         soc_block_list[4],
  80734         soc_genreg,
  80735         12,
  80736         0,
  80737         0x2c08008b,
  80738         SOC_REG_FLAG_ARRAY |
  80739                           SOC_REG_FLAG_RO,
  80740         0,
  80741         5,
  80742         soc_OP_QUEUE_RESET_VALUE_THDORQEEr_fields,
  80743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80744         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  80745         -1,
  80746         -1,
  80747     },
  80748 #endif /* chips */
  80749 
  80750 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  80751     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORQEE_BCM56260_A0r */
  80752         soc_block_list[4],
  80753         soc_genreg,
  80754         12,
  80755         0,
  80756         0xb2008b00,
  80757         SOC_REG_FLAG_ARRAY |
  80758                           SOC_REG_FLAG_RO,
  80759         0,
  80760         5,
  80761         soc_OP_QUEUE_RESET_VALUE_THDORDEE_BCM56260_A0r_fields,
  80762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80763         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  80764         -1,
  80765         -1,
  80766     },
  80767 #endif /* chips */
  80768 
  80769 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80770     defined(BCM_56450_B1)
  80771     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORQEE_BCM56450_A0r */
  80772         soc_block_list[4],
  80773         soc_genreg,
  80774         12,
  80775         0,
  80776         0xb2008b00,
  80777         SOC_REG_FLAG_ARRAY |
  80778                           SOC_REG_FLAG_RO,
  80779         0,
  80780         5,
  80781         soc_OP_QUEUE_RESET_VALUE_THDORDEEr_fields,
  80782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80783         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  80784         -1,
  80785         -1,
  80786     },
  80787 #endif /* chips */
  80788 
  80789 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80790     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORQEIr */
  80791         soc_block_list[4],
  80792         soc_genreg,
  80793         12,
  80794         0,
  80795         0x2b08008b,
  80796         SOC_REG_FLAG_ARRAY |
  80797                           SOC_REG_FLAG_RO,
  80798         0,
  80799         5,
  80800         soc_OP_QUEUE_RESET_VALUE_THDOEMAr_fields,
  80801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80802         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  80803         -1,
  80804         -1,
  80805     },
  80806 #endif /* chips */
  80807 
  80808 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  80809     defined(BCM_56270_A0)
  80810     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORQEI_BCM56260_A0r */
  80811         soc_block_list[4],
  80812         soc_genreg,
  80813         12,
  80814         0,
  80815         0xae008b00,
  80816         SOC_REG_FLAG_ARRAY |
  80817                           SOC_REG_FLAG_RO,
  80818         0,
  80819         5,
  80820         soc_OP_QUEUE_RESET_VALUE_THDORDEIr_fields,
  80821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80822         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  80823         -1,
  80824         -1,
  80825     },
  80826 #endif /* chips */
  80827 
  80828 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80829     defined(BCM_56450_B1)
  80830     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORQEI_BCM56450_A0r */
  80831         soc_block_list[4],
  80832         soc_genreg,
  80833         12,
  80834         0,
  80835         0xae008b00,
  80836         SOC_REG_FLAG_ARRAY |
  80837                           SOC_REG_FLAG_RO,
  80838         0,
  80839         5,
  80840         soc_OP_QUEUE_RESET_VALUE_THDOEMA_BCM56450_A0r_fields,
  80841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80842         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  80843         -1,
  80844         -1,
  80845     },
  80846 #endif /* chips */
  80847 
  80848 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80849     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORQEQr */
  80850         soc_block_list[4],
  80851         soc_genreg,
  80852         12,
  80853         0,
  80854         0x2d08008b,
  80855         SOC_REG_FLAG_ARRAY |
  80856                           SOC_REG_FLAG_RO,
  80857         0,
  80858         5,
  80859         soc_OP_QUEUE_RESET_VALUE_THDORQEQr_fields,
  80860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80861         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  80862         -1,
  80863         -1,
  80864     },
  80865 #endif /* chips */
  80866 
  80867 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  80868     defined(BCM_56270_A0)
  80869     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORQEQ_BCM56260_A0r */
  80870         soc_block_list[4],
  80871         soc_genreg,
  80872         12,
  80873         0,
  80874         0xb6008b00,
  80875         SOC_REG_FLAG_ARRAY |
  80876                           SOC_REG_FLAG_RO,
  80877         0,
  80878         5,
  80879         soc_OP_QUEUE_RESET_VALUE_THDORQEQ_BCM56260_A0r_fields,
  80880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80881         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  80882         -1,
  80883         -1,
  80884     },
  80885 #endif /* chips */
  80886 
  80887 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80888     defined(BCM_56450_B1)
  80889     { /* SOC_REG_INT_OP_QUEUE_RESET_VALUE_THDORQEQ_BCM56450_A0r */
  80890         soc_block_list[4],
  80891         soc_genreg,
  80892         12,
  80893         0,
  80894         0xb6008b00,
  80895         SOC_REG_FLAG_ARRAY |
  80896                           SOC_REG_FLAG_RO,
  80897         0,
  80898         5,
  80899         soc_OP_QUEUE_RESET_VALUE_THDORQEQ_BCM56450_A0r_fields,
  80900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80901         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  80902         -1,
  80903         -1,
  80904     },
  80905 #endif /* chips */
  80906 
  80907 #if defined(BCM_56800_A0)
  80908     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNTr */
  80909         soc_block_list[4],
  80910         soc_portreg,
  80911         10,
  80912         0,
  80913         0x3000040,
  80914         SOC_REG_FLAG_ARRAY |
  80915                           SOC_REG_FLAG_RO,
  80916         0,
  80917         1,
  80918         soc_OP_QUEUE_SHARED_COUNTr_fields,
  80919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80920         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  80921         -1,
  80922         -1,
  80923     },
  80924 #endif /* chips */
  80925 
  80926 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  80927     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_BCM56820_A0r */
  80928         soc_block_list[4],
  80929         soc_portreg,
  80930         32,
  80931         0,
  80932         0x3000140,
  80933         SOC_REG_FLAG_ARRAY |
  80934                           SOC_REG_FLAG_RO,
  80935         0,
  80936         1,
  80937         soc_OP_QUEUE_SHARED_COUNTr_fields,
  80938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80939         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  80940         -1,
  80941         9,
  80942     },
  80943 #endif /* chips */
  80944 
  80945 #if defined(BCM_88732_A0)
  80946     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_BCM88732_A0r */
  80947         soc_block_list[4],
  80948         soc_portreg,
  80949         10,
  80950         0,
  80951         0x3000140,
  80952         SOC_REG_FLAG_ARRAY |
  80953                           SOC_REG_FLAG_RO,
  80954         0,
  80955         1,
  80956         soc_OP_QUEUE_SHARED_COUNT_BCM88732_A0r_fields,
  80957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80958         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  80959         -1,
  80960         49,
  80961     },
  80962 #endif /* chips */
  80963 
  80964 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  80965     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  80966     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_CELLr */
  80967         soc_block_list[4],
  80968         soc_portreg,
  80969         48,
  80970         0,
  80971         0x3000340,
  80972         SOC_REG_FLAG_ARRAY |
  80973                           SOC_REG_FLAG_RO,
  80974         0,
  80975         1,
  80976         soc_OP_QUEUE_SHARED_COUNT_CELLr_fields,
  80977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80978         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  80979         -1,
  80980         0,
  80981     },
  80982 #endif /* chips */
  80983 
  80984 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  80985     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_CELL_BCM56334_A0r */
  80986         soc_block_list[4],
  80987         soc_portreg,
  80988         48,
  80989         0,
  80990         0x3000340,
  80991         SOC_REG_FLAG_ARRAY |
  80992                           SOC_REG_FLAG_RO,
  80993         0,
  80994         1,
  80995         soc_OP_QUEUE_SHARED_COUNT_CELL_BCM56334_A0r_fields,
  80996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80997         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  80998         -1,
  80999         28,
  81000     },
  81001 #endif /* chips */
  81002 
  81003 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  81004     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  81005     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  81006     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_CELL_BCM56634_A0r */
  81007         soc_block_list[4],
  81008         soc_portreg,
  81009         48,
  81010         0,
  81011         0x3000340,
  81012         SOC_REG_FLAG_ARRAY |
  81013                           SOC_REG_FLAG_RO,
  81014         0,
  81015         1,
  81016         soc_OP_QUEUE_SHARED_COUNT_CELLr_fields,
  81017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81018         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  81019         -1,
  81020         12,
  81021     },
  81022 #endif /* chips */
  81023 
  81024 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  81025     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_CELL_BCM56640_A0r */
  81026         soc_block_list[4],
  81027         soc_portreg,
  81028         48,
  81029         0,
  81030         0xc02c000,
  81031         SOC_REG_FLAG_ARRAY |
  81032                           SOC_REG_FLAG_RO,
  81033         0,
  81034         1,
  81035         soc_OP_QUEUE_SHARED_COUNT_CELL_BCM56640_A0r_fields,
  81036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81037         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  81038         -1,
  81039         62,
  81040     },
  81041 #endif /* chips */
  81042 
  81043 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  81044     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_CELL_BCM56840_A0r */
  81045         soc_block_list[4],
  81046         soc_portreg,
  81047         48,
  81048         0,
  81049         0x30002c0,
  81050         SOC_REG_FLAG_ARRAY |
  81051                           SOC_REG_FLAG_RO,
  81052         0,
  81053         1,
  81054         soc_OP_EX_QUEUE_SHARED_COUNT_CELLr_fields,
  81055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81056         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  81057         -1,
  81058         38,
  81059     },
  81060 #endif /* chips */
  81061 
  81062 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  81063     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  81064     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_PACKETr */
  81065         soc_block_list[4],
  81066         soc_portreg,
  81067         48,
  81068         0,
  81069         0x3000380,
  81070         SOC_REG_FLAG_ARRAY |
  81071                           SOC_REG_FLAG_RO,
  81072         0,
  81073         1,
  81074         soc_OP_QUEUE_SHARED_COUNT_PACKETr_fields,
  81075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81076         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81077         -1,
  81078         0,
  81079     },
  81080 #endif /* chips */
  81081 
  81082 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  81083     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_PACKET_BCM56334_A0r */
  81084         soc_block_list[4],
  81085         soc_portreg,
  81086         48,
  81087         0,
  81088         0x3000380,
  81089         SOC_REG_FLAG_ARRAY |
  81090                           SOC_REG_FLAG_RO,
  81091         0,
  81092         1,
  81093         soc_OP_QUEUE_SHARED_COUNT_PACKET_BCM56334_A0r_fields,
  81094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81095         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  81096         -1,
  81097         28,
  81098     },
  81099 #endif /* chips */
  81100 
  81101 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  81102     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  81103     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  81104     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_PACKET_BCM56634_A0r */
  81105         soc_block_list[4],
  81106         soc_portreg,
  81107         48,
  81108         0,
  81109         0x3000380,
  81110         SOC_REG_FLAG_ARRAY |
  81111                           SOC_REG_FLAG_RO,
  81112         0,
  81113         1,
  81114         soc_OP_QUEUE_SHARED_COUNT_PACKETr_fields,
  81115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81116         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81117         -1,
  81118         12,
  81119     },
  81120 #endif /* chips */
  81121 
  81122 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81123     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDOEMAr */
  81124         soc_block_list[4],
  81125         soc_genreg,
  81126         8,
  81127         0,
  81128         0x2e08004f,
  81129         SOC_REG_FLAG_ARRAY |
  81130                           SOC_REG_FLAG_RO,
  81131         0,
  81132         1,
  81133         soc_OP_QUEUE_SHARED_COUNTr_fields,
  81134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81135         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81136         -1,
  81137         -1,
  81138     },
  81139 #endif /* chips */
  81140 
  81141 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81142     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDOEMA_BCM56260_A0r */
  81143         soc_block_list[4],
  81144         soc_genreg,
  81145         8,
  81146         0,
  81147         0xba004f00,
  81148         SOC_REG_FLAG_ARRAY |
  81149                           SOC_REG_FLAG_RO,
  81150         0,
  81151         1,
  81152         soc_OP_QUEUE_SHARED_COUNT_THDOEMA_BCM56260_A0r_fields,
  81153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81154         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  81155         -1,
  81156         -1,
  81157     },
  81158 #endif /* chips */
  81159 
  81160 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81161     defined(BCM_56450_B1)
  81162     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDOEMA_BCM56450_A0r */
  81163         soc_block_list[4],
  81164         soc_genreg,
  81165         8,
  81166         0,
  81167         0xba004f00,
  81168         SOC_REG_FLAG_ARRAY |
  81169                           SOC_REG_FLAG_RO,
  81170         0,
  81171         1,
  81172         soc_OP_QUEUE_SHARED_COUNT_THDOEMAr_fields,
  81173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81174         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81175         -1,
  81176         -1,
  81177     },
  81178 #endif /* chips */
  81179 
  81180 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81181     defined(BCM_56450_B1)
  81182     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORDEEr */
  81183         soc_block_list[4],
  81184         soc_genreg,
  81185         8,
  81186         0,
  81187         0xc6004f00,
  81188         SOC_REG_FLAG_ARRAY |
  81189                           SOC_REG_FLAG_RO,
  81190         0,
  81191         1,
  81192         soc_OP_QUEUE_SHARED_COUNT_THDORDEEr_fields,
  81193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81194         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  81195         -1,
  81196         -1,
  81197     },
  81198 #endif /* chips */
  81199 
  81200 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81201     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORDEE_BCM56260_A0r */
  81202         soc_block_list[4],
  81203         soc_genreg,
  81204         8,
  81205         0,
  81206         0xc6004f00,
  81207         SOC_REG_FLAG_ARRAY |
  81208                           SOC_REG_FLAG_RO,
  81209         0,
  81210         1,
  81211         soc_OP_QUEUE_SHARED_COUNT_THDORDEE_BCM56260_A0r_fields,
  81212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81213         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  81214         -1,
  81215         -1,
  81216     },
  81217 #endif /* chips */
  81218 
  81219 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81220     defined(BCM_56450_B1)
  81221     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORDEIr */
  81222         soc_block_list[4],
  81223         soc_genreg,
  81224         8,
  81225         0,
  81226         0xc2004f00,
  81227         SOC_REG_FLAG_ARRAY |
  81228                           SOC_REG_FLAG_RO,
  81229         0,
  81230         1,
  81231         soc_OP_QUEUE_SHARED_COUNT_THDOEMAr_fields,
  81232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81233         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81234         -1,
  81235         -1,
  81236     },
  81237 #endif /* chips */
  81238 
  81239 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  81240     defined(BCM_56270_A0)
  81241     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORDEI_BCM56260_A0r */
  81242         soc_block_list[4],
  81243         soc_genreg,
  81244         8,
  81245         0,
  81246         0xc2004f00,
  81247         SOC_REG_FLAG_ARRAY |
  81248                           SOC_REG_FLAG_RO,
  81249         0,
  81250         1,
  81251         soc_OP_QUEUE_SHARED_COUNT_THDORDEIr_fields,
  81252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81253         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81254         -1,
  81255         -1,
  81256     },
  81257 #endif /* chips */
  81258 
  81259 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81260     defined(BCM_56450_B1)
  81261     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORDEQr */
  81262         soc_block_list[4],
  81263         soc_genreg,
  81264         16,
  81265         0,
  81266         0xca009700,
  81267         SOC_REG_FLAG_ARRAY |
  81268                           SOC_REG_FLAG_RO,
  81269         0,
  81270         1,
  81271         soc_OP_QUEUE_SHARED_COUNT_THDORDEQr_fields,
  81272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81273         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  81274         -1,
  81275         -1,
  81276     },
  81277 #endif /* chips */
  81278 
  81279 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81280     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORDEQ_BCM56260_A0r */
  81281         soc_block_list[4],
  81282         soc_genreg,
  81283         16,
  81284         0,
  81285         0xca009700,
  81286         SOC_REG_FLAG_ARRAY |
  81287                           SOC_REG_FLAG_RO,
  81288         0,
  81289         1,
  81290         soc_OP_QUEUE_SHARED_COUNT_THDORDEQ_BCM56260_A0r_fields,
  81291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81292         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  81293         -1,
  81294         -1,
  81295     },
  81296 #endif /* chips */
  81297 
  81298 #if defined(BCM_56270_A0)
  81299     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORDEQ_BCM56270_A0r */
  81300         soc_block_list[4],
  81301         soc_genreg,
  81302         8,
  81303         0,
  81304         0xca004f00,
  81305         SOC_REG_FLAG_ARRAY |
  81306                           SOC_REG_FLAG_RO,
  81307         0,
  81308         1,
  81309         soc_OP_QUEUE_SHARED_COUNT_THDORDEQ_BCM56260_A0r_fields,
  81310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81311         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  81312         -1,
  81313         -1,
  81314     },
  81315 #endif /* chips */
  81316 
  81317 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81318     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORQEEr */
  81319         soc_block_list[4],
  81320         soc_genreg,
  81321         12,
  81322         0,
  81323         0x2c080073,
  81324         SOC_REG_FLAG_ARRAY |
  81325                           SOC_REG_FLAG_RO,
  81326         0,
  81327         1,
  81328         soc_OP_QUEUE_SHARED_COUNT_THDORQEEr_fields,
  81329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81330         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  81331         -1,
  81332         -1,
  81333     },
  81334 #endif /* chips */
  81335 
  81336 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81337     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORQEE_BCM56260_A0r */
  81338         soc_block_list[4],
  81339         soc_genreg,
  81340         12,
  81341         0,
  81342         0xb2007300,
  81343         SOC_REG_FLAG_ARRAY |
  81344                           SOC_REG_FLAG_RO,
  81345         0,
  81346         1,
  81347         soc_OP_QUEUE_SHARED_COUNT_THDORDEE_BCM56260_A0r_fields,
  81348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81349         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  81350         -1,
  81351         -1,
  81352     },
  81353 #endif /* chips */
  81354 
  81355 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81356     defined(BCM_56450_B1)
  81357     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORQEE_BCM56450_A0r */
  81358         soc_block_list[4],
  81359         soc_genreg,
  81360         12,
  81361         0,
  81362         0xb2007300,
  81363         SOC_REG_FLAG_ARRAY |
  81364                           SOC_REG_FLAG_RO,
  81365         0,
  81366         1,
  81367         soc_OP_QUEUE_SHARED_COUNT_THDORDEEr_fields,
  81368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81369         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  81370         -1,
  81371         -1,
  81372     },
  81373 #endif /* chips */
  81374 
  81375 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81376     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORQEIr */
  81377         soc_block_list[4],
  81378         soc_genreg,
  81379         12,
  81380         0,
  81381         0x2b080073,
  81382         SOC_REG_FLAG_ARRAY |
  81383                           SOC_REG_FLAG_RO,
  81384         0,
  81385         1,
  81386         soc_OP_QUEUE_SHARED_COUNTr_fields,
  81387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81388         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81389         -1,
  81390         -1,
  81391     },
  81392 #endif /* chips */
  81393 
  81394 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  81395     defined(BCM_56270_A0)
  81396     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORQEI_BCM56260_A0r */
  81397         soc_block_list[4],
  81398         soc_genreg,
  81399         12,
  81400         0,
  81401         0xae007300,
  81402         SOC_REG_FLAG_ARRAY |
  81403                           SOC_REG_FLAG_RO,
  81404         0,
  81405         1,
  81406         soc_OP_QUEUE_SHARED_COUNT_THDORDEIr_fields,
  81407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81408         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81409         -1,
  81410         -1,
  81411     },
  81412 #endif /* chips */
  81413 
  81414 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81415     defined(BCM_56450_B1)
  81416     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORQEI_BCM56450_A0r */
  81417         soc_block_list[4],
  81418         soc_genreg,
  81419         12,
  81420         0,
  81421         0xae007300,
  81422         SOC_REG_FLAG_ARRAY |
  81423                           SOC_REG_FLAG_RO,
  81424         0,
  81425         1,
  81426         soc_OP_QUEUE_SHARED_COUNT_THDOEMAr_fields,
  81427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81428         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81429         -1,
  81430         -1,
  81431     },
  81432 #endif /* chips */
  81433 
  81434 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81435     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORQEQr */
  81436         soc_block_list[4],
  81437         soc_genreg,
  81438         12,
  81439         0,
  81440         0x2d080073,
  81441         SOC_REG_FLAG_ARRAY |
  81442                           SOC_REG_FLAG_RO,
  81443         0,
  81444         1,
  81445         soc_OP_QUEUE_SHARED_COUNT_THDORQEQr_fields,
  81446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81447         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  81448         -1,
  81449         -1,
  81450     },
  81451 #endif /* chips */
  81452 
  81453 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  81454     defined(BCM_56270_A0)
  81455     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORQEQ_BCM56260_A0r */
  81456         soc_block_list[4],
  81457         soc_genreg,
  81458         12,
  81459         0,
  81460         0xb6007300,
  81461         SOC_REG_FLAG_ARRAY |
  81462                           SOC_REG_FLAG_RO,
  81463         0,
  81464         1,
  81465         soc_OP_QUEUE_SHARED_COUNT_THDORQEQ_BCM56260_A0r_fields,
  81466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81467         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  81468         -1,
  81469         -1,
  81470     },
  81471 #endif /* chips */
  81472 
  81473 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81474     defined(BCM_56450_B1)
  81475     { /* SOC_REG_INT_OP_QUEUE_SHARED_COUNT_THDORQEQ_BCM56450_A0r */
  81476         soc_block_list[4],
  81477         soc_genreg,
  81478         12,
  81479         0,
  81480         0xb6007300,
  81481         SOC_REG_FLAG_ARRAY |
  81482                           SOC_REG_FLAG_RO,
  81483         0,
  81484         1,
  81485         soc_OP_QUEUE_SHARED_COUNT_THDORQEQ_BCM56450_A0r_fields,
  81486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81487         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  81488         -1,
  81489         -1,
  81490     },
  81491 #endif /* chips */
  81492 
  81493 #if defined(BCM_56800_A0)
  81494     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNTr */
  81495         soc_block_list[4],
  81496         soc_portreg,
  81497         10,
  81498         0,
  81499         0x3000050,
  81500         SOC_REG_FLAG_ARRAY |
  81501                           SOC_REG_FLAG_RO,
  81502         0,
  81503         1,
  81504         soc_OP_QUEUE_TOTAL_COUNTr_fields,
  81505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81506         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81507         -1,
  81508         -1,
  81509     },
  81510 #endif /* chips */
  81511 
  81512 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  81513     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_BCM56820_A0r */
  81514         soc_block_list[4],
  81515         soc_portreg,
  81516         32,
  81517         0,
  81518         0x3000180,
  81519         SOC_REG_FLAG_ARRAY |
  81520                           SOC_REG_FLAG_RO,
  81521         0,
  81522         1,
  81523         soc_OP_QUEUE_TOTAL_COUNTr_fields,
  81524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81525         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81526         -1,
  81527         9,
  81528     },
  81529 #endif /* chips */
  81530 
  81531 #if defined(BCM_88732_A0)
  81532     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_BCM88732_A0r */
  81533         soc_block_list[4],
  81534         soc_portreg,
  81535         10,
  81536         0,
  81537         0x3000180,
  81538         SOC_REG_FLAG_ARRAY |
  81539                           SOC_REG_FLAG_RO,
  81540         0,
  81541         1,
  81542         soc_OP_QUEUE_TOTAL_COUNT_BCM88732_A0r_fields,
  81543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81544         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  81545         -1,
  81546         49,
  81547     },
  81548 #endif /* chips */
  81549 
  81550 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  81551     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  81552     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_CELLr */
  81553         soc_block_list[4],
  81554         soc_portreg,
  81555         48,
  81556         0,
  81557         0x30003c0,
  81558         SOC_REG_FLAG_ARRAY |
  81559                           SOC_REG_FLAG_RO,
  81560         0,
  81561         1,
  81562         soc_OP_QUEUE_TOTAL_COUNT_CELLr_fields,
  81563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81564         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  81565         -1,
  81566         0,
  81567     },
  81568 #endif /* chips */
  81569 
  81570 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  81571     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_CELL_BCM56334_A0r */
  81572         soc_block_list[4],
  81573         soc_portreg,
  81574         48,
  81575         0,
  81576         0x30003c0,
  81577         SOC_REG_FLAG_ARRAY |
  81578                           SOC_REG_FLAG_RO,
  81579         0,
  81580         1,
  81581         soc_OP_QUEUE_TOTAL_COUNT_CELL_BCM56334_A0r_fields,
  81582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81583         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81584         -1,
  81585         28,
  81586     },
  81587 #endif /* chips */
  81588 
  81589 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  81590     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  81591     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  81592     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_CELL_BCM56634_A0r */
  81593         soc_block_list[4],
  81594         soc_portreg,
  81595         48,
  81596         0,
  81597         0x30003c0,
  81598         SOC_REG_FLAG_ARRAY |
  81599                           SOC_REG_FLAG_RO,
  81600         0,
  81601         1,
  81602         soc_OP_QUEUE_TOTAL_COUNT_CELLr_fields,
  81603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81604         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  81605         -1,
  81606         12,
  81607     },
  81608 #endif /* chips */
  81609 
  81610 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  81611     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_CELL_BCM56640_A0r */
  81612         soc_block_list[4],
  81613         soc_portreg,
  81614         48,
  81615         0,
  81616         0xc034000,
  81617         SOC_REG_FLAG_ARRAY |
  81618                           SOC_REG_FLAG_RO,
  81619         0,
  81620         1,
  81621         soc_OP_QUEUE_TOTAL_COUNT_CELL_BCM56640_A0r_fields,
  81622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81623         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  81624         -1,
  81625         62,
  81626     },
  81627 #endif /* chips */
  81628 
  81629 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  81630     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_CELL_BCM56840_A0r */
  81631         soc_block_list[4],
  81632         soc_portreg,
  81633         48,
  81634         0,
  81635         0x3000340,
  81636         SOC_REG_FLAG_ARRAY |
  81637                           SOC_REG_FLAG_RO,
  81638         0,
  81639         1,
  81640         soc_OP_EX_QUEUE_TOTAL_COUNT_CELLr_fields,
  81641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81642         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  81643         -1,
  81644         38,
  81645     },
  81646 #endif /* chips */
  81647 
  81648 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  81649     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  81650     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_PACKETr */
  81651         soc_block_list[4],
  81652         soc_portreg,
  81653         48,
  81654         0,
  81655         0x3000400,
  81656         SOC_REG_FLAG_ARRAY |
  81657                           SOC_REG_FLAG_RO,
  81658         0,
  81659         1,
  81660         soc_OP_QUEUE_TOTAL_COUNT_PACKETr_fields,
  81661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81662         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81663         -1,
  81664         0,
  81665     },
  81666 #endif /* chips */
  81667 
  81668 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  81669     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_PACKET_BCM56334_A0r */
  81670         soc_block_list[4],
  81671         soc_portreg,
  81672         48,
  81673         0,
  81674         0x3000400,
  81675         SOC_REG_FLAG_ARRAY |
  81676                           SOC_REG_FLAG_RO,
  81677         0,
  81678         1,
  81679         soc_OP_QUEUE_TOTAL_COUNT_PACKET_BCM56334_A0r_fields,
  81680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81681         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  81682         -1,
  81683         28,
  81684     },
  81685 #endif /* chips */
  81686 
  81687 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  81688     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  81689     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  81690     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_PACKET_BCM56634_A0r */
  81691         soc_block_list[4],
  81692         soc_portreg,
  81693         48,
  81694         0,
  81695         0x3000400,
  81696         SOC_REG_FLAG_ARRAY |
  81697                           SOC_REG_FLAG_RO,
  81698         0,
  81699         1,
  81700         soc_OP_QUEUE_TOTAL_COUNT_PACKETr_fields,
  81701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81702         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81703         -1,
  81704         12,
  81705     },
  81706 #endif /* chips */
  81707 
  81708 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81709     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDOEMAr */
  81710         soc_block_list[4],
  81711         soc_genreg,
  81712         8,
  81713         0,
  81714         0x2e080057,
  81715         SOC_REG_FLAG_ARRAY |
  81716                           SOC_REG_FLAG_RO,
  81717         0,
  81718         1,
  81719         soc_OP_QUEUE_TOTAL_COUNTr_fields,
  81720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81721         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81722         -1,
  81723         -1,
  81724     },
  81725 #endif /* chips */
  81726 
  81727 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81728     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDOEMA_BCM56260_A0r */
  81729         soc_block_list[4],
  81730         soc_genreg,
  81731         8,
  81732         0,
  81733         0xba005700,
  81734         SOC_REG_FLAG_ARRAY |
  81735                           SOC_REG_FLAG_RO,
  81736         0,
  81737         1,
  81738         soc_OP_QUEUE_TOTAL_COUNT_THDOEMA_BCM56260_A0r_fields,
  81739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81740         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  81741         -1,
  81742         -1,
  81743     },
  81744 #endif /* chips */
  81745 
  81746 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81747     defined(BCM_56450_B1)
  81748     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDOEMA_BCM56450_A0r */
  81749         soc_block_list[4],
  81750         soc_genreg,
  81751         8,
  81752         0,
  81753         0xba005700,
  81754         SOC_REG_FLAG_ARRAY |
  81755                           SOC_REG_FLAG_RO,
  81756         0,
  81757         1,
  81758         soc_OP_QUEUE_TOTAL_COUNT_THDOEMAr_fields,
  81759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81760         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81761         -1,
  81762         -1,
  81763     },
  81764 #endif /* chips */
  81765 
  81766 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81767     defined(BCM_56450_B1)
  81768     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORDEEr */
  81769         soc_block_list[4],
  81770         soc_genreg,
  81771         8,
  81772         0,
  81773         0xc6005700,
  81774         SOC_REG_FLAG_ARRAY |
  81775                           SOC_REG_FLAG_RO,
  81776         0,
  81777         1,
  81778         soc_OP_QUEUE_TOTAL_COUNT_THDORDEEr_fields,
  81779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81780         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  81781         -1,
  81782         -1,
  81783     },
  81784 #endif /* chips */
  81785 
  81786 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81787     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORDEE_BCM56260_A0r */
  81788         soc_block_list[4],
  81789         soc_genreg,
  81790         8,
  81791         0,
  81792         0xc6005700,
  81793         SOC_REG_FLAG_ARRAY |
  81794                           SOC_REG_FLAG_RO,
  81795         0,
  81796         1,
  81797         soc_OP_QUEUE_TOTAL_COUNT_THDORDEE_BCM56260_A0r_fields,
  81798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81799         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  81800         -1,
  81801         -1,
  81802     },
  81803 #endif /* chips */
  81804 
  81805 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81806     defined(BCM_56450_B1)
  81807     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORDEIr */
  81808         soc_block_list[4],
  81809         soc_genreg,
  81810         8,
  81811         0,
  81812         0xc2005700,
  81813         SOC_REG_FLAG_ARRAY |
  81814                           SOC_REG_FLAG_RO,
  81815         0,
  81816         1,
  81817         soc_OP_QUEUE_TOTAL_COUNT_THDOEMAr_fields,
  81818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81819         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81820         -1,
  81821         -1,
  81822     },
  81823 #endif /* chips */
  81824 
  81825 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  81826     defined(BCM_56270_A0)
  81827     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORDEI_BCM56260_A0r */
  81828         soc_block_list[4],
  81829         soc_genreg,
  81830         8,
  81831         0,
  81832         0xc2005700,
  81833         SOC_REG_FLAG_ARRAY |
  81834                           SOC_REG_FLAG_RO,
  81835         0,
  81836         1,
  81837         soc_OP_QUEUE_TOTAL_COUNT_THDORDEIr_fields,
  81838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81839         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81840         -1,
  81841         -1,
  81842     },
  81843 #endif /* chips */
  81844 
  81845 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81846     defined(BCM_56450_B1)
  81847     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORDEQr */
  81848         soc_block_list[4],
  81849         soc_genreg,
  81850         16,
  81851         0,
  81852         0xca00a700,
  81853         SOC_REG_FLAG_ARRAY |
  81854                           SOC_REG_FLAG_RO,
  81855         0,
  81856         1,
  81857         soc_OP_QUEUE_TOTAL_COUNT_THDORDEQr_fields,
  81858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81859         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  81860         -1,
  81861         -1,
  81862     },
  81863 #endif /* chips */
  81864 
  81865 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81866     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORDEQ_BCM56260_A0r */
  81867         soc_block_list[4],
  81868         soc_genreg,
  81869         16,
  81870         0,
  81871         0xca00a700,
  81872         SOC_REG_FLAG_ARRAY |
  81873                           SOC_REG_FLAG_RO,
  81874         0,
  81875         1,
  81876         soc_OP_QUEUE_TOTAL_COUNT_THDORDEQ_BCM56260_A0r_fields,
  81877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81878         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  81879         -1,
  81880         -1,
  81881     },
  81882 #endif /* chips */
  81883 
  81884 #if defined(BCM_56270_A0)
  81885     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORDEQ_BCM56270_A0r */
  81886         soc_block_list[4],
  81887         soc_genreg,
  81888         8,
  81889         0,
  81890         0xca005700,
  81891         SOC_REG_FLAG_ARRAY |
  81892                           SOC_REG_FLAG_RO,
  81893         0,
  81894         1,
  81895         soc_OP_QUEUE_TOTAL_COUNT_THDORDEQ_BCM56260_A0r_fields,
  81896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81897         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  81898         -1,
  81899         -1,
  81900     },
  81901 #endif /* chips */
  81902 
  81903 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81904     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORQEEr */
  81905         soc_block_list[4],
  81906         soc_genreg,
  81907         12,
  81908         0,
  81909         0x2c08007f,
  81910         SOC_REG_FLAG_ARRAY |
  81911                           SOC_REG_FLAG_RO,
  81912         0,
  81913         1,
  81914         soc_OP_QUEUE_TOTAL_COUNT_THDORQEEr_fields,
  81915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81916         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  81917         -1,
  81918         -1,
  81919     },
  81920 #endif /* chips */
  81921 
  81922 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81923     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORQEE_BCM56260_A0r */
  81924         soc_block_list[4],
  81925         soc_genreg,
  81926         12,
  81927         0,
  81928         0xb2007f00,
  81929         SOC_REG_FLAG_ARRAY |
  81930                           SOC_REG_FLAG_RO,
  81931         0,
  81932         1,
  81933         soc_OP_QUEUE_TOTAL_COUNT_THDORDEE_BCM56260_A0r_fields,
  81934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81935         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  81936         -1,
  81937         -1,
  81938     },
  81939 #endif /* chips */
  81940 
  81941 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81942     defined(BCM_56450_B1)
  81943     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORQEE_BCM56450_A0r */
  81944         soc_block_list[4],
  81945         soc_genreg,
  81946         12,
  81947         0,
  81948         0xb2007f00,
  81949         SOC_REG_FLAG_ARRAY |
  81950                           SOC_REG_FLAG_RO,
  81951         0,
  81952         1,
  81953         soc_OP_QUEUE_TOTAL_COUNT_THDORDEEr_fields,
  81954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81955         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  81956         -1,
  81957         -1,
  81958     },
  81959 #endif /* chips */
  81960 
  81961 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81962     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORQEIr */
  81963         soc_block_list[4],
  81964         soc_genreg,
  81965         12,
  81966         0,
  81967         0x2b08007f,
  81968         SOC_REG_FLAG_ARRAY |
  81969                           SOC_REG_FLAG_RO,
  81970         0,
  81971         1,
  81972         soc_OP_QUEUE_TOTAL_COUNTr_fields,
  81973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81974         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81975         -1,
  81976         -1,
  81977     },
  81978 #endif /* chips */
  81979 
  81980 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  81981     defined(BCM_56270_A0)
  81982     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORQEI_BCM56260_A0r */
  81983         soc_block_list[4],
  81984         soc_genreg,
  81985         12,
  81986         0,
  81987         0xae007f00,
  81988         SOC_REG_FLAG_ARRAY |
  81989                           SOC_REG_FLAG_RO,
  81990         0,
  81991         1,
  81992         soc_OP_QUEUE_TOTAL_COUNT_THDORDEIr_fields,
  81993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81994         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  81995         -1,
  81996         -1,
  81997     },
  81998 #endif /* chips */
  81999 
  82000 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  82001     defined(BCM_56450_B1)
  82002     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORQEI_BCM56450_A0r */
  82003         soc_block_list[4],
  82004         soc_genreg,
  82005         12,
  82006         0,
  82007         0xae007f00,
  82008         SOC_REG_FLAG_ARRAY |
  82009                           SOC_REG_FLAG_RO,
  82010         0,
  82011         1,
  82012         soc_OP_QUEUE_TOTAL_COUNT_THDOEMAr_fields,
  82013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82014         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  82015         -1,
  82016         -1,
  82017     },
  82018 #endif /* chips */
  82019 
  82020 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  82021     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORQEQr */
  82022         soc_block_list[4],
  82023         soc_genreg,
  82024         12,
  82025         0,
  82026         0x2d08007f,
  82027         SOC_REG_FLAG_ARRAY |
  82028                           SOC_REG_FLAG_RO,
  82029         0,
  82030         1,
  82031         soc_OP_QUEUE_TOTAL_COUNT_THDORQEQr_fields,
  82032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82033         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  82034         -1,
  82035         -1,
  82036     },
  82037 #endif /* chips */
  82038 
  82039 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  82040     defined(BCM_56270_A0)
  82041     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORQEQ_BCM56260_A0r */
  82042         soc_block_list[4],
  82043         soc_genreg,
  82044         12,
  82045         0,
  82046         0xb6007f00,
  82047         SOC_REG_FLAG_ARRAY |
  82048                           SOC_REG_FLAG_RO,
  82049         0,
  82050         1,
  82051         soc_OP_QUEUE_TOTAL_COUNT_THDORQEQ_BCM56260_A0r_fields,
  82052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82053         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  82054         -1,
  82055         -1,
  82056     },
  82057 #endif /* chips */
  82058 
  82059 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  82060     defined(BCM_56450_B1)
  82061     { /* SOC_REG_INT_OP_QUEUE_TOTAL_COUNT_THDORQEQ_BCM56450_A0r */
  82062         soc_block_list[4],
  82063         soc_genreg,
  82064         12,
  82065         0,
  82066         0xb6007f00,
  82067         SOC_REG_FLAG_ARRAY |
  82068                           SOC_REG_FLAG_RO,
  82069         0,
  82070         1,
  82071         soc_OP_QUEUE_TOTAL_COUNT_THDORQEQ_BCM56450_A0r_fields,
  82072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82073         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  82074         -1,
  82075         -1,
  82076     },
  82077 #endif /* chips */
  82078 
  82079 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  82080     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  82081     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  82082     { /* SOC_REG_INT_OP_RESUME_OFFSET_COLOR_CELL_PROFILEr */
  82083         soc_block_list[4],
  82084         soc_genreg,
  82085         8,
  82086         0,
  82087         0x3080030,
  82088         SOC_REG_FLAG_ARRAY,
  82089         0,
  82090         2,
  82091         soc_OP_RESUME_OFFSET_COLOR_CELL_PROFILEr_fields,
  82092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82093         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  82094         -1,
  82095         -1,
  82096     },
  82097 #endif /* chips */
  82098 
  82099 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  82100     { /* SOC_REG_INT_OP_RESUME_OFFSET_COLOR_CELL_PROFILE_BCM56334_A0r */
  82101         soc_block_list[4],
  82102         soc_genreg,
  82103         8,
  82104         0,
  82105         0x3080540,
  82106         SOC_REG_FLAG_ARRAY,
  82107         0,
  82108         2,
  82109         soc_OP_RESUME_OFFSET_COLOR_CELL_PROFILE_BCM56334_A0r_fields,
  82110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82111         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  82112         -1,
  82113         -1,
  82114     },
  82115 #endif /* chips */
  82116 
  82117 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  82118     { /* SOC_REG_INT_OP_RESUME_OFFSET_COLOR_CELL_PROFILE_BCM56640_A0r */
  82119         soc_block_list[4],
  82120         soc_genreg,
  82121         8,
  82122         0,
  82123         0xe00a000,
  82124         SOC_REG_FLAG_ARRAY,
  82125         0,
  82126         1,
  82127         soc_OP_RESUME_OFFSET_COLOR_CELL_PROFILE_BCM56640_A0r_fields,
  82128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82129         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  82130         -1,
  82131         -1,
  82132     },
  82133 #endif /* chips */
  82134 
  82135 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  82136     { /* SOC_REG_INT_OP_RESUME_OFFSET_COLOR_CELL_PROFILE_BCM56840_A0r */
  82137         soc_block_list[4],
  82138         soc_genreg,
  82139         8,
  82140         0,
  82141         0x30800a0,
  82142         SOC_REG_FLAG_ARRAY,
  82143         0,
  82144         1,
  82145         soc_OP_RESUME_OFFSET_COLOR_CELL_PROFILE_BCM56840_A0r_fields,
  82146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82147         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  82148         -1,
  82149         -1,
  82150     },
  82151 #endif /* chips */
  82152 
  82153 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  82154     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  82155     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  82156     { /* SOC_REG_INT_OP_RESUME_OFFSET_COLOR_PACKET_PROFILEr */
  82157         soc_block_list[4],
  82158         soc_genreg,
  82159         8,
  82160         0,
  82161         0x3080038,
  82162         SOC_REG_FLAG_ARRAY,
  82163         0,
  82164         2,
  82165         soc_OP_RESUME_OFFSET_COLOR_PACKET_PROFILEr_fields,
  82166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82167         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  82168         -1,
  82169         -1,
  82170     },
  82171 #endif /* chips */
  82172 
  82173 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  82174     { /* SOC_REG_INT_OP_RESUME_OFFSET_COLOR_PACKET_PROFILE_BCM56334_A0r */
  82175         soc_block_list[4],
  82176         soc_genreg,
  82177         8,
  82178         0,
  82179         0x3080550,
  82180         SOC_REG_FLAG_ARRAY,
  82181         0,
  82182         2,
  82183         soc_OP_RESUME_OFFSET_COLOR_PACKET_PROFILE_BCM56334_A0r_fields,
  82184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82185         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  82186         -1,
  82187         -1,
  82188     },
  82189 #endif /* chips */
  82190 
  82191 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  82192     { /* SOC_REG_INT_OP_SP_BST_THRESHOLD_SELr */
  82193         soc_block_list[4],
  82194         soc_genreg,
  82195         1,
  82196         0,
  82197         0xe065100,
  82198         0,
  82199         0,
  82200         8,
  82201         soc_OP_SP_BST_THRESHOLD_SELr_fields,
  82202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82203         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  82204         -1,
  82205         -1,
  82206     },
  82207 #endif /* chips */
  82208 
  82209 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  82210     { /* SOC_REG_INT_OP_THDU_CONFIGr */
  82211         soc_block_list[4],
  82212         soc_genreg,
  82213         1,
  82214         0,
  82215         0xaa001200,
  82216         0,
  82217         0,
  82218         6,
  82219         soc_OP_THDU_CONFIGr_fields,
  82220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82221         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82222         -1,
  82223         -1,
  82224     },
  82225 #endif /* chips */
  82226 
  82227 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  82228     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  82229     { /* SOC_REG_INT_OP_THDU_CONFIG_BCM56560_A0r */
  82230         soc_block_list[4],
  82231         soc_genreg,
  82232         1,
  82233         0,
  82234         0xaa001200,
  82235         0,
  82236         0,
  82237         6,
  82238         soc_OP_THDU_CONFIG_BCM56560_A0r_fields,
  82239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82240         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82241         -1,
  82242         -1,
  82243     },
  82244 #endif /* chips */
  82245 
  82246 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  82247     defined(BCM_56870_A0) || defined(BCM_56960_A0) || \
  82248     defined(BCM_56965_A0) || defined(BCM_56970_A0)
  82249     { /* SOC_REG_INT_OP_THDU_CONFIG_BCM56960_A0r */
  82250         soc_block_list[124],
  82251         soc_genreg,
  82252         1,
  82253         0,
  82254         0x3a001200,
  82255         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82256         0,
  82257         6,
  82258         soc_OP_THDU_CONFIG_BCM56960_A0r_fields,
  82259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82260         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82261         -1,
  82262         -1,
  82263         3,
  82264     },
  82265 #endif /* chips */
  82266 
  82267 #if defined(BCM_56800_A0)
  82268     { /* SOC_REG_INT_OP_THR_CONFIGr */
  82269         soc_block_list[4],
  82270         soc_genreg,
  82271         1,
  82272         0,
  82273         0x3080002,
  82274         0,
  82275         0,
  82276         5,
  82277         soc_OP_THR_CONFIGr_fields,
  82278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82279         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  82280         -1,
  82281         -1,
  82282     },
  82283 #endif /* chips */
  82284 
  82285 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  82286     { /* SOC_REG_INT_OP_THR_CONFIG_BCM56260_A0r */
  82287         soc_block_list[4],
  82288         soc_genreg,
  82289         1,
  82290         0,
  82291         0xe001200,
  82292         0,
  82293         0,
  82294         3,
  82295         soc_OP_THR_CONFIG_BCM56260_A0r_fields,
  82296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82297         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82298         -1,
  82299         -1,
  82300     },
  82301 #endif /* chips */
  82302 
  82303 #if defined(BCM_56270_A0)
  82304     { /* SOC_REG_INT_OP_THR_CONFIG_BCM56270_A0r */
  82305         soc_block_list[4],
  82306         soc_genreg,
  82307         1,
  82308         0,
  82309         0xe001200,
  82310         0,
  82311         0,
  82312         12,
  82313         soc_OP_THR_CONFIG_BCM56270_A0r_fields,
  82314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82315         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  82316         -1,
  82317         -1,
  82318     },
  82319 #endif /* chips */
  82320 
  82321 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  82322     { /* SOC_REG_INT_OP_THR_CONFIG_BCM56440_A0r */
  82323         soc_block_list[4],
  82324         soc_genreg,
  82325         1,
  82326         0,
  82327         0x3080012,
  82328         0,
  82329         0,
  82330         3,
  82331         soc_OP_THR_CONFIG_BCM56440_A0r_fields,
  82332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82333         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82334         -1,
  82335         -1,
  82336     },
  82337 #endif /* chips */
  82338 
  82339 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  82340     defined(BCM_56450_B1)
  82341     { /* SOC_REG_INT_OP_THR_CONFIG_BCM56450_A0r */
  82342         soc_block_list[4],
  82343         soc_genreg,
  82344         1,
  82345         0,
  82346         0xe001200,
  82347         0,
  82348         0,
  82349         3,
  82350         soc_OP_THR_CONFIG_BCM56450_A0r_fields,
  82351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82352         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82353         -1,
  82354         -1,
  82355     },
  82356 #endif /* chips */
  82357 
  82358 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  82359     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  82360     { /* SOC_REG_INT_OP_THR_CONFIG_BCM56624_A0r */
  82361         soc_block_list[4],
  82362         soc_genreg,
  82363         1,
  82364         0,
  82365         0x3080007,
  82366         0,
  82367         0,
  82368         3,
  82369         soc_OP_THR_CONFIG_BCM56624_A0r_fields,
  82370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82371         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  82372         -1,
  82373         -1,
  82374     },
  82375 #endif /* chips */
  82376 
  82377 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  82378     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  82379     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  82380     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  82381     { /* SOC_REG_INT_OP_THR_CONFIG_BCM56634_A0r */
  82382         soc_block_list[4],
  82383         soc_genreg,
  82384         1,
  82385         0,
  82386         0x3080007,
  82387         0,
  82388         0,
  82389         3,
  82390         soc_OP_THR_CONFIG_BCM56634_A0r_fields,
  82391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82392         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82393         -1,
  82394         -1,
  82395     },
  82396 #endif /* chips */
  82397 
  82398 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  82399     { /* SOC_REG_INT_OP_THR_CONFIG_BCM56640_A0r */
  82400         soc_block_list[4],
  82401         soc_genreg,
  82402         1,
  82403         0,
  82404         0xe001200,
  82405         0,
  82406         0,
  82407         5,
  82408         soc_OP_THR_CONFIG_BCM56640_A0r_fields,
  82409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82410         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82411         -1,
  82412         -1,
  82413     },
  82414 #endif /* chips */
  82415 
  82416 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  82417     { /* SOC_REG_INT_OP_THR_CONFIG_BCM56820_A0r */
  82418         soc_block_list[4],
  82419         soc_genreg,
  82420         1,
  82421         0,
  82422         0x3080002,
  82423         0,
  82424         0,
  82425         6,
  82426         soc_OP_THR_CONFIG_BCM56820_A0r_fields,
  82427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82428         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  82429         -1,
  82430         -1,
  82431     },
  82432 #endif /* chips */
  82433 
  82434 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  82435     { /* SOC_REG_INT_OP_THR_CONFIG_BCM56840_A0r */
  82436         soc_block_list[4],
  82437         soc_genreg,
  82438         1,
  82439         0,
  82440         0x3080012,
  82441         0,
  82442         0,
  82443         7,
  82444         soc_OP_THR_CONFIG_BCM56840_A0r_fields,
  82445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82446         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  82447         -1,
  82448         -1,
  82449     },
  82450 #endif /* chips */
  82451 
  82452 #if defined(BCM_88732_A0)
  82453     { /* SOC_REG_INT_OP_THR_CONFIG_BCM88732_A0r */
  82454         soc_block_list[4],
  82455         soc_genreg,
  82456         1,
  82457         0,
  82458         0x3080002,
  82459         0,
  82460         0,
  82461         2,
  82462         soc_OP_THR_CONFIG_BCM88732_A0r_fields,
  82463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82464         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  82465         -1,
  82466         -1,
  82467     },
  82468 #endif /* chips */
  82469 
  82470 #if defined(BCM_56840_B0)
  82471     { /* SOC_REG_INT_OP_THR_CONFIG_PLUSr */
  82472         soc_block_list[4],
  82473         soc_genreg,
  82474         1,
  82475         0,
  82476         0x3080013,
  82477         0,
  82478         0,
  82479         4,
  82480         soc_OP_THR_CONFIG_PLUSr_fields,
  82481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82482         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  82483         -1,
  82484         -1,
  82485     },
  82486 #endif /* chips */
  82487 
  82488 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  82489     { /* SOC_REG_INT_OP_THR_CONFIG_PLUS_BCM56640_A0r */
  82490         soc_block_list[4],
  82491         soc_genreg,
  82492         1,
  82493         0,
  82494         0xe001300,
  82495         0,
  82496         0,
  82497         4,
  82498         soc_OP_THR_CONFIG_PLUS_BCM56640_A0r_fields,
  82499         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  82500         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  82501         -1,
  82502         -1,
  82503     },
  82504 #endif /* chips */
  82505 
  82506 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  82507     { /* SOC_REG_INT_OP_UC_PORT_BST_THRESHOLDr */
  82508         soc_block_list[4],
  82509         soc_genreg,
  82510         8,
  82511         0,
  82512         0xe063000,
  82513         SOC_REG_FLAG_ARRAY,
  82514         0,
  82515         2,
  82516         soc_OP_UC_PORT_BST_THRESHOLDr_fields,
  82517         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  82518         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  82519         -1,
  82520         -1,
  82521     },
  82522 #endif /* chips */
  82523 
  82524 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  82525     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  82526     { /* SOC_REG_INT_OP_UC_PORT_BST_THRESHOLD_BCM56560_A0r */
  82527         soc_block_list[4],
  82528         soc_genreg,
  82529         8,
  82530         0,
  82531         0xaa083000,
  82532         SOC_REG_FLAG_ARRAY,
  82533         0,
  82534         1,
  82535         soc_OP_UC_PORT_BST_THRESHOLD_BCM56560_A0r_fields,
  82536         SOC_RESET_VAL_DEC(0x00001fff, 0x00000000)
  82537         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  82538         -1,
  82539         -1,
  82540     },
  82541 #endif /* chips */
  82542 
  82543 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  82544     { /* SOC_REG_INT_OP_UC_PORT_BST_THRESHOLD_BCM56850_A0r */
  82545         soc_block_list[4],
  82546         soc_genreg,
  82547         8,
  82548         0,
  82549         0xaa083000,
  82550         SOC_REG_FLAG_ARRAY,
  82551         0,
  82552         1,
  82553         soc_OP_UC_PORT_BST_THRESHOLD_BCM56850_A0r_fields,
  82554         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
  82555         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  82556         -1,
  82557         -1,
  82558     },
  82559 #endif /* chips */
  82560 
  82561 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  82562     defined(BCM_56870_A0)
  82563     { /* SOC_REG_INT_OP_UC_PORT_BST_THRESHOLD_BCM56870_A0r */
  82564         soc_block_list[124],
  82565         soc_xpereg,
  82566         8,
  82567         0,
  82568         0x3a883000,
  82569         SOC_REG_FLAG_ARRAY |
  82570                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82571         0,
  82572         1,
  82573         soc_MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_BCM56960_A0r_fields,
  82574         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  82575         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  82576         -1,
  82577         -1,
  82578         3,
  82579     },
  82580 #endif /* chips */
  82581 
  82582 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  82583     { /* SOC_REG_INT_OP_UC_PORT_BST_THRESHOLD_BCM56960_A0r */
  82584         soc_block_list[124],
  82585         soc_xpereg,
  82586         8,
  82587         0,
  82588         0x3a883000,
  82589         SOC_REG_FLAG_ARRAY |
  82590                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82591         0,
  82592         1,
  82593         soc_OP_UC_PORT_BST_THRESHOLD_BCM56960_A0r_fields,
  82594         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  82595         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  82596         -1,
  82597         -1,
  82598         3,
  82599     },
  82600 #endif /* chips */
  82601 
  82602 #if defined(BCM_56970_A0)
  82603     { /* SOC_REG_INT_OP_UC_PORT_BST_THRESHOLD_BCM56970_A0r */
  82604         soc_block_list[124],
  82605         soc_xpereg,
  82606         8,
  82607         0,
  82608         0x3a883000,
  82609         SOC_REG_FLAG_ARRAY |
  82610                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82611         0,
  82612         1,
  82613         soc_OP_UC_PORT_BST_THRESHOLD_BCM56970_A0r_fields,
  82614         SOC_RESET_VAL_DEC(0x00001fff, 0x00000000)
  82615         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  82616         -1,
  82617         -1,
  82618         3,
  82619     },
  82620 #endif /* chips */
  82621 
  82622 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  82623     { /* SOC_REG_INT_OP_UC_PORT_CONFIG1_CELLr */
  82624         soc_block_list[4],
  82625         soc_portreg,
  82626         1,
  82627         0,
  82628         0x3000029,
  82629         0,
  82630         0,
  82631         12,
  82632         soc_OP_UC_PORT_CONFIG1_CELLr_fields,
  82633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82634         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  82635         -1,
  82636         37,
  82637     },
  82638 #endif /* chips */
  82639 
  82640 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  82641     { /* SOC_REG_INT_OP_UC_PORT_CONFIG_CELLr */
  82642         soc_block_list[4],
  82643         soc_portreg,
  82644         4,
  82645         0,
  82646         0x3000024,
  82647         SOC_REG_FLAG_ARRAY,
  82648         0,
  82649         2,
  82650         soc_OP_PORT_CONFIG_CELL_BCM56840_A0r_fields,
  82651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82652         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82653         -1,
  82654         37,
  82655     },
  82656 #endif /* chips */
  82657 
  82658 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  82659     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATEr */
  82660         soc_block_list[4],
  82661         soc_genreg,
  82662         4,
  82663         0,
  82664         0xe061000,
  82665         SOC_REG_FLAG_64_BITS |
  82666                           SOC_REG_FLAG_ARRAY |
  82667                           SOC_REG_FLAG_RO,
  82668         0,
  82669         1,
  82670         soc_OP_UC_PORT_DROP_STATEr_fields,
  82671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82672         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  82673         -1,
  82674         -1,
  82675     },
  82676 #endif /* chips */
  82677 
  82678 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  82679     defined(BCM_56970_A0)
  82680     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_BCM56960_A0r */
  82681         soc_block_list[124],
  82682         soc_pipereg,
  82683         4,
  82684         0,
  82685         0x39861000,
  82686         SOC_REG_FLAG_64_BITS |
  82687                           SOC_REG_FLAG_ARRAY |
  82688                           SOC_REG_FLAG_RO |
  82689                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82690         0,
  82691         1,
  82692         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  82693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82694         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  82695         -1,
  82696         -1,
  82697         3,
  82698     },
  82699 #endif /* chips */
  82700 
  82701 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  82702     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_CELL_BMP0_64r */
  82703         soc_block_list[4],
  82704         soc_genreg,
  82705         4,
  82706         0,
  82707         0x3080068,
  82708         SOC_REG_FLAG_64_BITS |
  82709                           SOC_REG_FLAG_ARRAY |
  82710                           SOC_REG_FLAG_RO,
  82711         0,
  82712         1,
  82713         soc_OP_UC_PORT_DROP_STATE_CELL_BMP0_64r_fields,
  82714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  82716         -1,
  82717         -1,
  82718     },
  82719 #endif /* chips */
  82720 
  82721 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  82722     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_CELL_BMP1_64r */
  82723         soc_block_list[4],
  82724         soc_genreg,
  82725         4,
  82726         0,
  82727         0x308006c,
  82728         SOC_REG_FLAG_64_BITS |
  82729                           SOC_REG_FLAG_ARRAY |
  82730                           SOC_REG_FLAG_RO,
  82731         0,
  82732         1,
  82733         soc_OP_UC_PORT_DROP_STATE_CELL_BMP1_64r_fields,
  82734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  82736         -1,
  82737         -1,
  82738     },
  82739 #endif /* chips */
  82740 
  82741 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  82742     defined(BCM_56870_A0)
  82743     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_SPLIT0r */
  82744         soc_block_list[124],
  82745         soc_pipereg,
  82746         4,
  82747         0,
  82748         0x39861000,
  82749         SOC_REG_FLAG_64_BITS |
  82750                           SOC_REG_FLAG_ARRAY |
  82751                           SOC_REG_FLAG_RO |
  82752                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82753         0,
  82754         1,
  82755         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  82756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82757         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  82758         -1,
  82759         -1,
  82760         3,
  82761     },
  82762 #endif /* chips */
  82763 
  82764 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  82765     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_SPLIT1r */
  82766         soc_block_list[124],
  82767         soc_pipereg,
  82768         4,
  82769         0,
  82770         0x39862000,
  82771         SOC_REG_FLAG_ARRAY |
  82772                           SOC_REG_FLAG_RO |
  82773                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82774         0,
  82775         1,
  82776         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  82777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82778         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  82779         -1,
  82780         -1,
  82781         3,
  82782     },
  82783 #endif /* chips */
  82784 
  82785 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  82786     defined(BCM_56870_A0)
  82787     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_SPLIT0_XPE0r */
  82788         soc_block_list[124],
  82789         soc_pipereg,
  82790         4,
  82791         0,
  82792         0x39861000,
  82793         SOC_REG_FLAG_64_BITS |
  82794                           SOC_REG_FLAG_ARRAY |
  82795                           SOC_REG_FLAG_RO,
  82796         0,
  82797         1,
  82798         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  82799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82800         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  82801         -1,
  82802         -1,
  82803         3,
  82804     },
  82805 #endif /* chips */
  82806 
  82807 #if defined(BCM_56370_A0)
  82808     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r */
  82809         soc_block_list[124],
  82810         soc_pipereg,
  82811         4,
  82812         0,
  82813         0x39862000,
  82814         SOC_REG_FLAG_ARRAY |
  82815                           SOC_REG_FLAG_RO |
  82816                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82817         0,
  82818         1,
  82819         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  82820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82821         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82822         -1,
  82823         -1,
  82824         3,
  82825     },
  82826 #endif /* chips */
  82827 
  82828 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  82829     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_SPLIT1_XPE0r */
  82830         soc_block_list[124],
  82831         soc_pipereg,
  82832         4,
  82833         0,
  82834         0x39862000,
  82835         SOC_REG_FLAG_ARRAY |
  82836                           SOC_REG_FLAG_RO,
  82837         0,
  82838         1,
  82839         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  82840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82841         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  82842         -1,
  82843         -1,
  82844         3,
  82845     },
  82846 #endif /* chips */
  82847 
  82848 #if defined(BCM_56370_A0)
  82849     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_SPLIT1_XPE0_BCM56370_A0r */
  82850         soc_block_list[124],
  82851         soc_pipereg,
  82852         4,
  82853         0,
  82854         0x39862000,
  82855         SOC_REG_FLAG_ARRAY |
  82856                           SOC_REG_FLAG_RO,
  82857         0,
  82858         1,
  82859         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  82860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82861         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82862         -1,
  82863         -1,
  82864         3,
  82865     },
  82866 #endif /* chips */
  82867 
  82868 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  82869     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_Xr */
  82870         soc_block_list[4],
  82871         soc_genreg,
  82872         4,
  82873         0,
  82874         0xaa061000,
  82875         SOC_REG_FLAG_64_BITS |
  82876                           SOC_REG_FLAG_ARRAY |
  82877                           SOC_REG_FLAG_RO,
  82878         0,
  82879         1,
  82880         soc_OP_UC_PORT_DROP_STATE_Xr_fields,
  82881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82882         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
  82883         -1,
  82884         -1,
  82885     },
  82886 #endif /* chips */
  82887 
  82888 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  82889     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  82890     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_X0r */
  82891         soc_block_list[4],
  82892         soc_genreg,
  82893         4,
  82894         0,
  82895         0xaa061000,
  82896         SOC_REG_FLAG_64_BITS |
  82897                           SOC_REG_FLAG_ARRAY |
  82898                           SOC_REG_FLAG_RO,
  82899         0,
  82900         1,
  82901         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  82902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82903         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  82904         -1,
  82905         -1,
  82906     },
  82907 #endif /* chips */
  82908 
  82909 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  82910     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_X1r */
  82911         soc_block_list[4],
  82912         soc_genreg,
  82913         4,
  82914         0,
  82915         0xaa061800,
  82916         SOC_REG_FLAG_64_BITS |
  82917                           SOC_REG_FLAG_ARRAY |
  82918                           SOC_REG_FLAG_RO,
  82919         0,
  82920         1,
  82921         soc_OP_UC_PORT_DROP_STATE_X1r_fields,
  82922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82923         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  82924         -1,
  82925         -1,
  82926     },
  82927 #endif /* chips */
  82928 
  82929 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  82930     defined(BCM_56970_A0)
  82931     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_XPE0r */
  82932         soc_block_list[124],
  82933         soc_pipereg,
  82934         4,
  82935         0,
  82936         0x39861000,
  82937         SOC_REG_FLAG_64_BITS |
  82938                           SOC_REG_FLAG_ARRAY |
  82939                           SOC_REG_FLAG_RO,
  82940         0,
  82941         1,
  82942         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  82943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82944         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  82945         -1,
  82946         -1,
  82947         3,
  82948     },
  82949 #endif /* chips */
  82950 
  82951 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  82952     defined(BCM_56970_A0)
  82953     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_XPE1r */
  82954         soc_block_list[124],
  82955         soc_pipereg,
  82956         4,
  82957         0,
  82958         0x39861000,
  82959         SOC_REG_FLAG_64_BITS |
  82960                           SOC_REG_FLAG_ARRAY |
  82961                           SOC_REG_FLAG_RO |
  82962                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82963         0,
  82964         1,
  82965         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  82966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82967         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  82968         -1,
  82969         -1,
  82970         3,
  82971     },
  82972 #endif /* chips */
  82973 
  82974 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  82975     defined(BCM_56970_A0)
  82976     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_XPE2r */
  82977         soc_block_list[124],
  82978         soc_pipereg,
  82979         4,
  82980         0,
  82981         0x39861000,
  82982         SOC_REG_FLAG_64_BITS |
  82983                           SOC_REG_FLAG_ARRAY |
  82984                           SOC_REG_FLAG_RO |
  82985                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  82986         0,
  82987         1,
  82988         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  82989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82990         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  82991         -1,
  82992         -1,
  82993         3,
  82994     },
  82995 #endif /* chips */
  82996 
  82997 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  82998     defined(BCM_56970_A0)
  82999     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_XPE3r */
  83000         soc_block_list[124],
  83001         soc_pipereg,
  83002         4,
  83003         0,
  83004         0x39861000,
  83005         SOC_REG_FLAG_64_BITS |
  83006                           SOC_REG_FLAG_ARRAY |
  83007                           SOC_REG_FLAG_RO |
  83008                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83009         0,
  83010         1,
  83011         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83013         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83014         -1,
  83015         -1,
  83016         3,
  83017     },
  83018 #endif /* chips */
  83019 
  83020 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  83021     { /* SOC_REG_INT_OP_UC_PORT_DROP_STATE_Yr */
  83022         soc_block_list[4],
  83023         soc_genreg,
  83024         4,
  83025         0,
  83026         0xaa061800,
  83027         SOC_REG_FLAG_64_BITS |
  83028                           SOC_REG_FLAG_ARRAY |
  83029                           SOC_REG_FLAG_RO,
  83030         0,
  83031         1,
  83032         soc_OP_UC_PORT_DROP_STATE_Xr_fields,
  83033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83034         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
  83035         -1,
  83036         -1,
  83037     },
  83038 #endif /* chips */
  83039 
  83040 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  83041     { /* SOC_REG_INT_OP_UC_PORT_LIMIT_COLOR_CELLr */
  83042         soc_block_list[4],
  83043         soc_portreg,
  83044         4,
  83045         0,
  83046         0x300003c,
  83047         SOC_REG_FLAG_ARRAY,
  83048         0,
  83049         2,
  83050         soc_OP_UC_PORT_LIMIT_COLOR_CELLr_fields,
  83051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83052         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  83053         -1,
  83054         37,
  83055     },
  83056 #endif /* chips */
  83057 
  83058 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  83059     { /* SOC_REG_INT_OP_UC_PORT_LIMIT_RESUME_COLOR_CELLr */
  83060         soc_block_list[4],
  83061         soc_portreg,
  83062         4,
  83063         0,
  83064         0x3000094,
  83065         SOC_REG_FLAG_ARRAY,
  83066         0,
  83067         2,
  83068         soc_OP_UC_PORT_LIMIT_COLOR_CELLr_fields,
  83069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83070         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  83071         -1,
  83072         37,
  83073     },
  83074 #endif /* chips */
  83075 
  83076 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  83077     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATEr */
  83078         soc_block_list[4],
  83079         soc_genreg,
  83080         4,
  83081         0,
  83082         0xe061800,
  83083         SOC_REG_FLAG_64_BITS |
  83084                           SOC_REG_FLAG_ARRAY |
  83085                           SOC_REG_FLAG_RO,
  83086         0,
  83087         1,
  83088         soc_OP_UC_PORT_DROP_STATEr_fields,
  83089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83090         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  83091         -1,
  83092         -1,
  83093     },
  83094 #endif /* chips */
  83095 
  83096 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83097     defined(BCM_56970_A0)
  83098     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_BCM56960_A0r */
  83099         soc_block_list[124],
  83100         soc_pipereg,
  83101         4,
  83102         0,
  83103         0x39863000,
  83104         SOC_REG_FLAG_64_BITS |
  83105                           SOC_REG_FLAG_ARRAY |
  83106                           SOC_REG_FLAG_RO |
  83107                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83108         0,
  83109         1,
  83110         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83112         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83113         -1,
  83114         -1,
  83115         3,
  83116     },
  83117 #endif /* chips */
  83118 
  83119 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  83120     defined(BCM_56870_A0)
  83121     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_SPLIT0r */
  83122         soc_block_list[124],
  83123         soc_pipereg,
  83124         4,
  83125         0,
  83126         0x39865000,
  83127         SOC_REG_FLAG_64_BITS |
  83128                           SOC_REG_FLAG_ARRAY |
  83129                           SOC_REG_FLAG_RO |
  83130                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83131         0,
  83132         1,
  83133         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  83134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83135         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  83136         -1,
  83137         -1,
  83138         3,
  83139     },
  83140 #endif /* chips */
  83141 
  83142 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  83143     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_SPLIT1r */
  83144         soc_block_list[124],
  83145         soc_pipereg,
  83146         4,
  83147         0,
  83148         0x39866000,
  83149         SOC_REG_FLAG_ARRAY |
  83150                           SOC_REG_FLAG_RO |
  83151                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83152         0,
  83153         1,
  83154         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  83155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83156         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  83157         -1,
  83158         -1,
  83159         3,
  83160     },
  83161 #endif /* chips */
  83162 
  83163 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  83164     defined(BCM_56870_A0)
  83165     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_SPLIT0_XPE0r */
  83166         soc_block_list[124],
  83167         soc_pipereg,
  83168         4,
  83169         0,
  83170         0x39865000,
  83171         SOC_REG_FLAG_64_BITS |
  83172                           SOC_REG_FLAG_ARRAY |
  83173                           SOC_REG_FLAG_RO,
  83174         0,
  83175         1,
  83176         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  83177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83178         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  83179         -1,
  83180         -1,
  83181         3,
  83182     },
  83183 #endif /* chips */
  83184 
  83185 #if defined(BCM_56370_A0)
  83186     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_SPLIT1_BCM56370_A0r */
  83187         soc_block_list[124],
  83188         soc_pipereg,
  83189         4,
  83190         0,
  83191         0x39866000,
  83192         SOC_REG_FLAG_ARRAY |
  83193                           SOC_REG_FLAG_RO |
  83194                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83195         0,
  83196         1,
  83197         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  83198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83199         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  83200         -1,
  83201         -1,
  83202         3,
  83203     },
  83204 #endif /* chips */
  83205 
  83206 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  83207     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_SPLIT1_XPE0r */
  83208         soc_block_list[124],
  83209         soc_pipereg,
  83210         4,
  83211         0,
  83212         0x39866000,
  83213         SOC_REG_FLAG_ARRAY |
  83214                           SOC_REG_FLAG_RO,
  83215         0,
  83216         1,
  83217         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  83218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83219         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  83220         -1,
  83221         -1,
  83222         3,
  83223     },
  83224 #endif /* chips */
  83225 
  83226 #if defined(BCM_56370_A0)
  83227     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_SPLIT1_XPE0_BCM56370_A0r */
  83228         soc_block_list[124],
  83229         soc_pipereg,
  83230         4,
  83231         0,
  83232         0x39866000,
  83233         SOC_REG_FLAG_ARRAY |
  83234                           SOC_REG_FLAG_RO,
  83235         0,
  83236         1,
  83237         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  83238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83239         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  83240         -1,
  83241         -1,
  83242         3,
  83243     },
  83244 #endif /* chips */
  83245 
  83246 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  83247     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_Xr */
  83248         soc_block_list[4],
  83249         soc_genreg,
  83250         4,
  83251         0,
  83252         0xaa063000,
  83253         SOC_REG_FLAG_64_BITS |
  83254                           SOC_REG_FLAG_ARRAY |
  83255                           SOC_REG_FLAG_RO,
  83256         0,
  83257         1,
  83258         soc_OP_UC_PORT_DROP_STATE_Xr_fields,
  83259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83260         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
  83261         -1,
  83262         -1,
  83263     },
  83264 #endif /* chips */
  83265 
  83266 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  83267     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  83268     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_X0r */
  83269         soc_block_list[4],
  83270         soc_genreg,
  83271         4,
  83272         0,
  83273         0xaa063000,
  83274         SOC_REG_FLAG_64_BITS |
  83275                           SOC_REG_FLAG_ARRAY |
  83276                           SOC_REG_FLAG_RO,
  83277         0,
  83278         1,
  83279         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  83280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83281         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  83282         -1,
  83283         -1,
  83284     },
  83285 #endif /* chips */
  83286 
  83287 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  83288     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_X1r */
  83289         soc_block_list[4],
  83290         soc_genreg,
  83291         4,
  83292         0,
  83293         0xaa063800,
  83294         SOC_REG_FLAG_64_BITS |
  83295                           SOC_REG_FLAG_ARRAY |
  83296                           SOC_REG_FLAG_RO,
  83297         0,
  83298         1,
  83299         soc_OP_UC_PORT_DROP_STATE_X1r_fields,
  83300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83301         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  83302         -1,
  83303         -1,
  83304     },
  83305 #endif /* chips */
  83306 
  83307 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83308     defined(BCM_56970_A0)
  83309     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_XPE0r */
  83310         soc_block_list[124],
  83311         soc_pipereg,
  83312         4,
  83313         0,
  83314         0x39863000,
  83315         SOC_REG_FLAG_64_BITS |
  83316                           SOC_REG_FLAG_ARRAY |
  83317                           SOC_REG_FLAG_RO,
  83318         0,
  83319         1,
  83320         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83322         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83323         -1,
  83324         -1,
  83325         3,
  83326     },
  83327 #endif /* chips */
  83328 
  83329 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83330     defined(BCM_56970_A0)
  83331     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_XPE1r */
  83332         soc_block_list[124],
  83333         soc_pipereg,
  83334         4,
  83335         0,
  83336         0x39863000,
  83337         SOC_REG_FLAG_64_BITS |
  83338                           SOC_REG_FLAG_ARRAY |
  83339                           SOC_REG_FLAG_RO |
  83340                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83341         0,
  83342         1,
  83343         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83346         -1,
  83347         -1,
  83348         3,
  83349     },
  83350 #endif /* chips */
  83351 
  83352 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83353     defined(BCM_56970_A0)
  83354     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_XPE2r */
  83355         soc_block_list[124],
  83356         soc_pipereg,
  83357         4,
  83358         0,
  83359         0x39863000,
  83360         SOC_REG_FLAG_64_BITS |
  83361                           SOC_REG_FLAG_ARRAY |
  83362                           SOC_REG_FLAG_RO |
  83363                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83364         0,
  83365         1,
  83366         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83369         -1,
  83370         -1,
  83371         3,
  83372     },
  83373 #endif /* chips */
  83374 
  83375 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83376     defined(BCM_56970_A0)
  83377     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_XPE3r */
  83378         soc_block_list[124],
  83379         soc_pipereg,
  83380         4,
  83381         0,
  83382         0x39863000,
  83383         SOC_REG_FLAG_64_BITS |
  83384                           SOC_REG_FLAG_ARRAY |
  83385                           SOC_REG_FLAG_RO |
  83386                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83387         0,
  83388         1,
  83389         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83392         -1,
  83393         -1,
  83394         3,
  83395     },
  83396 #endif /* chips */
  83397 
  83398 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  83399     { /* SOC_REG_INT_OP_UC_PORT_RED_DROP_STATE_Yr */
  83400         soc_block_list[4],
  83401         soc_genreg,
  83402         4,
  83403         0,
  83404         0xaa063800,
  83405         SOC_REG_FLAG_64_BITS |
  83406                           SOC_REG_FLAG_ARRAY |
  83407                           SOC_REG_FLAG_RO,
  83408         0,
  83409         1,
  83410         soc_OP_UC_PORT_DROP_STATE_Xr_fields,
  83411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83412         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
  83413         -1,
  83414         -1,
  83415     },
  83416 #endif /* chips */
  83417 
  83418 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  83419     { /* SOC_REG_INT_OP_UC_PORT_SHARED_COUNT_CELLr */
  83420         soc_block_list[4],
  83421         soc_portreg,
  83422         4,
  83423         0,
  83424         0x3000054,
  83425         SOC_REG_FLAG_ARRAY |
  83426                           SOC_REG_FLAG_RO,
  83427         0,
  83428         1,
  83429         soc_OP_UC_PORT_SHARED_COUNT_CELLr_fields,
  83430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83431         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  83432         -1,
  83433         37,
  83434     },
  83435 #endif /* chips */
  83436 
  83437 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  83438     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATEr */
  83439         soc_block_list[4],
  83440         soc_genreg,
  83441         4,
  83442         0,
  83443         0xe061400,
  83444         SOC_REG_FLAG_64_BITS |
  83445                           SOC_REG_FLAG_ARRAY |
  83446                           SOC_REG_FLAG_RO,
  83447         0,
  83448         1,
  83449         soc_OP_UC_PORT_DROP_STATEr_fields,
  83450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83451         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  83452         -1,
  83453         -1,
  83454     },
  83455 #endif /* chips */
  83456 
  83457 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83458     defined(BCM_56970_A0)
  83459     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_BCM56960_A0r */
  83460         soc_block_list[124],
  83461         soc_pipereg,
  83462         4,
  83463         0,
  83464         0x39862000,
  83465         SOC_REG_FLAG_64_BITS |
  83466                           SOC_REG_FLAG_ARRAY |
  83467                           SOC_REG_FLAG_RO |
  83468                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83469         0,
  83470         1,
  83471         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83473         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83474         -1,
  83475         -1,
  83476         3,
  83477     },
  83478 #endif /* chips */
  83479 
  83480 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  83481     defined(BCM_56870_A0)
  83482     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_SPLIT0r */
  83483         soc_block_list[124],
  83484         soc_pipereg,
  83485         4,
  83486         0,
  83487         0x39863000,
  83488         SOC_REG_FLAG_64_BITS |
  83489                           SOC_REG_FLAG_ARRAY |
  83490                           SOC_REG_FLAG_RO |
  83491                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83492         0,
  83493         1,
  83494         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  83495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83496         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  83497         -1,
  83498         -1,
  83499         3,
  83500     },
  83501 #endif /* chips */
  83502 
  83503 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  83504     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_SPLIT1r */
  83505         soc_block_list[124],
  83506         soc_pipereg,
  83507         4,
  83508         0,
  83509         0x39864000,
  83510         SOC_REG_FLAG_ARRAY |
  83511                           SOC_REG_FLAG_RO |
  83512                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83513         0,
  83514         1,
  83515         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  83516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83517         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  83518         -1,
  83519         -1,
  83520         3,
  83521     },
  83522 #endif /* chips */
  83523 
  83524 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  83525     defined(BCM_56870_A0)
  83526     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_SPLIT0_XPE0r */
  83527         soc_block_list[124],
  83528         soc_pipereg,
  83529         4,
  83530         0,
  83531         0x39863000,
  83532         SOC_REG_FLAG_64_BITS |
  83533                           SOC_REG_FLAG_ARRAY |
  83534                           SOC_REG_FLAG_RO,
  83535         0,
  83536         1,
  83537         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  83538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83539         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  83540         -1,
  83541         -1,
  83542         3,
  83543     },
  83544 #endif /* chips */
  83545 
  83546 #if defined(BCM_56370_A0)
  83547     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_SPLIT1_BCM56370_A0r */
  83548         soc_block_list[124],
  83549         soc_pipereg,
  83550         4,
  83551         0,
  83552         0x39864000,
  83553         SOC_REG_FLAG_ARRAY |
  83554                           SOC_REG_FLAG_RO |
  83555                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83556         0,
  83557         1,
  83558         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  83559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83560         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  83561         -1,
  83562         -1,
  83563         3,
  83564     },
  83565 #endif /* chips */
  83566 
  83567 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  83568     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_SPLIT1_XPE0r */
  83569         soc_block_list[124],
  83570         soc_pipereg,
  83571         4,
  83572         0,
  83573         0x39864000,
  83574         SOC_REG_FLAG_ARRAY |
  83575                           SOC_REG_FLAG_RO,
  83576         0,
  83577         1,
  83578         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  83579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83580         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  83581         -1,
  83582         -1,
  83583         3,
  83584     },
  83585 #endif /* chips */
  83586 
  83587 #if defined(BCM_56370_A0)
  83588     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_SPLIT1_XPE0_BCM56370_A0r */
  83589         soc_block_list[124],
  83590         soc_pipereg,
  83591         4,
  83592         0,
  83593         0x39864000,
  83594         SOC_REG_FLAG_ARRAY |
  83595                           SOC_REG_FLAG_RO,
  83596         0,
  83597         1,
  83598         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  83599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83600         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  83601         -1,
  83602         -1,
  83603         3,
  83604     },
  83605 #endif /* chips */
  83606 
  83607 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  83608     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_Xr */
  83609         soc_block_list[4],
  83610         soc_genreg,
  83611         4,
  83612         0,
  83613         0xaa062000,
  83614         SOC_REG_FLAG_64_BITS |
  83615                           SOC_REG_FLAG_ARRAY |
  83616                           SOC_REG_FLAG_RO,
  83617         0,
  83618         1,
  83619         soc_OP_UC_PORT_DROP_STATE_Xr_fields,
  83620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83621         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
  83622         -1,
  83623         -1,
  83624     },
  83625 #endif /* chips */
  83626 
  83627 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  83628     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  83629     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_X0r */
  83630         soc_block_list[4],
  83631         soc_genreg,
  83632         4,
  83633         0,
  83634         0xaa062000,
  83635         SOC_REG_FLAG_64_BITS |
  83636                           SOC_REG_FLAG_ARRAY |
  83637                           SOC_REG_FLAG_RO,
  83638         0,
  83639         1,
  83640         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  83641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83642         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  83643         -1,
  83644         -1,
  83645     },
  83646 #endif /* chips */
  83647 
  83648 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  83649     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_X1r */
  83650         soc_block_list[4],
  83651         soc_genreg,
  83652         4,
  83653         0,
  83654         0xaa062800,
  83655         SOC_REG_FLAG_64_BITS |
  83656                           SOC_REG_FLAG_ARRAY |
  83657                           SOC_REG_FLAG_RO,
  83658         0,
  83659         1,
  83660         soc_OP_UC_PORT_DROP_STATE_X1r_fields,
  83661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83662         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  83663         -1,
  83664         -1,
  83665     },
  83666 #endif /* chips */
  83667 
  83668 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83669     defined(BCM_56970_A0)
  83670     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_XPE0r */
  83671         soc_block_list[124],
  83672         soc_pipereg,
  83673         4,
  83674         0,
  83675         0x39862000,
  83676         SOC_REG_FLAG_64_BITS |
  83677                           SOC_REG_FLAG_ARRAY |
  83678                           SOC_REG_FLAG_RO,
  83679         0,
  83680         1,
  83681         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83684         -1,
  83685         -1,
  83686         3,
  83687     },
  83688 #endif /* chips */
  83689 
  83690 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83691     defined(BCM_56970_A0)
  83692     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_XPE1r */
  83693         soc_block_list[124],
  83694         soc_pipereg,
  83695         4,
  83696         0,
  83697         0x39862000,
  83698         SOC_REG_FLAG_64_BITS |
  83699                           SOC_REG_FLAG_ARRAY |
  83700                           SOC_REG_FLAG_RO |
  83701                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83702         0,
  83703         1,
  83704         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83707         -1,
  83708         -1,
  83709         3,
  83710     },
  83711 #endif /* chips */
  83712 
  83713 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83714     defined(BCM_56970_A0)
  83715     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_XPE2r */
  83716         soc_block_list[124],
  83717         soc_pipereg,
  83718         4,
  83719         0,
  83720         0x39862000,
  83721         SOC_REG_FLAG_64_BITS |
  83722                           SOC_REG_FLAG_ARRAY |
  83723                           SOC_REG_FLAG_RO |
  83724                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83725         0,
  83726         1,
  83727         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83729         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83730         -1,
  83731         -1,
  83732         3,
  83733     },
  83734 #endif /* chips */
  83735 
  83736 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83737     defined(BCM_56970_A0)
  83738     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_XPE3r */
  83739         soc_block_list[124],
  83740         soc_pipereg,
  83741         4,
  83742         0,
  83743         0x39862000,
  83744         SOC_REG_FLAG_64_BITS |
  83745                           SOC_REG_FLAG_ARRAY |
  83746                           SOC_REG_FLAG_RO |
  83747                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83748         0,
  83749         1,
  83750         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83752         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83753         -1,
  83754         -1,
  83755         3,
  83756     },
  83757 #endif /* chips */
  83758 
  83759 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  83760     { /* SOC_REG_INT_OP_UC_PORT_YELLOW_DROP_STATE_Yr */
  83761         soc_block_list[4],
  83762         soc_genreg,
  83763         4,
  83764         0,
  83765         0xaa062800,
  83766         SOC_REG_FLAG_64_BITS |
  83767                           SOC_REG_FLAG_ARRAY |
  83768                           SOC_REG_FLAG_RO,
  83769         0,
  83770         1,
  83771         soc_OP_UC_PORT_DROP_STATE_Xr_fields,
  83772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83773         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
  83774         -1,
  83775         -1,
  83776     },
  83777 #endif /* chips */
  83778 
  83779 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  83780     { /* SOC_REG_INT_OP_UC_QGROUP_BST_THRESHOLDr */
  83781         soc_block_list[4],
  83782         soc_genreg,
  83783         8,
  83784         0,
  83785         0xe062800,
  83786         SOC_REG_FLAG_ARRAY,
  83787         0,
  83788         2,
  83789         soc_OP_UC_PORT_BST_THRESHOLDr_fields,
  83790         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  83791         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  83792         -1,
  83793         -1,
  83794     },
  83795 #endif /* chips */
  83796 
  83797 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  83798     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  83799     { /* SOC_REG_INT_OP_UC_QGROUP_BST_THRESHOLD_BCM56560_A0r */
  83800         soc_block_list[4],
  83801         soc_genreg,
  83802         8,
  83803         0,
  83804         0xaa082800,
  83805         SOC_REG_FLAG_ARRAY,
  83806         0,
  83807         1,
  83808         soc_OP_UC_PORT_BST_THRESHOLD_BCM56560_A0r_fields,
  83809         SOC_RESET_VAL_DEC(0x00001fff, 0x00000000)
  83810         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  83811         -1,
  83812         -1,
  83813     },
  83814 #endif /* chips */
  83815 
  83816 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  83817     { /* SOC_REG_INT_OP_UC_QGROUP_BST_THRESHOLD_BCM56850_A0r */
  83818         soc_block_list[4],
  83819         soc_genreg,
  83820         8,
  83821         0,
  83822         0xaa082800,
  83823         SOC_REG_FLAG_ARRAY,
  83824         0,
  83825         1,
  83826         soc_OP_UC_PORT_BST_THRESHOLD_BCM56850_A0r_fields,
  83827         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
  83828         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  83829         -1,
  83830         -1,
  83831     },
  83832 #endif /* chips */
  83833 
  83834 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  83835     defined(BCM_56870_A0)
  83836     { /* SOC_REG_INT_OP_UC_QGROUP_BST_THRESHOLD_BCM56870_A0r */
  83837         soc_block_list[124],
  83838         soc_xpereg,
  83839         8,
  83840         0,
  83841         0x3a882800,
  83842         SOC_REG_FLAG_ARRAY |
  83843                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83844         0,
  83845         1,
  83846         soc_MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_BCM56960_A0r_fields,
  83847         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  83848         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  83849         -1,
  83850         -1,
  83851         3,
  83852     },
  83853 #endif /* chips */
  83854 
  83855 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  83856     { /* SOC_REG_INT_OP_UC_QGROUP_BST_THRESHOLD_BCM56960_A0r */
  83857         soc_block_list[124],
  83858         soc_xpereg,
  83859         8,
  83860         0,
  83861         0x3a882800,
  83862         SOC_REG_FLAG_ARRAY |
  83863                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83864         0,
  83865         1,
  83866         soc_OP_UC_PORT_BST_THRESHOLD_BCM56960_A0r_fields,
  83867         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  83868         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  83869         -1,
  83870         -1,
  83871         3,
  83872     },
  83873 #endif /* chips */
  83874 
  83875 #if defined(BCM_56970_A0)
  83876     { /* SOC_REG_INT_OP_UC_QGROUP_BST_THRESHOLD_BCM56970_A0r */
  83877         soc_block_list[124],
  83878         soc_xpereg,
  83879         8,
  83880         0,
  83881         0x3a882800,
  83882         SOC_REG_FLAG_ARRAY |
  83883                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83884         0,
  83885         1,
  83886         soc_OP_UC_PORT_BST_THRESHOLD_BCM56970_A0r_fields,
  83887         SOC_RESET_VAL_DEC(0x00001fff, 0x00000000)
  83888         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  83889         -1,
  83890         -1,
  83891         3,
  83892     },
  83893 #endif /* chips */
  83894 
  83895 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  83896     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATEr */
  83897         soc_block_list[4],
  83898         soc_genreg,
  83899         4,
  83900         0,
  83901         0xe060000,
  83902         SOC_REG_FLAG_64_BITS |
  83903                           SOC_REG_FLAG_ARRAY |
  83904                           SOC_REG_FLAG_RO,
  83905         0,
  83906         1,
  83907         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  83908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83909         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  83910         -1,
  83911         -1,
  83912     },
  83913 #endif /* chips */
  83914 
  83915 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  83916     defined(BCM_56970_A0)
  83917     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_BCM56960_A0r */
  83918         soc_block_list[124],
  83919         soc_pipereg,
  83920         1,
  83921         0,
  83922         0x39850000,
  83923         SOC_REG_FLAG_64_BITS |
  83924                           SOC_REG_FLAG_RO |
  83925                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83926         0,
  83927         1,
  83928         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  83929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83930         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  83931         -1,
  83932         -1,
  83933         3,
  83934     },
  83935 #endif /* chips */
  83936 
  83937 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  83938     defined(BCM_56870_A0)
  83939     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_SPLIT0r */
  83940         soc_block_list[124],
  83941         soc_pipereg,
  83942         1,
  83943         0,
  83944         0x39850000,
  83945         SOC_REG_FLAG_64_BITS |
  83946                           SOC_REG_FLAG_RO |
  83947                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83948         0,
  83949         1,
  83950         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  83951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83952         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  83953         -1,
  83954         -1,
  83955         3,
  83956     },
  83957 #endif /* chips */
  83958 
  83959 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  83960     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_SPLIT1r */
  83961         soc_block_list[124],
  83962         soc_pipereg,
  83963         1,
  83964         0,
  83965         0x39851000,
  83966         SOC_REG_FLAG_RO |
  83967                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83968         0,
  83969         1,
  83970         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  83971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83972         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  83973         -1,
  83974         -1,
  83975         3,
  83976     },
  83977 #endif /* chips */
  83978 
  83979 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  83980     defined(BCM_56870_A0)
  83981     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_SPLIT0_XPE0r */
  83982         soc_block_list[124],
  83983         soc_pipereg,
  83984         1,
  83985         0,
  83986         0x39850000,
  83987         SOC_REG_FLAG_64_BITS |
  83988                           SOC_REG_FLAG_RO,
  83989         0,
  83990         1,
  83991         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  83992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83993         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  83994         -1,
  83995         -1,
  83996         3,
  83997     },
  83998 #endif /* chips */
  83999 
  84000 #if defined(BCM_56370_A0)
  84001     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_SPLIT1_BCM56370_A0r */
  84002         soc_block_list[124],
  84003         soc_pipereg,
  84004         1,
  84005         0,
  84006         0x39851000,
  84007         SOC_REG_FLAG_RO |
  84008                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84009         0,
  84010         1,
  84011         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  84012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84013         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  84014         -1,
  84015         -1,
  84016         3,
  84017     },
  84018 #endif /* chips */
  84019 
  84020 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  84021     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_SPLIT1_XPE0r */
  84022         soc_block_list[124],
  84023         soc_pipereg,
  84024         1,
  84025         0,
  84026         0x39851000,
  84027         SOC_REG_FLAG_RO,
  84028         0,
  84029         1,
  84030         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  84031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84032         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  84033         -1,
  84034         -1,
  84035         3,
  84036     },
  84037 #endif /* chips */
  84038 
  84039 #if defined(BCM_56370_A0)
  84040     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_SPLIT1_XPE0_BCM56370_A0r */
  84041         soc_block_list[124],
  84042         soc_pipereg,
  84043         1,
  84044         0,
  84045         0x39851000,
  84046         SOC_REG_FLAG_RO,
  84047         0,
  84048         1,
  84049         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  84050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84051         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  84052         -1,
  84053         -1,
  84054         3,
  84055     },
  84056 #endif /* chips */
  84057 
  84058 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84059     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_Xr */
  84060         soc_block_list[4],
  84061         soc_genreg,
  84062         2,
  84063         0,
  84064         0xaa050000,
  84065         SOC_REG_FLAG_64_BITS |
  84066                           SOC_REG_FLAG_ARRAY |
  84067                           SOC_REG_FLAG_RO,
  84068         0,
  84069         1,
  84070         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84072         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84073         -1,
  84074         -1,
  84075     },
  84076 #endif /* chips */
  84077 
  84078 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84079     defined(BCM_56970_A0)
  84080     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_XPE0r */
  84081         soc_block_list[124],
  84082         soc_pipereg,
  84083         1,
  84084         0,
  84085         0x39850000,
  84086         SOC_REG_FLAG_64_BITS |
  84087                           SOC_REG_FLAG_RO,
  84088         0,
  84089         1,
  84090         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84092         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84093         -1,
  84094         -1,
  84095         3,
  84096     },
  84097 #endif /* chips */
  84098 
  84099 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84100     defined(BCM_56970_A0)
  84101     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_XPE1r */
  84102         soc_block_list[124],
  84103         soc_pipereg,
  84104         1,
  84105         0,
  84106         0x39850000,
  84107         SOC_REG_FLAG_64_BITS |
  84108                           SOC_REG_FLAG_RO |
  84109                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84110         0,
  84111         1,
  84112         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84114         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84115         -1,
  84116         -1,
  84117         3,
  84118     },
  84119 #endif /* chips */
  84120 
  84121 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84122     defined(BCM_56970_A0)
  84123     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_XPE2r */
  84124         soc_block_list[124],
  84125         soc_pipereg,
  84126         1,
  84127         0,
  84128         0x39850000,
  84129         SOC_REG_FLAG_64_BITS |
  84130                           SOC_REG_FLAG_RO |
  84131                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84132         0,
  84133         1,
  84134         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84137         -1,
  84138         -1,
  84139         3,
  84140     },
  84141 #endif /* chips */
  84142 
  84143 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84144     defined(BCM_56970_A0)
  84145     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_XPE3r */
  84146         soc_block_list[124],
  84147         soc_pipereg,
  84148         1,
  84149         0,
  84150         0x39850000,
  84151         SOC_REG_FLAG_64_BITS |
  84152                           SOC_REG_FLAG_RO |
  84153                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84154         0,
  84155         1,
  84156         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84158         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84159         -1,
  84160         -1,
  84161         3,
  84162     },
  84163 #endif /* chips */
  84164 
  84165 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84166     { /* SOC_REG_INT_OP_UC_QGROUP_DROP_STATE_Yr */
  84167         soc_block_list[4],
  84168         soc_genreg,
  84169         2,
  84170         0,
  84171         0xaa051000,
  84172         SOC_REG_FLAG_64_BITS |
  84173                           SOC_REG_FLAG_ARRAY |
  84174                           SOC_REG_FLAG_RO,
  84175         0,
  84176         1,
  84177         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84179         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84180         -1,
  84181         -1,
  84182     },
  84183 #endif /* chips */
  84184 
  84185 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  84186     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATEr */
  84187         soc_block_list[4],
  84188         soc_genreg,
  84189         4,
  84190         0,
  84191         0xe060800,
  84192         SOC_REG_FLAG_64_BITS |
  84193                           SOC_REG_FLAG_ARRAY |
  84194                           SOC_REG_FLAG_RO,
  84195         0,
  84196         1,
  84197         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84199         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84200         -1,
  84201         -1,
  84202     },
  84203 #endif /* chips */
  84204 
  84205 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84206     defined(BCM_56970_A0)
  84207     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_BCM56960_A0r */
  84208         soc_block_list[124],
  84209         soc_pipereg,
  84210         1,
  84211         0,
  84212         0x39854000,
  84213         SOC_REG_FLAG_64_BITS |
  84214                           SOC_REG_FLAG_RO |
  84215                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84216         0,
  84217         1,
  84218         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84220         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84221         -1,
  84222         -1,
  84223         3,
  84224     },
  84225 #endif /* chips */
  84226 
  84227 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  84228     defined(BCM_56870_A0)
  84229     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_SPLIT0r */
  84230         soc_block_list[124],
  84231         soc_pipereg,
  84232         1,
  84233         0,
  84234         0x39854000,
  84235         SOC_REG_FLAG_64_BITS |
  84236                           SOC_REG_FLAG_RO |
  84237                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84238         0,
  84239         1,
  84240         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  84241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84242         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84243         -1,
  84244         -1,
  84245         3,
  84246     },
  84247 #endif /* chips */
  84248 
  84249 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  84250     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_SPLIT1r */
  84251         soc_block_list[124],
  84252         soc_pipereg,
  84253         1,
  84254         0,
  84255         0x39855000,
  84256         SOC_REG_FLAG_64_BITS |
  84257                           SOC_REG_FLAG_RO |
  84258                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84259         0,
  84260         1,
  84261         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  84262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84263         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  84264         -1,
  84265         -1,
  84266         3,
  84267     },
  84268 #endif /* chips */
  84269 
  84270 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  84271     defined(BCM_56870_A0)
  84272     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_SPLIT0_XPE0r */
  84273         soc_block_list[124],
  84274         soc_pipereg,
  84275         1,
  84276         0,
  84277         0x39854000,
  84278         SOC_REG_FLAG_64_BITS |
  84279                           SOC_REG_FLAG_RO,
  84280         0,
  84281         1,
  84282         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  84283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84284         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84285         -1,
  84286         -1,
  84287         3,
  84288     },
  84289 #endif /* chips */
  84290 
  84291 #if defined(BCM_56370_A0)
  84292     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_SPLIT1_BCM56370_A0r */
  84293         soc_block_list[124],
  84294         soc_pipereg,
  84295         1,
  84296         0,
  84297         0x39855000,
  84298         SOC_REG_FLAG_64_BITS |
  84299                           SOC_REG_FLAG_RO |
  84300                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84301         0,
  84302         1,
  84303         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  84304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84305         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  84306         -1,
  84307         -1,
  84308         3,
  84309     },
  84310 #endif /* chips */
  84311 
  84312 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  84313     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_SPLIT1_XPE0r */
  84314         soc_block_list[124],
  84315         soc_pipereg,
  84316         1,
  84317         0,
  84318         0x39855000,
  84319         SOC_REG_FLAG_64_BITS |
  84320                           SOC_REG_FLAG_RO,
  84321         0,
  84322         1,
  84323         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  84324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84325         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  84326         -1,
  84327         -1,
  84328         3,
  84329     },
  84330 #endif /* chips */
  84331 
  84332 #if defined(BCM_56370_A0)
  84333     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_SPLIT1_XPE0_BCM56370_A0r */
  84334         soc_block_list[124],
  84335         soc_pipereg,
  84336         1,
  84337         0,
  84338         0x39855000,
  84339         SOC_REG_FLAG_64_BITS |
  84340                           SOC_REG_FLAG_RO,
  84341         0,
  84342         1,
  84343         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  84344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84345         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  84346         -1,
  84347         -1,
  84348         3,
  84349     },
  84350 #endif /* chips */
  84351 
  84352 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84353     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_Xr */
  84354         soc_block_list[4],
  84355         soc_genreg,
  84356         2,
  84357         0,
  84358         0xaa054000,
  84359         SOC_REG_FLAG_64_BITS |
  84360                           SOC_REG_FLAG_ARRAY |
  84361                           SOC_REG_FLAG_RO,
  84362         0,
  84363         1,
  84364         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84366         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84367         -1,
  84368         -1,
  84369     },
  84370 #endif /* chips */
  84371 
  84372 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84373     defined(BCM_56970_A0)
  84374     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_XPE0r */
  84375         soc_block_list[124],
  84376         soc_pipereg,
  84377         1,
  84378         0,
  84379         0x39854000,
  84380         SOC_REG_FLAG_64_BITS |
  84381                           SOC_REG_FLAG_RO,
  84382         0,
  84383         1,
  84384         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84386         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84387         -1,
  84388         -1,
  84389         3,
  84390     },
  84391 #endif /* chips */
  84392 
  84393 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84394     defined(BCM_56970_A0)
  84395     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_XPE1r */
  84396         soc_block_list[124],
  84397         soc_pipereg,
  84398         1,
  84399         0,
  84400         0x39854000,
  84401         SOC_REG_FLAG_64_BITS |
  84402                           SOC_REG_FLAG_RO |
  84403                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84404         0,
  84405         1,
  84406         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84408         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84409         -1,
  84410         -1,
  84411         3,
  84412     },
  84413 #endif /* chips */
  84414 
  84415 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84416     defined(BCM_56970_A0)
  84417     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_XPE2r */
  84418         soc_block_list[124],
  84419         soc_pipereg,
  84420         1,
  84421         0,
  84422         0x39854000,
  84423         SOC_REG_FLAG_64_BITS |
  84424                           SOC_REG_FLAG_RO |
  84425                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84426         0,
  84427         1,
  84428         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84430         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84431         -1,
  84432         -1,
  84433         3,
  84434     },
  84435 #endif /* chips */
  84436 
  84437 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84438     defined(BCM_56970_A0)
  84439     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_XPE3r */
  84440         soc_block_list[124],
  84441         soc_pipereg,
  84442         1,
  84443         0,
  84444         0x39854000,
  84445         SOC_REG_FLAG_64_BITS |
  84446                           SOC_REG_FLAG_RO |
  84447                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84448         0,
  84449         1,
  84450         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84452         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84453         -1,
  84454         -1,
  84455         3,
  84456     },
  84457 #endif /* chips */
  84458 
  84459 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84460     { /* SOC_REG_INT_OP_UC_QGROUP_RED_DROP_STATE_Yr */
  84461         soc_block_list[4],
  84462         soc_genreg,
  84463         2,
  84464         0,
  84465         0xaa055000,
  84466         SOC_REG_FLAG_64_BITS |
  84467                           SOC_REG_FLAG_ARRAY |
  84468                           SOC_REG_FLAG_RO,
  84469         0,
  84470         1,
  84471         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84473         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84474         -1,
  84475         -1,
  84476     },
  84477 #endif /* chips */
  84478 
  84479 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  84480     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATEr */
  84481         soc_block_list[4],
  84482         soc_genreg,
  84483         4,
  84484         0,
  84485         0xe060400,
  84486         SOC_REG_FLAG_64_BITS |
  84487                           SOC_REG_FLAG_ARRAY |
  84488                           SOC_REG_FLAG_RO,
  84489         0,
  84490         1,
  84491         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84493         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84494         -1,
  84495         -1,
  84496     },
  84497 #endif /* chips */
  84498 
  84499 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84500     defined(BCM_56970_A0)
  84501     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_BCM56960_A0r */
  84502         soc_block_list[124],
  84503         soc_pipereg,
  84504         1,
  84505         0,
  84506         0x39852000,
  84507         SOC_REG_FLAG_64_BITS |
  84508                           SOC_REG_FLAG_RO |
  84509                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84510         0,
  84511         1,
  84512         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84514         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84515         -1,
  84516         -1,
  84517         3,
  84518     },
  84519 #endif /* chips */
  84520 
  84521 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  84522     defined(BCM_56870_A0)
  84523     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT0r */
  84524         soc_block_list[124],
  84525         soc_pipereg,
  84526         1,
  84527         0,
  84528         0x39852000,
  84529         SOC_REG_FLAG_64_BITS |
  84530                           SOC_REG_FLAG_RO |
  84531                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84532         0,
  84533         1,
  84534         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  84535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84536         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84537         -1,
  84538         -1,
  84539         3,
  84540     },
  84541 #endif /* chips */
  84542 
  84543 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  84544     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT1r */
  84545         soc_block_list[124],
  84546         soc_pipereg,
  84547         1,
  84548         0,
  84549         0x39853000,
  84550         SOC_REG_FLAG_RO |
  84551                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84552         0,
  84553         1,
  84554         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  84555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84556         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  84557         -1,
  84558         -1,
  84559         3,
  84560     },
  84561 #endif /* chips */
  84562 
  84563 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  84564     defined(BCM_56870_A0)
  84565     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT0_XPE0r */
  84566         soc_block_list[124],
  84567         soc_pipereg,
  84568         1,
  84569         0,
  84570         0x39852000,
  84571         SOC_REG_FLAG_64_BITS |
  84572                           SOC_REG_FLAG_RO,
  84573         0,
  84574         1,
  84575         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  84576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84577         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84578         -1,
  84579         -1,
  84580         3,
  84581     },
  84582 #endif /* chips */
  84583 
  84584 #if defined(BCM_56370_A0)
  84585     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT1_BCM56370_A0r */
  84586         soc_block_list[124],
  84587         soc_pipereg,
  84588         1,
  84589         0,
  84590         0x39853000,
  84591         SOC_REG_FLAG_RO |
  84592                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84593         0,
  84594         1,
  84595         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  84596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84597         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  84598         -1,
  84599         -1,
  84600         3,
  84601     },
  84602 #endif /* chips */
  84603 
  84604 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  84605     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT1_XPE0r */
  84606         soc_block_list[124],
  84607         soc_pipereg,
  84608         1,
  84609         0,
  84610         0x39853000,
  84611         SOC_REG_FLAG_RO,
  84612         0,
  84613         1,
  84614         soc_OP_UC_PORT_DROP_STATE_SPLIT1r_fields,
  84615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84616         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  84617         -1,
  84618         -1,
  84619         3,
  84620     },
  84621 #endif /* chips */
  84622 
  84623 #if defined(BCM_56370_A0)
  84624     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT1_XPE0_BCM56370_A0r */
  84625         soc_block_list[124],
  84626         soc_pipereg,
  84627         1,
  84628         0,
  84629         0x39853000,
  84630         SOC_REG_FLAG_RO,
  84631         0,
  84632         1,
  84633         soc_OP_UC_PORT_DROP_STATE_SPLIT1_BCM56370_A0r_fields,
  84634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84635         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  84636         -1,
  84637         -1,
  84638         3,
  84639     },
  84640 #endif /* chips */
  84641 
  84642 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84643     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_Xr */
  84644         soc_block_list[4],
  84645         soc_genreg,
  84646         2,
  84647         0,
  84648         0xaa052000,
  84649         SOC_REG_FLAG_64_BITS |
  84650                           SOC_REG_FLAG_ARRAY |
  84651                           SOC_REG_FLAG_RO,
  84652         0,
  84653         1,
  84654         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84656         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84657         -1,
  84658         -1,
  84659     },
  84660 #endif /* chips */
  84661 
  84662 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84663     defined(BCM_56970_A0)
  84664     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_XPE0r */
  84665         soc_block_list[124],
  84666         soc_pipereg,
  84667         1,
  84668         0,
  84669         0x39852000,
  84670         SOC_REG_FLAG_64_BITS |
  84671                           SOC_REG_FLAG_RO,
  84672         0,
  84673         1,
  84674         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84676         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84677         -1,
  84678         -1,
  84679         3,
  84680     },
  84681 #endif /* chips */
  84682 
  84683 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84684     defined(BCM_56970_A0)
  84685     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_XPE1r */
  84686         soc_block_list[124],
  84687         soc_pipereg,
  84688         1,
  84689         0,
  84690         0x39852000,
  84691         SOC_REG_FLAG_64_BITS |
  84692                           SOC_REG_FLAG_RO |
  84693                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84694         0,
  84695         1,
  84696         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84698         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84699         -1,
  84700         -1,
  84701         3,
  84702     },
  84703 #endif /* chips */
  84704 
  84705 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84706     defined(BCM_56970_A0)
  84707     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_XPE2r */
  84708         soc_block_list[124],
  84709         soc_pipereg,
  84710         1,
  84711         0,
  84712         0x39852000,
  84713         SOC_REG_FLAG_64_BITS |
  84714                           SOC_REG_FLAG_RO |
  84715                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84716         0,
  84717         1,
  84718         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84721         -1,
  84722         -1,
  84723         3,
  84724     },
  84725 #endif /* chips */
  84726 
  84727 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84728     defined(BCM_56970_A0)
  84729     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_XPE3r */
  84730         soc_block_list[124],
  84731         soc_pipereg,
  84732         1,
  84733         0,
  84734         0x39852000,
  84735         SOC_REG_FLAG_64_BITS |
  84736                           SOC_REG_FLAG_RO |
  84737                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84738         0,
  84739         1,
  84740         soc_OP_UC_PORT_DROP_STATE_BCM56960_A0r_fields,
  84741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  84743         -1,
  84744         -1,
  84745         3,
  84746     },
  84747 #endif /* chips */
  84748 
  84749 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84750     { /* SOC_REG_INT_OP_UC_QGROUP_YELLOW_DROP_STATE_Yr */
  84751         soc_block_list[4],
  84752         soc_genreg,
  84753         2,
  84754         0,
  84755         0xaa053000,
  84756         SOC_REG_FLAG_64_BITS |
  84757                           SOC_REG_FLAG_ARRAY |
  84758                           SOC_REG_FLAG_RO,
  84759         0,
  84760         1,
  84761         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84763         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84764         -1,
  84765         -1,
  84766     },
  84767 #endif /* chips */
  84768 
  84769 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  84770     { /* SOC_REG_INT_OP_UC_QUEUE_BST_THRESHOLDr */
  84771         soc_block_list[4],
  84772         soc_genreg,
  84773         8,
  84774         0,
  84775         0xe062000,
  84776         SOC_REG_FLAG_ARRAY,
  84777         0,
  84778         2,
  84779         soc_OP_UC_PORT_BST_THRESHOLDr_fields,
  84780         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  84781         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  84782         -1,
  84783         -1,
  84784     },
  84785 #endif /* chips */
  84786 
  84787 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  84788     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  84789     { /* SOC_REG_INT_OP_UC_QUEUE_BST_THRESHOLD_BCM56560_A0r */
  84790         soc_block_list[4],
  84791         soc_genreg,
  84792         8,
  84793         0,
  84794         0xaa082000,
  84795         SOC_REG_FLAG_ARRAY,
  84796         0,
  84797         1,
  84798         soc_OP_UC_PORT_BST_THRESHOLD_BCM56560_A0r_fields,
  84799         SOC_RESET_VAL_DEC(0x00001fff, 0x00000000)
  84800         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  84801         -1,
  84802         -1,
  84803     },
  84804 #endif /* chips */
  84805 
  84806 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84807     { /* SOC_REG_INT_OP_UC_QUEUE_BST_THRESHOLD_BCM56850_A0r */
  84808         soc_block_list[4],
  84809         soc_genreg,
  84810         8,
  84811         0,
  84812         0xaa082000,
  84813         SOC_REG_FLAG_ARRAY,
  84814         0,
  84815         1,
  84816         soc_OP_UC_PORT_BST_THRESHOLD_BCM56850_A0r_fields,
  84817         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
  84818         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  84819         -1,
  84820         -1,
  84821     },
  84822 #endif /* chips */
  84823 
  84824 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  84825     defined(BCM_56870_A0)
  84826     { /* SOC_REG_INT_OP_UC_QUEUE_BST_THRESHOLD_BCM56870_A0r */
  84827         soc_block_list[124],
  84828         soc_xpereg,
  84829         8,
  84830         0,
  84831         0x3a882000,
  84832         SOC_REG_FLAG_ARRAY |
  84833                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84834         0,
  84835         1,
  84836         soc_MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_BCM56960_A0r_fields,
  84837         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  84838         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  84839         -1,
  84840         -1,
  84841         3,
  84842     },
  84843 #endif /* chips */
  84844 
  84845 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  84846     { /* SOC_REG_INT_OP_UC_QUEUE_BST_THRESHOLD_BCM56960_A0r */
  84847         soc_block_list[124],
  84848         soc_xpereg,
  84849         8,
  84850         0,
  84851         0x3a882000,
  84852         SOC_REG_FLAG_ARRAY |
  84853                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84854         0,
  84855         1,
  84856         soc_OP_UC_PORT_BST_THRESHOLD_BCM56960_A0r_fields,
  84857         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  84858         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  84859         -1,
  84860         -1,
  84861         3,
  84862     },
  84863 #endif /* chips */
  84864 
  84865 #if defined(BCM_56970_A0)
  84866     { /* SOC_REG_INT_OP_UC_QUEUE_BST_THRESHOLD_BCM56970_A0r */
  84867         soc_block_list[124],
  84868         soc_xpereg,
  84869         8,
  84870         0,
  84871         0x3a882000,
  84872         SOC_REG_FLAG_ARRAY |
  84873                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84874         0,
  84875         1,
  84876         soc_OP_UC_PORT_BST_THRESHOLD_BCM56970_A0r_fields,
  84877         SOC_RESET_VAL_DEC(0x00001fff, 0x00000000)
  84878         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  84879         -1,
  84880         -1,
  84881         3,
  84882     },
  84883 #endif /* chips */
  84884 
  84885 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  84886     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATEr */
  84887         soc_block_list[4],
  84888         soc_genreg,
  84889         16,
  84890         0,
  84891         0xe054000,
  84892         SOC_REG_FLAG_64_BITS |
  84893                           SOC_REG_FLAG_ARRAY |
  84894                           SOC_REG_FLAG_RO,
  84895         0,
  84896         1,
  84897         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84899         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84900         -1,
  84901         -1,
  84902     },
  84903 #endif /* chips */
  84904 
  84905 #if defined(BCM_56370_A0)
  84906     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_BCM56370_A0r */
  84907         soc_block_list[124],
  84908         soc_pipereg,
  84909         20,
  84910         0,
  84911         0x39810000,
  84912         SOC_REG_FLAG_64_BITS |
  84913                           SOC_REG_FLAG_ARRAY |
  84914                           SOC_REG_FLAG_RO |
  84915                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84916         0,
  84917         1,
  84918         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  84919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84920         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84921         -1,
  84922         -1,
  84923         3,
  84924     },
  84925 #endif /* chips */
  84926 
  84927 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  84928     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_BCM56870_A0r */
  84929         soc_block_list[124],
  84930         soc_pipereg,
  84931         11,
  84932         0,
  84933         0x39810000,
  84934         SOC_REG_FLAG_64_BITS |
  84935                           SOC_REG_FLAG_ARRAY |
  84936                           SOC_REG_FLAG_RO |
  84937                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84938         0,
  84939         1,
  84940         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  84941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84942         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84943         -1,
  84944         -1,
  84945         3,
  84946     },
  84947 #endif /* chips */
  84948 
  84949 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84950     defined(BCM_56970_A0)
  84951     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_BCM56960_A0r */
  84952         soc_block_list[124],
  84953         soc_pipereg,
  84954         6,
  84955         0,
  84956         0x39810000,
  84957         SOC_REG_FLAG_64_BITS |
  84958                           SOC_REG_FLAG_ARRAY |
  84959                           SOC_REG_FLAG_RO |
  84960                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84961         0,
  84962         1,
  84963         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  84964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84965         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84966         -1,
  84967         -1,
  84968         3,
  84969     },
  84970 #endif /* chips */
  84971 
  84972 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84973     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_Xr */
  84974         soc_block_list[4],
  84975         soc_genreg,
  84976         24,
  84977         0,
  84978         0xaa010000,
  84979         SOC_REG_FLAG_64_BITS |
  84980                           SOC_REG_FLAG_ARRAY |
  84981                           SOC_REG_FLAG_RO,
  84982         0,
  84983         1,
  84984         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  84985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84986         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  84987         -1,
  84988         -1,
  84989     },
  84990 #endif /* chips */
  84991 
  84992 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  84993     defined(BCM_56970_A0)
  84994     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_XPE0r */
  84995         soc_block_list[124],
  84996         soc_pipereg,
  84997         6,
  84998         0,
  84999         0x39810000,
  85000         SOC_REG_FLAG_64_BITS |
  85001                           SOC_REG_FLAG_ARRAY |
  85002                           SOC_REG_FLAG_RO,
  85003         0,
  85004         1,
  85005         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85007         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85008         -1,
  85009         -1,
  85010         3,
  85011     },
  85012 #endif /* chips */
  85013 
  85014 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85015     defined(BCM_56970_A0)
  85016     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_XPE1r */
  85017         soc_block_list[124],
  85018         soc_pipereg,
  85019         6,
  85020         0,
  85021         0x39810000,
  85022         SOC_REG_FLAG_64_BITS |
  85023                           SOC_REG_FLAG_ARRAY |
  85024                           SOC_REG_FLAG_RO |
  85025                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85026         0,
  85027         1,
  85028         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85030         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85031         -1,
  85032         -1,
  85033         3,
  85034     },
  85035 #endif /* chips */
  85036 
  85037 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85038     defined(BCM_56970_A0)
  85039     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_XPE2r */
  85040         soc_block_list[124],
  85041         soc_pipereg,
  85042         6,
  85043         0,
  85044         0x39810000,
  85045         SOC_REG_FLAG_64_BITS |
  85046                           SOC_REG_FLAG_ARRAY |
  85047                           SOC_REG_FLAG_RO |
  85048                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85049         0,
  85050         1,
  85051         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85053         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85054         -1,
  85055         -1,
  85056         3,
  85057     },
  85058 #endif /* chips */
  85059 
  85060 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85061     defined(BCM_56970_A0)
  85062     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_XPE3r */
  85063         soc_block_list[124],
  85064         soc_pipereg,
  85065         6,
  85066         0,
  85067         0x39810000,
  85068         SOC_REG_FLAG_64_BITS |
  85069                           SOC_REG_FLAG_ARRAY |
  85070                           SOC_REG_FLAG_RO |
  85071                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85072         0,
  85073         1,
  85074         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85076         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85077         -1,
  85078         -1,
  85079         3,
  85080     },
  85081 #endif /* chips */
  85082 
  85083 #if defined(BCM_56370_A0)
  85084     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_XPE0_BCM56370_A0r */
  85085         soc_block_list[124],
  85086         soc_pipereg,
  85087         20,
  85088         0,
  85089         0x39810000,
  85090         SOC_REG_FLAG_64_BITS |
  85091                           SOC_REG_FLAG_ARRAY |
  85092                           SOC_REG_FLAG_RO,
  85093         0,
  85094         1,
  85095         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85097         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85098         -1,
  85099         -1,
  85100         3,
  85101     },
  85102 #endif /* chips */
  85103 
  85104 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  85105     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_XPE0_BCM56870_A0r */
  85106         soc_block_list[124],
  85107         soc_pipereg,
  85108         11,
  85109         0,
  85110         0x39810000,
  85111         SOC_REG_FLAG_64_BITS |
  85112                           SOC_REG_FLAG_ARRAY |
  85113                           SOC_REG_FLAG_RO,
  85114         0,
  85115         1,
  85116         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85118         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85119         -1,
  85120         -1,
  85121         3,
  85122     },
  85123 #endif /* chips */
  85124 
  85125 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  85126     { /* SOC_REG_INT_OP_UC_QUEUE_DROP_STATE_Yr */
  85127         soc_block_list[4],
  85128         soc_genreg,
  85129         24,
  85130         0,
  85131         0xaa018000,
  85132         SOC_REG_FLAG_64_BITS |
  85133                           SOC_REG_FLAG_ARRAY |
  85134                           SOC_REG_FLAG_RO,
  85135         0,
  85136         1,
  85137         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  85138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85139         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85140         -1,
  85141         -1,
  85142     },
  85143 #endif /* chips */
  85144 
  85145 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  85146     { /* SOC_REG_INT_OP_UC_QUEUE_MIN_COUNT_CELLr */
  85147         soc_block_list[4],
  85148         soc_portreg,
  85149         10,
  85150         0,
  85151         0x3000280,
  85152         SOC_REG_FLAG_ARRAY |
  85153                           SOC_REG_FLAG_RO,
  85154         0,
  85155         1,
  85156         soc_OP_EX_QUEUE_MIN_COUNT_CELLr_fields,
  85157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85158         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  85159         -1,
  85160         44,
  85161     },
  85162 #endif /* chips */
  85163 
  85164 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  85165     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATEr */
  85166         soc_block_list[4],
  85167         soc_genreg,
  85168         16,
  85169         0,
  85170         0xe05c000,
  85171         SOC_REG_FLAG_64_BITS |
  85172                           SOC_REG_FLAG_ARRAY |
  85173                           SOC_REG_FLAG_RO,
  85174         0,
  85175         1,
  85176         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  85177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85178         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85179         -1,
  85180         -1,
  85181     },
  85182 #endif /* chips */
  85183 
  85184 #if defined(BCM_56370_A0)
  85185     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_BCM56370_A0r */
  85186         soc_block_list[124],
  85187         soc_pipereg,
  85188         20,
  85189         0,
  85190         0x39830000,
  85191         SOC_REG_FLAG_64_BITS |
  85192                           SOC_REG_FLAG_ARRAY |
  85193                           SOC_REG_FLAG_RO |
  85194                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85195         0,
  85196         1,
  85197         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85199         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85200         -1,
  85201         -1,
  85202         3,
  85203     },
  85204 #endif /* chips */
  85205 
  85206 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  85207     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_BCM56870_A0r */
  85208         soc_block_list[124],
  85209         soc_pipereg,
  85210         11,
  85211         0,
  85212         0x39830000,
  85213         SOC_REG_FLAG_64_BITS |
  85214                           SOC_REG_FLAG_ARRAY |
  85215                           SOC_REG_FLAG_RO |
  85216                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85217         0,
  85218         1,
  85219         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85221         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85222         -1,
  85223         -1,
  85224         3,
  85225     },
  85226 #endif /* chips */
  85227 
  85228 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85229     defined(BCM_56970_A0)
  85230     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_BCM56960_A0r */
  85231         soc_block_list[124],
  85232         soc_pipereg,
  85233         6,
  85234         0,
  85235         0x39830000,
  85236         SOC_REG_FLAG_64_BITS |
  85237                           SOC_REG_FLAG_ARRAY |
  85238                           SOC_REG_FLAG_RO |
  85239                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85240         0,
  85241         1,
  85242         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85244         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85245         -1,
  85246         -1,
  85247         3,
  85248     },
  85249 #endif /* chips */
  85250 
  85251 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  85252     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_Xr */
  85253         soc_block_list[4],
  85254         soc_genreg,
  85255         24,
  85256         0,
  85257         0xaa030000,
  85258         SOC_REG_FLAG_64_BITS |
  85259                           SOC_REG_FLAG_ARRAY |
  85260                           SOC_REG_FLAG_RO,
  85261         0,
  85262         1,
  85263         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  85264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85265         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85266         -1,
  85267         -1,
  85268     },
  85269 #endif /* chips */
  85270 
  85271 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85272     defined(BCM_56970_A0)
  85273     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_XPE0r */
  85274         soc_block_list[124],
  85275         soc_pipereg,
  85276         6,
  85277         0,
  85278         0x39830000,
  85279         SOC_REG_FLAG_64_BITS |
  85280                           SOC_REG_FLAG_ARRAY |
  85281                           SOC_REG_FLAG_RO,
  85282         0,
  85283         1,
  85284         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85286         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85287         -1,
  85288         -1,
  85289         3,
  85290     },
  85291 #endif /* chips */
  85292 
  85293 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85294     defined(BCM_56970_A0)
  85295     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_XPE1r */
  85296         soc_block_list[124],
  85297         soc_pipereg,
  85298         6,
  85299         0,
  85300         0x39830000,
  85301         SOC_REG_FLAG_64_BITS |
  85302                           SOC_REG_FLAG_ARRAY |
  85303                           SOC_REG_FLAG_RO |
  85304                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85305         0,
  85306         1,
  85307         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85309         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85310         -1,
  85311         -1,
  85312         3,
  85313     },
  85314 #endif /* chips */
  85315 
  85316 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85317     defined(BCM_56970_A0)
  85318     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_XPE2r */
  85319         soc_block_list[124],
  85320         soc_pipereg,
  85321         6,
  85322         0,
  85323         0x39830000,
  85324         SOC_REG_FLAG_64_BITS |
  85325                           SOC_REG_FLAG_ARRAY |
  85326                           SOC_REG_FLAG_RO |
  85327                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85328         0,
  85329         1,
  85330         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85332         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85333         -1,
  85334         -1,
  85335         3,
  85336     },
  85337 #endif /* chips */
  85338 
  85339 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85340     defined(BCM_56970_A0)
  85341     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_XPE3r */
  85342         soc_block_list[124],
  85343         soc_pipereg,
  85344         6,
  85345         0,
  85346         0x39830000,
  85347         SOC_REG_FLAG_64_BITS |
  85348                           SOC_REG_FLAG_ARRAY |
  85349                           SOC_REG_FLAG_RO |
  85350                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85351         0,
  85352         1,
  85353         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85355         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85356         -1,
  85357         -1,
  85358         3,
  85359     },
  85360 #endif /* chips */
  85361 
  85362 #if defined(BCM_56370_A0)
  85363     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_XPE0_BCM56370_A0r */
  85364         soc_block_list[124],
  85365         soc_pipereg,
  85366         20,
  85367         0,
  85368         0x39830000,
  85369         SOC_REG_FLAG_64_BITS |
  85370                           SOC_REG_FLAG_ARRAY |
  85371                           SOC_REG_FLAG_RO,
  85372         0,
  85373         1,
  85374         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85376         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85377         -1,
  85378         -1,
  85379         3,
  85380     },
  85381 #endif /* chips */
  85382 
  85383 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  85384     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_XPE0_BCM56870_A0r */
  85385         soc_block_list[124],
  85386         soc_pipereg,
  85387         11,
  85388         0,
  85389         0x39830000,
  85390         SOC_REG_FLAG_64_BITS |
  85391                           SOC_REG_FLAG_ARRAY |
  85392                           SOC_REG_FLAG_RO,
  85393         0,
  85394         1,
  85395         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85397         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85398         -1,
  85399         -1,
  85400         3,
  85401     },
  85402 #endif /* chips */
  85403 
  85404 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  85405     { /* SOC_REG_INT_OP_UC_QUEUE_RED_DROP_STATE_Yr */
  85406         soc_block_list[4],
  85407         soc_genreg,
  85408         24,
  85409         0,
  85410         0xaa038000,
  85411         SOC_REG_FLAG_64_BITS |
  85412                           SOC_REG_FLAG_ARRAY |
  85413                           SOC_REG_FLAG_RO,
  85414         0,
  85415         1,
  85416         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  85417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85418         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85419         -1,
  85420         -1,
  85421     },
  85422 #endif /* chips */
  85423 
  85424 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  85425     { /* SOC_REG_INT_OP_UC_QUEUE_RESET_VALUE_CELLr */
  85426         soc_block_list[4],
  85427         soc_portreg,
  85428         10,
  85429         0,
  85430         0x3000400,
  85431         SOC_REG_FLAG_ARRAY |
  85432                           SOC_REG_FLAG_RO,
  85433         0,
  85434         4,
  85435         soc_OP_EX_QUEUE_RESET_VALUE_CELLr_fields,
  85436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85437         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  85438         -1,
  85439         44,
  85440     },
  85441 #endif /* chips */
  85442 
  85443 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  85444     { /* SOC_REG_INT_OP_UC_QUEUE_SHARED_COUNT_CELLr */
  85445         soc_block_list[4],
  85446         soc_portreg,
  85447         10,
  85448         0,
  85449         0x3000300,
  85450         SOC_REG_FLAG_ARRAY |
  85451                           SOC_REG_FLAG_RO,
  85452         0,
  85453         1,
  85454         soc_OP_EX_QUEUE_SHARED_COUNT_CELLr_fields,
  85455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85456         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  85457         -1,
  85458         44,
  85459     },
  85460 #endif /* chips */
  85461 
  85462 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  85463     { /* SOC_REG_INT_OP_UC_QUEUE_TOTAL_COUNT_CELLr */
  85464         soc_block_list[4],
  85465         soc_portreg,
  85466         10,
  85467         0,
  85468         0x3000380,
  85469         SOC_REG_FLAG_ARRAY |
  85470                           SOC_REG_FLAG_RO,
  85471         0,
  85472         1,
  85473         soc_OP_EX_QUEUE_TOTAL_COUNT_CELLr_fields,
  85474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85475         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  85476         -1,
  85477         44,
  85478     },
  85479 #endif /* chips */
  85480 
  85481 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  85482     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATEr */
  85483         soc_block_list[4],
  85484         soc_genreg,
  85485         16,
  85486         0,
  85487         0xe058000,
  85488         SOC_REG_FLAG_64_BITS |
  85489                           SOC_REG_FLAG_ARRAY |
  85490                           SOC_REG_FLAG_RO,
  85491         0,
  85492         1,
  85493         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  85494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85495         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85496         -1,
  85497         -1,
  85498     },
  85499 #endif /* chips */
  85500 
  85501 #if defined(BCM_56370_A0)
  85502     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_BCM56370_A0r */
  85503         soc_block_list[124],
  85504         soc_pipereg,
  85505         20,
  85506         0,
  85507         0x39820000,
  85508         SOC_REG_FLAG_64_BITS |
  85509                           SOC_REG_FLAG_ARRAY |
  85510                           SOC_REG_FLAG_RO |
  85511                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85512         0,
  85513         1,
  85514         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85516         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85517         -1,
  85518         -1,
  85519         3,
  85520     },
  85521 #endif /* chips */
  85522 
  85523 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  85524     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_BCM56870_A0r */
  85525         soc_block_list[124],
  85526         soc_pipereg,
  85527         11,
  85528         0,
  85529         0x39820000,
  85530         SOC_REG_FLAG_64_BITS |
  85531                           SOC_REG_FLAG_ARRAY |
  85532                           SOC_REG_FLAG_RO |
  85533                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85534         0,
  85535         1,
  85536         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85538         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85539         -1,
  85540         -1,
  85541         3,
  85542     },
  85543 #endif /* chips */
  85544 
  85545 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85546     defined(BCM_56970_A0)
  85547     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_BCM56960_A0r */
  85548         soc_block_list[124],
  85549         soc_pipereg,
  85550         6,
  85551         0,
  85552         0x39820000,
  85553         SOC_REG_FLAG_64_BITS |
  85554                           SOC_REG_FLAG_ARRAY |
  85555                           SOC_REG_FLAG_RO |
  85556                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85557         0,
  85558         1,
  85559         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85561         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85562         -1,
  85563         -1,
  85564         3,
  85565     },
  85566 #endif /* chips */
  85567 
  85568 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  85569     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_Xr */
  85570         soc_block_list[4],
  85571         soc_genreg,
  85572         24,
  85573         0,
  85574         0xaa020000,
  85575         SOC_REG_FLAG_64_BITS |
  85576                           SOC_REG_FLAG_ARRAY |
  85577                           SOC_REG_FLAG_RO,
  85578         0,
  85579         1,
  85580         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  85581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85582         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85583         -1,
  85584         -1,
  85585     },
  85586 #endif /* chips */
  85587 
  85588 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85589     defined(BCM_56970_A0)
  85590     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_XPE0r */
  85591         soc_block_list[124],
  85592         soc_pipereg,
  85593         6,
  85594         0,
  85595         0x39820000,
  85596         SOC_REG_FLAG_64_BITS |
  85597                           SOC_REG_FLAG_ARRAY |
  85598                           SOC_REG_FLAG_RO,
  85599         0,
  85600         1,
  85601         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85603         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85604         -1,
  85605         -1,
  85606         3,
  85607     },
  85608 #endif /* chips */
  85609 
  85610 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85611     defined(BCM_56970_A0)
  85612     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_XPE1r */
  85613         soc_block_list[124],
  85614         soc_pipereg,
  85615         6,
  85616         0,
  85617         0x39820000,
  85618         SOC_REG_FLAG_64_BITS |
  85619                           SOC_REG_FLAG_ARRAY |
  85620                           SOC_REG_FLAG_RO |
  85621                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85622         0,
  85623         1,
  85624         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85626         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85627         -1,
  85628         -1,
  85629         3,
  85630     },
  85631 #endif /* chips */
  85632 
  85633 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85634     defined(BCM_56970_A0)
  85635     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_XPE2r */
  85636         soc_block_list[124],
  85637         soc_pipereg,
  85638         6,
  85639         0,
  85640         0x39820000,
  85641         SOC_REG_FLAG_64_BITS |
  85642                           SOC_REG_FLAG_ARRAY |
  85643                           SOC_REG_FLAG_RO |
  85644                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85645         0,
  85646         1,
  85647         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85649         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85650         -1,
  85651         -1,
  85652         3,
  85653     },
  85654 #endif /* chips */
  85655 
  85656 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  85657     defined(BCM_56970_A0)
  85658     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_XPE3r */
  85659         soc_block_list[124],
  85660         soc_pipereg,
  85661         6,
  85662         0,
  85663         0x39820000,
  85664         SOC_REG_FLAG_64_BITS |
  85665                           SOC_REG_FLAG_ARRAY |
  85666                           SOC_REG_FLAG_RO |
  85667                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  85668         0,
  85669         1,
  85670         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85672         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85673         -1,
  85674         -1,
  85675         3,
  85676     },
  85677 #endif /* chips */
  85678 
  85679 #if defined(BCM_56370_A0)
  85680     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_XPE0_BCM56370_A0r */
  85681         soc_block_list[124],
  85682         soc_pipereg,
  85683         20,
  85684         0,
  85685         0x39820000,
  85686         SOC_REG_FLAG_64_BITS |
  85687                           SOC_REG_FLAG_ARRAY |
  85688                           SOC_REG_FLAG_RO,
  85689         0,
  85690         1,
  85691         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85693         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85694         -1,
  85695         -1,
  85696         3,
  85697     },
  85698 #endif /* chips */
  85699 
  85700 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  85701     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_XPE0_BCM56870_A0r */
  85702         soc_block_list[124],
  85703         soc_pipereg,
  85704         11,
  85705         0,
  85706         0x39820000,
  85707         SOC_REG_FLAG_64_BITS |
  85708                           SOC_REG_FLAG_ARRAY |
  85709                           SOC_REG_FLAG_RO,
  85710         0,
  85711         1,
  85712         soc_OP_UC_QUEUE_DROP_STATEr_fields,
  85713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85714         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85715         -1,
  85716         -1,
  85717         3,
  85718     },
  85719 #endif /* chips */
  85720 
  85721 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  85722     { /* SOC_REG_INT_OP_UC_QUEUE_YELLOW_DROP_STATE_Yr */
  85723         soc_block_list[4],
  85724         soc_genreg,
  85725         24,
  85726         0,
  85727         0xaa028000,
  85728         SOC_REG_FLAG_64_BITS |
  85729                           SOC_REG_FLAG_ARRAY |
  85730                           SOC_REG_FLAG_RO,
  85731         0,
  85732         1,
  85733         soc_OP_UC_QGROUP_DROP_STATEr_fields,
  85734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85735         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  85736         -1,
  85737         -1,
  85738     },
  85739 #endif /* chips */
  85740 
  85741 #if defined(BCM_56840_B0)
  85742     { /* SOC_REG_INT_OP_VOQ_MOP1B_CONFIGr */
  85743         soc_block_list[4],
  85744         soc_genreg,
  85745         1,
  85746         0,
  85747         0x3080015,
  85748         0,
  85749         0,
  85750         8,
  85751         soc_OP_VOQ_PORT_CONFIGr_fields,
  85752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85753         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  85754         -1,
  85755         -1,
  85756     },
  85757 #endif /* chips */
  85758 
  85759 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  85760     { /* SOC_REG_INT_OP_VOQ_PORT_CONFIGr */
  85761         soc_block_list[4],
  85762         soc_genreg,
  85763         1,
  85764         0,
  85765         0x3080014,
  85766         0,
  85767         0,
  85768         8,
  85769         soc_OP_VOQ_PORT_CONFIGr_fields,
  85770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85771         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  85772         -1,
  85773         -1,
  85774     },
  85775 #endif /* chips */
  85776 
  85777 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  85778     { /* SOC_REG_INT_OSC_ENr */
  85779         soc_block_list[1],
  85780         soc_iprocreg,
  85781         1,
  85782         0,
  85783         0x1800f390,
  85784         0,
  85785         0,
  85786         2,
  85787         soc_OSC_ENr_fields,
  85788         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  85789         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85790         -1,
  85791         -1,
  85792     },
  85793 #endif /* chips */
  85794 
  85795 #if defined(BCM_56970_A0)
  85796     { /* SOC_REG_INT_OTPC_2_CONTROLr */
  85797         soc_block_list[82],
  85798         soc_genreg,
  85799         1,
  85800         0,
  85801         0x200d200,
  85802         0,
  85803         0,
  85804         2,
  85805         soc_OTPC_2_CONTROLr_fields,
  85806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85807         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85808         -1,
  85809         -1,
  85810         3,
  85811     },
  85812 #endif /* chips */
  85813 
  85814 #if defined(BCM_56970_A0)
  85815     { /* SOC_REG_INT_OTPC_2_KEY0r */
  85816         soc_block_list[82],
  85817         soc_genreg,
  85818         1,
  85819         0,
  85820         0x200ce00,
  85821         0,
  85822         0,
  85823         1,
  85824         soc_OTPC_2_KEY0r_fields,
  85825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85826         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85827         -1,
  85828         -1,
  85829         3,
  85830     },
  85831 #endif /* chips */
  85832 
  85833 #if defined(BCM_56970_A0)
  85834     { /* SOC_REG_INT_OTPC_2_KEY1r */
  85835         soc_block_list[82],
  85836         soc_genreg,
  85837         1,
  85838         0,
  85839         0x200cf00,
  85840         0,
  85841         0,
  85842         1,
  85843         soc_OTPC_2_KEY0r_fields,
  85844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85846         -1,
  85847         -1,
  85848         3,
  85849     },
  85850 #endif /* chips */
  85851 
  85852 #if defined(BCM_56970_A0)
  85853     { /* SOC_REG_INT_OTPC_2_KEY2r */
  85854         soc_block_list[82],
  85855         soc_genreg,
  85856         1,
  85857         0,
  85858         0x200d000,
  85859         0,
  85860         0,
  85861         1,
  85862         soc_OTPC_2_KEY0r_fields,
  85863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85864         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85865         -1,
  85866         -1,
  85867         3,
  85868     },
  85869 #endif /* chips */
  85870 
  85871 #if defined(BCM_56970_A0)
  85872     { /* SOC_REG_INT_OTPC_2_KEY3r */
  85873         soc_block_list[82],
  85874         soc_genreg,
  85875         1,
  85876         0,
  85877         0x200d100,
  85878         0,
  85879         0,
  85880         1,
  85881         soc_OTPC_2_KEY0r_fields,
  85882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85883         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85884         -1,
  85885         -1,
  85886         3,
  85887     },
  85888 #endif /* chips */
  85889 
  85890 #if defined(BCM_56970_A0)
  85891     { /* SOC_REG_INT_OTPC_2_STATUSr */
  85892         soc_block_list[82],
  85893         soc_genreg,
  85894         1,
  85895         0,
  85896         0x200d300,
  85897         SOC_REG_FLAG_RO,
  85898         0,
  85899         3,
  85900         soc_OTPC_2_STATUSr_fields,
  85901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85902         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85903         -1,
  85904         -1,
  85905         3,
  85906     },
  85907 #endif /* chips */
  85908 
  85909 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  85910     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  85911     defined(BCM_56160_A0)
  85912     { /* SOC_REG_INT_OTPC_CMD_STARTr */
  85913         soc_block_list[122],
  85914         soc_genreg,
  85915         1,
  85916         0,
  85917         0x2020800,
  85918         0,
  85919         0,
  85920         2,
  85921         soc_OTPC_CMD_STARTr_fields,
  85922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85923         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  85924         -1,
  85925         -1,
  85926     },
  85927 #endif /* chips */
  85928 
  85929 #if defined(BCM_56150_A0)
  85930     { /* SOC_REG_INT_OTPC_CNTRL_0r */
  85931         soc_block_list[122],
  85932         soc_genreg,
  85933         1,
  85934         0,
  85935         0x2020800,
  85936         0,
  85937         0,
  85938         20,
  85939         soc_OTPC_CNTRL_0r_fields,
  85940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85941         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  85942         -1,
  85943         -1,
  85944     },
  85945 #endif /* chips */
  85946 
  85947 #if defined(BCM_56150_A0)
  85948     { /* SOC_REG_INT_OTPC_CNTRL_1r */
  85949         soc_block_list[122],
  85950         soc_genreg,
  85951         1,
  85952         0,
  85953         0x2020400,
  85954         0,
  85955         0,
  85956         8,
  85957         soc_OTPC_CNTRL_1r_fields,
  85958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85959         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  85960         -1,
  85961         -1,
  85962     },
  85963 #endif /* chips */
  85964 
  85965 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  85966     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  85967     defined(BCM_56160_A0)
  85968     { /* SOC_REG_INT_OTPC_COMMANDr */
  85969         soc_block_list[122],
  85970         soc_genreg,
  85971         1,
  85972         0,
  85973         0x2020400,
  85974         0,
  85975         0,
  85976         2,
  85977         soc_OTPC_COMMANDr_fields,
  85978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85979         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  85980         -1,
  85981         -1,
  85982     },
  85983 #endif /* chips */
  85984 
  85985 #if defined(BCM_56150_A0)
  85986     { /* SOC_REG_INT_OTPC_CPUADDR_REGr */
  85987         soc_block_list[122],
  85988         soc_genreg,
  85989         1,
  85990         0,
  85991         0x2022800,
  85992         0,
  85993         0,
  85994         2,
  85995         soc_OTPC_CPUADDR_REGr_fields,
  85996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85997         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  85998         -1,
  85999         -1,
  86000     },
  86001 #endif /* chips */
  86002 
  86003 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  86004     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  86005     defined(BCM_56160_A0)
  86006     { /* SOC_REG_INT_OTPC_CPUADDR_REG_BCM53400_A0r */
  86007         soc_block_list[122],
  86008         soc_genreg,
  86009         1,
  86010         0,
  86011         0x2022800,
  86012         0,
  86013         0,
  86014         2,
  86015         soc_OTPC_CPUADDR_REG_BCM53400_A0r_fields,
  86016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86017         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86018         -1,
  86019         -1,
  86020     },
  86021 #endif /* chips */
  86022 
  86023 #if defined(BCM_56150_A0)
  86024     { /* SOC_REG_INT_OTPC_CPU_DATAr */
  86025         soc_block_list[122],
  86026         soc_genreg,
  86027         1,
  86028         0,
  86029         0x2021000,
  86030         SOC_REG_FLAG_RO,
  86031         0,
  86032         1,
  86033         soc_OTPC_CPU_DATAr_fields,
  86034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86035         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86036         -1,
  86037         -1,
  86038     },
  86039 #endif /* chips */
  86040 
  86041 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  86042     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  86043     defined(BCM_56160_A0)
  86044     { /* SOC_REG_INT_OTPC_CPU_DATA_BCM53400_A0r */
  86045         soc_block_list[122],
  86046         soc_genreg,
  86047         1,
  86048         0,
  86049         0x2021000,
  86050         SOC_REG_FLAG_RO,
  86051         0,
  86052         1,
  86053         soc_OTPC_CPU_DATA_BCM53400_A0r_fields,
  86054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86055         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86056         -1,
  86057         -1,
  86058     },
  86059 #endif /* chips */
  86060 
  86061 #if defined(BCM_56150_A0)
  86062     { /* SOC_REG_INT_OTPC_CPU_STATUSr */
  86063         soc_block_list[122],
  86064         soc_genreg,
  86065         1,
  86066         0,
  86067         0x2020c00,
  86068         SOC_REG_FLAG_RO,
  86069         0,
  86070         17,
  86071         soc_OTPC_CPU_STATUSr_fields,
  86072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86073         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86074         -1,
  86075         -1,
  86076     },
  86077 #endif /* chips */
  86078 
  86079 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  86080     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  86081     defined(BCM_56160_A0)
  86082     { /* SOC_REG_INT_OTPC_CPU_STATUS_BCM53400_A0r */
  86083         soc_block_list[122],
  86084         soc_genreg,
  86085         1,
  86086         0,
  86087         0x2020c00,
  86088         SOC_REG_FLAG_RO,
  86089         0,
  86090         2,
  86091         soc_OTPC_CPU_STATUS_BCM53400_A0r_fields,
  86092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86093         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86094         -1,
  86095         -1,
  86096     },
  86097 #endif /* chips */
  86098 
  86099 #if defined(BCM_56150_A0)
  86100     { /* SOC_REG_INT_OTPC_CPU_WRITE_REGr */
  86101         soc_block_list[122],
  86102         soc_genreg,
  86103         1,
  86104         0,
  86105         0x2022c00,
  86106         0,
  86107         0,
  86108         1,
  86109         soc_OTPC_CPU_WRITE_REGr_fields,
  86110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86112         -1,
  86113         -1,
  86114     },
  86115 #endif /* chips */
  86116 
  86117 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  86118     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  86119     defined(BCM_56160_A0)
  86120     { /* SOC_REG_INT_OTPC_CPU_WRITE_REG_BCM53400_A0r */
  86121         soc_block_list[122],
  86122         soc_genreg,
  86123         1,
  86124         0,
  86125         0x2022c00,
  86126         0,
  86127         0,
  86128         1,
  86129         soc_OTPC_CPU_WRITE_REG_BCM53400_A0r_fields,
  86130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86131         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86132         -1,
  86133         -1,
  86134     },
  86135 #endif /* chips */
  86136 
  86137 #if defined(BCM_56150_A0)
  86138     { /* SOC_REG_INT_OTPC_MODE_REGr */
  86139         soc_block_list[122],
  86140         soc_genreg,
  86141         1,
  86142         0,
  86143         0x2020000,
  86144         0,
  86145         0,
  86146         3,
  86147         soc_OTPC_MODE_REGr_fields,
  86148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86150         -1,
  86151         -1,
  86152     },
  86153 #endif /* chips */
  86154 
  86155 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  86156     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  86157     defined(BCM_56160_A0)
  86158     { /* SOC_REG_INT_OTPC_MODE_REG_BCM53400_A0r */
  86159         soc_block_list[122],
  86160         soc_genreg,
  86161         1,
  86162         0,
  86163         0x2020000,
  86164         0,
  86165         0,
  86166         4,
  86167         soc_OTPC_MODE_REG_BCM53400_A0r_fields,
  86168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86169         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86170         -1,
  86171         -1,
  86172     },
  86173 #endif /* chips */
  86174 
  86175 #if defined(BCM_56150_A0)
  86176     { /* SOC_REG_INT_OTPC_SOFT_RESET_CNTRLr */
  86177         soc_block_list[122],
  86178         soc_genreg,
  86179         1,
  86180         0,
  86181         0x2022400,
  86182         0,
  86183         0,
  86184         2,
  86185         soc_OTPC_SOFT_RESET_CNTRLr_fields,
  86186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86188         -1,
  86189         -1,
  86190     },
  86191 #endif /* chips */
  86192 
  86193 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  86194     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  86195     defined(BCM_56160_A0)
  86196     { /* SOC_REG_INT_OTPC_SOFT_RESET_CNTRL_BCM53400_A0r */
  86197         soc_block_list[122],
  86198         soc_genreg,
  86199         1,
  86200         0,
  86201         0x2022400,
  86202         0,
  86203         0,
  86204         2,
  86205         soc_OTPC_SOFT_RESET_CNTRL_BCM53400_A0r_fields,
  86206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86207         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86208         -1,
  86209         -1,
  86210     },
  86211 #endif /* chips */
  86212 
  86213 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  86214     defined(BCM_56870_A0)
  86215     { /* SOC_REG_INT_OUTER_L2_FOR_IFP_AND_TRUNKr */
  86216         soc_block_list[115],
  86217         soc_genreg,
  86218         1,
  86219         0,
  86220         0x2002500,
  86221         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  86222         SOC_REG_FLAG_CCH,
  86223         1,
  86224         soc_OUTER_L2_FOR_IFP_AND_TRUNKr_fields,
  86225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86226         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86227         -1,
  86228         -1,
  86229         3,
  86230     },
  86231 #endif /* chips */
  86232 
  86233 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  86234     defined(BCM_56450_B1)
  86235     { /* SOC_REG_INT_OUTER_TPID_0r */
  86236         soc_block_list[5],
  86237         soc_genreg,
  86238         1,
  86239         0,
  86240         0x2000e00,
  86241         0,
  86242         0,
  86243         1,
  86244         soc_EGR_OUTER_TPID_0r_fields,
  86245         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  86246         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86247         -1,
  86248         -1,
  86249     },
  86250 #endif /* chips */
  86251 
  86252 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  86253     defined(BCM_56450_B1)
  86254     { /* SOC_REG_INT_OUTER_TPID_1r */
  86255         soc_block_list[5],
  86256         soc_genreg,
  86257         1,
  86258         0,
  86259         0x2000f00,
  86260         0,
  86261         0,
  86262         1,
  86263         soc_EGR_OUTER_TPID_1_BCM56640_A0r_fields,
  86264         SOC_RESET_VAL_DEC(0x00009100, 0x00000000)
  86265         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86266         -1,
  86267         -1,
  86268     },
  86269 #endif /* chips */
  86270 
  86271 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  86272     defined(BCM_56450_B1)
  86273     { /* SOC_REG_INT_OUTER_TPID_2r */
  86274         soc_block_list[5],
  86275         soc_genreg,
  86276         1,
  86277         0,
  86278         0x2001000,
  86279         0,
  86280         0,
  86281         1,
  86282         soc_EGR_OUTER_TPID_2_BCM56640_A0r_fields,
  86283         SOC_RESET_VAL_DEC(0x000088a8, 0x00000000)
  86284         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86285         -1,
  86286         -1,
  86287     },
  86288 #endif /* chips */
  86289 
  86290 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  86291     defined(BCM_56450_B1)
  86292     { /* SOC_REG_INT_OUTER_TPID_3r */
  86293         soc_block_list[5],
  86294         soc_genreg,
  86295         1,
  86296         0,
  86297         0x2001100,
  86298         0,
  86299         0,
  86300         1,
  86301         soc_EGR_LOOPBACK_PORT_TPIDr_fields,
  86302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86303         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86304         -1,
  86305         -1,
  86306     },
  86307 #endif /* chips */
  86308 
  86309 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  86310     defined(BCM_56270_A0)
  86311     { /* SOC_REG_INT_OUTER_TPID_0_BCM56260_A0r */
  86312         soc_block_list[5],
  86313         soc_genreg,
  86314         1,
  86315         0,
  86316         0x2000e00,
  86317         0,
  86318         0,
  86319         1,
  86320         soc_EGR_OUTER_TPID_0_BCM53400_A0r_fields,
  86321         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  86322         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86323         -1,
  86324         -1,
  86325     },
  86326 #endif /* chips */
  86327 
  86328 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  86329     defined(BCM_56270_A0)
  86330     { /* SOC_REG_INT_OUTER_TPID_1_BCM56260_A0r */
  86331         soc_block_list[5],
  86332         soc_genreg,
  86333         1,
  86334         0,
  86335         0x2000f00,
  86336         0,
  86337         0,
  86338         1,
  86339         soc_EGR_OUTER_TPID_1_BCM53400_A0r_fields,
  86340         SOC_RESET_VAL_DEC(0x00009100, 0x00000000)
  86341         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86342         -1,
  86343         -1,
  86344     },
  86345 #endif /* chips */
  86346 
  86347 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  86348     defined(BCM_56270_A0)
  86349     { /* SOC_REG_INT_OUTER_TPID_2_BCM56260_A0r */
  86350         soc_block_list[5],
  86351         soc_genreg,
  86352         1,
  86353         0,
  86354         0x2001000,
  86355         0,
  86356         0,
  86357         1,
  86358         soc_EGR_OUTER_TPID_2_BCM53400_A0r_fields,
  86359         SOC_RESET_VAL_DEC(0x000088a8, 0x00000000)
  86360         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86361         -1,
  86362         -1,
  86363     },
  86364 #endif /* chips */
  86365 
  86366 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  86367     defined(BCM_56270_A0)
  86368     { /* SOC_REG_INT_OUTER_TPID_3_BCM56260_A0r */
  86369         soc_block_list[5],
  86370         soc_genreg,
  86371         1,
  86372         0,
  86373         0x2001100,
  86374         0,
  86375         0,
  86376         1,
  86377         soc_EGR_OUTER_TPID_3_BCM53400_A0r_fields,
  86378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86379         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86380         -1,
  86381         -1,
  86382     },
  86383 #endif /* chips */
  86384 
  86385 #if defined(BCM_56800_A0)
  86386     { /* SOC_REG_INT_OUTPUT_PORT_RX_ENABLEr */
  86387         soc_block_list[4],
  86388         soc_genreg,
  86389         1,
  86390         0,
  86391         0x6080040,
  86392         0,
  86393         0,
  86394         1,
  86395         soc_OUTPUT_PORT_RX_ENABLEr_fields,
  86396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86397         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  86398         -1,
  86399         -1,
  86400     },
  86401 #endif /* chips */
  86402 
  86403 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86404     { /* SOC_REG_INT_OUTPUT_PORT_RX_ENABLE0_64r */
  86405         soc_block_list[4],
  86406         soc_genreg,
  86407         1,
  86408         0,
  86409         0x3080074,
  86410         SOC_REG_FLAG_64_BITS,
  86411         0,
  86412         3,
  86413         soc_OUTPUT_PORT_RX_ENABLE0_64r_fields,
  86414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  86416         -1,
  86417         -1,
  86418     },
  86419 #endif /* chips */
  86420 
  86421 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  86422     { /* SOC_REG_INT_OUTPUT_PORT_RX_ENABLE0_64_BCM56640_A0r */
  86423         soc_block_list[4],
  86424         soc_genreg,
  86425         1,
  86426         0,
  86427         0xe007400,
  86428         SOC_REG_FLAG_64_BITS,
  86429         0,
  86430         1,
  86431         soc_OUTPUT_PORT_RX_ENABLE0_64_BCM56640_A0r_fields,
  86432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86433         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  86434         -1,
  86435         -1,
  86436     },
  86437 #endif /* chips */
  86438 
  86439 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86440     { /* SOC_REG_INT_OUTPUT_PORT_RX_ENABLE1_64r */
  86441         soc_block_list[4],
  86442         soc_genreg,
  86443         1,
  86444         0,
  86445         0x3080075,
  86446         SOC_REG_FLAG_64_BITS,
  86447         0,
  86448         3,
  86449         soc_OUTPUT_PORT_RX_ENABLE1_64r_fields,
  86450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86451         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  86452         -1,
  86453         -1,
  86454     },
  86455 #endif /* chips */
  86456 
  86457 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  86458     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  86459     { /* SOC_REG_INT_OUTPUT_PORT_RX_ENABLE_64r */
  86460         soc_block_list[4],
  86461         soc_genreg,
  86462         1,
  86463         0,
  86464         0x308001b,
  86465         SOC_REG_FLAG_64_BITS,
  86466         0,
  86467         3,
  86468         soc_OUTPUT_PORT_RX_ENABLE_64r_fields,
  86469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86470         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  86471         -1,
  86472         -1,
  86473     },
  86474 #endif /* chips */
  86475 
  86476 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  86477     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  86478     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  86479     { /* SOC_REG_INT_OUTPUT_PORT_RX_ENABLE_64_BCM56634_A0r */
  86480         soc_block_list[4],
  86481         soc_genreg,
  86482         1,
  86483         0,
  86484         0x308001b,
  86485         SOC_REG_FLAG_64_BITS,
  86486         0,
  86487         3,
  86488         soc_OUTPUT_PORT_RX_ENABLE_64_BCM56634_A0r_fields,
  86489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86490         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  86491         -1,
  86492         -1,
  86493     },
  86494 #endif /* chips */
  86495 
  86496 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  86497     { /* SOC_REG_INT_OUTPUT_PORT_RX_ENABLE_BCM56334_A0r */
  86498         soc_block_list[4],
  86499         soc_genreg,
  86500         1,
  86501         0,
  86502         0x308001b,
  86503         0,
  86504         0,
  86505         1,
  86506         soc_OUTPUT_PORT_RX_ENABLE_BCM56334_A0r_fields,
  86507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86508         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  86509         -1,
  86510         -1,
  86511     },
  86512 #endif /* chips */
  86513 
  86514 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  86515     { /* SOC_REG_INT_OUTPUT_PORT_RX_ENABLE_BCM56820_A0r */
  86516         soc_block_list[4],
  86517         soc_genreg,
  86518         1,
  86519         0,
  86520         0x6080090,
  86521         0,
  86522         0,
  86523         1,
  86524         soc_OUTPUT_PORT_RX_ENABLE_BCM56820_A0r_fields,
  86525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86526         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  86527         -1,
  86528         -1,
  86529     },
  86530 #endif /* chips */
  86531 
  86532 #if defined(BCM_88732_A0)
  86533     { /* SOC_REG_INT_OUTPUT_PORT_RX_ENABLE_BCM88732_A0r */
  86534         soc_block_list[4],
  86535         soc_genreg,
  86536         1,
  86537         0,
  86538         0x6080090,
  86539         0,
  86540         0,
  86541         1,
  86542         soc_OUTPUT_PORT_RX_ENABLE_BCM88732_A0r_fields,
  86543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86544         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  86545         -1,
  86546         -1,
  86547     },
  86548 #endif /* chips */
  86549 
  86550 #if defined(BCM_88732_A0)
  86551     { /* SOC_REG_INT_OVERLAY_MODEr */
  86552         soc_block_list[5],
  86553         soc_genreg,
  86554         1,
  86555         0,
  86556         0x8080071,
  86557         0,
  86558         0,
  86559         1,
  86560         soc_OVERLAY_MODEr_fields,
  86561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86562         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  86563         -1,
  86564         -1,
  86565     },
  86566 #endif /* chips */
  86567 
  86568 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  86569     { /* SOC_REG_INT_OVF_L2_HITDA_ONLYr */
  86570         soc_block_list[5],
  86571         soc_genreg,
  86572         2,
  86573         0,
  86574         0x1e001100,
  86575         SOC_REG_FLAG_64_BITS |
  86576                           SOC_REG_FLAG_ARRAY,
  86577         0,
  86578         1,
  86579         soc_OVF_L2_HITDA_ONLYr_fields,
  86580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86581         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  86582         -1,
  86583         -1,
  86584     },
  86585 #endif /* chips */
  86586 
  86587 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  86588     { /* SOC_REG_INT_OVF_L2_HITDA_ONLY_BCM53570_A0r */
  86589         soc_block_list[5],
  86590         soc_genreg,
  86591         2,
  86592         0,
  86593         0x1e001500,
  86594         SOC_REG_FLAG_64_BITS |
  86595                           SOC_REG_FLAG_ARRAY,
  86596         0,
  86597         1,
  86598         soc_OVF_L2_HITDA_ONLYr_fields,
  86599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86600         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  86601         -1,
  86602         -1,
  86603     },
  86604 #endif /* chips */
  86605 
  86606 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  86607     { /* SOC_REG_INT_OVF_L2_HITSA_ONLYr */
  86608         soc_block_list[5],
  86609         soc_genreg,
  86610         4,
  86611         0,
  86612         0x1e000d00,
  86613         SOC_REG_FLAG_64_BITS |
  86614                           SOC_REG_FLAG_ARRAY,
  86615         0,
  86616         2,
  86617         soc_OVF_L2_HITSA_ONLYr_fields,
  86618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86619         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  86620         -1,
  86621         -1,
  86622     },
  86623 #endif /* chips */
  86624 
  86625 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  86626     { /* SOC_REG_INT_OVF_L2_HITSA_ONLY_BCM53570_A0r */
  86627         soc_block_list[5],
  86628         soc_genreg,
  86629         4,
  86630         0,
  86631         0x1e001100,
  86632         SOC_REG_FLAG_64_BITS |
  86633                           SOC_REG_FLAG_ARRAY,
  86634         0,
  86635         2,
  86636         soc_OVF_L2_HITSA_ONLYr_fields,
  86637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86638         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  86639         -1,
  86640         -1,
  86641     },
  86642 #endif /* chips */
  86643 
  86644 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86645     { /* SOC_REG_INT_OVQ_ADDRESS_RANGE_0r */
  86646         soc_block_list[4],
  86647         soc_genreg,
  86648         1,
  86649         0,
  86650         0x1f080014,
  86651         0,
  86652         0,
  86653         3,
  86654         soc_OVQ_ADDRESS_RANGE_0r_fields,
  86655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86656         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  86657         -1,
  86658         -1,
  86659     },
  86660 #endif /* chips */
  86661 
  86662 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86663     { /* SOC_REG_INT_OVQ_ADDRESS_RANGE_1r */
  86664         soc_block_list[4],
  86665         soc_genreg,
  86666         1,
  86667         0,
  86668         0x1f080018,
  86669         0,
  86670         0,
  86671         3,
  86672         soc_OVQ_ADDRESS_RANGE_1r_fields,
  86673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86674         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  86675         -1,
  86676         -1,
  86677     },
  86678 #endif /* chips */
  86679 
  86680 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86681     { /* SOC_REG_INT_OVQ_ADDRESS_RANGE_2r */
  86682         soc_block_list[4],
  86683         soc_genreg,
  86684         1,
  86685         0,
  86686         0x1f08001c,
  86687         0,
  86688         0,
  86689         3,
  86690         soc_OVQ_ADDRESS_RANGE_2r_fields,
  86691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86692         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  86693         -1,
  86694         -1,
  86695     },
  86696 #endif /* chips */
  86697 
  86698 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86699     { /* SOC_REG_INT_OVQ_ADDRESS_RANGE_3r */
  86700         soc_block_list[4],
  86701         soc_genreg,
  86702         1,
  86703         0,
  86704         0x1f080020,
  86705         0,
  86706         0,
  86707         3,
  86708         soc_OVQ_ADDRESS_RANGE_3r_fields,
  86709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86710         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  86711         -1,
  86712         -1,
  86713     },
  86714 #endif /* chips */
  86715 
  86716 #if defined(BCM_56840_B0)
  86717     { /* SOC_REG_INT_OVQ_BLOCK_COUNTERr */
  86718         soc_block_list[4],
  86719         soc_genreg,
  86720         1,
  86721         0,
  86722         0x1f08000f,
  86723         0,
  86724         0,
  86725         4,
  86726         soc_OVQ_BLOCK_COUNTERr_fields,
  86727         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  86728         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  86729         -1,
  86730         -1,
  86731     },
  86732 #endif /* chips */
  86733 
  86734 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  86735     { /* SOC_REG_INT_OVQ_BLOCK_COUNTER_BCM56640_A0r */
  86736         soc_block_list[4],
  86737         soc_genreg,
  86738         1,
  86739         0,
  86740         0x7e000f00,
  86741         SOC_REG_FLAG_RO,
  86742         0,
  86743         4,
  86744         soc_OVQ_BLOCK_COUNTER_BCM56640_A0r_fields,
  86745         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  86746         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  86747         -1,
  86748         -1,
  86749     },
  86750 #endif /* chips */
  86751 
  86752 #if defined(BCM_56840_B0)
  86753     { /* SOC_REG_INT_OVQ_BUBBLE_SIZE_REGr */
  86754         soc_block_list[4],
  86755         soc_genreg,
  86756         1,
  86757         0,
  86758         0x1f080011,
  86759         0,
  86760         0,
  86761         2,
  86762         soc_OVQ_BUBBLE_SIZE_REGr_fields,
  86763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86764         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  86765         -1,
  86766         -1,
  86767     },
  86768 #endif /* chips */
  86769 
  86770 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  86771     { /* SOC_REG_INT_OVQ_BUBBLE_SIZE_REG_BCM56640_A0r */
  86772         soc_block_list[4],
  86773         soc_genreg,
  86774         1,
  86775         0,
  86776         0x7e001100,
  86777         0,
  86778         0,
  86779         2,
  86780         soc_OVQ_BUBBLE_SIZE_REG_BCM56640_A0r_fields,
  86781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86782         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  86783         -1,
  86784         -1,
  86785     },
  86786 #endif /* chips */
  86787 
  86788 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86789     { /* SOC_REG_INT_OVQ_BUBBLE_THRESHOLDr */
  86790         soc_block_list[4],
  86791         soc_genreg,
  86792         1,
  86793         0,
  86794         0x1f080010,
  86795         0,
  86796         0,
  86797         2,
  86798         soc_OVQ_BUBBLE_THRESHOLDr_fields,
  86799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86800         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  86801         -1,
  86802         -1,
  86803     },
  86804 #endif /* chips */
  86805 
  86806 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  86807     { /* SOC_REG_INT_OVQ_BUBBLE_THRESHOLD_BCM56640_A0r */
  86808         soc_block_list[4],
  86809         soc_genreg,
  86810         1,
  86811         0,
  86812         0x7e001000,
  86813         0,
  86814         0,
  86815         2,
  86816         soc_OVQ_BUBBLE_THRESHOLD_BCM56640_A0r_fields,
  86817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86818         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  86819         -1,
  86820         -1,
  86821     },
  86822 #endif /* chips */
  86823 
  86824 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86825     { /* SOC_REG_INT_OVQ_DFTr */
  86826         soc_block_list[4],
  86827         soc_genreg,
  86828         1,
  86829         0,
  86830         0x1f080024,
  86831         0,
  86832         0,
  86833         4,
  86834         soc_OVQ_DFTr_fields,
  86835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86836         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86837         -1,
  86838         -1,
  86839     },
  86840 #endif /* chips */
  86841 
  86842 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  86843     { /* SOC_REG_INT_OVQ_DFT_BCM56640_A0r */
  86844         soc_block_list[4],
  86845         soc_genreg,
  86846         1,
  86847         0,
  86848         0x7e002000,
  86849         0,
  86850         0,
  86851         4,
  86852         soc_OVQ_DFT_BCM56640_A0r_fields,
  86853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86855         -1,
  86856         -1,
  86857     },
  86858 #endif /* chips */
  86859 
  86860 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86861     { /* SOC_REG_INT_OVQ_DISTRIBUTOR_DFTr */
  86862         soc_block_list[4],
  86863         soc_genreg,
  86864         1,
  86865         0,
  86866         0x1f080025,
  86867         0,
  86868         0,
  86869         3,
  86870         soc_OVQ_DISTRIBUTOR_DFTr_fields,
  86871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86873         -1,
  86874         -1,
  86875     },
  86876 #endif /* chips */
  86877 
  86878 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  86879     { /* SOC_REG_INT_OVQ_DISTRIBUTOR_DFT_BCM56640_A0r */
  86880         soc_block_list[4],
  86881         soc_genreg,
  86882         1,
  86883         0,
  86884         0x7e002400,
  86885         0,
  86886         0,
  86887         3,
  86888         soc_OVQ_DISTRIBUTOR_DFT_BCM56640_A0r_fields,
  86889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86890         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86891         -1,
  86892         -1,
  86893     },
  86894 #endif /* chips */
  86895 
  86896 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86897     { /* SOC_REG_INT_OVQ_DROP_THRESHOLD0r */
  86898         soc_block_list[4],
  86899         soc_genreg,
  86900         1,
  86901         0,
  86902         0x1f080004,
  86903         0,
  86904         0,
  86905         1,
  86906         soc_OVQ_DROP_THRESHOLD0r_fields,
  86907         SOC_RESET_VAL_DEC(0x00002ff0, 0x00000000)
  86908         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  86909         -1,
  86910         -1,
  86911     },
  86912 #endif /* chips */
  86913 
  86914 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  86915     { /* SOC_REG_INT_OVQ_DROP_THRESHOLD0_BCM56640_A0r */
  86916         soc_block_list[4],
  86917         soc_genreg,
  86918         1,
  86919         0,
  86920         0x7e000400,
  86921         0,
  86922         0,
  86923         1,
  86924         soc_OVQ_DROP_THRESHOLD0_BCM56640_A0r_fields,
  86925         SOC_RESET_VAL_DEC(0x00001800, 0x00000000)
  86926         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  86927         -1,
  86928         -1,
  86929     },
  86930 #endif /* chips */
  86931 
  86932 #if defined(BCM_56840_B0)
  86933     { /* SOC_REG_INT_OVQ_DROP_THRESHOLD_REGr */
  86934         soc_block_list[4],
  86935         soc_genreg,
  86936         1,
  86937         0,
  86938         0x1f080009,
  86939         0,
  86940         0,
  86941         2,
  86942         soc_OVQ_DROP_THRESHOLD_REGr_fields,
  86943         SOC_RESET_VAL_DEC(0x00003f7f, 0x00000000)
  86944         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86945         -1,
  86946         -1,
  86947     },
  86948 #endif /* chips */
  86949 
  86950 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  86951     { /* SOC_REG_INT_OVQ_DROP_THRESHOLD_REG_BCM56640_A0r */
  86952         soc_block_list[4],
  86953         soc_genreg,
  86954         1,
  86955         0,
  86956         0x7e000900,
  86957         SOC_REG_FLAG_RO,
  86958         0,
  86959         2,
  86960         soc_OVQ_DROP_THRESHOLD_REG_BCM56640_A0r_fields,
  86961         SOC_RESET_VAL_DEC(0x00003f7f, 0x00000000)
  86962         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  86963         -1,
  86964         -1,
  86965     },
  86966 #endif /* chips */
  86967 
  86968 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  86969     { /* SOC_REG_INT_OVQ_DROP_THRESHOLD_RESET_LIMITr */
  86970         soc_block_list[4],
  86971         soc_genreg,
  86972         1,
  86973         0,
  86974         0x1f08000c,
  86975         0,
  86976         0,
  86977         1,
  86978         soc_OVQ_DROP_THRESHOLD_RESET_LIMITr_fields,
  86979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86980         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  86981         -1,
  86982         -1,
  86983     },
  86984 #endif /* chips */
  86985 
  86986 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  86987     { /* SOC_REG_INT_OVQ_DROP_THRESHOLD_RESET_LIMIT_BCM56640_A0r */
  86988         soc_block_list[4],
  86989         soc_genreg,
  86990         1,
  86991         0,
  86992         0x7e000c00,
  86993         0,
  86994         0,
  86995         1,
  86996         soc_OVQ_DROP_THRESHOLD_RESET_LIMIT_BCM56640_A0r_fields,
  86997         SOC_RESET_VAL_DEC(0x00001600, 0x00000000)
  86998         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  86999         -1,
  87000         -1,
  87001     },
  87002 #endif /* chips */
  87003 
  87004 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  87005     { /* SOC_REG_INT_OVQ_ECC_BITMAPr */
  87006         soc_block_list[4],
  87007         soc_genreg,
  87008         1,
  87009         0,
  87010         0x1f080038,
  87011         SOC_REG_FLAG_64_BITS,
  87012         0,
  87013         11,
  87014         soc_OVQ_ECC_BITMAPr_fields,
  87015         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  87016         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  87017         -1,
  87018         -1,
  87019     },
  87020 #endif /* chips */
  87021 
  87022 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87023     { /* SOC_REG_INT_OVQ_ECC_BITMAP_BCM56640_A0r */
  87024         soc_block_list[4],
  87025         soc_genreg,
  87026         1,
  87027         0,
  87028         0x7e015000,
  87029         SOC_REG_FLAG_64_BITS |
  87030                           SOC_REG_FLAG_RO,
  87031         0,
  87032         11,
  87033         soc_OVQ_ECC_BITMAP_BCM56640_A0r_fields,
  87034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87035         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  87036         -1,
  87037         -1,
  87038     },
  87039 #endif /* chips */
  87040 
  87041 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  87042     { /* SOC_REG_INT_OVQ_FLOWCONTROL_COUNTERr */
  87043         soc_block_list[4],
  87044         soc_genreg,
  87045         1,
  87046         0,
  87047         0x1f08000e,
  87048         0,
  87049         0,
  87050         1,
  87051         soc_OVQ_FLOWCONTROL_COUNTERr_fields,
  87052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87053         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  87054         -1,
  87055         -1,
  87056     },
  87057 #endif /* chips */
  87058 
  87059 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87060     { /* SOC_REG_INT_OVQ_FLOWCONTROL_COUNTER_BCM56640_A0r */
  87061         soc_block_list[4],
  87062         soc_genreg,
  87063         1,
  87064         0,
  87065         0x7e010000,
  87066         0,
  87067         0,
  87068         1,
  87069         soc_OVQ_FLOWCONTROL_COUNTER_BCM56640_A0r_fields,
  87070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87071         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  87072         -1,
  87073         -1,
  87074     },
  87075 #endif /* chips */
  87076 
  87077 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  87078     { /* SOC_REG_INT_OVQ_FLOWCONTROL_THRESHOLDr */
  87079         soc_block_list[4],
  87080         soc_genreg,
  87081         1,
  87082         0,
  87083         0x1f080008,
  87084         0,
  87085         0,
  87086         3,
  87087         soc_OVQ_FLOWCONTROL_THRESHOLDr_fields,
  87088         SOC_RESET_VAL_DEC(0x0bffefff, 0x00000000)
  87089         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  87090         -1,
  87091         -1,
  87092     },
  87093 #endif /* chips */
  87094 
  87095 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87096     { /* SOC_REG_INT_OVQ_FLOWCONTROL_THRESHOLD_BCM56640_A0r */
  87097         soc_block_list[4],
  87098         soc_genreg,
  87099         1,
  87100         0,
  87101         0x7e000800,
  87102         0,
  87103         0,
  87104         3,
  87105         soc_OVQ_FLOWCONTROL_THRESHOLD_BCM56640_A0r_fields,
  87106         SOC_RESET_VAL_DEC(0x03fff000, 0x00000000)
  87107         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  87108         -1,
  87109         -1,
  87110     },
  87111 #endif /* chips */
  87112 
  87113 #if defined(BCM_56840_B0)
  87114     { /* SOC_REG_INT_OVQ_LINKED_LIST_REGr */
  87115         soc_block_list[4],
  87116         soc_genreg,
  87117         1,
  87118         0,
  87119         0x1f080031,
  87120         SOC_REG_FLAG_RO,
  87121         0,
  87122         4,
  87123         soc_OVQ_LINKED_LIST_REGr_fields,
  87124         SOC_RESET_VAL_DEC(0x00fff02f, 0x00000000)
  87125         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  87126         -1,
  87127         -1,
  87128     },
  87129 #endif /* chips */
  87130 
  87131 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87132     { /* SOC_REG_INT_OVQ_LINKED_LIST_REG_BCM56640_A0r */
  87133         soc_block_list[4],
  87134         soc_genreg,
  87135         1,
  87136         0,
  87137         0x7e012000,
  87138         SOC_REG_FLAG_RO,
  87139         0,
  87140         4,
  87141         soc_OVQ_LINKED_LIST_REG_BCM56640_A0r_fields,
  87142         SOC_RESET_VAL_DEC(0x00fff031, 0x00000000)
  87143         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  87144         -1,
  87145         -1,
  87146     },
  87147 #endif /* chips */
  87148 
  87149 #if defined(BCM_56840_B0)
  87150     { /* SOC_REG_INT_OVQ_LINKED_LIST_SELECTr */
  87151         soc_block_list[4],
  87152         soc_genreg,
  87153         1,
  87154         0,
  87155         0x1f080002,
  87156         0,
  87157         0,
  87158         1,
  87159         soc_OVQ_LINKED_LIST_SELECTr_fields,
  87160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87161         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  87162         -1,
  87163         -1,
  87164     },
  87165 #endif /* chips */
  87166 
  87167 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87168     { /* SOC_REG_INT_OVQ_LINKED_LIST_SELECT_BCM56640_A0r */
  87169         soc_block_list[4],
  87170         soc_genreg,
  87171         1,
  87172         0,
  87173         0x7e000200,
  87174         0,
  87175         0,
  87176         1,
  87177         soc_OVQ_LINKED_LIST_SELECT_BCM56640_A0r_fields,
  87178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87179         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  87180         -1,
  87181         -1,
  87182     },
  87183 #endif /* chips */
  87184 
  87185 #if defined(BCM_56840_B0)
  87186     { /* SOC_REG_INT_OVQ_LINKED_NEXTPTRr */
  87187         soc_block_list[4],
  87188         soc_genreg,
  87189         1,
  87190         0,
  87191         0x1f08000d,
  87192         SOC_REG_FLAG_RO,
  87193         0,
  87194         1,
  87195         soc_OVQ_LINKED_NEXTPTRr_fields,
  87196         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  87197         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  87198         -1,
  87199         -1,
  87200     },
  87201 #endif /* chips */
  87202 
  87203 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87204     { /* SOC_REG_INT_OVQ_LINKED_NEXTPTR_BCM56640_A0r */
  87205         soc_block_list[4],
  87206         soc_genreg,
  87207         1,
  87208         0,
  87209         0x7e000d00,
  87210         SOC_REG_FLAG_RO,
  87211         0,
  87212         1,
  87213         soc_OVQ_LINKED_NEXTPTR_BCM56640_A0r_fields,
  87214         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  87215         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  87216         -1,
  87217         -1,
  87218     },
  87219 #endif /* chips */
  87220 
  87221 #if defined(BCM_56840_B0)
  87222     { /* SOC_REG_INT_OVQ_LINKED_REGr */
  87223         soc_block_list[4],
  87224         soc_genreg,
  87225         1,
  87226         0,
  87227         0x1f080006,
  87228         SOC_REG_FLAG_RO,
  87229         0,
  87230         1,
  87231         soc_OVQ_LINKED_REGr_fields,
  87232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87233         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  87234         -1,
  87235         -1,
  87236     },
  87237 #endif /* chips */
  87238 
  87239 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87240     { /* SOC_REG_INT_OVQ_LINKED_REG_BCM56640_A0r */
  87241         soc_block_list[4],
  87242         soc_genreg,
  87243         1,
  87244         0,
  87245         0x7e000600,
  87246         SOC_REG_FLAG_RO,
  87247         0,
  87248         1,
  87249         soc_OVQ_LINKED_REG_BCM56640_A0r_fields,
  87250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87251         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  87252         -1,
  87253         -1,
  87254     },
  87255 #endif /* chips */
  87256 
  87257 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  87258     { /* SOC_REG_INT_OVQ_MCQ_CREDITSr */
  87259         soc_block_list[4],
  87260         soc_portreg,
  87261         5,
  87262         0,
  87263         0x1f000040,
  87264         SOC_REG_FLAG_ARRAY,
  87265         0,
  87266         1,
  87267         soc_OVQ_MCQ_CREDITSr_fields,
  87268         SOC_RESET_VAL_DEC(0x00000060, 0x00000000)
  87269         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  87270         -1,
  87271         48,
  87272     },
  87273 #endif /* chips */
  87274 
  87275 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87276     { /* SOC_REG_INT_OVQ_MCQ_CREDITS_BCM56640_A0r */
  87277         soc_block_list[4],
  87278         soc_portreg,
  87279         48,
  87280         0,
  87281         0x7c100000,
  87282         SOC_REG_FLAG_ARRAY,
  87283         0,
  87284         1,
  87285         soc_OVQ_MCQ_CREDITS_BCM56640_A0r_fields,
  87286         SOC_RESET_VAL_DEC(0x00000060, 0x00000000)
  87287         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  87288         -1,
  87289         64,
  87290     },
  87291 #endif /* chips */
  87292 
  87293 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  87294     { /* SOC_REG_INT_OVQ_MCQ_STATEr */
  87295         soc_block_list[4],
  87296         soc_portreg,
  87297         5,
  87298         0,
  87299         0x1f000050,
  87300         SOC_REG_FLAG_ARRAY |
  87301                           SOC_REG_FLAG_RO,
  87302         0,
  87303         1,
  87304         soc_OVQ_MCQ_STATEr_fields,
  87305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87306         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  87307         -1,
  87308         48,
  87309     },
  87310 #endif /* chips */
  87311 
  87312 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87313     { /* SOC_REG_INT_OVQ_MCQ_STATE_BCM56640_A0r */
  87314         soc_block_list[4],
  87315         soc_portreg,
  87316         48,
  87317         0,
  87318         0x7c110000,
  87319         SOC_REG_FLAG_ARRAY |
  87320                           SOC_REG_FLAG_RO,
  87321         0,
  87322         1,
  87323         soc_OVQ_MCQ_STATE_BCM56640_A0r_fields,
  87324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87325         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  87326         -1,
  87327         64,
  87328     },
  87329 #endif /* chips */
  87330 
  87331 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  87332     { /* SOC_REG_INT_OVQ_SCANNER_MAX_POINTERr */
  87333         soc_block_list[4],
  87334         soc_genreg,
  87335         1,
  87336         0,
  87337         0x1f080030,
  87338         0,
  87339         0,
  87340         2,
  87341         soc_OVQ_SCANNER_MAX_POINTERr_fields,
  87342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87343         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  87344         -1,
  87345         -1,
  87346     },
  87347 #endif /* chips */
  87348 
  87349 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87350     { /* SOC_REG_INT_OVQ_SCANNER_MAX_POINTER_BCM56640_A0r */
  87351         soc_block_list[4],
  87352         soc_genreg,
  87353         1,
  87354         0,
  87355         0x7e011000,
  87356         0,
  87357         0,
  87358         2,
  87359         soc_OVQ_SCANNER_MAX_POINTER_BCM56640_A0r_fields,
  87360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87361         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  87362         -1,
  87363         -1,
  87364     },
  87365 #endif /* chips */
  87366 
  87367 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  87368     { /* SOC_REG_INT_OVQ_SCANNER_POINTERr */
  87369         soc_block_list[4],
  87370         soc_genreg,
  87371         1,
  87372         0,
  87373         0x1f080029,
  87374         SOC_REG_FLAG_RO,
  87375         0,
  87376         2,
  87377         soc_OVQ_SCANNER_POINTERr_fields,
  87378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87379         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  87380         -1,
  87381         -1,
  87382     },
  87383 #endif /* chips */
  87384 
  87385 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  87386     { /* SOC_REG_INT_OVQ_SCANNER_POINTER_BCM56640_A0r */
  87387         soc_block_list[4],
  87388         soc_genreg,
  87389         1,
  87390         0,
  87391         0x7e006000,
  87392         SOC_REG_FLAG_RO,
  87393         0,
  87394         2,
  87395         soc_OVQ_SCANNER_POINTER_BCM56640_A0r_fields,
  87396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  87397         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  87398         -1,
  87399         -1,
  87400     },
  87401 #endif /* chips */
  87402 
  87403 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  87404     { /* SOC_REG_INT_OVR_SUB_GRP0_TBLr */
  87405         soc_block_list[125],
  87406         soc_pipereg,
  87407         12,
  87408         0,
  87409         0x39841400,
  87410         SOC_REG_FLAG_ARRAY |
  87411                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  87412         0,
  87413         2,
  87414         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  87415         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  87416         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  87417         -1,
  87418         -1,
  87419         3,
  87420     },
  87421 #endif /* chips */
  87422 
  87423 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  87424     { /* SOC_REG_INT_OVR_SUB_GRP1_TBLr */
  87425         soc_block_list[125],
  87426         soc_pipereg,
  87427         12,
  87428         0,
  87429         0x39842000,
  87430         SOC_REG_FLAG_ARRAY |
  87431                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  87432         0,
  87433         2,
  87434         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  87435         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  87436         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  87437         -1,
  87438         -1,
  87439         3,
  87440     },
  87441 #endif /* chips */
  87442 
  87443 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  87444     { /* SOC_REG_INT_OVR_SUB_GRP2_TBLr */
  87445         soc_block_list[125],
  87446         soc_pipereg,
  87447         12,
  87448         0,
  87449         0x39842c00,
  87450         SOC_REG_FLAG_ARRAY |
  87451                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  87452         0,
  87453         2,
  87454         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  87455         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  87456         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  87457         -1,
  87458         -1,
  87459         3,
  87460     },
  87461 #endif /* chips */
  87462 
  87463 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  87464     { /* SOC_REG_INT_OVR_SUB_GRP3_TBLr */
  87465         soc_block_list[125],
  87466         soc_pipereg,
  87467         12,
  87468         0,
  87469         0x39843800,
  87470         SOC_REG_FLAG_ARRAY |
  87471                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  87472         0,
  87473         2,
  87474         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  87475         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  87476         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  87477         -1,
  87478         -1,
  87479         3,
  87480     },
  87481 #endif /* chips */
  87482 
  87483 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  87484     { /* SOC_REG_INT_OVR_SUB_GRP4_TBLr */
  87485         soc_block_list[125],
  87486         soc_pipereg,
  87487         12,
  87488         0,
  87489         0x39844400,
  87490         SOC_REG_FLAG_ARRAY |
  87491                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  87492         0,
  87493         2,
  87494         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  87495         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  87496         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  87497         -1,
  87498         -1,
  87499         3,
  87500     },
  87501 #endif /* chips */
  87502 
  87503 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  87504     { /* SOC_REG_INT_OVR_SUB_GRP5_TBLr */
  87505         soc_block_list[125],
  87506         soc_pipereg,
  87507         12,
  87508         0,
  87509         0x39845000,
  87510         SOC_REG_FLAG_ARRAY |
  87511                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  87512         0,
  87513         2,
  87514         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  87515         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  87516         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  87517         -1,
  87518         -1,
  87519         3,
  87520     },
  87521 #endif /* chips */
  87522 
  87523 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  87524     { /* SOC_REG_INT_OVR_SUB_GRP6_TBLr */
  87525         soc_block_list[125],
  87526         soc_pipereg,
  87527         12,
  87528         0,
  87529         0x39845c00,
  87530         SOC_REG_FLAG_ARRAY |
  87531                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  87532         0,
  87533         2,
  87534         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  87535         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  87536         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  87537         -1,
  87538         -1,
  87539         3,
  87540     },
  87541 #endif /* chips */
  87542 
  87543 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  87544     { /* SOC_REG_INT_OVR_SUB_GRP7_TBLr */
  87545         soc_block_list[125],
  87546         soc_pipereg,
  87547         12,
  87548         0,
  87549         0x39846800,
  87550         SOC_REG_FLAG_ARRAY |
  87551                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  87552         0,
  87553         2,
  87554         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  87555         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  87556         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  87557         -1,
  87558         -1,
  87559         3,
  87560     },
  87561 #endif /* chips */
  87562 
  87563 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  87564     { /* SOC_REG_INT_OVR_SUB_GRP_CFGr */
  87565         soc_block_list[125],
  87566         soc_pipereg,
  87567         8,
  87568         0,
  87569         0x39840800,
  87570         SOC_REG_FLAG_ARRAY |
  87571                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  87572         0,
  87573         3,
  87574         soc_IS_OVR_SUB_GRP_CFGr_fields,
  87575         SOC_RESET_VAL_DEC(0x00000048, 0x00000000)
  87576         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  87577         -1,
  87578         -1,
  87579         3,
  87580     },
  87581 #endif /* chips */
  87582