allregs_l.i - openbcm - Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM

allregs_l.i (1708765B)
      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_l.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_56640_A0)
     16     { /* SOC_REG_INT_L0_COSWEIGHTSr */
     17         soc_block_list[4],
     18         soc_portreg,
     19         10,
     20         0,
     21         0x18000300,
     22         SOC_REG_FLAG_ARRAY,
     23         0,
     24         1,
     25         soc_HES_Q_COSWEIGHTSr_fields,
     26         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
     27         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
     28         -1,
     29         60,
     30     },
     31 #endif /* chips */
     32 
     33 #if defined(BCM_56640_A0)
     34     { /* SOC_REG_INT_L0_WERRCOUNTr */
     35         soc_block_list[4],
     36         soc_portreg,
     37         10,
     38         0,
     39         0x18001700,
     40         SOC_REG_FLAG_ARRAY,
     41         0,
     42         2,
     43         soc_HES_Q_WERRCOUNTr_fields,
     44         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     45         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
     46         -1,
     47         60,
     48     },
     49 #endif /* chips */
     50 
     51 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
     52     { /* SOC_REG_INT_L2GRE_CONTROLr */
     53         soc_block_list[5],
     54         soc_genreg,
     55         1,
     56         0,
     57         0xa004100,
     58         0,
     59         0,
     60         2,
     61         soc_EGR_L2GRE_CONTROLr_fields,
     62         SOC_RESET_VAL_DEC(0x00026558, 0x00000000)
     63         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
     64         -1,
     65         -1,
     66     },
     67 #endif /* chips */
     68 
     69 #if defined(BCM_56370_A0)
     70     { /* SOC_REG_INT_L2GRE_CONTROL_BCM56370_A0r */
     71         soc_block_list[5],
     72         soc_genreg,
     73         1,
     74         0,
     75         0x56002400,
     76         0,
     77         SOC_REG_FLAG_CCH,
     78         2,
     79         soc_L2GRE_CONTROLr_fields,
     80         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
     81         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
     82         -1,
     83         -1,
     84         0,
     85     },
     86 #endif /* chips */
     87 
     88 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
     89     defined(BCM_56670_A0) || defined(BCM_56670_B0)
     90     { /* SOC_REG_INT_L2GRE_CONTROL_BCM56560_A0r */
     91         soc_block_list[5],
     92         soc_genreg,
     93         1,
     94         0,
     95         0xa009000,
     96         0,
     97         0,
     98         2,
     99         soc_EGR_L2GRE_CONTROL_BCM56960_A0r_fields,
    100         SOC_RESET_VAL_DEC(0x00026558, 0x00000000)
    101         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    102         -1,
    103         -1,
    104     },
    105 #endif /* chips */
    106 
    107 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
    108     { /* SOC_REG_INT_L2GRE_CONTROL_BCM56850_A0r */
    109         soc_block_list[5],
    110         soc_genreg,
    111         1,
    112         0,
    113         0xa009000,
    114         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    115         0,
    116         2,
    117         soc_EGR_L2GRE_CONTROLr_fields,
    118         SOC_RESET_VAL_DEC(0x00026558, 0x00000000)
    119         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    120         -1,
    121         -1,
    122     },
    123 #endif /* chips */
    124 
    125 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
    126     { /* SOC_REG_INT_L2GRE_CONTROL_BCM56870_A0r */
    127         soc_block_list[5],
    128         soc_genreg,
    129         1,
    130         0,
    131         0x56002400,
    132         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    133         SOC_REG_FLAG_CCH,
    134         2,
    135         soc_L2GRE_CONTROLr_fields,
    136         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
    137         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    138         -1,
    139         -1,
    140         0,
    141     },
    142 #endif /* chips */
    143 
    144 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
    145     { /* SOC_REG_INT_L2GRE_CONTROL_BCM56960_A0r */
    146         soc_block_list[5],
    147         soc_genreg,
    148         1,
    149         0,
    150         0x2e001b00,
    151         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    152         0,
    153         2,
    154         soc_EGR_L2GRE_CONTROL_BCM56960_A0r_fields,
    155         SOC_RESET_VAL_DEC(0x00026558, 0x00000000)
    156         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    157         -1,
    158         -1,
    159         0,
    160     },
    161 #endif /* chips */
    162 
    163 #if defined(BCM_56970_A0)
    164     { /* SOC_REG_INT_L2GRE_CONTROL_BCM56970_A0r */
    165         soc_block_list[5],
    166         soc_genreg,
    167         1,
    168         0,
    169         0x52001b00,
    170         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    171         0,
    172         2,
    173         soc_EGR_L2GRE_CONTROL_BCM56960_A0r_fields,
    174         SOC_RESET_VAL_DEC(0x00026558, 0x00000000)
    175         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    176         -1,
    177         -1,
    178         0,
    179     },
    180 #endif /* chips */
    181 
    182 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
    183     { /* SOC_REG_INT_L2GRE_CONTROL_BCM56980_A0r */
    184         soc_block_list[5],
    185         soc_genreg,
    186         1,
    187         0,
    188         0x6001b00,
    189         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    190         0,
    191         2,
    192         soc_EGR_L2GRE_CONTROL_BCM56960_A0r_fields,
    193         SOC_RESET_VAL_DEC(0x00026558, 0x00000000)
    194         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    195         -1,
    196         -1,
    197         3,
    198     },
    199 #endif /* chips */
    200 
    201 #if defined(BCM_56850_A0)
    202     { /* SOC_REG_INT_L2GRE_DEFAULT_NETWORK_SVPr */
    203         soc_block_list[5],
    204         soc_genreg,
    205         1,
    206         0,
    207         0x52000100,
    208         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    209         0,
    210         1,
    211         soc_MIM_DEFAULT_NETWORK_SVP_BCM56640_A0r_fields,
    212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    213         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    214         -1,
    215         -1,
    216     },
    217 #endif /* chips */
    218 
    219 #if defined(BCM_56370_A0)
    220     { /* SOC_REG_INT_L2GRE_DEFAULT_NETWORK_SVP_BCM56370_A0r */
    221         soc_block_list[115],
    222         soc_genreg,
    223         1,
    224         0,
    225         0x2003300,
    226         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    227         SOC_REG_FLAG_CCH,
    228         1,
    229         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
    230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    231         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    232         -1,
    233         -1,
    234         3,
    235     },
    236 #endif /* chips */
    237 
    238 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
    239     defined(BCM_56670_A0) || defined(BCM_56670_B0)
    240     { /* SOC_REG_INT_L2GRE_DEFAULT_NETWORK_SVP_BCM56560_A0r */
    241         soc_block_list[5],
    242         soc_genreg,
    243         1,
    244         0,
    245         0x62000100,
    246         0,
    247         0,
    248         1,
    249         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
    250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    251         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    252         -1,
    253         -1,
    254     },
    255 #endif /* chips */
    256 
    257 #if defined(BCM_56860_A0)
    258     { /* SOC_REG_INT_L2GRE_DEFAULT_NETWORK_SVP_BCM56860_A0r */
    259         soc_block_list[5],
    260         soc_genreg,
    261         1,
    262         0,
    263         0x62000100,
    264         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    265         0,
    266         1,
    267         soc_MIM_DEFAULT_NETWORK_SVP_BCM56640_A0r_fields,
    268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    269         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    270         -1,
    271         -1,
    272     },
    273 #endif /* chips */
    274 
    275 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    276     defined(BCM_56870_A0)
    277     { /* SOC_REG_INT_L2GRE_DEFAULT_NETWORK_SVP_BCM56870_A0r */
    278         soc_block_list[115],
    279         soc_genreg,
    280         1,
    281         0,
    282         0x2003400,
    283         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    284         SOC_REG_FLAG_CCH,
    285         1,
    286         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
    287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    288         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    289         -1,
    290         -1,
    291         3,
    292     },
    293 #endif /* chips */
    294 
    295 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
    296     { /* SOC_REG_INT_L2GRE_DEFAULT_NETWORK_SVP_BCM56960_A0r */
    297         soc_block_list[5],
    298         soc_genreg,
    299         1,
    300         0,
    301         0x36000100,
    302         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    303         0,
    304         1,
    305         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
    306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    307         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    308         -1,
    309         -1,
    310         0,
    311     },
    312 #endif /* chips */
    313 
    314 #if defined(BCM_56970_A0)
    315     { /* SOC_REG_INT_L2GRE_DEFAULT_NETWORK_SVP_BCM56970_A0r */
    316         soc_block_list[5],
    317         soc_genreg,
    318         1,
    319         0,
    320         0x5a000100,
    321         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    322         0,
    323         1,
    324         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
    325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    326         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    327         -1,
    328         -1,
    329         0,
    330     },
    331 #endif /* chips */
    332 
    333 #if defined(BCM_56640_A0)
    334     { /* SOC_REG_INT_L2GRE_DEFAULT_SVPr */
    335         soc_block_list[5],
    336         soc_genreg,
    337         1,
    338         0,
    339         0x12000700,
    340         0,
    341         0,
    342         1,
    343         soc_L2GRE_DEFAULT_SVPr_fields,
    344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    345         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    346         -1,
    347         -1,
    348     },
    349 #endif /* chips */
    350 
    351 #if defined(BCM_56340_A0)
    352     { /* SOC_REG_INT_L2GRE_DEFAULT_SVP_BCM56340_A0r */
    353         soc_block_list[5],
    354         soc_genreg,
    355         1,
    356         0,
    357         0x12000700,
    358         0,
    359         0,
    360         1,
    361         soc_L2GRE_DEFAULT_SVP_BCM56340_A0r_fields,
    362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    363         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
    364         -1,
    365         -1,
    366     },
    367 #endif /* chips */
    368 
    369 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
    370     { /* SOC_REG_INT_L2L3_PASSTHRU_HIGHWAY_CONTROLr */
    371         soc_block_list[5],
    372         soc_genreg,
    373         1,
    374         0,
    375         0x1b1b0000,
    376         0,
    377         0,
    378         1,
    379         soc_E2EFC_MEM_TMr_fields,
    380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    381         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    382         -1,
    383         -1,
    384     },
    385 #endif /* chips */
    386 
    387 #if defined(BCM_56800_A0)
    388     { /* SOC_REG_INT_L2MC_DBGCTRLr */
    389         soc_block_list[5],
    390         soc_genreg,
    391         1,
    392         0,
    393         0x6080c0f,
    394         0,
    395         0,
    396         1,
    397         soc_CFAPMEMDEBUGr_fields,
    398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    399         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    400         -1,
    401         -1,
    402     },
    403 #endif /* chips */
    404 
    405 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
    406     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
    407     defined(BCM_56160_A0)
    408     { /* SOC_REG_INT_L2MC_DBGCTRL_BCM53400_A0r */
    409         soc_block_list[5],
    410         soc_genreg,
    411         1,
    412         0,
    413         0x22010000,
    414         0,
    415         0,
    416         1,
    417         soc_DSCP_CONTROLr_fields,
    418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    419         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    420         -1,
    421         -1,
    422     },
    423 #endif /* chips */
    424 
    425 #if defined(BCM_56142_A0)
    426     { /* SOC_REG_INT_L2MC_DBGCTRL_BCM56142_A0r */
    427         soc_block_list[5],
    428         soc_genreg,
    429         1,
    430         0,
    431         0x908014b,
    432         0,
    433         0,
    434         1,
    435         soc_CFAPMEMDEBUGr_fields,
    436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    438         -1,
    439         -1,
    440     },
    441 #endif /* chips */
    442 
    443 #if defined(BCM_56150_A0)
    444     { /* SOC_REG_INT_L2MC_DBGCTRL_BCM56150_A0r */
    445         soc_block_list[5],
    446         soc_genreg,
    447         1,
    448         0,
    449         0x26010000,
    450         0,
    451         0,
    452         1,
    453         soc_INTFO_QCN_SRAM_TMr_fields,
    454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    455         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    456         -1,
    457         -1,
    458     },
    459 #endif /* chips */
    460 
    461 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
    462     { /* SOC_REG_INT_L2MC_DBGCTRL_BCM56334_A0r */
    463         soc_block_list[5],
    464         soc_genreg,
    465         1,
    466         0,
    467         0x9080163,
    468         0,
    469         0,
    470         1,
    471         soc_CFAPMEMDEBUGr_fields,
    472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    473         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    474         -1,
    475         -1,
    476     },
    477 #endif /* chips */
    478 
    479 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    480     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    481     { /* SOC_REG_INT_L2MC_DBGCTRL_BCM56624_A0r */
    482         soc_block_list[5],
    483         soc_genreg,
    484         1,
    485         0,
    486         0x908013d,
    487         0,
    488         0,
    489         1,
    490         soc_CFAPMEMDEBUGr_fields,
    491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    492         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    493         -1,
    494         -1,
    495     },
    496 #endif /* chips */
    497 
    498 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
    499     { /* SOC_REG_INT_L2MC_DBGCTRL_BCM56820_A0r */
    500         soc_block_list[5],
    501         soc_genreg,
    502         1,
    503         0,
    504         0x6080c0f,
    505         0,
    506         0,
    507         2,
    508         soc_CFAPMEMDEBUG_BCM56820_A0r_fields,
    509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    510         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    511         -1,
    512         -1,
    513     },
    514 #endif /* chips */
    515 
    516 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
    517     defined(BCM_56270_A0)
    518     { /* SOC_REG_INT_L2MC_ECCP_CONTROLr */
    519         soc_block_list[5],
    520         soc_genreg,
    521         1,
    522         0,
    523         0x3a010700,
    524         0,
    525         0,
    526         2,
    527         soc_EGR_MASK_ECC_CONTROLr_fields,
    528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    529         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    530         -1,
    531         -1,
    532     },
    533 #endif /* chips */
    534 
    535 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
    536     defined(BCM_56820_A0)
    537     { /* SOC_REG_INT_L2MC_PARITY_CONTROLr */
    538         soc_block_list[5],
    539         soc_genreg,
    540         1,
    541         0,
    542         0x6080c11,
    543         0,
    544         0,
    545         2,
    546         soc_L2_ENTRY_PARITY_CONTROLr_fields,
    547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    548         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    549         -1,
    550         -1,
    551     },
    552 #endif /* chips */
    553 
    554 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
    555     defined(BCM_56160_A0)
    556     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM53400_A0r */
    557         soc_block_list[5],
    558         soc_genreg,
    559         1,
    560         0,
    561         0x22010100,
    562         0,
    563         0,
    564         1,
    565         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
    566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    567         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    568         -1,
    569         -1,
    570     },
    571 #endif /* chips */
    572 
    573 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
    574     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM53570_A0r */
    575         soc_block_list[5],
    576         soc_genreg,
    577         1,
    578         0,
    579         0x3e010800,
    580         0,
    581         0,
    582         1,
    583         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
    584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    585         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    586         -1,
    587         -1,
    588     },
    589 #endif /* chips */
    590 
    591 #if defined(BCM_56142_A0)
    592     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM56142_A0r */
    593         soc_block_list[5],
    594         soc_genreg,
    595         1,
    596         0,
    597         0x908014c,
    598         0,
    599         0,
    600         1,
    601         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
    602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    603         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    604         -1,
    605         -1,
    606     },
    607 #endif /* chips */
    608 
    609 #if defined(BCM_56150_A0)
    610     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM56150_A0r */
    611         soc_block_list[5],
    612         soc_genreg,
    613         1,
    614         0,
    615         0x26010100,
    616         0,
    617         0,
    618         1,
    619         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
    620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    621         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    622         -1,
    623         -1,
    624     },
    625 #endif /* chips */
    626 
    627 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
    628     defined(BCM_56224_A0) || defined(BCM_56224_B0)
    629     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM56224_A0r */
    630         soc_block_list[5],
    631         soc_genreg,
    632         1,
    633         0,
    634         0x7080001,
    635         0,
    636         0,
    637         2,
    638         soc_L2_ENTRY_PARITY_CONTROLr_fields,
    639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    640         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    641         -1,
    642         -1,
    643     },
    644 #endif /* chips */
    645 
    646 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
    647     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM56334_A0r */
    648         soc_block_list[5],
    649         soc_genreg,
    650         1,
    651         0,
    652         0x9080164,
    653         0,
    654         0,
    655         1,
    656         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
    657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    658         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    659         -1,
    660         -1,
    661     },
    662 #endif /* chips */
    663 
    664 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    665     defined(BCM_56450_B1)
    666     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM56450_A0r */
    667         soc_block_list[5],
    668         soc_genreg,
    669         1,
    670         0,
    671         0x3a010700,
    672         0,
    673         0,
    674         1,
    675         soc_FT_CNTR_SER_CONTROLr_fields,
    676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    677         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    678         -1,
    679         -1,
    680     },
    681 #endif /* chips */
    682 
    683 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    684     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    685     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM56624_A0r */
    686         soc_block_list[5],
    687         soc_genreg,
    688         1,
    689         0,
    690         0x908013e,
    691         0,
    692         0,
    693         1,
    694         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
    695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    696         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    697         -1,
    698         -1,
    699     },
    700 #endif /* chips */
    701 
    702 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    703     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    704     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    705     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM56634_A0r */
    706         soc_block_list[5],
    707         soc_genreg,
    708         1,
    709         0,
    710         0xd080225,
    711         0,
    712         0,
    713         1,
    714         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
    715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    716         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    717         -1,
    718         -1,
    719     },
    720 #endif /* chips */
    721 
    722 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
    723     defined(BCM_56840_A0) || defined(BCM_56840_B0)
    724     { /* SOC_REG_INT_L2MC_PARITY_CONTROL_BCM56840_A0r */
    725         soc_block_list[5],
    726         soc_genreg,
    727         1,
    728         0,
    729         0xe080d06,
    730         0,
    731         0,
    732         1,
    733         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
    734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    736         -1,
    737         -1,
    738     },
    739 #endif /* chips */
    740 
    741 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
    742     defined(BCM_56820_A0)
    743     { /* SOC_REG_INT_L2MC_PARITY_STATUSr */
    744         soc_block_list[5],
    745         soc_genreg,
    746         1,
    747         0,
    748         0x6080c12,
    749         SOC_REG_FLAG_RO,
    750         0,
    751         2,
    752         soc_L2MC_PARITY_STATUSr_fields,
    753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    754         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    755         -1,
    756         -1,
    757     },
    758 #endif /* chips */
    759 
    760 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
    761     { /* SOC_REG_INT_L2MC_PARITY_STATUS_BCM53400_A0r */
    762         soc_block_list[5],
    763         soc_genreg,
    764         1,
    765         0,
    766         0x22010200,
    767         0,
    768         0,
    769         3,
    770         soc_EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr_fields,
    771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    772         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    773         -1,
    774         -1,
    775     },
    776 #endif /* chips */
    777 
    778 #if defined(BCM_53540_A0)
    779     { /* SOC_REG_INT_L2MC_PARITY_STATUS_BCM53540_A0r */
    780         soc_block_list[5],
    781         soc_genreg,
    782         1,
    783         0,
    784         0x22010200,
    785         0,
    786         0,
    787         3,
    788         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
    789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    790         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
    791         -1,
    792         -1,
    793     },
    794 #endif /* chips */
    795 
    796 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
    797     { /* SOC_REG_INT_L2MC_PARITY_STATUS_BCM53570_A0r */
    798         soc_block_list[5],
    799         soc_genreg,
    800         1,
    801         0,
    802         0x3e010900,
    803         0,
    804         0,
    805         3,
    806         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
    807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    808         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    809         -1,
    810         -1,
    811     },
    812 #endif /* chips */
    813 
    814 #if defined(BCM_56142_A0)
    815     { /* SOC_REG_INT_L2MC_PARITY_STATUS_BCM56142_A0r */
    816         soc_block_list[5],
    817         soc_genreg,
    818         1,
    819         0,
    820         0x908014d,
    821         0,
    822         0,
    823         3,
    824         soc_EGR_IP_TUNNEL_PARITY_STATUSr_fields,
    825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    826         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    827         -1,
    828         -1,
    829     },
    830 #endif /* chips */
    831 
    832 #if defined(BCM_56150_A0)
    833     { /* SOC_REG_INT_L2MC_PARITY_STATUS_BCM56150_A0r */
    834         soc_block_list[5],
    835         soc_genreg,
    836         1,
    837         0,
    838         0x26010200,
    839         0,
    840         0,
    841         3,
    842         soc_AXP_WTX_FRAG_ID_PAR_STATUS_INTRr_fields,
    843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    844         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    845         -1,
    846         -1,
    847     },
    848 #endif /* chips */
    849 
    850 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
    851     defined(BCM_56224_A0) || defined(BCM_56224_B0)
    852     { /* SOC_REG_INT_L2MC_PARITY_STATUS_BCM56224_A0r */
    853         soc_block_list[5],
    854         soc_genreg,
    855         1,
    856         0,
    857         0x7080002,
    858         SOC_REG_FLAG_RO,
    859         0,
    860         2,
    861         soc_ING_L3_NEXT_HOP_PARITY_STATUSr_fields,
    862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    863         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
    864         -1,
    865         -1,
    866     },
    867 #endif /* chips */
    868 
    869 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
    870     { /* SOC_REG_INT_L2MC_PARITY_STATUS_BCM56334_A0r */
    871         soc_block_list[5],
    872         soc_genreg,
    873         1,
    874         0,
    875         0x9080165,
    876         0,
    877         0,
    878         3,
    879         soc_EGR_IP_TUNNEL_PARITY_STATUSr_fields,
    880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    881         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    882         -1,
    883         -1,
    884     },
    885 #endif /* chips */
    886 
    887 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    888     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    889     { /* SOC_REG_INT_L2MC_PARITY_STATUS_BCM56624_A0r */
    890         soc_block_list[5],
    891         soc_genreg,
    892         1,
    893         0,
    894         0x908013f,
    895         0,
    896         0,
    897         3,
    898         soc_EGR_IP_TUNNEL_PARITY_STATUSr_fields,
    899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    900         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    901         -1,
    902         -1,
    903     },
    904 #endif /* chips */
    905 
    906 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    907     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    908     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    909     { /* SOC_REG_INT_L2MC_PARITY_STATUS_INTRr */
    910         soc_block_list[5],
    911         soc_genreg,
    912         1,
    913         0,
    914         0xd080226,
    915         0,
    916         0,
    917         3,
    918         soc_EGR_IP_TUNNEL_PARITY_STATUSr_fields,
    919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    920         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    921         -1,
    922         -1,
    923     },
    924 #endif /* chips */
    925 
    926 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    927     { /* SOC_REG_INT_L2MC_PARITY_STATUS_INTR_BCM56440_A0r */
    928         soc_block_list[5],
    929         soc_genreg,
    930         1,
    931         0,
    932         0xe080d07,
    933         0,
    934         0,
    935         3,
    936         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
    937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    938         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    939         -1,
    940         -1,
    941     },
    942 #endif /* chips */
    943 
    944 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    945     defined(BCM_56450_B1)
    946     { /* SOC_REG_INT_L2MC_PARITY_STATUS_INTR_BCM56450_A0r */
    947         soc_block_list[5],
    948         soc_genreg,
    949         1,
    950         0,
    951         0x3a010800,
    952         0,
    953         0,
    954         3,
    955         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
    956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    958         -1,
    959         -1,
    960     },
    961 #endif /* chips */
    962 
    963 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
    964     { /* SOC_REG_INT_L2MC_PARITY_STATUS_INTR_BCM56840_A0r */
    965         soc_block_list[5],
    966         soc_genreg,
    967         1,
    968         0,
    969         0xe080d07,
    970         0,
    971         0,
    972         3,
    973         soc_L3_IIF_PARITY_STATUS_NACKr_fields,
    974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    976         -1,
    977         -1,
    978     },
    979 #endif /* chips */
    980 
    981 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    982     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    983     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    984     { /* SOC_REG_INT_L2MC_PARITY_STATUS_NACKr */
    985         soc_block_list[5],
    986         soc_genreg,
    987         1,
    988         0,
    989         0xd080227,
    990         0,
    991         0,
    992         3,
    993         soc_EGR_IP_TUNNEL_PARITY_STATUSr_fields,
    994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    995         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    996         -1,
    997         -1,
    998     },
    999 #endif /* chips */
   1000 
   1001 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1002     { /* SOC_REG_INT_L2MC_PARITY_STATUS_NACK_BCM56440_A0r */
   1003         soc_block_list[5],
   1004         soc_genreg,
   1005         1,
   1006         0,
   1007         0xe080d08,
   1008         0,
   1009         0,
   1010         3,
   1011         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
   1012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1013         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1014         -1,
   1015         -1,
   1016     },
   1017 #endif /* chips */
   1018 
   1019 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1020     defined(BCM_56450_B1)
   1021     { /* SOC_REG_INT_L2MC_PARITY_STATUS_NACK_BCM56450_A0r */
   1022         soc_block_list[5],
   1023         soc_genreg,
   1024         1,
   1025         0,
   1026         0x3a010900,
   1027         0,
   1028         0,
   1029         3,
   1030         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
   1031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1032         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1033         -1,
   1034         -1,
   1035     },
   1036 #endif /* chips */
   1037 
   1038 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   1039     { /* SOC_REG_INT_L2MC_PARITY_STATUS_NACK_BCM56840_A0r */
   1040         soc_block_list[5],
   1041         soc_genreg,
   1042         1,
   1043         0,
   1044         0xe080d08,
   1045         0,
   1046         0,
   1047         3,
   1048         soc_L3_IIF_PARITY_STATUS_NACKr_fields,
   1049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1050         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1051         -1,
   1052         -1,
   1053     },
   1054 #endif /* chips */
   1055 
   1056 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
   1057     defined(BCM_53570_B0) || defined(BCM_56160_A0)
   1058     { /* SOC_REG_INT_L2_128_OVF_LEARNED_CNTr */
   1059         soc_block_list[5],
   1060         soc_genreg,
   1061         1,
   1062         0,
   1063         0x1e000a00,
   1064         0,
   1065         0,
   1066         1,
   1067         soc_IHOST_PTIM_TIMER_COUNTERr_fields,
   1068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1069         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1070         -1,
   1071         -1,
   1072     },
   1073 #endif /* chips */
   1074 
   1075 #if defined(BCM_56504_A0) || defined(BCM_56504_B0)
   1076     { /* SOC_REG_INT_L2_AGE_DEBUGr */
   1077         soc_block_list[5],
   1078         soc_genreg,
   1079         1,
   1080         0,
   1081         0x80005,
   1082         0,
   1083         0,
   1084         3,
   1085         soc_L2_AGE_DEBUGr_fields,
   1086         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
   1087         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1088         -1,
   1089         -1,
   1090     },
   1091 #endif /* chips */
   1092 
   1093 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1094     defined(BCM_56334_B0) || defined(BCM_56524_A0) || \
   1095     defined(BCM_56524_B0) || defined(BCM_56624_A0) || \
   1096     defined(BCM_56624_B0) || defined(BCM_56634_A0) || \
   1097     defined(BCM_56634_B0) || defined(BCM_56680_A0) || \
   1098     defined(BCM_56680_B0) || defined(BCM_56685_A0) || \
   1099     defined(BCM_56685_B0)
   1100     { /* SOC_REG_INT_L2_AGE_DEBUG_2r */
   1101         soc_block_list[5],
   1102         soc_genreg,
   1103         1,
   1104         0,
   1105         0x80007,
   1106         0,
   1107         0,
   1108         1,
   1109         soc_L2_AGE_DEBUG_2r_fields,
   1110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1111         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1112         -1,
   1113         -1,
   1114     },
   1115 #endif /* chips */
   1116 
   1117 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   1118     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   1119     defined(BCM_56160_A0)
   1120     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM53400_A0r */
   1121         soc_block_list[5],
   1122         soc_genreg,
   1123         1,
   1124         0,
   1125         0x2000700,
   1126         0,
   1127         0,
   1128         1,
   1129         soc_L2_AGE_DEBUG_2_BCM53400_A0r_fields,
   1130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1131         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1132         -1,
   1133         -1,
   1134     },
   1135 #endif /* chips */
   1136 
   1137 #if defined(BCM_56150_A0)
   1138     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM56150_A0r */
   1139         soc_block_list[5],
   1140         soc_genreg,
   1141         1,
   1142         0,
   1143         0x2000700,
   1144         0,
   1145         0,
   1146         1,
   1147         soc_L2_AGE_DEBUG_2_BCM56150_A0r_fields,
   1148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1149         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1150         -1,
   1151         -1,
   1152     },
   1153 #endif /* chips */
   1154 
   1155 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   1156     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM56260_A0r */
   1157         soc_block_list[5],
   1158         soc_genreg,
   1159         1,
   1160         0,
   1161         0x2010900,
   1162         0,
   1163         0,
   1164         1,
   1165         soc_L2_AGE_DEBUG_2_BCM53400_A0r_fields,
   1166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1167         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1168         -1,
   1169         -1,
   1170     },
   1171 #endif /* chips */
   1172 
   1173 #if defined(BCM_56270_A0)
   1174     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM56270_A0r */
   1175         soc_block_list[5],
   1176         soc_genreg,
   1177         1,
   1178         0,
   1179         0x2010a00,
   1180         0,
   1181         0,
   1182         1,
   1183         soc_L2_AGE_DEBUG_2_BCM53400_A0r_fields,
   1184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1185         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1186         -1,
   1187         -1,
   1188     },
   1189 #endif /* chips */
   1190 
   1191 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1192     defined(BCM_56450_B1)
   1193     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM56450_A0r */
   1194         soc_block_list[5],
   1195         soc_genreg,
   1196         1,
   1197         0,
   1198         0x2010700,
   1199         0,
   1200         0,
   1201         1,
   1202         soc_L2_AGE_DEBUG_2_BCM56450_A0r_fields,
   1203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1204         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1205         -1,
   1206         -1,
   1207     },
   1208 #endif /* chips */
   1209 
   1210 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   1211     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   1212     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM56560_A0r */
   1213         soc_block_list[5],
   1214         soc_genreg,
   1215         1,
   1216         0,
   1217         0x77070000,
   1218         0,
   1219         0,
   1220         1,
   1221         soc_L2_AGE_DEBUG_2_BCM56560_A0r_fields,
   1222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1223         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   1224         -1,
   1225         -1,
   1226     },
   1227 #endif /* chips */
   1228 
   1229 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1230     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM56820_A0r */
   1231         soc_block_list[5],
   1232         soc_genreg,
   1233         1,
   1234         0,
   1235         0x80207,
   1236         0,
   1237         0,
   1238         1,
   1239         soc_L2_AGE_DEBUG_2r_fields,
   1240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1241         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1242         -1,
   1243         -1,
   1244     },
   1245 #endif /* chips */
   1246 
   1247 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   1248     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   1249     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM56840_A0r */
   1250         soc_block_list[5],
   1251         soc_genreg,
   1252         1,
   1253         0,
   1254         0x80707,
   1255         0,
   1256         0,
   1257         1,
   1258         soc_L2_AGE_DEBUG_2_BCM56840_A0r_fields,
   1259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1260         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1261         -1,
   1262         -1,
   1263     },
   1264 #endif /* chips */
   1265 
   1266 #if defined(BCM_56850_A0)
   1267     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM56850_A0r */
   1268         soc_block_list[5],
   1269         soc_genreg,
   1270         1,
   1271         0,
   1272         0x77070000,
   1273         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1274         0,
   1275         1,
   1276         soc_L2_AGE_DEBUG_2_BCM56850_A0r_fields,
   1277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1278         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   1279         -1,
   1280         -1,
   1281     },
   1282 #endif /* chips */
   1283 
   1284 #if defined(BCM_56860_A0)
   1285     { /* SOC_REG_INT_L2_AGE_DEBUG_2_BCM56860_A0r */
   1286         soc_block_list[5],
   1287         soc_genreg,
   1288         1,
   1289         0,
   1290         0x77070000,
   1291         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1292         0,
   1293         1,
   1294         soc_L2_AGE_DEBUG_2_BCM56860_A0r_fields,
   1295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1296         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   1297         -1,
   1298         -1,
   1299     },
   1300 #endif /* chips */
   1301 
   1302 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   1303     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM53314_A0r */
   1304         soc_block_list[5],
   1305         soc_genreg,
   1306         1,
   1307         0,
   1308         0x80005,
   1309         0,
   1310         0,
   1311         3,
   1312         soc_L2_AGE_DEBUG_BCM53314_A0r_fields,
   1313         SOC_RESET_VAL_DEC(0x00001fff, 0x00000000)
   1314         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1315         -1,
   1316         -1,
   1317     },
   1318 #endif /* chips */
   1319 
   1320 #if defined(BCM_53400_A0)
   1321     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM53400_A0r */
   1322         soc_block_list[5],
   1323         soc_genreg,
   1324         1,
   1325         0,
   1326         0x2000600,
   1327         0,
   1328         0,
   1329         3,
   1330         soc_L2_AGE_DEBUG_BCM53400_A0r_fields,
   1331         SOC_RESET_VAL_DEC(0x00004001, 0x00000000)
   1332         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1333         -1,
   1334         -1,
   1335     },
   1336 #endif /* chips */
   1337 
   1338 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   1339     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM53570_A0r */
   1340         soc_block_list[5],
   1341         soc_genreg,
   1342         1,
   1343         0,
   1344         0x2000600,
   1345         0,
   1346         0,
   1347         3,
   1348         soc_L2_AGE_DEBUG_BCM53570_A0r_fields,
   1349         SOC_RESET_VAL_DEC(0x0000807f, 0x00000000)
   1350         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1351         -1,
   1352         -1,
   1353     },
   1354 #endif /* chips */
   1355 
   1356 #if defined(BCM_56142_A0)
   1357     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56142_A0r */
   1358         soc_block_list[5],
   1359         soc_genreg,
   1360         1,
   1361         0,
   1362         0x80006,
   1363         0,
   1364         0,
   1365         3,
   1366         soc_L2_AGE_DEBUG_BCM56142_A0r_fields,
   1367         SOC_RESET_VAL_DEC(0x00004001, 0x00000000)
   1368         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1369         -1,
   1370         -1,
   1371     },
   1372 #endif /* chips */
   1373 
   1374 #if defined(BCM_56150_A0)
   1375     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56150_A0r */
   1376         soc_block_list[5],
   1377         soc_genreg,
   1378         1,
   1379         0,
   1380         0x2000600,
   1381         0,
   1382         0,
   1383         3,
   1384         soc_L2_AGE_DEBUG_BCM56150_A0r_fields,
   1385         SOC_RESET_VAL_DEC(0x00004001, 0x00000000)
   1386         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1387         -1,
   1388         -1,
   1389     },
   1390 #endif /* chips */
   1391 
   1392 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
   1393     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56160_A0r */
   1394         soc_block_list[5],
   1395         soc_genreg,
   1396         1,
   1397         0,
   1398         0x2000600,
   1399         0,
   1400         0,
   1401         3,
   1402         soc_L2_AGE_DEBUG_BCM56160_A0r_fields,
   1403         SOC_RESET_VAL_DEC(0x0000407f, 0x00000000)
   1404         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1405         -1,
   1406         -1,
   1407     },
   1408 #endif /* chips */
   1409 
   1410 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   1411     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56224_A0r */
   1412         soc_block_list[5],
   1413         soc_genreg,
   1414         1,
   1415         0,
   1416         0x80005,
   1417         0,
   1418         0,
   1419         3,
   1420         soc_L2_AGE_DEBUG_BCM56224_A0r_fields,
   1421         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
   1422         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1423         -1,
   1424         -1,
   1425     },
   1426 #endif /* chips */
   1427 
   1428 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   1429     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56260_A0r */
   1430         soc_block_list[5],
   1431         soc_genreg,
   1432         1,
   1433         0,
   1434         0x2010800,
   1435         0,
   1436         0,
   1437         4,
   1438         soc_L2_AGE_DEBUG_BCM56260_A0r_fields,
   1439         SOC_RESET_VAL_DEC(0x00008001, 0x00000000)
   1440         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   1441         -1,
   1442         -1,
   1443     },
   1444 #endif /* chips */
   1445 
   1446 #if defined(BCM_56270_A0)
   1447     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56270_A0r */
   1448         soc_block_list[5],
   1449         soc_genreg,
   1450         1,
   1451         0,
   1452         0x2010900,
   1453         0,
   1454         0,
   1455         4,
   1456         soc_L2_AGE_DEBUG_BCM56260_A0r_fields,
   1457         SOC_RESET_VAL_DEC(0x00008001, 0x00000000)
   1458         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   1459         -1,
   1460         -1,
   1461     },
   1462 #endif /* chips */
   1463 
   1464 #if defined(BCM_56314_A0)
   1465     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56314_A0r */
   1466         soc_block_list[5],
   1467         soc_genreg,
   1468         1,
   1469         0,
   1470         0x80005,
   1471         0,
   1472         0,
   1473         3,
   1474         soc_L2_AGE_DEBUG_BCM56314_A0r_fields,
   1475         SOC_RESET_VAL_DEC(0x000003ff, 0x00000000)
   1476         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1477         -1,
   1478         -1,
   1479     },
   1480 #endif /* chips */
   1481 
   1482 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1483     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56440_A0r */
   1484         soc_block_list[5],
   1485         soc_genreg,
   1486         1,
   1487         0,
   1488         0x80306,
   1489         0,
   1490         0,
   1491         4,
   1492         soc_L2_AGE_DEBUG_BCM56440_A0r_fields,
   1493         SOC_RESET_VAL_DEC(0x00008001, 0x00000000)
   1494         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   1495         -1,
   1496         -1,
   1497     },
   1498 #endif /* chips */
   1499 
   1500 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1501     defined(BCM_56450_B1)
   1502     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56450_A0r */
   1503         soc_block_list[5],
   1504         soc_genreg,
   1505         1,
   1506         0,
   1507         0x2010600,
   1508         0,
   1509         0,
   1510         4,
   1511         soc_L2_AGE_DEBUG_BCM56450_A0r_fields,
   1512         SOC_RESET_VAL_DEC(0x00010001, 0x00000000)
   1513         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   1514         -1,
   1515         -1,
   1516     },
   1517 #endif /* chips */
   1518 
   1519 #if defined(BCM_56514_A0)
   1520     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56514_A0r */
   1521         soc_block_list[5],
   1522         soc_genreg,
   1523         1,
   1524         0,
   1525         0x80005,
   1526         0,
   1527         0,
   1528         3,
   1529         soc_L2_AGE_DEBUG_BCM56514_A0r_fields,
   1530         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
   1531         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1532         -1,
   1533         -1,
   1534     },
   1535 #endif /* chips */
   1536 
   1537 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   1538     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56560_A0r */
   1539         soc_block_list[5],
   1540         soc_genreg,
   1541         1,
   1542         0,
   1543         0x77060000,
   1544         0,
   1545         0,
   1546         3,
   1547         soc_L2_AGE_DEBUG_BCM56560_A0r_fields,
   1548         SOC_RESET_VAL_DEC(0x0001ffff, 0x00000000)
   1549         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1550         -1,
   1551         -1,
   1552     },
   1553 #endif /* chips */
   1554 
   1555 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   1556     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   1557     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   1558     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   1559     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   1560     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   1561     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56624_A0r */
   1562         soc_block_list[5],
   1563         soc_genreg,
   1564         1,
   1565         0,
   1566         0x80006,
   1567         0,
   1568         0,
   1569         3,
   1570         soc_L2_AGE_DEBUG_BCM56624_A0r_fields,
   1571         SOC_RESET_VAL_DEC(0x00008001, 0x00000000)
   1572         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1573         -1,
   1574         -1,
   1575     },
   1576 #endif /* chips */
   1577 
   1578 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   1579     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56670_A0r */
   1580         soc_block_list[5],
   1581         soc_genreg,
   1582         1,
   1583         0,
   1584         0x77060000,
   1585         0,
   1586         0,
   1587         3,
   1588         soc_L2_AGE_DEBUG_BCM56670_A0r_fields,
   1589         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
   1590         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1591         -1,
   1592         -1,
   1593     },
   1594 #endif /* chips */
   1595 
   1596 #if defined(BCM_56800_A0)
   1597     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56800_A0r */
   1598         soc_block_list[5],
   1599         soc_genreg,
   1600         1,
   1601         0,
   1602         0x80206,
   1603         0,
   1604         0,
   1605         3,
   1606         soc_L2_AGE_DEBUG_BCM56314_A0r_fields,
   1607         SOC_RESET_VAL_DEC(0x000003ff, 0x00000000)
   1608         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1609         -1,
   1610         -1,
   1611     },
   1612 #endif /* chips */
   1613 
   1614 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1615     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56820_A0r */
   1616         soc_block_list[5],
   1617         soc_genreg,
   1618         1,
   1619         0,
   1620         0x80206,
   1621         0,
   1622         0,
   1623         5,
   1624         soc_L2_AGE_DEBUG_BCM56820_A0r_fields,
   1625         SOC_RESET_VAL_DEC(0x01008001, 0x00000000)
   1626         SOC_RESET_MASK_DEC(0x0ffdffff, 0x00000000)
   1627         -1,
   1628         -1,
   1629     },
   1630 #endif /* chips */
   1631 
   1632 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   1633     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56840_A0r */
   1634         soc_block_list[5],
   1635         soc_genreg,
   1636         1,
   1637         0,
   1638         0x80306,
   1639         0,
   1640         0,
   1641         4,
   1642         soc_L2_AGE_DEBUG_BCM56840_A0r_fields,
   1643         SOC_RESET_VAL_DEC(0x0001ffff, 0x00000000)
   1644         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   1645         -1,
   1646         -1,
   1647     },
   1648 #endif /* chips */
   1649 
   1650 #if defined(BCM_56850_A0)
   1651     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56850_A0r */
   1652         soc_block_list[5],
   1653         soc_genreg,
   1654         1,
   1655         0,
   1656         0x77060000,
   1657         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1658         0,
   1659         4,
   1660         soc_L2_AGE_DEBUG_BCM56850_A0r_fields,
   1661         SOC_RESET_VAL_DEC(0x0001ffff, 0x00000000)
   1662         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1663         -1,
   1664         -1,
   1665     },
   1666 #endif /* chips */
   1667 
   1668 #if defined(BCM_56860_A0)
   1669     { /* SOC_REG_INT_L2_AGE_DEBUG_BCM56860_A0r */
   1670         soc_block_list[5],
   1671         soc_genreg,
   1672         1,
   1673         0,
   1674         0x77060000,
   1675         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1676         0,
   1677         3,
   1678         soc_L2_AGE_DEBUG_BCM56860_A0r_fields,
   1679         SOC_RESET_VAL_DEC(0x0001ffff, 0x00000000)
   1680         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1681         -1,
   1682         -1,
   1683     },
   1684 #endif /* chips */
   1685 
   1686 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   1687     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
   1688     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1689     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1690     { /* SOC_REG_INT_L2_AGE_TIMERr */
   1691         soc_block_list[5],
   1692         soc_genreg,
   1693         1,
   1694         0,
   1695         0x80003,
   1696         0,
   1697         0,
   1698         2,
   1699         soc_L2_AGE_TIMERr_fields,
   1700         SOC_RESET_VAL_DEC(0x0010012c, 0x00000000)
   1701         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1702         -1,
   1703         -1,
   1704     },
   1705 #endif /* chips */
   1706 
   1707 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   1708     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   1709     defined(BCM_56160_A0)
   1710     { /* SOC_REG_INT_L2_AGE_TIMER_BCM53400_A0r */
   1711         soc_block_list[5],
   1712         soc_genreg,
   1713         1,
   1714         0,
   1715         0x2000400,
   1716         0,
   1717         0,
   1718         2,
   1719         soc_L2_AGE_TIMER_BCM53400_A0r_fields,
   1720         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1721         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1722         -1,
   1723         -1,
   1724     },
   1725 #endif /* chips */
   1726 
   1727 #if defined(BCM_56150_A0)
   1728     { /* SOC_REG_INT_L2_AGE_TIMER_BCM56150_A0r */
   1729         soc_block_list[5],
   1730         soc_genreg,
   1731         1,
   1732         0,
   1733         0x2000400,
   1734         0,
   1735         0,
   1736         2,
   1737         soc_L2_AGE_TIMER_BCM56850_A0r_fields,
   1738         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1739         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1740         -1,
   1741         -1,
   1742     },
   1743 #endif /* chips */
   1744 
   1745 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   1746     { /* SOC_REG_INT_L2_AGE_TIMER_BCM56260_A0r */
   1747         soc_block_list[5],
   1748         soc_genreg,
   1749         1,
   1750         0,
   1751         0x2010600,
   1752         0,
   1753         0,
   1754         2,
   1755         soc_L2_AGE_TIMER_BCM53400_A0r_fields,
   1756         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1757         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1758         -1,
   1759         -1,
   1760     },
   1761 #endif /* chips */
   1762 
   1763 #if defined(BCM_56270_A0)
   1764     { /* SOC_REG_INT_L2_AGE_TIMER_BCM56270_A0r */
   1765         soc_block_list[5],
   1766         soc_genreg,
   1767         1,
   1768         0,
   1769         0x2010700,
   1770         0,
   1771         0,
   1772         2,
   1773         soc_L2_AGE_TIMER_BCM53400_A0r_fields,
   1774         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1775         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1776         -1,
   1777         -1,
   1778     },
   1779 #endif /* chips */
   1780 
   1781 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1782     defined(BCM_56450_B1)
   1783     { /* SOC_REG_INT_L2_AGE_TIMER_BCM56450_A0r */
   1784         soc_block_list[5],
   1785         soc_genreg,
   1786         1,
   1787         0,
   1788         0x2010400,
   1789         0,
   1790         0,
   1791         2,
   1792         soc_L2_AGE_TIMER_BCM56850_A0r_fields,
   1793         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1794         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1795         -1,
   1796         -1,
   1797     },
   1798 #endif /* chips */
   1799 
   1800 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   1801     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   1802     { /* SOC_REG_INT_L2_AGE_TIMER_BCM56560_A0r */
   1803         soc_block_list[5],
   1804         soc_genreg,
   1805         1,
   1806         0,
   1807         0x77040000,
   1808         0,
   1809         0,
   1810         2,
   1811         soc_L2_AGE_TIMER_BCM53400_A0r_fields,
   1812         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1813         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1814         -1,
   1815         -1,
   1816     },
   1817 #endif /* chips */
   1818 
   1819 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1820     defined(BCM_56334_B0) || defined(BCM_56524_A0) || \
   1821     defined(BCM_56524_B0) || defined(BCM_56624_A0) || \
   1822     defined(BCM_56624_B0) || defined(BCM_56634_A0) || \
   1823     defined(BCM_56634_B0) || defined(BCM_56680_A0) || \
   1824     defined(BCM_56680_B0) || defined(BCM_56685_A0) || \
   1825     defined(BCM_56685_B0)
   1826     { /* SOC_REG_INT_L2_AGE_TIMER_BCM56624_A0r */
   1827         soc_block_list[5],
   1828         soc_genreg,
   1829         1,
   1830         0,
   1831         0x80004,
   1832         0,
   1833         0,
   1834         2,
   1835         soc_L2_AGE_TIMER_BCM56800_A0r_fields,
   1836         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1837         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1838         -1,
   1839         -1,
   1840     },
   1841 #endif /* chips */
   1842 
   1843 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   1844     defined(BCM_56820_A0)
   1845     { /* SOC_REG_INT_L2_AGE_TIMER_BCM56800_A0r */
   1846         soc_block_list[5],
   1847         soc_genreg,
   1848         1,
   1849         0,
   1850         0x80204,
   1851         0,
   1852         0,
   1853         2,
   1854         soc_L2_AGE_TIMER_BCM56800_A0r_fields,
   1855         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1856         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1857         -1,
   1858         -1,
   1859     },
   1860 #endif /* chips */
   1861 
   1862 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   1863     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   1864     { /* SOC_REG_INT_L2_AGE_TIMER_BCM56840_A0r */
   1865         soc_block_list[5],
   1866         soc_genreg,
   1867         1,
   1868         0,
   1869         0x80304,
   1870         0,
   1871         0,
   1872         2,
   1873         soc_L2_AGE_TIMER_BCM56800_A0r_fields,
   1874         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1875         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1876         -1,
   1877         -1,
   1878     },
   1879 #endif /* chips */
   1880 
   1881 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   1882     { /* SOC_REG_INT_L2_AGE_TIMER_BCM56850_A0r */
   1883         soc_block_list[5],
   1884         soc_genreg,
   1885         1,
   1886         0,
   1887         0x77040000,
   1888         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1889         0,
   1890         2,
   1891         soc_L2_AGE_TIMER_BCM56850_A0r_fields,
   1892         SOC_RESET_VAL_DEC(0x0000012c, 0x00000000)
   1893         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1894         -1,
   1895         -1,
   1896     },
   1897 #endif /* chips */
   1898 
   1899 #if defined(BCM_56514_A0)
   1900     { /* SOC_REG_INT_L2_AUX_HASH_CONTROLr */
   1901         soc_block_list[5],
   1902         soc_genreg,
   1903         1,
   1904         0,
   1905         0x608000e,
   1906         0,
   1907         0,
   1908         2,
   1909         soc_L2_AUX_HASH_CONTROLr_fields,
   1910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1911         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1912         -1,
   1913         -1,
   1914     },
   1915 #endif /* chips */
   1916 
   1917 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   1918     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM53314_A0r */
   1919         soc_block_list[5],
   1920         soc_genreg,
   1921         1,
   1922         0,
   1923         0x608000c,
   1924         0,
   1925         0,
   1926         2,
   1927         soc_L2_AUX_HASH_CONTROL_BCM53314_A0r_fields,
   1928         SOC_RESET_VAL_DEC(0x00000009, 0x00000000)
   1929         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1930         -1,
   1931         -1,
   1932     },
   1933 #endif /* chips */
   1934 
   1935 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   1936     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   1937     defined(BCM_56160_A0)
   1938     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM53400_A0r */
   1939         soc_block_list[5],
   1940         soc_genreg,
   1941         1,
   1942         0,
   1943         0x1e000100,
   1944         0,
   1945         0,
   1946         3,
   1947         soc_L2_AUX_HASH_CONTROL_BCM53400_A0r_fields,
   1948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1949         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1950         -1,
   1951         -1,
   1952     },
   1953 #endif /* chips */
   1954 
   1955 #if defined(BCM_56142_A0)
   1956     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM56142_A0r */
   1957         soc_block_list[5],
   1958         soc_genreg,
   1959         1,
   1960         0,
   1961         0x7080015,
   1962         0,
   1963         0,
   1964         3,
   1965         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
   1966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1967         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1968         -1,
   1969         -1,
   1970     },
   1971 #endif /* chips */
   1972 
   1973 #if defined(BCM_56150_A0)
   1974     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM56150_A0r */
   1975         soc_block_list[5],
   1976         soc_genreg,
   1977         1,
   1978         0,
   1979         0x1e000100,
   1980         0,
   1981         0,
   1982         3,
   1983         soc_L2_AUX_HASH_CONTROL_BCM56450_A0r_fields,
   1984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1985         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1986         -1,
   1987         -1,
   1988     },
   1989 #endif /* chips */
   1990 
   1991 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   1992     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM56224_A0r */
   1993         soc_block_list[5],
   1994         soc_genreg,
   1995         1,
   1996         0,
   1997         0x608000c,
   1998         0,
   1999         0,
   2000         2,
   2001         soc_L2_AUX_HASH_CONTROLr_fields,
   2002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2003         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2004         -1,
   2005         -1,
   2006     },
   2007 #endif /* chips */
   2008 
   2009 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   2010     defined(BCM_56270_A0)
   2011     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM56260_A0r */
   2012         soc_block_list[5],
   2013         soc_genreg,
   2014         1,
   2015         0,
   2016         0x1a000000,
   2017         0,
   2018         0,
   2019         3,
   2020         soc_L2_AUX_HASH_CONTROL_BCM53400_A0r_fields,
   2021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2022         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   2023         -1,
   2024         -1,
   2025     },
   2026 #endif /* chips */
   2027 
   2028 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2029     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM56440_A0r */
   2030         soc_block_list[5],
   2031         soc_genreg,
   2032         1,
   2033         0,
   2034         0x6080615,
   2035         0,
   2036         0,
   2037         3,
   2038         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
   2039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2040         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   2041         -1,
   2042         -1,
   2043     },
   2044 #endif /* chips */
   2045 
   2046 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2047     defined(BCM_56450_B1)
   2048     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM56450_A0r */
   2049         soc_block_list[5],
   2050         soc_genreg,
   2051         1,
   2052         0,
   2053         0x1a000000,
   2054         0,
   2055         0,
   2056         3,
   2057         soc_L2_AUX_HASH_CONTROL_BCM56450_A0r_fields,
   2058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2059         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   2060         -1,
   2061         -1,
   2062     },
   2063 #endif /* chips */
   2064 
   2065 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   2066     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2067     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   2068     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2069     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   2070     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2071     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM56624_A0r */
   2072         soc_block_list[5],
   2073         soc_genreg,
   2074         1,
   2075         0,
   2076         0x7080015,
   2077         0,
   2078         0,
   2079         3,
   2080         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
   2081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2082         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   2083         -1,
   2084         -1,
   2085     },
   2086 #endif /* chips */
   2087 
   2088 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   2089     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM56820_A0r */
   2090         soc_block_list[5],
   2091         soc_genreg,
   2092         1,
   2093         0,
   2094         0x6080617,
   2095         0,
   2096         0,
   2097         3,
   2098         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
   2099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2100         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   2101         -1,
   2102         -1,
   2103     },
   2104 #endif /* chips */
   2105 
   2106 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   2107     { /* SOC_REG_INT_L2_AUX_HASH_CONTROL_BCM56840_A0r */
   2108         soc_block_list[5],
   2109         soc_genreg,
   2110         1,
   2111         0,
   2112         0x6080600,
   2113         0,
   2114         0,
   2115         3,
   2116         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
   2117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2118         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   2119         -1,
   2120         -1,
   2121     },
   2122 #endif /* chips */
   2123 
   2124 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   2125     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   2126     { /* SOC_REG_INT_L2_BULK_CONTROLr */
   2127         soc_block_list[5],
   2128         soc_genreg,
   2129         1,
   2130         0,
   2131         0x80305,
   2132         0,
   2133         0,
   2134         4,
   2135         soc_L2_BULK_CONTROLr_fields,
   2136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2137         SOC_RESET_MASK_DEC(0x00000017, 0x00000000)
   2138         -1,
   2139         -1,
   2140     },
   2141 #endif /* chips */
   2142 
   2143 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   2144     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56260_A0r */
   2145         soc_block_list[5],
   2146         soc_genreg,
   2147         1,
   2148         0,
   2149         0x2010700,
   2150         0,
   2151         0,
   2152         4,
   2153         soc_L2_BULK_CONTROL_BCM56260_A0r_fields,
   2154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2155         SOC_RESET_MASK_DEC(0x00000017, 0x00000000)
   2156         -1,
   2157         -1,
   2158     },
   2159 #endif /* chips */
   2160 
   2161 #if defined(BCM_56270_A0)
   2162     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56270_A0r */
   2163         soc_block_list[5],
   2164         soc_genreg,
   2165         1,
   2166         0,
   2167         0x2010800,
   2168         0,
   2169         0,
   2170         4,
   2171         soc_L2_BULK_CONTROL_BCM56260_A0r_fields,
   2172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2173         SOC_RESET_MASK_DEC(0x00000017, 0x00000000)
   2174         -1,
   2175         -1,
   2176     },
   2177 #endif /* chips */
   2178 
   2179 #if defined(BCM_56340_A0)
   2180     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56340_A0r */
   2181         soc_block_list[87],
   2182         soc_genreg,
   2183         1,
   2184         0,
   2185         0xfe000200,
   2186         0,
   2187         0,
   2188         8,
   2189         soc_L2_BULK_CONTROL_BCM56340_A0r_fields,
   2190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2192         -1,
   2193         -1,
   2194     },
   2195 #endif /* chips */
   2196 
   2197 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2198     defined(BCM_56450_B1)
   2199     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56450_A0r */
   2200         soc_block_list[5],
   2201         soc_genreg,
   2202         1,
   2203         0,
   2204         0x2010500,
   2205         0,
   2206         0,
   2207         4,
   2208         soc_L2_BULK_CONTROL_BCM56850_A0r_fields,
   2209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2210         SOC_RESET_MASK_DEC(0x00000017, 0x00000000)
   2211         -1,
   2212         -1,
   2213     },
   2214 #endif /* chips */
   2215 
   2216 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   2217     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   2218     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56560_A0r */
   2219         soc_block_list[5],
   2220         soc_genreg,
   2221         1,
   2222         0,
   2223         0x77050000,
   2224         0,
   2225         0,
   2226         4,
   2227         soc_L2_BULK_CONTROL_BCM56560_A0r_fields,
   2228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2229         SOC_RESET_MASK_DEC(0x00000017, 0x00000000)
   2230         -1,
   2231         -1,
   2232     },
   2233 #endif /* chips */
   2234 
   2235 #if defined(BCM_56640_A0)
   2236     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56640_A0r */
   2237         soc_block_list[87],
   2238         soc_genreg,
   2239         1,
   2240         0,
   2241         0xfe000200,
   2242         0,
   2243         0,
   2244         8,
   2245         soc_L2_BULK_CONTROL_BCM56640_A0r_fields,
   2246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2247         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2248         -1,
   2249         -1,
   2250     },
   2251 #endif /* chips */
   2252 
   2253 #if defined(BCM_56850_A0)
   2254     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56850_A0r */
   2255         soc_block_list[5],
   2256         soc_genreg,
   2257         1,
   2258         0,
   2259         0x77050000,
   2260         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2261         0,
   2262         4,
   2263         soc_L2_BULK_CONTROL_BCM56850_A0r_fields,
   2264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2265         SOC_RESET_MASK_DEC(0x00000017, 0x00000000)
   2266         -1,
   2267         -1,
   2268     },
   2269 #endif /* chips */
   2270 
   2271 #if defined(BCM_56860_A0)
   2272     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56860_A0r */
   2273         soc_block_list[5],
   2274         soc_genreg,
   2275         1,
   2276         0,
   2277         0x77050000,
   2278         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2279         0,
   2280         4,
   2281         soc_L2_BULK_CONTROL_BCM56860_A0r_fields,
   2282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2283         SOC_RESET_MASK_DEC(0x00000017, 0x00000000)
   2284         -1,
   2285         -1,
   2286     },
   2287 #endif /* chips */
   2288 
   2289 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   2290     defined(BCM_56870_A0)
   2291     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56870_A0r */
   2292         soc_block_list[5],
   2293         soc_genreg,
   2294         1,
   2295         0,
   2296         0xaa000200,
   2297         0,
   2298         0,
   2299         6,
   2300         soc_L2_BULK_CONTROL_BCM56960_A0r_fields,
   2301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2303         -1,
   2304         -1,
   2305         3,
   2306     },
   2307 #endif /* chips */
   2308 
   2309 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2310     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56960_A0r */
   2311         soc_block_list[5],
   2312         soc_genreg,
   2313         1,
   2314         0,
   2315         0x62000200,
   2316         0,
   2317         0,
   2318         6,
   2319         soc_L2_BULK_CONTROL_BCM56960_A0r_fields,
   2320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2321         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2322         -1,
   2323         -1,
   2324         3,
   2325     },
   2326 #endif /* chips */
   2327 
   2328 #if defined(BCM_56970_A0)
   2329     { /* SOC_REG_INT_L2_BULK_CONTROL_BCM56970_A0r */
   2330         soc_block_list[5],
   2331         soc_genreg,
   2332         1,
   2333         0,
   2334         0xa2000200,
   2335         0,
   2336         0,
   2337         6,
   2338         soc_L2_BULK_CONTROL_BCM56960_A0r_fields,
   2339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2340         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2341         -1,
   2342         -1,
   2343         3,
   2344     },
   2345 #endif /* chips */
   2346 
   2347 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2348     { /* SOC_REG_INT_L2_BULK_ECC_STATUSr */
   2349         soc_block_list[5],
   2350         soc_genreg,
   2351         1,
   2352         0,
   2353         0x62000300,
   2354         0,
   2355         0,
   2356         2,
   2357         soc_L2_BULK_ECC_STATUSr_fields,
   2358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2359         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2360         -1,
   2361         -1,
   2362         3,
   2363     },
   2364 #endif /* chips */
   2365 
   2366 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   2367     { /* SOC_REG_INT_L2_BULK_ECC_STATUS_BCM56560_A0r */
   2368         soc_block_list[5],
   2369         soc_genreg,
   2370         1,
   2371         0,
   2372         0x1b190000,
   2373         0,
   2374         0,
   2375         2,
   2376         soc_L2_BULK_ECC_STATUS_BCM56560_A0r_fields,
   2377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2378         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2379         -1,
   2380         -1,
   2381     },
   2382 #endif /* chips */
   2383 
   2384 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   2385     { /* SOC_REG_INT_L2_BULK_ECC_STATUS_BCM56670_A0r */
   2386         soc_block_list[5],
   2387         soc_genreg,
   2388         1,
   2389         0,
   2390         0x1b1a0000,
   2391         0,
   2392         0,
   2393         2,
   2394         soc_L2_BULK_ECC_STATUS_BCM56560_A0r_fields,
   2395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2396         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2397         -1,
   2398         -1,
   2399     },
   2400 #endif /* chips */
   2401 
   2402 #if defined(BCM_56860_A0)
   2403     { /* SOC_REG_INT_L2_BULK_ECC_STATUS_BCM56860_A0r */
   2404         soc_block_list[5],
   2405         soc_genreg,
   2406         1,
   2407         0,
   2408         0x1b190000,
   2409         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2410         0,
   2411         2,
   2412         soc_L2_BULK_ECC_STATUS_BCM56860_A0r_fields,
   2413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2414         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2415         -1,
   2416         -1,
   2417     },
   2418 #endif /* chips */
   2419 
   2420 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   2421     defined(BCM_56870_A0)
   2422     { /* SOC_REG_INT_L2_BULK_ECC_STATUS_BCM56870_A0r */
   2423         soc_block_list[5],
   2424         soc_genreg,
   2425         1,
   2426         0,
   2427         0xaa000300,
   2428         0,
   2429         0,
   2430         2,
   2431         soc_L2_BULK_ECC_STATUSr_fields,
   2432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2433         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2434         -1,
   2435         -1,
   2436         3,
   2437     },
   2438 #endif /* chips */
   2439 
   2440 #if defined(BCM_56970_A0)
   2441     { /* SOC_REG_INT_L2_BULK_ECC_STATUS_BCM56970_A0r */
   2442         soc_block_list[5],
   2443         soc_genreg,
   2444         1,
   2445         0,
   2446         0xa2000300,
   2447         0,
   2448         0,
   2449         2,
   2450         soc_L2_BULK_ECC_STATUSr_fields,
   2451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2452         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2453         -1,
   2454         -1,
   2455         3,
   2456     },
   2457 #endif /* chips */
   2458 
   2459 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   2460     { /* SOC_REG_INT_L2_BULK_KEY_TYPE_PORT_Ar */
   2461         soc_block_list[87],
   2462         soc_genreg,
   2463         1,
   2464         0,
   2465         0xfe000500,
   2466         0,
   2467         0,
   2468         1,
   2469         soc_FLOOD_LEARN_KEY_TYPE_PORT_Ar_fields,
   2470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2471         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2472         -1,
   2473         -1,
   2474     },
   2475 #endif /* chips */
   2476 
   2477 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   2478     defined(BCM_56270_A0)
   2479     { /* SOC_REG_INT_L2_BULK_KEY_TYPE_PORT_A_BCM56260_A0r */
   2480         soc_block_list[5],
   2481         soc_genreg,
   2482         1,
   2483         0,
   2484         0x1a000600,
   2485         0,
   2486         0,
   2487         1,
   2488         soc_L2_BULK_KEY_TYPE_PORT_Ar_fields,
   2489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2490         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2491         -1,
   2492         -1,
   2493     },
   2494 #endif /* chips */
   2495 
   2496 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2497     defined(BCM_56450_B1)
   2498     { /* SOC_REG_INT_L2_BULK_KEY_TYPE_PORT_A_BCM56450_A0r */
   2499         soc_block_list[5],
   2500         soc_genreg,
   2501         1,
   2502         0,
   2503         0x1a000600,
   2504         0,
   2505         0,
   2506         1,
   2507         soc_FLOOD_LEARN_KEY_TYPE_PORT_Ar_fields,
   2508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2509         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2510         -1,
   2511         -1,
   2512     },
   2513 #endif /* chips */
   2514 
   2515 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   2516     { /* SOC_REG_INT_L2_BULK_KEY_TYPE_PORT_Br */
   2517         soc_block_list[87],
   2518         soc_genreg,
   2519         1,
   2520         0,
   2521         0xfe000600,
   2522         0,
   2523         0,
   2524         1,
   2525         soc_FLOOD_LEARN_KEY_TYPE_PORT_Ar_fields,
   2526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2527         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2528         -1,
   2529         -1,
   2530     },
   2531 #endif /* chips */
   2532 
   2533 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   2534     defined(BCM_56270_A0)
   2535     { /* SOC_REG_INT_L2_BULK_KEY_TYPE_PORT_B_BCM56260_A0r */
   2536         soc_block_list[5],
   2537         soc_genreg,
   2538         1,
   2539         0,
   2540         0x1a000700,
   2541         0,
   2542         0,
   2543         1,
   2544         soc_L2_BULK_KEY_TYPE_PORT_Ar_fields,
   2545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2546         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2547         -1,
   2548         -1,
   2549     },
   2550 #endif /* chips */
   2551 
   2552 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2553     defined(BCM_56450_B1)
   2554     { /* SOC_REG_INT_L2_BULK_KEY_TYPE_PORT_B_BCM56450_A0r */
   2555         soc_block_list[5],
   2556         soc_genreg,
   2557         1,
   2558         0,
   2559         0x1a000700,
   2560         0,
   2561         0,
   2562         1,
   2563         soc_FLOOD_LEARN_KEY_TYPE_PORT_Ar_fields,
   2564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2565         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2566         -1,
   2567         -1,
   2568     },
   2569 #endif /* chips */
   2570 
   2571 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   2572     { /* SOC_REG_INT_L2_BULK_MATCH_PORT_Ar */
   2573         soc_block_list[87],
   2574         soc_genreg,
   2575         1,
   2576         0,
   2577         0xfe000300,
   2578         0,
   2579         0,
   2580         4,
   2581         soc_L2_BULK_MATCH_PORT_Ar_fields,
   2582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2583         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2584         -1,
   2585         -1,
   2586     },
   2587 #endif /* chips */
   2588 
   2589 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   2590     defined(BCM_56270_A0)
   2591     { /* SOC_REG_INT_L2_BULK_MATCH_PORT_A_BCM56260_A0r */
   2592         soc_block_list[5],
   2593         soc_genreg,
   2594         1,
   2595         0,
   2596         0x1a000400,
   2597         0,
   2598         0,
   2599         4,
   2600         soc_L2_BULK_MATCH_PORT_A_BCM56260_A0r_fields,
   2601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2602         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2603         -1,
   2604         -1,
   2605     },
   2606 #endif /* chips */
   2607 
   2608 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2609     defined(BCM_56450_B1)
   2610     { /* SOC_REG_INT_L2_BULK_MATCH_PORT_A_BCM56450_A0r */
   2611         soc_block_list[5],
   2612         soc_genreg,
   2613         1,
   2614         0,
   2615         0x1a000400,
   2616         0,
   2617         0,
   2618         4,
   2619         soc_L2_BULK_MATCH_PORT_Ar_fields,
   2620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2621         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2622         -1,
   2623         -1,
   2624     },
   2625 #endif /* chips */
   2626 
   2627 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   2628     { /* SOC_REG_INT_L2_BULK_MATCH_PORT_Br */
   2629         soc_block_list[87],
   2630         soc_genreg,
   2631         1,
   2632         0,
   2633         0xfe000400,
   2634         0,
   2635         0,
   2636         4,
   2637         soc_L2_BULK_MATCH_PORT_Ar_fields,
   2638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2639         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2640         -1,
   2641         -1,
   2642     },
   2643 #endif /* chips */
   2644 
   2645 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   2646     defined(BCM_56270_A0)
   2647     { /* SOC_REG_INT_L2_BULK_MATCH_PORT_B_BCM56260_A0r */
   2648         soc_block_list[5],
   2649         soc_genreg,
   2650         1,
   2651         0,
   2652         0x1a000500,
   2653         0,
   2654         0,
   2655         4,
   2656         soc_L2_BULK_MATCH_PORT_A_BCM56260_A0r_fields,
   2657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2658         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2659         -1,
   2660         -1,
   2661     },
   2662 #endif /* chips */
   2663 
   2664 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2665     defined(BCM_56450_B1)
   2666     { /* SOC_REG_INT_L2_BULK_MATCH_PORT_B_BCM56450_A0r */
   2667         soc_block_list[5],
   2668         soc_genreg,
   2669         1,
   2670         0,
   2671         0x1a000500,
   2672         0,
   2673         0,
   2674         4,
   2675         soc_L2_BULK_MATCH_PORT_Ar_fields,
   2676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2677         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2678         -1,
   2679         -1,
   2680     },
   2681 #endif /* chips */
   2682 
   2683 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   2684     { /* SOC_REG_INT_L2_BULK_MATCH_VLANS_CONTROLr */
   2685         soc_block_list[5],
   2686         soc_genreg,
   2687         1,
   2688         0,
   2689         0x1a011500,
   2690         0,
   2691         0,
   2692         1,
   2693         soc_L2_BULK_MATCH_VLANS_CONTROLr_fields,
   2694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2695         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2696         -1,
   2697         -1,
   2698     },
   2699 #endif /* chips */
   2700 
   2701 #if defined(BCM_56270_A0)
   2702     { /* SOC_REG_INT_L2_BULK_MATCH_VLANS_CONTROL_BCM56270_A0r */
   2703         soc_block_list[5],
   2704         soc_genreg,
   2705         1,
   2706         0,
   2707         0x1a011500,
   2708         0,
   2709         0,
   2710         1,
   2711         soc_L2_BULK_MATCH_VLANS_CONTROL_BCM56270_A0r_fields,
   2712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2713         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2714         -1,
   2715         -1,
   2716     },
   2717 #endif /* chips */
   2718 
   2719 #if defined(BCM_56850_A0)
   2720     { /* SOC_REG_INT_L2_ENDPOINT_ID_DBGCTRL_0r */
   2721         soc_block_list[5],
   2722         soc_genreg,
   2723         1,
   2724         0,
   2725         0x1b160000,
   2726         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2727         0,
   2728         4,
   2729         soc_L2_ENDPOINT_ID_DBGCTRL_0r_fields,
   2730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2731         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2732         -1,
   2733         -1,
   2734     },
   2735 #endif /* chips */
   2736 
   2737 #if defined(BCM_56850_A0)
   2738     { /* SOC_REG_INT_L2_ENDPOINT_ID_DBGCTRL_1r */
   2739         soc_block_list[5],
   2740         soc_genreg,
   2741         1,
   2742         0,
   2743         0x1b170000,
   2744         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2745         0,
   2746         4,
   2747         soc_L2_ENDPOINT_ID_DBGCTRL_1r_fields,
   2748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2749         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2750         -1,
   2751         -1,
   2752     },
   2753 #endif /* chips */
   2754 
   2755 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   2756     { /* SOC_REG_INT_L2_ENDPOINT_ID_DBGCTRL_0_BCM56560_A0r */
   2757         soc_block_list[5],
   2758         soc_genreg,
   2759         1,
   2760         0,
   2761         0x1b170000,
   2762         0,
   2763         0,
   2764         4,
   2765         soc_L2_ENDPOINT_ID_DBGCTRL_0_BCM56560_A0r_fields,
   2766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2767         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2768         -1,
   2769         -1,
   2770     },
   2771 #endif /* chips */
   2772 
   2773 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   2774     { /* SOC_REG_INT_L2_ENDPOINT_ID_DBGCTRL_0_BCM56670_A0r */
   2775         soc_block_list[5],
   2776         soc_genreg,
   2777         1,
   2778         0,
   2779         0x1b180000,
   2780         0,
   2781         0,
   2782         4,
   2783         soc_L2_ENDPOINT_ID_DBGCTRL_0_BCM56560_A0r_fields,
   2784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2785         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2786         -1,
   2787         -1,
   2788     },
   2789 #endif /* chips */
   2790 
   2791 #if defined(BCM_56860_A0)
   2792     { /* SOC_REG_INT_L2_ENDPOINT_ID_DBGCTRL_0_BCM56860_A0r */
   2793         soc_block_list[5],
   2794         soc_genreg,
   2795         1,
   2796         0,
   2797         0x1b170000,
   2798         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2799         0,
   2800         4,
   2801         soc_L2_ENDPOINT_ID_DBGCTRL_0_BCM56860_A0r_fields,
   2802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2803         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2804         -1,
   2805         -1,
   2806     },
   2807 #endif /* chips */
   2808 
   2809 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   2810     { /* SOC_REG_INT_L2_ENDPOINT_ID_DBGCTRL_1_BCM56560_A0r */
   2811         soc_block_list[5],
   2812         soc_genreg,
   2813         1,
   2814         0,
   2815         0x1b180000,
   2816         0,
   2817         0,
   2818         4,
   2819         soc_L2_ENDPOINT_ID_DBGCTRL_1_BCM56560_A0r_fields,
   2820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2821         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2822         -1,
   2823         -1,
   2824     },
   2825 #endif /* chips */
   2826 
   2827 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   2828     { /* SOC_REG_INT_L2_ENDPOINT_ID_DBGCTRL_1_BCM56670_A0r */
   2829         soc_block_list[5],
   2830         soc_genreg,
   2831         1,
   2832         0,
   2833         0x1b190000,
   2834         0,
   2835         0,
   2836         4,
   2837         soc_L2_ENDPOINT_ID_DBGCTRL_1_BCM56560_A0r_fields,
   2838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2840         -1,
   2841         -1,
   2842     },
   2843 #endif /* chips */
   2844 
   2845 #if defined(BCM_56860_A0)
   2846     { /* SOC_REG_INT_L2_ENDPOINT_ID_DBGCTRL_1_BCM56860_A0r */
   2847         soc_block_list[5],
   2848         soc_genreg,
   2849         1,
   2850         0,
   2851         0x1b180000,
   2852         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2853         0,
   2854         4,
   2855         soc_L2_ENDPOINT_ID_DBGCTRL_1_BCM56860_A0r_fields,
   2856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2857         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2858         -1,
   2859         -1,
   2860     },
   2861 #endif /* chips */
   2862 
   2863 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   2864     { /* SOC_REG_INT_L2_ENDPOINT_ID_HASH_CONTROLr */
   2865         soc_block_list[5],
   2866         soc_genreg,
   2867         1,
   2868         0,
   2869         0x1a001900,
   2870         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2871         0,
   2872         2,
   2873         soc_EGR_VLAN_XLATE_HASH_CONTROL_BCM56850_A0r_fields,
   2874         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
   2875         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2876         -1,
   2877         -1,
   2878     },
   2879 #endif /* chips */
   2880 
   2881 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   2882     { /* SOC_REG_INT_L2_ENDPOINT_ID_HASH_CONTROL_BCM56560_A0r */
   2883         soc_block_list[5],
   2884         soc_genreg,
   2885         1,
   2886         0,
   2887         0x1a001900,
   2888         0,
   2889         0,
   2890         2,
   2891         soc_EGR_VLAN_XLATE_HASH_CONTROL_BCM53400_A0r_fields,
   2892         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
   2893         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2894         -1,
   2895         -1,
   2896     },
   2897 #endif /* chips */
   2898 
   2899 #if defined(BCM_56514_A0)
   2900     { /* SOC_REG_INT_L2_ENTRY_ADDR_MASKr */
   2901         soc_block_list[5],
   2902         soc_genreg,
   2903         1,
   2904         0,
   2905         0x608000f,
   2906         0,
   2907         0,
   2908         1,
   2909         soc_L2_ENTRY_ADDR_MASKr_fields,
   2910         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
   2911         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   2912         -1,
   2913         -1,
   2914     },
   2915 #endif /* chips */
   2916 
   2917 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   2918     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   2919     { /* SOC_REG_INT_L2_ENTRY_ADDR_MASK_BCM56224_A0r */
   2920         soc_block_list[5],
   2921         soc_genreg,
   2922         1,
   2923         0,
   2924         0x608000e,
   2925         0,
   2926         0,
   2927         1,
   2928         soc_L2_ENTRY_ADDR_MASK_BCM56224_A0r_fields,
   2929         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
   2930         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   2931         -1,
   2932         -1,
   2933     },
   2934 #endif /* chips */
   2935 
   2936 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
   2937     defined(BCM_53570_B0) || defined(BCM_56160_A0)
   2938     { /* SOC_REG_INT_L2_ENTRY_COLLISION_CNTr */
   2939         soc_block_list[5],
   2940         soc_genreg,
   2941         1,
   2942         0,
   2943         0x1e000800,
   2944         0,
   2945         0,
   2946         1,
   2947         soc_IHOST_PTIM_TIMER_COUNTERr_fields,
   2948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2950         -1,
   2951         -1,
   2952     },
   2953 #endif /* chips */
   2954 
   2955 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   2956     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   2957     { /* SOC_REG_INT_L2_ENTRY_CONTROLr */
   2958         soc_block_list[5],
   2959         soc_genreg,
   2960         1,
   2961         0,
   2962         0x6080009,
   2963         0,
   2964         0,
   2965         16,
   2966         soc_L2_ENTRY_CONTROLr_fields,
   2967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2968         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2969         -1,
   2970         -1,
   2971     },
   2972 #endif /* chips */
   2973 
   2974 #if defined(BCM_56850_A0)
   2975     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0r */
   2976         soc_block_list[5],
   2977         soc_genreg,
   2978         1,
   2979         0,
   2980         0x2b000000,
   2981         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2982         0,
   2983         16,
   2984         soc_L2_ENTRY_CONTROL_0r_fields,
   2985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2986         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2987         -1,
   2988         -1,
   2989     },
   2990 #endif /* chips */
   2991 
   2992 #if defined(BCM_56850_A0)
   2993     { /* SOC_REG_INT_L2_ENTRY_CONTROL_1r */
   2994         soc_block_list[5],
   2995         soc_genreg,
   2996         1,
   2997         0,
   2998         0x2b010000,
   2999         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3000         0,
   3001         4,
   3002         soc_L2_ENTRY_CONTROL_1r_fields,
   3003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3004         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3005         -1,
   3006         -1,
   3007     },
   3008 #endif /* chips */
   3009 
   3010 #if defined(BCM_56850_A0)
   3011     { /* SOC_REG_INT_L2_ENTRY_CONTROL_2r */
   3012         soc_block_list[5],
   3013         soc_genreg,
   3014         1,
   3015         0,
   3016         0x2b020000,
   3017         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3018         0,
   3019         6,
   3020         soc_L2_ENTRY_CONTROL_2r_fields,
   3021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3022         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3023         -1,
   3024         -1,
   3025     },
   3026 #endif /* chips */
   3027 
   3028 #if defined(BCM_56850_A0)
   3029     { /* SOC_REG_INT_L2_ENTRY_CONTROL_3r */
   3030         soc_block_list[5],
   3031         soc_genreg,
   3032         1,
   3033         0,
   3034         0x2b030000,
   3035         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3036         0,
   3037         6,
   3038         soc_L2_ENTRY_CONTROL_3r_fields,
   3039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3040         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3041         -1,
   3042         -1,
   3043     },
   3044 #endif /* chips */
   3045 
   3046 #if defined(BCM_56850_A0)
   3047     { /* SOC_REG_INT_L2_ENTRY_CONTROL_4r */
   3048         soc_block_list[5],
   3049         soc_genreg,
   3050         1,
   3051         0,
   3052         0x2b040000,
   3053         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3054         0,
   3055         6,
   3056         soc_L2_ENTRY_CONTROL_4r_fields,
   3057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3058         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3059         -1,
   3060         -1,
   3061     },
   3062 #endif /* chips */
   3063 
   3064 #if defined(BCM_56850_A0)
   3065     { /* SOC_REG_INT_L2_ENTRY_CONTROL_5r */
   3066         soc_block_list[5],
   3067         soc_genreg,
   3068         1,
   3069         0,
   3070         0x2b050000,
   3071         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3072         0,
   3073         2,
   3074         soc_L2_ENTRY_CONTROL_5r_fields,
   3075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3076         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3077         -1,
   3078         -1,
   3079     },
   3080 #endif /* chips */
   3081 
   3082 #if defined(BCM_56850_A0)
   3083     { /* SOC_REG_INT_L2_ENTRY_CONTROL_6r */
   3084         soc_block_list[5],
   3085         soc_genreg,
   3086         1,
   3087         0,
   3088         0x2b060000,
   3089         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3090         0,
   3091         5,
   3092         soc_L2_ENTRY_CONTROL_6r_fields,
   3093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3094         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3095         -1,
   3096         -1,
   3097     },
   3098 #endif /* chips */
   3099 
   3100 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   3101     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   3102     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_BCM56560_A0r */
   3103         soc_block_list[5],
   3104         soc_genreg,
   3105         1,
   3106         0,
   3107         0x3b000000,
   3108         0,
   3109         0,
   3110         1,
   3111         soc_L2_ENTRY_CONTROL_0_BCM56560_A0r_fields,
   3112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3113         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3114         -1,
   3115         -1,
   3116     },
   3117 #endif /* chips */
   3118 
   3119 #if defined(BCM_56860_A0)
   3120     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_BCM56860_A0r */
   3121         soc_block_list[5],
   3122         soc_genreg,
   3123         1,
   3124         0,
   3125         0x3b000000,
   3126         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3127         0,
   3128         1,
   3129         soc_L2_ENTRY_CONTROL_0_BCM56860_A0r_fields,
   3130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3131         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3132         -1,
   3133         -1,
   3134     },
   3135 #endif /* chips */
   3136 
   3137 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3138     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_BCM56960_A0r */
   3139         soc_block_list[5],
   3140         soc_genreg,
   3141         1,
   3142         0,
   3143         0x3b190000,
   3144         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3145         0,
   3146         4,
   3147         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3150         -1,
   3151         -1,
   3152         3,
   3153     },
   3154 #endif /* chips */
   3155 
   3156 #if defined(BCM_56970_A0)
   3157     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_BCM56970_A0r */
   3158         soc_block_list[5],
   3159         soc_genreg,
   3160         1,
   3161         0,
   3162         0x5f180000,
   3163         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3164         0,
   3165         4,
   3166         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3169         -1,
   3170         -1,
   3171         3,
   3172     },
   3173 #endif /* chips */
   3174 
   3175 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3176     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_PIPE0r */
   3177         soc_block_list[5],
   3178         soc_genreg,
   3179         1,
   3180         0,
   3181         0x3b190000,
   3182         0,
   3183         0,
   3184         4,
   3185         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3188         -1,
   3189         -1,
   3190         3,
   3191     },
   3192 #endif /* chips */
   3193 
   3194 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3195     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_PIPE1r */
   3196         soc_block_list[5],
   3197         soc_genreg,
   3198         1,
   3199         0,
   3200         0x3b190000,
   3201         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3202         0,
   3203         4,
   3204         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3206         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3207         -1,
   3208         -1,
   3209         3,
   3210     },
   3211 #endif /* chips */
   3212 
   3213 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3214     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_PIPE2r */
   3215         soc_block_list[5],
   3216         soc_genreg,
   3217         1,
   3218         0,
   3219         0x3b190000,
   3220         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3221         0,
   3222         4,
   3223         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3225         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3226         -1,
   3227         -1,
   3228         3,
   3229     },
   3230 #endif /* chips */
   3231 
   3232 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3233     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_PIPE3r */
   3234         soc_block_list[5],
   3235         soc_genreg,
   3236         1,
   3237         0,
   3238         0x3b190000,
   3239         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3240         0,
   3241         4,
   3242         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3244         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3245         -1,
   3246         -1,
   3247         3,
   3248     },
   3249 #endif /* chips */
   3250 
   3251 #if defined(BCM_56970_A0)
   3252     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_PIPE0_BCM56970_A0r */
   3253         soc_block_list[5],
   3254         soc_genreg,
   3255         1,
   3256         0,
   3257         0x5f180000,
   3258         0,
   3259         0,
   3260         4,
   3261         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3264         -1,
   3265         -1,
   3266         3,
   3267     },
   3268 #endif /* chips */
   3269 
   3270 #if defined(BCM_56970_A0)
   3271     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_PIPE1_BCM56970_A0r */
   3272         soc_block_list[5],
   3273         soc_genreg,
   3274         1,
   3275         0,
   3276         0x5f180000,
   3277         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3278         0,
   3279         4,
   3280         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3282         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3283         -1,
   3284         -1,
   3285         3,
   3286     },
   3287 #endif /* chips */
   3288 
   3289 #if defined(BCM_56970_A0)
   3290     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_PIPE2_BCM56970_A0r */
   3291         soc_block_list[5],
   3292         soc_genreg,
   3293         1,
   3294         0,
   3295         0x5f180000,
   3296         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3297         0,
   3298         4,
   3299         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3302         -1,
   3303         -1,
   3304         3,
   3305     },
   3306 #endif /* chips */
   3307 
   3308 #if defined(BCM_56970_A0)
   3309     { /* SOC_REG_INT_L2_ENTRY_CONTROL_0_PIPE3_BCM56970_A0r */
   3310         soc_block_list[5],
   3311         soc_genreg,
   3312         1,
   3313         0,
   3314         0x5f180000,
   3315         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3316         0,
   3317         4,
   3318         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   3319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3321         -1,
   3322         -1,
   3323         3,
   3324     },
   3325 #endif /* chips */
   3326 
   3327 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   3328     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   3329     { /* SOC_REG_INT_L2_ENTRY_CONTROL_6_BCM56560_A0r */
   3330         soc_block_list[5],
   3331         soc_genreg,
   3332         1,
   3333         0,
   3334         0x3b010000,
   3335         0,
   3336         0,
   3337         5,
   3338         soc_L2_ENTRY_CONTROL_6_BCM56960_A0r_fields,
   3339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3340         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3341         -1,
   3342         -1,
   3343     },
   3344 #endif /* chips */
   3345 
   3346 #if defined(BCM_56860_A0)
   3347     { /* SOC_REG_INT_L2_ENTRY_CONTROL_6_BCM56860_A0r */
   3348         soc_block_list[5],
   3349         soc_genreg,
   3350         1,
   3351         0,
   3352         0x3b010000,
   3353         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3354         0,
   3355         5,
   3356         soc_L2_ENTRY_CONTROL_6r_fields,
   3357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3358         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3359         -1,
   3360         -1,
   3361     },
   3362 #endif /* chips */
   3363 
   3364 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3365     { /* SOC_REG_INT_L2_ENTRY_CONTROL_6_BCM56960_A0r */
   3366         soc_block_list[5],
   3367         soc_genreg,
   3368         1,
   3369         0,
   3370         0x3b1a0000,
   3371         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3372         0,
   3373         5,
   3374         soc_L2_ENTRY_CONTROL_6_BCM56960_A0r_fields,
   3375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3376         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3377         -1,
   3378         -1,
   3379         3,
   3380     },
   3381 #endif /* chips */
   3382 
   3383 #if defined(BCM_56970_A0)
   3384     { /* SOC_REG_INT_L2_ENTRY_CONTROL_6_BCM56970_A0r */
   3385         soc_block_list[5],
   3386         soc_genreg,
   3387         1,
   3388         0,
   3389         0x5f190000,
   3390         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3391         0,
   3392         6,
   3393         soc_L2_ENTRY_CONTROL_6_BCM56970_A0r_fields,
   3394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3395         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3396         -1,
   3397         -1,
   3398         3,
   3399     },
   3400 #endif /* chips */
   3401 
   3402 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3403     { /* SOC_REG_INT_L2_ENTRY_DA_DBGCTRL_0r */
   3404         soc_block_list[5],
   3405         soc_genreg,
   3406         1,
   3407         0,
   3408         0x6080d07,
   3409         0,
   3410         0,
   3411         3,
   3412         soc_L2_ENTRY_DA_DBGCTRL_0r_fields,
   3413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3414         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3415         -1,
   3416         -1,
   3417     },
   3418 #endif /* chips */
   3419 
   3420 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3421     { /* SOC_REG_INT_L2_ENTRY_DA_DBGCTRL_1r */
   3422         soc_block_list[5],
   3423         soc_genreg,
   3424         1,
   3425         0,
   3426         0x6080d08,
   3427         0,
   3428         0,
   3429         3,
   3430         soc_L2_ENTRY_DA_DBGCTRL_1r_fields,
   3431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3433         -1,
   3434         -1,
   3435     },
   3436 #endif /* chips */
   3437 
   3438 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3439     { /* SOC_REG_INT_L2_ENTRY_DA_DBGCTRL_2r */
   3440         soc_block_list[5],
   3441         soc_genreg,
   3442         1,
   3443         0,
   3444         0x6080d09,
   3445         0,
   3446         0,
   3447         3,
   3448         soc_L2_ENTRY_DA_DBGCTRL_2r_fields,
   3449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3450         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3451         -1,
   3452         -1,
   3453     },
   3454 #endif /* chips */
   3455 
   3456 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3457     { /* SOC_REG_INT_L2_ENTRY_DA_DBGCTRL_3r */
   3458         soc_block_list[5],
   3459         soc_genreg,
   3460         1,
   3461         0,
   3462         0x6080d0a,
   3463         0,
   3464         0,
   3465         3,
   3466         soc_L2_ENTRY_DA_DBGCTRL_3r_fields,
   3467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3468         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3469         -1,
   3470         -1,
   3471     },
   3472 #endif /* chips */
   3473 
   3474 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3475     { /* SOC_REG_INT_L2_ENTRY_DA_DBGCTRL_4r */
   3476         soc_block_list[5],
   3477         soc_genreg,
   3478         1,
   3479         0,
   3480         0x6080d0b,
   3481         0,
   3482         0,
   3483         3,
   3484         soc_L2_ENTRY_DA_DBGCTRL_4r_fields,
   3485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3486         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3487         -1,
   3488         -1,
   3489     },
   3490 #endif /* chips */
   3491 
   3492 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3493     { /* SOC_REG_INT_L2_ENTRY_DA_DBGCTRL_5r */
   3494         soc_block_list[5],
   3495         soc_genreg,
   3496         1,
   3497         0,
   3498         0x6080d0c,
   3499         0,
   3500         0,
   3501         1,
   3502         soc_L2_ENTRY_DA_DBGCTRL_5r_fields,
   3503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3505         -1,
   3506         -1,
   3507     },
   3508 #endif /* chips */
   3509 
   3510 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3511     { /* SOC_REG_INT_L2_ENTRY_DA_DBGCTRL_6r */
   3512         soc_block_list[5],
   3513         soc_genreg,
   3514         1,
   3515         0,
   3516         0x6080d0d,
   3517         0,
   3518         0,
   3519         16,
   3520         soc_L2_ENTRY_DA_DBGCTRL_6r_fields,
   3521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3522         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3523         -1,
   3524         -1,
   3525     },
   3526 #endif /* chips */
   3527 
   3528 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3529     { /* SOC_REG_INT_L2_ENTRY_DA_DBGCTRL_7r */
   3530         soc_block_list[5],
   3531         soc_genreg,
   3532         1,
   3533         0,
   3534         0x6080d0e,
   3535         0,
   3536         0,
   3537         16,
   3538         soc_L2_ENTRY_DA_DBGCTRL_7r_fields,
   3539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3540         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3541         -1,
   3542         -1,
   3543     },
   3544 #endif /* chips */
   3545 
   3546 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3547     { /* SOC_REG_INT_L2_ENTRY_DA_DBGCTRL_8r */
   3548         soc_block_list[5],
   3549         soc_genreg,
   3550         1,
   3551         0,
   3552         0x6080d0f,
   3553         0,
   3554         0,
   3555         2,
   3556         soc_L2_ENTRY_DA_DBGCTRL_8r_fields,
   3557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3559         -1,
   3560         -1,
   3561     },
   3562 #endif /* chips */
   3563 
   3564 #if defined(BCM_56800_A0)
   3565     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL0r */
   3566         soc_block_list[5],
   3567         soc_genreg,
   3568         1,
   3569         0,
   3570         0x6080209,
   3571         0,
   3572         0,
   3573         4,
   3574         soc_L2_ENTRY_DBGCTRL0r_fields,
   3575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3577         -1,
   3578         -1,
   3579     },
   3580 #endif /* chips */
   3581 
   3582 #if defined(BCM_56800_A0)
   3583     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL1r */
   3584         soc_block_list[5],
   3585         soc_genreg,
   3586         1,
   3587         0,
   3588         0x608020a,
   3589         0,
   3590         0,
   3591         4,
   3592         soc_L2_ENTRY_DBGCTRL1r_fields,
   3593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3594         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3595         -1,
   3596         -1,
   3597     },
   3598 #endif /* chips */
   3599 
   3600 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   3601     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL0_BCM56820_A0r */
   3602         soc_block_list[5],
   3603         soc_genreg,
   3604         1,
   3605         0,
   3606         0x6080209,
   3607         0,
   3608         0,
   3609         2,
   3610         soc_L2_ENTRY_DBGCTRL0_BCM56820_A0r_fields,
   3611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3613         -1,
   3614         -1,
   3615     },
   3616 #endif /* chips */
   3617 
   3618 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   3619     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   3620     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0r */
   3621         soc_block_list[5],
   3622         soc_genreg,
   3623         1,
   3624         0,
   3625         0x7080131,
   3626         0,
   3627         0,
   3628         4,
   3629         soc_L2_ENTRY_DBGCTRL0r_fields,
   3630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3632         -1,
   3633         -1,
   3634     },
   3635 #endif /* chips */
   3636 
   3637 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   3638     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   3639     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1r */
   3640         soc_block_list[5],
   3641         soc_genreg,
   3642         1,
   3643         0,
   3644         0x7080132,
   3645         0,
   3646         0,
   3647         4,
   3648         soc_L2_ENTRY_DBGCTRL1r_fields,
   3649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3650         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3651         -1,
   3652         -1,
   3653     },
   3654 #endif /* chips */
   3655 
   3656 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3657     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3658     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3659     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_2r */
   3660         soc_block_list[5],
   3661         soc_genreg,
   3662         1,
   3663         0,
   3664         0x7080181,
   3665         0,
   3666         0,
   3667         4,
   3668         soc_L2_ENTRY_DBGCTRL_2r_fields,
   3669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3670         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3671         -1,
   3672         -1,
   3673     },
   3674 #endif /* chips */
   3675 
   3676 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3677     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3678     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3679     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_3r */
   3680         soc_block_list[5],
   3681         soc_genreg,
   3682         1,
   3683         0,
   3684         0x7080182,
   3685         0,
   3686         0,
   3687         4,
   3688         soc_L2_ENTRY_DBGCTRL_3r_fields,
   3689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3690         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3691         -1,
   3692         -1,
   3693     },
   3694 #endif /* chips */
   3695 
   3696 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3697     defined(BCM_56160_A0)
   3698     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_4r */
   3699         soc_block_list[5],
   3700         soc_genreg,
   3701         1,
   3702         0,
   3703         0x1e010900,
   3704         0,
   3705         0,
   3706         1,
   3707         soc_L2_ENTRY_DBGCTRL_4r_fields,
   3708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3710         -1,
   3711         -1,
   3712     },
   3713 #endif /* chips */
   3714 
   3715 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3716     defined(BCM_56160_A0)
   3717     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_5r */
   3718         soc_block_list[5],
   3719         soc_genreg,
   3720         1,
   3721         0,
   3722         0x1e010a00,
   3723         0,
   3724         0,
   3725         1,
   3726         soc_L2_ENTRY_DBGCTRL_5r_fields,
   3727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3728         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3729         -1,
   3730         -1,
   3731     },
   3732 #endif /* chips */
   3733 
   3734 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3735     defined(BCM_56160_A0)
   3736     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_6r */
   3737         soc_block_list[5],
   3738         soc_genreg,
   3739         1,
   3740         0,
   3741         0x1e010b00,
   3742         0,
   3743         0,
   3744         1,
   3745         soc_L2_ENTRY_DBGCTRL_6r_fields,
   3746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3747         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3748         -1,
   3749         -1,
   3750     },
   3751 #endif /* chips */
   3752 
   3753 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3754     defined(BCM_56160_A0)
   3755     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_7r */
   3756         soc_block_list[5],
   3757         soc_genreg,
   3758         1,
   3759         0,
   3760         0x1e010c00,
   3761         0,
   3762         0,
   3763         1,
   3764         soc_L2_ENTRY_DBGCTRL_7r_fields,
   3765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3766         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3767         -1,
   3768         -1,
   3769     },
   3770 #endif /* chips */
   3771 
   3772 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3773     defined(BCM_56160_A0)
   3774     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM53400_A0r */
   3775         soc_block_list[5],
   3776         soc_genreg,
   3777         1,
   3778         0,
   3779         0x1e010500,
   3780         0,
   3781         0,
   3782         1,
   3783         soc_L2_ENTRY_DBGCTRL_0_BCM53400_A0r_fields,
   3784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3785         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3786         -1,
   3787         -1,
   3788     },
   3789 #endif /* chips */
   3790 
   3791 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   3792     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM53570_A0r */
   3793         soc_block_list[5],
   3794         soc_genreg,
   3795         1,
   3796         0,
   3797         0x1e010500,
   3798         0,
   3799         0,
   3800         1,
   3801         soc_L2_ENTRY_DBGCTRL_0_BCM53570_A0r_fields,
   3802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3803         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3804         -1,
   3805         -1,
   3806     },
   3807 #endif /* chips */
   3808 
   3809 #if defined(BCM_56142_A0)
   3810     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM56142_A0r */
   3811         soc_block_list[5],
   3812         soc_genreg,
   3813         1,
   3814         0,
   3815         0x7080139,
   3816         0,
   3817         0,
   3818         4,
   3819         soc_L2_ENTRY_DBGCTRL0r_fields,
   3820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3821         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3822         -1,
   3823         -1,
   3824     },
   3825 #endif /* chips */
   3826 
   3827 #if defined(BCM_56150_A0)
   3828     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM56150_A0r */
   3829         soc_block_list[5],
   3830         soc_genreg,
   3831         1,
   3832         0,
   3833         0x1e010500,
   3834         0,
   3835         0,
   3836         3,
   3837         soc_MPLS_ENTRY_DBGCTRL_0r_fields,
   3838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3840         -1,
   3841         -1,
   3842     },
   3843 #endif /* chips */
   3844 
   3845 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3846     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM56260_A0r */
   3847         soc_block_list[5],
   3848         soc_genreg,
   3849         1,
   3850         0,
   3851         0x1a010500,
   3852         SOC_REG_FLAG_64_BITS,
   3853         0,
   3854         3,
   3855         soc_L2_ENTRY_DBGCTRL_0_BCM56260_A0r_fields,
   3856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3857         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3858         -1,
   3859         -1,
   3860     },
   3861 #endif /* chips */
   3862 
   3863 #if defined(BCM_56270_A0)
   3864     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM56270_A0r */
   3865         soc_block_list[5],
   3866         soc_genreg,
   3867         1,
   3868         0,
   3869         0x1a010500,
   3870         SOC_REG_FLAG_64_BITS,
   3871         0,
   3872         3,
   3873         soc_L2_ENTRY_DBGCTRL_0_BCM56270_A0r_fields,
   3874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3875         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3876         -1,
   3877         -1,
   3878     },
   3879 #endif /* chips */
   3880 
   3881 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   3882     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM56334_A0r */
   3883         soc_block_list[5],
   3884         soc_genreg,
   3885         1,
   3886         0,
   3887         0x7080151,
   3888         0,
   3889         0,
   3890         4,
   3891         soc_L2_ENTRY_DBGCTRL0r_fields,
   3892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3893         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3894         -1,
   3895         -1,
   3896     },
   3897 #endif /* chips */
   3898 
   3899 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3900     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM56440_A0r */
   3901         soc_block_list[5],
   3902         soc_genreg,
   3903         1,
   3904         0,
   3905         0x6080305,
   3906         0,
   3907         0,
   3908         3,
   3909         soc_L2_ENTRY_DA_DBGCTRL_0r_fields,
   3910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3912         -1,
   3913         -1,
   3914     },
   3915 #endif /* chips */
   3916 
   3917 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3918     defined(BCM_56450_B1)
   3919     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM56450_A0r */
   3920         soc_block_list[5],
   3921         soc_genreg,
   3922         1,
   3923         0,
   3924         0x1a010500,
   3925         SOC_REG_FLAG_64_BITS,
   3926         0,
   3927         6,
   3928         soc_L2_ENTRY_DBGCTRL_0_BCM56450_A0r_fields,
   3929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3930         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3931         -1,
   3932         -1,
   3933     },
   3934 #endif /* chips */
   3935 
   3936 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3937     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3938     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3939     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_0_BCM56634_A0r */
   3940         soc_block_list[5],
   3941         soc_genreg,
   3942         1,
   3943         0,
   3944         0x708017f,
   3945         0,
   3946         0,
   3947         4,
   3948         soc_L2_ENTRY_DBGCTRL_0r_fields,
   3949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3950         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3951         -1,
   3952         -1,
   3953     },
   3954 #endif /* chips */
   3955 
   3956 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3957     defined(BCM_56160_A0)
   3958     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM53400_A0r */
   3959         soc_block_list[5],
   3960         soc_genreg,
   3961         1,
   3962         0,
   3963         0x1e010600,
   3964         0,
   3965         0,
   3966         1,
   3967         soc_L2_ENTRY_DBGCTRL_1_BCM53400_A0r_fields,
   3968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3970         -1,
   3971         -1,
   3972     },
   3973 #endif /* chips */
   3974 
   3975 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   3976     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM53570_A0r */
   3977         soc_block_list[5],
   3978         soc_genreg,
   3979         1,
   3980         0,
   3981         0x1e010600,
   3982         0,
   3983         0,
   3984         1,
   3985         soc_L2_ENTRY_DBGCTRL_1_BCM53570_A0r_fields,
   3986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3987         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3988         -1,
   3989         -1,
   3990     },
   3991 #endif /* chips */
   3992 
   3993 #if defined(BCM_56142_A0)
   3994     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM56142_A0r */
   3995         soc_block_list[5],
   3996         soc_genreg,
   3997         1,
   3998         0,
   3999         0x708013a,
   4000         0,
   4001         0,
   4002         4,
   4003         soc_L2_ENTRY_DBGCTRL1r_fields,
   4004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4006         -1,
   4007         -1,
   4008     },
   4009 #endif /* chips */
   4010 
   4011 #if defined(BCM_56150_A0)
   4012     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM56150_A0r */
   4013         soc_block_list[5],
   4014         soc_genreg,
   4015         1,
   4016         0,
   4017         0x1e010600,
   4018         0,
   4019         0,
   4020         3,
   4021         soc_MPLS_ENTRY_DBGCTRL_1r_fields,
   4022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4023         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4024         -1,
   4025         -1,
   4026     },
   4027 #endif /* chips */
   4028 
   4029 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4030     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM56260_A0r */
   4031         soc_block_list[5],
   4032         soc_genreg,
   4033         1,
   4034         0,
   4035         0x1a010600,
   4036         SOC_REG_FLAG_64_BITS,
   4037         0,
   4038         3,
   4039         soc_L2_ENTRY_DBGCTRL_1_BCM56260_A0r_fields,
   4040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4041         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4042         -1,
   4043         -1,
   4044     },
   4045 #endif /* chips */
   4046 
   4047 #if defined(BCM_56270_A0)
   4048     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM56270_A0r */
   4049         soc_block_list[5],
   4050         soc_genreg,
   4051         1,
   4052         0,
   4053         0x1a010600,
   4054         SOC_REG_FLAG_64_BITS,
   4055         0,
   4056         3,
   4057         soc_L2_ENTRY_DBGCTRL_1_BCM56270_A0r_fields,
   4058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4059         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4060         -1,
   4061         -1,
   4062     },
   4063 #endif /* chips */
   4064 
   4065 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   4066     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM56334_A0r */
   4067         soc_block_list[5],
   4068         soc_genreg,
   4069         1,
   4070         0,
   4071         0x7080152,
   4072         0,
   4073         0,
   4074         4,
   4075         soc_L2_ENTRY_DBGCTRL1r_fields,
   4076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4077         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4078         -1,
   4079         -1,
   4080     },
   4081 #endif /* chips */
   4082 
   4083 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4084     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM56440_A0r */
   4085         soc_block_list[5],
   4086         soc_genreg,
   4087         1,
   4088         0,
   4089         0x6080306,
   4090         0,
   4091         0,
   4092         3,
   4093         soc_L2_ENTRY_DA_DBGCTRL_1r_fields,
   4094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4095         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4096         -1,
   4097         -1,
   4098     },
   4099 #endif /* chips */
   4100 
   4101 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4102     defined(BCM_56450_B1)
   4103     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM56450_A0r */
   4104         soc_block_list[5],
   4105         soc_genreg,
   4106         1,
   4107         0,
   4108         0x1a010600,
   4109         SOC_REG_FLAG_64_BITS,
   4110         0,
   4111         6,
   4112         soc_L2_ENTRY_DBGCTRL_1_BCM56450_A0r_fields,
   4113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4114         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4115         -1,
   4116         -1,
   4117     },
   4118 #endif /* chips */
   4119 
   4120 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   4121     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   4122     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   4123     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_1_BCM56634_A0r */
   4124         soc_block_list[5],
   4125         soc_genreg,
   4126         1,
   4127         0,
   4128         0x7080180,
   4129         0,
   4130         0,
   4131         4,
   4132         soc_L2_ENTRY_DBGCTRL_1r_fields,
   4133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4134         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4135         -1,
   4136         -1,
   4137     },
   4138 #endif /* chips */
   4139 
   4140 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4141     defined(BCM_56160_A0)
   4142     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_2_BCM53400_A0r */
   4143         soc_block_list[5],
   4144         soc_genreg,
   4145         1,
   4146         0,
   4147         0x1e010700,
   4148         0,
   4149         0,
   4150         1,
   4151         soc_L2_ENTRY_DBGCTRL_2_BCM53400_A0r_fields,
   4152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4153         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4154         -1,
   4155         -1,
   4156     },
   4157 #endif /* chips */
   4158 
   4159 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4160     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_2_BCM53570_A0r */
   4161         soc_block_list[5],
   4162         soc_genreg,
   4163         1,
   4164         0,
   4165         0x1e010700,
   4166         0,
   4167         0,
   4168         1,
   4169         soc_L2_ENTRY_DBGCTRL_2_BCM53570_A0r_fields,
   4170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4171         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4172         -1,
   4173         -1,
   4174     },
   4175 #endif /* chips */
   4176 
   4177 #if defined(BCM_56150_A0)
   4178     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_2_BCM56150_A0r */
   4179         soc_block_list[5],
   4180         soc_genreg,
   4181         1,
   4182         0,
   4183         0x1e010700,
   4184         0,
   4185         0,
   4186         2,
   4187         soc_MPLS_ENTRY_DBGCTRL_2_BCM56850_A0r_fields,
   4188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4189         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4190         -1,
   4191         -1,
   4192     },
   4193 #endif /* chips */
   4194 
   4195 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4196     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_2_BCM56260_A0r */
   4197         soc_block_list[5],
   4198         soc_genreg,
   4199         1,
   4200         0,
   4201         0x1a010700,
   4202         0,
   4203         0,
   4204         2,
   4205         soc_L2_ENTRY_DBGCTRL_2_BCM56260_A0r_fields,
   4206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4207         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4208         -1,
   4209         -1,
   4210     },
   4211 #endif /* chips */
   4212 
   4213 #if defined(BCM_56270_A0)
   4214     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_2_BCM56270_A0r */
   4215         soc_block_list[5],
   4216         soc_genreg,
   4217         1,
   4218         0,
   4219         0x1a010700,
   4220         SOC_REG_FLAG_64_BITS,
   4221         0,
   4222         2,
   4223         soc_L2_ENTRY_DBGCTRL_2_BCM56270_A0r_fields,
   4224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4225         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4226         -1,
   4227         -1,
   4228     },
   4229 #endif /* chips */
   4230 
   4231 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4232     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_2_BCM56440_A0r */
   4233         soc_block_list[5],
   4234         soc_genreg,
   4235         1,
   4236         0,
   4237         0x6080307,
   4238         0,
   4239         0,
   4240         2,
   4241         soc_MPLS_ENTRY_DBGCTRL_2r_fields,
   4242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4243         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4244         -1,
   4245         -1,
   4246     },
   4247 #endif /* chips */
   4248 
   4249 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4250     defined(BCM_56450_B1)
   4251     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_2_BCM56450_A0r */
   4252         soc_block_list[5],
   4253         soc_genreg,
   4254         1,
   4255         0,
   4256         0x1a010700,
   4257         SOC_REG_FLAG_64_BITS,
   4258         0,
   4259         4,
   4260         soc_L2_ENTRY_DBGCTRL_2_BCM56450_A0r_fields,
   4261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4262         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4263         -1,
   4264         -1,
   4265     },
   4266 #endif /* chips */
   4267 
   4268 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4269     defined(BCM_56160_A0)
   4270     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_3_BCM53400_A0r */
   4271         soc_block_list[5],
   4272         soc_genreg,
   4273         1,
   4274         0,
   4275         0x1e010800,
   4276         0,
   4277         0,
   4278         1,
   4279         soc_L2_ENTRY_DBGCTRL_3_BCM53400_A0r_fields,
   4280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4281         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4282         -1,
   4283         -1,
   4284     },
   4285 #endif /* chips */
   4286 
   4287 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4288     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_3_BCM53570_A0r */
   4289         soc_block_list[5],
   4290         soc_genreg,
   4291         1,
   4292         0,
   4293         0x1e010800,
   4294         0,
   4295         0,
   4296         1,
   4297         soc_L2_ENTRY_DBGCTRL_3_BCM53570_A0r_fields,
   4298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4300         -1,
   4301         -1,
   4302     },
   4303 #endif /* chips */
   4304 
   4305 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4306     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_4_BCM53570_A0r */
   4307         soc_block_list[5],
   4308         soc_genreg,
   4309         1,
   4310         0,
   4311         0x1e010900,
   4312         0,
   4313         0,
   4314         1,
   4315         soc_L2_ENTRY_DBGCTRL_4_BCM53570_A0r_fields,
   4316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4317         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4318         -1,
   4319         -1,
   4320     },
   4321 #endif /* chips */
   4322 
   4323 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4324     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_5_BCM53570_A0r */
   4325         soc_block_list[5],
   4326         soc_genreg,
   4327         1,
   4328         0,
   4329         0x1e010a00,
   4330         0,
   4331         0,
   4332         1,
   4333         soc_L2_ENTRY_DBGCTRL_5_BCM53570_A0r_fields,
   4334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4335         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4336         -1,
   4337         -1,
   4338     },
   4339 #endif /* chips */
   4340 
   4341 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4342     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_6_BCM53570_A0r */
   4343         soc_block_list[5],
   4344         soc_genreg,
   4345         1,
   4346         0,
   4347         0x1e010b00,
   4348         0,
   4349         0,
   4350         1,
   4351         soc_L2_ENTRY_DBGCTRL_6_BCM53570_A0r_fields,
   4352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4353         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4354         -1,
   4355         -1,
   4356     },
   4357 #endif /* chips */
   4358 
   4359 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4360     { /* SOC_REG_INT_L2_ENTRY_DBGCTRL_7_BCM53570_A0r */
   4361         soc_block_list[5],
   4362         soc_genreg,
   4363         1,
   4364         0,
   4365         0x1e010c00,
   4366         0,
   4367         0,
   4368         1,
   4369         soc_L2_ENTRY_DBGCTRL_7_BCM53570_A0r_fields,
   4370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4372         -1,
   4373         -1,
   4374     },
   4375 #endif /* chips */
   4376 
   4377 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   4378     defined(BCM_56270_A0)
   4379     { /* SOC_REG_INT_L2_ENTRY_ECC_CONTROLr */
   4380         soc_block_list[5],
   4381         soc_genreg,
   4382         1,
   4383         0,
   4384         0x1a010f00,
   4385         0,
   4386         0,
   4387         2,
   4388         soc_ING_DVP_TABLE_ECCP_CONTROLr_fields,
   4389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4390         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4391         -1,
   4392         -1,
   4393     },
   4394 #endif /* chips */
   4395 
   4396 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   4397     { /* SOC_REG_INT_L2_ENTRY_FLEX_COUNTER_STRENGTHr */
   4398         soc_block_list[5],
   4399         soc_genreg,
   4400         1,
   4401         0,
   4402         0x1a001c00,
   4403         0,
   4404         0,
   4405         1,
   4406         soc_L2_ENTRY_FLEX_COUNTER_STRENGTHr_fields,
   4407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4408         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4409         -1,
   4410         -1,
   4411     },
   4412 #endif /* chips */
   4413 
   4414 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
   4415     defined(BCM_53570_B0) || defined(BCM_56160_A0)
   4416     { /* SOC_REG_INT_L2_ENTRY_LEARNED_CNTr */
   4417         soc_block_list[5],
   4418         soc_genreg,
   4419         1,
   4420         0,
   4421         0x1e000900,
   4422         0,
   4423         0,
   4424         1,
   4425         soc_IHOST_PTIM_TIMER_COUNTERr_fields,
   4426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4428         -1,
   4429         -1,
   4430     },
   4431 #endif /* chips */
   4432 
   4433 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4434     defined(BCM_56450_B1)
   4435     { /* SOC_REG_INT_L2_ENTRY_LP_CONTROLr */
   4436         soc_block_list[5],
   4437         soc_genreg,
   4438         1,
   4439         0,
   4440         0x1a010800,
   4441         0,
   4442         0,
   4443         8,
   4444         soc_L2_ENTRY_LP_CONTROLr_fields,
   4445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4446         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4447         -1,
   4448         -1,
   4449     },
   4450 #endif /* chips */
   4451 
   4452 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4453     { /* SOC_REG_INT_L2_ENTRY_LP_CONTROL_BCM56260_A0r */
   4454         soc_block_list[5],
   4455         soc_genreg,
   4456         1,
   4457         0,
   4458         0x1a010800,
   4459         0,
   4460         0,
   4461         8,
   4462         soc_L2_ENTRY_LP_CONTROL_BCM56260_A0r_fields,
   4463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4464         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4465         -1,
   4466         -1,
   4467     },
   4468 #endif /* chips */
   4469 
   4470 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
   4471     defined(BCM_53570_B0) || defined(BCM_56160_A0)
   4472     { /* SOC_REG_INT_L2_ENTRY_NO_LEARN_STATUSr */
   4473         soc_block_list[5],
   4474         soc_genreg,
   4475         1,
   4476         0,
   4477         0x1e011b00,
   4478         0,
   4479         0,
   4480         1,
   4481         soc_L2_ENTRY_NO_LEARN_STATUSr_fields,
   4482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4483         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4484         -1,
   4485         -1,
   4486     },
   4487 #endif /* chips */
   4488 
   4489 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
   4490     defined(BCM_53570_B0) || defined(BCM_56160_A0)
   4491     { /* SOC_REG_INT_L2_ENTRY_OVF_NO_LEARN_STATUSr */
   4492         soc_block_list[5],
   4493         soc_genreg,
   4494         1,
   4495         0,
   4496         0x1e011c00,
   4497         0,
   4498         0,
   4499         1,
   4500         soc_L2_ENTRY_NO_LEARN_STATUSr_fields,
   4501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4502         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4503         -1,
   4504         -1,
   4505     },
   4506 #endif /* chips */
   4507 
   4508 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
   4509     defined(BCM_56514_A0)
   4510     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROLr */
   4511         soc_block_list[5],
   4512         soc_genreg,
   4513         1,
   4514         0,
   4515         0x608000c,
   4516         0,
   4517         0,
   4518         2,
   4519         soc_L2_ENTRY_PARITY_CONTROLr_fields,
   4520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4521         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4522         -1,
   4523         -1,
   4524     },
   4525 #endif /* chips */
   4526 
   4527 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4528     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   4529     defined(BCM_56160_A0)
   4530     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM53400_A0r */
   4531         soc_block_list[5],
   4532         soc_genreg,
   4533         1,
   4534         0,
   4535         0x1e011100,
   4536         0,
   4537         0,
   4538         1,
   4539         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
   4540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4541         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4542         -1,
   4543         -1,
   4544     },
   4545 #endif /* chips */
   4546 
   4547 #if defined(BCM_56142_A0)
   4548     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56142_A0r */
   4549         soc_block_list[5],
   4550         soc_genreg,
   4551         1,
   4552         0,
   4553         0x708013d,
   4554         0,
   4555         0,
   4556         1,
   4557         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   4558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4559         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4560         -1,
   4561         -1,
   4562     },
   4563 #endif /* chips */
   4564 
   4565 #if defined(BCM_56150_A0)
   4566     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56150_A0r */
   4567         soc_block_list[5],
   4568         soc_genreg,
   4569         1,
   4570         0,
   4571         0x1e010c00,
   4572         0,
   4573         0,
   4574         1,
   4575         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
   4576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4577         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4578         -1,
   4579         -1,
   4580     },
   4581 #endif /* chips */
   4582 
   4583 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   4584     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   4585     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56224_A0r */
   4586         soc_block_list[5],
   4587         soc_genreg,
   4588         1,
   4589         0,
   4590         0x6080007,
   4591         0,
   4592         0,
   4593         2,
   4594         soc_L2_ENTRY_PARITY_CONTROLr_fields,
   4595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4596         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4597         -1,
   4598         -1,
   4599     },
   4600 #endif /* chips */
   4601 
   4602 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   4603     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56334_A0r */
   4604         soc_block_list[5],
   4605         soc_genreg,
   4606         1,
   4607         0,
   4608         0x7080155,
   4609         0,
   4610         0,
   4611         1,
   4612         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   4613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4614         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4615         -1,
   4616         -1,
   4617     },
   4618 #endif /* chips */
   4619 
   4620 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4621     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56440_A0r */
   4622         soc_block_list[5],
   4623         soc_genreg,
   4624         1,
   4625         0,
   4626         0x608030c,
   4627         0,
   4628         0,
   4629         1,
   4630         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   4631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4632         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4633         -1,
   4634         -1,
   4635     },
   4636 #endif /* chips */
   4637 
   4638 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4639     defined(BCM_56450_B1)
   4640     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56450_A0r */
   4641         soc_block_list[5],
   4642         soc_genreg,
   4643         1,
   4644         0,
   4645         0x1a010d00,
   4646         0,
   4647         0,
   4648         1,
   4649         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
   4650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4651         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4652         -1,
   4653         -1,
   4654     },
   4655 #endif /* chips */
   4656 
   4657 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   4658     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56560_A0r */
   4659         soc_block_list[5],
   4660         soc_genreg,
   4661         1,
   4662         0,
   4663         0x1b0c0000,
   4664         0,
   4665         0,
   4666         12,
   4667         soc_L2_ENTRY_PARITY_CONTROL_BCM56560_A0r_fields,
   4668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4670         -1,
   4671         -1,
   4672     },
   4673 #endif /* chips */
   4674 
   4675 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   4676     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   4677     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56624_A0r */
   4678         soc_block_list[5],
   4679         soc_genreg,
   4680         1,
   4681         0,
   4682         0x7080135,
   4683         0,
   4684         0,
   4685         1,
   4686         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   4687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4688         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4689         -1,
   4690         -1,
   4691     },
   4692 #endif /* chips */
   4693 
   4694 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   4695     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   4696     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   4697     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56634_A0r */
   4698         soc_block_list[5],
   4699         soc_genreg,
   4700         1,
   4701         0,
   4702         0x7080185,
   4703         0,
   4704         0,
   4705         1,
   4706         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   4707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4708         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4709         -1,
   4710         -1,
   4711     },
   4712 #endif /* chips */
   4713 
   4714 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   4715     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56670_A0r */
   4716         soc_block_list[5],
   4717         soc_genreg,
   4718         1,
   4719         0,
   4720         0x1b0d0000,
   4721         0,
   4722         0,
   4723         12,
   4724         soc_L2_ENTRY_PARITY_CONTROL_BCM56670_A0r_fields,
   4725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4726         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4727         -1,
   4728         -1,
   4729     },
   4730 #endif /* chips */
   4731 
   4732 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   4733     defined(BCM_56820_A0)
   4734     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56800_A0r */
   4735         soc_block_list[5],
   4736         soc_genreg,
   4737         1,
   4738         0,
   4739         0x608020d,
   4740         0,
   4741         0,
   4742         2,
   4743         soc_L2_ENTRY_PARITY_CONTROLr_fields,
   4744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4745         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4746         -1,
   4747         -1,
   4748     },
   4749 #endif /* chips */
   4750 
   4751 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   4752     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56840_A0r */
   4753         soc_block_list[5],
   4754         soc_genreg,
   4755         1,
   4756         0,
   4757         0x6080d1e,
   4758         0,
   4759         0,
   4760         1,
   4761         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
   4762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4764         -1,
   4765         -1,
   4766     },
   4767 #endif /* chips */
   4768 
   4769 #if defined(BCM_56850_A0)
   4770     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56850_A0r */
   4771         soc_block_list[5],
   4772         soc_genreg,
   4773         1,
   4774         0,
   4775         0x1b0a0000,
   4776         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4777         0,
   4778         8,
   4779         soc_L2_ENTRY_PARITY_CONTROL_BCM56850_A0r_fields,
   4780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4782         -1,
   4783         -1,
   4784     },
   4785 #endif /* chips */
   4786 
   4787 #if defined(BCM_56860_A0)
   4788     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56860_A0r */
   4789         soc_block_list[5],
   4790         soc_genreg,
   4791         1,
   4792         0,
   4793         0x1b0c0000,
   4794         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4795         0,
   4796         10,
   4797         soc_L2_ENTRY_PARITY_CONTROL_BCM56860_A0r_fields,
   4798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4800         -1,
   4801         -1,
   4802     },
   4803 #endif /* chips */
   4804 
   4805 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   4806     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56960_A0r */
   4807         soc_block_list[5],
   4808         soc_genreg,
   4809         1,
   4810         0,
   4811         0x3b140000,
   4812         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4813         0,
   4814         4,
   4815         soc_L2_ENTRY_PARITY_CONTROL_BCM56960_A0r_fields,
   4816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4818         -1,
   4819         -1,
   4820         3,
   4821     },
   4822 #endif /* chips */
   4823 
   4824 #if defined(BCM_56970_A0)
   4825     { /* SOC_REG_INT_L2_ENTRY_PARITY_CONTROL_BCM56970_A0r */
   4826         soc_block_list[5],
   4827         soc_genreg,
   4828         1,
   4829         0,
   4830         0x5f130000,
   4831         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4832         0,
   4833         4,
   4834         soc_L2_ENTRY_PARITY_CONTROL_BCM56960_A0r_fields,
   4835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4836         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4837         -1,
   4838         -1,
   4839         3,
   4840     },
   4841 #endif /* chips */
   4842 
   4843 #if defined(BCM_56504_B0)
   4844     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUSr */
   4845         soc_block_list[5],
   4846         soc_genreg,
   4847         1,
   4848         0,
   4849         0x608000d,
   4850         SOC_REG_FLAG_RO,
   4851         0,
   4852         3,
   4853         soc_L2_ENTRY_PARITY_STATUSr_fields,
   4854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4855         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   4856         -1,
   4857         -1,
   4858     },
   4859 #endif /* chips */
   4860 
   4861 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   4862     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   4863     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_0r */
   4864         soc_block_list[5],
   4865         soc_genreg,
   4866         1,
   4867         0,
   4868         0x7080136,
   4869         0,
   4870         0,
   4871         3,
   4872         soc_L2_ENTRY_PARITY_STATUS_0r_fields,
   4873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4874         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   4875         -1,
   4876         -1,
   4877     },
   4878 #endif /* chips */
   4879 
   4880 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   4881     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   4882     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_1r */
   4883         soc_block_list[5],
   4884         soc_genreg,
   4885         1,
   4886         0,
   4887         0x7080137,
   4888         0,
   4889         0,
   4890         3,
   4891         soc_L2_ENTRY_PARITY_STATUS_1r_fields,
   4892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4893         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   4894         -1,
   4895         -1,
   4896     },
   4897 #endif /* chips */
   4898 
   4899 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4900     defined(BCM_56160_A0)
   4901     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_0_BCM53400_A0r */
   4902         soc_block_list[5],
   4903         soc_genreg,
   4904         1,
   4905         0,
   4906         0x1e011200,
   4907         0,
   4908         0,
   4909         3,
   4910         soc_L2_ENTRY_PARITY_STATUS_0_BCM53400_A0r_fields,
   4911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4912         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   4913         -1,
   4914         -1,
   4915     },
   4916 #endif /* chips */
   4917 
   4918 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4919     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_0_BCM53570_A0r */
   4920         soc_block_list[5],
   4921         soc_genreg,
   4922         1,
   4923         0,
   4924         0x1e011200,
   4925         0,
   4926         0,
   4927         4,
   4928         soc_L2_ENTRY_PARITY_STATUS_0_BCM53570_A0r_fields,
   4929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4930         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   4931         -1,
   4932         -1,
   4933     },
   4934 #endif /* chips */
   4935 
   4936 #if defined(BCM_56142_A0)
   4937     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_0_BCM56142_A0r */
   4938         soc_block_list[5],
   4939         soc_genreg,
   4940         1,
   4941         0,
   4942         0x708013e,
   4943         0,
   4944         0,
   4945         3,
   4946         soc_L2_ENTRY_PARITY_STATUS_0_BCM56142_A0r_fields,
   4947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4948         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   4949         -1,
   4950         -1,
   4951     },
   4952 #endif /* chips */
   4953 
   4954 #if defined(BCM_56150_A0)
   4955     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_0_BCM56150_A0r */
   4956         soc_block_list[5],
   4957         soc_genreg,
   4958         1,
   4959         0,
   4960         0x1e010d00,
   4961         0,
   4962         0,
   4963         3,
   4964         soc_L2_ENTRY_PARITY_STATUS_0_BCM56150_A0r_fields,
   4965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4966         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   4967         -1,
   4968         -1,
   4969     },
   4970 #endif /* chips */
   4971 
   4972 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   4973     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_0_BCM56334_A0r */
   4974         soc_block_list[5],
   4975         soc_genreg,
   4976         1,
   4977         0,
   4978         0x7080156,
   4979         0,
   4980         0,
   4981         3,
   4982         soc_L2_ENTRY_PARITY_STATUS_0r_fields,
   4983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4984         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   4985         -1,
   4986         -1,
   4987     },
   4988 #endif /* chips */
   4989 
   4990 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4991     defined(BCM_56160_A0)
   4992     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_1_BCM53400_A0r */
   4993         soc_block_list[5],
   4994         soc_genreg,
   4995         1,
   4996         0,
   4997         0x1e011300,
   4998         0,
   4999         0,
   5000         3,
   5001         soc_L2_ENTRY_PARITY_STATUS_1_BCM53400_A0r_fields,
   5002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5003         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5004         -1,
   5005         -1,
   5006     },
   5007 #endif /* chips */
   5008 
   5009 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5010     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_1_BCM53570_A0r */
   5011         soc_block_list[5],
   5012         soc_genreg,
   5013         1,
   5014         0,
   5015         0x1e011300,
   5016         0,
   5017         0,
   5018         4,
   5019         soc_L2_ENTRY_PARITY_STATUS_1_BCM53570_A0r_fields,
   5020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5021         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   5022         -1,
   5023         -1,
   5024     },
   5025 #endif /* chips */
   5026 
   5027 #if defined(BCM_56142_A0)
   5028     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_1_BCM56142_A0r */
   5029         soc_block_list[5],
   5030         soc_genreg,
   5031         1,
   5032         0,
   5033         0x708013f,
   5034         0,
   5035         0,
   5036         3,
   5037         soc_L2_ENTRY_PARITY_STATUS_1_BCM56142_A0r_fields,
   5038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5039         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5040         -1,
   5041         -1,
   5042     },
   5043 #endif /* chips */
   5044 
   5045 #if defined(BCM_56150_A0)
   5046     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_1_BCM56150_A0r */
   5047         soc_block_list[5],
   5048         soc_genreg,
   5049         1,
   5050         0,
   5051         0x1e010e00,
   5052         0,
   5053         0,
   5054         3,
   5055         soc_L2_ENTRY_PARITY_STATUS_1_BCM56150_A0r_fields,
   5056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5057         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5058         -1,
   5059         -1,
   5060     },
   5061 #endif /* chips */
   5062 
   5063 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   5064     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_1_BCM56334_A0r */
   5065         soc_block_list[5],
   5066         soc_genreg,
   5067         1,
   5068         0,
   5069         0x7080157,
   5070         0,
   5071         0,
   5072         3,
   5073         soc_L2_ENTRY_PARITY_STATUS_1r_fields,
   5074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5075         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5076         -1,
   5077         -1,
   5078     },
   5079 #endif /* chips */
   5080 
   5081 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   5082     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_BCM53314_A0r */
   5083         soc_block_list[5],
   5084         soc_genreg,
   5085         1,
   5086         0,
   5087         0x6080008,
   5088         SOC_REG_FLAG_RO,
   5089         0,
   5090         4,
   5091         soc_L2_ENTRY_PARITY_STATUS_BCM53314_A0r_fields,
   5092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5093         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5094         -1,
   5095         -1,
   5096     },
   5097 #endif /* chips */
   5098 
   5099 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   5100     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_BCM56224_A0r */
   5101         soc_block_list[5],
   5102         soc_genreg,
   5103         1,
   5104         0,
   5105         0x6080008,
   5106         SOC_REG_FLAG_RO,
   5107         0,
   5108         3,
   5109         soc_L2_ENTRY_PARITY_STATUSr_fields,
   5110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5111         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5112         -1,
   5113         -1,
   5114     },
   5115 #endif /* chips */
   5116 
   5117 #if defined(BCM_56314_A0)
   5118     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_BCM56314_A0r */
   5119         soc_block_list[5],
   5120         soc_genreg,
   5121         1,
   5122         0,
   5123         0x608000d,
   5124         SOC_REG_FLAG_RO,
   5125         0,
   5126         3,
   5127         soc_L3_ENTRY_PARITY_STATUSr_fields,
   5128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5129         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   5130         -1,
   5131         -1,
   5132     },
   5133 #endif /* chips */
   5134 
   5135 #if defined(BCM_56514_A0)
   5136     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_BCM56514_A0r */
   5137         soc_block_list[5],
   5138         soc_genreg,
   5139         1,
   5140         0,
   5141         0x608000d,
   5142         SOC_REG_FLAG_RO,
   5143         0,
   5144         3,
   5145         soc_L2_ENTRY_PARITY_STATUS_BCM56514_A0r_fields,
   5146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5147         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   5148         -1,
   5149         -1,
   5150     },
   5151 #endif /* chips */
   5152 
   5153 #if defined(BCM_56800_A0)
   5154     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_BCM56800_A0r */
   5155         soc_block_list[5],
   5156         soc_genreg,
   5157         1,
   5158         0,
   5159         0x608020e,
   5160         SOC_REG_FLAG_RO,
   5161         0,
   5162         3,
   5163         soc_L2_ENTRY_PARITY_STATUSr_fields,
   5164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5165         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5166         -1,
   5167         -1,
   5168     },
   5169 #endif /* chips */
   5170 
   5171 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   5172     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_BCM56820_A0r */
   5173         soc_block_list[5],
   5174         soc_genreg,
   5175         1,
   5176         0,
   5177         0x608020e,
   5178         SOC_REG_FLAG_RO,
   5179         0,
   5180         3,
   5181         soc_L2_ENTRY_PARITY_STATUS_BCM56514_A0r_fields,
   5182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5183         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   5184         -1,
   5185         -1,
   5186     },
   5187 #endif /* chips */
   5188 
   5189 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5190     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5191     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5192     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_INTR_0r */
   5193         soc_block_list[5],
   5194         soc_genreg,
   5195         1,
   5196         0,
   5197         0x7080186,
   5198         0,
   5199         0,
   5200         3,
   5201         soc_L2_ENTRY_PARITY_STATUS_INTR_0r_fields,
   5202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5203         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5204         -1,
   5205         -1,
   5206     },
   5207 #endif /* chips */
   5208 
   5209 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5210     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5211     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5212     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_INTR_1r */
   5213         soc_block_list[5],
   5214         soc_genreg,
   5215         1,
   5216         0,
   5217         0x7080187,
   5218         0,
   5219         0,
   5220         3,
   5221         soc_L2_ENTRY_PARITY_STATUS_INTR_0r_fields,
   5222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5223         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5224         -1,
   5225         -1,
   5226     },
   5227 #endif /* chips */
   5228 
   5229 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5230     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_INTR_0_BCM56440_A0r */
   5231         soc_block_list[5],
   5232         soc_genreg,
   5233         1,
   5234         0,
   5235         0x608030d,
   5236         0,
   5237         0,
   5238         3,
   5239         soc_L2_ENTRY_PARITY_STATUS_0r_fields,
   5240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5241         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5242         -1,
   5243         -1,
   5244     },
   5245 #endif /* chips */
   5246 
   5247 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5248     defined(BCM_56450_B1)
   5249     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_INTR_0_BCM56450_A0r */
   5250         soc_block_list[5],
   5251         soc_genreg,
   5252         1,
   5253         0,
   5254         0x1a010e00,
   5255         0,
   5256         0,
   5257         3,
   5258         soc_L2_ENTRY_PARITY_STATUS_INTR_0_BCM56450_A0r_fields,
   5259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5260         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   5261         -1,
   5262         -1,
   5263     },
   5264 #endif /* chips */
   5265 
   5266 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5267     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r */
   5268         soc_block_list[5],
   5269         soc_genreg,
   5270         1,
   5271         0,
   5272         0x6080d1f,
   5273         0,
   5274         0,
   5275         3,
   5276         soc_L2_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
   5277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5278         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5279         -1,
   5280         -1,
   5281     },
   5282 #endif /* chips */
   5283 
   5284 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5285     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_INTR_1_BCM56440_A0r */
   5286         soc_block_list[5],
   5287         soc_genreg,
   5288         1,
   5289         0,
   5290         0x608030e,
   5291         0,
   5292         0,
   5293         3,
   5294         soc_L2_ENTRY_PARITY_STATUS_1r_fields,
   5295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5296         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5297         -1,
   5298         -1,
   5299     },
   5300 #endif /* chips */
   5301 
   5302 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5303     defined(BCM_56450_B1)
   5304     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_INTR_1_BCM56450_A0r */
   5305         soc_block_list[5],
   5306         soc_genreg,
   5307         1,
   5308         0,
   5309         0x1a010f00,
   5310         0,
   5311         0,
   5312         3,
   5313         soc_L2_ENTRY_PARITY_STATUS_INTR_1r_fields,
   5314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5315         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   5316         -1,
   5317         -1,
   5318     },
   5319 #endif /* chips */
   5320 
   5321 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5322     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_INTR_1_BCM56840_A0r */
   5323         soc_block_list[5],
   5324         soc_genreg,
   5325         1,
   5326         0,
   5327         0x6080d20,
   5328         0,
   5329         0,
   5330         3,
   5331         soc_L2_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
   5332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5334         -1,
   5335         -1,
   5336     },
   5337 #endif /* chips */
   5338 
   5339 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5340     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5341     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5342     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_NACK_0r */
   5343         soc_block_list[5],
   5344         soc_genreg,
   5345         1,
   5346         0,
   5347         0x7080188,
   5348         0,
   5349         0,
   5350         3,
   5351         soc_L2_ENTRY_PARITY_STATUS_INTR_0r_fields,
   5352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5353         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5354         -1,
   5355         -1,
   5356     },
   5357 #endif /* chips */
   5358 
   5359 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5360     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5361     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5362     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_NACK_1r */
   5363         soc_block_list[5],
   5364         soc_genreg,
   5365         1,
   5366         0,
   5367         0x7080189,
   5368         0,
   5369         0,
   5370         3,
   5371         soc_L2_ENTRY_PARITY_STATUS_INTR_0r_fields,
   5372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5373         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5374         -1,
   5375         -1,
   5376     },
   5377 #endif /* chips */
   5378 
   5379 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5380     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_NACK_0_BCM56440_A0r */
   5381         soc_block_list[5],
   5382         soc_genreg,
   5383         1,
   5384         0,
   5385         0x608030f,
   5386         0,
   5387         0,
   5388         3,
   5389         soc_L2_ENTRY_PARITY_STATUS_0r_fields,
   5390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5391         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5392         -1,
   5393         -1,
   5394     },
   5395 #endif /* chips */
   5396 
   5397 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5398     defined(BCM_56450_B1)
   5399     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_NACK_0_BCM56450_A0r */
   5400         soc_block_list[5],
   5401         soc_genreg,
   5402         1,
   5403         0,
   5404         0x1a011000,
   5405         0,
   5406         0,
   5407         3,
   5408         soc_L2_ENTRY_PARITY_STATUS_INTR_0_BCM56450_A0r_fields,
   5409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5410         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   5411         -1,
   5412         -1,
   5413     },
   5414 #endif /* chips */
   5415 
   5416 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5417     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_NACK_0_BCM56840_A0r */
   5418         soc_block_list[5],
   5419         soc_genreg,
   5420         1,
   5421         0,
   5422         0x6080d21,
   5423         0,
   5424         0,
   5425         3,
   5426         soc_L2_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
   5427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5429         -1,
   5430         -1,
   5431     },
   5432 #endif /* chips */
   5433 
   5434 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5435     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_NACK_1_BCM56440_A0r */
   5436         soc_block_list[5],
   5437         soc_genreg,
   5438         1,
   5439         0,
   5440         0x6080310,
   5441         0,
   5442         0,
   5443         3,
   5444         soc_L2_ENTRY_PARITY_STATUS_1r_fields,
   5445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5446         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5447         -1,
   5448         -1,
   5449     },
   5450 #endif /* chips */
   5451 
   5452 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5453     defined(BCM_56450_B1)
   5454     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_NACK_1_BCM56450_A0r */
   5455         soc_block_list[5],
   5456         soc_genreg,
   5457         1,
   5458         0,
   5459         0x1a011100,
   5460         0,
   5461         0,
   5462         3,
   5463         soc_L2_ENTRY_PARITY_STATUS_INTR_1r_fields,
   5464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5465         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   5466         -1,
   5467         -1,
   5468     },
   5469 #endif /* chips */
   5470 
   5471 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5472     { /* SOC_REG_INT_L2_ENTRY_PARITY_STATUS_NACK_1_BCM56840_A0r */
   5473         soc_block_list[5],
   5474         soc_genreg,
   5475         1,
   5476         0,
   5477         0x6080d22,
   5478         0,
   5479         0,
   5480         3,
   5481         soc_L2_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
   5482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5484         -1,
   5485         -1,
   5486     },
   5487 #endif /* chips */
   5488 
   5489 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5490     { /* SOC_REG_INT_L2_ENTRY_SA_DBGCTRL_0r */
   5491         soc_block_list[5],
   5492         soc_genreg,
   5493         1,
   5494         0,
   5495         0x6080d10,
   5496         0,
   5497         0,
   5498         4,
   5499         soc_L2_ENTRY_SA_DBGCTRL_0r_fields,
   5500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5502         -1,
   5503         -1,
   5504     },
   5505 #endif /* chips */
   5506 
   5507 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5508     { /* SOC_REG_INT_L2_ENTRY_SA_DBGCTRL_1r */
   5509         soc_block_list[5],
   5510         soc_genreg,
   5511         1,
   5512         0,
   5513         0x6080d11,
   5514         0,
   5515         0,
   5516         3,
   5517         soc_L2_ENTRY_DA_DBGCTRL_1r_fields,
   5518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5519         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5520         -1,
   5521         -1,
   5522     },
   5523 #endif /* chips */
   5524 
   5525 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5526     { /* SOC_REG_INT_L2_ENTRY_SA_DBGCTRL_2r */
   5527         soc_block_list[5],
   5528         soc_genreg,
   5529         1,
   5530         0,
   5531         0x6080d12,
   5532         0,
   5533         0,
   5534         3,
   5535         soc_L2_ENTRY_DA_DBGCTRL_2r_fields,
   5536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5538         -1,
   5539         -1,
   5540     },
   5541 #endif /* chips */
   5542 
   5543 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5544     { /* SOC_REG_INT_L2_ENTRY_SA_DBGCTRL_3r */
   5545         soc_block_list[5],
   5546         soc_genreg,
   5547         1,
   5548         0,
   5549         0x6080d13,
   5550         0,
   5551         0,
   5552         3,
   5553         soc_L2_ENTRY_DA_DBGCTRL_3r_fields,
   5554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5556         -1,
   5557         -1,
   5558     },
   5559 #endif /* chips */
   5560 
   5561 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5562     { /* SOC_REG_INT_L2_ENTRY_SA_DBGCTRL_4r */
   5563         soc_block_list[5],
   5564         soc_genreg,
   5565         1,
   5566         0,
   5567         0x6080d14,
   5568         0,
   5569         0,
   5570         3,
   5571         soc_L2_ENTRY_DA_DBGCTRL_4r_fields,
   5572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5574         -1,
   5575         -1,
   5576     },
   5577 #endif /* chips */
   5578 
   5579 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5580     { /* SOC_REG_INT_L2_ENTRY_SA_DBGCTRL_5r */
   5581         soc_block_list[5],
   5582         soc_genreg,
   5583         1,
   5584         0,
   5585         0x6080d15,
   5586         0,
   5587         0,
   5588         1,
   5589         soc_L2_ENTRY_DA_DBGCTRL_5r_fields,
   5590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5592         -1,
   5593         -1,
   5594     },
   5595 #endif /* chips */
   5596 
   5597 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5598     { /* SOC_REG_INT_L2_ENTRY_SA_DBGCTRL_6r */
   5599         soc_block_list[5],
   5600         soc_genreg,
   5601         1,
   5602         0,
   5603         0x6080d16,
   5604         0,
   5605         0,
   5606         16,
   5607         soc_L2_ENTRY_DA_DBGCTRL_6r_fields,
   5608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5609         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5610         -1,
   5611         -1,
   5612     },
   5613 #endif /* chips */
   5614 
   5615 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5616     { /* SOC_REG_INT_L2_ENTRY_SA_DBGCTRL_7r */
   5617         soc_block_list[5],
   5618         soc_genreg,
   5619         1,
   5620         0,
   5621         0x6080d17,
   5622         0,
   5623         0,
   5624         16,
   5625         soc_L2_ENTRY_DA_DBGCTRL_7r_fields,
   5626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5628         -1,
   5629         -1,
   5630     },
   5631 #endif /* chips */
   5632 
   5633 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5634     { /* SOC_REG_INT_L2_ENTRY_SA_DBGCTRL_8r */
   5635         soc_block_list[5],
   5636         soc_genreg,
   5637         1,
   5638         0,
   5639         0x6080d18,
   5640         0,
   5641         0,
   5642         2,
   5643         soc_L2_ENTRY_DA_DBGCTRL_8r_fields,
   5644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5646         -1,
   5647         -1,
   5648     },
   5649 #endif /* chips */
   5650 
   5651 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   5652     { /* SOC_REG_INT_L2_HITDA_DBGCTRLr */
   5653         soc_block_list[5],
   5654         soc_genreg,
   5655         1,
   5656         0,
   5657         0x6080207,
   5658         0,
   5659         0,
   5660         2,
   5661         soc_L2_HITDA_DBGCTRLr_fields,
   5662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5663         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5664         -1,
   5665         -1,
   5666     },
   5667 #endif /* chips */
   5668 
   5669 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   5670     { /* SOC_REG_INT_L2_HITSA_DBGCTRLr */
   5671         soc_block_list[5],
   5672         soc_genreg,
   5673         1,
   5674         0,
   5675         0x6080206,
   5676         0,
   5677         0,
   5678         2,
   5679         soc_L2_HITDA_DBGCTRLr_fields,
   5680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5682         -1,
   5683         -1,
   5684     },
   5685 #endif /* chips */
   5686 
   5687 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
   5688     defined(BCM_56514_A0)
   5689     { /* SOC_REG_INT_L2_HIT_CONTROLr */
   5690         soc_block_list[5],
   5691         soc_genreg,
   5692         1,
   5693         0,
   5694         0x608000b,
   5695         0,
   5696         0,
   5697         4,
   5698         soc_L2_HIT_CONTROLr_fields,
   5699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5701         -1,
   5702         -1,
   5703     },
   5704 #endif /* chips */
   5705 
   5706 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   5707     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   5708     { /* SOC_REG_INT_L2_HIT_CONTROL_BCM56224_A0r */
   5709         soc_block_list[5],
   5710         soc_genreg,
   5711         1,
   5712         0,
   5713         0x6080006,
   5714         0,
   5715         0,
   5716         4,
   5717         soc_L2_HIT_CONTROLr_fields,
   5718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5719         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5720         -1,
   5721         -1,
   5722     },
   5723 #endif /* chips */
   5724 
   5725 #if defined(BCM_56800_A0)
   5726     { /* SOC_REG_INT_L2_HIT_DBGCTRLr */
   5727         soc_block_list[5],
   5728         soc_genreg,
   5729         1,
   5730         0,
   5731         0x608020c,
   5732         0,
   5733         0,
   5734         2,
   5735         soc_L2_HIT_DBGCTRLr_fields,
   5736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5737         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5738         -1,
   5739         -1,
   5740     },
   5741 #endif /* chips */
   5742 
   5743 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5744     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0r */
   5745         soc_block_list[5],
   5746         soc_genreg,
   5747         1,
   5748         0,
   5749         0x6080d19,
   5750         0,
   5751         0,
   5752         3,
   5753         soc_L2_HIT_DBGCTRL_0r_fields,
   5754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5755         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5756         -1,
   5757         -1,
   5758     },
   5759 #endif /* chips */
   5760 
   5761 #if defined(BCM_56860_A0)
   5762     { /* SOC_REG_INT_L2_HIT_DBGCTRL_01r */
   5763         soc_block_list[5],
   5764         soc_genreg,
   5765         1,
   5766         0,
   5767         0x1b080000,
   5768         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5769         0,
   5770         2,
   5771         soc_L2_HIT_DBGCTRL_01r_fields,
   5772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5774         -1,
   5775         -1,
   5776     },
   5777 #endif /* chips */
   5778 
   5779 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5780     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1r */
   5781         soc_block_list[5],
   5782         soc_genreg,
   5783         1,
   5784         0,
   5785         0x6080d1a,
   5786         0,
   5787         0,
   5788         3,
   5789         soc_L2_HIT_DBGCTRL_1r_fields,
   5790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5792         -1,
   5793         -1,
   5794     },
   5795 #endif /* chips */
   5796 
   5797 #if defined(BCM_56860_A0)
   5798     { /* SOC_REG_INT_L2_HIT_DBGCTRL_02r */
   5799         soc_block_list[5],
   5800         soc_genreg,
   5801         1,
   5802         0,
   5803         0x1b090000,
   5804         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5805         0,
   5806         2,
   5807         soc_L2_HIT_DBGCTRL_02r_fields,
   5808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5810         -1,
   5811         -1,
   5812     },
   5813 #endif /* chips */
   5814 
   5815 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5816     { /* SOC_REG_INT_L2_HIT_DBGCTRL_2r */
   5817         soc_block_list[5],
   5818         soc_genreg,
   5819         1,
   5820         0,
   5821         0x6080d1b,
   5822         0,
   5823         0,
   5824         3,
   5825         soc_L2_HIT_DBGCTRL_2r_fields,
   5826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5828         -1,
   5829         -1,
   5830     },
   5831 #endif /* chips */
   5832 
   5833 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5834     { /* SOC_REG_INT_L2_HIT_DBGCTRL_3r */
   5835         soc_block_list[5],
   5836         soc_genreg,
   5837         1,
   5838         0,
   5839         0x6080d1c,
   5840         0,
   5841         0,
   5842         3,
   5843         soc_L2_HIT_DBGCTRL_3r_fields,
   5844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5845         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5846         -1,
   5847         -1,
   5848     },
   5849 #endif /* chips */
   5850 
   5851 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5852     { /* SOC_REG_INT_L2_HIT_DBGCTRL_4r */
   5853         soc_block_list[5],
   5854         soc_genreg,
   5855         1,
   5856         0,
   5857         0x6080d1d,
   5858         0,
   5859         0,
   5860         24,
   5861         soc_L2_HIT_DBGCTRL_4r_fields,
   5862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5863         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5864         -1,
   5865         -1,
   5866     },
   5867 #endif /* chips */
   5868 
   5869 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   5870     { /* SOC_REG_INT_L2_HIT_DBGCTRL_01_BCM56560_A0r */
   5871         soc_block_list[5],
   5872         soc_genreg,
   5873         1,
   5874         0,
   5875         0x1b080000,
   5876         0,
   5877         0,
   5878         2,
   5879         soc_L2_HIT_DBGCTRL_01_BCM56560_A0r_fields,
   5880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5882         -1,
   5883         -1,
   5884     },
   5885 #endif /* chips */
   5886 
   5887 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   5888     { /* SOC_REG_INT_L2_HIT_DBGCTRL_01_BCM56670_A0r */
   5889         soc_block_list[5],
   5890         soc_genreg,
   5891         1,
   5892         0,
   5893         0x1b090000,
   5894         0,
   5895         0,
   5896         2,
   5897         soc_L2_HIT_DBGCTRL_01_BCM56560_A0r_fields,
   5898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5899         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5900         -1,
   5901         -1,
   5902     },
   5903 #endif /* chips */
   5904 
   5905 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   5906     { /* SOC_REG_INT_L2_HIT_DBGCTRL_02_BCM56560_A0r */
   5907         soc_block_list[5],
   5908         soc_genreg,
   5909         1,
   5910         0,
   5911         0x1b090000,
   5912         0,
   5913         0,
   5914         2,
   5915         soc_L2_HIT_DBGCTRL_02_BCM56560_A0r_fields,
   5916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5918         -1,
   5919         -1,
   5920     },
   5921 #endif /* chips */
   5922 
   5923 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   5924     { /* SOC_REG_INT_L2_HIT_DBGCTRL_02_BCM56670_A0r */
   5925         soc_block_list[5],
   5926         soc_genreg,
   5927         1,
   5928         0,
   5929         0x1b0a0000,
   5930         0,
   5931         0,
   5932         2,
   5933         soc_L2_HIT_DBGCTRL_02_BCM56560_A0r_fields,
   5934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5936         -1,
   5937         -1,
   5938     },
   5939 #endif /* chips */
   5940 
   5941 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5942     defined(BCM_56160_A0)
   5943     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM53400_A0r */
   5944         soc_block_list[5],
   5945         soc_genreg,
   5946         1,
   5947         0,
   5948         0x1e010f00,
   5949         0,
   5950         0,
   5951         1,
   5952         soc_L2_HIT_DBGCTRL_0_BCM53400_A0r_fields,
   5953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5954         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5955         -1,
   5956         -1,
   5957     },
   5958 #endif /* chips */
   5959 
   5960 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5961     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM53570_A0r */
   5962         soc_block_list[5],
   5963         soc_genreg,
   5964         1,
   5965         0,
   5966         0x1e010f00,
   5967         0,
   5968         0,
   5969         1,
   5970         soc_L2_HIT_DBGCTRL_0_BCM53570_A0r_fields,
   5971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5972         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5973         -1,
   5974         -1,
   5975     },
   5976 #endif /* chips */
   5977 
   5978 #if defined(BCM_56150_A0)
   5979     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56150_A0r */
   5980         soc_block_list[5],
   5981         soc_genreg,
   5982         1,
   5983         0,
   5984         0x1e010a00,
   5985         0,
   5986         0,
   5987         2,
   5988         soc_L2_HIT_DBGCTRL_0_BCM56150_A0r_fields,
   5989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5990         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5991         -1,
   5992         -1,
   5993     },
   5994 #endif /* chips */
   5995 
   5996 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   5997     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56260_A0r */
   5998         soc_block_list[5],
   5999         soc_genreg,
   6000         1,
   6001         0,
   6002         0x1a010d00,
   6003         0,
   6004         0,
   6005         1,
   6006         soc_L2_HIT_DBGCTRL_0_BCM56260_A0r_fields,
   6007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6008         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6009         -1,
   6010         -1,
   6011     },
   6012 #endif /* chips */
   6013 
   6014 #if defined(BCM_56270_A0)
   6015     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56270_A0r */
   6016         soc_block_list[5],
   6017         soc_genreg,
   6018         1,
   6019         0,
   6020         0x1a010d00,
   6021         0,
   6022         0,
   6023         1,
   6024         soc_L2_HIT_DBGCTRL_0_BCM53400_A0r_fields,
   6025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6026         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6027         -1,
   6028         -1,
   6029     },
   6030 #endif /* chips */
   6031 
   6032 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6033     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56440_A0r */
   6034         soc_block_list[5],
   6035         soc_genreg,
   6036         1,
   6037         0,
   6038         0x608030a,
   6039         0,
   6040         0,
   6041         3,
   6042         soc_L2_HIT_DBGCTRL_0_BCM56440_A0r_fields,
   6043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6044         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6045         -1,
   6046         -1,
   6047     },
   6048 #endif /* chips */
   6049 
   6050 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6051     defined(BCM_56450_B1)
   6052     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56450_A0r */
   6053         soc_block_list[5],
   6054         soc_genreg,
   6055         1,
   6056         0,
   6057         0x1a010b00,
   6058         0,
   6059         0,
   6060         3,
   6061         soc_L2_HIT_DBGCTRL_0_BCM56450_A0r_fields,
   6062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6064         -1,
   6065         -1,
   6066     },
   6067 #endif /* chips */
   6068 
   6069 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   6070     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56560_A0r */
   6071         soc_block_list[5],
   6072         soc_genreg,
   6073         1,
   6074         0,
   6075         0x1b070000,
   6076         0,
   6077         0,
   6078         2,
   6079         soc_L2_HIT_DBGCTRL_0_BCM56560_A0r_fields,
   6080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6081         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6082         -1,
   6083         -1,
   6084     },
   6085 #endif /* chips */
   6086 
   6087 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6088     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56670_A0r */
   6089         soc_block_list[5],
   6090         soc_genreg,
   6091         1,
   6092         0,
   6093         0x1b080000,
   6094         0,
   6095         0,
   6096         2,
   6097         soc_L2_HIT_DBGCTRL_0_BCM56560_A0r_fields,
   6098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6100         -1,
   6101         -1,
   6102     },
   6103 #endif /* chips */
   6104 
   6105 #if defined(BCM_56850_A0)
   6106     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56850_A0r */
   6107         soc_block_list[5],
   6108         soc_genreg,
   6109         1,
   6110         0,
   6111         0x1b070000,
   6112         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6113         0,
   6114         6,
   6115         soc_L2_HIT_DBGCTRL_0_BCM56850_A0r_fields,
   6116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6118         -1,
   6119         -1,
   6120     },
   6121 #endif /* chips */
   6122 
   6123 #if defined(BCM_56860_A0)
   6124     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56860_A0r */
   6125         soc_block_list[5],
   6126         soc_genreg,
   6127         1,
   6128         0,
   6129         0x1b070000,
   6130         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6131         0,
   6132         2,
   6133         soc_L2_HIT_DBGCTRL_0_BCM56860_A0r_fields,
   6134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6136         -1,
   6137         -1,
   6138     },
   6139 #endif /* chips */
   6140 
   6141 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6142     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56960_A0r */
   6143         soc_block_list[5],
   6144         soc_genreg,
   6145         1,
   6146         0,
   6147         0x3b130000,
   6148         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6149         0,
   6150         4,
   6151         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6153         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6154         -1,
   6155         -1,
   6156         3,
   6157     },
   6158 #endif /* chips */
   6159 
   6160 #if defined(BCM_56970_A0)
   6161     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_BCM56970_A0r */
   6162         soc_block_list[5],
   6163         soc_genreg,
   6164         1,
   6165         0,
   6166         0x5f120000,
   6167         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6168         0,
   6169         4,
   6170         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6172         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6173         -1,
   6174         -1,
   6175         3,
   6176     },
   6177 #endif /* chips */
   6178 
   6179 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6180     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_PIPE0r */
   6181         soc_block_list[5],
   6182         soc_genreg,
   6183         1,
   6184         0,
   6185         0x3b130000,
   6186         0,
   6187         0,
   6188         4,
   6189         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6192         -1,
   6193         -1,
   6194         3,
   6195     },
   6196 #endif /* chips */
   6197 
   6198 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6199     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_PIPE1r */
   6200         soc_block_list[5],
   6201         soc_genreg,
   6202         1,
   6203         0,
   6204         0x3b130000,
   6205         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6206         0,
   6207         4,
   6208         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6210         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6211         -1,
   6212         -1,
   6213         3,
   6214     },
   6215 #endif /* chips */
   6216 
   6217 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6218     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_PIPE2r */
   6219         soc_block_list[5],
   6220         soc_genreg,
   6221         1,
   6222         0,
   6223         0x3b130000,
   6224         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6225         0,
   6226         4,
   6227         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6229         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6230         -1,
   6231         -1,
   6232         3,
   6233     },
   6234 #endif /* chips */
   6235 
   6236 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6237     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_PIPE3r */
   6238         soc_block_list[5],
   6239         soc_genreg,
   6240         1,
   6241         0,
   6242         0x3b130000,
   6243         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6244         0,
   6245         4,
   6246         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6248         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6249         -1,
   6250         -1,
   6251         3,
   6252     },
   6253 #endif /* chips */
   6254 
   6255 #if defined(BCM_56970_A0)
   6256     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_PIPE0_BCM56970_A0r */
   6257         soc_block_list[5],
   6258         soc_genreg,
   6259         1,
   6260         0,
   6261         0x5f120000,
   6262         0,
   6263         0,
   6264         4,
   6265         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6267         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6268         -1,
   6269         -1,
   6270         3,
   6271     },
   6272 #endif /* chips */
   6273 
   6274 #if defined(BCM_56970_A0)
   6275     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_PIPE1_BCM56970_A0r */
   6276         soc_block_list[5],
   6277         soc_genreg,
   6278         1,
   6279         0,
   6280         0x5f120000,
   6281         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6282         0,
   6283         4,
   6284         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6286         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6287         -1,
   6288         -1,
   6289         3,
   6290     },
   6291 #endif /* chips */
   6292 
   6293 #if defined(BCM_56970_A0)
   6294     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_PIPE2_BCM56970_A0r */
   6295         soc_block_list[5],
   6296         soc_genreg,
   6297         1,
   6298         0,
   6299         0x5f120000,
   6300         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6301         0,
   6302         4,
   6303         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6305         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6306         -1,
   6307         -1,
   6308         3,
   6309     },
   6310 #endif /* chips */
   6311 
   6312 #if defined(BCM_56970_A0)
   6313     { /* SOC_REG_INT_L2_HIT_DBGCTRL_0_PIPE3_BCM56970_A0r */
   6314         soc_block_list[5],
   6315         soc_genreg,
   6316         1,
   6317         0,
   6318         0x5f120000,
   6319         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6320         0,
   6321         4,
   6322         soc_L2_HIT_DBGCTRL_0_BCM56960_A0r_fields,
   6323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6324         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6325         -1,
   6326         -1,
   6327         3,
   6328     },
   6329 #endif /* chips */
   6330 
   6331 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6332     defined(BCM_56160_A0)
   6333     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM53400_A0r */
   6334         soc_block_list[5],
   6335         soc_genreg,
   6336         1,
   6337         0,
   6338         0x1e011000,
   6339         0,
   6340         0,
   6341         1,
   6342         soc_L2_HIT_DBGCTRL_1_BCM53400_A0r_fields,
   6343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6345         -1,
   6346         -1,
   6347     },
   6348 #endif /* chips */
   6349 
   6350 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6351     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM53570_A0r */
   6352         soc_block_list[5],
   6353         soc_genreg,
   6354         1,
   6355         0,
   6356         0x1e011000,
   6357         0,
   6358         0,
   6359         1,
   6360         soc_L2_HIT_DBGCTRL_1_BCM53570_A0r_fields,
   6361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6362         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6363         -1,
   6364         -1,
   6365     },
   6366 #endif /* chips */
   6367 
   6368 #if defined(BCM_56150_A0)
   6369     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM56150_A0r */
   6370         soc_block_list[5],
   6371         soc_genreg,
   6372         1,
   6373         0,
   6374         0x1e010b00,
   6375         0,
   6376         0,
   6377         2,
   6378         soc_L2_HIT_DBGCTRL_1_BCM56150_A0r_fields,
   6379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6380         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6381         -1,
   6382         -1,
   6383     },
   6384 #endif /* chips */
   6385 
   6386 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   6387     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM56260_A0r */
   6388         soc_block_list[5],
   6389         soc_genreg,
   6390         1,
   6391         0,
   6392         0x1a010e00,
   6393         0,
   6394         0,
   6395         1,
   6396         soc_L2_HIT_DBGCTRL_1_BCM56260_A0r_fields,
   6397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6398         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6399         -1,
   6400         -1,
   6401     },
   6402 #endif /* chips */
   6403 
   6404 #if defined(BCM_56270_A0)
   6405     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM56270_A0r */
   6406         soc_block_list[5],
   6407         soc_genreg,
   6408         1,
   6409         0,
   6410         0x1a010e00,
   6411         0,
   6412         0,
   6413         1,
   6414         soc_L2_HIT_DBGCTRL_1_BCM53400_A0r_fields,
   6415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6416         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6417         -1,
   6418         -1,
   6419     },
   6420 #endif /* chips */
   6421 
   6422 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6423     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM56440_A0r */
   6424         soc_block_list[5],
   6425         soc_genreg,
   6426         1,
   6427         0,
   6428         0x608030b,
   6429         0,
   6430         0,
   6431         1,
   6432         soc_L2_HIT_DBGCTRL_1_BCM56440_A0r_fields,
   6433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6434         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6435         -1,
   6436         -1,
   6437     },
   6438 #endif /* chips */
   6439 
   6440 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6441     defined(BCM_56450_B1)
   6442     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM56450_A0r */
   6443         soc_block_list[5],
   6444         soc_genreg,
   6445         1,
   6446         0,
   6447         0x1a010c00,
   6448         0,
   6449         0,
   6450         1,
   6451         soc_L2_HIT_DBGCTRL_1_BCM56450_A0r_fields,
   6452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6453         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6454         -1,
   6455         -1,
   6456     },
   6457 #endif /* chips */
   6458 
   6459 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   6460     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM56560_A0r */
   6461         soc_block_list[5],
   6462         soc_genreg,
   6463         1,
   6464         0,
   6465         0x1b0a0000,
   6466         0,
   6467         0,
   6468         5,
   6469         soc_L2_HIT_DBGCTRL_1_BCM56560_A0r_fields,
   6470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6472         -1,
   6473         -1,
   6474     },
   6475 #endif /* chips */
   6476 
   6477 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6478     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM56670_A0r */
   6479         soc_block_list[5],
   6480         soc_genreg,
   6481         1,
   6482         0,
   6483         0x1b0b0000,
   6484         0,
   6485         0,
   6486         5,
   6487         soc_L2_HIT_DBGCTRL_1_BCM56560_A0r_fields,
   6488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6490         -1,
   6491         -1,
   6492     },
   6493 #endif /* chips */
   6494 
   6495 #if defined(BCM_56850_A0)
   6496     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM56850_A0r */
   6497         soc_block_list[5],
   6498         soc_genreg,
   6499         1,
   6500         0,
   6501         0x1b080000,
   6502         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6503         0,
   6504         5,
   6505         soc_L2_HIT_DBGCTRL_1_BCM56850_A0r_fields,
   6506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6508         -1,
   6509         -1,
   6510     },
   6511 #endif /* chips */
   6512 
   6513 #if defined(BCM_56860_A0)
   6514     { /* SOC_REG_INT_L2_HIT_DBGCTRL_1_BCM56860_A0r */
   6515         soc_block_list[5],
   6516         soc_genreg,
   6517         1,
   6518         0,
   6519         0x1b0a0000,
   6520         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6521         0,
   6522         5,
   6523         soc_L2_HIT_DBGCTRL_1_BCM56850_A0r_fields,
   6524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6525         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6526         -1,
   6527         -1,
   6528     },
   6529 #endif /* chips */
   6530 
   6531 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   6532     { /* SOC_REG_INT_L2_HIT_DBGCTRL_2_BCM56560_A0r */
   6533         soc_block_list[5],
   6534         soc_genreg,
   6535         1,
   6536         0,
   6537         0x1b0b0000,
   6538         0,
   6539         0,
   6540         1,
   6541         soc_L2_HIT_DBGCTRL_2_BCM56560_A0r_fields,
   6542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6544         -1,
   6545         -1,
   6546     },
   6547 #endif /* chips */
   6548 
   6549 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6550     { /* SOC_REG_INT_L2_HIT_DBGCTRL_2_BCM56670_A0r */
   6551         soc_block_list[5],
   6552         soc_genreg,
   6553         1,
   6554         0,
   6555         0x1b0c0000,
   6556         0,
   6557         0,
   6558         1,
   6559         soc_L2_HIT_DBGCTRL_2_BCM56560_A0r_fields,
   6560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6562         -1,
   6563         -1,
   6564     },
   6565 #endif /* chips */
   6566 
   6567 #if defined(BCM_56850_A0)
   6568     { /* SOC_REG_INT_L2_HIT_DBGCTRL_2_BCM56850_A0r */
   6569         soc_block_list[5],
   6570         soc_genreg,
   6571         1,
   6572         0,
   6573         0x1b090000,
   6574         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6575         0,
   6576         1,
   6577         soc_L2_HIT_DBGCTRL_2_BCM56850_A0r_fields,
   6578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6580         -1,
   6581         -1,
   6582     },
   6583 #endif /* chips */
   6584 
   6585 #if defined(BCM_56860_A0)
   6586     { /* SOC_REG_INT_L2_HIT_DBGCTRL_2_BCM56860_A0r */
   6587         soc_block_list[5],
   6588         soc_genreg,
   6589         1,
   6590         0,
   6591         0x1b0b0000,
   6592         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6593         0,
   6594         1,
   6595         soc_L2_HIT_DBGCTRL_2_BCM56850_A0r_fields,
   6596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6598         -1,
   6599         -1,
   6600     },
   6601 #endif /* chips */
   6602 
   6603 #if defined(BCM_56142_A0)
   6604     { /* SOC_REG_INT_L2_HIT_DBGCTRL_BCM56142_A0r */
   6605         soc_block_list[5],
   6606         soc_genreg,
   6607         1,
   6608         0,
   6609         0x708013c,
   6610         0,
   6611         0,
   6612         4,
   6613         soc_L2_HIT_DBGCTRL_BCM56624_A0r_fields,
   6614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6616         -1,
   6617         -1,
   6618     },
   6619 #endif /* chips */
   6620 
   6621 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   6622     { /* SOC_REG_INT_L2_HIT_DBGCTRL_BCM56334_A0r */
   6623         soc_block_list[5],
   6624         soc_genreg,
   6625         1,
   6626         0,
   6627         0x7080154,
   6628         0,
   6629         0,
   6630         4,
   6631         soc_L2_HIT_DBGCTRL_BCM56624_A0r_fields,
   6632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6634         -1,
   6635         -1,
   6636     },
   6637 #endif /* chips */
   6638 
   6639 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6640     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   6641     { /* SOC_REG_INT_L2_HIT_DBGCTRL_BCM56624_A0r */
   6642         soc_block_list[5],
   6643         soc_genreg,
   6644         1,
   6645         0,
   6646         0x7080134,
   6647         0,
   6648         0,
   6649         4,
   6650         soc_L2_HIT_DBGCTRL_BCM56624_A0r_fields,
   6651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6652         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6653         -1,
   6654         -1,
   6655     },
   6656 #endif /* chips */
   6657 
   6658 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6659     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6660     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6661     { /* SOC_REG_INT_L2_HIT_DBGCTRL_BCM56634_A0r */
   6662         soc_block_list[5],
   6663         soc_genreg,
   6664         1,
   6665         0,
   6666         0x7080184,
   6667         0,
   6668         0,
   6669         4,
   6670         soc_L2_HIT_DBGCTRL_BCM56624_A0r_fields,
   6671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6672         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6673         -1,
   6674         -1,
   6675     },
   6676 #endif /* chips */
   6677 
   6678 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   6679     { /* SOC_REG_INT_L2_ISS_BANK_CONFIGr */
   6680         soc_block_list[5],
   6681         soc_genreg,
   6682         1,
   6683         0,
   6684         0x1a001b00,
   6685         0,
   6686         0,
   6687         1,
   6688         soc_L2_ISS_BANK_CONFIGr_fields,
   6689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6690         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6691         -1,
   6692         -1,
   6693     },
   6694 #endif /* chips */
   6695 
   6696 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   6697     { /* SOC_REG_INT_L2_ISS_LOG_TO_PHY_BANK_MAPr */
   6698         soc_block_list[5],
   6699         soc_genreg,
   6700         1,
   6701         0,
   6702         0x1a001a00,
   6703         0,
   6704         0,
   6705         4,
   6706         soc_L2_ISS_LOG_TO_PHY_BANK_MAPr_fields,
   6707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6708         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6709         -1,
   6710         -1,
   6711     },
   6712 #endif /* chips */
   6713 
   6714 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6715     { /* SOC_REG_INT_L2_LEARN_CACHE_STATUSr */
   6716         soc_block_list[5],
   6717         soc_genreg,
   6718         1,
   6719         0,
   6720         0x12004500,
   6721         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6722         0,
   6723         2,
   6724         soc_L2_LEARN_CACHE_STATUSr_fields,
   6725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6726         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6727         -1,
   6728         -1,
   6729         3,
   6730     },
   6731 #endif /* chips */
   6732 
   6733 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6734     { /* SOC_REG_INT_L2_LEARN_CACHE_STATUS_PIPE0r */
   6735         soc_block_list[5],
   6736         soc_genreg,
   6737         1,
   6738         0,
   6739         0x12004500,
   6740         0,
   6741         0,
   6742         2,
   6743         soc_L2_LEARN_CACHE_STATUSr_fields,
   6744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6745         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6746         -1,
   6747         -1,
   6748         3,
   6749     },
   6750 #endif /* chips */
   6751 
   6752 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6753     { /* SOC_REG_INT_L2_LEARN_CACHE_STATUS_PIPE1r */
   6754         soc_block_list[5],
   6755         soc_genreg,
   6756         1,
   6757         0,
   6758         0x12004500,
   6759         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6760         0,
   6761         2,
   6762         soc_L2_LEARN_CACHE_STATUSr_fields,
   6763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6764         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6765         -1,
   6766         -1,
   6767         3,
   6768     },
   6769 #endif /* chips */
   6770 
   6771 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6772     { /* SOC_REG_INT_L2_LEARN_CACHE_STATUS_PIPE2r */
   6773         soc_block_list[5],
   6774         soc_genreg,
   6775         1,
   6776         0,
   6777         0x12004500,
   6778         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6779         0,
   6780         2,
   6781         soc_L2_LEARN_CACHE_STATUSr_fields,
   6782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6783         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6784         -1,
   6785         -1,
   6786         3,
   6787     },
   6788 #endif /* chips */
   6789 
   6790 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6791     { /* SOC_REG_INT_L2_LEARN_CACHE_STATUS_PIPE3r */
   6792         soc_block_list[5],
   6793         soc_genreg,
   6794         1,
   6795         0,
   6796         0x12004500,
   6797         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6798         0,
   6799         2,
   6800         soc_L2_LEARN_CACHE_STATUSr_fields,
   6801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6802         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6803         -1,
   6804         -1,
   6805         3,
   6806     },
   6807 #endif /* chips */
   6808 
   6809 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6810     { /* SOC_REG_INT_L2_LEARN_CACHE_STATUS_PIPE4r */
   6811         soc_block_list[5],
   6812         soc_genreg,
   6813         1,
   6814         0,
   6815         0x12004500,
   6816         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6817         0,
   6818         2,
   6819         soc_L2_LEARN_CACHE_STATUSr_fields,
   6820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6821         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6822         -1,
   6823         -1,
   6824         3,
   6825     },
   6826 #endif /* chips */
   6827 
   6828 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6829     { /* SOC_REG_INT_L2_LEARN_CACHE_STATUS_PIPE5r */
   6830         soc_block_list[5],
   6831         soc_genreg,
   6832         1,
   6833         0,
   6834         0x12004500,
   6835         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6836         0,
   6837         2,
   6838         soc_L2_LEARN_CACHE_STATUSr_fields,
   6839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6840         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6841         -1,
   6842         -1,
   6843         3,
   6844     },
   6845 #endif /* chips */
   6846 
   6847 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6848     { /* SOC_REG_INT_L2_LEARN_CACHE_STATUS_PIPE6r */
   6849         soc_block_list[5],
   6850         soc_genreg,
   6851         1,
   6852         0,
   6853         0x12004500,
   6854         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6855         0,
   6856         2,
   6857         soc_L2_LEARN_CACHE_STATUSr_fields,
   6858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6859         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6860         -1,
   6861         -1,
   6862         3,
   6863     },
   6864 #endif /* chips */
   6865 
   6866 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6867     { /* SOC_REG_INT_L2_LEARN_CACHE_STATUS_PIPE7r */
   6868         soc_block_list[5],
   6869         soc_genreg,
   6870         1,
   6871         0,
   6872         0x12004500,
   6873         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6874         0,
   6875         2,
   6876         soc_L2_LEARN_CACHE_STATUSr_fields,
   6877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6878         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6879         -1,
   6880         -1,
   6881         3,
   6882     },
   6883 #endif /* chips */
   6884 
   6885 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   6886     defined(BCM_56334_B0) || defined(BCM_56624_A0) || \
   6887     defined(BCM_56624_B0) || defined(BCM_56680_A0) || \
   6888     defined(BCM_56680_B0)
   6889     { /* SOC_REG_INT_L2_LEARN_CONTROLr */
   6890         soc_block_list[5],
   6891         soc_genreg,
   6892         1,
   6893         0,
   6894         0x7080033,
   6895         0,
   6896         0,
   6897         3,
   6898         soc_L2_LEARN_CONTROLr_fields,
   6899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6900         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6901         -1,
   6902         -1,
   6903     },
   6904 #endif /* chips */
   6905 
   6906 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6907     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6908     defined(BCM_56160_A0)
   6909     { /* SOC_REG_INT_L2_LEARN_CONTROL_BCM53400_A0r */
   6910         soc_block_list[5],
   6911         soc_genreg,
   6912         1,
   6913         0,
   6914         0x1e000700,
   6915         0,
   6916         0,
   6917         2,
   6918         soc_L2_LEARN_CONTROL_BCM53400_A0r_fields,
   6919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6920         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6921         -1,
   6922         -1,
   6923     },
   6924 #endif /* chips */
   6925 
   6926 #if defined(BCM_56150_A0)
   6927     { /* SOC_REG_INT_L2_LEARN_CONTROL_BCM56150_A0r */
   6928         soc_block_list[5],
   6929         soc_genreg,
   6930         1,
   6931         0,
   6932         0x1e000700,
   6933         0,
   6934         0,
   6935         2,
   6936         soc_L2_LEARN_CONTROL_BCM56150_A0r_fields,
   6937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6938         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6939         -1,
   6940         -1,
   6941     },
   6942 #endif /* chips */
   6943 
   6944 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   6945     defined(BCM_56270_A0)
   6946     { /* SOC_REG_INT_L2_LEARN_CONTROL_BCM56260_A0r */
   6947         soc_block_list[5],
   6948         soc_genreg,
   6949         1,
   6950         0,
   6951         0x1a000300,
   6952         0,
   6953         0,
   6954         2,
   6955         soc_L2_LEARN_CONTROL_BCM56260_A0r_fields,
   6956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6957         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6958         -1,
   6959         -1,
   6960     },
   6961 #endif /* chips */
   6962 
   6963 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6964     { /* SOC_REG_INT_L2_LEARN_CONTROL_BCM56440_A0r */
   6965         soc_block_list[5],
   6966         soc_genreg,
   6967         1,
   6968         0,
   6969         0x6080633,
   6970         0,
   6971         0,
   6972         2,
   6973         soc_L2_LEARN_CONTROL_BCM56440_A0r_fields,
   6974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6975         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6976         -1,
   6977         -1,
   6978     },
   6979 #endif /* chips */
   6980 
   6981 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6982     defined(BCM_56450_B1)
   6983     { /* SOC_REG_INT_L2_LEARN_CONTROL_BCM56450_A0r */
   6984         soc_block_list[5],
   6985         soc_genreg,
   6986         1,
   6987         0,
   6988         0x1a000300,
   6989         0,
   6990         0,
   6991         2,
   6992         soc_L2_LEARN_CONTROL_BCM56450_A0r_fields,
   6993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6994         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6995         -1,
   6996         -1,
   6997     },
   6998 #endif /* chips */
   6999 
   7000 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   7001     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   7002     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   7003     { /* SOC_REG_INT_L2_LEARN_CONTROL_BCM56634_A0r */
   7004         soc_block_list[5],
   7005         soc_genreg,
   7006         1,
   7007         0,
   7008         0x70800a3,
   7009         0,
   7010         0,
   7011         3,
   7012         soc_L2_LEARN_CONTROLr_fields,
   7013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7014         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7015         -1,
   7016         -1,
   7017     },
   7018 #endif /* chips */
   7019 
   7020 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   7021     { /* SOC_REG_INT_L2_LEARN_CONTROL_BCM56820_A0r */
   7022         soc_block_list[5],
   7023         soc_genreg,
   7024         1,
   7025         0,
   7026         0x608061d,
   7027         0,
   7028         0,
   7029         3,
   7030         soc_L2_LEARN_CONTROLr_fields,
   7031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7032         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7033         -1,
   7034         -1,
   7035     },
   7036 #endif /* chips */
   7037 
   7038 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   7039     { /* SOC_REG_INT_L2_LEARN_CONTROL_BCM56840_A0r */
   7040         soc_block_list[5],
   7041         soc_genreg,
   7042         1,
   7043         0,
   7044         0x6080617,
   7045         0,
   7046         0,
   7047         2,
   7048         soc_L2_LEARN_CONTROL_BCM56840_A0r_fields,
   7049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7050         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   7051         -1,
   7052         -1,
   7053     },
   7054 #endif /* chips */
   7055 
   7056 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7057     { /* SOC_REG_INT_L2_LEARN_COPY_CACHE_CTRLr */
   7058         soc_block_list[5],
   7059         soc_genreg,
   7060         1,
   7061         0,
   7062         0x12004600,
   7063         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7064         0,
   7065         4,
   7066         soc_L2_LEARN_COPY_CACHE_CTRLr_fields,
   7067         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
   7068         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7069         -1,
   7070         -1,
   7071         3,
   7072     },
   7073 #endif /* chips */
   7074 
   7075 #if defined(BCM_56850_A0)
   7076     { /* SOC_REG_INT_L2_LP_CONTROL_0r */
   7077         soc_block_list[5],
   7078         soc_genreg,
   7079         1,
   7080         0,
   7081         0x2b070000,
   7082         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7083         0,
   7084         4,
   7085         soc_L2_LP_CONTROL_0r_fields,
   7086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7088         -1,
   7089         -1,
   7090     },
   7091 #endif /* chips */
   7092 
   7093 #if defined(BCM_56850_A0)
   7094     { /* SOC_REG_INT_L2_LP_CONTROL_1r */
   7095         soc_block_list[5],
   7096         soc_genreg,
   7097         1,
   7098         0,
   7099         0x2b080000,
   7100         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7101         0,
   7102         3,
   7103         soc_L2_LP_CONTROL_1r_fields,
   7104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7105         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7106         -1,
   7107         -1,
   7108     },
   7109 #endif /* chips */
   7110 
   7111 #if defined(BCM_56850_A0)
   7112     { /* SOC_REG_INT_L2_LP_CONTROL_2r */
   7113         soc_block_list[5],
   7114         soc_genreg,
   7115         1,
   7116         0,
   7117         0x2b090000,
   7118         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7119         0,
   7120         1,
   7121         soc_L2_LP_CONTROL_2r_fields,
   7122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7124         -1,
   7125         -1,
   7126     },
   7127 #endif /* chips */
   7128 
   7129 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   7130     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   7131     { /* SOC_REG_INT_L2_LP_CONTROL_0_BCM56560_A0r */
   7132         soc_block_list[5],
   7133         soc_genreg,
   7134         1,
   7135         0,
   7136         0x3b020000,
   7137         0,
   7138         0,
   7139         1,
   7140         soc_L2_ENTRY_CONTROL_0_BCM56560_A0r_fields,
   7141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7142         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7143         -1,
   7144         -1,
   7145     },
   7146 #endif /* chips */
   7147 
   7148 #if defined(BCM_56860_A0)
   7149     { /* SOC_REG_INT_L2_LP_CONTROL_0_BCM56860_A0r */
   7150         soc_block_list[5],
   7151         soc_genreg,
   7152         1,
   7153         0,
   7154         0x3b020000,
   7155         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7156         0,
   7157         1,
   7158         soc_L2_ENTRY_CONTROL_0_BCM56860_A0r_fields,
   7159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7161         -1,
   7162         -1,
   7163     },
   7164 #endif /* chips */
   7165 
   7166 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7167     { /* SOC_REG_INT_L2_LP_CONTROL_0_BCM56960_A0r */
   7168         soc_block_list[5],
   7169         soc_genreg,
   7170         1,
   7171         0,
   7172         0x3b1b0000,
   7173         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7174         0,
   7175         4,
   7176         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7178         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7179         -1,
   7180         -1,
   7181         3,
   7182     },
   7183 #endif /* chips */
   7184 
   7185 #if defined(BCM_56970_A0)
   7186     { /* SOC_REG_INT_L2_LP_CONTROL_0_BCM56970_A0r */
   7187         soc_block_list[5],
   7188         soc_genreg,
   7189         1,
   7190         0,
   7191         0x5f1a0000,
   7192         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7193         0,
   7194         4,
   7195         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7197         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7198         -1,
   7199         -1,
   7200         3,
   7201     },
   7202 #endif /* chips */
   7203 
   7204 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7205     { /* SOC_REG_INT_L2_LP_CONTROL_0_PIPE0r */
   7206         soc_block_list[5],
   7207         soc_genreg,
   7208         1,
   7209         0,
   7210         0x3b1b0000,
   7211         0,
   7212         0,
   7213         4,
   7214         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7216         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7217         -1,
   7218         -1,
   7219         3,
   7220     },
   7221 #endif /* chips */
   7222 
   7223 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7224     { /* SOC_REG_INT_L2_LP_CONTROL_0_PIPE1r */
   7225         soc_block_list[5],
   7226         soc_genreg,
   7227         1,
   7228         0,
   7229         0x3b1b0000,
   7230         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7231         0,
   7232         4,
   7233         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7235         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7236         -1,
   7237         -1,
   7238         3,
   7239     },
   7240 #endif /* chips */
   7241 
   7242 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7243     { /* SOC_REG_INT_L2_LP_CONTROL_0_PIPE2r */
   7244         soc_block_list[5],
   7245         soc_genreg,
   7246         1,
   7247         0,
   7248         0x3b1b0000,
   7249         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7250         0,
   7251         4,
   7252         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7254         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7255         -1,
   7256         -1,
   7257         3,
   7258     },
   7259 #endif /* chips */
   7260 
   7261 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7262     { /* SOC_REG_INT_L2_LP_CONTROL_0_PIPE3r */
   7263         soc_block_list[5],
   7264         soc_genreg,
   7265         1,
   7266         0,
   7267         0x3b1b0000,
   7268         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7269         0,
   7270         4,
   7271         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7273         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7274         -1,
   7275         -1,
   7276         3,
   7277     },
   7278 #endif /* chips */
   7279 
   7280 #if defined(BCM_56970_A0)
   7281     { /* SOC_REG_INT_L2_LP_CONTROL_0_PIPE0_BCM56970_A0r */
   7282         soc_block_list[5],
   7283         soc_genreg,
   7284         1,
   7285         0,
   7286         0x5f1a0000,
   7287         0,
   7288         0,
   7289         4,
   7290         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7293         -1,
   7294         -1,
   7295         3,
   7296     },
   7297 #endif /* chips */
   7298 
   7299 #if defined(BCM_56970_A0)
   7300     { /* SOC_REG_INT_L2_LP_CONTROL_0_PIPE1_BCM56970_A0r */
   7301         soc_block_list[5],
   7302         soc_genreg,
   7303         1,
   7304         0,
   7305         0x5f1a0000,
   7306         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7307         0,
   7308         4,
   7309         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7312         -1,
   7313         -1,
   7314         3,
   7315     },
   7316 #endif /* chips */
   7317 
   7318 #if defined(BCM_56970_A0)
   7319     { /* SOC_REG_INT_L2_LP_CONTROL_0_PIPE2_BCM56970_A0r */
   7320         soc_block_list[5],
   7321         soc_genreg,
   7322         1,
   7323         0,
   7324         0x5f1a0000,
   7325         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7326         0,
   7327         4,
   7328         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7331         -1,
   7332         -1,
   7333         3,
   7334     },
   7335 #endif /* chips */
   7336 
   7337 #if defined(BCM_56970_A0)
   7338     { /* SOC_REG_INT_L2_LP_CONTROL_0_PIPE3_BCM56970_A0r */
   7339         soc_block_list[5],
   7340         soc_genreg,
   7341         1,
   7342         0,
   7343         0x5f1a0000,
   7344         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7345         0,
   7346         4,
   7347         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
   7348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7349         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7350         -1,
   7351         -1,
   7352         3,
   7353     },
   7354 #endif /* chips */
   7355 
   7356 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7357     { /* SOC_REG_INT_L2_MGMT_CONTROLr */
   7358         soc_block_list[5],
   7359         soc_genreg,
   7360         1,
   7361         0,
   7362         0x62000000,
   7363         0,
   7364         0,
   7365         3,
   7366         soc_L2_MGMT_CONTROLr_fields,
   7367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7368         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7369         -1,
   7370         -1,
   7371         3,
   7372     },
   7373 #endif /* chips */
   7374 
   7375 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7376     defined(BCM_56870_A0)
   7377     { /* SOC_REG_INT_L2_MGMT_CONTROL_BCM56870_A0r */
   7378         soc_block_list[5],
   7379         soc_genreg,
   7380         1,
   7381         0,
   7382         0xaa000000,
   7383         0,
   7384         0,
   7385         5,
   7386         soc_L2_MGMT_CONTROL_BCM56870_A0r_fields,
   7387         SOC_RESET_VAL_DEC(0x00001080, 0x00000000)
   7388         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   7389         -1,
   7390         -1,
   7391         3,
   7392     },
   7393 #endif /* chips */
   7394 
   7395 #if defined(BCM_56970_A0)
   7396     { /* SOC_REG_INT_L2_MGMT_CONTROL_BCM56970_A0r */
   7397         soc_block_list[5],
   7398         soc_genreg,
   7399         1,
   7400         0,
   7401         0xa2000000,
   7402         0,
   7403         0,
   7404         3,
   7405         soc_L2_MGMT_CONTROLr_fields,
   7406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7407         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7408         -1,
   7409         -1,
   7410         3,
   7411     },
   7412 #endif /* chips */
   7413 
   7414 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7415     { /* SOC_REG_INT_L2_MGMT_HW_RESET_CONTROL_0r */
   7416         soc_block_list[5],
   7417         soc_genreg,
   7418         1,
   7419         0,
   7420         0x62000a00,
   7421         0,
   7422         0,
   7423         2,
   7424         soc_L2_MGMT_HW_RESET_CONTROL_0r_fields,
   7425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7426         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7427         -1,
   7428         -1,
   7429         3,
   7430     },
   7431 #endif /* chips */
   7432 
   7433 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7434     { /* SOC_REG_INT_L2_MGMT_HW_RESET_CONTROL_1r */
   7435         soc_block_list[5],
   7436         soc_genreg,
   7437         1,
   7438         0,
   7439         0x62000b00,
   7440         0,
   7441         0,
   7442         4,
   7443         soc_L2_MGMT_HW_RESET_CONTROL_1r_fields,
   7444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7446         -1,
   7447         -1,
   7448         3,
   7449     },
   7450 #endif /* chips */
   7451 
   7452 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7453     defined(BCM_56870_A0)
   7454     { /* SOC_REG_INT_L2_MGMT_HW_RESET_CONTROL_0_BCM56870_A0r */
   7455         soc_block_list[5],
   7456         soc_genreg,
   7457         1,
   7458         0,
   7459         0xaa000a00,
   7460         0,
   7461         0,
   7462         2,
   7463         soc_L2_MGMT_HW_RESET_CONTROL_0r_fields,
   7464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7465         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7466         -1,
   7467         -1,
   7468         3,
   7469     },
   7470 #endif /* chips */
   7471 
   7472 #if defined(BCM_56970_A0)
   7473     { /* SOC_REG_INT_L2_MGMT_HW_RESET_CONTROL_0_BCM56970_A0r */
   7474         soc_block_list[5],
   7475         soc_genreg,
   7476         1,
   7477         0,
   7478         0xa2000a00,
   7479         0,
   7480         0,
   7481         2,
   7482         soc_L2_MGMT_HW_RESET_CONTROL_0r_fields,
   7483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7484         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7485         -1,
   7486         -1,
   7487         3,
   7488     },
   7489 #endif /* chips */
   7490 
   7491 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7492     defined(BCM_56870_A0)
   7493     { /* SOC_REG_INT_L2_MGMT_HW_RESET_CONTROL_1_BCM56870_A0r */
   7494         soc_block_list[5],
   7495         soc_genreg,
   7496         1,
   7497         0,
   7498         0xaa000b00,
   7499         0,
   7500         0,
   7501         4,
   7502         soc_L2_MGMT_HW_RESET_CONTROL_1r_fields,
   7503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7505         -1,
   7506         -1,
   7507         3,
   7508     },
   7509 #endif /* chips */
   7510 
   7511 #if defined(BCM_56970_A0)
   7512     { /* SOC_REG_INT_L2_MGMT_HW_RESET_CONTROL_1_BCM56970_A0r */
   7513         soc_block_list[5],
   7514         soc_genreg,
   7515         1,
   7516         0,
   7517         0xa2000b00,
   7518         0,
   7519         0,
   7520         4,
   7521         soc_L2_MGMT_HW_RESET_CONTROL_1r_fields,
   7522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7524         -1,
   7525         -1,
   7526         3,
   7527     },
   7528 #endif /* chips */
   7529 
   7530 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7531     { /* SOC_REG_INT_L2_MGMT_INTRr */
   7532         soc_block_list[5],
   7533         soc_genreg,
   7534         1,
   7535         0,
   7536         0x62000d00,
   7537         SOC_REG_FLAG_RO,
   7538         0,
   7539         5,
   7540         soc_L2_MGMT_INTRr_fields,
   7541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7542         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   7543         -1,
   7544         -1,
   7545         3,
   7546     },
   7547 #endif /* chips */
   7548 
   7549 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7550     defined(BCM_56870_A0)
   7551     { /* SOC_REG_INT_L2_MGMT_INTR_BCM56870_A0r */
   7552         soc_block_list[5],
   7553         soc_genreg,
   7554         1,
   7555         0,
   7556         0xaa000d00,
   7557         SOC_REG_FLAG_RO,
   7558         0,
   7559         5,
   7560         soc_L2_MGMT_INTRr_fields,
   7561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7562         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   7563         -1,
   7564         -1,
   7565         3,
   7566     },
   7567 #endif /* chips */
   7568 
   7569 #if defined(BCM_56970_A0)
   7570     { /* SOC_REG_INT_L2_MGMT_INTR_BCM56970_A0r */
   7571         soc_block_list[5],
   7572         soc_genreg,
   7573         1,
   7574         0,
   7575         0xa2000d00,
   7576         SOC_REG_FLAG_RO,
   7577         0,
   7578         5,
   7579         soc_L2_MGMT_INTRr_fields,
   7580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7581         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   7582         -1,
   7583         -1,
   7584         3,
   7585     },
   7586 #endif /* chips */
   7587 
   7588 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7589     { /* SOC_REG_INT_L2_MGMT_INTR_MASKr */
   7590         soc_block_list[5],
   7591         soc_genreg,
   7592         1,
   7593         0,
   7594         0x62000e00,
   7595         0,
   7596         0,
   7597         5,
   7598         soc_L2_MGMT_INTR_MASKr_fields,
   7599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7600         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   7601         -1,
   7602         -1,
   7603         3,
   7604     },
   7605 #endif /* chips */
   7606 
   7607 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7608     defined(BCM_56870_A0)
   7609     { /* SOC_REG_INT_L2_MGMT_INTR_MASK_BCM56870_A0r */
   7610         soc_block_list[5],
   7611         soc_genreg,
   7612         1,
   7613         0,
   7614         0xaa000e00,
   7615         0,
   7616         0,
   7617         5,
   7618         soc_L2_MGMT_INTR_MASKr_fields,
   7619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7620         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   7621         -1,
   7622         -1,
   7623         3,
   7624     },
   7625 #endif /* chips */
   7626 
   7627 #if defined(BCM_56970_A0)
   7628     { /* SOC_REG_INT_L2_MGMT_INTR_MASK_BCM56970_A0r */
   7629         soc_block_list[5],
   7630         soc_genreg,
   7631         1,
   7632         0,
   7633         0xa2000e00,
   7634         0,
   7635         0,
   7636         5,
   7637         soc_L2_MGMT_INTR_MASKr_fields,
   7638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7639         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   7640         -1,
   7641         -1,
   7642         3,
   7643     },
   7644 #endif /* chips */
   7645 
   7646 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7647     { /* SOC_REG_INT_L2_MGMT_SER_FIFO_CTRLr */
   7648         soc_block_list[5],
   7649         soc_genreg,
   7650         1,
   7651         0,
   7652         0x62000c00,
   7653         0,
   7654         0,
   7655         1,
   7656         soc_EGR_SER_FIFO_CTRL_BCM56960_A0r_fields,
   7657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7658         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7659         -1,
   7660         -1,
   7661         3,
   7662     },
   7663 #endif /* chips */
   7664 
   7665 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7666     defined(BCM_56870_A0)
   7667     { /* SOC_REG_INT_L2_MGMT_SER_FIFO_CTRL_BCM56870_A0r */
   7668         soc_block_list[5],
   7669         soc_genreg,
   7670         1,
   7671         0,
   7672         0xaa000c00,
   7673         0,
   7674         0,
   7675         1,
   7676         soc_EGR_SER_FIFO_CTRL_BCM56960_A0r_fields,
   7677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7678         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7679         -1,
   7680         -1,
   7681         3,
   7682     },
   7683 #endif /* chips */
   7684 
   7685 #if defined(BCM_56970_A0)
   7686     { /* SOC_REG_INT_L2_MGMT_SER_FIFO_CTRL_BCM56970_A0r */
   7687         soc_block_list[5],
   7688         soc_genreg,
   7689         1,
   7690         0,
   7691         0xa2000c00,
   7692         0,
   7693         0,
   7694         1,
   7695         soc_EGR_SER_FIFO_CTRL_BCM56960_A0r_fields,
   7696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7697         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7698         -1,
   7699         -1,
   7700         3,
   7701     },
   7702 #endif /* chips */
   7703 
   7704 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   7705     { /* SOC_REG_INT_L2_MOD_FIFO_CLAIM_AVAILr */
   7706         soc_block_list[87],
   7707         soc_genreg,
   7708         1,
   7709         0,
   7710         0xfe001900,
   7711         0,
   7712         0,
   7713         1,
   7714         soc_L2_MOD_FIFO_CLAIM_AVAILr_fields,
   7715         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   7716         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7717         -1,
   7718         -1,
   7719     },
   7720 #endif /* chips */
   7721 
   7722 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7723     defined(BCM_56870_A0)
   7724     { /* SOC_REG_INT_L2_MOD_FIFO_CLAIM_AVAIL_BCM56870_A0r */
   7725         soc_block_list[5],
   7726         soc_genreg,
   7727         1,
   7728         0,
   7729         0xaa000900,
   7730         0,
   7731         0,
   7732         1,
   7733         soc_L2_MOD_FIFO_CLAIM_AVAIL_BCM56870_A0r_fields,
   7734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7736         -1,
   7737         -1,
   7738         3,
   7739     },
   7740 #endif /* chips */
   7741 
   7742 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7743     { /* SOC_REG_INT_L2_MOD_FIFO_CLAIM_AVAIL_BCM56960_A0r */
   7744         soc_block_list[5],
   7745         soc_genreg,
   7746         1,
   7747         0,
   7748         0x62000900,
   7749         0,
   7750         0,
   7751         1,
   7752         soc_L2_MOD_FIFO_CLAIM_AVAIL_BCM56960_A0r_fields,
   7753         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   7754         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7755         -1,
   7756         -1,
   7757         3,
   7758     },
   7759 #endif /* chips */
   7760 
   7761 #if defined(BCM_56970_A0)
   7762     { /* SOC_REG_INT_L2_MOD_FIFO_CLAIM_AVAIL_BCM56970_A0r */
   7763         soc_block_list[5],
   7764         soc_genreg,
   7765         1,
   7766         0,
   7767         0xa2000900,
   7768         0,
   7769         0,
   7770         1,
   7771         soc_L2_MOD_FIFO_CLAIM_AVAIL_BCM56960_A0r_fields,
   7772         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   7773         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7774         -1,
   7775         -1,
   7776         3,
   7777     },
   7778 #endif /* chips */
   7779 
   7780 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   7781     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   7782     { /* SOC_REG_INT_L2_MOD_FIFO_CNTr */
   7783         soc_block_list[5],
   7784         soc_genreg,
   7785         1,
   7786         0,
   7787         0x608000a,
   7788         0,
   7789         0,
   7790         1,
   7791         soc_L2_MOD_FIFO_CNTr_fields,
   7792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7793         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   7794         -1,
   7795         -1,
   7796     },
   7797 #endif /* chips */
   7798 
   7799 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7800     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7801     defined(BCM_56160_A0)
   7802     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM53400_A0r */
   7803         soc_block_list[5],
   7804         soc_genreg,
   7805         1,
   7806         0,
   7807         0x1e011800,
   7808         SOC_REG_FLAG_RO,
   7809         0,
   7810         1,
   7811         soc_L2_MOD_FIFO_CNT_BCM53400_A0r_fields,
   7812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7813         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7814         -1,
   7815         -1,
   7816     },
   7817 #endif /* chips */
   7818 
   7819 #if defined(BCM_56142_A0)
   7820     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56142_A0r */
   7821         soc_block_list[5],
   7822         soc_genreg,
   7823         1,
   7824         0,
   7825         0x7080144,
   7826         SOC_REG_FLAG_RO,
   7827         0,
   7828         1,
   7829         soc_L2_MOD_FIFO_CNT_BCM56624_A0r_fields,
   7830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7831         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7832         -1,
   7833         -1,
   7834     },
   7835 #endif /* chips */
   7836 
   7837 #if defined(BCM_56150_A0)
   7838     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56150_A0r */
   7839         soc_block_list[5],
   7840         soc_genreg,
   7841         1,
   7842         0,
   7843         0x1e011300,
   7844         SOC_REG_FLAG_RO,
   7845         0,
   7846         1,
   7847         soc_L2_MOD_FIFO_CNT_BCM56450_A0r_fields,
   7848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7849         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7850         -1,
   7851         -1,
   7852     },
   7853 #endif /* chips */
   7854 
   7855 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   7856     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   7857     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56224_A0r */
   7858         soc_block_list[5],
   7859         soc_genreg,
   7860         1,
   7861         0,
   7862         0x6080005,
   7863         0,
   7864         0,
   7865         1,
   7866         soc_L2_MOD_FIFO_CNTr_fields,
   7867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7868         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   7869         -1,
   7870         -1,
   7871     },
   7872 #endif /* chips */
   7873 
   7874 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   7875     defined(BCM_56270_A0)
   7876     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56260_A0r */
   7877         soc_block_list[5],
   7878         soc_genreg,
   7879         1,
   7880         0,
   7881         0x1a011900,
   7882         SOC_REG_FLAG_RO,
   7883         0,
   7884         1,
   7885         soc_L2_MOD_FIFO_CNT_BCM53400_A0r_fields,
   7886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7887         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7888         -1,
   7889         -1,
   7890     },
   7891 #endif /* chips */
   7892 
   7893 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   7894     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56334_A0r */
   7895         soc_block_list[5],
   7896         soc_genreg,
   7897         1,
   7898         0,
   7899         0x708015c,
   7900         SOC_REG_FLAG_RO,
   7901         0,
   7902         1,
   7903         soc_L2_MOD_FIFO_CNT_BCM56624_A0r_fields,
   7904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7905         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7906         -1,
   7907         -1,
   7908     },
   7909 #endif /* chips */
   7910 
   7911 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7912     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56440_A0r */
   7913         soc_block_list[5],
   7914         soc_genreg,
   7915         1,
   7916         0,
   7917         0x6080315,
   7918         SOC_REG_FLAG_RO,
   7919         0,
   7920         1,
   7921         soc_L2_MOD_FIFO_CNT_BCM56624_A0r_fields,
   7922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7923         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7924         -1,
   7925         -1,
   7926     },
   7927 #endif /* chips */
   7928 
   7929 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7930     defined(BCM_56450_B1)
   7931     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56450_A0r */
   7932         soc_block_list[5],
   7933         soc_genreg,
   7934         1,
   7935         0,
   7936         0x1a011600,
   7937         SOC_REG_FLAG_RO,
   7938         0,
   7939         1,
   7940         soc_L2_MOD_FIFO_CNT_BCM56450_A0r_fields,
   7941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7942         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7943         -1,
   7944         -1,
   7945     },
   7946 #endif /* chips */
   7947 
   7948 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   7949     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56560_A0r */
   7950         soc_block_list[5],
   7951         soc_genreg,
   7952         1,
   7953         0,
   7954         0x1b130000,
   7955         SOC_REG_FLAG_RO,
   7956         0,
   7957         1,
   7958         soc_L2_MOD_FIFO_CNT_BCM56960_A0r_fields,
   7959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7960         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7961         -1,
   7962         -1,
   7963     },
   7964 #endif /* chips */
   7965 
   7966 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   7967     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   7968     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56624_A0r */
   7969         soc_block_list[5],
   7970         soc_genreg,
   7971         1,
   7972         0,
   7973         0x708013c,
   7974         SOC_REG_FLAG_RO,
   7975         0,
   7976         1,
   7977         soc_L2_MOD_FIFO_CNT_BCM56624_A0r_fields,
   7978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7979         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7980         -1,
   7981         -1,
   7982     },
   7983 #endif /* chips */
   7984 
   7985 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   7986     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   7987     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   7988     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56634_A0r */
   7989         soc_block_list[5],
   7990         soc_genreg,
   7991         1,
   7992         0,
   7993         0x70801a0,
   7994         SOC_REG_FLAG_RO,
   7995         0,
   7996         1,
   7997         soc_L2_MOD_FIFO_CNT_BCM56624_A0r_fields,
   7998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7999         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   8000         -1,
   8001         -1,
   8002     },
   8003 #endif /* chips */
   8004 
   8005 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   8006     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56640_A0r */
   8007         soc_block_list[87],
   8008         soc_genreg,
   8009         1,
   8010         0,
   8011         0xfe001800,
   8012         SOC_REG_FLAG_RO,
   8013         0,
   8014         1,
   8015         soc_L2_MOD_FIFO_CNT_BCM56640_A0r_fields,
   8016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8017         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8018         -1,
   8019         -1,
   8020     },
   8021 #endif /* chips */
   8022 
   8023 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   8024     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56670_A0r */
   8025         soc_block_list[5],
   8026         soc_genreg,
   8027         1,
   8028         0,
   8029         0x1b140000,
   8030         SOC_REG_FLAG_RO,
   8031         0,
   8032         1,
   8033         soc_L2_MOD_FIFO_CNT_BCM56960_A0r_fields,
   8034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8035         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8036         -1,
   8037         -1,
   8038     },
   8039 #endif /* chips */
   8040 
   8041 #if defined(BCM_56800_A0)
   8042     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56800_A0r */
   8043         soc_block_list[5],
   8044         soc_genreg,
   8045         1,
   8046         0,
   8047         0x608020b,
   8048         0,
   8049         0,
   8050         1,
   8051         soc_L2_MOD_FIFO_CNTr_fields,
   8052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8053         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   8054         -1,
   8055         -1,
   8056     },
   8057 #endif /* chips */
   8058 
   8059 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8060     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56820_A0r */
   8061         soc_block_list[5],
   8062         soc_genreg,
   8063         1,
   8064         0,
   8065         0x608021a,
   8066         SOC_REG_FLAG_RO,
   8067         0,
   8068         1,
   8069         soc_L2_MOD_FIFO_CNT_BCM56624_A0r_fields,
   8070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8071         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   8072         -1,
   8073         -1,
   8074     },
   8075 #endif /* chips */
   8076 
   8077 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   8078     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56840_A0r */
   8079         soc_block_list[5],
   8080         soc_genreg,
   8081         1,
   8082         0,
   8083         0x6080d2d,
   8084         SOC_REG_FLAG_RO,
   8085         0,
   8086         1,
   8087         soc_L2_MOD_FIFO_CNT_BCM56840_A0r_fields,
   8088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8089         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8090         -1,
   8091         -1,
   8092     },
   8093 #endif /* chips */
   8094 
   8095 #if defined(BCM_56850_A0)
   8096     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56850_A0r */
   8097         soc_block_list[5],
   8098         soc_genreg,
   8099         1,
   8100         0,
   8101         0x1b110000,
   8102         SOC_REG_FLAG_RO |
   8103                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8104         0,
   8105         1,
   8106         soc_L2_MOD_FIFO_CNT_BCM56640_A0r_fields,
   8107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8109         -1,
   8110         -1,
   8111     },
   8112 #endif /* chips */
   8113 
   8114 #if defined(BCM_56860_A0)
   8115     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56860_A0r */
   8116         soc_block_list[5],
   8117         soc_genreg,
   8118         1,
   8119         0,
   8120         0x1b130000,
   8121         SOC_REG_FLAG_RO |
   8122                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8123         0,
   8124         1,
   8125         soc_L2_MOD_FIFO_CNT_BCM56640_A0r_fields,
   8126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8127         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8128         -1,
   8129         -1,
   8130     },
   8131 #endif /* chips */
   8132 
   8133 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   8134     defined(BCM_56870_A0)
   8135     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56870_A0r */
   8136         soc_block_list[5],
   8137         soc_genreg,
   8138         1,
   8139         0,
   8140         0xaa000800,
   8141         SOC_REG_FLAG_RO,
   8142         0,
   8143         1,
   8144         soc_L2_MOD_FIFO_CNT_BCM56960_A0r_fields,
   8145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8146         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8147         -1,
   8148         -1,
   8149         3,
   8150     },
   8151 #endif /* chips */
   8152 
   8153 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8154     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56960_A0r */
   8155         soc_block_list[5],
   8156         soc_genreg,
   8157         1,
   8158         0,
   8159         0x62000800,
   8160         SOC_REG_FLAG_RO,
   8161         0,
   8162         1,
   8163         soc_L2_MOD_FIFO_CNT_BCM56960_A0r_fields,
   8164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8165         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8166         -1,
   8167         -1,
   8168         3,
   8169     },
   8170 #endif /* chips */
   8171 
   8172 #if defined(BCM_56970_A0)
   8173     { /* SOC_REG_INT_L2_MOD_FIFO_CNT_BCM56970_A0r */
   8174         soc_block_list[5],
   8175         soc_genreg,
   8176         1,
   8177         0,
   8178         0xa2000800,
   8179         SOC_REG_FLAG_RO,
   8180         0,
   8181         1,
   8182         soc_L2_MOD_FIFO_CNT_BCM56960_A0r_fields,
   8183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8184         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8185         -1,
   8186         -1,
   8187         3,
   8188     },
   8189 #endif /* chips */
   8190 
   8191 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   8192     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   8193     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRLr */
   8194         soc_block_list[5],
   8195         soc_genreg,
   8196         1,
   8197         0,
   8198         0x7080139,
   8199         0,
   8200         0,
   8201         1,
   8202         soc_L2_MOD_FIFO_DBGCTRLr_fields,
   8203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8205         -1,
   8206         -1,
   8207     },
   8208 #endif /* chips */
   8209 
   8210 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8211     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8212     defined(BCM_56160_A0)
   8213     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM53400_A0r */
   8214         soc_block_list[5],
   8215         soc_genreg,
   8216         1,
   8217         0,
   8218         0x1e011500,
   8219         0,
   8220         0,
   8221         1,
   8222         soc_L2_MOD_FIFO_DBGCTRL_BCM53400_A0r_fields,
   8223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8224         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8225         -1,
   8226         -1,
   8227     },
   8228 #endif /* chips */
   8229 
   8230 #if defined(BCM_56142_A0)
   8231     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56142_A0r */
   8232         soc_block_list[5],
   8233         soc_genreg,
   8234         1,
   8235         0,
   8236         0x7080141,
   8237         0,
   8238         0,
   8239         1,
   8240         soc_L2_MOD_FIFO_DBGCTRLr_fields,
   8241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8242         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8243         -1,
   8244         -1,
   8245     },
   8246 #endif /* chips */
   8247 
   8248 #if defined(BCM_56150_A0)
   8249     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56150_A0r */
   8250         soc_block_list[5],
   8251         soc_genreg,
   8252         1,
   8253         0,
   8254         0x1e011000,
   8255         0,
   8256         0,
   8257         1,
   8258         soc_L2_MOD_FIFO_DBGCTRL_BCM56450_A0r_fields,
   8259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8260         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8261         -1,
   8262         -1,
   8263     },
   8264 #endif /* chips */
   8265 
   8266 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   8267     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56260_A0r */
   8268         soc_block_list[5],
   8269         soc_genreg,
   8270         1,
   8271         0,
   8272         0x1a011600,
   8273         0,
   8274         0,
   8275         1,
   8276         soc_L2_MOD_FIFO_DBGCTRL_BCM56260_A0r_fields,
   8277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8278         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8279         -1,
   8280         -1,
   8281     },
   8282 #endif /* chips */
   8283 
   8284 #if defined(BCM_56270_A0)
   8285     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56270_A0r */
   8286         soc_block_list[5],
   8287         soc_genreg,
   8288         1,
   8289         0,
   8290         0x1a011600,
   8291         0,
   8292         0,
   8293         1,
   8294         soc_L2_MOD_FIFO_DBGCTRL_BCM53400_A0r_fields,
   8295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8296         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8297         -1,
   8298         -1,
   8299     },
   8300 #endif /* chips */
   8301 
   8302 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   8303     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56334_A0r */
   8304         soc_block_list[5],
   8305         soc_genreg,
   8306         1,
   8307         0,
   8308         0x7080159,
   8309         0,
   8310         0,
   8311         1,
   8312         soc_L2_MOD_FIFO_DBGCTRLr_fields,
   8313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8314         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8315         -1,
   8316         -1,
   8317     },
   8318 #endif /* chips */
   8319 
   8320 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8321     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56440_A0r */
   8322         soc_block_list[5],
   8323         soc_genreg,
   8324         1,
   8325         0,
   8326         0x6080312,
   8327         0,
   8328         0,
   8329         1,
   8330         soc_L2_MOD_FIFO_DBGCTRL_BCM56440_A0r_fields,
   8331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8332         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8333         -1,
   8334         -1,
   8335     },
   8336 #endif /* chips */
   8337 
   8338 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8339     defined(BCM_56450_B1)
   8340     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56450_A0r */
   8341         soc_block_list[5],
   8342         soc_genreg,
   8343         1,
   8344         0,
   8345         0x1a011300,
   8346         0,
   8347         0,
   8348         1,
   8349         soc_L2_MOD_FIFO_DBGCTRL_BCM56450_A0r_fields,
   8350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8351         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8352         -1,
   8353         -1,
   8354     },
   8355 #endif /* chips */
   8356 
   8357 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   8358     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56560_A0r */
   8359         soc_block_list[5],
   8360         soc_genreg,
   8361         1,
   8362         0,
   8363         0x1b100000,
   8364         0,
   8365         0,
   8366         2,
   8367         soc_L2_MOD_FIFO_DBGCTRL_BCM56560_A0r_fields,
   8368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8370         -1,
   8371         -1,
   8372     },
   8373 #endif /* chips */
   8374 
   8375 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8376     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8377     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8378     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56634_A0r */
   8379         soc_block_list[5],
   8380         soc_genreg,
   8381         1,
   8382         0,
   8383         0x708019d,
   8384         0,
   8385         0,
   8386         1,
   8387         soc_L2_MOD_FIFO_DBGCTRLr_fields,
   8388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8389         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8390         -1,
   8391         -1,
   8392     },
   8393 #endif /* chips */
   8394 
   8395 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   8396     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56670_A0r */
   8397         soc_block_list[5],
   8398         soc_genreg,
   8399         1,
   8400         0,
   8401         0x1b110000,
   8402         0,
   8403         0,
   8404         2,
   8405         soc_L2_MOD_FIFO_DBGCTRL_BCM56560_A0r_fields,
   8406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8408         -1,
   8409         -1,
   8410     },
   8411 #endif /* chips */
   8412 
   8413 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8414     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56820_A0r */
   8415         soc_block_list[5],
   8416         soc_genreg,
   8417         1,
   8418         0,
   8419         0x6080c08,
   8420         0,
   8421         0,
   8422         2,
   8423         soc_CFAPMEMDEBUG_BCM56820_A0r_fields,
   8424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8426         -1,
   8427         -1,
   8428     },
   8429 #endif /* chips */
   8430 
   8431 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   8432     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56840_A0r */
   8433         soc_block_list[5],
   8434         soc_genreg,
   8435         1,
   8436         0,
   8437         0x6080d2a,
   8438         0,
   8439         0,
   8440         2,
   8441         soc_L2_MOD_FIFO_DBGCTRL_BCM56840_A0r_fields,
   8442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8443         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8444         -1,
   8445         -1,
   8446     },
   8447 #endif /* chips */
   8448 
   8449 #if defined(BCM_56850_A0)
   8450     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56850_A0r */
   8451         soc_block_list[5],
   8452         soc_genreg,
   8453         1,
   8454         0,
   8455         0x1b0e0000,
   8456         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8457         0,
   8458         2,
   8459         soc_L2_MOD_FIFO_DBGCTRL_BCM56850_A0r_fields,
   8460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8461         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8462         -1,
   8463         -1,
   8464     },
   8465 #endif /* chips */
   8466 
   8467 #if defined(BCM_56860_A0)
   8468     { /* SOC_REG_INT_L2_MOD_FIFO_DBGCTRL_BCM56860_A0r */
   8469         soc_block_list[5],
   8470         soc_genreg,
   8471         1,
   8472         0,
   8473         0x1b100000,
   8474         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8475         0,
   8476         2,
   8477         soc_L2_MOD_FIFO_DBGCTRL_BCM56860_A0r_fields,
   8478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8479         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8480         -1,
   8481         -1,
   8482     },
   8483 #endif /* chips */
   8484 
   8485 #if defined(BCM_56640_A0)
   8486     { /* SOC_REG_INT_L2_MOD_FIFO_ENABLEr */
   8487         soc_block_list[87],
   8488         soc_genreg,
   8489         1,
   8490         0,
   8491         0xfe001000,
   8492         0,
   8493         0,
   8494         6,
   8495         soc_L2_MOD_FIFO_ENABLEr_fields,
   8496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8497         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   8498         -1,
   8499         -1,
   8500     },
   8501 #endif /* chips */
   8502 
   8503 #if defined(BCM_56340_A0)
   8504     { /* SOC_REG_INT_L2_MOD_FIFO_ENABLE_BCM56340_A0r */
   8505         soc_block_list[87],
   8506         soc_genreg,
   8507         1,
   8508         0,
   8509         0xfe001000,
   8510         0,
   8511         0,
   8512         6,
   8513         soc_L2_MOD_FIFO_ENABLE_BCM56340_A0r_fields,
   8514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8515         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   8516         -1,
   8517         -1,
   8518     },
   8519 #endif /* chips */
   8520 
   8521 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   8522     defined(BCM_56870_A0)
   8523     { /* SOC_REG_INT_L2_MOD_FIFO_ENABLE_BCM56870_A0r */
   8524         soc_block_list[5],
   8525         soc_genreg,
   8526         1,
   8527         0,
   8528         0xaa000500,
   8529         0,
   8530         0,
   8531         4,
   8532         soc_L2_MOD_FIFO_ENABLE_BCM56870_A0r_fields,
   8533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8534         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8535         -1,
   8536         -1,
   8537         3,
   8538     },
   8539 #endif /* chips */
   8540 
   8541 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8542     { /* SOC_REG_INT_L2_MOD_FIFO_ENABLE_BCM56960_A0r */
   8543         soc_block_list[5],
   8544         soc_genreg,
   8545         1,
   8546         0,
   8547         0x62000500,
   8548         0,
   8549         0,
   8550         5,
   8551         soc_L2_MOD_FIFO_ENABLE_BCM56960_A0r_fields,
   8552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8553         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   8554         -1,
   8555         -1,
   8556         3,
   8557     },
   8558 #endif /* chips */
   8559 
   8560 #if defined(BCM_56970_A0)
   8561     { /* SOC_REG_INT_L2_MOD_FIFO_ENABLE_BCM56970_A0r */
   8562         soc_block_list[5],
   8563         soc_genreg,
   8564         1,
   8565         0,
   8566         0xa2000500,
   8567         0,
   8568         0,
   8569         5,
   8570         soc_L2_MOD_FIFO_ENABLE_BCM56960_A0r_fields,
   8571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8572         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   8573         -1,
   8574         -1,
   8575         3,
   8576     },
   8577 #endif /* chips */
   8578 
   8579 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   8580     { /* SOC_REG_INT_L2_MOD_FIFO_MEMORY_CONTROL_0r */
   8581         soc_block_list[87],
   8582         soc_genreg,
   8583         1,
   8584         0,
   8585         0xfe009200,
   8586         0,
   8587         0,
   8588         2,
   8589         soc_L2_MOD_FIFO_MEMORY_CONTROL_0r_fields,
   8590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8592         -1,
   8593         -1,
   8594     },
   8595 #endif /* chips */
   8596 
   8597 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   8598     defined(BCM_56870_A0)
   8599     { /* SOC_REG_INT_L2_MOD_FIFO_MEMORY_CONTROL_0_BCM56870_A0r */
   8600         soc_block_list[5],
   8601         soc_genreg,
   8602         1,
   8603         0,
   8604         0xaa002000,
   8605         0,
   8606         0,
   8607         4,
   8608         soc_L2_MOD_FIFO_MEMORY_CONTROL_0_BCM56960_A0r_fields,
   8609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8610         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8611         -1,
   8612         -1,
   8613         3,
   8614     },
   8615 #endif /* chips */
   8616 
   8617 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8618     { /* SOC_REG_INT_L2_MOD_FIFO_MEMORY_CONTROL_0_BCM56960_A0r */
   8619         soc_block_list[5],
   8620         soc_genreg,
   8621         1,
   8622         0,
   8623         0x62002000,
   8624         0,
   8625         0,
   8626         4,
   8627         soc_L2_MOD_FIFO_MEMORY_CONTROL_0_BCM56960_A0r_fields,
   8628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8630         -1,
   8631         -1,
   8632         3,
   8633     },
   8634 #endif /* chips */
   8635 
   8636 #if defined(BCM_56970_A0)
   8637     { /* SOC_REG_INT_L2_MOD_FIFO_MEMORY_CONTROL_0_BCM56970_A0r */
   8638         soc_block_list[5],
   8639         soc_genreg,
   8640         1,
   8641         0,
   8642         0xa2002000,
   8643         0,
   8644         0,
   8645         4,
   8646         soc_L2_MOD_FIFO_MEMORY_CONTROL_0_BCM56960_A0r_fields,
   8647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8649         -1,
   8650         -1,
   8651         3,
   8652     },
   8653 #endif /* chips */
   8654 
   8655 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8656     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8657     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8658     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROLr */
   8659         soc_block_list[5],
   8660         soc_genreg,
   8661         1,
   8662         0,
   8663         0x708018d,
   8664         0,
   8665         0,
   8666         1,
   8667         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   8668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8669         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8670         -1,
   8671         -1,
   8672     },
   8673 #endif /* chips */
   8674 
   8675 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   8676     defined(BCM_56270_A0)
   8677     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56260_A0r */
   8678         soc_block_list[5],
   8679         soc_genreg,
   8680         1,
   8681         0,
   8682         0x1a011a00,
   8683         0,
   8684         0,
   8685         1,
   8686         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
   8687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8688         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8689         -1,
   8690         -1,
   8691     },
   8692 #endif /* chips */
   8693 
   8694 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8695     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56440_A0r */
   8696         soc_block_list[5],
   8697         soc_genreg,
   8698         1,
   8699         0,
   8700         0x6080316,
   8701         0,
   8702         0,
   8703         1,
   8704         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   8705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8706         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8707         -1,
   8708         -1,
   8709     },
   8710 #endif /* chips */
   8711 
   8712 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8713     defined(BCM_56450_B1)
   8714     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56450_A0r */
   8715         soc_block_list[5],
   8716         soc_genreg,
   8717         1,
   8718         0,
   8719         0x1a011700,
   8720         0,
   8721         0,
   8722         1,
   8723         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
   8724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8725         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8726         -1,
   8727         -1,
   8728     },
   8729 #endif /* chips */
   8730 
   8731 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   8732     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   8733     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56560_A0r */
   8734         soc_block_list[5],
   8735         soc_genreg,
   8736         1,
   8737         0,
   8738         0x1b0e0000,
   8739         0,
   8740         0,
   8741         1,
   8742         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
   8743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8744         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8745         -1,
   8746         -1,
   8747     },
   8748 #endif /* chips */
   8749 
   8750 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   8751     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56640_A0r */
   8752         soc_block_list[87],
   8753         soc_genreg,
   8754         1,
   8755         0,
   8756         0xfe001c00,
   8757         0,
   8758         0,
   8759         1,
   8760         soc_L2_MOD_FIFO_PARITY_CONTROLr_fields,
   8761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8762         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8763         -1,
   8764         -1,
   8765     },
   8766 #endif /* chips */
   8767 
   8768 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   8769     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56670_A0r */
   8770         soc_block_list[5],
   8771         soc_genreg,
   8772         1,
   8773         0,
   8774         0x1b0f0000,
   8775         0,
   8776         0,
   8777         1,
   8778         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
   8779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8781         -1,
   8782         -1,
   8783     },
   8784 #endif /* chips */
   8785 
   8786 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   8787     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56840_A0r */
   8788         soc_block_list[5],
   8789         soc_genreg,
   8790         1,
   8791         0,
   8792         0x6080d26,
   8793         0,
   8794         0,
   8795         1,
   8796         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
   8797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8798         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8799         -1,
   8800         -1,
   8801     },
   8802 #endif /* chips */
   8803 
   8804 #if defined(BCM_56850_A0)
   8805     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56850_A0r */
   8806         soc_block_list[5],
   8807         soc_genreg,
   8808         1,
   8809         0,
   8810         0x1b0c0000,
   8811         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8812         0,
   8813         1,
   8814         soc_FT_CNTR_SER_CONTROLr_fields,
   8815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8816         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8817         -1,
   8818         -1,
   8819     },
   8820 #endif /* chips */
   8821 
   8822 #if defined(BCM_56860_A0)
   8823     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56860_A0r */
   8824         soc_block_list[5],
   8825         soc_genreg,
   8826         1,
   8827         0,
   8828         0x1b0e0000,
   8829         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8830         0,
   8831         1,
   8832         soc_FT_CNTR_SER_CONTROLr_fields,
   8833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8835         -1,
   8836         -1,
   8837     },
   8838 #endif /* chips */
   8839 
   8840 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   8841     defined(BCM_56870_A0)
   8842     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56870_A0r */
   8843         soc_block_list[5],
   8844         soc_genreg,
   8845         1,
   8846         0,
   8847         0xaa002100,
   8848         0,
   8849         0,
   8850         2,
   8851         soc_L2_MOD_FIFO_PARITY_CONTROL_BCM56970_A0r_fields,
   8852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8853         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   8854         -1,
   8855         -1,
   8856         3,
   8857     },
   8858 #endif /* chips */
   8859 
   8860 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8861     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56960_A0r */
   8862         soc_block_list[5],
   8863         soc_genreg,
   8864         1,
   8865         0,
   8866         0x62002100,
   8867         0,
   8868         0,
   8869         1,
   8870         soc_L2_MOD_FIFO_PARITY_CONTROL_BCM56960_A0r_fields,
   8871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8872         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8873         -1,
   8874         -1,
   8875         3,
   8876     },
   8877 #endif /* chips */
   8878 
   8879 #if defined(BCM_56970_A0)
   8880     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_CONTROL_BCM56970_A0r */
   8881         soc_block_list[5],
   8882         soc_genreg,
   8883         1,
   8884         0,
   8885         0xa2002100,
   8886         0,
   8887         0,
   8888         2,
   8889         soc_L2_MOD_FIFO_PARITY_CONTROL_BCM56970_A0r_fields,
   8890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8891         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   8892         -1,
   8893         -1,
   8894         3,
   8895     },
   8896 #endif /* chips */
   8897 
   8898 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8899     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8900     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8901     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_STATUS_INTRr */
   8902         soc_block_list[5],
   8903         soc_genreg,
   8904         1,
   8905         0,
   8906         0x708018e,
   8907         0,
   8908         0,
   8909         3,
   8910         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTRr_fields,
   8911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8912         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   8913         -1,
   8914         -1,
   8915     },
   8916 #endif /* chips */
   8917 
   8918 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8919     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_STATUS_INTR_BCM56440_A0r */
   8920         soc_block_list[5],
   8921         soc_genreg,
   8922         1,
   8923         0,
   8924         0x6080317,
   8925         0,
   8926         0,
   8927         3,
   8928         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTRr_fields,
   8929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8930         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   8931         -1,
   8932         -1,
   8933     },
   8934 #endif /* chips */
   8935 
   8936 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8937     defined(BCM_56450_B1)
   8938     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_STATUS_INTR_BCM56450_A0r */
   8939         soc_block_list[5],
   8940         soc_genreg,
   8941         1,
   8942         0,
   8943         0x1a011800,
   8944         0,
   8945         0,
   8946         3,
   8947         soc_L2_MOD_FIFO_PARITY_STATUS_INTRr_fields,
   8948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8949         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   8950         -1,
   8951         -1,
   8952     },
   8953 #endif /* chips */
   8954 
   8955 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   8956     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_STATUS_INTR_BCM56840_A0r */
   8957         soc_block_list[5],
   8958         soc_genreg,
   8959         1,
   8960         0,
   8961         0x6080d27,
   8962         0,
   8963         0,
   8964         3,
   8965         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
   8966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8967         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8968         -1,
   8969         -1,
   8970     },
   8971 #endif /* chips */
   8972 
   8973 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8974     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8975     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8976     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_STATUS_NACKr */
   8977         soc_block_list[5],
   8978         soc_genreg,
   8979         1,
   8980         0,
   8981         0x708018f,
   8982         0,
   8983         0,
   8984         3,
   8985         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTRr_fields,
   8986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8987         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   8988         -1,
   8989         -1,
   8990     },
   8991 #endif /* chips */
   8992 
   8993 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8994     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_STATUS_NACK_BCM56440_A0r */
   8995         soc_block_list[5],
   8996         soc_genreg,
   8997         1,
   8998         0,
   8999         0x6080318,
   9000         0,
   9001         0,
   9002         3,
   9003         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTRr_fields,
   9004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9005         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   9006         -1,
   9007         -1,
   9008     },
   9009 #endif /* chips */
   9010 
   9011 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9012     defined(BCM_56450_B1)
   9013     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_STATUS_NACK_BCM56450_A0r */
   9014         soc_block_list[5],
   9015         soc_genreg,
   9016         1,
   9017         0,
   9018         0x1a011900,
   9019         0,
   9020         0,
   9021         3,
   9022         soc_L2_MOD_FIFO_PARITY_STATUS_INTRr_fields,
   9023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9024         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   9025         -1,
   9026         -1,
   9027     },
   9028 #endif /* chips */
   9029 
   9030 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   9031     { /* SOC_REG_INT_L2_MOD_FIFO_PARITY_STATUS_NACK_BCM56840_A0r */
   9032         soc_block_list[5],
   9033         soc_genreg,
   9034         1,
   9035         0,
   9036         0x6080d28,
   9037         0,
   9038         0,
   9039         3,
   9040         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
   9041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9042         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9043         -1,
   9044         -1,
   9045     },
   9046 #endif /* chips */
   9047 
   9048 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9049     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9050     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTRr */
   9051         soc_block_list[5],
   9052         soc_genreg,
   9053         1,
   9054         0,
   9055         0x708013a,
   9056         0,
   9057         0,
   9058         1,
   9059         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9061         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9062         -1,
   9063         -1,
   9064     },
   9065 #endif /* chips */
   9066 
   9067 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   9068     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   9069     defined(BCM_56160_A0)
   9070     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM53400_A0r */
   9071         soc_block_list[5],
   9072         soc_genreg,
   9073         1,
   9074         0,
   9075         0x1e011600,
   9076         0,
   9077         0,
   9078         1,
   9079         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9081         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9082         -1,
   9083         -1,
   9084     },
   9085 #endif /* chips */
   9086 
   9087 #if defined(BCM_56142_A0)
   9088     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56142_A0r */
   9089         soc_block_list[5],
   9090         soc_genreg,
   9091         1,
   9092         0,
   9093         0x7080142,
   9094         0,
   9095         0,
   9096         1,
   9097         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9099         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9100         -1,
   9101         -1,
   9102     },
   9103 #endif /* chips */
   9104 
   9105 #if defined(BCM_56150_A0)
   9106     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56150_A0r */
   9107         soc_block_list[5],
   9108         soc_genreg,
   9109         1,
   9110         0,
   9111         0x1e011100,
   9112         0,
   9113         0,
   9114         1,
   9115         soc_L2_MOD_FIFO_RD_PTR_BCM56640_A0r_fields,
   9116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9117         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9118         -1,
   9119         -1,
   9120     },
   9121 #endif /* chips */
   9122 
   9123 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   9124     defined(BCM_56270_A0)
   9125     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56260_A0r */
   9126         soc_block_list[5],
   9127         soc_genreg,
   9128         1,
   9129         0,
   9130         0x1a011700,
   9131         0,
   9132         0,
   9133         1,
   9134         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9136         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9137         -1,
   9138         -1,
   9139     },
   9140 #endif /* chips */
   9141 
   9142 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   9143     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56334_A0r */
   9144         soc_block_list[5],
   9145         soc_genreg,
   9146         1,
   9147         0,
   9148         0x708015a,
   9149         0,
   9150         0,
   9151         1,
   9152         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9154         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9155         -1,
   9156         -1,
   9157     },
   9158 #endif /* chips */
   9159 
   9160 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9161     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56440_A0r */
   9162         soc_block_list[5],
   9163         soc_genreg,
   9164         1,
   9165         0,
   9166         0x6080313,
   9167         0,
   9168         0,
   9169         1,
   9170         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9172         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9173         -1,
   9174         -1,
   9175     },
   9176 #endif /* chips */
   9177 
   9178 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9179     defined(BCM_56450_B1)
   9180     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56450_A0r */
   9181         soc_block_list[5],
   9182         soc_genreg,
   9183         1,
   9184         0,
   9185         0x1a011400,
   9186         0,
   9187         0,
   9188         1,
   9189         soc_L2_MOD_FIFO_RD_PTR_BCM56640_A0r_fields,
   9190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9191         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9192         -1,
   9193         -1,
   9194     },
   9195 #endif /* chips */
   9196 
   9197 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   9198     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56560_A0r */
   9199         soc_block_list[5],
   9200         soc_genreg,
   9201         1,
   9202         0,
   9203         0x1b110000,
   9204         0,
   9205         0,
   9206         1,
   9207         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9209         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9210         -1,
   9211         -1,
   9212     },
   9213 #endif /* chips */
   9214 
   9215 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9216     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9217     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9218     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56634_A0r */
   9219         soc_block_list[5],
   9220         soc_genreg,
   9221         1,
   9222         0,
   9223         0x708019e,
   9224         0,
   9225         0,
   9226         1,
   9227         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9229         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9230         -1,
   9231         -1,
   9232     },
   9233 #endif /* chips */
   9234 
   9235 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   9236     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56640_A0r */
   9237         soc_block_list[87],
   9238         soc_genreg,
   9239         1,
   9240         0,
   9241         0xfe001600,
   9242         0,
   9243         0,
   9244         1,
   9245         soc_L2_MOD_FIFO_RD_PTR_BCM56640_A0r_fields,
   9246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9247         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9248         -1,
   9249         -1,
   9250     },
   9251 #endif /* chips */
   9252 
   9253 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9254     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56670_A0r */
   9255         soc_block_list[5],
   9256         soc_genreg,
   9257         1,
   9258         0,
   9259         0x1b120000,
   9260         0,
   9261         0,
   9262         1,
   9263         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9265         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9266         -1,
   9267         -1,
   9268     },
   9269 #endif /* chips */
   9270 
   9271 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9272     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56820_A0r */
   9273         soc_block_list[5],
   9274         soc_genreg,
   9275         1,
   9276         0,
   9277         0x608021b,
   9278         0,
   9279         0,
   9280         1,
   9281         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9283         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9284         -1,
   9285         -1,
   9286     },
   9287 #endif /* chips */
   9288 
   9289 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   9290     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56840_A0r */
   9291         soc_block_list[5],
   9292         soc_genreg,
   9293         1,
   9294         0,
   9295         0x6080d2b,
   9296         0,
   9297         0,
   9298         1,
   9299         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9301         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9302         -1,
   9303         -1,
   9304     },
   9305 #endif /* chips */
   9306 
   9307 #if defined(BCM_56850_A0)
   9308     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56850_A0r */
   9309         soc_block_list[5],
   9310         soc_genreg,
   9311         1,
   9312         0,
   9313         0x1b0f0000,
   9314         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9315         0,
   9316         1,
   9317         soc_L2_MOD_FIFO_RD_PTR_BCM56640_A0r_fields,
   9318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9319         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9320         -1,
   9321         -1,
   9322     },
   9323 #endif /* chips */
   9324 
   9325 #if defined(BCM_56860_A0)
   9326     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56860_A0r */
   9327         soc_block_list[5],
   9328         soc_genreg,
   9329         1,
   9330         0,
   9331         0x1b110000,
   9332         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9333         0,
   9334         1,
   9335         soc_L2_MOD_FIFO_RD_PTR_BCM56640_A0r_fields,
   9336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9337         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9338         -1,
   9339         -1,
   9340     },
   9341 #endif /* chips */
   9342 
   9343 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   9344     defined(BCM_56870_A0)
   9345     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56870_A0r */
   9346         soc_block_list[5],
   9347         soc_genreg,
   9348         1,
   9349         0,
   9350         0xaa000600,
   9351         0,
   9352         0,
   9353         1,
   9354         soc_L2_MOD_FIFO_WR_PTR_BCM56560_A0r_fields,
   9355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9357         -1,
   9358         -1,
   9359         3,
   9360     },
   9361 #endif /* chips */
   9362 
   9363 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9364     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56960_A0r */
   9365         soc_block_list[5],
   9366         soc_genreg,
   9367         1,
   9368         0,
   9369         0x62000600,
   9370         0,
   9371         0,
   9372         1,
   9373         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9375         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9376         -1,
   9377         -1,
   9378         3,
   9379     },
   9380 #endif /* chips */
   9381 
   9382 #if defined(BCM_56970_A0)
   9383     { /* SOC_REG_INT_L2_MOD_FIFO_RD_PTR_BCM56970_A0r */
   9384         soc_block_list[5],
   9385         soc_genreg,
   9386         1,
   9387         0,
   9388         0xa2000600,
   9389         0,
   9390         0,
   9391         1,
   9392         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9394         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9395         -1,
   9396         -1,
   9397         3,
   9398     },
   9399 #endif /* chips */
   9400 
   9401 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9402     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9403     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTRr */
   9404         soc_block_list[5],
   9405         soc_genreg,
   9406         1,
   9407         0,
   9408         0x708013b,
   9409         0,
   9410         0,
   9411         1,
   9412         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9414         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9415         -1,
   9416         -1,
   9417     },
   9418 #endif /* chips */
   9419 
   9420 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   9421     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   9422     defined(BCM_56160_A0)
   9423     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM53400_A0r */
   9424         soc_block_list[5],
   9425         soc_genreg,
   9426         1,
   9427         0,
   9428         0x1e011700,
   9429         0,
   9430         0,
   9431         1,
   9432         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9434         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9435         -1,
   9436         -1,
   9437     },
   9438 #endif /* chips */
   9439 
   9440 #if defined(BCM_56142_A0)
   9441     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56142_A0r */
   9442         soc_block_list[5],
   9443         soc_genreg,
   9444         1,
   9445         0,
   9446         0x7080143,
   9447         0,
   9448         0,
   9449         1,
   9450         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9452         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9453         -1,
   9454         -1,
   9455     },
   9456 #endif /* chips */
   9457 
   9458 #if defined(BCM_56150_A0)
   9459     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56150_A0r */
   9460         soc_block_list[5],
   9461         soc_genreg,
   9462         1,
   9463         0,
   9464         0x1e011200,
   9465         0,
   9466         0,
   9467         1,
   9468         soc_L2_MOD_FIFO_RD_PTR_BCM56640_A0r_fields,
   9469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9470         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9471         -1,
   9472         -1,
   9473     },
   9474 #endif /* chips */
   9475 
   9476 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   9477     defined(BCM_56270_A0)
   9478     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56260_A0r */
   9479         soc_block_list[5],
   9480         soc_genreg,
   9481         1,
   9482         0,
   9483         0x1a011800,
   9484         0,
   9485         0,
   9486         1,
   9487         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9489         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9490         -1,
   9491         -1,
   9492     },
   9493 #endif /* chips */
   9494 
   9495 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   9496     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56334_A0r */
   9497         soc_block_list[5],
   9498         soc_genreg,
   9499         1,
   9500         0,
   9501         0x708015b,
   9502         0,
   9503         0,
   9504         1,
   9505         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9507         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9508         -1,
   9509         -1,
   9510     },
   9511 #endif /* chips */
   9512 
   9513 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9514     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56440_A0r */
   9515         soc_block_list[5],
   9516         soc_genreg,
   9517         1,
   9518         0,
   9519         0x6080314,
   9520         0,
   9521         0,
   9522         1,
   9523         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9525         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9526         -1,
   9527         -1,
   9528     },
   9529 #endif /* chips */
   9530 
   9531 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9532     defined(BCM_56450_B1)
   9533     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56450_A0r */
   9534         soc_block_list[5],
   9535         soc_genreg,
   9536         1,
   9537         0,
   9538         0x1a011500,
   9539         0,
   9540         0,
   9541         1,
   9542         soc_L2_MOD_FIFO_RD_PTR_BCM56640_A0r_fields,
   9543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9544         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9545         -1,
   9546         -1,
   9547     },
   9548 #endif /* chips */
   9549 
   9550 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   9551     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56560_A0r */
   9552         soc_block_list[5],
   9553         soc_genreg,
   9554         1,
   9555         0,
   9556         0x1b120000,
   9557         0,
   9558         0,
   9559         1,
   9560         soc_L2_MOD_FIFO_WR_PTR_BCM56560_A0r_fields,
   9561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9562         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9563         -1,
   9564         -1,
   9565     },
   9566 #endif /* chips */
   9567 
   9568 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9569     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9570     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9571     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56634_A0r */
   9572         soc_block_list[5],
   9573         soc_genreg,
   9574         1,
   9575         0,
   9576         0x708019f,
   9577         0,
   9578         0,
   9579         1,
   9580         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9582         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9583         -1,
   9584         -1,
   9585     },
   9586 #endif /* chips */
   9587 
   9588 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   9589     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56640_A0r */
   9590         soc_block_list[87],
   9591         soc_genreg,
   9592         1,
   9593         0,
   9594         0xfe001700,
   9595         0,
   9596         0,
   9597         1,
   9598         soc_L2_MOD_FIFO_RD_PTR_BCM56640_A0r_fields,
   9599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9600         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9601         -1,
   9602         -1,
   9603     },
   9604 #endif /* chips */
   9605 
   9606 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9607     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56670_A0r */
   9608         soc_block_list[5],
   9609         soc_genreg,
   9610         1,
   9611         0,
   9612         0x1b130000,
   9613         0,
   9614         0,
   9615         1,
   9616         soc_L2_MOD_FIFO_WR_PTR_BCM56560_A0r_fields,
   9617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9618         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9619         -1,
   9620         -1,
   9621     },
   9622 #endif /* chips */
   9623 
   9624 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9625     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56820_A0r */
   9626         soc_block_list[5],
   9627         soc_genreg,
   9628         1,
   9629         0,
   9630         0x608021c,
   9631         0,
   9632         0,
   9633         1,
   9634         soc_L2_MOD_FIFO_RD_PTRr_fields,
   9635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9636         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9637         -1,
   9638         -1,
   9639     },
   9640 #endif /* chips */
   9641 
   9642 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   9643     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56840_A0r */
   9644         soc_block_list[5],
   9645         soc_genreg,
   9646         1,
   9647         0,
   9648         0x6080d2c,
   9649         0,
   9650         0,
   9651         1,
   9652         soc_L2_MOD_FIFO_WR_PTRr_fields,
   9653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9654         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9655         -1,
   9656         -1,
   9657     },
   9658 #endif /* chips */
   9659 
   9660 #if defined(BCM_56850_A0)
   9661     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56850_A0r */
   9662         soc_block_list[5],
   9663         soc_genreg,
   9664         1,
   9665         0,
   9666         0x1b100000,
   9667         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9668         0,
   9669         1,
   9670         soc_L2_MOD_FIFO_WR_PTR_BCM56850_A0r_fields,
   9671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9672         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9673         -1,
   9674         -1,
   9675     },
   9676 #endif /* chips */
   9677 
   9678 #if defined(BCM_56860_A0)
   9679     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56860_A0r */
   9680         soc_block_list[5],
   9681         soc_genreg,
   9682         1,
   9683         0,
   9684         0x1b120000,
   9685         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9686         0,
   9687         1,
   9688         soc_L2_MOD_FIFO_WR_PTR_BCM56850_A0r_fields,
   9689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9690         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9691         -1,
   9692         -1,
   9693     },
   9694 #endif /* chips */
   9695 
   9696 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   9697     defined(BCM_56870_A0)
   9698     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56870_A0r */
   9699         soc_block_list[5],
   9700         soc_genreg,
   9701         1,
   9702         0,
   9703         0xaa000700,
   9704         0,
   9705         0,
   9706         1,
   9707         soc_L2_MOD_FIFO_WR_PTR_BCM56560_A0r_fields,
   9708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9710         -1,
   9711         -1,
   9712         3,
   9713     },
   9714 #endif /* chips */
   9715 
   9716 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9717     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56960_A0r */
   9718         soc_block_list[5],
   9719         soc_genreg,
   9720         1,
   9721         0,
   9722         0x62000700,
   9723         0,
   9724         0,
   9725         1,
   9726         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9728         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9729         -1,
   9730         -1,
   9731         3,
   9732     },
   9733 #endif /* chips */
   9734 
   9735 #if defined(BCM_56970_A0)
   9736     { /* SOC_REG_INT_L2_MOD_FIFO_WR_PTR_BCM56970_A0r */
   9737         soc_block_list[5],
   9738         soc_genreg,
   9739         1,
   9740         0,
   9741         0xa2000700,
   9742         0,
   9743         0,
   9744         1,
   9745         soc_L2_MOD_FIFO_RD_PTR_BCM53400_A0r_fields,
   9746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9747         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9748         -1,
   9749         -1,
   9750         3,
   9751     },
   9752 #endif /* chips */
   9753 
   9754 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
   9755     defined(BCM_53570_B0) || defined(BCM_56160_A0)
   9756     { /* SOC_REG_INT_L2_NON_LEARNED_MESSAGE_MACSAr */
   9757         soc_block_list[5],
   9758         soc_genreg,
   9759         1,
   9760         0,
   9761         0x1e000b00,
   9762         SOC_REG_FLAG_64_BITS,
   9763         0,
   9764         1,
   9765         soc_L2_NON_LEARNED_MESSAGE_MACSAr_fields,
   9766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9767         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   9768         -1,
   9769         -1,
   9770     },
   9771 #endif /* chips */
   9772 
   9773 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
   9774     { /* SOC_REG_INT_L2_NON_LEARNED_MESSAGE_VLAN_PORTr */
   9775         soc_block_list[5],
   9776         soc_genreg,
   9777         1,
   9778         0,
   9779         0x1e000c00,
   9780         0,
   9781         0,
   9782         2,
   9783         soc_L2_NON_LEARNED_MESSAGE_VLAN_PORTr_fields,
   9784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9785         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   9786         -1,
   9787         -1,
   9788     },
   9789 #endif /* chips */
   9790 
   9791 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   9792     { /* SOC_REG_INT_L2_NON_LEARNED_MESSAGE_VLAN_PORT_BCM53570_A0r */
   9793         soc_block_list[5],
   9794         soc_genreg,
   9795         1,
   9796         0,
   9797         0x1e000c00,
   9798         0,
   9799         0,
   9800         2,
   9801         soc_L2_NON_LEARNED_MESSAGE_VLAN_PORT_BCM53570_A0r_fields,
   9802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9803         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   9804         -1,
   9805         -1,
   9806     },
   9807 #endif /* chips */
   9808 
   9809 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
   9810     { /* SOC_REG_INT_L2_PYLD_INIT_SHIFT_AMOUNTr */
   9811         soc_block_list[5],
   9812         soc_genreg,
   9813         1,
   9814         0,
   9815         0x5a000100,
   9816         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9817         0,
   9818         1,
   9819         soc_L2_PYLD_INIT_SHIFT_AMOUNTr_fields,
   9820         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
   9821         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9822         -1,
   9823         -1,
   9824         3,
   9825     },
   9826 #endif /* chips */
   9827 
   9828 #if defined(BCM_56370_A0)
   9829     { /* SOC_REG_INT_L2_PYLD_INIT_SHIFT_AMOUNT_BCM56370_A0r */
   9830         soc_block_list[5],
   9831         soc_genreg,
   9832         1,
   9833         0,
   9834         0x5a000100,
   9835         0,
   9836         0,
   9837         1,
   9838         soc_L2_PYLD_INIT_SHIFT_AMOUNTr_fields,
   9839         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
   9840         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9841         -1,
   9842         -1,
   9843         3,
   9844     },
   9845 #endif /* chips */
   9846 
   9847 #if defined(BCM_56850_A0)
   9848     { /* SOC_REG_INT_L2_TABLE_HASH_CONTROLr */
   9849         soc_block_list[5],
   9850         soc_genreg,
   9851         1,
   9852         0,
   9853         0x1a001800,
   9854         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9855         0,
   9856         4,
   9857         soc_L2_TABLE_HASH_CONTROLr_fields,
   9858         SOC_RESET_VAL_DEC(0x00000c30, 0x00000000)
   9859         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   9860         -1,
   9861         -1,
   9862     },
   9863 #endif /* chips */
   9864 
   9865 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   9866     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9867     { /* SOC_REG_INT_L2_TABLE_HASH_CONTROL_BCM56560_A0r */
   9868         soc_block_list[5],
   9869         soc_genreg,
   9870         1,
   9871         0,
   9872         0x1a001800,
   9873         0,
   9874         0,
   9875         3,
   9876         soc_L2_TABLE_HASH_CONTROL_BCM56960_A0r_fields,
   9877         SOC_RESET_VAL_DEC(0x00000c30, 0x00000000)
   9878         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   9879         -1,
   9880         -1,
   9881     },
   9882 #endif /* chips */
   9883 
   9884 #if defined(BCM_56860_A0)
   9885     { /* SOC_REG_INT_L2_TABLE_HASH_CONTROL_BCM56860_A0r */
   9886         soc_block_list[5],
   9887         soc_genreg,
   9888         1,
   9889         0,
   9890         0x1a001800,
   9891         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9892         0,
   9893         4,
   9894         soc_L2_TABLE_HASH_CONTROL_BCM56860_A0r_fields,
   9895         SOC_RESET_VAL_DEC(0x00000c30, 0x00000000)
   9896         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9897         -1,
   9898         -1,
   9899     },
   9900 #endif /* chips */
   9901 
   9902 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9903     { /* SOC_REG_INT_L2_TABLE_HASH_CONTROL_BCM56960_A0r */
   9904         soc_block_list[5],
   9905         soc_genreg,
   9906         1,
   9907         0,
   9908         0x3a002800,
   9909         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9910         0,
   9911         3,
   9912         soc_L2_TABLE_HASH_CONTROL_BCM56960_A0r_fields,
   9913         SOC_RESET_VAL_DEC(0x00000c30, 0x00000000)
   9914         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   9915         -1,
   9916         -1,
   9917         3,
   9918     },
   9919 #endif /* chips */
   9920 
   9921 #if defined(BCM_56970_A0)
   9922     { /* SOC_REG_INT_L2_TABLE_HASH_CONTROL_BCM56970_A0r */
   9923         soc_block_list[5],
   9924         soc_genreg,
   9925         1,
   9926         0,
   9927         0x5e002900,
   9928         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9929         0,
   9930         3,
   9931         soc_L2_TABLE_HASH_CONTROL_BCM56960_A0r_fields,
   9932         SOC_RESET_VAL_DEC(0x00000c30, 0x00000000)
   9933         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   9934         -1,
   9935         -1,
   9936         3,
   9937     },
   9938 #endif /* chips */
   9939 
   9940 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9941     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9942     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIGr */
   9943         soc_block_list[5],
   9944         soc_genreg,
   9945         1,
   9946         0,
   9947         0x708012f,
   9948         0,
   9949         0,
   9950         4,
   9951         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
   9952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9953         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9954         -1,
   9955         -1,
   9956     },
   9957 #endif /* chips */
   9958 
   9959 #if defined(BCM_56970_A0)
   9960     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64r */
   9961         soc_block_list[5],
   9962         soc_genreg,
   9963         1,
   9964         0,
   9965         0x5f0f0000,
   9966         SOC_REG_FLAG_64_BITS |
   9967                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9968         0,
   9969         5,
   9970         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
   9971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9972         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9973         -1,
   9974         -1,
   9975         0,
   9976     },
   9977 #endif /* chips */
   9978 
   9979 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9980     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_BCM56980_A0r */
   9981         soc_block_list[5],
   9982         soc_genreg,
   9983         1,
   9984         0,
   9985         0xe011100,
   9986         SOC_REG_FLAG_64_BITS |
   9987                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9988         0,
   9989         5,
   9990         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
   9991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9992         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9993         -1,
   9994         -1,
   9995         3,
   9996     },
   9997 #endif /* chips */
   9998 
   9999 #if defined(BCM_56970_A0)
  10000     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE0r */
  10001         soc_block_list[5],
  10002         soc_genreg,
  10003         1,
  10004         0,
  10005         0x5f0f0000,
  10006         SOC_REG_FLAG_64_BITS,
  10007         0,
  10008         5,
  10009         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  10010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10012         -1,
  10013         -1,
  10014         0,
  10015     },
  10016 #endif /* chips */
  10017 
  10018 #if defined(BCM_56970_A0)
  10019     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE1r */
  10020         soc_block_list[5],
  10021         soc_genreg,
  10022         1,
  10023         0,
  10024         0x5f0f0000,
  10025         SOC_REG_FLAG_64_BITS |
  10026                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10027         0,
  10028         5,
  10029         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  10030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10032         -1,
  10033         -1,
  10034         0,
  10035     },
  10036 #endif /* chips */
  10037 
  10038 #if defined(BCM_56970_A0)
  10039     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE2r */
  10040         soc_block_list[5],
  10041         soc_genreg,
  10042         1,
  10043         0,
  10044         0x5f0f0000,
  10045         SOC_REG_FLAG_64_BITS |
  10046                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10047         0,
  10048         5,
  10049         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  10050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10052         -1,
  10053         -1,
  10054         0,
  10055     },
  10056 #endif /* chips */
  10057 
  10058 #if defined(BCM_56970_A0)
  10059     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE3r */
  10060         soc_block_list[5],
  10061         soc_genreg,
  10062         1,
  10063         0,
  10064         0x5f0f0000,
  10065         SOC_REG_FLAG_64_BITS |
  10066                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10067         0,
  10068         5,
  10069         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  10070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10072         -1,
  10073         -1,
  10074         0,
  10075     },
  10076 #endif /* chips */
  10077 
  10078 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10079     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE4r */
  10080         soc_block_list[5],
  10081         soc_genreg,
  10082         1,
  10083         0,
  10084         0xe011100,
  10085         SOC_REG_FLAG_64_BITS |
  10086                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10087         0,
  10088         5,
  10089         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  10090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10092         -1,
  10093         -1,
  10094         3,
  10095     },
  10096 #endif /* chips */
  10097 
  10098 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10099     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE5r */
  10100         soc_block_list[5],
  10101         soc_genreg,
  10102         1,
  10103         0,
  10104         0xe011100,
  10105         SOC_REG_FLAG_64_BITS |
  10106                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10107         0,
  10108         5,
  10109         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  10110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10112         -1,
  10113         -1,
  10114         3,
  10115     },
  10116 #endif /* chips */
  10117 
  10118 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10119     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE6r */
  10120         soc_block_list[5],
  10121         soc_genreg,
  10122         1,
  10123         0,
  10124         0xe011100,
  10125         SOC_REG_FLAG_64_BITS |
  10126                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10127         0,
  10128         5,
  10129         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  10130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10131         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10132         -1,
  10133         -1,
  10134         3,
  10135     },
  10136 #endif /* chips */
  10137 
  10138 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10139     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE7r */
  10140         soc_block_list[5],
  10141         soc_genreg,
  10142         1,
  10143         0,
  10144         0xe011100,
  10145         SOC_REG_FLAG_64_BITS |
  10146                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10147         0,
  10148         5,
  10149         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  10150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10151         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10152         -1,
  10153         -1,
  10154         3,
  10155     },
  10156 #endif /* chips */
  10157 
  10158 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10159     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE0_BCM56980_A0r */
  10160         soc_block_list[5],
  10161         soc_genreg,
  10162         1,
  10163         0,
  10164         0xe011100,
  10165         SOC_REG_FLAG_64_BITS,
  10166         0,
  10167         5,
  10168         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  10169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10170         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10171         -1,
  10172         -1,
  10173         3,
  10174     },
  10175 #endif /* chips */
  10176 
  10177 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10178     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE1_BCM56980_A0r */
  10179         soc_block_list[5],
  10180         soc_genreg,
  10181         1,
  10182         0,
  10183         0xe011100,
  10184         SOC_REG_FLAG_64_BITS |
  10185                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10186         0,
  10187         5,
  10188         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  10189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10190         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10191         -1,
  10192         -1,
  10193         3,
  10194     },
  10195 #endif /* chips */
  10196 
  10197 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10198     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE2_BCM56980_A0r */
  10199         soc_block_list[5],
  10200         soc_genreg,
  10201         1,
  10202         0,
  10203         0xe011100,
  10204         SOC_REG_FLAG_64_BITS |
  10205                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10206         0,
  10207         5,
  10208         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  10209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10210         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10211         -1,
  10212         -1,
  10213         3,
  10214     },
  10215 #endif /* chips */
  10216 
  10217 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10218     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE3_BCM56980_A0r */
  10219         soc_block_list[5],
  10220         soc_genreg,
  10221         1,
  10222         0,
  10223         0xe011100,
  10224         SOC_REG_FLAG_64_BITS |
  10225                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10226         0,
  10227         5,
  10228         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  10229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10230         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10231         -1,
  10232         -1,
  10233         3,
  10234     },
  10235 #endif /* chips */
  10236 
  10237 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  10238     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  10239     defined(BCM_56160_A0)
  10240     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r */
  10241         soc_block_list[5],
  10242         soc_genreg,
  10243         1,
  10244         0,
  10245         0x1e010300,
  10246         0,
  10247         0,
  10248         4,
  10249         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  10250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10252         -1,
  10253         -1,
  10254     },
  10255 #endif /* chips */
  10256 
  10257 #if defined(BCM_56142_A0)
  10258     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56142_A0r */
  10259         soc_block_list[5],
  10260         soc_genreg,
  10261         1,
  10262         0,
  10263         0x7080137,
  10264         0,
  10265         0,
  10266         4,
  10267         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  10268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10269         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10270         -1,
  10271         -1,
  10272     },
  10273 #endif /* chips */
  10274 
  10275 #if defined(BCM_56150_A0)
  10276     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56150_A0r */
  10277         soc_block_list[5],
  10278         soc_genreg,
  10279         1,
  10280         0,
  10281         0x1e010300,
  10282         0,
  10283         0,
  10284         4,
  10285         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  10286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10288         -1,
  10289         -1,
  10290     },
  10291 #endif /* chips */
  10292 
  10293 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  10294     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10295     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56224_A0r */
  10296         soc_block_list[5],
  10297         soc_genreg,
  10298         1,
  10299         0,
  10300         0x6080003,
  10301         0,
  10302         0,
  10303         4,
  10304         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  10305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10307         -1,
  10308         -1,
  10309     },
  10310 #endif /* chips */
  10311 
  10312 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10313     defined(BCM_56270_A0)
  10314     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56260_A0r */
  10315         soc_block_list[5],
  10316         soc_genreg,
  10317         1,
  10318         0,
  10319         0x1a010300,
  10320         0,
  10321         0,
  10322         4,
  10323         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  10324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10326         -1,
  10327         -1,
  10328     },
  10329 #endif /* chips */
  10330 
  10331 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  10332     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56334_A0r */
  10333         soc_block_list[5],
  10334         soc_genreg,
  10335         1,
  10336         0,
  10337         0x708014f,
  10338         0,
  10339         0,
  10340         4,
  10341         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  10342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10343         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10344         -1,
  10345         -1,
  10346     },
  10347 #endif /* chips */
  10348 
  10349 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10350     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56440_A0r */
  10351         soc_block_list[5],
  10352         soc_genreg,
  10353         1,
  10354         0,
  10355         0x6080303,
  10356         0,
  10357         0,
  10358         4,
  10359         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  10360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10361         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10362         -1,
  10363         -1,
  10364     },
  10365 #endif /* chips */
  10366 
  10367 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10368     defined(BCM_56450_B1)
  10369     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56450_A0r */
  10370         soc_block_list[5],
  10371         soc_genreg,
  10372         1,
  10373         0,
  10374         0x1a010300,
  10375         0,
  10376         0,
  10377         4,
  10378         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  10379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10380         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10381         -1,
  10382         -1,
  10383     },
  10384 #endif /* chips */
  10385 
  10386 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  10387     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56560_A0r */
  10388         soc_block_list[5],
  10389         soc_genreg,
  10390         1,
  10391         0,
  10392         0x1b050000,
  10393         0,
  10394         0,
  10395         4,
  10396         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  10397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10398         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10399         -1,
  10400         -1,
  10401     },
  10402 #endif /* chips */
  10403 
  10404 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10405     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10406     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10407     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56634_A0r */
  10408         soc_block_list[5],
  10409         soc_genreg,
  10410         1,
  10411         0,
  10412         0x708017d,
  10413         0,
  10414         0,
  10415         4,
  10416         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  10417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10418         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10419         -1,
  10420         -1,
  10421     },
  10422 #endif /* chips */
  10423 
  10424 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  10425     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56640_A0r */
  10426         soc_block_list[5],
  10427         soc_genreg,
  10428         1,
  10429         0,
  10430         0x1a010300,
  10431         0,
  10432         0,
  10433         4,
  10434         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  10435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10436         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10437         -1,
  10438         -1,
  10439     },
  10440 #endif /* chips */
  10441 
  10442 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10443     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56670_A0r */
  10444         soc_block_list[5],
  10445         soc_genreg,
  10446         1,
  10447         0,
  10448         0x1b060000,
  10449         0,
  10450         0,
  10451         4,
  10452         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  10453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10454         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10455         -1,
  10456         -1,
  10457     },
  10458 #endif /* chips */
  10459 
  10460 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  10461     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56820_A0r */
  10462         soc_block_list[5],
  10463         soc_genreg,
  10464         1,
  10465         0,
  10466         0x6080c03,
  10467         0,
  10468         0,
  10469         4,
  10470         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  10471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10472         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10473         -1,
  10474         -1,
  10475     },
  10476 #endif /* chips */
  10477 
  10478 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  10479     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56840_A0r */
  10480         soc_block_list[5],
  10481         soc_genreg,
  10482         1,
  10483         0,
  10484         0x6080d05,
  10485         0,
  10486         0,
  10487         4,
  10488         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  10489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10490         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10491         -1,
  10492         -1,
  10493     },
  10494 #endif /* chips */
  10495 
  10496 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  10497     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56850_A0r */
  10498         soc_block_list[5],
  10499         soc_genreg,
  10500         1,
  10501         0,
  10502         0x1b050000,
  10503         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10504         0,
  10505         4,
  10506         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  10507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10508         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10509         -1,
  10510         -1,
  10511     },
  10512 #endif /* chips */
  10513 
  10514 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10515     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM56960_A0r */
  10516         soc_block_list[5],
  10517         soc_genreg,
  10518         1,
  10519         0,
  10520         0x3b110000,
  10521         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10522         0,
  10523         4,
  10524         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  10525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10526         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10527         -1,
  10528         -1,
  10529         3,
  10530     },
  10531 #endif /* chips */
  10532 
  10533 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10534     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_PIPE0r */
  10535         soc_block_list[5],
  10536         soc_genreg,
  10537         1,
  10538         0,
  10539         0x3b110000,
  10540         0,
  10541         0,
  10542         4,
  10543         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  10544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10545         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10546         -1,
  10547         -1,
  10548         3,
  10549     },
  10550 #endif /* chips */
  10551 
  10552 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10553     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_PIPE1r */
  10554         soc_block_list[5],
  10555         soc_genreg,
  10556         1,
  10557         0,
  10558         0x3b110000,
  10559         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10560         0,
  10561         4,
  10562         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  10563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10564         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10565         -1,
  10566         -1,
  10567         3,
  10568     },
  10569 #endif /* chips */
  10570 
  10571 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10572     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_PIPE2r */
  10573         soc_block_list[5],
  10574         soc_genreg,
  10575         1,
  10576         0,
  10577         0x3b110000,
  10578         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10579         0,
  10580         4,
  10581         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  10582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10584         -1,
  10585         -1,
  10586         3,
  10587     },
  10588 #endif /* chips */
  10589 
  10590 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10591     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONFIG_PIPE3r */
  10592         soc_block_list[5],
  10593         soc_genreg,
  10594         1,
  10595         0,
  10596         0x3b110000,
  10597         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10598         0,
  10599         4,
  10600         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  10601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10602         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10603         -1,
  10604         -1,
  10605         3,
  10606     },
  10607 #endif /* chips */
  10608 
  10609 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  10610     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10611     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONTROLr */
  10612         soc_block_list[5],
  10613         soc_genreg,
  10614         1,
  10615         0,
  10616         0x6080001,
  10617         0,
  10618         0,
  10619         2,
  10620         soc_CPU_COS_CAM_DBGCTRLr_fields,
  10621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10622         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10623         -1,
  10624         -1,
  10625     },
  10626 #endif /* chips */
  10627 
  10628 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  10629     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_CONTROL_BCM56820_A0r */
  10630         soc_block_list[5],
  10631         soc_genreg,
  10632         1,
  10633         0,
  10634         0x6080c01,
  10635         0,
  10636         0,
  10637         3,
  10638         soc_L2_USER_ENTRY_CAM_BIST_CONTROLr_fields,
  10639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10640         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10641         -1,
  10642         -1,
  10643     },
  10644 #endif /* chips */
  10645 
  10646 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10647     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  10648     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRLr */
  10649         soc_block_list[5],
  10650         soc_genreg,
  10651         1,
  10652         0,
  10653         0x708012d,
  10654         0,
  10655         0,
  10656         2,
  10657         soc_CPU_COS_CAM_DBGCTRLr_fields,
  10658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10659         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10660         -1,
  10661         -1,
  10662     },
  10663 #endif /* chips */
  10664 
  10665 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  10666     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  10667     defined(BCM_56160_A0)
  10668     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM53400_A0r */
  10669         soc_block_list[5],
  10670         soc_genreg,
  10671         1,
  10672         0,
  10673         0x1e010100,
  10674         0,
  10675         0,
  10676         2,
  10677         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  10678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10679         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10680         -1,
  10681         -1,
  10682     },
  10683 #endif /* chips */
  10684 
  10685 #if defined(BCM_56142_A0)
  10686     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56142_A0r */
  10687         soc_block_list[5],
  10688         soc_genreg,
  10689         1,
  10690         0,
  10691         0x7080135,
  10692         0,
  10693         0,
  10694         2,
  10695         soc_CPU_COS_CAM_DBGCTRLr_fields,
  10696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10697         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10698         -1,
  10699         -1,
  10700     },
  10701 #endif /* chips */
  10702 
  10703 #if defined(BCM_56150_A0)
  10704     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56150_A0r */
  10705         soc_block_list[5],
  10706         soc_genreg,
  10707         1,
  10708         0,
  10709         0x1e010100,
  10710         0,
  10711         0,
  10712         2,
  10713         soc_CPU_COS_CAM_DBGCTRL_BCM56640_A0r_fields,
  10714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10715         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10716         -1,
  10717         -1,
  10718     },
  10719 #endif /* chips */
  10720 
  10721 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10722     defined(BCM_56270_A0)
  10723     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56260_A0r */
  10724         soc_block_list[5],
  10725         soc_genreg,
  10726         1,
  10727         0,
  10728         0x1a010100,
  10729         0,
  10730         0,
  10731         2,
  10732         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  10733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10734         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10735         -1,
  10736         -1,
  10737     },
  10738 #endif /* chips */
  10739 
  10740 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  10741     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56334_A0r */
  10742         soc_block_list[5],
  10743         soc_genreg,
  10744         1,
  10745         0,
  10746         0x708014d,
  10747         0,
  10748         0,
  10749         2,
  10750         soc_CPU_COS_CAM_DBGCTRLr_fields,
  10751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10752         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10753         -1,
  10754         -1,
  10755     },
  10756 #endif /* chips */
  10757 
  10758 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10759     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56440_A0r */
  10760         soc_block_list[5],
  10761         soc_genreg,
  10762         1,
  10763         0,
  10764         0x6080301,
  10765         0,
  10766         0,
  10767         2,
  10768         soc_CPU_COS_CAM_DBGCTRLr_fields,
  10769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10770         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10771         -1,
  10772         -1,
  10773     },
  10774 #endif /* chips */
  10775 
  10776 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10777     defined(BCM_56450_B1)
  10778     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56450_A0r */
  10779         soc_block_list[5],
  10780         soc_genreg,
  10781         1,
  10782         0,
  10783         0x1a010100,
  10784         0,
  10785         0,
  10786         2,
  10787         soc_CPU_COS_CAM_DBGCTRL_BCM56640_A0r_fields,
  10788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10790         -1,
  10791         -1,
  10792     },
  10793 #endif /* chips */
  10794 
  10795 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  10796     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56560_A0r */
  10797         soc_block_list[5],
  10798         soc_genreg,
  10799         1,
  10800         0,
  10801         0x1b030000,
  10802         0,
  10803         0,
  10804         2,
  10805         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  10806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10808         -1,
  10809         -1,
  10810     },
  10811 #endif /* chips */
  10812 
  10813 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10814     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10815     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10816     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56634_A0r */
  10817         soc_block_list[5],
  10818         soc_genreg,
  10819         1,
  10820         0,
  10821         0x708017b,
  10822         0,
  10823         0,
  10824         2,
  10825         soc_CPU_COS_CAM_DBGCTRLr_fields,
  10826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10828         -1,
  10829         -1,
  10830     },
  10831 #endif /* chips */
  10832 
  10833 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  10834     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56640_A0r */
  10835         soc_block_list[5],
  10836         soc_genreg,
  10837         1,
  10838         0,
  10839         0x1a010100,
  10840         0,
  10841         0,
  10842         2,
  10843         soc_CPU_COS_CAM_DBGCTRL_BCM56640_A0r_fields,
  10844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10845         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10846         -1,
  10847         -1,
  10848     },
  10849 #endif /* chips */
  10850 
  10851 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10852     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56670_A0r */
  10853         soc_block_list[5],
  10854         soc_genreg,
  10855         1,
  10856         0,
  10857         0x1b040000,
  10858         0,
  10859         0,
  10860         2,
  10861         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  10862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10863         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10864         -1,
  10865         -1,
  10866     },
  10867 #endif /* chips */
  10868 
  10869 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  10870     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56840_A0r */
  10871         soc_block_list[5],
  10872         soc_genreg,
  10873         1,
  10874         0,
  10875         0x6080d03,
  10876         0,
  10877         0,
  10878         2,
  10879         soc_CPU_COS_CAM_DBGCTRLr_fields,
  10880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10882         -1,
  10883         -1,
  10884     },
  10885 #endif /* chips */
  10886 
  10887 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  10888     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56850_A0r */
  10889         soc_block_list[5],
  10890         soc_genreg,
  10891         1,
  10892         0,
  10893         0x1b030000,
  10894         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10895         0,
  10896         2,
  10897         soc_CPU_COS_CAM_DBGCTRL_BCM56640_A0r_fields,
  10898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10899         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10900         -1,
  10901         -1,
  10902     },
  10903 #endif /* chips */
  10904 
  10905 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10906     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_BCM56960_A0r */
  10907         soc_block_list[5],
  10908         soc_genreg,
  10909         1,
  10910         0,
  10911         0x3b0f0000,
  10912         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10913         0,
  10914         2,
  10915         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  10916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10918         -1,
  10919         -1,
  10920         3,
  10921     },
  10922 #endif /* chips */
  10923 
  10924 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10925     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_PIPE0r */
  10926         soc_block_list[5],
  10927         soc_genreg,
  10928         1,
  10929         0,
  10930         0x3b0f0000,
  10931         0,
  10932         0,
  10933         2,
  10934         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  10935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10936         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10937         -1,
  10938         -1,
  10939         3,
  10940     },
  10941 #endif /* chips */
  10942 
  10943 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10944     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_PIPE1r */
  10945         soc_block_list[5],
  10946         soc_genreg,
  10947         1,
  10948         0,
  10949         0x3b0f0000,
  10950         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10951         0,
  10952         2,
  10953         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  10954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10956         -1,
  10957         -1,
  10958         3,
  10959     },
  10960 #endif /* chips */
  10961 
  10962 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10963     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_PIPE2r */
  10964         soc_block_list[5],
  10965         soc_genreg,
  10966         1,
  10967         0,
  10968         0x3b0f0000,
  10969         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10970         0,
  10971         2,
  10972         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  10973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10974         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10975         -1,
  10976         -1,
  10977         3,
  10978     },
  10979 #endif /* chips */
  10980 
  10981 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10982     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBGCTRL_PIPE3r */
  10983         soc_block_list[5],
  10984         soc_genreg,
  10985         1,
  10986         0,
  10987         0x3b0f0000,
  10988         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10989         0,
  10990         2,
  10991         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  10992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10994         -1,
  10995         -1,
  10996         3,
  10997     },
  10998 #endif /* chips */
  10999 
  11000 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11001     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  11002     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATAr */
  11003         soc_block_list[5],
  11004         soc_genreg,
  11005         1,
  11006         0,
  11007         0x7080130,
  11008         0,
  11009         0,
  11010         1,
  11011         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  11012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11013         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11014         -1,
  11015         -1,
  11016     },
  11017 #endif /* chips */
  11018 
  11019 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  11020     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  11021     defined(BCM_56160_A0)
  11022     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r */
  11023         soc_block_list[5],
  11024         soc_genreg,
  11025         1,
  11026         0,
  11027         0x1e010400,
  11028         0,
  11029         0,
  11030         1,
  11031         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11034         -1,
  11035         -1,
  11036     },
  11037 #endif /* chips */
  11038 
  11039 #if defined(BCM_56142_A0)
  11040     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56142_A0r */
  11041         soc_block_list[5],
  11042         soc_genreg,
  11043         1,
  11044         0,
  11045         0x7080138,
  11046         0,
  11047         0,
  11048         1,
  11049         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  11050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11052         -1,
  11053         -1,
  11054     },
  11055 #endif /* chips */
  11056 
  11057 #if defined(BCM_56150_A0)
  11058     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56150_A0r */
  11059         soc_block_list[5],
  11060         soc_genreg,
  11061         1,
  11062         0,
  11063         0x1e010400,
  11064         0,
  11065         0,
  11066         1,
  11067         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  11068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11070         -1,
  11071         -1,
  11072     },
  11073 #endif /* chips */
  11074 
  11075 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  11076     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  11077     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56224_A0r */
  11078         soc_block_list[5],
  11079         soc_genreg,
  11080         1,
  11081         0,
  11082         0x6080004,
  11083         0,
  11084         0,
  11085         1,
  11086         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  11087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11088         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11089         -1,
  11090         -1,
  11091     },
  11092 #endif /* chips */
  11093 
  11094 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  11095     defined(BCM_56270_A0)
  11096     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56260_A0r */
  11097         soc_block_list[5],
  11098         soc_genreg,
  11099         1,
  11100         0,
  11101         0x1a010400,
  11102         0,
  11103         0,
  11104         1,
  11105         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11107         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11108         -1,
  11109         -1,
  11110     },
  11111 #endif /* chips */
  11112 
  11113 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  11114     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56334_A0r */
  11115         soc_block_list[5],
  11116         soc_genreg,
  11117         1,
  11118         0,
  11119         0x7080150,
  11120         0,
  11121         0,
  11122         1,
  11123         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  11124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11125         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11126         -1,
  11127         -1,
  11128     },
  11129 #endif /* chips */
  11130 
  11131 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11132     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56440_A0r */
  11133         soc_block_list[5],
  11134         soc_genreg,
  11135         1,
  11136         0,
  11137         0x6080304,
  11138         0,
  11139         0,
  11140         1,
  11141         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  11142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11143         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11144         -1,
  11145         -1,
  11146     },
  11147 #endif /* chips */
  11148 
  11149 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11150     defined(BCM_56450_B1)
  11151     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56450_A0r */
  11152         soc_block_list[5],
  11153         soc_genreg,
  11154         1,
  11155         0,
  11156         0x1a010400,
  11157         0,
  11158         0,
  11159         1,
  11160         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  11161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11163         -1,
  11164         -1,
  11165     },
  11166 #endif /* chips */
  11167 
  11168 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  11169     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56560_A0r */
  11170         soc_block_list[5],
  11171         soc_genreg,
  11172         1,
  11173         0,
  11174         0x1b060000,
  11175         0,
  11176         0,
  11177         1,
  11178         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11180         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11181         -1,
  11182         -1,
  11183     },
  11184 #endif /* chips */
  11185 
  11186 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11187     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11188     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11189     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56634_A0r */
  11190         soc_block_list[5],
  11191         soc_genreg,
  11192         1,
  11193         0,
  11194         0x708017e,
  11195         0,
  11196         0,
  11197         1,
  11198         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  11199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11200         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11201         -1,
  11202         -1,
  11203     },
  11204 #endif /* chips */
  11205 
  11206 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  11207     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56640_A0r */
  11208         soc_block_list[5],
  11209         soc_genreg,
  11210         1,
  11211         0,
  11212         0x1a010400,
  11213         0,
  11214         0,
  11215         1,
  11216         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  11217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11218         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11219         -1,
  11220         -1,
  11221     },
  11222 #endif /* chips */
  11223 
  11224 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  11225     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56670_A0r */
  11226         soc_block_list[5],
  11227         soc_genreg,
  11228         1,
  11229         0,
  11230         0x1b070000,
  11231         0,
  11232         0,
  11233         1,
  11234         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11236         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11237         -1,
  11238         -1,
  11239     },
  11240 #endif /* chips */
  11241 
  11242 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11243     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56820_A0r */
  11244         soc_block_list[5],
  11245         soc_genreg,
  11246         1,
  11247         0,
  11248         0x6080c04,
  11249         0,
  11250         0,
  11251         1,
  11252         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  11253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11254         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11255         -1,
  11256         -1,
  11257     },
  11258 #endif /* chips */
  11259 
  11260 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11261     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56840_A0r */
  11262         soc_block_list[5],
  11263         soc_genreg,
  11264         1,
  11265         0,
  11266         0x6080d06,
  11267         0,
  11268         0,
  11269         1,
  11270         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  11271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11272         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11273         -1,
  11274         -1,
  11275     },
  11276 #endif /* chips */
  11277 
  11278 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  11279     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56850_A0r */
  11280         soc_block_list[5],
  11281         soc_genreg,
  11282         1,
  11283         0,
  11284         0x1b060000,
  11285         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11286         0,
  11287         1,
  11288         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  11289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11290         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11291         -1,
  11292         -1,
  11293     },
  11294 #endif /* chips */
  11295 
  11296 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11297     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56960_A0r */
  11298         soc_block_list[5],
  11299         soc_genreg,
  11300         1,
  11301         0,
  11302         0x3b120000,
  11303         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11304         0,
  11305         1,
  11306         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11308         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11309         -1,
  11310         -1,
  11311         3,
  11312     },
  11313 #endif /* chips */
  11314 
  11315 #if defined(BCM_56970_A0)
  11316     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56970_A0r */
  11317         soc_block_list[5],
  11318         soc_genreg,
  11319         1,
  11320         0,
  11321         0x5f110000,
  11322         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11323         0,
  11324         1,
  11325         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11328         -1,
  11329         -1,
  11330         3,
  11331     },
  11332 #endif /* chips */
  11333 
  11334 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11335     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM56980_A0r */
  11336         soc_block_list[5],
  11337         soc_genreg,
  11338         1,
  11339         0,
  11340         0xe011200,
  11341         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11342         0,
  11343         1,
  11344         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11346         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11347         -1,
  11348         -1,
  11349         3,
  11350     },
  11351 #endif /* chips */
  11352 
  11353 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11354     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE0r */
  11355         soc_block_list[5],
  11356         soc_genreg,
  11357         1,
  11358         0,
  11359         0x3b120000,
  11360         0,
  11361         0,
  11362         1,
  11363         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11365         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11366         -1,
  11367         -1,
  11368         3,
  11369     },
  11370 #endif /* chips */
  11371 
  11372 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11373     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE1r */
  11374         soc_block_list[5],
  11375         soc_genreg,
  11376         1,
  11377         0,
  11378         0x3b120000,
  11379         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11380         0,
  11381         1,
  11382         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11384         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11385         -1,
  11386         -1,
  11387         3,
  11388     },
  11389 #endif /* chips */
  11390 
  11391 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11392     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE2r */
  11393         soc_block_list[5],
  11394         soc_genreg,
  11395         1,
  11396         0,
  11397         0x3b120000,
  11398         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11399         0,
  11400         1,
  11401         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11403         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11404         -1,
  11405         -1,
  11406         3,
  11407     },
  11408 #endif /* chips */
  11409 
  11410 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11411     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE3r */
  11412         soc_block_list[5],
  11413         soc_genreg,
  11414         1,
  11415         0,
  11416         0x3b120000,
  11417         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11418         0,
  11419         1,
  11420         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11422         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11423         -1,
  11424         -1,
  11425         3,
  11426     },
  11427 #endif /* chips */
  11428 
  11429 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11430     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE4r */
  11431         soc_block_list[5],
  11432         soc_genreg,
  11433         1,
  11434         0,
  11435         0xe011200,
  11436         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11437         0,
  11438         1,
  11439         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11441         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11442         -1,
  11443         -1,
  11444         3,
  11445     },
  11446 #endif /* chips */
  11447 
  11448 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11449     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE5r */
  11450         soc_block_list[5],
  11451         soc_genreg,
  11452         1,
  11453         0,
  11454         0xe011200,
  11455         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11456         0,
  11457         1,
  11458         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11460         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11461         -1,
  11462         -1,
  11463         3,
  11464     },
  11465 #endif /* chips */
  11466 
  11467 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11468     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE6r */
  11469         soc_block_list[5],
  11470         soc_genreg,
  11471         1,
  11472         0,
  11473         0xe011200,
  11474         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11475         0,
  11476         1,
  11477         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11479         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11480         -1,
  11481         -1,
  11482         3,
  11483     },
  11484 #endif /* chips */
  11485 
  11486 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11487     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE7r */
  11488         soc_block_list[5],
  11489         soc_genreg,
  11490         1,
  11491         0,
  11492         0xe011200,
  11493         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11494         0,
  11495         1,
  11496         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11498         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11499         -1,
  11500         -1,
  11501         3,
  11502     },
  11503 #endif /* chips */
  11504 
  11505 #if defined(BCM_56970_A0)
  11506     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE0_BCM56970_A0r */
  11507         soc_block_list[5],
  11508         soc_genreg,
  11509         1,
  11510         0,
  11511         0x5f110000,
  11512         0,
  11513         0,
  11514         1,
  11515         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11517         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11518         -1,
  11519         -1,
  11520         3,
  11521     },
  11522 #endif /* chips */
  11523 
  11524 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11525     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE0_BCM56980_A0r */
  11526         soc_block_list[5],
  11527         soc_genreg,
  11528         1,
  11529         0,
  11530         0xe011200,
  11531         0,
  11532         0,
  11533         1,
  11534         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11536         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11537         -1,
  11538         -1,
  11539         3,
  11540     },
  11541 #endif /* chips */
  11542 
  11543 #if defined(BCM_56970_A0)
  11544     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE1_BCM56970_A0r */
  11545         soc_block_list[5],
  11546         soc_genreg,
  11547         1,
  11548         0,
  11549         0x5f110000,
  11550         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11551         0,
  11552         1,
  11553         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11556         -1,
  11557         -1,
  11558         3,
  11559     },
  11560 #endif /* chips */
  11561 
  11562 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11563     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE1_BCM56980_A0r */
  11564         soc_block_list[5],
  11565         soc_genreg,
  11566         1,
  11567         0,
  11568         0xe011200,
  11569         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11570         0,
  11571         1,
  11572         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11574         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11575         -1,
  11576         -1,
  11577         3,
  11578     },
  11579 #endif /* chips */
  11580 
  11581 #if defined(BCM_56970_A0)
  11582     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE2_BCM56970_A0r */
  11583         soc_block_list[5],
  11584         soc_genreg,
  11585         1,
  11586         0,
  11587         0x5f110000,
  11588         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11589         0,
  11590         1,
  11591         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11594         -1,
  11595         -1,
  11596         3,
  11597     },
  11598 #endif /* chips */
  11599 
  11600 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11601     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE2_BCM56980_A0r */
  11602         soc_block_list[5],
  11603         soc_genreg,
  11604         1,
  11605         0,
  11606         0xe011200,
  11607         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11608         0,
  11609         1,
  11610         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11613         -1,
  11614         -1,
  11615         3,
  11616     },
  11617 #endif /* chips */
  11618 
  11619 #if defined(BCM_56970_A0)
  11620     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE3_BCM56970_A0r */
  11621         soc_block_list[5],
  11622         soc_genreg,
  11623         1,
  11624         0,
  11625         0x5f110000,
  11626         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11627         0,
  11628         1,
  11629         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11632         -1,
  11633         -1,
  11634         3,
  11635     },
  11636 #endif /* chips */
  11637 
  11638 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11639     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE3_BCM56980_A0r */
  11640         soc_block_list[5],
  11641         soc_genreg,
  11642         1,
  11643         0,
  11644         0xe011200,
  11645         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11646         0,
  11647         1,
  11648         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  11649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11650         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11651         -1,
  11652         -1,
  11653         3,
  11654     },
  11655 #endif /* chips */
  11656 
  11657 #if defined(BCM_56504_A0)
  11658     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S10_STATUSr */
  11659         soc_block_list[5],
  11660         soc_genreg,
  11661         1,
  11662         0,
  11663         0x6080008,
  11664         SOC_REG_FLAG_RO,
  11665         0,
  11666         2,
  11667         soc_FP_CAM_BIST_S10_STATUSr_fields,
  11668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11670         -1,
  11671         -1,
  11672     },
  11673 #endif /* chips */
  11674 
  11675 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  11676     defined(BCM_56514_A0)
  11677     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S10_STATUS_BCM56504_B0r */
  11678         soc_block_list[5],
  11679         soc_genreg,
  11680         1,
  11681         0,
  11682         0x6080008,
  11683         SOC_REG_FLAG_RO,
  11684         0,
  11685         1,
  11686         soc_L2_USER_ENTRY_CAM_BIST_S10_STATUSr_fields,
  11687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11688         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11689         -1,
  11690         -1,
  11691     },
  11692 #endif /* chips */
  11693 
  11694 #if defined(BCM_56800_A0)
  11695     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S10_STATUS_BCM56800_A0r */
  11696         soc_block_list[5],
  11697         soc_genreg,
  11698         1,
  11699         0,
  11700         0x6080c08,
  11701         SOC_REG_FLAG_RO,
  11702         0,
  11703         2,
  11704         soc_FP_CAM_BIST_S10_STATUSr_fields,
  11705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11706         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11707         -1,
  11708         -1,
  11709     },
  11710 #endif /* chips */
  11711 
  11712 #if defined(BCM_56504_A0)
  11713     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S2_STATUSr */
  11714         soc_block_list[5],
  11715         soc_genreg,
  11716         1,
  11717         0,
  11718         0x6080003,
  11719         SOC_REG_FLAG_RO,
  11720         0,
  11721         3,
  11722         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  11723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11724         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11725         -1,
  11726         -1,
  11727     },
  11728 #endif /* chips */
  11729 
  11730 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  11731     defined(BCM_56514_A0)
  11732     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S2_STATUS_BCM56504_B0r */
  11733         soc_block_list[5],
  11734         soc_genreg,
  11735         1,
  11736         0,
  11737         0x6080003,
  11738         SOC_REG_FLAG_RO,
  11739         0,
  11740         1,
  11741         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUS_BCM56504_B0r_fields,
  11742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11744         -1,
  11745         -1,
  11746     },
  11747 #endif /* chips */
  11748 
  11749 #if defined(BCM_56800_A0)
  11750     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S2_STATUS_BCM56800_A0r */
  11751         soc_block_list[5],
  11752         soc_genreg,
  11753         1,
  11754         0,
  11755         0x6080c03,
  11756         SOC_REG_FLAG_RO,
  11757         0,
  11758         3,
  11759         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  11760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11762         -1,
  11763         -1,
  11764     },
  11765 #endif /* chips */
  11766 
  11767 #if defined(BCM_56504_A0)
  11768     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S3_STATUSr */
  11769         soc_block_list[5],
  11770         soc_genreg,
  11771         1,
  11772         0,
  11773         0x6080004,
  11774         SOC_REG_FLAG_RO,
  11775         0,
  11776         4,
  11777         soc_FP_CAM_BIST_S12_STATUSr_fields,
  11778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11779         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11780         -1,
  11781         -1,
  11782     },
  11783 #endif /* chips */
  11784 
  11785 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  11786     defined(BCM_56514_A0)
  11787     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S3_STATUS_BCM56504_B0r */
  11788         soc_block_list[5],
  11789         soc_genreg,
  11790         1,
  11791         0,
  11792         0x6080004,
  11793         SOC_REG_FLAG_RO,
  11794         0,
  11795         1,
  11796         soc_L2_USER_ENTRY_CAM_BIST_S3_STATUSr_fields,
  11797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11798         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11799         -1,
  11800         -1,
  11801     },
  11802 #endif /* chips */
  11803 
  11804 #if defined(BCM_56800_A0)
  11805     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S3_STATUS_BCM56800_A0r */
  11806         soc_block_list[5],
  11807         soc_genreg,
  11808         1,
  11809         0,
  11810         0x6080c04,
  11811         SOC_REG_FLAG_RO,
  11812         0,
  11813         4,
  11814         soc_FP_CAM_BIST_S12_STATUSr_fields,
  11815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11816         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11817         -1,
  11818         -1,
  11819     },
  11820 #endif /* chips */
  11821 
  11822 #if defined(BCM_56504_A0)
  11823     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S5_STATUSr */
  11824         soc_block_list[5],
  11825         soc_genreg,
  11826         1,
  11827         0,
  11828         0x6080005,
  11829         SOC_REG_FLAG_RO,
  11830         0,
  11831         3,
  11832         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  11833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11835         -1,
  11836         -1,
  11837     },
  11838 #endif /* chips */
  11839 
  11840 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  11841     defined(BCM_56514_A0)
  11842     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S5_STATUS_BCM56504_B0r */
  11843         soc_block_list[5],
  11844         soc_genreg,
  11845         1,
  11846         0,
  11847         0x6080005,
  11848         SOC_REG_FLAG_RO,
  11849         0,
  11850         1,
  11851         soc_L2_USER_ENTRY_CAM_BIST_S5_STATUSr_fields,
  11852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11854         -1,
  11855         -1,
  11856     },
  11857 #endif /* chips */
  11858 
  11859 #if defined(BCM_56800_A0)
  11860     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S5_STATUS_BCM56800_A0r */
  11861         soc_block_list[5],
  11862         soc_genreg,
  11863         1,
  11864         0,
  11865         0x6080c05,
  11866         SOC_REG_FLAG_RO,
  11867         0,
  11868         3,
  11869         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  11870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11872         -1,
  11873         -1,
  11874     },
  11875 #endif /* chips */
  11876 
  11877 #if defined(BCM_56504_A0)
  11878     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S6_STATUSr */
  11879         soc_block_list[5],
  11880         soc_genreg,
  11881         1,
  11882         0,
  11883         0x6080006,
  11884         SOC_REG_FLAG_RO,
  11885         0,
  11886         4,
  11887         soc_FP_CAM_BIST_S12_STATUSr_fields,
  11888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11889         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11890         -1,
  11891         -1,
  11892     },
  11893 #endif /* chips */
  11894 
  11895 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  11896     defined(BCM_56514_A0)
  11897     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S6_STATUS_BCM56504_B0r */
  11898         soc_block_list[5],
  11899         soc_genreg,
  11900         1,
  11901         0,
  11902         0x6080006,
  11903         SOC_REG_FLAG_RO,
  11904         0,
  11905         1,
  11906         soc_L2_USER_ENTRY_CAM_BIST_S6_STATUSr_fields,
  11907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11908         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11909         -1,
  11910         -1,
  11911     },
  11912 #endif /* chips */
  11913 
  11914 #if defined(BCM_56800_A0)
  11915     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S6_STATUS_BCM56800_A0r */
  11916         soc_block_list[5],
  11917         soc_genreg,
  11918         1,
  11919         0,
  11920         0x6080c06,
  11921         SOC_REG_FLAG_RO,
  11922         0,
  11923         4,
  11924         soc_FP_CAM_BIST_S12_STATUSr_fields,
  11925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11926         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11927         -1,
  11928         -1,
  11929     },
  11930 #endif /* chips */
  11931 
  11932 #if defined(BCM_56504_A0)
  11933     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S8_STATUSr */
  11934         soc_block_list[5],
  11935         soc_genreg,
  11936         1,
  11937         0,
  11938         0x6080007,
  11939         SOC_REG_FLAG_RO,
  11940         0,
  11941         4,
  11942         soc_FP_CAM_BIST_S12_STATUSr_fields,
  11943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11944         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11945         -1,
  11946         -1,
  11947     },
  11948 #endif /* chips */
  11949 
  11950 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  11951     defined(BCM_56514_A0)
  11952     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S8_STATUS_BCM56504_B0r */
  11953         soc_block_list[5],
  11954         soc_genreg,
  11955         1,
  11956         0,
  11957         0x6080007,
  11958         SOC_REG_FLAG_RO,
  11959         0,
  11960         1,
  11961         soc_L2_USER_ENTRY_CAM_BIST_S8_STATUSr_fields,
  11962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11963         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11964         -1,
  11965         -1,
  11966     },
  11967 #endif /* chips */
  11968 
  11969 #if defined(BCM_56800_A0)
  11970     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_S8_STATUS_BCM56800_A0r */
  11971         soc_block_list[5],
  11972         soc_genreg,
  11973         1,
  11974         0,
  11975         0x6080c07,
  11976         SOC_REG_FLAG_RO,
  11977         0,
  11978         4,
  11979         soc_FP_CAM_BIST_S12_STATUSr_fields,
  11980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11981         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11982         -1,
  11983         -1,
  11984     },
  11985 #endif /* chips */
  11986 
  11987 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  11988     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  11989     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUSr */
  11990         soc_block_list[5],
  11991         soc_genreg,
  11992         1,
  11993         0,
  11994         0x6080002,
  11995         0,
  11996         0,
  11997         2,
  11998         soc_L2_USER_ENTRY_CAM_BIST_STATUSr_fields,
  11999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12000         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12001         -1,
  12002         -1,
  12003     },
  12004 #endif /* chips */
  12005 
  12006 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  12007     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  12008     defined(BCM_56160_A0)
  12009     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM53400_A0r */
  12010         soc_block_list[5],
  12011         soc_genreg,
  12012         1,
  12013         0,
  12014         0x1e010200,
  12015         SOC_REG_FLAG_RO,
  12016         0,
  12017         1,
  12018         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12020         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12021         -1,
  12022         -1,
  12023     },
  12024 #endif /* chips */
  12025 
  12026 #if defined(BCM_56142_A0)
  12027     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56142_A0r */
  12028         soc_block_list[5],
  12029         soc_genreg,
  12030         1,
  12031         0,
  12032         0x7080136,
  12033         SOC_REG_FLAG_RO,
  12034         0,
  12035         1,
  12036         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  12037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12038         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12039         -1,
  12040         -1,
  12041     },
  12042 #endif /* chips */
  12043 
  12044 #if defined(BCM_56150_A0)
  12045     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56150_A0r */
  12046         soc_block_list[5],
  12047         soc_genreg,
  12048         1,
  12049         0,
  12050         0x1e010200,
  12051         SOC_REG_FLAG_RO,
  12052         0,
  12053         1,
  12054         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  12055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12056         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12057         -1,
  12058         -1,
  12059     },
  12060 #endif /* chips */
  12061 
  12062 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  12063     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  12064     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56224_A0r */
  12065         soc_block_list[5],
  12066         soc_genreg,
  12067         1,
  12068         0,
  12069         0x6080002,
  12070         SOC_REG_FLAG_RO,
  12071         0,
  12072         1,
  12073         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  12074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12075         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12076         -1,
  12077         -1,
  12078     },
  12079 #endif /* chips */
  12080 
  12081 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12082     defined(BCM_56270_A0)
  12083     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56260_A0r */
  12084         soc_block_list[5],
  12085         soc_genreg,
  12086         1,
  12087         0,
  12088         0x1a010200,
  12089         SOC_REG_FLAG_RO,
  12090         0,
  12091         1,
  12092         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12094         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12095         -1,
  12096         -1,
  12097     },
  12098 #endif /* chips */
  12099 
  12100 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  12101     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56334_A0r */
  12102         soc_block_list[5],
  12103         soc_genreg,
  12104         1,
  12105         0,
  12106         0x708014e,
  12107         SOC_REG_FLAG_RO,
  12108         0,
  12109         1,
  12110         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  12111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12112         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12113         -1,
  12114         -1,
  12115     },
  12116 #endif /* chips */
  12117 
  12118 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12119     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56440_A0r */
  12120         soc_block_list[5],
  12121         soc_genreg,
  12122         1,
  12123         0,
  12124         0x6080302,
  12125         SOC_REG_FLAG_RO,
  12126         0,
  12127         1,
  12128         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  12129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12130         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12131         -1,
  12132         -1,
  12133     },
  12134 #endif /* chips */
  12135 
  12136 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12137     defined(BCM_56450_B1)
  12138     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56450_A0r */
  12139         soc_block_list[5],
  12140         soc_genreg,
  12141         1,
  12142         0,
  12143         0x1a010200,
  12144         SOC_REG_FLAG_RO,
  12145         0,
  12146         1,
  12147         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  12148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12150         -1,
  12151         -1,
  12152     },
  12153 #endif /* chips */
  12154 
  12155 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  12156     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56560_A0r */
  12157         soc_block_list[5],
  12158         soc_genreg,
  12159         1,
  12160         0,
  12161         0x1b040000,
  12162         SOC_REG_FLAG_RO,
  12163         0,
  12164         1,
  12165         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12167         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12168         -1,
  12169         -1,
  12170     },
  12171 #endif /* chips */
  12172 
  12173 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  12174     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  12175     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56624_A0r */
  12176         soc_block_list[5],
  12177         soc_genreg,
  12178         1,
  12179         0,
  12180         0x708012e,
  12181         SOC_REG_FLAG_RO,
  12182         0,
  12183         1,
  12184         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  12185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12187         -1,
  12188         -1,
  12189     },
  12190 #endif /* chips */
  12191 
  12192 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12193     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12194     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12195     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56634_A0r */
  12196         soc_block_list[5],
  12197         soc_genreg,
  12198         1,
  12199         0,
  12200         0x708017c,
  12201         SOC_REG_FLAG_RO,
  12202         0,
  12203         1,
  12204         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  12205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12206         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12207         -1,
  12208         -1,
  12209     },
  12210 #endif /* chips */
  12211 
  12212 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  12213     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56640_A0r */
  12214         soc_block_list[5],
  12215         soc_genreg,
  12216         1,
  12217         0,
  12218         0x1a010200,
  12219         SOC_REG_FLAG_RO,
  12220         0,
  12221         1,
  12222         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  12223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12224         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12225         -1,
  12226         -1,
  12227     },
  12228 #endif /* chips */
  12229 
  12230 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  12231     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56670_A0r */
  12232         soc_block_list[5],
  12233         soc_genreg,
  12234         1,
  12235         0,
  12236         0x1b050000,
  12237         SOC_REG_FLAG_RO,
  12238         0,
  12239         1,
  12240         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12242         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12243         -1,
  12244         -1,
  12245     },
  12246 #endif /* chips */
  12247 
  12248 #if defined(BCM_56800_A0)
  12249     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56800_A0r */
  12250         soc_block_list[5],
  12251         soc_genreg,
  12252         1,
  12253         0,
  12254         0x6080c02,
  12255         0,
  12256         0,
  12257         2,
  12258         soc_L2_USER_ENTRY_CAM_BIST_STATUSr_fields,
  12259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12260         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12261         -1,
  12262         -1,
  12263     },
  12264 #endif /* chips */
  12265 
  12266 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  12267     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56820_A0r */
  12268         soc_block_list[5],
  12269         soc_genreg,
  12270         1,
  12271         0,
  12272         0x6080c02,
  12273         SOC_REG_FLAG_RO,
  12274         0,
  12275         1,
  12276         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  12277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12278         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12279         -1,
  12280         -1,
  12281     },
  12282 #endif /* chips */
  12283 
  12284 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  12285     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56840_A0r */
  12286         soc_block_list[5],
  12287         soc_genreg,
  12288         1,
  12289         0,
  12290         0x6080d04,
  12291         SOC_REG_FLAG_RO,
  12292         0,
  12293         1,
  12294         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  12295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12296         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12297         -1,
  12298         -1,
  12299     },
  12300 #endif /* chips */
  12301 
  12302 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  12303     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56850_A0r */
  12304         soc_block_list[5],
  12305         soc_genreg,
  12306         1,
  12307         0,
  12308         0x1b040000,
  12309         SOC_REG_FLAG_RO |
  12310                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12311         0,
  12312         1,
  12313         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  12314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12315         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12316         -1,
  12317         -1,
  12318     },
  12319 #endif /* chips */
  12320 
  12321 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12322     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56960_A0r */
  12323         soc_block_list[5],
  12324         soc_genreg,
  12325         1,
  12326         0,
  12327         0x3b100000,
  12328         SOC_REG_FLAG_RO |
  12329                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12330         0,
  12331         1,
  12332         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12334         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12335         -1,
  12336         -1,
  12337         3,
  12338     },
  12339 #endif /* chips */
  12340 
  12341 #if defined(BCM_56970_A0)
  12342     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56970_A0r */
  12343         soc_block_list[5],
  12344         soc_genreg,
  12345         1,
  12346         0,
  12347         0x5f100000,
  12348         SOC_REG_FLAG_RO |
  12349                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12350         0,
  12351         1,
  12352         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12354         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12355         -1,
  12356         -1,
  12357         3,
  12358     },
  12359 #endif /* chips */
  12360 
  12361 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12362     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_BCM56980_A0r */
  12363         soc_block_list[5],
  12364         soc_genreg,
  12365         1,
  12366         0,
  12367         0xe011300,
  12368         SOC_REG_FLAG_RO |
  12369                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12370         0,
  12371         1,
  12372         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12375         -1,
  12376         -1,
  12377         3,
  12378     },
  12379 #endif /* chips */
  12380 
  12381 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12382     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE0r */
  12383         soc_block_list[5],
  12384         soc_genreg,
  12385         1,
  12386         0,
  12387         0x3b100000,
  12388         SOC_REG_FLAG_RO,
  12389         0,
  12390         1,
  12391         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12393         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12394         -1,
  12395         -1,
  12396         3,
  12397     },
  12398 #endif /* chips */
  12399 
  12400 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12401     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE1r */
  12402         soc_block_list[5],
  12403         soc_genreg,
  12404         1,
  12405         0,
  12406         0x3b100000,
  12407         SOC_REG_FLAG_RO |
  12408                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12409         0,
  12410         1,
  12411         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12413         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12414         -1,
  12415         -1,
  12416         3,
  12417     },
  12418 #endif /* chips */
  12419 
  12420 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12421     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE2r */
  12422         soc_block_list[5],
  12423         soc_genreg,
  12424         1,
  12425         0,
  12426         0x3b100000,
  12427         SOC_REG_FLAG_RO |
  12428                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12429         0,
  12430         1,
  12431         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12433         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12434         -1,
  12435         -1,
  12436         3,
  12437     },
  12438 #endif /* chips */
  12439 
  12440 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12441     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE3r */
  12442         soc_block_list[5],
  12443         soc_genreg,
  12444         1,
  12445         0,
  12446         0x3b100000,
  12447         SOC_REG_FLAG_RO |
  12448                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12449         0,
  12450         1,
  12451         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12453         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12454         -1,
  12455         -1,
  12456         3,
  12457     },
  12458 #endif /* chips */
  12459 
  12460 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12461     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE4r */
  12462         soc_block_list[5],
  12463         soc_genreg,
  12464         1,
  12465         0,
  12466         0xe011300,
  12467         SOC_REG_FLAG_RO |
  12468                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12469         0,
  12470         1,
  12471         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12473         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12474         -1,
  12475         -1,
  12476         3,
  12477     },
  12478 #endif /* chips */
  12479 
  12480 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12481     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE5r */
  12482         soc_block_list[5],
  12483         soc_genreg,
  12484         1,
  12485         0,
  12486         0xe011300,
  12487         SOC_REG_FLAG_RO |
  12488                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12489         0,
  12490         1,
  12491         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12493         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12494         -1,
  12495         -1,
  12496         3,
  12497     },
  12498 #endif /* chips */
  12499 
  12500 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12501     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE6r */
  12502         soc_block_list[5],
  12503         soc_genreg,
  12504         1,
  12505         0,
  12506         0xe011300,
  12507         SOC_REG_FLAG_RO |
  12508                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12509         0,
  12510         1,
  12511         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12514         -1,
  12515         -1,
  12516         3,
  12517     },
  12518 #endif /* chips */
  12519 
  12520 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12521     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE7r */
  12522         soc_block_list[5],
  12523         soc_genreg,
  12524         1,
  12525         0,
  12526         0xe011300,
  12527         SOC_REG_FLAG_RO |
  12528                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12529         0,
  12530         1,
  12531         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12533         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12534         -1,
  12535         -1,
  12536         3,
  12537     },
  12538 #endif /* chips */
  12539 
  12540 #if defined(BCM_56970_A0)
  12541     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE0_BCM56970_A0r */
  12542         soc_block_list[5],
  12543         soc_genreg,
  12544         1,
  12545         0,
  12546         0x5f100000,
  12547         SOC_REG_FLAG_RO,
  12548         0,
  12549         1,
  12550         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12552         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12553         -1,
  12554         -1,
  12555         3,
  12556     },
  12557 #endif /* chips */
  12558 
  12559 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12560     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE0_BCM56980_A0r */
  12561         soc_block_list[5],
  12562         soc_genreg,
  12563         1,
  12564         0,
  12565         0xe011300,
  12566         SOC_REG_FLAG_RO,
  12567         0,
  12568         1,
  12569         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12572         -1,
  12573         -1,
  12574         3,
  12575     },
  12576 #endif /* chips */
  12577 
  12578 #if defined(BCM_56970_A0)
  12579     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE1_BCM56970_A0r */
  12580         soc_block_list[5],
  12581         soc_genreg,
  12582         1,
  12583         0,
  12584         0x5f100000,
  12585         SOC_REG_FLAG_RO |
  12586                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12587         0,
  12588         1,
  12589         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12592         -1,
  12593         -1,
  12594         3,
  12595     },
  12596 #endif /* chips */
  12597 
  12598 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12599     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE1_BCM56980_A0r */
  12600         soc_block_list[5],
  12601         soc_genreg,
  12602         1,
  12603         0,
  12604         0xe011300,
  12605         SOC_REG_FLAG_RO |
  12606                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12607         0,
  12608         1,
  12609         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12612         -1,
  12613         -1,
  12614         3,
  12615     },
  12616 #endif /* chips */
  12617 
  12618 #if defined(BCM_56970_A0)
  12619     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE2_BCM56970_A0r */
  12620         soc_block_list[5],
  12621         soc_genreg,
  12622         1,
  12623         0,
  12624         0x5f100000,
  12625         SOC_REG_FLAG_RO |
  12626                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12627         0,
  12628         1,
  12629         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12632         -1,
  12633         -1,
  12634         3,
  12635     },
  12636 #endif /* chips */
  12637 
  12638 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12639     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE2_BCM56980_A0r */
  12640         soc_block_list[5],
  12641         soc_genreg,
  12642         1,
  12643         0,
  12644         0xe011300,
  12645         SOC_REG_FLAG_RO |
  12646                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12647         0,
  12648         1,
  12649         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12652         -1,
  12653         -1,
  12654         3,
  12655     },
  12656 #endif /* chips */
  12657 
  12658 #if defined(BCM_56970_A0)
  12659     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE3_BCM56970_A0r */
  12660         soc_block_list[5],
  12661         soc_genreg,
  12662         1,
  12663         0,
  12664         0x5f100000,
  12665         SOC_REG_FLAG_RO |
  12666                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12667         0,
  12668         1,
  12669         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12671         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12672         -1,
  12673         -1,
  12674         3,
  12675     },
  12676 #endif /* chips */
  12677 
  12678 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12679     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_BIST_STATUS_PIPE3_BCM56980_A0r */
  12680         soc_block_list[5],
  12681         soc_genreg,
  12682         1,
  12683         0,
  12684         0xe011300,
  12685         SOC_REG_FLAG_RO |
  12686                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12687         0,
  12688         1,
  12689         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  12690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12692         -1,
  12693         -1,
  12694         3,
  12695     },
  12696 #endif /* chips */
  12697 
  12698 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  12699     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  12700     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_CONTROLr */
  12701         soc_block_list[5],
  12702         soc_genreg,
  12703         1,
  12704         0,
  12705         0x6080001,
  12706         0,
  12707         0,
  12708         2,
  12709         soc_EGR_VXLT_CAM_CONTROLr_fields,
  12710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12711         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12712         -1,
  12713         -1,
  12714     },
  12715 #endif /* chips */
  12716 
  12717 #if defined(BCM_56800_A0)
  12718     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRLr */
  12719         soc_block_list[5],
  12720         soc_genreg,
  12721         1,
  12722         0,
  12723         0x6080c01,
  12724         0,
  12725         0,
  12726         2,
  12727         soc_EGR_VXLT_CAM_CONTROL_BCM56800_A0r_fields,
  12728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12729         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12730         -1,
  12731         -1,
  12732     },
  12733 #endif /* chips */
  12734 
  12735 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  12736     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  12737     defined(BCM_56160_A0)
  12738     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM53400_A0r */
  12739         soc_block_list[5],
  12740         soc_genreg,
  12741         1,
  12742         0,
  12743         0x1e010000,
  12744         0,
  12745         0,
  12746         2,
  12747         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM53400_A0r_fields,
  12748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12749         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12750         -1,
  12751         -1,
  12752     },
  12753 #endif /* chips */
  12754 
  12755 #if defined(BCM_56142_A0)
  12756     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56142_A0r */
  12757         soc_block_list[5],
  12758         soc_genreg,
  12759         1,
  12760         0,
  12761         0x7080134,
  12762         0,
  12763         0,
  12764         1,
  12765         soc_FP_CAM_CONTROLr_fields,
  12766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12767         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12768         -1,
  12769         -1,
  12770     },
  12771 #endif /* chips */
  12772 
  12773 #if defined(BCM_56150_A0)
  12774     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56150_A0r */
  12775         soc_block_list[5],
  12776         soc_genreg,
  12777         1,
  12778         0,
  12779         0x1e010000,
  12780         0,
  12781         0,
  12782         2,
  12783         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56640_A0r_fields,
  12784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12785         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12786         -1,
  12787         -1,
  12788     },
  12789 #endif /* chips */
  12790 
  12791 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12792     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56260_A0r */
  12793         soc_block_list[5],
  12794         soc_genreg,
  12795         1,
  12796         0,
  12797         0x1a010000,
  12798         0,
  12799         0,
  12800         1,
  12801         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56260_A0r_fields,
  12802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12803         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12804         -1,
  12805         -1,
  12806     },
  12807 #endif /* chips */
  12808 
  12809 #if defined(BCM_56270_A0)
  12810     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56270_A0r */
  12811         soc_block_list[5],
  12812         soc_genreg,
  12813         1,
  12814         0,
  12815         0x1a010000,
  12816         0,
  12817         0,
  12818         1,
  12819         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r_fields,
  12820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12821         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12822         -1,
  12823         -1,
  12824     },
  12825 #endif /* chips */
  12826 
  12827 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  12828     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56334_A0r */
  12829         soc_block_list[5],
  12830         soc_genreg,
  12831         1,
  12832         0,
  12833         0x708014c,
  12834         0,
  12835         0,
  12836         1,
  12837         soc_FP_CAM_CONTROLr_fields,
  12838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12840         -1,
  12841         -1,
  12842     },
  12843 #endif /* chips */
  12844 
  12845 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12846     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56440_A0r */
  12847         soc_block_list[5],
  12848         soc_genreg,
  12849         1,
  12850         0,
  12851         0x6080300,
  12852         0,
  12853         0,
  12854         1,
  12855         soc_FP_CAM_CONTROL_SLICE_3_0r_fields,
  12856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12857         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12858         -1,
  12859         -1,
  12860     },
  12861 #endif /* chips */
  12862 
  12863 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12864     defined(BCM_56450_B1)
  12865     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56450_A0r */
  12866         soc_block_list[5],
  12867         soc_genreg,
  12868         1,
  12869         0,
  12870         0x1a010000,
  12871         0,
  12872         0,
  12873         1,
  12874         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
  12875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12877         -1,
  12878         -1,
  12879     },
  12880 #endif /* chips */
  12881 
  12882 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  12883     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56560_A0r */
  12884         soc_block_list[5],
  12885         soc_genreg,
  12886         1,
  12887         0,
  12888         0x1b020000,
  12889         0,
  12890         0,
  12891         2,
  12892         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM53400_A0r_fields,
  12893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12894         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12895         -1,
  12896         -1,
  12897     },
  12898 #endif /* chips */
  12899 
  12900 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  12901     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  12902     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56624_A0r */
  12903         soc_block_list[5],
  12904         soc_genreg,
  12905         1,
  12906         0,
  12907         0x708012c,
  12908         0,
  12909         0,
  12910         1,
  12911         soc_FP_CAM_CONTROLr_fields,
  12912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12913         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12914         -1,
  12915         -1,
  12916     },
  12917 #endif /* chips */
  12918 
  12919 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12920     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12921     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12922     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56634_A0r */
  12923         soc_block_list[5],
  12924         soc_genreg,
  12925         1,
  12926         0,
  12927         0x708017a,
  12928         0,
  12929         0,
  12930         1,
  12931         soc_FP_CAM_CONTROLr_fields,
  12932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12934         -1,
  12935         -1,
  12936     },
  12937 #endif /* chips */
  12938 
  12939 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  12940     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56640_A0r */
  12941         soc_block_list[5],
  12942         soc_genreg,
  12943         1,
  12944         0,
  12945         0x1a010000,
  12946         0,
  12947         0,
  12948         2,
  12949         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56640_A0r_fields,
  12950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12952         -1,
  12953         -1,
  12954     },
  12955 #endif /* chips */
  12956 
  12957 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  12958     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56670_A0r */
  12959         soc_block_list[5],
  12960         soc_genreg,
  12961         1,
  12962         0,
  12963         0x1b030000,
  12964         0,
  12965         0,
  12966         2,
  12967         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM53400_A0r_fields,
  12968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12970         -1,
  12971         -1,
  12972     },
  12973 #endif /* chips */
  12974 
  12975 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  12976     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56840_A0r */
  12977         soc_block_list[5],
  12978         soc_genreg,
  12979         1,
  12980         0,
  12981         0x6080d02,
  12982         0,
  12983         0,
  12984         2,
  12985         soc_L2_USER_ENTRY_CAM_DBGCTRLr_fields,
  12986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12987         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12988         -1,
  12989         -1,
  12990     },
  12991 #endif /* chips */
  12992 
  12993 #if defined(BCM_56850_A0)
  12994     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56850_A0r */
  12995         soc_block_list[5],
  12996         soc_genreg,
  12997         1,
  12998         0,
  12999         0x1b020000,
  13000         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13001         0,
  13002         2,
  13003         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56640_A0r_fields,
  13004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13006         -1,
  13007         -1,
  13008     },
  13009 #endif /* chips */
  13010 
  13011 #if defined(BCM_56860_A0)
  13012     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56860_A0r */
  13013         soc_block_list[5],
  13014         soc_genreg,
  13015         1,
  13016         0,
  13017         0x1b020000,
  13018         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13019         0,
  13020         2,
  13021         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56860_A0r_fields,
  13022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13023         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13024         -1,
  13025         -1,
  13026     },
  13027 #endif /* chips */
  13028 
  13029 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13030     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56960_A0r */
  13031         soc_block_list[5],
  13032         soc_genreg,
  13033         1,
  13034         0,
  13035         0x3b0e0000,
  13036         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13037         0,
  13038         2,
  13039         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56960_A0r_fields,
  13040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13041         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13042         -1,
  13043         -1,
  13044         3,
  13045     },
  13046 #endif /* chips */
  13047 
  13048 #if defined(BCM_56970_A0)
  13049     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56970_A0r */
  13050         soc_block_list[5],
  13051         soc_genreg,
  13052         1,
  13053         0,
  13054         0x5f0d0000,
  13055         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13056         0,
  13057         3,
  13058         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56970_A0r_fields,
  13059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13060         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13061         -1,
  13062         -1,
  13063         3,
  13064     },
  13065 #endif /* chips */
  13066 
  13067 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13068     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r */
  13069         soc_block_list[5],
  13070         soc_genreg,
  13071         1,
  13072         0,
  13073         0xe011400,
  13074         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13075         0,
  13076         4,
  13077         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r_fields,
  13078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13079         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13080         -1,
  13081         -1,
  13082         3,
  13083     },
  13084 #endif /* chips */
  13085 
  13086 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13087     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE0r */
  13088         soc_block_list[5],
  13089         soc_genreg,
  13090         1,
  13091         0,
  13092         0x3b0e0000,
  13093         0,
  13094         0,
  13095         2,
  13096         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56960_A0r_fields,
  13097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13098         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13099         -1,
  13100         -1,
  13101         3,
  13102     },
  13103 #endif /* chips */
  13104 
  13105 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13106     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE1r */
  13107         soc_block_list[5],
  13108         soc_genreg,
  13109         1,
  13110         0,
  13111         0x3b0e0000,
  13112         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13113         0,
  13114         2,
  13115         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56960_A0r_fields,
  13116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13118         -1,
  13119         -1,
  13120         3,
  13121     },
  13122 #endif /* chips */
  13123 
  13124 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13125     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE2r */
  13126         soc_block_list[5],
  13127         soc_genreg,
  13128         1,
  13129         0,
  13130         0x3b0e0000,
  13131         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13132         0,
  13133         2,
  13134         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56960_A0r_fields,
  13135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13136         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13137         -1,
  13138         -1,
  13139         3,
  13140     },
  13141 #endif /* chips */
  13142 
  13143 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13144     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE3r */
  13145         soc_block_list[5],
  13146         soc_genreg,
  13147         1,
  13148         0,
  13149         0x3b0e0000,
  13150         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13151         0,
  13152         2,
  13153         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56960_A0r_fields,
  13154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13155         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13156         -1,
  13157         -1,
  13158         3,
  13159     },
  13160 #endif /* chips */
  13161 
  13162 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13163     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE4r */
  13164         soc_block_list[5],
  13165         soc_genreg,
  13166         1,
  13167         0,
  13168         0xe011400,
  13169         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13170         0,
  13171         4,
  13172         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r_fields,
  13173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13174         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13175         -1,
  13176         -1,
  13177         3,
  13178     },
  13179 #endif /* chips */
  13180 
  13181 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13182     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE5r */
  13183         soc_block_list[5],
  13184         soc_genreg,
  13185         1,
  13186         0,
  13187         0xe011400,
  13188         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13189         0,
  13190         4,
  13191         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r_fields,
  13192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13193         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13194         -1,
  13195         -1,
  13196         3,
  13197     },
  13198 #endif /* chips */
  13199 
  13200 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13201     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE6r */
  13202         soc_block_list[5],
  13203         soc_genreg,
  13204         1,
  13205         0,
  13206         0xe011400,
  13207         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13208         0,
  13209         4,
  13210         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r_fields,
  13211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13212         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13213         -1,
  13214         -1,
  13215         3,
  13216     },
  13217 #endif /* chips */
  13218 
  13219 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13220     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE7r */
  13221         soc_block_list[5],
  13222         soc_genreg,
  13223         1,
  13224         0,
  13225         0xe011400,
  13226         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13227         0,
  13228         4,
  13229         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r_fields,
  13230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13232         -1,
  13233         -1,
  13234         3,
  13235     },
  13236 #endif /* chips */
  13237 
  13238 #if defined(BCM_56970_A0)
  13239     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE0_BCM56970_A0r */
  13240         soc_block_list[5],
  13241         soc_genreg,
  13242         1,
  13243         0,
  13244         0x5f0d0000,
  13245         0,
  13246         0,
  13247         3,
  13248         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56970_A0r_fields,
  13249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13250         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13251         -1,
  13252         -1,
  13253         3,
  13254     },
  13255 #endif /* chips */
  13256 
  13257 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13258     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE0_BCM56980_A0r */
  13259         soc_block_list[5],
  13260         soc_genreg,
  13261         1,
  13262         0,
  13263         0xe011400,
  13264         0,
  13265         0,
  13266         4,
  13267         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r_fields,
  13268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13269         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13270         -1,
  13271         -1,
  13272         3,
  13273     },
  13274 #endif /* chips */
  13275 
  13276 #if defined(BCM_56970_A0)
  13277     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE1_BCM56970_A0r */
  13278         soc_block_list[5],
  13279         soc_genreg,
  13280         1,
  13281         0,
  13282         0x5f0d0000,
  13283         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13284         0,
  13285         3,
  13286         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56970_A0r_fields,
  13287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13288         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13289         -1,
  13290         -1,
  13291         3,
  13292     },
  13293 #endif /* chips */
  13294 
  13295 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13296     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE1_BCM56980_A0r */
  13297         soc_block_list[5],
  13298         soc_genreg,
  13299         1,
  13300         0,
  13301         0xe011400,
  13302         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13303         0,
  13304         4,
  13305         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r_fields,
  13306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13308         -1,
  13309         -1,
  13310         3,
  13311     },
  13312 #endif /* chips */
  13313 
  13314 #if defined(BCM_56970_A0)
  13315     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE2_BCM56970_A0r */
  13316         soc_block_list[5],
  13317         soc_genreg,
  13318         1,
  13319         0,
  13320         0x5f0d0000,
  13321         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13322         0,
  13323         3,
  13324         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56970_A0r_fields,
  13325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13326         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13327         -1,
  13328         -1,
  13329         3,
  13330     },
  13331 #endif /* chips */
  13332 
  13333 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13334     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE2_BCM56980_A0r */
  13335         soc_block_list[5],
  13336         soc_genreg,
  13337         1,
  13338         0,
  13339         0xe011400,
  13340         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13341         0,
  13342         4,
  13343         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r_fields,
  13344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13346         -1,
  13347         -1,
  13348         3,
  13349     },
  13350 #endif /* chips */
  13351 
  13352 #if defined(BCM_56970_A0)
  13353     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE3_BCM56970_A0r */
  13354         soc_block_list[5],
  13355         soc_genreg,
  13356         1,
  13357         0,
  13358         0x5f0d0000,
  13359         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13360         0,
  13361         3,
  13362         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56970_A0r_fields,
  13363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13364         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13365         -1,
  13366         -1,
  13367         3,
  13368     },
  13369 #endif /* chips */
  13370 
  13371 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13372     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_DBGCTRL_PIPE3_BCM56980_A0r */
  13373         soc_block_list[5],
  13374         soc_genreg,
  13375         1,
  13376         0,
  13377         0xe011400,
  13378         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13379         0,
  13380         4,
  13381         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56980_A0r_fields,
  13382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13384         -1,
  13385         -1,
  13386         3,
  13387     },
  13388 #endif /* chips */
  13389 
  13390 #if defined(BCM_56970_A0)
  13391     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_SERCTRLr */
  13392         soc_block_list[5],
  13393         soc_genreg,
  13394         1,
  13395         0,
  13396         0x5f0e0000,
  13397         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13398         0,
  13399         2,
  13400         soc_IP_MULTICAST_CAM_SERCTRLr_fields,
  13401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13402         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13403         -1,
  13404         -1,
  13405         3,
  13406     },
  13407 #endif /* chips */
  13408 
  13409 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13410     { /* SOC_REG_INT_L2_USER_ENTRY_CAM_SERCTRL_BCM56980_A0r */
  13411         soc_block_list[5],
  13412         soc_genreg,
  13413         1,
  13414         0,
  13415         0xe011500,
  13416         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13417         0,
  13418         4,
  13419         soc_CPU_COS_CAM_SERCTRL_BCM56980_A0r_fields,
  13420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13421         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13422         -1,
  13423         -1,
  13424         3,
  13425     },
  13426 #endif /* chips */
  13427 
  13428 #if defined(BCM_56800_A0)
  13429     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRLr */
  13430         soc_block_list[5],
  13431         soc_genreg,
  13432         1,
  13433         0,
  13434         0x6080c10,
  13435         0,
  13436         0,
  13437         1,
  13438         soc_CFAPMEMDEBUGr_fields,
  13439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13440         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13441         -1,
  13442         -1,
  13443     },
  13444 #endif /* chips */
  13445 
  13446 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13447     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13448     defined(BCM_56160_A0)
  13449     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM53400_A0r */
  13450         soc_block_list[5],
  13451         soc_genreg,
  13452         1,
  13453         0,
  13454         0x1e011400,
  13455         0,
  13456         0,
  13457         1,
  13458         soc_DSCP_CONTROLr_fields,
  13459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13460         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13461         -1,
  13462         -1,
  13463     },
  13464 #endif /* chips */
  13465 
  13466 #if defined(BCM_56142_A0)
  13467     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56142_A0r */
  13468         soc_block_list[5],
  13469         soc_genreg,
  13470         1,
  13471         0,
  13472         0x7080140,
  13473         0,
  13474         0,
  13475         1,
  13476         soc_CFAPMEMDEBUGr_fields,
  13477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13479         -1,
  13480         -1,
  13481     },
  13482 #endif /* chips */
  13483 
  13484 #if defined(BCM_56150_A0)
  13485     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56150_A0r */
  13486         soc_block_list[5],
  13487         soc_genreg,
  13488         1,
  13489         0,
  13490         0x1e010f00,
  13491         0,
  13492         0,
  13493         1,
  13494         soc_INTFO_QCN_SRAM_TMr_fields,
  13495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13496         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13497         -1,
  13498         -1,
  13499     },
  13500 #endif /* chips */
  13501 
  13502 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13503     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56260_A0r */
  13504         soc_block_list[5],
  13505         soc_genreg,
  13506         1,
  13507         0,
  13508         0x1a011400,
  13509         0,
  13510         0,
  13511         1,
  13512         soc_VFP_CAM_CONTROL_TM_7_THRU_0r_fields,
  13513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13514         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13515         -1,
  13516         -1,
  13517     },
  13518 #endif /* chips */
  13519 
  13520 #if defined(BCM_56270_A0)
  13521     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56270_A0r */
  13522         soc_block_list[5],
  13523         soc_genreg,
  13524         1,
  13525         0,
  13526         0x1a011400,
  13527         0,
  13528         0,
  13529         1,
  13530         soc_E2EFC_MEM_TMr_fields,
  13531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13532         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13533         -1,
  13534         -1,
  13535     },
  13536 #endif /* chips */
  13537 
  13538 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  13539     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56334_A0r */
  13540         soc_block_list[5],
  13541         soc_genreg,
  13542         1,
  13543         0,
  13544         0x7080158,
  13545         0,
  13546         0,
  13547         1,
  13548         soc_CFAPMEMDEBUGr_fields,
  13549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13550         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13551         -1,
  13552         -1,
  13553     },
  13554 #endif /* chips */
  13555 
  13556 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13557     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56440_A0r */
  13558         soc_block_list[5],
  13559         soc_genreg,
  13560         1,
  13561         0,
  13562         0x6080311,
  13563         0,
  13564         0,
  13565         1,
  13566         soc_CFAPMEMDEBUG_BCM88732_A0r_fields,
  13567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13568         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13569         -1,
  13570         -1,
  13571     },
  13572 #endif /* chips */
  13573 
  13574 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13575     defined(BCM_56450_B1)
  13576     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56450_A0r */
  13577         soc_block_list[5],
  13578         soc_genreg,
  13579         1,
  13580         0,
  13581         0x1a011200,
  13582         0,
  13583         0,
  13584         1,
  13585         soc_INTFO_QCN_SRAM_TMr_fields,
  13586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13587         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13588         -1,
  13589         -1,
  13590     },
  13591 #endif /* chips */
  13592 
  13593 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13594     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56560_A0r */
  13595         soc_block_list[5],
  13596         soc_genreg,
  13597         1,
  13598         0,
  13599         0x1b0f0000,
  13600         0,
  13601         0,
  13602         2,
  13603         soc_L2_USER_ENTRY_DATA_DBGCTRL_BCM56560_A0r_fields,
  13604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13605         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13606         -1,
  13607         -1,
  13608     },
  13609 #endif /* chips */
  13610 
  13611 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  13612     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  13613     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56624_A0r */
  13614         soc_block_list[5],
  13615         soc_genreg,
  13616         1,
  13617         0,
  13618         0x7080138,
  13619         0,
  13620         0,
  13621         1,
  13622         soc_CFAPMEMDEBUGr_fields,
  13623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13624         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13625         -1,
  13626         -1,
  13627     },
  13628 #endif /* chips */
  13629 
  13630 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  13631     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  13632     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  13633     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56634_A0r */
  13634         soc_block_list[5],
  13635         soc_genreg,
  13636         1,
  13637         0,
  13638         0x708019c,
  13639         0,
  13640         0,
  13641         1,
  13642         soc_CFAPMEMDEBUGr_fields,
  13643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13644         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13645         -1,
  13646         -1,
  13647     },
  13648 #endif /* chips */
  13649 
  13650 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  13651     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56640_A0r */
  13652         soc_block_list[5],
  13653         soc_genreg,
  13654         1,
  13655         0,
  13656         0x1a010600,
  13657         0,
  13658         0,
  13659         2,
  13660         soc_IFP_ING_DVP_2_CONTROL_BCM56640_A0r_fields,
  13661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13662         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13663         -1,
  13664         -1,
  13665     },
  13666 #endif /* chips */
  13667 
  13668 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13669     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56670_A0r */
  13670         soc_block_list[5],
  13671         soc_genreg,
  13672         1,
  13673         0,
  13674         0x1b100000,
  13675         0,
  13676         0,
  13677         1,
  13678         soc_E2EFC_MEM_TMr_fields,
  13679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13680         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13681         -1,
  13682         -1,
  13683     },
  13684 #endif /* chips */
  13685 
  13686 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  13687     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56820_A0r */
  13688         soc_block_list[5],
  13689         soc_genreg,
  13690         1,
  13691         0,
  13692         0x6080c10,
  13693         0,
  13694         0,
  13695         2,
  13696         soc_CFAPMEMDEBUG_BCM56820_A0r_fields,
  13697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13698         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13699         -1,
  13700         -1,
  13701     },
  13702 #endif /* chips */
  13703 
  13704 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  13705     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56840_A0r */
  13706         soc_block_list[5],
  13707         soc_genreg,
  13708         1,
  13709         0,
  13710         0x6080d29,
  13711         0,
  13712         0,
  13713         2,
  13714         soc_IFP_ING_DVP_2_CONTROLr_fields,
  13715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13716         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13717         -1,
  13718         -1,
  13719     },
  13720 #endif /* chips */
  13721 
  13722 #if defined(BCM_56850_A0)
  13723     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56850_A0r */
  13724         soc_block_list[5],
  13725         soc_genreg,
  13726         1,
  13727         0,
  13728         0x1b0d0000,
  13729         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13730         0,
  13731         2,
  13732         soc_IFP_ING_DVP_2_CONTROL_BCM56640_A0r_fields,
  13733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13734         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13735         -1,
  13736         -1,
  13737     },
  13738 #endif /* chips */
  13739 
  13740 #if defined(BCM_56860_A0)
  13741     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56860_A0r */
  13742         soc_block_list[5],
  13743         soc_genreg,
  13744         1,
  13745         0,
  13746         0x1b0f0000,
  13747         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13748         0,
  13749         2,
  13750         soc_L2_USER_ENTRY_DATA_DBGCTRLr_fields,
  13751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13752         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13753         -1,
  13754         -1,
  13755     },
  13756 #endif /* chips */
  13757 
  13758 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13759     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56960_A0r */
  13760         soc_block_list[5],
  13761         soc_genreg,
  13762         1,
  13763         0,
  13764         0x3b160000,
  13765         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13766         0,
  13767         2,
  13768         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13770         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13771         -1,
  13772         -1,
  13773         3,
  13774     },
  13775 #endif /* chips */
  13776 
  13777 #if defined(BCM_56970_A0)
  13778     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_BCM56970_A0r */
  13779         soc_block_list[5],
  13780         soc_genreg,
  13781         1,
  13782         0,
  13783         0x5f150000,
  13784         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13785         0,
  13786         2,
  13787         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13790         -1,
  13791         -1,
  13792         3,
  13793     },
  13794 #endif /* chips */
  13795 
  13796 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13797     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_PIPE0r */
  13798         soc_block_list[5],
  13799         soc_genreg,
  13800         1,
  13801         0,
  13802         0x3b160000,
  13803         0,
  13804         0,
  13805         2,
  13806         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13808         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13809         -1,
  13810         -1,
  13811         3,
  13812     },
  13813 #endif /* chips */
  13814 
  13815 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13816     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_PIPE1r */
  13817         soc_block_list[5],
  13818         soc_genreg,
  13819         1,
  13820         0,
  13821         0x3b160000,
  13822         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13823         0,
  13824         2,
  13825         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13828         -1,
  13829         -1,
  13830         3,
  13831     },
  13832 #endif /* chips */
  13833 
  13834 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13835     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_PIPE2r */
  13836         soc_block_list[5],
  13837         soc_genreg,
  13838         1,
  13839         0,
  13840         0x3b160000,
  13841         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13842         0,
  13843         2,
  13844         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13846         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13847         -1,
  13848         -1,
  13849         3,
  13850     },
  13851 #endif /* chips */
  13852 
  13853 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13854     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_PIPE3r */
  13855         soc_block_list[5],
  13856         soc_genreg,
  13857         1,
  13858         0,
  13859         0x3b160000,
  13860         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13861         0,
  13862         2,
  13863         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13865         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13866         -1,
  13867         -1,
  13868         3,
  13869     },
  13870 #endif /* chips */
  13871 
  13872 #if defined(BCM_56970_A0)
  13873     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_PIPE0_BCM56970_A0r */
  13874         soc_block_list[5],
  13875         soc_genreg,
  13876         1,
  13877         0,
  13878         0x5f150000,
  13879         0,
  13880         0,
  13881         2,
  13882         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13884         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13885         -1,
  13886         -1,
  13887         3,
  13888     },
  13889 #endif /* chips */
  13890 
  13891 #if defined(BCM_56970_A0)
  13892     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_PIPE1_BCM56970_A0r */
  13893         soc_block_list[5],
  13894         soc_genreg,
  13895         1,
  13896         0,
  13897         0x5f150000,
  13898         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13899         0,
  13900         2,
  13901         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13904         -1,
  13905         -1,
  13906         3,
  13907     },
  13908 #endif /* chips */
  13909 
  13910 #if defined(BCM_56970_A0)
  13911     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_PIPE2_BCM56970_A0r */
  13912         soc_block_list[5],
  13913         soc_genreg,
  13914         1,
  13915         0,
  13916         0x5f150000,
  13917         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13918         0,
  13919         2,
  13920         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13922         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13923         -1,
  13924         -1,
  13925         3,
  13926     },
  13927 #endif /* chips */
  13928 
  13929 #if defined(BCM_56970_A0)
  13930     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_DBGCTRL_PIPE3_BCM56970_A0r */
  13931         soc_block_list[5],
  13932         soc_genreg,
  13933         1,
  13934         0,
  13935         0x5f150000,
  13936         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13937         0,
  13938         2,
  13939         soc_IFP_ING_DVP_2_CONTROL_BCM56960_A0r_fields,
  13940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13941         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13942         -1,
  13943         -1,
  13944         3,
  13945     },
  13946 #endif /* chips */
  13947 
  13948 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13949     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13950     defined(BCM_56160_A0)
  13951     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_ONLY_PARITY_CONTROLr */
  13952         soc_block_list[5],
  13953         soc_genreg,
  13954         1,
  13955         0,
  13956         0x1e011900,
  13957         0,
  13958         0,
  13959         1,
  13960         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  13961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13962         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13963         -1,
  13964         -1,
  13965     },
  13966 #endif /* chips */
  13967 
  13968 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13969     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13970     defined(BCM_56160_A0)
  13971     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_ONLY_PARITY_STATUSr */
  13972         soc_block_list[5],
  13973         soc_genreg,
  13974         1,
  13975         0,
  13976         0x1e011a00,
  13977         0,
  13978         0,
  13979         3,
  13980         soc_EGR_XP0_DBITS_PARITY_STATUSr_fields,
  13981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13982         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13983         -1,
  13984         -1,
  13985     },
  13986 #endif /* chips */
  13987 
  13988 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  13989     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  13990     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  13991     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_CONTROLr */
  13992         soc_block_list[5],
  13993         soc_genreg,
  13994         1,
  13995         0,
  13996         0x708018a,
  13997         0,
  13998         0,
  13999         1,
  14000         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  14001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14002         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  14003         -1,
  14004         -1,
  14005     },
  14006 #endif /* chips */
  14007 
  14008 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14009     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_CONTROL_BCM56560_A0r */
  14010         soc_block_list[5],
  14011         soc_genreg,
  14012         1,
  14013         0,
  14014         0x1b0d0000,
  14015         0,
  14016         0,
  14017         1,
  14018         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  14019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14020         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14021         -1,
  14022         -1,
  14023     },
  14024 #endif /* chips */
  14025 
  14026 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  14027     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_CONTROL_BCM56840_A0r */
  14028         soc_block_list[5],
  14029         soc_genreg,
  14030         1,
  14031         0,
  14032         0x6080d23,
  14033         0,
  14034         0,
  14035         1,
  14036         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  14037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14038         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14039         -1,
  14040         -1,
  14041     },
  14042 #endif /* chips */
  14043 
  14044 #if defined(BCM_56850_A0)
  14045     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_CONTROL_BCM56850_A0r */
  14046         soc_block_list[5],
  14047         soc_genreg,
  14048         1,
  14049         0,
  14050         0x1b0b0000,
  14051         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14052         0,
  14053         1,
  14054         soc_FT_CNTR_SER_CONTROLr_fields,
  14055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14056         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14057         -1,
  14058         -1,
  14059     },
  14060 #endif /* chips */
  14061 
  14062 #if defined(BCM_56860_A0)
  14063     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_CONTROL_BCM56860_A0r */
  14064         soc_block_list[5],
  14065         soc_genreg,
  14066         1,
  14067         0,
  14068         0x1b0d0000,
  14069         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14070         0,
  14071         1,
  14072         soc_FT_CNTR_SER_CONTROLr_fields,
  14073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14074         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14075         -1,
  14076         -1,
  14077     },
  14078 #endif /* chips */
  14079 
  14080 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  14081     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_CONTROL_BCM56960_A0r */
  14082         soc_block_list[5],
  14083         soc_genreg,
  14084         1,
  14085         0,
  14086         0x3b150000,
  14087         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14088         0,
  14089         1,
  14090         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  14091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14092         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14093         -1,
  14094         -1,
  14095         3,
  14096     },
  14097 #endif /* chips */
  14098 
  14099 #if defined(BCM_56970_A0)
  14100     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_CONTROL_BCM56970_A0r */
  14101         soc_block_list[5],
  14102         soc_genreg,
  14103         1,
  14104         0,
  14105         0x5f140000,
  14106         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14107         0,
  14108         2,
  14109         soc_L2_USER_ENTRY_DATA_PARITY_CONTROL_BCM56970_A0r_fields,
  14110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14112         -1,
  14113         -1,
  14114         3,
  14115     },
  14116 #endif /* chips */
  14117 
  14118 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  14119     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  14120     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  14121     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_STATUS_INTRr */
  14122         soc_block_list[5],
  14123         soc_genreg,
  14124         1,
  14125         0,
  14126         0x708018b,
  14127         0,
  14128         0,
  14129         3,
  14130         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  14131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14132         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  14133         -1,
  14134         -1,
  14135     },
  14136 #endif /* chips */
  14137 
  14138 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  14139     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_STATUS_INTR_BCM56840_A0r */
  14140         soc_block_list[5],
  14141         soc_genreg,
  14142         1,
  14143         0,
  14144         0x6080d24,
  14145         0,
  14146         0,
  14147         3,
  14148         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  14149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14150         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14151         -1,
  14152         -1,
  14153     },
  14154 #endif /* chips */
  14155 
  14156 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  14157     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  14158     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  14159     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_STATUS_NACKr */
  14160         soc_block_list[5],
  14161         soc_genreg,
  14162         1,
  14163         0,
  14164         0x708018c,
  14165         0,
  14166         0,
  14167         3,
  14168         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  14169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14170         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  14171         -1,
  14172         -1,
  14173     },
  14174 #endif /* chips */
  14175 
  14176 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  14177     { /* SOC_REG_INT_L2_USER_ENTRY_DATA_PARITY_STATUS_NACK_BCM56840_A0r */
  14178         soc_block_list[5],
  14179         soc_genreg,
  14180         1,
  14181         0,
  14182         0x6080d25,
  14183         0,
  14184         0,
  14185         3,
  14186         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  14187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14188         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14189         -1,
  14190         -1,
  14191     },
  14192 #endif /* chips */
  14193 
  14194 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  14195     { /* SOC_REG_INT_L2_USER_ENTRY_DBGCTRLr */
  14196         soc_block_list[5],
  14197         soc_genreg,
  14198         1,
  14199         0,
  14200         0x6080c0a,
  14201         0,
  14202         0,
  14203         1,
  14204         soc_FP_CAM_CONTROLr_fields,
  14205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14206         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14207         -1,
  14208         -1,
  14209     },
  14210 #endif /* chips */
  14211 
  14212 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  14213     defined(BCM_56870_A0)
  14214     { /* SOC_REG_INT_L2_USER_ENTRY_ONLY_CAM_BIST_CONFIG_64r */
  14215         soc_block_list[5],
  14216         soc_genreg,
  14217         1,
  14218         0,
  14219         0x6b040000,
  14220         SOC_REG_FLAG_64_BITS |
  14221                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14222         0,
  14223         6,
  14224         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  14225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14226         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14227         -1,
  14228         -1,
  14229         3,
  14230     },
  14231 #endif /* chips */
  14232 
  14233 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  14234     defined(BCM_56870_A0)
  14235     { /* SOC_REG_INT_L2_USER_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE0r */
  14236         soc_block_list[5],
  14237         soc_genreg,
  14238         1,
  14239         0,
  14240         0x6b040000,
  14241         SOC_REG_FLAG_64_BITS,
  14242         0,
  14243         6,
  14244         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  14245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14246         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14247         -1,
  14248         -1,
  14249         3,
  14250     },
  14251 #endif /* chips */
  14252 
  14253 #if defined(BCM_56870_A0)
  14254     { /* SOC_REG_INT_L2_USER_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE1r */
  14255         soc_block_list[5],
  14256         soc_genreg,
  14257         1,
  14258         0,
  14259         0x6b040000,
  14260         SOC_REG_FLAG_64_BITS |
  14261                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14262         0,
  14263         6,
  14264         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  14265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14266         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14267         -1,
  14268         -1,
  14269         3,
  14270     },
  14271 #endif /* chips */
  14272 
  14273 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  14274     defined(BCM_56870_A0)
  14275     { /* SOC_REG_INT_L2_USER_ENTRY_ONLY_CAM_BIST_STATUSr */
  14276         soc_block_list[5],
  14277         soc_genreg,
  14278         1,
  14279         0,
  14280         0x6b030000,
  14281         SOC_REG_FLAG_RO |
  14282                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14283         0,
  14284         1,
  14285         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14288         -1,
  14289         -1,
  14290         3,
  14291     },
  14292 #endif /* chips */
  14293 
  14294 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  14295     defined(BCM_56870_A0)
  14296     { /* SOC_REG_INT_L2_USER_ENTRY_ONLY_CAM_BIST_STATUS_PIPE0r */
  14297         soc_block_list[5],
  14298         soc_genreg,
  14299         1,
  14300         0,
  14301         0x6b030000,
  14302         SOC_REG_FLAG_RO,
  14303         0,
  14304         1,
  14305         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14308         -1,
  14309         -1,
  14310         3,
  14311     },
  14312 #endif /* chips */
  14313 
  14314 #if defined(BCM_56870_A0)
  14315     { /* SOC_REG_INT_L2_USER_ENTRY_ONLY_CAM_BIST_STATUS_PIPE1r */
  14316         soc_block_list[5],
  14317         soc_genreg,
  14318         1,
  14319         0,
  14320         0x6b030000,
  14321         SOC_REG_FLAG_RO |
  14322                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14323         0,
  14324         1,
  14325         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14328         -1,
  14329         -1,
  14330         3,
  14331     },
  14332 #endif /* chips */
  14333 
  14334 #if defined(BCM_56800_A0)
  14335     { /* SOC_REG_INT_L3MC_DBGCTRLr */
  14336         soc_block_list[5],
  14337         soc_genreg,
  14338         1,
  14339         0,
  14340         0x9080c00,
  14341         0,
  14342         0,
  14343         1,
  14344         soc_CFAPMEMDEBUGr_fields,
  14345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14346         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14347         -1,
  14348         -1,
  14349     },
  14350 #endif /* chips */
  14351 
  14352 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14353     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14354     defined(BCM_56160_A0)
  14355     { /* SOC_REG_INT_L3MC_DBGCTRL_BCM53400_A0r */
  14356         soc_block_list[5],
  14357         soc_genreg,
  14358         1,
  14359         0,
  14360         0x2e010000,
  14361         0,
  14362         0,
  14363         1,
  14364         soc_DSCP_CONTROLr_fields,
  14365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14366         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14367         -1,
  14368         -1,
  14369     },
  14370 #endif /* chips */
  14371 
  14372 #if defined(BCM_56142_A0)
  14373     { /* SOC_REG_INT_L3MC_DBGCTRL_BCM56142_A0r */
  14374         soc_block_list[5],
  14375         soc_genreg,
  14376         1,
  14377         0,
  14378         0xb08015d,
  14379         0,
  14380         0,
  14381         1,
  14382         soc_CFAPMEMDEBUGr_fields,
  14383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14384         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14385         -1,
  14386         -1,
  14387     },
  14388 #endif /* chips */
  14389 
  14390 #if defined(BCM_56150_A0)
  14391     { /* SOC_REG_INT_L3MC_DBGCTRL_BCM56150_A0r */
  14392         soc_block_list[5],
  14393         soc_genreg,
  14394         1,
  14395         0,
  14396         0x2e010000,
  14397         0,
  14398         0,
  14399         1,
  14400         soc_INTFO_QCN_SRAM_TMr_fields,
  14401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14402         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14403         -1,
  14404         -1,
  14405     },
  14406 #endif /* chips */
  14407 
  14408 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  14409     { /* SOC_REG_INT_L3MC_DBGCTRL_BCM56334_A0r */
  14410         soc_block_list[5],
  14411         soc_genreg,
  14412         1,
  14413         0,
  14414         0xb080180,
  14415         0,
  14416         0,
  14417         1,
  14418         soc_CFAPMEMDEBUGr_fields,
  14419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14420         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14421         -1,
  14422         -1,
  14423     },
  14424 #endif /* chips */
  14425 
  14426 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  14427     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  14428     { /* SOC_REG_INT_L3MC_DBGCTRL_BCM56624_A0r */
  14429         soc_block_list[5],
  14430         soc_genreg,
  14431         1,
  14432         0,
  14433         0xb08015b,
  14434         0,
  14435         0,
  14436         1,
  14437         soc_CFAPMEMDEBUGr_fields,
  14438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14439         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14440         -1,
  14441         -1,
  14442     },
  14443 #endif /* chips */
  14444 
  14445 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  14446     { /* SOC_REG_INT_L3MC_DBGCTRL_BCM56820_A0r */
  14447         soc_block_list[5],
  14448         soc_genreg,
  14449         1,
  14450         0,
  14451         0x9080c00,
  14452         0,
  14453         0,
  14454         2,
  14455         soc_CFAPMEMDEBUG_BCM56820_A0r_fields,
  14456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14457         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14458         -1,
  14459         -1,
  14460     },
  14461 #endif /* chips */
  14462 
  14463 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  14464     { /* SOC_REG_INT_L3MC_PARITY_CONTROLr */
  14465         soc_block_list[5],
  14466         soc_genreg,
  14467         1,
  14468         0,
  14469         0x9080c01,
  14470         0,
  14471         0,
  14472         2,
  14473         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  14474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14475         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14476         -1,
  14477         -1,
  14478     },
  14479 #endif /* chips */
  14480 
  14481 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14482     defined(BCM_56160_A0)
  14483     { /* SOC_REG_INT_L3MC_PARITY_CONTROL_BCM53400_A0r */
  14484         soc_block_list[5],
  14485         soc_genreg,
  14486         1,
  14487         0,
  14488         0x2e010100,
  14489         0,
  14490         0,
  14491         1,
  14492         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  14493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14494         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  14495         -1,
  14496         -1,
  14497     },
  14498 #endif /* chips */
  14499 
  14500 #if defined(BCM_56142_A0)
  14501     { /* SOC_REG_INT_L3MC_PARITY_CONTROL_BCM56142_A0r */
  14502         soc_block_list[5],
  14503         soc_genreg,
  14504         1,
  14505         0,
  14506         0xb08015e,
  14507         0,
  14508         0,
  14509         1,
  14510         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  14511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14512         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  14513         -1,
  14514         -1,
  14515     },
  14516 #endif /* chips */
  14517 
  14518 #if defined(BCM_56150_A0)
  14519     { /* SOC_REG_INT_L3MC_PARITY_CONTROL_BCM56150_A0r */
  14520         soc_block_list[5],
  14521         soc_genreg,
  14522         1,
  14523         0,
  14524         0x2e010100,
  14525         0,
  14526         0,
  14527         1,
  14528         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  14529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14530         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  14531         -1,
  14532         -1,
  14533     },
  14534 #endif /* chips */
  14535 
  14536 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  14537     { /* SOC_REG_INT_L3MC_PARITY_CONTROL_BCM56334_A0r */
  14538         soc_block_list[5],
  14539         soc_genreg,
  14540         1,
  14541         0,
  14542         0xb080181,
  14543         0,
  14544         0,
  14545         1,
  14546         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  14547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14548         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  14549         -1,
  14550         -1,
  14551     },
  14552 #endif /* chips */
  14553 
  14554 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  14555     { /* SOC_REG_INT_L3MC_PARITY_STATUSr */
  14556         soc_block_list[5],
  14557         soc_genreg,
  14558         1,
  14559         0,
  14560         0x9080c02,
  14561         SOC_REG_FLAG_RO,
  14562         0,
  14563         2,
  14564         soc_L3MC_PARITY_STATUSr_fields,
  14565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14566         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  14567         -1,
  14568         -1,
  14569     },
  14570 #endif /* chips */
  14571 
  14572 #if defined(BCM_53400_A0)
  14573     { /* SOC_REG_INT_L3MC_PARITY_STATUS_BCM53400_A0r */
  14574         soc_block_list[5],
  14575         soc_genreg,
  14576         1,
  14577         0,
  14578         0x2e010200,
  14579         0,
  14580         0,
  14581         3,
  14582         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  14583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14584         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14585         -1,
  14586         -1,
  14587     },
  14588 #endif /* chips */
  14589 
  14590 #if defined(BCM_53540_A0)
  14591     { /* SOC_REG_INT_L3MC_PARITY_STATUS_BCM53540_A0r */
  14592         soc_block_list[5],
  14593         soc_genreg,
  14594         1,
  14595         0,
  14596         0x2e010200,
  14597         0,
  14598         0,
  14599         3,
  14600         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUSr_fields,
  14601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14602         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14603         -1,
  14604         -1,
  14605     },
  14606 #endif /* chips */
  14607 
  14608 #if defined(BCM_56142_A0)
  14609     { /* SOC_REG_INT_L3MC_PARITY_STATUS_BCM56142_A0r */
  14610         soc_block_list[5],
  14611         soc_genreg,
  14612         1,
  14613         0,
  14614         0xb08015f,
  14615         0,
  14616         0,
  14617         3,
  14618         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  14619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14620         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14621         -1,
  14622         -1,
  14623     },
  14624 #endif /* chips */
  14625 
  14626 #if defined(BCM_56150_A0)
  14627     { /* SOC_REG_INT_L3MC_PARITY_STATUS_BCM56150_A0r */
  14628         soc_block_list[5],
  14629         soc_genreg,
  14630         1,
  14631         0,
  14632         0x2e010200,
  14633         0,
  14634         0,
  14635         3,
  14636         soc_FP_FIELD_SEL_PARITY_STATUS_INTRr_fields,
  14637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14638         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  14639         -1,
  14640         -1,
  14641     },
  14642 #endif /* chips */
  14643 
  14644 #if defined(BCM_56160_A0)
  14645     { /* SOC_REG_INT_L3MC_PARITY_STATUS_BCM56160_A0r */
  14646         soc_block_list[5],
  14647         soc_genreg,
  14648         1,
  14649         0,
  14650         0x2e010200,
  14651         0,
  14652         0,
  14653         3,
  14654         soc_EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr_fields,
  14655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14656         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  14657         -1,
  14658         -1,
  14659     },
  14660 #endif /* chips */
  14661 
  14662 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  14663     { /* SOC_REG_INT_L3MC_PARITY_STATUS_BCM56334_A0r */
  14664         soc_block_list[5],
  14665         soc_genreg,
  14666         1,
  14667         0,
  14668         0xb080182,
  14669         0,
  14670         0,
  14671         3,
  14672         soc_EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr_fields,
  14673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14674         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  14675         -1,
  14676         -1,
  14677     },
  14678 #endif /* chips */
  14679 
  14680 #if defined(BCM_56514_A0)
  14681     { /* SOC_REG_INT_L3_AUX_HASH_CONTROLr */
  14682         soc_block_list[5],
  14683         soc_genreg,
  14684         1,
  14685         0,
  14686         0x808000e,
  14687         0,
  14688         0,
  14689         2,
  14690         soc_L2_AUX_HASH_CONTROLr_fields,
  14691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14692         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  14693         -1,
  14694         -1,
  14695     },
  14696 #endif /* chips */
  14697 
  14698 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14699     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14700     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14701     defined(BCM_56260_B0) || defined(BCM_56270_A0)
  14702     { /* SOC_REG_INT_L3_AUX_HASH_CONTROL_BCM53400_A0r */
  14703         soc_block_list[5],
  14704         soc_genreg,
  14705         1,
  14706         0,
  14707         0x26000000,
  14708         0,
  14709         0,
  14710         3,
  14711         soc_L2_AUX_HASH_CONTROL_BCM53400_A0r_fields,
  14712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14713         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  14714         -1,
  14715         -1,
  14716     },
  14717 #endif /* chips */
  14718 
  14719 #if defined(BCM_56142_A0)
  14720     { /* SOC_REG_INT_L3_AUX_HASH_CONTROL_BCM56142_A0r */
  14721         soc_block_list[5],
  14722         soc_genreg,
  14723         1,
  14724         0,
  14725         0xa080010,
  14726         0,
  14727         0,
  14728         3,
  14729         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
  14730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14731         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  14732         -1,
  14733         -1,
  14734     },
  14735 #endif /* chips */
  14736 
  14737 #if defined(BCM_56150_A0)
  14738     { /* SOC_REG_INT_L3_AUX_HASH_CONTROL_BCM56150_A0r */
  14739         soc_block_list[5],
  14740         soc_genreg,
  14741         1,
  14742         0,
  14743         0x2a000000,
  14744         0,
  14745         0,
  14746         3,
  14747         soc_L2_AUX_HASH_CONTROL_BCM56450_A0r_fields,
  14748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14749         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  14750         -1,
  14751         -1,
  14752     },
  14753 #endif /* chips */
  14754 
  14755 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  14756     { /* SOC_REG_INT_L3_AUX_HASH_CONTROL_BCM56224_A0r */
  14757         soc_block_list[5],
  14758         soc_genreg,
  14759         1,
  14760         0,
  14761         0x8080007,
  14762         0,
  14763         0,
  14764         2,
  14765         soc_L2_AUX_HASH_CONTROLr_fields,
  14766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14767         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  14768         -1,
  14769         -1,
  14770     },
  14771 #endif /* chips */
  14772 
  14773 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14774     defined(BCM_56450_B1)
  14775     { /* SOC_REG_INT_L3_AUX_HASH_CONTROL_BCM56450_A0r */
  14776         soc_block_list[5],
  14777         soc_genreg,
  14778         1,
  14779         0,
  14780         0x26000000,
  14781         0,
  14782         0,
  14783         3,
  14784         soc_L2_AUX_HASH_CONTROL_BCM56450_A0r_fields,
  14785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14786         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  14787         -1,
  14788         -1,
  14789     },
  14790 #endif /* chips */
  14791 
  14792 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  14793     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  14794     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  14795     { /* SOC_REG_INT_L3_AUX_HASH_CONTROL_BCM56624_A0r */
  14796         soc_block_list[5],
  14797         soc_genreg,
  14798         1,
  14799         0,
  14800         0xa080010,
  14801         0,
  14802         0,
  14803         3,
  14804         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
  14805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14806         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  14807         -1,
  14808         -1,
  14809     },
  14810 #endif /* chips */
  14811 
  14812 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  14813     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  14814     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  14815     { /* SOC_REG_INT_L3_AUX_HASH_CONTROL_BCM56634_A0r */
  14816         soc_block_list[5],
  14817         soc_genreg,
  14818         1,
  14819         0,
  14820         0x9080000,
  14821         0,
  14822         0,
  14823         3,
  14824         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
  14825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14826         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  14827         -1,
  14828         -1,
  14829     },
  14830 #endif /* chips */
  14831 
  14832 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  14833     { /* SOC_REG_INT_L3_AUX_HASH_CONTROL_BCM56820_A0r */
  14834         soc_block_list[5],
  14835         soc_genreg,
  14836         1,
  14837         0,
  14838         0x808060f,
  14839         0,
  14840         0,
  14841         3,
  14842         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
  14843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14844         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  14845         -1,
  14846         -1,
  14847     },
  14848 #endif /* chips */
  14849 
  14850 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  14851     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  14852     { /* SOC_REG_INT_L3_AUX_HASH_CONTROL_BCM56840_A0r */
  14853         soc_block_list[5],
  14854         soc_genreg,
  14855         1,
  14856         0,
  14857         0x9080600,
  14858         0,
  14859         0,
  14860         3,
  14861         soc_L2_AUX_HASH_CONTROL_BCM56624_A0r_fields,
  14862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14863         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  14864         -1,
  14865         -1,
  14866     },
  14867 #endif /* chips */
  14868 
  14869 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  14870     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  14871     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONFIGr */
  14872         soc_block_list[5],
  14873         soc_genreg,
  14874         1,
  14875         0,
  14876         0xa080157,
  14877         0,
  14878         0,
  14879         4,
  14880         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  14881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14882         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14883         -1,
  14884         -1,
  14885     },
  14886 #endif /* chips */
  14887 
  14888 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  14889     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONFIG_BCM56334_A0r */
  14890         soc_block_list[5],
  14891         soc_genreg,
  14892         1,
  14893         0,
  14894         0xa08017c,
  14895         0,
  14896         0,
  14897         4,
  14898         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  14899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14901         -1,
  14902         -1,
  14903     },
  14904 #endif /* chips */
  14905 
  14906 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  14907     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONFIG_BCM56440_A0r */
  14908         soc_block_list[5],
  14909         soc_genreg,
  14910         1,
  14911         0,
  14912         0xa080d0f,
  14913         0,
  14914         0,
  14915         4,
  14916         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  14917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14919         -1,
  14920         -1,
  14921     },
  14922 #endif /* chips */
  14923 
  14924 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  14925     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  14926     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  14927     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONFIG_BCM56634_A0r */
  14928         soc_block_list[5],
  14929         soc_genreg,
  14930         1,
  14931         0,
  14932         0x90801ba,
  14933         0,
  14934         0,
  14935         4,
  14936         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  14937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14938         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14939         -1,
  14940         -1,
  14941     },
  14942 #endif /* chips */
  14943 
  14944 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  14945     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONFIG_BCM56820_A0r */
  14946         soc_block_list[5],
  14947         soc_genreg,
  14948         1,
  14949         0,
  14950         0x8080d03,
  14951         0,
  14952         0,
  14953         4,
  14954         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  14955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14956         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14957         -1,
  14958         -1,
  14959     },
  14960 #endif /* chips */
  14961 
  14962 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  14963     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONFIG_BCM56840_A0r */
  14964         soc_block_list[5],
  14965         soc_genreg,
  14966         1,
  14967         0,
  14968         0xa080d10,
  14969         0,
  14970         0,
  14971         4,
  14972         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  14973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14974         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14975         -1,
  14976         -1,
  14977     },
  14978 #endif /* chips */
  14979 
  14980 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  14981     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  14982     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONTROLr */
  14983         soc_block_list[5],
  14984         soc_genreg,
  14985         1,
  14986         0,
  14987         0xa080155,
  14988         0,
  14989         0,
  14990         4,
  14991         soc_L3_DEFIP_128_CAM_BIST_CONTROLr_fields,
  14992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14994         -1,
  14995         -1,
  14996     },
  14997 #endif /* chips */
  14998 
  14999 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  15000     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONTROL_BCM56334_A0r */
  15001         soc_block_list[5],
  15002         soc_genreg,
  15003         1,
  15004         0,
  15005         0xa08017a,
  15006         0,
  15007         0,
  15008         4,
  15009         soc_L3_DEFIP_128_CAM_BIST_CONTROLr_fields,
  15010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15012         -1,
  15013         -1,
  15014     },
  15015 #endif /* chips */
  15016 
  15017 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  15018     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONTROL_BCM56440_A0r */
  15019         soc_block_list[5],
  15020         soc_genreg,
  15021         1,
  15022         0,
  15023         0xa080d0d,
  15024         0,
  15025         0,
  15026         4,
  15027         soc_L3_DEFIP_128_CAM_BIST_CONTROLr_fields,
  15028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15030         -1,
  15031         -1,
  15032     },
  15033 #endif /* chips */
  15034 
  15035 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15036     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15037     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15038     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONTROL_BCM56634_A0r */
  15039         soc_block_list[5],
  15040         soc_genreg,
  15041         1,
  15042         0,
  15043         0x90801b8,
  15044         0,
  15045         0,
  15046         4,
  15047         soc_L3_DEFIP_128_CAM_BIST_CONTROLr_fields,
  15048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15050         -1,
  15051         -1,
  15052     },
  15053 #endif /* chips */
  15054 
  15055 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  15056     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONTROL_BCM56820_A0r */
  15057         soc_block_list[5],
  15058         soc_genreg,
  15059         1,
  15060         0,
  15061         0x8080d01,
  15062         0,
  15063         0,
  15064         5,
  15065         soc_L3_DEFIP_128_CAM_BIST_CONTROL_BCM56820_A0r_fields,
  15066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15067         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15068         -1,
  15069         -1,
  15070     },
  15071 #endif /* chips */
  15072 
  15073 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15074     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_CONTROL_BCM56840_A0r */
  15075         soc_block_list[5],
  15076         soc_genreg,
  15077         1,
  15078         0,
  15079         0xa080d0e,
  15080         0,
  15081         0,
  15082         4,
  15083         soc_L3_DEFIP_128_CAM_BIST_CONTROLr_fields,
  15084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15086         -1,
  15087         -1,
  15088     },
  15089 #endif /* chips */
  15090 
  15091 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  15092     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  15093     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_DBG_DATAr */
  15094         soc_block_list[5],
  15095         soc_genreg,
  15096         1,
  15097         0,
  15098         0xa080158,
  15099         0,
  15100         0,
  15101         1,
  15102         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  15103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15105         -1,
  15106         -1,
  15107     },
  15108 #endif /* chips */
  15109 
  15110 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  15111     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_DBG_DATA_BCM56334_A0r */
  15112         soc_block_list[5],
  15113         soc_genreg,
  15114         1,
  15115         0,
  15116         0xa08017d,
  15117         0,
  15118         0,
  15119         1,
  15120         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  15121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15122         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15123         -1,
  15124         -1,
  15125     },
  15126 #endif /* chips */
  15127 
  15128 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  15129     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_DBG_DATA_BCM56440_A0r */
  15130         soc_block_list[5],
  15131         soc_genreg,
  15132         1,
  15133         0,
  15134         0xa080d10,
  15135         0,
  15136         0,
  15137         1,
  15138         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  15139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15141         -1,
  15142         -1,
  15143     },
  15144 #endif /* chips */
  15145 
  15146 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15147     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15148     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15149     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_DBG_DATA_BCM56634_A0r */
  15150         soc_block_list[5],
  15151         soc_genreg,
  15152         1,
  15153         0,
  15154         0x90801bb,
  15155         0,
  15156         0,
  15157         1,
  15158         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  15159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15161         -1,
  15162         -1,
  15163     },
  15164 #endif /* chips */
  15165 
  15166 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  15167     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_DBG_DATA_BCM56820_A0r */
  15168         soc_block_list[5],
  15169         soc_genreg,
  15170         1,
  15171         0,
  15172         0x8080d04,
  15173         0,
  15174         0,
  15175         1,
  15176         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  15177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15178         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15179         -1,
  15180         -1,
  15181     },
  15182 #endif /* chips */
  15183 
  15184 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15185     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_DBG_DATA_BCM56840_A0r */
  15186         soc_block_list[5],
  15187         soc_genreg,
  15188         1,
  15189         0,
  15190         0xa080d11,
  15191         0,
  15192         0,
  15193         1,
  15194         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  15195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15196         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15197         -1,
  15198         -1,
  15199     },
  15200 #endif /* chips */
  15201 
  15202 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  15203     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  15204     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_STATUSr */
  15205         soc_block_list[5],
  15206         soc_genreg,
  15207         1,
  15208         0,
  15209         0xa080156,
  15210         SOC_REG_FLAG_RO,
  15211         0,
  15212         1,
  15213         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  15214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15215         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15216         -1,
  15217         -1,
  15218     },
  15219 #endif /* chips */
  15220 
  15221 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  15222     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_STATUS_BCM56334_A0r */
  15223         soc_block_list[5],
  15224         soc_genreg,
  15225         1,
  15226         0,
  15227         0xa08017b,
  15228         SOC_REG_FLAG_RO,
  15229         0,
  15230         1,
  15231         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  15232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15233         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15234         -1,
  15235         -1,
  15236     },
  15237 #endif /* chips */
  15238 
  15239 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  15240     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_STATUS_BCM56440_A0r */
  15241         soc_block_list[5],
  15242         soc_genreg,
  15243         1,
  15244         0,
  15245         0xa080d0e,
  15246         SOC_REG_FLAG_RO,
  15247         0,
  15248         1,
  15249         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  15250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15252         -1,
  15253         -1,
  15254     },
  15255 #endif /* chips */
  15256 
  15257 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15258     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15259     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15260     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_STATUS_BCM56634_A0r */
  15261         soc_block_list[5],
  15262         soc_genreg,
  15263         1,
  15264         0,
  15265         0x90801b9,
  15266         SOC_REG_FLAG_RO,
  15267         0,
  15268         1,
  15269         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  15270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15272         -1,
  15273         -1,
  15274     },
  15275 #endif /* chips */
  15276 
  15277 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  15278     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_STATUS_BCM56820_A0r */
  15279         soc_block_list[5],
  15280         soc_genreg,
  15281         1,
  15282         0,
  15283         0x8080d02,
  15284         SOC_REG_FLAG_RO,
  15285         0,
  15286         1,
  15287         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  15288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15289         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15290         -1,
  15291         -1,
  15292     },
  15293 #endif /* chips */
  15294 
  15295 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15296     { /* SOC_REG_INT_L3_DEFIP_128_CAM_BIST_STATUS_BCM56840_A0r */
  15297         soc_block_list[5],
  15298         soc_genreg,
  15299         1,
  15300         0,
  15301         0xa080d0f,
  15302         SOC_REG_FLAG_RO,
  15303         0,
  15304         1,
  15305         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  15306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15308         -1,
  15309         -1,
  15310     },
  15311 #endif /* chips */
  15312 
  15313 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  15314     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  15315     { /* SOC_REG_INT_L3_DEFIP_128_CAM_DBGCTRLr */
  15316         soc_block_list[5],
  15317         soc_genreg,
  15318         1,
  15319         0,
  15320         0xa080153,
  15321         0,
  15322         0,
  15323         2,
  15324         soc_L3_DEFIP_128_CAM_DBGCTRLr_fields,
  15325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15326         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15327         -1,
  15328         -1,
  15329     },
  15330 #endif /* chips */
  15331 
  15332 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  15333     { /* SOC_REG_INT_L3_DEFIP_128_CAM_DBGCTRL0r */
  15334         soc_block_list[5],
  15335         soc_genreg,
  15336         1,
  15337         0,
  15338         0x8080d00,
  15339         0,
  15340         0,
  15341         1,
  15342         soc_L3_DEFIP_CAM_DBGCTRL0r_fields,
  15343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15345         -1,
  15346         -1,
  15347     },
  15348 #endif /* chips */
  15349 
  15350 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  15351     { /* SOC_REG_INT_L3_DEFIP_128_CAM_DBGCTRL_BCM56334_A0r */
  15352         soc_block_list[5],
  15353         soc_genreg,
  15354         1,
  15355         0,
  15356         0xa080178,
  15357         0,
  15358         0,
  15359         2,
  15360         soc_L3_DEFIP_128_CAM_DBGCTRLr_fields,
  15361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15362         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15363         -1,
  15364         -1,
  15365     },
  15366 #endif /* chips */
  15367 
  15368 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  15369     { /* SOC_REG_INT_L3_DEFIP_128_CAM_DBGCTRL_BCM56440_A0r */
  15370         soc_block_list[5],
  15371         soc_genreg,
  15372         1,
  15373         0,
  15374         0xa080d0b,
  15375         0,
  15376         0,
  15377         2,
  15378         soc_L3_DEFIP_128_CAM_DBGCTRL_BCM56840_A0r_fields,
  15379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15380         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15381         -1,
  15382         -1,
  15383     },
  15384 #endif /* chips */
  15385 
  15386 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15387     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15388     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15389     { /* SOC_REG_INT_L3_DEFIP_128_CAM_DBGCTRL_BCM56634_A0r */
  15390         soc_block_list[5],
  15391         soc_genreg,
  15392         1,
  15393         0,
  15394         0x90801b6,
  15395         0,
  15396         0,
  15397         2,
  15398         soc_L3_DEFIP_128_CAM_DBGCTRLr_fields,
  15399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15400         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15401         -1,
  15402         -1,
  15403     },
  15404 #endif /* chips */
  15405 
  15406 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15407     { /* SOC_REG_INT_L3_DEFIP_128_CAM_DBGCTRL_BCM56840_A0r */
  15408         soc_block_list[5],
  15409         soc_genreg,
  15410         1,
  15411         0,
  15412         0xa080d0c,
  15413         0,
  15414         0,
  15415         2,
  15416         soc_L3_DEFIP_128_CAM_DBGCTRL_BCM56840_A0r_fields,
  15417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15418         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15419         -1,
  15420         -1,
  15421     },
  15422 #endif /* chips */
  15423 
  15424 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  15425     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  15426     { /* SOC_REG_INT_L3_DEFIP_128_CAM_ENABLEr */
  15427         soc_block_list[5],
  15428         soc_genreg,
  15429         1,
  15430         0,
  15431         0xa080154,
  15432         0,
  15433         0,
  15434         2,
  15435         soc_L3_DEFIP_128_CAM_ENABLEr_fields,
  15436         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15437         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15438         -1,
  15439         -1,
  15440     },
  15441 #endif /* chips */
  15442 
  15443 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  15444     { /* SOC_REG_INT_L3_DEFIP_128_CAM_ENABLE_BCM56334_A0r */
  15445         soc_block_list[5],
  15446         soc_genreg,
  15447         1,
  15448         0,
  15449         0xa080179,
  15450         0,
  15451         0,
  15452         2,
  15453         soc_L3_DEFIP_128_CAM_ENABLEr_fields,
  15454         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15455         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15456         -1,
  15457         -1,
  15458     },
  15459 #endif /* chips */
  15460 
  15461 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  15462     { /* SOC_REG_INT_L3_DEFIP_128_CAM_ENABLE_BCM56440_A0r */
  15463         soc_block_list[5],
  15464         soc_genreg,
  15465         1,
  15466         0,
  15467         0xa080d0c,
  15468         0,
  15469         0,
  15470         2,
  15471         soc_L3_DEFIP_128_CAM_ENABLE_BCM56840_A0r_fields,
  15472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15473         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15474         -1,
  15475         -1,
  15476     },
  15477 #endif /* chips */
  15478 
  15479 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15480     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15481     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15482     { /* SOC_REG_INT_L3_DEFIP_128_CAM_ENABLE_BCM56634_A0r */
  15483         soc_block_list[5],
  15484         soc_genreg,
  15485         1,
  15486         0,
  15487         0x90801b7,
  15488         0,
  15489         0,
  15490         2,
  15491         soc_L3_DEFIP_128_CAM_ENABLEr_fields,
  15492         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15493         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15494         -1,
  15495         -1,
  15496     },
  15497 #endif /* chips */
  15498 
  15499 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  15500     { /* SOC_REG_INT_L3_DEFIP_128_CAM_ENABLE_BCM56820_A0r */
  15501         soc_block_list[5],
  15502         soc_genreg,
  15503         1,
  15504         0,
  15505         0x8080d09,
  15506         0,
  15507         0,
  15508         2,
  15509         soc_L3_DEFIP_128_CAM_ENABLEr_fields,
  15510         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15511         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15512         -1,
  15513         -1,
  15514     },
  15515 #endif /* chips */
  15516 
  15517 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15518     { /* SOC_REG_INT_L3_DEFIP_128_CAM_ENABLE_BCM56840_A0r */
  15519         soc_block_list[5],
  15520         soc_genreg,
  15521         1,
  15522         0,
  15523         0xa080d0d,
  15524         0,
  15525         0,
  15526         2,
  15527         soc_L3_DEFIP_128_CAM_ENABLE_BCM56840_A0r_fields,
  15528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15529         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15530         -1,
  15531         -1,
  15532     },
  15533 #endif /* chips */
  15534 
  15535 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  15536     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  15537     { /* SOC_REG_INT_L3_DEFIP_128_DATA_DBGCTRLr */
  15538         soc_block_list[5],
  15539         soc_genreg,
  15540         1,
  15541         0,
  15542         0xa080151,
  15543         0,
  15544         0,
  15545         1,
  15546         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
  15547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15548         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15549         -1,
  15550         -1,
  15551     },
  15552 #endif /* chips */
  15553 
  15554 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  15555     { /* SOC_REG_INT_L3_DEFIP_128_DATA_DBGCTRL_BCM56334_A0r */
  15556         soc_block_list[5],
  15557         soc_genreg,
  15558         1,
  15559         0,
  15560         0xa080176,
  15561         0,
  15562         0,
  15563         1,
  15564         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
  15565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15566         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15567         -1,
  15568         -1,
  15569     },
  15570 #endif /* chips */
  15571 
  15572 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  15573     { /* SOC_REG_INT_L3_DEFIP_128_DATA_DBGCTRL_BCM56440_A0r */
  15574         soc_block_list[5],
  15575         soc_genreg,
  15576         1,
  15577         0,
  15578         0xa080d0a,
  15579         0,
  15580         0,
  15581         3,
  15582         soc_L3_DEFIP_128_DATA_DBGCTRL_BCM56840_A0r_fields,
  15583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15584         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15585         -1,
  15586         -1,
  15587     },
  15588 #endif /* chips */
  15589 
  15590 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15591     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15592     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15593     { /* SOC_REG_INT_L3_DEFIP_128_DATA_DBGCTRL_BCM56634_A0r */
  15594         soc_block_list[5],
  15595         soc_genreg,
  15596         1,
  15597         0,
  15598         0x90801b4,
  15599         0,
  15600         0,
  15601         1,
  15602         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
  15603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15604         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15605         -1,
  15606         -1,
  15607     },
  15608 #endif /* chips */
  15609 
  15610 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  15611     { /* SOC_REG_INT_L3_DEFIP_128_DATA_DBGCTRL_BCM56820_A0r */
  15612         soc_block_list[5],
  15613         soc_genreg,
  15614         1,
  15615         0,
  15616         0x8080d0e,
  15617         0,
  15618         0,
  15619         2,
  15620         soc_L3_DEFIP_128_DATA_DBGCTRLr_fields,
  15621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15622         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15623         -1,
  15624         -1,
  15625     },
  15626 #endif /* chips */
  15627 
  15628 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15629     { /* SOC_REG_INT_L3_DEFIP_128_DATA_DBGCTRL_BCM56840_A0r */
  15630         soc_block_list[5],
  15631         soc_genreg,
  15632         1,
  15633         0,
  15634         0xa080d0b,
  15635         0,
  15636         0,
  15637         3,
  15638         soc_L3_DEFIP_128_DATA_DBGCTRL_BCM56840_A0r_fields,
  15639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15640         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15641         -1,
  15642         -1,
  15643     },
  15644 #endif /* chips */
  15645 
  15646 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15647     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15648     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15649     { /* SOC_REG_INT_L3_DEFIP_128_DATA_PARITY_CONTROLr */
  15650         soc_block_list[5],
  15651         soc_genreg,
  15652         1,
  15653         0,
  15654         0x90801bf,
  15655         0,
  15656         0,
  15657         1,
  15658         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  15659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15660         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  15661         -1,
  15662         -1,
  15663     },
  15664 #endif /* chips */
  15665 
  15666 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  15667     { /* SOC_REG_INT_L3_DEFIP_128_DATA_PARITY_CONTROL_BCM56440_A0r */
  15668         soc_block_list[5],
  15669         soc_genreg,
  15670         1,
  15671         0,
  15672         0xa080d14,
  15673         0,
  15674         0,
  15675         1,
  15676         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  15677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15678         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15679         -1,
  15680         -1,
  15681     },
  15682 #endif /* chips */
  15683 
  15684 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15685     { /* SOC_REG_INT_L3_DEFIP_128_DATA_PARITY_CONTROL_BCM56840_A0r */
  15686         soc_block_list[5],
  15687         soc_genreg,
  15688         1,
  15689         0,
  15690         0xa080d15,
  15691         0,
  15692         0,
  15693         1,
  15694         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  15695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15696         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15697         -1,
  15698         -1,
  15699     },
  15700 #endif /* chips */
  15701 
  15702 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15703     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15704     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15705     { /* SOC_REG_INT_L3_DEFIP_128_DATA_PARITY_STATUS_INTRr */
  15706         soc_block_list[5],
  15707         soc_genreg,
  15708         1,
  15709         0,
  15710         0x90801c0,
  15711         0,
  15712         0,
  15713         3,
  15714         soc_CPU_TS_PARITY_STATUS_INTRr_fields,
  15715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15716         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  15717         -1,
  15718         -1,
  15719     },
  15720 #endif /* chips */
  15721 
  15722 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  15723     { /* SOC_REG_INT_L3_DEFIP_128_DATA_PARITY_STATUS_INTR_BCM56440_A0r */
  15724         soc_block_list[5],
  15725         soc_genreg,
  15726         1,
  15727         0,
  15728         0xa080d15,
  15729         0,
  15730         0,
  15731         3,
  15732         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  15733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15734         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15735         -1,
  15736         -1,
  15737     },
  15738 #endif /* chips */
  15739 
  15740 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  15741     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15742     { /* SOC_REG_INT_L3_DEFIP_128_DATA_PARITY_STATUS_INTR_BCM56840_A0r */
  15743         soc_block_list[5],
  15744         soc_genreg,
  15745         1,
  15746         0,
  15747         0xa080d16,
  15748         0,
  15749         0,
  15750         3,
  15751         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  15752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15754         -1,
  15755         -1,
  15756     },
  15757 #endif /* chips */
  15758 
  15759 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15760     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15761     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15762     { /* SOC_REG_INT_L3_DEFIP_128_DATA_PARITY_STATUS_NACKr */
  15763         soc_block_list[5],
  15764         soc_genreg,
  15765         1,
  15766         0,
  15767         0x90801c1,
  15768         0,
  15769         0,
  15770         3,
  15771         soc_CPU_TS_PARITY_STATUS_INTRr_fields,
  15772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15773         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  15774         -1,
  15775         -1,
  15776     },
  15777 #endif /* chips */
  15778 
  15779 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15780     { /* SOC_REG_INT_L3_DEFIP_128_DATA_PARITY_STATUS_NACK_BCM56840_A0r */
  15781         soc_block_list[5],
  15782         soc_genreg,
  15783         1,
  15784         0,
  15785         0xa080d17,
  15786         0,
  15787         0,
  15788         3,
  15789         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  15790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15792         -1,
  15793         -1,
  15794     },
  15795 #endif /* chips */
  15796 
  15797 #if defined(BCM_56850_A0)
  15798     { /* SOC_REG_INT_L3_DEFIP_ALPM_CFGr */
  15799         soc_block_list[5],
  15800         soc_genreg,
  15801         1,
  15802         0,
  15803         0x2a000600,
  15804         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15805         0,
  15806         9,
  15807         soc_L3_DEFIP_ALPM_CFGr_fields,
  15808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15809         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15810         -1,
  15811         -1,
  15812     },
  15813 #endif /* chips */
  15814 
  15815 #if defined(BCM_56370_A0)
  15816     { /* SOC_REG_INT_L3_DEFIP_ALPM_CFG_BCM56370_A0r */
  15817         soc_block_list[5],
  15818         soc_genreg,
  15819         1,
  15820         0,
  15821         0x6b900000,
  15822         0,
  15823         0,
  15824         5,
  15825         soc_L3_DEFIP_ALPM_CFG_BCM56870_A0r_fields,
  15826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15827         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15828         -1,
  15829         -1,
  15830         3,
  15831     },
  15832 #endif /* chips */
  15833 
  15834 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  15835     { /* SOC_REG_INT_L3_DEFIP_ALPM_CFG_BCM56560_A0r */
  15836         soc_block_list[5],
  15837         soc_genreg,
  15838         1,
  15839         0,
  15840         0x3a000600,
  15841         0,
  15842         0,
  15843         9,
  15844         soc_L3_DEFIP_ALPM_CFG_BCM56960_A0r_fields,
  15845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15846         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15847         -1,
  15848         -1,
  15849     },
  15850 #endif /* chips */
  15851 
  15852 #if defined(BCM_56860_A0)
  15853     { /* SOC_REG_INT_L3_DEFIP_ALPM_CFG_BCM56860_A0r */
  15854         soc_block_list[5],
  15855         soc_genreg,
  15856         1,
  15857         0,
  15858         0x3a000600,
  15859         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15860         0,
  15861         9,
  15862         soc_L3_DEFIP_ALPM_CFGr_fields,
  15863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15864         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15865         -1,
  15866         -1,
  15867     },
  15868 #endif /* chips */
  15869 
  15870 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  15871     { /* SOC_REG_INT_L3_DEFIP_ALPM_CFG_BCM56870_A0r */
  15872         soc_block_list[5],
  15873         soc_genreg,
  15874         1,
  15875         0,
  15876         0x6b900000,
  15877         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15878         0,
  15879         5,
  15880         soc_L3_DEFIP_ALPM_CFG_BCM56870_A0r_fields,
  15881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15882         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15883         -1,
  15884         -1,
  15885         3,
  15886     },
  15887 #endif /* chips */
  15888 
  15889 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15890     { /* SOC_REG_INT_L3_DEFIP_ALPM_CFG_BCM56960_A0r */
  15891         soc_block_list[5],
  15892         soc_genreg,
  15893         1,
  15894         0,
  15895         0x3b910000,
  15896         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15897         0,
  15898         9,
  15899         soc_L3_DEFIP_ALPM_CFG_BCM56960_A0r_fields,
  15900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15901         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15902         -1,
  15903         -1,
  15904         3,
  15905     },
  15906 #endif /* chips */
  15907 
  15908 #if defined(BCM_56970_A0)
  15909     { /* SOC_REG_INT_L3_DEFIP_ALPM_CFG_BCM56970_A0r */
  15910         soc_block_list[5],
  15911         soc_genreg,
  15912         1,
  15913         0,
  15914         0x5f8f0000,
  15915         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15916         0,
  15917         9,
  15918         soc_L3_DEFIP_ALPM_CFG_BCM56960_A0r_fields,
  15919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15920         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15921         -1,
  15922         -1,
  15923         3,
  15924     },
  15925 #endif /* chips */
  15926 
  15927 #if defined(BCM_56850_A0)
  15928     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRLr */
  15929         soc_block_list[5],
  15930         soc_genreg,
  15931         1,
  15932         0,
  15933         0x2a000300,
  15934         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15935         0,
  15936         8,
  15937         soc_L3_DEFIP_AUX_CTRLr_fields,
  15938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15940         -1,
  15941         -1,
  15942     },
  15943 #endif /* chips */
  15944 
  15945 #if defined(BCM_56850_A0)
  15946     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_1r */
  15947         soc_block_list[5],
  15948         soc_genreg,
  15949         1,
  15950         0,
  15951         0x2a000400,
  15952         SOC_REG_FLAG_RO |
  15953                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15954         0,
  15955         2,
  15956         soc_L3_DEFIP_AUX_CTRL_1r_fields,
  15957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15959         -1,
  15960         -1,
  15961     },
  15962 #endif /* chips */
  15963 
  15964 #if defined(BCM_56370_A0)
  15965     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_1_BCM56370_A0r */
  15966         soc_block_list[5],
  15967         soc_genreg,
  15968         1,
  15969         0,
  15970         0x6b8f0000,
  15971         SOC_REG_FLAG_RO,
  15972         0,
  15973         4,
  15974         soc_L3_DEFIP_AUX_CTRL_1_BCM56370_A0r_fields,
  15975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15976         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15977         -1,
  15978         -1,
  15979         3,
  15980     },
  15981 #endif /* chips */
  15982 
  15983 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  15984     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_1_BCM56560_A0r */
  15985         soc_block_list[5],
  15986         soc_genreg,
  15987         1,
  15988         0,
  15989         0x3a000400,
  15990         SOC_REG_FLAG_RO,
  15991         0,
  15992         3,
  15993         soc_L3_DEFIP_AUX_CTRL_1_BCM56560_A0r_fields,
  15994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15995         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15996         -1,
  15997         -1,
  15998     },
  15999 #endif /* chips */
  16000 
  16001 #if defined(BCM_56860_A0)
  16002     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_1_BCM56860_A0r */
  16003         soc_block_list[5],
  16004         soc_genreg,
  16005         1,
  16006         0,
  16007         0x3a000400,
  16008         SOC_REG_FLAG_RO |
  16009                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16010         0,
  16011         2,
  16012         soc_L3_DEFIP_AUX_CTRL_1r_fields,
  16013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16014         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16015         -1,
  16016         -1,
  16017     },
  16018 #endif /* chips */
  16019 
  16020 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  16021     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_1_BCM56870_A0r */
  16022         soc_block_list[5],
  16023         soc_genreg,
  16024         1,
  16025         0,
  16026         0x6b8f0000,
  16027         SOC_REG_FLAG_RO |
  16028                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16029         0,
  16030         3,
  16031         soc_L3_DEFIP_AUX_CTRL_1_BCM56960_A0r_fields,
  16032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16034         -1,
  16035         -1,
  16036         3,
  16037     },
  16038 #endif /* chips */
  16039 
  16040 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  16041     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_1_BCM56960_A0r */
  16042         soc_block_list[5],
  16043         soc_genreg,
  16044         1,
  16045         0,
  16046         0x3b900000,
  16047         SOC_REG_FLAG_RO |
  16048                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16049         0,
  16050         3,
  16051         soc_L3_DEFIP_AUX_CTRL_1_BCM56960_A0r_fields,
  16052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16053         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16054         -1,
  16055         -1,
  16056         3,
  16057     },
  16058 #endif /* chips */
  16059 
  16060 #if defined(BCM_56970_A0)
  16061     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_1_BCM56970_A0r */
  16062         soc_block_list[5],
  16063         soc_genreg,
  16064         1,
  16065         0,
  16066         0x5f8e0000,
  16067         SOC_REG_FLAG_RO |
  16068                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16069         0,
  16070         3,
  16071         soc_L3_DEFIP_AUX_CTRL_1_BCM56560_A0r_fields,
  16072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16073         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16074         -1,
  16075         -1,
  16076         3,
  16077     },
  16078 #endif /* chips */
  16079 
  16080 #if defined(BCM_56370_A0)
  16081     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_BCM56370_A0r */
  16082         soc_block_list[5],
  16083         soc_genreg,
  16084         1,
  16085         0,
  16086         0x6b8e0000,
  16087         0,
  16088         0,
  16089         9,
  16090         soc_L3_DEFIP_AUX_CTRL_BCM56370_A0r_fields,
  16091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16092         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16093         -1,
  16094         -1,
  16095         3,
  16096     },
  16097 #endif /* chips */
  16098 
  16099 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  16100     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_BCM56560_A0r */
  16101         soc_block_list[5],
  16102         soc_genreg,
  16103         1,
  16104         0,
  16105         0x3a000300,
  16106         0,
  16107         0,
  16108         8,
  16109         soc_L3_DEFIP_AUX_CTRL_BCM56960_A0r_fields,
  16110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16112         -1,
  16113         -1,
  16114     },
  16115 #endif /* chips */
  16116 
  16117 #if defined(BCM_56860_A0)
  16118     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_BCM56860_A0r */
  16119         soc_block_list[5],
  16120         soc_genreg,
  16121         1,
  16122         0,
  16123         0x3a000300,
  16124         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16125         0,
  16126         8,
  16127         soc_L3_DEFIP_AUX_CTRLr_fields,
  16128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16129         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16130         -1,
  16131         -1,
  16132     },
  16133 #endif /* chips */
  16134 
  16135 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  16136     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_BCM56870_A0r */
  16137         soc_block_list[5],
  16138         soc_genreg,
  16139         1,
  16140         0,
  16141         0x6b8e0000,
  16142         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16143         0,
  16144         8,
  16145         soc_L3_DEFIP_AUX_CTRL_BCM56870_A0r_fields,
  16146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16148         -1,
  16149         -1,
  16150         3,
  16151     },
  16152 #endif /* chips */
  16153 
  16154 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  16155     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_BCM56960_A0r */
  16156         soc_block_list[5],
  16157         soc_genreg,
  16158         1,
  16159         0,
  16160         0x3b8f0000,
  16161         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16162         0,
  16163         8,
  16164         soc_L3_DEFIP_AUX_CTRL_BCM56960_A0r_fields,
  16165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16166         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16167         -1,
  16168         -1,
  16169         3,
  16170     },
  16171 #endif /* chips */
  16172 
  16173 #if defined(BCM_56970_A0)
  16174     { /* SOC_REG_INT_L3_DEFIP_AUX_CTRL_BCM56970_A0r */
  16175         soc_block_list[5],
  16176         soc_genreg,
  16177         1,
  16178         0,
  16179         0x5f8d0000,
  16180         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16181         0,
  16182         8,
  16183         soc_L3_DEFIP_AUX_CTRL_BCM56970_A0r_fields,
  16184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16186         -1,
  16187         -1,
  16188         3,
  16189     },
  16190 #endif /* chips */
  16191 
  16192 #if defined(BCM_56850_A0)
  16193     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0r */
  16194         soc_block_list[5],
  16195         soc_genreg,
  16196         1,
  16197         0,
  16198         0x2b900000,
  16199         SOC_REG_FLAG_64_BITS |
  16200                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16201         0,
  16202         8,
  16203         soc_L3_DEFIP_AUX_RAM_CTRL_0r_fields,
  16204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16206         -1,
  16207         -1,
  16208     },
  16209 #endif /* chips */
  16210 
  16211 #if defined(BCM_56850_A0)
  16212     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_1r */
  16213         soc_block_list[5],
  16214         soc_genreg,
  16215         1,
  16216         0,
  16217         0x2b910000,
  16218         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16219         0,
  16220         10,
  16221         soc_L3_DEFIP_AUX_RAM_CTRL_1r_fields,
  16222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16224         -1,
  16225         -1,
  16226     },
  16227 #endif /* chips */
  16228 
  16229 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  16230     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32r */
  16231         soc_block_list[5],
  16232         soc_genreg,
  16233         1,
  16234         0,
  16235         0x3b8c0000,
  16236         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16237         0,
  16238         2,
  16239         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16241         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16242         -1,
  16243         -1,
  16244         3,
  16245     },
  16246 #endif /* chips */
  16247 
  16248 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  16249     defined(BCM_56870_A0)
  16250     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_BCM56870_A0r */
  16251         soc_block_list[5],
  16252         soc_genreg,
  16253         1,
  16254         0,
  16255         0x6b8b0000,
  16256         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16257         0,
  16258         2,
  16259         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16261         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16262         -1,
  16263         -1,
  16264         3,
  16265     },
  16266 #endif /* chips */
  16267 
  16268 #if defined(BCM_56970_A0)
  16269     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_BCM56970_A0r */
  16270         soc_block_list[5],
  16271         soc_genreg,
  16272         1,
  16273         0,
  16274         0x5f8a0000,
  16275         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16276         0,
  16277         2,
  16278         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16280         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16281         -1,
  16282         -1,
  16283         3,
  16284     },
  16285 #endif /* chips */
  16286 
  16287 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  16288     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE0r */
  16289         soc_block_list[5],
  16290         soc_genreg,
  16291         1,
  16292         0,
  16293         0x3b8c0000,
  16294         0,
  16295         0,
  16296         2,
  16297         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16300         -1,
  16301         -1,
  16302         3,
  16303     },
  16304 #endif /* chips */
  16305 
  16306 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  16307     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE1r */
  16308         soc_block_list[5],
  16309         soc_genreg,
  16310         1,
  16311         0,
  16312         0x3b8c0000,
  16313         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16314         0,
  16315         2,
  16316         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16319         -1,
  16320         -1,
  16321         3,
  16322     },
  16323 #endif /* chips */
  16324 
  16325 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  16326     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE2r */
  16327         soc_block_list[5],
  16328         soc_genreg,
  16329         1,
  16330         0,
  16331         0x3b8c0000,
  16332         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16333         0,
  16334         2,
  16335         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16337         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16338         -1,
  16339         -1,
  16340         3,
  16341     },
  16342 #endif /* chips */
  16343 
  16344 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  16345     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE3r */
  16346         soc_block_list[5],
  16347         soc_genreg,
  16348         1,
  16349         0,
  16350         0x3b8c0000,
  16351         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16352         0,
  16353         2,
  16354         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16357         -1,
  16358         -1,
  16359         3,
  16360     },
  16361 #endif /* chips */
  16362 
  16363 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  16364     defined(BCM_56870_A0)
  16365     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE0_BCM56870_A0r */
  16366         soc_block_list[5],
  16367         soc_genreg,
  16368         1,
  16369         0,
  16370         0x6b8b0000,
  16371         0,
  16372         0,
  16373         2,
  16374         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16376         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16377         -1,
  16378         -1,
  16379         3,
  16380     },
  16381 #endif /* chips */
  16382 
  16383 #if defined(BCM_56970_A0)
  16384     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE0_BCM56970_A0r */
  16385         soc_block_list[5],
  16386         soc_genreg,
  16387         1,
  16388         0,
  16389         0x5f8a0000,
  16390         0,
  16391         0,
  16392         2,
  16393         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16395         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16396         -1,
  16397         -1,
  16398         3,
  16399     },
  16400 #endif /* chips */
  16401 
  16402 #if defined(BCM_56870_A0)
  16403     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE1_BCM56870_A0r */
  16404         soc_block_list[5],
  16405         soc_genreg,
  16406         1,
  16407         0,
  16408         0x6b8b0000,
  16409         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16410         0,
  16411         2,
  16412         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16414         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16415         -1,
  16416         -1,
  16417         3,
  16418     },
  16419 #endif /* chips */
  16420 
  16421 #if defined(BCM_56970_A0)
  16422     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE1_BCM56970_A0r */
  16423         soc_block_list[5],
  16424         soc_genreg,
  16425         1,
  16426         0,
  16427         0x5f8a0000,
  16428         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16429         0,
  16430         2,
  16431         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16433         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16434         -1,
  16435         -1,
  16436         3,
  16437     },
  16438 #endif /* chips */
  16439 
  16440 #if defined(BCM_56970_A0)
  16441     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE2_BCM56970_A0r */
  16442         soc_block_list[5],
  16443         soc_genreg,
  16444         1,
  16445         0,
  16446         0x5f8a0000,
  16447         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16448         0,
  16449         2,
  16450         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16452         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16453         -1,
  16454         -1,
  16455         3,
  16456     },
  16457 #endif /* chips */
  16458 
  16459 #if defined(BCM_56970_A0)
  16460     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE3_BCM56970_A0r */
  16461         soc_block_list[5],
  16462         soc_genreg,
  16463         1,
  16464         0,
  16465         0x5f8a0000,
  16466         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16467         0,
  16468         2,
  16469         soc_L3_DEFIP_AUX_RAM_CTRL_0_32r_fields,
  16470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16472         -1,
  16473         -1,
  16474         3,
  16475     },
  16476 #endif /* chips */
  16477 
  16478 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  16479     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_BCM56560_A0r */
  16480         soc_block_list[5],
  16481         soc_genreg,
  16482         1,
  16483         0,
  16484         0x3b8e0000,
  16485         0,
  16486         0,
  16487         1,
  16488         soc_L3_DEFIP_AUX_RAM_CTRL_0_BCM56560_A0r_fields,
  16489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16490         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16491         -1,
  16492         -1,
  16493     },
  16494 #endif /* chips */
  16495 
  16496 #if defined(BCM_56860_A0)
  16497     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_0_BCM56860_A0r */
  16498         soc_block_list[5],
  16499         soc_genreg,
  16500         1,
  16501         0,
  16502         0x3b8e0000,
  16503         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16504         0,
  16505         1,
  16506         soc_L3_DEFIP_AUX_RAM_CTRL_0_BCM56860_A0r_fields,
  16507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16508         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16509         -1,
  16510         -1,
  16511     },
  16512 #endif /* chips */
  16513 
  16514 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  16515     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_1_BCM56560_A0r */
  16516         soc_block_list[5],
  16517         soc_genreg,
  16518         1,
  16519         0,
  16520         0x3b8f0000,
  16521         0,
  16522         0,
  16523         10,
  16524         soc_L3_DEFIP_AUX_RAM_CTRL_1_BCM56560_A0r_fields,
  16525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16526         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16527         -1,
  16528         -1,
  16529     },
  16530 #endif /* chips */
  16531 
  16532 #if defined(BCM_56860_A0)
  16533     { /* SOC_REG_INT_L3_DEFIP_AUX_RAM_CTRL_1_BCM56860_A0r */
  16534         soc_block_list[5],
  16535         soc_genreg,
  16536         1,
  16537         0,
  16538         0x3b8f0000,
  16539         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16540         0,
  16541         10,
  16542         soc_L3_DEFIP_AUX_RAM_CTRL_1r_fields,
  16543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16544         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16545         -1,
  16546         -1,
  16547     },
  16548 #endif /* chips */
  16549 
  16550 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  16551     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  16552     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIGr */
  16553         soc_block_list[5],
  16554         soc_genreg,
  16555         1,
  16556         0,
  16557         0xa080148,
  16558         0,
  16559         0,
  16560         4,
  16561         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  16562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16564         -1,
  16565         -1,
  16566     },
  16567 #endif /* chips */
  16568 
  16569 #if defined(BCM_56970_A0)
  16570     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64r */
  16571         soc_block_list[5],
  16572         soc_genreg,
  16573         1,
  16574         0,
  16575         0x5f860000,
  16576         SOC_REG_FLAG_64_BITS |
  16577                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16578         0,
  16579         5,
  16580         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  16581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16582         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16583         -1,
  16584         -1,
  16585         0,
  16586     },
  16587 #endif /* chips */
  16588 
  16589 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16590     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_BCM56980_A0r */
  16591         soc_block_list[5],
  16592         soc_genreg,
  16593         1,
  16594         0,
  16595         0xe011600,
  16596         SOC_REG_FLAG_64_BITS |
  16597                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16598         0,
  16599         6,
  16600         soc_L3_DEFIP_CAM_BIST_CONFIG_64r_fields,
  16601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16602         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16603         -1,
  16604         -1,
  16605         3,
  16606     },
  16607 #endif /* chips */
  16608 
  16609 #if defined(BCM_56970_A0)
  16610     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r */
  16611         soc_block_list[5],
  16612         soc_genreg,
  16613         1,
  16614         0,
  16615         0x5f860000,
  16616         SOC_REG_FLAG_64_BITS,
  16617         0,
  16618         5,
  16619         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  16620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16622         -1,
  16623         -1,
  16624         0,
  16625     },
  16626 #endif /* chips */
  16627 
  16628 #if defined(BCM_56970_A0)
  16629     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r */
  16630         soc_block_list[5],
  16631         soc_genreg,
  16632         1,
  16633         0,
  16634         0x5f860000,
  16635         SOC_REG_FLAG_64_BITS |
  16636                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16637         0,
  16638         5,
  16639         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  16640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16641         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16642         -1,
  16643         -1,
  16644         0,
  16645     },
  16646 #endif /* chips */
  16647 
  16648 #if defined(BCM_56970_A0)
  16649     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r */
  16650         soc_block_list[5],
  16651         soc_genreg,
  16652         1,
  16653         0,
  16654         0x5f860000,
  16655         SOC_REG_FLAG_64_BITS |
  16656                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16657         0,
  16658         5,
  16659         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  16660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16661         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16662         -1,
  16663         -1,
  16664         0,
  16665     },
  16666 #endif /* chips */
  16667 
  16668 #if defined(BCM_56970_A0)
  16669     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r */
  16670         soc_block_list[5],
  16671         soc_genreg,
  16672         1,
  16673         0,
  16674         0x5f860000,
  16675         SOC_REG_FLAG_64_BITS |
  16676                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16677         0,
  16678         5,
  16679         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  16680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16682         -1,
  16683         -1,
  16684         0,
  16685     },
  16686 #endif /* chips */
  16687 
  16688 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16689     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE4r */
  16690         soc_block_list[5],
  16691         soc_genreg,
  16692         1,
  16693         0,
  16694         0xe011600,
  16695         SOC_REG_FLAG_64_BITS |
  16696                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16697         0,
  16698         6,
  16699         soc_L3_DEFIP_CAM_BIST_CONFIG_64r_fields,
  16700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16701         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16702         -1,
  16703         -1,
  16704         3,
  16705     },
  16706 #endif /* chips */
  16707 
  16708 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16709     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE5r */
  16710         soc_block_list[5],
  16711         soc_genreg,
  16712         1,
  16713         0,
  16714         0xe011600,
  16715         SOC_REG_FLAG_64_BITS |
  16716                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16717         0,
  16718         6,
  16719         soc_L3_DEFIP_CAM_BIST_CONFIG_64r_fields,
  16720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16722         -1,
  16723         -1,
  16724         3,
  16725     },
  16726 #endif /* chips */
  16727 
  16728 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16729     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE6r */
  16730         soc_block_list[5],
  16731         soc_genreg,
  16732         1,
  16733         0,
  16734         0xe011600,
  16735         SOC_REG_FLAG_64_BITS |
  16736                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16737         0,
  16738         6,
  16739         soc_L3_DEFIP_CAM_BIST_CONFIG_64r_fields,
  16740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16742         -1,
  16743         -1,
  16744         3,
  16745     },
  16746 #endif /* chips */
  16747 
  16748 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16749     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE7r */
  16750         soc_block_list[5],
  16751         soc_genreg,
  16752         1,
  16753         0,
  16754         0xe011600,
  16755         SOC_REG_FLAG_64_BITS |
  16756                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16757         0,
  16758         6,
  16759         soc_L3_DEFIP_CAM_BIST_CONFIG_64r_fields,
  16760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16762         -1,
  16763         -1,
  16764         3,
  16765     },
  16766 #endif /* chips */
  16767 
  16768 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16769     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0_BCM56980_A0r */
  16770         soc_block_list[5],
  16771         soc_genreg,
  16772         1,
  16773         0,
  16774         0xe011600,
  16775         SOC_REG_FLAG_64_BITS,
  16776         0,
  16777         6,
  16778         soc_L3_DEFIP_CAM_BIST_CONFIG_64r_fields,
  16779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16781         -1,
  16782         -1,
  16783         3,
  16784     },
  16785 #endif /* chips */
  16786 
  16787 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16788     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1_BCM56980_A0r */
  16789         soc_block_list[5],
  16790         soc_genreg,
  16791         1,
  16792         0,
  16793         0xe011600,
  16794         SOC_REG_FLAG_64_BITS |
  16795                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16796         0,
  16797         6,
  16798         soc_L3_DEFIP_CAM_BIST_CONFIG_64r_fields,
  16799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16801         -1,
  16802         -1,
  16803         3,
  16804     },
  16805 #endif /* chips */
  16806 
  16807 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16808     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2_BCM56980_A0r */
  16809         soc_block_list[5],
  16810         soc_genreg,
  16811         1,
  16812         0,
  16813         0xe011600,
  16814         SOC_REG_FLAG_64_BITS |
  16815                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16816         0,
  16817         6,
  16818         soc_L3_DEFIP_CAM_BIST_CONFIG_64r_fields,
  16819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16820         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16821         -1,
  16822         -1,
  16823         3,
  16824     },
  16825 #endif /* chips */
  16826 
  16827 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16828     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3_BCM56980_A0r */
  16829         soc_block_list[5],
  16830         soc_genreg,
  16831         1,
  16832         0,
  16833         0xe011600,
  16834         SOC_REG_FLAG_64_BITS |
  16835                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16836         0,
  16837         6,
  16838         soc_L3_DEFIP_CAM_BIST_CONFIG_64r_fields,
  16839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16840         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16841         -1,
  16842         -1,
  16843         3,
  16844     },
  16845 #endif /* chips */
  16846 
  16847 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16848     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16849     defined(BCM_56160_A0)
  16850     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM53400_A0r */
  16851         soc_block_list[5],
  16852         soc_genreg,
  16853         1,
  16854         0,
  16855         0x26010700,
  16856         0,
  16857         0,
  16858         4,
  16859         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  16860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16861         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16862         -1,
  16863         -1,
  16864     },
  16865 #endif /* chips */
  16866 
  16867 #if defined(BCM_56150_A0)
  16868     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56150_A0r */
  16869         soc_block_list[5],
  16870         soc_genreg,
  16871         1,
  16872         0,
  16873         0x2a010700,
  16874         0,
  16875         0,
  16876         4,
  16877         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  16878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16879         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16880         -1,
  16881         -1,
  16882     },
  16883 #endif /* chips */
  16884 
  16885 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  16886     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56224_A0r */
  16887         soc_block_list[5],
  16888         soc_genreg,
  16889         1,
  16890         0,
  16891         0x8080002,
  16892         0,
  16893         0,
  16894         5,
  16895         soc_L3_DEFIP_CAM_BIST_CONFIGr_fields,
  16896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16898         -1,
  16899         -1,
  16900     },
  16901 #endif /* chips */
  16902 
  16903 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  16904     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56260_A0r */
  16905         soc_block_list[5],
  16906         soc_genreg,
  16907         1,
  16908         0,
  16909         0x2a010a00,
  16910         0,
  16911         0,
  16912         4,
  16913         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  16914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16916         -1,
  16917         -1,
  16918     },
  16919 #endif /* chips */
  16920 
  16921 #if defined(BCM_56270_A0)
  16922     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56270_A0r */
  16923         soc_block_list[5],
  16924         soc_genreg,
  16925         1,
  16926         0,
  16927         0x2a010400,
  16928         0,
  16929         0,
  16930         4,
  16931         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  16932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16934         -1,
  16935         -1,
  16936     },
  16937 #endif /* chips */
  16938 
  16939 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  16940     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56334_A0r */
  16941         soc_block_list[5],
  16942         soc_genreg,
  16943         1,
  16944         0,
  16945         0xa08016d,
  16946         0,
  16947         0,
  16948         4,
  16949         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  16950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16952         -1,
  16953         -1,
  16954     },
  16955 #endif /* chips */
  16956 
  16957 #if defined(BCM_56340_A0)
  16958     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56340_A0r */
  16959         soc_block_list[5],
  16960         soc_genreg,
  16961         1,
  16962         0,
  16963         0x22011b00,
  16964         0,
  16965         0,
  16966         4,
  16967         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  16968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16970         -1,
  16971         -1,
  16972     },
  16973 #endif /* chips */
  16974 
  16975 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  16976     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56440_A0r */
  16977         soc_block_list[5],
  16978         soc_genreg,
  16979         1,
  16980         0,
  16981         0xa080d05,
  16982         0,
  16983         0,
  16984         4,
  16985         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  16986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16987         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16988         -1,
  16989         -1,
  16990     },
  16991 #endif /* chips */
  16992 
  16993 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16994     defined(BCM_56450_B1)
  16995     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56450_A0r */
  16996         soc_block_list[5],
  16997         soc_genreg,
  16998         1,
  16999         0,
  17000         0x2a010a00,
  17001         0,
  17002         0,
  17003         4,
  17004         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  17005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17006         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17007         -1,
  17008         -1,
  17009     },
  17010 #endif /* chips */
  17011 
  17012 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  17013     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56560_A0r */
  17014         soc_block_list[5],
  17015         soc_genreg,
  17016         1,
  17017         0,
  17018         0x3b880000,
  17019         0,
  17020         0,
  17021         4,
  17022         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  17023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17024         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17025         -1,
  17026         -1,
  17027     },
  17028 #endif /* chips */
  17029 
  17030 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  17031     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  17032     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  17033     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56634_A0r */
  17034         soc_block_list[5],
  17035         soc_genreg,
  17036         1,
  17037         0,
  17038         0x90801a9,
  17039         0,
  17040         0,
  17041         4,
  17042         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  17043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17044         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17045         -1,
  17046         -1,
  17047     },
  17048 #endif /* chips */
  17049 
  17050 #if defined(BCM_56640_A0)
  17051     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56640_A0r */
  17052         soc_block_list[5],
  17053         soc_genreg,
  17054         1,
  17055         0,
  17056         0x22010800,
  17057         0,
  17058         0,
  17059         4,
  17060         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  17061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17062         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17063         -1,
  17064         -1,
  17065     },
  17066 #endif /* chips */
  17067 
  17068 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17069     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56670_A0r */
  17070         soc_block_list[5],
  17071         soc_genreg,
  17072         1,
  17073         0,
  17074         0x3b870000,
  17075         0,
  17076         0,
  17077         4,
  17078         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  17079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17080         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17081         -1,
  17082         -1,
  17083     },
  17084 #endif /* chips */
  17085 
  17086 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  17087     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56820_A0r */
  17088         soc_block_list[5],
  17089         soc_genreg,
  17090         1,
  17091         0,
  17092         0x8080c03,
  17093         0,
  17094         0,
  17095         4,
  17096         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  17097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17098         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17099         -1,
  17100         -1,
  17101     },
  17102 #endif /* chips */
  17103 
  17104 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  17105     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56840_A0r */
  17106         soc_block_list[5],
  17107         soc_genreg,
  17108         1,
  17109         0,
  17110         0xa080d06,
  17111         0,
  17112         0,
  17113         4,
  17114         soc_L2_USER_ENTRY_CAM_BIST_CONFIGr_fields,
  17115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17116         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17117         -1,
  17118         -1,
  17119     },
  17120 #endif /* chips */
  17121 
  17122 #if defined(BCM_56850_A0)
  17123     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56850_A0r */
  17124         soc_block_list[5],
  17125         soc_genreg,
  17126         1,
  17127         0,
  17128         0x2b880000,
  17129         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17130         0,
  17131         4,
  17132         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  17133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17134         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17135         -1,
  17136         -1,
  17137     },
  17138 #endif /* chips */
  17139 
  17140 #if defined(BCM_56860_A0)
  17141     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56860_A0r */
  17142         soc_block_list[5],
  17143         soc_genreg,
  17144         1,
  17145         0,
  17146         0x3b880000,
  17147         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17148         0,
  17149         4,
  17150         soc_ESM_PKT_TYPE_ID_CAM_BIST_CONFIGr_fields,
  17151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17152         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17153         -1,
  17154         -1,
  17155     },
  17156 #endif /* chips */
  17157 
  17158 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17159     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_BCM56960_A0r */
  17160         soc_block_list[5],
  17161         soc_genreg,
  17162         1,
  17163         0,
  17164         0x3b870000,
  17165         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17166         0,
  17167         4,
  17168         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  17169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17170         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17171         -1,
  17172         -1,
  17173         3,
  17174     },
  17175 #endif /* chips */
  17176 
  17177 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17178     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_PIPE0r */
  17179         soc_block_list[5],
  17180         soc_genreg,
  17181         1,
  17182         0,
  17183         0x3b870000,
  17184         0,
  17185         0,
  17186         4,
  17187         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  17188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17189         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17190         -1,
  17191         -1,
  17192         3,
  17193     },
  17194 #endif /* chips */
  17195 
  17196 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17197     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_PIPE1r */
  17198         soc_block_list[5],
  17199         soc_genreg,
  17200         1,
  17201         0,
  17202         0x3b870000,
  17203         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17204         0,
  17205         4,
  17206         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  17207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17208         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17209         -1,
  17210         -1,
  17211         3,
  17212     },
  17213 #endif /* chips */
  17214 
  17215 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17216     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_PIPE2r */
  17217         soc_block_list[5],
  17218         soc_genreg,
  17219         1,
  17220         0,
  17221         0x3b870000,
  17222         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17223         0,
  17224         4,
  17225         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  17226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17227         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17228         -1,
  17229         -1,
  17230         3,
  17231     },
  17232 #endif /* chips */
  17233 
  17234 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17235     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONFIG_PIPE3r */
  17236         soc_block_list[5],
  17237         soc_genreg,
  17238         1,
  17239         0,
  17240         0x3b870000,
  17241         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17242         0,
  17243         4,
  17244         soc_L2_USER_ENTRY_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  17245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17246         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17247         -1,
  17248         -1,
  17249         3,
  17250     },
  17251 #endif /* chips */
  17252 
  17253 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  17254     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONTROLr */
  17255         soc_block_list[5],
  17256         soc_genreg,
  17257         1,
  17258         0,
  17259         0x8080000,
  17260         0,
  17261         0,
  17262         8,
  17263         soc_L3_DEFIP_CAM_BIST_CONTROLr_fields,
  17264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17265         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17266         -1,
  17267         -1,
  17268     },
  17269 #endif /* chips */
  17270 
  17271 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  17272     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_CONTROL_BCM56820_A0r */
  17273         soc_block_list[5],
  17274         soc_genreg,
  17275         1,
  17276         0,
  17277         0x8080c01,
  17278         0,
  17279         0,
  17280         13,
  17281         soc_L3_DEFIP_CAM_BIST_CONTROL_BCM56820_A0r_fields,
  17282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17284         -1,
  17285         -1,
  17286     },
  17287 #endif /* chips */
  17288 
  17289 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  17290     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  17291     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRLr */
  17292         soc_block_list[5],
  17293         soc_genreg,
  17294         1,
  17295         0,
  17296         0xa080146,
  17297         0,
  17298         0,
  17299         17,
  17300         soc_L3_DEFIP_CAM_BIST_DBGCTRLr_fields,
  17301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17303         -1,
  17304         -1,
  17305     },
  17306 #endif /* chips */
  17307 
  17308 #if defined(BCM_56340_A0)
  17309     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_0r */
  17310         soc_block_list[5],
  17311         soc_genreg,
  17312         1,
  17313         0,
  17314         0x22011800,
  17315         0,
  17316         0,
  17317         1,
  17318         soc_L3_DEFIP_CAM_BIST_DBGCTRL_0r_fields,
  17319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17321         -1,
  17322         -1,
  17323     },
  17324 #endif /* chips */
  17325 
  17326 #if defined(BCM_56340_A0)
  17327     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_1r */
  17328         soc_block_list[5],
  17329         soc_genreg,
  17330         1,
  17331         0,
  17332         0x22011900,
  17333         0,
  17334         0,
  17335         32,
  17336         soc_L3_DEFIP_CAM_BIST_DBGCTRL_1r_fields,
  17337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17339         -1,
  17340         -1,
  17341     },
  17342 #endif /* chips */
  17343 
  17344 #if defined(BCM_53400_A0)
  17345     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM53400_A0r */
  17346         soc_block_list[5],
  17347         soc_genreg,
  17348         1,
  17349         0,
  17350         0x26010500,
  17351         0,
  17352         0,
  17353         2,
  17354         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  17355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17357         -1,
  17358         -1,
  17359     },
  17360 #endif /* chips */
  17361 
  17362 #if defined(BCM_53570_B0)
  17363     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM53570_B0r */
  17364         soc_block_list[5],
  17365         soc_genreg,
  17366         1,
  17367         0,
  17368         0x26010500,
  17369         SOC_REG_FLAG_64_BITS,
  17370         0,
  17371         64,
  17372         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM53570_B0r_fields,
  17373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17375         -1,
  17376         -1,
  17377     },
  17378 #endif /* chips */
  17379 
  17380 #if defined(BCM_56150_A0)
  17381     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56150_A0r */
  17382         soc_block_list[5],
  17383         soc_genreg,
  17384         1,
  17385         0,
  17386         0x2a010500,
  17387         0,
  17388         0,
  17389         2,
  17390         soc_CPU_COS_CAM_DBGCTRL_BCM56640_A0r_fields,
  17391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17393         -1,
  17394         -1,
  17395     },
  17396 #endif /* chips */
  17397 
  17398 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  17399     defined(BCM_56160_A0)
  17400     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56160_A0r */
  17401         soc_block_list[5],
  17402         soc_genreg,
  17403         1,
  17404         0,
  17405         0x26010500,
  17406         0,
  17407         0,
  17408         4,
  17409         soc_ING_SNAT_CAM_BIST_CONTROL_BCM56960_A0r_fields,
  17410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17411         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17412         -1,
  17413         -1,
  17414     },
  17415 #endif /* chips */
  17416 
  17417 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  17418     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56260_A0r */
  17419         soc_block_list[5],
  17420         soc_genreg,
  17421         1,
  17422         0,
  17423         0x2a010800,
  17424         0,
  17425         0,
  17426         7,
  17427         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56260_A0r_fields,
  17428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17429         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17430         -1,
  17431         -1,
  17432     },
  17433 #endif /* chips */
  17434 
  17435 #if defined(BCM_56270_A0)
  17436     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56270_A0r */
  17437         soc_block_list[5],
  17438         soc_genreg,
  17439         1,
  17440         0,
  17441         0x2a010200,
  17442         0,
  17443         0,
  17444         5,
  17445         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56270_A0r_fields,
  17446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17448         -1,
  17449         -1,
  17450     },
  17451 #endif /* chips */
  17452 
  17453 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  17454     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56334_A0r */
  17455         soc_block_list[5],
  17456         soc_genreg,
  17457         1,
  17458         0,
  17459         0xa08016b,
  17460         0,
  17461         0,
  17462         13,
  17463         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56334_A0r_fields,
  17464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17465         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17466         -1,
  17467         -1,
  17468     },
  17469 #endif /* chips */
  17470 
  17471 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  17472     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56440_A0r */
  17473         soc_block_list[5],
  17474         soc_genreg,
  17475         1,
  17476         0,
  17477         0xa080d03,
  17478         0,
  17479         0,
  17480         7,
  17481         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56440_A0r_fields,
  17482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17484         -1,
  17485         -1,
  17486     },
  17487 #endif /* chips */
  17488 
  17489 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17490     defined(BCM_56450_B1)
  17491     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56450_A0r */
  17492         soc_block_list[5],
  17493         soc_genreg,
  17494         1,
  17495         0,
  17496         0x2a010800,
  17497         0,
  17498         0,
  17499         17,
  17500         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56450_A0r_fields,
  17501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17502         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17503         -1,
  17504         -1,
  17505     },
  17506 #endif /* chips */
  17507 
  17508 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  17509     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56560_A0r */
  17510         soc_block_list[5],
  17511         soc_genreg,
  17512         1,
  17513         0,
  17514         0x3b860000,
  17515         0,
  17516         0,
  17517         9,
  17518         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56960_A0r_fields,
  17519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17520         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17521         -1,
  17522         -1,
  17523     },
  17524 #endif /* chips */
  17525 
  17526 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  17527     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  17528     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  17529     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56634_A0r */
  17530         soc_block_list[5],
  17531         soc_genreg,
  17532         1,
  17533         0,
  17534         0x90801a7,
  17535         0,
  17536         0,
  17537         17,
  17538         soc_L3_DEFIP_CAM_BIST_DBGCTRLr_fields,
  17539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17540         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17541         -1,
  17542         -1,
  17543     },
  17544 #endif /* chips */
  17545 
  17546 #if defined(BCM_56640_A0)
  17547     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56640_A0r */
  17548         soc_block_list[5],
  17549         soc_genreg,
  17550         1,
  17551         0,
  17552         0x22010600,
  17553         0,
  17554         0,
  17555         9,
  17556         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56640_A0r_fields,
  17557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17559         -1,
  17560         -1,
  17561     },
  17562 #endif /* chips */
  17563 
  17564 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17565     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56670_A0r */
  17566         soc_block_list[5],
  17567         soc_genreg,
  17568         1,
  17569         0,
  17570         0x3b850000,
  17571         0,
  17572         0,
  17573         9,
  17574         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56960_A0r_fields,
  17575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17577         -1,
  17578         -1,
  17579     },
  17580 #endif /* chips */
  17581 
  17582 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  17583     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56840_A0r */
  17584         soc_block_list[5],
  17585         soc_genreg,
  17586         1,
  17587         0,
  17588         0xa080d04,
  17589         0,
  17590         0,
  17591         17,
  17592         soc_L3_DEFIP_CAM_BIST_DBGCTRLr_fields,
  17593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17594         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17595         -1,
  17596         -1,
  17597     },
  17598 #endif /* chips */
  17599 
  17600 #if defined(BCM_56850_A0)
  17601     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56850_A0r */
  17602         soc_block_list[5],
  17603         soc_genreg,
  17604         1,
  17605         0,
  17606         0x2b860000,
  17607         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17608         0,
  17609         9,
  17610         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56640_A0r_fields,
  17611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17613         -1,
  17614         -1,
  17615     },
  17616 #endif /* chips */
  17617 
  17618 #if defined(BCM_56860_A0)
  17619     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56860_A0r */
  17620         soc_block_list[5],
  17621         soc_genreg,
  17622         1,
  17623         0,
  17624         0x3b860000,
  17625         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17626         0,
  17627         9,
  17628         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56640_A0r_fields,
  17629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17631         -1,
  17632         -1,
  17633     },
  17634 #endif /* chips */
  17635 
  17636 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17637     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56960_A0r */
  17638         soc_block_list[5],
  17639         soc_genreg,
  17640         1,
  17641         0,
  17642         0x3b850000,
  17643         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17644         0,
  17645         9,
  17646         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56960_A0r_fields,
  17647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17649         -1,
  17650         -1,
  17651         3,
  17652     },
  17653 #endif /* chips */
  17654 
  17655 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17656     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_PIPE0r */
  17657         soc_block_list[5],
  17658         soc_genreg,
  17659         1,
  17660         0,
  17661         0x3b850000,
  17662         0,
  17663         0,
  17664         9,
  17665         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56960_A0r_fields,
  17666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17667         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17668         -1,
  17669         -1,
  17670         3,
  17671     },
  17672 #endif /* chips */
  17673 
  17674 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17675     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_PIPE1r */
  17676         soc_block_list[5],
  17677         soc_genreg,
  17678         1,
  17679         0,
  17680         0x3b850000,
  17681         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17682         0,
  17683         9,
  17684         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56960_A0r_fields,
  17685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17686         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17687         -1,
  17688         -1,
  17689         3,
  17690     },
  17691 #endif /* chips */
  17692 
  17693 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17694     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_PIPE2r */
  17695         soc_block_list[5],
  17696         soc_genreg,
  17697         1,
  17698         0,
  17699         0x3b850000,
  17700         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17701         0,
  17702         9,
  17703         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56960_A0r_fields,
  17704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17706         -1,
  17707         -1,
  17708         3,
  17709     },
  17710 #endif /* chips */
  17711 
  17712 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17713     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBGCTRL_PIPE3r */
  17714         soc_block_list[5],
  17715         soc_genreg,
  17716         1,
  17717         0,
  17718         0x3b850000,
  17719         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17720         0,
  17721         9,
  17722         soc_L3_DEFIP_CAM_BIST_DBGCTRL_BCM56960_A0r_fields,
  17723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17724         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17725         -1,
  17726         -1,
  17727         3,
  17728     },
  17729 #endif /* chips */
  17730 
  17731 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  17732     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  17733     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATAr */
  17734         soc_block_list[5],
  17735         soc_genreg,
  17736         1,
  17737         0,
  17738         0xa080149,
  17739         0,
  17740         0,
  17741         1,
  17742         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  17743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17744         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17745         -1,
  17746         -1,
  17747     },
  17748 #endif /* chips */
  17749 
  17750 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17751     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17752     defined(BCM_56160_A0)
  17753     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM53400_A0r */
  17754         soc_block_list[5],
  17755         soc_genreg,
  17756         1,
  17757         0,
  17758         0x26010800,
  17759         0,
  17760         0,
  17761         1,
  17762         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  17763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17764         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17765         -1,
  17766         -1,
  17767     },
  17768 #endif /* chips */
  17769 
  17770 #if defined(BCM_56150_A0)
  17771     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56150_A0r */
  17772         soc_block_list[5],
  17773         soc_genreg,
  17774         1,
  17775         0,
  17776         0x2a010800,
  17777         0,
  17778         0,
  17779         1,
  17780         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  17781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17782         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17783         -1,
  17784         -1,
  17785     },
  17786 #endif /* chips */
  17787 
  17788 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  17789     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56224_A0r */
  17790         soc_block_list[5],
  17791         soc_genreg,
  17792         1,
  17793         0,
  17794         0x8080003,
  17795         0,
  17796         0,
  17797         1,
  17798         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  17799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17801         -1,
  17802         -1,
  17803     },
  17804 #endif /* chips */
  17805 
  17806 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  17807     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56260_A0r */
  17808         soc_block_list[5],
  17809         soc_genreg,
  17810         1,
  17811         0,
  17812         0x2a010b00,
  17813         0,
  17814         0,
  17815         1,
  17816         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  17817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17819         -1,
  17820         -1,
  17821     },
  17822 #endif /* chips */
  17823 
  17824 #if defined(BCM_56270_A0)
  17825     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56270_A0r */
  17826         soc_block_list[5],
  17827         soc_genreg,
  17828         1,
  17829         0,
  17830         0x2a010500,
  17831         0,
  17832         0,
  17833         1,
  17834         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  17835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17836         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17837         -1,
  17838         -1,
  17839     },
  17840 #endif /* chips */
  17841 
  17842 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  17843     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56334_A0r */
  17844         soc_block_list[5],
  17845         soc_genreg,
  17846         1,
  17847         0,
  17848         0xa08016e,
  17849         0,
  17850         0,
  17851         1,
  17852         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  17853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17855         -1,
  17856         -1,
  17857     },
  17858 #endif /* chips */
  17859 
  17860 #if defined(BCM_56340_A0)
  17861     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56340_A0r */
  17862         soc_block_list[5],
  17863         soc_genreg,
  17864         1,
  17865         0,
  17866         0x22011c00,
  17867         0,
  17868         0,
  17869         1,
  17870         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  17871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17873         -1,
  17874         -1,
  17875     },
  17876 #endif /* chips */
  17877 
  17878 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  17879     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56440_A0r */
  17880         soc_block_list[5],
  17881         soc_genreg,
  17882         1,
  17883         0,
  17884         0xa080d06,
  17885         0,
  17886         0,
  17887         1,
  17888         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  17889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17890         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17891         -1,
  17892         -1,
  17893     },
  17894 #endif /* chips */
  17895 
  17896 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17897     defined(BCM_56450_B1)
  17898     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56450_A0r */
  17899         soc_block_list[5],
  17900         soc_genreg,
  17901         1,
  17902         0,
  17903         0x2a010b00,
  17904         0,
  17905         0,
  17906         1,
  17907         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  17908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17909         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17910         -1,
  17911         -1,
  17912     },
  17913 #endif /* chips */
  17914 
  17915 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  17916     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56560_A0r */
  17917         soc_block_list[5],
  17918         soc_genreg,
  17919         1,
  17920         0,
  17921         0x3b890000,
  17922         0,
  17923         0,
  17924         1,
  17925         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  17926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17927         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17928         -1,
  17929         -1,
  17930     },
  17931 #endif /* chips */
  17932 
  17933 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  17934     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  17935     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  17936     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56634_A0r */
  17937         soc_block_list[5],
  17938         soc_genreg,
  17939         1,
  17940         0,
  17941         0x90801aa,
  17942         0,
  17943         0,
  17944         1,
  17945         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  17946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17947         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17948         -1,
  17949         -1,
  17950     },
  17951 #endif /* chips */
  17952 
  17953 #if defined(BCM_56640_A0)
  17954     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56640_A0r */
  17955         soc_block_list[5],
  17956         soc_genreg,
  17957         1,
  17958         0,
  17959         0x22010900,
  17960         0,
  17961         0,
  17962         1,
  17963         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  17964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17965         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17966         -1,
  17967         -1,
  17968     },
  17969 #endif /* chips */
  17970 
  17971 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17972     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56670_A0r */
  17973         soc_block_list[5],
  17974         soc_genreg,
  17975         1,
  17976         0,
  17977         0x3b880000,
  17978         0,
  17979         0,
  17980         1,
  17981         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  17982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17983         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17984         -1,
  17985         -1,
  17986     },
  17987 #endif /* chips */
  17988 
  17989 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  17990     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56820_A0r */
  17991         soc_block_list[5],
  17992         soc_genreg,
  17993         1,
  17994         0,
  17995         0x8080c04,
  17996         0,
  17997         0,
  17998         1,
  17999         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  18000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18001         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18002         -1,
  18003         -1,
  18004     },
  18005 #endif /* chips */
  18006 
  18007 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  18008     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56840_A0r */
  18009         soc_block_list[5],
  18010         soc_genreg,
  18011         1,
  18012         0,
  18013         0xa080d07,
  18014         0,
  18015         0,
  18016         1,
  18017         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  18018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18019         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18020         -1,
  18021         -1,
  18022     },
  18023 #endif /* chips */
  18024 
  18025 #if defined(BCM_56850_A0)
  18026     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56850_A0r */
  18027         soc_block_list[5],
  18028         soc_genreg,
  18029         1,
  18030         0,
  18031         0x2b890000,
  18032         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18033         0,
  18034         1,
  18035         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  18036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18037         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18038         -1,
  18039         -1,
  18040     },
  18041 #endif /* chips */
  18042 
  18043 #if defined(BCM_56860_A0)
  18044     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56860_A0r */
  18045         soc_block_list[5],
  18046         soc_genreg,
  18047         1,
  18048         0,
  18049         0x3b890000,
  18050         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18051         0,
  18052         1,
  18053         soc_ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATAr_fields,
  18054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18055         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18056         -1,
  18057         -1,
  18058     },
  18059 #endif /* chips */
  18060 
  18061 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18062     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56960_A0r */
  18063         soc_block_list[5],
  18064         soc_genreg,
  18065         1,
  18066         0,
  18067         0x3b880000,
  18068         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18069         0,
  18070         1,
  18071         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18073         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18074         -1,
  18075         -1,
  18076         3,
  18077     },
  18078 #endif /* chips */
  18079 
  18080 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  18081     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_BCM56980_A0r */
  18082         soc_block_list[5],
  18083         soc_genreg,
  18084         1,
  18085         0,
  18086         0xe011700,
  18087         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18088         0,
  18089         1,
  18090         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18092         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18093         -1,
  18094         -1,
  18095         3,
  18096     },
  18097 #endif /* chips */
  18098 
  18099 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18100     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE0r */
  18101         soc_block_list[5],
  18102         soc_genreg,
  18103         1,
  18104         0,
  18105         0x3b880000,
  18106         0,
  18107         0,
  18108         1,
  18109         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18112         -1,
  18113         -1,
  18114         3,
  18115     },
  18116 #endif /* chips */
  18117 
  18118 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18119     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE1r */
  18120         soc_block_list[5],
  18121         soc_genreg,
  18122         1,
  18123         0,
  18124         0x3b880000,
  18125         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18126         0,
  18127         1,
  18128         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18130         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18131         -1,
  18132         -1,
  18133         3,
  18134     },
  18135 #endif /* chips */
  18136 
  18137 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18138     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE2r */
  18139         soc_block_list[5],
  18140         soc_genreg,
  18141         1,
  18142         0,
  18143         0x3b880000,
  18144         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18145         0,
  18146         1,
  18147         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18150         -1,
  18151         -1,
  18152         3,
  18153     },
  18154 #endif /* chips */
  18155 
  18156 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18157     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE3r */
  18158         soc_block_list[5],
  18159         soc_genreg,
  18160         1,
  18161         0,
  18162         0x3b880000,
  18163         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18164         0,
  18165         1,
  18166         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18169         -1,
  18170         -1,
  18171         3,
  18172     },
  18173 #endif /* chips */
  18174 
  18175 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  18176     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE4r */
  18177         soc_block_list[5],
  18178         soc_genreg,
  18179         1,
  18180         0,
  18181         0xe011700,
  18182         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18183         0,
  18184         1,
  18185         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18188         -1,
  18189         -1,
  18190         3,
  18191     },
  18192 #endif /* chips */
  18193 
  18194 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  18195     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE5r */
  18196         soc_block_list[5],
  18197         soc_genreg,
  18198         1,
  18199         0,
  18200         0xe011700,
  18201         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18202         0,
  18203         1,
  18204         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18206         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18207         -1,
  18208         -1,
  18209         3,
  18210     },
  18211 #endif /* chips */
  18212 
  18213 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  18214     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE6r */
  18215         soc_block_list[5],
  18216         soc_genreg,
  18217         1,
  18218         0,
  18219         0xe011700,
  18220         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18221         0,
  18222         1,
  18223         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18225         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18226         -1,
  18227         -1,
  18228         3,
  18229     },
  18230 #endif /* chips */
  18231 
  18232 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  18233     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE7r */
  18234         soc_block_list[5],
  18235         soc_genreg,
  18236         1,
  18237         0,
  18238         0xe011700,
  18239         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18240         0,
  18241         1,
  18242         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18244         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18245         -1,
  18246         -1,
  18247         3,
  18248     },
  18249 #endif /* chips */
  18250 
  18251 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  18252     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE0_BCM56980_A0r */
  18253         soc_block_list[5],
  18254         soc_genreg,
  18255         1,
  18256         0,
  18257         0xe011700,
  18258         0,
  18259         0,
  18260         1,
  18261         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18264         -1,
  18265         -1,
  18266         3,
  18267     },
  18268 #endif /* chips */
  18269 
  18270 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  18271     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE1_BCM56980_A0r */
  18272         soc_block_list[5],
  18273         soc_genreg,
  18274         1,
  18275         0,
  18276         0xe011700,
  18277         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18278         0,
  18279         1,
  18280         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18282         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18283         -1,
  18284         -1,
  18285         3,
  18286     },
  18287 #endif /* chips */
  18288 
  18289 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  18290     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE2_BCM56980_A0r */
  18291         soc_block_list[5],
  18292         soc_genreg,
  18293         1,
  18294         0,
  18295         0xe011700,
  18296         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18297         0,
  18298         1,
  18299         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18302         -1,
  18303         -1,
  18304         3,
  18305     },
  18306 #endif /* chips */
  18307 
  18308 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  18309     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_DBG_DATA_PIPE3_BCM56980_A0r */
  18310         soc_block_list[5],
  18311         soc_genreg,
  18312         1,
  18313         0,
  18314         0xe011700,
  18315         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18316         0,
  18317         1,
  18318         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  18319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18321         -1,
  18322         -1,
  18323         3,
  18324     },
  18325 #endif /* chips */
  18326 
  18327 #if defined(BCM_56504_A0)
  18328     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S10_STATUSr */
  18329         soc_block_list[5],
  18330         soc_genreg,
  18331         1,
  18332         0,
  18333         0x8080008,
  18334         SOC_REG_FLAG_RO,
  18335         0,
  18336         2,
  18337         soc_L3_DEFIP_CAM_BIST_S10_STATUSr_fields,
  18338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18339         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18340         -1,
  18341         -1,
  18342     },
  18343 #endif /* chips */
  18344 
  18345 #if defined(BCM_56314_A0)
  18346     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S10_STATUS_BCM56314_A0r */
  18347         soc_block_list[5],
  18348         soc_genreg,
  18349         1,
  18350         0,
  18351         0x8080008,
  18352         SOC_REG_FLAG_RO,
  18353         0,
  18354         1,
  18355         soc_L3_DEFIP_CAM_BIST_S10_STATUS_BCM56314_A0r_fields,
  18356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18358         -1,
  18359         -1,
  18360     },
  18361 #endif /* chips */
  18362 
  18363 #if defined(BCM_56504_B0) || defined(BCM_56514_A0)
  18364     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S10_STATUS_BCM56504_B0r */
  18365         soc_block_list[5],
  18366         soc_genreg,
  18367         1,
  18368         0,
  18369         0x8080008,
  18370         SOC_REG_FLAG_RO,
  18371         0,
  18372         1,
  18373         soc_L3_DEFIP_CAM_BIST_S10_STATUS_BCM56504_B0r_fields,
  18374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18375         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18376         -1,
  18377         -1,
  18378     },
  18379 #endif /* chips */
  18380 
  18381 #if defined(BCM_56800_A0)
  18382     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S10_STATUS_BCM56800_A0r */
  18383         soc_block_list[5],
  18384         soc_genreg,
  18385         1,
  18386         0,
  18387         0x8080c08,
  18388         SOC_REG_FLAG_RO,
  18389         0,
  18390         2,
  18391         soc_EGR_VXLT_CAM_BIST_S8_STATUSr_fields,
  18392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18393         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18394         -1,
  18395         -1,
  18396     },
  18397 #endif /* chips */
  18398 
  18399 #if defined(BCM_56514_A0)
  18400     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S12_STATUSr */
  18401         soc_block_list[5],
  18402         soc_genreg,
  18403         1,
  18404         0,
  18405         0x8080009,
  18406         SOC_REG_FLAG_RO,
  18407         0,
  18408         1,
  18409         soc_L3_DEFIP_CAM_BIST_S12_STATUSr_fields,
  18410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18411         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18412         -1,
  18413         -1,
  18414     },
  18415 #endif /* chips */
  18416 
  18417 #if defined(BCM_56504_A0)
  18418     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S2_STATUSr */
  18419         soc_block_list[5],
  18420         soc_genreg,
  18421         1,
  18422         0,
  18423         0x8080003,
  18424         SOC_REG_FLAG_RO,
  18425         0,
  18426         3,
  18427         soc_L3_DEFIP_CAM_BIST_S2_STATUSr_fields,
  18428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18429         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18430         -1,
  18431         -1,
  18432     },
  18433 #endif /* chips */
  18434 
  18435 #if defined(BCM_56314_A0)
  18436     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S2_STATUS_BCM56314_A0r */
  18437         soc_block_list[5],
  18438         soc_genreg,
  18439         1,
  18440         0,
  18441         0x8080003,
  18442         SOC_REG_FLAG_RO,
  18443         0,
  18444         1,
  18445         soc_L3_DEFIP_CAM_BIST_S2_STATUS_BCM56314_A0r_fields,
  18446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18448         -1,
  18449         -1,
  18450     },
  18451 #endif /* chips */
  18452 
  18453 #if defined(BCM_56504_B0) || defined(BCM_56514_A0)
  18454     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S2_STATUS_BCM56504_B0r */
  18455         soc_block_list[5],
  18456         soc_genreg,
  18457         1,
  18458         0,
  18459         0x8080003,
  18460         SOC_REG_FLAG_RO,
  18461         0,
  18462         1,
  18463         soc_L3_DEFIP_CAM_BIST_S2_STATUS_BCM56504_B0r_fields,
  18464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18465         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18466         -1,
  18467         -1,
  18468     },
  18469 #endif /* chips */
  18470 
  18471 #if defined(BCM_56800_A0)
  18472     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S2_STATUS_BCM56800_A0r */
  18473         soc_block_list[5],
  18474         soc_genreg,
  18475         1,
  18476         0,
  18477         0x8080c03,
  18478         SOC_REG_FLAG_RO,
  18479         0,
  18480         3,
  18481         soc_L3_DEFIP_CAM_BIST_S2_STATUS_BCM56800_A0r_fields,
  18482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18484         -1,
  18485         -1,
  18486     },
  18487 #endif /* chips */
  18488 
  18489 #if defined(BCM_56504_A0)
  18490     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S3_STATUSr */
  18491         soc_block_list[5],
  18492         soc_genreg,
  18493         1,
  18494         0,
  18495         0x8080004,
  18496         SOC_REG_FLAG_RO,
  18497         0,
  18498         4,
  18499         soc_L3_DEFIP_CAM_BIST_S3_STATUSr_fields,
  18500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18502         -1,
  18503         -1,
  18504     },
  18505 #endif /* chips */
  18506 
  18507 #if defined(BCM_56314_A0)
  18508     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S3_STATUS_BCM56314_A0r */
  18509         soc_block_list[5],
  18510         soc_genreg,
  18511         1,
  18512         0,
  18513         0x8080004,
  18514         SOC_REG_FLAG_RO,
  18515         0,
  18516         1,
  18517         soc_L3_DEFIP_CAM_BIST_S3_STATUS_BCM56314_A0r_fields,
  18518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18519         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18520         -1,
  18521         -1,
  18522     },
  18523 #endif /* chips */
  18524 
  18525 #if defined(BCM_56504_B0) || defined(BCM_56514_A0)
  18526     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S3_STATUS_BCM56504_B0r */
  18527         soc_block_list[5],
  18528         soc_genreg,
  18529         1,
  18530         0,
  18531         0x8080004,
  18532         SOC_REG_FLAG_RO,
  18533         0,
  18534         1,
  18535         soc_L3_DEFIP_CAM_BIST_S3_STATUS_BCM56504_B0r_fields,
  18536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18538         -1,
  18539         -1,
  18540     },
  18541 #endif /* chips */
  18542 
  18543 #if defined(BCM_56800_A0)
  18544     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S3_STATUS_BCM56800_A0r */
  18545         soc_block_list[5],
  18546         soc_genreg,
  18547         1,
  18548         0,
  18549         0x8080c04,
  18550         SOC_REG_FLAG_RO,
  18551         0,
  18552         4,
  18553         soc_EGR_VXLT_CAM_BIST_S3_STATUSr_fields,
  18554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18556         -1,
  18557         -1,
  18558     },
  18559 #endif /* chips */
  18560 
  18561 #if defined(BCM_56504_A0)
  18562     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S5_STATUSr */
  18563         soc_block_list[5],
  18564         soc_genreg,
  18565         1,
  18566         0,
  18567         0x8080005,
  18568         SOC_REG_FLAG_RO,
  18569         0,
  18570         3,
  18571         soc_L3_DEFIP_CAM_BIST_S2_STATUSr_fields,
  18572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18574         -1,
  18575         -1,
  18576     },
  18577 #endif /* chips */
  18578 
  18579 #if defined(BCM_56314_A0)
  18580     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S5_STATUS_BCM56314_A0r */
  18581         soc_block_list[5],
  18582         soc_genreg,
  18583         1,
  18584         0,
  18585         0x8080005,
  18586         SOC_REG_FLAG_RO,
  18587         0,
  18588         1,
  18589         soc_L3_DEFIP_CAM_BIST_S5_STATUS_BCM56314_A0r_fields,
  18590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18592         -1,
  18593         -1,
  18594     },
  18595 #endif /* chips */
  18596 
  18597 #if defined(BCM_56504_B0) || defined(BCM_56514_A0)
  18598     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S5_STATUS_BCM56504_B0r */
  18599         soc_block_list[5],
  18600         soc_genreg,
  18601         1,
  18602         0,
  18603         0x8080005,
  18604         SOC_REG_FLAG_RO,
  18605         0,
  18606         1,
  18607         soc_L3_DEFIP_CAM_BIST_S5_STATUSr_fields,
  18608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18609         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18610         -1,
  18611         -1,
  18612     },
  18613 #endif /* chips */
  18614 
  18615 #if defined(BCM_56800_A0)
  18616     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S5_STATUS_BCM56800_A0r */
  18617         soc_block_list[5],
  18618         soc_genreg,
  18619         1,
  18620         0,
  18621         0x8080c05,
  18622         SOC_REG_FLAG_RO,
  18623         0,
  18624         3,
  18625         soc_L3_DEFIP_CAM_BIST_S2_STATUS_BCM56800_A0r_fields,
  18626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18628         -1,
  18629         -1,
  18630     },
  18631 #endif /* chips */
  18632 
  18633 #if defined(BCM_56504_A0)
  18634     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S6_STATUSr */
  18635         soc_block_list[5],
  18636         soc_genreg,
  18637         1,
  18638         0,
  18639         0x8080006,
  18640         SOC_REG_FLAG_RO,
  18641         0,
  18642         4,
  18643         soc_L3_DEFIP_CAM_BIST_S3_STATUSr_fields,
  18644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18646         -1,
  18647         -1,
  18648     },
  18649 #endif /* chips */
  18650 
  18651 #if defined(BCM_56314_A0)
  18652     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S6_STATUS_BCM56314_A0r */
  18653         soc_block_list[5],
  18654         soc_genreg,
  18655         1,
  18656         0,
  18657         0x8080006,
  18658         SOC_REG_FLAG_RO,
  18659         0,
  18660         1,
  18661         soc_L3_DEFIP_CAM_BIST_S6_STATUS_BCM56314_A0r_fields,
  18662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18663         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18664         -1,
  18665         -1,
  18666     },
  18667 #endif /* chips */
  18668 
  18669 #if defined(BCM_56504_B0) || defined(BCM_56514_A0)
  18670     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S6_STATUS_BCM56504_B0r */
  18671         soc_block_list[5],
  18672         soc_genreg,
  18673         1,
  18674         0,
  18675         0x8080006,
  18676         SOC_REG_FLAG_RO,
  18677         0,
  18678         1,
  18679         soc_L3_DEFIP_CAM_BIST_S6_STATUSr_fields,
  18680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18682         -1,
  18683         -1,
  18684     },
  18685 #endif /* chips */
  18686 
  18687 #if defined(BCM_56800_A0)
  18688     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S6_STATUS_BCM56800_A0r */
  18689         soc_block_list[5],
  18690         soc_genreg,
  18691         1,
  18692         0,
  18693         0x8080c06,
  18694         SOC_REG_FLAG_RO,
  18695         0,
  18696         4,
  18697         soc_EGR_VXLT_CAM_BIST_S3_STATUSr_fields,
  18698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18700         -1,
  18701         -1,
  18702     },
  18703 #endif /* chips */
  18704 
  18705 #if defined(BCM_56504_A0)
  18706     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S8_STATUSr */
  18707         soc_block_list[5],
  18708         soc_genreg,
  18709         1,
  18710         0,
  18711         0x8080007,
  18712         SOC_REG_FLAG_RO,
  18713         0,
  18714         4,
  18715         soc_L3_DEFIP_CAM_BIST_S3_STATUSr_fields,
  18716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18718         -1,
  18719         -1,
  18720     },
  18721 #endif /* chips */
  18722 
  18723 #if defined(BCM_56314_A0)
  18724     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S8_STATUS_BCM56314_A0r */
  18725         soc_block_list[5],
  18726         soc_genreg,
  18727         1,
  18728         0,
  18729         0x8080007,
  18730         SOC_REG_FLAG_RO,
  18731         0,
  18732         1,
  18733         soc_L3_DEFIP_CAM_BIST_S8_STATUS_BCM56314_A0r_fields,
  18734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18736         -1,
  18737         -1,
  18738     },
  18739 #endif /* chips */
  18740 
  18741 #if defined(BCM_56504_B0) || defined(BCM_56514_A0)
  18742     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S8_STATUS_BCM56504_B0r */
  18743         soc_block_list[5],
  18744         soc_genreg,
  18745         1,
  18746         0,
  18747         0x8080007,
  18748         SOC_REG_FLAG_RO,
  18749         0,
  18750         1,
  18751         soc_L3_DEFIP_CAM_BIST_S8_STATUSr_fields,
  18752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18754         -1,
  18755         -1,
  18756     },
  18757 #endif /* chips */
  18758 
  18759 #if defined(BCM_56800_A0)
  18760     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_S8_STATUS_BCM56800_A0r */
  18761         soc_block_list[5],
  18762         soc_genreg,
  18763         1,
  18764         0,
  18765         0x8080c07,
  18766         SOC_REG_FLAG_RO,
  18767         0,
  18768         4,
  18769         soc_EGR_VXLT_CAM_BIST_S3_STATUSr_fields,
  18770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18772         -1,
  18773         -1,
  18774     },
  18775 #endif /* chips */
  18776 
  18777 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  18778     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  18779     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUSr */
  18780         soc_block_list[5],
  18781         soc_genreg,
  18782         1,
  18783         0,
  18784         0x8080002,
  18785         0,
  18786         0,
  18787         2,
  18788         soc_L2_USER_ENTRY_CAM_BIST_STATUSr_fields,
  18789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18791         -1,
  18792         -1,
  18793     },
  18794 #endif /* chips */
  18795 
  18796 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18797     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18798     defined(BCM_56160_A0)
  18799     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM53400_A0r */
  18800         soc_block_list[5],
  18801         soc_genreg,
  18802         1,
  18803         0,
  18804         0x26010600,
  18805         SOC_REG_FLAG_RO,
  18806         0,
  18807         1,
  18808         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  18809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18810         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18811         -1,
  18812         -1,
  18813     },
  18814 #endif /* chips */
  18815 
  18816 #if defined(BCM_56150_A0)
  18817     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56150_A0r */
  18818         soc_block_list[5],
  18819         soc_genreg,
  18820         1,
  18821         0,
  18822         0x2a010600,
  18823         SOC_REG_FLAG_RO,
  18824         0,
  18825         1,
  18826         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  18827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18828         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18829         -1,
  18830         -1,
  18831     },
  18832 #endif /* chips */
  18833 
  18834 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  18835     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56224_A0r */
  18836         soc_block_list[5],
  18837         soc_genreg,
  18838         1,
  18839         0,
  18840         0x8080001,
  18841         SOC_REG_FLAG_RO,
  18842         0,
  18843         1,
  18844         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  18845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18846         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18847         -1,
  18848         -1,
  18849     },
  18850 #endif /* chips */
  18851 
  18852 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  18853     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56260_A0r */
  18854         soc_block_list[5],
  18855         soc_genreg,
  18856         1,
  18857         0,
  18858         0x2a010900,
  18859         SOC_REG_FLAG_RO,
  18860         0,
  18861         1,
  18862         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  18863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18864         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18865         -1,
  18866         -1,
  18867     },
  18868 #endif /* chips */
  18869 
  18870 #if defined(BCM_56270_A0)
  18871     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56270_A0r */
  18872         soc_block_list[5],
  18873         soc_genreg,
  18874         1,
  18875         0,
  18876         0x2a010300,
  18877         SOC_REG_FLAG_RO,
  18878         0,
  18879         1,
  18880         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  18881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18882         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18883         -1,
  18884         -1,
  18885     },
  18886 #endif /* chips */
  18887 
  18888 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  18889     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56334_A0r */
  18890         soc_block_list[5],
  18891         soc_genreg,
  18892         1,
  18893         0,
  18894         0xa08016c,
  18895         SOC_REG_FLAG_RO,
  18896         0,
  18897         1,
  18898         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  18899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18901         -1,
  18902         -1,
  18903     },
  18904 #endif /* chips */
  18905 
  18906 #if defined(BCM_56340_A0)
  18907     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56340_A0r */
  18908         soc_block_list[5],
  18909         soc_genreg,
  18910         1,
  18911         0,
  18912         0x22011a00,
  18913         SOC_REG_FLAG_RO,
  18914         0,
  18915         1,
  18916         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  18917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18919         -1,
  18920         -1,
  18921     },
  18922 #endif /* chips */
  18923 
  18924 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  18925     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56440_A0r */
  18926         soc_block_list[5],
  18927         soc_genreg,
  18928         1,
  18929         0,
  18930         0xa080d04,
  18931         SOC_REG_FLAG_RO,
  18932         0,
  18933         1,
  18934         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  18935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18936         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18937         -1,
  18938         -1,
  18939     },
  18940 #endif /* chips */
  18941 
  18942 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18943     defined(BCM_56450_B1)
  18944     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56450_A0r */
  18945         soc_block_list[5],
  18946         soc_genreg,
  18947         1,
  18948         0,
  18949         0x2a010900,
  18950         SOC_REG_FLAG_RO,
  18951         0,
  18952         1,
  18953         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  18954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18956         -1,
  18957         -1,
  18958     },
  18959 #endif /* chips */
  18960 
  18961 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  18962     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56560_A0r */
  18963         soc_block_list[5],
  18964         soc_genreg,
  18965         1,
  18966         0,
  18967         0x3b870000,
  18968         SOC_REG_FLAG_RO,
  18969         0,
  18970         1,
  18971         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  18972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18973         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18974         -1,
  18975         -1,
  18976     },
  18977 #endif /* chips */
  18978 
  18979 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  18980     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  18981     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56624_A0r */
  18982         soc_block_list[5],
  18983         soc_genreg,
  18984         1,
  18985         0,
  18986         0xa080147,
  18987         SOC_REG_FLAG_RO,
  18988         0,
  18989         1,
  18990         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  18991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18992         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18993         -1,
  18994         -1,
  18995     },
  18996 #endif /* chips */
  18997 
  18998 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  18999     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  19000     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  19001     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56634_A0r */
  19002         soc_block_list[5],
  19003         soc_genreg,
  19004         1,
  19005         0,
  19006         0x90801a8,
  19007         SOC_REG_FLAG_RO,
  19008         0,
  19009         1,
  19010         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  19011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19012         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19013         -1,
  19014         -1,
  19015     },
  19016 #endif /* chips */
  19017 
  19018 #if defined(BCM_56640_A0)
  19019     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56640_A0r */
  19020         soc_block_list[5],
  19021         soc_genreg,
  19022         1,
  19023         0,
  19024         0x22010700,
  19025         SOC_REG_FLAG_RO,
  19026         0,
  19027         1,
  19028         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  19029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19030         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19031         -1,
  19032         -1,
  19033     },
  19034 #endif /* chips */
  19035 
  19036 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  19037     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56670_A0r */
  19038         soc_block_list[5],
  19039         soc_genreg,
  19040         1,
  19041         0,
  19042         0x3b860000,
  19043         SOC_REG_FLAG_RO,
  19044         0,
  19045         1,
  19046         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19048         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19049         -1,
  19050         -1,
  19051     },
  19052 #endif /* chips */
  19053 
  19054 #if defined(BCM_56800_A0)
  19055     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56800_A0r */
  19056         soc_block_list[5],
  19057         soc_genreg,
  19058         1,
  19059         0,
  19060         0x8080c02,
  19061         0,
  19062         0,
  19063         2,
  19064         soc_L2_USER_ENTRY_CAM_BIST_STATUSr_fields,
  19065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19066         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19067         -1,
  19068         -1,
  19069     },
  19070 #endif /* chips */
  19071 
  19072 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  19073     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56820_A0r */
  19074         soc_block_list[5],
  19075         soc_genreg,
  19076         1,
  19077         0,
  19078         0x8080c02,
  19079         SOC_REG_FLAG_RO,
  19080         0,
  19081         1,
  19082         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  19083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19084         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19085         -1,
  19086         -1,
  19087     },
  19088 #endif /* chips */
  19089 
  19090 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19091     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56840_A0r */
  19092         soc_block_list[5],
  19093         soc_genreg,
  19094         1,
  19095         0,
  19096         0xa080d05,
  19097         SOC_REG_FLAG_RO,
  19098         0,
  19099         1,
  19100         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  19101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19102         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19103         -1,
  19104         -1,
  19105     },
  19106 #endif /* chips */
  19107 
  19108 #if defined(BCM_56850_A0)
  19109     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56850_A0r */
  19110         soc_block_list[5],
  19111         soc_genreg,
  19112         1,
  19113         0,
  19114         0x2b870000,
  19115         SOC_REG_FLAG_RO |
  19116                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19117         0,
  19118         1,
  19119         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  19120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19121         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19122         -1,
  19123         -1,
  19124     },
  19125 #endif /* chips */
  19126 
  19127 #if defined(BCM_56860_A0)
  19128     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56860_A0r */
  19129         soc_block_list[5],
  19130         soc_genreg,
  19131         1,
  19132         0,
  19133         0x3b870000,
  19134         SOC_REG_FLAG_RO |
  19135                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19136         0,
  19137         1,
  19138         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  19139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19141         -1,
  19142         -1,
  19143     },
  19144 #endif /* chips */
  19145 
  19146 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19147     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56960_A0r */
  19148         soc_block_list[5],
  19149         soc_genreg,
  19150         1,
  19151         0,
  19152         0x3b860000,
  19153         SOC_REG_FLAG_RO |
  19154                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19155         0,
  19156         1,
  19157         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19160         -1,
  19161         -1,
  19162         3,
  19163     },
  19164 #endif /* chips */
  19165 
  19166 #if defined(BCM_56970_A0)
  19167     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56970_A0r */
  19168         soc_block_list[5],
  19169         soc_genreg,
  19170         1,
  19171         0,
  19172         0x5f850000,
  19173         SOC_REG_FLAG_RO |
  19174                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19175         0,
  19176         1,
  19177         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19179         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19180         -1,
  19181         -1,
  19182         3,
  19183     },
  19184 #endif /* chips */
  19185 
  19186 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  19187     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_BCM56980_A0r */
  19188         soc_block_list[5],
  19189         soc_genreg,
  19190         1,
  19191         0,
  19192         0xe011800,
  19193         SOC_REG_FLAG_RO |
  19194                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19195         0,
  19196         1,
  19197         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19200         -1,
  19201         -1,
  19202         3,
  19203     },
  19204 #endif /* chips */
  19205 
  19206 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19207     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE0r */
  19208         soc_block_list[5],
  19209         soc_genreg,
  19210         1,
  19211         0,
  19212         0x3b860000,
  19213         SOC_REG_FLAG_RO,
  19214         0,
  19215         1,
  19216         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19218         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19219         -1,
  19220         -1,
  19221         3,
  19222     },
  19223 #endif /* chips */
  19224 
  19225 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19226     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE1r */
  19227         soc_block_list[5],
  19228         soc_genreg,
  19229         1,
  19230         0,
  19231         0x3b860000,
  19232         SOC_REG_FLAG_RO |
  19233                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19234         0,
  19235         1,
  19236         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19238         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19239         -1,
  19240         -1,
  19241         3,
  19242     },
  19243 #endif /* chips */
  19244 
  19245 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19246     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE2r */
  19247         soc_block_list[5],
  19248         soc_genreg,
  19249         1,
  19250         0,
  19251         0x3b860000,
  19252         SOC_REG_FLAG_RO |
  19253                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19254         0,
  19255         1,
  19256         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19258         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19259         -1,
  19260         -1,
  19261         3,
  19262     },
  19263 #endif /* chips */
  19264 
  19265 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19266     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE3r */
  19267         soc_block_list[5],
  19268         soc_genreg,
  19269         1,
  19270         0,
  19271         0x3b860000,
  19272         SOC_REG_FLAG_RO |
  19273                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19274         0,
  19275         1,
  19276         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19278         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19279         -1,
  19280         -1,
  19281         3,
  19282     },
  19283 #endif /* chips */
  19284 
  19285 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  19286     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE4r */
  19287         soc_block_list[5],
  19288         soc_genreg,
  19289         1,
  19290         0,
  19291         0xe011800,
  19292         SOC_REG_FLAG_RO |
  19293                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19294         0,
  19295         1,
  19296         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19298         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19299         -1,
  19300         -1,
  19301         3,
  19302     },
  19303 #endif /* chips */
  19304 
  19305 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  19306     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE5r */
  19307         soc_block_list[5],
  19308         soc_genreg,
  19309         1,
  19310         0,
  19311         0xe011800,
  19312         SOC_REG_FLAG_RO |
  19313                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19314         0,
  19315         1,
  19316         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19319         -1,
  19320         -1,
  19321         3,
  19322     },
  19323 #endif /* chips */
  19324 
  19325 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  19326     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE6r */
  19327         soc_block_list[5],
  19328         soc_genreg,
  19329         1,
  19330         0,
  19331         0xe011800,
  19332         SOC_REG_FLAG_RO |
  19333                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19334         0,
  19335         1,
  19336         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19339         -1,
  19340         -1,
  19341         3,
  19342     },
  19343 #endif /* chips */
  19344 
  19345 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  19346     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE7r */
  19347         soc_block_list[5],
  19348         soc_genreg,
  19349         1,
  19350         0,
  19351         0xe011800,
  19352         SOC_REG_FLAG_RO |
  19353                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19354         0,
  19355         1,
  19356         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19358         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19359         -1,
  19360         -1,
  19361         3,
  19362     },
  19363 #endif /* chips */
  19364 
  19365 #if defined(BCM_56970_A0)
  19366     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE0_BCM56970_A0r */
  19367         soc_block_list[5],
  19368         soc_genreg,
  19369         1,
  19370         0,
  19371         0x5f850000,
  19372         SOC_REG_FLAG_RO,
  19373         0,
  19374         1,
  19375         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19378         -1,
  19379         -1,
  19380         3,
  19381     },
  19382 #endif /* chips */
  19383 
  19384 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  19385     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE0_BCM56980_A0r */
  19386         soc_block_list[5],
  19387         soc_genreg,
  19388         1,
  19389         0,
  19390         0xe011800,
  19391         SOC_REG_FLAG_RO,
  19392         0,
  19393         1,
  19394         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19397         -1,
  19398         -1,
  19399         3,
  19400     },
  19401 #endif /* chips */
  19402 
  19403 #if defined(BCM_56970_A0)
  19404     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE1_BCM56970_A0r */
  19405         soc_block_list[5],
  19406         soc_genreg,
  19407         1,
  19408         0,
  19409         0x5f850000,
  19410         SOC_REG_FLAG_RO |
  19411                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19412         0,
  19413         1,
  19414         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19416         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19417         -1,
  19418         -1,
  19419         3,
  19420     },
  19421 #endif /* chips */
  19422 
  19423 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  19424     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE1_BCM56980_A0r */
  19425         soc_block_list[5],
  19426         soc_genreg,
  19427         1,
  19428         0,
  19429         0xe011800,
  19430         SOC_REG_FLAG_RO |
  19431                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19432         0,
  19433         1,
  19434         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19436         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19437         -1,
  19438         -1,
  19439         3,
  19440     },
  19441 #endif /* chips */
  19442 
  19443 #if defined(BCM_56970_A0)
  19444     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE2_BCM56970_A0r */
  19445         soc_block_list[5],
  19446         soc_genreg,
  19447         1,
  19448         0,
  19449         0x5f850000,
  19450         SOC_REG_FLAG_RO |
  19451                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19452         0,
  19453         1,
  19454         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19456         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19457         -1,
  19458         -1,
  19459         3,
  19460     },
  19461 #endif /* chips */
  19462 
  19463 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  19464     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE2_BCM56980_A0r */
  19465         soc_block_list[5],
  19466         soc_genreg,
  19467         1,
  19468         0,
  19469         0xe011800,
  19470         SOC_REG_FLAG_RO |
  19471                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19472         0,
  19473         1,
  19474         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19476         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19477         -1,
  19478         -1,
  19479         3,
  19480     },
  19481 #endif /* chips */
  19482 
  19483 #if defined(BCM_56970_A0)
  19484     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE3_BCM56970_A0r */
  19485         soc_block_list[5],
  19486         soc_genreg,
  19487         1,
  19488         0,
  19489         0x5f850000,
  19490         SOC_REG_FLAG_RO |
  19491                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19492         0,
  19493         1,
  19494         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19496         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19497         -1,
  19498         -1,
  19499         3,
  19500     },
  19501 #endif /* chips */
  19502 
  19503 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  19504     { /* SOC_REG_INT_L3_DEFIP_CAM_BIST_STATUS_PIPE3_BCM56980_A0r */
  19505         soc_block_list[5],
  19506         soc_genreg,
  19507         1,
  19508         0,
  19509         0xe011800,
  19510         SOC_REG_FLAG_RO |
  19511                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19512         0,
  19513         1,
  19514         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19516         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19517         -1,
  19518         -1,
  19519         3,
  19520     },
  19521 #endif /* chips */
  19522 
  19523 #if defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
  19524     defined(BCM_56514_A0)
  19525     { /* SOC_REG_INT_L3_DEFIP_CAM_CONTROL0r */
  19526         soc_block_list[5],
  19527         soc_genreg,
  19528         1,
  19529         0,
  19530         0x8080000,
  19531         0,
  19532         0,
  19533         6,
  19534         soc_L3_DEFIP_CAM_CONTROL0r_fields,
  19535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19536         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19537         -1,
  19538         -1,
  19539     },
  19540 #endif /* chips */
  19541 
  19542 #if defined(BCM_56504_A0)
  19543     { /* SOC_REG_INT_L3_DEFIP_CAM_CONTROL1r */
  19544         soc_block_list[5],
  19545         soc_genreg,
  19546         1,
  19547         0,
  19548         0x8080001,
  19549         0,
  19550         0,
  19551         7,
  19552         soc_L3_DEFIP_CAM_CONTROL1r_fields,
  19553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19554         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19555         -1,
  19556         -1,
  19557     },
  19558 #endif /* chips */
  19559 
  19560 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  19561     { /* SOC_REG_INT_L3_DEFIP_CAM_CONTROL2r */
  19562         soc_block_list[5],
  19563         soc_genreg,
  19564         1,
  19565         0,
  19566         0x2a010200,
  19567         0,
  19568         0,
  19569         2,
  19570         soc_L3_DEFIP_CAM_CONTROL2r_fields,
  19571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19572         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19573         -1,
  19574         -1,
  19575     },
  19576 #endif /* chips */
  19577 
  19578 #if defined(BCM_56314_A0)
  19579     { /* SOC_REG_INT_L3_DEFIP_CAM_CONTROL0_BCM56314_A0r */
  19580         soc_block_list[5],
  19581         soc_genreg,
  19582         1,
  19583         0,
  19584         0x8080000,
  19585         0,
  19586         0,
  19587         1,
  19588         soc_L3_DEFIP_CAM_CONTROL0_BCM56314_A0r_fields,
  19589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19590         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19591         -1,
  19592         -1,
  19593     },
  19594 #endif /* chips */
  19595 
  19596 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  19597     { /* SOC_REG_INT_L3_DEFIP_CAM_CONTROL1_BCM56260_A0r */
  19598         soc_block_list[5],
  19599         soc_genreg,
  19600         1,
  19601         0,
  19602         0x2a010100,
  19603         0,
  19604         0,
  19605         2,
  19606         soc_L3_DEFIP_CAM_CONTROL1_BCM56260_A0r_fields,
  19607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19608         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19609         -1,
  19610         -1,
  19611     },
  19612 #endif /* chips */
  19613 
  19614 #if defined(BCM_56270_A0)
  19615     { /* SOC_REG_INT_L3_DEFIP_CAM_CONTROL1_BCM56270_A0r */
  19616         soc_block_list[5],
  19617         soc_genreg,
  19618         1,
  19619         0,
  19620         0x2a010100,
  19621         SOC_REG_FLAG_64_BITS,
  19622         0,
  19623         2,
  19624         soc_L3_DEFIP_CAM_CONTROL1_BCM56270_A0r_fields,
  19625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19626         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19627         -1,
  19628         -1,
  19629     },
  19630 #endif /* chips */
  19631 
  19632 #if defined(BCM_56314_A0)
  19633     { /* SOC_REG_INT_L3_DEFIP_CAM_CONTROL1_BCM56314_A0r */
  19634         soc_block_list[5],
  19635         soc_genreg,
  19636         1,
  19637         0,
  19638         0x8080001,
  19639         0,
  19640         0,
  19641         3,
  19642         soc_L3_DEFIP_CAM_CONTROL1_BCM56314_A0r_fields,
  19643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19644         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19645         -1,
  19646         -1,
  19647     },
  19648 #endif /* chips */
  19649 
  19650 #if defined(BCM_56504_B0)
  19651     { /* SOC_REG_INT_L3_DEFIP_CAM_CONTROL1_BCM56504_B0r */
  19652         soc_block_list[5],
  19653         soc_genreg,
  19654         1,
  19655         0,
  19656         0x8080001,
  19657         0,
  19658         0,
  19659         8,
  19660         soc_L3_DEFIP_CAM_CONTROL1_BCM56504_B0r_fields,
  19661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19662         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19663         -1,
  19664         -1,
  19665     },
  19666 #endif /* chips */
  19667 
  19668 #if defined(BCM_56514_A0)
  19669     { /* SOC_REG_INT_L3_DEFIP_CAM_CONTROL1_BCM56514_A0r */
  19670         soc_block_list[5],
  19671         soc_genreg,
  19672         1,
  19673         0,
  19674         0x8080001,
  19675         0,
  19676         0,
  19677         14,
  19678         soc_L3_DEFIP_CAM_CONTROL1_BCM56514_A0r_fields,
  19679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19680         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19681         -1,
  19682         -1,
  19683     },
  19684 #endif /* chips */
  19685 
  19686 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  19687     defined(BCM_56820_A0)
  19688     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0r */
  19689         soc_block_list[5],
  19690         soc_genreg,
  19691         1,
  19692         0,
  19693         0x8080c00,
  19694         0,
  19695         0,
  19696         1,
  19697         soc_L3_DEFIP_CAM_DBGCTRL0r_fields,
  19698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19700         -1,
  19701         -1,
  19702     },
  19703 #endif /* chips */
  19704 
  19705 #if defined(BCM_56340_A0)
  19706     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL01r */
  19707         soc_block_list[5],
  19708         soc_genreg,
  19709         1,
  19710         0,
  19711         0x22010600,
  19712         0,
  19713         0,
  19714         2,
  19715         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56450_A0r_fields,
  19716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19718         -1,
  19719         -1,
  19720     },
  19721 #endif /* chips */
  19722 
  19723 #if defined(BCM_56800_A0)
  19724     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1r */
  19725         soc_block_list[5],
  19726         soc_genreg,
  19727         1,
  19728         0,
  19729         0x8080c01,
  19730         0,
  19731         0,
  19732         2,
  19733         soc_L3_DEFIP_CAM_DBGCTRL1r_fields,
  19734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19736         -1,
  19737         -1,
  19738     },
  19739 #endif /* chips */
  19740 
  19741 #if defined(BCM_56340_A0)
  19742     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL02r */
  19743         soc_block_list[5],
  19744         soc_genreg,
  19745         1,
  19746         0,
  19747         0x22010c00,
  19748         0,
  19749         0,
  19750         2,
  19751         soc_L3_DEFIP_CAM_DBGCTRL02r_fields,
  19752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19754         -1,
  19755         -1,
  19756     },
  19757 #endif /* chips */
  19758 
  19759 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  19760     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  19761     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2r */
  19762         soc_block_list[5],
  19763         soc_genreg,
  19764         1,
  19765         0,
  19766         0xa080144,
  19767         0,
  19768         0,
  19769         2,
  19770         soc_L3_DEFIP_CAM_DBGCTRL2r_fields,
  19771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19773         -1,
  19774         -1,
  19775     },
  19776 #endif /* chips */
  19777 
  19778 #if defined(BCM_56340_A0)
  19779     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL03r */
  19780         soc_block_list[5],
  19781         soc_genreg,
  19782         1,
  19783         0,
  19784         0x22011200,
  19785         0,
  19786         0,
  19787         2,
  19788         soc_L3_DEFIP_CAM_DBGCTRL03r_fields,
  19789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19791         -1,
  19792         -1,
  19793     },
  19794 #endif /* chips */
  19795 
  19796 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  19797     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  19798     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3r */
  19799         soc_block_list[5],
  19800         soc_genreg,
  19801         1,
  19802         0,
  19803         0xa080145,
  19804         0,
  19805         0,
  19806         2,
  19807         soc_L3_DEFIP_CAM_DBGCTRL3r_fields,
  19808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19810         -1,
  19811         -1,
  19812     },
  19813 #endif /* chips */
  19814 
  19815 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  19816     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4r */
  19817         soc_block_list[5],
  19818         soc_genreg,
  19819         1,
  19820         0,
  19821         0x22010400,
  19822         0,
  19823         0,
  19824         4,
  19825         soc_L3_DEFIP_CAM_DBGCTRL4r_fields,
  19826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19828         -1,
  19829         -1,
  19830     },
  19831 #endif /* chips */
  19832 
  19833 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  19834     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5r */
  19835         soc_block_list[5],
  19836         soc_genreg,
  19837         1,
  19838         0,
  19839         0x22010500,
  19840         0,
  19841         0,
  19842         4,
  19843         soc_L3_DEFIP_CAM_DBGCTRL5r_fields,
  19844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19845         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19846         -1,
  19847         -1,
  19848     },
  19849 #endif /* chips */
  19850 
  19851 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  19852     defined(BCM_56450_B1)
  19853     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL6r */
  19854         soc_block_list[5],
  19855         soc_genreg,
  19856         1,
  19857         0,
  19858         0x2a010600,
  19859         0,
  19860         0,
  19861         2,
  19862         soc_L3_DEFIP_CAM_DBGCTRL6r_fields,
  19863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19864         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19865         -1,
  19866         -1,
  19867     },
  19868 #endif /* chips */
  19869 
  19870 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  19871     defined(BCM_56450_B1)
  19872     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL7r */
  19873         soc_block_list[5],
  19874         soc_genreg,
  19875         1,
  19876         0,
  19877         0x2a010700,
  19878         0,
  19879         0,
  19880         2,
  19881         soc_L3_DEFIP_CAM_DBGCTRL7r_fields,
  19882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19883         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19884         -1,
  19885         -1,
  19886     },
  19887 #endif /* chips */
  19888 
  19889 #if defined(BCM_56340_A0)
  19890     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL11r */
  19891         soc_block_list[5],
  19892         soc_genreg,
  19893         1,
  19894         0,
  19895         0x22010700,
  19896         0,
  19897         0,
  19898         2,
  19899         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56450_A0r_fields,
  19900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19901         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19902         -1,
  19903         -1,
  19904     },
  19905 #endif /* chips */
  19906 
  19907 #if defined(BCM_56340_A0)
  19908     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL12r */
  19909         soc_block_list[5],
  19910         soc_genreg,
  19911         1,
  19912         0,
  19913         0x22010d00,
  19914         0,
  19915         0,
  19916         2,
  19917         soc_L3_DEFIP_CAM_DBGCTRL12r_fields,
  19918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19919         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19920         -1,
  19921         -1,
  19922     },
  19923 #endif /* chips */
  19924 
  19925 #if defined(BCM_56340_A0)
  19926     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL13r */
  19927         soc_block_list[5],
  19928         soc_genreg,
  19929         1,
  19930         0,
  19931         0x22011300,
  19932         0,
  19933         0,
  19934         2,
  19935         soc_L3_DEFIP_CAM_DBGCTRL13r_fields,
  19936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19938         -1,
  19939         -1,
  19940     },
  19941 #endif /* chips */
  19942 
  19943 #if defined(BCM_56340_A0)
  19944     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL21r */
  19945         soc_block_list[5],
  19946         soc_genreg,
  19947         1,
  19948         0,
  19949         0x22010800,
  19950         0,
  19951         0,
  19952         2,
  19953         soc_L3_DEFIP_CAM_DBGCTRL6r_fields,
  19954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19956         -1,
  19957         -1,
  19958     },
  19959 #endif /* chips */
  19960 
  19961 #if defined(BCM_56340_A0)
  19962     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL22r */
  19963         soc_block_list[5],
  19964         soc_genreg,
  19965         1,
  19966         0,
  19967         0x22010e00,
  19968         0,
  19969         0,
  19970         2,
  19971         soc_L3_DEFIP_CAM_DBGCTRL22r_fields,
  19972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19973         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19974         -1,
  19975         -1,
  19976     },
  19977 #endif /* chips */
  19978 
  19979 #if defined(BCM_56340_A0)
  19980     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL23r */
  19981         soc_block_list[5],
  19982         soc_genreg,
  19983         1,
  19984         0,
  19985         0x22011400,
  19986         0,
  19987         0,
  19988         2,
  19989         soc_L3_DEFIP_CAM_DBGCTRL23r_fields,
  19990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19992         -1,
  19993         -1,
  19994     },
  19995 #endif /* chips */
  19996 
  19997 #if defined(BCM_56340_A0)
  19998     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL31r */
  19999         soc_block_list[5],
  20000         soc_genreg,
  20001         1,
  20002         0,
  20003         0x22010900,
  20004         0,
  20005         0,
  20006         2,
  20007         soc_L3_DEFIP_CAM_DBGCTRL7r_fields,
  20008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20010         -1,
  20011         -1,
  20012     },
  20013 #endif /* chips */
  20014 
  20015 #if defined(BCM_56340_A0)
  20016     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL32r */
  20017         soc_block_list[5],
  20018         soc_genreg,
  20019         1,
  20020         0,
  20021         0x22010f00,
  20022         0,
  20023         0,
  20024         2,
  20025         soc_L3_DEFIP_CAM_DBGCTRL32r_fields,
  20026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20027         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20028         -1,
  20029         -1,
  20030     },
  20031 #endif /* chips */
  20032 
  20033 #if defined(BCM_56340_A0)
  20034     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL33r */
  20035         soc_block_list[5],
  20036         soc_genreg,
  20037         1,
  20038         0,
  20039         0x22011500,
  20040         0,
  20041         0,
  20042         2,
  20043         soc_L3_DEFIP_CAM_DBGCTRL33r_fields,
  20044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20046         -1,
  20047         -1,
  20048     },
  20049 #endif /* chips */
  20050 
  20051 #if defined(BCM_56340_A0)
  20052     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL41r */
  20053         soc_block_list[5],
  20054         soc_genreg,
  20055         1,
  20056         0,
  20057         0x22010a00,
  20058         0,
  20059         0,
  20060         4,
  20061         soc_L3_DEFIP_CAM_DBGCTRL41r_fields,
  20062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20064         -1,
  20065         -1,
  20066     },
  20067 #endif /* chips */
  20068 
  20069 #if defined(BCM_56340_A0)
  20070     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL42r */
  20071         soc_block_list[5],
  20072         soc_genreg,
  20073         1,
  20074         0,
  20075         0x22011000,
  20076         0,
  20077         0,
  20078         4,
  20079         soc_L3_DEFIP_CAM_DBGCTRL42r_fields,
  20080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20081         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20082         -1,
  20083         -1,
  20084     },
  20085 #endif /* chips */
  20086 
  20087 #if defined(BCM_56340_A0)
  20088     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL43r */
  20089         soc_block_list[5],
  20090         soc_genreg,
  20091         1,
  20092         0,
  20093         0x22011600,
  20094         0,
  20095         0,
  20096         4,
  20097         soc_L3_DEFIP_CAM_DBGCTRL43r_fields,
  20098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20100         -1,
  20101         -1,
  20102     },
  20103 #endif /* chips */
  20104 
  20105 #if defined(BCM_56340_A0)
  20106     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL51r */
  20107         soc_block_list[5],
  20108         soc_genreg,
  20109         1,
  20110         0,
  20111         0x22010b00,
  20112         0,
  20113         0,
  20114         4,
  20115         soc_L3_DEFIP_CAM_DBGCTRL51r_fields,
  20116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20118         -1,
  20119         -1,
  20120     },
  20121 #endif /* chips */
  20122 
  20123 #if defined(BCM_56340_A0)
  20124     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL52r */
  20125         soc_block_list[5],
  20126         soc_genreg,
  20127         1,
  20128         0,
  20129         0x22011100,
  20130         0,
  20131         0,
  20132         4,
  20133         soc_L3_DEFIP_CAM_DBGCTRL52r_fields,
  20134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20136         -1,
  20137         -1,
  20138     },
  20139 #endif /* chips */
  20140 
  20141 #if defined(BCM_56340_A0)
  20142     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL53r */
  20143         soc_block_list[5],
  20144         soc_genreg,
  20145         1,
  20146         0,
  20147         0x22011700,
  20148         0,
  20149         0,
  20150         4,
  20151         soc_L3_DEFIP_CAM_DBGCTRL53r_fields,
  20152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20153         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20154         -1,
  20155         -1,
  20156     },
  20157 #endif /* chips */
  20158 
  20159 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  20160     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_64r */
  20161         soc_block_list[5],
  20162         soc_genreg,
  20163         1,
  20164         0,
  20165         0x2a010000,
  20166         SOC_REG_FLAG_64_BITS,
  20167         0,
  20168         3,
  20169         soc_L3_DEFIP_CAM_DBGCTRL0_64r_fields,
  20170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20171         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20172         -1,
  20173         -1,
  20174     },
  20175 #endif /* chips */
  20176 
  20177 #if defined(BCM_56270_A0)
  20178     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_64_BCM56270_A0r */
  20179         soc_block_list[5],
  20180         soc_genreg,
  20181         1,
  20182         0,
  20183         0x2a010000,
  20184         SOC_REG_FLAG_64_BITS,
  20185         0,
  20186         3,
  20187         soc_L3_DEFIP_CAM_DBGCTRL0_64_BCM56270_A0r_fields,
  20188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20189         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20190         -1,
  20191         -1,
  20192     },
  20193 #endif /* chips */
  20194 
  20195 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  20196     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  20197     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM53400_A0r */
  20198         soc_block_list[5],
  20199         soc_genreg,
  20200         1,
  20201         0,
  20202         0x26010200,
  20203         0,
  20204         0,
  20205         2,
  20206         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM53400_A0r_fields,
  20207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20208         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20209         -1,
  20210         -1,
  20211     },
  20212 #endif /* chips */
  20213 
  20214 #if defined(BCM_53540_A0)
  20215     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM53540_A0r */
  20216         soc_block_list[5],
  20217         soc_genreg,
  20218         1,
  20219         0,
  20220         0x26010200,
  20221         0,
  20222         0,
  20223         2,
  20224         soc_L3_DEFIP_CAM_DBGCTRL0_BCM53540_A0r_fields,
  20225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20226         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20227         -1,
  20228         -1,
  20229     },
  20230 #endif /* chips */
  20231 
  20232 #if defined(BCM_56142_A0)
  20233     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56142_A0r */
  20234         soc_block_list[5],
  20235         soc_genreg,
  20236         1,
  20237         0,
  20238         0xa080150,
  20239         0,
  20240         0,
  20241         2,
  20242         soc_L3_DEFIP_128_CAM_DBGCTRLr_fields,
  20243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20244         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20245         -1,
  20246         -1,
  20247     },
  20248 #endif /* chips */
  20249 
  20250 #if defined(BCM_56150_A0)
  20251     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56150_A0r */
  20252         soc_block_list[5],
  20253         soc_genreg,
  20254         1,
  20255         0,
  20256         0x2a010200,
  20257         0,
  20258         0,
  20259         2,
  20260         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56640_A0r_fields,
  20261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20262         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20263         -1,
  20264         -1,
  20265     },
  20266 #endif /* chips */
  20267 
  20268 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  20269     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56334_A0r */
  20270         soc_block_list[5],
  20271         soc_genreg,
  20272         1,
  20273         0,
  20274         0xa080168,
  20275         0,
  20276         0,
  20277         2,
  20278         soc_L3_DEFIP_128_CAM_DBGCTRLr_fields,
  20279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20280         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20281         -1,
  20282         -1,
  20283     },
  20284 #endif /* chips */
  20285 
  20286 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  20287     defined(BCM_56450_B1)
  20288     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56450_A0r */
  20289         soc_block_list[5],
  20290         soc_genreg,
  20291         1,
  20292         0,
  20293         0x2a010000,
  20294         0,
  20295         0,
  20296         3,
  20297         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56450_A0r_fields,
  20298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20300         -1,
  20301         -1,
  20302     },
  20303 #endif /* chips */
  20304 
  20305 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  20306     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  20307     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56560_A0r */
  20308         soc_block_list[5],
  20309         soc_genreg,
  20310         1,
  20311         0,
  20312         0x3b800000,
  20313         0,
  20314         0,
  20315         1,
  20316         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56560_A0r_fields,
  20317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20319         -1,
  20320         -1,
  20321     },
  20322 #endif /* chips */
  20323 
  20324 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  20325     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  20326     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56624_A0r */
  20327         soc_block_list[5],
  20328         soc_genreg,
  20329         1,
  20330         0,
  20331         0xa080142,
  20332         0,
  20333         0,
  20334         2,
  20335         soc_L3_DEFIP_128_CAM_DBGCTRLr_fields,
  20336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20337         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20338         -1,
  20339         -1,
  20340     },
  20341 #endif /* chips */
  20342 
  20343 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  20344     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  20345     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  20346     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56634_A0r */
  20347         soc_block_list[5],
  20348         soc_genreg,
  20349         1,
  20350         0,
  20351         0x90801a3,
  20352         0,
  20353         0,
  20354         2,
  20355         soc_L3_DEFIP_128_CAM_DBGCTRLr_fields,
  20356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20358         -1,
  20359         -1,
  20360     },
  20361 #endif /* chips */
  20362 
  20363 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  20364     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56640_A0r */
  20365         soc_block_list[5],
  20366         soc_genreg,
  20367         1,
  20368         0,
  20369         0x22010000,
  20370         0,
  20371         0,
  20372         2,
  20373         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56640_A0r_fields,
  20374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20375         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20376         -1,
  20377         -1,
  20378     },
  20379 #endif /* chips */
  20380 
  20381 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  20382     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20383     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56840_A0r */
  20384         soc_block_list[5],
  20385         soc_genreg,
  20386         1,
  20387         0,
  20388         0xa080d00,
  20389         0,
  20390         0,
  20391         2,
  20392         soc_L3_DEFIP_128_CAM_DBGCTRL_BCM56840_A0r_fields,
  20393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20394         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20395         -1,
  20396         -1,
  20397     },
  20398 #endif /* chips */
  20399 
  20400 #if defined(BCM_56850_A0)
  20401     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56850_A0r */
  20402         soc_block_list[5],
  20403         soc_genreg,
  20404         1,
  20405         0,
  20406         0x2b800000,
  20407         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20408         0,
  20409         2,
  20410         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56640_A0r_fields,
  20411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20412         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20413         -1,
  20414         -1,
  20415     },
  20416 #endif /* chips */
  20417 
  20418 #if defined(BCM_56860_A0)
  20419     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56860_A0r */
  20420         soc_block_list[5],
  20421         soc_genreg,
  20422         1,
  20423         0,
  20424         0x3b800000,
  20425         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20426         0,
  20427         1,
  20428         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56860_A0r_fields,
  20429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20430         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20431         -1,
  20432         -1,
  20433     },
  20434 #endif /* chips */
  20435 
  20436 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  20437     defined(BCM_56870_A0)
  20438     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56870_A0r */
  20439         soc_block_list[5],
  20440         soc_genreg,
  20441         1,
  20442         0,
  20443         0x6b800000,
  20444         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20445         0,
  20446         2,
  20447         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56870_A0r_fields,
  20448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20449         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20450         -1,
  20451         -1,
  20452         3,
  20453     },
  20454 #endif /* chips */
  20455 
  20456 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20457     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56960_A0r */
  20458         soc_block_list[5],
  20459         soc_genreg,
  20460         1,
  20461         0,
  20462         0x3b800000,
  20463         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20464         0,
  20465         2,
  20466         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56960_A0r_fields,
  20467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20468         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20469         -1,
  20470         -1,
  20471         3,
  20472     },
  20473 #endif /* chips */
  20474 
  20475 #if defined(BCM_56970_A0)
  20476     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_BCM56970_A0r */
  20477         soc_block_list[5],
  20478         soc_genreg,
  20479         1,
  20480         0,
  20481         0x5f800000,
  20482         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20483         0,
  20484         3,
  20485         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56970_A0r_fields,
  20486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20488         -1,
  20489         -1,
  20490         3,
  20491     },
  20492 #endif /* chips */
  20493 
  20494 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20495     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE0r */
  20496         soc_block_list[5],
  20497         soc_genreg,
  20498         1,
  20499         0,
  20500         0x3b800000,
  20501         0,
  20502         0,
  20503         2,
  20504         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56960_A0r_fields,
  20505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20506         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20507         -1,
  20508         -1,
  20509         3,
  20510     },
  20511 #endif /* chips */
  20512 
  20513 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20514     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE1r */
  20515         soc_block_list[5],
  20516         soc_genreg,
  20517         1,
  20518         0,
  20519         0x3b800000,
  20520         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20521         0,
  20522         2,
  20523         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56960_A0r_fields,
  20524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20525         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20526         -1,
  20527         -1,
  20528         3,
  20529     },
  20530 #endif /* chips */
  20531 
  20532 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20533     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE2r */
  20534         soc_block_list[5],
  20535         soc_genreg,
  20536         1,
  20537         0,
  20538         0x3b800000,
  20539         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20540         0,
  20541         2,
  20542         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56960_A0r_fields,
  20543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20544         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20545         -1,
  20546         -1,
  20547         3,
  20548     },
  20549 #endif /* chips */
  20550 
  20551 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20552     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE3r */
  20553         soc_block_list[5],
  20554         soc_genreg,
  20555         1,
  20556         0,
  20557         0x3b800000,
  20558         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20559         0,
  20560         2,
  20561         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56960_A0r_fields,
  20562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20564         -1,
  20565         -1,
  20566         3,
  20567     },
  20568 #endif /* chips */
  20569 
  20570 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  20571     defined(BCM_56870_A0)
  20572     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE0_BCM56870_A0r */
  20573         soc_block_list[5],
  20574         soc_genreg,
  20575         1,
  20576         0,
  20577         0x6b800000,
  20578         0,
  20579         0,
  20580         2,
  20581         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56870_A0r_fields,
  20582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20584         -1,
  20585         -1,
  20586         3,
  20587     },
  20588 #endif /* chips */
  20589 
  20590 #if defined(BCM_56970_A0)
  20591     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE0_BCM56970_A0r */
  20592         soc_block_list[5],
  20593         soc_genreg,
  20594         1,
  20595         0,
  20596         0x5f800000,
  20597         0,
  20598         0,
  20599         3,
  20600         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56970_A0r_fields,
  20601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20602         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20603         -1,
  20604         -1,
  20605         3,
  20606     },
  20607 #endif /* chips */
  20608 
  20609 #if defined(BCM_56870_A0)
  20610     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE1_BCM56870_A0r */
  20611         soc_block_list[5],
  20612         soc_genreg,
  20613         1,
  20614         0,
  20615         0x6b800000,
  20616         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20617         0,
  20618         2,
  20619         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56870_A0r_fields,
  20620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20622         -1,
  20623         -1,
  20624         3,
  20625     },
  20626 #endif /* chips */
  20627 
  20628 #if defined(BCM_56970_A0)
  20629     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE1_BCM56970_A0r */
  20630         soc_block_list[5],
  20631         soc_genreg,
  20632         1,
  20633         0,
  20634         0x5f800000,
  20635         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20636         0,
  20637         3,
  20638         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56970_A0r_fields,
  20639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20640         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20641         -1,
  20642         -1,
  20643         3,
  20644     },
  20645 #endif /* chips */
  20646 
  20647 #if defined(BCM_56970_A0)
  20648     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE2_BCM56970_A0r */
  20649         soc_block_list[5],
  20650         soc_genreg,
  20651         1,
  20652         0,
  20653         0x5f800000,
  20654         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20655         0,
  20656         3,
  20657         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56970_A0r_fields,
  20658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20659         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20660         -1,
  20661         -1,
  20662         3,
  20663     },
  20664 #endif /* chips */
  20665 
  20666 #if defined(BCM_56970_A0)
  20667     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL0_PIPE3_BCM56970_A0r */
  20668         soc_block_list[5],
  20669         soc_genreg,
  20670         1,
  20671         0,
  20672         0x5f800000,
  20673         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20674         0,
  20675         3,
  20676         soc_L3_DEFIP_CAM_DBGCTRL0_BCM56970_A0r_fields,
  20677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20678         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20679         -1,
  20680         -1,
  20681         3,
  20682     },
  20683 #endif /* chips */
  20684 
  20685 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20686     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20687     defined(BCM_56160_A0)
  20688     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM53400_A0r */
  20689         soc_block_list[5],
  20690         soc_genreg,
  20691         1,
  20692         0,
  20693         0x26010300,
  20694         0,
  20695         0,
  20696         2,
  20697         soc_L3_DEFIP_CAM_DBGCTRL1_BCM53400_A0r_fields,
  20698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20700         -1,
  20701         -1,
  20702     },
  20703 #endif /* chips */
  20704 
  20705 #if defined(BCM_56142_A0)
  20706     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56142_A0r */
  20707         soc_block_list[5],
  20708         soc_genreg,
  20709         1,
  20710         0,
  20711         0xa080151,
  20712         0,
  20713         0,
  20714         2,
  20715         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56624_A0r_fields,
  20716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20718         -1,
  20719         -1,
  20720     },
  20721 #endif /* chips */
  20722 
  20723 #if defined(BCM_56150_A0)
  20724     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56150_A0r */
  20725         soc_block_list[5],
  20726         soc_genreg,
  20727         1,
  20728         0,
  20729         0x2a010300,
  20730         0,
  20731         0,
  20732         2,
  20733         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56150_A0r_fields,
  20734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20736         -1,
  20737         -1,
  20738     },
  20739 #endif /* chips */
  20740 
  20741 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  20742     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56334_A0r */
  20743         soc_block_list[5],
  20744         soc_genreg,
  20745         1,
  20746         0,
  20747         0xa080169,
  20748         0,
  20749         0,
  20750         2,
  20751         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56624_A0r_fields,
  20752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20754         -1,
  20755         -1,
  20756     },
  20757 #endif /* chips */
  20758 
  20759 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  20760     defined(BCM_56450_B1)
  20761     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56450_A0r */
  20762         soc_block_list[5],
  20763         soc_genreg,
  20764         1,
  20765         0,
  20766         0x2a010100,
  20767         0,
  20768         0,
  20769         2,
  20770         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56640_A0r_fields,
  20771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20773         -1,
  20774         -1,
  20775     },
  20776 #endif /* chips */
  20777 
  20778 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  20779     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56560_A0r */
  20780         soc_block_list[5],
  20781         soc_genreg,
  20782         1,
  20783         0,
  20784         0x3b810000,
  20785         0,
  20786         0,
  20787         2,
  20788         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56560_A0r_fields,
  20789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20791         -1,
  20792         -1,
  20793     },
  20794 #endif /* chips */
  20795 
  20796 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  20797     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  20798     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56624_A0r */
  20799         soc_block_list[5],
  20800         soc_genreg,
  20801         1,
  20802         0,
  20803         0xa080143,
  20804         0,
  20805         0,
  20806         2,
  20807         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56624_A0r_fields,
  20808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20810         -1,
  20811         -1,
  20812     },
  20813 #endif /* chips */
  20814 
  20815 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  20816     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  20817     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  20818     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56634_A0r */
  20819         soc_block_list[5],
  20820         soc_genreg,
  20821         1,
  20822         0,
  20823         0x90801a4,
  20824         0,
  20825         0,
  20826         2,
  20827         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56624_A0r_fields,
  20828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20829         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20830         -1,
  20831         -1,
  20832     },
  20833 #endif /* chips */
  20834 
  20835 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  20836     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56640_A0r */
  20837         soc_block_list[5],
  20838         soc_genreg,
  20839         1,
  20840         0,
  20841         0x22010100,
  20842         0,
  20843         0,
  20844         2,
  20845         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56640_A0r_fields,
  20846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20847         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20848         -1,
  20849         -1,
  20850     },
  20851 #endif /* chips */
  20852 
  20853 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  20854     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20855     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56840_A0r */
  20856         soc_block_list[5],
  20857         soc_genreg,
  20858         1,
  20859         0,
  20860         0xa080d01,
  20861         0,
  20862         0,
  20863         2,
  20864         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56840_A0r_fields,
  20865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20866         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20867         -1,
  20868         -1,
  20869     },
  20870 #endif /* chips */
  20871 
  20872 #if defined(BCM_56850_A0)
  20873     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56850_A0r */
  20874         soc_block_list[5],
  20875         soc_genreg,
  20876         1,
  20877         0,
  20878         0x2b810000,
  20879         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20880         0,
  20881         2,
  20882         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56640_A0r_fields,
  20883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20884         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20885         -1,
  20886         -1,
  20887     },
  20888 #endif /* chips */
  20889 
  20890 #if defined(BCM_56860_A0)
  20891     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL1_BCM56860_A0r */
  20892         soc_block_list[5],
  20893         soc_genreg,
  20894         1,
  20895         0,
  20896         0x3b810000,
  20897         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20898         0,
  20899         2,
  20900         soc_L3_DEFIP_CAM_DBGCTRL1_BCM56640_A0r_fields,
  20901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20902         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20903         -1,
  20904         -1,
  20905     },
  20906 #endif /* chips */
  20907 
  20908 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20909     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20910     defined(BCM_56160_A0)
  20911     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM53400_A0r */
  20912         soc_block_list[5],
  20913         soc_genreg,
  20914         1,
  20915         0,
  20916         0x26010400,
  20917         0,
  20918         0,
  20919         2,
  20920         soc_L3_DEFIP_CAM_DBGCTRL2_BCM53400_A0r_fields,
  20921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20922         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20923         -1,
  20924         -1,
  20925     },
  20926 #endif /* chips */
  20927 
  20928 #if defined(BCM_56142_A0)
  20929     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56142_A0r */
  20930         soc_block_list[5],
  20931         soc_genreg,
  20932         1,
  20933         0,
  20934         0xa080152,
  20935         0,
  20936         0,
  20937         2,
  20938         soc_L3_DEFIP_CAM_DBGCTRL2r_fields,
  20939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20940         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20941         -1,
  20942         -1,
  20943     },
  20944 #endif /* chips */
  20945 
  20946 #if defined(BCM_56150_A0)
  20947     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56150_A0r */
  20948         soc_block_list[5],
  20949         soc_genreg,
  20950         1,
  20951         0,
  20952         0x2a010400,
  20953         0,
  20954         0,
  20955         2,
  20956         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56150_A0r_fields,
  20957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20959         -1,
  20960         -1,
  20961     },
  20962 #endif /* chips */
  20963 
  20964 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  20965     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56334_A0r */
  20966         soc_block_list[5],
  20967         soc_genreg,
  20968         1,
  20969         0,
  20970         0xa08016a,
  20971         0,
  20972         0,
  20973         2,
  20974         soc_L3_DEFIP_CAM_DBGCTRL2r_fields,
  20975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20976         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20977         -1,
  20978         -1,
  20979     },
  20980 #endif /* chips */
  20981 
  20982 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  20983     defined(BCM_56450_B1)
  20984     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56450_A0r */
  20985         soc_block_list[5],
  20986         soc_genreg,
  20987         1,
  20988         0,
  20989         0x2a010200,
  20990         0,
  20991         0,
  20992         2,
  20993         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56640_A0r_fields,
  20994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20995         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20996         -1,
  20997         -1,
  20998     },
  20999 #endif /* chips */
  21000 
  21001 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  21002     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56560_A0r */
  21003         soc_block_list[5],
  21004         soc_genreg,
  21005         1,
  21006         0,
  21007         0x3b820000,
  21008         0,
  21009         0,
  21010         2,
  21011         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21013         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21014         -1,
  21015         -1,
  21016     },
  21017 #endif /* chips */
  21018 
  21019 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  21020     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  21021     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  21022     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56634_A0r */
  21023         soc_block_list[5],
  21024         soc_genreg,
  21025         1,
  21026         0,
  21027         0x90801a5,
  21028         0,
  21029         0,
  21030         2,
  21031         soc_L3_DEFIP_CAM_DBGCTRL2r_fields,
  21032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21034         -1,
  21035         -1,
  21036     },
  21037 #endif /* chips */
  21038 
  21039 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  21040     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56640_A0r */
  21041         soc_block_list[5],
  21042         soc_genreg,
  21043         1,
  21044         0,
  21045         0x22010200,
  21046         0,
  21047         0,
  21048         2,
  21049         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56640_A0r_fields,
  21050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21052         -1,
  21053         -1,
  21054     },
  21055 #endif /* chips */
  21056 
  21057 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  21058     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56670_A0r */
  21059         soc_block_list[5],
  21060         soc_genreg,
  21061         1,
  21062         0,
  21063         0x3b810000,
  21064         0,
  21065         0,
  21066         2,
  21067         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56670_A0r_fields,
  21068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21070         -1,
  21071         -1,
  21072     },
  21073 #endif /* chips */
  21074 
  21075 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  21076     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  21077     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56840_A0r */
  21078         soc_block_list[5],
  21079         soc_genreg,
  21080         1,
  21081         0,
  21082         0xa080d02,
  21083         0,
  21084         0,
  21085         2,
  21086         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56840_A0r_fields,
  21087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21088         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21089         -1,
  21090         -1,
  21091     },
  21092 #endif /* chips */
  21093 
  21094 #if defined(BCM_56850_A0)
  21095     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56850_A0r */
  21096         soc_block_list[5],
  21097         soc_genreg,
  21098         1,
  21099         0,
  21100         0x2b820000,
  21101         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21102         0,
  21103         2,
  21104         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56640_A0r_fields,
  21105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21106         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21107         -1,
  21108         -1,
  21109     },
  21110 #endif /* chips */
  21111 
  21112 #if defined(BCM_56860_A0)
  21113     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56860_A0r */
  21114         soc_block_list[5],
  21115         soc_genreg,
  21116         1,
  21117         0,
  21118         0x3b820000,
  21119         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21120         0,
  21121         2,
  21122         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56860_A0r_fields,
  21123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21124         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21125         -1,
  21126         -1,
  21127     },
  21128 #endif /* chips */
  21129 
  21130 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  21131     defined(BCM_56870_A0)
  21132     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56870_A0r */
  21133         soc_block_list[5],
  21134         soc_genreg,
  21135         1,
  21136         0,
  21137         0x6b810000,
  21138         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21139         0,
  21140         2,
  21141         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21143         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21144         -1,
  21145         -1,
  21146         3,
  21147     },
  21148 #endif /* chips */
  21149 
  21150 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21151     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r */
  21152         soc_block_list[5],
  21153         soc_genreg,
  21154         1,
  21155         0,
  21156         0x3b810000,
  21157         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21158         0,
  21159         2,
  21160         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21163         -1,
  21164         -1,
  21165         3,
  21166     },
  21167 #endif /* chips */
  21168 
  21169 #if defined(BCM_56970_A0)
  21170     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_BCM56970_A0r */
  21171         soc_block_list[5],
  21172         soc_genreg,
  21173         1,
  21174         0,
  21175         0x5f810000,
  21176         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21177         0,
  21178         2,
  21179         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21182         -1,
  21183         -1,
  21184         3,
  21185     },
  21186 #endif /* chips */
  21187 
  21188 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21189     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE0r */
  21190         soc_block_list[5],
  21191         soc_genreg,
  21192         1,
  21193         0,
  21194         0x3b810000,
  21195         0,
  21196         0,
  21197         2,
  21198         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21200         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21201         -1,
  21202         -1,
  21203         3,
  21204     },
  21205 #endif /* chips */
  21206 
  21207 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21208     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE1r */
  21209         soc_block_list[5],
  21210         soc_genreg,
  21211         1,
  21212         0,
  21213         0x3b810000,
  21214         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21215         0,
  21216         2,
  21217         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21219         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21220         -1,
  21221         -1,
  21222         3,
  21223     },
  21224 #endif /* chips */
  21225 
  21226 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21227     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE2r */
  21228         soc_block_list[5],
  21229         soc_genreg,
  21230         1,
  21231         0,
  21232         0x3b810000,
  21233         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21234         0,
  21235         2,
  21236         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21238         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21239         -1,
  21240         -1,
  21241         3,
  21242     },
  21243 #endif /* chips */
  21244 
  21245 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21246     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE3r */
  21247         soc_block_list[5],
  21248         soc_genreg,
  21249         1,
  21250         0,
  21251         0x3b810000,
  21252         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21253         0,
  21254         2,
  21255         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21257         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21258         -1,
  21259         -1,
  21260         3,
  21261     },
  21262 #endif /* chips */
  21263 
  21264 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  21265     defined(BCM_56870_A0)
  21266     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE0_BCM56870_A0r */
  21267         soc_block_list[5],
  21268         soc_genreg,
  21269         1,
  21270         0,
  21271         0x6b810000,
  21272         0,
  21273         0,
  21274         2,
  21275         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21277         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21278         -1,
  21279         -1,
  21280         3,
  21281     },
  21282 #endif /* chips */
  21283 
  21284 #if defined(BCM_56970_A0)
  21285     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE0_BCM56970_A0r */
  21286         soc_block_list[5],
  21287         soc_genreg,
  21288         1,
  21289         0,
  21290         0x5f810000,
  21291         0,
  21292         0,
  21293         2,
  21294         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21296         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21297         -1,
  21298         -1,
  21299         3,
  21300     },
  21301 #endif /* chips */
  21302 
  21303 #if defined(BCM_56870_A0)
  21304     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE1_BCM56870_A0r */
  21305         soc_block_list[5],
  21306         soc_genreg,
  21307         1,
  21308         0,
  21309         0x6b810000,
  21310         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21311         0,
  21312         2,
  21313         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21315         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21316         -1,
  21317         -1,
  21318         3,
  21319     },
  21320 #endif /* chips */
  21321 
  21322 #if defined(BCM_56970_A0)
  21323     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE1_BCM56970_A0r */
  21324         soc_block_list[5],
  21325         soc_genreg,
  21326         1,
  21327         0,
  21328         0x5f810000,
  21329         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21330         0,
  21331         2,
  21332         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21334         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21335         -1,
  21336         -1,
  21337         3,
  21338     },
  21339 #endif /* chips */
  21340 
  21341 #if defined(BCM_56970_A0)
  21342     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE2_BCM56970_A0r */
  21343         soc_block_list[5],
  21344         soc_genreg,
  21345         1,
  21346         0,
  21347         0x5f810000,
  21348         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21349         0,
  21350         2,
  21351         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21353         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21354         -1,
  21355         -1,
  21356         3,
  21357     },
  21358 #endif /* chips */
  21359 
  21360 #if defined(BCM_56970_A0)
  21361     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL2_PIPE3_BCM56970_A0r */
  21362         soc_block_list[5],
  21363         soc_genreg,
  21364         1,
  21365         0,
  21366         0x5f810000,
  21367         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21368         0,
  21369         2,
  21370         soc_L3_DEFIP_CAM_DBGCTRL2_BCM56960_A0r_fields,
  21371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21372         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21373         -1,
  21374         -1,
  21375         3,
  21376     },
  21377 #endif /* chips */
  21378 
  21379 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  21380     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56260_A0r */
  21381         soc_block_list[5],
  21382         soc_genreg,
  21383         1,
  21384         0,
  21385         0x2a010300,
  21386         0,
  21387         0,
  21388         2,
  21389         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56260_A0r_fields,
  21390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21391         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21392         -1,
  21393         -1,
  21394     },
  21395 #endif /* chips */
  21396 
  21397 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  21398     defined(BCM_56450_B1)
  21399     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56450_A0r */
  21400         soc_block_list[5],
  21401         soc_genreg,
  21402         1,
  21403         0,
  21404         0x2a010300,
  21405         0,
  21406         0,
  21407         2,
  21408         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56640_A0r_fields,
  21409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21410         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21411         -1,
  21412         -1,
  21413     },
  21414 #endif /* chips */
  21415 
  21416 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  21417     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56560_A0r */
  21418         soc_block_list[5],
  21419         soc_genreg,
  21420         1,
  21421         0,
  21422         0x3b830000,
  21423         0,
  21424         0,
  21425         2,
  21426         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21429         -1,
  21430         -1,
  21431     },
  21432 #endif /* chips */
  21433 
  21434 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  21435     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  21436     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  21437     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56634_A0r */
  21438         soc_block_list[5],
  21439         soc_genreg,
  21440         1,
  21441         0,
  21442         0x90801a6,
  21443         0,
  21444         0,
  21445         2,
  21446         soc_L3_DEFIP_CAM_DBGCTRL3r_fields,
  21447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21448         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21449         -1,
  21450         -1,
  21451     },
  21452 #endif /* chips */
  21453 
  21454 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  21455     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56640_A0r */
  21456         soc_block_list[5],
  21457         soc_genreg,
  21458         1,
  21459         0,
  21460         0x22010300,
  21461         0,
  21462         0,
  21463         2,
  21464         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56640_A0r_fields,
  21465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21466         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21467         -1,
  21468         -1,
  21469     },
  21470 #endif /* chips */
  21471 
  21472 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  21473     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56670_A0r */
  21474         soc_block_list[5],
  21475         soc_genreg,
  21476         1,
  21477         0,
  21478         0x3b820000,
  21479         0,
  21480         0,
  21481         2,
  21482         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56670_A0r_fields,
  21483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21484         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21485         -1,
  21486         -1,
  21487     },
  21488 #endif /* chips */
  21489 
  21490 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  21491     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56840_A0r */
  21492         soc_block_list[5],
  21493         soc_genreg,
  21494         1,
  21495         0,
  21496         0xa080d03,
  21497         0,
  21498         0,
  21499         2,
  21500         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56840_A0r_fields,
  21501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21502         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21503         -1,
  21504         -1,
  21505     },
  21506 #endif /* chips */
  21507 
  21508 #if defined(BCM_56850_A0)
  21509     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56850_A0r */
  21510         soc_block_list[5],
  21511         soc_genreg,
  21512         1,
  21513         0,
  21514         0x2b830000,
  21515         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21516         0,
  21517         2,
  21518         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56640_A0r_fields,
  21519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21520         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21521         -1,
  21522         -1,
  21523     },
  21524 #endif /* chips */
  21525 
  21526 #if defined(BCM_56860_A0)
  21527     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56860_A0r */
  21528         soc_block_list[5],
  21529         soc_genreg,
  21530         1,
  21531         0,
  21532         0x3b830000,
  21533         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21534         0,
  21535         2,
  21536         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56860_A0r_fields,
  21537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21539         -1,
  21540         -1,
  21541     },
  21542 #endif /* chips */
  21543 
  21544 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  21545     defined(BCM_56870_A0)
  21546     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56870_A0r */
  21547         soc_block_list[5],
  21548         soc_genreg,
  21549         1,
  21550         0,
  21551         0x6b820000,
  21552         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21553         0,
  21554         2,
  21555         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21558         -1,
  21559         -1,
  21560         3,
  21561     },
  21562 #endif /* chips */
  21563 
  21564 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21565     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r */
  21566         soc_block_list[5],
  21567         soc_genreg,
  21568         1,
  21569         0,
  21570         0x3b820000,
  21571         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21572         0,
  21573         2,
  21574         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21577         -1,
  21578         -1,
  21579         3,
  21580     },
  21581 #endif /* chips */
  21582 
  21583 #if defined(BCM_56970_A0)
  21584     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_BCM56970_A0r */
  21585         soc_block_list[5],
  21586         soc_genreg,
  21587         1,
  21588         0,
  21589         0x5f820000,
  21590         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21591         0,
  21592         2,
  21593         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21595         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21596         -1,
  21597         -1,
  21598         3,
  21599     },
  21600 #endif /* chips */
  21601 
  21602 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21603     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE0r */
  21604         soc_block_list[5],
  21605         soc_genreg,
  21606         1,
  21607         0,
  21608         0x3b820000,
  21609         0,
  21610         0,
  21611         2,
  21612         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21614         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21615         -1,
  21616         -1,
  21617         3,
  21618     },
  21619 #endif /* chips */
  21620 
  21621 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21622     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE1r */
  21623         soc_block_list[5],
  21624         soc_genreg,
  21625         1,
  21626         0,
  21627         0x3b820000,
  21628         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21629         0,
  21630         2,
  21631         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21634         -1,
  21635         -1,
  21636         3,
  21637     },
  21638 #endif /* chips */
  21639 
  21640 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21641     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE2r */
  21642         soc_block_list[5],
  21643         soc_genreg,
  21644         1,
  21645         0,
  21646         0x3b820000,
  21647         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21648         0,
  21649         2,
  21650         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21652         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21653         -1,
  21654         -1,
  21655         3,
  21656     },
  21657 #endif /* chips */
  21658 
  21659 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21660     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE3r */
  21661         soc_block_list[5],
  21662         soc_genreg,
  21663         1,
  21664         0,
  21665         0x3b820000,
  21666         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21667         0,
  21668         2,
  21669         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21671         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21672         -1,
  21673         -1,
  21674         3,
  21675     },
  21676 #endif /* chips */
  21677 
  21678 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  21679     defined(BCM_56870_A0)
  21680     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE0_BCM56870_A0r */
  21681         soc_block_list[5],
  21682         soc_genreg,
  21683         1,
  21684         0,
  21685         0x6b820000,
  21686         0,
  21687         0,
  21688         2,
  21689         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21692         -1,
  21693         -1,
  21694         3,
  21695     },
  21696 #endif /* chips */
  21697 
  21698 #if defined(BCM_56970_A0)
  21699     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE0_BCM56970_A0r */
  21700         soc_block_list[5],
  21701         soc_genreg,
  21702         1,
  21703         0,
  21704         0x5f820000,
  21705         0,
  21706         0,
  21707         2,
  21708         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21710         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21711         -1,
  21712         -1,
  21713         3,
  21714     },
  21715 #endif /* chips */
  21716 
  21717 #if defined(BCM_56870_A0)
  21718     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE1_BCM56870_A0r */
  21719         soc_block_list[5],
  21720         soc_genreg,
  21721         1,
  21722         0,
  21723         0x6b820000,
  21724         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21725         0,
  21726         2,
  21727         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21729         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21730         -1,
  21731         -1,
  21732         3,
  21733     },
  21734 #endif /* chips */
  21735 
  21736 #if defined(BCM_56970_A0)
  21737     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE1_BCM56970_A0r */
  21738         soc_block_list[5],
  21739         soc_genreg,
  21740         1,
  21741         0,
  21742         0x5f820000,
  21743         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21744         0,
  21745         2,
  21746         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21748         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21749         -1,
  21750         -1,
  21751         3,
  21752     },
  21753 #endif /* chips */
  21754 
  21755 #if defined(BCM_56970_A0)
  21756     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE2_BCM56970_A0r */
  21757         soc_block_list[5],
  21758         soc_genreg,
  21759         1,
  21760         0,
  21761         0x5f820000,
  21762         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21763         0,
  21764         2,
  21765         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21767         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21768         -1,
  21769         -1,
  21770         3,
  21771     },
  21772 #endif /* chips */
  21773 
  21774 #if defined(BCM_56970_A0)
  21775     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL3_PIPE3_BCM56970_A0r */
  21776         soc_block_list[5],
  21777         soc_genreg,
  21778         1,
  21779         0,
  21780         0x5f820000,
  21781         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21782         0,
  21783         2,
  21784         soc_L3_DEFIP_CAM_DBGCTRL3_BCM56960_A0r_fields,
  21785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21786         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21787         -1,
  21788         -1,
  21789         3,
  21790     },
  21791 #endif /* chips */
  21792 
  21793 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  21794     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_BCM56260_A0r */
  21795         soc_block_list[5],
  21796         soc_genreg,
  21797         1,
  21798         0,
  21799         0x2a010400,
  21800         0,
  21801         0,
  21802         2,
  21803         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56260_A0r_fields,
  21804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21805         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21806         -1,
  21807         -1,
  21808     },
  21809 #endif /* chips */
  21810 
  21811 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  21812     defined(BCM_56450_B1)
  21813     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_BCM56450_A0r */
  21814         soc_block_list[5],
  21815         soc_genreg,
  21816         1,
  21817         0,
  21818         0x2a010400,
  21819         0,
  21820         0,
  21821         2,
  21822         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56450_A0r_fields,
  21823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21824         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21825         -1,
  21826         -1,
  21827     },
  21828 #endif /* chips */
  21829 
  21830 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  21831     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_BCM56560_A0r */
  21832         soc_block_list[5],
  21833         soc_genreg,
  21834         1,
  21835         0,
  21836         0x3b840000,
  21837         0,
  21838         0,
  21839         2,
  21840         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  21841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21842         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21843         -1,
  21844         -1,
  21845     },
  21846 #endif /* chips */
  21847 
  21848 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  21849     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_BCM56670_A0r */
  21850         soc_block_list[5],
  21851         soc_genreg,
  21852         1,
  21853         0,
  21854         0x3b830000,
  21855         0,
  21856         0,
  21857         2,
  21858         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56670_A0r_fields,
  21859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21860         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21861         -1,
  21862         -1,
  21863     },
  21864 #endif /* chips */
  21865 
  21866 #if defined(BCM_56850_A0)
  21867     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_BCM56850_A0r */
  21868         soc_block_list[5],
  21869         soc_genreg,
  21870         1,
  21871         0,
  21872         0x2b840000,
  21873         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21874         0,
  21875         4,
  21876         soc_L3_DEFIP_CAM_DBGCTRL4r_fields,
  21877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21878         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21879         -1,
  21880         -1,
  21881     },
  21882 #endif /* chips */
  21883 
  21884 #if defined(BCM_56860_A0)
  21885     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_BCM56860_A0r */
  21886         soc_block_list[5],
  21887         soc_genreg,
  21888         1,
  21889         0,
  21890         0x3b840000,
  21891         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21892         0,
  21893         2,
  21894         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56860_A0r_fields,
  21895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21896         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21897         -1,
  21898         -1,
  21899     },
  21900 #endif /* chips */
  21901 
  21902 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  21903     defined(BCM_56870_A0)
  21904     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_BCM56870_A0r */
  21905         soc_block_list[5],
  21906         soc_genreg,
  21907         1,
  21908         0,
  21909         0x6b830000,
  21910         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21911         0,
  21912         2,
  21913         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  21914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21916         -1,
  21917         -1,
  21918         3,
  21919     },
  21920 #endif /* chips */
  21921 
  21922 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21923     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r */
  21924         soc_block_list[5],
  21925         soc_genreg,
  21926         1,
  21927         0,
  21928         0x3b830000,
  21929         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21930         0,
  21931         2,
  21932         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  21933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21934         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21935         -1,
  21936         -1,
  21937         3,
  21938     },
  21939 #endif /* chips */
  21940 
  21941 #if defined(BCM_56970_A0)
  21942     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_BCM56970_A0r */
  21943         soc_block_list[5],
  21944         soc_genreg,
  21945         1,
  21946         0,
  21947         0x5f830000,
  21948         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21949         0,
  21950         2,
  21951         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  21952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21953         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21954         -1,
  21955         -1,
  21956         3,
  21957     },
  21958 #endif /* chips */
  21959 
  21960 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21961     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE0r */
  21962         soc_block_list[5],
  21963         soc_genreg,
  21964         1,
  21965         0,
  21966         0x3b830000,
  21967         0,
  21968         0,
  21969         2,
  21970         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  21971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21972         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21973         -1,
  21974         -1,
  21975         3,
  21976     },
  21977 #endif /* chips */
  21978 
  21979 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21980     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE1r */
  21981         soc_block_list[5],
  21982         soc_genreg,
  21983         1,
  21984         0,
  21985         0x3b830000,
  21986         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21987         0,
  21988         2,
  21989         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  21990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21992         -1,
  21993         -1,
  21994         3,
  21995     },
  21996 #endif /* chips */
  21997 
  21998 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21999     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE2r */
  22000         soc_block_list[5],
  22001         soc_genreg,
  22002         1,
  22003         0,
  22004         0x3b830000,
  22005         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22006         0,
  22007         2,
  22008         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  22009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22010         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22011         -1,
  22012         -1,
  22013         3,
  22014     },
  22015 #endif /* chips */
  22016 
  22017 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22018     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE3r */
  22019         soc_block_list[5],
  22020         soc_genreg,
  22021         1,
  22022         0,
  22023         0x3b830000,
  22024         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22025         0,
  22026         2,
  22027         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  22028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22030         -1,
  22031         -1,
  22032         3,
  22033     },
  22034 #endif /* chips */
  22035 
  22036 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  22037     defined(BCM_56870_A0)
  22038     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE0_BCM56870_A0r */
  22039         soc_block_list[5],
  22040         soc_genreg,
  22041         1,
  22042         0,
  22043         0x6b830000,
  22044         0,
  22045         0,
  22046         2,
  22047         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  22048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22050         -1,
  22051         -1,
  22052         3,
  22053     },
  22054 #endif /* chips */
  22055 
  22056 #if defined(BCM_56970_A0)
  22057     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE0_BCM56970_A0r */
  22058         soc_block_list[5],
  22059         soc_genreg,
  22060         1,
  22061         0,
  22062         0x5f830000,
  22063         0,
  22064         0,
  22065         2,
  22066         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  22067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22068         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22069         -1,
  22070         -1,
  22071         3,
  22072     },
  22073 #endif /* chips */
  22074 
  22075 #if defined(BCM_56870_A0)
  22076     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE1_BCM56870_A0r */
  22077         soc_block_list[5],
  22078         soc_genreg,
  22079         1,
  22080         0,
  22081         0x6b830000,
  22082         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22083         0,
  22084         2,
  22085         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  22086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22088         -1,
  22089         -1,
  22090         3,
  22091     },
  22092 #endif /* chips */
  22093 
  22094 #if defined(BCM_56970_A0)
  22095     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE1_BCM56970_A0r */
  22096         soc_block_list[5],
  22097         soc_genreg,
  22098         1,
  22099         0,
  22100         0x5f830000,
  22101         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22102         0,
  22103         2,
  22104         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  22105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22106         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22107         -1,
  22108         -1,
  22109         3,
  22110     },
  22111 #endif /* chips */
  22112 
  22113 #if defined(BCM_56970_A0)
  22114     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE2_BCM56970_A0r */
  22115         soc_block_list[5],
  22116         soc_genreg,
  22117         1,
  22118         0,
  22119         0x5f830000,
  22120         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22121         0,
  22122         2,
  22123         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  22124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22125         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22126         -1,
  22127         -1,
  22128         3,
  22129     },
  22130 #endif /* chips */
  22131 
  22132 #if defined(BCM_56970_A0)
  22133     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL4_PIPE3_BCM56970_A0r */
  22134         soc_block_list[5],
  22135         soc_genreg,
  22136         1,
  22137         0,
  22138         0x5f830000,
  22139         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22140         0,
  22141         2,
  22142         soc_L3_DEFIP_CAM_DBGCTRL4_BCM56960_A0r_fields,
  22143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22144         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22145         -1,
  22146         -1,
  22147         3,
  22148     },
  22149 #endif /* chips */
  22150 
  22151 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  22152     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_BCM56260_A0r */
  22153         soc_block_list[5],
  22154         soc_genreg,
  22155         1,
  22156         0,
  22157         0x2a010500,
  22158         0,
  22159         0,
  22160         2,
  22161         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56260_A0r_fields,
  22162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22163         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22164         -1,
  22165         -1,
  22166     },
  22167 #endif /* chips */
  22168 
  22169 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  22170     defined(BCM_56450_B1)
  22171     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_BCM56450_A0r */
  22172         soc_block_list[5],
  22173         soc_genreg,
  22174         1,
  22175         0,
  22176         0x2a010500,
  22177         0,
  22178         0,
  22179         2,
  22180         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56450_A0r_fields,
  22181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22182         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22183         -1,
  22184         -1,
  22185     },
  22186 #endif /* chips */
  22187 
  22188 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  22189     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_BCM56560_A0r */
  22190         soc_block_list[5],
  22191         soc_genreg,
  22192         1,
  22193         0,
  22194         0x3b850000,
  22195         0,
  22196         0,
  22197         2,
  22198         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22200         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22201         -1,
  22202         -1,
  22203     },
  22204 #endif /* chips */
  22205 
  22206 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  22207     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_BCM56670_A0r */
  22208         soc_block_list[5],
  22209         soc_genreg,
  22210         1,
  22211         0,
  22212         0x3b840000,
  22213         0,
  22214         0,
  22215         2,
  22216         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56670_A0r_fields,
  22217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22218         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22219         -1,
  22220         -1,
  22221     },
  22222 #endif /* chips */
  22223 
  22224 #if defined(BCM_56850_A0)
  22225     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_BCM56850_A0r */
  22226         soc_block_list[5],
  22227         soc_genreg,
  22228         1,
  22229         0,
  22230         0x2b850000,
  22231         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22232         0,
  22233         4,
  22234         soc_L3_DEFIP_CAM_DBGCTRL5r_fields,
  22235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22236         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22237         -1,
  22238         -1,
  22239     },
  22240 #endif /* chips */
  22241 
  22242 #if defined(BCM_56860_A0)
  22243     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_BCM56860_A0r */
  22244         soc_block_list[5],
  22245         soc_genreg,
  22246         1,
  22247         0,
  22248         0x3b850000,
  22249         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22250         0,
  22251         2,
  22252         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56860_A0r_fields,
  22253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22254         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22255         -1,
  22256         -1,
  22257     },
  22258 #endif /* chips */
  22259 
  22260 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  22261     defined(BCM_56870_A0)
  22262     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_BCM56870_A0r */
  22263         soc_block_list[5],
  22264         soc_genreg,
  22265         1,
  22266         0,
  22267         0x6b840000,
  22268         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22269         0,
  22270         2,
  22271         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22273         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22274         -1,
  22275         -1,
  22276         3,
  22277     },
  22278 #endif /* chips */
  22279 
  22280 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22281     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r */
  22282         soc_block_list[5],
  22283         soc_genreg,
  22284         1,
  22285         0,
  22286         0x3b840000,
  22287         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22288         0,
  22289         2,
  22290         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22293         -1,
  22294         -1,
  22295         3,
  22296     },
  22297 #endif /* chips */
  22298 
  22299 #if defined(BCM_56970_A0)
  22300     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_BCM56970_A0r */
  22301         soc_block_list[5],
  22302         soc_genreg,
  22303         1,
  22304         0,
  22305         0x5f840000,
  22306         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22307         0,
  22308         2,
  22309         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22312         -1,
  22313         -1,
  22314         3,
  22315     },
  22316 #endif /* chips */
  22317 
  22318 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22319     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE0r */
  22320         soc_block_list[5],
  22321         soc_genreg,
  22322         1,
  22323         0,
  22324         0x3b840000,
  22325         0,
  22326         0,
  22327         2,
  22328         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22331         -1,
  22332         -1,
  22333         3,
  22334     },
  22335 #endif /* chips */
  22336 
  22337 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22338     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE1r */
  22339         soc_block_list[5],
  22340         soc_genreg,
  22341         1,
  22342         0,
  22343         0x3b840000,
  22344         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22345         0,
  22346         2,
  22347         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22349         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22350         -1,
  22351         -1,
  22352         3,
  22353     },
  22354 #endif /* chips */
  22355 
  22356 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22357     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE2r */
  22358         soc_block_list[5],
  22359         soc_genreg,
  22360         1,
  22361         0,
  22362         0x3b840000,
  22363         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22364         0,
  22365         2,
  22366         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22369         -1,
  22370         -1,
  22371         3,
  22372     },
  22373 #endif /* chips */
  22374 
  22375 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22376     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE3r */
  22377         soc_block_list[5],
  22378         soc_genreg,
  22379         1,
  22380         0,
  22381         0x3b840000,
  22382         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22383         0,
  22384         2,
  22385         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22387         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22388         -1,
  22389         -1,
  22390         3,
  22391     },
  22392 #endif /* chips */
  22393 
  22394 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  22395     defined(BCM_56870_A0)
  22396     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE0_BCM56870_A0r */
  22397         soc_block_list[5],
  22398         soc_genreg,
  22399         1,
  22400         0,
  22401         0x6b840000,
  22402         0,
  22403         0,
  22404         2,
  22405         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22408         -1,
  22409         -1,
  22410         3,
  22411     },
  22412 #endif /* chips */
  22413 
  22414 #if defined(BCM_56970_A0)
  22415     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE0_BCM56970_A0r */
  22416         soc_block_list[5],
  22417         soc_genreg,
  22418         1,
  22419         0,
  22420         0x5f840000,
  22421         0,
  22422         0,
  22423         2,
  22424         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22426         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22427         -1,
  22428         -1,
  22429         3,
  22430     },
  22431 #endif /* chips */
  22432 
  22433 #if defined(BCM_56870_A0)
  22434     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE1_BCM56870_A0r */
  22435         soc_block_list[5],
  22436         soc_genreg,
  22437         1,
  22438         0,
  22439         0x6b840000,
  22440         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22441         0,
  22442         2,
  22443         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22446         -1,
  22447         -1,
  22448         3,
  22449     },
  22450 #endif /* chips */
  22451 
  22452 #if defined(BCM_56970_A0)
  22453     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE1_BCM56970_A0r */
  22454         soc_block_list[5],
  22455         soc_genreg,
  22456         1,
  22457         0,
  22458         0x5f840000,
  22459         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22460         0,
  22461         2,
  22462         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22464         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22465         -1,
  22466         -1,
  22467         3,
  22468     },
  22469 #endif /* chips */
  22470 
  22471 #if defined(BCM_56970_A0)
  22472     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE2_BCM56970_A0r */
  22473         soc_block_list[5],
  22474         soc_genreg,
  22475         1,
  22476         0,
  22477         0x5f840000,
  22478         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22479         0,
  22480         2,
  22481         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22484         -1,
  22485         -1,
  22486         3,
  22487     },
  22488 #endif /* chips */
  22489 
  22490 #if defined(BCM_56970_A0)
  22491     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL5_PIPE3_BCM56970_A0r */
  22492         soc_block_list[5],
  22493         soc_genreg,
  22494         1,
  22495         0,
  22496         0x5f840000,
  22497         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22498         0,
  22499         2,
  22500         soc_L3_DEFIP_CAM_DBGCTRL5_BCM56960_A0r_fields,
  22501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22502         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22503         -1,
  22504         -1,
  22505         3,
  22506     },
  22507 #endif /* chips */
  22508 
  22509 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  22510     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL6_BCM56260_A0r */
  22511         soc_block_list[5],
  22512         soc_genreg,
  22513         1,
  22514         0,
  22515         0x2a010600,
  22516         0,
  22517         0,
  22518         2,
  22519         soc_L3_DEFIP_CAM_DBGCTRL6_BCM56260_A0r_fields,
  22520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22522         -1,
  22523         -1,
  22524     },
  22525 #endif /* chips */
  22526 
  22527 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  22528     { /* SOC_REG_INT_L3_DEFIP_CAM_DBGCTRL7_BCM56260_A0r */
  22529         soc_block_list[5],
  22530         soc_genreg,
  22531         1,
  22532         0,
  22533         0x2a010700,
  22534         0,
  22535         0,
  22536         2,
  22537         soc_L3_DEFIP_CAM_DBGCTRL7_BCM56260_A0r_fields,
  22538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22540         -1,
  22541         -1,
  22542     },
  22543 #endif /* chips */
  22544 
  22545 #if defined(BCM_56514_A0)
  22546     { /* SOC_REG_INT_L3_DEFIP_CAM_DEBUG_DATA_0r */
  22547         soc_block_list[5],
  22548         soc_genreg,
  22549         1,
  22550         0,
  22551         0x808000f,
  22552         SOC_REG_FLAG_WO,
  22553         0,
  22554         1,
  22555         soc_FP_CAM_DEBUG_DATA_0r_fields,
  22556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22558         -1,
  22559         -1,
  22560     },
  22561 #endif /* chips */
  22562 
  22563 #if defined(BCM_56514_A0)
  22564     { /* SOC_REG_INT_L3_DEFIP_CAM_DEBUG_DATA_1r */
  22565         soc_block_list[5],
  22566         soc_genreg,
  22567         1,
  22568         0,
  22569         0x8080010,
  22570         SOC_REG_FLAG_WO,
  22571         0,
  22572         1,
  22573         soc_FP_CAM_DEBUG_DATA_0r_fields,
  22574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22576         -1,
  22577         -1,
  22578     },
  22579 #endif /* chips */
  22580 
  22581 #if defined(BCM_56514_A0)
  22582     { /* SOC_REG_INT_L3_DEFIP_CAM_DEBUG_DATA_2r */
  22583         soc_block_list[5],
  22584         soc_genreg,
  22585         1,
  22586         0,
  22587         0x8080011,
  22588         SOC_REG_FLAG_WO,
  22589         0,
  22590         1,
  22591         soc_FP_CAM_DEBUG_DATA_0r_fields,
  22592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22594         -1,
  22595         -1,
  22596     },
  22597 #endif /* chips */
  22598 
  22599 #if defined(BCM_56514_A0)
  22600     { /* SOC_REG_INT_L3_DEFIP_CAM_DEBUG_SENDr */
  22601         soc_block_list[5],
  22602         soc_genreg,
  22603         1,
  22604         0,
  22605         0x8080012,
  22606         SOC_REG_FLAG_WO,
  22607         0,
  22608         1,
  22609         soc_FP_CAM_DEBUG_SENDr_fields,
  22610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22612         -1,
  22613         -1,
  22614     },
  22615 #endif /* chips */
  22616 
  22617 #if defined(BCM_56504_A0) || defined(BCM_56504_B0)
  22618     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLEr */
  22619         soc_block_list[5],
  22620         soc_genreg,
  22621         1,
  22622         0,
  22623         0x8080009,
  22624         0,
  22625         0,
  22626         6,
  22627         soc_L3_DEFIP_CAM_ENABLEr_fields,
  22628         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  22629         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22630         -1,
  22631         -1,
  22632     },
  22633 #endif /* chips */
  22634 
  22635 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22636     defined(BCM_53570_A0) || defined(BCM_56160_A0)
  22637     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM53400_A0r */
  22638         soc_block_list[5],
  22639         soc_genreg,
  22640         1,
  22641         0,
  22642         0x26010900,
  22643         0,
  22644         0,
  22645         6,
  22646         soc_L3_DEFIP_CAM_ENABLE_BCM53400_A0r_fields,
  22647         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  22648         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22649         -1,
  22650         -1,
  22651     },
  22652 #endif /* chips */
  22653 
  22654 #if defined(BCM_53570_B0)
  22655     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM53570_B0r */
  22656         soc_block_list[5],
  22657         soc_genreg,
  22658         1,
  22659         0,
  22660         0x26010900,
  22661         0,
  22662         0,
  22663         32,
  22664         soc_L3_DEFIP_CAM_ENABLE_BCM53570_B0r_fields,
  22665         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  22666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22667         -1,
  22668         -1,
  22669     },
  22670 #endif /* chips */
  22671 
  22672 #if defined(BCM_56142_A0)
  22673     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56142_A0r */
  22674         soc_block_list[5],
  22675         soc_genreg,
  22676         1,
  22677         0,
  22678         0xa080153,
  22679         0,
  22680         0,
  22681         6,
  22682         soc_L3_DEFIP_CAM_ENABLEr_fields,
  22683         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  22684         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22685         -1,
  22686         -1,
  22687     },
  22688 #endif /* chips */
  22689 
  22690 #if defined(BCM_56150_A0)
  22691     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56150_A0r */
  22692         soc_block_list[5],
  22693         soc_genreg,
  22694         1,
  22695         0,
  22696         0x2a010900,
  22697         0,
  22698         0,
  22699         6,
  22700         soc_L3_DEFIP_CAM_ENABLE_BCM56150_A0r_fields,
  22701         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  22702         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22703         -1,
  22704         -1,
  22705     },
  22706 #endif /* chips */
  22707 
  22708 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  22709     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56224_A0r */
  22710         soc_block_list[5],
  22711         soc_genreg,
  22712         1,
  22713         0,
  22714         0x8080004,
  22715         0,
  22716         0,
  22717         4,
  22718         soc_L3_DEFIP_CAM_ENABLE_BCM56224_A0r_fields,
  22719         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  22720         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  22721         -1,
  22722         -1,
  22723     },
  22724 #endif /* chips */
  22725 
  22726 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  22727     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56260_A0r */
  22728         soc_block_list[5],
  22729         soc_genreg,
  22730         1,
  22731         0,
  22732         0x2a010c00,
  22733         0,
  22734         0,
  22735         6,
  22736         soc_L3_DEFIP_CAM_ENABLE_BCM53400_A0r_fields,
  22737         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  22738         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22739         -1,
  22740         -1,
  22741     },
  22742 #endif /* chips */
  22743 
  22744 #if defined(BCM_56270_A0)
  22745     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56270_A0r */
  22746         soc_block_list[5],
  22747         soc_genreg,
  22748         1,
  22749         0,
  22750         0x2a010600,
  22751         0,
  22752         0,
  22753         4,
  22754         soc_L3_DEFIP_CAM_ENABLE_BCM56270_A0r_fields,
  22755         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  22756         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  22757         -1,
  22758         -1,
  22759     },
  22760 #endif /* chips */
  22761 
  22762 #if defined(BCM_56314_A0)
  22763     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56314_A0r */
  22764         soc_block_list[5],
  22765         soc_genreg,
  22766         1,
  22767         0,
  22768         0x8080009,
  22769         0,
  22770         0,
  22771         1,
  22772         soc_L3_DEFIP_CAM_ENABLE_BCM56314_A0r_fields,
  22773         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  22774         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22775         -1,
  22776         -1,
  22777     },
  22778 #endif /* chips */
  22779 
  22780 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  22781     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56334_A0r */
  22782         soc_block_list[5],
  22783         soc_genreg,
  22784         1,
  22785         0,
  22786         0xa08016f,
  22787         0,
  22788         0,
  22789         6,
  22790         soc_L3_DEFIP_CAM_ENABLEr_fields,
  22791         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  22792         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22793         -1,
  22794         -1,
  22795     },
  22796 #endif /* chips */
  22797 
  22798 #if defined(BCM_56340_A0)
  22799     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56340_A0r */
  22800         soc_block_list[5],
  22801         soc_genreg,
  22802         1,
  22803         0,
  22804         0x22011d00,
  22805         0,
  22806         0,
  22807         16,
  22808         soc_L3_DEFIP_CAM_ENABLE_BCM56340_A0r_fields,
  22809         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  22810         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22811         -1,
  22812         -1,
  22813     },
  22814 #endif /* chips */
  22815 
  22816 #if defined(BCM_56370_A0)
  22817     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56370_A0r */
  22818         soc_block_list[5],
  22819         soc_genreg,
  22820         1,
  22821         0,
  22822         0x6b870000,
  22823         0,
  22824         0,
  22825         8,
  22826         soc_L3_DEFIP_CAM_ENABLE_BCM56960_A0r_fields,
  22827         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  22828         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  22829         -1,
  22830         -1,
  22831         3,
  22832     },
  22833 #endif /* chips */
  22834 
  22835 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  22836     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56440_A0r */
  22837         soc_block_list[5],
  22838         soc_genreg,
  22839         1,
  22840         0,
  22841         0xa080d07,
  22842         0,
  22843         0,
  22844         6,
  22845         soc_L3_DEFIP_CAM_ENABLEr_fields,
  22846         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  22847         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22848         -1,
  22849         -1,
  22850     },
  22851 #endif /* chips */
  22852 
  22853 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  22854     defined(BCM_56450_B1)
  22855     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56450_A0r */
  22856         soc_block_list[5],
  22857         soc_genreg,
  22858         1,
  22859         0,
  22860         0x2a010c00,
  22861         0,
  22862         0,
  22863         16,
  22864         soc_L3_DEFIP_CAM_ENABLE_BCM56450_A0r_fields,
  22865         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  22866         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22867         -1,
  22868         -1,
  22869     },
  22870 #endif /* chips */
  22871 
  22872 #if defined(BCM_56514_A0)
  22873     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56514_A0r */
  22874         soc_block_list[5],
  22875         soc_genreg,
  22876         1,
  22877         0,
  22878         0x808000a,
  22879         0,
  22880         0,
  22881         6,
  22882         soc_L3_DEFIP_CAM_ENABLEr_fields,
  22883         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  22884         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22885         -1,
  22886         -1,
  22887     },
  22888 #endif /* chips */
  22889 
  22890 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  22891     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56560_A0r */
  22892         soc_block_list[5],
  22893         soc_genreg,
  22894         1,
  22895         0,
  22896         0x3b8a0000,
  22897         0,
  22898         0,
  22899         8,
  22900         soc_L3_DEFIP_CAM_ENABLE_BCM56960_A0r_fields,
  22901         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  22902         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  22903         -1,
  22904         -1,
  22905     },
  22906 #endif /* chips */
  22907 
  22908 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  22909     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  22910     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56624_A0r */
  22911         soc_block_list[5],
  22912         soc_genreg,
  22913         1,
  22914         0,
  22915         0xa08014a,
  22916         0,
  22917         0,
  22918         8,
  22919         soc_L3_DEFIP_CAM_ENABLE_BCM56624_A0r_fields,
  22920         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  22921         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  22922         -1,
  22923         -1,
  22924     },
  22925 #endif /* chips */
  22926 
  22927 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  22928     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  22929     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  22930     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56634_A0r */
  22931         soc_block_list[5],
  22932         soc_genreg,
  22933         1,
  22934         0,
  22935         0x90801ab,
  22936         0,
  22937         0,
  22938         8,
  22939         soc_L3_DEFIP_CAM_ENABLE_BCM56624_A0r_fields,
  22940         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  22941         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  22942         -1,
  22943         -1,
  22944     },
  22945 #endif /* chips */
  22946 
  22947 #if defined(BCM_56640_A0)
  22948     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56640_A0r */
  22949         soc_block_list[5],
  22950         soc_genreg,
  22951         1,
  22952         0,
  22953         0x22010a00,
  22954         0,
  22955         0,
  22956         8,
  22957         soc_L3_DEFIP_CAM_ENABLE_BCM56640_A0r_fields,
  22958         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  22959         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  22960         -1,
  22961         -1,
  22962     },
  22963 #endif /* chips */
  22964 
  22965 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  22966     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56670_A0r */
  22967         soc_block_list[5],
  22968         soc_genreg,
  22969         1,
  22970         0,
  22971         0x3b890000,
  22972         0,
  22973         0,
  22974         8,
  22975         soc_L3_DEFIP_CAM_ENABLE_BCM56960_A0r_fields,
  22976         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  22977         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  22978         -1,
  22979         -1,
  22980     },
  22981 #endif /* chips */
  22982 
  22983 #if defined(BCM_56800_A0)
  22984     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56800_A0r */
  22985         soc_block_list[5],
  22986         soc_genreg,
  22987         1,
  22988         0,
  22989         0x8080c09,
  22990         0,
  22991         0,
  22992         1,
  22993         soc_L3_DEFIP_CAM_ENABLE_BCM56314_A0r_fields,
  22994         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  22995         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22996         -1,
  22997         -1,
  22998     },
  22999 #endif /* chips */
  23000 
  23001 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  23002     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56820_A0r */
  23003         soc_block_list[5],
  23004         soc_genreg,
  23005         1,
  23006         0,
  23007         0x8080c09,
  23008         0,
  23009         0,
  23010         6,
  23011         soc_L3_DEFIP_CAM_ENABLEr_fields,
  23012         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  23013         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  23014         -1,
  23015         -1,
  23016     },
  23017 #endif /* chips */
  23018 
  23019 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  23020     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56840_A0r */
  23021         soc_block_list[5],
  23022         soc_genreg,
  23023         1,
  23024         0,
  23025         0xa080d08,
  23026         0,
  23027         0,
  23028         9,
  23029         soc_L3_DEFIP_CAM_ENABLE_BCM56840_A0r_fields,
  23030         SOC_RESET_VAL_DEC(0x000003ff, 0x00000000)
  23031         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  23032         -1,
  23033         -1,
  23034     },
  23035 #endif /* chips */
  23036 
  23037 #if defined(BCM_56850_A0)
  23038     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56850_A0r */
  23039         soc_block_list[5],
  23040         soc_genreg,
  23041         1,
  23042         0,
  23043         0x2b8a0000,
  23044         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23045         0,
  23046         8,
  23047         soc_L3_DEFIP_CAM_ENABLE_BCM56640_A0r_fields,
  23048         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  23049         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  23050         -1,
  23051         -1,
  23052     },
  23053 #endif /* chips */
  23054 
  23055 #if defined(BCM_56860_A0)
  23056     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56860_A0r */
  23057         soc_block_list[5],
  23058         soc_genreg,
  23059         1,
  23060         0,
  23061         0x3b8a0000,
  23062         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23063         0,
  23064         8,
  23065         soc_L3_DEFIP_CAM_ENABLE_BCM56640_A0r_fields,
  23066         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  23067         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  23068         -1,
  23069         -1,
  23070     },
  23071 #endif /* chips */
  23072 
  23073 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  23074     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56870_A0r */
  23075         soc_block_list[5],
  23076         soc_genreg,
  23077         1,
  23078         0,
  23079         0x6b870000,
  23080         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23081         0,
  23082         8,
  23083         soc_L3_DEFIP_CAM_ENABLE_BCM56960_A0r_fields,
  23084         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  23085         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  23086         -1,
  23087         -1,
  23088         3,
  23089     },
  23090 #endif /* chips */
  23091 
  23092 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  23093     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56960_A0r */
  23094         soc_block_list[5],
  23095         soc_genreg,
  23096         1,
  23097         0,
  23098         0x3b890000,
  23099         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23100         0,
  23101         8,
  23102         soc_L3_DEFIP_CAM_ENABLE_BCM56960_A0r_fields,
  23103         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  23104         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  23105         -1,
  23106         -1,
  23107         3,
  23108     },
  23109 #endif /* chips */
  23110 
  23111 #if defined(BCM_56970_A0)
  23112     { /* SOC_REG_INT_L3_DEFIP_CAM_ENABLE_BCM56970_A0r */
  23113         soc_block_list[5],
  23114         soc_genreg,
  23115         1,
  23116         0,
  23117         0x5f870000,
  23118         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23119         0,
  23120         8,
  23121         soc_L3_DEFIP_CAM_ENABLE_BCM56960_A0r_fields,
  23122         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  23123         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  23124         -1,
  23125         -1,
  23126         3,
  23127     },
  23128 #endif /* chips */
  23129 
  23130 #if defined(BCM_56800_A0)
  23131     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRLr */
  23132         soc_block_list[5],
  23133         soc_genreg,
  23134         1,
  23135         0,
  23136         0x8080c0e,
  23137         0,
  23138         0,
  23139         1,
  23140         soc_CFAPMEMDEBUGr_fields,
  23141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23142         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23143         -1,
  23144         -1,
  23145     },
  23146 #endif /* chips */
  23147 
  23148 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  23149     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0r */
  23150         soc_block_list[5],
  23151         soc_genreg,
  23152         1,
  23153         0,
  23154         0xa080d09,
  23155         0,
  23156         0,
  23157         3,
  23158         soc_L3_DEFIP_DATA_DBGCTRL_0r_fields,
  23159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23161         -1,
  23162         -1,
  23163     },
  23164 #endif /* chips */
  23165 
  23166 #if defined(BCM_56840_A0)
  23167     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_1r */
  23168         soc_block_list[5],
  23169         soc_genreg,
  23170         1,
  23171         0,
  23172         0xa080d0a,
  23173         0,
  23174         0,
  23175         9,
  23176         soc_L3_DEFIP_DATA_DBGCTRL_1r_fields,
  23177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23178         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23179         -1,
  23180         -1,
  23181     },
  23182 #endif /* chips */
  23183 
  23184 #if defined(BCM_56340_A0)
  23185     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_2r */
  23186         soc_block_list[5],
  23187         soc_genreg,
  23188         1,
  23189         0,
  23190         0x22012000,
  23191         0,
  23192         0,
  23193         3,
  23194         soc_L3_DEFIP_DATA_DBGCTRL_2r_fields,
  23195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23196         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23197         -1,
  23198         -1,
  23199     },
  23200 #endif /* chips */
  23201 
  23202 #if defined(BCM_56340_A0)
  23203     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_3r */
  23204         soc_block_list[5],
  23205         soc_genreg,
  23206         1,
  23207         0,
  23208         0x22012100,
  23209         0,
  23210         0,
  23211         3,
  23212         soc_L3_DEFIP_DATA_DBGCTRL_3r_fields,
  23213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23214         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23215         -1,
  23216         -1,
  23217     },
  23218 #endif /* chips */
  23219 
  23220 #if defined(BCM_56340_A0)
  23221     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_4r */
  23222         soc_block_list[5],
  23223         soc_genreg,
  23224         1,
  23225         0,
  23226         0x22012200,
  23227         0,
  23228         0,
  23229         3,
  23230         soc_L3_DEFIP_DATA_DBGCTRL_4r_fields,
  23231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23233         -1,
  23234         -1,
  23235     },
  23236 #endif /* chips */
  23237 
  23238 #if defined(BCM_56340_A0)
  23239     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_5r */
  23240         soc_block_list[5],
  23241         soc_genreg,
  23242         1,
  23243         0,
  23244         0x22012300,
  23245         0,
  23246         0,
  23247         1,
  23248         soc_L3_DEFIP_DATA_DBGCTRL_5r_fields,
  23249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23250         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23251         -1,
  23252         -1,
  23253     },
  23254 #endif /* chips */
  23255 
  23256 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  23257     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56260_A0r */
  23258         soc_block_list[5],
  23259         soc_genreg,
  23260         1,
  23261         0,
  23262         0x2a010d00,
  23263         0,
  23264         0,
  23265         3,
  23266         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56260_A0r_fields,
  23267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23268         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23269         -1,
  23270         -1,
  23271     },
  23272 #endif /* chips */
  23273 
  23274 #if defined(BCM_56270_A0)
  23275     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56270_A0r */
  23276         soc_block_list[5],
  23277         soc_genreg,
  23278         1,
  23279         0,
  23280         0x2a010700,
  23281         0,
  23282         0,
  23283         1,
  23284         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56270_A0r_fields,
  23285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23286         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23287         -1,
  23288         -1,
  23289     },
  23290 #endif /* chips */
  23291 
  23292 #if defined(BCM_56340_A0)
  23293     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56340_A0r */
  23294         soc_block_list[5],
  23295         soc_genreg,
  23296         1,
  23297         0,
  23298         0x22011e00,
  23299         0,
  23300         0,
  23301         3,
  23302         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56640_A0r_fields,
  23303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23304         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23305         -1,
  23306         -1,
  23307     },
  23308 #endif /* chips */
  23309 
  23310 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  23311     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56440_A0r */
  23312         soc_block_list[5],
  23313         soc_genreg,
  23314         1,
  23315         0,
  23316         0xa080d08,
  23317         0,
  23318         0,
  23319         2,
  23320         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56440_A0r_fields,
  23321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23322         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23323         -1,
  23324         -1,
  23325     },
  23326 #endif /* chips */
  23327 
  23328 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23329     defined(BCM_56450_B1)
  23330     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56450_A0r */
  23331         soc_block_list[5],
  23332         soc_genreg,
  23333         1,
  23334         0,
  23335         0x2a010d00,
  23336         0,
  23337         0,
  23338         4,
  23339         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56450_A0r_fields,
  23340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23341         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23342         -1,
  23343         -1,
  23344     },
  23345 #endif /* chips */
  23346 
  23347 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  23348     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56560_A0r */
  23349         soc_block_list[5],
  23350         soc_genreg,
  23351         1,
  23352         0,
  23353         0x3b8b0000,
  23354         0,
  23355         0,
  23356         1,
  23357         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56560_A0r_fields,
  23358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23359         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23360         -1,
  23361         -1,
  23362     },
  23363 #endif /* chips */
  23364 
  23365 #if defined(BCM_56640_A0)
  23366     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56640_A0r */
  23367         soc_block_list[5],
  23368         soc_genreg,
  23369         1,
  23370         0,
  23371         0x22010b00,
  23372         0,
  23373         0,
  23374         3,
  23375         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56640_A0r_fields,
  23376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23378         -1,
  23379         -1,
  23380     },
  23381 #endif /* chips */
  23382 
  23383 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  23384     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56670_A0r */
  23385         soc_block_list[5],
  23386         soc_genreg,
  23387         1,
  23388         0,
  23389         0x3b8a0000,
  23390         0,
  23391         0,
  23392         1,
  23393         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56670_A0r_fields,
  23394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23395         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23396         -1,
  23397         -1,
  23398     },
  23399 #endif /* chips */
  23400 
  23401 #if defined(BCM_56850_A0)
  23402     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56850_A0r */
  23403         soc_block_list[5],
  23404         soc_genreg,
  23405         1,
  23406         0,
  23407         0x2b8b0000,
  23408         SOC_REG_FLAG_64_BITS |
  23409                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23410         0,
  23411         6,
  23412         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56850_A0r_fields,
  23413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23414         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23415         -1,
  23416         -1,
  23417     },
  23418 #endif /* chips */
  23419 
  23420 #if defined(BCM_56860_A0)
  23421     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56860_A0r */
  23422         soc_block_list[5],
  23423         soc_genreg,
  23424         1,
  23425         0,
  23426         0x3b8b0000,
  23427         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23428         0,
  23429         1,
  23430         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56860_A0r_fields,
  23431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23433         -1,
  23434         -1,
  23435     },
  23436 #endif /* chips */
  23437 
  23438 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  23439     defined(BCM_56870_A0)
  23440     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56870_A0r */
  23441         soc_block_list[5],
  23442         soc_genreg,
  23443         1,
  23444         0,
  23445         0x6b880000,
  23446         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23447         0,
  23448         2,
  23449         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23451         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23452         -1,
  23453         -1,
  23454         3,
  23455     },
  23456 #endif /* chips */
  23457 
  23458 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  23459     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r */
  23460         soc_block_list[5],
  23461         soc_genreg,
  23462         1,
  23463         0,
  23464         0x3b8a0000,
  23465         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23466         0,
  23467         2,
  23468         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23470         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23471         -1,
  23472         -1,
  23473         3,
  23474     },
  23475 #endif /* chips */
  23476 
  23477 #if defined(BCM_56970_A0)
  23478     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_BCM56970_A0r */
  23479         soc_block_list[5],
  23480         soc_genreg,
  23481         1,
  23482         0,
  23483         0x5f880000,
  23484         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23485         0,
  23486         2,
  23487         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23490         -1,
  23491         -1,
  23492         3,
  23493     },
  23494 #endif /* chips */
  23495 
  23496 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  23497     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE0r */
  23498         soc_block_list[5],
  23499         soc_genreg,
  23500         1,
  23501         0,
  23502         0x3b8a0000,
  23503         0,
  23504         0,
  23505         2,
  23506         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23508         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23509         -1,
  23510         -1,
  23511         3,
  23512     },
  23513 #endif /* chips */
  23514 
  23515 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  23516     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE1r */
  23517         soc_block_list[5],
  23518         soc_genreg,
  23519         1,
  23520         0,
  23521         0x3b8a0000,
  23522         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23523         0,
  23524         2,
  23525         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23527         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23528         -1,
  23529         -1,
  23530         3,
  23531     },
  23532 #endif /* chips */
  23533 
  23534 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  23535     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE2r */
  23536         soc_block_list[5],
  23537         soc_genreg,
  23538         1,
  23539         0,
  23540         0x3b8a0000,
  23541         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23542         0,
  23543         2,
  23544         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23546         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23547         -1,
  23548         -1,
  23549         3,
  23550     },
  23551 #endif /* chips */
  23552 
  23553 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  23554     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE3r */
  23555         soc_block_list[5],
  23556         soc_genreg,
  23557         1,
  23558         0,
  23559         0x3b8a0000,
  23560         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23561         0,
  23562         2,
  23563         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23565         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23566         -1,
  23567         -1,
  23568         3,
  23569     },
  23570 #endif /* chips */
  23571 
  23572 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  23573     defined(BCM_56870_A0)
  23574     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE0_BCM56870_A0r */
  23575         soc_block_list[5],
  23576         soc_genreg,
  23577         1,
  23578         0,
  23579         0x6b880000,
  23580         0,
  23581         0,
  23582         2,
  23583         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23585         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23586         -1,
  23587         -1,
  23588         3,
  23589     },
  23590 #endif /* chips */
  23591 
  23592 #if defined(BCM_56970_A0)
  23593     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE0_BCM56970_A0r */
  23594         soc_block_list[5],
  23595         soc_genreg,
  23596         1,
  23597         0,
  23598         0x5f880000,
  23599         0,
  23600         0,
  23601         2,
  23602         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23604         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23605         -1,
  23606         -1,
  23607         3,
  23608     },
  23609 #endif /* chips */
  23610 
  23611 #if defined(BCM_56870_A0)
  23612     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE1_BCM56870_A0r */
  23613         soc_block_list[5],
  23614         soc_genreg,
  23615         1,
  23616         0,
  23617         0x6b880000,
  23618         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23619         0,
  23620         2,
  23621         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23623         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23624         -1,
  23625         -1,
  23626         3,
  23627     },
  23628 #endif /* chips */
  23629 
  23630 #if defined(BCM_56970_A0)
  23631     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE1_BCM56970_A0r */
  23632         soc_block_list[5],
  23633         soc_genreg,
  23634         1,
  23635         0,
  23636         0x5f880000,
  23637         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23638         0,
  23639         2,
  23640         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23642         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23643         -1,
  23644         -1,
  23645         3,
  23646     },
  23647 #endif /* chips */
  23648 
  23649 #if defined(BCM_56970_A0)
  23650     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE2_BCM56970_A0r */
  23651         soc_block_list[5],
  23652         soc_genreg,
  23653         1,
  23654         0,
  23655         0x5f880000,
  23656         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23657         0,
  23658         2,
  23659         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23661         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23662         -1,
  23663         -1,
  23664         3,
  23665     },
  23666 #endif /* chips */
  23667 
  23668 #if defined(BCM_56970_A0)
  23669     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_0_PIPE3_BCM56970_A0r */
  23670         soc_block_list[5],
  23671         soc_genreg,
  23672         1,
  23673         0,
  23674         0x5f880000,
  23675         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23676         0,
  23677         2,
  23678         soc_L3_DEFIP_DATA_DBGCTRL_0_BCM56960_A0r_fields,
  23679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23680         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23681         -1,
  23682         -1,
  23683         3,
  23684     },
  23685 #endif /* chips */
  23686 
  23687 #if defined(BCM_56340_A0)
  23688     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_1_BCM56340_A0r */
  23689         soc_block_list[5],
  23690         soc_genreg,
  23691         1,
  23692         0,
  23693         0x22011f00,
  23694         0,
  23695         0,
  23696         3,
  23697         soc_L3_DEFIP_DATA_DBGCTRL_1_BCM56340_A0r_fields,
  23698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23700         -1,
  23701         -1,
  23702     },
  23703 #endif /* chips */
  23704 
  23705 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  23706     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_1_BCM56440_A0r */
  23707         soc_block_list[5],
  23708         soc_genreg,
  23709         1,
  23710         0,
  23711         0xa080d09,
  23712         0,
  23713         0,
  23714         1,
  23715         soc_L3_DEFIP_DATA_DBGCTRL_1_BCM56440_A0r_fields,
  23716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23718         -1,
  23719         -1,
  23720     },
  23721 #endif /* chips */
  23722 
  23723 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  23724     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_1_BCM56560_A0r */
  23725         soc_block_list[5],
  23726         soc_genreg,
  23727         1,
  23728         0,
  23729         0x3b8c0000,
  23730         0,
  23731         0,
  23732         4,
  23733         soc_L3_DEFIP_DATA_DBGCTRL_1_BCM56560_A0r_fields,
  23734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23736         -1,
  23737         -1,
  23738     },
  23739 #endif /* chips */
  23740 
  23741 #if defined(BCM_56640_A0)
  23742     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_1_BCM56640_A0r */
  23743         soc_block_list[5],
  23744         soc_genreg,
  23745         1,
  23746         0,
  23747         0x22010c00,
  23748         0,
  23749         0,
  23750         9,
  23751         soc_L3_DEFIP_DATA_DBGCTRL_1_BCM56640_A0r_fields,
  23752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23754         -1,
  23755         -1,
  23756     },
  23757 #endif /* chips */
  23758 
  23759 #if defined(BCM_56840_B0)
  23760     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_1_BCM56840_B0r */
  23761         soc_block_list[5],
  23762         soc_genreg,
  23763         1,
  23764         0,
  23765         0xa080d0a,
  23766         0,
  23767         0,
  23768         11,
  23769         soc_L3_DEFIP_DATA_DBGCTRL_1_BCM56840_B0r_fields,
  23770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23772         -1,
  23773         -1,
  23774     },
  23775 #endif /* chips */
  23776 
  23777 #if defined(BCM_56850_A0)
  23778     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_1_BCM56850_A0r */
  23779         soc_block_list[5],
  23780         soc_genreg,
  23781         1,
  23782         0,
  23783         0x2b8c0000,
  23784         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23785         0,
  23786         4,
  23787         soc_L3_DEFIP_DATA_DBGCTRL_1_BCM56850_A0r_fields,
  23788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23790         -1,
  23791         -1,
  23792     },
  23793 #endif /* chips */
  23794 
  23795 #if defined(BCM_56860_A0)
  23796     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_1_BCM56860_A0r */
  23797         soc_block_list[5],
  23798         soc_genreg,
  23799         1,
  23800         0,
  23801         0x3b8c0000,
  23802         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23803         0,
  23804         4,
  23805         soc_L3_DEFIP_DATA_DBGCTRL_1_BCM56850_A0r_fields,
  23806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23808         -1,
  23809         -1,
  23810     },
  23811 #endif /* chips */
  23812 
  23813 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23814     defined(BCM_56160_A0)
  23815     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_BCM53400_A0r */
  23816         soc_block_list[5],
  23817         soc_genreg,
  23818         1,
  23819         0,
  23820         0x26011d00,
  23821         0,
  23822         0,
  23823         1,
  23824         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
  23825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23826         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23827         -1,
  23828         -1,
  23829     },
  23830 #endif /* chips */
  23831 
  23832 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  23833     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_BCM53570_A0r */
  23834         soc_block_list[5],
  23835         soc_genreg,
  23836         1,
  23837         0,
  23838         0x26011d00,
  23839         0,
  23840         0,
  23841         1,
  23842         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56260_A0r_fields,
  23843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23844         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23845         -1,
  23846         -1,
  23847     },
  23848 #endif /* chips */
  23849 
  23850 #if defined(BCM_56142_A0)
  23851     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_BCM56142_A0r */
  23852         soc_block_list[5],
  23853         soc_genreg,
  23854         1,
  23855         0,
  23856         0xa080159,
  23857         0,
  23858         0,
  23859         1,
  23860         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
  23861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23862         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23863         -1,
  23864         -1,
  23865     },
  23866 #endif /* chips */
  23867 
  23868 #if defined(BCM_56150_A0)
  23869     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_BCM56150_A0r */
  23870         soc_block_list[5],
  23871         soc_genreg,
  23872         1,
  23873         0,
  23874         0x2a011000,
  23875         0,
  23876         0,
  23877         1,
  23878         soc_FT_CNTR_RAM_CONTROLr_fields,
  23879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23880         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23881         -1,
  23882         -1,
  23883     },
  23884 #endif /* chips */
  23885 
  23886 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  23887     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_BCM56334_A0r */
  23888         soc_block_list[5],
  23889         soc_genreg,
  23890         1,
  23891         0,
  23892         0xa080175,
  23893         0,
  23894         0,
  23895         1,
  23896         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
  23897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23899         -1,
  23900         -1,
  23901     },
  23902 #endif /* chips */
  23903 
  23904 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  23905     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  23906     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_BCM56624_A0r */
  23907         soc_block_list[5],
  23908         soc_genreg,
  23909         1,
  23910         0,
  23911         0xa080150,
  23912         0,
  23913         0,
  23914         1,
  23915         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
  23916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23918         -1,
  23919         -1,
  23920     },
  23921 #endif /* chips */
  23922 
  23923 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  23924     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  23925     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  23926     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_BCM56634_A0r */
  23927         soc_block_list[5],
  23928         soc_genreg,
  23929         1,
  23930         0,
  23931         0x90801b3,
  23932         0,
  23933         0,
  23934         1,
  23935         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
  23936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23938         -1,
  23939         -1,
  23940     },
  23941 #endif /* chips */
  23942 
  23943 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  23944     { /* SOC_REG_INT_L3_DEFIP_DATA_DBGCTRL_BCM56820_A0r */
  23945         soc_block_list[5],
  23946         soc_genreg,
  23947         1,
  23948         0,
  23949         0x8080c0e,
  23950         0,
  23951         0,
  23952         2,
  23953         soc_L3_DEFIP_128_DATA_DBGCTRLr_fields,
  23954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23956         -1,
  23957         -1,
  23958     },
  23959 #endif /* chips */
  23960 
  23961 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  23962     { /* SOC_REG_INT_L3_DEFIP_DATA_ECC_CONTROLr */
  23963         soc_block_list[5],
  23964         soc_genreg,
  23965         1,
  23966         0,
  23967         0x2a010f00,
  23968         0,
  23969         0,
  23970         2,
  23971         soc_EGR_MASK_ECC_CONTROLr_fields,
  23972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23973         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23974         -1,
  23975         -1,
  23976     },
  23977 #endif /* chips */
  23978 
  23979 #if defined(BCM_56270_A0)
  23980     { /* SOC_REG_INT_L3_DEFIP_DATA_ECC_CONTROL_BCM56270_A0r */
  23981         soc_block_list[5],
  23982         soc_genreg,
  23983         1,
  23984         0,
  23985         0x2a010900,
  23986         0,
  23987         0,
  23988         2,
  23989         soc_EGR_MASK_ECC_CONTROLr_fields,
  23990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23992         -1,
  23993         -1,
  23994     },
  23995 #endif /* chips */
  23996 
  23997 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  23998     { /* SOC_REG_INT_L3_DEFIP_DATA_ECC_STATUS_INTRr */
  23999         soc_block_list[5],
  24000         soc_genreg,
  24001         1,
  24002         0,
  24003         0x2a011000,
  24004         0,
  24005         0,
  24006         4,
  24007         soc_L3_DEFIP_DATA_ECC_STATUS_INTRr_fields,
  24008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24010         -1,
  24011         -1,
  24012     },
  24013 #endif /* chips */
  24014 
  24015 #if defined(BCM_56270_A0)
  24016     { /* SOC_REG_INT_L3_DEFIP_DATA_ECC_STATUS_INTR_BCM56270_A0r */
  24017         soc_block_list[5],
  24018         soc_genreg,
  24019         1,
  24020         0,
  24021         0x2a010a00,
  24022         0,
  24023         0,
  24024         4,
  24025         soc_L3_DEFIP_DATA_ECC_STATUS_INTR_BCM56270_A0r_fields,
  24026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24027         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24028         -1,
  24029         -1,
  24030     },
  24031 #endif /* chips */
  24032 
  24033 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  24034     { /* SOC_REG_INT_L3_DEFIP_DATA_ECC_STATUS_NACKr */
  24035         soc_block_list[5],
  24036         soc_genreg,
  24037         1,
  24038         0,
  24039         0x2a011100,
  24040         0,
  24041         0,
  24042         4,
  24043         soc_L3_DEFIP_DATA_ECC_STATUS_INTRr_fields,
  24044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24046         -1,
  24047         -1,
  24048     },
  24049 #endif /* chips */
  24050 
  24051 #if defined(BCM_56270_A0)
  24052     { /* SOC_REG_INT_L3_DEFIP_DATA_ECC_STATUS_NACK_BCM56270_A0r */
  24053         soc_block_list[5],
  24054         soc_genreg,
  24055         1,
  24056         0,
  24057         0x2a010b00,
  24058         0,
  24059         0,
  24060         4,
  24061         soc_L3_DEFIP_DATA_ECC_STATUS_INTR_BCM56270_A0r_fields,
  24062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24064         -1,
  24065         -1,
  24066     },
  24067 #endif /* chips */
  24068 
  24069 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  24070     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  24071     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  24072     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_CONTROLr */
  24073         soc_block_list[5],
  24074         soc_genreg,
  24075         1,
  24076         0,
  24077         0x90801bc,
  24078         0,
  24079         0,
  24080         1,
  24081         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  24082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24083         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24084         -1,
  24085         -1,
  24086     },
  24087 #endif /* chips */
  24088 
  24089 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  24090     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_CONTROL_BCM56440_A0r */
  24091         soc_block_list[5],
  24092         soc_genreg,
  24093         1,
  24094         0,
  24095         0xa080d11,
  24096         0,
  24097         0,
  24098         1,
  24099         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  24100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24101         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24102         -1,
  24103         -1,
  24104     },
  24105 #endif /* chips */
  24106 
  24107 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24108     defined(BCM_56450_B1)
  24109     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_CONTROL_BCM56450_A0r */
  24110         soc_block_list[5],
  24111         soc_genreg,
  24112         1,
  24113         0,
  24114         0x2a010f00,
  24115         0,
  24116         0,
  24117         1,
  24118         soc_FT_CNTR_SER_CONTROLr_fields,
  24119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24120         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24121         -1,
  24122         -1,
  24123     },
  24124 #endif /* chips */
  24125 
  24126 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  24127     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_CONTROL_BCM56840_A0r */
  24128         soc_block_list[5],
  24129         soc_genreg,
  24130         1,
  24131         0,
  24132         0xa080d12,
  24133         0,
  24134         0,
  24135         1,
  24136         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  24137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24138         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24139         -1,
  24140         -1,
  24141     },
  24142 #endif /* chips */
  24143 
  24144 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  24145     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  24146     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  24147     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_STATUS_INTRr */
  24148         soc_block_list[5],
  24149         soc_genreg,
  24150         1,
  24151         0,
  24152         0x90801bd,
  24153         0,
  24154         0,
  24155         3,
  24156         soc_EGR_MASK_PARITY_STATUSr_fields,
  24157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24158         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  24159         -1,
  24160         -1,
  24161     },
  24162 #endif /* chips */
  24163 
  24164 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  24165     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_STATUS_INTR_BCM56440_A0r */
  24166         soc_block_list[5],
  24167         soc_genreg,
  24168         1,
  24169         0,
  24170         0xa080d12,
  24171         0,
  24172         0,
  24173         3,
  24174         soc_L3_IIF_PARITY_STATUS_NACKr_fields,
  24175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24176         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24177         -1,
  24178         -1,
  24179     },
  24180 #endif /* chips */
  24181 
  24182 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24183     defined(BCM_56450_B1)
  24184     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_STATUS_INTR_BCM56450_A0r */
  24185         soc_block_list[5],
  24186         soc_genreg,
  24187         1,
  24188         0,
  24189         0x2a011000,
  24190         0,
  24191         0,
  24192         3,
  24193         soc_EGR_DSCP_TABLE_PARITY_STATUS_INTRr_fields,
  24194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24195         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24196         -1,
  24197         -1,
  24198     },
  24199 #endif /* chips */
  24200 
  24201 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  24202     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  24203     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_STATUS_INTR_BCM56840_A0r */
  24204         soc_block_list[5],
  24205         soc_genreg,
  24206         1,
  24207         0,
  24208         0xa080d13,
  24209         0,
  24210         0,
  24211         3,
  24212         soc_L3_IIF_PARITY_STATUS_NACKr_fields,
  24213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24214         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24215         -1,
  24216         -1,
  24217     },
  24218 #endif /* chips */
  24219 
  24220 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  24221     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  24222     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  24223     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_STATUS_NACKr */
  24224         soc_block_list[5],
  24225         soc_genreg,
  24226         1,
  24227         0,
  24228         0x90801be,
  24229         0,
  24230         0,
  24231         3,
  24232         soc_EGR_MASK_PARITY_STATUSr_fields,
  24233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24234         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  24235         -1,
  24236         -1,
  24237     },
  24238 #endif /* chips */
  24239 
  24240 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24241     defined(BCM_56450_B1)
  24242     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_STATUS_NACK_BCM56450_A0r */
  24243         soc_block_list[5],
  24244         soc_genreg,
  24245         1,
  24246         0,
  24247         0x2a011100,
  24248         0,
  24249         0,
  24250         3,
  24251         soc_EGR_DSCP_TABLE_PARITY_STATUS_INTRr_fields,
  24252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24253         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24254         -1,
  24255         -1,
  24256     },
  24257 #endif /* chips */
  24258 
  24259 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  24260     { /* SOC_REG_INT_L3_DEFIP_DATA_PARITY_STATUS_NACK_BCM56840_A0r */
  24261         soc_block_list[5],
  24262         soc_genreg,
  24263         1,
  24264         0,
  24265         0xa080d14,
  24266         0,
  24267         0,
  24268         3,
  24269         soc_L3_IIF_PARITY_STATUS_NACKr_fields,
  24270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24272         -1,
  24273         -1,
  24274     },
  24275 #endif /* chips */
  24276 
  24277 #if defined(BCM_56640_A0)
  24278     { /* SOC_REG_INT_L3_DEFIP_DATA_PDA_CONTROL_0r */
  24279         soc_block_list[5],
  24280         soc_genreg,
  24281         1,
  24282         0,
  24283         0x22010f00,
  24284         0,
  24285         0,
  24286         2,
  24287         soc_L3_DEFIP_DATA_PDA_CONTROL_0r_fields,
  24288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24289         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24290         -1,
  24291         -1,
  24292     },
  24293 #endif /* chips */
  24294 
  24295 #if defined(BCM_56640_A0)
  24296     { /* SOC_REG_INT_L3_DEFIP_DATA_PDA_CONTROL_1r */
  24297         soc_block_list[5],
  24298         soc_genreg,
  24299         1,
  24300         0,
  24301         0x22011000,
  24302         0,
  24303         0,
  24304         2,
  24305         soc_L3_DEFIP_DATA_PDA_CONTROL_1r_fields,
  24306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24308         -1,
  24309         -1,
  24310     },
  24311 #endif /* chips */
  24312 
  24313 #if defined(BCM_56340_A0)
  24314     { /* SOC_REG_INT_L3_DEFIP_DATA_PDA_CONTROL_2r */
  24315         soc_block_list[5],
  24316         soc_genreg,
  24317         1,
  24318         0,
  24319         0x22012800,
  24320         0,
  24321         0,
  24322         4,
  24323         soc_L3_DEFIP_DATA_PDA_CONTROL_2r_fields,
  24324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24326         -1,
  24327         -1,
  24328     },
  24329 #endif /* chips */
  24330 
  24331 #if defined(BCM_56340_A0)
  24332     { /* SOC_REG_INT_L3_DEFIP_DATA_PDA_CONTROL_3r */
  24333         soc_block_list[5],
  24334         soc_genreg,
  24335         1,
  24336         0,
  24337         0x22012900,
  24338         0,
  24339         0,
  24340         4,
  24341         soc_L3_DEFIP_DATA_PDA_CONTROL_3r_fields,
  24342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24343         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24344         -1,
  24345         -1,
  24346     },
  24347 #endif /* chips */
  24348 
  24349 #if defined(BCM_56340_A0)
  24350     { /* SOC_REG_INT_L3_DEFIP_DATA_PDA_CONTROL_0_BCM56340_A0r */
  24351         soc_block_list[5],
  24352         soc_genreg,
  24353         1,
  24354         0,
  24355         0x22012600,
  24356         0,
  24357         0,
  24358         4,
  24359         soc_VFI_PDA_CONTROLr_fields,
  24360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24361         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24362         -1,
  24363         -1,
  24364     },
  24365 #endif /* chips */
  24366 
  24367 #if defined(BCM_56850_A0)
  24368     { /* SOC_REG_INT_L3_DEFIP_DATA_PDA_CONTROL_0_BCM56850_A0r */
  24369         soc_block_list[5],
  24370         soc_genreg,
  24371         1,
  24372         0,
  24373         0x2b8e0000,
  24374         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24375         0,
  24376         4,
  24377         soc_L3_DEFIP_DATA_PDA_CONTROL_0_BCM56850_A0r_fields,
  24378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24379         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24380         -1,
  24381         -1,
  24382     },
  24383 #endif /* chips */
  24384 
  24385 #if defined(BCM_56340_A0)
  24386     { /* SOC_REG_INT_L3_DEFIP_DATA_PDA_CONTROL_1_BCM56340_A0r */
  24387         soc_block_list[5],
  24388         soc_genreg,
  24389         1,
  24390         0,
  24391         0x22012700,
  24392         0,
  24393         0,
  24394         4,
  24395         soc_L3_DEFIP_DATA_PDA_CONTROL_1_BCM56340_A0r_fields,
  24396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24397         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24398         -1,
  24399         -1,
  24400     },
  24401 #endif /* chips */
  24402 
  24403 #if defined(BCM_56850_A0)
  24404     { /* SOC_REG_INT_L3_DEFIP_DATA_PDA_CONTROL_1_BCM56850_A0r */
  24405         soc_block_list[5],
  24406         soc_genreg,
  24407         1,
  24408         0,
  24409         0x2b8f0000,
  24410         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24411         0,
  24412         4,
  24413         soc_L3_DEFIP_DATA_PDA_CONTROL_1_BCM56850_A0r_fields,
  24414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24415         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24416         -1,
  24417         -1,
  24418     },
  24419 #endif /* chips */
  24420 
  24421 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  24422     { /* SOC_REG_INT_L3_DEFIP_KEY_SELr */
  24423         soc_block_list[5],
  24424         soc_genreg,
  24425         1,
  24426         0,
  24427         0xa080602,
  24428         0,
  24429         0,
  24430         9,
  24431         soc_L3_DEFIP_KEY_SELr_fields,
  24432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24433         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  24434         -1,
  24435         -1,
  24436     },
  24437 #endif /* chips */
  24438 
  24439 #if defined(BCM_56340_A0)
  24440     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_0r */
  24441         soc_block_list[5],
  24442         soc_genreg,
  24443         1,
  24444         0,
  24445         0x22000200,
  24446         0,
  24447         0,
  24448         16,
  24449         soc_L3_DEFIP_KEY_SEL_0r_fields,
  24450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24451         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24452         -1,
  24453         -1,
  24454     },
  24455 #endif /* chips */
  24456 
  24457 #if defined(BCM_56340_A0)
  24458     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_1r */
  24459         soc_block_list[5],
  24460         soc_genreg,
  24461         1,
  24462         0,
  24463         0x22000300,
  24464         0,
  24465         0,
  24466         32,
  24467         soc_L3_DEFIP_KEY_SEL_1r_fields,
  24468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24469         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24470         -1,
  24471         -1,
  24472     },
  24473 #endif /* chips */
  24474 
  24475 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  24476     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56260_A0r */
  24477         soc_block_list[5],
  24478         soc_genreg,
  24479         1,
  24480         0,
  24481         0x2a000100,
  24482         0,
  24483         0,
  24484         3,
  24485         soc_L3_DEFIP_KEY_SEL_BCM56260_A0r_fields,
  24486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24487         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  24488         -1,
  24489         -1,
  24490     },
  24491 #endif /* chips */
  24492 
  24493 #if defined(BCM_56270_A0)
  24494     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56270_A0r */
  24495         soc_block_list[5],
  24496         soc_genreg,
  24497         1,
  24498         0,
  24499         0x2a000100,
  24500         0,
  24501         0,
  24502         2,
  24503         soc_L3_DEFIP_KEY_SEL_BCM56270_A0r_fields,
  24504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24505         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  24506         -1,
  24507         -1,
  24508     },
  24509 #endif /* chips */
  24510 
  24511 #if defined(BCM_56370_A0)
  24512     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56370_A0r */
  24513         soc_block_list[5],
  24514         soc_genreg,
  24515         1,
  24516         0,
  24517         0x6b8d0000,
  24518         0,
  24519         0,
  24520         5,
  24521         soc_L3_DEFIP_KEY_SEL_BCM56870_A0r_fields,
  24522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24523         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  24524         -1,
  24525         -1,
  24526         3,
  24527     },
  24528 #endif /* chips */
  24529 
  24530 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24531     defined(BCM_56450_B1)
  24532     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56450_A0r */
  24533         soc_block_list[5],
  24534         soc_genreg,
  24535         1,
  24536         0,
  24537         0x2a000100,
  24538         0,
  24539         0,
  24540         8,
  24541         soc_L3_DEFIP_KEY_SEL_BCM56450_A0r_fields,
  24542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24543         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24544         -1,
  24545         -1,
  24546     },
  24547 #endif /* chips */
  24548 
  24549 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  24550     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  24551     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56560_A0r */
  24552         soc_block_list[5],
  24553         soc_genreg,
  24554         1,
  24555         0,
  24556         0x3a000200,
  24557         0,
  24558         0,
  24559         9,
  24560         soc_L3_DEFIP_KEY_SEL_BCM56960_A0r_fields,
  24561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24562         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  24563         -1,
  24564         -1,
  24565     },
  24566 #endif /* chips */
  24567 
  24568 #if defined(BCM_56640_A0)
  24569     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56640_A0r */
  24570         soc_block_list[5],
  24571         soc_genreg,
  24572         1,
  24573         0,
  24574         0x22000200,
  24575         0,
  24576         0,
  24577         10,
  24578         soc_L3_DEFIP_KEY_SEL_BCM56640_A0r_fields,
  24579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24580         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  24581         -1,
  24582         -1,
  24583     },
  24584 #endif /* chips */
  24585 
  24586 #if defined(BCM_56850_A0)
  24587     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56850_A0r */
  24588         soc_block_list[5],
  24589         soc_genreg,
  24590         1,
  24591         0,
  24592         0x2a000200,
  24593         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24594         0,
  24595         9,
  24596         soc_L3_DEFIP_KEY_SEL_BCM56850_A0r_fields,
  24597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24598         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  24599         -1,
  24600         -1,
  24601     },
  24602 #endif /* chips */
  24603 
  24604 #if defined(BCM_56860_A0)
  24605     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56860_A0r */
  24606         soc_block_list[5],
  24607         soc_genreg,
  24608         1,
  24609         0,
  24610         0x3a000200,
  24611         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24612         0,
  24613         9,
  24614         soc_L3_DEFIP_KEY_SEL_BCM56850_A0r_fields,
  24615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24616         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  24617         -1,
  24618         -1,
  24619     },
  24620 #endif /* chips */
  24621 
  24622 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  24623     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56870_A0r */
  24624         soc_block_list[5],
  24625         soc_genreg,
  24626         1,
  24627         0,
  24628         0x6b8d0000,
  24629         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24630         0,
  24631         5,
  24632         soc_L3_DEFIP_KEY_SEL_BCM56870_A0r_fields,
  24633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24634         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  24635         -1,
  24636         -1,
  24637         3,
  24638     },
  24639 #endif /* chips */
  24640 
  24641 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  24642     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56960_A0r */
  24643         soc_block_list[5],
  24644         soc_genreg,
  24645         1,
  24646         0,
  24647         0x3b8e0000,
  24648         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24649         0,
  24650         9,
  24651         soc_L3_DEFIP_KEY_SEL_BCM56960_A0r_fields,
  24652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24653         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  24654         -1,
  24655         -1,
  24656         3,
  24657     },
  24658 #endif /* chips */
  24659 
  24660 #if defined(BCM_56970_A0)
  24661     { /* SOC_REG_INT_L3_DEFIP_KEY_SEL_BCM56970_A0r */
  24662         soc_block_list[5],
  24663         soc_genreg,
  24664         1,
  24665         0,
  24666         0x5f8c0000,
  24667         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24668         0,
  24669         12,
  24670         soc_L3_DEFIP_KEY_SEL_BCM56970_A0r_fields,
  24671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24672         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  24673         -1,
  24674         -1,
  24675         3,
  24676     },
  24677 #endif /* chips */
  24678 
  24679 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  24680     defined(BCM_56870_A0)
  24681     { /* SOC_REG_INT_L3_DEFIP_ONLY_CAM_BIST_CONFIG_64r */
  24682         soc_block_list[5],
  24683         soc_genreg,
  24684         1,
  24685         0,
  24686         0x6b860000,
  24687         SOC_REG_FLAG_64_BITS |
  24688                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24689         0,
  24690         6,
  24691         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  24692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24693         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24694         -1,
  24695         -1,
  24696         3,
  24697     },
  24698 #endif /* chips */
  24699 
  24700 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  24701     defined(BCM_56870_A0)
  24702     { /* SOC_REG_INT_L3_DEFIP_ONLY_CAM_BIST_CONFIG_64_PIPE0r */
  24703         soc_block_list[5],
  24704         soc_genreg,
  24705         1,
  24706         0,
  24707         0x6b860000,
  24708         SOC_REG_FLAG_64_BITS,
  24709         0,
  24710         6,
  24711         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  24712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24713         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24714         -1,
  24715         -1,
  24716         3,
  24717     },
  24718 #endif /* chips */
  24719 
  24720 #if defined(BCM_56870_A0)
  24721     { /* SOC_REG_INT_L3_DEFIP_ONLY_CAM_BIST_CONFIG_64_PIPE1r */
  24722         soc_block_list[5],
  24723         soc_genreg,
  24724         1,
  24725         0,
  24726         0x6b860000,
  24727         SOC_REG_FLAG_64_BITS |
  24728                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24729         0,
  24730         6,
  24731         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  24732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24734         -1,
  24735         -1,
  24736         3,
  24737     },
  24738 #endif /* chips */
  24739 
  24740 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  24741     defined(BCM_56870_A0)
  24742     { /* SOC_REG_INT_L3_DEFIP_ONLY_CAM_BIST_STATUSr */
  24743         soc_block_list[5],
  24744         soc_genreg,
  24745         1,
  24746         0,
  24747         0x6b850000,
  24748         SOC_REG_FLAG_RO |
  24749                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24750         0,
  24751         1,
  24752         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  24753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24754         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24755         -1,
  24756         -1,
  24757         3,
  24758     },
  24759 #endif /* chips */
  24760 
  24761 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  24762     defined(BCM_56870_A0)
  24763     { /* SOC_REG_INT_L3_DEFIP_ONLY_CAM_BIST_STATUS_PIPE0r */
  24764         soc_block_list[5],
  24765         soc_genreg,
  24766         1,
  24767         0,
  24768         0x6b850000,
  24769         SOC_REG_FLAG_RO,
  24770         0,
  24771         1,
  24772         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  24773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24774         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24775         -1,
  24776         -1,
  24777         3,
  24778     },
  24779 #endif /* chips */
  24780 
  24781 #if defined(BCM_56870_A0)
  24782     { /* SOC_REG_INT_L3_DEFIP_ONLY_CAM_BIST_STATUS_PIPE1r */
  24783         soc_block_list[5],
  24784         soc_genreg,
  24785         1,
  24786         0,
  24787         0x6b850000,
  24788         SOC_REG_FLAG_RO |
  24789                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24790         0,
  24791         1,
  24792         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  24793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24794         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24795         -1,
  24796         -1,
  24797         3,
  24798     },
  24799 #endif /* chips */
  24800 
  24801 #if defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  24802     defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  24803     defined(BCM_56514_A0)
  24804     { /* SOC_REG_INT_L3_DEFIP_PARITY_CONTROLr */
  24805         soc_block_list[5],
  24806         soc_genreg,
  24807         1,
  24808         0,
  24809         0xa080000,
  24810         0,
  24811         0,
  24812         2,
  24813         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  24814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24815         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  24816         -1,
  24817         -1,
  24818     },
  24819 #endif /* chips */
  24820 
  24821 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24822     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24823     defined(BCM_56160_A0)
  24824     { /* SOC_REG_INT_L3_DEFIP_PARITY_CONTROL_BCM53400_A0r */
  24825         soc_block_list[5],
  24826         soc_genreg,
  24827         1,
  24828         0,
  24829         0x2a010000,
  24830         0,
  24831         0,
  24832         1,
  24833         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  24834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24835         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24836         -1,
  24837         -1,
  24838     },
  24839 #endif /* chips */
  24840 
  24841 #if defined(BCM_56142_A0)
  24842     { /* SOC_REG_INT_L3_DEFIP_PARITY_CONTROL_BCM56142_A0r */
  24843         soc_block_list[5],
  24844         soc_genreg,
  24845         1,
  24846         0,
  24847         0xc08015b,
  24848         0,
  24849         0,
  24850         1,
  24851         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  24852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24853         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24854         -1,
  24855         -1,
  24856     },
  24857 #endif /* chips */
  24858 
  24859 #if defined(BCM_56150_A0)
  24860     { /* SOC_REG_INT_L3_DEFIP_PARITY_CONTROL_BCM56150_A0r */
  24861         soc_block_list[5],
  24862         soc_genreg,
  24863         1,
  24864         0,
  24865         0x32010000,
  24866         0,
  24867         0,
  24868         1,
  24869         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  24870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24871         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24872         -1,
  24873         -1,
  24874     },
  24875 #endif /* chips */
  24876 
  24877 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  24878     { /* SOC_REG_INT_L3_DEFIP_PARITY_CONTROL_BCM56334_A0r */
  24879         soc_block_list[5],
  24880         soc_genreg,
  24881         1,
  24882         0,
  24883         0xc08017e,
  24884         0,
  24885         0,
  24886         1,
  24887         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  24888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24889         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24890         -1,
  24891         -1,
  24892     },
  24893 #endif /* chips */
  24894 
  24895 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  24896     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  24897     { /* SOC_REG_INT_L3_DEFIP_PARITY_CONTROL_BCM56624_A0r */
  24898         soc_block_list[5],
  24899         soc_genreg,
  24900         1,
  24901         0,
  24902         0xc080159,
  24903         0,
  24904         0,
  24905         1,
  24906         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  24907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24908         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24909         -1,
  24910         -1,
  24911     },
  24912 #endif /* chips */
  24913 
  24914 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  24915     { /* SOC_REG_INT_L3_DEFIP_PARITY_CONTROL_BCM56820_A0r */
  24916         soc_block_list[5],
  24917         soc_genreg,
  24918         1,
  24919         0,
  24920         0xa080c00,
  24921         0,
  24922         0,
  24923         2,
  24924         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  24925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24926         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  24927         -1,
  24928         -1,
  24929     },
  24930 #endif /* chips */
  24931 
  24932 #if defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  24933     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  24934     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUSr */
  24935         soc_block_list[5],
  24936         soc_genreg,
  24937         1,
  24938         0,
  24939         0xa080001,
  24940         SOC_REG_FLAG_RO,
  24941         0,
  24942         2,
  24943         soc_L3_DEFIP_PARITY_STATUSr_fields,
  24944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24945         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24946         -1,
  24947         -1,
  24948     },
  24949 #endif /* chips */
  24950 
  24951 #if defined(BCM_53400_A0)
  24952     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM53400_A0r */
  24953         soc_block_list[5],
  24954         soc_genreg,
  24955         1,
  24956         0,
  24957         0x2a010100,
  24958         0,
  24959         0,
  24960         3,
  24961         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
  24962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24963         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  24964         -1,
  24965         -1,
  24966     },
  24967 #endif /* chips */
  24968 
  24969 #if defined(BCM_53540_A0)
  24970     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM53540_A0r */
  24971         soc_block_list[5],
  24972         soc_genreg,
  24973         1,
  24974         0,
  24975         0x2a010100,
  24976         0,
  24977         0,
  24978         3,
  24979         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUSr_fields,
  24980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24981         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24982         -1,
  24983         -1,
  24984     },
  24985 #endif /* chips */
  24986 
  24987 #if defined(BCM_53570_B0)
  24988     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM53570_B0r */
  24989         soc_block_list[5],
  24990         soc_genreg,
  24991         1,
  24992         0,
  24993         0x2a010100,
  24994         0,
  24995         0,
  24996         3,
  24997         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM53570_B0r_fields,
  24998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24999         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25000         -1,
  25001         -1,
  25002     },
  25003 #endif /* chips */
  25004 
  25005 #if defined(BCM_56142_A0)
  25006     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM56142_A0r */
  25007         soc_block_list[5],
  25008         soc_genreg,
  25009         1,
  25010         0,
  25011         0xc08015c,
  25012         0,
  25013         0,
  25014         3,
  25015         soc_MAC_BLOCK_TABLE_PARITY_STATUS_INTRr_fields,
  25016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25017         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25018         -1,
  25019         -1,
  25020     },
  25021 #endif /* chips */
  25022 
  25023 #if defined(BCM_56150_A0)
  25024     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM56150_A0r */
  25025         soc_block_list[5],
  25026         soc_genreg,
  25027         1,
  25028         0,
  25029         0x32010100,
  25030         0,
  25031         0,
  25032         3,
  25033         soc_EGR_FP_COUNTER_PARITY_STATUSr_fields,
  25034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25035         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  25036         -1,
  25037         -1,
  25038     },
  25039 #endif /* chips */
  25040 
  25041 #if defined(BCM_53570_A0) || defined(BCM_56160_A0)
  25042     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM56160_A0r */
  25043         soc_block_list[5],
  25044         soc_genreg,
  25045         1,
  25046         0,
  25047         0x2a010100,
  25048         0,
  25049         0,
  25050         3,
  25051         soc_EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr_fields,
  25052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25053         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  25054         -1,
  25055         -1,
  25056     },
  25057 #endif /* chips */
  25058 
  25059 #if defined(BCM_56314_A0)
  25060     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM56314_A0r */
  25061         soc_block_list[5],
  25062         soc_genreg,
  25063         1,
  25064         0,
  25065         0xa080001,
  25066         SOC_REG_FLAG_RO,
  25067         0,
  25068         2,
  25069         soc_L3_DEFIP_PARITY_STATUS_BCM56314_A0r_fields,
  25070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25071         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  25072         -1,
  25073         -1,
  25074     },
  25075 #endif /* chips */
  25076 
  25077 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  25078     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM56334_A0r */
  25079         soc_block_list[5],
  25080         soc_genreg,
  25081         1,
  25082         0,
  25083         0xc08017f,
  25084         0,
  25085         0,
  25086         3,
  25087         soc_EGR_MASK_PARITY_STATUSr_fields,
  25088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25089         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  25090         -1,
  25091         -1,
  25092     },
  25093 #endif /* chips */
  25094 
  25095 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  25096     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  25097     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM56624_A0r */
  25098         soc_block_list[5],
  25099         soc_genreg,
  25100         1,
  25101         0,
  25102         0xc08015a,
  25103         0,
  25104         0,
  25105         3,
  25106         soc_EGR_MASK_PARITY_STATUSr_fields,
  25107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25108         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  25109         -1,
  25110         -1,
  25111     },
  25112 #endif /* chips */
  25113 
  25114 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  25115     { /* SOC_REG_INT_L3_DEFIP_PARITY_STATUS_BCM56820_A0r */
  25116         soc_block_list[5],
  25117         soc_genreg,
  25118         1,
  25119         0,
  25120         0xa080c01,
  25121         SOC_REG_FLAG_RO,
  25122         0,
  25123         3,
  25124         soc_L3_DEFIP_PARITY_STATUS_BCM56820_A0r_fields,
  25125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25126         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  25127         -1,
  25128         -1,
  25129     },
  25130 #endif /* chips */
  25131 
  25132 #if defined(BCM_56514_A0)
  25133     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROLr */
  25134         soc_block_list[5],
  25135         soc_genreg,
  25136         1,
  25137         0,
  25138         0xa080002,
  25139         0,
  25140         0,
  25141         1,
  25142         soc_L3_DEFIP_RPF_CONTROLr_fields,
  25143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25144         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25145         -1,
  25146         -1,
  25147     },
  25148 #endif /* chips */
  25149 
  25150 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  25151     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
  25152     defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  25153     defined(BCM_56270_A0)
  25154     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56260_A0r */
  25155         soc_block_list[5],
  25156         soc_genreg,
  25157         1,
  25158         0,
  25159         0x2a000000,
  25160         0,
  25161         0,
  25162         1,
  25163         soc_L3_DEFIP_RPF_CONTROL_BCM56260_A0r_fields,
  25164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25165         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25166         -1,
  25167         -1,
  25168     },
  25169 #endif /* chips */
  25170 
  25171 #if defined(BCM_56370_A0)
  25172     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56370_A0r */
  25173         soc_block_list[5],
  25174         soc_genreg,
  25175         1,
  25176         0,
  25177         0x6b8c0000,
  25178         0,
  25179         0,
  25180         4,
  25181         soc_L3_DEFIP_RPF_CONTROL_BCM56870_A0r_fields,
  25182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25183         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25184         -1,
  25185         -1,
  25186         3,
  25187     },
  25188 #endif /* chips */
  25189 
  25190 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25191     defined(BCM_56450_B1)
  25192     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56450_A0r */
  25193         soc_block_list[5],
  25194         soc_genreg,
  25195         1,
  25196         0,
  25197         0x2a000000,
  25198         0,
  25199         0,
  25200         1,
  25201         soc_L3_DEFIP_RPF_CONTROL_BCM56640_A0r_fields,
  25202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25203         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25204         -1,
  25205         -1,
  25206     },
  25207 #endif /* chips */
  25208 
  25209 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  25210     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56560_A0r */
  25211         soc_block_list[5],
  25212         soc_genreg,
  25213         1,
  25214         0,
  25215         0x3a000100,
  25216         0,
  25217         0,
  25218         4,
  25219         soc_L3_DEFIP_RPF_CONTROL_BCM56960_A0r_fields,
  25220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25221         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  25222         -1,
  25223         -1,
  25224     },
  25225 #endif /* chips */
  25226 
  25227 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  25228     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  25229     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  25230     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56624_A0r */
  25231         soc_block_list[5],
  25232         soc_genreg,
  25233         1,
  25234         0,
  25235         0xc080002,
  25236         0,
  25237         0,
  25238         1,
  25239         soc_L3_DEFIP_RPF_CONTROLr_fields,
  25240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25241         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25242         -1,
  25243         -1,
  25244     },
  25245 #endif /* chips */
  25246 
  25247 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25248     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  25249     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  25250     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56634_A0r */
  25251         soc_block_list[5],
  25252         soc_genreg,
  25253         1,
  25254         0,
  25255         0x9080001,
  25256         0,
  25257         0,
  25258         1,
  25259         soc_L3_DEFIP_RPF_CONTROLr_fields,
  25260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25261         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25262         -1,
  25263         -1,
  25264     },
  25265 #endif /* chips */
  25266 
  25267 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  25268     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56640_A0r */
  25269         soc_block_list[5],
  25270         soc_genreg,
  25271         1,
  25272         0,
  25273         0x22000100,
  25274         0,
  25275         0,
  25276         1,
  25277         soc_L3_DEFIP_RPF_CONTROL_BCM56640_A0r_fields,
  25278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25279         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25280         -1,
  25281         -1,
  25282     },
  25283 #endif /* chips */
  25284 
  25285 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  25286     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56670_A0r */
  25287         soc_block_list[5],
  25288         soc_genreg,
  25289         1,
  25290         0,
  25291         0x3a000100,
  25292         0,
  25293         0,
  25294         2,
  25295         soc_L3_DEFIP_RPF_CONTROL_BCM56670_A0r_fields,
  25296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25297         SOC_RESET_MASK_DEC(0x00000011, 0x00000000)
  25298         -1,
  25299         -1,
  25300     },
  25301 #endif /* chips */
  25302 
  25303 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  25304     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56820_A0r */
  25305         soc_block_list[5],
  25306         soc_genreg,
  25307         1,
  25308         0,
  25309         0xa080602,
  25310         0,
  25311         0,
  25312         1,
  25313         soc_L3_DEFIP_RPF_CONTROLr_fields,
  25314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25315         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25316         -1,
  25317         -1,
  25318     },
  25319 #endif /* chips */
  25320 
  25321 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  25322     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  25323     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56840_A0r */
  25324         soc_block_list[5],
  25325         soc_genreg,
  25326         1,
  25327         0,
  25328         0xa080601,
  25329         0,
  25330         0,
  25331         1,
  25332         soc_L3_DEFIP_RPF_CONTROLr_fields,
  25333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25334         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25335         -1,
  25336         -1,
  25337     },
  25338 #endif /* chips */
  25339 
  25340 #if defined(BCM_56850_A0)
  25341     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56850_A0r */
  25342         soc_block_list[5],
  25343         soc_genreg,
  25344         1,
  25345         0,
  25346         0x2a000100,
  25347         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  25348         0,
  25349         3,
  25350         soc_L3_DEFIP_RPF_CONTROL_BCM56850_A0r_fields,
  25351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25352         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  25353         -1,
  25354         -1,
  25355     },
  25356 #endif /* chips */
  25357 
  25358 #if defined(BCM_56860_A0)
  25359     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56860_A0r */
  25360         soc_block_list[5],
  25361         soc_genreg,
  25362         1,
  25363         0,
  25364         0x3a000100,
  25365         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  25366         0,
  25367         3,
  25368         soc_L3_DEFIP_RPF_CONTROL_BCM56850_A0r_fields,
  25369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25370         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  25371         -1,
  25372         -1,
  25373     },
  25374 #endif /* chips */
  25375 
  25376 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  25377     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56870_A0r */
  25378         soc_block_list[5],
  25379         soc_genreg,
  25380         1,
  25381         0,
  25382         0x6b8c0000,
  25383         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  25384         0,
  25385         4,
  25386         soc_L3_DEFIP_RPF_CONTROL_BCM56870_A0r_fields,
  25387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25388         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25389         -1,
  25390         -1,
  25391         3,
  25392     },
  25393 #endif /* chips */
  25394 
  25395 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  25396     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56960_A0r */
  25397         soc_block_list[5],
  25398         soc_genreg,
  25399         1,
  25400         0,
  25401         0x3b8d0000,
  25402         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  25403         0,
  25404         4,
  25405         soc_L3_DEFIP_RPF_CONTROL_BCM56960_A0r_fields,
  25406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25407         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  25408         -1,
  25409         -1,
  25410         3,
  25411     },
  25412 #endif /* chips */
  25413 
  25414 #if defined(BCM_56970_A0)
  25415     { /* SOC_REG_INT_L3_DEFIP_RPF_CONTROL_BCM56970_A0r */
  25416         soc_block_list[5],
  25417         soc_genreg,
  25418         1,
  25419         0,
  25420         0x5f8b0000,
  25421         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  25422         0,
  25423         4,
  25424         soc_L3_DEFIP_RPF_CONTROL_BCM56960_A0r_fields,
  25425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25426         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  25427         -1,
  25428         -1,
  25429         3,
  25430     },
  25431 #endif /* chips */
  25432 
  25433 #if defined(BCM_56800_A0)
  25434     { /* SOC_REG_INT_L3_ECMP_DBGCTRLr */
  25435         soc_block_list[5],
  25436         soc_genreg,
  25437         1,
  25438         0,
  25439         0xd080c00,
  25440         0,
  25441         0,
  25442         1,
  25443         soc_CFAPMEMDEBUGr_fields,
  25444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25446         -1,
  25447         -1,
  25448     },
  25449 #endif /* chips */
  25450 
  25451 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  25452     defined(BCM_56270_A0)
  25453     { /* SOC_REG_INT_L3_ECMP_GROUP_ECCP_CONTROLr */
  25454         soc_block_list[5],
  25455         soc_genreg,
  25456         1,
  25457         0,
  25458         0x3a011300,
  25459         0,
  25460         0,
  25461         2,
  25462         soc_EGR_MASK_ECC_CONTROLr_fields,
  25463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25464         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25465         -1,
  25466         -1,
  25467     },
  25468 #endif /* chips */
  25469 
  25470 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25471     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  25472     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  25473     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_CONTROLr */
  25474         soc_block_list[5],
  25475         soc_genreg,
  25476         1,
  25477         0,
  25478         0xd08022e,
  25479         0,
  25480         0,
  25481         1,
  25482         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  25483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25484         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25485         -1,
  25486         -1,
  25487     },
  25488 #endif /* chips */
  25489 
  25490 #if defined(BCM_53400_A0)
  25491     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_CONTROL_BCM53400_A0r */
  25492         soc_block_list[5],
  25493         soc_genreg,
  25494         1,
  25495         0,
  25496         0x3e010300,
  25497         0,
  25498         0,
  25499         1,
  25500         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  25501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25502         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25503         -1,
  25504         -1,
  25505     },
  25506 #endif /* chips */
  25507 
  25508 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25509     defined(BCM_56160_A0)
  25510     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_CONTROL_BCM56160_A0r */
  25511         soc_block_list[5],
  25512         soc_genreg,
  25513         1,
  25514         0,
  25515         0x3e010400,
  25516         0,
  25517         0,
  25518         1,
  25519         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  25520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25521         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25522         -1,
  25523         -1,
  25524     },
  25525 #endif /* chips */
  25526 
  25527 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25528     defined(BCM_56450_B1)
  25529     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_CONTROL_BCM56450_A0r */
  25530         soc_block_list[5],
  25531         soc_genreg,
  25532         1,
  25533         0,
  25534         0x3a011300,
  25535         0,
  25536         0,
  25537         1,
  25538         soc_FT_CNTR_SER_CONTROLr_fields,
  25539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25540         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25541         -1,
  25542         -1,
  25543     },
  25544 #endif /* chips */
  25545 
  25546 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  25547     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  25548     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_CONTROL_BCM56840_A0r */
  25549         soc_block_list[5],
  25550         soc_genreg,
  25551         1,
  25552         0,
  25553         0xe080d0f,
  25554         0,
  25555         0,
  25556         1,
  25557         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  25558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25559         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25560         -1,
  25561         -1,
  25562     },
  25563 #endif /* chips */
  25564 
  25565 #if defined(BCM_53400_A0)
  25566     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_STATUSr */
  25567         soc_block_list[5],
  25568         soc_genreg,
  25569         1,
  25570         0,
  25571         0x3e010400,
  25572         0,
  25573         0,
  25574         3,
  25575         soc_EGR_XP0_DBITS_PARITY_STATUSr_fields,
  25576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25577         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  25578         -1,
  25579         -1,
  25580     },
  25581 #endif /* chips */
  25582 
  25583 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  25584     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_STATUS_BCM53570_A0r */
  25585         soc_block_list[5],
  25586         soc_genreg,
  25587         1,
  25588         0,
  25589         0x3e010500,
  25590         0,
  25591         0,
  25592         3,
  25593         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  25594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25595         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  25596         -1,
  25597         -1,
  25598     },
  25599 #endif /* chips */
  25600 
  25601 #if defined(BCM_56160_A0)
  25602     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_STATUS_BCM56160_A0r */
  25603         soc_block_list[5],
  25604         soc_genreg,
  25605         1,
  25606         0,
  25607         0x3e010500,
  25608         0,
  25609         0,
  25610         3,
  25611         soc_EGR_XP0_DBITS_PARITY_STATUSr_fields,
  25612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25613         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  25614         -1,
  25615         -1,
  25616     },
  25617 #endif /* chips */
  25618 
  25619 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25620     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  25621     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  25622     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_STATUS_INTRr */
  25623         soc_block_list[5],
  25624         soc_genreg,
  25625         1,
  25626         0,
  25627         0xd08022f,
  25628         0,
  25629         0,
  25630         3,
  25631         soc_EGR_IP_TUNNEL_PARITY_STATUSr_fields,
  25632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25633         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  25634         -1,
  25635         -1,
  25636     },
  25637 #endif /* chips */
  25638 
  25639 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25640     defined(BCM_56450_B1)
  25641     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_STATUS_INTR_BCM56450_A0r */
  25642         soc_block_list[5],
  25643         soc_genreg,
  25644         1,
  25645         0,
  25646         0x3a011400,
  25647         0,
  25648         0,
  25649         3,
  25650         soc_EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_INTRr_fields,
  25651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25652         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25653         -1,
  25654         -1,
  25655     },
  25656 #endif /* chips */
  25657 
  25658 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  25659     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  25660     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_STATUS_INTR_BCM56840_A0r */
  25661         soc_block_list[5],
  25662         soc_genreg,
  25663         1,
  25664         0,
  25665         0xe080d10,
  25666         0,
  25667         0,
  25668         3,
  25669         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
  25670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25671         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25672         -1,
  25673         -1,
  25674     },
  25675 #endif /* chips */
  25676 
  25677 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25678     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  25679     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  25680     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_STATUS_NACKr */
  25681         soc_block_list[5],
  25682         soc_genreg,
  25683         1,
  25684         0,
  25685         0xd080230,
  25686         0,
  25687         0,
  25688         3,
  25689         soc_EGR_IP_TUNNEL_PARITY_STATUSr_fields,
  25690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25691         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  25692         -1,
  25693         -1,
  25694     },
  25695 #endif /* chips */
  25696 
  25697 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25698     defined(BCM_56450_B1)
  25699     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_STATUS_NACK_BCM56450_A0r */
  25700         soc_block_list[5],
  25701         soc_genreg,
  25702         1,
  25703         0,
  25704         0x3a011500,
  25705         0,
  25706         0,
  25707         3,
  25708         soc_EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_INTRr_fields,
  25709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25710         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25711         -1,
  25712         -1,
  25713     },
  25714 #endif /* chips */
  25715 
  25716 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  25717     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  25718     { /* SOC_REG_INT_L3_ECMP_GROUP_PARITY_STATUS_NACK_BCM56840_A0r */
  25719         soc_block_list[5],
  25720         soc_genreg,
  25721         1,
  25722         0,
  25723         0xe080d11,
  25724         0,
  25725         0,
  25726         3,
  25727         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
  25728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25729         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25730         -1,
  25731         -1,
  25732     },
  25733 #endif /* chips */
  25734 
  25735 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25736     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  25737     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  25738     { /* SOC_REG_INT_L3_ECMP_PARITY_CONTROLr */
  25739         soc_block_list[5],
  25740         soc_genreg,
  25741         1,
  25742         0,
  25743         0xd080231,
  25744         0,
  25745         0,
  25746         1,
  25747         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  25748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25749         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25750         -1,
  25751         -1,
  25752     },
  25753 #endif /* chips */
  25754 
  25755 #if defined(BCM_53400_A0)
  25756     { /* SOC_REG_INT_L3_ECMP_PARITY_CONTROL_BCM53400_A0r */
  25757         soc_block_list[5],
  25758         soc_genreg,
  25759         1,
  25760         0,
  25761         0x3e010500,
  25762         0,
  25763         0,
  25764         1,
  25765         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  25766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25767         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25768         -1,
  25769         -1,
  25770     },
  25771 #endif /* chips */
  25772 
  25773 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25774     defined(BCM_56160_A0)
  25775     { /* SOC_REG_INT_L3_ECMP_PARITY_CONTROL_BCM56160_A0r */
  25776         soc_block_list[5],
  25777         soc_genreg,
  25778         1,
  25779         0,
  25780         0x3e010600,
  25781         0,
  25782         0,
  25783         1,
  25784         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  25785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25786         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25787         -1,
  25788         -1,
  25789     },
  25790 #endif /* chips */
  25791 
  25792 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  25793     defined(BCM_56270_A0)
  25794     { /* SOC_REG_INT_L3_ECMP_PARITY_CONTROL_BCM56260_A0r */
  25795         soc_block_list[5],
  25796         soc_genreg,
  25797         1,
  25798         0,
  25799         0x3a011600,
  25800         0,
  25801         0,
  25802         1,
  25803         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  25804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25805         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25806         -1,
  25807         -1,
  25808     },
  25809 #endif /* chips */
  25810 
  25811 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25812     defined(BCM_56450_B1)
  25813     { /* SOC_REG_INT_L3_ECMP_PARITY_CONTROL_BCM56450_A0r */
  25814         soc_block_list[5],
  25815         soc_genreg,
  25816         1,
  25817         0,
  25818         0x3a011600,
  25819         0,
  25820         0,
  25821         1,
  25822         soc_FT_CNTR_SER_CONTROLr_fields,
  25823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25824         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25825         -1,
  25826         -1,
  25827     },
  25828 #endif /* chips */
  25829 
  25830 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  25831     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  25832     { /* SOC_REG_INT_L3_ECMP_PARITY_CONTROL_BCM56840_A0r */
  25833         soc_block_list[5],
  25834         soc_genreg,
  25835         1,
  25836         0,
  25837         0xe080d12,
  25838         0,
  25839         0,
  25840         1,
  25841         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  25842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25843         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25844         -1,
  25845         -1,
  25846     },
  25847 #endif /* chips */
  25848 
  25849 #if defined(BCM_53400_A0)
  25850     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUSr */
  25851         soc_block_list[5],
  25852         soc_genreg,
  25853         1,
  25854         0,
  25855         0x3e010600,
  25856         0,
  25857         0,
  25858         3,
  25859         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM53400_A0r_fields,
  25860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25861         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  25862         -1,
  25863         -1,
  25864     },
  25865 #endif /* chips */
  25866 
  25867 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25868     defined(BCM_56160_A0)
  25869     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUS_BCM56160_A0r */
  25870         soc_block_list[5],
  25871         soc_genreg,
  25872         1,
  25873         0,
  25874         0x3e010700,
  25875         0,
  25876         0,
  25877         3,
  25878         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM53400_A0r_fields,
  25879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25880         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  25881         -1,
  25882         -1,
  25883     },
  25884 #endif /* chips */
  25885 
  25886 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25887     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  25888     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  25889     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUS_INTRr */
  25890         soc_block_list[5],
  25891         soc_genreg,
  25892         1,
  25893         0,
  25894         0xd080232,
  25895         0,
  25896         0,
  25897         3,
  25898         soc_EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr_fields,
  25899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25900         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  25901         -1,
  25902         -1,
  25903     },
  25904 #endif /* chips */
  25905 
  25906 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  25907     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUS_INTR_BCM56440_A0r */
  25908         soc_block_list[5],
  25909         soc_genreg,
  25910         1,
  25911         0,
  25912         0xe080d13,
  25913         0,
  25914         0,
  25915         3,
  25916         soc_CPB_PARITY_STATUS_INTRr_fields,
  25917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25919         -1,
  25920         -1,
  25921     },
  25922 #endif /* chips */
  25923 
  25924 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25925     defined(BCM_56450_B1)
  25926     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUS_INTR_BCM56450_A0r */
  25927         soc_block_list[5],
  25928         soc_genreg,
  25929         1,
  25930         0,
  25931         0x3a011700,
  25932         0,
  25933         0,
  25934         3,
  25935         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  25936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25938         -1,
  25939         -1,
  25940     },
  25941 #endif /* chips */
  25942 
  25943 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  25944     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUS_INTR_BCM56840_A0r */
  25945         soc_block_list[5],
  25946         soc_genreg,
  25947         1,
  25948         0,
  25949         0xe080d13,
  25950         0,
  25951         0,
  25952         3,
  25953         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  25954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25956         -1,
  25957         -1,
  25958     },
  25959 #endif /* chips */
  25960 
  25961 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25962     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  25963     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  25964     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUS_NACKr */
  25965         soc_block_list[5],
  25966         soc_genreg,
  25967         1,
  25968         0,
  25969         0xd080233,
  25970         0,
  25971         0,
  25972         3,
  25973         soc_EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr_fields,
  25974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25975         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  25976         -1,
  25977         -1,
  25978     },
  25979 #endif /* chips */
  25980 
  25981 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  25982     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUS_NACK_BCM56440_A0r */
  25983         soc_block_list[5],
  25984         soc_genreg,
  25985         1,
  25986         0,
  25987         0xe080d14,
  25988         0,
  25989         0,
  25990         3,
  25991         soc_CPB_PARITY_STATUS_INTRr_fields,
  25992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25994         -1,
  25995         -1,
  25996     },
  25997 #endif /* chips */
  25998 
  25999 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26000     defined(BCM_56450_B1)
  26001     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUS_NACK_BCM56450_A0r */
  26002         soc_block_list[5],
  26003         soc_genreg,
  26004         1,
  26005         0,
  26006         0x3a011800,
  26007         0,
  26008         0,
  26009         3,
  26010         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  26011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26012         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26013         -1,
  26014         -1,
  26015     },
  26016 #endif /* chips */
  26017 
  26018 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26019     { /* SOC_REG_INT_L3_ECMP_PARITY_STATUS_NACK_BCM56840_A0r */
  26020         soc_block_list[5],
  26021         soc_genreg,
  26022         1,
  26023         0,
  26024         0xe080d14,
  26025         0,
  26026         0,
  26027         3,
  26028         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  26029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26030         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26031         -1,
  26032         -1,
  26033     },
  26034 #endif /* chips */
  26035 
  26036 #if defined(BCM_56514_A0)
  26037     { /* SOC_REG_INT_L3_ENTRY_ADDR_MASKr */
  26038         soc_block_list[5],
  26039         soc_genreg,
  26040         1,
  26041         0,
  26042         0x8080013,
  26043         0,
  26044         0,
  26045         1,
  26046         soc_L3_ENTRY_ADDR_MASKr_fields,
  26047         SOC_RESET_VAL_DEC(0x000003ff, 0x00000000)
  26048         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  26049         -1,
  26050         -1,
  26051     },
  26052 #endif /* chips */
  26053 
  26054 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  26055     defined(BCM_56504_B0)
  26056     { /* SOC_REG_INT_L3_ENTRY_CONTROLr */
  26057         soc_block_list[5],
  26058         soc_genreg,
  26059         1,
  26060         0,
  26061         0x808000a,
  26062         0,
  26063         0,
  26064         16,
  26065         soc_L2_ENTRY_CONTROLr_fields,
  26066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26067         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26068         -1,
  26069         -1,
  26070     },
  26071 #endif /* chips */
  26072 
  26073 #if defined(BCM_56850_A0)
  26074     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0r */
  26075         soc_block_list[5],
  26076         soc_genreg,
  26077         1,
  26078         0,
  26079         0x2b0a0000,
  26080         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26081         0,
  26082         4,
  26083         soc_ISS_MEMORY_CONTROL_0r_fields,
  26084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26086         -1,
  26087         -1,
  26088     },
  26089 #endif /* chips */
  26090 
  26091 #if defined(BCM_56850_A0)
  26092     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1r */
  26093         soc_block_list[5],
  26094         soc_genreg,
  26095         1,
  26096         0,
  26097         0x2b0b0000,
  26098         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26099         0,
  26100         4,
  26101         soc_ISS_MEMORY_CONTROL_9r_fields,
  26102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26103         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26104         -1,
  26105         -1,
  26106     },
  26107 #endif /* chips */
  26108 
  26109 #if defined(BCM_56850_A0)
  26110     { /* SOC_REG_INT_L3_ENTRY_CONTROL_2r */
  26111         soc_block_list[5],
  26112         soc_genreg,
  26113         1,
  26114         0,
  26115         0x2b0c0000,
  26116         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26117         0,
  26118         4,
  26119         soc_STAGE0_MEMORY_CONTROL_15r_fields,
  26120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26121         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26122         -1,
  26123         -1,
  26124     },
  26125 #endif /* chips */
  26126 
  26127 #if defined(BCM_56850_A0)
  26128     { /* SOC_REG_INT_L3_ENTRY_CONTROL_3r */
  26129         soc_block_list[5],
  26130         soc_genreg,
  26131         1,
  26132         0,
  26133         0x2b0d0000,
  26134         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26135         0,
  26136         4,
  26137         soc_ISS_MEMORY_CONTROL_27r_fields,
  26138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26139         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26140         -1,
  26141         -1,
  26142     },
  26143 #endif /* chips */
  26144 
  26145 #if defined(BCM_56850_A0)
  26146     { /* SOC_REG_INT_L3_ENTRY_CONTROL_4r */
  26147         soc_block_list[5],
  26148         soc_genreg,
  26149         1,
  26150         0,
  26151         0x2b0e0000,
  26152         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26153         0,
  26154         3,
  26155         soc_STAGE0_MEMORY_CONTROL_6r_fields,
  26156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26157         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26158         -1,
  26159         -1,
  26160     },
  26161 #endif /* chips */
  26162 
  26163 #if defined(BCM_56850_A0)
  26164     { /* SOC_REG_INT_L3_ENTRY_CONTROL_5r */
  26165         soc_block_list[5],
  26166         soc_genreg,
  26167         1,
  26168         0,
  26169         0x2b0f0000,
  26170         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26171         0,
  26172         3,
  26173         soc_L3_ENTRY_CONTROL_5r_fields,
  26174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26175         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26176         -1,
  26177         -1,
  26178     },
  26179 #endif /* chips */
  26180 
  26181 #if defined(BCM_56850_A0)
  26182     { /* SOC_REG_INT_L3_ENTRY_CONTROL_6r */
  26183         soc_block_list[5],
  26184         soc_genreg,
  26185         1,
  26186         0,
  26187         0x2b100000,
  26188         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26189         0,
  26190         3,
  26191         soc_L3_ENTRY_CONTROL_6r_fields,
  26192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26193         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26194         -1,
  26195         -1,
  26196     },
  26197 #endif /* chips */
  26198 
  26199 #if defined(BCM_56850_A0)
  26200     { /* SOC_REG_INT_L3_ENTRY_CONTROL_7r */
  26201         soc_block_list[5],
  26202         soc_genreg,
  26203         1,
  26204         0,
  26205         0x2b110000,
  26206         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26207         0,
  26208         3,
  26209         soc_L3_ENTRY_CONTROL_7r_fields,
  26210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26212         -1,
  26213         -1,
  26214     },
  26215 #endif /* chips */
  26216 
  26217 #if defined(BCM_56850_A0)
  26218     { /* SOC_REG_INT_L3_ENTRY_CONTROL_8r */
  26219         soc_block_list[5],
  26220         soc_genreg,
  26221         1,
  26222         0,
  26223         0x2b120000,
  26224         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26225         0,
  26226         3,
  26227         soc_ISS_MEMORY_CONTROL_72r_fields,
  26228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26229         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26230         -1,
  26231         -1,
  26232     },
  26233 #endif /* chips */
  26234 
  26235 #if defined(BCM_56850_A0)
  26236     { /* SOC_REG_INT_L3_ENTRY_CONTROL_9r */
  26237         soc_block_list[5],
  26238         soc_genreg,
  26239         1,
  26240         0,
  26241         0x2b130000,
  26242         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26243         0,
  26244         1,
  26245         soc_L3_ENTRY_CONTROL_9r_fields,
  26246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26247         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26248         -1,
  26249         -1,
  26250     },
  26251 #endif /* chips */
  26252 
  26253 #if defined(BCM_56850_A0)
  26254     { /* SOC_REG_INT_L3_ENTRY_CONTROL_10r */
  26255         soc_block_list[5],
  26256         soc_genreg,
  26257         1,
  26258         0,
  26259         0x2b140000,
  26260         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26261         0,
  26262         5,
  26263         soc_L3_ENTRY_CONTROL_10r_fields,
  26264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26265         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26266         -1,
  26267         -1,
  26268     },
  26269 #endif /* chips */
  26270 
  26271 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  26272     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  26273     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_BCM56560_A0r */
  26274         soc_block_list[5],
  26275         soc_genreg,
  26276         1,
  26277         0,
  26278         0x3b030000,
  26279         0,
  26280         0,
  26281         1,
  26282         soc_L2_ENTRY_CONTROL_0_BCM56560_A0r_fields,
  26283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26284         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26285         -1,
  26286         -1,
  26287     },
  26288 #endif /* chips */
  26289 
  26290 #if defined(BCM_56860_A0)
  26291     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_BCM56860_A0r */
  26292         soc_block_list[5],
  26293         soc_genreg,
  26294         1,
  26295         0,
  26296         0x3b030000,
  26297         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26298         0,
  26299         1,
  26300         soc_L2_ENTRY_CONTROL_0_BCM56860_A0r_fields,
  26301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26303         -1,
  26304         -1,
  26305     },
  26306 #endif /* chips */
  26307 
  26308 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26309     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_BCM56960_A0r */
  26310         soc_block_list[5],
  26311         soc_genreg,
  26312         1,
  26313         0,
  26314         0x3b1c0000,
  26315         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26316         0,
  26317         4,
  26318         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26321         -1,
  26322         -1,
  26323         3,
  26324     },
  26325 #endif /* chips */
  26326 
  26327 #if defined(BCM_56970_A0)
  26328     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_BCM56970_A0r */
  26329         soc_block_list[5],
  26330         soc_genreg,
  26331         1,
  26332         0,
  26333         0x5f1b0000,
  26334         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26335         0,
  26336         4,
  26337         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26339         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26340         -1,
  26341         -1,
  26342         3,
  26343     },
  26344 #endif /* chips */
  26345 
  26346 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26347     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_PIPE0r */
  26348         soc_block_list[5],
  26349         soc_genreg,
  26350         1,
  26351         0,
  26352         0x3b1c0000,
  26353         0,
  26354         0,
  26355         4,
  26356         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26358         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26359         -1,
  26360         -1,
  26361         3,
  26362     },
  26363 #endif /* chips */
  26364 
  26365 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26366     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_PIPE1r */
  26367         soc_block_list[5],
  26368         soc_genreg,
  26369         1,
  26370         0,
  26371         0x3b1c0000,
  26372         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26373         0,
  26374         4,
  26375         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26378         -1,
  26379         -1,
  26380         3,
  26381     },
  26382 #endif /* chips */
  26383 
  26384 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26385     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_PIPE2r */
  26386         soc_block_list[5],
  26387         soc_genreg,
  26388         1,
  26389         0,
  26390         0x3b1c0000,
  26391         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26392         0,
  26393         4,
  26394         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26397         -1,
  26398         -1,
  26399         3,
  26400     },
  26401 #endif /* chips */
  26402 
  26403 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26404     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_PIPE3r */
  26405         soc_block_list[5],
  26406         soc_genreg,
  26407         1,
  26408         0,
  26409         0x3b1c0000,
  26410         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26411         0,
  26412         4,
  26413         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26415         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26416         -1,
  26417         -1,
  26418         3,
  26419     },
  26420 #endif /* chips */
  26421 
  26422 #if defined(BCM_56970_A0)
  26423     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_PIPE0_BCM56970_A0r */
  26424         soc_block_list[5],
  26425         soc_genreg,
  26426         1,
  26427         0,
  26428         0x5f1b0000,
  26429         0,
  26430         0,
  26431         4,
  26432         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26434         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26435         -1,
  26436         -1,
  26437         3,
  26438     },
  26439 #endif /* chips */
  26440 
  26441 #if defined(BCM_56970_A0)
  26442     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_PIPE1_BCM56970_A0r */
  26443         soc_block_list[5],
  26444         soc_genreg,
  26445         1,
  26446         0,
  26447         0x5f1b0000,
  26448         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26449         0,
  26450         4,
  26451         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26453         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26454         -1,
  26455         -1,
  26456         3,
  26457     },
  26458 #endif /* chips */
  26459 
  26460 #if defined(BCM_56970_A0)
  26461     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_PIPE2_BCM56970_A0r */
  26462         soc_block_list[5],
  26463         soc_genreg,
  26464         1,
  26465         0,
  26466         0x5f1b0000,
  26467         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26468         0,
  26469         4,
  26470         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26472         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26473         -1,
  26474         -1,
  26475         3,
  26476     },
  26477 #endif /* chips */
  26478 
  26479 #if defined(BCM_56970_A0)
  26480     { /* SOC_REG_INT_L3_ENTRY_CONTROL_0_PIPE3_BCM56970_A0r */
  26481         soc_block_list[5],
  26482         soc_genreg,
  26483         1,
  26484         0,
  26485         0x5f1b0000,
  26486         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26487         0,
  26488         4,
  26489         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  26490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26491         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26492         -1,
  26493         -1,
  26494         3,
  26495     },
  26496 #endif /* chips */
  26497 
  26498 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  26499     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  26500     { /* SOC_REG_INT_L3_ENTRY_CONTROL_10_BCM56560_A0r */
  26501         soc_block_list[5],
  26502         soc_genreg,
  26503         1,
  26504         0,
  26505         0x3b040000,
  26506         0,
  26507         0,
  26508         5,
  26509         soc_L3_ENTRY_CONTROL_10_BCM56960_A0r_fields,
  26510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26511         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26512         -1,
  26513         -1,
  26514     },
  26515 #endif /* chips */
  26516 
  26517 #if defined(BCM_56860_A0)
  26518     { /* SOC_REG_INT_L3_ENTRY_CONTROL_10_BCM56860_A0r */
  26519         soc_block_list[5],
  26520         soc_genreg,
  26521         1,
  26522         0,
  26523         0x3b040000,
  26524         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26525         0,
  26526         5,
  26527         soc_L3_ENTRY_CONTROL_10r_fields,
  26528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26529         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26530         -1,
  26531         -1,
  26532     },
  26533 #endif /* chips */
  26534 
  26535 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26536     { /* SOC_REG_INT_L3_ENTRY_CONTROL_10_BCM56960_A0r */
  26537         soc_block_list[5],
  26538         soc_genreg,
  26539         1,
  26540         0,
  26541         0x3b1e0000,
  26542         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26543         0,
  26544         5,
  26545         soc_L3_ENTRY_CONTROL_10_BCM56960_A0r_fields,
  26546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26547         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26548         -1,
  26549         -1,
  26550         3,
  26551     },
  26552 #endif /* chips */
  26553 
  26554 #if defined(BCM_56970_A0)
  26555     { /* SOC_REG_INT_L3_ENTRY_CONTROL_10_BCM56970_A0r */
  26556         soc_block_list[5],
  26557         soc_genreg,
  26558         1,
  26559         0,
  26560         0x5f1d0000,
  26561         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26562         0,
  26563         6,
  26564         soc_L3_ENTRY_CONTROL_10_BCM56970_A0r_fields,
  26565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26566         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26567         -1,
  26568         -1,
  26569         3,
  26570     },
  26571 #endif /* chips */
  26572 
  26573 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26574     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_BCM56960_A0r */
  26575         soc_block_list[5],
  26576         soc_genreg,
  26577         1,
  26578         0,
  26579         0x3b1d0000,
  26580         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26581         0,
  26582         4,
  26583         soc_L3_ENTRY_CONTROL_1r_fields,
  26584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26585         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26586         -1,
  26587         -1,
  26588         3,
  26589     },
  26590 #endif /* chips */
  26591 
  26592 #if defined(BCM_56970_A0)
  26593     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_BCM56970_A0r */
  26594         soc_block_list[5],
  26595         soc_genreg,
  26596         1,
  26597         0,
  26598         0x5f1c0000,
  26599         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26600         0,
  26601         4,
  26602         soc_L3_ENTRY_CONTROL_1r_fields,
  26603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26604         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26605         -1,
  26606         -1,
  26607         3,
  26608     },
  26609 #endif /* chips */
  26610 
  26611 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26612     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_PIPE0r */
  26613         soc_block_list[5],
  26614         soc_genreg,
  26615         1,
  26616         0,
  26617         0x3b1d0000,
  26618         0,
  26619         0,
  26620         4,
  26621         soc_L3_ENTRY_CONTROL_1r_fields,
  26622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26623         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26624         -1,
  26625         -1,
  26626         3,
  26627     },
  26628 #endif /* chips */
  26629 
  26630 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26631     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_PIPE1r */
  26632         soc_block_list[5],
  26633         soc_genreg,
  26634         1,
  26635         0,
  26636         0x3b1d0000,
  26637         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26638         0,
  26639         4,
  26640         soc_L3_ENTRY_CONTROL_1r_fields,
  26641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26642         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26643         -1,
  26644         -1,
  26645         3,
  26646     },
  26647 #endif /* chips */
  26648 
  26649 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26650     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_PIPE2r */
  26651         soc_block_list[5],
  26652         soc_genreg,
  26653         1,
  26654         0,
  26655         0x3b1d0000,
  26656         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26657         0,
  26658         4,
  26659         soc_L3_ENTRY_CONTROL_1r_fields,
  26660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26661         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26662         -1,
  26663         -1,
  26664         3,
  26665     },
  26666 #endif /* chips */
  26667 
  26668 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  26669     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_PIPE3r */
  26670         soc_block_list[5],
  26671         soc_genreg,
  26672         1,
  26673         0,
  26674         0x3b1d0000,
  26675         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26676         0,
  26677         4,
  26678         soc_L3_ENTRY_CONTROL_1r_fields,
  26679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26680         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26681         -1,
  26682         -1,
  26683         3,
  26684     },
  26685 #endif /* chips */
  26686 
  26687 #if defined(BCM_56970_A0)
  26688     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_PIPE0_BCM56970_A0r */
  26689         soc_block_list[5],
  26690         soc_genreg,
  26691         1,
  26692         0,
  26693         0x5f1c0000,
  26694         0,
  26695         0,
  26696         4,
  26697         soc_L3_ENTRY_CONTROL_1r_fields,
  26698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26700         -1,
  26701         -1,
  26702         3,
  26703     },
  26704 #endif /* chips */
  26705 
  26706 #if defined(BCM_56970_A0)
  26707     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_PIPE1_BCM56970_A0r */
  26708         soc_block_list[5],
  26709         soc_genreg,
  26710         1,
  26711         0,
  26712         0x5f1c0000,
  26713         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26714         0,
  26715         4,
  26716         soc_L3_ENTRY_CONTROL_1r_fields,
  26717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26718         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26719         -1,
  26720         -1,
  26721         3,
  26722     },
  26723 #endif /* chips */
  26724 
  26725 #if defined(BCM_56970_A0)
  26726     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_PIPE2_BCM56970_A0r */
  26727         soc_block_list[5],
  26728         soc_genreg,
  26729         1,
  26730         0,
  26731         0x5f1c0000,
  26732         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26733         0,
  26734         4,
  26735         soc_L3_ENTRY_CONTROL_1r_fields,
  26736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26737         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26738         -1,
  26739         -1,
  26740         3,
  26741     },
  26742 #endif /* chips */
  26743 
  26744 #if defined(BCM_56970_A0)
  26745     { /* SOC_REG_INT_L3_ENTRY_CONTROL_1_PIPE3_BCM56970_A0r */
  26746         soc_block_list[5],
  26747         soc_genreg,
  26748         1,
  26749         0,
  26750         0x5f1c0000,
  26751         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  26752         0,
  26753         4,
  26754         soc_L3_ENTRY_CONTROL_1r_fields,
  26755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26756         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26757         -1,
  26758         -1,
  26759         3,
  26760     },
  26761 #endif /* chips */
  26762 
  26763 #if defined(BCM_56514_A0)
  26764     { /* SOC_REG_INT_L3_ENTRY_CONTROL_BCM56514_A0r */
  26765         soc_block_list[5],
  26766         soc_genreg,
  26767         1,
  26768         0,
  26769         0x808000b,
  26770         0,
  26771         0,
  26772         16,
  26773         soc_L2_ENTRY_CONTROLr_fields,
  26774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26775         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26776         -1,
  26777         -1,
  26778     },
  26779 #endif /* chips */
  26780 
  26781 #if defined(BCM_56800_A0)
  26782     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0r */
  26783         soc_block_list[5],
  26784         soc_genreg,
  26785         1,
  26786         0,
  26787         0x808020a,
  26788         0,
  26789         0,
  26790         4,
  26791         soc_L2_ENTRY_DBGCTRL0r_fields,
  26792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26793         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26794         -1,
  26795         -1,
  26796     },
  26797 #endif /* chips */
  26798 
  26799 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  26800     defined(BCM_56160_A0)
  26801     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL00r */
  26802         soc_block_list[5],
  26803         soc_genreg,
  26804         1,
  26805         0,
  26806         0x26010a00,
  26807         0,
  26808         0,
  26809         1,
  26810         soc_L3_ENTRY_DBGCTRL00r_fields,
  26811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26812         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26813         -1,
  26814         -1,
  26815     },
  26816 #endif /* chips */
  26817 
  26818 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  26819     defined(BCM_56160_A0)
  26820     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL01r */
  26821         soc_block_list[5],
  26822         soc_genreg,
  26823         1,
  26824         0,
  26825         0x26010b00,
  26826         0,
  26827         0,
  26828         1,
  26829         soc_L3_ENTRY_DBGCTRL01r_fields,
  26830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26832         -1,
  26833         -1,
  26834     },
  26835 #endif /* chips */
  26836 
  26837 #if defined(BCM_56800_A0)
  26838     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1r */
  26839         soc_block_list[5],
  26840         soc_genreg,
  26841         1,
  26842         0,
  26843         0x808020b,
  26844         0,
  26845         0,
  26846         4,
  26847         soc_L2_ENTRY_DBGCTRL1r_fields,
  26848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26850         -1,
  26851         -1,
  26852     },
  26853 #endif /* chips */
  26854 
  26855 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  26856     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26857     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL2r */
  26858         soc_block_list[5],
  26859         soc_genreg,
  26860         1,
  26861         0,
  26862         0x9080d02,
  26863         0,
  26864         0,
  26865         3,
  26866         soc_L2_ENTRY_DA_DBGCTRL_2r_fields,
  26867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26868         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26869         -1,
  26870         -1,
  26871     },
  26872 #endif /* chips */
  26873 
  26874 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  26875     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26876     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL3r */
  26877         soc_block_list[5],
  26878         soc_genreg,
  26879         1,
  26880         0,
  26881         0x9080d03,
  26882         0,
  26883         0,
  26884         3,
  26885         soc_L2_ENTRY_DA_DBGCTRL_3r_fields,
  26886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26887         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26888         -1,
  26889         -1,
  26890     },
  26891 #endif /* chips */
  26892 
  26893 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  26894     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26895     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL4r */
  26896         soc_block_list[5],
  26897         soc_genreg,
  26898         1,
  26899         0,
  26900         0x9080d04,
  26901         0,
  26902         0,
  26903         3,
  26904         soc_L2_ENTRY_DA_DBGCTRL_4r_fields,
  26905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26906         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26907         -1,
  26908         -1,
  26909     },
  26910 #endif /* chips */
  26911 
  26912 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  26913     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26914     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL5r */
  26915         soc_block_list[5],
  26916         soc_genreg,
  26917         1,
  26918         0,
  26919         0x9080d05,
  26920         0,
  26921         0,
  26922         17,
  26923         soc_L3_ENTRY_DBGCTRL5r_fields,
  26924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26926         -1,
  26927         -1,
  26928     },
  26929 #endif /* chips */
  26930 
  26931 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  26932     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26933     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL6r */
  26934         soc_block_list[5],
  26935         soc_genreg,
  26936         1,
  26937         0,
  26938         0x9080d06,
  26939         0,
  26940         0,
  26941         17,
  26942         soc_L3_ENTRY_DBGCTRL6r_fields,
  26943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26944         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26945         -1,
  26946         -1,
  26947     },
  26948 #endif /* chips */
  26949 
  26950 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  26951     defined(BCM_56160_A0)
  26952     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL10r */
  26953         soc_block_list[5],
  26954         soc_genreg,
  26955         1,
  26956         0,
  26957         0x26010c00,
  26958         0,
  26959         0,
  26960         1,
  26961         soc_L3_ENTRY_DBGCTRL10r_fields,
  26962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26963         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26964         -1,
  26965         -1,
  26966     },
  26967 #endif /* chips */
  26968 
  26969 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  26970     defined(BCM_56160_A0)
  26971     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL11r */
  26972         soc_block_list[5],
  26973         soc_genreg,
  26974         1,
  26975         0,
  26976         0x26010d00,
  26977         0,
  26978         0,
  26979         1,
  26980         soc_L3_ENTRY_DBGCTRL11r_fields,
  26981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26982         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26983         -1,
  26984         -1,
  26985     },
  26986 #endif /* chips */
  26987 
  26988 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  26989     defined(BCM_56160_A0)
  26990     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL20r */
  26991         soc_block_list[5],
  26992         soc_genreg,
  26993         1,
  26994         0,
  26995         0x26010e00,
  26996         0,
  26997         0,
  26998         1,
  26999         soc_L3_ENTRY_DBGCTRL20r_fields,
  27000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27001         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27002         -1,
  27003         -1,
  27004     },
  27005 #endif /* chips */
  27006 
  27007 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27008     defined(BCM_56160_A0)
  27009     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL21r */
  27010         soc_block_list[5],
  27011         soc_genreg,
  27012         1,
  27013         0,
  27014         0x26010f00,
  27015         0,
  27016         0,
  27017         1,
  27018         soc_L3_ENTRY_DBGCTRL21r_fields,
  27019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27020         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27021         -1,
  27022         -1,
  27023     },
  27024 #endif /* chips */
  27025 
  27026 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27027     defined(BCM_56160_A0)
  27028     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL30r */
  27029         soc_block_list[5],
  27030         soc_genreg,
  27031         1,
  27032         0,
  27033         0x26011000,
  27034         0,
  27035         0,
  27036         1,
  27037         soc_L3_ENTRY_DBGCTRL30r_fields,
  27038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27040         -1,
  27041         -1,
  27042     },
  27043 #endif /* chips */
  27044 
  27045 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27046     defined(BCM_56160_A0)
  27047     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL31r */
  27048         soc_block_list[5],
  27049         soc_genreg,
  27050         1,
  27051         0,
  27052         0x26011100,
  27053         0,
  27054         0,
  27055         1,
  27056         soc_L3_ENTRY_DBGCTRL31r_fields,
  27057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27058         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27059         -1,
  27060         -1,
  27061     },
  27062 #endif /* chips */
  27063 
  27064 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27065     defined(BCM_56160_A0)
  27066     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL40r */
  27067         soc_block_list[5],
  27068         soc_genreg,
  27069         1,
  27070         0,
  27071         0x26011200,
  27072         0,
  27073         0,
  27074         1,
  27075         soc_L3_ENTRY_DBGCTRL40r_fields,
  27076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27077         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27078         -1,
  27079         -1,
  27080     },
  27081 #endif /* chips */
  27082 
  27083 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27084     defined(BCM_56160_A0)
  27085     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL41r */
  27086         soc_block_list[5],
  27087         soc_genreg,
  27088         1,
  27089         0,
  27090         0x26011300,
  27091         0,
  27092         0,
  27093         1,
  27094         soc_L3_ENTRY_DBGCTRL41r_fields,
  27095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27096         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27097         -1,
  27098         -1,
  27099     },
  27100 #endif /* chips */
  27101 
  27102 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27103     defined(BCM_56160_A0)
  27104     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL50r */
  27105         soc_block_list[5],
  27106         soc_genreg,
  27107         1,
  27108         0,
  27109         0x26011400,
  27110         0,
  27111         0,
  27112         1,
  27113         soc_L3_ENTRY_DBGCTRL50r_fields,
  27114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27115         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27116         -1,
  27117         -1,
  27118     },
  27119 #endif /* chips */
  27120 
  27121 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27122     defined(BCM_56160_A0)
  27123     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL51r */
  27124         soc_block_list[5],
  27125         soc_genreg,
  27126         1,
  27127         0,
  27128         0x26011500,
  27129         0,
  27130         0,
  27131         1,
  27132         soc_L3_ENTRY_DBGCTRL51r_fields,
  27133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27134         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27135         -1,
  27136         -1,
  27137     },
  27138 #endif /* chips */
  27139 
  27140 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27141     defined(BCM_56160_A0)
  27142     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL60r */
  27143         soc_block_list[5],
  27144         soc_genreg,
  27145         1,
  27146         0,
  27147         0x26011600,
  27148         0,
  27149         0,
  27150         1,
  27151         soc_L3_ENTRY_DBGCTRL60r_fields,
  27152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27153         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27154         -1,
  27155         -1,
  27156     },
  27157 #endif /* chips */
  27158 
  27159 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27160     defined(BCM_56160_A0)
  27161     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL61r */
  27162         soc_block_list[5],
  27163         soc_genreg,
  27164         1,
  27165         0,
  27166         0x26011700,
  27167         0,
  27168         0,
  27169         1,
  27170         soc_L3_ENTRY_DBGCTRL61r_fields,
  27171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27172         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27173         -1,
  27174         -1,
  27175     },
  27176 #endif /* chips */
  27177 
  27178 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27179     defined(BCM_56160_A0)
  27180     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL70r */
  27181         soc_block_list[5],
  27182         soc_genreg,
  27183         1,
  27184         0,
  27185         0x26011800,
  27186         0,
  27187         0,
  27188         1,
  27189         soc_L3_ENTRY_DBGCTRL70r_fields,
  27190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27192         -1,
  27193         -1,
  27194     },
  27195 #endif /* chips */
  27196 
  27197 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27198     defined(BCM_56160_A0)
  27199     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL71r */
  27200         soc_block_list[5],
  27201         soc_genreg,
  27202         1,
  27203         0,
  27204         0x26011900,
  27205         0,
  27206         0,
  27207         1,
  27208         soc_L3_ENTRY_DBGCTRL71r_fields,
  27209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27210         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27211         -1,
  27212         -1,
  27213     },
  27214 #endif /* chips */
  27215 
  27216 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27217     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL00_BCM53570_A0r */
  27218         soc_block_list[5],
  27219         soc_genreg,
  27220         1,
  27221         0,
  27222         0x26010a00,
  27223         0,
  27224         0,
  27225         1,
  27226         soc_L3_ENTRY_DBGCTRL00_BCM53570_A0r_fields,
  27227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27228         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27229         -1,
  27230         -1,
  27231     },
  27232 #endif /* chips */
  27233 
  27234 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27235     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL01_BCM53570_A0r */
  27236         soc_block_list[5],
  27237         soc_genreg,
  27238         1,
  27239         0,
  27240         0x26010b00,
  27241         0,
  27242         0,
  27243         1,
  27244         soc_L3_ENTRY_DBGCTRL01_BCM53570_A0r_fields,
  27245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27246         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27247         -1,
  27248         -1,
  27249     },
  27250 #endif /* chips */
  27251 
  27252 #if defined(BCM_56142_A0)
  27253     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56142_A0r */
  27254         soc_block_list[5],
  27255         soc_genreg,
  27256         1,
  27257         0,
  27258         0xa080154,
  27259         0,
  27260         0,
  27261         4,
  27262         soc_L2_ENTRY_DBGCTRL0r_fields,
  27263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27264         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27265         -1,
  27266         -1,
  27267     },
  27268 #endif /* chips */
  27269 
  27270 #if defined(BCM_56150_A0)
  27271     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56150_A0r */
  27272         soc_block_list[5],
  27273         soc_genreg,
  27274         1,
  27275         0,
  27276         0x2a010a00,
  27277         0,
  27278         0,
  27279         3,
  27280         soc_MPLS_ENTRY_DBGCTRL_0r_fields,
  27281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27282         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27283         -1,
  27284         -1,
  27285     },
  27286 #endif /* chips */
  27287 
  27288 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  27289     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56260_A0r */
  27290         soc_block_list[5],
  27291         soc_genreg,
  27292         1,
  27293         0,
  27294         0x26010000,
  27295         SOC_REG_FLAG_64_BITS,
  27296         0,
  27297         3,
  27298         soc_L2_ENTRY_DBGCTRL_0_BCM56260_A0r_fields,
  27299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27300         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27301         -1,
  27302         -1,
  27303     },
  27304 #endif /* chips */
  27305 
  27306 #if defined(BCM_56270_A0)
  27307     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56270_A0r */
  27308         soc_block_list[5],
  27309         soc_genreg,
  27310         1,
  27311         0,
  27312         0x26010000,
  27313         SOC_REG_FLAG_64_BITS,
  27314         0,
  27315         3,
  27316         soc_L2_ENTRY_DBGCTRL_0_BCM56270_A0r_fields,
  27317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27319         -1,
  27320         -1,
  27321     },
  27322 #endif /* chips */
  27323 
  27324 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  27325     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56334_A0r */
  27326         soc_block_list[5],
  27327         soc_genreg,
  27328         1,
  27329         0,
  27330         0xa080170,
  27331         0,
  27332         0,
  27333         4,
  27334         soc_L2_ENTRY_DBGCTRL0r_fields,
  27335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27336         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27337         -1,
  27338         -1,
  27339     },
  27340 #endif /* chips */
  27341 
  27342 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27343     defined(BCM_56450_B1)
  27344     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56450_A0r */
  27345         soc_block_list[5],
  27346         soc_genreg,
  27347         1,
  27348         0,
  27349         0x26010000,
  27350         SOC_REG_FLAG_64_BITS,
  27351         0,
  27352         6,
  27353         soc_L2_ENTRY_DBGCTRL_0_BCM56450_A0r_fields,
  27354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27355         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27356         -1,
  27357         -1,
  27358     },
  27359 #endif /* chips */
  27360 
  27361 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  27362     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  27363     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56624_A0r */
  27364         soc_block_list[5],
  27365         soc_genreg,
  27366         1,
  27367         0,
  27368         0xa08014b,
  27369         0,
  27370         0,
  27371         4,
  27372         soc_L2_ENTRY_DBGCTRL0r_fields,
  27373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27375         -1,
  27376         -1,
  27377     },
  27378 #endif /* chips */
  27379 
  27380 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  27381     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  27382     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  27383     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56634_A0r */
  27384         soc_block_list[5],
  27385         soc_genreg,
  27386         1,
  27387         0,
  27388         0x90801ac,
  27389         0,
  27390         0,
  27391         4,
  27392         soc_L2_ENTRY_DBGCTRL0r_fields,
  27393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27394         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27395         -1,
  27396         -1,
  27397     },
  27398 #endif /* chips */
  27399 
  27400 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  27401     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56820_A0r */
  27402         soc_block_list[5],
  27403         soc_genreg,
  27404         1,
  27405         0,
  27406         0x808020a,
  27407         0,
  27408         0,
  27409         2,
  27410         soc_L2_ENTRY_DBGCTRL0_BCM56820_A0r_fields,
  27411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27412         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27413         -1,
  27414         -1,
  27415     },
  27416 #endif /* chips */
  27417 
  27418 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  27419     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  27420     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL0_BCM56840_A0r */
  27421         soc_block_list[5],
  27422         soc_genreg,
  27423         1,
  27424         0,
  27425         0x9080d00,
  27426         0,
  27427         0,
  27428         3,
  27429         soc_L2_ENTRY_DA_DBGCTRL_0r_fields,
  27430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27431         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27432         -1,
  27433         -1,
  27434     },
  27435 #endif /* chips */
  27436 
  27437 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27438     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL10_BCM53570_A0r */
  27439         soc_block_list[5],
  27440         soc_genreg,
  27441         1,
  27442         0,
  27443         0x26010c00,
  27444         0,
  27445         0,
  27446         1,
  27447         soc_L3_ENTRY_DBGCTRL10_BCM53570_A0r_fields,
  27448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27449         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27450         -1,
  27451         -1,
  27452     },
  27453 #endif /* chips */
  27454 
  27455 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27456     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL11_BCM53570_A0r */
  27457         soc_block_list[5],
  27458         soc_genreg,
  27459         1,
  27460         0,
  27461         0x26010d00,
  27462         0,
  27463         0,
  27464         1,
  27465         soc_L3_ENTRY_DBGCTRL11_BCM53570_A0r_fields,
  27466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27467         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27468         -1,
  27469         -1,
  27470     },
  27471 #endif /* chips */
  27472 
  27473 #if defined(BCM_56142_A0)
  27474     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1_BCM56142_A0r */
  27475         soc_block_list[5],
  27476         soc_genreg,
  27477         1,
  27478         0,
  27479         0xa080155,
  27480         0,
  27481         0,
  27482         4,
  27483         soc_L2_ENTRY_DBGCTRL1r_fields,
  27484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27486         -1,
  27487         -1,
  27488     },
  27489 #endif /* chips */
  27490 
  27491 #if defined(BCM_56150_A0)
  27492     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1_BCM56150_A0r */
  27493         soc_block_list[5],
  27494         soc_genreg,
  27495         1,
  27496         0,
  27497         0x2a010b00,
  27498         0,
  27499         0,
  27500         3,
  27501         soc_MPLS_ENTRY_DBGCTRL_1r_fields,
  27502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27503         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27504         -1,
  27505         -1,
  27506     },
  27507 #endif /* chips */
  27508 
  27509 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  27510     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1_BCM56260_A0r */
  27511         soc_block_list[5],
  27512         soc_genreg,
  27513         1,
  27514         0,
  27515         0x26010100,
  27516         SOC_REG_FLAG_64_BITS,
  27517         0,
  27518         3,
  27519         soc_L2_ENTRY_DBGCTRL_1_BCM56260_A0r_fields,
  27520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27522         -1,
  27523         -1,
  27524     },
  27525 #endif /* chips */
  27526 
  27527 #if defined(BCM_56270_A0)
  27528     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1_BCM56270_A0r */
  27529         soc_block_list[5],
  27530         soc_genreg,
  27531         1,
  27532         0,
  27533         0x26010100,
  27534         SOC_REG_FLAG_64_BITS,
  27535         0,
  27536         3,
  27537         soc_L2_ENTRY_DBGCTRL_1_BCM56270_A0r_fields,
  27538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27540         -1,
  27541         -1,
  27542     },
  27543 #endif /* chips */
  27544 
  27545 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  27546     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1_BCM56334_A0r */
  27547         soc_block_list[5],
  27548         soc_genreg,
  27549         1,
  27550         0,
  27551         0xa080171,
  27552         0,
  27553         0,
  27554         4,
  27555         soc_L2_ENTRY_DBGCTRL1r_fields,
  27556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27558         -1,
  27559         -1,
  27560     },
  27561 #endif /* chips */
  27562 
  27563 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27564     defined(BCM_56450_B1)
  27565     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1_BCM56450_A0r */
  27566         soc_block_list[5],
  27567         soc_genreg,
  27568         1,
  27569         0,
  27570         0x26010100,
  27571         SOC_REG_FLAG_64_BITS,
  27572         0,
  27573         6,
  27574         soc_L2_ENTRY_DBGCTRL_1_BCM56450_A0r_fields,
  27575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27577         -1,
  27578         -1,
  27579     },
  27580 #endif /* chips */
  27581 
  27582 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  27583     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  27584     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1_BCM56624_A0r */
  27585         soc_block_list[5],
  27586         soc_genreg,
  27587         1,
  27588         0,
  27589         0xa08014c,
  27590         0,
  27591         0,
  27592         4,
  27593         soc_L2_ENTRY_DBGCTRL1r_fields,
  27594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27595         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27596         -1,
  27597         -1,
  27598     },
  27599 #endif /* chips */
  27600 
  27601 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  27602     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  27603     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  27604     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1_BCM56634_A0r */
  27605         soc_block_list[5],
  27606         soc_genreg,
  27607         1,
  27608         0,
  27609         0x90801ad,
  27610         0,
  27611         0,
  27612         4,
  27613         soc_L2_ENTRY_DBGCTRL1r_fields,
  27614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27616         -1,
  27617         -1,
  27618     },
  27619 #endif /* chips */
  27620 
  27621 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  27622     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  27623     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL1_BCM56840_A0r */
  27624         soc_block_list[5],
  27625         soc_genreg,
  27626         1,
  27627         0,
  27628         0x9080d01,
  27629         0,
  27630         0,
  27631         3,
  27632         soc_L2_ENTRY_DA_DBGCTRL_1r_fields,
  27633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27634         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27635         -1,
  27636         -1,
  27637     },
  27638 #endif /* chips */
  27639 
  27640 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27641     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL20_BCM53570_A0r */
  27642         soc_block_list[5],
  27643         soc_genreg,
  27644         1,
  27645         0,
  27646         0x26010e00,
  27647         0,
  27648         0,
  27649         1,
  27650         soc_L3_ENTRY_DBGCTRL20_BCM53570_A0r_fields,
  27651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27652         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27653         -1,
  27654         -1,
  27655     },
  27656 #endif /* chips */
  27657 
  27658 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27659     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL21_BCM53570_A0r */
  27660         soc_block_list[5],
  27661         soc_genreg,
  27662         1,
  27663         0,
  27664         0x26010f00,
  27665         0,
  27666         0,
  27667         1,
  27668         soc_L3_ENTRY_DBGCTRL21_BCM53570_A0r_fields,
  27669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27670         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27671         -1,
  27672         -1,
  27673     },
  27674 #endif /* chips */
  27675 
  27676 #if defined(BCM_56150_A0)
  27677     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL2_BCM56150_A0r */
  27678         soc_block_list[5],
  27679         soc_genreg,
  27680         1,
  27681         0,
  27682         0x2a010c00,
  27683         0,
  27684         0,
  27685         2,
  27686         soc_MPLS_ENTRY_DBGCTRL_2_BCM56850_A0r_fields,
  27687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27688         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27689         -1,
  27690         -1,
  27691     },
  27692 #endif /* chips */
  27693 
  27694 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  27695     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL2_BCM56260_A0r */
  27696         soc_block_list[5],
  27697         soc_genreg,
  27698         1,
  27699         0,
  27700         0x26010200,
  27701         SOC_REG_FLAG_64_BITS,
  27702         0,
  27703         3,
  27704         soc_L3_ENTRY_DBGCTRL2_BCM56260_A0r_fields,
  27705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27706         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27707         -1,
  27708         -1,
  27709     },
  27710 #endif /* chips */
  27711 
  27712 #if defined(BCM_56270_A0)
  27713     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL2_BCM56270_A0r */
  27714         soc_block_list[5],
  27715         soc_genreg,
  27716         1,
  27717         0,
  27718         0x26010200,
  27719         SOC_REG_FLAG_64_BITS,
  27720         0,
  27721         3,
  27722         soc_L3_ENTRY_DBGCTRL2_BCM56270_A0r_fields,
  27723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27724         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27725         -1,
  27726         -1,
  27727     },
  27728 #endif /* chips */
  27729 
  27730 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27731     defined(BCM_56450_B1)
  27732     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL2_BCM56450_A0r */
  27733         soc_block_list[5],
  27734         soc_genreg,
  27735         1,
  27736         0,
  27737         0x26010200,
  27738         SOC_REG_FLAG_64_BITS,
  27739         0,
  27740         6,
  27741         soc_L3_ENTRY_DBGCTRL2r_fields,
  27742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27744         -1,
  27745         -1,
  27746     },
  27747 #endif /* chips */
  27748 
  27749 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27750     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL30_BCM53570_A0r */
  27751         soc_block_list[5],
  27752         soc_genreg,
  27753         1,
  27754         0,
  27755         0x26011000,
  27756         0,
  27757         0,
  27758         1,
  27759         soc_L3_ENTRY_DBGCTRL30_BCM53570_A0r_fields,
  27760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27762         -1,
  27763         -1,
  27764     },
  27765 #endif /* chips */
  27766 
  27767 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27768     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL31_BCM53570_A0r */
  27769         soc_block_list[5],
  27770         soc_genreg,
  27771         1,
  27772         0,
  27773         0x26011100,
  27774         0,
  27775         0,
  27776         1,
  27777         soc_L3_ENTRY_DBGCTRL31_BCM53570_A0r_fields,
  27778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27779         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27780         -1,
  27781         -1,
  27782     },
  27783 #endif /* chips */
  27784 
  27785 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  27786     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL3_BCM56260_A0r */
  27787         soc_block_list[5],
  27788         soc_genreg,
  27789         1,
  27790         0,
  27791         0x26010300,
  27792         SOC_REG_FLAG_64_BITS,
  27793         0,
  27794         3,
  27795         soc_L3_ENTRY_DBGCTRL3_BCM56260_A0r_fields,
  27796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27797         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27798         -1,
  27799         -1,
  27800     },
  27801 #endif /* chips */
  27802 
  27803 #if defined(BCM_56270_A0)
  27804     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL3_BCM56270_A0r */
  27805         soc_block_list[5],
  27806         soc_genreg,
  27807         1,
  27808         0,
  27809         0x26010300,
  27810         SOC_REG_FLAG_64_BITS,
  27811         0,
  27812         3,
  27813         soc_L3_ENTRY_DBGCTRL3_BCM56270_A0r_fields,
  27814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27815         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27816         -1,
  27817         -1,
  27818     },
  27819 #endif /* chips */
  27820 
  27821 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27822     defined(BCM_56450_B1)
  27823     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL3_BCM56450_A0r */
  27824         soc_block_list[5],
  27825         soc_genreg,
  27826         1,
  27827         0,
  27828         0x26010300,
  27829         SOC_REG_FLAG_64_BITS,
  27830         0,
  27831         6,
  27832         soc_L3_ENTRY_DBGCTRL3r_fields,
  27833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27835         -1,
  27836         -1,
  27837     },
  27838 #endif /* chips */
  27839 
  27840 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27841     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL40_BCM53570_A0r */
  27842         soc_block_list[5],
  27843         soc_genreg,
  27844         1,
  27845         0,
  27846         0x26011200,
  27847         0,
  27848         0,
  27849         1,
  27850         soc_L3_ENTRY_DBGCTRL40_BCM53570_A0r_fields,
  27851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27852         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27853         -1,
  27854         -1,
  27855     },
  27856 #endif /* chips */
  27857 
  27858 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27859     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL41_BCM53570_A0r */
  27860         soc_block_list[5],
  27861         soc_genreg,
  27862         1,
  27863         0,
  27864         0x26011300,
  27865         0,
  27866         0,
  27867         1,
  27868         soc_L3_ENTRY_DBGCTRL41_BCM53570_A0r_fields,
  27869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27870         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27871         -1,
  27872         -1,
  27873     },
  27874 #endif /* chips */
  27875 
  27876 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  27877     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL4_BCM56260_A0r */
  27878         soc_block_list[5],
  27879         soc_genreg,
  27880         1,
  27881         0,
  27882         0x26010400,
  27883         SOC_REG_FLAG_64_BITS,
  27884         0,
  27885         3,
  27886         soc_L3_ENTRY_DBGCTRL4_BCM56260_A0r_fields,
  27887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27888         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27889         -1,
  27890         -1,
  27891     },
  27892 #endif /* chips */
  27893 
  27894 #if defined(BCM_56270_A0)
  27895     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL4_BCM56270_A0r */
  27896         soc_block_list[5],
  27897         soc_genreg,
  27898         1,
  27899         0,
  27900         0x26010400,
  27901         SOC_REG_FLAG_64_BITS,
  27902         0,
  27903         3,
  27904         soc_L3_ENTRY_DBGCTRL4_BCM56270_A0r_fields,
  27905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27906         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27907         -1,
  27908         -1,
  27909     },
  27910 #endif /* chips */
  27911 
  27912 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27913     defined(BCM_56450_B1)
  27914     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL4_BCM56450_A0r */
  27915         soc_block_list[5],
  27916         soc_genreg,
  27917         1,
  27918         0,
  27919         0x26010400,
  27920         SOC_REG_FLAG_64_BITS,
  27921         0,
  27922         6,
  27923         soc_L3_ENTRY_DBGCTRL4r_fields,
  27924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27926         -1,
  27927         -1,
  27928     },
  27929 #endif /* chips */
  27930 
  27931 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27932     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL50_BCM53570_A0r */
  27933         soc_block_list[5],
  27934         soc_genreg,
  27935         1,
  27936         0,
  27937         0x26011400,
  27938         0,
  27939         0,
  27940         1,
  27941         soc_L3_ENTRY_DBGCTRL50_BCM53570_A0r_fields,
  27942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27943         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27944         -1,
  27945         -1,
  27946     },
  27947 #endif /* chips */
  27948 
  27949 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27950     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL51_BCM53570_A0r */
  27951         soc_block_list[5],
  27952         soc_genreg,
  27953         1,
  27954         0,
  27955         0x26011500,
  27956         0,
  27957         0,
  27958         1,
  27959         soc_L3_ENTRY_DBGCTRL51_BCM53570_A0r_fields,
  27960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27961         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27962         -1,
  27963         -1,
  27964     },
  27965 #endif /* chips */
  27966 
  27967 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  27968     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL5_BCM56260_A0r */
  27969         soc_block_list[5],
  27970         soc_genreg,
  27971         1,
  27972         0,
  27973         0x26010500,
  27974         0,
  27975         0,
  27976         1,
  27977         soc_L3_ENTRY_DBGCTRL5_BCM56260_A0r_fields,
  27978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27979         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27980         -1,
  27981         -1,
  27982     },
  27983 #endif /* chips */
  27984 
  27985 #if defined(BCM_56270_A0)
  27986     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL5_BCM56270_A0r */
  27987         soc_block_list[5],
  27988         soc_genreg,
  27989         1,
  27990         0,
  27991         0x26010500,
  27992         0,
  27993         0,
  27994         1,
  27995         soc_L3_ENTRY_DBGCTRL5_BCM56270_A0r_fields,
  27996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27997         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27998         -1,
  27999         -1,
  28000     },
  28001 #endif /* chips */
  28002 
  28003 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  28004     defined(BCM_56450_B1)
  28005     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL5_BCM56450_A0r */
  28006         soc_block_list[5],
  28007         soc_genreg,
  28008         1,
  28009         0,
  28010         0x26010500,
  28011         0,
  28012         0,
  28013         2,
  28014         soc_L3_ENTRY_DBGCTRL5_BCM56450_A0r_fields,
  28015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28016         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28017         -1,
  28018         -1,
  28019     },
  28020 #endif /* chips */
  28021 
  28022 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  28023     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL60_BCM53570_A0r */
  28024         soc_block_list[5],
  28025         soc_genreg,
  28026         1,
  28027         0,
  28028         0x26011600,
  28029         0,
  28030         0,
  28031         1,
  28032         soc_L3_ENTRY_DBGCTRL60_BCM53570_A0r_fields,
  28033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28034         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28035         -1,
  28036         -1,
  28037     },
  28038 #endif /* chips */
  28039 
  28040 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  28041     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL61_BCM53570_A0r */
  28042         soc_block_list[5],
  28043         soc_genreg,
  28044         1,
  28045         0,
  28046         0x26011700,
  28047         0,
  28048         0,
  28049         1,
  28050         soc_L3_ENTRY_DBGCTRL61_BCM53570_A0r_fields,
  28051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28052         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28053         -1,
  28054         -1,
  28055     },
  28056 #endif /* chips */
  28057 
  28058 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  28059     defined(BCM_56270_A0)
  28060     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL6_BCM56260_A0r */
  28061         soc_block_list[5],
  28062         soc_genreg,
  28063         1,
  28064         0,
  28065         0x26010600,
  28066         0,
  28067         0,
  28068         17,
  28069         soc_L3_ENTRY_DBGCTRL6_BCM56260_A0r_fields,
  28070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28072         -1,
  28073         -1,
  28074     },
  28075 #endif /* chips */
  28076 
  28077 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  28078     defined(BCM_56450_B1)
  28079     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL6_BCM56450_A0r */
  28080         soc_block_list[5],
  28081         soc_genreg,
  28082         1,
  28083         0,
  28084         0x26010600,
  28085         0,
  28086         0,
  28087         17,
  28088         soc_L3_ENTRY_DBGCTRL6_BCM56450_A0r_fields,
  28089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28091         -1,
  28092         -1,
  28093     },
  28094 #endif /* chips */
  28095 
  28096 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  28097     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL70_BCM53570_A0r */
  28098         soc_block_list[5],
  28099         soc_genreg,
  28100         1,
  28101         0,
  28102         0x26011800,
  28103         0,
  28104         0,
  28105         1,
  28106         soc_L3_ENTRY_DBGCTRL70_BCM53570_A0r_fields,
  28107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28109         -1,
  28110         -1,
  28111     },
  28112 #endif /* chips */
  28113 
  28114 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  28115     { /* SOC_REG_INT_L3_ENTRY_DBGCTRL71_BCM53570_A0r */
  28116         soc_block_list[5],
  28117         soc_genreg,
  28118         1,
  28119         0,
  28120         0x26011900,
  28121         0,
  28122         0,
  28123         1,
  28124         soc_L3_ENTRY_DBGCTRL71_BCM53570_A0r_fields,
  28125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28126         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28127         -1,
  28128         -1,
  28129     },
  28130 #endif /* chips */
  28131 
  28132 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  28133     defined(BCM_56270_A0)
  28134     { /* SOC_REG_INT_L3_ENTRY_ECC_CONTROLr */
  28135         soc_block_list[5],
  28136         soc_genreg,
  28137         1,
  28138         0,
  28139         0x26010700,
  28140         0,
  28141         0,
  28142         2,
  28143         soc_EGR_MASK_ECC_CONTROLr_fields,
  28144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28145         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28146         -1,
  28147         -1,
  28148     },
  28149 #endif /* chips */
  28150 
  28151 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  28152     { /* SOC_REG_INT_L3_ENTRY_ECC_STATUS_INTR_0r */
  28153         soc_block_list[5],
  28154         soc_genreg,
  28155         1,
  28156         0,
  28157         0x26010800,
  28158         0,
  28159         0,
  28160         4,
  28161         soc_L3_ENTRY_ECC_STATUS_INTR_0r_fields,
  28162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28163         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28164         -1,
  28165         -1,
  28166     },
  28167 #endif /* chips */
  28168 
  28169 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  28170     { /* SOC_REG_INT_L3_ENTRY_ECC_STATUS_INTR_1r */
  28171         soc_block_list[5],
  28172         soc_genreg,
  28173         1,
  28174         0,
  28175         0x26010900,
  28176         0,
  28177         0,
  28178         4,
  28179         soc_L3_ENTRY_ECC_STATUS_INTR_0r_fields,
  28180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28182         -1,
  28183         -1,
  28184     },
  28185 #endif /* chips */
  28186 
  28187 #if defined(BCM_56270_A0)
  28188     { /* SOC_REG_INT_L3_ENTRY_ECC_STATUS_INTR_0_BCM56270_A0r */
  28189         soc_block_list[5],
  28190         soc_genreg,
  28191         1,
  28192         0,
  28193         0x26010800,
  28194         0,
  28195         0,
  28196         4,
  28197         soc_L3_ENTRY_ECC_STATUS_INTR_0_BCM56270_A0r_fields,
  28198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28200         -1,
  28201         -1,
  28202     },
  28203 #endif /* chips */
  28204 
  28205 #if defined(BCM_56270_A0)
  28206     { /* SOC_REG_INT_L3_ENTRY_ECC_STATUS_INTR_1_BCM56270_A0r */
  28207         soc_block_list[5],
  28208         soc_genreg,
  28209         1,
  28210         0,
  28211         0x26010900,
  28212         0,
  28213         0,
  28214         4,
  28215         soc_L3_ENTRY_ECC_STATUS_INTR_0_BCM56270_A0r_fields,
  28216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28217         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28218         -1,
  28219         -1,
  28220     },
  28221 #endif /* chips */
  28222 
  28223 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  28224     { /* SOC_REG_INT_L3_ENTRY_ECC_STATUS_NACK_0r */
  28225         soc_block_list[5],
  28226         soc_genreg,
  28227         1,
  28228         0,
  28229         0x26010a00,
  28230         0,
  28231         0,
  28232         4,
  28233         soc_L3_ENTRY_ECC_STATUS_INTR_0r_fields,
  28234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28235         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28236         -1,
  28237         -1,
  28238     },
  28239 #endif /* chips */
  28240 
  28241 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  28242     { /* SOC_REG_INT_L3_ENTRY_ECC_STATUS_NACK_1r */
  28243         soc_block_list[5],
  28244         soc_genreg,
  28245         1,
  28246         0,
  28247         0x26010b00,
  28248         0,
  28249         0,
  28250         4,
  28251         soc_L3_ENTRY_ECC_STATUS_INTR_0r_fields,
  28252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28253         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28254         -1,
  28255         -1,
  28256     },
  28257 #endif /* chips */
  28258 
  28259 #if defined(BCM_56270_A0)
  28260     { /* SOC_REG_INT_L3_ENTRY_ECC_STATUS_NACK_0_BCM56270_A0r */
  28261         soc_block_list[5],
  28262         soc_genreg,
  28263         1,
  28264         0,
  28265         0x26010a00,
  28266         0,
  28267         0,
  28268         4,
  28269         soc_L3_ENTRY_ECC_STATUS_INTR_0_BCM56270_A0r_fields,
  28270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28272         -1,
  28273         -1,
  28274     },
  28275 #endif /* chips */
  28276 
  28277 #if defined(BCM_56270_A0)
  28278     { /* SOC_REG_INT_L3_ENTRY_ECC_STATUS_NACK_1_BCM56270_A0r */
  28279         soc_block_list[5],
  28280         soc_genreg,
  28281         1,
  28282         0,
  28283         0x26010b00,
  28284         0,
  28285         0,
  28286         4,
  28287         soc_L3_ENTRY_ECC_STATUS_INTR_0_BCM56270_A0r_fields,
  28288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28289         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28290         -1,
  28291         -1,
  28292     },
  28293 #endif /* chips */
  28294 
  28295 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  28296     defined(BCM_56450_B1)
  28297     { /* SOC_REG_INT_L3_ENTRY_LP_CONTROLr */
  28298         soc_block_list[5],
  28299         soc_genreg,
  28300         1,
  28301         0,
  28302         0x26012000,
  28303         0,
  28304         0,
  28305         16,
  28306         soc_L3_ENTRY_LP_CONTROLr_fields,
  28307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28308         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28309         -1,
  28310         -1,
  28311     },
  28312 #endif /* chips */
  28313 
  28314 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  28315     defined(BCM_56270_A0)
  28316     { /* SOC_REG_INT_L3_ENTRY_LP_CONTROL_BCM56260_A0r */
  28317         soc_block_list[5],
  28318         soc_genreg,
  28319         1,
  28320         0,
  28321         0x26012300,
  28322         0,
  28323         0,
  28324         16,
  28325         soc_L3_ENTRY_LP_CONTROL_BCM56260_A0r_fields,
  28326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28328         -1,
  28329         -1,
  28330     },
  28331 #endif /* chips */
  28332 
  28333 #if defined(BCM_56314_A0) || defined(BCM_56504_B0)
  28334     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROLr */
  28335         soc_block_list[5],
  28336         soc_genreg,
  28337         1,
  28338         0,
  28339         0x808000b,
  28340         0,
  28341         0,
  28342         2,
  28343         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  28344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28345         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  28346         -1,
  28347         -1,
  28348     },
  28349 #endif /* chips */
  28350 
  28351 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28352     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28353     defined(BCM_56160_A0)
  28354     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM53400_A0r */
  28355         soc_block_list[5],
  28356         soc_genreg,
  28357         1,
  28358         0,
  28359         0x26011a00,
  28360         0,
  28361         0,
  28362         1,
  28363         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  28364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28365         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  28366         -1,
  28367         -1,
  28368     },
  28369 #endif /* chips */
  28370 
  28371 #if defined(BCM_56142_A0)
  28372     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56142_A0r */
  28373         soc_block_list[5],
  28374         soc_genreg,
  28375         1,
  28376         0,
  28377         0xa080156,
  28378         0,
  28379         0,
  28380         1,
  28381         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  28382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28383         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  28384         -1,
  28385         -1,
  28386     },
  28387 #endif /* chips */
  28388 
  28389 #if defined(BCM_56150_A0)
  28390     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56150_A0r */
  28391         soc_block_list[5],
  28392         soc_genreg,
  28393         1,
  28394         0,
  28395         0x2a010d00,
  28396         0,
  28397         0,
  28398         1,
  28399         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  28400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28401         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  28402         -1,
  28403         -1,
  28404     },
  28405 #endif /* chips */
  28406 
  28407 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  28408     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56224_A0r */
  28409         soc_block_list[5],
  28410         soc_genreg,
  28411         1,
  28412         0,
  28413         0x8080005,
  28414         0,
  28415         0,
  28416         2,
  28417         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  28418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28419         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  28420         -1,
  28421         -1,
  28422     },
  28423 #endif /* chips */
  28424 
  28425 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  28426     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56334_A0r */
  28427         soc_block_list[5],
  28428         soc_genreg,
  28429         1,
  28430         0,
  28431         0xa080172,
  28432         0,
  28433         0,
  28434         1,
  28435         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  28436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28437         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  28438         -1,
  28439         -1,
  28440     },
  28441 #endif /* chips */
  28442 
  28443 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  28444     defined(BCM_56450_B1)
  28445     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56450_A0r */
  28446         soc_block_list[5],
  28447         soc_genreg,
  28448         1,
  28449         0,
  28450         0x26010700,
  28451         0,
  28452         0,
  28453         1,
  28454         soc_FT_CNTR_SER_CONTROLr_fields,
  28455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28456         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28457         -1,
  28458         -1,
  28459     },
  28460 #endif /* chips */
  28461 
  28462 #if defined(BCM_56514_A0)
  28463     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56514_A0r */
  28464         soc_block_list[5],
  28465         soc_genreg,
  28466         1,
  28467         0,
  28468         0x808000c,
  28469         0,
  28470         0,
  28471         2,
  28472         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  28473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28474         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  28475         -1,
  28476         -1,
  28477     },
  28478 #endif /* chips */
  28479 
  28480 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  28481     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56560_A0r */
  28482         soc_block_list[5],
  28483         soc_genreg,
  28484         1,
  28485         0,
  28486         0x2b000000,
  28487         0,
  28488         0,
  28489         10,
  28490         soc_L3_ENTRY_PARITY_CONTROL_BCM56560_A0r_fields,
  28491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28492         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28493         -1,
  28494         -1,
  28495     },
  28496 #endif /* chips */
  28497 
  28498 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  28499     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  28500     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56624_A0r */
  28501         soc_block_list[5],
  28502         soc_genreg,
  28503         1,
  28504         0,
  28505         0xa08014d,
  28506         0,
  28507         0,
  28508         1,
  28509         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  28510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28511         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  28512         -1,
  28513         -1,
  28514     },
  28515 #endif /* chips */
  28516 
  28517 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  28518     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  28519     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  28520     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56634_A0r */
  28521         soc_block_list[5],
  28522         soc_genreg,
  28523         1,
  28524         0,
  28525         0x90801ae,
  28526         0,
  28527         0,
  28528         1,
  28529         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  28530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28531         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  28532         -1,
  28533         -1,
  28534     },
  28535 #endif /* chips */
  28536 
  28537 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  28538     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56670_A0r */
  28539         soc_block_list[5],
  28540         soc_genreg,
  28541         1,
  28542         0,
  28543         0x2b010000,
  28544         0,
  28545         0,
  28546         10,
  28547         soc_L3_ENTRY_PARITY_CONTROL_BCM56560_A0r_fields,
  28548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28549         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28550         -1,
  28551         -1,
  28552     },
  28553 #endif /* chips */
  28554 
  28555 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  28556     defined(BCM_56820_A0)
  28557     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56800_A0r */
  28558         soc_block_list[5],
  28559         soc_genreg,
  28560         1,
  28561         0,
  28562         0x808020c,
  28563         0,
  28564         0,
  28565         2,
  28566         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  28567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28568         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  28569         -1,
  28570         -1,
  28571     },
  28572 #endif /* chips */
  28573 
  28574 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  28575     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  28576     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56840_A0r */
  28577         soc_block_list[5],
  28578         soc_genreg,
  28579         1,
  28580         0,
  28581         0x9080d07,
  28582         0,
  28583         0,
  28584         1,
  28585         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  28586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28587         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28588         -1,
  28589         -1,
  28590     },
  28591 #endif /* chips */
  28592 
  28593 #if defined(BCM_56850_A0)
  28594     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56850_A0r */
  28595         soc_block_list[5],
  28596         soc_genreg,
  28597         1,
  28598         0,
  28599         0x27000000,
  28600         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  28601         0,
  28602         7,
  28603         soc_L3_ENTRY_PARITY_CONTROLr_fields,
  28604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28605         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28606         -1,
  28607         -1,
  28608     },
  28609 #endif /* chips */
  28610 
  28611 #if defined(BCM_56860_A0)
  28612     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56860_A0r */
  28613         soc_block_list[5],
  28614         soc_genreg,
  28615         1,
  28616         0,
  28617         0x2b000000,
  28618         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  28619         0,
  28620         8,
  28621         soc_L3_ENTRY_PARITY_CONTROL_BCM56860_A0r_fields,
  28622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28623         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28624         -1,
  28625         -1,
  28626     },
  28627 #endif /* chips */
  28628 
  28629 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  28630     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56960_A0r */
  28631         soc_block_list[5],
  28632         soc_genreg,
  28633         1,
  28634         0,
  28635         0x3b170000,
  28636         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  28637         0,
  28638         4,
  28639         soc_L3_ENTRY_PARITY_CONTROL_BCM56960_A0r_fields,
  28640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28641         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28642         -1,
  28643         -1,
  28644         3,
  28645     },
  28646 #endif /* chips */
  28647 
  28648 #if defined(BCM_56970_A0)
  28649     { /* SOC_REG_INT_L3_ENTRY_PARITY_CONTROL_BCM56970_A0r */
  28650         soc_block_list[5],
  28651         soc_genreg,
  28652         1,
  28653         0,
  28654         0x5f160000,
  28655         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  28656         0,
  28657         4,
  28658         soc_L3_ENTRY_PARITY_CONTROL_BCM56960_A0r_fields,
  28659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28661         -1,
  28662         -1,
  28663         3,
  28664     },
  28665 #endif /* chips */
  28666 
  28667 #if defined(BCM_56504_B0)
  28668     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUSr */
  28669         soc_block_list[5],
  28670         soc_genreg,
  28671         1,
  28672         0,
  28673         0x808000c,
  28674         SOC_REG_FLAG_RO,
  28675         0,
  28676         3,
  28677         soc_L3_ENTRY_PARITY_STATUSr_fields,
  28678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28679         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  28680         -1,
  28681         -1,
  28682     },
  28683 #endif /* chips */
  28684 
  28685 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  28686     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  28687     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_0r */
  28688         soc_block_list[5],
  28689         soc_genreg,
  28690         1,
  28691         0,
  28692         0xa08014e,
  28693         0,
  28694         0,
  28695         3,
  28696         soc_L3_ENTRY_PARITY_STATUS_0r_fields,
  28697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28698         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  28699         -1,
  28700         -1,
  28701     },
  28702 #endif /* chips */
  28703 
  28704 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  28705     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  28706     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_1r */
  28707         soc_block_list[5],
  28708         soc_genreg,
  28709         1,
  28710         0,
  28711         0xa08014f,
  28712         0,
  28713         0,
  28714         3,
  28715         soc_L3_ENTRY_PARITY_STATUS_1r_fields,
  28716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28717         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  28718         -1,
  28719         -1,
  28720     },
  28721 #endif /* chips */
  28722 
  28723 #if defined(BCM_53400_A0) || defined(BCM_53540_A0)
  28724     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_0_BCM53400_A0r */
  28725         soc_block_list[5],
  28726         soc_genreg,
  28727         1,
  28728         0,
  28729         0x26011b00,
  28730         0,
  28731         0,
  28732         3,
  28733         soc_L3_ENTRY_PARITY_STATUS_0_BCM53400_A0r_fields,
  28734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28735         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  28736         -1,
  28737         -1,
  28738     },
  28739 #endif /* chips */
  28740 
  28741 #if defined(BCM_53570_B0)
  28742     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_0_BCM53570_B0r */
  28743         soc_block_list[5],
  28744         soc_genreg,
  28745         1,
  28746         0,
  28747         0x26011b00,
  28748         0,
  28749         0,
  28750         3,
  28751         soc_L3_ENTRY_PARITY_STATUS_0_BCM53570_B0r_fields,
  28752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28753         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  28754         -1,
  28755         -1,
  28756     },
  28757 #endif /* chips */
  28758 
  28759 #if defined(BCM_56142_A0)
  28760     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_0_BCM56142_A0r */
  28761         soc_block_list[5],
  28762         soc_genreg,
  28763         1,
  28764         0,
  28765         0xa080157,
  28766         0,
  28767         0,
  28768         3,
  28769         soc_L3_ENTRY_PARITY_STATUS_0_BCM56142_A0r_fields,
  28770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28771         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  28772         -1,
  28773         -1,
  28774     },
  28775 #endif /* chips */
  28776 
  28777 #if defined(BCM_56150_A0)
  28778     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_0_BCM56150_A0r */
  28779         soc_block_list[5],
  28780         soc_genreg,
  28781         1,
  28782         0,
  28783         0x2a010e00,
  28784         0,
  28785         0,
  28786         3,
  28787         soc_L3_ENTRY_PARITY_STATUS_0_BCM56150_A0r_fields,
  28788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28789         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  28790         -1,
  28791         -1,
  28792     },
  28793 #endif /* chips */
  28794 
  28795 #if defined(BCM_53570_A0) || defined(BCM_56160_A0)
  28796     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_0_BCM56160_A0r */
  28797         soc_block_list[5],
  28798         soc_genreg,
  28799         1,
  28800         0,
  28801         0x26011b00,
  28802         0,
  28803         0,
  28804         3,
  28805         soc_L3_ENTRY_PARITY_STATUS_0_BCM56160_A0r_fields,
  28806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28807         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28808         -1,
  28809         -1,
  28810     },
  28811 #endif /* chips */
  28812 
  28813 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  28814     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_0_BCM56334_A0r */
  28815         soc_block_list[5],
  28816         soc_genreg,
  28817         1,
  28818         0,
  28819         0xa080173,
  28820         0,
  28821         0,
  28822         3,
  28823         soc_L3_ENTRY_PARITY_STATUS_0_BCM56334_A0r_fields,
  28824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28825         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28826         -1,
  28827         -1,
  28828     },
  28829 #endif /* chips */
  28830 
  28831 #if defined(BCM_53400_A0) || defined(BCM_53540_A0)
  28832     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_1_BCM53400_A0r */
  28833         soc_block_list[5],
  28834         soc_genreg,
  28835         1,
  28836         0,
  28837         0x26011c00,
  28838         0,
  28839         0,
  28840         3,
  28841         soc_L3_ENTRY_PARITY_STATUS_1_BCM53400_A0r_fields,
  28842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28843         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  28844         -1,
  28845         -1,
  28846     },
  28847 #endif /* chips */
  28848 
  28849 #if defined(BCM_53570_B0)
  28850     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_1_BCM53570_B0r */
  28851         soc_block_list[5],
  28852         soc_genreg,
  28853         1,
  28854         0,
  28855         0x26011c00,
  28856         0,
  28857         0,
  28858         3,
  28859         soc_L3_ENTRY_PARITY_STATUS_1_BCM53570_B0r_fields,
  28860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28861         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  28862         -1,
  28863         -1,
  28864     },
  28865 #endif /* chips */
  28866 
  28867 #if defined(BCM_56142_A0)
  28868     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_1_BCM56142_A0r */
  28869         soc_block_list[5],
  28870         soc_genreg,
  28871         1,
  28872         0,
  28873         0xa080158,
  28874         0,
  28875         0,
  28876         3,
  28877         soc_L3_ENTRY_PARITY_STATUS_1_BCM56142_A0r_fields,
  28878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28879         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  28880         -1,
  28881         -1,
  28882     },
  28883 #endif /* chips */
  28884 
  28885 #if defined(BCM_56150_A0)
  28886     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_1_BCM56150_A0r */
  28887         soc_block_list[5],
  28888         soc_genreg,
  28889         1,
  28890         0,
  28891         0x2a010f00,
  28892         0,
  28893         0,
  28894         3,
  28895         soc_L3_ENTRY_PARITY_STATUS_1_BCM56150_A0r_fields,
  28896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28897         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  28898         -1,
  28899         -1,
  28900     },
  28901 #endif /* chips */
  28902 
  28903 #if defined(BCM_53570_A0) || defined(BCM_56160_A0)
  28904     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_1_BCM56160_A0r */
  28905         soc_block_list[5],
  28906         soc_genreg,
  28907         1,
  28908         0,
  28909         0x26011c00,
  28910         0,
  28911         0,
  28912         3,
  28913         soc_L3_ENTRY_PARITY_STATUS_1_BCM56160_A0r_fields,
  28914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28915         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28916         -1,
  28917         -1,
  28918     },
  28919 #endif /* chips */
  28920 
  28921 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  28922     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_1_BCM56334_A0r */
  28923         soc_block_list[5],
  28924         soc_genreg,
  28925         1,
  28926         0,
  28927         0xa080174,
  28928         0,
  28929         0,
  28930         3,
  28931         soc_L3_ENTRY_PARITY_STATUS_1_BCM56334_A0r_fields,
  28932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28933         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28934         -1,
  28935         -1,
  28936     },
  28937 #endif /* chips */
  28938 
  28939 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  28940     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_BCM56224_A0r */
  28941         soc_block_list[5],
  28942         soc_genreg,
  28943         1,
  28944         0,
  28945         0x8080006,
  28946         SOC_REG_FLAG_RO,
  28947         0,
  28948         3,
  28949         soc_L3_ENTRY_PARITY_STATUS_BCM56224_A0r_fields,
  28950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28951         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  28952         -1,
  28953         -1,
  28954     },
  28955 #endif /* chips */
  28956 
  28957 #if defined(BCM_56314_A0)
  28958     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_BCM56314_A0r */
  28959         soc_block_list[5],
  28960         soc_genreg,
  28961         1,
  28962         0,
  28963         0x808000c,
  28964         SOC_REG_FLAG_RO,
  28965         0,
  28966         3,
  28967         soc_L3_ENTRY_PARITY_STATUS_BCM56314_A0r_fields,
  28968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28969         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  28970         -1,
  28971         -1,
  28972     },
  28973 #endif /* chips */
  28974 
  28975 #if defined(BCM_56514_A0)
  28976     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_BCM56514_A0r */
  28977         soc_block_list[5],
  28978         soc_genreg,
  28979         1,
  28980         0,
  28981         0x808000d,
  28982         SOC_REG_FLAG_RO,
  28983         0,
  28984         3,
  28985         soc_L3_ENTRY_PARITY_STATUSr_fields,
  28986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28987         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  28988         -1,
  28989         -1,
  28990     },
  28991 #endif /* chips */
  28992 
  28993 #if defined(BCM_56800_A0)
  28994     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_BCM56800_A0r */
  28995         soc_block_list[5],
  28996         soc_genreg,
  28997         1,
  28998         0,
  28999         0x808020d,
  29000         SOC_REG_FLAG_RO,
  29001         0,
  29002         3,
  29003         soc_L3_ENTRY_PARITY_STATUS_BCM56800_A0r_fields,
  29004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29005         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  29006         -1,
  29007         -1,
  29008     },
  29009 #endif /* chips */
  29010 
  29011 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  29012     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_BCM56820_A0r */
  29013         soc_block_list[5],
  29014         soc_genreg,
  29015         1,
  29016         0,
  29017         0x808020d,
  29018         SOC_REG_FLAG_RO,
  29019         0,
  29020         3,
  29021         soc_L2_ENTRY_PARITY_STATUSr_fields,
  29022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29023         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  29024         -1,
  29025         -1,
  29026     },
  29027 #endif /* chips */
  29028 
  29029 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  29030     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  29031     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  29032     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_INTR_0r */
  29033         soc_block_list[5],
  29034         soc_genreg,
  29035         1,
  29036         0,
  29037         0x90801af,
  29038         0,
  29039         0,
  29040         3,
  29041         soc_L3_ENTRY_PARITY_STATUS_INTR_0r_fields,
  29042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29043         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  29044         -1,
  29045         -1,
  29046     },
  29047 #endif /* chips */
  29048 
  29049 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  29050     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  29051     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  29052     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_INTR_1r */
  29053         soc_block_list[5],
  29054         soc_genreg,
  29055         1,
  29056         0,
  29057         0x90801b0,
  29058         0,
  29059         0,
  29060         3,
  29061         soc_L3_ENTRY_PARITY_STATUS_INTR_0r_fields,
  29062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29063         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  29064         -1,
  29065         -1,
  29066     },
  29067 #endif /* chips */
  29068 
  29069 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29070     defined(BCM_56450_B1)
  29071     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56450_A0r */
  29072         soc_block_list[5],
  29073         soc_genreg,
  29074         1,
  29075         0,
  29076         0x26010800,
  29077         0,
  29078         0,
  29079         3,
  29080         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56450_A0r_fields,
  29081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29082         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29083         -1,
  29084         -1,
  29085     },
  29086 #endif /* chips */
  29087 
  29088 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  29089     defined(BCM_56840_A0)
  29090     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r */
  29091         soc_block_list[5],
  29092         soc_genreg,
  29093         1,
  29094         0,
  29095         0x9080d08,
  29096         0,
  29097         0,
  29098         3,
  29099         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
  29100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29101         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29102         -1,
  29103         -1,
  29104     },
  29105 #endif /* chips */
  29106 
  29107 #if defined(BCM_56840_B0)
  29108     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_B0r */
  29109         soc_block_list[5],
  29110         soc_genreg,
  29111         1,
  29112         0,
  29113         0x9080d08,
  29114         0,
  29115         0,
  29116         3,
  29117         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_B0r_fields,
  29118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29119         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29120         -1,
  29121         -1,
  29122     },
  29123 #endif /* chips */
  29124 
  29125 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29126     defined(BCM_56450_B1)
  29127     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_INTR_1_BCM56450_A0r */
  29128         soc_block_list[5],
  29129         soc_genreg,
  29130         1,
  29131         0,
  29132         0x26010900,
  29133         0,
  29134         0,
  29135         3,
  29136         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56450_A0r_fields,
  29137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29138         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29139         -1,
  29140         -1,
  29141     },
  29142 #endif /* chips */
  29143 
  29144 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  29145     defined(BCM_56840_A0)
  29146     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_INTR_1_BCM56840_A0r */
  29147         soc_block_list[5],
  29148         soc_genreg,
  29149         1,
  29150         0,
  29151         0x9080d09,
  29152         0,
  29153         0,
  29154         3,
  29155         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
  29156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29157         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29158         -1,
  29159         -1,
  29160     },
  29161 #endif /* chips */
  29162 
  29163 #if defined(BCM_56840_B0)
  29164     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_INTR_1_BCM56840_B0r */
  29165         soc_block_list[5],
  29166         soc_genreg,
  29167         1,
  29168         0,
  29169         0x9080d09,
  29170         0,
  29171         0,
  29172         3,
  29173         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_B0r_fields,
  29174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29175         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29176         -1,
  29177         -1,
  29178     },
  29179 #endif /* chips */
  29180 
  29181 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  29182     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  29183     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  29184     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_NACK_0r */
  29185         soc_block_list[5],
  29186         soc_genreg,
  29187         1,
  29188         0,
  29189         0x90801b1,
  29190         0,
  29191         0,
  29192         3,
  29193         soc_L3_ENTRY_PARITY_STATUS_INTR_0r_fields,
  29194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29195         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  29196         -1,
  29197         -1,
  29198     },
  29199 #endif /* chips */
  29200 
  29201 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  29202     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  29203     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  29204     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_NACK_1r */
  29205         soc_block_list[5],
  29206         soc_genreg,
  29207         1,
  29208         0,
  29209         0x90801b2,
  29210         0,
  29211         0,
  29212         3,
  29213         soc_L3_ENTRY_PARITY_STATUS_INTR_0r_fields,
  29214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29215         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  29216         -1,
  29217         -1,
  29218     },
  29219 #endif /* chips */
  29220 
  29221 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29222     defined(BCM_56450_B1)
  29223     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_NACK_0_BCM56450_A0r */
  29224         soc_block_list[5],
  29225         soc_genreg,
  29226         1,
  29227         0,
  29228         0x26010a00,
  29229         0,
  29230         0,
  29231         3,
  29232         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56450_A0r_fields,
  29233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29234         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29235         -1,
  29236         -1,
  29237     },
  29238 #endif /* chips */
  29239 
  29240 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  29241     defined(BCM_56840_A0)
  29242     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_NACK_0_BCM56840_A0r */
  29243         soc_block_list[5],
  29244         soc_genreg,
  29245         1,
  29246         0,
  29247         0x9080d0a,
  29248         0,
  29249         0,
  29250         3,
  29251         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
  29252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29253         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29254         -1,
  29255         -1,
  29256     },
  29257 #endif /* chips */
  29258 
  29259 #if defined(BCM_56840_B0)
  29260     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_NACK_0_BCM56840_B0r */
  29261         soc_block_list[5],
  29262         soc_genreg,
  29263         1,
  29264         0,
  29265         0x9080d0a,
  29266         0,
  29267         0,
  29268         3,
  29269         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_B0r_fields,
  29270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29272         -1,
  29273         -1,
  29274     },
  29275 #endif /* chips */
  29276 
  29277 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29278     defined(BCM_56450_B1)
  29279     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_NACK_1_BCM56450_A0r */
  29280         soc_block_list[5],
  29281         soc_genreg,
  29282         1,
  29283         0,
  29284         0x26010b00,
  29285         0,
  29286         0,
  29287         3,
  29288         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56450_A0r_fields,
  29289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29290         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29291         -1,
  29292         -1,
  29293     },
  29294 #endif /* chips */
  29295 
  29296 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  29297     defined(BCM_56840_A0)
  29298     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_NACK_1_BCM56840_A0r */
  29299         soc_block_list[5],
  29300         soc_genreg,
  29301         1,
  29302         0,
  29303         0x9080d0b,
  29304         0,
  29305         0,
  29306         3,
  29307         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
  29308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29309         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29310         -1,
  29311         -1,
  29312     },
  29313 #endif /* chips */
  29314 
  29315 #if defined(BCM_56840_B0)
  29316     { /* SOC_REG_INT_L3_ENTRY_PARITY_STATUS_NACK_1_BCM56840_B0r */
  29317         soc_block_list[5],
  29318         soc_genreg,
  29319         1,
  29320         0,
  29321         0x9080d0b,
  29322         0,
  29323         0,
  29324         3,
  29325         soc_L3_ENTRY_PARITY_STATUS_INTR_0_BCM56840_B0r_fields,
  29326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29328         -1,
  29329         -1,
  29330     },
  29331 #endif /* chips */
  29332 
  29333 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29334     defined(BCM_56504_B0)
  29335     { /* SOC_REG_INT_L3_HIT_DEBUGr */
  29336         soc_block_list[5],
  29337         soc_genreg,
  29338         1,
  29339         0,
  29340         0xb080007,
  29341         0,
  29342         0,
  29343         2,
  29344         soc_L3_HIT_DEBUGr_fields,
  29345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29346         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29347         -1,
  29348         -1,
  29349     },
  29350 #endif /* chips */
  29351 
  29352 #if defined(BCM_56514_A0)
  29353     { /* SOC_REG_INT_L3_HIT_DEBUG_BCM56514_A0r */
  29354         soc_block_list[5],
  29355         soc_genreg,
  29356         1,
  29357         0,
  29358         0xb080007,
  29359         0,
  29360         0,
  29361         6,
  29362         soc_L3_HIT_DEBUG_BCM56514_A0r_fields,
  29363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29364         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29365         -1,
  29366         -1,
  29367     },
  29368 #endif /* chips */
  29369 
  29370 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  29371     { /* SOC_REG_INT_L3_IIF_DBGCTRLr */
  29372         soc_block_list[5],
  29373         soc_genreg,
  29374         1,
  29375         0,
  29376         0x12010200,
  29377         0,
  29378         0,
  29379         1,
  29380         soc_E2EFC_MEM_TMr_fields,
  29381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29382         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29383         -1,
  29384         -1,
  29385     },
  29386 #endif /* chips */
  29387 
  29388 #if defined(BCM_53570_A0)
  29389     { /* SOC_REG_INT_L3_IIF_DBGCTRL_BCM53570_A0r */
  29390         soc_block_list[5],
  29391         soc_genreg,
  29392         1,
  29393         0,
  29394         0x12010900,
  29395         0,
  29396         0,
  29397         1,
  29398         soc_E2EFC_MEM_TMr_fields,
  29399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29400         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29401         -1,
  29402         -1,
  29403     },
  29404 #endif /* chips */
  29405 
  29406 #if defined(BCM_53570_B0)
  29407     { /* SOC_REG_INT_L3_IIF_DBGCTRL_BCM53570_B0r */
  29408         soc_block_list[5],
  29409         soc_genreg,
  29410         1,
  29411         0,
  29412         0x12010900,
  29413         0,
  29414         0,
  29415         1,
  29416         soc_DSCP_CONTROLr_fields,
  29417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29418         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29419         -1,
  29420         -1,
  29421     },
  29422 #endif /* chips */
  29423 
  29424 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  29425     defined(BCM_56270_A0)
  29426     { /* SOC_REG_INT_L3_IIF_ECC_CONTROLr */
  29427         soc_block_list[5],
  29428         soc_genreg,
  29429         1,
  29430         0,
  29431         0x16011000,
  29432         0,
  29433         0,
  29434         2,
  29435         soc_EGR_MASK_ECC_CONTROLr_fields,
  29436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29438         -1,
  29439         -1,
  29440     },
  29441 #endif /* chips */
  29442 
  29443 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  29444     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  29445     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROLr */
  29446         soc_block_list[5],
  29447         soc_genreg,
  29448         1,
  29449         0,
  29450         0x6080128,
  29451         0,
  29452         0,
  29453         1,
  29454         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  29455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29456         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29457         -1,
  29458         -1,
  29459     },
  29460 #endif /* chips */
  29461 
  29462 #if defined(BCM_53570_A0)
  29463     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM53570_A0r */
  29464         soc_block_list[5],
  29465         soc_genreg,
  29466         1,
  29467         0,
  29468         0x12010e00,
  29469         0,
  29470         0,
  29471         1,
  29472         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  29473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29474         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29475         -1,
  29476         -1,
  29477     },
  29478 #endif /* chips */
  29479 
  29480 #if defined(BCM_53570_B0)
  29481     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM53570_B0r */
  29482         soc_block_list[5],
  29483         soc_genreg,
  29484         1,
  29485         0,
  29486         0x12010f00,
  29487         0,
  29488         0,
  29489         1,
  29490         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  29491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29492         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29493         -1,
  29494         -1,
  29495     },
  29496 #endif /* chips */
  29497 
  29498 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  29499     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM56160_A0r */
  29500         soc_block_list[5],
  29501         soc_genreg,
  29502         1,
  29503         0,
  29504         0x12010700,
  29505         0,
  29506         0,
  29507         1,
  29508         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  29509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29510         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29511         -1,
  29512         -1,
  29513     },
  29514 #endif /* chips */
  29515 
  29516 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  29517     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM56334_A0r */
  29518         soc_block_list[5],
  29519         soc_genreg,
  29520         1,
  29521         0,
  29522         0x6080141,
  29523         0,
  29524         0,
  29525         1,
  29526         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  29527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29528         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29529         -1,
  29530         -1,
  29531     },
  29532 #endif /* chips */
  29533 
  29534 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29535     defined(BCM_56450_B1)
  29536     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM56450_A0r */
  29537         soc_block_list[5],
  29538         soc_genreg,
  29539         1,
  29540         0,
  29541         0x16010f00,
  29542         0,
  29543         0,
  29544         1,
  29545         soc_FT_CNTR_SER_CONTROLr_fields,
  29546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29547         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29548         -1,
  29549         -1,
  29550     },
  29551 #endif /* chips */
  29552 
  29553 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  29554     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  29555     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM56560_A0r */
  29556         soc_block_list[5],
  29557         soc_genreg,
  29558         1,
  29559         0,
  29560         0x17090000,
  29561         0,
  29562         0,
  29563         1,
  29564         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  29565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29566         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29567         -1,
  29568         -1,
  29569     },
  29570 #endif /* chips */
  29571 
  29572 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  29573     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  29574     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  29575     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM56634_A0r */
  29576         soc_block_list[5],
  29577         soc_genreg,
  29578         1,
  29579         0,
  29580         0x5080169,
  29581         0,
  29582         0,
  29583         1,
  29584         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  29585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29586         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29587         -1,
  29588         -1,
  29589     },
  29590 #endif /* chips */
  29591 
  29592 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  29593     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  29594     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM56840_A0r */
  29595         soc_block_list[5],
  29596         soc_genreg,
  29597         1,
  29598         0,
  29599         0x5080d0f,
  29600         0,
  29601         0,
  29602         1,
  29603         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  29604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29605         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29606         -1,
  29607         -1,
  29608     },
  29609 #endif /* chips */
  29610 
  29611 #if defined(BCM_56850_A0)
  29612     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM56850_A0r */
  29613         soc_block_list[5],
  29614         soc_genreg,
  29615         1,
  29616         0,
  29617         0x17060000,
  29618         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  29619         0,
  29620         1,
  29621         soc_FT_CNTR_SER_CONTROLr_fields,
  29622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29623         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29624         -1,
  29625         -1,
  29626     },
  29627 #endif /* chips */
  29628 
  29629 #if defined(BCM_56860_A0)
  29630     { /* SOC_REG_INT_L3_IIF_PARITY_CONTROL_BCM56860_A0r */
  29631         soc_block_list[5],
  29632         soc_genreg,
  29633         1,
  29634         0,
  29635         0x17090000,
  29636         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  29637         0,
  29638         1,
  29639         soc_FT_CNTR_SER_CONTROLr_fields,
  29640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29641         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29642         -1,
  29643         -1,
  29644     },
  29645 #endif /* chips */
  29646 
  29647 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  29648     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  29649     { /* SOC_REG_INT_L3_IIF_PARITY_STATUSr */
  29650         soc_block_list[5],
  29651         soc_genreg,
  29652         1,
  29653         0,
  29654         0x6080129,
  29655         0,
  29656         0,
  29657         3,
  29658         soc_EGR_MASK_PARITY_STATUSr_fields,
  29659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29660         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  29661         -1,
  29662         -1,
  29663     },
  29664 #endif /* chips */
  29665 
  29666 #if defined(BCM_53540_A0)
  29667     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_BCM53540_A0r */
  29668         soc_block_list[5],
  29669         soc_genreg,
  29670         1,
  29671         0,
  29672         0x12010800,
  29673         0,
  29674         0,
  29675         3,
  29676         soc_EGR_CM_DBITS_PARITY_STATUS_BCM53400_A0r_fields,
  29677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29678         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  29679         -1,
  29680         -1,
  29681     },
  29682 #endif /* chips */
  29683 
  29684 #if defined(BCM_53570_A0)
  29685     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_BCM53570_A0r */
  29686         soc_block_list[5],
  29687         soc_genreg,
  29688         1,
  29689         0,
  29690         0x12010f00,
  29691         0,
  29692         0,
  29693         3,
  29694         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
  29695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29696         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  29697         -1,
  29698         -1,
  29699     },
  29700 #endif /* chips */
  29701 
  29702 #if defined(BCM_53570_B0)
  29703     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_BCM53570_B0r */
  29704         soc_block_list[5],
  29705         soc_genreg,
  29706         1,
  29707         0,
  29708         0x12011000,
  29709         0,
  29710         0,
  29711         3,
  29712         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  29713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29714         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  29715         -1,
  29716         -1,
  29717     },
  29718 #endif /* chips */
  29719 
  29720 #if defined(BCM_56160_A0)
  29721     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_BCM56160_A0r */
  29722         soc_block_list[5],
  29723         soc_genreg,
  29724         1,
  29725         0,
  29726         0x12010800,
  29727         0,
  29728         0,
  29729         3,
  29730         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
  29731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29732         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  29733         -1,
  29734         -1,
  29735     },
  29736 #endif /* chips */
  29737 
  29738 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  29739     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  29740     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  29741     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_INTRr */
  29742         soc_block_list[5],
  29743         soc_genreg,
  29744         1,
  29745         0,
  29746         0x508016a,
  29747         0,
  29748         0,
  29749         3,
  29750         soc_EGR_MASK_PARITY_STATUSr_fields,
  29751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29752         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  29753         -1,
  29754         -1,
  29755     },
  29756 #endif /* chips */
  29757 
  29758 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  29759     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_INTR_BCM56334_A0r */
  29760         soc_block_list[5],
  29761         soc_genreg,
  29762         1,
  29763         0,
  29764         0x6080142,
  29765         0,
  29766         0,
  29767         3,
  29768         soc_EGR_MASK_PARITY_STATUSr_fields,
  29769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29770         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  29771         -1,
  29772         -1,
  29773     },
  29774 #endif /* chips */
  29775 
  29776 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29777     defined(BCM_56450_B1)
  29778     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_INTR_BCM56450_A0r */
  29779         soc_block_list[5],
  29780         soc_genreg,
  29781         1,
  29782         0,
  29783         0x16011000,
  29784         0,
  29785         0,
  29786         3,
  29787         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  29788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29790         -1,
  29791         -1,
  29792     },
  29793 #endif /* chips */
  29794 
  29795 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  29796     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  29797     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_INTR_BCM56840_A0r */
  29798         soc_block_list[5],
  29799         soc_genreg,
  29800         1,
  29801         0,
  29802         0x5080d10,
  29803         0,
  29804         0,
  29805         3,
  29806         soc_L3_IIF_PARITY_STATUS_NACKr_fields,
  29807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29808         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29809         -1,
  29810         -1,
  29811     },
  29812 #endif /* chips */
  29813 
  29814 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  29815     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  29816     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  29817     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_NACKr */
  29818         soc_block_list[5],
  29819         soc_genreg,
  29820         1,
  29821         0,
  29822         0x508016b,
  29823         0,
  29824         0,
  29825         3,
  29826         soc_EGR_MASK_PARITY_STATUSr_fields,
  29827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29828         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  29829         -1,
  29830         -1,
  29831     },
  29832 #endif /* chips */
  29833 
  29834 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  29835     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_NACK_BCM56334_A0r */
  29836         soc_block_list[5],
  29837         soc_genreg,
  29838         1,
  29839         0,
  29840         0x6080143,
  29841         0,
  29842         0,
  29843         3,
  29844         soc_L3_IIF_PARITY_STATUS_NACKr_fields,
  29845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29846         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29847         -1,
  29848         -1,
  29849     },
  29850 #endif /* chips */
  29851 
  29852 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29853     defined(BCM_56450_B1)
  29854     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_NACK_BCM56450_A0r */
  29855         soc_block_list[5],
  29856         soc_genreg,
  29857         1,
  29858         0,
  29859         0x16011100,
  29860         0,
  29861         0,
  29862         3,
  29863         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  29864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29865         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29866         -1,
  29867         -1,
  29868     },
  29869 #endif /* chips */
  29870 
  29871 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  29872     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  29873     { /* SOC_REG_INT_L3_IIF_PARITY_STATUS_NACK_BCM56840_A0r */
  29874         soc_block_list[5],
  29875         soc_genreg,
  29876         1,
  29877         0,
  29878         0x5080d11,
  29879         0,
  29880         0,
  29881         3,
  29882         soc_L3_IIF_PARITY_STATUS_NACKr_fields,
  29883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29884         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29885         -1,
  29886         -1,
  29887     },
  29888 #endif /* chips */
  29889 
  29890 #if defined(BCM_56640_A0)
  29891     { /* SOC_REG_INT_L3_IIF_PDA_CONTROLr */
  29892         soc_block_list[5],
  29893         soc_genreg,
  29894         1,
  29895         0,
  29896         0x16010c00,
  29897         0,
  29898         0,
  29899         3,
  29900         soc_L3_IIF_PDA_CONTROLr_fields,
  29901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29902         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29903         -1,
  29904         -1,
  29905     },
  29906 #endif /* chips */
  29907 
  29908 #if defined(BCM_56340_A0)
  29909     { /* SOC_REG_INT_L3_IIF_PDA_CONTROL_BCM56340_A0r */
  29910         soc_block_list[5],
  29911         soc_genreg,
  29912         1,
  29913         0,
  29914         0x16010c00,
  29915         0,
  29916         0,
  29917         2,
  29918         soc_L3_IIF_PDA_CONTROL_BCM56340_A0r_fields,
  29919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29920         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29921         -1,
  29922         -1,
  29923     },
  29924 #endif /* chips */
  29925 
  29926 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  29927     defined(BCM_56270_A0)
  29928     { /* SOC_REG_INT_L3_IPMC_1_ECCP_CONTROLr */
  29929         soc_block_list[5],
  29930         soc_genreg,
  29931         1,
  29932         0,
  29933         0x2e011c00,
  29934         0,
  29935         0,
  29936         2,
  29937         soc_ING_DVP_TABLE_ECCP_CONTROLr_fields,
  29938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29939         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  29940         -1,
  29941         -1,
  29942     },
  29943 #endif /* chips */
  29944 
  29945 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  29946     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  29947     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  29948     { /* SOC_REG_INT_L3_IPMC_1_PARITY_CONTROLr */
  29949         soc_block_list[5],
  29950         soc_genreg,
  29951         1,
  29952         0,
  29953         0xa0801e8,
  29954         0,
  29955         0,
  29956         1,
  29957         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  29958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29959         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29960         -1,
  29961         -1,
  29962     },
  29963 #endif /* chips */
  29964 
  29965 #if defined(BCM_53570_A0)
  29966     { /* SOC_REG_INT_L3_IPMC_1_PARITY_CONTROL_BCM53570_A0r */
  29967         soc_block_list[5],
  29968         soc_genreg,
  29969         1,
  29970         0,
  29971         0x32011400,
  29972         0,
  29973         0,
  29974         1,
  29975         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  29976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29977         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29978         -1,
  29979         -1,
  29980     },
  29981 #endif /* chips */
  29982 
  29983 #if defined(BCM_53570_B0)
  29984     { /* SOC_REG_INT_L3_IPMC_1_PARITY_CONTROL_BCM53570_B0r */
  29985         soc_block_list[5],
  29986         soc_genreg,
  29987         1,
  29988         0,
  29989         0x32011500,
  29990         0,
  29991         0,
  29992         1,
  29993         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  29994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29995         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29996         -1,
  29997         -1,
  29998     },
  29999 #endif /* chips */
  30000 
  30001 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  30002     { /* SOC_REG_INT_L3_IPMC_1_PARITY_CONTROL_BCM56440_A0r */
  30003         soc_block_list[5],
  30004         soc_genreg,
  30005         1,
  30006         0,
  30007         0xb080d19,
  30008         0,
  30009         0,
  30010         1,
  30011         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  30012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30013         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30014         -1,
  30015         -1,
  30016     },
  30017 #endif /* chips */
  30018 
  30019 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30020     defined(BCM_56450_B1)
  30021     { /* SOC_REG_INT_L3_IPMC_1_PARITY_CONTROL_BCM56450_A0r */
  30022         soc_block_list[5],
  30023         soc_genreg,
  30024         1,
  30025         0,
  30026         0x2e011900,
  30027         0,
  30028         0,
  30029         1,
  30030         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  30031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30032         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30033         -1,
  30034         -1,
  30035     },
  30036 #endif /* chips */
  30037 
  30038 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  30039     { /* SOC_REG_INT_L3_IPMC_1_PARITY_CONTROL_BCM56840_A0r */
  30040         soc_block_list[5],
  30041         soc_genreg,
  30042         1,
  30043         0,
  30044         0xb080d1d,
  30045         0,
  30046         0,
  30047         1,
  30048         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  30049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30050         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30051         -1,
  30052         -1,
  30053     },
  30054 #endif /* chips */
  30055 
  30056 #if defined(BCM_53570_A0)
  30057     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUSr */
  30058         soc_block_list[5],
  30059         soc_genreg,
  30060         1,
  30061         0,
  30062         0x32011500,
  30063         0,
  30064         0,
  30065         3,
  30066         soc_EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr_fields,
  30067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30068         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  30069         -1,
  30070         -1,
  30071     },
  30072 #endif /* chips */
  30073 
  30074 #if defined(BCM_53570_B0)
  30075     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUS_BCM53570_B0r */
  30076         soc_block_list[5],
  30077         soc_genreg,
  30078         1,
  30079         0,
  30080         0x32011600,
  30081         0,
  30082         0,
  30083         3,
  30084         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  30085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30086         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30087         -1,
  30088         -1,
  30089     },
  30090 #endif /* chips */
  30091 
  30092 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30093     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  30094     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30095     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUS_INTRr */
  30096         soc_block_list[5],
  30097         soc_genreg,
  30098         1,
  30099         0,
  30100         0xa0801e9,
  30101         0,
  30102         0,
  30103         3,
  30104         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30106         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30107         -1,
  30108         -1,
  30109     },
  30110 #endif /* chips */
  30111 
  30112 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  30113     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUS_INTR_BCM56440_A0r */
  30114         soc_block_list[5],
  30115         soc_genreg,
  30116         1,
  30117         0,
  30118         0xb080d1a,
  30119         0,
  30120         0,
  30121         3,
  30122         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30124         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30125         -1,
  30126         -1,
  30127     },
  30128 #endif /* chips */
  30129 
  30130 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30131     defined(BCM_56450_B1)
  30132     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUS_INTR_BCM56450_A0r */
  30133         soc_block_list[5],
  30134         soc_genreg,
  30135         1,
  30136         0,
  30137         0x2e011a00,
  30138         0,
  30139         0,
  30140         3,
  30141         soc_AXP_WTX_DSCP_MAP_PAR_STATUS_INTRr_fields,
  30142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30143         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30144         -1,
  30145         -1,
  30146     },
  30147 #endif /* chips */
  30148 
  30149 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  30150     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUS_INTR_BCM56840_A0r */
  30151         soc_block_list[5],
  30152         soc_genreg,
  30153         1,
  30154         0,
  30155         0xb080d1e,
  30156         0,
  30157         0,
  30158         3,
  30159         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30161         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30162         -1,
  30163         -1,
  30164     },
  30165 #endif /* chips */
  30166 
  30167 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30168     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  30169     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30170     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUS_NACKr */
  30171         soc_block_list[5],
  30172         soc_genreg,
  30173         1,
  30174         0,
  30175         0xa0801ea,
  30176         0,
  30177         0,
  30178         3,
  30179         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30181         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30182         -1,
  30183         -1,
  30184     },
  30185 #endif /* chips */
  30186 
  30187 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  30188     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUS_NACK_BCM56440_A0r */
  30189         soc_block_list[5],
  30190         soc_genreg,
  30191         1,
  30192         0,
  30193         0xb080d1b,
  30194         0,
  30195         0,
  30196         3,
  30197         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30199         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30200         -1,
  30201         -1,
  30202     },
  30203 #endif /* chips */
  30204 
  30205 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30206     defined(BCM_56450_B1)
  30207     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUS_NACK_BCM56450_A0r */
  30208         soc_block_list[5],
  30209         soc_genreg,
  30210         1,
  30211         0,
  30212         0x2e011b00,
  30213         0,
  30214         0,
  30215         3,
  30216         soc_AXP_WTX_DSCP_MAP_PAR_STATUS_INTRr_fields,
  30217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30218         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30219         -1,
  30220         -1,
  30221     },
  30222 #endif /* chips */
  30223 
  30224 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  30225     { /* SOC_REG_INT_L3_IPMC_1_PARITY_STATUS_NACK_BCM56840_A0r */
  30226         soc_block_list[5],
  30227         soc_genreg,
  30228         1,
  30229         0,
  30230         0xb080d1f,
  30231         0,
  30232         0,
  30233         3,
  30234         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30236         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30237         -1,
  30238         -1,
  30239     },
  30240 #endif /* chips */
  30241 
  30242 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30243     defined(BCM_56450_B1)
  30244     { /* SOC_REG_INT_L3_IPMC_2_PARITY_CONTROLr */
  30245         soc_block_list[5],
  30246         soc_genreg,
  30247         1,
  30248         0,
  30249         0x3a010d00,
  30250         0,
  30251         0,
  30252         1,
  30253         soc_FT_CNTR_SER_CONTROLr_fields,
  30254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30255         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30256         -1,
  30257         -1,
  30258     },
  30259 #endif /* chips */
  30260 
  30261 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30262     defined(BCM_56450_B1)
  30263     { /* SOC_REG_INT_L3_IPMC_2_PARITY_STATUS_INTRr */
  30264         soc_block_list[5],
  30265         soc_genreg,
  30266         1,
  30267         0,
  30268         0x3a010e00,
  30269         0,
  30270         0,
  30271         3,
  30272         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
  30273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30274         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30275         -1,
  30276         -1,
  30277     },
  30278 #endif /* chips */
  30279 
  30280 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30281     defined(BCM_56450_B1)
  30282     { /* SOC_REG_INT_L3_IPMC_2_PARITY_STATUS_NACKr */
  30283         soc_block_list[5],
  30284         soc_genreg,
  30285         1,
  30286         0,
  30287         0x3a010f00,
  30288         0,
  30289         0,
  30290         3,
  30291         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
  30292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30293         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30294         -1,
  30295         -1,
  30296     },
  30297 #endif /* chips */
  30298 
  30299 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  30300     defined(BCM_56270_A0)
  30301     { /* SOC_REG_INT_L3_IPMC_ECCP_CONTROLr */
  30302         soc_block_list[5],
  30303         soc_genreg,
  30304         1,
  30305         0,
  30306         0x3a010a00,
  30307         0,
  30308         0,
  30309         2,
  30310         soc_EGR_MASK_ECC_CONTROLr_fields,
  30311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30312         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30313         -1,
  30314         -1,
  30315     },
  30316 #endif /* chips */
  30317 
  30318 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  30319     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  30320     { /* SOC_REG_INT_L3_IPMC_PARITY_CONTROLr */
  30321         soc_block_list[5],
  30322         soc_genreg,
  30323         1,
  30324         0,
  30325         0xb08015c,
  30326         0,
  30327         0,
  30328         1,
  30329         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  30330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30331         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30332         -1,
  30333         -1,
  30334     },
  30335 #endif /* chips */
  30336 
  30337 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  30338     { /* SOC_REG_INT_L3_IPMC_PARITY_CONTROL_BCM53570_A0r */
  30339         soc_block_list[5],
  30340         soc_genreg,
  30341         1,
  30342         0,
  30343         0x3e010a00,
  30344         0,
  30345         0,
  30346         1,
  30347         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  30348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30349         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30350         -1,
  30351         -1,
  30352     },
  30353 #endif /* chips */
  30354 
  30355 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  30356     { /* SOC_REG_INT_L3_IPMC_PARITY_CONTROL_BCM56224_A0r */
  30357         soc_block_list[5],
  30358         soc_genreg,
  30359         1,
  30360         0,
  30361         0x9080000,
  30362         0,
  30363         0,
  30364         2,
  30365         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  30366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30367         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  30368         -1,
  30369         -1,
  30370     },
  30371 #endif /* chips */
  30372 
  30373 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30374     defined(BCM_56450_B1)
  30375     { /* SOC_REG_INT_L3_IPMC_PARITY_CONTROL_BCM56450_A0r */
  30376         soc_block_list[5],
  30377         soc_genreg,
  30378         1,
  30379         0,
  30380         0x3a010a00,
  30381         0,
  30382         0,
  30383         1,
  30384         soc_FT_CNTR_SER_CONTROLr_fields,
  30385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30386         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30387         -1,
  30388         -1,
  30389     },
  30390 #endif /* chips */
  30391 
  30392 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30393     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  30394     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30395     { /* SOC_REG_INT_L3_IPMC_PARITY_CONTROL_BCM56634_A0r */
  30396         soc_block_list[5],
  30397         soc_genreg,
  30398         1,
  30399         0,
  30400         0xd080228,
  30401         0,
  30402         0,
  30403         1,
  30404         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  30405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30406         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30407         -1,
  30408         -1,
  30409     },
  30410 #endif /* chips */
  30411 
  30412 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  30413     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  30414     { /* SOC_REG_INT_L3_IPMC_PARITY_CONTROL_BCM56840_A0r */
  30415         soc_block_list[5],
  30416         soc_genreg,
  30417         1,
  30418         0,
  30419         0xe080d09,
  30420         0,
  30421         0,
  30422         1,
  30423         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  30424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30426         -1,
  30427         -1,
  30428     },
  30429 #endif /* chips */
  30430 
  30431 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  30432     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  30433     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUSr */
  30434         soc_block_list[5],
  30435         soc_genreg,
  30436         1,
  30437         0,
  30438         0xb08015d,
  30439         0,
  30440         0,
  30441         3,
  30442         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30444         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30445         -1,
  30446         -1,
  30447     },
  30448 #endif /* chips */
  30449 
  30450 #if defined(BCM_53570_A0)
  30451     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUS_BCM53570_A0r */
  30452         soc_block_list[5],
  30453         soc_genreg,
  30454         1,
  30455         0,
  30456         0x3e010b00,
  30457         0,
  30458         0,
  30459         3,
  30460         soc_EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr_fields,
  30461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30462         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  30463         -1,
  30464         -1,
  30465     },
  30466 #endif /* chips */
  30467 
  30468 #if defined(BCM_53570_B0)
  30469     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUS_BCM53570_B0r */
  30470         soc_block_list[5],
  30471         soc_genreg,
  30472         1,
  30473         0,
  30474         0x3e010b00,
  30475         0,
  30476         0,
  30477         3,
  30478         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  30479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30480         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30481         -1,
  30482         -1,
  30483     },
  30484 #endif /* chips */
  30485 
  30486 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  30487     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUS_BCM56224_A0r */
  30488         soc_block_list[5],
  30489         soc_genreg,
  30490         1,
  30491         0,
  30492         0x9080001,
  30493         SOC_REG_FLAG_RO,
  30494         0,
  30495         2,
  30496         soc_L3_IPMC_PARITY_STATUSr_fields,
  30497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30498         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  30499         -1,
  30500         -1,
  30501     },
  30502 #endif /* chips */
  30503 
  30504 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30505     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  30506     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30507     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUS_INTRr */
  30508         soc_block_list[5],
  30509         soc_genreg,
  30510         1,
  30511         0,
  30512         0xd080229,
  30513         0,
  30514         0,
  30515         3,
  30516         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30518         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30519         -1,
  30520         -1,
  30521     },
  30522 #endif /* chips */
  30523 
  30524 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30525     defined(BCM_56450_B1)
  30526     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUS_INTR_BCM56450_A0r */
  30527         soc_block_list[5],
  30528         soc_genreg,
  30529         1,
  30530         0,
  30531         0x3a010b00,
  30532         0,
  30533         0,
  30534         3,
  30535         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
  30536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30538         -1,
  30539         -1,
  30540     },
  30541 #endif /* chips */
  30542 
  30543 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  30544     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  30545     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUS_INTR_BCM56840_A0r */
  30546         soc_block_list[5],
  30547         soc_genreg,
  30548         1,
  30549         0,
  30550         0xe080d0a,
  30551         0,
  30552         0,
  30553         3,
  30554         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  30555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30556         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30557         -1,
  30558         -1,
  30559     },
  30560 #endif /* chips */
  30561 
  30562 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30563     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  30564     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30565     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUS_NACKr */
  30566         soc_block_list[5],
  30567         soc_genreg,
  30568         1,
  30569         0,
  30570         0xd08022a,
  30571         0,
  30572         0,
  30573         3,
  30574         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30576         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30577         -1,
  30578         -1,
  30579     },
  30580 #endif /* chips */
  30581 
  30582 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30583     defined(BCM_56450_B1)
  30584     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUS_NACK_BCM56450_A0r */
  30585         soc_block_list[5],
  30586         soc_genreg,
  30587         1,
  30588         0,
  30589         0x3a010c00,
  30590         0,
  30591         0,
  30592         3,
  30593         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
  30594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30595         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30596         -1,
  30597         -1,
  30598     },
  30599 #endif /* chips */
  30600 
  30601 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  30602     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  30603     { /* SOC_REG_INT_L3_IPMC_PARITY_STATUS_NACK_BCM56840_A0r */
  30604         soc_block_list[5],
  30605         soc_genreg,
  30606         1,
  30607         0,
  30608         0xe080d0b,
  30609         0,
  30610         0,
  30611         3,
  30612         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  30613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30614         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30615         -1,
  30616         -1,
  30617     },
  30618 #endif /* chips */
  30619 
  30620 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30621     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  30622     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30623     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_CONTROLr */
  30624         soc_block_list[5],
  30625         soc_genreg,
  30626         1,
  30627         0,
  30628         0xd08022b,
  30629         0,
  30630         0,
  30631         1,
  30632         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  30633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30634         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30635         -1,
  30636         -1,
  30637     },
  30638 #endif /* chips */
  30639 
  30640 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  30641     defined(BCM_56270_A0)
  30642     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_CONTROL_BCM56260_A0r */
  30643         soc_block_list[5],
  30644         soc_genreg,
  30645         1,
  30646         0,
  30647         0x3a011000,
  30648         0,
  30649         0,
  30650         1,
  30651         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  30652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30654         -1,
  30655         -1,
  30656     },
  30657 #endif /* chips */
  30658 
  30659 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30660     defined(BCM_56450_B1)
  30661     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_CONTROL_BCM56450_A0r */
  30662         soc_block_list[5],
  30663         soc_genreg,
  30664         1,
  30665         0,
  30666         0x3a011000,
  30667         0,
  30668         0,
  30669         1,
  30670         soc_FT_CNTR_SER_CONTROLr_fields,
  30671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30672         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30673         -1,
  30674         -1,
  30675     },
  30676 #endif /* chips */
  30677 
  30678 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  30679     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  30680     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_CONTROL_BCM56840_A0r */
  30681         soc_block_list[5],
  30682         soc_genreg,
  30683         1,
  30684         0,
  30685         0xe080d0c,
  30686         0,
  30687         0,
  30688         1,
  30689         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  30690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30692         -1,
  30693         -1,
  30694     },
  30695 #endif /* chips */
  30696 
  30697 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30698     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  30699     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30700     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_STATUS_INTRr */
  30701         soc_block_list[5],
  30702         soc_genreg,
  30703         1,
  30704         0,
  30705         0xd08022c,
  30706         0,
  30707         0,
  30708         3,
  30709         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30711         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30712         -1,
  30713         -1,
  30714     },
  30715 #endif /* chips */
  30716 
  30717 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30718     defined(BCM_56450_B1)
  30719     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_STATUS_INTR_BCM56450_A0r */
  30720         soc_block_list[5],
  30721         soc_genreg,
  30722         1,
  30723         0,
  30724         0x3a011100,
  30725         0,
  30726         0,
  30727         3,
  30728         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
  30729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30730         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30731         -1,
  30732         -1,
  30733     },
  30734 #endif /* chips */
  30735 
  30736 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  30737     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  30738     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_STATUS_INTR_BCM56840_A0r */
  30739         soc_block_list[5],
  30740         soc_genreg,
  30741         1,
  30742         0,
  30743         0xe080d0d,
  30744         0,
  30745         0,
  30746         3,
  30747         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  30748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30749         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30750         -1,
  30751         -1,
  30752     },
  30753 #endif /* chips */
  30754 
  30755 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30756     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  30757     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30758     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_STATUS_NACKr */
  30759         soc_block_list[5],
  30760         soc_genreg,
  30761         1,
  30762         0,
  30763         0xd08022d,
  30764         0,
  30765         0,
  30766         3,
  30767         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  30768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30769         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  30770         -1,
  30771         -1,
  30772     },
  30773 #endif /* chips */
  30774 
  30775 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30776     defined(BCM_56450_B1)
  30777     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_STATUS_NACK_BCM56450_A0r */
  30778         soc_block_list[5],
  30779         soc_genreg,
  30780         1,
  30781         0,
  30782         0x3a011200,
  30783         0,
  30784         0,
  30785         3,
  30786         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
  30787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30788         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30789         -1,
  30790         -1,
  30791     },
  30792 #endif /* chips */
  30793 
  30794 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  30795     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  30796     { /* SOC_REG_INT_L3_IPMC_REMAP_PARITY_STATUS_NACK_BCM56840_A0r */
  30797         soc_block_list[5],
  30798         soc_genreg,
  30799         1,
  30800         0,
  30801         0xe080d0e,
  30802         0,
  30803         0,
  30804         3,
  30805         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  30806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30808         -1,
  30809         -1,
  30810     },
  30811 #endif /* chips */
  30812 
  30813 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  30814     { /* SOC_REG_INT_L3_ISS_BANK_CONFIGr */
  30815         soc_block_list[5],
  30816         soc_genreg,
  30817         1,
  30818         0,
  30819         0x2a000300,
  30820         0,
  30821         0,
  30822         1,
  30823         soc_L3_ISS_BANK_CONFIGr_fields,
  30824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30825         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  30826         -1,
  30827         -1,
  30828     },
  30829 #endif /* chips */
  30830 
  30831 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  30832     { /* SOC_REG_INT_L3_ISS_LOG_TO_PHY_BANK_MAPr */
  30833         soc_block_list[5],
  30834         soc_genreg,
  30835         1,
  30836         0,
  30837         0x2a000200,
  30838         0,
  30839         0,
  30840         4,
  30841         soc_L3_ISS_LOG_TO_PHY_BANK_MAPr_fields,
  30842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30843         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  30844         -1,
  30845         -1,
  30846     },
  30847 #endif /* chips */
  30848 
  30849 #if defined(BCM_56850_A0)
  30850     { /* SOC_REG_INT_L3_LP_CONTROL_0r */
  30851         soc_block_list[5],
  30852         soc_genreg,
  30853         1,
  30854         0,
  30855         0x2b150000,
  30856         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  30857         0,
  30858         4,
  30859         soc_L2_LP_CONTROL_0r_fields,
  30860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30861         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30862         -1,
  30863         -1,
  30864     },
  30865 #endif /* chips */
  30866 
  30867 #if defined(BCM_56850_A0)
  30868     { /* SOC_REG_INT_L3_LP_CONTROL_1r */
  30869         soc_block_list[5],
  30870         soc_genreg,
  30871         1,
  30872         0,
  30873         0x2b160000,
  30874         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  30875         0,
  30876         4,
  30877         soc_L3_LP_CONTROL_1r_fields,
  30878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30879         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30880         -1,
  30881         -1,
  30882     },
  30883 #endif /* chips */
  30884 
  30885 #if defined(BCM_56850_A0)
  30886     { /* SOC_REG_INT_L3_LP_CONTROL_2r */
  30887         soc_block_list[5],
  30888         soc_genreg,
  30889         1,
  30890         0,
  30891         0x2b170000,
  30892         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  30893         0,
  30894         3,
  30895         soc_L2_LP_CONTROL_1r_fields,
  30896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30898         -1,
  30899         -1,
  30900     },
  30901 #endif /* chips */
  30902 
  30903 #if defined(BCM_56850_A0)
  30904     { /* SOC_REG_INT_L3_LP_CONTROL_3r */
  30905         soc_block_list[5],
  30906         soc_genreg,
  30907         1,
  30908         0,
  30909         0x2b180000,
  30910         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  30911         0,
  30912         3,
  30913         soc_L3_LP_CONTROL_3r_fields,
  30914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30916         -1,
  30917         -1,
  30918     },
  30919 #endif /* chips */
  30920 
  30921 #if defined(BCM_56850_A0)
  30922     { /* SOC_REG_INT_L3_LP_CONTROL_4r */
  30923         soc_block_list[5],
  30924         soc_genreg,
  30925         1,
  30926         0,
  30927         0x2b190000,
  30928         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  30929         0,
  30930         2,
  30931         soc_STAGE0_MEMORY_CONTROL_20r_fields,
  30932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30934         -1,
  30935         -1,
  30936     },
  30937 #endif /* chips */
  30938 
  30939 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  30940     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  30941     { /* SOC_REG_INT_L3_LP_CONTROL_0_BCM56560_A0r */
  30942         soc_block_list[5],
  30943         soc_genreg,
  30944         1,
  30945         0,
  30946         0x3b050000,
  30947         0,
  30948         0,
  30949         1,
  30950         soc_L2_ENTRY_CONTROL_0_BCM56560_A0r_fields,
  30951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30952         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30953         -1,
  30954         -1,
  30955     },
  30956 #endif /* chips */
  30957 
  30958 #if defined(BCM_56860_A0)
  30959     { /* SOC_REG_INT_L3_LP_CONTROL_0_BCM56860_A0r */
  30960         soc_block_list[5],
  30961         soc_genreg,
  30962         1,
  30963         0,
  30964         0x3b050000,
  30965         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  30966         0,
  30967         1,
  30968         soc_L2_ENTRY_CONTROL_0_BCM56860_A0r_fields,
  30969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30971         -1,
  30972         -1,
  30973     },
  30974 #endif /* chips */
  30975 
  30976 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  30977     { /* SOC_REG_INT_L3_LP_CONTROL_0_BCM56960_A0r */
  30978         soc_block_list[5],
  30979         soc_genreg,
  30980         1,
  30981         0,
  30982         0x3b1f0000,
  30983         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  30984         0,
  30985         4,
  30986         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  30987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30988         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30989         -1,
  30990         -1,
  30991         3,
  30992     },
  30993 #endif /* chips */
  30994 
  30995 #if defined(BCM_56970_A0)
  30996     { /* SOC_REG_INT_L3_LP_CONTROL_0_BCM56970_A0r */
  30997         soc_block_list[5],
  30998         soc_genreg,
  30999         1,
  31000         0,
  31001         0x5f1e0000,
  31002         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31003         0,
  31004         4,
  31005         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  31006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31007         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31008         -1,
  31009         -1,
  31010         3,
  31011     },
  31012 #endif /* chips */
  31013 
  31014 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31015     { /* SOC_REG_INT_L3_LP_CONTROL_0_PIPE0r */
  31016         soc_block_list[5],
  31017         soc_genreg,
  31018         1,
  31019         0,
  31020         0x3b1f0000,
  31021         0,
  31022         0,
  31023         4,
  31024         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  31025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31026         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31027         -1,
  31028         -1,
  31029         3,
  31030     },
  31031 #endif /* chips */
  31032 
  31033 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31034     { /* SOC_REG_INT_L3_LP_CONTROL_0_PIPE1r */
  31035         soc_block_list[5],
  31036         soc_genreg,
  31037         1,
  31038         0,
  31039         0x3b1f0000,
  31040         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31041         0,
  31042         4,
  31043         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  31044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31046         -1,
  31047         -1,
  31048         3,
  31049     },
  31050 #endif /* chips */
  31051 
  31052 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31053     { /* SOC_REG_INT_L3_LP_CONTROL_0_PIPE2r */
  31054         soc_block_list[5],
  31055         soc_genreg,
  31056         1,
  31057         0,
  31058         0x3b1f0000,
  31059         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31060         0,
  31061         4,
  31062         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  31063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31064         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31065         -1,
  31066         -1,
  31067         3,
  31068     },
  31069 #endif /* chips */
  31070 
  31071 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31072     { /* SOC_REG_INT_L3_LP_CONTROL_0_PIPE3r */
  31073         soc_block_list[5],
  31074         soc_genreg,
  31075         1,
  31076         0,
  31077         0x3b1f0000,
  31078         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31079         0,
  31080         4,
  31081         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  31082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31084         -1,
  31085         -1,
  31086         3,
  31087     },
  31088 #endif /* chips */
  31089 
  31090 #if defined(BCM_56970_A0)
  31091     { /* SOC_REG_INT_L3_LP_CONTROL_0_PIPE0_BCM56970_A0r */
  31092         soc_block_list[5],
  31093         soc_genreg,
  31094         1,
  31095         0,
  31096         0x5f1e0000,
  31097         0,
  31098         0,
  31099         4,
  31100         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  31101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31102         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31103         -1,
  31104         -1,
  31105         3,
  31106     },
  31107 #endif /* chips */
  31108 
  31109 #if defined(BCM_56970_A0)
  31110     { /* SOC_REG_INT_L3_LP_CONTROL_0_PIPE1_BCM56970_A0r */
  31111         soc_block_list[5],
  31112         soc_genreg,
  31113         1,
  31114         0,
  31115         0x5f1e0000,
  31116         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31117         0,
  31118         4,
  31119         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  31120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31121         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31122         -1,
  31123         -1,
  31124         3,
  31125     },
  31126 #endif /* chips */
  31127 
  31128 #if defined(BCM_56970_A0)
  31129     { /* SOC_REG_INT_L3_LP_CONTROL_0_PIPE2_BCM56970_A0r */
  31130         soc_block_list[5],
  31131         soc_genreg,
  31132         1,
  31133         0,
  31134         0x5f1e0000,
  31135         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31136         0,
  31137         4,
  31138         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  31139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31141         -1,
  31142         -1,
  31143         3,
  31144     },
  31145 #endif /* chips */
  31146 
  31147 #if defined(BCM_56970_A0)
  31148     { /* SOC_REG_INT_L3_LP_CONTROL_0_PIPE3_BCM56970_A0r */
  31149         soc_block_list[5],
  31150         soc_genreg,
  31151         1,
  31152         0,
  31153         0x5f1e0000,
  31154         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31155         0,
  31156         4,
  31157         soc_L2_ENTRY_CONTROL_0_BCM56960_A0r_fields,
  31158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31160         -1,
  31161         -1,
  31162         3,
  31163     },
  31164 #endif /* chips */
  31165 
  31166 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31167     { /* SOC_REG_INT_L3_LP_CONTROL_1_BCM56960_A0r */
  31168         soc_block_list[5],
  31169         soc_genreg,
  31170         1,
  31171         0,
  31172         0x3b200000,
  31173         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31174         0,
  31175         4,
  31176         soc_L3_ENTRY_CONTROL_1r_fields,
  31177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31178         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31179         -1,
  31180         -1,
  31181         3,
  31182     },
  31183 #endif /* chips */
  31184 
  31185 #if defined(BCM_56970_A0)
  31186     { /* SOC_REG_INT_L3_LP_CONTROL_1_BCM56970_A0r */
  31187         soc_block_list[5],
  31188         soc_genreg,
  31189         1,
  31190         0,
  31191         0x5f1f0000,
  31192         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31193         0,
  31194         4,
  31195         soc_L3_ENTRY_CONTROL_1r_fields,
  31196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31197         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31198         -1,
  31199         -1,
  31200         3,
  31201     },
  31202 #endif /* chips */
  31203 
  31204 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31205     { /* SOC_REG_INT_L3_LP_CONTROL_1_PIPE0r */
  31206         soc_block_list[5],
  31207         soc_genreg,
  31208         1,
  31209         0,
  31210         0x3b200000,
  31211         0,
  31212         0,
  31213         4,
  31214         soc_L3_ENTRY_CONTROL_1r_fields,
  31215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31216         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31217         -1,
  31218         -1,
  31219         3,
  31220     },
  31221 #endif /* chips */
  31222 
  31223 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31224     { /* SOC_REG_INT_L3_LP_CONTROL_1_PIPE1r */
  31225         soc_block_list[5],
  31226         soc_genreg,
  31227         1,
  31228         0,
  31229         0x3b200000,
  31230         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31231         0,
  31232         4,
  31233         soc_L3_ENTRY_CONTROL_1r_fields,
  31234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31235         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31236         -1,
  31237         -1,
  31238         3,
  31239     },
  31240 #endif /* chips */
  31241 
  31242 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31243     { /* SOC_REG_INT_L3_LP_CONTROL_1_PIPE2r */
  31244         soc_block_list[5],
  31245         soc_genreg,
  31246         1,
  31247         0,
  31248         0x3b200000,
  31249         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31250         0,
  31251         4,
  31252         soc_L3_ENTRY_CONTROL_1r_fields,
  31253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31254         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31255         -1,
  31256         -1,
  31257         3,
  31258     },
  31259 #endif /* chips */
  31260 
  31261 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31262     { /* SOC_REG_INT_L3_LP_CONTROL_1_PIPE3r */
  31263         soc_block_list[5],
  31264         soc_genreg,
  31265         1,
  31266         0,
  31267         0x3b200000,
  31268         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31269         0,
  31270         4,
  31271         soc_L3_ENTRY_CONTROL_1r_fields,
  31272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31273         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31274         -1,
  31275         -1,
  31276         3,
  31277     },
  31278 #endif /* chips */
  31279 
  31280 #if defined(BCM_56970_A0)
  31281     { /* SOC_REG_INT_L3_LP_CONTROL_1_PIPE0_BCM56970_A0r */
  31282         soc_block_list[5],
  31283         soc_genreg,
  31284         1,
  31285         0,
  31286         0x5f1f0000,
  31287         0,
  31288         0,
  31289         4,
  31290         soc_L3_ENTRY_CONTROL_1r_fields,
  31291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31293         -1,
  31294         -1,
  31295         3,
  31296     },
  31297 #endif /* chips */
  31298 
  31299 #if defined(BCM_56970_A0)
  31300     { /* SOC_REG_INT_L3_LP_CONTROL_1_PIPE1_BCM56970_A0r */
  31301         soc_block_list[5],
  31302         soc_genreg,
  31303         1,
  31304         0,
  31305         0x5f1f0000,
  31306         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31307         0,
  31308         4,
  31309         soc_L3_ENTRY_CONTROL_1r_fields,
  31310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31312         -1,
  31313         -1,
  31314         3,
  31315     },
  31316 #endif /* chips */
  31317 
  31318 #if defined(BCM_56970_A0)
  31319     { /* SOC_REG_INT_L3_LP_CONTROL_1_PIPE2_BCM56970_A0r */
  31320         soc_block_list[5],
  31321         soc_genreg,
  31322         1,
  31323         0,
  31324         0x5f1f0000,
  31325         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31326         0,
  31327         4,
  31328         soc_L3_ENTRY_CONTROL_1r_fields,
  31329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31331         -1,
  31332         -1,
  31333         3,
  31334     },
  31335 #endif /* chips */
  31336 
  31337 #if defined(BCM_56970_A0)
  31338     { /* SOC_REG_INT_L3_LP_CONTROL_1_PIPE3_BCM56970_A0r */
  31339         soc_block_list[5],
  31340         soc_genreg,
  31341         1,
  31342         0,
  31343         0x5f1f0000,
  31344         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31345         0,
  31346         4,
  31347         soc_L3_ENTRY_CONTROL_1r_fields,
  31348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31349         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31350         -1,
  31351         -1,
  31352         3,
  31353     },
  31354 #endif /* chips */
  31355 
  31356 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  31357     { /* SOC_REG_INT_L3_MTU_VALUES_ECC_CONTROLr */
  31358         soc_block_list[5],
  31359         soc_genreg,
  31360         1,
  31361         0,
  31362         0x3e010600,
  31363         0,
  31364         0,
  31365         2,
  31366         soc_EGR_MASK_ECC_CONTROLr_fields,
  31367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31369         -1,
  31370         -1,
  31371     },
  31372 #endif /* chips */
  31373 
  31374 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  31375     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  31376     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROLr */
  31377         soc_block_list[5],
  31378         soc_genreg,
  31379         1,
  31380         0,
  31381         0x1108017d,
  31382         0,
  31383         0,
  31384         1,
  31385         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  31386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31387         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  31388         -1,
  31389         -1,
  31390     },
  31391 #endif /* chips */
  31392 
  31393 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31394     defined(BCM_56160_A0)
  31395     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROL_BCM53400_A0r */
  31396         soc_block_list[5],
  31397         soc_genreg,
  31398         1,
  31399         0,
  31400         0x42010200,
  31401         0,
  31402         0,
  31403         1,
  31404         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  31405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31406         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  31407         -1,
  31408         -1,
  31409     },
  31410 #endif /* chips */
  31411 
  31412 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  31413     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROL_BCM53570_A0r */
  31414         soc_block_list[5],
  31415         soc_genreg,
  31416         1,
  31417         0,
  31418         0x42010700,
  31419         0,
  31420         0,
  31421         1,
  31422         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  31423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31424         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  31425         -1,
  31426         -1,
  31427     },
  31428 #endif /* chips */
  31429 
  31430 #if defined(BCM_56142_A0)
  31431     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROL_BCM56142_A0r */
  31432         soc_block_list[5],
  31433         soc_genreg,
  31434         1,
  31435         0,
  31436         0x11080180,
  31437         0,
  31438         0,
  31439         1,
  31440         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  31441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31442         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  31443         -1,
  31444         -1,
  31445     },
  31446 #endif /* chips */
  31447 
  31448 #if defined(BCM_56150_A0)
  31449     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROL_BCM56150_A0r */
  31450         soc_block_list[5],
  31451         soc_genreg,
  31452         1,
  31453         0,
  31454         0x46010200,
  31455         0,
  31456         0,
  31457         1,
  31458         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  31459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31460         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  31461         -1,
  31462         -1,
  31463     },
  31464 #endif /* chips */
  31465 
  31466 #if defined(BCM_56270_A0)
  31467     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROL_BCM56270_A0r */
  31468         soc_block_list[5],
  31469         soc_genreg,
  31470         1,
  31471         0,
  31472         0x3e010600,
  31473         0,
  31474         0,
  31475         1,
  31476         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  31477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31479         -1,
  31480         -1,
  31481     },
  31482 #endif /* chips */
  31483 
  31484 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  31485     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROL_BCM56334_A0r */
  31486         soc_block_list[5],
  31487         soc_genreg,
  31488         1,
  31489         0,
  31490         0x110801ac,
  31491         0,
  31492         0,
  31493         1,
  31494         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  31495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31496         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  31497         -1,
  31498         -1,
  31499     },
  31500 #endif /* chips */
  31501 
  31502 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  31503     defined(BCM_56450_B1)
  31504     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROL_BCM56450_A0r */
  31505         soc_block_list[5],
  31506         soc_genreg,
  31507         1,
  31508         0,
  31509         0x3e010600,
  31510         0,
  31511         0,
  31512         1,
  31513         soc_FT_CNTR_SER_CONTROLr_fields,
  31514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31515         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31516         -1,
  31517         -1,
  31518     },
  31519 #endif /* chips */
  31520 
  31521 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  31522     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  31523     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  31524     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROL_BCM56634_A0r */
  31525         soc_block_list[5],
  31526         soc_genreg,
  31527         1,
  31528         0,
  31529         0xe080240,
  31530         0,
  31531         0,
  31532         1,
  31533         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  31534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31535         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  31536         -1,
  31537         -1,
  31538     },
  31539 #endif /* chips */
  31540 
  31541 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  31542     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  31543     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_CONTROL_BCM56840_A0r */
  31544         soc_block_list[5],
  31545         soc_genreg,
  31546         1,
  31547         0,
  31548         0xf080d06,
  31549         0,
  31550         0,
  31551         1,
  31552         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  31553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31554         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31555         -1,
  31556         -1,
  31557     },
  31558 #endif /* chips */
  31559 
  31560 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  31561     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  31562     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUSr */
  31563         soc_block_list[5],
  31564         soc_genreg,
  31565         1,
  31566         0,
  31567         0x1108017e,
  31568         0,
  31569         0,
  31570         3,
  31571         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM56624_A0r_fields,
  31572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31573         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  31574         -1,
  31575         -1,
  31576     },
  31577 #endif /* chips */
  31578 
  31579 #if defined(BCM_53400_A0)
  31580     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_BCM53400_A0r */
  31581         soc_block_list[5],
  31582         soc_genreg,
  31583         1,
  31584         0,
  31585         0x42010300,
  31586         0,
  31587         0,
  31588         3,
  31589         soc_EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr_fields,
  31590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31591         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  31592         -1,
  31593         -1,
  31594     },
  31595 #endif /* chips */
  31596 
  31597 #if defined(BCM_53570_A0)
  31598     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_BCM53570_A0r */
  31599         soc_block_list[5],
  31600         soc_genreg,
  31601         1,
  31602         0,
  31603         0x42010800,
  31604         0,
  31605         0,
  31606         3,
  31607         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM53400_A0r_fields,
  31608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31609         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  31610         -1,
  31611         -1,
  31612     },
  31613 #endif /* chips */
  31614 
  31615 #if defined(BCM_53570_B0)
  31616     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_BCM53570_B0r */
  31617         soc_block_list[5],
  31618         soc_genreg,
  31619         1,
  31620         0,
  31621         0x42010800,
  31622         0,
  31623         0,
  31624         3,
  31625         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_BCM56160_A0r_fields,
  31626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31627         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  31628         -1,
  31629         -1,
  31630     },
  31631 #endif /* chips */
  31632 
  31633 #if defined(BCM_56142_A0)
  31634     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_BCM56142_A0r */
  31635         soc_block_list[5],
  31636         soc_genreg,
  31637         1,
  31638         0,
  31639         0x11080181,
  31640         0,
  31641         0,
  31642         3,
  31643         soc_EGR_IP_TUNNEL_PARITY_STATUSr_fields,
  31644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31645         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  31646         -1,
  31647         -1,
  31648     },
  31649 #endif /* chips */
  31650 
  31651 #if defined(BCM_56150_A0)
  31652     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_BCM56150_A0r */
  31653         soc_block_list[5],
  31654         soc_genreg,
  31655         1,
  31656         0,
  31657         0x46010300,
  31658         0,
  31659         0,
  31660         3,
  31661         soc_AXP_WTX_FRAG_ID_PAR_STATUS_INTRr_fields,
  31662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31663         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  31664         -1,
  31665         -1,
  31666     },
  31667 #endif /* chips */
  31668 
  31669 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  31670     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_BCM56160_A0r */
  31671         soc_block_list[5],
  31672         soc_genreg,
  31673         1,
  31674         0,
  31675         0x42010300,
  31676         0,
  31677         0,
  31678         3,
  31679         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM53400_A0r_fields,
  31680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31681         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  31682         -1,
  31683         -1,
  31684     },
  31685 #endif /* chips */
  31686 
  31687 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  31688     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_BCM56334_A0r */
  31689         soc_block_list[5],
  31690         soc_genreg,
  31691         1,
  31692         0,
  31693         0x110801ad,
  31694         0,
  31695         0,
  31696         3,
  31697         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM56624_A0r_fields,
  31698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31699         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  31700         -1,
  31701         -1,
  31702     },
  31703 #endif /* chips */
  31704 
  31705 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  31706     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  31707     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  31708     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_INTRr */
  31709         soc_block_list[5],
  31710         soc_genreg,
  31711         1,
  31712         0,
  31713         0xe080241,
  31714         0,
  31715         0,
  31716         3,
  31717         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM56624_A0r_fields,
  31718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31719         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  31720         -1,
  31721         -1,
  31722     },
  31723 #endif /* chips */
  31724 
  31725 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  31726     defined(BCM_56450_B1)
  31727     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_INTR_BCM56450_A0r */
  31728         soc_block_list[5],
  31729         soc_genreg,
  31730         1,
  31731         0,
  31732         0x3e010700,
  31733         0,
  31734         0,
  31735         3,
  31736         soc_EGR_DSCP_TABLE_PARITY_STATUS_INTRr_fields,
  31737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31738         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31739         -1,
  31740         -1,
  31741     },
  31742 #endif /* chips */
  31743 
  31744 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  31745     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  31746     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_INTR_BCM56840_A0r */
  31747         soc_block_list[5],
  31748         soc_genreg,
  31749         1,
  31750         0,
  31751         0xf080d07,
  31752         0,
  31753         0,
  31754         3,
  31755         soc_L3_MTU_VALUES_PARITY_STATUS_INTRr_fields,
  31756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31758         -1,
  31759         -1,
  31760     },
  31761 #endif /* chips */
  31762 
  31763 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  31764     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  31765     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  31766     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_NACKr */
  31767         soc_block_list[5],
  31768         soc_genreg,
  31769         1,
  31770         0,
  31771         0xe080242,
  31772         0,
  31773         0,
  31774         3,
  31775         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM56624_A0r_fields,
  31776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31777         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  31778         -1,
  31779         -1,
  31780     },
  31781 #endif /* chips */
  31782 
  31783 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  31784     defined(BCM_56450_B1)
  31785     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_NACK_BCM56450_A0r */
  31786         soc_block_list[5],
  31787         soc_genreg,
  31788         1,
  31789         0,
  31790         0x3e010800,
  31791         0,
  31792         0,
  31793         3,
  31794         soc_EGR_DSCP_TABLE_PARITY_STATUS_INTRr_fields,
  31795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31796         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31797         -1,
  31798         -1,
  31799     },
  31800 #endif /* chips */
  31801 
  31802 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  31803     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  31804     { /* SOC_REG_INT_L3_MTU_VALUES_PARITY_STATUS_NACK_BCM56840_A0r */
  31805         soc_block_list[5],
  31806         soc_genreg,
  31807         1,
  31808         0,
  31809         0xf080d08,
  31810         0,
  31811         0,
  31812         3,
  31813         soc_L3_MTU_VALUES_PARITY_STATUS_INTRr_fields,
  31814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31815         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31816         -1,
  31817         -1,
  31818     },
  31819 #endif /* chips */
  31820 
  31821 #if defined(BCM_56850_A0)
  31822     { /* SOC_REG_INT_L3_TABLE_HASH_CONTROLr */
  31823         soc_block_list[5],
  31824         soc_genreg,
  31825         1,
  31826         0,
  31827         0x26000100,
  31828         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31829         0,
  31830         6,
  31831         soc_L3_TABLE_HASH_CONTROLr_fields,
  31832         SOC_RESET_VAL_DEC(0x00c30c30, 0x00000000)
  31833         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  31834         -1,
  31835         -1,
  31836     },
  31837 #endif /* chips */
  31838 
  31839 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  31840     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  31841     { /* SOC_REG_INT_L3_TABLE_HASH_CONTROL_BCM56560_A0r */
  31842         soc_block_list[5],
  31843         soc_genreg,
  31844         1,
  31845         0,
  31846         0x2a000100,
  31847         0,
  31848         0,
  31849         5,
  31850         soc_L3_TABLE_HASH_CONTROL_BCM56960_A0r_fields,
  31851         SOC_RESET_VAL_DEC(0x00c30c30, 0x00000000)
  31852         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  31853         -1,
  31854         -1,
  31855     },
  31856 #endif /* chips */
  31857 
  31858 #if defined(BCM_56860_A0)
  31859     { /* SOC_REG_INT_L3_TABLE_HASH_CONTROL_BCM56860_A0r */
  31860         soc_block_list[5],
  31861         soc_genreg,
  31862         1,
  31863         0,
  31864         0x2a000100,
  31865         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31866         0,
  31867         6,
  31868         soc_L3_TABLE_HASH_CONTROL_BCM56860_A0r_fields,
  31869         SOC_RESET_VAL_DEC(0x00c30c30, 0x00000000)
  31870         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  31871         -1,
  31872         -1,
  31873     },
  31874 #endif /* chips */
  31875 
  31876 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  31877     { /* SOC_REG_INT_L3_TABLE_HASH_CONTROL_BCM56960_A0r */
  31878         soc_block_list[5],
  31879         soc_genreg,
  31880         1,
  31881         0,
  31882         0x3a002900,
  31883         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31884         0,
  31885         5,
  31886         soc_L3_TABLE_HASH_CONTROL_BCM56960_A0r_fields,
  31887         SOC_RESET_VAL_DEC(0x00c30c30, 0x00000000)
  31888         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  31889         -1,
  31890         -1,
  31891         3,
  31892     },
  31893 #endif /* chips */
  31894 
  31895 #if defined(BCM_56970_A0)
  31896     { /* SOC_REG_INT_L3_TABLE_HASH_CONTROL_BCM56970_A0r */
  31897         soc_block_list[5],
  31898         soc_genreg,
  31899         1,
  31900         0,
  31901         0x5e002a00,
  31902         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31903         0,
  31904         5,
  31905         soc_L3_TABLE_HASH_CONTROL_BCM56960_A0r_fields,
  31906         SOC_RESET_VAL_DEC(0x00c30c30, 0x00000000)
  31907         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  31908         -1,
  31909         -1,
  31910         3,
  31911     },
  31912 #endif /* chips */
  31913 
  31914 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  31915     defined(BCM_56870_A0)
  31916     { /* SOC_REG_INT_L3_TUNNEL_BIST_CONFIG_64r */
  31917         soc_block_list[5],
  31918         soc_genreg,
  31919         1,
  31920         0,
  31921         0x57000000,
  31922         SOC_REG_FLAG_64_BITS |
  31923                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31924         0,
  31925         3,
  31926         soc_IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64r_fields,
  31927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31928         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31929         -1,
  31930         -1,
  31931         3,
  31932     },
  31933 #endif /* chips */
  31934 
  31935 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  31936     defined(BCM_56870_A0)
  31937     { /* SOC_REG_INT_L3_TUNNEL_BIST_CONFIG_64_PIPE0r */
  31938         soc_block_list[5],
  31939         soc_genreg,
  31940         1,
  31941         0,
  31942         0x57000000,
  31943         SOC_REG_FLAG_64_BITS,
  31944         0,
  31945         3,
  31946         soc_IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64r_fields,
  31947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31948         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31949         -1,
  31950         -1,
  31951         3,
  31952     },
  31953 #endif /* chips */
  31954 
  31955 #if defined(BCM_56870_A0)
  31956     { /* SOC_REG_INT_L3_TUNNEL_BIST_CONFIG_64_PIPE1r */
  31957         soc_block_list[5],
  31958         soc_genreg,
  31959         1,
  31960         0,
  31961         0x57000000,
  31962         SOC_REG_FLAG_64_BITS |
  31963                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31964         0,
  31965         3,
  31966         soc_IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64r_fields,
  31967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31968         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31969         -1,
  31970         -1,
  31971         3,
  31972     },
  31973 #endif /* chips */
  31974 
  31975 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  31976     defined(BCM_56870_A0)
  31977     { /* SOC_REG_INT_L3_TUNNEL_BIST_STATUSr */
  31978         soc_block_list[5],
  31979         soc_genreg,
  31980         1,
  31981         0,
  31982         0x57010000,
  31983         SOC_REG_FLAG_RO |
  31984                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  31985         0,
  31986         1,
  31987         soc_SUBPORT_TAG_SGPP_MAP_CAM_BIST_STATUS_BCM56560_A0r_fields,
  31988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31990         -1,
  31991         -1,
  31992         3,
  31993     },
  31994 #endif /* chips */
  31995 
  31996 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  31997     defined(BCM_56870_A0)
  31998     { /* SOC_REG_INT_L3_TUNNEL_BIST_STATUS_PIPE0r */
  31999         soc_block_list[5],
  32000         soc_genreg,
  32001         1,
  32002         0,
  32003         0x57010000,
  32004         SOC_REG_FLAG_RO,
  32005         0,
  32006         1,
  32007         soc_SUBPORT_TAG_SGPP_MAP_CAM_BIST_STATUS_BCM56560_A0r_fields,
  32008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32010         -1,
  32011         -1,
  32012         3,
  32013     },
  32014 #endif /* chips */
  32015 
  32016 #if defined(BCM_56870_A0)
  32017     { /* SOC_REG_INT_L3_TUNNEL_BIST_STATUS_PIPE1r */
  32018         soc_block_list[5],
  32019         soc_genreg,
  32020         1,
  32021         0,
  32022         0x57010000,
  32023         SOC_REG_FLAG_RO |
  32024                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32025         0,
  32026         1,
  32027         soc_SUBPORT_TAG_SGPP_MAP_CAM_BIST_STATUS_BCM56560_A0r_fields,
  32028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32030         -1,
  32031         -1,
  32032         3,
  32033     },
  32034 #endif /* chips */
  32035 
  32036 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  32037     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  32038     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIGr */
  32039         soc_block_list[5],
  32040         soc_genreg,
  32041         1,
  32042         0,
  32043         0x2080104,
  32044         0,
  32045         0,
  32046         4,
  32047         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  32048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32050         -1,
  32051         -1,
  32052     },
  32053 #endif /* chips */
  32054 
  32055 #if defined(BCM_56970_A0)
  32056     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_64r */
  32057         soc_block_list[5],
  32058         soc_genreg,
  32059         1,
  32060         0,
  32061         0x53030000,
  32062         SOC_REG_FLAG_64_BITS |
  32063                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32064         0,
  32065         5,
  32066         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  32067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32068         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32069         -1,
  32070         -1,
  32071         0,
  32072     },
  32073 #endif /* chips */
  32074 
  32075 #if defined(BCM_56970_A0)
  32076     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE0r */
  32077         soc_block_list[5],
  32078         soc_genreg,
  32079         1,
  32080         0,
  32081         0x53030000,
  32082         SOC_REG_FLAG_64_BITS,
  32083         0,
  32084         5,
  32085         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  32086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32088         -1,
  32089         -1,
  32090         0,
  32091     },
  32092 #endif /* chips */
  32093 
  32094 #if defined(BCM_56970_A0)
  32095     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE1r */
  32096         soc_block_list[5],
  32097         soc_genreg,
  32098         1,
  32099         0,
  32100         0x53030000,
  32101         SOC_REG_FLAG_64_BITS |
  32102                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32103         0,
  32104         5,
  32105         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  32106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32107         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32108         -1,
  32109         -1,
  32110         0,
  32111     },
  32112 #endif /* chips */
  32113 
  32114 #if defined(BCM_56970_A0)
  32115     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE2r */
  32116         soc_block_list[5],
  32117         soc_genreg,
  32118         1,
  32119         0,
  32120         0x53030000,
  32121         SOC_REG_FLAG_64_BITS |
  32122                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32123         0,
  32124         5,
  32125         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  32126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32127         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32128         -1,
  32129         -1,
  32130         0,
  32131     },
  32132 #endif /* chips */
  32133 
  32134 #if defined(BCM_56970_A0)
  32135     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE3r */
  32136         soc_block_list[5],
  32137         soc_genreg,
  32138         1,
  32139         0,
  32140         0x53030000,
  32141         SOC_REG_FLAG_64_BITS |
  32142                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32143         0,
  32144         5,
  32145         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  32146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32148         -1,
  32149         -1,
  32150         0,
  32151     },
  32152 #endif /* chips */
  32153 
  32154 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32155     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32156     defined(BCM_56160_A0)
  32157     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM53400_A0r */
  32158         soc_block_list[5],
  32159         soc_genreg,
  32160         1,
  32161         0,
  32162         0xa010200,
  32163         0,
  32164         0,
  32165         4,
  32166         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  32167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32169         -1,
  32170         -1,
  32171     },
  32172 #endif /* chips */
  32173 
  32174 #if defined(BCM_56150_A0)
  32175     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56150_A0r */
  32176         soc_block_list[5],
  32177         soc_genreg,
  32178         1,
  32179         0,
  32180         0xa010200,
  32181         0,
  32182         0,
  32183         4,
  32184         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
  32185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32187         -1,
  32188         -1,
  32189     },
  32190 #endif /* chips */
  32191 
  32192 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  32193     defined(BCM_56270_A0)
  32194     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56260_A0r */
  32195         soc_block_list[5],
  32196         soc_genreg,
  32197         1,
  32198         0,
  32199         0xa010200,
  32200         0,
  32201         0,
  32202         4,
  32203         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  32204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32206         -1,
  32207         -1,
  32208     },
  32209 #endif /* chips */
  32210 
  32211 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  32212     defined(BCM_56334_B0)
  32213     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56334_A0r */
  32214         soc_block_list[5],
  32215         soc_genreg,
  32216         1,
  32217         0,
  32218         0x208010c,
  32219         0,
  32220         0,
  32221         4,
  32222         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  32223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32224         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32225         -1,
  32226         -1,
  32227     },
  32228 #endif /* chips */
  32229 
  32230 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  32231     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  32232     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56560_A0r */
  32233         soc_block_list[5],
  32234         soc_genreg,
  32235         1,
  32236         0,
  32237         0xb020000,
  32238         0,
  32239         0,
  32240         4,
  32241         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  32242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32243         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32244         -1,
  32245         -1,
  32246     },
  32247 #endif /* chips */
  32248 
  32249 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  32250     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  32251     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  32252     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56634_A0r */
  32253         soc_block_list[5],
  32254         soc_genreg,
  32255         1,
  32256         0,
  32257         0x2080112,
  32258         0,
  32259         0,
  32260         4,
  32261         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  32262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32264         -1,
  32265         -1,
  32266     },
  32267 #endif /* chips */
  32268 
  32269 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32270     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  32271     defined(BCM_56640_A0)
  32272     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56640_A0r */
  32273         soc_block_list[5],
  32274         soc_genreg,
  32275         1,
  32276         0,
  32277         0xa010200,
  32278         0,
  32279         0,
  32280         4,
  32281         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
  32282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32284         -1,
  32285         -1,
  32286     },
  32287 #endif /* chips */
  32288 
  32289 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  32290     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56820_A0r */
  32291         soc_block_list[5],
  32292         soc_genreg,
  32293         1,
  32294         0,
  32295         0x2080c10,
  32296         0,
  32297         0,
  32298         4,
  32299         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  32300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32302         -1,
  32303         -1,
  32304     },
  32305 #endif /* chips */
  32306 
  32307 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  32308     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  32309     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56840_A0r */
  32310         soc_block_list[5],
  32311         soc_genreg,
  32312         1,
  32313         0,
  32314         0x2080d02,
  32315         0,
  32316         0,
  32317         4,
  32318         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  32319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32321         -1,
  32322         -1,
  32323     },
  32324 #endif /* chips */
  32325 
  32326 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  32327     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56850_A0r */
  32328         soc_block_list[5],
  32329         soc_genreg,
  32330         1,
  32331         0,
  32332         0xb020000,
  32333         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32334         0,
  32335         4,
  32336         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
  32337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32339         -1,
  32340         -1,
  32341     },
  32342 #endif /* chips */
  32343 
  32344 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32345     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_BCM56960_A0r */
  32346         soc_block_list[5],
  32347         soc_genreg,
  32348         1,
  32349         0,
  32350         0x2f020000,
  32351         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32352         0,
  32353         4,
  32354         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  32355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32357         -1,
  32358         -1,
  32359         0,
  32360     },
  32361 #endif /* chips */
  32362 
  32363 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32364     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_PIPE0r */
  32365         soc_block_list[5],
  32366         soc_genreg,
  32367         1,
  32368         0,
  32369         0x2f020000,
  32370         0,
  32371         0,
  32372         4,
  32373         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  32374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32375         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32376         -1,
  32377         -1,
  32378         0,
  32379     },
  32380 #endif /* chips */
  32381 
  32382 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32383     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_PIPE1r */
  32384         soc_block_list[5],
  32385         soc_genreg,
  32386         1,
  32387         0,
  32388         0x2f020000,
  32389         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32390         0,
  32391         4,
  32392         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  32393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32394         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32395         -1,
  32396         -1,
  32397         0,
  32398     },
  32399 #endif /* chips */
  32400 
  32401 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32402     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_PIPE2r */
  32403         soc_block_list[5],
  32404         soc_genreg,
  32405         1,
  32406         0,
  32407         0x2f020000,
  32408         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32409         0,
  32410         4,
  32411         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  32412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32413         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32414         -1,
  32415         -1,
  32416         0,
  32417     },
  32418 #endif /* chips */
  32419 
  32420 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32421     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_CONFIG_PIPE3r */
  32422         soc_block_list[5],
  32423         soc_genreg,
  32424         1,
  32425         0,
  32426         0x2f020000,
  32427         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32428         0,
  32429         4,
  32430         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  32431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32433         -1,
  32434         -1,
  32435         0,
  32436     },
  32437 #endif /* chips */
  32438 
  32439 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  32440     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  32441     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATAr */
  32442         soc_block_list[5],
  32443         soc_genreg,
  32444         1,
  32445         0,
  32446         0x2080105,
  32447         SOC_REG_FLAG_WO,
  32448         0,
  32449         1,
  32450         soc_FP_CAM_DEBUG_DATA_0r_fields,
  32451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32452         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32453         -1,
  32454         -1,
  32455     },
  32456 #endif /* chips */
  32457 
  32458 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32459     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32460     defined(BCM_56160_A0)
  32461     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM53400_A0r */
  32462         soc_block_list[5],
  32463         soc_genreg,
  32464         1,
  32465         0,
  32466         0xa010300,
  32467         SOC_REG_FLAG_WO,
  32468         0,
  32469         1,
  32470         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  32471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32472         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32473         -1,
  32474         -1,
  32475     },
  32476 #endif /* chips */
  32477 
  32478 #if defined(BCM_56150_A0)
  32479     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56150_A0r */
  32480         soc_block_list[5],
  32481         soc_genreg,
  32482         1,
  32483         0,
  32484         0xa010300,
  32485         SOC_REG_FLAG_WO,
  32486         0,
  32487         1,
  32488         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
  32489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32490         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32491         -1,
  32492         -1,
  32493     },
  32494 #endif /* chips */
  32495 
  32496 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  32497     defined(BCM_56270_A0)
  32498     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56260_A0r */
  32499         soc_block_list[5],
  32500         soc_genreg,
  32501         1,
  32502         0,
  32503         0xa010300,
  32504         SOC_REG_FLAG_WO,
  32505         0,
  32506         1,
  32507         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  32508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32509         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32510         -1,
  32511         -1,
  32512     },
  32513 #endif /* chips */
  32514 
  32515 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  32516     defined(BCM_56334_B0)
  32517     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56334_A0r */
  32518         soc_block_list[5],
  32519         soc_genreg,
  32520         1,
  32521         0,
  32522         0x208010d,
  32523         SOC_REG_FLAG_WO,
  32524         0,
  32525         1,
  32526         soc_FP_CAM_DEBUG_DATA_0r_fields,
  32527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32528         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32529         -1,
  32530         -1,
  32531     },
  32532 #endif /* chips */
  32533 
  32534 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  32535     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  32536     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56560_A0r */
  32537         soc_block_list[5],
  32538         soc_genreg,
  32539         1,
  32540         0,
  32541         0xb030000,
  32542         SOC_REG_FLAG_WO,
  32543         0,
  32544         1,
  32545         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  32546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32547         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32548         -1,
  32549         -1,
  32550     },
  32551 #endif /* chips */
  32552 
  32553 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  32554     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  32555     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  32556     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56634_A0r */
  32557         soc_block_list[5],
  32558         soc_genreg,
  32559         1,
  32560         0,
  32561         0x2080113,
  32562         SOC_REG_FLAG_WO,
  32563         0,
  32564         1,
  32565         soc_FP_CAM_DEBUG_DATA_0r_fields,
  32566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32567         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32568         -1,
  32569         -1,
  32570     },
  32571 #endif /* chips */
  32572 
  32573 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32574     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  32575     defined(BCM_56640_A0)
  32576     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56640_A0r */
  32577         soc_block_list[5],
  32578         soc_genreg,
  32579         1,
  32580         0,
  32581         0xa010300,
  32582         SOC_REG_FLAG_WO,
  32583         0,
  32584         1,
  32585         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
  32586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32587         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32588         -1,
  32589         -1,
  32590     },
  32591 #endif /* chips */
  32592 
  32593 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  32594     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56820_A0r */
  32595         soc_block_list[5],
  32596         soc_genreg,
  32597         1,
  32598         0,
  32599         0x2080c11,
  32600         SOC_REG_FLAG_WO,
  32601         0,
  32602         1,
  32603         soc_FP_CAM_DEBUG_DATA_0r_fields,
  32604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32605         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32606         -1,
  32607         -1,
  32608     },
  32609 #endif /* chips */
  32610 
  32611 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  32612     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  32613     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56840_A0r */
  32614         soc_block_list[5],
  32615         soc_genreg,
  32616         1,
  32617         0,
  32618         0x2080d03,
  32619         SOC_REG_FLAG_WO,
  32620         0,
  32621         1,
  32622         soc_FP_CAM_DEBUG_DATA_0r_fields,
  32623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32624         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32625         -1,
  32626         -1,
  32627     },
  32628 #endif /* chips */
  32629 
  32630 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  32631     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56850_A0r */
  32632         soc_block_list[5],
  32633         soc_genreg,
  32634         1,
  32635         0,
  32636         0xb030000,
  32637         SOC_REG_FLAG_WO |
  32638                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32639         0,
  32640         1,
  32641         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
  32642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32643         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32644         -1,
  32645         -1,
  32646     },
  32647 #endif /* chips */
  32648 
  32649 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32650     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_BCM56960_A0r */
  32651         soc_block_list[5],
  32652         soc_genreg,
  32653         1,
  32654         0,
  32655         0x2f030000,
  32656         SOC_REG_FLAG_WO |
  32657                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32658         0,
  32659         1,
  32660         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  32661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32662         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32663         -1,
  32664         -1,
  32665         0,
  32666     },
  32667 #endif /* chips */
  32668 
  32669 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32670     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_PIPE0r */
  32671         soc_block_list[5],
  32672         soc_genreg,
  32673         1,
  32674         0,
  32675         0x2f030000,
  32676         SOC_REG_FLAG_WO,
  32677         0,
  32678         1,
  32679         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  32680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32682         -1,
  32683         -1,
  32684         0,
  32685     },
  32686 #endif /* chips */
  32687 
  32688 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32689     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_PIPE1r */
  32690         soc_block_list[5],
  32691         soc_genreg,
  32692         1,
  32693         0,
  32694         0x2f030000,
  32695         SOC_REG_FLAG_WO |
  32696                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32697         0,
  32698         1,
  32699         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  32700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32701         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32702         -1,
  32703         -1,
  32704         0,
  32705     },
  32706 #endif /* chips */
  32707 
  32708 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32709     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_PIPE2r */
  32710         soc_block_list[5],
  32711         soc_genreg,
  32712         1,
  32713         0,
  32714         0x2f030000,
  32715         SOC_REG_FLAG_WO |
  32716                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32717         0,
  32718         1,
  32719         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  32720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32722         -1,
  32723         -1,
  32724         0,
  32725     },
  32726 #endif /* chips */
  32727 
  32728 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  32729     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_DBG_DATA_PIPE3r */
  32730         soc_block_list[5],
  32731         soc_genreg,
  32732         1,
  32733         0,
  32734         0x2f030000,
  32735         SOC_REG_FLAG_WO |
  32736                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  32737         0,
  32738         1,
  32739         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  32740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32742         -1,
  32743         -1,
  32744         0,
  32745     },
  32746 #endif /* chips */
  32747 
  32748 #if defined(BCM_56504_A0)
  32749     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S10_STATUSr */
  32750         soc_block_list[6],
  32751         soc_genreg,
  32752         1,
  32753         0,
  32754         0x2080015,
  32755         SOC_REG_FLAG_RO,
  32756         0,
  32757         2,
  32758         soc_FP_CAM_BIST_S10_STATUSr_fields,
  32759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32760         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32761         -1,
  32762         -1,
  32763     },
  32764 #endif /* chips */
  32765 
  32766 #if defined(BCM_56314_A0) || defined(BCM_56504_B0)
  32767     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S10_STATUS_BCM56504_B0r */
  32768         soc_block_list[6],
  32769         soc_genreg,
  32770         1,
  32771         0,
  32772         0x2080015,
  32773         SOC_REG_FLAG_RO,
  32774         0,
  32775         1,
  32776         soc_L2_USER_ENTRY_CAM_BIST_S10_STATUSr_fields,
  32777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32778         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32779         -1,
  32780         -1,
  32781     },
  32782 #endif /* chips */
  32783 
  32784 #if defined(BCM_56514_A0)
  32785     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S10_STATUS_BCM56514_A0r */
  32786         soc_block_list[5],
  32787         soc_genreg,
  32788         1,
  32789         0,
  32790         0x2080015,
  32791         SOC_REG_FLAG_RO,
  32792         0,
  32793         1,
  32794         soc_L2_USER_ENTRY_CAM_BIST_S10_STATUSr_fields,
  32795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32796         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32797         -1,
  32798         -1,
  32799     },
  32800 #endif /* chips */
  32801 
  32802 #if defined(BCM_56800_A0)
  32803     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S10_STATUS_BCM56800_A0r */
  32804         soc_block_list[5],
  32805         soc_genreg,
  32806         1,
  32807         0,
  32808         0x2080c15,
  32809         SOC_REG_FLAG_RO,
  32810         0,
  32811         2,
  32812         soc_FP_CAM_BIST_S10_STATUSr_fields,
  32813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32814         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32815         -1,
  32816         -1,
  32817     },
  32818 #endif /* chips */
  32819 
  32820 #if defined(BCM_56504_A0)
  32821     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S2_STATUSr */
  32822         soc_block_list[6],
  32823         soc_genreg,
  32824         1,
  32825         0,
  32826         0x2080010,
  32827         SOC_REG_FLAG_RO,
  32828         0,
  32829         3,
  32830         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  32831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32833         -1,
  32834         -1,
  32835     },
  32836 #endif /* chips */
  32837 
  32838 #if defined(BCM_56314_A0) || defined(BCM_56504_B0)
  32839     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S2_STATUS_BCM56504_B0r */
  32840         soc_block_list[6],
  32841         soc_genreg,
  32842         1,
  32843         0,
  32844         0x2080010,
  32845         SOC_REG_FLAG_RO,
  32846         0,
  32847         1,
  32848         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUS_BCM56504_B0r_fields,
  32849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32851         -1,
  32852         -1,
  32853     },
  32854 #endif /* chips */
  32855 
  32856 #if defined(BCM_56514_A0)
  32857     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S2_STATUS_BCM56514_A0r */
  32858         soc_block_list[5],
  32859         soc_genreg,
  32860         1,
  32861         0,
  32862         0x2080010,
  32863         SOC_REG_FLAG_RO,
  32864         0,
  32865         1,
  32866         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUS_BCM56504_B0r_fields,
  32867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32868         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32869         -1,
  32870         -1,
  32871     },
  32872 #endif /* chips */
  32873 
  32874 #if defined(BCM_56800_A0)
  32875     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S2_STATUS_BCM56800_A0r */
  32876         soc_block_list[5],
  32877         soc_genreg,
  32878         1,
  32879         0,
  32880         0x2080c10,
  32881         SOC_REG_FLAG_RO,
  32882         0,
  32883         3,
  32884         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  32885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32886         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32887         -1,
  32888         -1,
  32889     },
  32890 #endif /* chips */
  32891 
  32892 #if defined(BCM_56504_A0)
  32893     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S3_STATUSr */
  32894         soc_block_list[6],
  32895         soc_genreg,
  32896         1,
  32897         0,
  32898         0x2080011,
  32899         SOC_REG_FLAG_RO,
  32900         0,
  32901         4,
  32902         soc_FP_CAM_BIST_S12_STATUSr_fields,
  32903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32904         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32905         -1,
  32906         -1,
  32907     },
  32908 #endif /* chips */
  32909 
  32910 #if defined(BCM_56314_A0) || defined(BCM_56504_B0)
  32911     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S3_STATUS_BCM56504_B0r */
  32912         soc_block_list[6],
  32913         soc_genreg,
  32914         1,
  32915         0,
  32916         0x2080011,
  32917         SOC_REG_FLAG_RO,
  32918         0,
  32919         1,
  32920         soc_L2_USER_ENTRY_CAM_BIST_S3_STATUSr_fields,
  32921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32922         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32923         -1,
  32924         -1,
  32925     },
  32926 #endif /* chips */
  32927 
  32928 #if defined(BCM_56514_A0)
  32929     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S3_STATUS_BCM56514_A0r */
  32930         soc_block_list[5],
  32931         soc_genreg,
  32932         1,
  32933         0,
  32934         0x2080011,
  32935         SOC_REG_FLAG_RO,
  32936         0,
  32937         1,
  32938         soc_L2_USER_ENTRY_CAM_BIST_S3_STATUSr_fields,
  32939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32940         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32941         -1,
  32942         -1,
  32943     },
  32944 #endif /* chips */
  32945 
  32946 #if defined(BCM_56800_A0)
  32947     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S3_STATUS_BCM56800_A0r */
  32948         soc_block_list[5],
  32949         soc_genreg,
  32950         1,
  32951         0,
  32952         0x2080c11,
  32953         SOC_REG_FLAG_RO,
  32954         0,
  32955         4,
  32956         soc_FP_CAM_BIST_S12_STATUSr_fields,
  32957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32959         -1,
  32960         -1,
  32961     },
  32962 #endif /* chips */
  32963 
  32964 #if defined(BCM_56504_A0)
  32965     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S5_STATUSr */
  32966         soc_block_list[6],
  32967         soc_genreg,
  32968         1,
  32969         0,
  32970         0x2080012,
  32971         SOC_REG_FLAG_RO,
  32972         0,
  32973         3,
  32974         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  32975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32976         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32977         -1,
  32978         -1,
  32979     },
  32980 #endif /* chips */
  32981 
  32982 #if defined(BCM_56314_A0) || defined(BCM_56504_B0)
  32983     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S5_STATUS_BCM56504_B0r */
  32984         soc_block_list[6],
  32985         soc_genreg,
  32986         1,
  32987         0,
  32988         0x2080012,
  32989         SOC_REG_FLAG_RO,
  32990         0,
  32991         1,
  32992         soc_L2_USER_ENTRY_CAM_BIST_S5_STATUSr_fields,
  32993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32994         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32995         -1,
  32996         -1,
  32997     },
  32998 #endif /* chips */
  32999 
  33000 #if defined(BCM_56514_A0)
  33001     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S5_STATUS_BCM56514_A0r */
  33002         soc_block_list[5],
  33003         soc_genreg,
  33004         1,
  33005         0,
  33006         0x2080012,
  33007         SOC_REG_FLAG_RO,
  33008         0,
  33009         1,
  33010         soc_L2_USER_ENTRY_CAM_BIST_S5_STATUSr_fields,
  33011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33012         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33013         -1,
  33014         -1,
  33015     },
  33016 #endif /* chips */
  33017 
  33018 #if defined(BCM_56800_A0)
  33019     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S5_STATUS_BCM56800_A0r */
  33020         soc_block_list[5],
  33021         soc_genreg,
  33022         1,
  33023         0,
  33024         0x2080c12,
  33025         SOC_REG_FLAG_RO,
  33026         0,
  33027         3,
  33028         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  33029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33030         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33031         -1,
  33032         -1,
  33033     },
  33034 #endif /* chips */
  33035 
  33036 #if defined(BCM_56504_A0)
  33037     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S6_STATUSr */
  33038         soc_block_list[6],
  33039         soc_genreg,
  33040         1,
  33041         0,
  33042         0x2080013,
  33043         SOC_REG_FLAG_RO,
  33044         0,
  33045         4,
  33046         soc_FP_CAM_BIST_S12_STATUSr_fields,
  33047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33048         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33049         -1,
  33050         -1,
  33051     },
  33052 #endif /* chips */
  33053 
  33054 #if defined(BCM_56314_A0) || defined(BCM_56504_B0)
  33055     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S6_STATUS_BCM56504_B0r */
  33056         soc_block_list[6],
  33057         soc_genreg,
  33058         1,
  33059         0,
  33060         0x2080013,
  33061         SOC_REG_FLAG_RO,
  33062         0,
  33063         1,
  33064         soc_L2_USER_ENTRY_CAM_BIST_S6_STATUSr_fields,
  33065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33066         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33067         -1,
  33068         -1,
  33069     },
  33070 #endif /* chips */
  33071 
  33072 #if defined(BCM_56514_A0)
  33073     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S6_STATUS_BCM56514_A0r */
  33074         soc_block_list[5],
  33075         soc_genreg,
  33076         1,
  33077         0,
  33078         0x2080013,
  33079         SOC_REG_FLAG_RO,
  33080         0,
  33081         1,
  33082         soc_L2_USER_ENTRY_CAM_BIST_S6_STATUSr_fields,
  33083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33084         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33085         -1,
  33086         -1,
  33087     },
  33088 #endif /* chips */
  33089 
  33090 #if defined(BCM_56800_A0)
  33091     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S6_STATUS_BCM56800_A0r */
  33092         soc_block_list[5],
  33093         soc_genreg,
  33094         1,
  33095         0,
  33096         0x2080c13,
  33097         SOC_REG_FLAG_RO,
  33098         0,
  33099         4,
  33100         soc_FP_CAM_BIST_S12_STATUSr_fields,
  33101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33102         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33103         -1,
  33104         -1,
  33105     },
  33106 #endif /* chips */
  33107 
  33108 #if defined(BCM_56504_A0)
  33109     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S8_STATUSr */
  33110         soc_block_list[6],
  33111         soc_genreg,
  33112         1,
  33113         0,
  33114         0x2080014,
  33115         SOC_REG_FLAG_RO,
  33116         0,
  33117         4,
  33118         soc_FP_CAM_BIST_S12_STATUSr_fields,
  33119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33120         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33121         -1,
  33122         -1,
  33123     },
  33124 #endif /* chips */
  33125 
  33126 #if defined(BCM_56314_A0) || defined(BCM_56504_B0)
  33127     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S8_STATUS_BCM56504_B0r */
  33128         soc_block_list[6],
  33129         soc_genreg,
  33130         1,
  33131         0,
  33132         0x2080014,
  33133         SOC_REG_FLAG_RO,
  33134         0,
  33135         1,
  33136         soc_L2_USER_ENTRY_CAM_BIST_S8_STATUSr_fields,
  33137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33138         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33139         -1,
  33140         -1,
  33141     },
  33142 #endif /* chips */
  33143 
  33144 #if defined(BCM_56514_A0)
  33145     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S8_STATUS_BCM56514_A0r */
  33146         soc_block_list[5],
  33147         soc_genreg,
  33148         1,
  33149         0,
  33150         0x2080014,
  33151         SOC_REG_FLAG_RO,
  33152         0,
  33153         1,
  33154         soc_L2_USER_ENTRY_CAM_BIST_S8_STATUSr_fields,
  33155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33156         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33157         -1,
  33158         -1,
  33159     },
  33160 #endif /* chips */
  33161 
  33162 #if defined(BCM_56800_A0)
  33163     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_S8_STATUS_BCM56800_A0r */
  33164         soc_block_list[5],
  33165         soc_genreg,
  33166         1,
  33167         0,
  33168         0x2080c14,
  33169         SOC_REG_FLAG_RO,
  33170         0,
  33171         4,
  33172         soc_FP_CAM_BIST_S12_STATUSr_fields,
  33173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33174         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33175         -1,
  33176         -1,
  33177     },
  33178 #endif /* chips */
  33179 
  33180 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  33181     defined(BCM_56504_B0)
  33182     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUSr */
  33183         soc_block_list[6],
  33184         soc_genreg,
  33185         1,
  33186         0,
  33187         0x2080017,
  33188         SOC_REG_FLAG_RO,
  33189         0,
  33190         2,
  33191         soc_EGR_VXLT_CAM_BIST_STATUSr_fields,
  33192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33193         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33194         -1,
  33195         -1,
  33196     },
  33197 #endif /* chips */
  33198 
  33199 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33200     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33201     defined(BCM_56160_A0)
  33202     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM53400_A0r */
  33203         soc_block_list[5],
  33204         soc_genreg,
  33205         1,
  33206         0,
  33207         0xa010100,
  33208         SOC_REG_FLAG_RO,
  33209         0,
  33210         1,
  33211         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33213         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33214         -1,
  33215         -1,
  33216     },
  33217 #endif /* chips */
  33218 
  33219 #if defined(BCM_56150_A0)
  33220     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56150_A0r */
  33221         soc_block_list[5],
  33222         soc_genreg,
  33223         1,
  33224         0,
  33225         0xa010100,
  33226         SOC_REG_FLAG_RO,
  33227         0,
  33228         1,
  33229         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  33230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33232         -1,
  33233         -1,
  33234     },
  33235 #endif /* chips */
  33236 
  33237 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  33238     defined(BCM_56270_A0)
  33239     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56260_A0r */
  33240         soc_block_list[5],
  33241         soc_genreg,
  33242         1,
  33243         0,
  33244         0xa010100,
  33245         SOC_REG_FLAG_RO,
  33246         0,
  33247         1,
  33248         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33250         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33251         -1,
  33252         -1,
  33253     },
  33254 #endif /* chips */
  33255 
  33256 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  33257     defined(BCM_56334_B0)
  33258     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56334_A0r */
  33259         soc_block_list[5],
  33260         soc_genreg,
  33261         1,
  33262         0,
  33263         0x208010b,
  33264         SOC_REG_FLAG_RO,
  33265         0,
  33266         1,
  33267         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  33268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33269         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33270         -1,
  33271         -1,
  33272     },
  33273 #endif /* chips */
  33274 
  33275 #if defined(BCM_56514_A0)
  33276     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56514_A0r */
  33277         soc_block_list[5],
  33278         soc_genreg,
  33279         1,
  33280         0,
  33281         0x2080017,
  33282         SOC_REG_FLAG_RO,
  33283         0,
  33284         2,
  33285         soc_EGR_VXLT_CAM_BIST_STATUSr_fields,
  33286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33288         -1,
  33289         -1,
  33290     },
  33291 #endif /* chips */
  33292 
  33293 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  33294     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  33295     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56560_A0r */
  33296         soc_block_list[5],
  33297         soc_genreg,
  33298         1,
  33299         0,
  33300         0xb010000,
  33301         SOC_REG_FLAG_RO,
  33302         0,
  33303         1,
  33304         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33307         -1,
  33308         -1,
  33309     },
  33310 #endif /* chips */
  33311 
  33312 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  33313     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  33314     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56624_A0r */
  33315         soc_block_list[5],
  33316         soc_genreg,
  33317         1,
  33318         0,
  33319         0x2080103,
  33320         SOC_REG_FLAG_RO,
  33321         0,
  33322         1,
  33323         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  33324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33326         -1,
  33327         -1,
  33328     },
  33329 #endif /* chips */
  33330 
  33331 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  33332     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  33333     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  33334     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56634_A0r */
  33335         soc_block_list[5],
  33336         soc_genreg,
  33337         1,
  33338         0,
  33339         0x2080111,
  33340         SOC_REG_FLAG_RO,
  33341         0,
  33342         1,
  33343         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  33344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33346         -1,
  33347         -1,
  33348     },
  33349 #endif /* chips */
  33350 
  33351 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  33352     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  33353     defined(BCM_56640_A0)
  33354     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56640_A0r */
  33355         soc_block_list[5],
  33356         soc_genreg,
  33357         1,
  33358         0,
  33359         0xa010100,
  33360         SOC_REG_FLAG_RO,
  33361         0,
  33362         1,
  33363         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  33364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33365         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33366         -1,
  33367         -1,
  33368     },
  33369 #endif /* chips */
  33370 
  33371 #if defined(BCM_56800_A0)
  33372     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56800_A0r */
  33373         soc_block_list[5],
  33374         soc_genreg,
  33375         1,
  33376         0,
  33377         0x2080c17,
  33378         SOC_REG_FLAG_RO,
  33379         0,
  33380         2,
  33381         soc_EGR_VXLT_CAM_BIST_STATUSr_fields,
  33382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33384         -1,
  33385         -1,
  33386     },
  33387 #endif /* chips */
  33388 
  33389 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  33390     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56820_A0r */
  33391         soc_block_list[5],
  33392         soc_genreg,
  33393         1,
  33394         0,
  33395         0x2080c17,
  33396         SOC_REG_FLAG_RO,
  33397         0,
  33398         1,
  33399         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  33400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33402         -1,
  33403         -1,
  33404     },
  33405 #endif /* chips */
  33406 
  33407 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  33408     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  33409     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56840_A0r */
  33410         soc_block_list[5],
  33411         soc_genreg,
  33412         1,
  33413         0,
  33414         0x2080d01,
  33415         SOC_REG_FLAG_RO,
  33416         0,
  33417         1,
  33418         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  33419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33420         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33421         -1,
  33422         -1,
  33423     },
  33424 #endif /* chips */
  33425 
  33426 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  33427     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56850_A0r */
  33428         soc_block_list[5],
  33429         soc_genreg,
  33430         1,
  33431         0,
  33432         0xb010000,
  33433         SOC_REG_FLAG_RO |
  33434                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33435         0,
  33436         1,
  33437         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  33438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33439         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33440         -1,
  33441         -1,
  33442     },
  33443 #endif /* chips */
  33444 
  33445 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33446     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56960_A0r */
  33447         soc_block_list[5],
  33448         soc_genreg,
  33449         1,
  33450         0,
  33451         0x2f010000,
  33452         SOC_REG_FLAG_RO |
  33453                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33454         0,
  33455         1,
  33456         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33458         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33459         -1,
  33460         -1,
  33461         0,
  33462     },
  33463 #endif /* chips */
  33464 
  33465 #if defined(BCM_56970_A0)
  33466     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_BCM56970_A0r */
  33467         soc_block_list[5],
  33468         soc_genreg,
  33469         1,
  33470         0,
  33471         0x53020000,
  33472         SOC_REG_FLAG_RO |
  33473                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33474         0,
  33475         1,
  33476         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33479         -1,
  33480         -1,
  33481         0,
  33482     },
  33483 #endif /* chips */
  33484 
  33485 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33486     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_PIPE0r */
  33487         soc_block_list[5],
  33488         soc_genreg,
  33489         1,
  33490         0,
  33491         0x2f010000,
  33492         SOC_REG_FLAG_RO,
  33493         0,
  33494         1,
  33495         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33497         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33498         -1,
  33499         -1,
  33500         0,
  33501     },
  33502 #endif /* chips */
  33503 
  33504 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33505     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_PIPE1r */
  33506         soc_block_list[5],
  33507         soc_genreg,
  33508         1,
  33509         0,
  33510         0x2f010000,
  33511         SOC_REG_FLAG_RO |
  33512                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33513         0,
  33514         1,
  33515         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33517         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33518         -1,
  33519         -1,
  33520         0,
  33521     },
  33522 #endif /* chips */
  33523 
  33524 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33525     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_PIPE2r */
  33526         soc_block_list[5],
  33527         soc_genreg,
  33528         1,
  33529         0,
  33530         0x2f010000,
  33531         SOC_REG_FLAG_RO |
  33532                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33533         0,
  33534         1,
  33535         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33538         -1,
  33539         -1,
  33540         0,
  33541     },
  33542 #endif /* chips */
  33543 
  33544 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33545     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_PIPE3r */
  33546         soc_block_list[5],
  33547         soc_genreg,
  33548         1,
  33549         0,
  33550         0x2f010000,
  33551         SOC_REG_FLAG_RO |
  33552                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33553         0,
  33554         1,
  33555         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33558         -1,
  33559         -1,
  33560         0,
  33561     },
  33562 #endif /* chips */
  33563 
  33564 #if defined(BCM_56970_A0)
  33565     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_PIPE0_BCM56970_A0r */
  33566         soc_block_list[5],
  33567         soc_genreg,
  33568         1,
  33569         0,
  33570         0x53020000,
  33571         SOC_REG_FLAG_RO,
  33572         0,
  33573         1,
  33574         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33577         -1,
  33578         -1,
  33579         0,
  33580     },
  33581 #endif /* chips */
  33582 
  33583 #if defined(BCM_56970_A0)
  33584     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_PIPE1_BCM56970_A0r */
  33585         soc_block_list[5],
  33586         soc_genreg,
  33587         1,
  33588         0,
  33589         0x53020000,
  33590         SOC_REG_FLAG_RO |
  33591                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33592         0,
  33593         1,
  33594         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33596         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33597         -1,
  33598         -1,
  33599         0,
  33600     },
  33601 #endif /* chips */
  33602 
  33603 #if defined(BCM_56970_A0)
  33604     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_PIPE2_BCM56970_A0r */
  33605         soc_block_list[5],
  33606         soc_genreg,
  33607         1,
  33608         0,
  33609         0x53020000,
  33610         SOC_REG_FLAG_RO |
  33611                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33612         0,
  33613         1,
  33614         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33616         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33617         -1,
  33618         -1,
  33619         0,
  33620     },
  33621 #endif /* chips */
  33622 
  33623 #if defined(BCM_56970_A0)
  33624     { /* SOC_REG_INT_L3_TUNNEL_CAM_BIST_STATUS_PIPE3_BCM56970_A0r */
  33625         soc_block_list[5],
  33626         soc_genreg,
  33627         1,
  33628         0,
  33629         0x53020000,
  33630         SOC_REG_FLAG_RO |
  33631                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33632         0,
  33633         1,
  33634         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  33635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33636         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33637         -1,
  33638         -1,
  33639         0,
  33640     },
  33641 #endif /* chips */
  33642 
  33643 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  33644     defined(BCM_56504_B0)
  33645     { /* SOC_REG_INT_L3_TUNNEL_CAM_CONTROLr */
  33646         soc_block_list[6],
  33647         soc_genreg,
  33648         1,
  33649         0,
  33650         0x2080018,
  33651         0,
  33652         0,
  33653         2,
  33654         soc_EGR_VXLT_CAM_CONTROLr_fields,
  33655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33656         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33657         -1,
  33658         -1,
  33659     },
  33660 #endif /* chips */
  33661 
  33662 #if defined(BCM_56514_A0)
  33663     { /* SOC_REG_INT_L3_TUNNEL_CAM_CONTROL_BCM56514_A0r */
  33664         soc_block_list[5],
  33665         soc_genreg,
  33666         1,
  33667         0,
  33668         0x2080018,
  33669         0,
  33670         0,
  33671         2,
  33672         soc_EGR_VXLT_CAM_CONTROLr_fields,
  33673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33674         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33675         -1,
  33676         -1,
  33677     },
  33678 #endif /* chips */
  33679 
  33680 #if defined(BCM_56800_A0)
  33681     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRLr */
  33682         soc_block_list[5],
  33683         soc_genreg,
  33684         1,
  33685         0,
  33686         0x2080c18,
  33687         0,
  33688         0,
  33689         2,
  33690         soc_EGR_VXLT_CAM_CONTROL_BCM56800_A0r_fields,
  33691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33692         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33693         -1,
  33694         -1,
  33695     },
  33696 #endif /* chips */
  33697 
  33698 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33699     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64r */
  33700         soc_block_list[5],
  33701         soc_genreg,
  33702         1,
  33703         0,
  33704         0x2f000000,
  33705         SOC_REG_FLAG_64_BITS |
  33706                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33707         0,
  33708         5,
  33709         soc_L3_TUNNEL_CAM_DBGCTRL_64r_fields,
  33710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33711         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33712         -1,
  33713         -1,
  33714         0,
  33715     },
  33716 #endif /* chips */
  33717 
  33718 #if defined(BCM_56970_A0)
  33719     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64_BCM56970_A0r */
  33720         soc_block_list[5],
  33721         soc_genreg,
  33722         1,
  33723         0,
  33724         0x53000000,
  33725         SOC_REG_FLAG_64_BITS |
  33726                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33727         0,
  33728         5,
  33729         soc_L3_TUNNEL_CAM_DBGCTRL_64_BCM56970_A0r_fields,
  33730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33731         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33732         -1,
  33733         -1,
  33734         0,
  33735     },
  33736 #endif /* chips */
  33737 
  33738 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33739     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64_PIPE0r */
  33740         soc_block_list[5],
  33741         soc_genreg,
  33742         1,
  33743         0,
  33744         0x2f000000,
  33745         SOC_REG_FLAG_64_BITS,
  33746         0,
  33747         5,
  33748         soc_L3_TUNNEL_CAM_DBGCTRL_64r_fields,
  33749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33750         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33751         -1,
  33752         -1,
  33753         0,
  33754     },
  33755 #endif /* chips */
  33756 
  33757 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33758     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64_PIPE1r */
  33759         soc_block_list[5],
  33760         soc_genreg,
  33761         1,
  33762         0,
  33763         0x2f000000,
  33764         SOC_REG_FLAG_64_BITS |
  33765                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33766         0,
  33767         5,
  33768         soc_L3_TUNNEL_CAM_DBGCTRL_64r_fields,
  33769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33770         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33771         -1,
  33772         -1,
  33773         0,
  33774     },
  33775 #endif /* chips */
  33776 
  33777 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33778     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64_PIPE2r */
  33779         soc_block_list[5],
  33780         soc_genreg,
  33781         1,
  33782         0,
  33783         0x2f000000,
  33784         SOC_REG_FLAG_64_BITS |
  33785                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33786         0,
  33787         5,
  33788         soc_L3_TUNNEL_CAM_DBGCTRL_64r_fields,
  33789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33791         -1,
  33792         -1,
  33793         0,
  33794     },
  33795 #endif /* chips */
  33796 
  33797 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  33798     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64_PIPE3r */
  33799         soc_block_list[5],
  33800         soc_genreg,
  33801         1,
  33802         0,
  33803         0x2f000000,
  33804         SOC_REG_FLAG_64_BITS |
  33805                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33806         0,
  33807         5,
  33808         soc_L3_TUNNEL_CAM_DBGCTRL_64r_fields,
  33809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33810         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33811         -1,
  33812         -1,
  33813         0,
  33814     },
  33815 #endif /* chips */
  33816 
  33817 #if defined(BCM_56970_A0)
  33818     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64_PIPE0_BCM56970_A0r */
  33819         soc_block_list[5],
  33820         soc_genreg,
  33821         1,
  33822         0,
  33823         0x53000000,
  33824         SOC_REG_FLAG_64_BITS,
  33825         0,
  33826         5,
  33827         soc_L3_TUNNEL_CAM_DBGCTRL_64_BCM56970_A0r_fields,
  33828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33829         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33830         -1,
  33831         -1,
  33832         0,
  33833     },
  33834 #endif /* chips */
  33835 
  33836 #if defined(BCM_56970_A0)
  33837     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64_PIPE1_BCM56970_A0r */
  33838         soc_block_list[5],
  33839         soc_genreg,
  33840         1,
  33841         0,
  33842         0x53000000,
  33843         SOC_REG_FLAG_64_BITS |
  33844                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33845         0,
  33846         5,
  33847         soc_L3_TUNNEL_CAM_DBGCTRL_64_BCM56970_A0r_fields,
  33848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33850         -1,
  33851         -1,
  33852         0,
  33853     },
  33854 #endif /* chips */
  33855 
  33856 #if defined(BCM_56970_A0)
  33857     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64_PIPE2_BCM56970_A0r */
  33858         soc_block_list[5],
  33859         soc_genreg,
  33860         1,
  33861         0,
  33862         0x53000000,
  33863         SOC_REG_FLAG_64_BITS |
  33864                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33865         0,
  33866         5,
  33867         soc_L3_TUNNEL_CAM_DBGCTRL_64_BCM56970_A0r_fields,
  33868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33870         -1,
  33871         -1,
  33872         0,
  33873     },
  33874 #endif /* chips */
  33875 
  33876 #if defined(BCM_56970_A0)
  33877     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_64_PIPE3_BCM56970_A0r */
  33878         soc_block_list[5],
  33879         soc_genreg,
  33880         1,
  33881         0,
  33882         0x53000000,
  33883         SOC_REG_FLAG_64_BITS |
  33884                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  33885         0,
  33886         5,
  33887         soc_L3_TUNNEL_CAM_DBGCTRL_64_BCM56970_A0r_fields,
  33888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33889         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33890         -1,
  33891         -1,
  33892         0,
  33893     },
  33894 #endif /* chips */
  33895 
  33896 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33897     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33898     defined(BCM_56160_A0)
  33899     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM53400_A0r */
  33900         soc_block_list[5],
  33901         soc_genreg,
  33902         1,
  33903         0,
  33904         0xa010000,
  33905         0,
  33906         0,
  33907         3,
  33908         soc_L3_TUNNEL_CAM_DBGCTRL_BCM53400_A0r_fields,
  33909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33910         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33911         -1,
  33912         -1,
  33913     },
  33914 #endif /* chips */
  33915 
  33916 #if defined(BCM_56150_A0)
  33917     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56150_A0r */
  33918         soc_block_list[5],
  33919         soc_genreg,
  33920         1,
  33921         0,
  33922         0xa010000,
  33923         0,
  33924         0,
  33925         3,
  33926         soc_L3_TUNNEL_CAM_DBGCTRL_BCM56150_A0r_fields,
  33927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33928         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33929         -1,
  33930         -1,
  33931     },
  33932 #endif /* chips */
  33933 
  33934 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  33935     defined(BCM_56270_A0)
  33936     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56260_A0r */
  33937         soc_block_list[5],
  33938         soc_genreg,
  33939         1,
  33940         0,
  33941         0xa010000,
  33942         0,
  33943         0,
  33944         2,
  33945         soc_L3_TUNNEL_CAM_DBGCTRL_BCM56260_A0r_fields,
  33946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33947         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33948         -1,
  33949         -1,
  33950     },
  33951 #endif /* chips */
  33952 
  33953 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  33954     defined(BCM_56334_B0)
  33955     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56334_A0r */
  33956         soc_block_list[5],
  33957         soc_genreg,
  33958         1,
  33959         0,
  33960         0x208010a,
  33961         0,
  33962         0,
  33963         3,
  33964         soc_L3_TUNNEL_CAM_DBGCTRLr_fields,
  33965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33966         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33967         -1,
  33968         -1,
  33969     },
  33970 #endif /* chips */
  33971 
  33972 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  33973     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  33974     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56560_A0r */
  33975         soc_block_list[5],
  33976         soc_genreg,
  33977         1,
  33978         0,
  33979         0xb000000,
  33980         0,
  33981         0,
  33982         3,
  33983         soc_L3_TUNNEL_CAM_DBGCTRL_BCM56560_A0r_fields,
  33984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33985         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33986         -1,
  33987         -1,
  33988     },
  33989 #endif /* chips */
  33990 
  33991 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  33992     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  33993     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56624_A0r */
  33994         soc_block_list[5],
  33995         soc_genreg,
  33996         1,
  33997         0,
  33998         0x2080102,
  33999         0,
  34000         0,
  34001         3,
  34002         soc_L3_TUNNEL_CAM_DBGCTRLr_fields,
  34003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34004         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34005         -1,
  34006         -1,
  34007     },
  34008 #endif /* chips */
  34009 
  34010 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  34011     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  34012     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  34013     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56634_A0r */
  34014         soc_block_list[5],
  34015         soc_genreg,
  34016         1,
  34017         0,
  34018         0x2080110,
  34019         0,
  34020         0,
  34021         3,
  34022         soc_L3_TUNNEL_CAM_DBGCTRLr_fields,
  34023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34024         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34025         -1,
  34026         -1,
  34027     },
  34028 #endif /* chips */
  34029 
  34030 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  34031     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  34032     defined(BCM_56640_A0)
  34033     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56640_A0r */
  34034         soc_block_list[5],
  34035         soc_genreg,
  34036         1,
  34037         0,
  34038         0xa010000,
  34039         0,
  34040         0,
  34041         3,
  34042         soc_L3_TUNNEL_CAM_DBGCTRL_BCM56640_A0r_fields,
  34043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34044         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34045         -1,
  34046         -1,
  34047     },
  34048 #endif /* chips */
  34049 
  34050 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  34051     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56820_A0r */
  34052         soc_block_list[5],
  34053         soc_genreg,
  34054         1,
  34055         0,
  34056         0x2080c18,
  34057         0,
  34058         0,
  34059         3,
  34060         soc_L3_TUNNEL_CAM_DBGCTRLr_fields,
  34061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34062         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34063         -1,
  34064         -1,
  34065     },
  34066 #endif /* chips */
  34067 
  34068 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  34069     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  34070     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56840_A0r */
  34071         soc_block_list[5],
  34072         soc_genreg,
  34073         1,
  34074         0,
  34075         0x2080d00,
  34076         0,
  34077         0,
  34078         3,
  34079         soc_L3_TUNNEL_CAM_DBGCTRL_BCM56840_A0r_fields,
  34080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34081         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34082         -1,
  34083         -1,
  34084     },
  34085 #endif /* chips */
  34086 
  34087 #if defined(BCM_56850_A0)
  34088     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56850_A0r */
  34089         soc_block_list[5],
  34090         soc_genreg,
  34091         1,
  34092         0,
  34093         0xb000000,
  34094         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34095         0,
  34096         3,
  34097         soc_L3_TUNNEL_CAM_DBGCTRL_BCM56640_A0r_fields,
  34098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34100         -1,
  34101         -1,
  34102     },
  34103 #endif /* chips */
  34104 
  34105 #if defined(BCM_56860_A0)
  34106     { /* SOC_REG_INT_L3_TUNNEL_CAM_DBGCTRL_BCM56860_A0r */
  34107         soc_block_list[5],
  34108         soc_genreg,
  34109         1,
  34110         0,
  34111         0xb000000,
  34112         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34113         0,
  34114         3,
  34115         soc_L3_TUNNEL_CAM_DBGCTRL_BCM56860_A0r_fields,
  34116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34118         -1,
  34119         -1,
  34120     },
  34121 #endif /* chips */
  34122 
  34123 #if defined(BCM_56970_A0)
  34124     { /* SOC_REG_INT_L3_TUNNEL_CAM_SER_CONTROLr */
  34125         soc_block_list[5],
  34126         soc_genreg,
  34127         1,
  34128         0,
  34129         0x53010000,
  34130         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34131         0,
  34132         2,
  34133         soc_L3_TUNNEL_CAM_SER_CONTROLr_fields,
  34134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34136         -1,
  34137         -1,
  34138         0,
  34139     },
  34140 #endif /* chips */
  34141 
  34142 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  34143     defined(BCM_56334_B0)
  34144     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_CONTROLr */
  34145         soc_block_list[5],
  34146         soc_genreg,
  34147         1,
  34148         0,
  34149         0x208011b,
  34150         0,
  34151         0,
  34152         1,
  34153         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  34154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34155         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  34156         -1,
  34157         -1,
  34158     },
  34159 #endif /* chips */
  34160 
  34161 #if defined(BCM_53400_A0)
  34162     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_CONTROL_BCM53400_A0r */
  34163         soc_block_list[5],
  34164         soc_genreg,
  34165         1,
  34166         0,
  34167         0xa010700,
  34168         0,
  34169         0,
  34170         1,
  34171         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  34172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34173         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  34174         -1,
  34175         -1,
  34176     },
  34177 #endif /* chips */
  34178 
  34179 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  34180     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_CONTROL_BCM53570_A0r */
  34181         soc_block_list[5],
  34182         soc_genreg,
  34183         1,
  34184         0,
  34185         0xa010c00,
  34186         0,
  34187         0,
  34188         1,
  34189         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  34190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34191         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  34192         -1,
  34193         -1,
  34194     },
  34195 #endif /* chips */
  34196 
  34197 #if defined(BCM_56150_A0)
  34198     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_CONTROL_BCM56150_A0r */
  34199         soc_block_list[5],
  34200         soc_genreg,
  34201         1,
  34202         0,
  34203         0xa010700,
  34204         0,
  34205         0,
  34206         1,
  34207         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  34208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34209         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  34210         -1,
  34211         -1,
  34212     },
  34213 #endif /* chips */
  34214 
  34215 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  34216     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  34217     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_CONTROL_BCM56160_A0r */
  34218         soc_block_list[5],
  34219         soc_genreg,
  34220         1,
  34221         0,
  34222         0xa010a00,
  34223         0,
  34224         0,
  34225         1,
  34226         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  34227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34228         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  34229         -1,
  34230         -1,
  34231     },
  34232 #endif /* chips */
  34233 
  34234 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  34235     defined(BCM_56334_B0)
  34236     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_STATUSr */
  34237         soc_block_list[5],
  34238         soc_genreg,
  34239         1,
  34240         0,
  34241         0x208011c,
  34242         0,
  34243         0,
  34244         3,
  34245         soc_CPU_TS_PARITY_STATUS_INTRr_fields,
  34246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34247         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  34248         -1,
  34249         -1,
  34250     },
  34251 #endif /* chips */
  34252 
  34253 #if defined(BCM_53400_A0)
  34254     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_STATUS_BCM53400_A0r */
  34255         soc_block_list[5],
  34256         soc_genreg,
  34257         1,
  34258         0,
  34259         0xa010800,
  34260         0,
  34261         0,
  34262         3,
  34263         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  34264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34265         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  34266         -1,
  34267         -1,
  34268     },
  34269 #endif /* chips */
  34270 
  34271 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  34272     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_STATUS_BCM53570_A0r */
  34273         soc_block_list[5],
  34274         soc_genreg,
  34275         1,
  34276         0,
  34277         0xa010d00,
  34278         0,
  34279         0,
  34280         3,
  34281         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  34282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34283         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  34284         -1,
  34285         -1,
  34286     },
  34287 #endif /* chips */
  34288 
  34289 #if defined(BCM_56150_A0)
  34290     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_STATUS_BCM56150_A0r */
  34291         soc_block_list[5],
  34292         soc_genreg,
  34293         1,
  34294         0,
  34295         0xa010800,
  34296         0,
  34297         0,
  34298         3,
  34299         soc_FP_FIELD_SEL_PARITY_STATUS_INTRr_fields,
  34300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34301         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  34302         -1,
  34303         -1,
  34304     },
  34305 #endif /* chips */
  34306 
  34307 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  34308     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  34309     { /* SOC_REG_INT_L3_TUNNEL_DATA_ONLY_PARITY_STATUS_BCM56160_A0r */
  34310         soc_block_list[5],
  34311         soc_genreg,
  34312         1,
  34313         0,
  34314         0xa010b00,
  34315         0,
  34316         0,
  34317         3,
  34318         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  34319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34320         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  34321         -1,
  34322         -1,
  34323     },
  34324 #endif /* chips */
  34325 
  34326 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34327     { /* SOC_REG_INT_L3_TUNNEL_KEY_SELr */
  34328         soc_block_list[5],
  34329         soc_genreg,
  34330         1,
  34331         0,
  34332         0x56002600,
  34333         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34334         0,
  34335         4,
  34336         soc_L3_TUNNEL_KEY_SELr_fields,
  34337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34338         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  34339         -1,
  34340         -1,
  34341         3,
  34342     },
  34343 #endif /* chips */
  34344 
  34345 #if defined(BCM_56370_A0)
  34346     { /* SOC_REG_INT_L3_TUNNEL_KEY_SEL_BCM56370_A0r */
  34347         soc_block_list[5],
  34348         soc_genreg,
  34349         1,
  34350         0,
  34351         0x56002600,
  34352         0,
  34353         0,
  34354         4,
  34355         soc_L3_TUNNEL_KEY_SELr_fields,
  34356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34357         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  34358         -1,
  34359         -1,
  34360         3,
  34361     },
  34362 #endif /* chips */
  34363 
  34364 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  34365     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  34366     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  34367     { /* SOC_REG_INT_L3_TUNNEL_PARITY_CONTROLr */
  34368         soc_block_list[5],
  34369         soc_genreg,
  34370         1,
  34371         0,
  34372         0x2080125,
  34373         0,
  34374         0,
  34375         1,
  34376         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  34377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34378         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  34379         -1,
  34380         -1,
  34381     },
  34382 #endif /* chips */
  34383 
  34384 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  34385     defined(BCM_56270_A0)
  34386     { /* SOC_REG_INT_L3_TUNNEL_PARITY_CONTROL_BCM56260_A0r */
  34387         soc_block_list[5],
  34388         soc_genreg,
  34389         1,
  34390         0,
  34391         0xa011f00,
  34392         0,
  34393         0,
  34394         1,
  34395         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  34396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34397         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34398         -1,
  34399         -1,
  34400     },
  34401 #endif /* chips */
  34402 
  34403 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  34404     defined(BCM_56450_B1)
  34405     { /* SOC_REG_INT_L3_TUNNEL_PARITY_CONTROL_BCM56450_A0r */
  34406         soc_block_list[5],
  34407         soc_genreg,
  34408         1,
  34409         0,
  34410         0xa011500,
  34411         0,
  34412         0,
  34413         1,
  34414         soc_FT_CNTR_SER_CONTROLr_fields,
  34415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34416         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34417         -1,
  34418         -1,
  34419     },
  34420 #endif /* chips */
  34421 
  34422 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  34423     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  34424     { /* SOC_REG_INT_L3_TUNNEL_PARITY_CONTROL_BCM56840_A0r */
  34425         soc_block_list[5],
  34426         soc_genreg,
  34427         1,
  34428         0,
  34429         0x2080d15,
  34430         0,
  34431         0,
  34432         1,
  34433         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  34434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34435         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34436         -1,
  34437         -1,
  34438     },
  34439 #endif /* chips */
  34440 
  34441 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  34442     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  34443     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  34444     { /* SOC_REG_INT_L3_TUNNEL_PARITY_STATUS_INTRr */
  34445         soc_block_list[5],
  34446         soc_genreg,
  34447         1,
  34448         0,
  34449         0x2080126,
  34450         0,
  34451         0,
  34452         3,
  34453         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  34454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34455         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  34456         -1,
  34457         -1,
  34458     },
  34459 #endif /* chips */
  34460 
  34461 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  34462     defined(BCM_56450_B1)
  34463     { /* SOC_REG_INT_L3_TUNNEL_PARITY_STATUS_INTR_BCM56450_A0r */
  34464         soc_block_list[5],
  34465         soc_genreg,
  34466         1,
  34467         0,
  34468         0xa011600,
  34469         0,
  34470         0,
  34471         3,
  34472         soc_EFP_METER_PARITY_STATUS_INTRr_fields,
  34473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34474         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34475         -1,
  34476         -1,
  34477     },
  34478 #endif /* chips */
  34479 
  34480 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  34481     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  34482     { /* SOC_REG_INT_L3_TUNNEL_PARITY_STATUS_INTR_BCM56840_A0r */
  34483         soc_block_list[5],
  34484         soc_genreg,
  34485         1,
  34486         0,
  34487         0x2080d16,
  34488         0,
  34489         0,
  34490         3,
  34491         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  34492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34493         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34494         -1,
  34495         -1,
  34496     },
  34497 #endif /* chips */
  34498 
  34499 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  34500     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  34501     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  34502     { /* SOC_REG_INT_L3_TUNNEL_PARITY_STATUS_NACKr */
  34503         soc_block_list[5],
  34504         soc_genreg,
  34505         1,
  34506         0,
  34507         0x2080127,
  34508         0,
  34509         0,
  34510         3,
  34511         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  34512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34513         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  34514         -1,
  34515         -1,
  34516     },
  34517 #endif /* chips */
  34518 
  34519 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  34520     defined(BCM_56450_B1)
  34521     { /* SOC_REG_INT_L3_TUNNEL_PARITY_STATUS_NACK_BCM56450_A0r */
  34522         soc_block_list[5],
  34523         soc_genreg,
  34524         1,
  34525         0,
  34526         0xa011700,
  34527         0,
  34528         0,
  34529         3,
  34530         soc_EFP_METER_PARITY_STATUS_INTRr_fields,
  34531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34532         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34533         -1,
  34534         -1,
  34535     },
  34536 #endif /* chips */
  34537 
  34538 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  34539     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  34540     { /* SOC_REG_INT_L3_TUNNEL_PARITY_STATUS_NACK_BCM56840_A0r */
  34541         soc_block_list[5],
  34542         soc_genreg,
  34543         1,
  34544         0,
  34545         0x2080d17,
  34546         0,
  34547         0,
  34548         3,
  34549         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  34550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34551         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34552         -1,
  34553         -1,
  34554     },
  34555 #endif /* chips */
  34556 
  34557 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34558     { /* SOC_REG_INT_L4_DST_PORT_MAPr */
  34559         soc_block_list[5],
  34560         soc_genreg,
  34561         16,
  34562         0,
  34563         0x3a014000,
  34564         SOC_REG_FLAG_ARRAY |
  34565                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34566         0,
  34567         3,
  34568         soc_L4_DST_PORT_MAPr_fields,
  34569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34570         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34571         -1,
  34572         -1,
  34573         0,
  34574     },
  34575 #endif /* chips */
  34576 
  34577 #if defined(BCM_56370_A0)
  34578     { /* SOC_REG_INT_L4_DST_PORT_MAP_BCM56370_A0r */
  34579         soc_block_list[5],
  34580         soc_genreg,
  34581         16,
  34582         0,
  34583         0x6a004500,
  34584         SOC_REG_FLAG_ARRAY |
  34585                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34586         0,
  34587         3,
  34588         soc_L4_DST_PORT_MAPr_fields,
  34589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34590         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34591         -1,
  34592         -1,
  34593         0,
  34594     },
  34595 #endif /* chips */
  34596 
  34597 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34598     { /* SOC_REG_INT_L4_DST_PORT_MAP_BCM56870_A0r */
  34599         soc_block_list[5],
  34600         soc_genreg,
  34601         16,
  34602         0,
  34603         0x6a004400,
  34604         SOC_REG_FLAG_ARRAY |
  34605                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34606         0,
  34607         3,
  34608         soc_L4_DST_PORT_MAPr_fields,
  34609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34610         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34611         -1,
  34612         -1,
  34613         0,
  34614     },
  34615 #endif /* chips */
  34616 
  34617 #if defined(BCM_56970_A0)
  34618     { /* SOC_REG_INT_L4_DST_PORT_MAP_BCM56970_A0r */
  34619         soc_block_list[5],
  34620         soc_genreg,
  34621         16,
  34622         0,
  34623         0x5e014000,
  34624         SOC_REG_FLAG_ARRAY |
  34625                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34626         0,
  34627         3,
  34628         soc_L4_DST_PORT_MAPr_fields,
  34629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34630         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34631         -1,
  34632         -1,
  34633         0,
  34634     },
  34635 #endif /* chips */
  34636 
  34637 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34638     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE0r */
  34639         soc_block_list[5],
  34640         soc_genreg,
  34641         16,
  34642         0,
  34643         0x3a014000,
  34644         SOC_REG_FLAG_ARRAY,
  34645         0,
  34646         3,
  34647         soc_L4_DST_PORT_MAPr_fields,
  34648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34649         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34650         -1,
  34651         -1,
  34652         0,
  34653     },
  34654 #endif /* chips */
  34655 
  34656 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34657     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE1r */
  34658         soc_block_list[5],
  34659         soc_genreg,
  34660         16,
  34661         0,
  34662         0x3a014000,
  34663         SOC_REG_FLAG_ARRAY |
  34664                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34665         0,
  34666         3,
  34667         soc_L4_DST_PORT_MAPr_fields,
  34668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34669         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34670         -1,
  34671         -1,
  34672         0,
  34673     },
  34674 #endif /* chips */
  34675 
  34676 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34677     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE2r */
  34678         soc_block_list[5],
  34679         soc_genreg,
  34680         16,
  34681         0,
  34682         0x3a014000,
  34683         SOC_REG_FLAG_ARRAY |
  34684                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34685         0,
  34686         3,
  34687         soc_L4_DST_PORT_MAPr_fields,
  34688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34689         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34690         -1,
  34691         -1,
  34692         0,
  34693     },
  34694 #endif /* chips */
  34695 
  34696 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34697     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE3r */
  34698         soc_block_list[5],
  34699         soc_genreg,
  34700         16,
  34701         0,
  34702         0x3a014000,
  34703         SOC_REG_FLAG_ARRAY |
  34704                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34705         0,
  34706         3,
  34707         soc_L4_DST_PORT_MAPr_fields,
  34708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34709         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34710         -1,
  34711         -1,
  34712         0,
  34713     },
  34714 #endif /* chips */
  34715 
  34716 #if defined(BCM_56370_A0)
  34717     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE0_BCM56370_A0r */
  34718         soc_block_list[5],
  34719         soc_genreg,
  34720         16,
  34721         0,
  34722         0x6a004500,
  34723         SOC_REG_FLAG_ARRAY,
  34724         0,
  34725         3,
  34726         soc_L4_DST_PORT_MAPr_fields,
  34727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34728         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34729         -1,
  34730         -1,
  34731         0,
  34732     },
  34733 #endif /* chips */
  34734 
  34735 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34736     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE0_BCM56870_A0r */
  34737         soc_block_list[5],
  34738         soc_genreg,
  34739         16,
  34740         0,
  34741         0x6a004400,
  34742         SOC_REG_FLAG_ARRAY,
  34743         0,
  34744         3,
  34745         soc_L4_DST_PORT_MAPr_fields,
  34746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34747         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34748         -1,
  34749         -1,
  34750         0,
  34751     },
  34752 #endif /* chips */
  34753 
  34754 #if defined(BCM_56970_A0)
  34755     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE0_BCM56970_A0r */
  34756         soc_block_list[5],
  34757         soc_genreg,
  34758         16,
  34759         0,
  34760         0x5e014000,
  34761         SOC_REG_FLAG_ARRAY,
  34762         0,
  34763         3,
  34764         soc_L4_DST_PORT_MAPr_fields,
  34765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34766         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34767         -1,
  34768         -1,
  34769         0,
  34770     },
  34771 #endif /* chips */
  34772 
  34773 #if defined(BCM_56870_A0)
  34774     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE1_BCM56870_A0r */
  34775         soc_block_list[5],
  34776         soc_genreg,
  34777         16,
  34778         0,
  34779         0x6a004400,
  34780         SOC_REG_FLAG_ARRAY |
  34781                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34782         0,
  34783         3,
  34784         soc_L4_DST_PORT_MAPr_fields,
  34785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34786         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34787         -1,
  34788         -1,
  34789         0,
  34790     },
  34791 #endif /* chips */
  34792 
  34793 #if defined(BCM_56970_A0)
  34794     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE1_BCM56970_A0r */
  34795         soc_block_list[5],
  34796         soc_genreg,
  34797         16,
  34798         0,
  34799         0x5e014000,
  34800         SOC_REG_FLAG_ARRAY |
  34801                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34802         0,
  34803         3,
  34804         soc_L4_DST_PORT_MAPr_fields,
  34805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34806         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34807         -1,
  34808         -1,
  34809         0,
  34810     },
  34811 #endif /* chips */
  34812 
  34813 #if defined(BCM_56970_A0)
  34814     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE2_BCM56970_A0r */
  34815         soc_block_list[5],
  34816         soc_genreg,
  34817         16,
  34818         0,
  34819         0x5e014000,
  34820         SOC_REG_FLAG_ARRAY |
  34821                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34822         0,
  34823         3,
  34824         soc_L4_DST_PORT_MAPr_fields,
  34825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34826         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34827         -1,
  34828         -1,
  34829         0,
  34830     },
  34831 #endif /* chips */
  34832 
  34833 #if defined(BCM_56970_A0)
  34834     { /* SOC_REG_INT_L4_DST_PORT_MAP_PIPE3_BCM56970_A0r */
  34835         soc_block_list[5],
  34836         soc_genreg,
  34837         16,
  34838         0,
  34839         0x5e014000,
  34840         SOC_REG_FLAG_ARRAY |
  34841                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34842         0,
  34843         3,
  34844         soc_L4_DST_PORT_MAPr_fields,
  34845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34846         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34847         -1,
  34848         -1,
  34849         0,
  34850     },
  34851 #endif /* chips */
  34852 
  34853 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34854     { /* SOC_REG_INT_L4_SRC_PORT_MAPr */
  34855         soc_block_list[5],
  34856         soc_genreg,
  34857         16,
  34858         0,
  34859         0x3a012000,
  34860         SOC_REG_FLAG_ARRAY |
  34861                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34862         0,
  34863         3,
  34864         soc_L4_SRC_PORT_MAPr_fields,
  34865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34866         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34867         -1,
  34868         -1,
  34869         0,
  34870     },
  34871 #endif /* chips */
  34872 
  34873 #if defined(BCM_56370_A0)
  34874     { /* SOC_REG_INT_L4_SRC_PORT_MAP_BCM56370_A0r */
  34875         soc_block_list[5],
  34876         soc_genreg,
  34877         16,
  34878         0,
  34879         0x6a003500,
  34880         SOC_REG_FLAG_ARRAY |
  34881                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34882         0,
  34883         3,
  34884         soc_L4_SRC_PORT_MAPr_fields,
  34885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34886         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34887         -1,
  34888         -1,
  34889         0,
  34890     },
  34891 #endif /* chips */
  34892 
  34893 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34894     { /* SOC_REG_INT_L4_SRC_PORT_MAP_BCM56870_A0r */
  34895         soc_block_list[5],
  34896         soc_genreg,
  34897         16,
  34898         0,
  34899         0x6a003400,
  34900         SOC_REG_FLAG_ARRAY |
  34901                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34902         0,
  34903         3,
  34904         soc_L4_SRC_PORT_MAPr_fields,
  34905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34906         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34907         -1,
  34908         -1,
  34909         0,
  34910     },
  34911 #endif /* chips */
  34912 
  34913 #if defined(BCM_56970_A0)
  34914     { /* SOC_REG_INT_L4_SRC_PORT_MAP_BCM56970_A0r */
  34915         soc_block_list[5],
  34916         soc_genreg,
  34917         16,
  34918         0,
  34919         0x5e012000,
  34920         SOC_REG_FLAG_ARRAY |
  34921                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34922         0,
  34923         3,
  34924         soc_L4_SRC_PORT_MAPr_fields,
  34925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34926         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34927         -1,
  34928         -1,
  34929         0,
  34930     },
  34931 #endif /* chips */
  34932 
  34933 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34934     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE0r */
  34935         soc_block_list[5],
  34936         soc_genreg,
  34937         16,
  34938         0,
  34939         0x3a012000,
  34940         SOC_REG_FLAG_ARRAY,
  34941         0,
  34942         3,
  34943         soc_L4_SRC_PORT_MAPr_fields,
  34944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34945         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34946         -1,
  34947         -1,
  34948         0,
  34949     },
  34950 #endif /* chips */
  34951 
  34952 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34953     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE1r */
  34954         soc_block_list[5],
  34955         soc_genreg,
  34956         16,
  34957         0,
  34958         0x3a012000,
  34959         SOC_REG_FLAG_ARRAY |
  34960                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34961         0,
  34962         3,
  34963         soc_L4_SRC_PORT_MAPr_fields,
  34964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34965         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34966         -1,
  34967         -1,
  34968         0,
  34969     },
  34970 #endif /* chips */
  34971 
  34972 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34973     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE2r */
  34974         soc_block_list[5],
  34975         soc_genreg,
  34976         16,
  34977         0,
  34978         0x3a012000,
  34979         SOC_REG_FLAG_ARRAY |
  34980                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  34981         0,
  34982         3,
  34983         soc_L4_SRC_PORT_MAPr_fields,
  34984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34985         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  34986         -1,
  34987         -1,
  34988         0,
  34989     },
  34990 #endif /* chips */
  34991 
  34992 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  34993     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE3r */
  34994         soc_block_list[5],
  34995         soc_genreg,
  34996         16,
  34997         0,
  34998         0x3a012000,
  34999         SOC_REG_FLAG_ARRAY |
  35000                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  35001         0,
  35002         3,
  35003         soc_L4_SRC_PORT_MAPr_fields,
  35004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35005         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  35006         -1,
  35007         -1,
  35008         0,
  35009     },
  35010 #endif /* chips */
  35011 
  35012 #if defined(BCM_56370_A0)
  35013     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE0_BCM56370_A0r */
  35014         soc_block_list[5],
  35015         soc_genreg,
  35016         16,
  35017         0,
  35018         0x6a003500,
  35019         SOC_REG_FLAG_ARRAY,
  35020         0,
  35021         3,
  35022         soc_L4_SRC_PORT_MAPr_fields,
  35023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35024         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  35025         -1,
  35026         -1,
  35027         0,
  35028     },
  35029 #endif /* chips */
  35030 
  35031 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35032     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE0_BCM56870_A0r */
  35033         soc_block_list[5],
  35034         soc_genreg,
  35035         16,
  35036         0,
  35037         0x6a003400,
  35038         SOC_REG_FLAG_ARRAY,
  35039         0,
  35040         3,
  35041         soc_L4_SRC_PORT_MAPr_fields,
  35042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35043         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  35044         -1,
  35045         -1,
  35046         0,
  35047     },
  35048 #endif /* chips */
  35049 
  35050 #if defined(BCM_56970_A0)
  35051     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE0_BCM56970_A0r */
  35052         soc_block_list[5],
  35053         soc_genreg,
  35054         16,
  35055         0,
  35056         0x5e012000,
  35057         SOC_REG_FLAG_ARRAY,
  35058         0,
  35059         3,
  35060         soc_L4_SRC_PORT_MAPr_fields,
  35061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35062         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  35063         -1,
  35064         -1,
  35065         0,
  35066     },
  35067 #endif /* chips */
  35068 
  35069 #if defined(BCM_56870_A0)
  35070     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE1_BCM56870_A0r */
  35071         soc_block_list[5],
  35072         soc_genreg,
  35073         16,
  35074         0,
  35075         0x6a003400,
  35076         SOC_REG_FLAG_ARRAY |
  35077                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  35078         0,
  35079         3,
  35080         soc_L4_SRC_PORT_MAPr_fields,
  35081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35082         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  35083         -1,
  35084         -1,
  35085         0,
  35086     },
  35087 #endif /* chips */
  35088 
  35089 #if defined(BCM_56970_A0)
  35090     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE1_BCM56970_A0r */
  35091         soc_block_list[5],
  35092         soc_genreg,
  35093         16,
  35094         0,
  35095         0x5e012000,
  35096         SOC_REG_FLAG_ARRAY |
  35097                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  35098         0,
  35099         3,
  35100         soc_L4_SRC_PORT_MAPr_fields,
  35101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35102         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  35103         -1,
  35104         -1,
  35105         0,
  35106     },
  35107 #endif /* chips */
  35108 
  35109 #if defined(BCM_56970_A0)
  35110     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE2_BCM56970_A0r */
  35111         soc_block_list[5],
  35112         soc_genreg,
  35113         16,
  35114         0,
  35115         0x5e012000,
  35116         SOC_REG_FLAG_ARRAY |
  35117                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  35118         0,
  35119         3,
  35120         soc_L4_SRC_PORT_MAPr_fields,
  35121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35122         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  35123         -1,
  35124         -1,
  35125         0,
  35126     },
  35127 #endif /* chips */
  35128 
  35129 #if defined(BCM_56970_A0)
  35130     { /* SOC_REG_INT_L4_SRC_PORT_MAP_PIPE3_BCM56970_A0r */
  35131         soc_block_list[5],
  35132         soc_genreg,
  35133         16,
  35134         0,
  35135         0x5e012000,
  35136         SOC_REG_FLAG_ARRAY |
  35137                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  35138         0,
  35139         3,
  35140         soc_L4_SRC_PORT_MAPr_fields,
  35141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35142         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  35143         -1,
  35144         -1,
  35145         0,
  35146     },
  35147 #endif /* chips */
  35148 
  35149 #if defined(BCM_56840_A0)
  35150     { /* SOC_REG_INT_LAG_FAILOVER_CONFIGr */
  35151         soc_block_list[16],
  35152         soc_portreg,
  35153         1,
  35154         0,
  35155         0x224,
  35156         0,
  35157         0,
  35158         4,
  35159         soc_LAG_FAILOVER_CONFIGr_fields,
  35160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35161         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35162         -1,
  35163         -1,
  35164     },
  35165 #endif /* chips */
  35166 
  35167 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  35168     { /* SOC_REG_INT_LAG_FAILOVER_CONFIG_BCM56260_A0r */
  35169         soc_block_list[83],
  35170         soc_portreg,
  35171         1,
  35172         0,
  35173         0x20700,
  35174         0,
  35175         0,
  35176         1,
  35177         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  35178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35179         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35180         -1,
  35181         -1,
  35182     },
  35183 #endif /* chips */
  35184 
  35185 #if defined(BCM_56270_A0)
  35186     { /* SOC_REG_INT_LAG_FAILOVER_CONFIG_BCM56270_A0r */
  35187         soc_block_list[83],
  35188         soc_portreg,
  35189         1,
  35190         0,
  35191         0x20700,
  35192         0,
  35193         0,
  35194         1,
  35195         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  35196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35197         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35198         -1,
  35199         -1,
  35200     },
  35201 #endif /* chips */
  35202 
  35203 #if defined(BCM_56340_A0)
  35204     { /* SOC_REG_INT_LAG_FAILOVER_CONFIG_BCM56340_A0r */
  35205         soc_block_list[214],
  35206         soc_portreg,
  35207         1,
  35208         0,
  35209         0x24600,
  35210         0,
  35211         0,
  35212         4,
  35213         soc_LAG_FAILOVER_CONFIG_BCM56640_A0r_fields,
  35214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35215         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35216         -1,
  35217         -1,
  35218     },
  35219 #endif /* chips */
  35220 
  35221 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  35222     { /* SOC_REG_INT_LAG_FAILOVER_CONFIG_BCM56440_A0r */
  35223         soc_block_list[83],
  35224         soc_portreg,
  35225         1,
  35226         0,
  35227         0x21a,
  35228         0,
  35229         0,
  35230         4,
  35231         soc_LAG_FAILOVER_CONFIGr_fields,
  35232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35233         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35234         -1,
  35235         -1,
  35236     },
  35237 #endif /* chips */
  35238 
  35239 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  35240     defined(BCM_56450_B1)
  35241     { /* SOC_REG_INT_LAG_FAILOVER_CONFIG_BCM56450_A0r */
  35242         soc_block_list[83],
  35243         soc_portreg,
  35244         1,
  35245         0,
  35246         0x21a00,
  35247         0,
  35248         0,
  35249         4,
  35250         soc_LAG_FAILOVER_CONFIG_BCM56450_A0r_fields,
  35251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35252         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35253         -1,
  35254         -1,
  35255     },
  35256 #endif /* chips */
  35257 
  35258 #if defined(BCM_56640_A0)
  35259     { /* SOC_REG_INT_LAG_FAILOVER_CONFIG_BCM56640_A0r */
  35260         soc_block_list[212],
  35261         soc_portreg,
  35262         1,
  35263         0,
  35264         0x24600,
  35265         0,
  35266         0,
  35267         4,
  35268         soc_LAG_FAILOVER_CONFIG_BCM56640_A0r_fields,
  35269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35270         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35271         -1,
  35272         -1,
  35273     },
  35274 #endif /* chips */
  35275 
  35276 #if defined(BCM_56840_B0)
  35277     { /* SOC_REG_INT_LAG_FAILOVER_CONFIG_BCM56840_B0r */
  35278         soc_block_list[16],
  35279         soc_portreg,
  35280         1,
  35281         0,
  35282         0x224,
  35283         0,
  35284         0,
  35285         4,
  35286         soc_LAG_FAILOVER_CONFIGr_fields,
  35287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35288         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35289         -1,
  35290         -1,
  35291     },
  35292 #endif /* chips */
  35293 
  35294 #if defined(BCM_88270_A0)
  35295     { /* SOC_REG_INT_LAG_FAILOVER_CONFIG_BCM88270_A0r */
  35296         soc_block_list[149],
  35297         soc_portreg,
  35298         1,
  35299         0,
  35300         0x20300,
  35301         0,
  35302         0,
  35303         1,
  35304         soc_LAG_FAILOVER_CONFIG_BCM88270_A0r_fields,
  35305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35306         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35307         -1,
  35308         -1,
  35309     },
  35310 #endif /* chips */
  35311 
  35312 #if defined(BCM_88732_A0)
  35313     { /* SOC_REG_INT_LAG_FAILOVER_CONFIG_BCM88732_A0r */
  35314         soc_block_list[16],
  35315         soc_portreg,
  35316         1,
  35317         0,
  35318         0x224,
  35319         0,
  35320         0,
  35321         4,
  35322         soc_LAG_FAILOVER_CONFIGr_fields,
  35323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35324         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35325         -1,
  35326         -1,
  35327     },
  35328 #endif /* chips */
  35329 
  35330 #if defined(BCM_88650_A0)
  35331     { /* SOC_REG_INT_LAG_FAILOVER_RATE_LIMITERr */
  35332         soc_block_list[211],
  35333         soc_portreg,
  35334         1,
  35335         0,
  35336         0x24700,
  35337         0,
  35338         0,
  35339         1,
  35340         soc_LAG_FAILOVER_RATE_LIMITERr_fields,
  35341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35342         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  35343         -1,
  35344         -1,
  35345     },
  35346 #endif /* chips */
  35347 
  35348 #if defined(BCM_56340_A0)
  35349     { /* SOC_REG_INT_LAG_FAILOVER_RATE_LIMITER_BCM56340_A0r */
  35350         soc_block_list[214],
  35351         soc_portreg,
  35352         1,
  35353         0,
  35354         0x24700,
  35355         0,
  35356         0,
  35357         1,
  35358         soc_LAG_FAILOVER_RATE_LIMITER_BCM56640_A0r_fields,
  35359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35360         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  35361         -1,
  35362         -1,
  35363     },
  35364 #endif /* chips */
  35365 
  35366 #if defined(BCM_56640_A0)
  35367     { /* SOC_REG_INT_LAG_FAILOVER_RATE_LIMITER_BCM56640_A0r */
  35368         soc_block_list[212],
  35369         soc_portreg,
  35370         1,
  35371         0,
  35372         0x24700,
  35373         0,
  35374         0,
  35375         1,
  35376         soc_LAG_FAILOVER_RATE_LIMITER_BCM56640_A0r_fields,
  35377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35378         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  35379         -1,
  35380         -1,
  35381     },
  35382 #endif /* chips */
  35383 
  35384 #if defined(BCM_88650_B0)
  35385     { /* SOC_REG_INT_LAG_FAILOVER_RATE_LIMITER_BCM88650_B0r */
  35386         soc_block_list[211],
  35387         soc_portreg,
  35388         1,
  35389         0,
  35390         0x24700,
  35391         0,
  35392         0,
  35393         1,
  35394         soc_LAG_FAILOVER_RATE_LIMITER_BCM88650_B0r_fields,
  35395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35396         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  35397         -1,
  35398         -1,
  35399     },
  35400 #endif /* chips */
  35401 
  35402 #if defined(BCM_88660_A0)
  35403     { /* SOC_REG_INT_LAG_FAILOVER_RATE_LIMITER_BCM88660_A0r */
  35404         soc_block_list[211],
  35405         soc_portreg,
  35406         1,
  35407         0,
  35408         0x24700,
  35409         0,
  35410         0,
  35411         1,
  35412         soc_LAG_FAILOVER_RATE_LIMITER_BCM88660_A0r_fields,
  35413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35414         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  35415         -1,
  35416         -1,
  35417     },
  35418 #endif /* chips */
  35419 
  35420 #if defined(BCM_56840_A0)
  35421     { /* SOC_REG_INT_LAG_FAILOVER_STATUSr */
  35422         soc_block_list[16],
  35423         soc_portreg,
  35424         1,
  35425         0,
  35426         0x225,
  35427         SOC_REG_FLAG_RO,
  35428         0,
  35429         1,
  35430         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  35431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35433         -1,
  35434         -1,
  35435     },
  35436 #endif /* chips */
  35437 
  35438 #if defined(BCM_56340_A0)
  35439     { /* SOC_REG_INT_LAG_FAILOVER_STATUS_BCM56340_A0r */
  35440         soc_block_list[214],
  35441         soc_portreg,
  35442         1,
  35443         0,
  35444         0x24800,
  35445         SOC_REG_FLAG_RO,
  35446         0,
  35447         1,
  35448         soc_LAG_FAILOVER_STATUSr_fields,
  35449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35450         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35451         -1,
  35452         -1,
  35453     },
  35454 #endif /* chips */
  35455 
  35456 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  35457     { /* SOC_REG_INT_LAG_FAILOVER_STATUS_BCM56440_A0r */
  35458         soc_block_list[83],
  35459         soc_portreg,
  35460         1,
  35461         0,
  35462         0x21b,
  35463         SOC_REG_FLAG_RO,
  35464         0,
  35465         1,
  35466         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  35467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35468         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35469         -1,
  35470         -1,
  35471     },
  35472 #endif /* chips */
  35473 
  35474 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  35475     defined(BCM_56450_B1)
  35476     { /* SOC_REG_INT_LAG_FAILOVER_STATUS_BCM56450_A0r */
  35477         soc_block_list[83],
  35478         soc_portreg,
  35479         1,
  35480         0,
  35481         0x21b00,
  35482         SOC_REG_FLAG_RO,
  35483         0,
  35484         1,
  35485         soc_LAG_FAILOVER_STATUSr_fields,
  35486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35488         -1,
  35489         -1,
  35490     },
  35491 #endif /* chips */
  35492 
  35493 #if defined(BCM_56640_A0)
  35494     { /* SOC_REG_INT_LAG_FAILOVER_STATUS_BCM56640_A0r */
  35495         soc_block_list[212],
  35496         soc_portreg,
  35497         1,
  35498         0,
  35499         0x24800,
  35500         SOC_REG_FLAG_RO,
  35501         0,
  35502         1,
  35503         soc_LAG_FAILOVER_STATUSr_fields,
  35504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35505         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35506         -1,
  35507         -1,
  35508     },
  35509 #endif /* chips */
  35510 
  35511 #if defined(BCM_56840_B0)
  35512     { /* SOC_REG_INT_LAG_FAILOVER_STATUS_BCM56840_B0r */
  35513         soc_block_list[16],
  35514         soc_portreg,
  35515         1,
  35516         0,
  35517         0x225,
  35518         SOC_REG_FLAG_RO,
  35519         0,
  35520         1,
  35521         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  35522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35524         -1,
  35525         -1,
  35526     },
  35527 #endif /* chips */
  35528 
  35529 #if defined(BCM_88732_A0)
  35530     { /* SOC_REG_INT_LAG_FAILOVER_STATUS_BCM88732_A0r */
  35531         soc_block_list[16],
  35532         soc_portreg,
  35533         1,
  35534         0,
  35535         0x225,
  35536         SOC_REG_FLAG_RO,
  35537         0,
  35538         1,
  35539         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  35540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35541         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35542         -1,
  35543         -1,
  35544     },
  35545 #endif /* chips */
  35546 
  35547 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35548     { /* SOC_REG_INT_LARGE_SCALE_NAT_CONTROLr */
  35549         soc_block_list[115],
  35550         soc_genreg,
  35551         1,
  35552         0,
  35553         0x2004000,
  35554         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  35555         SOC_REG_FLAG_CCH,
  35556         14,
  35557         soc_LARGE_SCALE_NAT_CONTROLr_fields,
  35558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35559         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  35560         -1,
  35561         -1,
  35562         3,
  35563     },
  35564 #endif /* chips */
  35565 
  35566 #if defined(BCM_56370_A0)
  35567     { /* SOC_REG_INT_LARGE_SCALE_NAT_CONTROL_BCM56370_A0r */
  35568         soc_block_list[115],
  35569         soc_genreg,
  35570         1,
  35571         0,
  35572         0x2003e00,
  35573         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  35574         SOC_REG_FLAG_CCH,
  35575         14,
  35576         soc_LARGE_SCALE_NAT_CONTROLr_fields,
  35577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35578         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  35579         -1,
  35580         -1,
  35581         3,
  35582     },
  35583 #endif /* chips */
  35584 
  35585 #if defined(BCM_88790_A0)
  35586     { /* SOC_REG_INT_LCM_ADMIT_DENY_DFL_FULL_CNTr */
  35587         soc_block_list[114],
  35588         soc_genreg,
  35589         1,
  35590         0,
  35591         0x384,
  35592         SOC_REG_FLAG_RO,
  35593         SOC_REG_FLAG_COUNTER_FEILDS,
  35594         1,
  35595         soc_LCM_ADMIT_DENY_DFL_FULL_CNTr_fields,
  35596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35598         -1,
  35599         -1,
  35600     },
  35601 #endif /* chips */
  35602 
  35603 #if defined(BCM_88790_A0)
  35604     { /* SOC_REG_INT_LCM_ADMIT_DROP_CNTr */
  35605         soc_block_list[114],
  35606         soc_genreg,
  35607         2,
  35608         0,
  35609         0x28b,
  35610         SOC_REG_FLAG_ARRAY |
  35611                           SOC_REG_FLAG_RO |
  35612                           SOC_REG_FLAG_REG_ARRAY,
  35613         SOC_REG_FLAG_COUNTER_FEILDS,
  35614         2,
  35615         soc_LCM_ADMIT_DROP_CNTr_fields,
  35616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35618         -1,
  35619         -1,
  35620     },
  35621 #endif /* chips */
  35622 
  35623 #if defined(BCM_88790_A0)
  35624     { /* SOC_REG_INT_LCM_ADMIT_DROP_CPU_CNTr */
  35625         soc_block_list[114],
  35626         soc_genreg,
  35627         1,
  35628         0,
  35629         0x28d,
  35630         SOC_REG_FLAG_RO,
  35631         SOC_REG_FLAG_COUNTER_FEILDS,
  35632         2,
  35633         soc_LCM_ADMIT_DROP_CPU_CNTr_fields,
  35634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35635         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35636         -1,
  35637         -1,
  35638     },
  35639 #endif /* chips */
  35640 
  35641 #if defined(BCM_88790_A0)
  35642     { /* SOC_REG_INT_LCM_ADMIT_DROP_REASONS_DCHr */
  35643         soc_block_list[114],
  35644         soc_genreg,
  35645         8,
  35646         0,
  35647         0x296,
  35648         SOC_REG_FLAG_ARRAY |
  35649                           SOC_REG_FLAG_RO |
  35650                           SOC_REG_FLAG_REG_ARRAY,
  35651         0,
  35652         1,
  35653         soc_LCM_ADMIT_DROP_REASONS_DCHr_fields,
  35654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35655         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35656         -1,
  35657         -1,
  35658     },
  35659 #endif /* chips */
  35660 
  35661 #if defined(BCM_88790_A0)
  35662     { /* SOC_REG_INT_LCM_AUTO_DOC_NAME_0r */
  35663         soc_block_list[114],
  35664         soc_genreg,
  35665         1,
  35666         0,
  35667         0x104,
  35668         0,
  35669         0,
  35670         1,
  35671         soc_LCM_AUTO_DOC_NAME_0r_fields,
  35672         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  35673         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35674         -1,
  35675         -1,
  35676     },
  35677 #endif /* chips */
  35678 
  35679 #if defined(BCM_88790_A0)
  35680     { /* SOC_REG_INT_LCM_AUTO_DOC_NAME_1r */
  35681         soc_block_list[114],
  35682         soc_genreg,
  35683         24,
  35684         0,
  35685         0x29e,
  35686         SOC_REG_FLAG_ARRAY |
  35687                           SOC_REG_FLAG_RO |
  35688                           SOC_REG_FLAG_REG_ARRAY,
  35689         0,
  35690         1,
  35691         soc_LCM_AUTO_DOC_NAME_1r_fields,
  35692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35693         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  35694         -1,
  35695         -1,
  35696     },
  35697 #endif /* chips */
  35698 
  35699 #if defined(BCM_88790_A0)
  35700     { /* SOC_REG_INT_LCM_AUTO_DOC_NAME_2r */
  35701         soc_block_list[114],
  35702         soc_genreg,
  35703         1,
  35704         0,
  35705         0x2b6,
  35706         SOC_REG_FLAG_RO,
  35707         0,
  35708         10,
  35709         soc_LCM_AUTO_DOC_NAME_2r_fields,
  35710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35711         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  35712         -1,
  35713         -1,
  35714     },
  35715 #endif /* chips */
  35716 
  35717 #if defined(BCM_88790_A0)
  35718     { /* SOC_REG_INT_LCM_AUTO_DOC_NAME_3r */
  35719         soc_block_list[114],
  35720         soc_genreg,
  35721         1,
  35722         0,
  35723         0x2b7,
  35724         SOC_REG_FLAG_RO,
  35725         0,
  35726         3,
  35727         soc_LCM_AUTO_DOC_NAME_3r_fields,
  35728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35729         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  35730         -1,
  35731         -1,
  35732     },
  35733 #endif /* chips */
  35734 
  35735 #if defined(BCM_88790_A0)
  35736     { /* SOC_REG_INT_LCM_AUTO_DOC_NAME_4r */
  35737         soc_block_list[114],
  35738         soc_genreg,
  35739         24,
  35740         0,
  35741         0x2b8,
  35742         SOC_REG_FLAG_ARRAY |
  35743                           SOC_REG_FLAG_RO |
  35744                           SOC_REG_FLAG_REG_ARRAY,
  35745         0,
  35746         3,
  35747         soc_LCM_AUTO_DOC_NAME_4r_fields,
  35748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35749         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  35750         -1,
  35751         -1,
  35752     },
  35753 #endif /* chips */
  35754 
  35755 #if defined(BCM_88790_A0)
  35756     { /* SOC_REG_INT_LCM_AUTO_DOC_NAME_5r */
  35757         soc_block_list[114],
  35758         soc_genreg,
  35759         24,
  35760         0,
  35761         0x2d0,
  35762         SOC_REG_FLAG_ARRAY |
  35763                           SOC_REG_FLAG_RO |
  35764                           SOC_REG_FLAG_REG_ARRAY,
  35765         0,
  35766         1,
  35767         soc_LCM_AUTO_DOC_NAME_5r_fields,
  35768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35769         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  35770         -1,
  35771         -1,
  35772     },
  35773 #endif /* chips */
  35774 
  35775 #if defined(BCM_88790_A0)
  35776     { /* SOC_REG_INT_LCM_AUTO_DOC_NAME_6r */
  35777         soc_block_list[114],
  35778         soc_genreg,
  35779         24,
  35780         0,
  35781         0x2e8,
  35782         SOC_REG_FLAG_ARRAY |
  35783                           SOC_REG_FLAG_RO |
  35784                           SOC_REG_FLAG_REG_ARRAY,
  35785         0,
  35786         1,
  35787         soc_LCM_AUTO_DOC_NAME_6r_fields,
  35788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35789         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  35790         -1,
  35791         -1,
  35792     },
  35793 #endif /* chips */
  35794 
  35795 #if defined(BCM_88790_A0)
  35796     { /* SOC_REG_INT_LCM_AUTO_DOC_NAME_7r */
  35797         soc_block_list[114],
  35798         soc_genreg,
  35799         1,
  35800         0,
  35801         0x300,
  35802         SOC_REG_FLAG_RO,
  35803         0,
  35804         2,
  35805         soc_LCM_AUTO_DOC_NAME_7r_fields,
  35806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35807         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  35808         -1,
  35809         -1,
  35810     },
  35811 #endif /* chips */
  35812 
  35813 #if defined(BCM_88790_A0)
  35814     { /* SOC_REG_INT_LCM_DCML_SEPARATION_REGISTERr */
  35815         soc_block_list[114],
  35816         soc_genreg,
  35817         1,
  35818         0,
  35819         0x307,
  35820         0,
  35821         0,
  35822         6,
  35823         soc_LCM_DCML_SEPARATION_REGISTERr_fields,
  35824         SOC_RESET_VAL_DEC(0x00000188, 0x00000000)
  35825         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  35826         -1,
  35827         -1,
  35828     },
  35829 #endif /* chips */
  35830 
  35831 #if defined(BCM_88790_A0)
  35832     { /* SOC_REG_INT_LCM_DFL_BANKS_MC_DROP_THr */
  35833         soc_block_list[114],
  35834         soc_genreg,
  35835         1,
  35836         0,
  35837         0x208,
  35838         SOC_REG_FLAG_64_BITS,
  35839         0,
  35840         4,
  35841         soc_LCM_DFL_BANKS_MC_DROP_THr_fields,
  35842         SOC_RESET_VAL_DEC(0xc2384708, 0x00000e11)
  35843         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  35844         -1,
  35845         -1,
  35846     },
  35847 #endif /* chips */
  35848 
  35849 #if defined(BCM_88790_A0)
  35850     { /* SOC_REG_INT_LCM_DFL_BANKS_THr */
  35851         soc_block_list[114],
  35852         soc_genreg,
  35853         1,
  35854         0,
  35855         0x207,
  35856         0,
  35857         0,
  35858         1,
  35859         soc_LCM_DFL_BANKS_THr_fields,
  35860         SOC_RESET_VAL_DEC(0x00000708, 0x00000000)
  35861         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  35862         -1,
  35863         -1,
  35864     },
  35865 #endif /* chips */
  35866 
  35867 #if defined(BCM_88790_A0)
  35868     { /* SOC_REG_INT_LCM_DFL_FC_TH_METHOD_1r */
  35869         soc_block_list[114],
  35870         soc_genreg,
  35871         1,
  35872         0,
  35873         0x203,
  35874         SOC_REG_FLAG_64_BITS,
  35875         0,
  35876         3,
  35877         soc_LCM_DFL_FC_TH_METHOD_1r_fields,
  35878         SOC_RESET_VAL_DEC(0x8ca08ca0, 0x00008ca0)
  35879         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  35880         -1,
  35881         -1,
  35882     },
  35883 #endif /* chips */
  35884 
  35885 #if defined(BCM_88790_A0)
  35886     { /* SOC_REG_INT_LCM_DFL_FC_TH_METHOD_2r */
  35887         soc_block_list[114],
  35888         soc_genreg,
  35889         1,
  35890         0,
  35891         0x205,
  35892         SOC_REG_FLAG_64_BITS,
  35893         0,
  35894         3,
  35895         soc_LCM_DFL_FC_TH_METHOD_2r_fields,
  35896         SOC_RESET_VAL_DEC(0xf00d2f00, 0x0d2f00d2)
  35897         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  35898         -1,
  35899         -1,
  35900     },
  35901 #endif /* chips */
  35902 
  35903 #if defined(BCM_88790_A0)
  35904     { /* SOC_REG_INT_LCM_DFL_GCI_COPIES_THRESHOLDSr */
  35905         soc_block_list[114],
  35906         soc_genreg,
  35907         1,
  35908         0,
  35909         0x1f2,
  35910         SOC_REG_FLAG_ABOVE_64_BITS,
  35911         0,
  35912         9,
  35913         soc_LCM_DFL_GCI_COPIES_THRESHOLDSr_fields,
  35914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35916         -1,
  35917         -1,
  35918     },
  35919 #endif /* chips */
  35920 
  35921 #if defined(BCM_88790_A0)
  35922     { /* SOC_REG_INT_LCM_DFL_GCI_TH_METHOD_1r */
  35923         soc_block_list[114],
  35924         soc_genreg,
  35925         1,
  35926         0,
  35927         0x1e7,
  35928         SOC_REG_FLAG_ABOVE_64_BITS,
  35929         0,
  35930         9,
  35931         soc_LCM_DFL_GCI_TH_METHOD_1r_fields,
  35932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35934         -1,
  35935         -1,
  35936     },
  35937 #endif /* chips */
  35938 
  35939 #if defined(BCM_88790_A0)
  35940     { /* SOC_REG_INT_LCM_DFL_GCI_TH_METHOD_2r */
  35941         soc_block_list[114],
  35942         soc_genreg,
  35943         1,
  35944         0,
  35945         0x1ec,
  35946         SOC_REG_FLAG_ABOVE_64_BITS,
  35947         0,
  35948         9,
  35949         soc_LCM_DFL_GCI_TH_METHOD_2r_fields,
  35950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35952         -1,
  35953         -1,
  35954     },
  35955 #endif /* chips */
  35956 
  35957 #if defined(BCM_88790_A0)
  35958     { /* SOC_REG_INT_LCM_DFL_MC_COPIES_ADMIT_THRESHOLDSr */
  35959         soc_block_list[114],
  35960         soc_genreg,
  35961         1,
  35962         0,
  35963         0x1e4,
  35964         SOC_REG_FLAG_ABOVE_64_BITS,
  35965         0,
  35966         4,
  35967         soc_LCM_DFL_MC_COPIES_ADMIT_THRESHOLDSr_fields,
  35968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35970         -1,
  35971         -1,
  35972     },
  35973 #endif /* chips */
  35974 
  35975 #if defined(BCM_88790_A0)
  35976     { /* SOC_REG_INT_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_1r */
  35977         soc_block_list[114],
  35978         soc_genreg,
  35979         1,
  35980         0,
  35981         0x1db,
  35982         SOC_REG_FLAG_ABOVE_64_BITS,
  35983         0,
  35984         8,
  35985         soc_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_1r_fields,
  35986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35987         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35988         -1,
  35989         -1,
  35990     },
  35991 #endif /* chips */
  35992 
  35993 #if defined(BCM_88790_A0)
  35994     { /* SOC_REG_INT_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_2r */
  35995         soc_block_list[114],
  35996         soc_genreg,
  35997         1,
  35998         0,
  35999         0x1df,
  36000         SOC_REG_FLAG_ABOVE_64_BITS,
  36001         0,
  36002         8,
  36003         soc_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_2r_fields,
  36004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36006         -1,
  36007         -1,
  36008     },
  36009 #endif /* chips */
  36010 
  36011 #if defined(BCM_88790_A0)
  36012     { /* SOC_REG_INT_LCM_DFL_PIPE_COPIES_FRAG_CNT_INFO_Pr */
  36013         soc_block_list[114],
  36014         soc_genreg,
  36015         3,
  36016         0,
  36017         0x23e,
  36018         SOC_REG_FLAG_ARRAY |
  36019                           SOC_REG_FLAG_RO |
  36020                           SOC_REG_FLAG_REG_ARRAY,
  36021         0,
  36022         1,
  36023         soc_LCM_DFL_PIPE_COPIES_FRAG_CNT_INFO_Pr_fields,
  36024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36025         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  36026         -1,
  36027         -1,
  36028     },
  36029 #endif /* chips */
  36030 
  36031 #if defined(BCM_88790_A0)
  36032     { /* SOC_REG_INT_LCM_DFL_PIPE_MC_FRAG_CNT_INFO_Pr */
  36033         soc_block_list[114],
  36034         soc_genreg,
  36035         3,
  36036         0,
  36037         0x241,
  36038         SOC_REG_FLAG_ARRAY |
  36039                           SOC_REG_FLAG_RO |
  36040                           SOC_REG_FLAG_REG_ARRAY,
  36041         0,
  36042         1,
  36043         soc_LCM_DFL_PIPE_MC_FRAG_CNT_INFO_Pr_fields,
  36044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36045         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  36046         -1,
  36047         -1,
  36048     },
  36049 #endif /* chips */
  36050 
  36051 #if defined(BCM_88790_A0)
  36052     { /* SOC_REG_INT_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_DIFF_Pr */
  36053         soc_block_list[114],
  36054         soc_genreg,
  36055         3,
  36056         0,
  36057         0x23b,
  36058         SOC_REG_FLAG_ARRAY |
  36059                           SOC_REG_FLAG_RO |
  36060                           SOC_REG_FLAG_REG_ARRAY,
  36061         0,
  36062         1,
  36063         soc_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_DIFF_Pr_fields,
  36064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36065         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  36066         -1,
  36067         -1,
  36068     },
  36069 #endif /* chips */
  36070 
  36071 #if defined(BCM_88790_A0)
  36072     { /* SOC_REG_INT_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_1_Pr */
  36073         soc_block_list[114],
  36074         soc_genreg,
  36075         3,
  36076         0,
  36077         0x232,
  36078         SOC_REG_FLAG_ARRAY |
  36079                           SOC_REG_FLAG_RO |
  36080                           SOC_REG_FLAG_REG_ARRAY,
  36081         0,
  36082         1,
  36083         soc_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_1_Pr_fields,
  36084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36085         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  36086         -1,
  36087         -1,
  36088     },
  36089 #endif /* chips */
  36090 
  36091 #if defined(BCM_88790_A0)
  36092     { /* SOC_REG_INT_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_2_Pr */
  36093         soc_block_list[114],
  36094         soc_genreg,
  36095         3,
  36096         0,
  36097         0x238,
  36098         SOC_REG_FLAG_ARRAY |
  36099                           SOC_REG_FLAG_RO |
  36100                           SOC_REG_FLAG_REG_ARRAY,
  36101         0,
  36102         1,
  36103         soc_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_2_Pr_fields,
  36104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36105         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  36106         -1,
  36107         -1,
  36108     },
  36109 #endif /* chips */
  36110 
  36111 #if defined(BCM_88790_A0)
  36112     { /* SOC_REG_INT_LCM_DFL_PIPE_SHARED_FRAG_CNT_REFr */
  36113         soc_block_list[114],
  36114         soc_genreg,
  36115         1,
  36116         0,
  36117         0x105,
  36118         0,
  36119         0,
  36120         3,
  36121         soc_LCM_DFL_PIPE_SHARED_FRAG_CNT_REFr_fields,
  36122         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  36123         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  36124         -1,
  36125         -1,
  36126     },
  36127 #endif /* chips */
  36128 
  36129 #if defined(BCM_88790_A0)
  36130     { /* SOC_REG_INT_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_1_Pr */
  36131         soc_block_list[114],
  36132         soc_genreg,
  36133         3,
  36134         0,
  36135         0x22f,
  36136         SOC_REG_FLAG_ARRAY |
  36137                           SOC_REG_FLAG_RO |
  36138                           SOC_REG_FLAG_REG_ARRAY,
  36139         0,
  36140         1,
  36141         soc_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_1_Pr_fields,
  36142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36143         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  36144         -1,
  36145         -1,
  36146     },
  36147 #endif /* chips */
  36148 
  36149 #if defined(BCM_88790_A0)
  36150     { /* SOC_REG_INT_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_2_Pr */
  36151         soc_block_list[114],
  36152         soc_genreg,
  36153         3,
  36154         0,
  36155         0x235,
  36156         SOC_REG_FLAG_ARRAY |
  36157                           SOC_REG_FLAG_RO |
  36158                           SOC_REG_FLAG_REG_ARRAY,
  36159         0,
  36160         1,
  36161         soc_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_2_Pr_fields,
  36162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36163         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  36164         -1,
  36165         -1,
  36166     },
  36167 #endif /* chips */
  36168 
  36169 #if defined(BCM_88790_A0)
  36170     { /* SOC_REG_INT_LCM_DFL_RCI_TH_METHOD_1r */
  36171         soc_block_list[114],
  36172         soc_genreg,
  36173         1,
  36174         0,
  36175         0x1f8,
  36176         SOC_REG_FLAG_ABOVE_64_BITS,
  36177         0,
  36178         9,
  36179         soc_LCM_DFL_RCI_TH_METHOD_1r_fields,
  36180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36182         -1,
  36183         -1,
  36184     },
  36185 #endif /* chips */
  36186 
  36187 #if defined(BCM_88790_A0)
  36188     { /* SOC_REG_INT_LCM_DFL_RCI_TH_METHOD_2r */
  36189         soc_block_list[114],
  36190         soc_genreg,
  36191         1,
  36192         0,
  36193         0x1fd,
  36194         SOC_REG_FLAG_ABOVE_64_BITS,
  36195         0,
  36196         9,
  36197         soc_LCM_DFL_RCI_TH_METHOD_2r_fields,
  36198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36200         -1,
  36201         -1,
  36202     },
  36203 #endif /* chips */
  36204 
  36205 #if defined(BCM_88790_A0)
  36206     { /* SOC_REG_INT_LCM_DISABLE_MACr */
  36207         soc_block_list[114],
  36208         soc_genreg,
  36209         1,
  36210         0,
  36211         0x356,
  36212         0,
  36213         0,
  36214         1,
  36215         soc_LCM_DISABLE_MACr_fields,
  36216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36217         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  36218         -1,
  36219         -1,
  36220     },
  36221 #endif /* chips */
  36222 
  36223 #if defined(BCM_88790_A0)
  36224     { /* SOC_REG_INT_LCM_DTL_ADMIT_LR_TH_PROFILEr */
  36225         soc_block_list[114],
  36226         soc_genreg,
  36227         2,
  36228         0,
  36229         0x178,
  36230         SOC_REG_FLAG_ABOVE_64_BITS |
  36231                           SOC_REG_FLAG_ARRAY |
  36232                           SOC_REG_FLAG_REG_ARRAY,
  36233         0,
  36234         16,
  36235         soc_LCM_DTL_ADMIT_LR_TH_PROFILEr_fields,
  36236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36237         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36238         -1,
  36239         -1,
  36240     },
  36241 #endif /* chips */
  36242 
  36243 #if defined(BCM_88790_A0)
  36244     { /* SOC_REG_INT_LCM_DTL_ADMIT_NLR_TH_PROFILEr */
  36245         soc_block_list[114],
  36246         soc_genreg,
  36247         2,
  36248         0,
  36249         0x16a,
  36250         SOC_REG_FLAG_ABOVE_64_BITS |
  36251                           SOC_REG_FLAG_ARRAY |
  36252                           SOC_REG_FLAG_REG_ARRAY,
  36253         0,
  36254         16,
  36255         soc_LCM_DTL_ADMIT_NLR_TH_PROFILEr_fields,
  36256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36257         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36258         -1,
  36259         -1,
  36260     },
  36261 #endif /* chips */
  36262 
  36263 #if defined(BCM_88790_A0)
  36264     { /* SOC_REG_INT_LCM_DTL_CPU_CELL_CNTr */
  36265         soc_block_list[114],
  36266         soc_genreg,
  36267         1,
  36268         0,
  36269         0x37b,
  36270         SOC_REG_FLAG_RO,
  36271         SOC_REG_FLAG_COUNTER_FEILDS,
  36272         1,
  36273         soc_LCM_DTL_CPU_CELL_CNTr_fields,
  36274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36276         -1,
  36277         -1,
  36278     },
  36279 #endif /* chips */
  36280 
  36281 #if defined(BCM_88790_A0)
  36282     { /* SOC_REG_INT_LCM_DTL_CPU_TAGS_THr */
  36283         soc_block_list[114],
  36284         soc_genreg,
  36285         1,
  36286         0,
  36287         0x20e,
  36288         0,
  36289         0,
  36290         1,
  36291         soc_LCM_DTL_CPU_TAGS_THr_fields,
  36292         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  36293         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  36294         -1,
  36295         -1,
  36296     },
  36297 #endif /* chips */
  36298 
  36299 #if defined(BCM_88790_A0)
  36300     { /* SOC_REG_INT_LCM_DTL_CPU_TAG_FIFO_STATUSr */
  36301         soc_block_list[114],
  36302         soc_genreg,
  36303         1,
  36304         0,
  36305         0x28a,
  36306         SOC_REG_FLAG_RO,
  36307         0,
  36308         2,
  36309         soc_LCM_DTL_CPU_TAG_FIFO_STATUSr_fields,
  36310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36311         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  36312         -1,
  36313         -1,
  36314     },
  36315 #endif /* chips */
  36316 
  36317 #if defined(BCM_88790_A0)
  36318     { /* SOC_REG_INT_LCM_DTL_DROPPED_IP_PR_P_0_CNTr */
  36319         soc_block_list[114],
  36320         soc_genreg,
  36321         4,
  36322         0,
  36323         0x35a,
  36324         SOC_REG_FLAG_ARRAY |
  36325                           SOC_REG_FLAG_RO |
  36326                           SOC_REG_FLAG_REG_ARRAY,
  36327         SOC_REG_FLAG_COUNTER_FEILDS,
  36328         1,
  36329         soc_LCM_DTL_DROPPED_IP_PR_P_0_CNTr_fields,
  36330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36331         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36332         -1,
  36333         -1,
  36334     },
  36335 #endif /* chips */
  36336 
  36337 #if defined(BCM_88790_A0)
  36338     { /* SOC_REG_INT_LCM_DTL_DROPPED_IP_PR_P_1_CNTr */
  36339         soc_block_list[114],
  36340         soc_genreg,
  36341         4,
  36342         0,
  36343         0x35e,
  36344         SOC_REG_FLAG_ARRAY |
  36345                           SOC_REG_FLAG_RO |
  36346                           SOC_REG_FLAG_REG_ARRAY,
  36347         SOC_REG_FLAG_COUNTER_FEILDS,
  36348         1,
  36349         soc_LCM_DTL_DROPPED_IP_PR_P_1_CNTr_fields,
  36350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36351         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36352         -1,
  36353         -1,
  36354     },
  36355 #endif /* chips */
  36356 
  36357 #if defined(BCM_88790_A0)
  36358     { /* SOC_REG_INT_LCM_DTL_DROPPED_IP_PR_P_2_CNTr */
  36359         soc_block_list[114],
  36360         soc_genreg,
  36361         4,
  36362         0,
  36363         0x362,
  36364         SOC_REG_FLAG_ARRAY |
  36365                           SOC_REG_FLAG_RO |
  36366                           SOC_REG_FLAG_REG_ARRAY,
  36367         SOC_REG_FLAG_COUNTER_FEILDS,
  36368         1,
  36369         soc_LCM_DTL_DROPPED_IP_PR_P_2_CNTr_fields,
  36370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36372         -1,
  36373         -1,
  36374     },
  36375 #endif /* chips */
  36376 
  36377 #if defined(BCM_88790_A0)
  36378     { /* SOC_REG_INT_LCM_DTL_DROPPED_SRC_P_CNTr */
  36379         soc_block_list[114],
  36380         soc_genreg,
  36381         3,
  36382         0,
  36383         0x366,
  36384         SOC_REG_FLAG_ARRAY |
  36385                           SOC_REG_FLAG_RO |
  36386                           SOC_REG_FLAG_REG_ARRAY,
  36387         SOC_REG_FLAG_COUNTER_FEILDS,
  36388         1,
  36389         soc_LCM_DTL_DROPPED_SRC_P_CNTr_fields,
  36390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36392         -1,
  36393         -1,
  36394     },
  36395 #endif /* chips */
  36396 
  36397 #if defined(BCM_88790_A0)
  36398     { /* SOC_REG_INT_LCM_DTL_FC_TH_LR_PROFILEr */
  36399         soc_block_list[114],
  36400         soc_genreg,
  36401         2,
  36402         0,
  36403         0x1d4,
  36404         SOC_REG_FLAG_ABOVE_64_BITS |
  36405                           SOC_REG_FLAG_ARRAY |
  36406                           SOC_REG_FLAG_REG_ARRAY,
  36407         0,
  36408         6,
  36409         soc_LCM_DTL_FC_TH_LR_PROFILEr_fields,
  36410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36411         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36412         -1,
  36413         -1,
  36414     },
  36415 #endif /* chips */
  36416 
  36417 #if defined(BCM_88790_A0)
  36418     { /* SOC_REG_INT_LCM_DTL_FC_TH_NLR_PROFILEr */
  36419         soc_block_list[114],
  36420         soc_genreg,
  36421         2,
  36422         0,
  36423         0x1ce,
  36424         SOC_REG_FLAG_ABOVE_64_BITS |
  36425                           SOC_REG_FLAG_ARRAY |
  36426                           SOC_REG_FLAG_REG_ARRAY,
  36427         0,
  36428         6,
  36429         soc_LCM_DTL_FC_TH_NLR_PROFILEr_fields,
  36430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36431         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36432         -1,
  36433         -1,
  36434     },
  36435 #endif /* chips */
  36436 
  36437 #if defined(BCM_88790_A0)
  36438     { /* SOC_REG_INT_LCM_DTL_FIFOS_DEPTH_TYPEr */
  36439         soc_block_list[114],
  36440         soc_genreg,
  36441         2,
  36442         0,
  36443         0x216,
  36444         SOC_REG_FLAG_64_BITS |
  36445                           SOC_REG_FLAG_ARRAY |
  36446                           SOC_REG_FLAG_REG_ARRAY,
  36447         0,
  36448         3,
  36449         soc_LCM_DTL_FIFOS_DEPTH_TYPEr_fields,
  36450         SOC_RESET_VAL_DEC(0x54554554, 0x00000005)
  36451         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  36452         -1,
  36453         -1,
  36454     },
  36455 #endif /* chips */
  36456 
  36457 #if defined(BCM_88790_A0)
  36458     { /* SOC_REG_INT_LCM_DTL_FRAG_MAX_LEVEL_LR_Pr */
  36459         soc_block_list[114],
  36460         soc_genreg,
  36461         3,
  36462         0,
  36463         0x286,
  36464         SOC_REG_FLAG_ARRAY |
  36465                           SOC_REG_FLAG_RO |
  36466                           SOC_REG_FLAG_REG_ARRAY,
  36467         0,
  36468         2,
  36469         soc_LCM_DTL_FRAG_MAX_LEVEL_LR_Pr_fields,
  36470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36471         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  36472         -1,
  36473         -1,
  36474     },
  36475 #endif /* chips */
  36476 
  36477 #if defined(BCM_88790_A0)
  36478     { /* SOC_REG_INT_LCM_DTL_FRAG_MAX_LEVEL_NLR_Pr */
  36479         soc_block_list[114],
  36480         soc_genreg,
  36481         3,
  36482         0,
  36483         0x283,
  36484         SOC_REG_FLAG_ARRAY |
  36485                           SOC_REG_FLAG_RO |
  36486                           SOC_REG_FLAG_REG_ARRAY,
  36487         0,
  36488         2,
  36489         soc_LCM_DTL_FRAG_MAX_LEVEL_NLR_Pr_fields,
  36490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36491         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  36492         -1,
  36493         -1,
  36494     },
  36495 #endif /* chips */
  36496 
  36497 #if defined(BCM_88790_A0)
  36498     { /* SOC_REG_INT_LCM_DTL_GCI_TH_P_0_LR_PROFILEr */
  36499         soc_block_list[114],
  36500         soc_genreg,
  36501         2,
  36502         0,
  36503         0x198,
  36504         SOC_REG_FLAG_ABOVE_64_BITS |
  36505                           SOC_REG_FLAG_ARRAY |
  36506                           SOC_REG_FLAG_REG_ARRAY,
  36507         0,
  36508         6,
  36509         soc_LCM_DTL_GCI_TH_P_0_LR_PROFILEr_fields,
  36510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36511         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36512         -1,
  36513         -1,
  36514     },
  36515 #endif /* chips */
  36516 
  36517 #if defined(BCM_88790_A0)
  36518     { /* SOC_REG_INT_LCM_DTL_GCI_TH_P_0_NLR_PROFILEr */
  36519         soc_block_list[114],
  36520         soc_genreg,
  36521         2,
  36522         0,
  36523         0x186,
  36524         SOC_REG_FLAG_ABOVE_64_BITS |
  36525                           SOC_REG_FLAG_ARRAY |
  36526                           SOC_REG_FLAG_REG_ARRAY,
  36527         0,
  36528         6,
  36529         soc_LCM_DTL_GCI_TH_P_0_NLR_PROFILEr_fields,
  36530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36531         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36532         -1,
  36533         -1,
  36534     },
  36535 #endif /* chips */
  36536 
  36537 #if defined(BCM_88790_A0)
  36538     { /* SOC_REG_INT_LCM_DTL_GCI_TH_P_1_LR_PROFILEr */
  36539         soc_block_list[114],
  36540         soc_genreg,
  36541         2,
  36542         0,
  36543         0x19e,
  36544         SOC_REG_FLAG_ABOVE_64_BITS |
  36545                           SOC_REG_FLAG_ARRAY |
  36546                           SOC_REG_FLAG_REG_ARRAY,
  36547         0,
  36548         6,
  36549         soc_LCM_DTL_GCI_TH_P_1_LR_PROFILEr_fields,
  36550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36551         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36552         -1,
  36553         -1,
  36554     },
  36555 #endif /* chips */
  36556 
  36557 #if defined(BCM_88790_A0)
  36558     { /* SOC_REG_INT_LCM_DTL_GCI_TH_P_1_NLR_PROFILEr */
  36559         soc_block_list[114],
  36560         soc_genreg,
  36561         2,
  36562         0,
  36563         0x18c,
  36564         SOC_REG_FLAG_ABOVE_64_BITS |
  36565                           SOC_REG_FLAG_ARRAY |
  36566                           SOC_REG_FLAG_REG_ARRAY,
  36567         0,
  36568         6,
  36569         soc_LCM_DTL_GCI_TH_P_1_NLR_PROFILEr_fields,
  36570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36572         -1,
  36573         -1,
  36574     },
  36575 #endif /* chips */
  36576 
  36577 #if defined(BCM_88790_A0)
  36578     { /* SOC_REG_INT_LCM_DTL_GCI_TH_P_2_LR_PROFILEr */
  36579         soc_block_list[114],
  36580         soc_genreg,
  36581         2,
  36582         0,
  36583         0x1a4,
  36584         SOC_REG_FLAG_ABOVE_64_BITS |
  36585                           SOC_REG_FLAG_ARRAY |
  36586                           SOC_REG_FLAG_REG_ARRAY,
  36587         0,
  36588         6,
  36589         soc_LCM_DTL_GCI_TH_P_2_LR_PROFILEr_fields,
  36590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36592         -1,
  36593         -1,
  36594     },
  36595 #endif /* chips */
  36596 
  36597 #if defined(BCM_88790_A0)
  36598     { /* SOC_REG_INT_LCM_DTL_GCI_TH_P_2_NLR_PROFILEr */
  36599         soc_block_list[114],
  36600         soc_genreg,
  36601         2,
  36602         0,
  36603         0x192,
  36604         SOC_REG_FLAG_ABOVE_64_BITS |
  36605                           SOC_REG_FLAG_ARRAY |
  36606                           SOC_REG_FLAG_REG_ARRAY,
  36607         0,
  36608         6,
  36609         soc_LCM_DTL_GCI_TH_P_2_NLR_PROFILEr_fields,
  36610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36612         -1,
  36613         -1,
  36614     },
  36615 #endif /* chips */
  36616 
  36617 #if defined(BCM_88790_A0)
  36618     { /* SOC_REG_INT_LCM_DTL_LCLRT_CPU_CELL_CNTr */
  36619         soc_block_list[114],
  36620         soc_genreg,
  36621         1,
  36622         0,
  36623         0x37c,
  36624         SOC_REG_FLAG_RO,
  36625         SOC_REG_FLAG_COUNTER_FEILDS,
  36626         1,
  36627         soc_LCM_DTL_LCLRT_CPU_CELL_CNTr_fields,
  36628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36629         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36630         -1,
  36631         -1,
  36632     },
  36633 #endif /* chips */
  36634 
  36635 #if defined(BCM_88790_A0)
  36636     { /* SOC_REG_INT_LCM_DTL_LCLRT_DROPPED_IP_PR_P_0_CNTr */
  36637         soc_block_list[114],
  36638         soc_genreg,
  36639         4,
  36640         0,
  36641         0x36c,
  36642         SOC_REG_FLAG_ARRAY |
  36643                           SOC_REG_FLAG_RO |
  36644                           SOC_REG_FLAG_REG_ARRAY,
  36645         SOC_REG_FLAG_COUNTER_FEILDS,
  36646         1,
  36647         soc_LCM_DTL_LCLRT_DROPPED_IP_PR_P_0_CNTr_fields,
  36648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36649         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36650         -1,
  36651         -1,
  36652     },
  36653 #endif /* chips */
  36654 
  36655 #if defined(BCM_88790_A0)
  36656     { /* SOC_REG_INT_LCM_DTL_LCLRT_DROPPED_IP_PR_P_1_CNTr */
  36657         soc_block_list[114],
  36658         soc_genreg,
  36659         4,
  36660         0,
  36661         0x370,
  36662         SOC_REG_FLAG_ARRAY |
  36663                           SOC_REG_FLAG_RO |
  36664                           SOC_REG_FLAG_REG_ARRAY,
  36665         SOC_REG_FLAG_COUNTER_FEILDS,
  36666         1,
  36667         soc_LCM_DTL_LCLRT_DROPPED_IP_PR_P_1_CNTr_fields,
  36668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36670         -1,
  36671         -1,
  36672     },
  36673 #endif /* chips */
  36674 
  36675 #if defined(BCM_88790_A0)
  36676     { /* SOC_REG_INT_LCM_DTL_LCLRT_DROPPED_IP_PR_P_2_CNTr */
  36677         soc_block_list[114],
  36678         soc_genreg,
  36679         4,
  36680         0,
  36681         0x374,
  36682         SOC_REG_FLAG_ARRAY |
  36683                           SOC_REG_FLAG_RO |
  36684                           SOC_REG_FLAG_REG_ARRAY,
  36685         SOC_REG_FLAG_COUNTER_FEILDS,
  36686         1,
  36687         soc_LCM_DTL_LCLRT_DROPPED_IP_PR_P_2_CNTr_fields,
  36688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36690         -1,
  36691         -1,
  36692     },
  36693 #endif /* chips */
  36694 
  36695 #if defined(BCM_88790_A0)
  36696     { /* SOC_REG_INT_LCM_DTL_LCLRT_DROPPED_SRC_P_CNTr */
  36697         soc_block_list[114],
  36698         soc_genreg,
  36699         3,
  36700         0,
  36701         0x378,
  36702         SOC_REG_FLAG_ARRAY |
  36703                           SOC_REG_FLAG_RO |
  36704                           SOC_REG_FLAG_REG_ARRAY,
  36705         SOC_REG_FLAG_COUNTER_FEILDS,
  36706         1,
  36707         soc_LCM_DTL_LCLRT_DROPPED_SRC_P_CNTr_fields,
  36708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36709         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36710         -1,
  36711         -1,
  36712     },
  36713 #endif /* chips */
  36714 
  36715 #if defined(BCM_88790_A0)
  36716     { /* SOC_REG_INT_LCM_DTL_LCLRT_LINK_TYPEr */
  36717         soc_block_list[114],
  36718         soc_genreg,
  36719         1,
  36720         0,
  36721         0x21a,
  36722         0,
  36723         0,
  36724         1,
  36725         soc_LCM_DTL_LCLRT_LINK_TYPEr_fields,
  36726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36727         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  36728         -1,
  36729         -1,
  36730     },
  36731 #endif /* chips */
  36732 
  36733 #if defined(BCM_88790_A0)
  36734     { /* SOC_REG_INT_LCM_DTL_LCLRT_TOTAL_IN_CELL_P_CNTr */
  36735         soc_block_list[114],
  36736         soc_genreg,
  36737         3,
  36738         0,
  36739         0x369,
  36740         SOC_REG_FLAG_ARRAY |
  36741                           SOC_REG_FLAG_RO |
  36742                           SOC_REG_FLAG_REG_ARRAY,
  36743         SOC_REG_FLAG_COUNTER_FEILDS,
  36744         1,
  36745         soc_LCM_DTL_LCLRT_TOTAL_IN_CELL_P_CNTr_fields,
  36746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36747         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36748         -1,
  36749         -1,
  36750     },
  36751 #endif /* chips */
  36752 
  36753 #if defined(BCM_88790_A0)
  36754     { /* SOC_REG_INT_LCM_DTL_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTERr */
  36755         soc_block_list[114],
  36756         soc_genreg,
  36757         1,
  36758         0,
  36759         0x22e,
  36760         0,
  36761         0,
  36762         2,
  36763         soc_LCM_DTL_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTERr_fields,
  36764         SOC_RESET_VAL_DEC(0x04001000, 0x00000000)
  36765         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  36766         -1,
  36767         -1,
  36768     },
  36769 #endif /* chips */
  36770 
  36771 #if defined(BCM_88790_A0)
  36772     { /* SOC_REG_INT_LCM_DTL_LINK_TYPEr */
  36773         soc_block_list[114],
  36774         soc_genreg,
  36775         1,
  36776         0,
  36777         0x215,
  36778         0,
  36779         0,
  36780         1,
  36781         soc_LCM_DTL_LINK_TYPEr_fields,
  36782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36783         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  36784         -1,
  36785         -1,
  36786     },
  36787 #endif /* chips */
  36788 
  36789 #if defined(BCM_88790_A0)
  36790     { /* SOC_REG_INT_LCM_DTL_PIPES_WEIGHTS_REGISTERr */
  36791         soc_block_list[114],
  36792         soc_genreg,
  36793         1,
  36794         0,
  36795         0x34d,
  36796         0,
  36797         0,
  36798         7,
  36799         soc_LCM_DTL_PIPES_WEIGHTS_REGISTERr_fields,
  36800         SOC_RESET_VAL_DEC(0x18010101, 0x00000000)
  36801         SOC_RESET_MASK_DEC(0x3f7f7f7f, 0x00000000)
  36802         -1,
  36803         -1,
  36804     },
  36805 #endif /* chips */
  36806 
  36807 #if defined(BCM_88790_A0)
  36808     { /* SOC_REG_INT_LCM_DTL_RCI_TH_P_0_LR_PROFILEr */
  36809         soc_block_list[114],
  36810         soc_genreg,
  36811         2,
  36812         0,
  36813         0x1bc,
  36814         SOC_REG_FLAG_ABOVE_64_BITS |
  36815                           SOC_REG_FLAG_ARRAY |
  36816                           SOC_REG_FLAG_REG_ARRAY,
  36817         0,
  36818         6,
  36819         soc_LCM_DTL_RCI_TH_P_0_LR_PROFILEr_fields,
  36820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36821         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36822         -1,
  36823         -1,
  36824     },
  36825 #endif /* chips */
  36826 
  36827 #if defined(BCM_88790_A0)
  36828     { /* SOC_REG_INT_LCM_DTL_RCI_TH_P_0_NLR_PROFILEr */
  36829         soc_block_list[114],
  36830         soc_genreg,
  36831         2,
  36832         0,
  36833         0x1aa,
  36834         SOC_REG_FLAG_ABOVE_64_BITS |
  36835                           SOC_REG_FLAG_ARRAY |
  36836                           SOC_REG_FLAG_REG_ARRAY,
  36837         0,
  36838         6,
  36839         soc_LCM_DTL_RCI_TH_P_0_NLR_PROFILEr_fields,
  36840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36841         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36842         -1,
  36843         -1,
  36844     },
  36845 #endif /* chips */
  36846 
  36847 #if defined(BCM_88790_A0)
  36848     { /* SOC_REG_INT_LCM_DTL_RCI_TH_P_1_LR_PROFILEr */
  36849         soc_block_list[114],
  36850         soc_genreg,
  36851         2,
  36852         0,
  36853         0x1c2,
  36854         SOC_REG_FLAG_ABOVE_64_BITS |
  36855                           SOC_REG_FLAG_ARRAY |
  36856                           SOC_REG_FLAG_REG_ARRAY,
  36857         0,
  36858         6,
  36859         soc_LCM_DTL_RCI_TH_P_1_LR_PROFILEr_fields,
  36860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36861         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36862         -1,
  36863         -1,
  36864     },
  36865 #endif /* chips */
  36866 
  36867 #if defined(BCM_88790_A0)
  36868     { /* SOC_REG_INT_LCM_DTL_RCI_TH_P_1_NLR_PROFILEr */
  36869         soc_block_list[114],
  36870         soc_genreg,
  36871         2,
  36872         0,
  36873         0x1b0,
  36874         SOC_REG_FLAG_ABOVE_64_BITS |
  36875                           SOC_REG_FLAG_ARRAY |
  36876                           SOC_REG_FLAG_REG_ARRAY,
  36877         0,
  36878         6,
  36879         soc_LCM_DTL_RCI_TH_P_1_NLR_PROFILEr_fields,
  36880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36882         -1,
  36883         -1,
  36884     },
  36885 #endif /* chips */
  36886 
  36887 #if defined(BCM_88790_A0)
  36888     { /* SOC_REG_INT_LCM_DTL_RCI_TH_P_2_LR_PROFILEr */
  36889         soc_block_list[114],
  36890         soc_genreg,
  36891         2,
  36892         0,
  36893         0x1c8,
  36894         SOC_REG_FLAG_ABOVE_64_BITS |
  36895                           SOC_REG_FLAG_ARRAY |
  36896                           SOC_REG_FLAG_REG_ARRAY,
  36897         0,
  36898         6,
  36899         soc_LCM_DTL_RCI_TH_P_2_LR_PROFILEr_fields,
  36900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36901         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36902         -1,
  36903         -1,
  36904     },
  36905 #endif /* chips */
  36906 
  36907 #if defined(BCM_88790_A0)
  36908     { /* SOC_REG_INT_LCM_DTL_RCI_TH_P_2_NLR_PROFILEr */
  36909         soc_block_list[114],
  36910         soc_genreg,
  36911         2,
  36912         0,
  36913         0x1b6,
  36914         SOC_REG_FLAG_ABOVE_64_BITS |
  36915                           SOC_REG_FLAG_ARRAY |
  36916                           SOC_REG_FLAG_REG_ARRAY,
  36917         0,
  36918         6,
  36919         soc_LCM_DTL_RCI_TH_P_2_NLR_PROFILEr_fields,
  36920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36922         -1,
  36923         -1,
  36924     },
  36925 #endif /* chips */
  36926 
  36927 #if defined(BCM_88790_A0)
  36928     { /* SOC_REG_INT_LCM_DTL_TH_PROFILES_MAPPINGr */
  36929         soc_block_list[114],
  36930         soc_genreg,
  36931         1,
  36932         0,
  36933         0x1da,
  36934         0,
  36935         0,
  36936         1,
  36937         soc_LCM_DTL_TH_PROFILES_MAPPINGr_fields,
  36938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36939         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  36940         -1,
  36941         -1,
  36942     },
  36943 #endif /* chips */
  36944 
  36945 #if defined(BCM_88790_A0)
  36946     { /* SOC_REG_INT_LCM_DTL_TOTAL_IN_CELL_P_CNTr */
  36947         soc_block_list[114],
  36948         soc_genreg,
  36949         3,
  36950         0,
  36951         0x357,
  36952         SOC_REG_FLAG_ARRAY |
  36953                           SOC_REG_FLAG_RO |
  36954                           SOC_REG_FLAG_REG_ARRAY,
  36955         SOC_REG_FLAG_COUNTER_FEILDS,
  36956         1,
  36957         soc_LCM_DTL_TOTAL_IN_CELL_P_CNTr_fields,
  36958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36959         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36960         -1,
  36961         -1,
  36962     },
  36963 #endif /* chips */
  36964 
  36965 #if defined(BCM_88790_A0)
  36966     { /* SOC_REG_INT_LCM_DTL_WFQ_DYN_WEIGHT_THD_REGISTERr */
  36967         soc_block_list[114],
  36968         soc_genreg,
  36969         1,
  36970         0,
  36971         0x22d,
  36972         0,
  36973         0,
  36974         2,
  36975         soc_LCM_DTL_WFQ_DYN_WEIGHT_THD_REGISTERr_fields,
  36976         SOC_RESET_VAL_DEC(0x04001000, 0x00000000)
  36977         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  36978         -1,
  36979         -1,
  36980     },
  36981 #endif /* chips */
  36982 
  36983 #if defined(BCM_88790_A0)
  36984     { /* SOC_REG_INT_LCM_DTMLOP_PIPES_WEIGHTS_COUNTER_PNr */
  36985         soc_block_list[114],
  36986         soc_genreg,
  36987         3,
  36988         0,
  36989         0x350,
  36990         SOC_REG_FLAG_ARRAY |
  36991                           SOC_REG_FLAG_RO |
  36992                           SOC_REG_FLAG_REG_ARRAY,
  36993         0,
  36994         1,
  36995         soc_LCM_DTMLOP_PIPES_WEIGHTS_COUNTER_PNr_fields,
  36996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36997         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  36998         -1,
  36999         -1,
  37000     },
  37001 #endif /* chips */
  37002 
  37003 #if defined(BCM_88790_A0)
  37004     { /* SOC_REG_INT_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_2r */
  37005         soc_block_list[114],
  37006         soc_genreg,
  37007         1,
  37008         0,
  37009         0x34e,
  37010         0,
  37011         0,
  37012         1,
  37013         soc_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_2r_fields,
  37014         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  37015         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  37016         -1,
  37017         -1,
  37018     },
  37019 #endif /* chips */
  37020 
  37021 #if defined(BCM_88790_A0)
  37022     { /* SOC_REG_INT_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_3r */
  37023         soc_block_list[114],
  37024         soc_genreg,
  37025         1,
  37026         0,
  37027         0x34f,
  37028         0,
  37029         0,
  37030         1,
  37031         soc_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_3r_fields,
  37032         SOC_RESET_VAL_DEC(0x007fffff, 0x00000000)
  37033         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  37034         -1,
  37035         -1,
  37036     },
  37037 #endif /* chips */
  37038 
  37039 #if defined(BCM_88790_A0)
  37040     { /* SOC_REG_INT_LCM_DTML_ENABLERSr */
  37041         soc_block_list[114],
  37042         soc_genreg,
  37043         1,
  37044         0,
  37045         0x306,
  37046         0,
  37047         0,
  37048         8,
  37049         soc_LCM_DTML_ENABLERSr_fields,
  37050         SOC_RESET_VAL_DEC(0x00100004, 0x00000000)
  37051         SOC_RESET_MASK_DEC(0x01f7fff7, 0x00000000)
  37052         -1,
  37053         -1,
  37054     },
  37055 #endif /* chips */
  37056 
  37057 #if defined(BCM_88790_A0)
  37058     { /* SOC_REG_INT_LCM_DTM_ADMIT_CYCLE_TH_PROFILEr */
  37059         soc_block_list[114],
  37060         soc_genreg,
  37061         2,
  37062         0,
  37063         0x138,
  37064         SOC_REG_FLAG_64_BITS |
  37065                           SOC_REG_FLAG_ARRAY |
  37066                           SOC_REG_FLAG_REG_ARRAY,
  37067         0,
  37068         4,
  37069         soc_LCM_DTM_ADMIT_CYCLE_TH_PROFILEr_fields,
  37070         SOC_RESET_VAL_DEC(0x24004800, 0x09001200)
  37071         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  37072         -1,
  37073         -1,
  37074     },
  37075 #endif /* chips */
  37076 
  37077 #if defined(BCM_88790_A0)
  37078     { /* SOC_REG_INT_LCM_DTM_ADMIT_JOB_FIFO_CYCLE_THr */
  37079         soc_block_list[114],
  37080         soc_genreg,
  37081         1,
  37082         0,
  37083         0x164,
  37084         SOC_REG_FLAG_ABOVE_64_BITS,
  37085         0,
  37086         4,
  37087         soc_LCM_DTM_ADMIT_JOB_FIFO_CYCLE_THr_fields,
  37088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37089         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37090         -1,
  37091         -1,
  37092     },
  37093 #endif /* chips */
  37094 
  37095 #if defined(BCM_88790_A0)
  37096     { /* SOC_REG_INT_LCM_DTM_ADMIT_TH_PROFILEr */
  37097         soc_block_list[114],
  37098         soc_genreg,
  37099         2,
  37100         0,
  37101         0x12a,
  37102         SOC_REG_FLAG_ABOVE_64_BITS |
  37103                           SOC_REG_FLAG_ARRAY |
  37104                           SOC_REG_FLAG_REG_ARRAY,
  37105         0,
  37106         16,
  37107         soc_LCM_DTM_ADMIT_TH_PROFILEr_fields,
  37108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37110         -1,
  37111         -1,
  37112     },
  37113 #endif /* chips */
  37114 
  37115 #if defined(BCM_88790_A0)
  37116     { /* SOC_REG_INT_LCM_DTM_CNT_INFO_1r */
  37117         soc_block_list[114],
  37118         soc_genreg,
  37119         1,
  37120         0,
  37121         0x275,
  37122         SOC_REG_FLAG_64_BITS |
  37123                           SOC_REG_FLAG_RO,
  37124         0,
  37125         2,
  37126         soc_LCM_DTM_CNT_INFO_1r_fields,
  37127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37128         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  37129         -1,
  37130         -1,
  37131     },
  37132 #endif /* chips */
  37133 
  37134 #if defined(BCM_88790_A0)
  37135     { /* SOC_REG_INT_LCM_DTM_CNT_INFO_2r */
  37136         soc_block_list[114],
  37137         soc_genreg,
  37138         1,
  37139         0,
  37140         0x277,
  37141         SOC_REG_FLAG_RO,
  37142         0,
  37143         2,
  37144         soc_LCM_DTM_CNT_INFO_2r_fields,
  37145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37146         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  37147         -1,
  37148         -1,
  37149     },
  37150 #endif /* chips */
  37151 
  37152 #if defined(BCM_88790_A0)
  37153     { /* SOC_REG_INT_LCM_DTM_CNT_INFO_3r */
  37154         soc_block_list[114],
  37155         soc_genreg,
  37156         1,
  37157         0,
  37158         0x278,
  37159         SOC_REG_FLAG_64_BITS |
  37160                           SOC_REG_FLAG_RO,
  37161         0,
  37162         2,
  37163         soc_LCM_DTM_CNT_INFO_3r_fields,
  37164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37165         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  37166         -1,
  37167         -1,
  37168     },
  37169 #endif /* chips */
  37170 
  37171 #if defined(BCM_88790_A0)
  37172     { /* SOC_REG_INT_LCM_DTM_CNT_INFO_SELECTr */
  37173         soc_block_list[114],
  37174         soc_genreg,
  37175         1,
  37176         0,
  37177         0x274,
  37178         0,
  37179         0,
  37180         3,
  37181         soc_LCM_DTM_CNT_INFO_SELECTr_fields,
  37182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37183         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  37184         -1,
  37185         -1,
  37186     },
  37187 #endif /* chips */
  37188 
  37189 #if defined(BCM_88790_A0)
  37190     { /* SOC_REG_INT_LCM_DTM_COPIES_RTP_FC_THRESHOLDSr */
  37191         soc_block_list[114],
  37192         soc_genreg,
  37193         1,
  37194         0,
  37195         0x167,
  37196         SOC_REG_FLAG_ABOVE_64_BITS,
  37197         0,
  37198         4,
  37199         soc_LCM_DTM_COPIES_RTP_FC_THRESHOLDSr_fields,
  37200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37201         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37202         -1,
  37203         -1,
  37204     },
  37205 #endif /* chips */
  37206 
  37207 #if defined(BCM_88790_A0)
  37208     { /* SOC_REG_INT_LCM_DTM_CPU_TAGS_STATUSr */
  37209         soc_block_list[114],
  37210         soc_genreg,
  37211         1,
  37212         0,
  37213         0x289,
  37214         SOC_REG_FLAG_RO,
  37215         0,
  37216         1,
  37217         soc_LCM_DTM_CPU_TAGS_STATUSr_fields,
  37218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37219         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  37220         -1,
  37221         -1,
  37222     },
  37223 #endif /* chips */
  37224 
  37225 #if defined(BCM_88790_A0)
  37226     { /* SOC_REG_INT_LCM_DTM_CPU_TAGS_THr */
  37227         soc_block_list[114],
  37228         soc_genreg,
  37229         1,
  37230         0,
  37231         0x20d,
  37232         0,
  37233         0,
  37234         1,
  37235         soc_LCM_DTM_CPU_TAGS_THr_fields,
  37236         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  37237         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  37238         -1,
  37239         -1,
  37240     },
  37241 #endif /* chips */
  37242 
  37243 #if defined(BCM_88790_A0)
  37244     { /* SOC_REG_INT_LCM_DTM_DTL_FLOW_CONTROL_CNT_Pr */
  37245         soc_block_list[114],
  37246         soc_genreg,
  37247         3,
  37248         0,
  37249         0x33f,
  37250         SOC_REG_FLAG_ARRAY |
  37251                           SOC_REG_FLAG_RO |
  37252                           SOC_REG_FLAG_REG_ARRAY,
  37253         SOC_REG_FLAG_COUNTER_FEILDS,
  37254         1,
  37255         soc_LCM_DTM_DTL_FLOW_CONTROL_CNT_Pr_fields,
  37256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37258         -1,
  37259         -1,
  37260     },
  37261 #endif /* chips */
  37262 
  37263 #if defined(BCM_88790_A0)
  37264     { /* SOC_REG_INT_LCM_DTM_DYN_PIPES_WEIGHTS_REGISTERr */
  37265         soc_block_list[114],
  37266         soc_genreg,
  37267         1,
  37268         0,
  37269         0x314,
  37270         0,
  37271         0,
  37272         4,
  37273         soc_LCM_DTM_DYN_PIPES_WEIGHTS_REGISTERr_fields,
  37274         SOC_RESET_VAL_DEC(0x01010101, 0x00000000)
  37275         SOC_RESET_MASK_DEC(0x7f7f7f7f, 0x00000000)
  37276         -1,
  37277         -1,
  37278     },
  37279 #endif /* chips */
  37280 
  37281 #if defined(BCM_88790_A0)
  37282     { /* SOC_REG_INT_LCM_DTM_FC_TH_PROFILEr */
  37283         soc_block_list[114],
  37284         soc_genreg,
  37285         2,
  37286         0,
  37287         0x15c,
  37288         SOC_REG_FLAG_ABOVE_64_BITS |
  37289                           SOC_REG_FLAG_ARRAY |
  37290                           SOC_REG_FLAG_REG_ARRAY,
  37291         0,
  37292         9,
  37293         soc_LCM_DTM_FC_TH_PROFILEr_fields,
  37294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37296         -1,
  37297         -1,
  37298     },
  37299 #endif /* chips */
  37300 
  37301 #if defined(BCM_88790_A0)
  37302     { /* SOC_REG_INT_LCM_DTM_FIFOS_DEPTH_TYPEr */
  37303         soc_block_list[114],
  37304         soc_genreg,
  37305         2,
  37306         0,
  37307         0x213,
  37308         SOC_REG_FLAG_ARRAY |
  37309                           SOC_REG_FLAG_REG_ARRAY,
  37310         0,
  37311         2,
  37312         soc_LCM_DTM_FIFOS_DEPTH_TYPEr_fields,
  37313         SOC_RESET_VAL_DEC(0x06000600, 0x00000000)
  37314         SOC_RESET_MASK_DEC(0x1fff1fff, 0x00000000)
  37315         -1,
  37316         -1,
  37317     },
  37318 #endif /* chips */
  37319 
  37320 #if defined(BCM_88790_A0)
  37321     { /* SOC_REG_INT_LCM_DTM_FIFO_TYPE_BMPr */
  37322         soc_block_list[114],
  37323         soc_genreg,
  37324         1,
  37325         0,
  37326         0x212,
  37327         0,
  37328         0,
  37329         1,
  37330         soc_LCM_DTM_FIFO_TYPE_BMPr_fields,
  37331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37332         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  37333         -1,
  37334         -1,
  37335     },
  37336 #endif /* chips */
  37337 
  37338 #if defined(BCM_88790_A0)
  37339     { /* SOC_REG_INT_LCM_DTM_FRAG_CNT_INFO_P_0_DCHr */
  37340         soc_block_list[114],
  37341         soc_genreg,
  37342         8,
  37343         0,
  37344         0x24c,
  37345         SOC_REG_FLAG_ARRAY |
  37346                           SOC_REG_FLAG_RO |
  37347                           SOC_REG_FLAG_REG_ARRAY,
  37348         0,
  37349         2,
  37350         soc_LCM_DTM_FRAG_CNT_INFO_P_0_DCHr_fields,
  37351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37352         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37353         -1,
  37354         -1,
  37355     },
  37356 #endif /* chips */
  37357 
  37358 #if defined(BCM_88790_A0)
  37359     { /* SOC_REG_INT_LCM_DTM_FRAG_CNT_INFO_P_1_DCHr */
  37360         soc_block_list[114],
  37361         soc_genreg,
  37362         8,
  37363         0,
  37364         0x25c,
  37365         SOC_REG_FLAG_ARRAY |
  37366                           SOC_REG_FLAG_RO |
  37367                           SOC_REG_FLAG_REG_ARRAY,
  37368         0,
  37369         2,
  37370         soc_LCM_DTM_FRAG_CNT_INFO_P_1_DCHr_fields,
  37371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37372         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37373         -1,
  37374         -1,
  37375     },
  37376 #endif /* chips */
  37377 
  37378 #if defined(BCM_88790_A0)
  37379     { /* SOC_REG_INT_LCM_DTM_FRAG_CNT_INFO_P_2_DCHr */
  37380         soc_block_list[114],
  37381         soc_genreg,
  37382         8,
  37383         0,
  37384         0x26c,
  37385         SOC_REG_FLAG_ARRAY |
  37386                           SOC_REG_FLAG_RO |
  37387                           SOC_REG_FLAG_REG_ARRAY,
  37388         0,
  37389         2,
  37390         soc_LCM_DTM_FRAG_CNT_INFO_P_2_DCHr_fields,
  37391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37392         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37393         -1,
  37394         -1,
  37395     },
  37396 #endif /* chips */
  37397 
  37398 #if defined(BCM_88790_A0)
  37399     { /* SOC_REG_INT_LCM_DTM_GCI_TH_PROFILEr */
  37400         soc_block_list[114],
  37401         soc_genreg,
  37402         2,
  37403         0,
  37404         0x13c,
  37405         SOC_REG_FLAG_ABOVE_64_BITS |
  37406                           SOC_REG_FLAG_ARRAY |
  37407                           SOC_REG_FLAG_REG_ARRAY,
  37408         0,
  37409         18,
  37410         soc_LCM_DTM_GCI_TH_PROFILEr_fields,
  37411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37412         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37413         -1,
  37414         -1,
  37415     },
  37416 #endif /* chips */
  37417 
  37418 #if defined(BCM_88790_A0)
  37419     { /* SOC_REG_INT_LCM_DTM_LATENCY_CFGr */
  37420         soc_block_list[114],
  37421         soc_genreg,
  37422         3,
  37423         0,
  37424         0x308,
  37425         SOC_REG_FLAG_ARRAY |
  37426                           SOC_REG_FLAG_REG_ARRAY,
  37427         0,
  37428         1,
  37429         soc_LCM_DTM_LATENCY_CFGr_fields,
  37430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37431         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  37432         -1,
  37433         -1,
  37434     },
  37435 #endif /* chips */
  37436 
  37437 #if defined(BCM_88790_A0)
  37438     { /* SOC_REG_INT_LCM_DTM_LCLRT_DTL_FLOW_CONTROL_CNT_Pr */
  37439         soc_block_list[114],
  37440         soc_genreg,
  37441         3,
  37442         0,
  37443         0x342,
  37444         SOC_REG_FLAG_ARRAY |
  37445                           SOC_REG_FLAG_RO |
  37446                           SOC_REG_FLAG_REG_ARRAY,
  37447         SOC_REG_FLAG_COUNTER_FEILDS,
  37448         1,
  37449         soc_LCM_DTM_LCLRT_DTL_FLOW_CONTROL_CNT_Pr_fields,
  37450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37451         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37452         -1,
  37453         -1,
  37454     },
  37455 #endif /* chips */
  37456 
  37457 #if defined(BCM_88790_A0)
  37458     { /* SOC_REG_INT_LCM_DTM_LCLRT_PIPES_WEIGHTS_COUNTER_PNr */
  37459         soc_block_list[114],
  37460         soc_genreg,
  37461         3,
  37462         0,
  37463         0x311,
  37464         SOC_REG_FLAG_ARRAY |
  37465                           SOC_REG_FLAG_RO |
  37466                           SOC_REG_FLAG_REG_ARRAY,
  37467         0,
  37468         1,
  37469         soc_LCM_DTM_LCLRT_PIPES_WEIGHTS_COUNTER_PNr_fields,
  37470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37471         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  37472         -1,
  37473         -1,
  37474     },
  37475 #endif /* chips */
  37476 
  37477 #if defined(BCM_88790_A0)
  37478     { /* SOC_REG_INT_LCM_DTM_LCLRT_TOTAL_OUT_CELL_CNT_Pr */
  37479         soc_block_list[114],
  37480         soc_genreg,
  37481         3,
  37482         0,
  37483         0x330,
  37484         SOC_REG_FLAG_ARRAY |
  37485                           SOC_REG_FLAG_RO |
  37486                           SOC_REG_FLAG_REG_ARRAY,
  37487         SOC_REG_FLAG_COUNTER_FEILDS,
  37488         1,
  37489         soc_LCM_DTM_LCLRT_TOTAL_OUT_CELL_CNT_Pr_fields,
  37490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37491         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37492         -1,
  37493         -1,
  37494     },
  37495 #endif /* chips */
  37496 
  37497 #if defined(BCM_88790_A0)
  37498     { /* SOC_REG_INT_LCM_DTM_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTERr */
  37499         soc_block_list[114],
  37500         soc_genreg,
  37501         1,
  37502         0,
  37503         0x22c,
  37504         0,
  37505         0,
  37506         2,
  37507         soc_LCM_DTM_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTERr_fields,
  37508         SOC_RESET_VAL_DEC(0x04801200, 0x00000000)
  37509         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37510         -1,
  37511         -1,
  37512     },
  37513 #endif /* chips */
  37514 
  37515 #if defined(BCM_88790_A0)
  37516     { /* SOC_REG_INT_LCM_DTM_MASK_FC_AGING_PERIODr */
  37517         soc_block_list[114],
  37518         soc_genreg,
  37519         1,
  37520         0,
  37521         0x345,
  37522         0,
  37523         0,
  37524         1,
  37525         soc_LCM_DTM_MASK_FC_AGING_PERIODr_fields,
  37526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37528         -1,
  37529         -1,
  37530     },
  37531 #endif /* chips */
  37532 
  37533 #if defined(BCM_88790_A0)
  37534     { /* SOC_REG_INT_LCM_DTM_PIPES_WEIGHTS_COUNTER_PNr */
  37535         soc_block_list[114],
  37536         soc_genreg,
  37537         3,
  37538         0,
  37539         0x30e,
  37540         SOC_REG_FLAG_ARRAY |
  37541                           SOC_REG_FLAG_RO |
  37542                           SOC_REG_FLAG_REG_ARRAY,
  37543         0,
  37544         1,
  37545         soc_LCM_DTM_PIPES_WEIGHTS_COUNTER_PNr_fields,
  37546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37547         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  37548         -1,
  37549         -1,
  37550     },
  37551 #endif /* chips */
  37552 
  37553 #if defined(BCM_88790_A0)
  37554     { /* SOC_REG_INT_LCM_DTM_PIPES_WEIGHTS_REGISTERr */
  37555         soc_block_list[114],
  37556         soc_genreg,
  37557         1,
  37558         0,
  37559         0x30b,
  37560         0,
  37561         0,
  37562         8,
  37563         soc_LCM_DTM_PIPES_WEIGHTS_REGISTERr_fields,
  37564         SOC_RESET_VAL_DEC(0x18010101, 0x00000000)
  37565         SOC_RESET_MASK_DEC(0x7f7f7f7f, 0x00000000)
  37566         -1,
  37567         -1,
  37568     },
  37569 #endif /* chips */
  37570 
  37571 #if defined(BCM_88790_A0)
  37572     { /* SOC_REG_INT_LCM_DTM_PIPES_WEIGHTS_REGISTER_2r */
  37573         soc_block_list[114],
  37574         soc_genreg,
  37575         1,
  37576         0,
  37577         0x30c,
  37578         0,
  37579         0,
  37580         1,
  37581         soc_LCM_DTM_PIPES_WEIGHTS_REGISTER_2r_fields,
  37582         SOC_RESET_VAL_DEC(0x003fffff, 0x00000000)
  37583         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  37584         -1,
  37585         -1,
  37586     },
  37587 #endif /* chips */
  37588 
  37589 #if defined(BCM_88790_A0)
  37590     { /* SOC_REG_INT_LCM_DTM_PIPES_WEIGHTS_REGISTER_3r */
  37591         soc_block_list[114],
  37592         soc_genreg,
  37593         1,
  37594         0,
  37595         0x30d,
  37596         0,
  37597         0,
  37598         1,
  37599         soc_LCM_DTM_PIPES_WEIGHTS_REGISTER_3r_fields,
  37600         SOC_RESET_VAL_DEC(0x0007ffff, 0x00000000)
  37601         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  37602         -1,
  37603         -1,
  37604     },
  37605 #endif /* chips */
  37606 
  37607 #if defined(BCM_88790_A0)
  37608     { /* SOC_REG_INT_LCM_DTM_RCI_TH_PROFILEr */
  37609         soc_block_list[114],
  37610         soc_genreg,
  37611         2,
  37612         0,
  37613         0x14c,
  37614         SOC_REG_FLAG_ABOVE_64_BITS |
  37615                           SOC_REG_FLAG_ARRAY |
  37616                           SOC_REG_FLAG_REG_ARRAY,
  37617         0,
  37618         18,
  37619         soc_LCM_DTM_RCI_TH_PROFILEr_fields,
  37620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37622         -1,
  37623         -1,
  37624     },
  37625 #endif /* chips */
  37626 
  37627 #if defined(BCM_88790_A0)
  37628     { /* SOC_REG_INT_LCM_DTM_TAG_CNT_INFO_P_0_DCHr */
  37629         soc_block_list[114],
  37630         soc_genreg,
  37631         8,
  37632         0,
  37633         0x244,
  37634         SOC_REG_FLAG_ARRAY |
  37635                           SOC_REG_FLAG_RO |
  37636                           SOC_REG_FLAG_REG_ARRAY,
  37637         0,
  37638         2,
  37639         soc_LCM_DTM_TAG_CNT_INFO_P_0_DCHr_fields,
  37640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37641         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  37642         -1,
  37643         -1,
  37644     },
  37645 #endif /* chips */
  37646 
  37647 #if defined(BCM_88790_A0)
  37648     { /* SOC_REG_INT_LCM_DTM_TAG_CNT_INFO_P_1_DCHr */
  37649         soc_block_list[114],
  37650         soc_genreg,
  37651         8,
  37652         0,
  37653         0x254,
  37654         SOC_REG_FLAG_ARRAY |
  37655                           SOC_REG_FLAG_RO |
  37656                           SOC_REG_FLAG_REG_ARRAY,
  37657         0,
  37658         2,
  37659         soc_LCM_DTM_TAG_CNT_INFO_P_1_DCHr_fields,
  37660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37661         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  37662         -1,
  37663         -1,
  37664     },
  37665 #endif /* chips */
  37666 
  37667 #if defined(BCM_88790_A0)
  37668     { /* SOC_REG_INT_LCM_DTM_TAG_CNT_INFO_P_2_DCHr */
  37669         soc_block_list[114],
  37670         soc_genreg,
  37671         8,
  37672         0,
  37673         0x264,
  37674         SOC_REG_FLAG_ARRAY |
  37675                           SOC_REG_FLAG_RO |
  37676                           SOC_REG_FLAG_REG_ARRAY,
  37677         0,
  37678         2,
  37679         soc_LCM_DTM_TAG_CNT_INFO_P_2_DCHr_fields,
  37680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37681         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  37682         -1,
  37683         -1,
  37684     },
  37685 #endif /* chips */
  37686 
  37687 #if defined(BCM_88790_A0)
  37688     { /* SOC_REG_INT_LCM_DTM_TOTAL_CELL_CNT_DCH_P_0r */
  37689         soc_block_list[114],
  37690         soc_genreg,
  37691         8,
  37692         0,
  37693         0x315,
  37694         SOC_REG_FLAG_ARRAY |
  37695                           SOC_REG_FLAG_RO |
  37696                           SOC_REG_FLAG_REG_ARRAY,
  37697         SOC_REG_FLAG_COUNTER_FEILDS,
  37698         1,
  37699         soc_LCM_DTM_TOTAL_CELL_CNT_DCH_P_0r_fields,
  37700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37702         -1,
  37703         -1,
  37704     },
  37705 #endif /* chips */
  37706 
  37707 #if defined(BCM_88790_A0)
  37708     { /* SOC_REG_INT_LCM_DTM_TOTAL_CELL_CNT_DCH_P_1r */
  37709         soc_block_list[114],
  37710         soc_genreg,
  37711         8,
  37712         0,
  37713         0x31d,
  37714         SOC_REG_FLAG_ARRAY |
  37715                           SOC_REG_FLAG_RO |
  37716                           SOC_REG_FLAG_REG_ARRAY,
  37717         SOC_REG_FLAG_COUNTER_FEILDS,
  37718         1,
  37719         soc_LCM_DTM_TOTAL_CELL_CNT_DCH_P_1r_fields,
  37720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37721         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37722         -1,
  37723         -1,
  37724     },
  37725 #endif /* chips */
  37726 
  37727 #if defined(BCM_88790_A0)
  37728     { /* SOC_REG_INT_LCM_DTM_TOTAL_CELL_CNT_DCH_P_2r */
  37729         soc_block_list[114],
  37730         soc_genreg,
  37731         8,
  37732         0,
  37733         0x325,
  37734         SOC_REG_FLAG_ARRAY |
  37735                           SOC_REG_FLAG_RO |
  37736                           SOC_REG_FLAG_REG_ARRAY,
  37737         SOC_REG_FLAG_COUNTER_FEILDS,
  37738         1,
  37739         soc_LCM_DTM_TOTAL_CELL_CNT_DCH_P_2r_fields,
  37740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37742         -1,
  37743         -1,
  37744     },
  37745 #endif /* chips */
  37746 
  37747 #if defined(BCM_88790_A0)
  37748     { /* SOC_REG_INT_LCM_DTM_TOTAL_OUT_CELL_CNT_Pr */
  37749         soc_block_list[114],
  37750         soc_genreg,
  37751         3,
  37752         0,
  37753         0x32d,
  37754         SOC_REG_FLAG_ARRAY |
  37755                           SOC_REG_FLAG_RO |
  37756                           SOC_REG_FLAG_REG_ARRAY,
  37757         SOC_REG_FLAG_COUNTER_FEILDS,
  37758         1,
  37759         soc_LCM_DTM_TOTAL_OUT_CELL_CNT_Pr_fields,
  37760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37762         -1,
  37763         -1,
  37764     },
  37765 #endif /* chips */
  37766 
  37767 #if defined(BCM_88790_A0)
  37768     { /* SOC_REG_INT_LCM_DTM_WFQ_DYN_WEIGHT_THD_REGISTERr */
  37769         soc_block_list[114],
  37770         soc_genreg,
  37771         1,
  37772         0,
  37773         0x22b,
  37774         0,
  37775         0,
  37776         2,
  37777         soc_LCM_DTM_WFQ_DYN_WEIGHT_THD_REGISTERr_fields,
  37778         SOC_RESET_VAL_DEC(0x04801200, 0x00000000)
  37779         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37780         -1,
  37781         -1,
  37782     },
  37783 #endif /* chips */
  37784 
  37785 #if defined(BCM_88790_A0)
  37786     { /* SOC_REG_INT_LCM_DYN_PIPES_WEIGHTS_REGISTERr */
  37787         soc_block_list[114],
  37788         soc_genreg,
  37789         1,
  37790         0,
  37791         0x353,
  37792         0,
  37793         0,
  37794         4,
  37795         soc_LCM_DYN_PIPES_WEIGHTS_REGISTERr_fields,
  37796         SOC_RESET_VAL_DEC(0x01010101, 0x00000000)
  37797         SOC_RESET_MASK_DEC(0x7f7f7f7f, 0x00000000)
  37798         -1,
  37799         -1,
  37800     },
  37801 #endif /* chips */
  37802 
  37803 #if defined(BCM_88790_A0)
  37804     { /* SOC_REG_INT_LCM_ECC_1B_ERR_CNTr */
  37805         soc_block_list[114],
  37806         soc_genreg,
  37807         1,
  37808         0,
  37809         0x94,
  37810         SOC_REG_FLAG_64_BITS |
  37811                           SOC_REG_FLAG_RO,
  37812         SOC_REG_FLAG_COUNTER_FEILDS,
  37813         4,
  37814         soc_LCM_ECC_1B_ERR_CNTr_fields,
  37815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37816         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  37817         -1,
  37818         -1,
  37819     },
  37820 #endif /* chips */
  37821 
  37822 #if defined(BCM_88790_A0)
  37823     { /* SOC_REG_INT_LCM_ECC_2B_ERR_CNTr */
  37824         soc_block_list[114],
  37825         soc_genreg,
  37826         1,
  37827         0,
  37828         0x96,
  37829         SOC_REG_FLAG_64_BITS |
  37830                           SOC_REG_FLAG_RO,
  37831         SOC_REG_FLAG_COUNTER_FEILDS,
  37832         4,
  37833         soc_LCM_ECC_2B_ERR_CNTr_fields,
  37834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37835         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  37836         -1,
  37837         -1,
  37838     },
  37839 #endif /* chips */
  37840 
  37841 #if defined(BCM_88790_A0)
  37842     { /* SOC_REG_INT_LCM_ECC_ERR_1B_INITIATEr */
  37843         soc_block_list[114],
  37844         soc_genreg,
  37845         1,
  37846         0,
  37847         0xa4,
  37848         0,
  37849         0,
  37850         5,
  37851         soc_LCM_ECC_ERR_1B_INITIATEr_fields,
  37852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37853         SOC_RESET_MASK_DEC(0x00382080, 0x00000000)
  37854         -1,
  37855         -1,
  37856     },
  37857 #endif /* chips */
  37858 
  37859 #if defined(BCM_88790_A0)
  37860     { /* SOC_REG_INT_LCM_ECC_ERR_1B_MONITOR_MEM_MASKr */
  37861         soc_block_list[114],
  37862         soc_genreg,
  37863         1,
  37864         0,
  37865         0x9a,
  37866         0,
  37867         0,
  37868         5,
  37869         soc_LCM_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  37870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37871         SOC_RESET_MASK_DEC(0x00382080, 0x00000000)
  37872         -1,
  37873         -1,
  37874     },
  37875 #endif /* chips */
  37876 
  37877 #if defined(BCM_88790_A0)
  37878     { /* SOC_REG_INT_LCM_ECC_ERR_2B_INITIATEr */
  37879         soc_block_list[114],
  37880         soc_genreg,
  37881         1,
  37882         0,
  37883         0xa6,
  37884         0,
  37885         0,
  37886         5,
  37887         soc_LCM_ECC_ERR_2B_INITIATEr_fields,
  37888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37889         SOC_RESET_MASK_DEC(0x00382080, 0x00000000)
  37890         -1,
  37891         -1,
  37892     },
  37893 #endif /* chips */
  37894 
  37895 #if defined(BCM_88790_A0)
  37896     { /* SOC_REG_INT_LCM_ECC_ERR_2B_MONITOR_MEM_MASKr */
  37897         soc_block_list[114],
  37898         soc_genreg,
  37899         1,
  37900         0,
  37901         0x9c,
  37902         0,
  37903         0,
  37904         5,
  37905         soc_LCM_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  37906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37907         SOC_RESET_MASK_DEC(0x00382080, 0x00000000)
  37908         -1,
  37909         -1,
  37910     },
  37911 #endif /* chips */
  37912 
  37913 #if defined(BCM_88790_A0)
  37914     { /* SOC_REG_INT_LCM_ECC_INTERRUPT_REGISTERr */
  37915         soc_block_list[114],
  37916         soc_genreg,
  37917         1,
  37918         0,
  37919         0x7,
  37920         SOC_REG_FLAG_INTERRUPT |
  37921                           SOC_REG_FLAG_SIGNAL,
  37922         0,
  37923         3,
  37924         soc_LCM_ECC_INTERRUPT_REGISTERr_fields,
  37925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37926         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37927         -1,
  37928         -1,
  37929     },
  37930 #endif /* chips */
  37931 
  37932 #if defined(BCM_88790_A0)
  37933     { /* SOC_REG_INT_LCM_ECC_INTERRUPT_REGISTER_MASKr */
  37934         soc_block_list[114],
  37935         soc_genreg,
  37936         1,
  37937         0,
  37938         0x17,
  37939         0,
  37940         0,
  37941         3,
  37942         soc_LCM_ECC_INTERRUPT_REGISTER_MASKr_fields,
  37943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37944         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37945         -1,
  37946         -1,
  37947     },
  37948 #endif /* chips */
  37949 
  37950 #if defined(BCM_88790_A0)
  37951     { /* SOC_REG_INT_LCM_ECC_INTERRUPT_REGISTER_TESTr */
  37952         soc_block_list[114],
  37953         soc_genreg,
  37954         1,
  37955         0,
  37956         0x1f,
  37957         0,
  37958         0,
  37959         1,
  37960         soc_LCM_ECC_INTERRUPT_REGISTER_TESTr_fields,
  37961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37962         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37963         -1,
  37964         -1,
  37965     },
  37966 #endif /* chips */
  37967 
  37968 #if defined(BCM_88790_A0)
  37969     { /* SOC_REG_INT_LCM_ERROR_INITIATION_DATAr */
  37970         soc_block_list[114],
  37971         soc_genreg,
  37972         1,
  37973         0,
  37974         0xa3,
  37975         0,
  37976         0,
  37977         1,
  37978         soc_LCM_ERROR_INITIATION_DATAr_fields,
  37979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37980         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37981         -1,
  37982         -1,
  37983     },
  37984 #endif /* chips */
  37985 
  37986 #if defined(BCM_88790_A0)
  37987     { /* SOC_REG_INT_LCM_FAP_GLOBAL_GENERAL_CFG_1r */
  37988         soc_block_list[114],
  37989         soc_genreg,
  37990         1,
  37991         0,
  37992         0xc3,
  37993         0,
  37994         0,
  37995         2,
  37996         soc_LCM_FAP_GLOBAL_GENERAL_CFG_1r_fields,
  37997         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  37998         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37999         -1,
  38000         -1,
  38001     },
  38002 #endif /* chips */
  38003 
  38004 #if defined(BCM_88790_A0)
  38005     { /* SOC_REG_INT_LCM_FE_GLOBAL_DCH_CAPTURE_CELLS_DCMLr */
  38006         soc_block_list[114],
  38007         soc_genreg,
  38008         1,
  38009         0,
  38010         0xf5,
  38011         0,
  38012         0,
  38013         8,
  38014         soc_LCM_FE_GLOBAL_DCH_CAPTURE_CELLS_DCMLr_fields,
  38015         SOC_RESET_VAL_DEC(0x00fac688, 0x00000000)
  38016         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  38017         -1,
  38018         -1,
  38019     },
  38020 #endif /* chips */
  38021 
  38022 #if defined(BCM_88790_A0)
  38023     { /* SOC_REG_INT_LCM_FE_GLOBAL_GENERAL_CFG_1r */
  38024         soc_block_list[114],
  38025         soc_genreg,
  38026         1,
  38027         0,
  38028         0xf4,
  38029         0,
  38030         0,
  38031         4,
  38032         soc_LCM_FE_GLOBAL_GENERAL_CFG_1r_fields,
  38033         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  38034         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38035         -1,
  38036         -1,
  38037     },
  38038 #endif /* chips */
  38039 
  38040 #if defined(BCM_88790_A0)
  38041     { /* SOC_REG_INT_LCM_GLOBAL_MEM_OPTIONSr */
  38042         soc_block_list[114],
  38043         soc_genreg,
  38044         1,
  38045         0,
  38046         0xc2,
  38047         0,
  38048         0,
  38049         6,
  38050         soc_LCM_GLOBAL_MEM_OPTIONSr_fields,
  38051         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  38052         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  38053         -1,
  38054         -1,
  38055     },
  38056 #endif /* chips */
  38057 
  38058 #if defined(BCM_88790_A0)
  38059     { /* SOC_REG_INT_LCM_GTIMER_CONFIGURATIONr */
  38060         soc_block_list[114],
  38061         soc_genreg,
  38062         1,
  38063         0,
  38064         0x89,
  38065         0,
  38066         0,
  38067         3,
  38068         soc_LCM_GTIMER_CONFIGURATIONr_fields,
  38069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38070         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  38071         -1,
  38072         -1,
  38073     },
  38074 #endif /* chips */
  38075 
  38076 #if defined(BCM_88790_A0)
  38077     { /* SOC_REG_INT_LCM_GTIMER_CYCLEr */
  38078         soc_block_list[114],
  38079         soc_genreg,
  38080         1,
  38081         0,
  38082         0x88,
  38083         0,
  38084         0,
  38085         1,
  38086         soc_LCM_GTIMER_CYCLEr_fields,
  38087         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  38088         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38089         -1,
  38090         -1,
  38091     },
  38092 #endif /* chips */
  38093 
  38094 #if defined(BCM_88790_A0)
  38095     { /* SOC_REG_INT_LCM_INTERRUPT_MASK_REGISTERr */
  38096         soc_block_list[114],
  38097         soc_genreg,
  38098         1,
  38099         0,
  38100         0x10,
  38101         0,
  38102         0,
  38103         5,
  38104         soc_LCM_INTERRUPT_MASK_REGISTERr_fields,
  38105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38106         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  38107         -1,
  38108         -1,
  38109     },
  38110 #endif /* chips */
  38111 
  38112 #if defined(BCM_88790_A0)
  38113     { /* SOC_REG_INT_LCM_INTERRUPT_REGISTERr */
  38114         soc_block_list[114],
  38115         soc_genreg,
  38116         1,
  38117         0,
  38118         0,
  38119         SOC_REG_FLAG_INTERRUPT |
  38120                           SOC_REG_FLAG_SIGNAL,
  38121         0,
  38122         5,
  38123         soc_LCM_INTERRUPT_REGISTERr_fields,
  38124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38125         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  38126         -1,
  38127         -1,
  38128     },
  38129 #endif /* chips */
  38130 
  38131 #if defined(BCM_88790_A0)
  38132     { /* SOC_REG_INT_LCM_INTERRUPT_REGISTER_TESTr */
  38133         soc_block_list[114],
  38134         soc_genreg,
  38135         1,
  38136         0,
  38137         0x18,
  38138         0,
  38139         0,
  38140         1,
  38141         soc_LCM_INTERRUPT_REGISTER_TESTr_fields,
  38142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38143         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  38144         -1,
  38145         -1,
  38146     },
  38147 #endif /* chips */
  38148 
  38149 #if defined(BCM_88790_A0)
  38150     { /* SOC_REG_INT_LCM_LCLRT_FIFOS_DEPTH_TYPEr */
  38151         soc_block_list[114],
  38152         soc_genreg,
  38153         2,
  38154         0,
  38155         0x21b,
  38156         SOC_REG_FLAG_64_BITS |
  38157                           SOC_REG_FLAG_ARRAY |
  38158                           SOC_REG_FLAG_REG_ARRAY,
  38159         0,
  38160         3,
  38161         soc_LCM_LCLRT_FIFOS_DEPTH_TYPEr_fields,
  38162         SOC_RESET_VAL_DEC(0xa82a82a8, 0x00000002)
  38163         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00000007)
  38164         -1,
  38165         -1,
  38166     },
  38167 #endif /* chips */
  38168 
  38169 #if defined(BCM_88790_A0)
  38170     { /* SOC_REG_INT_LCM_LCM_ADMIT_ENABLERSr */
  38171         soc_block_list[114],
  38172         soc_genreg,
  38173         1,
  38174         0,
  38175         0x106,
  38176         0,
  38177         0,
  38178         4,
  38179         soc_LCM_LCM_ADMIT_ENABLERSr_fields,
  38180         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  38181         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38182         -1,
  38183         -1,
  38184     },
  38185 #endif /* chips */
  38186 
  38187 #if defined(BCM_88790_A0)
  38188     { /* SOC_REG_INT_LCM_LCM_FC_ENABLERSr */
  38189         soc_block_list[114],
  38190         soc_genreg,
  38191         1,
  38192         0,
  38193         0x10a,
  38194         0,
  38195         0,
  38196         6,
  38197         soc_LCM_LCM_FC_ENABLERSr_fields,
  38198         SOC_RESET_VAL_DEC(0x00003ff7, 0x00000000)
  38199         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  38200         -1,
  38201         -1,
  38202     },
  38203 #endif /* chips */
  38204 
  38205 #if defined(BCM_88790_A0)
  38206     { /* SOC_REG_INT_LCM_LCM_GCI_ENABLERSr */
  38207         soc_block_list[114],
  38208         soc_genreg,
  38209         1,
  38210         0,
  38211         0x107,
  38212         0,
  38213         0,
  38214         3,
  38215         soc_LCM_LCM_GCI_ENABLERSr_fields,
  38216         SOC_RESET_VAL_DEC(0x07ffffff, 0x00000000)
  38217         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  38218         -1,
  38219         -1,
  38220     },
  38221 #endif /* chips */
  38222 
  38223 #if defined(BCM_88790_A0)
  38224     { /* SOC_REG_INT_LCM_LCM_INTERRUPT_REGISTERr */
  38225         soc_block_list[114],
  38226         soc_genreg,
  38227         1,
  38228         0,
  38229         0x100,
  38230         SOC_REG_FLAG_INTERRUPT |
  38231                           SOC_REG_FLAG_SIGNAL,
  38232         0,
  38233         5,
  38234         soc_LCM_LCM_INTERRUPT_REGISTERr_fields,
  38235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38236         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  38237         -1,
  38238         -1,
  38239     },
  38240 #endif /* chips */
  38241 
  38242 #if defined(BCM_88790_A0)
  38243     { /* SOC_REG_INT_LCM_LCM_INTERRUPT_REGISTER_MASKr */
  38244         soc_block_list[114],
  38245         soc_genreg,
  38246         1,
  38247         0,
  38248         0x101,
  38249         0,
  38250         0,
  38251         5,
  38252         soc_LCM_LCM_INTERRUPT_REGISTER_MASKr_fields,
  38253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38254         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  38255         -1,
  38256         -1,
  38257     },
  38258 #endif /* chips */
  38259 
  38260 #if defined(BCM_88790_A0)
  38261     { /* SOC_REG_INT_LCM_LCM_INTERRUPT_REGISTER_TESTr */
  38262         soc_block_list[114],
  38263         soc_genreg,
  38264         1,
  38265         0,
  38266         0x102,
  38267         0,
  38268         0,
  38269         1,
  38270         soc_LCM_LCM_INTERRUPT_REGISTER_TESTr_fields,
  38271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38272         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  38273         -1,
  38274         -1,
  38275     },
  38276 #endif /* chips */
  38277 
  38278 #if defined(BCM_88790_A0)
  38279     { /* SOC_REG_INT_LCM_LCM_RCI_ENABLERSr */
  38280         soc_block_list[114],
  38281         soc_genreg,
  38282         1,
  38283         0,
  38284         0x108,
  38285         SOC_REG_FLAG_64_BITS,
  38286         0,
  38287         4,
  38288         soc_LCM_LCM_RCI_ENABLERSr_fields,
  38289         SOC_RESET_VAL_DEC(0xffffffff, 0x003fffff)
  38290         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  38291         -1,
  38292         -1,
  38293     },
  38294 #endif /* chips */
  38295 
  38296 #if defined(BCM_88790_A0)
  38297     { /* SOC_REG_INT_LCM_LCM_REGISTER_0r */
  38298         soc_block_list[114],
  38299         soc_genreg,
  38300         1,
  38301         0,
  38302         0x301,
  38303         SOC_REG_FLAG_64_BITS,
  38304         0,
  38305         2,
  38306         soc_LCM_LCM_REGISTER_0r_fields,
  38307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38308         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  38309         -1,
  38310         -1,
  38311     },
  38312 #endif /* chips */
  38313 
  38314 #if defined(BCM_88790_A0)
  38315     { /* SOC_REG_INT_LCM_LCM_REGISTER_1r */
  38316         soc_block_list[114],
  38317         soc_genreg,
  38318         1,
  38319         0,
  38320         0x303,
  38321         0,
  38322         0,
  38323         3,
  38324         soc_LCM_LCM_REGISTER_1r_fields,
  38325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38326         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  38327         -1,
  38328         -1,
  38329     },
  38330 #endif /* chips */
  38331 
  38332 #if defined(BCM_88790_A0)
  38333     { /* SOC_REG_INT_LCM_LCM_REGISTER_2r */
  38334         soc_block_list[114],
  38335         soc_genreg,
  38336         1,
  38337         0,
  38338         0x304,
  38339         0,
  38340         0,
  38341         5,
  38342         soc_LCM_LCM_REGISTER_2r_fields,
  38343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38344         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  38345         -1,
  38346         -1,
  38347     },
  38348 #endif /* chips */
  38349 
  38350 #if defined(BCM_88790_A0)
  38351     { /* SOC_REG_INT_LCM_LCM_REGISTER_3r */
  38352         soc_block_list[114],
  38353         soc_genreg,
  38354         1,
  38355         0,
  38356         0x305,
  38357         0,
  38358         0,
  38359         7,
  38360         soc_LCM_LCM_REGISTER_3r_fields,
  38361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38362         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  38363         -1,
  38364         -1,
  38365     },
  38366 #endif /* chips */
  38367 
  38368 #if defined(BCM_88790_A0)
  38369     { /* SOC_REG_INT_LCM_LCM_REGISTER_5r */
  38370         soc_block_list[114],
  38371         soc_genreg,
  38372         2,
  38373         0,
  38374         0x21f,
  38375         SOC_REG_FLAG_64_BITS |
  38376                           SOC_REG_FLAG_ARRAY |
  38377                           SOC_REG_FLAG_REG_ARRAY,
  38378         0,
  38379         3,
  38380         soc_LCM_LCM_REGISTER_5r_fields,
  38381         SOC_RESET_VAL_DEC(0x06000600, 0x00000600)
  38382         SOC_RESET_MASK_DEC(0x1fff1fff, 0x00001fff)
  38383         -1,
  38384         -1,
  38385     },
  38386 #endif /* chips */
  38387 
  38388 #if defined(BCM_88790_A0)
  38389     { /* SOC_REG_INT_LCM_LCM_REGISTER_6r */
  38390         soc_block_list[114],
  38391         soc_genreg,
  38392         2,
  38393         0,
  38394         0x223,
  38395         SOC_REG_FLAG_64_BITS |
  38396                           SOC_REG_FLAG_ARRAY |
  38397                           SOC_REG_FLAG_REG_ARRAY,
  38398         0,
  38399         3,
  38400         soc_LCM_LCM_REGISTER_6r_fields,
  38401         SOC_RESET_VAL_DEC(0x50aa8554, 0x00000015)
  38402         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  38403         -1,
  38404         -1,
  38405     },
  38406 #endif /* chips */
  38407 
  38408 #if defined(BCM_88790_A0)
  38409     { /* SOC_REG_INT_LCM_LCM_REGISTER_7r */
  38410         soc_block_list[114],
  38411         soc_genreg,
  38412         2,
  38413         0,
  38414         0x227,
  38415         SOC_REG_FLAG_64_BITS |
  38416                           SOC_REG_FLAG_ARRAY |
  38417                           SOC_REG_FLAG_REG_ARRAY,
  38418         0,
  38419         3,
  38420         soc_LCM_LCM_REGISTER_7r_fields,
  38421         SOC_RESET_VAL_DEC(0xa05502a8, 0x0000000a)
  38422         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  38423         -1,
  38424         -1,
  38425     },
  38426 #endif /* chips */
  38427 
  38428 #if defined(BCM_88790_A0)
  38429     { /* SOC_REG_INT_LCM_LCM_REGISTER_8r */
  38430         soc_block_list[114],
  38431         soc_genreg,
  38432         8,
  38433         0,
  38434         0x28e,
  38435         SOC_REG_FLAG_ARRAY |
  38436                           SOC_REG_FLAG_RO |
  38437                           SOC_REG_FLAG_REG_ARRAY,
  38438         0,
  38439         1,
  38440         soc_LCM_LCM_REGISTER_8r_fields,
  38441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38442         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  38443         -1,
  38444         -1,
  38445     },
  38446 #endif /* chips */
  38447 
  38448 #if defined(BCM_88790_A0)
  38449     { /* SOC_REG_INT_LCM_LCM_REGISTER_9r */
  38450         soc_block_list[114],
  38451         soc_genreg,
  38452         3,
  38453         0,
  38454         0x333,
  38455         SOC_REG_FLAG_ABOVE_64_BITS |
  38456                           SOC_REG_FLAG_ARRAY |
  38457                           SOC_REG_FLAG_RO |
  38458                           SOC_REG_FLAG_REG_ARRAY,
  38459         0,
  38460         8,
  38461         soc_LCM_LCM_REGISTER_9r_fields,
  38462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38464         -1,
  38465         -1,
  38466     },
  38467 #endif /* chips */
  38468 
  38469 #if defined(BCM_88790_A0)
  38470     { /* SOC_REG_INT_LCM_LINK_CNT_INFO_1r */
  38471         soc_block_list[114],
  38472         soc_genreg,
  38473         1,
  38474         0,
  38475         0x27b,
  38476         SOC_REG_FLAG_RO,
  38477         0,
  38478         2,
  38479         soc_LCM_LINK_CNT_INFO_1r_fields,
  38480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38481         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  38482         -1,
  38483         -1,
  38484     },
  38485 #endif /* chips */
  38486 
  38487 #if defined(BCM_88790_A0)
  38488     { /* SOC_REG_INT_LCM_LINK_CNT_INFO_2r */
  38489         soc_block_list[114],
  38490         soc_genreg,
  38491         1,
  38492         0,
  38493         0x27c,
  38494         SOC_REG_FLAG_RO,
  38495         0,
  38496         2,
  38497         soc_LCM_LINK_CNT_INFO_2r_fields,
  38498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38499         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  38500         -1,
  38501         -1,
  38502     },
  38503 #endif /* chips */
  38504 
  38505 #if defined(BCM_88790_A0)
  38506     { /* SOC_REG_INT_LCM_LINK_CNT_INFO_3r */
  38507         soc_block_list[114],
  38508         soc_genreg,
  38509         1,
  38510         0,
  38511         0x27d,
  38512         SOC_REG_FLAG_RO,
  38513         0,
  38514         2,
  38515         soc_LCM_LINK_CNT_INFO_3r_fields,
  38516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38517         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  38518         -1,
  38519         -1,
  38520     },
  38521 #endif /* chips */
  38522 
  38523 #if defined(BCM_88790_A0)
  38524     { /* SOC_REG_INT_LCM_LINK_CNT_INFO_4r */
  38525         soc_block_list[114],
  38526         soc_genreg,
  38527         1,
  38528         0,
  38529         0x27e,
  38530         SOC_REG_FLAG_RO,
  38531         0,
  38532         2,
  38533         soc_LCM_LINK_CNT_INFO_4r_fields,
  38534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38535         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  38536         -1,
  38537         -1,
  38538     },
  38539 #endif /* chips */
  38540 
  38541 #if defined(BCM_88790_A0)
  38542     { /* SOC_REG_INT_LCM_LINK_CNT_INFO_5r */
  38543         soc_block_list[114],
  38544         soc_genreg,
  38545         1,
  38546         0,
  38547         0x27f,
  38548         SOC_REG_FLAG_RO,
  38549         0,
  38550         2,
  38551         soc_LCM_LINK_CNT_INFO_5r_fields,
  38552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38553         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38554         -1,
  38555         -1,
  38556     },
  38557 #endif /* chips */
  38558 
  38559 #if defined(BCM_88790_A0)
  38560     { /* SOC_REG_INT_LCM_LINK_CNT_INFO_6r */
  38561         soc_block_list[114],
  38562         soc_genreg,
  38563         1,
  38564         0,
  38565         0x280,
  38566         SOC_REG_FLAG_RO,
  38567         0,
  38568         2,
  38569         soc_LCM_LINK_CNT_INFO_6r_fields,
  38570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38572         -1,
  38573         -1,
  38574     },
  38575 #endif /* chips */
  38576 
  38577 #if defined(BCM_88790_A0)
  38578     { /* SOC_REG_INT_LCM_LINK_CNT_INFO_7r */
  38579         soc_block_list[114],
  38580         soc_genreg,
  38581         1,
  38582         0,
  38583         0x281,
  38584         SOC_REG_FLAG_64_BITS |
  38585                           SOC_REG_FLAG_RO,
  38586         0,
  38587         2,
  38588         soc_LCM_LINK_CNT_INFO_7r_fields,
  38589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38590         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  38591         -1,
  38592         -1,
  38593     },
  38594 #endif /* chips */
  38595 
  38596 #if defined(BCM_88790_A0)
  38597     { /* SOC_REG_INT_LCM_LINK_CNT_INFO_SELECTr */
  38598         soc_block_list[114],
  38599         soc_genreg,
  38600         1,
  38601         0,
  38602         0x27a,
  38603         0,
  38604         0,
  38605         2,
  38606         soc_LCM_LINK_CNT_INFO_SELECTr_fields,
  38607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38608         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  38609         -1,
  38610         -1,
  38611     },
  38612 #endif /* chips */
  38613 
  38614 #if defined(BCM_88790_A0)
  38615     { /* SOC_REG_INT_LCM_LINK_FC_TH_PROFILEr */
  38616         soc_block_list[114],
  38617         soc_genreg,
  38618         2,
  38619         0,
  38620         0x111,
  38621         SOC_REG_FLAG_64_BITS |
  38622                           SOC_REG_FLAG_ARRAY |
  38623                           SOC_REG_FLAG_REG_ARRAY,
  38624         0,
  38625         3,
  38626         soc_LCM_LINK_FC_TH_PROFILEr_fields,
  38627         SOC_RESET_VAL_DEC(0x8ca08ca0, 0x00008ca0)
  38628         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  38629         -1,
  38630         -1,
  38631     },
  38632 #endif /* chips */
  38633 
  38634 #if defined(BCM_88790_A0)
  38635     { /* SOC_REG_INT_LCM_LINK_LEVEL_FLOW_CONTROL_Pr */
  38636         soc_block_list[114],
  38637         soc_genreg,
  38638         3,
  38639         0,
  38640         0x37d,
  38641         SOC_REG_FLAG_ARRAY |
  38642                           SOC_REG_FLAG_RO |
  38643                           SOC_REG_FLAG_REG_ARRAY |
  38644                           SOC_REG_FLAG_SIGNAL,
  38645         0,
  38646         1,
  38647         soc_LCM_LINK_LEVEL_FLOW_CONTROL_Pr_fields,
  38648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38649         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  38650         -1,
  38651         -1,
  38652     },
  38653 #endif /* chips */
  38654 
  38655 #if defined(BCM_88790_A0)
  38656     { /* SOC_REG_INT_LCM_LINK_LOAD_COUNT_CFGr */
  38657         soc_block_list[114],
  38658         soc_genreg,
  38659         1,
  38660         0,
  38661         0x20f,
  38662         0,
  38663         0,
  38664         1,
  38665         soc_LCM_LINK_LOAD_COUNT_CFGr_fields,
  38666         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  38667         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  38668         -1,
  38669         -1,
  38670     },
  38671 #endif /* chips */
  38672 
  38673 #if defined(BCM_88790_A0)
  38674     { /* SOC_REG_INT_LCM_LINK_LOAD_HYST_THr */
  38675         soc_block_list[114],
  38676         soc_genreg,
  38677         1,
  38678         0,
  38679         0x211,
  38680         0,
  38681         0,
  38682         2,
  38683         soc_LCM_LINK_LOAD_HYST_THr_fields,
  38684         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
  38685         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38686         -1,
  38687         -1,
  38688     },
  38689 #endif /* chips */
  38690 
  38691 #if defined(BCM_88790_A0)
  38692     { /* SOC_REG_INT_LCM_LINK_LOAD_HYST_TYPEr */
  38693         soc_block_list[114],
  38694         soc_genreg,
  38695         1,
  38696         0,
  38697         0x210,
  38698         0,
  38699         0,
  38700         1,
  38701         soc_LCM_LINK_LOAD_HYST_TYPEr_fields,
  38702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38703         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  38704         -1,
  38705         -1,
  38706     },
  38707 #endif /* chips */
  38708 
  38709 #if defined(BCM_88790_A0)
  38710     { /* SOC_REG_INT_LCM_LINK_RCI_GRNT_TH_PROFILEr */
  38711         soc_block_list[114],
  38712         soc_genreg,
  38713         2,
  38714         0,
  38715         0x115,
  38716         SOC_REG_FLAG_ABOVE_64_BITS |
  38717                           SOC_REG_FLAG_ARRAY |
  38718                           SOC_REG_FLAG_REG_ARRAY,
  38719         0,
  38720         9,
  38721         soc_LCM_LINK_RCI_GRNT_TH_PROFILEr_fields,
  38722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38724         -1,
  38725         -1,
  38726     },
  38727 #endif /* chips */
  38728 
  38729 #if defined(BCM_88790_A0)
  38730     { /* SOC_REG_INT_LCM_LINK_RCI_TOTAL_TH_PROFILEr */
  38731         soc_block_list[114],
  38732         soc_genreg,
  38733         2,
  38734         0,
  38735         0x11f,
  38736         SOC_REG_FLAG_ABOVE_64_BITS |
  38737                           SOC_REG_FLAG_ARRAY |
  38738                           SOC_REG_FLAG_REG_ARRAY,
  38739         0,
  38740         9,
  38741         soc_LCM_LINK_RCI_TOTAL_TH_PROFILEr_fields,
  38742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38744         -1,
  38745         -1,
  38746     },
  38747 #endif /* chips */
  38748 
  38749 #if defined(BCM_88790_A0)
  38750     { /* SOC_REG_INT_LCM_LINK_TH_PROFILEr */
  38751         soc_block_list[114],
  38752         soc_genreg,
  38753         2,
  38754         0,
  38755         0x10b,
  38756         SOC_REG_FLAG_ABOVE_64_BITS |
  38757                           SOC_REG_FLAG_ARRAY |
  38758                           SOC_REG_FLAG_REG_ARRAY,
  38759         0,
  38760         6,
  38761         soc_LCM_LINK_TH_PROFILEr_fields,
  38762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38764         -1,
  38765         -1,
  38766     },
  38767 #endif /* chips */
  38768 
  38769 #if defined(BCM_88790_A0)
  38770     { /* SOC_REG_INT_LCM_LINK_TH_PROFILES_MAPPINGr */
  38771         soc_block_list[114],
  38772         soc_genreg,
  38773         1,
  38774         0,
  38775         0x129,
  38776         0,
  38777         0,
  38778         1,
  38779         soc_LCM_LINK_TH_PROFILES_MAPPINGr_fields,
  38780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38781         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  38782         -1,
  38783         -1,
  38784     },
  38785 #endif /* chips */
  38786 
  38787 #if defined(BCM_88790_A0)
  38788     { /* SOC_REG_INT_LCM_LLFC_RATE_CNT_Pr */
  38789         soc_block_list[114],
  38790         soc_genreg,
  38791         3,
  38792         0,
  38793         0x380,
  38794         SOC_REG_FLAG_ARRAY |
  38795                           SOC_REG_FLAG_RO |
  38796                           SOC_REG_FLAG_REG_ARRAY,
  38797         SOC_REG_FLAG_COUNTER_FEILDS,
  38798         1,
  38799         soc_LCM_LLFC_RATE_CNT_Pr_fields,
  38800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38801         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38802         -1,
  38803         -1,
  38804     },
  38805 #endif /* chips */
  38806 
  38807 #if defined(BCM_88790_A0)
  38808     { /* SOC_REG_INT_LCM_PIPES_MAPPING_ENr */
  38809         soc_block_list[114],
  38810         soc_genreg,
  38811         1,
  38812         0,
  38813         0x346,
  38814         0,
  38815         0,
  38816         1,
  38817         soc_LCM_PIPES_MAPPING_ENr_fields,
  38818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38819         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  38820         -1,
  38821         -1,
  38822     },
  38823 #endif /* chips */
  38824 
  38825 #if defined(BCM_88790_A0)
  38826     { /* SOC_REG_INT_LCM_PIPES_SEPARATION_REGISTERr */
  38827         soc_block_list[114],
  38828         soc_genreg,
  38829         1,
  38830         0,
  38831         0x103,
  38832         0,
  38833         0,
  38834         8,
  38835         soc_LCM_PIPES_SEPARATION_REGISTERr_fields,
  38836         SOC_RESET_VAL_DEC(0x00008095, 0x00000000)
  38837         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  38838         -1,
  38839         -1,
  38840     },
  38841 #endif /* chips */
  38842 
  38843 #if defined(BCM_88790_A0)
  38844     { /* SOC_REG_INT_LCM_RCI_TABLE_PIPEr */
  38845         soc_block_list[114],
  38846         soc_genreg,
  38847         3,
  38848         0,
  38849         0x20a,
  38850         SOC_REG_FLAG_ARRAY |
  38851                           SOC_REG_FLAG_REG_ARRAY,
  38852         0,
  38853         1,
  38854         soc_LCM_RCI_TABLE_PIPEr_fields,
  38855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38856         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38857         -1,
  38858         -1,
  38859     },
  38860 #endif /* chips */
  38861 
  38862 #if defined(BCM_88790_A0)
  38863     { /* SOC_REG_INT_LCM_READ_MECH_DEBUG_1r */
  38864         soc_block_list[114],
  38865         soc_genreg,
  38866         1,
  38867         0,
  38868         0x383,
  38869         0,
  38870         0,
  38871         1,
  38872         soc_LCM_READ_MECH_DEBUG_1r_fields,
  38873         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  38874         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  38875         -1,
  38876         -1,
  38877     },
  38878 #endif /* chips */
  38879 
  38880 #if defined(BCM_88790_A0)
  38881     { /* SOC_REG_INT_LCM_REMOTE_PRI_PIPE_IDXr */
  38882         soc_block_list[114],
  38883         soc_genreg,
  38884         1,
  38885         0,
  38886         0x347,
  38887         SOC_REG_FLAG_64_BITS,
  38888         0,
  38889         1,
  38890         soc_LCM_REMOTE_PRI_PIPE_IDXr_fields,
  38891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38892         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  38893         -1,
  38894         -1,
  38895     },
  38896 #endif /* chips */
  38897 
  38898 #if defined(BCM_88790_A0)
  38899     { /* SOC_REG_INT_LCM_REMOTE_SEC_PIPE_IDXr */
  38900         soc_block_list[114],
  38901         soc_genreg,
  38902         1,
  38903         0,
  38904         0x349,
  38905         SOC_REG_FLAG_64_BITS,
  38906         0,
  38907         1,
  38908         soc_LCM_REMOTE_SEC_PIPE_IDXr_fields,
  38909         SOC_RESET_VAL_DEC(0x55555555, 0x00005555)
  38910         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  38911         -1,
  38912         -1,
  38913     },
  38914 #endif /* chips */
  38915 
  38916 #if defined(BCM_88790_A0)
  38917     { /* SOC_REG_INT_LCM_RESERVED_MIRROR_ADDRr */
  38918         soc_block_list[114],
  38919         soc_genreg,
  38920         1,
  38921         0,
  38922         0x85,
  38923         0,
  38924         0,
  38925         2,
  38926         soc_LCM_RESERVED_MIRROR_ADDRr_fields,
  38927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38928         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  38929         -1,
  38930         -1,
  38931     },
  38932 #endif /* chips */
  38933 
  38934 #if defined(BCM_88790_A0)
  38935     { /* SOC_REG_INT_LCM_RESERVED_MTCDr */
  38936         soc_block_list[114],
  38937         soc_genreg,
  38938         1,
  38939         0,
  38940         0xae,
  38941         0,
  38942         0,
  38943         6,
  38944         soc_LCM_RESERVED_MTCDr_fields,
  38945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38946         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  38947         -1,
  38948         -1,
  38949     },
  38950 #endif /* chips */
  38951 
  38952 #if defined(BCM_88790_A0)
  38953     { /* SOC_REG_INT_LCM_RESERVED_MTCPr */
  38954         soc_block_list[114],
  38955         soc_genreg,
  38956         1,
  38957         0,
  38958         0xad,
  38959         SOC_REG_FLAG_64_BITS,
  38960         0,
  38961         17,
  38962         soc_LCM_RESERVED_MTCPr_fields,
  38963         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  38964         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  38965         -1,
  38966         -1,
  38967     },
  38968 #endif /* chips */
  38969 
  38970 #if defined(BCM_88790_A0)
  38971     { /* SOC_REG_INT_LCM_RESERVED_SPARE_0r */
  38972         soc_block_list[114],
  38973         soc_genreg,
  38974         1,
  38975         0,
  38976         0x90,
  38977         0,
  38978         0,
  38979         1,
  38980         soc_LCM_RESERVED_SPARE_0r_fields,
  38981         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  38982         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38983         -1,
  38984         -1,
  38985     },
  38986 #endif /* chips */
  38987 
  38988 #if defined(BCM_88790_A0)
  38989     { /* SOC_REG_INT_LCM_RESERVED_SPARE_1r */
  38990         soc_block_list[114],
  38991         soc_genreg,
  38992         1,
  38993         0,
  38994         0x91,
  38995         0,
  38996         0,
  38997         1,
  38998         soc_LCM_RESERVED_SPARE_1r_fields,
  38999         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  39000         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39001         -1,
  39002         -1,
  39003     },
  39004 #endif /* chips */
  39005 
  39006 #if defined(BCM_88790_A0)
  39007     { /* SOC_REG_INT_LCM_RESERVED_SPARE_2r */
  39008         soc_block_list[114],
  39009         soc_genreg,
  39010         1,
  39011         0,
  39012         0x92,
  39013         0,
  39014         0,
  39015         1,
  39016         soc_LCM_RESERVED_SPARE_2r_fields,
  39017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39018         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39019         -1,
  39020         -1,
  39021     },
  39022 #endif /* chips */
  39023 
  39024 #if defined(BCM_88790_A0)
  39025     { /* SOC_REG_INT_LCM_RESERVED_SPARE_3r */
  39026         soc_block_list[114],
  39027         soc_genreg,
  39028         1,
  39029         0,
  39030         0x93,
  39031         0,
  39032         0,
  39033         1,
  39034         soc_LCM_RESERVED_SPARE_3r_fields,
  39035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39037         -1,
  39038         -1,
  39039     },
  39040 #endif /* chips */
  39041 
  39042 #if defined(BCM_88790_A0)
  39043     { /* SOC_REG_INT_LCM_SBUS_BROADCAST_IDr */
  39044         soc_block_list[114],
  39045         soc_genreg,
  39046         1,
  39047         0,
  39048         0x86,
  39049         0,
  39050         0,
  39051         1,
  39052         soc_LCM_SBUS_BROADCAST_IDr_fields,
  39053         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  39054         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  39055         -1,
  39056         -1,
  39057     },
  39058 #endif /* chips */
  39059 
  39060 #if defined(BCM_88790_A0)
  39061     { /* SOC_REG_INT_LCM_SBUS_LAST_IN_CHAINr */
  39062         soc_block_list[114],
  39063         soc_genreg,
  39064         1,
  39065         0,
  39066         0x87,
  39067         0,
  39068         0,
  39069         1,
  39070         soc_LCM_SBUS_LAST_IN_CHAINr_fields,
  39071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39072         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39073         -1,
  39074         -1,
  39075     },
  39076 #endif /* chips */
  39077 
  39078 #if defined(BCM_88790_A0)
  39079     { /* SOC_REG_INT_LCM_THREE_PIPES_BMPr */
  39080         soc_block_list[114],
  39081         soc_genreg,
  39082         1,
  39083         0,
  39084         0x34c,
  39085         0,
  39086         0,
  39087         1,
  39088         soc_LCM_THREE_PIPES_BMPr_fields,
  39089         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  39090         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  39091         -1,
  39092         -1,
  39093     },
  39094 #endif /* chips */
  39095 
  39096 #if defined(BCM_88790_A0)
  39097     { /* SOC_REG_INT_LCM_TWO_PIPES_BMPr */
  39098         soc_block_list[114],
  39099         soc_genreg,
  39100         1,
  39101         0,
  39102         0x34b,
  39103         0,
  39104         0,
  39105         1,
  39106         soc_LCM_TWO_PIPES_BMPr_fields,
  39107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39108         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  39109         -1,
  39110         -1,
  39111     },
  39112 #endif /* chips */
  39113 
  39114 #if defined(BCM_88790_A0)
  39115     { /* SOC_REG_INT_LCM_TX_CPU_CELL_OUTPUT_LINKr */
  39116         soc_block_list[114],
  39117         soc_genreg,
  39118         1,
  39119         0,
  39120         0x355,
  39121         0,
  39122         0,
  39123         2,
  39124         soc_LCM_TX_CPU_CELL_OUTPUT_LINKr_fields,
  39125         SOC_RESET_VAL_DEC(0x00007f00, 0x00000000)
  39126         SOC_RESET_MASK_DEC(0x0000ff1f, 0x00000000)
  39127         -1,
  39128         -1,
  39129     },
  39130 #endif /* chips */
  39131 
  39132 #if defined(BCM_88790_A0)
  39133     { /* SOC_REG_INT_LCM_TX_CPU_CELL_TRGr */
  39134         soc_block_list[114],
  39135         soc_genreg,
  39136         1,
  39137         0,
  39138         0x354,
  39139         SOC_REG_FLAG_SIGNAL,
  39140         0,
  39141         1,
  39142         soc_LCM_TX_CPU_CELL_TRGr_fields,
  39143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39144         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  39145         -1,
  39146         -1,
  39147     },
  39148 #endif /* chips */
  39149 
  39150 #if defined(BCM_56640_A0)
  39151     { /* SOC_REG_INT_LEARN_CONTROLr */
  39152         soc_block_list[87],
  39153         soc_genreg,
  39154         1,
  39155         0,
  39156         0xfe001100,
  39157         0,
  39158         0,
  39159         4,
  39160         soc_LEARN_CONTROLr_fields,
  39161         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  39162         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  39163         -1,
  39164         -1,
  39165     },
  39166 #endif /* chips */
  39167 
  39168 #if defined(BCM_56340_A0)
  39169     { /* SOC_REG_INT_LEARN_CONTROL_BCM56340_A0r */
  39170         soc_block_list[87],
  39171         soc_genreg,
  39172         1,
  39173         0,
  39174         0xfe001100,
  39175         0,
  39176         0,
  39177         4,
  39178         soc_LEARN_CONTROL_BCM56340_A0r_fields,
  39179         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  39180         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  39181         -1,
  39182         -1,
  39183     },
  39184 #endif /* chips */
  39185 
  39186 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  39187     defined(BCM_56870_A0)
  39188     { /* SOC_REG_INT_LEARN_CONTROL_BCM56870_A0r */
  39189         soc_block_list[5],
  39190         soc_genreg,
  39191         1,
  39192         0,
  39193         0xaa000100,
  39194         0,
  39195         0,
  39196         3,
  39197         soc_LEARN_CONTROL_BCM56870_A0r_fields,
  39198         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  39199         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  39200         -1,
  39201         -1,
  39202         3,
  39203     },
  39204 #endif /* chips */
  39205 
  39206 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  39207     { /* SOC_REG_INT_LEARN_CONTROL_BCM56960_A0r */
  39208         soc_block_list[5],
  39209         soc_genreg,
  39210         1,
  39211         0,
  39212         0x62000100,
  39213         0,
  39214         0,
  39215         2,
  39216         soc_IARB_LEARN_CONTROL_BCM53400_A0r_fields,
  39217         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  39218         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  39219         -1,
  39220         -1,
  39221         3,
  39222     },
  39223 #endif /* chips */
  39224 
  39225 #if defined(BCM_56970_A0)
  39226     { /* SOC_REG_INT_LEARN_CONTROL_BCM56970_A0r */
  39227         soc_block_list[5],
  39228         soc_genreg,
  39229         1,
  39230         0,
  39231         0xa2000100,
  39232         0,
  39233         0,
  39234         2,
  39235         soc_IARB_LEARN_CONTROL_BCM53400_A0r_fields,
  39236         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  39237         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  39238         -1,
  39239         -1,
  39240         3,
  39241     },
  39242 #endif /* chips */
  39243 
  39244 #if defined(BCM_56640_A0)
  39245     { /* SOC_REG_INT_LEARN_FIFO_ECC_CONTROLr */
  39246         soc_block_list[87],
  39247         soc_genreg,
  39248         1,
  39249         0,
  39250         0xfe001d00,
  39251         0,
  39252         0,
  39253         3,
  39254         soc_LEARN_FIFO_ECC_CONTROLr_fields,
  39255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39256         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39257         -1,
  39258         -1,
  39259     },
  39260 #endif /* chips */
  39261 
  39262 #if defined(BCM_56340_A0)
  39263     { /* SOC_REG_INT_LEARN_FIFO_ECC_CONTROL_BCM56340_A0r */
  39264         soc_block_list[87],
  39265         soc_genreg,
  39266         1,
  39267         0,
  39268         0xfe001d00,
  39269         0,
  39270         0,
  39271         4,
  39272         soc_LEARN_FIFO_ECC_CONTROL_BCM56340_A0r_fields,
  39273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39274         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39275         -1,
  39276         -1,
  39277     },
  39278 #endif /* chips */
  39279 
  39280 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  39281     defined(BCM_56870_A0)
  39282     { /* SOC_REG_INT_LEARN_FIFO_ECC_CONTROL_BCM56870_A0r */
  39283         soc_block_list[5],
  39284         soc_genreg,
  39285         1,
  39286         0,
  39287         0xaa002200,
  39288         0,
  39289         0,
  39290         4,
  39291         soc_LEARN_FIFO_ECC_CONTROL_BCM56960_A0r_fields,
  39292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39293         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39294         -1,
  39295         -1,
  39296         3,
  39297     },
  39298 #endif /* chips */
  39299 
  39300 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  39301     { /* SOC_REG_INT_LEARN_FIFO_ECC_CONTROL_BCM56960_A0r */
  39302         soc_block_list[5],
  39303         soc_genreg,
  39304         1,
  39305         0,
  39306         0x62002200,
  39307         0,
  39308         0,
  39309         4,
  39310         soc_LEARN_FIFO_ECC_CONTROL_BCM56960_A0r_fields,
  39311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39312         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39313         -1,
  39314         -1,
  39315         3,
  39316     },
  39317 #endif /* chips */
  39318 
  39319 #if defined(BCM_56970_A0)
  39320     { /* SOC_REG_INT_LEARN_FIFO_ECC_CONTROL_BCM56970_A0r */
  39321         soc_block_list[5],
  39322         soc_genreg,
  39323         1,
  39324         0,
  39325         0xa2002200,
  39326         0,
  39327         0,
  39328         4,
  39329         soc_LEARN_FIFO_ECC_CONTROL_BCM56960_A0r_fields,
  39330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39332         -1,
  39333         -1,
  39334         3,
  39335     },
  39336 #endif /* chips */
  39337 
  39338 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  39339     { /* SOC_REG_INT_LINK_LIST_DEBUG_TMr */
  39340         soc_block_list[4],
  39341         soc_genreg,
  39342         1,
  39343         0,
  39344         0x92016100,
  39345         0,
  39346         0,
  39347         1,
  39348         soc_UCQDBMEMDEBUGr_fields,
  39349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39351         -1,
  39352         -1,
  39353     },
  39354 #endif /* chips */
  39355 
  39356 #if defined(BCM_56370_A0)
  39357     { /* SOC_REG_INT_LINK_LIST_DEBUG_TM_BCM56370_A0r */
  39358         soc_block_list[124],
  39359         soc_genreg,
  39360         1,
  39361         0,
  39362         0x2e016100,
  39363         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  39364         0,
  39365         1,
  39366         soc_FP_METER_TMr_fields,
  39367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39369         -1,
  39370         -1,
  39371         3,
  39372     },
  39373 #endif /* chips */
  39374 
  39375 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  39376     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  39377     { /* SOC_REG_INT_LINK_LIST_DEBUG_TM_BCM56560_A0r */
  39378         soc_block_list[4],
  39379         soc_genreg,
  39380         1,
  39381         0,
  39382         0x92016100,
  39383         0,
  39384         0,
  39385         1,
  39386         soc_E2EFC_MEM_TMr_fields,
  39387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39388         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39389         -1,
  39390         -1,
  39391     },
  39392 #endif /* chips */
  39393 
  39394 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  39395     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  39396     defined(BCM_56970_A0)
  39397     { /* SOC_REG_INT_LINK_LIST_DEBUG_TM_BCM56960_A0r */
  39398         soc_block_list[124],
  39399         soc_genreg,
  39400         1,
  39401         0,
  39402         0x2e016100,
  39403         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  39404         0,
  39405         1,
  39406         soc_CCPMEMDEBUG_BCM56960_A0r_fields,
  39407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39408         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39409         -1,
  39410         -1,
  39411         3,
  39412     },
  39413 #endif /* chips */
  39414 
  39415 #if defined(BCM_56800_A0)
  39416     { /* SOC_REG_INT_LINK_STATUSr */
  39417         soc_block_list[5],
  39418         soc_genreg,
  39419         1,
  39420         0,
  39421         0xe080639,
  39422         0,
  39423         0,
  39424         1,
  39425         soc_LINK_STATUSr_fields,
  39426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39427         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39428         -1,
  39429         -1,
  39430     },
  39431 #endif /* chips */
  39432 
  39433 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  39434     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  39435     { /* SOC_REG_INT_LINK_STATUS_64r */
  39436         soc_block_list[5],
  39437         soc_genreg,
  39438         1,
  39439         0,
  39440         0x11080039,
  39441         SOC_REG_FLAG_64_BITS,
  39442         0,
  39443         3,
  39444         soc_LINK_STATUS_64r_fields,
  39445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39446         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39447         -1,
  39448         -1,
  39449     },
  39450 #endif /* chips */
  39451 
  39452 #if defined(BCM_53400_A0)
  39453     { /* SOC_REG_INT_LINK_STATUS_64_BCM53400_A0r */
  39454         soc_block_list[5],
  39455         soc_genreg,
  39456         1,
  39457         0,
  39458         0x42002c00,
  39459         0,
  39460         0,
  39461         2,
  39462         soc_LINK_STATUS_64_BCM53400_A0r_fields,
  39463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39464         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39465         -1,
  39466         -1,
  39467     },
  39468 #endif /* chips */
  39469 
  39470 #if defined(BCM_56142_A0)
  39471     { /* SOC_REG_INT_LINK_STATUS_64_BCM56142_A0r */
  39472         soc_block_list[5],
  39473         soc_genreg,
  39474         1,
  39475         0,
  39476         0x11080094,
  39477         0,
  39478         0,
  39479         2,
  39480         soc_LINK_STATUS_64_BCM56334_A0r_fields,
  39481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39482         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39483         -1,
  39484         -1,
  39485     },
  39486 #endif /* chips */
  39487 
  39488 #if defined(BCM_56150_A0)
  39489     { /* SOC_REG_INT_LINK_STATUS_64_BCM56150_A0r */
  39490         soc_block_list[5],
  39491         soc_genreg,
  39492         1,
  39493         0,
  39494         0x46002c00,
  39495         0,
  39496         0,
  39497         2,
  39498         soc_LINK_STATUS_64_BCM56150_A0r_fields,
  39499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39500         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39501         -1,
  39502         -1,
  39503     },
  39504 #endif /* chips */
  39505 
  39506 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  39507     { /* SOC_REG_INT_LINK_STATUS_64_BCM56160_A0r */
  39508         soc_block_list[5],
  39509         soc_genreg,
  39510         1,
  39511         0,
  39512         0x42002c00,
  39513         0,
  39514         0,
  39515         2,
  39516         soc_LINK_STATUS_64_BCM56160_A0r_fields,
  39517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39518         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39519         -1,
  39520         -1,
  39521     },
  39522 #endif /* chips */
  39523 
  39524 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  39525     { /* SOC_REG_INT_LINK_STATUS_64_BCM56334_A0r */
  39526         soc_block_list[5],
  39527         soc_genreg,
  39528         1,
  39529         0,
  39530         0x11080039,
  39531         0,
  39532         0,
  39533         2,
  39534         soc_LINK_STATUS_64_BCM56334_A0r_fields,
  39535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39536         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39537         -1,
  39538         -1,
  39539     },
  39540 #endif /* chips */
  39541 
  39542 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  39543     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  39544     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  39545     { /* SOC_REG_INT_LINK_STATUS_64_BCM56634_A0r */
  39546         soc_block_list[5],
  39547         soc_genreg,
  39548         1,
  39549         0,
  39550         0xe080049,
  39551         SOC_REG_FLAG_64_BITS,
  39552         0,
  39553         3,
  39554         soc_LINK_STATUS_64r_fields,
  39555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39556         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39557         -1,
  39558         -1,
  39559     },
  39560 #endif /* chips */
  39561 
  39562 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  39563     { /* SOC_REG_INT_LINK_STATUS_BCM56820_A0r */
  39564         soc_block_list[5],
  39565         soc_genreg,
  39566         1,
  39567         0,
  39568         0xf080687,
  39569         0,
  39570         0,
  39571         1,
  39572         soc_LINK_STATUS_BCM56820_A0r_fields,
  39573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39574         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39575         -1,
  39576         -1,
  39577     },
  39578 #endif /* chips */
  39579 
  39580 #if defined(BCM_88732_A0)
  39581     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_0r */
  39582         soc_block_list[78],
  39583         soc_genreg,
  39584         1,
  39585         0,
  39586         0x8002a,
  39587         0,
  39588         0,
  39589         1,
  39590         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39591         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39592         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39593         -1,
  39594         -1,
  39595     },
  39596 #endif /* chips */
  39597 
  39598 #if defined(BCM_88732_A0)
  39599     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_1r */
  39600         soc_block_list[78],
  39601         soc_genreg,
  39602         1,
  39603         0,
  39604         0x8002b,
  39605         0,
  39606         0,
  39607         1,
  39608         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39609         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39610         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39611         -1,
  39612         -1,
  39613     },
  39614 #endif /* chips */
  39615 
  39616 #if defined(BCM_88732_A0)
  39617     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_2r */
  39618         soc_block_list[78],
  39619         soc_genreg,
  39620         1,
  39621         0,
  39622         0x8002c,
  39623         0,
  39624         0,
  39625         1,
  39626         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39627         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39628         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39629         -1,
  39630         -1,
  39631     },
  39632 #endif /* chips */
  39633 
  39634 #if defined(BCM_88732_A0)
  39635     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_3r */
  39636         soc_block_list[78],
  39637         soc_genreg,
  39638         1,
  39639         0,
  39640         0x8002d,
  39641         0,
  39642         0,
  39643         1,
  39644         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39645         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39646         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39647         -1,
  39648         -1,
  39649     },
  39650 #endif /* chips */
  39651 
  39652 #if defined(BCM_88732_A0)
  39653     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_4r */
  39654         soc_block_list[78],
  39655         soc_genreg,
  39656         1,
  39657         0,
  39658         0x8002e,
  39659         0,
  39660         0,
  39661         1,
  39662         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39663         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39664         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39665         -1,
  39666         -1,
  39667     },
  39668 #endif /* chips */
  39669 
  39670 #if defined(BCM_88732_A0)
  39671     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_5r */
  39672         soc_block_list[78],
  39673         soc_genreg,
  39674         1,
  39675         0,
  39676         0x8002f,
  39677         0,
  39678         0,
  39679         1,
  39680         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39681         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39682         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39683         -1,
  39684         -1,
  39685     },
  39686 #endif /* chips */
  39687 
  39688 #if defined(BCM_88732_A0)
  39689     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_6r */
  39690         soc_block_list[78],
  39691         soc_genreg,
  39692         1,
  39693         0,
  39694         0x80030,
  39695         0,
  39696         0,
  39697         1,
  39698         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39699         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39700         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39701         -1,
  39702         -1,
  39703     },
  39704 #endif /* chips */
  39705 
  39706 #if defined(BCM_88732_A0)
  39707     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_7r */
  39708         soc_block_list[78],
  39709         soc_genreg,
  39710         1,
  39711         0,
  39712         0x80031,
  39713         0,
  39714         0,
  39715         1,
  39716         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39717         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39718         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39719         -1,
  39720         -1,
  39721     },
  39722 #endif /* chips */
  39723 
  39724 #if defined(BCM_88732_A0)
  39725     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_8r */
  39726         soc_block_list[78],
  39727         soc_genreg,
  39728         1,
  39729         0,
  39730         0x80032,
  39731         0,
  39732         0,
  39733         1,
  39734         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39735         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39736         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39737         -1,
  39738         -1,
  39739     },
  39740 #endif /* chips */
  39741 
  39742 #if defined(BCM_88732_A0)
  39743     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_9r */
  39744         soc_block_list[78],
  39745         soc_genreg,
  39746         1,
  39747         0,
  39748         0x80033,
  39749         0,
  39750         0,
  39751         1,
  39752         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39753         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39754         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39755         -1,
  39756         -1,
  39757     },
  39758 #endif /* chips */
  39759 
  39760 #if defined(BCM_88732_A0)
  39761     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_10r */
  39762         soc_block_list[78],
  39763         soc_genreg,
  39764         1,
  39765         0,
  39766         0x80034,
  39767         0,
  39768         0,
  39769         1,
  39770         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39771         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39772         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39773         -1,
  39774         -1,
  39775     },
  39776 #endif /* chips */
  39777 
  39778 #if defined(BCM_88732_A0)
  39779     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_11r */
  39780         soc_block_list[78],
  39781         soc_genreg,
  39782         1,
  39783         0,
  39784         0x80035,
  39785         0,
  39786         0,
  39787         1,
  39788         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39789         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39790         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39791         -1,
  39792         -1,
  39793     },
  39794 #endif /* chips */
  39795 
  39796 #if defined(BCM_88732_A0)
  39797     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_12r */
  39798         soc_block_list[78],
  39799         soc_genreg,
  39800         1,
  39801         0,
  39802         0x80036,
  39803         0,
  39804         0,
  39805         1,
  39806         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39807         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39808         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39809         -1,
  39810         -1,
  39811     },
  39812 #endif /* chips */
  39813 
  39814 #if defined(BCM_88732_A0)
  39815     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_13r */
  39816         soc_block_list[78],
  39817         soc_genreg,
  39818         1,
  39819         0,
  39820         0x80037,
  39821         0,
  39822         0,
  39823         1,
  39824         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39825         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39826         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39827         -1,
  39828         -1,
  39829     },
  39830 #endif /* chips */
  39831 
  39832 #if defined(BCM_88732_A0)
  39833     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_14r */
  39834         soc_block_list[78],
  39835         soc_genreg,
  39836         1,
  39837         0,
  39838         0x80038,
  39839         0,
  39840         0,
  39841         1,
  39842         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39843         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39844         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39845         -1,
  39846         -1,
  39847     },
  39848 #endif /* chips */
  39849 
  39850 #if defined(BCM_88732_A0)
  39851     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_15r */
  39852         soc_block_list[78],
  39853         soc_genreg,
  39854         1,
  39855         0,
  39856         0x80039,
  39857         0,
  39858         0,
  39859         1,
  39860         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39861         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39862         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39863         -1,
  39864         -1,
  39865     },
  39866 #endif /* chips */
  39867 
  39868 #if defined(BCM_88732_A0)
  39869     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_16r */
  39870         soc_block_list[78],
  39871         soc_genreg,
  39872         1,
  39873         0,
  39874         0x8003a,
  39875         0,
  39876         0,
  39877         1,
  39878         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39879         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39880         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39881         -1,
  39882         -1,
  39883     },
  39884 #endif /* chips */
  39885 
  39886 #if defined(BCM_88732_A0)
  39887     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_17r */
  39888         soc_block_list[78],
  39889         soc_genreg,
  39890         1,
  39891         0,
  39892         0x8003b,
  39893         0,
  39894         0,
  39895         1,
  39896         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39897         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39898         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39899         -1,
  39900         -1,
  39901     },
  39902 #endif /* chips */
  39903 
  39904 #if defined(BCM_88732_A0)
  39905     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_18r */
  39906         soc_block_list[78],
  39907         soc_genreg,
  39908         1,
  39909         0,
  39910         0x8003c,
  39911         0,
  39912         0,
  39913         1,
  39914         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39915         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39916         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39917         -1,
  39918         -1,
  39919     },
  39920 #endif /* chips */
  39921 
  39922 #if defined(BCM_88732_A0)
  39923     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_19r */
  39924         soc_block_list[78],
  39925         soc_genreg,
  39926         1,
  39927         0,
  39928         0x8003d,
  39929         0,
  39930         0,
  39931         1,
  39932         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39933         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39934         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39935         -1,
  39936         -1,
  39937     },
  39938 #endif /* chips */
  39939 
  39940 #if defined(BCM_88732_A0)
  39941     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_20r */
  39942         soc_block_list[78],
  39943         soc_genreg,
  39944         1,
  39945         0,
  39946         0x8003e,
  39947         0,
  39948         0,
  39949         1,
  39950         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39951         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39952         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39953         -1,
  39954         -1,
  39955     },
  39956 #endif /* chips */
  39957 
  39958 #if defined(BCM_88732_A0)
  39959     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_21r */
  39960         soc_block_list[78],
  39961         soc_genreg,
  39962         1,
  39963         0,
  39964         0x8003f,
  39965         0,
  39966         0,
  39967         1,
  39968         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39969         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39970         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39971         -1,
  39972         -1,
  39973     },
  39974 #endif /* chips */
  39975 
  39976 #if defined(BCM_88732_A0)
  39977     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_22r */
  39978         soc_block_list[78],
  39979         soc_genreg,
  39980         1,
  39981         0,
  39982         0x80040,
  39983         0,
  39984         0,
  39985         1,
  39986         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  39987         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  39988         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39989         -1,
  39990         -1,
  39991     },
  39992 #endif /* chips */
  39993 
  39994 #if defined(BCM_88732_A0)
  39995     { /* SOC_REG_INT_LINK_STATUS_DEBOUNCE_TIMEOUT_23r */
  39996         soc_block_list[78],
  39997         soc_genreg,
  39998         1,
  39999         0,
  40000         0x80041,
  40001         0,
  40002         0,
  40003         1,
  40004         soc_LINK_STATUS_DEBOUNCE_TIMEOUT_0r_fields,
  40005         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  40006         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40007         -1,
  40008         -1,
  40009     },
  40010 #endif /* chips */
  40011 
  40012 #if defined(BCM_88732_A0)
  40013     { /* SOC_REG_INT_LINK_STATUS_GLITCH_DETECTr */
  40014         soc_block_list[78],
  40015         soc_genreg,
  40016         1,
  40017         0,
  40018         0x80028,
  40019         0,
  40020         0,
  40021         1,
  40022         soc_LINK_STATUS_GLITCH_DETECTr_fields,
  40023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40024         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40025         -1,
  40026         -1,
  40027     },
  40028 #endif /* chips */
  40029 
  40030 #if defined(BCM_53570_A0)
  40031     { /* SOC_REG_INT_LINK_STATUS_HIr */
  40032         soc_block_list[5],
  40033         soc_genreg,
  40034         1,
  40035         0,
  40036         0x42006200,
  40037         SOC_REG_FLAG_64_BITS,
  40038         0,
  40039         3,
  40040         soc_LINK_STATUS_HIr_fields,
  40041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40042         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40043         -1,
  40044         -1,
  40045     },
  40046 #endif /* chips */
  40047 
  40048 #if defined(BCM_53570_B0)
  40049     { /* SOC_REG_INT_LINK_STATUS_HI_BCM53570_B0r */
  40050         soc_block_list[5],
  40051         soc_genreg,
  40052         1,
  40053         0,
  40054         0x42006600,
  40055         SOC_REG_FLAG_64_BITS,
  40056         0,
  40057         3,
  40058         soc_LINK_STATUS_HIr_fields,
  40059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40060         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40061         -1,
  40062         -1,
  40063     },
  40064 #endif /* chips */
  40065 
  40066 #if defined(BCM_53570_A0)
  40067     { /* SOC_REG_INT_LINK_STATUS_LOr */
  40068         soc_block_list[5],
  40069         soc_genreg,
  40070         1,
  40071         0,
  40072         0x42006100,
  40073         SOC_REG_FLAG_64_BITS,
  40074         0,
  40075         4,
  40076         soc_LINK_STATUS_LOr_fields,
  40077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40078         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40079         -1,
  40080         -1,
  40081     },
  40082 #endif /* chips */
  40083 
  40084 #if defined(BCM_53570_B0)
  40085     { /* SOC_REG_INT_LINK_STATUS_LO_BCM53570_B0r */
  40086         soc_block_list[5],
  40087         soc_genreg,
  40088         1,
  40089         0,
  40090         0x42006500,
  40091         SOC_REG_FLAG_64_BITS,
  40092         0,
  40093         4,
  40094         soc_LINK_STATUS_LOr_fields,
  40095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40096         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40097         -1,
  40098         -1,
  40099     },
  40100 #endif /* chips */
  40101 
  40102 #if defined(BCM_88732_A0)
  40103     { /* SOC_REG_INT_LINK_STATUS_TIMERr */
  40104         soc_block_list[78],
  40105         soc_genreg,
  40106         1,
  40107         0,
  40108         0x80029,
  40109         0,
  40110         0,
  40111         1,
  40112         soc_LINK_STATUS_TIMERr_fields,
  40113         SOC_RESET_VAL_DEC(0x000596dc, 0x00000000)
  40114         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  40115         -1,
  40116         -1,
  40117     },
  40118 #endif /* chips */
  40119 
  40120 #if defined(BCM_56440_A0)
  40121     { /* SOC_REG_INT_LLS_ACTIVATION_EVENT_SEENr */
  40122         soc_block_list[85],
  40123         soc_genreg,
  40124         1,
  40125         0,
  40126         0x80038,
  40127         0,
  40128         0,
  40129         19,
  40130         soc_LLS_ACTIVATION_EVENT_SEENr_fields,
  40131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40132         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  40133         -1,
  40134         -1,
  40135     },
  40136 #endif /* chips */
  40137 
  40138 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  40139     { /* SOC_REG_INT_LLS_ACTIVATION_EVENT_SEEN_BCM56260_A0r */
  40140         soc_block_list[85],
  40141         soc_genreg,
  40142         1,
  40143         0,
  40144         0x2008d00,
  40145         0,
  40146         0,
  40147         19,
  40148         soc_LLS_ACTIVATION_EVENT_SEEN_BCM56260_A0r_fields,
  40149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40150         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  40151         -1,
  40152         -1,
  40153     },
  40154 #endif /* chips */
  40155 
  40156 #if defined(BCM_56270_A0)
  40157     { /* SOC_REG_INT_LLS_ACTIVATION_EVENT_SEEN_BCM56270_A0r */
  40158         soc_block_list[85],
  40159         soc_genreg,
  40160         1,
  40161         0,
  40162         0x2007400,
  40163         0,
  40164         0,
  40165         19,
  40166         soc_LLS_ACTIVATION_EVENT_SEEN_BCM56260_A0r_fields,
  40167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40168         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  40169         -1,
  40170         -1,
  40171     },
  40172 #endif /* chips */
  40173 
  40174 #if defined(BCM_56440_B0)
  40175     { /* SOC_REG_INT_LLS_ACTIVATION_EVENT_SEEN_BCM56440_B0r */
  40176         soc_block_list[85],
  40177         soc_genreg,
  40178         1,
  40179         0,
  40180         0x80040,
  40181         0,
  40182         0,
  40183         19,
  40184         soc_LLS_ACTIVATION_EVENT_SEENr_fields,
  40185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40186         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  40187         -1,
  40188         -1,
  40189     },
  40190 #endif /* chips */
  40191 
  40192 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40193     defined(BCM_56450_B1)
  40194     { /* SOC_REG_INT_LLS_ACTIVATION_EVENT_SEEN_BCM56450_A0r */
  40195         soc_block_list[85],
  40196         soc_genreg,
  40197         1,
  40198         0,
  40199         0x2010c00,
  40200         0,
  40201         0,
  40202         19,
  40203         soc_LLS_ACTIVATION_EVENT_SEEN_BCM56450_A0r_fields,
  40204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40205         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  40206         -1,
  40207         -1,
  40208     },
  40209 #endif /* chips */
  40210 
  40211 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  40212     { /* SOC_REG_INT_LLS_ACTIVATION_EVENT_SEEN_BCM56560_A0r */
  40213         soc_block_list[4],
  40214         soc_genreg,
  40215         1,
  40216         0,
  40217         0x62003c00,
  40218         0,
  40219         0,
  40220         21,
  40221         soc_LLS_ACTIVATION_EVENT_SEEN_BCM56560_A0r_fields,
  40222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40223         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  40224         -1,
  40225         -1,
  40226     },
  40227 #endif /* chips */
  40228 
  40229 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40230     { /* SOC_REG_INT_LLS_ACTIVATION_EVENT_SEEN_BCM56640_A0r */
  40231         soc_block_list[4],
  40232         soc_genreg,
  40233         1,
  40234         0,
  40235         0x5a00a600,
  40236         0,
  40237         0,
  40238         19,
  40239         soc_LLS_ACTIVATION_EVENT_SEEN_BCM56640_A0r_fields,
  40240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40241         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40242         -1,
  40243         -1,
  40244     },
  40245 #endif /* chips */
  40246 
  40247 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  40248     { /* SOC_REG_INT_LLS_ACT_ECC_DEBUGr */
  40249         soc_block_list[4],
  40250         soc_genreg,
  40251         1,
  40252         0,
  40253         0x62007900,
  40254         0,
  40255         0,
  40256         14,
  40257         soc_LLS_ACT_ECC_DEBUGr_fields,
  40258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40259         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  40260         -1,
  40261         -1,
  40262     },
  40263 #endif /* chips */
  40264 
  40265 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40266     { /* SOC_REG_INT_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_32_37r */
  40267         soc_block_list[4],
  40268         soc_genreg,
  40269         1,
  40270         0,
  40271         0x5a00a800,
  40272         0,
  40273         0,
  40274         6,
  40275         soc_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_32_37r_fields,
  40276         SOC_RESET_VAL_DEC(0x0e739ce7, 0x00000000)
  40277         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  40278         -1,
  40279         -1,
  40280     },
  40281 #endif /* chips */
  40282 
  40283 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40284     { /* SOC_REG_INT_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_38_43r */
  40285         soc_block_list[4],
  40286         soc_genreg,
  40287         1,
  40288         0,
  40289         0x5a00a900,
  40290         0,
  40291         0,
  40292         6,
  40293         soc_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_38_43r_fields,
  40294         SOC_RESET_VAL_DEC(0x0e739ce7, 0x00000000)
  40295         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  40296         -1,
  40297         -1,
  40298     },
  40299 #endif /* chips */
  40300 
  40301 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40302     { /* SOC_REG_INT_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_44_49r */
  40303         soc_block_list[4],
  40304         soc_genreg,
  40305         1,
  40306         0,
  40307         0x5a00aa00,
  40308         0,
  40309         0,
  40310         6,
  40311         soc_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_44_49r_fields,
  40312         SOC_RESET_VAL_DEC(0x0e739ce7, 0x00000000)
  40313         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  40314         -1,
  40315         -1,
  40316     },
  40317 #endif /* chips */
  40318 
  40319 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40320     { /* SOC_REG_INT_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_50_55r */
  40321         soc_block_list[4],
  40322         soc_genreg,
  40323         1,
  40324         0,
  40325         0x5a00ab00,
  40326         0,
  40327         0,
  40328         6,
  40329         soc_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_50_55r_fields,
  40330         SOC_RESET_VAL_DEC(0x0e739ce7, 0x00000000)
  40331         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  40332         -1,
  40333         -1,
  40334     },
  40335 #endif /* chips */
  40336 
  40337 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40338     { /* SOC_REG_INT_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_15_8r */
  40339         soc_block_list[4],
  40340         soc_genreg,
  40341         1,
  40342         0,
  40343         0x5a000f00,
  40344         0,
  40345         0,
  40346         8,
  40347         soc_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_15_8r_fields,
  40348         SOC_RESET_VAL_DEC(0x11111111, 0x00000000)
  40349         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40350         -1,
  40351         -1,
  40352     },
  40353 #endif /* chips */
  40354 
  40355 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40356     { /* SOC_REG_INT_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_23_16r */
  40357         soc_block_list[4],
  40358         soc_genreg,
  40359         1,
  40360         0,
  40361         0x5a001000,
  40362         0,
  40363         0,
  40364         8,
  40365         soc_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_23_16r_fields,
  40366         SOC_RESET_VAL_DEC(0x11111111, 0x00000000)
  40367         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40368         -1,
  40369         -1,
  40370     },
  40371 #endif /* chips */
  40372 
  40373 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40374     { /* SOC_REG_INT_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_31_24r */
  40375         soc_block_list[4],
  40376         soc_genreg,
  40377         1,
  40378         0,
  40379         0x5a001100,
  40380         0,
  40381         0,
  40382         8,
  40383         soc_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_31_24r_fields,
  40384         SOC_RESET_VAL_DEC(0x11111111, 0x00000000)
  40385         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40386         -1,
  40387         -1,
  40388     },
  40389 #endif /* chips */
  40390 
  40391 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40392     { /* SOC_REG_INT_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_39_32r */
  40393         soc_block_list[4],
  40394         soc_genreg,
  40395         1,
  40396         0,
  40397         0x5a001200,
  40398         0,
  40399         0,
  40400         8,
  40401         soc_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_39_32r_fields,
  40402         SOC_RESET_VAL_DEC(0x11111111, 0x00000000)
  40403         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40404         -1,
  40405         -1,
  40406     },
  40407 #endif /* chips */
  40408 
  40409 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40410     { /* SOC_REG_INT_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_47_40r */
  40411         soc_block_list[4],
  40412         soc_genreg,
  40413         1,
  40414         0,
  40415         0x5a001300,
  40416         0,
  40417         0,
  40418         8,
  40419         soc_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_47_40r_fields,
  40420         SOC_RESET_VAL_DEC(0x11111111, 0x00000000)
  40421         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40422         -1,
  40423         -1,
  40424     },
  40425 #endif /* chips */
  40426 
  40427 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40428     { /* SOC_REG_INT_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_55_48r */
  40429         soc_block_list[4],
  40430         soc_genreg,
  40431         1,
  40432         0,
  40433         0x5a001400,
  40434         0,
  40435         0,
  40436         8,
  40437         soc_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_55_48r_fields,
  40438         SOC_RESET_VAL_DEC(0x11111111, 0x00000000)
  40439         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40440         -1,
  40441         -1,
  40442     },
  40443 #endif /* chips */
  40444 
  40445 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40446     { /* SOC_REG_INT_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_63_56r */
  40447         soc_block_list[4],
  40448         soc_genreg,
  40449         1,
  40450         0,
  40451         0x5a001500,
  40452         0,
  40453         0,
  40454         8,
  40455         soc_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_63_56r_fields,
  40456         SOC_RESET_VAL_DEC(0x11111111, 0x00000000)
  40457         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40458         -1,
  40459         -1,
  40460     },
  40461 #endif /* chips */
  40462 
  40463 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40464     { /* SOC_REG_INT_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_7_0r */
  40465         soc_block_list[4],
  40466         soc_genreg,
  40467         1,
  40468         0,
  40469         0x5a000e00,
  40470         0,
  40471         0,
  40472         8,
  40473         soc_LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_7_0r_fields,
  40474         SOC_RESET_VAL_DEC(0x11111111, 0x00000000)
  40475         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40476         -1,
  40477         -1,
  40478     },
  40479 #endif /* chips */
  40480 
  40481 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40482     { /* SOC_REG_INT_LLS_AXP_PORT_56_CFG_WEIGHTr */
  40483         soc_block_list[4],
  40484         soc_genreg,
  40485         1,
  40486         0,
  40487         0x5a00a100,
  40488         0,
  40489         0,
  40490         1,
  40491         soc_LLS_AXP_PORT_56_CFG_WEIGHTr_fields,
  40492         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  40493         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  40494         -1,
  40495         -1,
  40496     },
  40497 #endif /* chips */
  40498 
  40499 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40500     { /* SOC_REG_INT_LLS_AXP_PORT_57_CFG_WEIGHTr */
  40501         soc_block_list[4],
  40502         soc_genreg,
  40503         1,
  40504         0,
  40505         0x5a00a200,
  40506         0,
  40507         0,
  40508         1,
  40509         soc_LLS_AXP_PORT_56_CFG_WEIGHTr_fields,
  40510         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  40511         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  40512         -1,
  40513         -1,
  40514     },
  40515 #endif /* chips */
  40516 
  40517 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40518     { /* SOC_REG_INT_LLS_AXP_PORT_58_CFG_WEIGHTr */
  40519         soc_block_list[4],
  40520         soc_genreg,
  40521         1,
  40522         0,
  40523         0x5a00a300,
  40524         0,
  40525         0,
  40526         1,
  40527         soc_LLS_AXP_PORT_56_CFG_WEIGHTr_fields,
  40528         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  40529         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  40530         -1,
  40531         -1,
  40532     },
  40533 #endif /* chips */
  40534 
  40535 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40536     { /* SOC_REG_INT_LLS_AXP_PORT_61_CFG_WEIGHTr */
  40537         soc_block_list[4],
  40538         soc_genreg,
  40539         1,
  40540         0,
  40541         0x5a00a400,
  40542         0,
  40543         0,
  40544         1,
  40545         soc_LLS_AXP_PORT_56_CFG_WEIGHTr_fields,
  40546         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  40547         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  40548         -1,
  40549         -1,
  40550     },
  40551 #endif /* chips */
  40552 
  40553 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  40554     { /* SOC_REG_INT_LLS_AXP_PORT_62_CFG_WEIGHTr */
  40555         soc_block_list[4],
  40556         soc_genreg,
  40557         1,
  40558         0,
  40559         0x5a00a500,
  40560         0,
  40561         0,
  40562         1,
  40563         soc_LLS_AXP_PORT_56_CFG_WEIGHTr_fields,
  40564         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  40565         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  40566         -1,
  40567         -1,
  40568     },
  40569 #endif /* chips */
  40570 
  40571 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  40572     { /* SOC_REG_INT_LLS_CAPT_ENQUEUE_VIOL_IDr */
  40573         soc_block_list[85],
  40574         soc_genreg,
  40575         1,
  40576         0,
  40577         0x8001b,
  40578         0,
  40579         0,
  40580         1,
  40581         soc_LLS_CAPT_ENQUEUE_VIOL_IDr_fields,
  40582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40583         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  40584         -1,
  40585         -1,
  40586     },
  40587 #endif /* chips */
  40588 
  40589 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  40590     { /* SOC_REG_INT_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56260_A0r */
  40591         soc_block_list[85],
  40592         soc_genreg,
  40593         1,
  40594         0,
  40595         0x2002800,
  40596         0,
  40597         0,
  40598         1,
  40599         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  40600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40601         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  40602         -1,
  40603         -1,
  40604     },
  40605 #endif /* chips */
  40606 
  40607 #if defined(BCM_56270_A0)
  40608     { /* SOC_REG_INT_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56270_A0r */
  40609         soc_block_list[85],
  40610         soc_genreg,
  40611         1,
  40612         0,
  40613         0x2002800,
  40614         0,
  40615         0,
  40616         1,
  40617         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  40618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40619         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  40620         -1,
  40621         -1,
  40622     },
  40623 #endif /* chips */
  40624 
  40625 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40626     defined(BCM_56450_B1)
  40627     { /* SOC_REG_INT_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56450_A0r */
  40628         soc_block_list[85],
  40629         soc_genreg,
  40630         1,
  40631         0,
  40632         0x2002700,
  40633         0,
  40634         0,
  40635         1,
  40636         soc_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56450_A0r_fields,
  40637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40638         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  40639         -1,
  40640         -1,
  40641     },
  40642 #endif /* chips */
  40643 
  40644 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  40645     { /* SOC_REG_INT_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56560_A0r */
  40646         soc_block_list[4],
  40647         soc_genreg,
  40648         1,
  40649         0,
  40650         0x62002000,
  40651         0,
  40652         0,
  40653         1,
  40654         soc_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56560_A0r_fields,
  40655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40656         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  40657         -1,
  40658         -1,
  40659     },
  40660 #endif /* chips */
  40661 
  40662 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  40663     { /* SOC_REG_INT_LLS_CAPT_LIST_HEAD_MISMATCH_IDr */
  40664         soc_block_list[4],
  40665         soc_genreg,
  40666         1,
  40667         0,
  40668         0x62002a00,
  40669         0,
  40670         0,
  40671         1,
  40672         soc_LLS_CAPT_LIST_HEAD_MISMATCH_IDr_fields,
  40673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40674         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  40675         -1,
  40676         -1,
  40677     },
  40678 #endif /* chips */
  40679 
  40680 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  40681     { /* SOC_REG_INT_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r */
  40682         soc_block_list[85],
  40683         soc_genreg,
  40684         1,
  40685         0,
  40686         0x2004e00,
  40687         0,
  40688         0,
  40689         1,
  40690         soc_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r_fields,
  40691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40692         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40693         -1,
  40694         -1,
  40695     },
  40696 #endif /* chips */
  40697 
  40698 #if defined(BCM_56270_A0)
  40699     { /* SOC_REG_INT_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56270_A0r */
  40700         soc_block_list[85],
  40701         soc_genreg,
  40702         1,
  40703         0,
  40704         0x2004a00,
  40705         0,
  40706         0,
  40707         1,
  40708         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  40709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40710         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  40711         -1,
  40712         -1,
  40713     },
  40714 #endif /* chips */
  40715 
  40716 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  40717     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_IDr */
  40718         soc_block_list[85],
  40719         soc_genreg,
  40720         1,
  40721         0,
  40722         0x8001e,
  40723         0,
  40724         0,
  40725         1,
  40726         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_IDr_fields,
  40727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40728         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40729         -1,
  40730         -1,
  40731     },
  40732 #endif /* chips */
  40733 
  40734 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  40735     defined(BCM_56270_A0)
  40736     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56260_A0r */
  40737         soc_block_list[85],
  40738         soc_genreg,
  40739         1,
  40740         0,
  40741         0x2002d00,
  40742         0,
  40743         0,
  40744         1,
  40745         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  40746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40747         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  40748         -1,
  40749         -1,
  40750     },
  40751 #endif /* chips */
  40752 
  40753 #if defined(BCM_56270_A0)
  40754     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56270_A0r */
  40755         soc_block_list[85],
  40756         soc_genreg,
  40757         1,
  40758         0,
  40759         0x2002c00,
  40760         0,
  40761         0,
  40762         1,
  40763         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r_fields,
  40764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40765         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  40766         -1,
  40767         -1,
  40768     },
  40769 #endif /* chips */
  40770 
  40771 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40772     defined(BCM_56450_B1)
  40773     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56450_A0r */
  40774         soc_block_list[85],
  40775         soc_genreg,
  40776         1,
  40777         0,
  40778         0x2002c00,
  40779         0,
  40780         0,
  40781         1,
  40782         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56450_A0r_fields,
  40783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40784         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  40785         -1,
  40786         -1,
  40787     },
  40788 #endif /* chips */
  40789 
  40790 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  40791     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L0_UNDERFLOW_IDr */
  40792         soc_block_list[85],
  40793         soc_genreg,
  40794         1,
  40795         0,
  40796         0x80027,
  40797         0,
  40798         0,
  40799         1,
  40800         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_IDr_fields,
  40801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40802         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40803         -1,
  40804         -1,
  40805     },
  40806 #endif /* chips */
  40807 
  40808 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  40809     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L0_UNDERFLOW_ID_BCM56260_A0r */
  40810         soc_block_list[85],
  40811         soc_genreg,
  40812         1,
  40813         0,
  40814         0x2003600,
  40815         0,
  40816         0,
  40817         1,
  40818         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  40819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40820         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  40821         -1,
  40822         -1,
  40823     },
  40824 #endif /* chips */
  40825 
  40826 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40827     defined(BCM_56450_B1)
  40828     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L0_UNDERFLOW_ID_BCM56450_A0r */
  40829         soc_block_list[85],
  40830         soc_genreg,
  40831         1,
  40832         0,
  40833         0x2003700,
  40834         0,
  40835         0,
  40836         1,
  40837         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56450_A0r_fields,
  40838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40839         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  40840         -1,
  40841         -1,
  40842     },
  40843 #endif /* chips */
  40844 
  40845 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  40846     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_IDr */
  40847         soc_block_list[85],
  40848         soc_genreg,
  40849         1,
  40850         0,
  40851         0x8001f,
  40852         0,
  40853         0,
  40854         1,
  40855         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_IDr_fields,
  40856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40857         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  40858         -1,
  40859         -1,
  40860     },
  40861 #endif /* chips */
  40862 
  40863 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  40864     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56260_A0r */
  40865         soc_block_list[85],
  40866         soc_genreg,
  40867         1,
  40868         0,
  40869         0x2002e00,
  40870         0,
  40871         0,
  40872         1,
  40873         soc_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r_fields,
  40874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40875         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40876         -1,
  40877         -1,
  40878     },
  40879 #endif /* chips */
  40880 
  40881 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40882     defined(BCM_56450_B1)
  40883     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56450_A0r */
  40884         soc_block_list[85],
  40885         soc_genreg,
  40886         1,
  40887         0,
  40888         0x2002d00,
  40889         0,
  40890         0,
  40891         1,
  40892         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56450_A0r_fields,
  40893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40894         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  40895         -1,
  40896         -1,
  40897     },
  40898 #endif /* chips */
  40899 
  40900 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  40901     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L1_UNDERFLOW_IDr */
  40902         soc_block_list[85],
  40903         soc_genreg,
  40904         1,
  40905         0,
  40906         0x80028,
  40907         0,
  40908         0,
  40909         1,
  40910         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_IDr_fields,
  40911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40912         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  40913         -1,
  40914         -1,
  40915     },
  40916 #endif /* chips */
  40917 
  40918 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  40919     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L1_UNDERFLOW_ID_BCM56260_A0r */
  40920         soc_block_list[85],
  40921         soc_genreg,
  40922         1,
  40923         0,
  40924         0x2003700,
  40925         0,
  40926         0,
  40927         1,
  40928         soc_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r_fields,
  40929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40930         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40931         -1,
  40932         -1,
  40933     },
  40934 #endif /* chips */
  40935 
  40936 #if defined(BCM_56270_A0)
  40937     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L1_UNDERFLOW_ID_BCM56270_A0r */
  40938         soc_block_list[85],
  40939         soc_genreg,
  40940         1,
  40941         0,
  40942         0x2003500,
  40943         0,
  40944         0,
  40945         1,
  40946         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  40947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40948         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  40949         -1,
  40950         -1,
  40951     },
  40952 #endif /* chips */
  40953 
  40954 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40955     defined(BCM_56450_B1)
  40956     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L1_UNDERFLOW_ID_BCM56450_A0r */
  40957         soc_block_list[85],
  40958         soc_genreg,
  40959         1,
  40960         0,
  40961         0x2003800,
  40962         0,
  40963         0,
  40964         1,
  40965         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56450_A0r_fields,
  40966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40967         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  40968         -1,
  40969         -1,
  40970     },
  40971 #endif /* chips */
  40972 
  40973 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  40974     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr */
  40975         soc_block_list[85],
  40976         soc_genreg,
  40977         1,
  40978         0,
  40979         0x80021,
  40980         0,
  40981         0,
  40982         1,
  40983         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr_fields,
  40984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40985         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  40986         -1,
  40987         -1,
  40988     },
  40989 #endif /* chips */
  40990 
  40991 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40992     defined(BCM_56450_B1)
  40993     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r */
  40994         soc_block_list[85],
  40995         soc_genreg,
  40996         1,
  40997         0,
  40998         0x2002f00,
  40999         0,
  41000         0,
  41001         1,
  41002         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r_fields,
  41003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41004         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41005         -1,
  41006         -1,
  41007     },
  41008 #endif /* chips */
  41009 
  41010 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41011     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_UNDERFLOW_IDr */
  41012         soc_block_list[85],
  41013         soc_genreg,
  41014         1,
  41015         0,
  41016         0x8002a,
  41017         0,
  41018         0,
  41019         1,
  41020         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr_fields,
  41021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41022         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41023         -1,
  41024         -1,
  41025     },
  41026 #endif /* chips */
  41027 
  41028 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41029     defined(BCM_56450_B1)
  41030     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_UNDERFLOW_ID_BCM56450_A0r */
  41031         soc_block_list[85],
  41032         soc_genreg,
  41033         1,
  41034         0,
  41035         0x2003a00,
  41036         0,
  41037         0,
  41038         1,
  41039         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r_fields,
  41040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41041         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41042         -1,
  41043         -1,
  41044     },
  41045 #endif /* chips */
  41046 
  41047 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41048     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_OVERFLOW_IDr */
  41049         soc_block_list[85],
  41050         soc_genreg,
  41051         1,
  41052         0,
  41053         0x2002f00,
  41054         0,
  41055         0,
  41056         1,
  41057         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  41058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41059         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  41060         -1,
  41061         -1,
  41062     },
  41063 #endif /* chips */
  41064 
  41065 #if defined(BCM_56270_A0)
  41066     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_OVERFLOW_ID_BCM56270_A0r */
  41067         soc_block_list[85],
  41068         soc_genreg,
  41069         1,
  41070         0,
  41071         0x2002e00,
  41072         0,
  41073         0,
  41074         1,
  41075         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  41076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41077         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  41078         -1,
  41079         -1,
  41080     },
  41081 #endif /* chips */
  41082 
  41083 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41084     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_UNDERFLOW_IDr */
  41085         soc_block_list[85],
  41086         soc_genreg,
  41087         1,
  41088         0,
  41089         0x2003800,
  41090         0,
  41091         0,
  41092         1,
  41093         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  41094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41095         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  41096         -1,
  41097         -1,
  41098     },
  41099 #endif /* chips */
  41100 
  41101 #if defined(BCM_56270_A0)
  41102     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_UNDERFLOW_ID_BCM56270_A0r */
  41103         soc_block_list[85],
  41104         soc_genreg,
  41105         1,
  41106         0,
  41107         0x2003600,
  41108         0,
  41109         0,
  41110         1,
  41111         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  41112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41113         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  41114         -1,
  41115         -1,
  41116     },
  41117 #endif /* chips */
  41118 
  41119 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41120     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_UPPER_OVERFLOW_IDr */
  41121         soc_block_list[85],
  41122         soc_genreg,
  41123         1,
  41124         0,
  41125         0x80020,
  41126         0,
  41127         0,
  41128         1,
  41129         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr_fields,
  41130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41131         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41132         -1,
  41133         -1,
  41134     },
  41135 #endif /* chips */
  41136 
  41137 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41138     defined(BCM_56450_B1)
  41139     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_UPPER_OVERFLOW_ID_BCM56450_A0r */
  41140         soc_block_list[85],
  41141         soc_genreg,
  41142         1,
  41143         0,
  41144         0x2002e00,
  41145         0,
  41146         0,
  41147         1,
  41148         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r_fields,
  41149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41150         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41151         -1,
  41152         -1,
  41153     },
  41154 #endif /* chips */
  41155 
  41156 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41157     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_UPPER_UNDERFLOW_IDr */
  41158         soc_block_list[85],
  41159         soc_genreg,
  41160         1,
  41161         0,
  41162         0x80029,
  41163         0,
  41164         0,
  41165         1,
  41166         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr_fields,
  41167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41168         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41169         -1,
  41170         -1,
  41171     },
  41172 #endif /* chips */
  41173 
  41174 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41175     defined(BCM_56450_B1)
  41176     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_L2_UPPER_UNDERFLOW_ID_BCM56450_A0r */
  41177         soc_block_list[85],
  41178         soc_genreg,
  41179         1,
  41180         0,
  41181         0x2003900,
  41182         0,
  41183         0,
  41184         1,
  41185         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r_fields,
  41186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41187         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41188         -1,
  41189         -1,
  41190     },
  41191 #endif /* chips */
  41192 
  41193 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41194     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_IDr */
  41195         soc_block_list[85],
  41196         soc_genreg,
  41197         1,
  41198         0,
  41199         0x8001d,
  41200         0,
  41201         0,
  41202         1,
  41203         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_IDr_fields,
  41204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41205         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  41206         -1,
  41207         -1,
  41208     },
  41209 #endif /* chips */
  41210 
  41211 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41212     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r */
  41213         soc_block_list[85],
  41214         soc_genreg,
  41215         1,
  41216         0,
  41217         0x2002c00,
  41218         0,
  41219         0,
  41220         1,
  41221         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  41222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41223         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  41224         -1,
  41225         -1,
  41226     },
  41227 #endif /* chips */
  41228 
  41229 #if defined(BCM_56270_A0)
  41230     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56270_A0r */
  41231         soc_block_list[85],
  41232         soc_genreg,
  41233         1,
  41234         0,
  41235         0x2002b00,
  41236         0,
  41237         0,
  41238         1,
  41239         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID_BCM56260_A0r_fields,
  41240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41241         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41242         -1,
  41243         -1,
  41244     },
  41245 #endif /* chips */
  41246 
  41247 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41248     defined(BCM_56450_B1)
  41249     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56450_A0r */
  41250         soc_block_list[85],
  41251         soc_genreg,
  41252         1,
  41253         0,
  41254         0x2002b00,
  41255         0,
  41256         0,
  41257         1,
  41258         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56450_A0r_fields,
  41259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41260         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  41261         -1,
  41262         -1,
  41263     },
  41264 #endif /* chips */
  41265 
  41266 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41267     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_UNDERFLOW_IDr */
  41268         soc_block_list[85],
  41269         soc_genreg,
  41270         1,
  41271         0,
  41272         0x80026,
  41273         0,
  41274         0,
  41275         1,
  41276         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_IDr_fields,
  41277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41278         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  41279         -1,
  41280         -1,
  41281     },
  41282 #endif /* chips */
  41283 
  41284 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41285     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_UNDERFLOW_ID_BCM56260_A0r */
  41286         soc_block_list[85],
  41287         soc_genreg,
  41288         1,
  41289         0,
  41290         0x2003500,
  41291         0,
  41292         0,
  41293         1,
  41294         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  41295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41296         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  41297         -1,
  41298         -1,
  41299     },
  41300 #endif /* chips */
  41301 
  41302 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41303     defined(BCM_56450_B1)
  41304     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_UNDERFLOW_ID_BCM56450_A0r */
  41305         soc_block_list[85],
  41306         soc_genreg,
  41307         1,
  41308         0,
  41309         0x2003600,
  41310         0,
  41311         0,
  41312         1,
  41313         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56450_A0r_fields,
  41314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41315         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  41316         -1,
  41317         -1,
  41318     },
  41319 #endif /* chips */
  41320 
  41321 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41322     defined(BCM_56450_B1)
  41323     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_IDr */
  41324         soc_block_list[85],
  41325         soc_genreg,
  41326         1,
  41327         0,
  41328         0x2002a00,
  41329         0,
  41330         0,
  41331         1,
  41332         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_IDr_fields,
  41333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41334         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  41335         -1,
  41336         -1,
  41337     },
  41338 #endif /* chips */
  41339 
  41340 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41341     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID_BCM56260_A0r */
  41342         soc_block_list[85],
  41343         soc_genreg,
  41344         1,
  41345         0,
  41346         0x2002a00,
  41347         0,
  41348         0,
  41349         1,
  41350         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID_BCM56260_A0r_fields,
  41351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41352         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41353         -1,
  41354         -1,
  41355     },
  41356 #endif /* chips */
  41357 
  41358 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41359     defined(BCM_56450_B1)
  41360     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S0_UNDERFLOW_IDr */
  41361         soc_block_list[85],
  41362         soc_genreg,
  41363         1,
  41364         0,
  41365         0x2003500,
  41366         0,
  41367         0,
  41368         1,
  41369         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_IDr_fields,
  41370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41371         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  41372         -1,
  41373         -1,
  41374     },
  41375 #endif /* chips */
  41376 
  41377 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  41378     defined(BCM_56270_A0)
  41379     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S0_UNDERFLOW_ID_BCM56260_A0r */
  41380         soc_block_list[85],
  41381         soc_genreg,
  41382         1,
  41383         0,
  41384         0x2003300,
  41385         0,
  41386         0,
  41387         1,
  41388         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID_BCM56260_A0r_fields,
  41389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41390         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41391         -1,
  41392         -1,
  41393     },
  41394 #endif /* chips */
  41395 
  41396 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41397     defined(BCM_56450_B1)
  41398     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_IDr */
  41399         soc_block_list[85],
  41400         soc_genreg,
  41401         1,
  41402         0,
  41403         0x2002900,
  41404         0,
  41405         0,
  41406         1,
  41407         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_IDr_fields,
  41408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41409         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41410         -1,
  41411         -1,
  41412     },
  41413 #endif /* chips */
  41414 
  41415 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41416     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r */
  41417         soc_block_list[85],
  41418         soc_genreg,
  41419         1,
  41420         0,
  41421         0x2002b00,
  41422         0,
  41423         0,
  41424         1,
  41425         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r_fields,
  41426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41427         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  41428         -1,
  41429         -1,
  41430     },
  41431 #endif /* chips */
  41432 
  41433 #if defined(BCM_56270_A0)
  41434     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56270_A0r */
  41435         soc_block_list[85],
  41436         soc_genreg,
  41437         1,
  41438         0,
  41439         0x2002a00,
  41440         0,
  41441         0,
  41442         1,
  41443         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  41444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41445         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  41446         -1,
  41447         -1,
  41448     },
  41449 #endif /* chips */
  41450 
  41451 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41452     defined(BCM_56450_B1)
  41453     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S1_UNDERFLOW_IDr */
  41454         soc_block_list[85],
  41455         soc_genreg,
  41456         1,
  41457         0,
  41458         0x2003400,
  41459         0,
  41460         0,
  41461         1,
  41462         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_IDr_fields,
  41463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41464         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41465         -1,
  41466         -1,
  41467     },
  41468 #endif /* chips */
  41469 
  41470 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  41471     defined(BCM_56270_A0)
  41472     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S1_UNDERFLOW_ID_BCM56260_A0r */
  41473         soc_block_list[85],
  41474         soc_genreg,
  41475         1,
  41476         0,
  41477         0x2003400,
  41478         0,
  41479         0,
  41480         1,
  41481         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r_fields,
  41482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41483         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  41484         -1,
  41485         -1,
  41486     },
  41487 #endif /* chips */
  41488 
  41489 #if defined(BCM_56270_A0)
  41490     { /* SOC_REG_INT_LLS_CAPT_MAX_SHAPER_BUCKET_S1_UNDERFLOW_ID_BCM56270_A0r */
  41491         soc_block_list[85],
  41492         soc_genreg,
  41493         1,
  41494         0,
  41495         0x2003200,
  41496         0,
  41497         0,
  41498         1,
  41499         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  41500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41501         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  41502         -1,
  41503         -1,
  41504     },
  41505 #endif /* chips */
  41506 
  41507 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41508     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L0_OVERFLOW_IDr */
  41509         soc_block_list[85],
  41510         soc_genreg,
  41511         1,
  41512         0,
  41513         0x80022,
  41514         0,
  41515         0,
  41516         1,
  41517         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_IDr_fields,
  41518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41519         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41520         -1,
  41521         -1,
  41522     },
  41523 #endif /* chips */
  41524 
  41525 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  41526     defined(BCM_56270_A0)
  41527     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56260_A0r */
  41528         soc_block_list[85],
  41529         soc_genreg,
  41530         1,
  41531         0,
  41532         0x2003000,
  41533         0,
  41534         0,
  41535         1,
  41536         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  41537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41538         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  41539         -1,
  41540         -1,
  41541     },
  41542 #endif /* chips */
  41543 
  41544 #if defined(BCM_56270_A0)
  41545     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56270_A0r */
  41546         soc_block_list[85],
  41547         soc_genreg,
  41548         1,
  41549         0,
  41550         0x2002f00,
  41551         0,
  41552         0,
  41553         1,
  41554         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r_fields,
  41555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41556         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  41557         -1,
  41558         -1,
  41559     },
  41560 #endif /* chips */
  41561 
  41562 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41563     defined(BCM_56450_B1)
  41564     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56450_A0r */
  41565         soc_block_list[85],
  41566         soc_genreg,
  41567         1,
  41568         0,
  41569         0x2003000,
  41570         0,
  41571         0,
  41572         1,
  41573         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56450_A0r_fields,
  41574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41575         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  41576         -1,
  41577         -1,
  41578     },
  41579 #endif /* chips */
  41580 
  41581 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41582     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L0_UNDERFLOW_IDr */
  41583         soc_block_list[85],
  41584         soc_genreg,
  41585         1,
  41586         0,
  41587         0x8002b,
  41588         0,
  41589         0,
  41590         1,
  41591         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_IDr_fields,
  41592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41593         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41594         -1,
  41595         -1,
  41596     },
  41597 #endif /* chips */
  41598 
  41599 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41600     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L0_UNDERFLOW_ID_BCM56260_A0r */
  41601         soc_block_list[85],
  41602         soc_genreg,
  41603         1,
  41604         0,
  41605         0x2003900,
  41606         0,
  41607         0,
  41608         1,
  41609         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  41610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41611         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  41612         -1,
  41613         -1,
  41614     },
  41615 #endif /* chips */
  41616 
  41617 #if defined(BCM_56270_A0)
  41618     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L0_UNDERFLOW_ID_BCM56270_A0r */
  41619         soc_block_list[85],
  41620         soc_genreg,
  41621         1,
  41622         0,
  41623         0x2003700,
  41624         0,
  41625         0,
  41626         1,
  41627         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r_fields,
  41628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41629         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  41630         -1,
  41631         -1,
  41632     },
  41633 #endif /* chips */
  41634 
  41635 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41636     defined(BCM_56450_B1)
  41637     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L0_UNDERFLOW_ID_BCM56450_A0r */
  41638         soc_block_list[85],
  41639         soc_genreg,
  41640         1,
  41641         0,
  41642         0x2003b00,
  41643         0,
  41644         0,
  41645         1,
  41646         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56450_A0r_fields,
  41647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41648         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  41649         -1,
  41650         -1,
  41651     },
  41652 #endif /* chips */
  41653 
  41654 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41655     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L1_OVERFLOW_IDr */
  41656         soc_block_list[85],
  41657         soc_genreg,
  41658         1,
  41659         0,
  41660         0x80023,
  41661         0,
  41662         0,
  41663         1,
  41664         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_IDr_fields,
  41665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41666         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  41667         -1,
  41668         -1,
  41669     },
  41670 #endif /* chips */
  41671 
  41672 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41673     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56260_A0r */
  41674         soc_block_list[85],
  41675         soc_genreg,
  41676         1,
  41677         0,
  41678         0x2003100,
  41679         0,
  41680         0,
  41681         1,
  41682         soc_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r_fields,
  41683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41684         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41685         -1,
  41686         -1,
  41687     },
  41688 #endif /* chips */
  41689 
  41690 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41691     defined(BCM_56450_B1)
  41692     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56450_A0r */
  41693         soc_block_list[85],
  41694         soc_genreg,
  41695         1,
  41696         0,
  41697         0x2003100,
  41698         0,
  41699         0,
  41700         1,
  41701         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56450_A0r_fields,
  41702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41703         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  41704         -1,
  41705         -1,
  41706     },
  41707 #endif /* chips */
  41708 
  41709 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41710     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L1_UNDERFLOW_IDr */
  41711         soc_block_list[85],
  41712         soc_genreg,
  41713         1,
  41714         0,
  41715         0x8002c,
  41716         0,
  41717         0,
  41718         1,
  41719         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_IDr_fields,
  41720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41721         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  41722         -1,
  41723         -1,
  41724     },
  41725 #endif /* chips */
  41726 
  41727 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41728     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L1_UNDERFLOW_ID_BCM56260_A0r */
  41729         soc_block_list[85],
  41730         soc_genreg,
  41731         1,
  41732         0,
  41733         0x2003a00,
  41734         0,
  41735         0,
  41736         1,
  41737         soc_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r_fields,
  41738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41739         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41740         -1,
  41741         -1,
  41742     },
  41743 #endif /* chips */
  41744 
  41745 #if defined(BCM_56270_A0)
  41746     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L1_UNDERFLOW_ID_BCM56270_A0r */
  41747         soc_block_list[85],
  41748         soc_genreg,
  41749         1,
  41750         0,
  41751         0x2003800,
  41752         0,
  41753         0,
  41754         1,
  41755         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  41756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41757         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  41758         -1,
  41759         -1,
  41760     },
  41761 #endif /* chips */
  41762 
  41763 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41764     defined(BCM_56450_B1)
  41765     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L1_UNDERFLOW_ID_BCM56450_A0r */
  41766         soc_block_list[85],
  41767         soc_genreg,
  41768         1,
  41769         0,
  41770         0x2003c00,
  41771         0,
  41772         0,
  41773         1,
  41774         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56450_A0r_fields,
  41775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41776         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  41777         -1,
  41778         -1,
  41779     },
  41780 #endif /* chips */
  41781 
  41782 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41783     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr */
  41784         soc_block_list[85],
  41785         soc_genreg,
  41786         1,
  41787         0,
  41788         0x80025,
  41789         0,
  41790         0,
  41791         1,
  41792         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr_fields,
  41793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41794         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41795         -1,
  41796         -1,
  41797     },
  41798 #endif /* chips */
  41799 
  41800 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41801     defined(BCM_56450_B1)
  41802     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r */
  41803         soc_block_list[85],
  41804         soc_genreg,
  41805         1,
  41806         0,
  41807         0x2003300,
  41808         0,
  41809         0,
  41810         1,
  41811         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r_fields,
  41812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41813         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41814         -1,
  41815         -1,
  41816     },
  41817 #endif /* chips */
  41818 
  41819 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41820     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_LOWER_UNDERFLOW_IDr */
  41821         soc_block_list[85],
  41822         soc_genreg,
  41823         1,
  41824         0,
  41825         0x8002e,
  41826         0,
  41827         0,
  41828         1,
  41829         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr_fields,
  41830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41831         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41832         -1,
  41833         -1,
  41834     },
  41835 #endif /* chips */
  41836 
  41837 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41838     defined(BCM_56450_B1)
  41839     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_LOWER_UNDERFLOW_ID_BCM56450_A0r */
  41840         soc_block_list[85],
  41841         soc_genreg,
  41842         1,
  41843         0,
  41844         0x2003e00,
  41845         0,
  41846         0,
  41847         1,
  41848         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r_fields,
  41849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41850         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41851         -1,
  41852         -1,
  41853     },
  41854 #endif /* chips */
  41855 
  41856 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41857     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_OVERFLOW_IDr */
  41858         soc_block_list[85],
  41859         soc_genreg,
  41860         1,
  41861         0,
  41862         0x2003200,
  41863         0,
  41864         0,
  41865         1,
  41866         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  41867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41868         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  41869         -1,
  41870         -1,
  41871     },
  41872 #endif /* chips */
  41873 
  41874 #if defined(BCM_56270_A0)
  41875     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_OVERFLOW_ID_BCM56270_A0r */
  41876         soc_block_list[85],
  41877         soc_genreg,
  41878         1,
  41879         0,
  41880         0x2003100,
  41881         0,
  41882         0,
  41883         1,
  41884         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  41885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41886         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  41887         -1,
  41888         -1,
  41889     },
  41890 #endif /* chips */
  41891 
  41892 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  41893     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_UNDERFLOW_IDr */
  41894         soc_block_list[85],
  41895         soc_genreg,
  41896         1,
  41897         0,
  41898         0x2003b00,
  41899         0,
  41900         0,
  41901         1,
  41902         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  41903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41904         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  41905         -1,
  41906         -1,
  41907     },
  41908 #endif /* chips */
  41909 
  41910 #if defined(BCM_56270_A0)
  41911     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_UNDERFLOW_ID_BCM56270_A0r */
  41912         soc_block_list[85],
  41913         soc_genreg,
  41914         1,
  41915         0,
  41916         0x2003900,
  41917         0,
  41918         0,
  41919         1,
  41920         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  41921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41922         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  41923         -1,
  41924         -1,
  41925     },
  41926 #endif /* chips */
  41927 
  41928 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41929     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_UPPER_OVERFLOW_IDr */
  41930         soc_block_list[85],
  41931         soc_genreg,
  41932         1,
  41933         0,
  41934         0x80024,
  41935         0,
  41936         0,
  41937         1,
  41938         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr_fields,
  41939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41940         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41941         -1,
  41942         -1,
  41943     },
  41944 #endif /* chips */
  41945 
  41946 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41947     defined(BCM_56450_B1)
  41948     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_UPPER_OVERFLOW_ID_BCM56450_A0r */
  41949         soc_block_list[85],
  41950         soc_genreg,
  41951         1,
  41952         0,
  41953         0x2003200,
  41954         0,
  41955         0,
  41956         1,
  41957         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r_fields,
  41958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41959         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41960         -1,
  41961         -1,
  41962     },
  41963 #endif /* chips */
  41964 
  41965 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41966     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_UPPER_UNDERFLOW_IDr */
  41967         soc_block_list[85],
  41968         soc_genreg,
  41969         1,
  41970         0,
  41971         0x8002d,
  41972         0,
  41973         0,
  41974         1,
  41975         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_IDr_fields,
  41976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41977         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41978         -1,
  41979         -1,
  41980     },
  41981 #endif /* chips */
  41982 
  41983 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41984     defined(BCM_56450_B1)
  41985     { /* SOC_REG_INT_LLS_CAPT_MIN_SHAPER_BUCKET_L2_UPPER_UNDERFLOW_ID_BCM56450_A0r */
  41986         soc_block_list[85],
  41987         soc_genreg,
  41988         1,
  41989         0,
  41990         0x2003d00,
  41991         0,
  41992         0,
  41993         1,
  41994         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID_BCM56450_A0r_fields,
  41995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41996         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  41997         -1,
  41998         -1,
  41999     },
  42000 #endif /* chips */
  42001 
  42002 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42003     { /* SOC_REG_INT_LLS_CAPT_PORT_1_IN_4_VIOL_IDr */
  42004         soc_block_list[85],
  42005         soc_genreg,
  42006         1,
  42007         0,
  42008         0x8001c,
  42009         0,
  42010         0,
  42011         1,
  42012         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_IDr_fields,
  42013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42014         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  42015         -1,
  42016         -1,
  42017     },
  42018 #endif /* chips */
  42019 
  42020 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42021     { /* SOC_REG_INT_LLS_CAPT_PORT_1_IN_4_VIOL_ID_BCM56260_A0r */
  42022         soc_block_list[85],
  42023         soc_genreg,
  42024         1,
  42025         0,
  42026         0x2002900,
  42027         0,
  42028         0,
  42029         1,
  42030         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  42031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42032         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  42033         -1,
  42034         -1,
  42035     },
  42036 #endif /* chips */
  42037 
  42038 #if defined(BCM_56270_A0)
  42039     { /* SOC_REG_INT_LLS_CAPT_PORT_1_IN_4_VIOL_ID_BCM56270_A0r */
  42040         soc_block_list[85],
  42041         soc_genreg,
  42042         1,
  42043         0,
  42044         0x2002900,
  42045         0,
  42046         0,
  42047         1,
  42048         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID_BCM56260_A0r_fields,
  42049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42050         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  42051         -1,
  42052         -1,
  42053     },
  42054 #endif /* chips */
  42055 
  42056 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42057     defined(BCM_56450_B1)
  42058     { /* SOC_REG_INT_LLS_CAPT_PORT_1_IN_4_VIOL_ID_BCM56450_A0r */
  42059         soc_block_list[85],
  42060         soc_genreg,
  42061         1,
  42062         0,
  42063         0x2002800,
  42064         0,
  42065         0,
  42066         1,
  42067         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56450_A0r_fields,
  42068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42069         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  42070         -1,
  42071         -1,
  42072     },
  42073 #endif /* chips */
  42074 
  42075 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  42076     { /* SOC_REG_INT_LLS_CAPT_PORT_1_IN_4_VIOL_ID_BCM56560_A0r */
  42077         soc_block_list[4],
  42078         soc_genreg,
  42079         1,
  42080         0,
  42081         0x62002100,
  42082         0,
  42083         0,
  42084         1,
  42085         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42087         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42088         -1,
  42089         -1,
  42090     },
  42091 #endif /* chips */
  42092 
  42093 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42094     defined(BCM_56450_B1)
  42095     { /* SOC_REG_INT_LLS_CAPT_PORT_L2_COUNT_OVERFLOW_IDr */
  42096         soc_block_list[85],
  42097         soc_genreg,
  42098         1,
  42099         0,
  42100         0x2002600,
  42101         0,
  42102         0,
  42103         1,
  42104         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56450_A0r_fields,
  42105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42106         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  42107         -1,
  42108         -1,
  42109     },
  42110 #endif /* chips */
  42111 
  42112 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42113     { /* SOC_REG_INT_LLS_CAPT_PORT_L2_COUNT_OVERFLOW_ID_BCM56260_A0r */
  42114         soc_block_list[85],
  42115         soc_genreg,
  42116         1,
  42117         0,
  42118         0x2002700,
  42119         0,
  42120         0,
  42121         1,
  42122         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  42123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42124         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  42125         -1,
  42126         -1,
  42127     },
  42128 #endif /* chips */
  42129 
  42130 #if defined(BCM_56270_A0)
  42131     { /* SOC_REG_INT_LLS_CAPT_PORT_L2_COUNT_OVERFLOW_ID_BCM56270_A0r */
  42132         soc_block_list[85],
  42133         soc_genreg,
  42134         1,
  42135         0,
  42136         0x2002700,
  42137         0,
  42138         0,
  42139         1,
  42140         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID_BCM56260_A0r_fields,
  42141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42142         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  42143         -1,
  42144         -1,
  42145     },
  42146 #endif /* chips */
  42147 
  42148 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  42149     { /* SOC_REG_INT_LLS_CAPT_PORT_L2_COUNT_OVERFLOW_ID_BCM56560_A0r */
  42150         soc_block_list[4],
  42151         soc_genreg,
  42152         1,
  42153         0,
  42154         0x62001f00,
  42155         0,
  42156         0,
  42157         1,
  42158         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42160         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42161         -1,
  42162         -1,
  42163     },
  42164 #endif /* chips */
  42165 
  42166 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42167     defined(BCM_56450_B1)
  42168     { /* SOC_REG_INT_LLS_CAPT_PORT_L2_COUNT_UNDERRUN_IDr */
  42169         soc_block_list[85],
  42170         soc_genreg,
  42171         1,
  42172         0,
  42173         0x2002300,
  42174         0,
  42175         0,
  42176         1,
  42177         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56450_A0r_fields,
  42178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42179         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  42180         -1,
  42181         -1,
  42182     },
  42183 #endif /* chips */
  42184 
  42185 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42186     { /* SOC_REG_INT_LLS_CAPT_PORT_L2_COUNT_UNDERRUN_ID_BCM56260_A0r */
  42187         soc_block_list[85],
  42188         soc_genreg,
  42189         1,
  42190         0,
  42191         0x2002400,
  42192         0,
  42193         0,
  42194         1,
  42195         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  42196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42197         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  42198         -1,
  42199         -1,
  42200     },
  42201 #endif /* chips */
  42202 
  42203 #if defined(BCM_56270_A0)
  42204     { /* SOC_REG_INT_LLS_CAPT_PORT_L2_COUNT_UNDERRUN_ID_BCM56270_A0r */
  42205         soc_block_list[85],
  42206         soc_genreg,
  42207         1,
  42208         0,
  42209         0x2002400,
  42210         0,
  42211         0,
  42212         1,
  42213         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID_BCM56260_A0r_fields,
  42214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42215         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  42216         -1,
  42217         -1,
  42218     },
  42219 #endif /* chips */
  42220 
  42221 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  42222     { /* SOC_REG_INT_LLS_CAPT_PORT_L2_COUNT_UNDERRUN_ID_BCM56560_A0r */
  42223         soc_block_list[4],
  42224         soc_genreg,
  42225         1,
  42226         0,
  42227         0x62001c00,
  42228         0,
  42229         0,
  42230         1,
  42231         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42233         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42234         -1,
  42235         -1,
  42236     },
  42237 #endif /* chips */
  42238 
  42239 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42240     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_MIN_OVERFLOW_IDr */
  42241         soc_block_list[85],
  42242         soc_genreg,
  42243         1,
  42244         0,
  42245         0x2004900,
  42246         0,
  42247         0,
  42248         1,
  42249         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42251         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42252         -1,
  42253         -1,
  42254     },
  42255 #endif /* chips */
  42256 
  42257 #if defined(BCM_56270_A0)
  42258     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_MIN_OVERFLOW_ID_BCM56270_A0r */
  42259         soc_block_list[85],
  42260         soc_genreg,
  42261         1,
  42262         0,
  42263         0x2004500,
  42264         0,
  42265         0,
  42266         1,
  42267         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r_fields,
  42268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42269         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  42270         -1,
  42271         -1,
  42272     },
  42273 #endif /* chips */
  42274 
  42275 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42276     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_MIN_UNDERRUN_IDr */
  42277         soc_block_list[85],
  42278         soc_genreg,
  42279         1,
  42280         0,
  42281         0x2004800,
  42282         0,
  42283         0,
  42284         1,
  42285         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42287         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42288         -1,
  42289         -1,
  42290     },
  42291 #endif /* chips */
  42292 
  42293 #if defined(BCM_56270_A0)
  42294     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_MIN_UNDERRUN_ID_BCM56270_A0r */
  42295         soc_block_list[85],
  42296         soc_genreg,
  42297         1,
  42298         0,
  42299         0x2004400,
  42300         0,
  42301         0,
  42302         1,
  42303         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r_fields,
  42304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42305         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  42306         -1,
  42307         -1,
  42308     },
  42309 #endif /* chips */
  42310 
  42311 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42312     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr */
  42313         soc_block_list[85],
  42314         soc_genreg,
  42315         1,
  42316         0,
  42317         0x80032,
  42318         0,
  42319         0,
  42320         1,
  42321         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_IDr_fields,
  42322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42323         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42324         -1,
  42325         -1,
  42326     },
  42327 #endif /* chips */
  42328 
  42329 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42330     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_ID_BCM56260_A0r */
  42331         soc_block_list[85],
  42332         soc_genreg,
  42333         1,
  42334         0,
  42335         0x2004300,
  42336         0,
  42337         0,
  42338         1,
  42339         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42341         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42342         -1,
  42343         -1,
  42344     },
  42345 #endif /* chips */
  42346 
  42347 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42348     defined(BCM_56450_B1)
  42349     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_ID_BCM56450_A0r */
  42350         soc_block_list[85],
  42351         soc_genreg,
  42352         1,
  42353         0,
  42354         0x2004600,
  42355         0,
  42356         0,
  42357         1,
  42358         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56450_A0r_fields,
  42359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42360         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42361         -1,
  42362         -1,
  42363     },
  42364 #endif /* chips */
  42365 
  42366 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  42367     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_ID_BCM56560_A0r */
  42368         soc_block_list[4],
  42369         soc_genreg,
  42370         1,
  42371         0,
  42372         0x62002500,
  42373         0,
  42374         0,
  42375         1,
  42376         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  42377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42378         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42379         -1,
  42380         -1,
  42381     },
  42382 #endif /* chips */
  42383 
  42384 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42385     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_UNDERRUN_IDr */
  42386         soc_block_list[85],
  42387         soc_genreg,
  42388         1,
  42389         0,
  42390         0x80031,
  42391         0,
  42392         0,
  42393         1,
  42394         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_IDr_fields,
  42395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42396         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42397         -1,
  42398         -1,
  42399     },
  42400 #endif /* chips */
  42401 
  42402 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42403     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_UNDERRUN_ID_BCM56260_A0r */
  42404         soc_block_list[85],
  42405         soc_genreg,
  42406         1,
  42407         0,
  42408         0x2004200,
  42409         0,
  42410         0,
  42411         1,
  42412         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42414         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42415         -1,
  42416         -1,
  42417     },
  42418 #endif /* chips */
  42419 
  42420 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42421     defined(BCM_56450_B1)
  42422     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_UNDERRUN_ID_BCM56450_A0r */
  42423         soc_block_list[85],
  42424         soc_genreg,
  42425         1,
  42426         0,
  42427         0x2004500,
  42428         0,
  42429         0,
  42430         1,
  42431         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID_BCM56450_A0r_fields,
  42432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42433         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42434         -1,
  42435         -1,
  42436     },
  42437 #endif /* chips */
  42438 
  42439 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  42440     { /* SOC_REG_INT_LLS_CAPT_UPD2_L0_ERROR_UNDERRUN_ID_BCM56560_A0r */
  42441         soc_block_list[4],
  42442         soc_genreg,
  42443         1,
  42444         0,
  42445         0x62002400,
  42446         0,
  42447         0,
  42448         1,
  42449         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  42450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42451         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42452         -1,
  42453         -1,
  42454     },
  42455 #endif /* chips */
  42456 
  42457 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42458     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_MIN_OVERFLOW_IDr */
  42459         soc_block_list[85],
  42460         soc_genreg,
  42461         1,
  42462         0,
  42463         0x2004b00,
  42464         0,
  42465         0,
  42466         1,
  42467         soc_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r_fields,
  42468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42469         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42470         -1,
  42471         -1,
  42472     },
  42473 #endif /* chips */
  42474 
  42475 #if defined(BCM_56270_A0)
  42476     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_MIN_OVERFLOW_ID_BCM56270_A0r */
  42477         soc_block_list[85],
  42478         soc_genreg,
  42479         1,
  42480         0,
  42481         0x2004700,
  42482         0,
  42483         0,
  42484         1,
  42485         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42487         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42488         -1,
  42489         -1,
  42490     },
  42491 #endif /* chips */
  42492 
  42493 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42494     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_MIN_UNDERRUN_IDr */
  42495         soc_block_list[85],
  42496         soc_genreg,
  42497         1,
  42498         0,
  42499         0x2004a00,
  42500         0,
  42501         0,
  42502         1,
  42503         soc_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r_fields,
  42504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42505         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42506         -1,
  42507         -1,
  42508     },
  42509 #endif /* chips */
  42510 
  42511 #if defined(BCM_56270_A0)
  42512     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_MIN_UNDERRUN_ID_BCM56270_A0r */
  42513         soc_block_list[85],
  42514         soc_genreg,
  42515         1,
  42516         0,
  42517         0x2004600,
  42518         0,
  42519         0,
  42520         1,
  42521         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42523         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42524         -1,
  42525         -1,
  42526     },
  42527 #endif /* chips */
  42528 
  42529 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42530     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_OVERFLOW_IDr */
  42531         soc_block_list[85],
  42532         soc_genreg,
  42533         1,
  42534         0,
  42535         0x80034,
  42536         0,
  42537         0,
  42538         1,
  42539         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_IDr_fields,
  42540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42541         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42542         -1,
  42543         -1,
  42544     },
  42545 #endif /* chips */
  42546 
  42547 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42548     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_OVERFLOW_ID_BCM56260_A0r */
  42549         soc_block_list[85],
  42550         soc_genreg,
  42551         1,
  42552         0,
  42553         0x2004500,
  42554         0,
  42555         0,
  42556         1,
  42557         soc_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r_fields,
  42558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42559         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42560         -1,
  42561         -1,
  42562     },
  42563 #endif /* chips */
  42564 
  42565 #if defined(BCM_56270_A0)
  42566     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_OVERFLOW_ID_BCM56270_A0r */
  42567         soc_block_list[85],
  42568         soc_genreg,
  42569         1,
  42570         0,
  42571         0x2004100,
  42572         0,
  42573         0,
  42574         1,
  42575         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42577         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42578         -1,
  42579         -1,
  42580     },
  42581 #endif /* chips */
  42582 
  42583 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42584     defined(BCM_56450_B1)
  42585     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_OVERFLOW_ID_BCM56450_A0r */
  42586         soc_block_list[85],
  42587         soc_genreg,
  42588         1,
  42589         0,
  42590         0x2004800,
  42591         0,
  42592         0,
  42593         1,
  42594         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56450_A0r_fields,
  42595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42596         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42597         -1,
  42598         -1,
  42599     },
  42600 #endif /* chips */
  42601 
  42602 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  42603     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_OVERFLOW_ID_BCM56560_A0r */
  42604         soc_block_list[4],
  42605         soc_genreg,
  42606         1,
  42607         0,
  42608         0x62002700,
  42609         0,
  42610         0,
  42611         1,
  42612         soc_LLS_CAPT_LIST_HEAD_MISMATCH_IDr_fields,
  42613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42614         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  42615         -1,
  42616         -1,
  42617     },
  42618 #endif /* chips */
  42619 
  42620 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42621     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_UNDERRUN_IDr */
  42622         soc_block_list[85],
  42623         soc_genreg,
  42624         1,
  42625         0,
  42626         0x80033,
  42627         0,
  42628         0,
  42629         1,
  42630         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_IDr_fields,
  42631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42632         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42633         -1,
  42634         -1,
  42635     },
  42636 #endif /* chips */
  42637 
  42638 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42639     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_UNDERRUN_ID_BCM56260_A0r */
  42640         soc_block_list[85],
  42641         soc_genreg,
  42642         1,
  42643         0,
  42644         0x2004400,
  42645         0,
  42646         0,
  42647         1,
  42648         soc_LLS_CAPT_LIST_HEAD_MISMATCH_ID_BCM56260_A0r_fields,
  42649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42650         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42651         -1,
  42652         -1,
  42653     },
  42654 #endif /* chips */
  42655 
  42656 #if defined(BCM_56270_A0)
  42657     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_UNDERRUN_ID_BCM56270_A0r */
  42658         soc_block_list[85],
  42659         soc_genreg,
  42660         1,
  42661         0,
  42662         0x2004000,
  42663         0,
  42664         0,
  42665         1,
  42666         soc_LLS_CAPT_PORT_1_IN_4_VIOL_IDr_fields,
  42667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42668         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  42669         -1,
  42670         -1,
  42671     },
  42672 #endif /* chips */
  42673 
  42674 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42675     defined(BCM_56450_B1)
  42676     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_UNDERRUN_ID_BCM56450_A0r */
  42677         soc_block_list[85],
  42678         soc_genreg,
  42679         1,
  42680         0,
  42681         0x2004700,
  42682         0,
  42683         0,
  42684         1,
  42685         soc_LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_ID_BCM56450_A0r_fields,
  42686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42687         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42688         -1,
  42689         -1,
  42690     },
  42691 #endif /* chips */
  42692 
  42693 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  42694     { /* SOC_REG_INT_LLS_CAPT_UPD2_L1_ERROR_UNDERRUN_ID_BCM56560_A0r */
  42695         soc_block_list[4],
  42696         soc_genreg,
  42697         1,
  42698         0,
  42699         0x62002600,
  42700         0,
  42701         0,
  42702         1,
  42703         soc_LLS_CAPT_LIST_HEAD_MISMATCH_IDr_fields,
  42704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42705         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  42706         -1,
  42707         -1,
  42708     },
  42709 #endif /* chips */
  42710 
  42711 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42712     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_MIN_OVERFLOW_IDr */
  42713         soc_block_list[85],
  42714         soc_genreg,
  42715         1,
  42716         0,
  42717         0x2004d00,
  42718         0,
  42719         0,
  42720         1,
  42721         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  42722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42723         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42724         -1,
  42725         -1,
  42726     },
  42727 #endif /* chips */
  42728 
  42729 #if defined(BCM_56270_A0)
  42730     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_MIN_OVERFLOW_ID_BCM56270_A0r */
  42731         soc_block_list[85],
  42732         soc_genreg,
  42733         1,
  42734         0,
  42735         0x2004900,
  42736         0,
  42737         0,
  42738         1,
  42739         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  42740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42741         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42742         -1,
  42743         -1,
  42744     },
  42745 #endif /* chips */
  42746 
  42747 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42748     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_MIN_UNDERRUN_IDr */
  42749         soc_block_list[85],
  42750         soc_genreg,
  42751         1,
  42752         0,
  42753         0x2004c00,
  42754         0,
  42755         0,
  42756         1,
  42757         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  42758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42759         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42760         -1,
  42761         -1,
  42762     },
  42763 #endif /* chips */
  42764 
  42765 #if defined(BCM_56270_A0)
  42766     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_MIN_UNDERRUN_ID_BCM56270_A0r */
  42767         soc_block_list[85],
  42768         soc_genreg,
  42769         1,
  42770         0,
  42771         0x2004800,
  42772         0,
  42773         0,
  42774         1,
  42775         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  42776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42777         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42778         -1,
  42779         -1,
  42780     },
  42781 #endif /* chips */
  42782 
  42783 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42784     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_OVERFLOW_IDr */
  42785         soc_block_list[85],
  42786         soc_genreg,
  42787         1,
  42788         0,
  42789         0x80036,
  42790         0,
  42791         0,
  42792         1,
  42793         soc_LLS_CAPT_ENQUEUE_VIOL_IDr_fields,
  42794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42795         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42796         -1,
  42797         -1,
  42798     },
  42799 #endif /* chips */
  42800 
  42801 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42802     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_OVERFLOW_ID_BCM56260_A0r */
  42803         soc_block_list[85],
  42804         soc_genreg,
  42805         1,
  42806         0,
  42807         0x2004700,
  42808         0,
  42809         0,
  42810         1,
  42811         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  42812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42813         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42814         -1,
  42815         -1,
  42816     },
  42817 #endif /* chips */
  42818 
  42819 #if defined(BCM_56270_A0)
  42820     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_OVERFLOW_ID_BCM56270_A0r */
  42821         soc_block_list[85],
  42822         soc_genreg,
  42823         1,
  42824         0,
  42825         0x2004300,
  42826         0,
  42827         0,
  42828         1,
  42829         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  42830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42831         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42832         -1,
  42833         -1,
  42834     },
  42835 #endif /* chips */
  42836 
  42837 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42838     defined(BCM_56450_B1)
  42839     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_OVERFLOW_ID_BCM56450_A0r */
  42840         soc_block_list[85],
  42841         soc_genreg,
  42842         1,
  42843         0,
  42844         0x2004a00,
  42845         0,
  42846         0,
  42847         1,
  42848         soc_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56450_A0r_fields,
  42849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42850         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42851         -1,
  42852         -1,
  42853     },
  42854 #endif /* chips */
  42855 
  42856 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  42857     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_OVERFLOW_ID_BCM56560_A0r */
  42858         soc_block_list[4],
  42859         soc_genreg,
  42860         1,
  42861         0,
  42862         0x62002900,
  42863         0,
  42864         0,
  42865         1,
  42866         soc_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56560_A0r_fields,
  42867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42868         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  42869         -1,
  42870         -1,
  42871     },
  42872 #endif /* chips */
  42873 
  42874 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42875     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_UNDERRUN_IDr */
  42876         soc_block_list[85],
  42877         soc_genreg,
  42878         1,
  42879         0,
  42880         0x80035,
  42881         0,
  42882         0,
  42883         1,
  42884         soc_LLS_CAPT_ENQUEUE_VIOL_IDr_fields,
  42885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42886         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42887         -1,
  42888         -1,
  42889     },
  42890 #endif /* chips */
  42891 
  42892 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42893     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_UNDERRUN_ID_BCM56260_A0r */
  42894         soc_block_list[85],
  42895         soc_genreg,
  42896         1,
  42897         0,
  42898         0x2004600,
  42899         0,
  42900         0,
  42901         1,
  42902         soc_LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_IDr_fields,
  42903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42904         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42905         -1,
  42906         -1,
  42907     },
  42908 #endif /* chips */
  42909 
  42910 #if defined(BCM_56270_A0)
  42911     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_UNDERRUN_ID_BCM56270_A0r */
  42912         soc_block_list[85],
  42913         soc_genreg,
  42914         1,
  42915         0,
  42916         0x2004200,
  42917         0,
  42918         0,
  42919         1,
  42920         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  42921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42922         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42923         -1,
  42924         -1,
  42925     },
  42926 #endif /* chips */
  42927 
  42928 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42929     defined(BCM_56450_B1)
  42930     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_UNDERRUN_ID_BCM56450_A0r */
  42931         soc_block_list[85],
  42932         soc_genreg,
  42933         1,
  42934         0,
  42935         0x2004900,
  42936         0,
  42937         0,
  42938         1,
  42939         soc_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56450_A0r_fields,
  42940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42941         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42942         -1,
  42943         -1,
  42944     },
  42945 #endif /* chips */
  42946 
  42947 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  42948     { /* SOC_REG_INT_LLS_CAPT_UPD2_L2_ERROR_UNDERRUN_ID_BCM56560_A0r */
  42949         soc_block_list[4],
  42950         soc_genreg,
  42951         1,
  42952         0,
  42953         0x62002800,
  42954         0,
  42955         0,
  42956         1,
  42957         soc_LLS_CAPT_ENQUEUE_VIOL_ID_BCM56560_A0r_fields,
  42958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42959         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  42960         -1,
  42961         -1,
  42962     },
  42963 #endif /* chips */
  42964 
  42965 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42966     { /* SOC_REG_INT_LLS_CAPT_UPD2_PORT_ERROR_OVERFLOW_IDr */
  42967         soc_block_list[85],
  42968         soc_genreg,
  42969         1,
  42970         0,
  42971         0x80030,
  42972         0,
  42973         0,
  42974         1,
  42975         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_IDr_fields,
  42976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42977         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  42978         -1,
  42979         -1,
  42980     },
  42981 #endif /* chips */
  42982 
  42983 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  42984     { /* SOC_REG_INT_LLS_CAPT_UPD2_PORT_ERROR_OVERFLOW_ID_BCM56260_A0r */
  42985         soc_block_list[85],
  42986         soc_genreg,
  42987         1,
  42988         0,
  42989         0x2004100,
  42990         0,
  42991         0,
  42992         1,
  42993         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  42994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42995         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  42996         -1,
  42997         -1,
  42998     },
  42999 #endif /* chips */
  43000 
  43001 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43002     defined(BCM_56450_B1)
  43003     { /* SOC_REG_INT_LLS_CAPT_UPD2_PORT_ERROR_OVERFLOW_ID_BCM56450_A0r */
  43004         soc_block_list[85],
  43005         soc_genreg,
  43006         1,
  43007         0,
  43008         0x2004400,
  43009         0,
  43010         0,
  43011         1,
  43012         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56450_A0r_fields,
  43013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43014         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43015         -1,
  43016         -1,
  43017     },
  43018 #endif /* chips */
  43019 
  43020 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  43021     { /* SOC_REG_INT_LLS_CAPT_UPD2_PORT_ERROR_UNDERRUN_IDr */
  43022         soc_block_list[85],
  43023         soc_genreg,
  43024         1,
  43025         0,
  43026         0x8002f,
  43027         0,
  43028         0,
  43029         1,
  43030         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_IDr_fields,
  43031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43032         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43033         -1,
  43034         -1,
  43035     },
  43036 #endif /* chips */
  43037 
  43038 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  43039     { /* SOC_REG_INT_LLS_CAPT_UPD2_PORT_ERROR_UNDERRUN_ID_BCM56260_A0r */
  43040         soc_block_list[85],
  43041         soc_genreg,
  43042         1,
  43043         0,
  43044         0x2004000,
  43045         0,
  43046         0,
  43047         1,
  43048         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  43049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43050         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  43051         -1,
  43052         -1,
  43053     },
  43054 #endif /* chips */
  43055 
  43056 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43057     defined(BCM_56450_B1)
  43058     { /* SOC_REG_INT_LLS_CAPT_UPD2_PORT_ERROR_UNDERRUN_ID_BCM56450_A0r */
  43059         soc_block_list[85],
  43060         soc_genreg,
  43061         1,
  43062         0,
  43063         0x2004300,
  43064         0,
  43065         0,
  43066         1,
  43067         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56450_A0r_fields,
  43068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43069         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43070         -1,
  43071         -1,
  43072     },
  43073 #endif /* chips */
  43074 
  43075 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43076     defined(BCM_56450_B1)
  43077     { /* SOC_REG_INT_LLS_CAPT_UPD2_S0_ERROR_OVERFLOW_IDr */
  43078         soc_block_list[85],
  43079         soc_genreg,
  43080         1,
  43081         0,
  43082         0x2004000,
  43083         0,
  43084         0,
  43085         1,
  43086         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_IDr_fields,
  43087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43088         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  43089         -1,
  43090         -1,
  43091     },
  43092 #endif /* chips */
  43093 
  43094 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43095     defined(BCM_56270_A0)
  43096     { /* SOC_REG_INT_LLS_CAPT_UPD2_S0_ERROR_OVERFLOW_ID_BCM56260_A0r */
  43097         soc_block_list[85],
  43098         soc_genreg,
  43099         1,
  43100         0,
  43101         0x2003d00,
  43102         0,
  43103         0,
  43104         1,
  43105         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID_BCM56260_A0r_fields,
  43106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43107         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  43108         -1,
  43109         -1,
  43110     },
  43111 #endif /* chips */
  43112 
  43113 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43114     defined(BCM_56450_B1)
  43115     { /* SOC_REG_INT_LLS_CAPT_UPD2_S0_ERROR_UNDERRUN_IDr */
  43116         soc_block_list[85],
  43117         soc_genreg,
  43118         1,
  43119         0,
  43120         0x2003f00,
  43121         0,
  43122         0,
  43123         1,
  43124         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_IDr_fields,
  43125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43126         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  43127         -1,
  43128         -1,
  43129     },
  43130 #endif /* chips */
  43131 
  43132 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43133     defined(BCM_56270_A0)
  43134     { /* SOC_REG_INT_LLS_CAPT_UPD2_S0_ERROR_UNDERRUN_ID_BCM56260_A0r */
  43135         soc_block_list[85],
  43136         soc_genreg,
  43137         1,
  43138         0,
  43139         0x2003c00,
  43140         0,
  43141         0,
  43142         1,
  43143         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID_BCM56260_A0r_fields,
  43144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43145         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  43146         -1,
  43147         -1,
  43148     },
  43149 #endif /* chips */
  43150 
  43151 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43152     defined(BCM_56450_B1)
  43153     { /* SOC_REG_INT_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr */
  43154         soc_block_list[85],
  43155         soc_genreg,
  43156         1,
  43157         0,
  43158         0x2004200,
  43159         0,
  43160         0,
  43161         1,
  43162         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_IDr_fields,
  43163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43164         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43165         -1,
  43166         -1,
  43167     },
  43168 #endif /* chips */
  43169 
  43170 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43171     defined(BCM_56270_A0)
  43172     { /* SOC_REG_INT_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_ID_BCM56260_A0r */
  43173         soc_block_list[85],
  43174         soc_genreg,
  43175         1,
  43176         0,
  43177         0x2003f00,
  43178         0,
  43179         0,
  43180         1,
  43181         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r_fields,
  43182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43183         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43184         -1,
  43185         -1,
  43186     },
  43187 #endif /* chips */
  43188 
  43189 #if defined(BCM_56270_A0)
  43190     { /* SOC_REG_INT_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_ID_BCM56270_A0r */
  43191         soc_block_list[85],
  43192         soc_genreg,
  43193         1,
  43194         0,
  43195         0x2003b00,
  43196         0,
  43197         0,
  43198         1,
  43199         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  43200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43201         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  43202         -1,
  43203         -1,
  43204     },
  43205 #endif /* chips */
  43206 
  43207 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  43208     { /* SOC_REG_INT_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_ID_BCM56560_A0r */
  43209         soc_block_list[4],
  43210         soc_genreg,
  43211         1,
  43212         0,
  43213         0x62002300,
  43214         0,
  43215         0,
  43216         1,
  43217         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  43218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43219         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  43220         -1,
  43221         -1,
  43222     },
  43223 #endif /* chips */
  43224 
  43225 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43226     defined(BCM_56450_B1)
  43227     { /* SOC_REG_INT_LLS_CAPT_UPD2_S1_ERROR_UNDERRUN_IDr */
  43228         soc_block_list[85],
  43229         soc_genreg,
  43230         1,
  43231         0,
  43232         0x2004100,
  43233         0,
  43234         0,
  43235         1,
  43236         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_IDr_fields,
  43237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43238         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43239         -1,
  43240         -1,
  43241     },
  43242 #endif /* chips */
  43243 
  43244 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43245     defined(BCM_56270_A0)
  43246     { /* SOC_REG_INT_LLS_CAPT_UPD2_S1_ERROR_UNDERRUN_ID_BCM56260_A0r */
  43247         soc_block_list[85],
  43248         soc_genreg,
  43249         1,
  43250         0,
  43251         0x2003e00,
  43252         0,
  43253         0,
  43254         1,
  43255         soc_LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID_BCM56260_A0r_fields,
  43256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43257         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43258         -1,
  43259         -1,
  43260     },
  43261 #endif /* chips */
  43262 
  43263 #if defined(BCM_56270_A0)
  43264     { /* SOC_REG_INT_LLS_CAPT_UPD2_S1_ERROR_UNDERRUN_ID_BCM56270_A0r */
  43265         soc_block_list[85],
  43266         soc_genreg,
  43267         1,
  43268         0,
  43269         0x2003a00,
  43270         0,
  43271         0,
  43272         1,
  43273         soc_LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID_BCM56260_A0r_fields,
  43274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43275         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  43276         -1,
  43277         -1,
  43278     },
  43279 #endif /* chips */
  43280 
  43281 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  43282     { /* SOC_REG_INT_LLS_CAPT_UPD2_S1_ERROR_UNDERRUN_ID_BCM56560_A0r */
  43283         soc_block_list[4],
  43284         soc_genreg,
  43285         1,
  43286         0,
  43287         0x62002200,
  43288         0,
  43289         0,
  43290         1,
  43291         soc_LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_IDr_fields,
  43292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43293         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  43294         -1,
  43295         -1,
  43296     },
  43297 #endif /* chips */
  43298 
  43299 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  43300     { /* SOC_REG_INT_LLS_CFG_ERR_BYTE_ADJUSTr */
  43301         soc_block_list[4],
  43302         soc_genreg,
  43303         1,
  43304         0,
  43305         0x5a00a000,
  43306         0,
  43307         0,
  43308         1,
  43309         soc_LLS_CFG_ERR_BYTE_ADJUSTr_fields,
  43310         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  43311         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43312         -1,
  43313         -1,
  43314     },
  43315 #endif /* chips */
  43316 
  43317 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43318     defined(BCM_56450_B1)
  43319     { /* SOC_REG_INT_LLS_CLEAR_S1_CREDITSr */
  43320         soc_block_list[85],
  43321         soc_genreg,
  43322         1,
  43323         0,
  43324         0x2005900,
  43325         0,
  43326         0,
  43327         2,
  43328         soc_LLS_CLEAR_S1_CREDITSr_fields,
  43329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43330         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  43331         -1,
  43332         -1,
  43333     },
  43334 #endif /* chips */
  43335 
  43336 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  43337     { /* SOC_REG_INT_LLS_CLEAR_S1_CREDITS_BCM56260_A0r */
  43338         soc_block_list[85],
  43339         soc_genreg,
  43340         1,
  43341         0,
  43342         0x2005c00,
  43343         0,
  43344         0,
  43345         2,
  43346         soc_LLS_CLEAR_S1_CREDITS_BCM56260_A0r_fields,
  43347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43348         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43349         -1,
  43350         -1,
  43351     },
  43352 #endif /* chips */
  43353 
  43354 #if defined(BCM_56270_A0)
  43355     { /* SOC_REG_INT_LLS_CLEAR_S1_CREDITS_BCM56270_A0r */
  43356         soc_block_list[85],
  43357         soc_genreg,
  43358         1,
  43359         0,
  43360         0x2005800,
  43361         0,
  43362         0,
  43363         2,
  43364         soc_LLS_CLEAR_S1_CREDITS_BCM56260_A0r_fields,
  43365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43366         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43367         -1,
  43368         -1,
  43369     },
  43370 #endif /* chips */
  43371 
  43372 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  43373     { /* SOC_REG_INT_LLS_COE_CPU_READ_S1_CREDITr */
  43374         soc_block_list[85],
  43375         soc_genreg,
  43376         1,
  43377         0,
  43378         0x2008600,
  43379         0,
  43380         0,
  43381         1,
  43382         soc_LLS_COE_CPU_READ_S1_CREDITr_fields,
  43383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43384         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  43385         -1,
  43386         -1,
  43387     },
  43388 #endif /* chips */
  43389 
  43390 #if defined(BCM_56270_A0)
  43391     { /* SOC_REG_INT_LLS_COE_CPU_READ_S1_CREDIT_BCM56270_A0r */
  43392         soc_block_list[85],
  43393         soc_genreg,
  43394         1,
  43395         0,
  43396         0x2006e00,
  43397         0,
  43398         0,
  43399         1,
  43400         soc_LLS_COE_CPU_READ_S1_CREDITr_fields,
  43401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43402         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  43403         -1,
  43404         -1,
  43405     },
  43406 #endif /* chips */
  43407 
  43408 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  43409     { /* SOC_REG_INT_LLS_COE_CREDIT_READ_IDr */
  43410         soc_block_list[85],
  43411         soc_genreg,
  43412         1,
  43413         0,
  43414         0x2008500,
  43415         0,
  43416         0,
  43417         1,
  43418         soc_LLS_COE_CREDIT_READ_IDr_fields,
  43419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43420         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  43421         -1,
  43422         -1,
  43423     },
  43424 #endif /* chips */
  43425 
  43426 #if defined(BCM_56270_A0)
  43427     { /* SOC_REG_INT_LLS_COE_CREDIT_READ_ID_BCM56270_A0r */
  43428         soc_block_list[85],
  43429         soc_genreg,
  43430         1,
  43431         0,
  43432         0x2006d00,
  43433         0,
  43434         0,
  43435         1,
  43436         soc_LLS_COE_CREDIT_READ_IDr_fields,
  43437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43438         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  43439         -1,
  43440         -1,
  43441     },
  43442 #endif /* chips */
  43443 
  43444 #if defined(BCM_56440_A0)
  43445     { /* SOC_REG_INT_LLS_CONFIG0r */
  43446         soc_block_list[85],
  43447         soc_genreg,
  43448         1,
  43449         0,
  43450         0x80003,
  43451         0,
  43452         0,
  43453         6,
  43454         soc_LLS_CONFIG0r_fields,
  43455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43456         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  43457         -1,
  43458         -1,
  43459     },
  43460 #endif /* chips */
  43461 
  43462 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43463     defined(BCM_56270_A0)
  43464     { /* SOC_REG_INT_LLS_CONFIG0_BCM56260_A0r */
  43465         soc_block_list[85],
  43466         soc_genreg,
  43467         1,
  43468         0,
  43469         0x2000300,
  43470         0,
  43471         0,
  43472         9,
  43473         soc_LLS_CONFIG0_BCM56260_A0r_fields,
  43474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43475         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  43476         -1,
  43477         -1,
  43478     },
  43479 #endif /* chips */
  43480 
  43481 #if defined(BCM_56440_B0)
  43482     { /* SOC_REG_INT_LLS_CONFIG0_BCM56440_B0r */
  43483         soc_block_list[85],
  43484         soc_genreg,
  43485         1,
  43486         0,
  43487         0x80003,
  43488         0,
  43489         0,
  43490         9,
  43491         soc_LLS_CONFIG0_BCM56440_B0r_fields,
  43492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43493         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  43494         -1,
  43495         -1,
  43496     },
  43497 #endif /* chips */
  43498 
  43499 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43500     defined(BCM_56450_B1)
  43501     { /* SOC_REG_INT_LLS_CONFIG0_BCM56450_A0r */
  43502         soc_block_list[85],
  43503         soc_genreg,
  43504         1,
  43505         0,
  43506         0x2000300,
  43507         0,
  43508         0,
  43509         9,
  43510         soc_LLS_CONFIG0_BCM56450_A0r_fields,
  43511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43512         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  43513         -1,
  43514         -1,
  43515     },
  43516 #endif /* chips */
  43517 
  43518 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  43519     { /* SOC_REG_INT_LLS_CONFIG0_BCM56560_A0r */
  43520         soc_block_list[4],
  43521         soc_genreg,
  43522         1,
  43523         0,
  43524         0x62000300,
  43525         0,
  43526         0,
  43527         9,
  43528         soc_LLS_CONFIG0_BCM56560_A0r_fields,
  43529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43530         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  43531         -1,
  43532         -1,
  43533     },
  43534 #endif /* chips */
  43535 
  43536 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  43537     { /* SOC_REG_INT_LLS_CONFIG0_BCM56640_A0r */
  43538         soc_block_list[4],
  43539         soc_genreg,
  43540         1,
  43541         0,
  43542         0x5a000200,
  43543         0,
  43544         0,
  43545         12,
  43546         soc_LLS_CONFIG0_BCM56640_A0r_fields,
  43547         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  43548         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  43549         -1,
  43550         -1,
  43551     },
  43552 #endif /* chips */
  43553 
  43554 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  43555     { /* SOC_REG_INT_LLS_CONFIG_SPAREr */
  43556         soc_block_list[4],
  43557         soc_genreg,
  43558         1,
  43559         0,
  43560         0x5a00ac00,
  43561         0,
  43562         0,
  43563         1,
  43564         soc_LLS_CONFIG_SPAREr_fields,
  43565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43566         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43567         -1,
  43568         -1,
  43569     },
  43570 #endif /* chips */
  43571 
  43572 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  43573     { /* SOC_REG_INT_LLS_CONFIG_SP_MIN_PRIORITYr */
  43574         soc_block_list[85],
  43575         soc_genreg,
  43576         1,
  43577         0,
  43578         0x8000c,
  43579         0,
  43580         0,
  43581         3,
  43582         soc_LLS_CONFIG_SP_MIN_PRIORITYr_fields,
  43583         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  43584         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43585         -1,
  43586         -1,
  43587     },
  43588 #endif /* chips */
  43589 
  43590 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43591     defined(BCM_56270_A0)
  43592     { /* SOC_REG_INT_LLS_CONFIG_SP_MIN_PRIORITY_BCM56260_A0r */
  43593         soc_block_list[85],
  43594         soc_genreg,
  43595         1,
  43596         0,
  43597         0x2001000,
  43598         0,
  43599         0,
  43600         3,
  43601         soc_LLS_CONFIG_SP_MIN_PRIORITY_BCM56560_A0r_fields,
  43602         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  43603         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43604         -1,
  43605         -1,
  43606     },
  43607 #endif /* chips */
  43608 
  43609 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43610     defined(BCM_56450_B1)
  43611     { /* SOC_REG_INT_LLS_CONFIG_SP_MIN_PRIORITY_BCM56450_A0r */
  43612         soc_block_list[85],
  43613         soc_genreg,
  43614         1,
  43615         0,
  43616         0x2001000,
  43617         0,
  43618         0,
  43619         3,
  43620         soc_LLS_CONFIG_SP_MIN_PRIORITY_BCM56450_A0r_fields,
  43621         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  43622         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43623         -1,
  43624         -1,
  43625     },
  43626 #endif /* chips */
  43627 
  43628 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  43629     { /* SOC_REG_INT_LLS_CONFIG_SP_MIN_PRIORITY_BCM56560_A0r */
  43630         soc_block_list[4],
  43631         soc_genreg,
  43632         1,
  43633         0,
  43634         0x62000c00,
  43635         0,
  43636         0,
  43637         3,
  43638         soc_LLS_CONFIG_SP_MIN_PRIORITY_BCM56560_A0r_fields,
  43639         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  43640         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43641         -1,
  43642         -1,
  43643     },
  43644 #endif /* chips */
  43645 
  43646 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  43647     { /* SOC_REG_INT_LLS_CONFIG_SP_MIN_PRIORITY_BCM56640_A0r */
  43648         soc_block_list[4],
  43649         soc_genreg,
  43650         1,
  43651         0,
  43652         0x5a000600,
  43653         0,
  43654         0,
  43655         3,
  43656         soc_LLS_CONFIG_SP_MIN_PRIORITY_BCM56640_A0r_fields,
  43657         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  43658         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  43659         -1,
  43660         -1,
  43661     },
  43662 #endif /* chips */
  43663 
  43664 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  43665     { /* SOC_REG_INT_LLS_DEBUG_DEQ_BLOCKr */
  43666         soc_block_list[85],
  43667         soc_genreg,
  43668         1,
  43669         0,
  43670         0x80011,
  43671         0,
  43672         0,
  43673         4,
  43674         soc_LLS_DEBUG_DEQ_BLOCKr_fields,
  43675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43676         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  43677         -1,
  43678         -1,
  43679     },
  43680 #endif /* chips */
  43681 
  43682 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43683     defined(BCM_56270_A0)
  43684     { /* SOC_REG_INT_LLS_DEBUG_DEQ_BLOCK_BCM56260_A0r */
  43685         soc_block_list[85],
  43686         soc_genreg,
  43687         1,
  43688         0,
  43689         0x2001500,
  43690         0,
  43691         0,
  43692         7,
  43693         soc_LLS_DEBUG_DEQ_BLOCK_BCM56560_A0r_fields,
  43694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43695         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  43696         -1,
  43697         -1,
  43698     },
  43699 #endif /* chips */
  43700 
  43701 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43702     defined(BCM_56450_B1)
  43703     { /* SOC_REG_INT_LLS_DEBUG_DEQ_BLOCK_BCM56450_A0r */
  43704         soc_block_list[85],
  43705         soc_genreg,
  43706         1,
  43707         0,
  43708         0x2001500,
  43709         0,
  43710         0,
  43711         4,
  43712         soc_LLS_DEBUG_DEQ_BLOCK_BCM56450_A0r_fields,
  43713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43714         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  43715         -1,
  43716         -1,
  43717     },
  43718 #endif /* chips */
  43719 
  43720 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  43721     { /* SOC_REG_INT_LLS_DEBUG_DEQ_BLOCK_BCM56560_A0r */
  43722         soc_block_list[4],
  43723         soc_genreg,
  43724         1,
  43725         0,
  43726         0x62001100,
  43727         0,
  43728         0,
  43729         7,
  43730         soc_LLS_DEBUG_DEQ_BLOCK_BCM56560_A0r_fields,
  43731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43732         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  43733         -1,
  43734         -1,
  43735     },
  43736 #endif /* chips */
  43737 
  43738 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  43739     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L0r */
  43740         soc_block_list[85],
  43741         soc_genreg,
  43742         1,
  43743         0,
  43744         0x8000e,
  43745         0,
  43746         0,
  43747         1,
  43748         soc_LLS_DEBUG_ENQ_BLOCK_ON_L0r_fields,
  43749         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  43750         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43751         -1,
  43752         -1,
  43753     },
  43754 #endif /* chips */
  43755 
  43756 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  43757     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L1r */
  43758         soc_block_list[85],
  43759         soc_genreg,
  43760         1,
  43761         0,
  43762         0x8000f,
  43763         0,
  43764         0,
  43765         1,
  43766         soc_LLS_DEBUG_ENQ_BLOCK_ON_L1r_fields,
  43767         SOC_RESET_VAL_DEC(0x00004008, 0x00000000)
  43768         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43769         -1,
  43770         -1,
  43771     },
  43772 #endif /* chips */
  43773 
  43774 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  43775     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L2r */
  43776         soc_block_list[85],
  43777         soc_genreg,
  43778         1,
  43779         0,
  43780         0x80010,
  43781         0,
  43782         0,
  43783         1,
  43784         soc_LLS_DEBUG_ENQ_BLOCK_ON_L2r_fields,
  43785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43786         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43787         -1,
  43788         -1,
  43789     },
  43790 #endif /* chips */
  43791 
  43792 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43793     defined(BCM_56270_A0)
  43794     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L0_BCM56260_A0r */
  43795         soc_block_list[85],
  43796         soc_genreg,
  43797         1,
  43798         0,
  43799         0x2001200,
  43800         0,
  43801         0,
  43802         1,
  43803         soc_LLS_DEBUG_ENQ_BLOCK_ON_L0_BCM56560_A0r_fields,
  43804         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  43805         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43806         -1,
  43807         -1,
  43808     },
  43809 #endif /* chips */
  43810 
  43811 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43812     defined(BCM_56450_B1)
  43813     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L0_BCM56450_A0r */
  43814         soc_block_list[85],
  43815         soc_genreg,
  43816         1,
  43817         0,
  43818         0x2001200,
  43819         0,
  43820         0,
  43821         1,
  43822         soc_LLS_DEBUG_ENQ_BLOCK_ON_L0_BCM56640_A0r_fields,
  43823         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  43824         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43825         -1,
  43826         -1,
  43827     },
  43828 #endif /* chips */
  43829 
  43830 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  43831     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L0_BCM56560_A0r */
  43832         soc_block_list[4],
  43833         soc_genreg,
  43834         1,
  43835         0,
  43836         0x62000e00,
  43837         0,
  43838         0,
  43839         1,
  43840         soc_LLS_DEBUG_ENQ_BLOCK_ON_L0_BCM56560_A0r_fields,
  43841         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  43842         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43843         -1,
  43844         -1,
  43845     },
  43846 #endif /* chips */
  43847 
  43848 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  43849     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L0_BCM56640_A0r */
  43850         soc_block_list[4],
  43851         soc_genreg,
  43852         1,
  43853         0,
  43854         0x5a000900,
  43855         0,
  43856         0,
  43857         1,
  43858         soc_LLS_DEBUG_ENQ_BLOCK_ON_L0_BCM56640_A0r_fields,
  43859         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  43860         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43861         -1,
  43862         -1,
  43863     },
  43864 #endif /* chips */
  43865 
  43866 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43867     defined(BCM_56270_A0)
  43868     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L1_BCM56260_A0r */
  43869         soc_block_list[85],
  43870         soc_genreg,
  43871         1,
  43872         0,
  43873         0x2001300,
  43874         0,
  43875         0,
  43876         1,
  43877         soc_LLS_DEBUG_ENQ_BLOCK_ON_L1_BCM56560_A0r_fields,
  43878         SOC_RESET_VAL_DEC(0x00004008, 0x00000000)
  43879         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43880         -1,
  43881         -1,
  43882     },
  43883 #endif /* chips */
  43884 
  43885 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43886     defined(BCM_56450_B1)
  43887     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L1_BCM56450_A0r */
  43888         soc_block_list[85],
  43889         soc_genreg,
  43890         1,
  43891         0,
  43892         0x2001300,
  43893         0,
  43894         0,
  43895         1,
  43896         soc_LLS_DEBUG_ENQ_BLOCK_ON_L1_BCM56640_A0r_fields,
  43897         SOC_RESET_VAL_DEC(0x00004008, 0x00000000)
  43898         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43899         -1,
  43900         -1,
  43901     },
  43902 #endif /* chips */
  43903 
  43904 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  43905     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L1_BCM56560_A0r */
  43906         soc_block_list[4],
  43907         soc_genreg,
  43908         1,
  43909         0,
  43910         0x62000f00,
  43911         0,
  43912         0,
  43913         1,
  43914         soc_LLS_DEBUG_ENQ_BLOCK_ON_L1_BCM56560_A0r_fields,
  43915         SOC_RESET_VAL_DEC(0x00004008, 0x00000000)
  43916         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43917         -1,
  43918         -1,
  43919     },
  43920 #endif /* chips */
  43921 
  43922 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  43923     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L1_BCM56640_A0r */
  43924         soc_block_list[4],
  43925         soc_genreg,
  43926         1,
  43927         0,
  43928         0x5a000a00,
  43929         0,
  43930         0,
  43931         1,
  43932         soc_LLS_DEBUG_ENQ_BLOCK_ON_L1_BCM56640_A0r_fields,
  43933         SOC_RESET_VAL_DEC(0x00004008, 0x00000000)
  43934         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43935         -1,
  43936         -1,
  43937     },
  43938 #endif /* chips */
  43939 
  43940 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  43941     defined(BCM_56270_A0)
  43942     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L2_BCM56260_A0r */
  43943         soc_block_list[85],
  43944         soc_genreg,
  43945         1,
  43946         0,
  43947         0x2001400,
  43948         0,
  43949         0,
  43950         1,
  43951         soc_LLS_DEBUG_ENQ_BLOCK_ON_L2_BCM56560_A0r_fields,
  43952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43953         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43954         -1,
  43955         -1,
  43956     },
  43957 #endif /* chips */
  43958 
  43959 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43960     defined(BCM_56450_B1)
  43961     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L2_BCM56450_A0r */
  43962         soc_block_list[85],
  43963         soc_genreg,
  43964         1,
  43965         0,
  43966         0x2001400,
  43967         0,
  43968         0,
  43969         1,
  43970         soc_LLS_DEBUG_ENQ_BLOCK_ON_L2_BCM56640_A0r_fields,
  43971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43972         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43973         -1,
  43974         -1,
  43975     },
  43976 #endif /* chips */
  43977 
  43978 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  43979     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L2_BCM56560_A0r */
  43980         soc_block_list[4],
  43981         soc_genreg,
  43982         1,
  43983         0,
  43984         0x62001000,
  43985         0,
  43986         0,
  43987         1,
  43988         soc_LLS_DEBUG_ENQ_BLOCK_ON_L2_BCM56560_A0r_fields,
  43989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43990         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  43991         -1,
  43992         -1,
  43993     },
  43994 #endif /* chips */
  43995 
  43996 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  43997     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_L2_BCM56640_A0r */
  43998         soc_block_list[4],
  43999         soc_genreg,
  44000         1,
  44001         0,
  44002         0x5a000b00,
  44003         0,
  44004         0,
  44005         1,
  44006         soc_LLS_DEBUG_ENQ_BLOCK_ON_L2_BCM56640_A0r_fields,
  44007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44008         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  44009         -1,
  44010         -1,
  44011     },
  44012 #endif /* chips */
  44013 
  44014 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  44015     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_PORTr */
  44016         soc_block_list[85],
  44017         soc_genreg,
  44018         1,
  44019         0,
  44020         0x8000d,
  44021         0,
  44022         0,
  44023         1,
  44024         soc_LLS_DEBUG_ENQ_BLOCK_ON_PORTr_fields,
  44025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44026         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  44027         -1,
  44028         -1,
  44029     },
  44030 #endif /* chips */
  44031 
  44032 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  44033     defined(BCM_56270_A0)
  44034     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_PORT_BCM56260_A0r */
  44035         soc_block_list[85],
  44036         soc_genreg,
  44037         1,
  44038         0,
  44039         0x2001100,
  44040         0,
  44041         0,
  44042         1,
  44043         soc_LLS_DEBUG_ENQ_BLOCK_ON_PORT_BCM56560_A0r_fields,
  44044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44045         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  44046         -1,
  44047         -1,
  44048     },
  44049 #endif /* chips */
  44050 
  44051 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44052     defined(BCM_56450_B1)
  44053     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_PORT_BCM56450_A0r */
  44054         soc_block_list[85],
  44055         soc_genreg,
  44056         1,
  44057         0,
  44058         0x2001100,
  44059         0,
  44060         0,
  44061         1,
  44062         soc_LLS_DEBUG_ENQ_BLOCK_ON_PORT_BCM56640_A0r_fields,
  44063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44064         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  44065         -1,
  44066         -1,
  44067     },
  44068 #endif /* chips */
  44069 
  44070 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44071     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_PORT_BCM56560_A0r */
  44072         soc_block_list[4],
  44073         soc_genreg,
  44074         1,
  44075         0,
  44076         0x62000d00,
  44077         0,
  44078         0,
  44079         1,
  44080         soc_LLS_DEBUG_ENQ_BLOCK_ON_PORT_BCM56560_A0r_fields,
  44081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44082         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  44083         -1,
  44084         -1,
  44085     },
  44086 #endif /* chips */
  44087 
  44088 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  44089     { /* SOC_REG_INT_LLS_DEBUG_ENQ_BLOCK_ON_PORT_BCM56640_A0r */
  44090         soc_block_list[4],
  44091         soc_genreg,
  44092         1,
  44093         0,
  44094         0x5a000800,
  44095         0,
  44096         0,
  44097         1,
  44098         soc_LLS_DEBUG_ENQ_BLOCK_ON_PORT_BCM56640_A0r_fields,
  44099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44100         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  44101         -1,
  44102         -1,
  44103     },
  44104 #endif /* chips */
  44105 
  44106 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44107     { /* SOC_REG_INT_LLS_DEBUG_FORCE_CPU_COSMASK0r */
  44108         soc_block_list[4],
  44109         soc_genreg,
  44110         1,
  44111         0,
  44112         0x62004200,
  44113         0,
  44114         0,
  44115         1,
  44116         soc_LLS_DEBUG_FORCE_CPU_COSMASK0r_fields,
  44117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44118         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44119         -1,
  44120         -1,
  44121     },
  44122 #endif /* chips */
  44123 
  44124 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44125     { /* SOC_REG_INT_LLS_DEBUG_FORCE_CPU_COSMASK1r */
  44126         soc_block_list[4],
  44127         soc_genreg,
  44128         1,
  44129         0,
  44130         0x62004300,
  44131         0,
  44132         0,
  44133         1,
  44134         soc_LLS_DEBUG_FORCE_CPU_COSMASK1r_fields,
  44135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44137         -1,
  44138         -1,
  44139     },
  44140 #endif /* chips */
  44141 
  44142 #if defined(BCM_56440_A0)
  44143     { /* SOC_REG_INT_LLS_DEBUG_INJECT_ACTIVATIONr */
  44144         soc_block_list[85],
  44145         soc_genreg,
  44146         1,
  44147         0,
  44148         0x80037,
  44149         0,
  44150         0,
  44151         4,
  44152         soc_LLS_DEBUG_INJECT_ACTIVATIONr_fields,
  44153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44154         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  44155         -1,
  44156         -1,
  44157     },
  44158 #endif /* chips */
  44159 
  44160 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  44161     { /* SOC_REG_INT_LLS_DEBUG_INJECT_ACTIVATION_BCM56260_A0r */
  44162         soc_block_list[85],
  44163         soc_genreg,
  44164         1,
  44165         0,
  44166         0x2008700,
  44167         0,
  44168         0,
  44169         4,
  44170         soc_LLS_DEBUG_INJECT_ACTIVATION_BCM56260_A0r_fields,
  44171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44172         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  44173         -1,
  44174         -1,
  44175     },
  44176 #endif /* chips */
  44177 
  44178 #if defined(BCM_56270_A0)
  44179     { /* SOC_REG_INT_LLS_DEBUG_INJECT_ACTIVATION_BCM56270_A0r */
  44180         soc_block_list[85],
  44181         soc_genreg,
  44182         1,
  44183         0,
  44184         0x2006f00,
  44185         0,
  44186         0,
  44187         4,
  44188         soc_LLS_DEBUG_INJECT_ACTIVATION_BCM56270_A0r_fields,
  44189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44190         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  44191         -1,
  44192         -1,
  44193     },
  44194 #endif /* chips */
  44195 
  44196 #if defined(BCM_56440_B0)
  44197     { /* SOC_REG_INT_LLS_DEBUG_INJECT_ACTIVATION_BCM56440_B0r */
  44198         soc_block_list[85],
  44199         soc_genreg,
  44200         1,
  44201         0,
  44202         0x8003f,
  44203         0,
  44204         0,
  44205         4,
  44206         soc_LLS_DEBUG_INJECT_ACTIVATIONr_fields,
  44207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44208         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  44209         -1,
  44210         -1,
  44211     },
  44212 #endif /* chips */
  44213 
  44214 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44215     defined(BCM_56450_B1)
  44216     { /* SOC_REG_INT_LLS_DEBUG_INJECT_ACTIVATION_BCM56450_A0r */
  44217         soc_block_list[85],
  44218         soc_genreg,
  44219         1,
  44220         0,
  44221         0x2010900,
  44222         0,
  44223         0,
  44224         4,
  44225         soc_LLS_DEBUG_INJECT_ACTIVATION_BCM56450_A0r_fields,
  44226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44227         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  44228         -1,
  44229         -1,
  44230     },
  44231 #endif /* chips */
  44232 
  44233 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44234     { /* SOC_REG_INT_LLS_DEBUG_INJECT_ACTIVATION_BCM56560_A0r */
  44235         soc_block_list[4],
  44236         soc_genreg,
  44237         1,
  44238         0,
  44239         0x62003700,
  44240         0,
  44241         0,
  44242         4,
  44243         soc_LLS_DEBUG_INJECT_ACTIVATION_BCM56560_A0r_fields,
  44244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44245         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  44246         -1,
  44247         -1,
  44248     },
  44249 #endif /* chips */
  44250 
  44251 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  44252     { /* SOC_REG_INT_LLS_DEBUG_INJECT_ACTIVATION_BCM56640_A0r */
  44253         soc_block_list[4],
  44254         soc_genreg,
  44255         1,
  44256         0,
  44257         0x5a000c00,
  44258         0,
  44259         0,
  44260         4,
  44261         soc_LLS_DEBUG_INJECT_ACTIVATION_BCM56640_A0r_fields,
  44262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44264         -1,
  44265         -1,
  44266     },
  44267 #endif /* chips */
  44268 
  44269 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44270     { /* SOC_REG_INT_LLS_DEBUG_INJECT_FLOWCONTROL1r */
  44271         soc_block_list[4],
  44272         soc_genreg,
  44273         1,
  44274         0,
  44275         0x62003900,
  44276         0,
  44277         0,
  44278         2,
  44279         soc_LLS_DEBUG_INJECT_FLOWCONTROL1r_fields,
  44280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44282         -1,
  44283         -1,
  44284     },
  44285 #endif /* chips */
  44286 
  44287 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44288     { /* SOC_REG_INT_LLS_DEBUG_INJECT_FLOWCONTROL2r */
  44289         soc_block_list[4],
  44290         soc_genreg,
  44291         1,
  44292         0,
  44293         0x62003a00,
  44294         0,
  44295         0,
  44296         2,
  44297         soc_LLS_DEBUG_INJECT_FLOWCONTROL1r_fields,
  44298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44300         -1,
  44301         -1,
  44302     },
  44303 #endif /* chips */
  44304 
  44305 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44306     { /* SOC_REG_INT_LLS_DEBUG_INJECT_FLOWCONTROL3r */
  44307         soc_block_list[4],
  44308         soc_genreg,
  44309         1,
  44310         0,
  44311         0x62003b00,
  44312         0,
  44313         0,
  44314         4,
  44315         soc_LLS_DEBUG_INJECT_FLOWCONTROL3r_fields,
  44316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44317         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  44318         -1,
  44319         -1,
  44320     },
  44321 #endif /* chips */
  44322 
  44323 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  44324     { /* SOC_REG_INT_LLS_DEBUG_INJECT_FLOWCONTROL1_BCM56260_A0r */
  44325         soc_block_list[85],
  44326         soc_genreg,
  44327         1,
  44328         0,
  44329         0x2008a00,
  44330         0,
  44331         0,
  44332         2,
  44333         soc_LLS_DEBUG_INJECT_FLOWCONTROL1r_fields,
  44334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44336         -1,
  44337         -1,
  44338     },
  44339 #endif /* chips */
  44340 
  44341 #if defined(BCM_56270_A0)
  44342     { /* SOC_REG_INT_LLS_DEBUG_INJECT_FLOWCONTROL1_BCM56270_A0r */
  44343         soc_block_list[85],
  44344         soc_genreg,
  44345         1,
  44346         0,
  44347         0x2007100,
  44348         0,
  44349         0,
  44350         2,
  44351         soc_LLS_DEBUG_INJECT_FLOWCONTROL1r_fields,
  44352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44354         -1,
  44355         -1,
  44356     },
  44357 #endif /* chips */
  44358 
  44359 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  44360     { /* SOC_REG_INT_LLS_DEBUG_INJECT_FLOWCONTROL2_BCM56260_A0r */
  44361         soc_block_list[85],
  44362         soc_genreg,
  44363         1,
  44364         0,
  44365         0x2008b00,
  44366         0,
  44367         0,
  44368         2,
  44369         soc_LLS_DEBUG_INJECT_FLOWCONTROL1r_fields,
  44370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44372         -1,
  44373         -1,
  44374     },
  44375 #endif /* chips */
  44376 
  44377 #if defined(BCM_56270_A0)
  44378     { /* SOC_REG_INT_LLS_DEBUG_INJECT_FLOWCONTROL2_BCM56270_A0r */
  44379         soc_block_list[85],
  44380         soc_genreg,
  44381         1,
  44382         0,
  44383         0x2007200,
  44384         0,
  44385         0,
  44386         2,
  44387         soc_LLS_DEBUG_INJECT_FLOWCONTROL1r_fields,
  44388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44389         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44390         -1,
  44391         -1,
  44392     },
  44393 #endif /* chips */
  44394 
  44395 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  44396     { /* SOC_REG_INT_LLS_DEBUG_INJECT_FLOWCONTROL3_BCM56260_A0r */
  44397         soc_block_list[85],
  44398         soc_genreg,
  44399         1,
  44400         0,
  44401         0x2008c00,
  44402         0,
  44403         0,
  44404         4,
  44405         soc_LLS_DEBUG_INJECT_FLOWCONTROL3_BCM56260_A0r_fields,
  44406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44407         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  44408         -1,
  44409         -1,
  44410     },
  44411 #endif /* chips */
  44412 
  44413 #if defined(BCM_56270_A0)
  44414     { /* SOC_REG_INT_LLS_DEBUG_INJECT_FLOWCONTROL3_BCM56270_A0r */
  44415         soc_block_list[85],
  44416         soc_genreg,
  44417         1,
  44418         0,
  44419         0x2007300,
  44420         0,
  44421         0,
  44422         4,
  44423         soc_LLS_DEBUG_INJECT_FLOWCONTROL3_BCM56270_A0r_fields,
  44424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44425         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  44426         -1,
  44427         -1,
  44428     },
  44429 #endif /* chips */
  44430 
  44431 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44432     defined(BCM_56450_B1)
  44433     { /* SOC_REG_INT_LLS_DEBUG_INJECT_S0_MAX_ACTIVATIONr */
  44434         soc_block_list[85],
  44435         soc_genreg,
  44436         1,
  44437         0,
  44438         0x2010b00,
  44439         0,
  44440         0,
  44441         2,
  44442         soc_LLS_DEBUG_INJECT_S0_MAX_ACTIVATIONr_fields,
  44443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44444         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  44445         -1,
  44446         -1,
  44447     },
  44448 #endif /* chips */
  44449 
  44450 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  44451     { /* SOC_REG_INT_LLS_DEBUG_INJECT_S0_MAX_ACTIVATION_BCM56260_A0r */
  44452         soc_block_list[85],
  44453         soc_genreg,
  44454         1,
  44455         0,
  44456         0x2008800,
  44457         0,
  44458         0,
  44459         2,
  44460         soc_LLS_DEBUG_INJECT_S0_MAX_ACTIVATION_BCM56260_A0r_fields,
  44461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44462         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  44463         -1,
  44464         -1,
  44465     },
  44466 #endif /* chips */
  44467 
  44468 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44469     defined(BCM_56450_B1)
  44470     { /* SOC_REG_INT_LLS_DEBUG_INJECT_S1_MAX_ACTIVATIONr */
  44471         soc_block_list[85],
  44472         soc_genreg,
  44473         1,
  44474         0,
  44475         0x2010a00,
  44476         0,
  44477         0,
  44478         2,
  44479         soc_LLS_DEBUG_INJECT_S1_MAX_ACTIVATIONr_fields,
  44480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44481         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  44482         -1,
  44483         -1,
  44484     },
  44485 #endif /* chips */
  44486 
  44487 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  44488     { /* SOC_REG_INT_LLS_DEBUG_INJECT_S1_MAX_ACTIVATION_BCM56260_A0r */
  44489         soc_block_list[85],
  44490         soc_genreg,
  44491         1,
  44492         0,
  44493         0x2008900,
  44494         0,
  44495         0,
  44496         2,
  44497         soc_LLS_DEBUG_INJECT_S1_MAX_ACTIVATION_BCM56260_A0r_fields,
  44498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44499         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  44500         -1,
  44501         -1,
  44502     },
  44503 #endif /* chips */
  44504 
  44505 #if defined(BCM_56270_A0)
  44506     { /* SOC_REG_INT_LLS_DEBUG_INJECT_S1_MAX_ACTIVATION_BCM56270_A0r */
  44507         soc_block_list[85],
  44508         soc_genreg,
  44509         1,
  44510         0,
  44511         0x2007000,
  44512         0,
  44513         0,
  44514         2,
  44515         soc_LLS_DEBUG_INJECT_S1_MAX_ACTIVATION_BCM56270_A0r_fields,
  44516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44517         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  44518         -1,
  44519         -1,
  44520     },
  44521 #endif /* chips */
  44522 
  44523 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44524     { /* SOC_REG_INT_LLS_DEBUG_INJECT_S1_MAX_ACTIVATION_BCM56560_A0r */
  44525         soc_block_list[4],
  44526         soc_genreg,
  44527         1,
  44528         0,
  44529         0x62003800,
  44530         0,
  44531         0,
  44532         2,
  44533         soc_LLS_DEBUG_INJECT_S1_MAX_ACTIVATION_BCM56560_A0r_fields,
  44534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44535         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44536         -1,
  44537         -1,
  44538     },
  44539 #endif /* chips */
  44540 
  44541 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  44542     { /* SOC_REG_INT_LLS_DEBUG_P_WERR_MAX_SC_RESETr */
  44543         soc_block_list[4],
  44544         soc_genreg,
  44545         1,
  44546         0,
  44547         0x5a009f00,
  44548         0,
  44549         0,
  44550         1,
  44551         soc_LLS_DEBUG_P_WERR_MAX_SC_RESETr_fields,
  44552         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  44553         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  44554         -1,
  44555         -1,
  44556     },
  44557 #endif /* chips */
  44558 
  44559 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44560     { /* SOC_REG_INT_LLS_DEBUG_P_WERR_MAX_SC_RESET_BCM56560_A0r */
  44561         soc_block_list[4],
  44562         soc_genreg,
  44563         1,
  44564         0,
  44565         0x62001200,
  44566         0,
  44567         0,
  44568         3,
  44569         soc_LLS_DEBUG_P_WERR_MAX_SC_RESET_BCM56560_A0r_fields,
  44570         SOC_RESET_VAL_DEC(0x000000fd, 0x00000000)
  44571         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  44572         -1,
  44573         -1,
  44574     },
  44575 #endif /* chips */
  44576 
  44577 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  44578     defined(BCM_56270_A0)
  44579     { /* SOC_REG_INT_LLS_DEBUG_WRR_CTRLr */
  44580         soc_block_list[85],
  44581         soc_genreg,
  44582         1,
  44583         0,
  44584         0x2001600,
  44585         0,
  44586         0,
  44587         3,
  44588         soc_LLS_DEBUG_P_WERR_MAX_SC_RESET_BCM56560_A0r_fields,
  44589         SOC_RESET_VAL_DEC(0x000000fd, 0x00000000)
  44590         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  44591         -1,
  44592         -1,
  44593     },
  44594 #endif /* chips */
  44595 
  44596 #if defined(BCM_56440_A0)
  44597     { /* SOC_REG_INT_LLS_DEQUEUE_EVENT_SEENr */
  44598         soc_block_list[85],
  44599         soc_genreg,
  44600         1,
  44601         0,
  44602         0x80039,
  44603         0,
  44604         0,
  44605         25,
  44606         soc_LLS_DEQUEUE_EVENT_SEENr_fields,
  44607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44608         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  44609         -1,
  44610         -1,
  44611     },
  44612 #endif /* chips */
  44613 
  44614 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  44615     { /* SOC_REG_INT_LLS_DEQUEUE_EVENT_SEEN_BCM56260_A0r */
  44616         soc_block_list[85],
  44617         soc_genreg,
  44618         1,
  44619         0,
  44620         0x2008e00,
  44621         0,
  44622         0,
  44623         25,
  44624         soc_LLS_DEQUEUE_EVENT_SEEN_BCM56560_A0r_fields,
  44625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44626         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  44627         -1,
  44628         -1,
  44629     },
  44630 #endif /* chips */
  44631 
  44632 #if defined(BCM_56270_A0)
  44633     { /* SOC_REG_INT_LLS_DEQUEUE_EVENT_SEEN_BCM56270_A0r */
  44634         soc_block_list[85],
  44635         soc_genreg,
  44636         1,
  44637         0,
  44638         0x2007500,
  44639         0,
  44640         0,
  44641         25,
  44642         soc_LLS_DEQUEUE_EVENT_SEEN_BCM56560_A0r_fields,
  44643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44644         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  44645         -1,
  44646         -1,
  44647     },
  44648 #endif /* chips */
  44649 
  44650 #if defined(BCM_56440_B0)
  44651     { /* SOC_REG_INT_LLS_DEQUEUE_EVENT_SEEN_BCM56440_B0r */
  44652         soc_block_list[85],
  44653         soc_genreg,
  44654         1,
  44655         0,
  44656         0x80041,
  44657         0,
  44658         0,
  44659         25,
  44660         soc_LLS_DEQUEUE_EVENT_SEENr_fields,
  44661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44662         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  44663         -1,
  44664         -1,
  44665     },
  44666 #endif /* chips */
  44667 
  44668 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44669     defined(BCM_56450_B1)
  44670     { /* SOC_REG_INT_LLS_DEQUEUE_EVENT_SEEN_BCM56450_A0r */
  44671         soc_block_list[85],
  44672         soc_genreg,
  44673         1,
  44674         0,
  44675         0x2010d00,
  44676         0,
  44677         0,
  44678         25,
  44679         soc_LLS_DEQUEUE_EVENT_SEEN_BCM56450_A0r_fields,
  44680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44681         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  44682         -1,
  44683         -1,
  44684     },
  44685 #endif /* chips */
  44686 
  44687 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44688     { /* SOC_REG_INT_LLS_DEQUEUE_EVENT_SEEN_BCM56560_A0r */
  44689         soc_block_list[4],
  44690         soc_genreg,
  44691         1,
  44692         0,
  44693         0x62003d00,
  44694         0,
  44695         0,
  44696         25,
  44697         soc_LLS_DEQUEUE_EVENT_SEEN_BCM56560_A0r_fields,
  44698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44699         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  44700         -1,
  44701         -1,
  44702     },
  44703 #endif /* chips */
  44704 
  44705 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  44706     { /* SOC_REG_INT_LLS_DEQUEUE_EVENT_SEEN_BCM56640_A0r */
  44707         soc_block_list[4],
  44708         soc_genreg,
  44709         1,
  44710         0,
  44711         0x5a00a700,
  44712         0,
  44713         0,
  44714         25,
  44715         soc_LLS_DEQUEUE_EVENT_SEEN_BCM56640_A0r_fields,
  44716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44718         -1,
  44719         -1,
  44720     },
  44721 #endif /* chips */
  44722 
  44723 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44724     defined(BCM_56450_B1)
  44725     { /* SOC_REG_INT_LLS_DYNAMIC_UPDATE_INTr */
  44726         soc_block_list[85],
  44727         soc_genreg,
  44728         1,
  44729         0,
  44730         0x2002100,
  44731         0,
  44732         0,
  44733         4,
  44734         soc_LLS_DYNAMIC_UPDATE_INTr_fields,
  44735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44736         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44737         -1,
  44738         -1,
  44739     },
  44740 #endif /* chips */
  44741 
  44742 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  44743     defined(BCM_56270_A0)
  44744     { /* SOC_REG_INT_LLS_DYNAMIC_UPDATE_INT_BCM56260_A0r */
  44745         soc_block_list[85],
  44746         soc_genreg,
  44747         1,
  44748         0,
  44749         0x2002200,
  44750         0,
  44751         0,
  44752         4,
  44753         soc_LLS_DYNAMIC_UPDATE_INT_BCM56560_A0r_fields,
  44754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44755         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44756         -1,
  44757         -1,
  44758     },
  44759 #endif /* chips */
  44760 
  44761 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44762     { /* SOC_REG_INT_LLS_DYNAMIC_UPDATE_INT_BCM56560_A0r */
  44763         soc_block_list[4],
  44764         soc_genreg,
  44765         1,
  44766         0,
  44767         0x62001a00,
  44768         0,
  44769         0,
  44770         4,
  44771         soc_LLS_DYNAMIC_UPDATE_INT_BCM56560_A0r_fields,
  44772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44773         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44774         -1,
  44775         -1,
  44776     },
  44777 #endif /* chips */
  44778 
  44779 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44780     defined(BCM_56450_B1)
  44781     { /* SOC_REG_INT_LLS_DYNAMIC_UPDATE_INT_MASKr */
  44782         soc_block_list[85],
  44783         soc_genreg,
  44784         1,
  44785         0,
  44786         0x2002200,
  44787         0,
  44788         0,
  44789         4,
  44790         soc_LLS_DYNAMIC_UPDATE_INT_MASKr_fields,
  44791         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  44792         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44793         -1,
  44794         -1,
  44795     },
  44796 #endif /* chips */
  44797 
  44798 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  44799     defined(BCM_56270_A0)
  44800     { /* SOC_REG_INT_LLS_DYNAMIC_UPDATE_INT_MASK_BCM56260_A0r */
  44801         soc_block_list[85],
  44802         soc_genreg,
  44803         1,
  44804         0,
  44805         0x2002300,
  44806         0,
  44807         0,
  44808         4,
  44809         soc_LLS_DYNAMIC_UPDATE_INT_MASK_BCM56560_A0r_fields,
  44810         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  44811         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44812         -1,
  44813         -1,
  44814     },
  44815 #endif /* chips */
  44816 
  44817 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44818     { /* SOC_REG_INT_LLS_DYNAMIC_UPDATE_INT_MASK_BCM56560_A0r */
  44819         soc_block_list[4],
  44820         soc_genreg,
  44821         1,
  44822         0,
  44823         0x62001b00,
  44824         0,
  44825         0,
  44826         4,
  44827         soc_LLS_DYNAMIC_UPDATE_INT_MASK_BCM56560_A0r_fields,
  44828         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  44829         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  44830         -1,
  44831         -1,
  44832     },
  44833 #endif /* chips */
  44834 
  44835 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44836     { /* SOC_REG_INT_LLS_EN_COR_ERR_RPT_L0r */
  44837         soc_block_list[4],
  44838         soc_genreg,
  44839         1,
  44840         0,
  44841         0x62007b00,
  44842         0,
  44843         0,
  44844         11,
  44845         soc_LLS_EN_COR_ERR_RPT_L0r_fields,
  44846         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  44847         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  44848         -1,
  44849         -1,
  44850     },
  44851 #endif /* chips */
  44852 
  44853 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44854     { /* SOC_REG_INT_LLS_EN_COR_ERR_RPT_L1r */
  44855         soc_block_list[4],
  44856         soc_genreg,
  44857         1,
  44858         0,
  44859         0x62007c00,
  44860         0,
  44861         0,
  44862         15,
  44863         soc_LLS_EN_COR_ERR_RPT_L1r_fields,
  44864         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  44865         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  44866         -1,
  44867         -1,
  44868     },
  44869 #endif /* chips */
  44870 
  44871 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44872     { /* SOC_REG_INT_LLS_EN_COR_ERR_RPT_L2r */
  44873         soc_block_list[4],
  44874         soc_genreg,
  44875         1,
  44876         0,
  44877         0x62007d00,
  44878         0,
  44879         0,
  44880         14,
  44881         soc_LLS_EN_COR_ERR_RPT_L2r_fields,
  44882         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
  44883         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  44884         -1,
  44885         -1,
  44886     },
  44887 #endif /* chips */
  44888 
  44889 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44890     { /* SOC_REG_INT_LLS_EN_COR_ERR_RPT_PORTr */
  44891         soc_block_list[4],
  44892         soc_genreg,
  44893         1,
  44894         0,
  44895         0x62007a00,
  44896         0,
  44897         0,
  44898         9,
  44899         soc_LLS_EN_COR_ERR_RPT_PORTr_fields,
  44900         SOC_RESET_VAL_DEC(0x000001ff, 0x00000000)
  44901         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  44902         -1,
  44903         -1,
  44904     },
  44905 #endif /* chips */
  44906 
  44907 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  44908     { /* SOC_REG_INT_LLS_ERRORr */
  44909         soc_block_list[85],
  44910         soc_genreg,
  44911         1,
  44912         0,
  44913         0x80017,
  44914         0,
  44915         0,
  44916         29,
  44917         soc_LLS_ERRORr_fields,
  44918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44919         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  44920         -1,
  44921         -1,
  44922     },
  44923 #endif /* chips */
  44924 
  44925 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44926     defined(BCM_56450_B1)
  44927     { /* SOC_REG_INT_LLS_ERROR2r */
  44928         soc_block_list[85],
  44929         soc_genreg,
  44930         1,
  44931         0,
  44932         0x2001d00,
  44933         0,
  44934         0,
  44935         8,
  44936         soc_LLS_ERROR2r_fields,
  44937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44938         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  44939         -1,
  44940         -1,
  44941     },
  44942 #endif /* chips */
  44943 
  44944 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  44945     defined(BCM_56270_A0)
  44946     { /* SOC_REG_INT_LLS_ERROR2_BCM56260_A0r */
  44947         soc_block_list[85],
  44948         soc_genreg,
  44949         1,
  44950         0,
  44951         0x2001e00,
  44952         0,
  44953         0,
  44954         14,
  44955         soc_LLS_ERROR2_BCM56260_A0r_fields,
  44956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44957         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  44958         -1,
  44959         -1,
  44960     },
  44961 #endif /* chips */
  44962 
  44963 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  44964     { /* SOC_REG_INT_LLS_ERROR2_BCM56560_A0r */
  44965         soc_block_list[4],
  44966         soc_genreg,
  44967         1,
  44968         0,
  44969         0x62001600,
  44970         0,
  44971         0,
  44972         14,
  44973         soc_LLS_ERROR2_BCM56560_A0r_fields,
  44974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44975         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  44976         -1,
  44977         -1,
  44978     },
  44979 #endif /* chips */
  44980 
  44981 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44982     defined(BCM_56450_B1)
  44983     { /* SOC_REG_INT_LLS_ERROR2_MASKr */
  44984         soc_block_list[85],
  44985         soc_genreg,
  44986         1,
  44987         0,
  44988         0x2001e00,
  44989         0,
  44990         0,
  44991         8,
  44992         soc_LLS_ERROR2_MASKr_fields,
  44993         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  44994         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  44995         -1,
  44996         -1,
  44997     },
  44998 #endif /* chips */
  44999 
  45000 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  45001     defined(BCM_56270_A0)
  45002     { /* SOC_REG_INT_LLS_ERROR2_MASK_BCM56260_A0r */
  45003         soc_block_list[85],
  45004         soc_genreg,
  45005         1,
  45006         0,
  45007         0x2001f00,
  45008         0,
  45009         0,
  45010         14,
  45011         soc_LLS_ERROR2_MASK_BCM56260_A0r_fields,
  45012         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
  45013         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  45014         -1,
  45015         -1,
  45016     },
  45017 #endif /* chips */
  45018 
  45019 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  45020     { /* SOC_REG_INT_LLS_ERROR2_MASK_BCM56560_A0r */
  45021         soc_block_list[4],
  45022         soc_genreg,
  45023         1,
  45024         0,
  45025         0x62001700,
  45026         0,
  45027         0,
  45028         14,
  45029         soc_LLS_ERROR2_MASK_BCM56560_A0r_fields,
  45030         SOC_RESET_VAL_DEC(0x000003ff, 0x00000000)
  45031         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  45032         -1,
  45033         -1,
  45034     },
  45035 #endif /* chips */
  45036 
  45037 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  45038     defined(BCM_56270_A0)
  45039     { /* SOC_REG_INT_LLS_ERROR_BCM56260_A0r */
  45040         soc_block_list[85],
  45041         soc_genreg,
  45042         1,
  45043         0,
  45044         0x2001c00,
  45045         0,
  45046         0,
  45047         27,
  45048         soc_LLS_ERROR_BCM56260_A0r_fields,
  45049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45050         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  45051         -1,
  45052         -1,
  45053     },
  45054 #endif /* chips */
  45055 
  45056 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45057     defined(BCM_56450_B1)
  45058     { /* SOC_REG_INT_LLS_ERROR_BCM56450_A0r */
  45059         soc_block_list[85],
  45060         soc_genreg,
  45061         1,
  45062         0,
  45063         0x2001b00,
  45064         0,
  45065         0,
  45066         32,
  45067         soc_LLS_ERROR_BCM56450_A0r_fields,
  45068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45069         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45070         -1,
  45071         -1,
  45072     },
  45073 #endif /* chips */
  45074 
  45075 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  45076     { /* SOC_REG_INT_LLS_ERROR_BCM56560_A0r */
  45077         soc_block_list[4],
  45078         soc_genreg,
  45079         1,
  45080         0,
  45081         0x62001400,
  45082         0,
  45083         0,
  45084         4,
  45085         soc_LLS_ERROR_BCM56560_A0r_fields,
  45086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45087         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  45088         -1,
  45089         -1,
  45090     },
  45091 #endif /* chips */
  45092 
  45093 #if defined(BCM_56440_A0)
  45094     { /* SOC_REG_INT_LLS_ERROR_ECC_DEBUGr */
  45095         soc_block_list[85],
  45096         soc_genreg,
  45097         1,
  45098         0,
  45099         0x80072,
  45100         0,
  45101         0,
  45102         6,
  45103         soc_LLS_ERROR_ECC_DEBUGr_fields,
  45104         SOC_RESET_VAL_DEC(0x00000015, 0x00000000)
  45105         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  45106         -1,
  45107         -1,
  45108     },
  45109 #endif /* chips */
  45110 
  45111 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  45112     { /* SOC_REG_INT_LLS_ERROR_ECC_DEBUG_BCM56260_A0r */
  45113         soc_block_list[85],
  45114         soc_genreg,
  45115         1,
  45116         0,
  45117         0x200cd00,
  45118         0,
  45119         0,
  45120         6,
  45121         soc_LLS_ERROR_ECC_DEBUG_BCM56260_A0r_fields,
  45122         SOC_RESET_VAL_DEC(0x00000049, 0x00000000)
  45123         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  45124         -1,
  45125         -1,
  45126     },
  45127 #endif /* chips */
  45128 
  45129 #if defined(BCM_56270_A0)
  45130     { /* SOC_REG_INT_LLS_ERROR_ECC_DEBUG_BCM56270_A0r */
  45131         soc_block_list[85],
  45132         soc_genreg,
  45133         1,
  45134         0,
  45135         0x200b400,
  45136         0,
  45137         0,
  45138         6,
  45139         soc_LLS_ERROR_ECC_DEBUG_BCM56260_A0r_fields,
  45140         SOC_RESET_VAL_DEC(0x00000049, 0x00000000)
  45141         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  45142         -1,
  45143         -1,
  45144     },
  45145 #endif /* chips */
  45146 
  45147 #if defined(BCM_56440_B0)
  45148     { /* SOC_REG_INT_LLS_ERROR_ECC_DEBUG_BCM56440_B0r */
  45149         soc_block_list[85],
  45150         soc_genreg,
  45151         1,
  45152         0,
  45153         0x8007a,
  45154         0,
  45155         0,
  45156         12,
  45157         soc_LLS_ERROR_ECC_DEBUG_BCM56440_B0r_fields,
  45158         SOC_RESET_VAL_DEC(0x00000555, 0x00000000)
  45159         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  45160         -1,
  45161         -1,
  45162     },
  45163 #endif /* chips */
  45164 
  45165 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45166     defined(BCM_56450_B1)
  45167     { /* SOC_REG_INT_LLS_ERROR_ECC_DEBUG_BCM56450_A0r */
  45168         soc_block_list[85],
  45169         soc_genreg,
  45170         1,
  45171         0,
  45172         0x2014f00,
  45173         0,
  45174         0,
  45175         16,
  45176         soc_LLS_ERROR_ECC_DEBUG_BCM56450_A0r_fields,
  45177         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  45178         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  45179         -1,
  45180         -1,
  45181     },
  45182 #endif /* chips */
  45183 
  45184 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  45185     { /* SOC_REG_INT_LLS_ERROR_ECC_DEBUG_BCM56560_A0r */
  45186         soc_block_list[4],
  45187         soc_genreg,
  45188         1,
  45189         0,
  45190         0x62007700,
  45191         0,
  45192         0,
  45193         8,
  45194         soc_LLS_ERROR_ECC_DEBUG_BCM56560_A0r_fields,
  45195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45196         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  45197         -1,
  45198         -1,
  45199     },
  45200 #endif /* chips */
  45201 
  45202 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45203     { /* SOC_REG_INT_LLS_ERROR_MASKr */
  45204         soc_block_list[85],
  45205         soc_genreg,
  45206         1,
  45207         0,
  45208         0x80018,
  45209         0,
  45210         0,
  45211         29,
  45212         soc_LLS_ERROR_MASKr_fields,
  45213         SOC_RESET_VAL_DEC(0x1fffffff, 0x00000000)
  45214         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  45215         -1,
  45216         -1,
  45217     },
  45218 #endif /* chips */
  45219 
  45220 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  45221     defined(BCM_56270_A0)
  45222     { /* SOC_REG_INT_LLS_ERROR_MASK_BCM56260_A0r */
  45223         soc_block_list[85],
  45224         soc_genreg,
  45225         1,
  45226         0,
  45227         0x2001d00,
  45228         0,
  45229         0,
  45230         27,
  45231         soc_LLS_ERROR_MASK_BCM56260_A0r_fields,
  45232         SOC_RESET_VAL_DEC(0x07ffffff, 0x00000000)
  45233         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  45234         -1,
  45235         -1,
  45236     },
  45237 #endif /* chips */
  45238 
  45239 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45240     defined(BCM_56450_B1)
  45241     { /* SOC_REG_INT_LLS_ERROR_MASK_BCM56450_A0r */
  45242         soc_block_list[85],
  45243         soc_genreg,
  45244         1,
  45245         0,
  45246         0x2001c00,
  45247         0,
  45248         0,
  45249         32,
  45250         soc_LLS_ERROR_MASK_BCM56450_A0r_fields,
  45251         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  45252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45253         -1,
  45254         -1,
  45255     },
  45256 #endif /* chips */
  45257 
  45258 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  45259     { /* SOC_REG_INT_LLS_ERROR_MASK_BCM56560_A0r */
  45260         soc_block_list[4],
  45261         soc_genreg,
  45262         1,
  45263         0,
  45264         0x62001500,
  45265         0,
  45266         0,
  45267         4,
  45268         soc_LLS_ERROR_MASK_BCM56560_A0r_fields,
  45269         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  45270         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  45271         -1,
  45272         -1,
  45273     },
  45274 #endif /* chips */
  45275 
  45276 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45277     { /* SOC_REG_INT_LLS_ERROR_UPD2r */
  45278         soc_block_list[85],
  45279         soc_genreg,
  45280         1,
  45281         0,
  45282         0x80019,
  45283         0,
  45284         0,
  45285         9,
  45286         soc_LLS_ERROR_UPD2r_fields,
  45287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45288         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  45289         -1,
  45290         -1,
  45291     },
  45292 #endif /* chips */
  45293 
  45294 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  45295     { /* SOC_REG_INT_LLS_ERROR_UPD2_BCM56260_A0r */
  45296         soc_block_list[85],
  45297         soc_genreg,
  45298         1,
  45299         0,
  45300         0x2002000,
  45301         0,
  45302         0,
  45303         19,
  45304         soc_LLS_ERROR_UPD2_BCM56260_A0r_fields,
  45305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45306         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  45307         -1,
  45308         -1,
  45309     },
  45310 #endif /* chips */
  45311 
  45312 #if defined(BCM_56270_A0)
  45313     { /* SOC_REG_INT_LLS_ERROR_UPD2_BCM56270_A0r */
  45314         soc_block_list[85],
  45315         soc_genreg,
  45316         1,
  45317         0,
  45318         0x2002000,
  45319         0,
  45320         0,
  45321         17,
  45322         soc_LLS_ERROR_UPD2_BCM56270_A0r_fields,
  45323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45324         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45325         -1,
  45326         -1,
  45327     },
  45328 #endif /* chips */
  45329 
  45330 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45331     defined(BCM_56450_B1)
  45332     { /* SOC_REG_INT_LLS_ERROR_UPD2_BCM56450_A0r */
  45333         soc_block_list[85],
  45334         soc_genreg,
  45335         1,
  45336         0,
  45337         0x2001f00,
  45338         0,
  45339         0,
  45340         13,
  45341         soc_LLS_ERROR_UPD2_BCM56450_A0r_fields,
  45342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45343         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  45344         -1,
  45345         -1,
  45346     },
  45347 #endif /* chips */
  45348 
  45349 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  45350     { /* SOC_REG_INT_LLS_ERROR_UPD2_BCM56560_A0r */
  45351         soc_block_list[4],
  45352         soc_genreg,
  45353         1,
  45354         0,
  45355         0x62001800,
  45356         0,
  45357         0,
  45358         9,
  45359         soc_LLS_ERROR_UPD2_BCM56560_A0r_fields,
  45360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45361         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  45362         -1,
  45363         -1,
  45364     },
  45365 #endif /* chips */
  45366 
  45367 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45368     { /* SOC_REG_INT_LLS_ERROR_UPD2_MASKr */
  45369         soc_block_list[85],
  45370         soc_genreg,
  45371         1,
  45372         0,
  45373         0x8001a,
  45374         0,
  45375         0,
  45376         9,
  45377         soc_LLS_ERROR_UPD2_MASKr_fields,
  45378         SOC_RESET_VAL_DEC(0x000001ff, 0x00000000)
  45379         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  45380         -1,
  45381         -1,
  45382     },
  45383 #endif /* chips */
  45384 
  45385 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  45386     { /* SOC_REG_INT_LLS_ERROR_UPD2_MASK_BCM56260_A0r */
  45387         soc_block_list[85],
  45388         soc_genreg,
  45389         1,
  45390         0,
  45391         0x2002100,
  45392         0,
  45393         0,
  45394         19,
  45395         soc_LLS_ERROR_UPD2_MASK_BCM56260_A0r_fields,
  45396         SOC_RESET_VAL_DEC(0x0007ffff, 0x00000000)
  45397         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  45398         -1,
  45399         -1,
  45400     },
  45401 #endif /* chips */
  45402 
  45403 #if defined(BCM_56270_A0)
  45404     { /* SOC_REG_INT_LLS_ERROR_UPD2_MASK_BCM56270_A0r */
  45405         soc_block_list[85],
  45406         soc_genreg,
  45407         1,
  45408         0,
  45409         0x2002100,
  45410         0,
  45411         0,
  45412         17,
  45413         soc_LLS_ERROR_UPD2_MASK_BCM56270_A0r_fields,
  45414         SOC_RESET_VAL_DEC(0x0001ffff, 0x00000000)
  45415         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45416         -1,
  45417         -1,
  45418     },
  45419 #endif /* chips */
  45420 
  45421 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45422     defined(BCM_56450_B1)
  45423     { /* SOC_REG_INT_LLS_ERROR_UPD2_MASK_BCM56450_A0r */
  45424         soc_block_list[85],
  45425         soc_genreg,
  45426         1,
  45427         0,
  45428         0x2002000,
  45429         0,
  45430         0,
  45431         13,
  45432         soc_LLS_ERROR_UPD2_MASK_BCM56450_A0r_fields,
  45433         SOC_RESET_VAL_DEC(0x00001fff, 0x00000000)
  45434         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  45435         -1,
  45436         -1,
  45437     },
  45438 #endif /* chips */
  45439 
  45440 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  45441     { /* SOC_REG_INT_LLS_ERROR_UPD2_MASK_BCM56560_A0r */
  45442         soc_block_list[4],
  45443         soc_genreg,
  45444         1,
  45445         0,
  45446         0x62001900,
  45447         0,
  45448         0,
  45449         9,
  45450         soc_LLS_ERROR_UPD2_MASK_BCM56560_A0r_fields,
  45451         SOC_RESET_VAL_DEC(0x000001ff, 0x00000000)
  45452         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  45453         -1,
  45454         -1,
  45455     },
  45456 #endif /* chips */
  45457 
  45458 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  45459     { /* SOC_REG_INT_LLS_ERROR_VIOLATE_1IN4_TDMr */
  45460         soc_block_list[4],
  45461         soc_genreg,
  45462         1,
  45463         0,
  45464         0x5a000d00,
  45465         0,
  45466         0,
  45467         1,
  45468         soc_LLS_ERROR_VIOLATE_1IN4_TDMr_fields,
  45469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45470         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  45471         -1,
  45472         -1,
  45473     },
  45474 #endif /* chips */
  45475 
  45476 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45477     { /* SOC_REG_INT_LLS_FC_CONFIGr */
  45478         soc_block_list[85],
  45479         soc_genreg,
  45480         1,
  45481         0,
  45482         0x8000b,
  45483         0,
  45484         0,
  45485         5,
  45486         soc_LLS_FC_CONFIGr_fields,
  45487         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  45488         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  45489         -1,
  45490         -1,
  45491     },
  45492 #endif /* chips */
  45493 
  45494 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  45495     defined(BCM_56270_A0)
  45496     { /* SOC_REG_INT_LLS_FC_CONFIG_BCM56260_A0r */
  45497         soc_block_list[85],
  45498         soc_genreg,
  45499         1,
  45500         0,
  45501         0x2000e00,
  45502         0,
  45503         0,
  45504         7,
  45505         soc_LLS_FC_CONFIG_BCM56260_A0r_fields,
  45506         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  45507         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45508         -1,
  45509         -1,
  45510     },
  45511 #endif /* chips */
  45512 
  45513 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45514     defined(BCM_56450_B1)
  45515     { /* SOC_REG_INT_LLS_FC_CONFIG_BCM56450_A0r */
  45516         soc_block_list[85],
  45517         soc_genreg,
  45518         1,
  45519         0,
  45520         0x2000e00,
  45521         0,
  45522         0,
  45523         7,
  45524         soc_LLS_FC_CONFIG_BCM56450_A0r_fields,
  45525         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  45526         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45527         -1,
  45528         -1,
  45529     },
  45530 #endif /* chips */
  45531 
  45532 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  45533     { /* SOC_REG_INT_LLS_FC_CONFIG_BCM56560_A0r */
  45534         soc_block_list[4],
  45535         soc_genreg,
  45536         1,
  45537         0,
  45538         0x62000a00,
  45539         0,
  45540         0,
  45541         8,
  45542         soc_LLS_FC_CONFIG_BCM56560_A0r_fields,
  45543         SOC_RESET_VAL_DEC(0x00000034, 0x00000000)
  45544         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  45545         -1,
  45546         -1,
  45547     },
  45548 #endif /* chips */
  45549 
  45550 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  45551     { /* SOC_REG_INT_LLS_FC_CONFIG_BCM56640_A0r */
  45552         soc_block_list[4],
  45553         soc_genreg,
  45554         1,
  45555         0,
  45556         0x5a000500,
  45557         0,
  45558         0,
  45559         6,
  45560         soc_LLS_FC_CONFIG_BCM56640_A0r_fields,
  45561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45562         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  45563         -1,
  45564         -1,
  45565     },
  45566 #endif /* chips */
  45567 
  45568 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  45569     { /* SOC_REG_INT_LLS_FIXED_DEQ_LENr */
  45570         soc_block_list[4],
  45571         soc_genreg,
  45572         1,
  45573         0,
  45574         0x5a000700,
  45575         0,
  45576         0,
  45577         1,
  45578         soc_LLS_FIXED_DEQ_LENr_fields,
  45579         SOC_RESET_VAL_DEC(0x000000be, 0x00000000)
  45580         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  45581         -1,
  45582         -1,
  45583     },
  45584 #endif /* chips */
  45585 
  45586 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45587     { /* SOC_REG_INT_LLS_INITr */
  45588         soc_block_list[85],
  45589         soc_genreg,
  45590         1,
  45591         0,
  45592         0x80002,
  45593         0,
  45594         0,
  45595         2,
  45596         soc_LLS_INITr_fields,
  45597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45598         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  45599         -1,
  45600         -1,
  45601     },
  45602 #endif /* chips */
  45603 
  45604 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  45605     defined(BCM_56270_A0)
  45606     { /* SOC_REG_INT_LLS_INIT_BCM56260_A0r */
  45607         soc_block_list[85],
  45608         soc_genreg,
  45609         1,
  45610         0,
  45611         0x2000200,
  45612         0,
  45613         0,
  45614         2,
  45615         soc_LLS_INIT_BCM56560_A0r_fields,
  45616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45617         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  45618         -1,
  45619         -1,
  45620     },
  45621 #endif /* chips */
  45622 
  45623 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45624     defined(BCM_56450_B1)
  45625     { /* SOC_REG_INT_LLS_INIT_BCM56450_A0r */
  45626         soc_block_list[85],
  45627         soc_genreg,
  45628         1,
  45629         0,
  45630         0x2000200,
  45631         0,
  45632         0,
  45633         2,
  45634         soc_LLS_INIT_BCM56450_A0r_fields,
  45635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45636         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  45637         -1,
  45638         -1,
  45639     },
  45640 #endif /* chips */
  45641 
  45642 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  45643     { /* SOC_REG_INT_LLS_INIT_BCM56560_A0r */
  45644         soc_block_list[4],
  45645         soc_genreg,
  45646         1,
  45647         0,
  45648         0x62000200,
  45649         0,
  45650         0,
  45651         2,
  45652         soc_LLS_INIT_BCM56560_A0r_fields,
  45653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45654         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  45655         -1,
  45656         -1,
  45657     },
  45658 #endif /* chips */
  45659 
  45660 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  45661     { /* SOC_REG_INT_LLS_INIT_BCM56640_A0r */
  45662         soc_block_list[4],
  45663         soc_genreg,
  45664         1,
  45665         0,
  45666         0x5a000100,
  45667         0,
  45668         0,
  45669         2,
  45670         soc_LLS_INIT_BCM56640_A0r_fields,
  45671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45672         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45673         -1,
  45674         -1,
  45675     },
  45676 #endif /* chips */
  45677 
  45678 #if defined(BCM_56440_A0)
  45679     { /* SOC_REG_INT_LLS_L0_CHILD_STATE1_ECC_STATUSr */
  45680         soc_block_list[85],
  45681         soc_genreg,
  45682         1,
  45683         0,
  45684         0x80086,
  45685         0,
  45686         0,
  45687         1,
  45688         soc_LLS_L0_CHILD_STATE1_ECC_STATUSr_fields,
  45689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45690         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45691         -1,
  45692         -1,
  45693     },
  45694 #endif /* chips */
  45695 
  45696 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  45697     { /* SOC_REG_INT_LLS_L0_CHILD_STATE1_ECC_STATUS_BCM56260_A0r */
  45698         soc_block_list[85],
  45699         soc_genreg,
  45700         1,
  45701         0,
  45702         0x200e000,
  45703         0,
  45704         0,
  45705         1,
  45706         soc_LLS_L0_CHILD_STATE1_ECC_STATUS_BCM56260_A0r_fields,
  45707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45708         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  45709         -1,
  45710         -1,
  45711     },
  45712 #endif /* chips */
  45713 
  45714 #if defined(BCM_56270_A0)
  45715     { /* SOC_REG_INT_LLS_L0_CHILD_STATE1_ECC_STATUS_BCM56270_A0r */
  45716         soc_block_list[85],
  45717         soc_genreg,
  45718         1,
  45719         0,
  45720         0x200c700,
  45721         0,
  45722         0,
  45723         1,
  45724         soc_LLS_L0_CHILD_STATE1_ECC_STATUS_BCM56260_A0r_fields,
  45725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45726         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  45727         -1,
  45728         -1,
  45729     },
  45730 #endif /* chips */
  45731 
  45732 #if defined(BCM_56440_B0)
  45733     { /* SOC_REG_INT_LLS_L0_CHILD_STATE1_ECC_STATUS_BCM56440_B0r */
  45734         soc_block_list[85],
  45735         soc_genreg,
  45736         1,
  45737         0,
  45738         0x8008e,
  45739         0,
  45740         0,
  45741         1,
  45742         soc_LLS_L0_CHILD_STATE1_ECC_STATUSr_fields,
  45743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45744         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45745         -1,
  45746         -1,
  45747     },
  45748 #endif /* chips */
  45749 
  45750 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45751     defined(BCM_56450_B1)
  45752     { /* SOC_REG_INT_LLS_L0_CHILD_STATE1_ECC_STATUS_BCM56450_A0r */
  45753         soc_block_list[85],
  45754         soc_genreg,
  45755         1,
  45756         0,
  45757         0x2016800,
  45758         0,
  45759         0,
  45760         1,
  45761         soc_LLS_L0_CHILD_STATE1_ECC_STATUS_BCM56450_A0r_fields,
  45762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45763         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  45764         -1,
  45765         -1,
  45766     },
  45767 #endif /* chips */
  45768 
  45769 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  45770     { /* SOC_REG_INT_LLS_L0_CHILD_STATE1_ECC_STATUS_BCM56640_A0r */
  45771         soc_block_list[4],
  45772         soc_genreg,
  45773         1,
  45774         0,
  45775         0x5a008500,
  45776         0,
  45777         0,
  45778         1,
  45779         soc_LLS_L0_CHILD_STATE1_ECC_STATUS_BCM56640_A0r_fields,
  45780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45781         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45782         -1,
  45783         -1,
  45784     },
  45785 #endif /* chips */
  45786 
  45787 #if defined(BCM_56440_A0)
  45788     { /* SOC_REG_INT_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr */
  45789         soc_block_list[85],
  45790         soc_genreg,
  45791         1,
  45792         0,
  45793         0x80087,
  45794         0,
  45795         0,
  45796         1,
  45797         soc_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr_fields,
  45798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45799         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45800         -1,
  45801         -1,
  45802     },
  45803 #endif /* chips */
  45804 
  45805 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  45806     { /* SOC_REG_INT_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56260_A0r */
  45807         soc_block_list[85],
  45808         soc_genreg,
  45809         1,
  45810         0,
  45811         0x200e100,
  45812         0,
  45813         0,
  45814         1,
  45815         soc_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56260_A0r_fields,
  45816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45817         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  45818         -1,
  45819         -1,
  45820     },
  45821 #endif /* chips */
  45822 
  45823 #if defined(BCM_56270_A0)
  45824     { /* SOC_REG_INT_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56270_A0r */
  45825         soc_block_list[85],
  45826         soc_genreg,
  45827         1,
  45828         0,
  45829         0x200c800,
  45830         0,
  45831         0,
  45832         1,
  45833         soc_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56270_A0r_fields,
  45834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45835         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  45836         -1,
  45837         -1,
  45838     },
  45839 #endif /* chips */
  45840 
  45841 #if defined(BCM_56440_B0)
  45842     { /* SOC_REG_INT_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56440_B0r */
  45843         soc_block_list[85],
  45844         soc_genreg,
  45845         1,
  45846         0,
  45847         0x8008f,
  45848         0,
  45849         0,
  45850         1,
  45851         soc_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr_fields,
  45852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45853         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45854         -1,
  45855         -1,
  45856     },
  45857 #endif /* chips */
  45858 
  45859 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45860     defined(BCM_56450_B1)
  45861     { /* SOC_REG_INT_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56450_A0r */
  45862         soc_block_list[85],
  45863         soc_genreg,
  45864         1,
  45865         0,
  45866         0x2016900,
  45867         0,
  45868         0,
  45869         1,
  45870         soc_LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56450_A0r_fields,
  45871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45872         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  45873         -1,
  45874         -1,
  45875     },
  45876 #endif /* chips */
  45877 
  45878 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  45879     { /* SOC_REG_INT_LLS_L0_CHILD_WEIGHT_CFG_ECC_STATUSr */
  45880         soc_block_list[4],
  45881         soc_genreg,
  45882         1,
  45883         0,
  45884         0x5a008600,
  45885         0,
  45886         0,
  45887         1,
  45888         soc_LLS_L0_CHILD_WEIGHT_CFG_ECC_STATUSr_fields,
  45889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45890         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45891         -1,
  45892         -1,
  45893     },
  45894 #endif /* chips */
  45895 
  45896 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  45897     { /* SOC_REG_INT_LLS_L0_CHILD_WEIGHT_WORKING_ECC_STATUSr */
  45898         soc_block_list[4],
  45899         soc_genreg,
  45900         1,
  45901         0,
  45902         0x5a008700,
  45903         0,
  45904         0,
  45905         1,
  45906         soc_LLS_L0_CHILD_WEIGHT_WORKING_ECC_STATUSr_fields,
  45907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45908         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45909         -1,
  45910         -1,
  45911     },
  45912 #endif /* chips */
  45913 
  45914 #if defined(BCM_56440_A0)
  45915     { /* SOC_REG_INT_LLS_L0_CONFIG_ECC_STATUSr */
  45916         soc_block_list[85],
  45917         soc_genreg,
  45918         1,
  45919         0,
  45920         0x80080,
  45921         0,
  45922         0,
  45923         1,
  45924         soc_LLS_L0_CONFIG_ECC_STATUSr_fields,
  45925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45926         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45927         -1,
  45928         -1,
  45929     },
  45930 #endif /* chips */
  45931 
  45932 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  45933     { /* SOC_REG_INT_LLS_L0_CONFIG_ECC_STATUS_BCM56260_A0r */
  45934         soc_block_list[85],
  45935         soc_genreg,
  45936         1,
  45937         0,
  45938         0x200d900,
  45939         0,
  45940         0,
  45941         1,
  45942         soc_LLS_L0_CONFIG_ECC_STATUS_BCM56260_A0r_fields,
  45943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45944         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  45945         -1,
  45946         -1,
  45947     },
  45948 #endif /* chips */
  45949 
  45950 #if defined(BCM_56270_A0)
  45951     { /* SOC_REG_INT_LLS_L0_CONFIG_ECC_STATUS_BCM56270_A0r */
  45952         soc_block_list[85],
  45953         soc_genreg,
  45954         1,
  45955         0,
  45956         0x200c000,
  45957         0,
  45958         0,
  45959         1,
  45960         soc_LLS_L0_CONFIG_ECC_STATUS_BCM56270_A0r_fields,
  45961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45962         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  45963         -1,
  45964         -1,
  45965     },
  45966 #endif /* chips */
  45967 
  45968 #if defined(BCM_56440_B0)
  45969     { /* SOC_REG_INT_LLS_L0_CONFIG_ECC_STATUS_BCM56440_B0r */
  45970         soc_block_list[85],
  45971         soc_genreg,
  45972         1,
  45973         0,
  45974         0x80088,
  45975         0,
  45976         0,
  45977         1,
  45978         soc_LLS_L0_CONFIG_ECC_STATUSr_fields,
  45979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45980         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  45981         -1,
  45982         -1,
  45983     },
  45984 #endif /* chips */
  45985 
  45986 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45987     defined(BCM_56450_B1)
  45988     { /* SOC_REG_INT_LLS_L0_CONFIG_ECC_STATUS_BCM56450_A0r */
  45989         soc_block_list[85],
  45990         soc_genreg,
  45991         1,
  45992         0,
  45993         0x2016200,
  45994         0,
  45995         0,
  45996         1,
  45997         soc_LLS_L0_CONFIG_ECC_STATUS_BCM56450_A0r_fields,
  45998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45999         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46000         -1,
  46001         -1,
  46002     },
  46003 #endif /* chips */
  46004 
  46005 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  46006     { /* SOC_REG_INT_LLS_L0_CONFIG_ECC_STATUS_BCM56640_A0r */
  46007         soc_block_list[4],
  46008         soc_genreg,
  46009         1,
  46010         0,
  46011         0x5a008100,
  46012         0,
  46013         0,
  46014         1,
  46015         soc_LLS_L0_CONFIG_ECC_STATUS_BCM56640_A0r_fields,
  46016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46017         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46018         -1,
  46019         -1,
  46020     },
  46021 #endif /* chips */
  46022 
  46023 #if defined(BCM_56440_A0)
  46024     { /* SOC_REG_INT_LLS_L0_ECC_1B_COUNTERr */
  46025         soc_block_list[85],
  46026         soc_genreg,
  46027         1,
  46028         0,
  46029         0x80065,
  46030         0,
  46031         0,
  46032         1,
  46033         soc_LLS_L0_ECC_1B_COUNTERr_fields,
  46034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46035         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46036         -1,
  46037         -1,
  46038     },
  46039 #endif /* chips */
  46040 
  46041 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46042     { /* SOC_REG_INT_LLS_L0_ECC_1B_COUNTER_BCM56260_A0r */
  46043         soc_block_list[85],
  46044         soc_genreg,
  46045         1,
  46046         0,
  46047         0x200c000,
  46048         0,
  46049         0,
  46050         1,
  46051         soc_LLS_L0_ECC_1B_COUNTER_BCM56260_A0r_fields,
  46052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46053         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46054         -1,
  46055         -1,
  46056     },
  46057 #endif /* chips */
  46058 
  46059 #if defined(BCM_56270_A0)
  46060     { /* SOC_REG_INT_LLS_L0_ECC_1B_COUNTER_BCM56270_A0r */
  46061         soc_block_list[85],
  46062         soc_genreg,
  46063         1,
  46064         0,
  46065         0x200a700,
  46066         0,
  46067         0,
  46068         1,
  46069         soc_LLS_L0_ECC_1B_COUNTER_BCM56260_A0r_fields,
  46070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46071         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46072         -1,
  46073         -1,
  46074     },
  46075 #endif /* chips */
  46076 
  46077 #if defined(BCM_56440_B0)
  46078     { /* SOC_REG_INT_LLS_L0_ECC_1B_COUNTER_BCM56440_B0r */
  46079         soc_block_list[85],
  46080         soc_genreg,
  46081         1,
  46082         0,
  46083         0x8006d,
  46084         0,
  46085         0,
  46086         1,
  46087         soc_LLS_L0_ECC_1B_COUNTERr_fields,
  46088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46089         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46090         -1,
  46091         -1,
  46092     },
  46093 #endif /* chips */
  46094 
  46095 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46096     defined(BCM_56450_B1)
  46097     { /* SOC_REG_INT_LLS_L0_ECC_1B_COUNTER_BCM56450_A0r */
  46098         soc_block_list[85],
  46099         soc_genreg,
  46100         1,
  46101         0,
  46102         0x2014200,
  46103         0,
  46104         0,
  46105         1,
  46106         soc_LLS_L0_ECC_1B_COUNTER_BCM56450_A0r_fields,
  46107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46108         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46109         -1,
  46110         -1,
  46111     },
  46112 #endif /* chips */
  46113 
  46114 #if defined(BCM_56440_A0)
  46115     { /* SOC_REG_INT_LLS_L0_ECC_2B_COUNTERr */
  46116         soc_block_list[85],
  46117         soc_genreg,
  46118         1,
  46119         0,
  46120         0x80066,
  46121         0,
  46122         0,
  46123         1,
  46124         soc_LLS_L0_ECC_2B_COUNTERr_fields,
  46125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46126         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46127         -1,
  46128         -1,
  46129     },
  46130 #endif /* chips */
  46131 
  46132 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46133     { /* SOC_REG_INT_LLS_L0_ECC_2B_COUNTER_BCM56260_A0r */
  46134         soc_block_list[85],
  46135         soc_genreg,
  46136         1,
  46137         0,
  46138         0x200c100,
  46139         0,
  46140         0,
  46141         1,
  46142         soc_LLS_L0_ECC_2B_COUNTER_BCM56260_A0r_fields,
  46143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46144         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46145         -1,
  46146         -1,
  46147     },
  46148 #endif /* chips */
  46149 
  46150 #if defined(BCM_56270_A0)
  46151     { /* SOC_REG_INT_LLS_L0_ECC_2B_COUNTER_BCM56270_A0r */
  46152         soc_block_list[85],
  46153         soc_genreg,
  46154         1,
  46155         0,
  46156         0x200a800,
  46157         0,
  46158         0,
  46159         1,
  46160         soc_LLS_L0_ECC_2B_COUNTER_BCM56260_A0r_fields,
  46161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46162         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46163         -1,
  46164         -1,
  46165     },
  46166 #endif /* chips */
  46167 
  46168 #if defined(BCM_56440_B0)
  46169     { /* SOC_REG_INT_LLS_L0_ECC_2B_COUNTER_BCM56440_B0r */
  46170         soc_block_list[85],
  46171         soc_genreg,
  46172         1,
  46173         0,
  46174         0x8006e,
  46175         0,
  46176         0,
  46177         1,
  46178         soc_LLS_L0_ECC_2B_COUNTERr_fields,
  46179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46180         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46181         -1,
  46182         -1,
  46183     },
  46184 #endif /* chips */
  46185 
  46186 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46187     defined(BCM_56450_B1)
  46188     { /* SOC_REG_INT_LLS_L0_ECC_2B_COUNTER_BCM56450_A0r */
  46189         soc_block_list[85],
  46190         soc_genreg,
  46191         1,
  46192         0,
  46193         0x2014300,
  46194         0,
  46195         0,
  46196         1,
  46197         soc_LLS_L0_ECC_2B_COUNTER_BCM56450_A0r_fields,
  46198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46199         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46200         -1,
  46201         -1,
  46202     },
  46203 #endif /* chips */
  46204 
  46205 #if defined(BCM_56440_A0)
  46206     { /* SOC_REG_INT_LLS_L0_ECC_DEBUGr */
  46207         soc_block_list[85],
  46208         soc_genreg,
  46209         1,
  46210         0,
  46211         0x8006c,
  46212         0,
  46213         0,
  46214         24,
  46215         soc_LLS_L0_ECC_DEBUGr_fields,
  46216         SOC_RESET_VAL_DEC(0x00555555, 0x00000000)
  46217         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  46218         -1,
  46219         -1,
  46220     },
  46221 #endif /* chips */
  46222 
  46223 #if defined(BCM_56440_A0)
  46224     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG1r */
  46225         soc_block_list[85],
  46226         soc_genreg,
  46227         1,
  46228         0,
  46229         0x8006d,
  46230         0,
  46231         0,
  46232         4,
  46233         soc_LLS_L0_ECC_DEBUG1r_fields,
  46234         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  46235         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  46236         -1,
  46237         -1,
  46238     },
  46239 #endif /* chips */
  46240 
  46241 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46242     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG1_BCM56260_A0r */
  46243         soc_block_list[85],
  46244         soc_genreg,
  46245         1,
  46246         0,
  46247         0x200c800,
  46248         0,
  46249         0,
  46250         8,
  46251         soc_LLS_L0_ECC_DEBUG1_BCM56260_A0r_fields,
  46252         SOC_RESET_VAL_DEC(0x00000249, 0x00000000)
  46253         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  46254         -1,
  46255         -1,
  46256     },
  46257 #endif /* chips */
  46258 
  46259 #if defined(BCM_56270_A0)
  46260     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG1_BCM56270_A0r */
  46261         soc_block_list[85],
  46262         soc_genreg,
  46263         1,
  46264         0,
  46265         0x200af00,
  46266         0,
  46267         0,
  46268         8,
  46269         soc_LLS_L0_ECC_DEBUG1_BCM56260_A0r_fields,
  46270         SOC_RESET_VAL_DEC(0x00000249, 0x00000000)
  46271         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  46272         -1,
  46273         -1,
  46274     },
  46275 #endif /* chips */
  46276 
  46277 #if defined(BCM_56440_B0)
  46278     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG1_BCM56440_B0r */
  46279         soc_block_list[85],
  46280         soc_genreg,
  46281         1,
  46282         0,
  46283         0x80075,
  46284         0,
  46285         0,
  46286         4,
  46287         soc_LLS_L0_ECC_DEBUG1r_fields,
  46288         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  46289         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  46290         -1,
  46291         -1,
  46292     },
  46293 #endif /* chips */
  46294 
  46295 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46296     defined(BCM_56450_B1)
  46297     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG1_BCM56450_A0r */
  46298         soc_block_list[85],
  46299         soc_genreg,
  46300         1,
  46301         0,
  46302         0x2014a00,
  46303         0,
  46304         0,
  46305         4,
  46306         soc_LLS_L0_ECC_DEBUG1_BCM56450_A0r_fields,
  46307         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  46308         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  46309         -1,
  46310         -1,
  46311     },
  46312 #endif /* chips */
  46313 
  46314 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  46315     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG1_BCM56560_A0r */
  46316         soc_block_list[4],
  46317         soc_genreg,
  46318         1,
  46319         0,
  46320         0x62007300,
  46321         0,
  46322         0,
  46323         4,
  46324         soc_LLS_L0_ECC_DEBUG1_BCM56560_A0r_fields,
  46325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46326         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  46327         -1,
  46328         -1,
  46329     },
  46330 #endif /* chips */
  46331 
  46332 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46333     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG_BCM56260_A0r */
  46334         soc_block_list[85],
  46335         soc_genreg,
  46336         1,
  46337         0,
  46338         0x200c700,
  46339         0,
  46340         0,
  46341         20,
  46342         soc_LLS_L0_ECC_DEBUG_BCM56260_A0r_fields,
  46343         SOC_RESET_VAL_DEC(0x09249249, 0x00000000)
  46344         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  46345         -1,
  46346         -1,
  46347     },
  46348 #endif /* chips */
  46349 
  46350 #if defined(BCM_56270_A0)
  46351     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG_BCM56270_A0r */
  46352         soc_block_list[85],
  46353         soc_genreg,
  46354         1,
  46355         0,
  46356         0x200ae00,
  46357         0,
  46358         0,
  46359         20,
  46360         soc_LLS_L0_ECC_DEBUG_BCM56260_A0r_fields,
  46361         SOC_RESET_VAL_DEC(0x09249249, 0x00000000)
  46362         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  46363         -1,
  46364         -1,
  46365     },
  46366 #endif /* chips */
  46367 
  46368 #if defined(BCM_56440_B0)
  46369     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG_BCM56440_B0r */
  46370         soc_block_list[85],
  46371         soc_genreg,
  46372         1,
  46373         0,
  46374         0x80074,
  46375         0,
  46376         0,
  46377         24,
  46378         soc_LLS_L0_ECC_DEBUGr_fields,
  46379         SOC_RESET_VAL_DEC(0x00555555, 0x00000000)
  46380         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  46381         -1,
  46382         -1,
  46383     },
  46384 #endif /* chips */
  46385 
  46386 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46387     defined(BCM_56450_B1)
  46388     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG_BCM56450_A0r */
  46389         soc_block_list[85],
  46390         soc_genreg,
  46391         1,
  46392         0,
  46393         0x2014900,
  46394         0,
  46395         0,
  46396         24,
  46397         soc_LLS_L0_ECC_DEBUG_BCM56450_A0r_fields,
  46398         SOC_RESET_VAL_DEC(0x00555555, 0x00000000)
  46399         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  46400         -1,
  46401         -1,
  46402     },
  46403 #endif /* chips */
  46404 
  46405 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  46406     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG_BCM56560_A0r */
  46407         soc_block_list[4],
  46408         soc_genreg,
  46409         1,
  46410         0,
  46411         0x62007200,
  46412         0,
  46413         0,
  46414         18,
  46415         soc_LLS_L0_ECC_DEBUG_BCM56560_A0r_fields,
  46416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46417         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  46418         -1,
  46419         -1,
  46420     },
  46421 #endif /* chips */
  46422 
  46423 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  46424     { /* SOC_REG_INT_LLS_L0_ECC_DEBUG_BCM56640_A0r */
  46425         soc_block_list[4],
  46426         soc_genreg,
  46427         1,
  46428         0,
  46429         0x5a007700,
  46430         0,
  46431         0,
  46432         12,
  46433         soc_LLS_L0_ECC_DEBUG_BCM56640_A0r_fields,
  46434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46435         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  46436         -1,
  46437         -1,
  46438     },
  46439 #endif /* chips */
  46440 
  46441 #if defined(BCM_56440_A0)
  46442     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1r */
  46443         soc_block_list[85],
  46444         soc_genreg,
  46445         1,
  46446         0,
  46447         0x80075,
  46448         0,
  46449         0,
  46450         28,
  46451         soc_LLS_L0_ECC_ERROR1r_fields,
  46452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46453         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46454         -1,
  46455         -1,
  46456     },
  46457 #endif /* chips */
  46458 
  46459 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46460     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_BCM56260_A0r */
  46461         soc_block_list[85],
  46462         soc_genreg,
  46463         1,
  46464         0,
  46465         0x200d000,
  46466         0,
  46467         0,
  46468         28,
  46469         soc_LLS_L0_ECC_ERROR1_BCM56260_A0r_fields,
  46470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46471         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46472         -1,
  46473         -1,
  46474     },
  46475 #endif /* chips */
  46476 
  46477 #if defined(BCM_56270_A0)
  46478     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_BCM56270_A0r */
  46479         soc_block_list[85],
  46480         soc_genreg,
  46481         1,
  46482         0,
  46483         0x200b700,
  46484         0,
  46485         0,
  46486         28,
  46487         soc_LLS_L0_ECC_ERROR1_BCM56260_A0r_fields,
  46488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46489         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46490         -1,
  46491         -1,
  46492     },
  46493 #endif /* chips */
  46494 
  46495 #if defined(BCM_56440_B0)
  46496     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_BCM56440_B0r */
  46497         soc_block_list[85],
  46498         soc_genreg,
  46499         1,
  46500         0,
  46501         0x8007d,
  46502         0,
  46503         0,
  46504         28,
  46505         soc_LLS_L0_ECC_ERROR1r_fields,
  46506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46507         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46508         -1,
  46509         -1,
  46510     },
  46511 #endif /* chips */
  46512 
  46513 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46514     defined(BCM_56450_B1)
  46515     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_BCM56450_A0r */
  46516         soc_block_list[85],
  46517         soc_genreg,
  46518         1,
  46519         0,
  46520         0x2015200,
  46521         0,
  46522         0,
  46523         28,
  46524         soc_LLS_L0_ECC_ERROR1_BCM56450_A0r_fields,
  46525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46526         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46527         -1,
  46528         -1,
  46529     },
  46530 #endif /* chips */
  46531 
  46532 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  46533     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_BCM56640_A0r */
  46534         soc_block_list[4],
  46535         soc_genreg,
  46536         1,
  46537         0,
  46538         0x5a007b00,
  46539         0,
  46540         0,
  46541         24,
  46542         soc_LLS_L0_ECC_ERROR1_BCM56640_A0r_fields,
  46543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46544         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  46545         -1,
  46546         -1,
  46547     },
  46548 #endif /* chips */
  46549 
  46550 #if defined(BCM_56440_A0)
  46551     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_MASKr */
  46552         soc_block_list[85],
  46553         soc_genreg,
  46554         1,
  46555         0,
  46556         0x80076,
  46557         0,
  46558         0,
  46559         28,
  46560         soc_LLS_L0_ECC_ERROR1_MASKr_fields,
  46561         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  46562         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46563         -1,
  46564         -1,
  46565     },
  46566 #endif /* chips */
  46567 
  46568 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46569     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_MASK_BCM56260_A0r */
  46570         soc_block_list[85],
  46571         soc_genreg,
  46572         1,
  46573         0,
  46574         0x200d100,
  46575         0,
  46576         0,
  46577         28,
  46578         soc_LLS_L0_ECC_ERROR1_MASK_BCM56260_A0r_fields,
  46579         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  46580         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46581         -1,
  46582         -1,
  46583     },
  46584 #endif /* chips */
  46585 
  46586 #if defined(BCM_56270_A0)
  46587     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_MASK_BCM56270_A0r */
  46588         soc_block_list[85],
  46589         soc_genreg,
  46590         1,
  46591         0,
  46592         0x200b800,
  46593         0,
  46594         0,
  46595         28,
  46596         soc_LLS_L0_ECC_ERROR1_MASK_BCM56260_A0r_fields,
  46597         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  46598         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46599         -1,
  46600         -1,
  46601     },
  46602 #endif /* chips */
  46603 
  46604 #if defined(BCM_56440_B0)
  46605     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_MASK_BCM56440_B0r */
  46606         soc_block_list[85],
  46607         soc_genreg,
  46608         1,
  46609         0,
  46610         0x8007e,
  46611         0,
  46612         0,
  46613         28,
  46614         soc_LLS_L0_ECC_ERROR1_MASKr_fields,
  46615         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  46616         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46617         -1,
  46618         -1,
  46619     },
  46620 #endif /* chips */
  46621 
  46622 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46623     defined(BCM_56450_B1)
  46624     { /* SOC_REG_INT_LLS_L0_ECC_ERROR1_MASK_BCM56450_A0r */
  46625         soc_block_list[85],
  46626         soc_genreg,
  46627         1,
  46628         0,
  46629         0x2015300,
  46630         0,
  46631         0,
  46632         28,
  46633         soc_LLS_L0_ECC_ERROR1_MASK_BCM56450_A0r_fields,
  46634         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  46635         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  46636         -1,
  46637         -1,
  46638     },
  46639 #endif /* chips */
  46640 
  46641 #if defined(BCM_56440_A0)
  46642     { /* SOC_REG_INT_LLS_L0_EF_NEXT_ECC_STATUSr */
  46643         soc_block_list[85],
  46644         soc_genreg,
  46645         1,
  46646         0,
  46647         0x8008a,
  46648         0,
  46649         0,
  46650         1,
  46651         soc_LLS_L0_EF_NEXT_ECC_STATUSr_fields,
  46652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46653         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46654         -1,
  46655         -1,
  46656     },
  46657 #endif /* chips */
  46658 
  46659 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46660     { /* SOC_REG_INT_LLS_L0_EF_NEXT_ECC_STATUS_BCM56260_A0r */
  46661         soc_block_list[85],
  46662         soc_genreg,
  46663         1,
  46664         0,
  46665         0x200e400,
  46666         0,
  46667         0,
  46668         1,
  46669         soc_LLS_L0_EF_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  46670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46671         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  46672         -1,
  46673         -1,
  46674     },
  46675 #endif /* chips */
  46676 
  46677 #if defined(BCM_56270_A0)
  46678     { /* SOC_REG_INT_LLS_L0_EF_NEXT_ECC_STATUS_BCM56270_A0r */
  46679         soc_block_list[85],
  46680         soc_genreg,
  46681         1,
  46682         0,
  46683         0x200cb00,
  46684         0,
  46685         0,
  46686         1,
  46687         soc_LLS_L0_EF_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  46688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46689         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  46690         -1,
  46691         -1,
  46692     },
  46693 #endif /* chips */
  46694 
  46695 #if defined(BCM_56440_B0)
  46696     { /* SOC_REG_INT_LLS_L0_EF_NEXT_ECC_STATUS_BCM56440_B0r */
  46697         soc_block_list[85],
  46698         soc_genreg,
  46699         1,
  46700         0,
  46701         0x80092,
  46702         0,
  46703         0,
  46704         1,
  46705         soc_LLS_L0_EF_NEXT_ECC_STATUSr_fields,
  46706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46707         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46708         -1,
  46709         -1,
  46710     },
  46711 #endif /* chips */
  46712 
  46713 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46714     defined(BCM_56450_B1)
  46715     { /* SOC_REG_INT_LLS_L0_EF_NEXT_ECC_STATUS_BCM56450_A0r */
  46716         soc_block_list[85],
  46717         soc_genreg,
  46718         1,
  46719         0,
  46720         0x2016c00,
  46721         0,
  46722         0,
  46723         1,
  46724         soc_LLS_L0_EF_NEXT_ECC_STATUS_BCM56450_A0r_fields,
  46725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46726         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46727         -1,
  46728         -1,
  46729     },
  46730 #endif /* chips */
  46731 
  46732 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  46733     { /* SOC_REG_INT_LLS_L0_EF_NEXT_ECC_STATUS_BCM56640_A0r */
  46734         soc_block_list[4],
  46735         soc_genreg,
  46736         1,
  46737         0,
  46738         0x5a008a00,
  46739         0,
  46740         0,
  46741         1,
  46742         soc_LLS_L0_EF_NEXT_ECC_STATUS_BCM56640_A0r_fields,
  46743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46744         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46745         -1,
  46746         -1,
  46747     },
  46748 #endif /* chips */
  46749 
  46750 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46751     defined(BCM_56450_B1)
  46752     { /* SOC_REG_INT_LLS_L0_EMPTY_SEEN_STATUSr */
  46753         soc_block_list[85],
  46754         soc_genreg,
  46755         1,
  46756         0,
  46757         0x2010f00,
  46758         0,
  46759         0,
  46760         1,
  46761         soc_LLS_L0_EMPTY_SEEN_STATUSr_fields,
  46762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46763         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46764         -1,
  46765         -1,
  46766     },
  46767 #endif /* chips */
  46768 
  46769 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46770     { /* SOC_REG_INT_LLS_L0_EMPTY_SEEN_STATUS_BCM56260_A0r */
  46771         soc_block_list[85],
  46772         soc_genreg,
  46773         1,
  46774         0,
  46775         0x2009000,
  46776         0,
  46777         0,
  46778         1,
  46779         soc_LLS_L0_EMPTY_SEEN_STATUS_BCM56260_A0r_fields,
  46780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46781         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  46782         -1,
  46783         -1,
  46784     },
  46785 #endif /* chips */
  46786 
  46787 #if defined(BCM_56270_A0)
  46788     { /* SOC_REG_INT_LLS_L0_EMPTY_SEEN_STATUS_BCM56270_A0r */
  46789         soc_block_list[85],
  46790         soc_genreg,
  46791         1,
  46792         0,
  46793         0x2007700,
  46794         0,
  46795         0,
  46796         1,
  46797         soc_LLS_L0_EMPTY_SEEN_STATUS_BCM56270_A0r_fields,
  46798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46799         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  46800         -1,
  46801         -1,
  46802     },
  46803 #endif /* chips */
  46804 
  46805 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  46806     { /* SOC_REG_INT_LLS_L0_EMPTY_SEEN_STATUS_BCM56560_A0r */
  46807         soc_block_list[4],
  46808         soc_genreg,
  46809         1,
  46810         0,
  46811         0x62003f00,
  46812         0,
  46813         0,
  46814         1,
  46815         soc_LLS_L0_EMPTY_SEEN_STATUS_BCM56560_A0r_fields,
  46816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46817         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  46818         -1,
  46819         -1,
  46820     },
  46821 #endif /* chips */
  46822 
  46823 #if defined(BCM_56440_A0)
  46824     { /* SOC_REG_INT_LLS_L0_ERROR_ECC_STATUSr */
  46825         soc_block_list[85],
  46826         soc_genreg,
  46827         1,
  46828         0,
  46829         0x800a8,
  46830         0,
  46831         0,
  46832         1,
  46833         soc_LLS_L0_ERROR_ECC_STATUSr_fields,
  46834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46835         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46836         -1,
  46837         -1,
  46838     },
  46839 #endif /* chips */
  46840 
  46841 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46842     { /* SOC_REG_INT_LLS_L0_ERROR_ECC_STATUS_BCM56260_A0r */
  46843         soc_block_list[85],
  46844         soc_genreg,
  46845         1,
  46846         0,
  46847         0x200fd00,
  46848         0,
  46849         0,
  46850         1,
  46851         soc_LLS_L0_ERROR_ECC_STATUS_BCM56260_A0r_fields,
  46852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46853         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46854         -1,
  46855         -1,
  46856     },
  46857 #endif /* chips */
  46858 
  46859 #if defined(BCM_56270_A0)
  46860     { /* SOC_REG_INT_LLS_L0_ERROR_ECC_STATUS_BCM56270_A0r */
  46861         soc_block_list[85],
  46862         soc_genreg,
  46863         1,
  46864         0,
  46865         0x200e400,
  46866         0,
  46867         0,
  46868         1,
  46869         soc_LLS_L0_ERROR_ECC_STATUS_BCM56270_A0r_fields,
  46870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46871         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  46872         -1,
  46873         -1,
  46874     },
  46875 #endif /* chips */
  46876 
  46877 #if defined(BCM_56440_B0)
  46878     { /* SOC_REG_INT_LLS_L0_ERROR_ECC_STATUS_BCM56440_B0r */
  46879         soc_block_list[85],
  46880         soc_genreg,
  46881         1,
  46882         0,
  46883         0x800b0,
  46884         0,
  46885         0,
  46886         1,
  46887         soc_LLS_L0_ERROR_ECC_STATUSr_fields,
  46888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46889         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46890         -1,
  46891         -1,
  46892     },
  46893 #endif /* chips */
  46894 
  46895 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46896     defined(BCM_56450_B1)
  46897     { /* SOC_REG_INT_LLS_L0_ERROR_ECC_STATUS_BCM56450_A0r */
  46898         soc_block_list[85],
  46899         soc_genreg,
  46900         1,
  46901         0,
  46902         0x2018c00,
  46903         0,
  46904         0,
  46905         1,
  46906         soc_LLS_L0_ERROR_ECC_STATUS_BCM56450_A0r_fields,
  46907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46908         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46909         -1,
  46910         -1,
  46911     },
  46912 #endif /* chips */
  46913 
  46914 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  46915     { /* SOC_REG_INT_LLS_L0_ERROR_ECC_STATUS_BCM56640_A0r */
  46916         soc_block_list[4],
  46917         soc_genreg,
  46918         1,
  46919         0,
  46920         0x5a008b00,
  46921         0,
  46922         0,
  46923         1,
  46924         soc_LLS_L0_ERROR_ECC_STATUS_BCM56640_A0r_fields,
  46925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46926         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46927         -1,
  46928         -1,
  46929     },
  46930 #endif /* chips */
  46931 
  46932 #if defined(BCM_56440_B0)
  46933     { /* SOC_REG_INT_LLS_L0_ERROR_MIN_ECC_STATUSr */
  46934         soc_block_list[85],
  46935         soc_genreg,
  46936         1,
  46937         0,
  46938         0x800b3,
  46939         0,
  46940         0,
  46941         1,
  46942         soc_LLS_L0_ERROR_MIN_ECC_STATUSr_fields,
  46943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46944         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46945         -1,
  46946         -1,
  46947     },
  46948 #endif /* chips */
  46949 
  46950 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46951     defined(BCM_56450_B1)
  46952     { /* SOC_REG_INT_LLS_L0_ERROR_MIN_ECC_STATUS_BCM56450_A0r */
  46953         soc_block_list[85],
  46954         soc_genreg,
  46955         1,
  46956         0,
  46957         0x2018f00,
  46958         0,
  46959         0,
  46960         1,
  46961         soc_LLS_L0_ERROR_MIN_ECC_STATUS_BCM56450_A0r_fields,
  46962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46963         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46964         -1,
  46965         -1,
  46966     },
  46967 #endif /* chips */
  46968 
  46969 #if defined(BCM_56440_A0)
  46970     { /* SOC_REG_INT_LLS_L0_HEADS_TAILS_ECC_STATUSr */
  46971         soc_block_list[85],
  46972         soc_genreg,
  46973         1,
  46974         0,
  46975         0x80083,
  46976         0,
  46977         0,
  46978         1,
  46979         soc_LLS_L0_HEADS_TAILS_ECC_STATUSr_fields,
  46980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46981         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46982         -1,
  46983         -1,
  46984     },
  46985 #endif /* chips */
  46986 
  46987 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46988     { /* SOC_REG_INT_LLS_L0_HEADS_TAILS_ECC_STATUS_BCM56260_A0r */
  46989         soc_block_list[85],
  46990         soc_genreg,
  46991         1,
  46992         0,
  46993         0x200dd00,
  46994         0,
  46995         0,
  46996         1,
  46997         soc_LLS_L0_HEADS_TAILS_ECC_STATUS_BCM56260_A0r_fields,
  46998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46999         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47000         -1,
  47001         -1,
  47002     },
  47003 #endif /* chips */
  47004 
  47005 #if defined(BCM_56270_A0)
  47006     { /* SOC_REG_INT_LLS_L0_HEADS_TAILS_ECC_STATUS_BCM56270_A0r */
  47007         soc_block_list[85],
  47008         soc_genreg,
  47009         1,
  47010         0,
  47011         0x200c400,
  47012         0,
  47013         0,
  47014         1,
  47015         soc_LLS_L0_HEADS_TAILS_ECC_STATUS_BCM56270_A0r_fields,
  47016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47017         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47018         -1,
  47019         -1,
  47020     },
  47021 #endif /* chips */
  47022 
  47023 #if defined(BCM_56440_B0)
  47024     { /* SOC_REG_INT_LLS_L0_HEADS_TAILS_ECC_STATUS_BCM56440_B0r */
  47025         soc_block_list[85],
  47026         soc_genreg,
  47027         1,
  47028         0,
  47029         0x8008b,
  47030         0,
  47031         0,
  47032         1,
  47033         soc_LLS_L0_HEADS_TAILS_ECC_STATUSr_fields,
  47034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47035         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47036         -1,
  47037         -1,
  47038     },
  47039 #endif /* chips */
  47040 
  47041 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47042     defined(BCM_56450_B1)
  47043     { /* SOC_REG_INT_LLS_L0_HEADS_TAILS_ECC_STATUS_BCM56450_A0r */
  47044         soc_block_list[85],
  47045         soc_genreg,
  47046         1,
  47047         0,
  47048         0x2016500,
  47049         0,
  47050         0,
  47051         1,
  47052         soc_LLS_L0_HEADS_TAILS_ECC_STATUS_BCM56450_A0r_fields,
  47053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47054         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47055         -1,
  47056         -1,
  47057     },
  47058 #endif /* chips */
  47059 
  47060 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  47061     { /* SOC_REG_INT_LLS_L0_HEADS_TAILS_ECC_STATUS_BCM56640_A0r */
  47062         soc_block_list[4],
  47063         soc_genreg,
  47064         1,
  47065         0,
  47066         0x5a008300,
  47067         0,
  47068         0,
  47069         1,
  47070         soc_LLS_L0_HEADS_TAILS_ECC_STATUS_BCM56640_A0r_fields,
  47071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47072         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47073         -1,
  47074         -1,
  47075     },
  47076 #endif /* chips */
  47077 
  47078 #if defined(BCM_56440_A0)
  47079     { /* SOC_REG_INT_LLS_L0_MIN_BUCKET_C_ECC_STATUSr */
  47080         soc_block_list[85],
  47081         soc_genreg,
  47082         1,
  47083         0,
  47084         0x80085,
  47085         0,
  47086         0,
  47087         1,
  47088         soc_LLS_L0_MIN_BUCKET_C_ECC_STATUSr_fields,
  47089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47090         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47091         -1,
  47092         -1,
  47093     },
  47094 #endif /* chips */
  47095 
  47096 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47097     { /* SOC_REG_INT_LLS_L0_MIN_BUCKET_C_ECC_STATUS_BCM56260_A0r */
  47098         soc_block_list[85],
  47099         soc_genreg,
  47100         1,
  47101         0,
  47102         0x200df00,
  47103         0,
  47104         0,
  47105         1,
  47106         soc_LLS_L0_MIN_BUCKET_C_ECC_STATUS_BCM56260_A0r_fields,
  47107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47108         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47109         -1,
  47110         -1,
  47111     },
  47112 #endif /* chips */
  47113 
  47114 #if defined(BCM_56270_A0)
  47115     { /* SOC_REG_INT_LLS_L0_MIN_BUCKET_C_ECC_STATUS_BCM56270_A0r */
  47116         soc_block_list[85],
  47117         soc_genreg,
  47118         1,
  47119         0,
  47120         0x200c600,
  47121         0,
  47122         0,
  47123         1,
  47124         soc_LLS_L0_MIN_BUCKET_C_ECC_STATUS_BCM56270_A0r_fields,
  47125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47126         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47127         -1,
  47128         -1,
  47129     },
  47130 #endif /* chips */
  47131 
  47132 #if defined(BCM_56440_B0)
  47133     { /* SOC_REG_INT_LLS_L0_MIN_BUCKET_C_ECC_STATUS_BCM56440_B0r */
  47134         soc_block_list[85],
  47135         soc_genreg,
  47136         1,
  47137         0,
  47138         0x8008d,
  47139         0,
  47140         0,
  47141         1,
  47142         soc_LLS_L0_MIN_BUCKET_C_ECC_STATUSr_fields,
  47143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47144         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47145         -1,
  47146         -1,
  47147     },
  47148 #endif /* chips */
  47149 
  47150 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47151     defined(BCM_56450_B1)
  47152     { /* SOC_REG_INT_LLS_L0_MIN_BUCKET_C_ECC_STATUS_BCM56450_A0r */
  47153         soc_block_list[85],
  47154         soc_genreg,
  47155         1,
  47156         0,
  47157         0x2016700,
  47158         0,
  47159         0,
  47160         1,
  47161         soc_LLS_L0_MIN_BUCKET_C_ECC_STATUS_BCM56450_A0r_fields,
  47162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47163         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47164         -1,
  47165         -1,
  47166     },
  47167 #endif /* chips */
  47168 
  47169 #if defined(BCM_56440_A0)
  47170     { /* SOC_REG_INT_LLS_L0_MIN_CONFIG_C_ECC_STATUSr */
  47171         soc_block_list[85],
  47172         soc_genreg,
  47173         1,
  47174         0,
  47175         0x80081,
  47176         0,
  47177         0,
  47178         1,
  47179         soc_LLS_L0_MIN_CONFIG_C_ECC_STATUSr_fields,
  47180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47181         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47182         -1,
  47183         -1,
  47184     },
  47185 #endif /* chips */
  47186 
  47187 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47188     { /* SOC_REG_INT_LLS_L0_MIN_CONFIG_C_ECC_STATUS_BCM56260_A0r */
  47189         soc_block_list[85],
  47190         soc_genreg,
  47191         1,
  47192         0,
  47193         0x200db00,
  47194         0,
  47195         0,
  47196         1,
  47197         soc_LLS_L0_MIN_CONFIG_C_ECC_STATUS_BCM56260_A0r_fields,
  47198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47199         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47200         -1,
  47201         -1,
  47202     },
  47203 #endif /* chips */
  47204 
  47205 #if defined(BCM_56270_A0)
  47206     { /* SOC_REG_INT_LLS_L0_MIN_CONFIG_C_ECC_STATUS_BCM56270_A0r */
  47207         soc_block_list[85],
  47208         soc_genreg,
  47209         1,
  47210         0,
  47211         0x200c200,
  47212         0,
  47213         0,
  47214         1,
  47215         soc_LLS_L0_MIN_CONFIG_C_ECC_STATUS_BCM56270_A0r_fields,
  47216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47217         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47218         -1,
  47219         -1,
  47220     },
  47221 #endif /* chips */
  47222 
  47223 #if defined(BCM_56440_B0)
  47224     { /* SOC_REG_INT_LLS_L0_MIN_CONFIG_C_ECC_STATUS_BCM56440_B0r */
  47225         soc_block_list[85],
  47226         soc_genreg,
  47227         1,
  47228         0,
  47229         0x80089,
  47230         0,
  47231         0,
  47232         1,
  47233         soc_LLS_L0_MIN_CONFIG_C_ECC_STATUSr_fields,
  47234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47235         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47236         -1,
  47237         -1,
  47238     },
  47239 #endif /* chips */
  47240 
  47241 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47242     defined(BCM_56450_B1)
  47243     { /* SOC_REG_INT_LLS_L0_MIN_CONFIG_C_ECC_STATUS_BCM56450_A0r */
  47244         soc_block_list[85],
  47245         soc_genreg,
  47246         1,
  47247         0,
  47248         0x2016300,
  47249         0,
  47250         0,
  47251         1,
  47252         soc_LLS_L0_MIN_CONFIG_C_ECC_STATUS_BCM56450_A0r_fields,
  47253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47254         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47255         -1,
  47256         -1,
  47257     },
  47258 #endif /* chips */
  47259 
  47260 #if defined(BCM_56440_A0)
  47261     { /* SOC_REG_INT_LLS_L0_MIN_NEXT_ECC_STATUSr */
  47262         soc_block_list[85],
  47263         soc_genreg,
  47264         1,
  47265         0,
  47266         0x80089,
  47267         0,
  47268         0,
  47269         1,
  47270         soc_LLS_L0_MIN_NEXT_ECC_STATUSr_fields,
  47271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47272         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47273         -1,
  47274         -1,
  47275     },
  47276 #endif /* chips */
  47277 
  47278 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47279     { /* SOC_REG_INT_LLS_L0_MIN_NEXT_ECC_STATUS_BCM56260_A0r */
  47280         soc_block_list[85],
  47281         soc_genreg,
  47282         1,
  47283         0,
  47284         0x200e300,
  47285         0,
  47286         0,
  47287         1,
  47288         soc_LLS_L0_MIN_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  47289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47290         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47291         -1,
  47292         -1,
  47293     },
  47294 #endif /* chips */
  47295 
  47296 #if defined(BCM_56270_A0)
  47297     { /* SOC_REG_INT_LLS_L0_MIN_NEXT_ECC_STATUS_BCM56270_A0r */
  47298         soc_block_list[85],
  47299         soc_genreg,
  47300         1,
  47301         0,
  47302         0x200ca00,
  47303         0,
  47304         0,
  47305         1,
  47306         soc_LLS_L0_MIN_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  47307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47308         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47309         -1,
  47310         -1,
  47311     },
  47312 #endif /* chips */
  47313 
  47314 #if defined(BCM_56440_B0)
  47315     { /* SOC_REG_INT_LLS_L0_MIN_NEXT_ECC_STATUS_BCM56440_B0r */
  47316         soc_block_list[85],
  47317         soc_genreg,
  47318         1,
  47319         0,
  47320         0x80091,
  47321         0,
  47322         0,
  47323         1,
  47324         soc_LLS_L0_MIN_NEXT_ECC_STATUSr_fields,
  47325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47326         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47327         -1,
  47328         -1,
  47329     },
  47330 #endif /* chips */
  47331 
  47332 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47333     defined(BCM_56450_B1)
  47334     { /* SOC_REG_INT_LLS_L0_MIN_NEXT_ECC_STATUS_BCM56450_A0r */
  47335         soc_block_list[85],
  47336         soc_genreg,
  47337         1,
  47338         0,
  47339         0x2016b00,
  47340         0,
  47341         0,
  47342         1,
  47343         soc_LLS_L0_MIN_NEXT_ECC_STATUS_BCM56450_A0r_fields,
  47344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47345         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47346         -1,
  47347         -1,
  47348     },
  47349 #endif /* chips */
  47350 
  47351 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  47352     { /* SOC_REG_INT_LLS_L0_MIN_NEXT_ECC_STATUS_BCM56640_A0r */
  47353         soc_block_list[4],
  47354         soc_genreg,
  47355         1,
  47356         0,
  47357         0x5a008900,
  47358         0,
  47359         0,
  47360         1,
  47361         soc_LLS_L0_MIN_NEXT_ECC_STATUS_BCM56640_A0r_fields,
  47362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47363         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47364         -1,
  47365         -1,
  47366     },
  47367 #endif /* chips */
  47368 
  47369 #if defined(BCM_56440_A0)
  47370     { /* SOC_REG_INT_LLS_L0_PARENT_ECC_STATUSr */
  47371         soc_block_list[85],
  47372         soc_genreg,
  47373         1,
  47374         0,
  47375         0x8007f,
  47376         0,
  47377         0,
  47378         1,
  47379         soc_LLS_L0_PARENT_ECC_STATUSr_fields,
  47380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47381         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47382         -1,
  47383         -1,
  47384     },
  47385 #endif /* chips */
  47386 
  47387 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47388     { /* SOC_REG_INT_LLS_L0_PARENT_ECC_STATUS_BCM56260_A0r */
  47389         soc_block_list[85],
  47390         soc_genreg,
  47391         1,
  47392         0,
  47393         0x200d800,
  47394         0,
  47395         0,
  47396         1,
  47397         soc_LLS_L0_PARENT_ECC_STATUS_BCM56260_A0r_fields,
  47398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47399         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47400         -1,
  47401         -1,
  47402     },
  47403 #endif /* chips */
  47404 
  47405 #if defined(BCM_56270_A0)
  47406     { /* SOC_REG_INT_LLS_L0_PARENT_ECC_STATUS_BCM56270_A0r */
  47407         soc_block_list[85],
  47408         soc_genreg,
  47409         1,
  47410         0,
  47411         0x200bf00,
  47412         0,
  47413         0,
  47414         1,
  47415         soc_LLS_L0_PARENT_ECC_STATUS_BCM56260_A0r_fields,
  47416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47417         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47418         -1,
  47419         -1,
  47420     },
  47421 #endif /* chips */
  47422 
  47423 #if defined(BCM_56440_B0)
  47424     { /* SOC_REG_INT_LLS_L0_PARENT_ECC_STATUS_BCM56440_B0r */
  47425         soc_block_list[85],
  47426         soc_genreg,
  47427         1,
  47428         0,
  47429         0x80087,
  47430         0,
  47431         0,
  47432         1,
  47433         soc_LLS_L0_PARENT_ECC_STATUSr_fields,
  47434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47435         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47436         -1,
  47437         -1,
  47438     },
  47439 #endif /* chips */
  47440 
  47441 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47442     defined(BCM_56450_B1)
  47443     { /* SOC_REG_INT_LLS_L0_PARENT_ECC_STATUS_BCM56450_A0r */
  47444         soc_block_list[85],
  47445         soc_genreg,
  47446         1,
  47447         0,
  47448         0x2016100,
  47449         0,
  47450         0,
  47451         1,
  47452         soc_LLS_L0_PARENT_ECC_STATUS_BCM56450_A0r_fields,
  47453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47454         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47455         -1,
  47456         -1,
  47457     },
  47458 #endif /* chips */
  47459 
  47460 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  47461     { /* SOC_REG_INT_LLS_L0_PARENT_ECC_STATUS_BCM56640_A0r */
  47462         soc_block_list[4],
  47463         soc_genreg,
  47464         1,
  47465         0,
  47466         0x5a008000,
  47467         0,
  47468         0,
  47469         1,
  47470         soc_LLS_L0_PARENT_ECC_STATUS_BCM56640_A0r_fields,
  47471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47472         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47473         -1,
  47474         -1,
  47475     },
  47476 #endif /* chips */
  47477 
  47478 #if defined(BCM_56440_A0)
  47479     { /* SOC_REG_INT_LLS_L0_PARENT_STATE_ECC_STATUSr */
  47480         soc_block_list[85],
  47481         soc_genreg,
  47482         1,
  47483         0,
  47484         0x80082,
  47485         0,
  47486         0,
  47487         1,
  47488         soc_LLS_L0_PARENT_STATE_ECC_STATUSr_fields,
  47489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47490         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47491         -1,
  47492         -1,
  47493     },
  47494 #endif /* chips */
  47495 
  47496 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47497     { /* SOC_REG_INT_LLS_L0_PARENT_STATE_ECC_STATUS_BCM56260_A0r */
  47498         soc_block_list[85],
  47499         soc_genreg,
  47500         1,
  47501         0,
  47502         0x200dc00,
  47503         0,
  47504         0,
  47505         1,
  47506         soc_LLS_L0_PARENT_STATE_ECC_STATUS_BCM56260_A0r_fields,
  47507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47508         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47509         -1,
  47510         -1,
  47511     },
  47512 #endif /* chips */
  47513 
  47514 #if defined(BCM_56270_A0)
  47515     { /* SOC_REG_INT_LLS_L0_PARENT_STATE_ECC_STATUS_BCM56270_A0r */
  47516         soc_block_list[85],
  47517         soc_genreg,
  47518         1,
  47519         0,
  47520         0x200c300,
  47521         0,
  47522         0,
  47523         1,
  47524         soc_LLS_L0_PARENT_STATE_ECC_STATUS_BCM56270_A0r_fields,
  47525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47526         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47527         -1,
  47528         -1,
  47529     },
  47530 #endif /* chips */
  47531 
  47532 #if defined(BCM_56440_B0)
  47533     { /* SOC_REG_INT_LLS_L0_PARENT_STATE_ECC_STATUS_BCM56440_B0r */
  47534         soc_block_list[85],
  47535         soc_genreg,
  47536         1,
  47537         0,
  47538         0x8008a,
  47539         0,
  47540         0,
  47541         1,
  47542         soc_LLS_L0_PARENT_STATE_ECC_STATUSr_fields,
  47543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47544         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47545         -1,
  47546         -1,
  47547     },
  47548 #endif /* chips */
  47549 
  47550 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47551     defined(BCM_56450_B1)
  47552     { /* SOC_REG_INT_LLS_L0_PARENT_STATE_ECC_STATUS_BCM56450_A0r */
  47553         soc_block_list[85],
  47554         soc_genreg,
  47555         1,
  47556         0,
  47557         0x2016400,
  47558         0,
  47559         0,
  47560         1,
  47561         soc_LLS_L0_PARENT_STATE_ECC_STATUS_BCM56450_A0r_fields,
  47562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47563         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47564         -1,
  47565         -1,
  47566     },
  47567 #endif /* chips */
  47568 
  47569 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  47570     { /* SOC_REG_INT_LLS_L0_PARENT_STATE_ECC_STATUS_BCM56640_A0r */
  47571         soc_block_list[4],
  47572         soc_genreg,
  47573         1,
  47574         0,
  47575         0x5a008200,
  47576         0,
  47577         0,
  47578         1,
  47579         soc_LLS_L0_PARENT_STATE_ECC_STATUS_BCM56640_A0r_fields,
  47580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47581         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47582         -1,
  47583         -1,
  47584     },
  47585 #endif /* chips */
  47586 
  47587 #if defined(BCM_56440_A0)
  47588     { /* SOC_REG_INT_LLS_L0_SHAPER_BUCKET_C_ECC_STATUSr */
  47589         soc_block_list[85],
  47590         soc_genreg,
  47591         1,
  47592         0,
  47593         0x8008c,
  47594         0,
  47595         0,
  47596         1,
  47597         soc_LLS_L0_SHAPER_BUCKET_C_ECC_STATUSr_fields,
  47598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47599         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47600         -1,
  47601         -1,
  47602     },
  47603 #endif /* chips */
  47604 
  47605 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47606     { /* SOC_REG_INT_LLS_L0_SHAPER_BUCKET_C_ECC_STATUS_BCM56260_A0r */
  47607         soc_block_list[85],
  47608         soc_genreg,
  47609         1,
  47610         0,
  47611         0x200e500,
  47612         0,
  47613         0,
  47614         1,
  47615         soc_LLS_L0_SHAPER_BUCKET_C_ECC_STATUS_BCM56260_A0r_fields,
  47616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47617         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47618         -1,
  47619         -1,
  47620     },
  47621 #endif /* chips */
  47622 
  47623 #if defined(BCM_56270_A0)
  47624     { /* SOC_REG_INT_LLS_L0_SHAPER_BUCKET_C_ECC_STATUS_BCM56270_A0r */
  47625         soc_block_list[85],
  47626         soc_genreg,
  47627         1,
  47628         0,
  47629         0x200cc00,
  47630         0,
  47631         0,
  47632         1,
  47633         soc_LLS_L0_SHAPER_BUCKET_C_ECC_STATUS_BCM56270_A0r_fields,
  47634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47635         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47636         -1,
  47637         -1,
  47638     },
  47639 #endif /* chips */
  47640 
  47641 #if defined(BCM_56440_B0)
  47642     { /* SOC_REG_INT_LLS_L0_SHAPER_BUCKET_C_ECC_STATUS_BCM56440_B0r */
  47643         soc_block_list[85],
  47644         soc_genreg,
  47645         1,
  47646         0,
  47647         0x80094,
  47648         0,
  47649         0,
  47650         1,
  47651         soc_LLS_L0_SHAPER_BUCKET_C_ECC_STATUSr_fields,
  47652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47653         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47654         -1,
  47655         -1,
  47656     },
  47657 #endif /* chips */
  47658 
  47659 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47660     defined(BCM_56450_B1)
  47661     { /* SOC_REG_INT_LLS_L0_SHAPER_BUCKET_C_ECC_STATUS_BCM56450_A0r */
  47662         soc_block_list[85],
  47663         soc_genreg,
  47664         1,
  47665         0,
  47666         0x2016e00,
  47667         0,
  47668         0,
  47669         1,
  47670         soc_LLS_L0_SHAPER_BUCKET_C_ECC_STATUS_BCM56450_A0r_fields,
  47671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47672         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47673         -1,
  47674         -1,
  47675     },
  47676 #endif /* chips */
  47677 
  47678 #if defined(BCM_56440_A0)
  47679     { /* SOC_REG_INT_LLS_L0_SHAPER_CONFIG_C_ECC_STATUSr */
  47680         soc_block_list[85],
  47681         soc_genreg,
  47682         1,
  47683         0,
  47684         0x8008b,
  47685         0,
  47686         0,
  47687         1,
  47688         soc_LLS_L0_SHAPER_CONFIG_C_ECC_STATUSr_fields,
  47689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47690         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47691         -1,
  47692         -1,
  47693     },
  47694 #endif /* chips */
  47695 
  47696 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47697     { /* SOC_REG_INT_LLS_L0_SHAPER_CONFIG_C_ECC_STATUS_BCM56260_A0r */
  47698         soc_block_list[85],
  47699         soc_genreg,
  47700         1,
  47701         0,
  47702         0x200da00,
  47703         0,
  47704         0,
  47705         1,
  47706         soc_LLS_L0_SHAPER_CONFIG_C_ECC_STATUS_BCM56260_A0r_fields,
  47707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47708         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47709         -1,
  47710         -1,
  47711     },
  47712 #endif /* chips */
  47713 
  47714 #if defined(BCM_56270_A0)
  47715     { /* SOC_REG_INT_LLS_L0_SHAPER_CONFIG_C_ECC_STATUS_BCM56270_A0r */
  47716         soc_block_list[85],
  47717         soc_genreg,
  47718         1,
  47719         0,
  47720         0x200c100,
  47721         0,
  47722         0,
  47723         1,
  47724         soc_LLS_L0_SHAPER_CONFIG_C_ECC_STATUS_BCM56270_A0r_fields,
  47725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47726         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47727         -1,
  47728         -1,
  47729     },
  47730 #endif /* chips */
  47731 
  47732 #if defined(BCM_56440_B0)
  47733     { /* SOC_REG_INT_LLS_L0_SHAPER_CONFIG_C_ECC_STATUS_BCM56440_B0r */
  47734         soc_block_list[85],
  47735         soc_genreg,
  47736         1,
  47737         0,
  47738         0x80093,
  47739         0,
  47740         0,
  47741         1,
  47742         soc_LLS_L0_SHAPER_CONFIG_C_ECC_STATUSr_fields,
  47743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47744         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47745         -1,
  47746         -1,
  47747     },
  47748 #endif /* chips */
  47749 
  47750 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47751     defined(BCM_56450_B1)
  47752     { /* SOC_REG_INT_LLS_L0_SHAPER_CONFIG_C_ECC_STATUS_BCM56450_A0r */
  47753         soc_block_list[85],
  47754         soc_genreg,
  47755         1,
  47756         0,
  47757         0x2016d00,
  47758         0,
  47759         0,
  47760         1,
  47761         soc_LLS_L0_SHAPER_CONFIG_C_ECC_STATUS_BCM56450_A0r_fields,
  47762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47763         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47764         -1,
  47765         -1,
  47766     },
  47767 #endif /* chips */
  47768 
  47769 #if defined(BCM_56440_A0)
  47770     { /* SOC_REG_INT_LLS_L0_WERR_MAX_SC_ECC_STATUSr */
  47771         soc_block_list[85],
  47772         soc_genreg,
  47773         1,
  47774         0,
  47775         0x80084,
  47776         0,
  47777         0,
  47778         1,
  47779         soc_LLS_L0_WERR_MAX_SC_ECC_STATUSr_fields,
  47780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47781         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47782         -1,
  47783         -1,
  47784     },
  47785 #endif /* chips */
  47786 
  47787 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47788     { /* SOC_REG_INT_LLS_L0_WERR_MAX_SC_ECC_STATUS_BCM56260_A0r */
  47789         soc_block_list[85],
  47790         soc_genreg,
  47791         1,
  47792         0,
  47793         0x200de00,
  47794         0,
  47795         0,
  47796         1,
  47797         soc_LLS_L0_WERR_MAX_SC_ECC_STATUS_BCM56260_A0r_fields,
  47798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47799         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47800         -1,
  47801         -1,
  47802     },
  47803 #endif /* chips */
  47804 
  47805 #if defined(BCM_56270_A0)
  47806     { /* SOC_REG_INT_LLS_L0_WERR_MAX_SC_ECC_STATUS_BCM56270_A0r */
  47807         soc_block_list[85],
  47808         soc_genreg,
  47809         1,
  47810         0,
  47811         0x200c500,
  47812         0,
  47813         0,
  47814         1,
  47815         soc_LLS_L0_WERR_MAX_SC_ECC_STATUS_BCM56270_A0r_fields,
  47816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47817         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47818         -1,
  47819         -1,
  47820     },
  47821 #endif /* chips */
  47822 
  47823 #if defined(BCM_56440_B0)
  47824     { /* SOC_REG_INT_LLS_L0_WERR_MAX_SC_ECC_STATUS_BCM56440_B0r */
  47825         soc_block_list[85],
  47826         soc_genreg,
  47827         1,
  47828         0,
  47829         0x8008c,
  47830         0,
  47831         0,
  47832         1,
  47833         soc_LLS_L0_WERR_MAX_SC_ECC_STATUSr_fields,
  47834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47835         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47836         -1,
  47837         -1,
  47838     },
  47839 #endif /* chips */
  47840 
  47841 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47842     defined(BCM_56450_B1)
  47843     { /* SOC_REG_INT_LLS_L0_WERR_MAX_SC_ECC_STATUS_BCM56450_A0r */
  47844         soc_block_list[85],
  47845         soc_genreg,
  47846         1,
  47847         0,
  47848         0x2016600,
  47849         0,
  47850         0,
  47851         1,
  47852         soc_LLS_L0_WERR_MAX_SC_ECC_STATUS_BCM56450_A0r_fields,
  47853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47854         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47855         -1,
  47856         -1,
  47857     },
  47858 #endif /* chips */
  47859 
  47860 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  47861     { /* SOC_REG_INT_LLS_L0_WERR_MAX_SC_ECC_STATUS_BCM56640_A0r */
  47862         soc_block_list[4],
  47863         soc_genreg,
  47864         1,
  47865         0,
  47866         0x5a008400,
  47867         0,
  47868         0,
  47869         1,
  47870         soc_LLS_L0_WERR_MAX_SC_ECC_STATUS_BCM56640_A0r_fields,
  47871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47872         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47873         -1,
  47874         -1,
  47875     },
  47876 #endif /* chips */
  47877 
  47878 #if defined(BCM_56440_A0)
  47879     { /* SOC_REG_INT_LLS_L0_WERR_NEXT_ECC_STATUSr */
  47880         soc_block_list[85],
  47881         soc_genreg,
  47882         1,
  47883         0,
  47884         0x80088,
  47885         0,
  47886         0,
  47887         1,
  47888         soc_LLS_L0_WERR_NEXT_ECC_STATUSr_fields,
  47889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47890         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47891         -1,
  47892         -1,
  47893     },
  47894 #endif /* chips */
  47895 
  47896 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47897     { /* SOC_REG_INT_LLS_L0_WERR_NEXT_ECC_STATUS_BCM56260_A0r */
  47898         soc_block_list[85],
  47899         soc_genreg,
  47900         1,
  47901         0,
  47902         0x200e200,
  47903         0,
  47904         0,
  47905         1,
  47906         soc_LLS_L0_WERR_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  47907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47908         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47909         -1,
  47910         -1,
  47911     },
  47912 #endif /* chips */
  47913 
  47914 #if defined(BCM_56270_A0)
  47915     { /* SOC_REG_INT_LLS_L0_WERR_NEXT_ECC_STATUS_BCM56270_A0r */
  47916         soc_block_list[85],
  47917         soc_genreg,
  47918         1,
  47919         0,
  47920         0x200c900,
  47921         0,
  47922         0,
  47923         1,
  47924         soc_LLS_L0_WERR_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  47925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47926         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  47927         -1,
  47928         -1,
  47929     },
  47930 #endif /* chips */
  47931 
  47932 #if defined(BCM_56440_B0)
  47933     { /* SOC_REG_INT_LLS_L0_WERR_NEXT_ECC_STATUS_BCM56440_B0r */
  47934         soc_block_list[85],
  47935         soc_genreg,
  47936         1,
  47937         0,
  47938         0x80090,
  47939         0,
  47940         0,
  47941         1,
  47942         soc_LLS_L0_WERR_NEXT_ECC_STATUSr_fields,
  47943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47944         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47945         -1,
  47946         -1,
  47947     },
  47948 #endif /* chips */
  47949 
  47950 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47951     defined(BCM_56450_B1)
  47952     { /* SOC_REG_INT_LLS_L0_WERR_NEXT_ECC_STATUS_BCM56450_A0r */
  47953         soc_block_list[85],
  47954         soc_genreg,
  47955         1,
  47956         0,
  47957         0x2016a00,
  47958         0,
  47959         0,
  47960         1,
  47961         soc_LLS_L0_WERR_NEXT_ECC_STATUS_BCM56450_A0r_fields,
  47962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47963         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47964         -1,
  47965         -1,
  47966     },
  47967 #endif /* chips */
  47968 
  47969 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  47970     { /* SOC_REG_INT_LLS_L0_WERR_NEXT_ECC_STATUS_BCM56640_A0r */
  47971         soc_block_list[4],
  47972         soc_genreg,
  47973         1,
  47974         0,
  47975         0x5a008800,
  47976         0,
  47977         0,
  47978         1,
  47979         soc_LLS_L0_WERR_NEXT_ECC_STATUS_BCM56640_A0r_fields,
  47980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47981         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47982         -1,
  47983         -1,
  47984     },
  47985 #endif /* chips */
  47986 
  47987 #if defined(BCM_56440_A0)
  47988     { /* SOC_REG_INT_LLS_L1_CHILD_STATE1_ECC_STATUSr */
  47989         soc_block_list[85],
  47990         soc_genreg,
  47991         1,
  47992         0,
  47993         0x80094,
  47994         0,
  47995         0,
  47996         1,
  47997         soc_LLS_L1_CHILD_STATE1_ECC_STATUSr_fields,
  47998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47999         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48000         -1,
  48001         -1,
  48002     },
  48003 #endif /* chips */
  48004 
  48005 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48006     { /* SOC_REG_INT_LLS_L1_CHILD_STATE1_ECC_STATUS_BCM56260_A0r */
  48007         soc_block_list[85],
  48008         soc_genreg,
  48009         1,
  48010         0,
  48011         0x200ee00,
  48012         0,
  48013         0,
  48014         1,
  48015         soc_LLS_L1_CHILD_STATE1_ECC_STATUS_BCM56260_A0r_fields,
  48016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48017         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48018         -1,
  48019         -1,
  48020     },
  48021 #endif /* chips */
  48022 
  48023 #if defined(BCM_56270_A0)
  48024     { /* SOC_REG_INT_LLS_L1_CHILD_STATE1_ECC_STATUS_BCM56270_A0r */
  48025         soc_block_list[85],
  48026         soc_genreg,
  48027         1,
  48028         0,
  48029         0x200d500,
  48030         0,
  48031         0,
  48032         1,
  48033         soc_LLS_L1_CHILD_STATE1_ECC_STATUS_BCM56270_A0r_fields,
  48034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48035         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  48036         -1,
  48037         -1,
  48038     },
  48039 #endif /* chips */
  48040 
  48041 #if defined(BCM_56440_B0)
  48042     { /* SOC_REG_INT_LLS_L1_CHILD_STATE1_ECC_STATUS_BCM56440_B0r */
  48043         soc_block_list[85],
  48044         soc_genreg,
  48045         1,
  48046         0,
  48047         0x8009c,
  48048         0,
  48049         0,
  48050         1,
  48051         soc_LLS_L1_CHILD_STATE1_ECC_STATUSr_fields,
  48052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48053         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48054         -1,
  48055         -1,
  48056     },
  48057 #endif /* chips */
  48058 
  48059 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48060     defined(BCM_56450_B1)
  48061     { /* SOC_REG_INT_LLS_L1_CHILD_STATE1_ECC_STATUS_BCM56450_A0r */
  48062         soc_block_list[85],
  48063         soc_genreg,
  48064         1,
  48065         0,
  48066         0x2017600,
  48067         0,
  48068         0,
  48069         1,
  48070         soc_LLS_L1_CHILD_STATE1_ECC_STATUS_BCM56450_A0r_fields,
  48071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48072         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48073         -1,
  48074         -1,
  48075     },
  48076 #endif /* chips */
  48077 
  48078 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  48079     { /* SOC_REG_INT_LLS_L1_CHILD_STATE1_ECC_STATUS_BCM56640_A0r */
  48080         soc_block_list[4],
  48081         soc_genreg,
  48082         1,
  48083         0,
  48084         0x5a009100,
  48085         0,
  48086         0,
  48087         1,
  48088         soc_LLS_L1_CHILD_STATE1_ECC_STATUS_BCM56640_A0r_fields,
  48089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48090         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  48091         -1,
  48092         -1,
  48093     },
  48094 #endif /* chips */
  48095 
  48096 #if defined(BCM_56440_A0)
  48097     { /* SOC_REG_INT_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr */
  48098         soc_block_list[85],
  48099         soc_genreg,
  48100         1,
  48101         0,
  48102         0x80095,
  48103         0,
  48104         0,
  48105         1,
  48106         soc_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr_fields,
  48107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48108         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48109         -1,
  48110         -1,
  48111     },
  48112 #endif /* chips */
  48113 
  48114 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48115     { /* SOC_REG_INT_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56260_A0r */
  48116         soc_block_list[85],
  48117         soc_genreg,
  48118         1,
  48119         0,
  48120         0x200ef00,
  48121         0,
  48122         0,
  48123         1,
  48124         soc_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56260_A0r_fields,
  48125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48126         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48127         -1,
  48128         -1,
  48129     },
  48130 #endif /* chips */
  48131 
  48132 #if defined(BCM_56270_A0)
  48133     { /* SOC_REG_INT_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56270_A0r */
  48134         soc_block_list[85],
  48135         soc_genreg,
  48136         1,
  48137         0,
  48138         0x200d600,
  48139         0,
  48140         0,
  48141         1,
  48142         soc_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56270_A0r_fields,
  48143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48144         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  48145         -1,
  48146         -1,
  48147     },
  48148 #endif /* chips */
  48149 
  48150 #if defined(BCM_56440_B0)
  48151     { /* SOC_REG_INT_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56440_B0r */
  48152         soc_block_list[85],
  48153         soc_genreg,
  48154         1,
  48155         0,
  48156         0x8009d,
  48157         0,
  48158         0,
  48159         1,
  48160         soc_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr_fields,
  48161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48162         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48163         -1,
  48164         -1,
  48165     },
  48166 #endif /* chips */
  48167 
  48168 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48169     defined(BCM_56450_B1)
  48170     { /* SOC_REG_INT_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56450_A0r */
  48171         soc_block_list[85],
  48172         soc_genreg,
  48173         1,
  48174         0,
  48175         0x2017700,
  48176         0,
  48177         0,
  48178         1,
  48179         soc_LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUS_BCM56450_A0r_fields,
  48180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48181         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48182         -1,
  48183         -1,
  48184     },
  48185 #endif /* chips */
  48186 
  48187 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  48188     { /* SOC_REG_INT_LLS_L1_CHILD_WEIGHT_CFG_ECC_STATUSr */
  48189         soc_block_list[4],
  48190         soc_genreg,
  48191         1,
  48192         0,
  48193         0x5a009200,
  48194         0,
  48195         0,
  48196         1,
  48197         soc_LLS_L1_CHILD_WEIGHT_CFG_ECC_STATUSr_fields,
  48198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48199         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  48200         -1,
  48201         -1,
  48202     },
  48203 #endif /* chips */
  48204 
  48205 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  48206     { /* SOC_REG_INT_LLS_L1_CHILD_WEIGHT_WORKING_ECC_STATUSr */
  48207         soc_block_list[4],
  48208         soc_genreg,
  48209         1,
  48210         0,
  48211         0x5a009300,
  48212         0,
  48213         0,
  48214         1,
  48215         soc_LLS_L1_CHILD_WEIGHT_WORKING_ECC_STATUSr_fields,
  48216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48217         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  48218         -1,
  48219         -1,
  48220     },
  48221 #endif /* chips */
  48222 
  48223 #if defined(BCM_56440_A0)
  48224     { /* SOC_REG_INT_LLS_L1_CONFIG_ECC_STATUSr */
  48225         soc_block_list[85],
  48226         soc_genreg,
  48227         1,
  48228         0,
  48229         0x8008f,
  48230         0,
  48231         0,
  48232         1,
  48233         soc_LLS_L1_CONFIG_ECC_STATUSr_fields,
  48234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48235         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48236         -1,
  48237         -1,
  48238     },
  48239 #endif /* chips */
  48240 
  48241 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48242     { /* SOC_REG_INT_LLS_L1_CONFIG_ECC_STATUS_BCM56260_A0r */
  48243         soc_block_list[85],
  48244         soc_genreg,
  48245         1,
  48246         0,
  48247         0x200e800,
  48248         0,
  48249         0,
  48250         1,
  48251         soc_LLS_L1_CONFIG_ECC_STATUS_BCM56260_A0r_fields,
  48252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48253         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48254         -1,
  48255         -1,
  48256     },
  48257 #endif /* chips */
  48258 
  48259 #if defined(BCM_56270_A0)
  48260     { /* SOC_REG_INT_LLS_L1_CONFIG_ECC_STATUS_BCM56270_A0r */
  48261         soc_block_list[85],
  48262         soc_genreg,
  48263         1,
  48264         0,
  48265         0x200cf00,
  48266         0,
  48267         0,
  48268         1,
  48269         soc_LLS_L1_CONFIG_ECC_STATUS_BCM56270_A0r_fields,
  48270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48271         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  48272         -1,
  48273         -1,
  48274     },
  48275 #endif /* chips */
  48276 
  48277 #if defined(BCM_56440_B0)
  48278     { /* SOC_REG_INT_LLS_L1_CONFIG_ECC_STATUS_BCM56440_B0r */
  48279         soc_block_list[85],
  48280         soc_genreg,
  48281         1,
  48282         0,
  48283         0x80097,
  48284         0,
  48285         0,
  48286         1,
  48287         soc_LLS_L1_CONFIG_ECC_STATUSr_fields,
  48288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48289         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48290         -1,
  48291         -1,
  48292     },
  48293 #endif /* chips */
  48294 
  48295 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48296     defined(BCM_56450_B1)
  48297     { /* SOC_REG_INT_LLS_L1_CONFIG_ECC_STATUS_BCM56450_A0r */
  48298         soc_block_list[85],
  48299         soc_genreg,
  48300         1,
  48301         0,
  48302         0x2017100,
  48303         0,
  48304         0,
  48305         1,
  48306         soc_LLS_L1_CONFIG_ECC_STATUS_BCM56450_A0r_fields,
  48307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48308         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48309         -1,
  48310         -1,
  48311     },
  48312 #endif /* chips */
  48313 
  48314 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  48315     { /* SOC_REG_INT_LLS_L1_CONFIG_ECC_STATUS_BCM56640_A0r */
  48316         soc_block_list[4],
  48317         soc_genreg,
  48318         1,
  48319         0,
  48320         0x5a008e00,
  48321         0,
  48322         0,
  48323         1,
  48324         soc_LLS_L1_CONFIG_ECC_STATUS_BCM56640_A0r_fields,
  48325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48326         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  48327         -1,
  48328         -1,
  48329     },
  48330 #endif /* chips */
  48331 
  48332 #if defined(BCM_56440_A0)
  48333     { /* SOC_REG_INT_LLS_L1_ECC_1B_COUNTERr */
  48334         soc_block_list[85],
  48335         soc_genreg,
  48336         1,
  48337         0,
  48338         0x80067,
  48339         0,
  48340         0,
  48341         1,
  48342         soc_LLS_L1_ECC_1B_COUNTERr_fields,
  48343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48344         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48345         -1,
  48346         -1,
  48347     },
  48348 #endif /* chips */
  48349 
  48350 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48351     { /* SOC_REG_INT_LLS_L1_ECC_1B_COUNTER_BCM56260_A0r */
  48352         soc_block_list[85],
  48353         soc_genreg,
  48354         1,
  48355         0,
  48356         0x200c200,
  48357         0,
  48358         0,
  48359         1,
  48360         soc_LLS_L1_ECC_1B_COUNTER_BCM56260_A0r_fields,
  48361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48362         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48363         -1,
  48364         -1,
  48365     },
  48366 #endif /* chips */
  48367 
  48368 #if defined(BCM_56270_A0)
  48369     { /* SOC_REG_INT_LLS_L1_ECC_1B_COUNTER_BCM56270_A0r */
  48370         soc_block_list[85],
  48371         soc_genreg,
  48372         1,
  48373         0,
  48374         0x200a900,
  48375         0,
  48376         0,
  48377         1,
  48378         soc_LLS_L1_ECC_1B_COUNTER_BCM56260_A0r_fields,
  48379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48380         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48381         -1,
  48382         -1,
  48383     },
  48384 #endif /* chips */
  48385 
  48386 #if defined(BCM_56440_B0)
  48387     { /* SOC_REG_INT_LLS_L1_ECC_1B_COUNTER_BCM56440_B0r */
  48388         soc_block_list[85],
  48389         soc_genreg,
  48390         1,
  48391         0,
  48392         0x8006f,
  48393         0,
  48394         0,
  48395         1,
  48396         soc_LLS_L1_ECC_1B_COUNTERr_fields,
  48397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48398         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48399         -1,
  48400         -1,
  48401     },
  48402 #endif /* chips */
  48403 
  48404 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48405     defined(BCM_56450_B1)
  48406     { /* SOC_REG_INT_LLS_L1_ECC_1B_COUNTER_BCM56450_A0r */
  48407         soc_block_list[85],
  48408         soc_genreg,
  48409         1,
  48410         0,
  48411         0x2014400,
  48412         0,
  48413         0,
  48414         1,
  48415         soc_LLS_L1_ECC_1B_COUNTER_BCM56450_A0r_fields,
  48416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48417         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48418         -1,
  48419         -1,
  48420     },
  48421 #endif /* chips */
  48422 
  48423 #if defined(BCM_56440_A0)
  48424     { /* SOC_REG_INT_LLS_L1_ECC_2B_COUNTERr */
  48425         soc_block_list[85],
  48426         soc_genreg,
  48427         1,
  48428         0,
  48429         0x80068,
  48430         0,
  48431         0,
  48432         1,
  48433         soc_LLS_L1_ECC_2B_COUNTERr_fields,
  48434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48435         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48436         -1,
  48437         -1,
  48438     },
  48439 #endif /* chips */
  48440 
  48441 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48442     { /* SOC_REG_INT_LLS_L1_ECC_2B_COUNTER_BCM56260_A0r */
  48443         soc_block_list[85],
  48444         soc_genreg,
  48445         1,
  48446         0,
  48447         0x200c300,
  48448         0,
  48449         0,
  48450         1,
  48451         soc_LLS_L1_ECC_2B_COUNTER_BCM56260_A0r_fields,
  48452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48453         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48454         -1,
  48455         -1,
  48456     },
  48457 #endif /* chips */
  48458 
  48459 #if defined(BCM_56270_A0)
  48460     { /* SOC_REG_INT_LLS_L1_ECC_2B_COUNTER_BCM56270_A0r */
  48461         soc_block_list[85],
  48462         soc_genreg,
  48463         1,
  48464         0,
  48465         0x200aa00,
  48466         0,
  48467         0,
  48468         1,
  48469         soc_LLS_L1_ECC_2B_COUNTER_BCM56260_A0r_fields,
  48470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48471         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48472         -1,
  48473         -1,
  48474     },
  48475 #endif /* chips */
  48476 
  48477 #if defined(BCM_56440_B0)
  48478     { /* SOC_REG_INT_LLS_L1_ECC_2B_COUNTER_BCM56440_B0r */
  48479         soc_block_list[85],
  48480         soc_genreg,
  48481         1,
  48482         0,
  48483         0x80070,
  48484         0,
  48485         0,
  48486         1,
  48487         soc_LLS_L1_ECC_2B_COUNTERr_fields,
  48488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48489         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48490         -1,
  48491         -1,
  48492     },
  48493 #endif /* chips */
  48494 
  48495 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48496     defined(BCM_56450_B1)
  48497     { /* SOC_REG_INT_LLS_L1_ECC_2B_COUNTER_BCM56450_A0r */
  48498         soc_block_list[85],
  48499         soc_genreg,
  48500         1,
  48501         0,
  48502         0x2014500,
  48503         0,
  48504         0,
  48505         1,
  48506         soc_LLS_L1_ECC_2B_COUNTER_BCM56450_A0r_fields,
  48507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48508         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48509         -1,
  48510         -1,
  48511     },
  48512 #endif /* chips */
  48513 
  48514 #if defined(BCM_56440_A0)
  48515     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1r */
  48516         soc_block_list[85],
  48517         soc_genreg,
  48518         1,
  48519         0,
  48520         0x8006e,
  48521         0,
  48522         0,
  48523         28,
  48524         soc_LLS_L1_ECC_DEBUG1r_fields,
  48525         SOC_RESET_VAL_DEC(0x05555555, 0x00000000)
  48526         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48527         -1,
  48528         -1,
  48529     },
  48530 #endif /* chips */
  48531 
  48532 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  48533     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1Ar */
  48534         soc_block_list[4],
  48535         soc_genreg,
  48536         1,
  48537         0,
  48538         0x62007500,
  48539         0,
  48540         0,
  48541         16,
  48542         soc_LLS_L1_ECC_DEBUG1Ar_fields,
  48543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48544         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  48545         -1,
  48546         -1,
  48547     },
  48548 #endif /* chips */
  48549 
  48550 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48551     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1A_BCM56260_A0r */
  48552         soc_block_list[85],
  48553         soc_genreg,
  48554         1,
  48555         0,
  48556         0x200ca00,
  48557         0,
  48558         0,
  48559         20,
  48560         soc_LLS_L1_ECC_DEBUG1A_BCM56260_A0r_fields,
  48561         SOC_RESET_VAL_DEC(0x09249249, 0x00000000)
  48562         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  48563         -1,
  48564         -1,
  48565     },
  48566 #endif /* chips */
  48567 
  48568 #if defined(BCM_56270_A0)
  48569     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1A_BCM56270_A0r */
  48570         soc_block_list[85],
  48571         soc_genreg,
  48572         1,
  48573         0,
  48574         0x200b100,
  48575         0,
  48576         0,
  48577         20,
  48578         soc_LLS_L1_ECC_DEBUG1A_BCM56260_A0r_fields,
  48579         SOC_RESET_VAL_DEC(0x09249249, 0x00000000)
  48580         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  48581         -1,
  48582         -1,
  48583     },
  48584 #endif /* chips */
  48585 
  48586 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48587     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1_BCM56260_A0r */
  48588         soc_block_list[85],
  48589         soc_genreg,
  48590         1,
  48591         0,
  48592         0x200c900,
  48593         0,
  48594         0,
  48595         8,
  48596         soc_LLS_L1_ECC_DEBUG1_BCM56260_A0r_fields,
  48597         SOC_RESET_VAL_DEC(0x00000249, 0x00000000)
  48598         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48599         -1,
  48600         -1,
  48601     },
  48602 #endif /* chips */
  48603 
  48604 #if defined(BCM_56270_A0)
  48605     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1_BCM56270_A0r */
  48606         soc_block_list[85],
  48607         soc_genreg,
  48608         1,
  48609         0,
  48610         0x200b000,
  48611         0,
  48612         0,
  48613         8,
  48614         soc_LLS_L1_ECC_DEBUG1_BCM56260_A0r_fields,
  48615         SOC_RESET_VAL_DEC(0x00000249, 0x00000000)
  48616         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48617         -1,
  48618         -1,
  48619     },
  48620 #endif /* chips */
  48621 
  48622 #if defined(BCM_56440_B0)
  48623     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1_BCM56440_B0r */
  48624         soc_block_list[85],
  48625         soc_genreg,
  48626         1,
  48627         0,
  48628         0x80076,
  48629         0,
  48630         0,
  48631         28,
  48632         soc_LLS_L1_ECC_DEBUG1r_fields,
  48633         SOC_RESET_VAL_DEC(0x05555555, 0x00000000)
  48634         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48635         -1,
  48636         -1,
  48637     },
  48638 #endif /* chips */
  48639 
  48640 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48641     defined(BCM_56450_B1)
  48642     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1_BCM56450_A0r */
  48643         soc_block_list[85],
  48644         soc_genreg,
  48645         1,
  48646         0,
  48647         0x2014b00,
  48648         0,
  48649         0,
  48650         28,
  48651         soc_LLS_L1_ECC_DEBUG1_BCM56450_A0r_fields,
  48652         SOC_RESET_VAL_DEC(0x05555555, 0x00000000)
  48653         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48654         -1,
  48655         -1,
  48656     },
  48657 #endif /* chips */
  48658 
  48659 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  48660     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1_BCM56560_A0r */
  48661         soc_block_list[4],
  48662         soc_genreg,
  48663         1,
  48664         0,
  48665         0x62007400,
  48666         0,
  48667         0,
  48668         6,
  48669         soc_LLS_L1_ECC_DEBUG1_BCM56560_A0r_fields,
  48670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48671         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  48672         -1,
  48673         -1,
  48674     },
  48675 #endif /* chips */
  48676 
  48677 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  48678     { /* SOC_REG_INT_LLS_L1_ECC_DEBUG1_BCM56640_A0r */
  48679         soc_block_list[4],
  48680         soc_genreg,
  48681         1,
  48682         0,
  48683         0x5a007800,
  48684         0,
  48685         0,
  48686         12,
  48687         soc_LLS_L1_ECC_DEBUG1_BCM56640_A0r_fields,
  48688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48689         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48690         -1,
  48691         -1,
  48692     },
  48693 #endif /* chips */
  48694 
  48695 #if defined(BCM_56440_A0)
  48696     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1r */
  48697         soc_block_list[85],
  48698         soc_genreg,
  48699         1,
  48700         0,
  48701         0x80077,
  48702         0,
  48703         0,
  48704         28,
  48705         soc_LLS_L1_ECC_ERROR1r_fields,
  48706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48707         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48708         -1,
  48709         -1,
  48710     },
  48711 #endif /* chips */
  48712 
  48713 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48714     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_BCM56260_A0r */
  48715         soc_block_list[85],
  48716         soc_genreg,
  48717         1,
  48718         0,
  48719         0x200d200,
  48720         0,
  48721         0,
  48722         28,
  48723         soc_LLS_L1_ECC_ERROR1_BCM56260_A0r_fields,
  48724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48725         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48726         -1,
  48727         -1,
  48728     },
  48729 #endif /* chips */
  48730 
  48731 #if defined(BCM_56270_A0)
  48732     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_BCM56270_A0r */
  48733         soc_block_list[85],
  48734         soc_genreg,
  48735         1,
  48736         0,
  48737         0x200b900,
  48738         0,
  48739         0,
  48740         28,
  48741         soc_LLS_L1_ECC_ERROR1_BCM56260_A0r_fields,
  48742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48743         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48744         -1,
  48745         -1,
  48746     },
  48747 #endif /* chips */
  48748 
  48749 #if defined(BCM_56440_B0)
  48750     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_BCM56440_B0r */
  48751         soc_block_list[85],
  48752         soc_genreg,
  48753         1,
  48754         0,
  48755         0x8007f,
  48756         0,
  48757         0,
  48758         28,
  48759         soc_LLS_L1_ECC_ERROR1r_fields,
  48760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48761         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48762         -1,
  48763         -1,
  48764     },
  48765 #endif /* chips */
  48766 
  48767 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48768     defined(BCM_56450_B1)
  48769     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_BCM56450_A0r */
  48770         soc_block_list[85],
  48771         soc_genreg,
  48772         1,
  48773         0,
  48774         0x2015400,
  48775         0,
  48776         0,
  48777         28,
  48778         soc_LLS_L1_ECC_ERROR1_BCM56450_A0r_fields,
  48779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48780         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48781         -1,
  48782         -1,
  48783     },
  48784 #endif /* chips */
  48785 
  48786 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  48787     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_BCM56640_A0r */
  48788         soc_block_list[4],
  48789         soc_genreg,
  48790         1,
  48791         0,
  48792         0x5a007c00,
  48793         0,
  48794         0,
  48795         24,
  48796         soc_LLS_L1_ECC_ERROR1_BCM56640_A0r_fields,
  48797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48798         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  48799         -1,
  48800         -1,
  48801     },
  48802 #endif /* chips */
  48803 
  48804 #if defined(BCM_56440_A0)
  48805     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_MASKr */
  48806         soc_block_list[85],
  48807         soc_genreg,
  48808         1,
  48809         0,
  48810         0x80078,
  48811         0,
  48812         0,
  48813         28,
  48814         soc_LLS_L1_ECC_ERROR1_MASKr_fields,
  48815         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  48816         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48817         -1,
  48818         -1,
  48819     },
  48820 #endif /* chips */
  48821 
  48822 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48823     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_MASK_BCM56260_A0r */
  48824         soc_block_list[85],
  48825         soc_genreg,
  48826         1,
  48827         0,
  48828         0x200d300,
  48829         0,
  48830         0,
  48831         28,
  48832         soc_LLS_L1_ECC_ERROR1_MASK_BCM56260_A0r_fields,
  48833         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  48834         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48835         -1,
  48836         -1,
  48837     },
  48838 #endif /* chips */
  48839 
  48840 #if defined(BCM_56270_A0)
  48841     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_MASK_BCM56270_A0r */
  48842         soc_block_list[85],
  48843         soc_genreg,
  48844         1,
  48845         0,
  48846         0x200ba00,
  48847         0,
  48848         0,
  48849         28,
  48850         soc_LLS_L1_ECC_ERROR1_MASK_BCM56260_A0r_fields,
  48851         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  48852         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48853         -1,
  48854         -1,
  48855     },
  48856 #endif /* chips */
  48857 
  48858 #if defined(BCM_56440_B0)
  48859     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_MASK_BCM56440_B0r */
  48860         soc_block_list[85],
  48861         soc_genreg,
  48862         1,
  48863         0,
  48864         0x80080,
  48865         0,
  48866         0,
  48867         28,
  48868         soc_LLS_L1_ECC_ERROR1_MASKr_fields,
  48869         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  48870         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48871         -1,
  48872         -1,
  48873     },
  48874 #endif /* chips */
  48875 
  48876 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48877     defined(BCM_56450_B1)
  48878     { /* SOC_REG_INT_LLS_L1_ECC_ERROR1_MASK_BCM56450_A0r */
  48879         soc_block_list[85],
  48880         soc_genreg,
  48881         1,
  48882         0,
  48883         0x2015500,
  48884         0,
  48885         0,
  48886         28,
  48887         soc_LLS_L1_ECC_ERROR1_MASK_BCM56450_A0r_fields,
  48888         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  48889         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  48890         -1,
  48891         -1,
  48892     },
  48893 #endif /* chips */
  48894 
  48895 #if defined(BCM_56440_A0)
  48896     { /* SOC_REG_INT_LLS_L1_EF_NEXT_ECC_STATUSr */
  48897         soc_block_list[85],
  48898         soc_genreg,
  48899         1,
  48900         0,
  48901         0x80098,
  48902         0,
  48903         0,
  48904         1,
  48905         soc_LLS_L1_EF_NEXT_ECC_STATUSr_fields,
  48906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48907         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48908         -1,
  48909         -1,
  48910     },
  48911 #endif /* chips */
  48912 
  48913 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48914     { /* SOC_REG_INT_LLS_L1_EF_NEXT_ECC_STATUS_BCM56260_A0r */
  48915         soc_block_list[85],
  48916         soc_genreg,
  48917         1,
  48918         0,
  48919         0x200f200,
  48920         0,
  48921         0,
  48922         1,
  48923         soc_LLS_L1_EF_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  48924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48925         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48926         -1,
  48927         -1,
  48928     },
  48929 #endif /* chips */
  48930 
  48931 #if defined(BCM_56270_A0)
  48932     { /* SOC_REG_INT_LLS_L1_EF_NEXT_ECC_STATUS_BCM56270_A0r */
  48933         soc_block_list[85],
  48934         soc_genreg,
  48935         1,
  48936         0,
  48937         0x200d900,
  48938         0,
  48939         0,
  48940         1,
  48941         soc_LLS_L1_EF_NEXT_ECC_STATUS_BCM56270_A0r_fields,
  48942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48943         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  48944         -1,
  48945         -1,
  48946     },
  48947 #endif /* chips */
  48948 
  48949 #if defined(BCM_56440_B0)
  48950     { /* SOC_REG_INT_LLS_L1_EF_NEXT_ECC_STATUS_BCM56440_B0r */
  48951         soc_block_list[85],
  48952         soc_genreg,
  48953         1,
  48954         0,
  48955         0x800a0,
  48956         0,
  48957         0,
  48958         1,
  48959         soc_LLS_L1_EF_NEXT_ECC_STATUSr_fields,
  48960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48961         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48962         -1,
  48963         -1,
  48964     },
  48965 #endif /* chips */
  48966 
  48967 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48968     defined(BCM_56450_B1)
  48969     { /* SOC_REG_INT_LLS_L1_EF_NEXT_ECC_STATUS_BCM56450_A0r */
  48970         soc_block_list[85],
  48971         soc_genreg,
  48972         1,
  48973         0,
  48974         0x2017a00,
  48975         0,
  48976         0,
  48977         1,
  48978         soc_LLS_L1_EF_NEXT_ECC_STATUS_BCM56450_A0r_fields,
  48979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48980         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  48981         -1,
  48982         -1,
  48983     },
  48984 #endif /* chips */
  48985 
  48986 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  48987     { /* SOC_REG_INT_LLS_L1_EF_NEXT_ECC_STATUS_BCM56640_A0r */
  48988         soc_block_list[4],
  48989         soc_genreg,
  48990         1,
  48991         0,
  48992         0x5a009600,
  48993         0,
  48994         0,
  48995         1,
  48996         soc_LLS_L1_EF_NEXT_ECC_STATUS_BCM56640_A0r_fields,
  48997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48998         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  48999         -1,
  49000         -1,
  49001     },
  49002 #endif /* chips */
  49003 
  49004 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49005     defined(BCM_56450_B1)
  49006     { /* SOC_REG_INT_LLS_L1_EMPTY_SEEN_STATUSr */
  49007         soc_block_list[85],
  49008         soc_genreg,
  49009         1,
  49010         0,
  49011         0x2011000,
  49012         0,
  49013         0,
  49014         1,
  49015         soc_LLS_L1_EMPTY_SEEN_STATUSr_fields,
  49016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49017         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49018         -1,
  49019         -1,
  49020     },
  49021 #endif /* chips */
  49022 
  49023 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49024     { /* SOC_REG_INT_LLS_L1_EMPTY_SEEN_STATUS_BCM56260_A0r */
  49025         soc_block_list[85],
  49026         soc_genreg,
  49027         1,
  49028         0,
  49029         0x2009100,
  49030         0,
  49031         0,
  49032         1,
  49033         soc_LLS_L1_EMPTY_SEEN_STATUS_BCM56260_A0r_fields,
  49034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49035         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49036         -1,
  49037         -1,
  49038     },
  49039 #endif /* chips */
  49040 
  49041 #if defined(BCM_56270_A0)
  49042     { /* SOC_REG_INT_LLS_L1_EMPTY_SEEN_STATUS_BCM56270_A0r */
  49043         soc_block_list[85],
  49044         soc_genreg,
  49045         1,
  49046         0,
  49047         0x2007800,
  49048         0,
  49049         0,
  49050         1,
  49051         soc_LLS_L1_EMPTY_SEEN_STATUS_BCM56270_A0r_fields,
  49052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49053         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  49054         -1,
  49055         -1,
  49056     },
  49057 #endif /* chips */
  49058 
  49059 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  49060     { /* SOC_REG_INT_LLS_L1_EMPTY_SEEN_STATUS_BCM56560_A0r */
  49061         soc_block_list[4],
  49062         soc_genreg,
  49063         1,
  49064         0,
  49065         0x62004000,
  49066         0,
  49067         0,
  49068         1,
  49069         soc_LLS_L1_EMPTY_SEEN_STATUS_BCM56560_A0r_fields,
  49070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49071         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  49072         -1,
  49073         -1,
  49074     },
  49075 #endif /* chips */
  49076 
  49077 #if defined(BCM_56440_A0)
  49078     { /* SOC_REG_INT_LLS_L1_ERROR_ECC_STATUSr */
  49079         soc_block_list[85],
  49080         soc_genreg,
  49081         1,
  49082         0,
  49083         0x800a9,
  49084         0,
  49085         0,
  49086         1,
  49087         soc_LLS_L1_ERROR_ECC_STATUSr_fields,
  49088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49089         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49090         -1,
  49091         -1,
  49092     },
  49093 #endif /* chips */
  49094 
  49095 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49096     { /* SOC_REG_INT_LLS_L1_ERROR_ECC_STATUS_BCM56260_A0r */
  49097         soc_block_list[85],
  49098         soc_genreg,
  49099         1,
  49100         0,
  49101         0x200fe00,
  49102         0,
  49103         0,
  49104         1,
  49105         soc_LLS_L1_ERROR_ECC_STATUS_BCM56260_A0r_fields,
  49106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49107         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49108         -1,
  49109         -1,
  49110     },
  49111 #endif /* chips */
  49112 
  49113 #if defined(BCM_56270_A0)
  49114     { /* SOC_REG_INT_LLS_L1_ERROR_ECC_STATUS_BCM56270_A0r */
  49115         soc_block_list[85],
  49116         soc_genreg,
  49117         1,
  49118         0,
  49119         0x200e500,
  49120         0,
  49121         0,
  49122         1,
  49123         soc_LLS_L1_ERROR_ECC_STATUS_BCM56270_A0r_fields,
  49124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49125         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49126         -1,
  49127         -1,
  49128     },
  49129 #endif /* chips */
  49130 
  49131 #if defined(BCM_56440_B0)
  49132     { /* SOC_REG_INT_LLS_L1_ERROR_ECC_STATUS_BCM56440_B0r */
  49133         soc_block_list[85],
  49134         soc_genreg,
  49135         1,
  49136         0,
  49137         0x800b1,
  49138         0,
  49139         0,
  49140         1,
  49141         soc_LLS_L1_ERROR_ECC_STATUSr_fields,
  49142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49143         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49144         -1,
  49145         -1,
  49146     },
  49147 #endif /* chips */
  49148 
  49149 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49150     defined(BCM_56450_B1)
  49151     { /* SOC_REG_INT_LLS_L1_ERROR_ECC_STATUS_BCM56450_A0r */
  49152         soc_block_list[85],
  49153         soc_genreg,
  49154         1,
  49155         0,
  49156         0x2018d00,
  49157         0,
  49158         0,
  49159         1,
  49160         soc_LLS_L1_ERROR_ECC_STATUS_BCM56450_A0r_fields,
  49161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49162         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49163         -1,
  49164         -1,
  49165     },
  49166 #endif /* chips */
  49167 
  49168 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  49169     { /* SOC_REG_INT_LLS_L1_ERROR_ECC_STATUS_BCM56640_A0r */
  49170         soc_block_list[4],
  49171         soc_genreg,
  49172         1,
  49173         0,
  49174         0x5a009700,
  49175         0,
  49176         0,
  49177         1,
  49178         soc_LLS_L1_ERROR_ECC_STATUS_BCM56640_A0r_fields,
  49179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49180         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49181         -1,
  49182         -1,
  49183     },
  49184 #endif /* chips */
  49185 
  49186 #if defined(BCM_56440_B0)
  49187     { /* SOC_REG_INT_LLS_L1_ERROR_MIN_ECC_STATUSr */
  49188         soc_block_list[85],
  49189         soc_genreg,
  49190         1,
  49191         0,
  49192         0x800b4,
  49193         0,
  49194         0,
  49195         1,
  49196         soc_LLS_L1_ERROR_MIN_ECC_STATUSr_fields,
  49197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49198         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49199         -1,
  49200         -1,
  49201     },
  49202 #endif /* chips */
  49203 
  49204 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49205     defined(BCM_56450_B1)
  49206     { /* SOC_REG_INT_LLS_L1_ERROR_MIN_ECC_STATUS_BCM56450_A0r */
  49207         soc_block_list[85],
  49208         soc_genreg,
  49209         1,
  49210         0,
  49211         0x2019000,
  49212         0,
  49213         0,
  49214         1,
  49215         soc_LLS_L1_ERROR_MIN_ECC_STATUS_BCM56450_A0r_fields,
  49216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49217         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49218         -1,
  49219         -1,
  49220     },
  49221 #endif /* chips */
  49222 
  49223 #if defined(BCM_56440_A0)
  49224     { /* SOC_REG_INT_LLS_L1_HEADS_TAILS_ECC_STATUSr */
  49225         soc_block_list[85],
  49226         soc_genreg,
  49227         1,
  49228         0,
  49229         0x8008e,
  49230         0,
  49231         0,
  49232         1,
  49233         soc_LLS_L1_HEADS_TAILS_ECC_STATUSr_fields,
  49234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49235         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49236         -1,
  49237         -1,
  49238     },
  49239 #endif /* chips */
  49240 
  49241 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49242     { /* SOC_REG_INT_LLS_L1_HEADS_TAILS_ECC_STATUS_BCM56260_A0r */
  49243         soc_block_list[85],
  49244         soc_genreg,
  49245         1,
  49246         0,
  49247         0x200e700,
  49248         0,
  49249         0,
  49250         1,
  49251         soc_LLS_L1_HEADS_TAILS_ECC_STATUS_BCM56260_A0r_fields,
  49252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49253         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49254         -1,
  49255         -1,
  49256     },
  49257 #endif /* chips */
  49258 
  49259 #if defined(BCM_56270_A0)
  49260     { /* SOC_REG_INT_LLS_L1_HEADS_TAILS_ECC_STATUS_BCM56270_A0r */
  49261         soc_block_list[85],
  49262         soc_genreg,
  49263         1,
  49264         0,
  49265         0x200ce00,
  49266         0,
  49267         0,
  49268         1,
  49269         soc_LLS_L1_HEADS_TAILS_ECC_STATUS_BCM56270_A0r_fields,
  49270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49271         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  49272         -1,
  49273         -1,
  49274     },
  49275 #endif /* chips */
  49276 
  49277 #if defined(BCM_56440_B0)
  49278     { /* SOC_REG_INT_LLS_L1_HEADS_TAILS_ECC_STATUS_BCM56440_B0r */
  49279         soc_block_list[85],
  49280         soc_genreg,
  49281         1,
  49282         0,
  49283         0x80096,
  49284         0,
  49285         0,
  49286         1,
  49287         soc_LLS_L1_HEADS_TAILS_ECC_STATUSr_fields,
  49288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49289         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49290         -1,
  49291         -1,
  49292     },
  49293 #endif /* chips */
  49294 
  49295 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49296     defined(BCM_56450_B1)
  49297     { /* SOC_REG_INT_LLS_L1_HEADS_TAILS_ECC_STATUS_BCM56450_A0r */
  49298         soc_block_list[85],
  49299         soc_genreg,
  49300         1,
  49301         0,
  49302         0x2017000,
  49303         0,
  49304         0,
  49305         1,
  49306         soc_LLS_L1_HEADS_TAILS_ECC_STATUS_BCM56450_A0r_fields,
  49307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49308         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49309         -1,
  49310         -1,
  49311     },
  49312 #endif /* chips */
  49313 
  49314 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  49315     { /* SOC_REG_INT_LLS_L1_HEADS_TAILS_ECC_STATUS_BCM56640_A0r */
  49316         soc_block_list[4],
  49317         soc_genreg,
  49318         1,
  49319         0,
  49320         0x5a008d00,
  49321         0,
  49322         0,
  49323         1,
  49324         soc_LLS_L1_HEADS_TAILS_ECC_STATUS_BCM56640_A0r_fields,
  49325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49326         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49327         -1,
  49328         -1,
  49329     },
  49330 #endif /* chips */
  49331 
  49332 #if defined(BCM_56440_A0)
  49333     { /* SOC_REG_INT_LLS_L1_MIN_BUCKET_C_ECC_STATUSr */
  49334         soc_block_list[85],
  49335         soc_genreg,
  49336         1,
  49337         0,
  49338         0x80092,
  49339         0,
  49340         0,
  49341         1,
  49342         soc_LLS_L1_MIN_BUCKET_C_ECC_STATUSr_fields,
  49343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49344         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49345         -1,
  49346         -1,
  49347     },
  49348 #endif /* chips */
  49349 
  49350 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49351     { /* SOC_REG_INT_LLS_L1_MIN_BUCKET_C_ECC_STATUS_BCM56260_A0r */
  49352         soc_block_list[85],
  49353         soc_genreg,
  49354         1,
  49355         0,
  49356         0x200ec00,
  49357         0,
  49358         0,
  49359         1,
  49360         soc_LLS_L1_MIN_BUCKET_C_ECC_STATUS_BCM56260_A0r_fields,
  49361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49362         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49363         -1,
  49364         -1,
  49365     },
  49366 #endif /* chips */
  49367 
  49368 #if defined(BCM_56270_A0)
  49369     { /* SOC_REG_INT_LLS_L1_MIN_BUCKET_C_ECC_STATUS_BCM56270_A0r */
  49370         soc_block_list[85],
  49371         soc_genreg,
  49372         1,
  49373         0,
  49374         0x200d300,
  49375         0,
  49376         0,
  49377         1,
  49378         soc_LLS_L1_MIN_BUCKET_C_ECC_STATUS_BCM56270_A0r_fields,
  49379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49380         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  49381         -1,
  49382         -1,
  49383     },
  49384 #endif /* chips */
  49385 
  49386 #if defined(BCM_56440_B0)
  49387     { /* SOC_REG_INT_LLS_L1_MIN_BUCKET_C_ECC_STATUS_BCM56440_B0r */
  49388         soc_block_list[85],
  49389         soc_genreg,
  49390         1,
  49391         0,
  49392         0x8009a,
  49393         0,
  49394         0,
  49395         1,
  49396         soc_LLS_L1_MIN_BUCKET_C_ECC_STATUSr_fields,
  49397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49398         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49399         -1,
  49400         -1,
  49401     },
  49402 #endif /* chips */
  49403 
  49404 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49405     defined(BCM_56450_B1)
  49406     { /* SOC_REG_INT_LLS_L1_MIN_BUCKET_C_ECC_STATUS_BCM56450_A0r */
  49407         soc_block_list[85],
  49408         soc_genreg,
  49409         1,
  49410         0,
  49411         0x2017400,
  49412         0,
  49413         0,
  49414         1,
  49415         soc_LLS_L1_MIN_BUCKET_C_ECC_STATUS_BCM56450_A0r_fields,
  49416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49417         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49418         -1,
  49419         -1,
  49420     },
  49421 #endif /* chips */
  49422 
  49423 #if defined(BCM_56440_A0)
  49424     { /* SOC_REG_INT_LLS_L1_MIN_CONFIG_C_ECC_STATUSr */
  49425         soc_block_list[85],
  49426         soc_genreg,
  49427         1,
  49428         0,
  49429         0x80090,
  49430         0,
  49431         0,
  49432         1,
  49433         soc_LLS_L1_MIN_CONFIG_C_ECC_STATUSr_fields,
  49434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49435         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49436         -1,
  49437         -1,
  49438     },
  49439 #endif /* chips */
  49440 
  49441 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49442     { /* SOC_REG_INT_LLS_L1_MIN_CONFIG_C_ECC_STATUS_BCM56260_A0r */
  49443         soc_block_list[85],
  49444         soc_genreg,
  49445         1,
  49446         0,
  49447         0x200ea00,
  49448         0,
  49449         0,
  49450         1,
  49451         soc_LLS_L1_MIN_CONFIG_C_ECC_STATUS_BCM56260_A0r_fields,
  49452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49453         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49454         -1,
  49455         -1,
  49456     },
  49457 #endif /* chips */
  49458 
  49459 #if defined(BCM_56270_A0)
  49460     { /* SOC_REG_INT_LLS_L1_MIN_CONFIG_C_ECC_STATUS_BCM56270_A0r */
  49461         soc_block_list[85],
  49462         soc_genreg,
  49463         1,
  49464         0,
  49465         0x200d100,
  49466         0,
  49467         0,
  49468         1,
  49469         soc_LLS_L1_MIN_CONFIG_C_ECC_STATUS_BCM56270_A0r_fields,
  49470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49471         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  49472         -1,
  49473         -1,
  49474     },
  49475 #endif /* chips */
  49476 
  49477 #if defined(BCM_56440_B0)
  49478     { /* SOC_REG_INT_LLS_L1_MIN_CONFIG_C_ECC_STATUS_BCM56440_B0r */
  49479         soc_block_list[85],
  49480         soc_genreg,
  49481         1,
  49482         0,
  49483         0x80098,
  49484         0,
  49485         0,
  49486         1,
  49487         soc_LLS_L1_MIN_CONFIG_C_ECC_STATUSr_fields,
  49488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49489         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49490         -1,
  49491         -1,
  49492     },
  49493 #endif /* chips */
  49494 
  49495 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49496     defined(BCM_56450_B1)
  49497     { /* SOC_REG_INT_LLS_L1_MIN_CONFIG_C_ECC_STATUS_BCM56450_A0r */
  49498         soc_block_list[85],
  49499         soc_genreg,
  49500         1,
  49501         0,
  49502         0x2017200,
  49503         0,
  49504         0,
  49505         1,
  49506         soc_LLS_L1_MIN_CONFIG_C_ECC_STATUS_BCM56450_A0r_fields,
  49507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49508         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49509         -1,
  49510         -1,
  49511     },
  49512 #endif /* chips */
  49513 
  49514 #if defined(BCM_56440_A0)
  49515     { /* SOC_REG_INT_LLS_L1_MIN_NEXT_ECC_STATUSr */
  49516         soc_block_list[85],
  49517         soc_genreg,
  49518         1,
  49519         0,
  49520         0x80097,
  49521         0,
  49522         0,
  49523         1,
  49524         soc_LLS_L1_MIN_NEXT_ECC_STATUSr_fields,
  49525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49526         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49527         -1,
  49528         -1,
  49529     },
  49530 #endif /* chips */
  49531 
  49532 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49533     { /* SOC_REG_INT_LLS_L1_MIN_NEXT_ECC_STATUS_BCM56260_A0r */
  49534         soc_block_list[85],
  49535         soc_genreg,
  49536         1,
  49537         0,
  49538         0x200f100,
  49539         0,
  49540         0,
  49541         1,
  49542         soc_LLS_L1_MIN_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  49543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49544         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49545         -1,
  49546         -1,
  49547     },
  49548 #endif /* chips */
  49549 
  49550 #if defined(BCM_56270_A0)
  49551     { /* SOC_REG_INT_LLS_L1_MIN_NEXT_ECC_STATUS_BCM56270_A0r */
  49552         soc_block_list[85],
  49553         soc_genreg,
  49554         1,
  49555         0,
  49556         0x200d800,
  49557         0,
  49558         0,
  49559         1,
  49560         soc_LLS_L1_MIN_NEXT_ECC_STATUS_BCM56270_A0r_fields,
  49561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49562         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  49563         -1,
  49564         -1,
  49565     },
  49566 #endif /* chips */
  49567 
  49568 #if defined(BCM_56440_B0)
  49569     { /* SOC_REG_INT_LLS_L1_MIN_NEXT_ECC_STATUS_BCM56440_B0r */
  49570         soc_block_list[85],
  49571         soc_genreg,
  49572         1,
  49573         0,
  49574         0x8009f,
  49575         0,
  49576         0,
  49577         1,
  49578         soc_LLS_L1_MIN_NEXT_ECC_STATUSr_fields,
  49579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49580         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49581         -1,
  49582         -1,
  49583     },
  49584 #endif /* chips */
  49585 
  49586 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49587     defined(BCM_56450_B1)
  49588     { /* SOC_REG_INT_LLS_L1_MIN_NEXT_ECC_STATUS_BCM56450_A0r */
  49589         soc_block_list[85],
  49590         soc_genreg,
  49591         1,
  49592         0,
  49593         0x2017900,
  49594         0,
  49595         0,
  49596         1,
  49597         soc_LLS_L1_MIN_NEXT_ECC_STATUS_BCM56450_A0r_fields,
  49598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49599         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49600         -1,
  49601         -1,
  49602     },
  49603 #endif /* chips */
  49604 
  49605 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  49606     { /* SOC_REG_INT_LLS_L1_MIN_NEXT_ECC_STATUS_BCM56640_A0r */
  49607         soc_block_list[4],
  49608         soc_genreg,
  49609         1,
  49610         0,
  49611         0x5a009500,
  49612         0,
  49613         0,
  49614         1,
  49615         soc_LLS_L1_MIN_NEXT_ECC_STATUS_BCM56640_A0r_fields,
  49616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49617         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49618         -1,
  49619         -1,
  49620     },
  49621 #endif /* chips */
  49622 
  49623 #if defined(BCM_56440_A0)
  49624     { /* SOC_REG_INT_LLS_L1_PARENT_ECC_STATUSr */
  49625         soc_block_list[85],
  49626         soc_genreg,
  49627         1,
  49628         0,
  49629         0x8008d,
  49630         0,
  49631         0,
  49632         1,
  49633         soc_LLS_L1_PARENT_ECC_STATUSr_fields,
  49634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49635         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49636         -1,
  49637         -1,
  49638     },
  49639 #endif /* chips */
  49640 
  49641 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49642     { /* SOC_REG_INT_LLS_L1_PARENT_ECC_STATUS_BCM56260_A0r */
  49643         soc_block_list[85],
  49644         soc_genreg,
  49645         1,
  49646         0,
  49647         0x200e600,
  49648         0,
  49649         0,
  49650         1,
  49651         soc_LLS_L1_PARENT_ECC_STATUS_BCM56260_A0r_fields,
  49652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49653         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49654         -1,
  49655         -1,
  49656     },
  49657 #endif /* chips */
  49658 
  49659 #if defined(BCM_56270_A0)
  49660     { /* SOC_REG_INT_LLS_L1_PARENT_ECC_STATUS_BCM56270_A0r */
  49661         soc_block_list[85],
  49662         soc_genreg,
  49663         1,
  49664         0,
  49665         0x200cd00,
  49666         0,
  49667         0,
  49668         1,
  49669         soc_LLS_L1_PARENT_ECC_STATUS_BCM56270_A0r_fields,
  49670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49671         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  49672         -1,
  49673         -1,
  49674     },
  49675 #endif /* chips */
  49676 
  49677 #if defined(BCM_56440_B0)
  49678     { /* SOC_REG_INT_LLS_L1_PARENT_ECC_STATUS_BCM56440_B0r */
  49679         soc_block_list[85],
  49680         soc_genreg,
  49681         1,
  49682         0,
  49683         0x80095,
  49684         0,
  49685         0,
  49686         1,
  49687         soc_LLS_L1_PARENT_ECC_STATUSr_fields,
  49688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49689         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49690         -1,
  49691         -1,
  49692     },
  49693 #endif /* chips */
  49694 
  49695 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49696     defined(BCM_56450_B1)
  49697     { /* SOC_REG_INT_LLS_L1_PARENT_ECC_STATUS_BCM56450_A0r */
  49698         soc_block_list[85],
  49699         soc_genreg,
  49700         1,
  49701         0,
  49702         0x2016f00,
  49703         0,
  49704         0,
  49705         1,
  49706         soc_LLS_L1_PARENT_ECC_STATUS_BCM56450_A0r_fields,
  49707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49708         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49709         -1,
  49710         -1,
  49711     },
  49712 #endif /* chips */
  49713 
  49714 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  49715     { /* SOC_REG_INT_LLS_L1_PARENT_ECC_STATUS_BCM56640_A0r */
  49716         soc_block_list[4],
  49717         soc_genreg,
  49718         1,
  49719         0,
  49720         0x5a008c00,
  49721         0,
  49722         0,
  49723         1,
  49724         soc_LLS_L1_PARENT_ECC_STATUS_BCM56640_A0r_fields,
  49725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49726         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49727         -1,
  49728         -1,
  49729     },
  49730 #endif /* chips */
  49731 
  49732 #if defined(BCM_56440_A0)
  49733     { /* SOC_REG_INT_LLS_L1_PARENT_STATE_ECC_STATUSr */
  49734         soc_block_list[85],
  49735         soc_genreg,
  49736         1,
  49737         0,
  49738         0x80093,
  49739         0,
  49740         0,
  49741         1,
  49742         soc_LLS_L1_PARENT_STATE_ECC_STATUSr_fields,
  49743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49744         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49745         -1,
  49746         -1,
  49747     },
  49748 #endif /* chips */
  49749 
  49750 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49751     { /* SOC_REG_INT_LLS_L1_PARENT_STATE_ECC_STATUS_BCM56260_A0r */
  49752         soc_block_list[85],
  49753         soc_genreg,
  49754         1,
  49755         0,
  49756         0x200ed00,
  49757         0,
  49758         0,
  49759         1,
  49760         soc_LLS_L1_PARENT_STATE_ECC_STATUS_BCM56260_A0r_fields,
  49761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49762         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49763         -1,
  49764         -1,
  49765     },
  49766 #endif /* chips */
  49767 
  49768 #if defined(BCM_56270_A0)
  49769     { /* SOC_REG_INT_LLS_L1_PARENT_STATE_ECC_STATUS_BCM56270_A0r */
  49770         soc_block_list[85],
  49771         soc_genreg,
  49772         1,
  49773         0,
  49774         0x200d400,
  49775         0,
  49776         0,
  49777         1,
  49778         soc_LLS_L1_PARENT_STATE_ECC_STATUS_BCM56270_A0r_fields,
  49779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49780         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  49781         -1,
  49782         -1,
  49783     },
  49784 #endif /* chips */
  49785 
  49786 #if defined(BCM_56440_B0)
  49787     { /* SOC_REG_INT_LLS_L1_PARENT_STATE_ECC_STATUS_BCM56440_B0r */
  49788         soc_block_list[85],
  49789         soc_genreg,
  49790         1,
  49791         0,
  49792         0x8009b,
  49793         0,
  49794         0,
  49795         1,
  49796         soc_LLS_L1_PARENT_STATE_ECC_STATUSr_fields,
  49797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49798         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49799         -1,
  49800         -1,
  49801     },
  49802 #endif /* chips */
  49803 
  49804 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49805     defined(BCM_56450_B1)
  49806     { /* SOC_REG_INT_LLS_L1_PARENT_STATE_ECC_STATUS_BCM56450_A0r */
  49807         soc_block_list[85],
  49808         soc_genreg,
  49809         1,
  49810         0,
  49811         0x2017500,
  49812         0,
  49813         0,
  49814         1,
  49815         soc_LLS_L1_PARENT_STATE_ECC_STATUS_BCM56450_A0r_fields,
  49816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49817         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49818         -1,
  49819         -1,
  49820     },
  49821 #endif /* chips */
  49822 
  49823 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  49824     { /* SOC_REG_INT_LLS_L1_PARENT_STATE_ECC_STATUS_BCM56640_A0r */
  49825         soc_block_list[4],
  49826         soc_genreg,
  49827         1,
  49828         0,
  49829         0x5a009000,
  49830         0,
  49831         0,
  49832         1,
  49833         soc_LLS_L1_PARENT_STATE_ECC_STATUS_BCM56640_A0r_fields,
  49834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49835         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49836         -1,
  49837         -1,
  49838     },
  49839 #endif /* chips */
  49840 
  49841 #if defined(BCM_56440_A0)
  49842     { /* SOC_REG_INT_LLS_L1_SHAPER_BUCKET_C_ECC_STATUSr */
  49843         soc_block_list[85],
  49844         soc_genreg,
  49845         1,
  49846         0,
  49847         0x8009a,
  49848         0,
  49849         0,
  49850         1,
  49851         soc_LLS_L1_SHAPER_BUCKET_C_ECC_STATUSr_fields,
  49852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49853         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49854         -1,
  49855         -1,
  49856     },
  49857 #endif /* chips */
  49858 
  49859 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49860     { /* SOC_REG_INT_LLS_L1_SHAPER_BUCKET_C_ECC_STATUS_BCM56260_A0r */
  49861         soc_block_list[85],
  49862         soc_genreg,
  49863         1,
  49864         0,
  49865         0x200f300,
  49866         0,
  49867         0,
  49868         1,
  49869         soc_LLS_L1_SHAPER_BUCKET_C_ECC_STATUS_BCM56260_A0r_fields,
  49870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49871         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49872         -1,
  49873         -1,
  49874     },
  49875 #endif /* chips */
  49876 
  49877 #if defined(BCM_56270_A0)
  49878     { /* SOC_REG_INT_LLS_L1_SHAPER_BUCKET_C_ECC_STATUS_BCM56270_A0r */
  49879         soc_block_list[85],
  49880         soc_genreg,
  49881         1,
  49882         0,
  49883         0x200da00,
  49884         0,
  49885         0,
  49886         1,
  49887         soc_LLS_L1_SHAPER_BUCKET_C_ECC_STATUS_BCM56270_A0r_fields,
  49888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49889         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  49890         -1,
  49891         -1,
  49892     },
  49893 #endif /* chips */
  49894 
  49895 #if defined(BCM_56440_B0)
  49896     { /* SOC_REG_INT_LLS_L1_SHAPER_BUCKET_C_ECC_STATUS_BCM56440_B0r */
  49897         soc_block_list[85],
  49898         soc_genreg,
  49899         1,
  49900         0,
  49901         0x800a2,
  49902         0,
  49903         0,
  49904         1,
  49905         soc_LLS_L1_SHAPER_BUCKET_C_ECC_STATUSr_fields,
  49906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49907         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49908         -1,
  49909         -1,
  49910     },
  49911 #endif /* chips */
  49912 
  49913 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  49914     defined(BCM_56450_B1)
  49915     { /* SOC_REG_INT_LLS_L1_SHAPER_BUCKET_C_ECC_STATUS_BCM56450_A0r */
  49916         soc_block_list[85],
  49917         soc_genreg,
  49918         1,
  49919         0,
  49920         0x2017c00,
  49921         0,
  49922         0,
  49923         1,
  49924         soc_LLS_L1_SHAPER_BUCKET_C_ECC_STATUS_BCM56450_A0r_fields,
  49925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49926         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49927         -1,
  49928         -1,
  49929     },
  49930 #endif /* chips */
  49931 
  49932 #if defined(BCM_56440_A0)
  49933     { /* SOC_REG_INT_LLS_L1_SHAPER_CONFIG_C_ECC_STATUSr */
  49934         soc_block_list[85],
  49935         soc_genreg,
  49936         1,
  49937         0,
  49938         0x80099,
  49939         0,
  49940         0,
  49941         1,
  49942         soc_LLS_L1_SHAPER_CONFIG_C_ECC_STATUSr_fields,
  49943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49944         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49945         -1,
  49946         -1,
  49947     },
  49948 #endif /* chips */
  49949 
  49950 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49951     { /* SOC_REG_INT_LLS_L1_SHAPER_CONFIG_C_ECC_STATUS_BCM56260_A0r */
  49952         soc_block_list[85],
  49953         soc_genreg,
  49954         1,
  49955         0,
  49956         0x200e900,
  49957         0,
  49958         0,
  49959         1,
  49960         soc_LLS_L1_SHAPER_CONFIG_C_ECC_STATUS_BCM56260_A0r_fields,
  49961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49962         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49963         -1,
  49964         -1,
  49965     },
  49966 #endif /* chips */
  49967 
  49968 #if defined(BCM_56270_A0)
  49969     { /* SOC_REG_INT_LLS_L1_SHAPER_CONFIG_C_ECC_STATUS_BCM56270_A0r */
  49970         soc_block_list[85],
  49971         soc_genreg,
  49972         1,
  49973         0,
  49974         0x200d000,
  49975         0,
  49976         0,
  49977         1,
  49978         soc_LLS_L1_SHAPER_CONFIG_C_ECC_STATUS_BCM56270_A0r_fields,
  49979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49980         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  49981         -1,
  49982         -1,
  49983     },
  49984 #endif /* chips */
  49985 
  49986 #if defined(BCM_56440_B0)
  49987     { /* SOC_REG_INT_LLS_L1_SHAPER_CONFIG_C_ECC_STATUS_BCM56440_B0r */
  49988         soc_block_list[85],
  49989         soc_genreg,
  49990         1,
  49991         0,
  49992         0x800a1,
  49993         0,
  49994         0,
  49995         1,
  49996         soc_LLS_L1_SHAPER_CONFIG_C_ECC_STATUSr_fields,
  49997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49998         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49999         -1,
  50000         -1,
  50001     },
  50002 #endif /* chips */
  50003 
  50004 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50005     defined(BCM_56450_B1)
  50006     { /* SOC_REG_INT_LLS_L1_SHAPER_CONFIG_C_ECC_STATUS_BCM56450_A0r */
  50007         soc_block_list[85],
  50008         soc_genreg,
  50009         1,
  50010         0,
  50011         0x2017b00,
  50012         0,
  50013         0,
  50014         1,
  50015         soc_LLS_L1_SHAPER_CONFIG_C_ECC_STATUS_BCM56450_A0r_fields,
  50016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50017         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50018         -1,
  50019         -1,
  50020     },
  50021 #endif /* chips */
  50022 
  50023 #if defined(BCM_56440_A0)
  50024     { /* SOC_REG_INT_LLS_L1_WERR_MAX_SC_ECC_STATUSr */
  50025         soc_block_list[85],
  50026         soc_genreg,
  50027         1,
  50028         0,
  50029         0x80091,
  50030         0,
  50031         0,
  50032         1,
  50033         soc_LLS_L1_WERR_MAX_SC_ECC_STATUSr_fields,
  50034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50035         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50036         -1,
  50037         -1,
  50038     },
  50039 #endif /* chips */
  50040 
  50041 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50042     { /* SOC_REG_INT_LLS_L1_WERR_MAX_SC_ECC_STATUS_BCM56260_A0r */
  50043         soc_block_list[85],
  50044         soc_genreg,
  50045         1,
  50046         0,
  50047         0x200eb00,
  50048         0,
  50049         0,
  50050         1,
  50051         soc_LLS_L1_WERR_MAX_SC_ECC_STATUS_BCM56260_A0r_fields,
  50052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50053         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50054         -1,
  50055         -1,
  50056     },
  50057 #endif /* chips */
  50058 
  50059 #if defined(BCM_56270_A0)
  50060     { /* SOC_REG_INT_LLS_L1_WERR_MAX_SC_ECC_STATUS_BCM56270_A0r */
  50061         soc_block_list[85],
  50062         soc_genreg,
  50063         1,
  50064         0,
  50065         0x200d200,
  50066         0,
  50067         0,
  50068         1,
  50069         soc_LLS_L1_WERR_MAX_SC_ECC_STATUS_BCM56270_A0r_fields,
  50070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50071         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50072         -1,
  50073         -1,
  50074     },
  50075 #endif /* chips */
  50076 
  50077 #if defined(BCM_56440_B0)
  50078     { /* SOC_REG_INT_LLS_L1_WERR_MAX_SC_ECC_STATUS_BCM56440_B0r */
  50079         soc_block_list[85],
  50080         soc_genreg,
  50081         1,
  50082         0,
  50083         0x80099,
  50084         0,
  50085         0,
  50086         1,
  50087         soc_LLS_L1_WERR_MAX_SC_ECC_STATUSr_fields,
  50088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50089         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50090         -1,
  50091         -1,
  50092     },
  50093 #endif /* chips */
  50094 
  50095 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50096     defined(BCM_56450_B1)
  50097     { /* SOC_REG_INT_LLS_L1_WERR_MAX_SC_ECC_STATUS_BCM56450_A0r */
  50098         soc_block_list[85],
  50099         soc_genreg,
  50100         1,
  50101         0,
  50102         0x2017300,
  50103         0,
  50104         0,
  50105         1,
  50106         soc_LLS_L1_WERR_MAX_SC_ECC_STATUS_BCM56450_A0r_fields,
  50107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50108         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50109         -1,
  50110         -1,
  50111     },
  50112 #endif /* chips */
  50113 
  50114 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  50115     { /* SOC_REG_INT_LLS_L1_WERR_MAX_SC_ECC_STATUS_BCM56640_A0r */
  50116         soc_block_list[4],
  50117         soc_genreg,
  50118         1,
  50119         0,
  50120         0x5a008f00,
  50121         0,
  50122         0,
  50123         1,
  50124         soc_LLS_L1_WERR_MAX_SC_ECC_STATUS_BCM56640_A0r_fields,
  50125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50126         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  50127         -1,
  50128         -1,
  50129     },
  50130 #endif /* chips */
  50131 
  50132 #if defined(BCM_56440_A0)
  50133     { /* SOC_REG_INT_LLS_L1_WERR_NEXT_ECC_STATUSr */
  50134         soc_block_list[85],
  50135         soc_genreg,
  50136         1,
  50137         0,
  50138         0x80096,
  50139         0,
  50140         0,
  50141         1,
  50142         soc_LLS_L1_WERR_NEXT_ECC_STATUSr_fields,
  50143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50144         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50145         -1,
  50146         -1,
  50147     },
  50148 #endif /* chips */
  50149 
  50150 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50151     { /* SOC_REG_INT_LLS_L1_WERR_NEXT_ECC_STATUS_BCM56260_A0r */
  50152         soc_block_list[85],
  50153         soc_genreg,
  50154         1,
  50155         0,
  50156         0x200f000,
  50157         0,
  50158         0,
  50159         1,
  50160         soc_LLS_L1_WERR_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  50161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50162         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50163         -1,
  50164         -1,
  50165     },
  50166 #endif /* chips */
  50167 
  50168 #if defined(BCM_56270_A0)
  50169     { /* SOC_REG_INT_LLS_L1_WERR_NEXT_ECC_STATUS_BCM56270_A0r */
  50170         soc_block_list[85],
  50171         soc_genreg,
  50172         1,
  50173         0,
  50174         0x200d700,
  50175         0,
  50176         0,
  50177         1,
  50178         soc_LLS_L1_WERR_NEXT_ECC_STATUS_BCM56270_A0r_fields,
  50179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50180         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50181         -1,
  50182         -1,
  50183     },
  50184 #endif /* chips */
  50185 
  50186 #if defined(BCM_56440_B0)
  50187     { /* SOC_REG_INT_LLS_L1_WERR_NEXT_ECC_STATUS_BCM56440_B0r */
  50188         soc_block_list[85],
  50189         soc_genreg,
  50190         1,
  50191         0,
  50192         0x8009e,
  50193         0,
  50194         0,
  50195         1,
  50196         soc_LLS_L1_WERR_NEXT_ECC_STATUSr_fields,
  50197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50198         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50199         -1,
  50200         -1,
  50201     },
  50202 #endif /* chips */
  50203 
  50204 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50205     defined(BCM_56450_B1)
  50206     { /* SOC_REG_INT_LLS_L1_WERR_NEXT_ECC_STATUS_BCM56450_A0r */
  50207         soc_block_list[85],
  50208         soc_genreg,
  50209         1,
  50210         0,
  50211         0x2017800,
  50212         0,
  50213         0,
  50214         1,
  50215         soc_LLS_L1_WERR_NEXT_ECC_STATUS_BCM56450_A0r_fields,
  50216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50217         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50218         -1,
  50219         -1,
  50220     },
  50221 #endif /* chips */
  50222 
  50223 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  50224     { /* SOC_REG_INT_LLS_L1_WERR_NEXT_ECC_STATUS_BCM56640_A0r */
  50225         soc_block_list[4],
  50226         soc_genreg,
  50227         1,
  50228         0,
  50229         0x5a009400,
  50230         0,
  50231         0,
  50232         1,
  50233         soc_LLS_L1_WERR_NEXT_ECC_STATUS_BCM56640_A0r_fields,
  50234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50235         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  50236         -1,
  50237         -1,
  50238     },
  50239 #endif /* chips */
  50240 
  50241 #if defined(BCM_56440_A0)
  50242     { /* SOC_REG_INT_LLS_L2_ACT_MIN_ECC_STATUSr */
  50243         soc_block_list[85],
  50244         soc_genreg,
  50245         1,
  50246         0,
  50247         0x800ab,
  50248         0,
  50249         0,
  50250         1,
  50251         soc_LLS_L2_ACT_MIN_ECC_STATUSr_fields,
  50252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50253         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50254         -1,
  50255         -1,
  50256     },
  50257 #endif /* chips */
  50258 
  50259 #if defined(BCM_56440_B0)
  50260     { /* SOC_REG_INT_LLS_L2_ACT_MIN_ECC_STATUS_BCM56440_B0r */
  50261         soc_block_list[85],
  50262         soc_genreg,
  50263         1,
  50264         0,
  50265         0x800b6,
  50266         0,
  50267         0,
  50268         1,
  50269         soc_LLS_L2_ACT_MIN_ECC_STATUSr_fields,
  50270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50271         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50272         -1,
  50273         -1,
  50274     },
  50275 #endif /* chips */
  50276 
  50277 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50278     defined(BCM_56450_B1)
  50279     { /* SOC_REG_INT_LLS_L2_ACT_MIN_ECC_STATUS_BCM56450_A0r */
  50280         soc_block_list[85],
  50281         soc_genreg,
  50282         1,
  50283         0,
  50284         0x2019200,
  50285         0,
  50286         0,
  50287         1,
  50288         soc_LLS_L2_ACT_MIN_ECC_STATUS_BCM56450_A0r_fields,
  50289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50290         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50291         -1,
  50292         -1,
  50293     },
  50294 #endif /* chips */
  50295 
  50296 #if defined(BCM_56440_A0)
  50297     { /* SOC_REG_INT_LLS_L2_ACT_SHAPER_ECC_STATUSr */
  50298         soc_block_list[85],
  50299         soc_genreg,
  50300         1,
  50301         0,
  50302         0x800ac,
  50303         0,
  50304         0,
  50305         1,
  50306         soc_LLS_L2_ACT_SHAPER_ECC_STATUSr_fields,
  50307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50308         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50309         -1,
  50310         -1,
  50311     },
  50312 #endif /* chips */
  50313 
  50314 #if defined(BCM_56440_B0)
  50315     { /* SOC_REG_INT_LLS_L2_ACT_SHAPER_ECC_STATUS_BCM56440_B0r */
  50316         soc_block_list[85],
  50317         soc_genreg,
  50318         1,
  50319         0,
  50320         0x800b7,
  50321         0,
  50322         0,
  50323         1,
  50324         soc_LLS_L2_ACT_SHAPER_ECC_STATUSr_fields,
  50325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50326         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50327         -1,
  50328         -1,
  50329     },
  50330 #endif /* chips */
  50331 
  50332 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50333     defined(BCM_56450_B1)
  50334     { /* SOC_REG_INT_LLS_L2_ACT_SHAPER_ECC_STATUS_BCM56450_A0r */
  50335         soc_block_list[85],
  50336         soc_genreg,
  50337         1,
  50338         0,
  50339         0x2019300,
  50340         0,
  50341         0,
  50342         1,
  50343         soc_LLS_L2_ACT_SHAPER_ECC_STATUS_BCM56450_A0r_fields,
  50344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50345         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50346         -1,
  50347         -1,
  50348     },
  50349 #endif /* chips */
  50350 
  50351 #if defined(BCM_56440_A0)
  50352     { /* SOC_REG_INT_LLS_L2_ACT_XON_ECC_STATUSr */
  50353         soc_block_list[85],
  50354         soc_genreg,
  50355         1,
  50356         0,
  50357         0x800ad,
  50358         0,
  50359         0,
  50360         1,
  50361         soc_LLS_L2_ACT_XON_ECC_STATUSr_fields,
  50362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50363         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50364         -1,
  50365         -1,
  50366     },
  50367 #endif /* chips */
  50368 
  50369 #if defined(BCM_56440_B0)
  50370     { /* SOC_REG_INT_LLS_L2_ACT_XON_ECC_STATUS_BCM56440_B0r */
  50371         soc_block_list[85],
  50372         soc_genreg,
  50373         1,
  50374         0,
  50375         0x800b8,
  50376         0,
  50377         0,
  50378         1,
  50379         soc_LLS_L2_ACT_XON_ECC_STATUSr_fields,
  50380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50381         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50382         -1,
  50383         -1,
  50384     },
  50385 #endif /* chips */
  50386 
  50387 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50388     defined(BCM_56450_B1)
  50389     { /* SOC_REG_INT_LLS_L2_ACT_XON_ECC_STATUS_BCM56450_A0r */
  50390         soc_block_list[85],
  50391         soc_genreg,
  50392         1,
  50393         0,
  50394         0x2019400,
  50395         0,
  50396         0,
  50397         1,
  50398         soc_LLS_L2_ACT_XON_ECC_STATUS_BCM56450_A0r_fields,
  50399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50400         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50401         -1,
  50402         -1,
  50403     },
  50404 #endif /* chips */
  50405 
  50406 #if defined(BCM_56440_A0)
  50407     { /* SOC_REG_INT_LLS_L2_CHILD_STATE1_ECC_STATUSr */
  50408         soc_block_list[85],
  50409         soc_genreg,
  50410         1,
  50411         0,
  50412         0x800a7,
  50413         0,
  50414         0,
  50415         1,
  50416         soc_LLS_L2_CHILD_STATE1_ECC_STATUSr_fields,
  50417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50418         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50419         -1,
  50420         -1,
  50421     },
  50422 #endif /* chips */
  50423 
  50424 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50425     { /* SOC_REG_INT_LLS_L2_CHILD_STATE1_ECC_STATUS_BCM56260_A0r */
  50426         soc_block_list[85],
  50427         soc_genreg,
  50428         1,
  50429         0,
  50430         0x200fc00,
  50431         0,
  50432         0,
  50433         1,
  50434         soc_LLS_L2_CHILD_STATE1_ECC_STATUS_BCM56260_A0r_fields,
  50435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50436         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50437         -1,
  50438         -1,
  50439     },
  50440 #endif /* chips */
  50441 
  50442 #if defined(BCM_56270_A0)
  50443     { /* SOC_REG_INT_LLS_L2_CHILD_STATE1_ECC_STATUS_BCM56270_A0r */
  50444         soc_block_list[85],
  50445         soc_genreg,
  50446         1,
  50447         0,
  50448         0x200e300,
  50449         0,
  50450         0,
  50451         1,
  50452         soc_LLS_L2_CHILD_STATE1_ECC_STATUS_BCM56270_A0r_fields,
  50453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50454         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  50455         -1,
  50456         -1,
  50457     },
  50458 #endif /* chips */
  50459 
  50460 #if defined(BCM_56440_B0)
  50461     { /* SOC_REG_INT_LLS_L2_CHILD_STATE1_ECC_STATUS_BCM56440_B0r */
  50462         soc_block_list[85],
  50463         soc_genreg,
  50464         1,
  50465         0,
  50466         0x800af,
  50467         0,
  50468         0,
  50469         1,
  50470         soc_LLS_L2_CHILD_STATE1_ECC_STATUSr_fields,
  50471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50472         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50473         -1,
  50474         -1,
  50475     },
  50476 #endif /* chips */
  50477 
  50478 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50479     defined(BCM_56450_B1)
  50480     { /* SOC_REG_INT_LLS_L2_CHILD_STATE1_ECC_STATUS_BCM56450_A0r */
  50481         soc_block_list[85],
  50482         soc_genreg,
  50483         1,
  50484         0,
  50485         0x2018900,
  50486         0,
  50487         0,
  50488         1,
  50489         soc_LLS_L2_CHILD_STATE1_ECC_STATUS_BCM56450_A0r_fields,
  50490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50491         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50492         -1,
  50493         -1,
  50494     },
  50495 #endif /* chips */
  50496 
  50497 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  50498     { /* SOC_REG_INT_LLS_L2_CHILD_STATE1_ECC_STATUS_BCM56640_A0r */
  50499         soc_block_list[4],
  50500         soc_genreg,
  50501         1,
  50502         0,
  50503         0x5a009d00,
  50504         0,
  50505         0,
  50506         1,
  50507         soc_LLS_L2_CHILD_STATE1_ECC_STATUS_BCM56640_A0r_fields,
  50508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50509         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  50510         -1,
  50511         -1,
  50512     },
  50513 #endif /* chips */
  50514 
  50515 #if defined(BCM_56440_A0)
  50516     { /* SOC_REG_INT_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUSr */
  50517         soc_block_list[85],
  50518         soc_genreg,
  50519         1,
  50520         0,
  50521         0x8009c,
  50522         0,
  50523         0,
  50524         1,
  50525         soc_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUSr_fields,
  50526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50527         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50528         -1,
  50529         -1,
  50530     },
  50531 #endif /* chips */
  50532 
  50533 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50534     { /* SOC_REG_INT_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS_BCM56260_A0r */
  50535         soc_block_list[85],
  50536         soc_genreg,
  50537         1,
  50538         0,
  50539         0x200f500,
  50540         0,
  50541         0,
  50542         1,
  50543         soc_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS_BCM56260_A0r_fields,
  50544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50545         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50546         -1,
  50547         -1,
  50548     },
  50549 #endif /* chips */
  50550 
  50551 #if defined(BCM_56270_A0)
  50552     { /* SOC_REG_INT_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS_BCM56270_A0r */
  50553         soc_block_list[85],
  50554         soc_genreg,
  50555         1,
  50556         0,
  50557         0x200dc00,
  50558         0,
  50559         0,
  50560         1,
  50561         soc_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS_BCM56270_A0r_fields,
  50562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50563         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  50564         -1,
  50565         -1,
  50566     },
  50567 #endif /* chips */
  50568 
  50569 #if defined(BCM_56440_B0)
  50570     { /* SOC_REG_INT_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS_BCM56440_B0r */
  50571         soc_block_list[85],
  50572         soc_genreg,
  50573         1,
  50574         0,
  50575         0x800a4,
  50576         0,
  50577         0,
  50578         1,
  50579         soc_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUSr_fields,
  50580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50581         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50582         -1,
  50583         -1,
  50584     },
  50585 #endif /* chips */
  50586 
  50587 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50588     defined(BCM_56450_B1)
  50589     { /* SOC_REG_INT_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS_BCM56450_A0r */
  50590         soc_block_list[85],
  50591         soc_genreg,
  50592         1,
  50593         0,
  50594         0x2017e00,
  50595         0,
  50596         0,
  50597         1,
  50598         soc_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS_BCM56450_A0r_fields,
  50599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50600         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50601         -1,
  50602         -1,
  50603     },
  50604 #endif /* chips */
  50605 
  50606 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  50607     { /* SOC_REG_INT_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS_BCM56640_A0r */
  50608         soc_block_list[4],
  50609         soc_genreg,
  50610         1,
  50611         0,
  50612         0x5a009900,
  50613         0,
  50614         0,
  50615         1,
  50616         soc_LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS_BCM56640_A0r_fields,
  50617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50618         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  50619         -1,
  50620         -1,
  50621     },
  50622 #endif /* chips */
  50623 
  50624 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  50625     { /* SOC_REG_INT_LLS_L2_CHILD_WEIGHT_WORKING_ECC_STATUSr */
  50626         soc_block_list[4],
  50627         soc_genreg,
  50628         1,
  50629         0,
  50630         0x5a009a00,
  50631         0,
  50632         0,
  50633         1,
  50634         soc_LLS_L2_CHILD_WEIGHT_WORKING_ECC_STATUSr_fields,
  50635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50636         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  50637         -1,
  50638         -1,
  50639     },
  50640 #endif /* chips */
  50641 
  50642 #if defined(BCM_56440_A0)
  50643     { /* SOC_REG_INT_LLS_L2_ECC_1B_COUNTERr */
  50644         soc_block_list[85],
  50645         soc_genreg,
  50646         1,
  50647         0,
  50648         0x80069,
  50649         0,
  50650         0,
  50651         1,
  50652         soc_LLS_L2_ECC_1B_COUNTERr_fields,
  50653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50654         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50655         -1,
  50656         -1,
  50657     },
  50658 #endif /* chips */
  50659 
  50660 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50661     { /* SOC_REG_INT_LLS_L2_ECC_1B_COUNTER_BCM56260_A0r */
  50662         soc_block_list[85],
  50663         soc_genreg,
  50664         1,
  50665         0,
  50666         0x200c400,
  50667         0,
  50668         0,
  50669         1,
  50670         soc_LLS_L2_ECC_1B_COUNTER_BCM56260_A0r_fields,
  50671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50672         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50673         -1,
  50674         -1,
  50675     },
  50676 #endif /* chips */
  50677 
  50678 #if defined(BCM_56270_A0)
  50679     { /* SOC_REG_INT_LLS_L2_ECC_1B_COUNTER_BCM56270_A0r */
  50680         soc_block_list[85],
  50681         soc_genreg,
  50682         1,
  50683         0,
  50684         0x200ab00,
  50685         0,
  50686         0,
  50687         1,
  50688         soc_LLS_L2_ECC_1B_COUNTER_BCM56260_A0r_fields,
  50689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50690         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50691         -1,
  50692         -1,
  50693     },
  50694 #endif /* chips */
  50695 
  50696 #if defined(BCM_56440_B0)
  50697     { /* SOC_REG_INT_LLS_L2_ECC_1B_COUNTER_BCM56440_B0r */
  50698         soc_block_list[85],
  50699         soc_genreg,
  50700         1,
  50701         0,
  50702         0x80071,
  50703         0,
  50704         0,
  50705         1,
  50706         soc_LLS_L2_ECC_1B_COUNTERr_fields,
  50707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50708         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50709         -1,
  50710         -1,
  50711     },
  50712 #endif /* chips */
  50713 
  50714 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50715     defined(BCM_56450_B1)
  50716     { /* SOC_REG_INT_LLS_L2_ECC_1B_COUNTER_BCM56450_A0r */
  50717         soc_block_list[85],
  50718         soc_genreg,
  50719         1,
  50720         0,
  50721         0x2014600,
  50722         0,
  50723         0,
  50724         1,
  50725         soc_LLS_L2_ECC_1B_COUNTER_BCM56450_A0r_fields,
  50726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50727         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50728         -1,
  50729         -1,
  50730     },
  50731 #endif /* chips */
  50732 
  50733 #if defined(BCM_56440_A0)
  50734     { /* SOC_REG_INT_LLS_L2_ECC_2B_COUNTERr */
  50735         soc_block_list[85],
  50736         soc_genreg,
  50737         1,
  50738         0,
  50739         0x8006a,
  50740         0,
  50741         0,
  50742         1,
  50743         soc_LLS_L2_ECC_2B_COUNTERr_fields,
  50744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50745         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50746         -1,
  50747         -1,
  50748     },
  50749 #endif /* chips */
  50750 
  50751 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50752     { /* SOC_REG_INT_LLS_L2_ECC_2B_COUNTER_BCM56260_A0r */
  50753         soc_block_list[85],
  50754         soc_genreg,
  50755         1,
  50756         0,
  50757         0x200c500,
  50758         0,
  50759         0,
  50760         1,
  50761         soc_LLS_L2_ECC_2B_COUNTER_BCM56260_A0r_fields,
  50762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50763         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50764         -1,
  50765         -1,
  50766     },
  50767 #endif /* chips */
  50768 
  50769 #if defined(BCM_56270_A0)
  50770     { /* SOC_REG_INT_LLS_L2_ECC_2B_COUNTER_BCM56270_A0r */
  50771         soc_block_list[85],
  50772         soc_genreg,
  50773         1,
  50774         0,
  50775         0x200ac00,
  50776         0,
  50777         0,
  50778         1,
  50779         soc_LLS_L2_ECC_2B_COUNTER_BCM56260_A0r_fields,
  50780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50781         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50782         -1,
  50783         -1,
  50784     },
  50785 #endif /* chips */
  50786 
  50787 #if defined(BCM_56440_B0)
  50788     { /* SOC_REG_INT_LLS_L2_ECC_2B_COUNTER_BCM56440_B0r */
  50789         soc_block_list[85],
  50790         soc_genreg,
  50791         1,
  50792         0,
  50793         0x80072,
  50794         0,
  50795         0,
  50796         1,
  50797         soc_LLS_L2_ECC_2B_COUNTERr_fields,
  50798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50799         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50800         -1,
  50801         -1,
  50802     },
  50803 #endif /* chips */
  50804 
  50805 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50806     defined(BCM_56450_B1)
  50807     { /* SOC_REG_INT_LLS_L2_ECC_2B_COUNTER_BCM56450_A0r */
  50808         soc_block_list[85],
  50809         soc_genreg,
  50810         1,
  50811         0,
  50812         0x2014700,
  50813         0,
  50814         0,
  50815         1,
  50816         soc_LLS_L2_ECC_2B_COUNTER_BCM56450_A0r_fields,
  50817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50818         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50819         -1,
  50820         -1,
  50821     },
  50822 #endif /* chips */
  50823 
  50824 #if defined(BCM_56440_A0)
  50825     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG1r */
  50826         soc_block_list[85],
  50827         soc_genreg,
  50828         1,
  50829         0,
  50830         0x8006f,
  50831         0,
  50832         0,
  50833         10,
  50834         soc_LLS_L2_ECC_DEBUG1r_fields,
  50835         SOC_RESET_VAL_DEC(0x00000155, 0x00000000)
  50836         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50837         -1,
  50838         -1,
  50839     },
  50840 #endif /* chips */
  50841 
  50842 #if defined(BCM_56440_A0)
  50843     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG2r */
  50844         soc_block_list[85],
  50845         soc_genreg,
  50846         1,
  50847         0,
  50848         0x80070,
  50849         0,
  50850         0,
  50851         16,
  50852         soc_LLS_L2_ECC_DEBUG2r_fields,
  50853         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  50854         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  50855         -1,
  50856         -1,
  50857     },
  50858 #endif /* chips */
  50859 
  50860 #if defined(BCM_56440_A0)
  50861     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG3r */
  50862         soc_block_list[85],
  50863         soc_genreg,
  50864         1,
  50865         0,
  50866         0x80071,
  50867         0,
  50868         0,
  50869         6,
  50870         soc_LLS_L2_ECC_DEBUG3r_fields,
  50871         SOC_RESET_VAL_DEC(0x00000015, 0x00000000)
  50872         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  50873         -1,
  50874         -1,
  50875     },
  50876 #endif /* chips */
  50877 
  50878 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50879     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG1_BCM56260_A0r */
  50880         soc_block_list[85],
  50881         soc_genreg,
  50882         1,
  50883         0,
  50884         0x200cb00,
  50885         0,
  50886         0,
  50887         10,
  50888         soc_LLS_L2_ECC_DEBUG1_BCM56260_A0r_fields,
  50889         SOC_RESET_VAL_DEC(0x00001249, 0x00000000)
  50890         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  50891         -1,
  50892         -1,
  50893     },
  50894 #endif /* chips */
  50895 
  50896 #if defined(BCM_56270_A0)
  50897     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG1_BCM56270_A0r */
  50898         soc_block_list[85],
  50899         soc_genreg,
  50900         1,
  50901         0,
  50902         0x200b200,
  50903         0,
  50904         0,
  50905         10,
  50906         soc_LLS_L2_ECC_DEBUG1_BCM56260_A0r_fields,
  50907         SOC_RESET_VAL_DEC(0x00001249, 0x00000000)
  50908         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  50909         -1,
  50910         -1,
  50911     },
  50912 #endif /* chips */
  50913 
  50914 #if defined(BCM_56440_B0)
  50915     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG1_BCM56440_B0r */
  50916         soc_block_list[85],
  50917         soc_genreg,
  50918         1,
  50919         0,
  50920         0x80077,
  50921         0,
  50922         0,
  50923         10,
  50924         soc_LLS_L2_ECC_DEBUG1r_fields,
  50925         SOC_RESET_VAL_DEC(0x00000155, 0x00000000)
  50926         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50927         -1,
  50928         -1,
  50929     },
  50930 #endif /* chips */
  50931 
  50932 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  50933     defined(BCM_56450_B1)
  50934     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG1_BCM56450_A0r */
  50935         soc_block_list[85],
  50936         soc_genreg,
  50937         1,
  50938         0,
  50939         0x2014c00,
  50940         0,
  50941         0,
  50942         10,
  50943         soc_LLS_L2_ECC_DEBUG1_BCM56450_A0r_fields,
  50944         SOC_RESET_VAL_DEC(0x00000155, 0x00000000)
  50945         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  50946         -1,
  50947         -1,
  50948     },
  50949 #endif /* chips */
  50950 
  50951 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  50952     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG1_BCM56560_A0r */
  50953         soc_block_list[4],
  50954         soc_genreg,
  50955         1,
  50956         0,
  50957         0x62007600,
  50958         0,
  50959         0,
  50960         16,
  50961         soc_LLS_L2_ECC_DEBUG1_BCM56560_A0r_fields,
  50962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50963         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  50964         -1,
  50965         -1,
  50966     },
  50967 #endif /* chips */
  50968 
  50969 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  50970     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG1_BCM56640_A0r */
  50971         soc_block_list[4],
  50972         soc_genreg,
  50973         1,
  50974         0,
  50975         0x5a007900,
  50976         0,
  50977         0,
  50978         7,
  50979         soc_LLS_L2_ECC_DEBUG1_BCM56640_A0r_fields,
  50980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50981         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  50982         -1,
  50983         -1,
  50984     },
  50985 #endif /* chips */
  50986 
  50987 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50988     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG2_BCM56260_A0r */
  50989         soc_block_list[85],
  50990         soc_genreg,
  50991         1,
  50992         0,
  50993         0x200cc00,
  50994         0,
  50995         0,
  50996         8,
  50997         soc_LLS_L2_ECC_DEBUG2_BCM56260_A0r_fields,
  50998         SOC_RESET_VAL_DEC(0x00000249, 0x00000000)
  50999         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51000         -1,
  51001         -1,
  51002     },
  51003 #endif /* chips */
  51004 
  51005 #if defined(BCM_56270_A0)
  51006     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG2_BCM56270_A0r */
  51007         soc_block_list[85],
  51008         soc_genreg,
  51009         1,
  51010         0,
  51011         0x200b300,
  51012         0,
  51013         0,
  51014         8,
  51015         soc_LLS_L2_ECC_DEBUG2_BCM56260_A0r_fields,
  51016         SOC_RESET_VAL_DEC(0x00000249, 0x00000000)
  51017         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51018         -1,
  51019         -1,
  51020     },
  51021 #endif /* chips */
  51022 
  51023 #if defined(BCM_56440_B0)
  51024     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG2_BCM56440_B0r */
  51025         soc_block_list[85],
  51026         soc_genreg,
  51027         1,
  51028         0,
  51029         0x80078,
  51030         0,
  51031         0,
  51032         16,
  51033         soc_LLS_L2_ECC_DEBUG2r_fields,
  51034         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  51035         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  51036         -1,
  51037         -1,
  51038     },
  51039 #endif /* chips */
  51040 
  51041 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51042     defined(BCM_56450_B1)
  51043     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG2_BCM56450_A0r */
  51044         soc_block_list[85],
  51045         soc_genreg,
  51046         1,
  51047         0,
  51048         0x2014d00,
  51049         0,
  51050         0,
  51051         16,
  51052         soc_LLS_L2_ECC_DEBUG2_BCM56450_A0r_fields,
  51053         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  51054         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  51055         -1,
  51056         -1,
  51057     },
  51058 #endif /* chips */
  51059 
  51060 #if defined(BCM_56440_B0)
  51061     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG3_BCM56440_B0r */
  51062         soc_block_list[85],
  51063         soc_genreg,
  51064         1,
  51065         0,
  51066         0x80079,
  51067         0,
  51068         0,
  51069         6,
  51070         soc_LLS_L2_ECC_DEBUG3r_fields,
  51071         SOC_RESET_VAL_DEC(0x00000015, 0x00000000)
  51072         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  51073         -1,
  51074         -1,
  51075     },
  51076 #endif /* chips */
  51077 
  51078 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51079     defined(BCM_56450_B1)
  51080     { /* SOC_REG_INT_LLS_L2_ECC_DEBUG3_BCM56450_A0r */
  51081         soc_block_list[85],
  51082         soc_genreg,
  51083         1,
  51084         0,
  51085         0x2014e00,
  51086         0,
  51087         0,
  51088         6,
  51089         soc_LLS_L2_ECC_DEBUG3_BCM56450_A0r_fields,
  51090         SOC_RESET_VAL_DEC(0x00000015, 0x00000000)
  51091         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  51092         -1,
  51093         -1,
  51094     },
  51095 #endif /* chips */
  51096 
  51097 #if defined(BCM_56440_A0)
  51098     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1r */
  51099         soc_block_list[85],
  51100         soc_genreg,
  51101         1,
  51102         0,
  51103         0x80079,
  51104         0,
  51105         0,
  51106         26,
  51107         soc_LLS_L2_ECC_ERROR1r_fields,
  51108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51109         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  51110         -1,
  51111         -1,
  51112     },
  51113 #endif /* chips */
  51114 
  51115 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  51116     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_BCM56260_A0r */
  51117         soc_block_list[85],
  51118         soc_genreg,
  51119         1,
  51120         0,
  51121         0x200d400,
  51122         0,
  51123         0,
  51124         18,
  51125         soc_LLS_L2_ECC_ERROR1_BCM56260_A0r_fields,
  51126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51127         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  51128         -1,
  51129         -1,
  51130     },
  51131 #endif /* chips */
  51132 
  51133 #if defined(BCM_56270_A0)
  51134     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_BCM56270_A0r */
  51135         soc_block_list[85],
  51136         soc_genreg,
  51137         1,
  51138         0,
  51139         0x200bb00,
  51140         0,
  51141         0,
  51142         18,
  51143         soc_LLS_L2_ECC_ERROR1_BCM56260_A0r_fields,
  51144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51145         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  51146         -1,
  51147         -1,
  51148     },
  51149 #endif /* chips */
  51150 
  51151 #if defined(BCM_56440_B0)
  51152     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_BCM56440_B0r */
  51153         soc_block_list[85],
  51154         soc_genreg,
  51155         1,
  51156         0,
  51157         0x80081,
  51158         0,
  51159         0,
  51160         26,
  51161         soc_LLS_L2_ECC_ERROR1r_fields,
  51162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51163         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  51164         -1,
  51165         -1,
  51166     },
  51167 #endif /* chips */
  51168 
  51169 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51170     defined(BCM_56450_B1)
  51171     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_BCM56450_A0r */
  51172         soc_block_list[85],
  51173         soc_genreg,
  51174         1,
  51175         0,
  51176         0x2015600,
  51177         0,
  51178         0,
  51179         26,
  51180         soc_LLS_L2_ECC_ERROR1_BCM56450_A0r_fields,
  51181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51182         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  51183         -1,
  51184         -1,
  51185     },
  51186 #endif /* chips */
  51187 
  51188 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  51189     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_BCM56640_A0r */
  51190         soc_block_list[4],
  51191         soc_genreg,
  51192         1,
  51193         0,
  51194         0x5a007d00,
  51195         0,
  51196         0,
  51197         14,
  51198         soc_LLS_L2_ECC_ERROR1_BCM56640_A0r_fields,
  51199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51200         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  51201         -1,
  51202         -1,
  51203     },
  51204 #endif /* chips */
  51205 
  51206 #if defined(BCM_56440_A0)
  51207     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_MASKr */
  51208         soc_block_list[85],
  51209         soc_genreg,
  51210         1,
  51211         0,
  51212         0x8007a,
  51213         0,
  51214         0,
  51215         26,
  51216         soc_LLS_L2_ECC_ERROR1_MASKr_fields,
  51217         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  51218         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  51219         -1,
  51220         -1,
  51221     },
  51222 #endif /* chips */
  51223 
  51224 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  51225     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_MASK_BCM56260_A0r */
  51226         soc_block_list[85],
  51227         soc_genreg,
  51228         1,
  51229         0,
  51230         0x200d500,
  51231         0,
  51232         0,
  51233         18,
  51234         soc_LLS_L2_ECC_ERROR1_MASK_BCM56260_A0r_fields,
  51235         SOC_RESET_VAL_DEC(0x0003ffff, 0x00000000)
  51236         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  51237         -1,
  51238         -1,
  51239     },
  51240 #endif /* chips */
  51241 
  51242 #if defined(BCM_56270_A0)
  51243     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_MASK_BCM56270_A0r */
  51244         soc_block_list[85],
  51245         soc_genreg,
  51246         1,
  51247         0,
  51248         0x200bc00,
  51249         0,
  51250         0,
  51251         18,
  51252         soc_LLS_L2_ECC_ERROR1_MASK_BCM56260_A0r_fields,
  51253         SOC_RESET_VAL_DEC(0x0003ffff, 0x00000000)
  51254         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  51255         -1,
  51256         -1,
  51257     },
  51258 #endif /* chips */
  51259 
  51260 #if defined(BCM_56440_B0)
  51261     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_MASK_BCM56440_B0r */
  51262         soc_block_list[85],
  51263         soc_genreg,
  51264         1,
  51265         0,
  51266         0x80082,
  51267         0,
  51268         0,
  51269         26,
  51270         soc_LLS_L2_ECC_ERROR1_MASKr_fields,
  51271         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  51272         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  51273         -1,
  51274         -1,
  51275     },
  51276 #endif /* chips */
  51277 
  51278 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51279     defined(BCM_56450_B1)
  51280     { /* SOC_REG_INT_LLS_L2_ECC_ERROR1_MASK_BCM56450_A0r */
  51281         soc_block_list[85],
  51282         soc_genreg,
  51283         1,
  51284         0,
  51285         0x2015700,
  51286         0,
  51287         0,
  51288         26,
  51289         soc_LLS_L2_ECC_ERROR1_MASK_BCM56450_A0r_fields,
  51290         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  51291         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  51292         -1,
  51293         -1,
  51294     },
  51295 #endif /* chips */
  51296 
  51297 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51298     defined(BCM_56450_B1)
  51299     { /* SOC_REG_INT_LLS_L2_EMPTY_SEEN_STATUSr */
  51300         soc_block_list[85],
  51301         soc_genreg,
  51302         1,
  51303         0,
  51304         0x2011100,
  51305         0,
  51306         0,
  51307         1,
  51308         soc_LLS_L2_EMPTY_SEEN_STATUSr_fields,
  51309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51310         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51311         -1,
  51312         -1,
  51313     },
  51314 #endif /* chips */
  51315 
  51316 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  51317     { /* SOC_REG_INT_LLS_L2_EMPTY_SEEN_STATUS_BCM56260_A0r */
  51318         soc_block_list[85],
  51319         soc_genreg,
  51320         1,
  51321         0,
  51322         0x2009200,
  51323         0,
  51324         0,
  51325         1,
  51326         soc_LLS_L2_EMPTY_SEEN_STATUS_BCM56260_A0r_fields,
  51327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51328         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  51329         -1,
  51330         -1,
  51331     },
  51332 #endif /* chips */
  51333 
  51334 #if defined(BCM_56270_A0)
  51335     { /* SOC_REG_INT_LLS_L2_EMPTY_SEEN_STATUS_BCM56270_A0r */
  51336         soc_block_list[85],
  51337         soc_genreg,
  51338         1,
  51339         0,
  51340         0x2007900,
  51341         0,
  51342         0,
  51343         1,
  51344         soc_LLS_L2_EMPTY_SEEN_STATUS_BCM56270_A0r_fields,
  51345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51346         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51347         -1,
  51348         -1,
  51349     },
  51350 #endif /* chips */
  51351 
  51352 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  51353     { /* SOC_REG_INT_LLS_L2_EMPTY_SEEN_STATUS_BCM56560_A0r */
  51354         soc_block_list[4],
  51355         soc_genreg,
  51356         1,
  51357         0,
  51358         0x62004100,
  51359         0,
  51360         0,
  51361         1,
  51362         soc_LLS_L2_EMPTY_SEEN_STATUS_BCM56560_A0r_fields,
  51363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51364         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  51365         -1,
  51366         -1,
  51367     },
  51368 #endif /* chips */
  51369 
  51370 #if defined(BCM_56440_A0)
  51371     { /* SOC_REG_INT_LLS_L2_ERROR_ECC_STATUSr */
  51372         soc_block_list[85],
  51373         soc_genreg,
  51374         1,
  51375         0,
  51376         0x800aa,
  51377         0,
  51378         0,
  51379         1,
  51380         soc_LLS_L2_ERROR_ECC_STATUSr_fields,
  51381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51382         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51383         -1,
  51384         -1,
  51385     },
  51386 #endif /* chips */
  51387 
  51388 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  51389     { /* SOC_REG_INT_LLS_L2_ERROR_ECC_STATUS_BCM56260_A0r */
  51390         soc_block_list[85],
  51391         soc_genreg,
  51392         1,
  51393         0,
  51394         0x200ff00,
  51395         0,
  51396         0,
  51397         1,
  51398         soc_LLS_L2_ERROR_ECC_STATUS_BCM56260_A0r_fields,
  51399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51400         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  51401         -1,
  51402         -1,
  51403     },
  51404 #endif /* chips */
  51405 
  51406 #if defined(BCM_56270_A0)
  51407     { /* SOC_REG_INT_LLS_L2_ERROR_ECC_STATUS_BCM56270_A0r */
  51408         soc_block_list[85],
  51409         soc_genreg,
  51410         1,
  51411         0,
  51412         0x200e600,
  51413         0,
  51414         0,
  51415         1,
  51416         soc_LLS_L2_ERROR_ECC_STATUS_BCM56270_A0r_fields,
  51417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51418         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  51419         -1,
  51420         -1,
  51421     },
  51422 #endif /* chips */
  51423 
  51424 #if defined(BCM_56440_B0)
  51425     { /* SOC_REG_INT_LLS_L2_ERROR_ECC_STATUS_BCM56440_B0r */
  51426         soc_block_list[85],
  51427         soc_genreg,
  51428         1,
  51429         0,
  51430         0x800b2,
  51431         0,
  51432         0,
  51433         1,
  51434         soc_LLS_L2_ERROR_ECC_STATUSr_fields,
  51435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51436         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51437         -1,
  51438         -1,
  51439     },
  51440 #endif /* chips */
  51441 
  51442 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51443     defined(BCM_56450_B1)
  51444     { /* SOC_REG_INT_LLS_L2_ERROR_ECC_STATUS_BCM56450_A0r */
  51445         soc_block_list[85],
  51446         soc_genreg,
  51447         1,
  51448         0,
  51449         0x2018e00,
  51450         0,
  51451         0,
  51452         1,
  51453         soc_LLS_L2_ERROR_ECC_STATUS_BCM56450_A0r_fields,
  51454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51455         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51456         -1,
  51457         -1,
  51458     },
  51459 #endif /* chips */
  51460 
  51461 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  51462     { /* SOC_REG_INT_LLS_L2_ERROR_ECC_STATUS_BCM56640_A0r */
  51463         soc_block_list[4],
  51464         soc_genreg,
  51465         1,
  51466         0,
  51467         0x5a009e00,
  51468         0,
  51469         0,
  51470         1,
  51471         soc_LLS_L2_ERROR_ECC_STATUS_BCM56640_A0r_fields,
  51472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51473         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  51474         -1,
  51475         -1,
  51476     },
  51477 #endif /* chips */
  51478 
  51479 #if defined(BCM_56440_B0)
  51480     { /* SOC_REG_INT_LLS_L2_ERROR_MIN_ECC_STATUSr */
  51481         soc_block_list[85],
  51482         soc_genreg,
  51483         1,
  51484         0,
  51485         0x800b5,
  51486         0,
  51487         0,
  51488         1,
  51489         soc_LLS_L2_ERROR_MIN_ECC_STATUSr_fields,
  51490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51491         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51492         -1,
  51493         -1,
  51494     },
  51495 #endif /* chips */
  51496 
  51497 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51498     defined(BCM_56450_B1)
  51499     { /* SOC_REG_INT_LLS_L2_ERROR_MIN_ECC_STATUS_BCM56450_A0r */
  51500         soc_block_list[85],
  51501         soc_genreg,
  51502         1,
  51503         0,
  51504         0x2019100,
  51505         0,
  51506         0,
  51507         1,
  51508         soc_LLS_L2_ERROR_MIN_ECC_STATUS_BCM56450_A0r_fields,
  51509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51510         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51511         -1,
  51512         -1,
  51513     },
  51514 #endif /* chips */
  51515 
  51516 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  51517     { /* SOC_REG_INT_LLS_L2_MIN_BUCKET_C_ECC_STATUSr */
  51518         soc_block_list[85],
  51519         soc_genreg,
  51520         1,
  51521         0,
  51522         0x200fb00,
  51523         0,
  51524         0,
  51525         1,
  51526         soc_LLS_L2_MIN_BUCKET_C_ECC_STATUSr_fields,
  51527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51528         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  51529         -1,
  51530         -1,
  51531     },
  51532 #endif /* chips */
  51533 
  51534 #if defined(BCM_56270_A0)
  51535     { /* SOC_REG_INT_LLS_L2_MIN_BUCKET_C_ECC_STATUS_BCM56270_A0r */
  51536         soc_block_list[85],
  51537         soc_genreg,
  51538         1,
  51539         0,
  51540         0x200e200,
  51541         0,
  51542         0,
  51543         1,
  51544         soc_LLS_L2_MIN_BUCKET_C_ECC_STATUS_BCM56270_A0r_fields,
  51545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51546         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  51547         -1,
  51548         -1,
  51549     },
  51550 #endif /* chips */
  51551 
  51552 #if defined(BCM_56440_A0)
  51553     { /* SOC_REG_INT_LLS_L2_MIN_BUCKET_LOWER_C_ECC_STATUSr */
  51554         soc_block_list[85],
  51555         soc_genreg,
  51556         1,
  51557         0,
  51558         0x800a6,
  51559         0,
  51560         0,
  51561         1,
  51562         soc_LLS_L2_MIN_BUCKET_LOWER_C_ECC_STATUSr_fields,
  51563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51564         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51565         -1,
  51566         -1,
  51567     },
  51568 #endif /* chips */
  51569 
  51570 #if defined(BCM_56440_B0)
  51571     { /* SOC_REG_INT_LLS_L2_MIN_BUCKET_LOWER_C_ECC_STATUS_BCM56440_B0r */
  51572         soc_block_list[85],
  51573         soc_genreg,
  51574         1,
  51575         0,
  51576         0x800ae,
  51577         0,
  51578         0,
  51579         1,
  51580         soc_LLS_L2_MIN_BUCKET_LOWER_C_ECC_STATUSr_fields,
  51581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51582         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51583         -1,
  51584         -1,
  51585     },
  51586 #endif /* chips */
  51587 
  51588 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51589     defined(BCM_56450_B1)
  51590     { /* SOC_REG_INT_LLS_L2_MIN_BUCKET_LOWER_C_ECC_STATUS_BCM56450_A0r */
  51591         soc_block_list[85],
  51592         soc_genreg,
  51593         1,
  51594         0,
  51595         0x2018800,
  51596         0,
  51597         0,
  51598         1,
  51599         soc_LLS_L2_MIN_BUCKET_LOWER_C_ECC_STATUS_BCM56450_A0r_fields,
  51600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51601         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51602         -1,
  51603         -1,
  51604     },
  51605 #endif /* chips */
  51606 
  51607 #if defined(BCM_56440_A0)
  51608     { /* SOC_REG_INT_LLS_L2_MIN_BUCKET_UPPER_C_ECC_STATUSr */
  51609         soc_block_list[85],
  51610         soc_genreg,
  51611         1,
  51612         0,
  51613         0x800a2,
  51614         0,
  51615         0,
  51616         1,
  51617         soc_LLS_L2_MIN_BUCKET_UPPER_C_ECC_STATUSr_fields,
  51618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51619         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51620         -1,
  51621         -1,
  51622     },
  51623 #endif /* chips */
  51624 
  51625 #if defined(BCM_56440_B0)
  51626     { /* SOC_REG_INT_LLS_L2_MIN_BUCKET_UPPER_C_ECC_STATUS_BCM56440_B0r */
  51627         soc_block_list[85],
  51628         soc_genreg,
  51629         1,
  51630         0,
  51631         0x800aa,
  51632         0,
  51633         0,
  51634         1,
  51635         soc_LLS_L2_MIN_BUCKET_UPPER_C_ECC_STATUSr_fields,
  51636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51637         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51638         -1,
  51639         -1,
  51640     },
  51641 #endif /* chips */
  51642 
  51643 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51644     defined(BCM_56450_B1)
  51645     { /* SOC_REG_INT_LLS_L2_MIN_BUCKET_UPPER_C_ECC_STATUS_BCM56450_A0r */
  51646         soc_block_list[85],
  51647         soc_genreg,
  51648         1,
  51649         0,
  51650         0x2018400,
  51651         0,
  51652         0,
  51653         1,
  51654         soc_LLS_L2_MIN_BUCKET_UPPER_C_ECC_STATUS_BCM56450_A0r_fields,
  51655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51656         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51657         -1,
  51658         -1,
  51659     },
  51660 #endif /* chips */
  51661 
  51662 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  51663     { /* SOC_REG_INT_LLS_L2_MIN_CONFIG_C_ECC_STATUSr */
  51664         soc_block_list[85],
  51665         soc_genreg,
  51666         1,
  51667         0,
  51668         0x200fa00,
  51669         0,
  51670         0,
  51671         1,
  51672         soc_LLS_L2_MIN_CONFIG_C_ECC_STATUSr_fields,
  51673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51674         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  51675         -1,
  51676         -1,
  51677     },
  51678 #endif /* chips */
  51679 
  51680 #if defined(BCM_56270_A0)
  51681     { /* SOC_REG_INT_LLS_L2_MIN_CONFIG_C_ECC_STATUS_BCM56270_A0r */
  51682         soc_block_list[85],
  51683         soc_genreg,
  51684         1,
  51685         0,
  51686         0x200e100,
  51687         0,
  51688         0,
  51689         1,
  51690         soc_LLS_L2_MIN_CONFIG_C_ECC_STATUS_BCM56270_A0r_fields,
  51691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51692         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  51693         -1,
  51694         -1,
  51695     },
  51696 #endif /* chips */
  51697 
  51698 #if defined(BCM_56440_A0)
  51699     { /* SOC_REG_INT_LLS_L2_MIN_CONFIG_LOWER_C_ECC_STATUSr */
  51700         soc_block_list[85],
  51701         soc_genreg,
  51702         1,
  51703         0,
  51704         0x800a5,
  51705         0,
  51706         0,
  51707         1,
  51708         soc_LLS_L2_MIN_CONFIG_LOWER_C_ECC_STATUSr_fields,
  51709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51710         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51711         -1,
  51712         -1,
  51713     },
  51714 #endif /* chips */
  51715 
  51716 #if defined(BCM_56440_B0)
  51717     { /* SOC_REG_INT_LLS_L2_MIN_CONFIG_LOWER_C_ECC_STATUS_BCM56440_B0r */
  51718         soc_block_list[85],
  51719         soc_genreg,
  51720         1,
  51721         0,
  51722         0x800ad,
  51723         0,
  51724         0,
  51725         1,
  51726         soc_LLS_L2_MIN_CONFIG_LOWER_C_ECC_STATUSr_fields,
  51727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51728         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51729         -1,
  51730         -1,
  51731     },
  51732 #endif /* chips */
  51733 
  51734 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51735     defined(BCM_56450_B1)
  51736     { /* SOC_REG_INT_LLS_L2_MIN_CONFIG_LOWER_C_ECC_STATUS_BCM56450_A0r */
  51737         soc_block_list[85],
  51738         soc_genreg,
  51739         1,
  51740         0,
  51741         0x2018700,
  51742         0,
  51743         0,
  51744         1,
  51745         soc_LLS_L2_MIN_CONFIG_LOWER_C_ECC_STATUS_BCM56450_A0r_fields,
  51746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51747         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51748         -1,
  51749         -1,
  51750     },
  51751 #endif /* chips */
  51752 
  51753 #if defined(BCM_56440_A0)
  51754     { /* SOC_REG_INT_LLS_L2_MIN_CONFIG_UPPER_C_ECC_STATUSr */
  51755         soc_block_list[85],
  51756         soc_genreg,
  51757         1,
  51758         0,
  51759         0x800a1,
  51760         0,
  51761         0,
  51762         1,
  51763         soc_LLS_L2_MIN_CONFIG_UPPER_C_ECC_STATUSr_fields,
  51764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51765         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51766         -1,
  51767         -1,
  51768     },
  51769 #endif /* chips */
  51770 
  51771 #if defined(BCM_56440_B0)
  51772     { /* SOC_REG_INT_LLS_L2_MIN_CONFIG_UPPER_C_ECC_STATUS_BCM56440_B0r */
  51773         soc_block_list[85],
  51774         soc_genreg,
  51775         1,
  51776         0,
  51777         0x800a9,
  51778         0,
  51779         0,
  51780         1,
  51781         soc_LLS_L2_MIN_CONFIG_UPPER_C_ECC_STATUSr_fields,
  51782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51783         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51784         -1,
  51785         -1,
  51786     },
  51787 #endif /* chips */
  51788 
  51789 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51790     defined(BCM_56450_B1)
  51791     { /* SOC_REG_INT_LLS_L2_MIN_CONFIG_UPPER_C_ECC_STATUS_BCM56450_A0r */
  51792         soc_block_list[85],
  51793         soc_genreg,
  51794         1,
  51795         0,
  51796         0x2018300,
  51797         0,
  51798         0,
  51799         1,
  51800         soc_LLS_L2_MIN_CONFIG_UPPER_C_ECC_STATUS_BCM56450_A0r_fields,
  51801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51802         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51803         -1,
  51804         -1,
  51805     },
  51806 #endif /* chips */
  51807 
  51808 #if defined(BCM_56440_A0)
  51809     { /* SOC_REG_INT_LLS_L2_MIN_NEXT_ECC_STATUSr */
  51810         soc_block_list[85],
  51811         soc_genreg,
  51812         1,
  51813         0,
  51814         0x8009e,
  51815         0,
  51816         0,
  51817         1,
  51818         soc_LLS_L2_MIN_NEXT_ECC_STATUSr_fields,
  51819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51820         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51821         -1,
  51822         -1,
  51823     },
  51824 #endif /* chips */
  51825 
  51826 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  51827     { /* SOC_REG_INT_LLS_L2_MIN_NEXT_ECC_STATUS_BCM56260_A0r */
  51828         soc_block_list[85],
  51829         soc_genreg,
  51830         1,
  51831         0,
  51832         0x200f700,
  51833         0,
  51834         0,
  51835         1,
  51836         soc_LLS_L2_MIN_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  51837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51838         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  51839         -1,
  51840         -1,
  51841     },
  51842 #endif /* chips */
  51843 
  51844 #if defined(BCM_56270_A0)
  51845     { /* SOC_REG_INT_LLS_L2_MIN_NEXT_ECC_STATUS_BCM56270_A0r */
  51846         soc_block_list[85],
  51847         soc_genreg,
  51848         1,
  51849         0,
  51850         0x200de00,
  51851         0,
  51852         0,
  51853         1,
  51854         soc_LLS_L2_MIN_NEXT_ECC_STATUS_BCM56270_A0r_fields,
  51855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51856         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51857         -1,
  51858         -1,
  51859     },
  51860 #endif /* chips */
  51861 
  51862 #if defined(BCM_56440_B0)
  51863     { /* SOC_REG_INT_LLS_L2_MIN_NEXT_ECC_STATUS_BCM56440_B0r */
  51864         soc_block_list[85],
  51865         soc_genreg,
  51866         1,
  51867         0,
  51868         0x800a6,
  51869         0,
  51870         0,
  51871         1,
  51872         soc_LLS_L2_MIN_NEXT_ECC_STATUSr_fields,
  51873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51874         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51875         -1,
  51876         -1,
  51877     },
  51878 #endif /* chips */
  51879 
  51880 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51881     defined(BCM_56450_B1)
  51882     { /* SOC_REG_INT_LLS_L2_MIN_NEXT_ECC_STATUS_BCM56450_A0r */
  51883         soc_block_list[85],
  51884         soc_genreg,
  51885         1,
  51886         0,
  51887         0x2018000,
  51888         0,
  51889         0,
  51890         1,
  51891         soc_LLS_L2_MIN_NEXT_ECC_STATUS_BCM56450_A0r_fields,
  51892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51893         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51894         -1,
  51895         -1,
  51896     },
  51897 #endif /* chips */
  51898 
  51899 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  51900     { /* SOC_REG_INT_LLS_L2_MIN_NEXT_ECC_STATUS_BCM56640_A0r */
  51901         soc_block_list[4],
  51902         soc_genreg,
  51903         1,
  51904         0,
  51905         0x5a009c00,
  51906         0,
  51907         0,
  51908         1,
  51909         soc_LLS_L2_MIN_NEXT_ECC_STATUS_BCM56640_A0r_fields,
  51910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51911         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  51912         -1,
  51913         -1,
  51914     },
  51915 #endif /* chips */
  51916 
  51917 #if defined(BCM_56440_A0)
  51918     { /* SOC_REG_INT_LLS_L2_PARENT_ECC_STATUSr */
  51919         soc_block_list[85],
  51920         soc_genreg,
  51921         1,
  51922         0,
  51923         0x8009b,
  51924         0,
  51925         0,
  51926         1,
  51927         soc_LLS_L2_PARENT_ECC_STATUSr_fields,
  51928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51929         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51930         -1,
  51931         -1,
  51932     },
  51933 #endif /* chips */
  51934 
  51935 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  51936     { /* SOC_REG_INT_LLS_L2_PARENT_ECC_STATUS_BCM56260_A0r */
  51937         soc_block_list[85],
  51938         soc_genreg,
  51939         1,
  51940         0,
  51941         0x200f400,
  51942         0,
  51943         0,
  51944         1,
  51945         soc_LLS_L2_PARENT_ECC_STATUS_BCM56260_A0r_fields,
  51946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51947         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  51948         -1,
  51949         -1,
  51950     },
  51951 #endif /* chips */
  51952 
  51953 #if defined(BCM_56270_A0)
  51954     { /* SOC_REG_INT_LLS_L2_PARENT_ECC_STATUS_BCM56270_A0r */
  51955         soc_block_list[85],
  51956         soc_genreg,
  51957         1,
  51958         0,
  51959         0x200db00,
  51960         0,
  51961         0,
  51962         1,
  51963         soc_LLS_L2_PARENT_ECC_STATUS_BCM56270_A0r_fields,
  51964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51965         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51966         -1,
  51967         -1,
  51968     },
  51969 #endif /* chips */
  51970 
  51971 #if defined(BCM_56440_B0)
  51972     { /* SOC_REG_INT_LLS_L2_PARENT_ECC_STATUS_BCM56440_B0r */
  51973         soc_block_list[85],
  51974         soc_genreg,
  51975         1,
  51976         0,
  51977         0x800a3,
  51978         0,
  51979         0,
  51980         1,
  51981         soc_LLS_L2_PARENT_ECC_STATUSr_fields,
  51982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51983         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51984         -1,
  51985         -1,
  51986     },
  51987 #endif /* chips */
  51988 
  51989 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  51990     defined(BCM_56450_B1)
  51991     { /* SOC_REG_INT_LLS_L2_PARENT_ECC_STATUS_BCM56450_A0r */
  51992         soc_block_list[85],
  51993         soc_genreg,
  51994         1,
  51995         0,
  51996         0x2017d00,
  51997         0,
  51998         0,
  51999         1,
  52000         soc_LLS_L2_PARENT_ECC_STATUS_BCM56450_A0r_fields,
  52001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52002         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  52003         -1,
  52004         -1,
  52005     },
  52006 #endif /* chips */
  52007 
  52008 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  52009     { /* SOC_REG_INT_LLS_L2_PARENT_ECC_STATUS_BCM56640_A0r */
  52010         soc_block_list[4],
  52011         soc_genreg,
  52012         1,
  52013         0,
  52014         0x5a009800,
  52015         0,
  52016         0,
  52017         1,
  52018         soc_LLS_L2_PARENT_ECC_STATUS_BCM56640_A0r_fields,
  52019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52020         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52021         -1,
  52022         -1,
  52023     },
  52024 #endif /* chips */
  52025 
  52026 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52027     { /* SOC_REG_INT_LLS_L2_SHAPER_BUCKET_C_ECC_STATUSr */
  52028         soc_block_list[85],
  52029         soc_genreg,
  52030         1,
  52031         0,
  52032         0x200f800,
  52033         0,
  52034         0,
  52035         1,
  52036         soc_LLS_L2_SHAPER_BUCKET_C_ECC_STATUSr_fields,
  52037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52038         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  52039         -1,
  52040         -1,
  52041     },
  52042 #endif /* chips */
  52043 
  52044 #if defined(BCM_56270_A0)
  52045     { /* SOC_REG_INT_LLS_L2_SHAPER_BUCKET_C_ECC_STATUS_BCM56270_A0r */
  52046         soc_block_list[85],
  52047         soc_genreg,
  52048         1,
  52049         0,
  52050         0x200df00,
  52051         0,
  52052         0,
  52053         1,
  52054         soc_LLS_L2_SHAPER_BUCKET_C_ECC_STATUS_BCM56270_A0r_fields,
  52055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52056         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  52057         -1,
  52058         -1,
  52059     },
  52060 #endif /* chips */
  52061 
  52062 #if defined(BCM_56440_A0)
  52063     { /* SOC_REG_INT_LLS_L2_SHAPER_BUCKET_LOWER_C_ECC_STATUSr */
  52064         soc_block_list[85],
  52065         soc_genreg,
  52066         1,
  52067         0,
  52068         0x800a4,
  52069         0,
  52070         0,
  52071         1,
  52072         soc_LLS_L2_SHAPER_BUCKET_LOWER_C_ECC_STATUSr_fields,
  52073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52074         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52075         -1,
  52076         -1,
  52077     },
  52078 #endif /* chips */
  52079 
  52080 #if defined(BCM_56440_B0)
  52081     { /* SOC_REG_INT_LLS_L2_SHAPER_BUCKET_LOWER_C_ECC_STATUS_BCM56440_B0r */
  52082         soc_block_list[85],
  52083         soc_genreg,
  52084         1,
  52085         0,
  52086         0x800ac,
  52087         0,
  52088         0,
  52089         1,
  52090         soc_LLS_L2_SHAPER_BUCKET_LOWER_C_ECC_STATUSr_fields,
  52091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52092         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52093         -1,
  52094         -1,
  52095     },
  52096 #endif /* chips */
  52097 
  52098 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52099     defined(BCM_56450_B1)
  52100     { /* SOC_REG_INT_LLS_L2_SHAPER_BUCKET_LOWER_C_ECC_STATUS_BCM56450_A0r */
  52101         soc_block_list[85],
  52102         soc_genreg,
  52103         1,
  52104         0,
  52105         0x2018600,
  52106         0,
  52107         0,
  52108         1,
  52109         soc_LLS_L2_SHAPER_BUCKET_LOWER_C_ECC_STATUS_BCM56450_A0r_fields,
  52110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52111         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52112         -1,
  52113         -1,
  52114     },
  52115 #endif /* chips */
  52116 
  52117 #if defined(BCM_56440_A0)
  52118     { /* SOC_REG_INT_LLS_L2_SHAPER_BUCKET_UPPER_C_ECC_STATUSr */
  52119         soc_block_list[85],
  52120         soc_genreg,
  52121         1,
  52122         0,
  52123         0x800a0,
  52124         0,
  52125         0,
  52126         1,
  52127         soc_LLS_L2_SHAPER_BUCKET_UPPER_C_ECC_STATUSr_fields,
  52128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52129         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52130         -1,
  52131         -1,
  52132     },
  52133 #endif /* chips */
  52134 
  52135 #if defined(BCM_56440_B0)
  52136     { /* SOC_REG_INT_LLS_L2_SHAPER_BUCKET_UPPER_C_ECC_STATUS_BCM56440_B0r */
  52137         soc_block_list[85],
  52138         soc_genreg,
  52139         1,
  52140         0,
  52141         0x800a8,
  52142         0,
  52143         0,
  52144         1,
  52145         soc_LLS_L2_SHAPER_BUCKET_UPPER_C_ECC_STATUSr_fields,
  52146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52147         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52148         -1,
  52149         -1,
  52150     },
  52151 #endif /* chips */
  52152 
  52153 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52154     defined(BCM_56450_B1)
  52155     { /* SOC_REG_INT_LLS_L2_SHAPER_BUCKET_UPPER_C_ECC_STATUS_BCM56450_A0r */
  52156         soc_block_list[85],
  52157         soc_genreg,
  52158         1,
  52159         0,
  52160         0x2018200,
  52161         0,
  52162         0,
  52163         1,
  52164         soc_LLS_L2_SHAPER_BUCKET_UPPER_C_ECC_STATUS_BCM56450_A0r_fields,
  52165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52166         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52167         -1,
  52168         -1,
  52169     },
  52170 #endif /* chips */
  52171 
  52172 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52173     { /* SOC_REG_INT_LLS_L2_SHAPER_CONFIG_C_ECC_STATUSr */
  52174         soc_block_list[85],
  52175         soc_genreg,
  52176         1,
  52177         0,
  52178         0x200f900,
  52179         0,
  52180         0,
  52181         1,
  52182         soc_LLS_L2_SHAPER_CONFIG_C_ECC_STATUSr_fields,
  52183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52184         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  52185         -1,
  52186         -1,
  52187     },
  52188 #endif /* chips */
  52189 
  52190 #if defined(BCM_56270_A0)
  52191     { /* SOC_REG_INT_LLS_L2_SHAPER_CONFIG_C_ECC_STATUS_BCM56270_A0r */
  52192         soc_block_list[85],
  52193         soc_genreg,
  52194         1,
  52195         0,
  52196         0x200e000,
  52197         0,
  52198         0,
  52199         1,
  52200         soc_LLS_L2_SHAPER_CONFIG_C_ECC_STATUS_BCM56270_A0r_fields,
  52201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52202         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  52203         -1,
  52204         -1,
  52205     },
  52206 #endif /* chips */
  52207 
  52208 #if defined(BCM_56440_A0)
  52209     { /* SOC_REG_INT_LLS_L2_SHAPER_CONFIG_LOWER_C_ECC_STATUSr */
  52210         soc_block_list[85],
  52211         soc_genreg,
  52212         1,
  52213         0,
  52214         0x800a3,
  52215         0,
  52216         0,
  52217         1,
  52218         soc_LLS_L2_SHAPER_CONFIG_LOWER_C_ECC_STATUSr_fields,
  52219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52220         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52221         -1,
  52222         -1,
  52223     },
  52224 #endif /* chips */
  52225 
  52226 #if defined(BCM_56440_B0)
  52227     { /* SOC_REG_INT_LLS_L2_SHAPER_CONFIG_LOWER_C_ECC_STATUS_BCM56440_B0r */
  52228         soc_block_list[85],
  52229         soc_genreg,
  52230         1,
  52231         0,
  52232         0x800ab,
  52233         0,
  52234         0,
  52235         1,
  52236         soc_LLS_L2_SHAPER_CONFIG_LOWER_C_ECC_STATUSr_fields,
  52237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52238         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52239         -1,
  52240         -1,
  52241     },
  52242 #endif /* chips */
  52243 
  52244 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52245     defined(BCM_56450_B1)
  52246     { /* SOC_REG_INT_LLS_L2_SHAPER_CONFIG_LOWER_C_ECC_STATUS_BCM56450_A0r */
  52247         soc_block_list[85],
  52248         soc_genreg,
  52249         1,
  52250         0,
  52251         0x2018500,
  52252         0,
  52253         0,
  52254         1,
  52255         soc_LLS_L2_SHAPER_CONFIG_LOWER_C_ECC_STATUS_BCM56450_A0r_fields,
  52256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52257         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52258         -1,
  52259         -1,
  52260     },
  52261 #endif /* chips */
  52262 
  52263 #if defined(BCM_56440_A0)
  52264     { /* SOC_REG_INT_LLS_L2_SHAPER_CONFIG_UPPER_C_ECC_STATUSr */
  52265         soc_block_list[85],
  52266         soc_genreg,
  52267         1,
  52268         0,
  52269         0x8009f,
  52270         0,
  52271         0,
  52272         1,
  52273         soc_LLS_L2_SHAPER_CONFIG_UPPER_C_ECC_STATUSr_fields,
  52274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52275         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52276         -1,
  52277         -1,
  52278     },
  52279 #endif /* chips */
  52280 
  52281 #if defined(BCM_56440_B0)
  52282     { /* SOC_REG_INT_LLS_L2_SHAPER_CONFIG_UPPER_C_ECC_STATUS_BCM56440_B0r */
  52283         soc_block_list[85],
  52284         soc_genreg,
  52285         1,
  52286         0,
  52287         0x800a7,
  52288         0,
  52289         0,
  52290         1,
  52291         soc_LLS_L2_SHAPER_CONFIG_UPPER_C_ECC_STATUSr_fields,
  52292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52293         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52294         -1,
  52295         -1,
  52296     },
  52297 #endif /* chips */
  52298 
  52299 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52300     defined(BCM_56450_B1)
  52301     { /* SOC_REG_INT_LLS_L2_SHAPER_CONFIG_UPPER_C_ECC_STATUS_BCM56450_A0r */
  52302         soc_block_list[85],
  52303         soc_genreg,
  52304         1,
  52305         0,
  52306         0x2018100,
  52307         0,
  52308         0,
  52309         1,
  52310         soc_LLS_L2_SHAPER_CONFIG_UPPER_C_ECC_STATUS_BCM56450_A0r_fields,
  52311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52312         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52313         -1,
  52314         -1,
  52315     },
  52316 #endif /* chips */
  52317 
  52318 #if defined(BCM_56440_A0)
  52319     { /* SOC_REG_INT_LLS_L2_WERR_NEXT_ECC_STATUSr */
  52320         soc_block_list[85],
  52321         soc_genreg,
  52322         1,
  52323         0,
  52324         0x8009d,
  52325         0,
  52326         0,
  52327         1,
  52328         soc_LLS_L2_WERR_NEXT_ECC_STATUSr_fields,
  52329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52330         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  52331         -1,
  52332         -1,
  52333     },
  52334 #endif /* chips */
  52335 
  52336 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52337     { /* SOC_REG_INT_LLS_L2_WERR_NEXT_ECC_STATUS_BCM56260_A0r */
  52338         soc_block_list[85],
  52339         soc_genreg,
  52340         1,
  52341         0,
  52342         0x200f600,
  52343         0,
  52344         0,
  52345         1,
  52346         soc_LLS_L2_WERR_NEXT_ECC_STATUS_BCM56260_A0r_fields,
  52347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52348         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  52349         -1,
  52350         -1,
  52351     },
  52352 #endif /* chips */
  52353 
  52354 #if defined(BCM_56270_A0)
  52355     { /* SOC_REG_INT_LLS_L2_WERR_NEXT_ECC_STATUS_BCM56270_A0r */
  52356         soc_block_list[85],
  52357         soc_genreg,
  52358         1,
  52359         0,
  52360         0x200dd00,
  52361         0,
  52362         0,
  52363         1,
  52364         soc_LLS_L2_WERR_NEXT_ECC_STATUS_BCM56270_A0r_fields,
  52365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52366         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52367         -1,
  52368         -1,
  52369     },
  52370 #endif /* chips */
  52371 
  52372 #if defined(BCM_56440_B0)
  52373     { /* SOC_REG_INT_LLS_L2_WERR_NEXT_ECC_STATUS_BCM56440_B0r */
  52374         soc_block_list[85],
  52375         soc_genreg,
  52376         1,
  52377         0,
  52378         0x800a5,
  52379         0,
  52380         0,
  52381         1,
  52382         soc_LLS_L2_WERR_NEXT_ECC_STATUSr_fields,
  52383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52384         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  52385         -1,
  52386         -1,
  52387     },
  52388 #endif /* chips */
  52389 
  52390 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52391     defined(BCM_56450_B1)
  52392     { /* SOC_REG_INT_LLS_L2_WERR_NEXT_ECC_STATUS_BCM56450_A0r */
  52393         soc_block_list[85],
  52394         soc_genreg,
  52395         1,
  52396         0,
  52397         0x2017f00,
  52398         0,
  52399         0,
  52400         1,
  52401         soc_LLS_L2_WERR_NEXT_ECC_STATUS_BCM56450_A0r_fields,
  52402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52403         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  52404         -1,
  52405         -1,
  52406     },
  52407 #endif /* chips */
  52408 
  52409 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  52410     { /* SOC_REG_INT_LLS_L2_WERR_NEXT_ECC_STATUS_BCM56640_A0r */
  52411         soc_block_list[4],
  52412         soc_genreg,
  52413         1,
  52414         0,
  52415         0x5a009b00,
  52416         0,
  52417         0,
  52418         1,
  52419         soc_LLS_L2_WERR_NEXT_ECC_STATUS_BCM56640_A0r_fields,
  52420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52421         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52422         -1,
  52423         -1,
  52424     },
  52425 #endif /* chips */
  52426 
  52427 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52428     defined(BCM_56450_B1)
  52429     { /* SOC_REG_INT_LLS_LB_L0_COSr */
  52430         soc_block_list[85],
  52431         soc_genreg,
  52432         1,
  52433         0,
  52434         0x2000f00,
  52435         0,
  52436         0,
  52437         2,
  52438         soc_LLS_LB_L0_COSr_fields,
  52439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52440         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  52441         -1,
  52442         -1,
  52443     },
  52444 #endif /* chips */
  52445 
  52446 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52447     { /* SOC_REG_INT_LLS_LB_L0_COS_BCM56260_A0r */
  52448         soc_block_list[85],
  52449         soc_genreg,
  52450         1,
  52451         0,
  52452         0x2000f00,
  52453         0,
  52454         0,
  52455         2,
  52456         soc_LLS_LB_L0_COS_BCM56560_A0r_fields,
  52457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52458         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  52459         -1,
  52460         -1,
  52461     },
  52462 #endif /* chips */
  52463 
  52464 #if defined(BCM_56270_A0)
  52465     { /* SOC_REG_INT_LLS_LB_L0_COS_BCM56270_A0r */
  52466         soc_block_list[85],
  52467         soc_genreg,
  52468         1,
  52469         0,
  52470         0x2000f00,
  52471         0,
  52472         0,
  52473         2,
  52474         soc_LLS_LB_L0_COS_BCM56270_A0r_fields,
  52475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52476         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  52477         -1,
  52478         -1,
  52479     },
  52480 #endif /* chips */
  52481 
  52482 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  52483     { /* SOC_REG_INT_LLS_LB_L0_COS_BCM56560_A0r */
  52484         soc_block_list[4],
  52485         soc_genreg,
  52486         1,
  52487         0,
  52488         0x62000b00,
  52489         0,
  52490         0,
  52491         2,
  52492         soc_LLS_LB_L0_COS_BCM56560_A0r_fields,
  52493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52494         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  52495         -1,
  52496         -1,
  52497     },
  52498 #endif /* chips */
  52499 
  52500 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52501     defined(BCM_56450_B1)
  52502     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_COUNT_S1r */
  52503         soc_block_list[85],
  52504         soc_genreg,
  52505         1,
  52506         0,
  52507         0x2010600,
  52508         0,
  52509         0,
  52510         2,
  52511         soc_LLS_LINKPHY_CONFIG_COUNT_S1r_fields,
  52512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52513         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  52514         -1,
  52515         -1,
  52516     },
  52517 #endif /* chips */
  52518 
  52519 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52520     defined(BCM_56450_B1)
  52521     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_001_000r */
  52522         soc_block_list[85],
  52523         soc_genreg,
  52524         1,
  52525         0,
  52526         0x2010500,
  52527         0,
  52528         0,
  52529         2,
  52530         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_001_000r_fields,
  52531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52532         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52533         -1,
  52534         -1,
  52535     },
  52536 #endif /* chips */
  52537 
  52538 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52539     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_003_000r */
  52540         soc_block_list[85],
  52541         soc_genreg,
  52542         1,
  52543         0,
  52544         0x2008400,
  52545         0,
  52546         0,
  52547         4,
  52548         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_003_000r_fields,
  52549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52550         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52551         -1,
  52552         -1,
  52553     },
  52554 #endif /* chips */
  52555 
  52556 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52557     defined(BCM_56450_B1)
  52558     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_003_002r */
  52559         soc_block_list[85],
  52560         soc_genreg,
  52561         1,
  52562         0,
  52563         0x2010400,
  52564         0,
  52565         0,
  52566         2,
  52567         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_003_002r_fields,
  52568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52569         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52570         -1,
  52571         -1,
  52572     },
  52573 #endif /* chips */
  52574 
  52575 #if defined(BCM_56270_A0)
  52576     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_003_000_BCM56270_A0r */
  52577         soc_block_list[85],
  52578         soc_genreg,
  52579         1,
  52580         0,
  52581         0x2006c00,
  52582         0,
  52583         0,
  52584         4,
  52585         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_003_000r_fields,
  52586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52587         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52588         -1,
  52589         -1,
  52590     },
  52591 #endif /* chips */
  52592 
  52593 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52594     defined(BCM_56450_B1)
  52595     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_005_004r */
  52596         soc_block_list[85],
  52597         soc_genreg,
  52598         1,
  52599         0,
  52600         0x2010300,
  52601         0,
  52602         0,
  52603         2,
  52604         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_005_004r_fields,
  52605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52606         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52607         -1,
  52608         -1,
  52609     },
  52610 #endif /* chips */
  52611 
  52612 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52613     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_007_004r */
  52614         soc_block_list[85],
  52615         soc_genreg,
  52616         1,
  52617         0,
  52618         0x2008300,
  52619         0,
  52620         0,
  52621         4,
  52622         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_007_004r_fields,
  52623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52624         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52625         -1,
  52626         -1,
  52627     },
  52628 #endif /* chips */
  52629 
  52630 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52631     defined(BCM_56450_B1)
  52632     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_007_006r */
  52633         soc_block_list[85],
  52634         soc_genreg,
  52635         1,
  52636         0,
  52637         0x2010200,
  52638         0,
  52639         0,
  52640         2,
  52641         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_007_006r_fields,
  52642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52643         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52644         -1,
  52645         -1,
  52646     },
  52647 #endif /* chips */
  52648 
  52649 #if defined(BCM_56270_A0)
  52650     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_007_004_BCM56270_A0r */
  52651         soc_block_list[85],
  52652         soc_genreg,
  52653         1,
  52654         0,
  52655         0x2006b00,
  52656         0,
  52657         0,
  52658         4,
  52659         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_007_004r_fields,
  52660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52661         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52662         -1,
  52663         -1,
  52664     },
  52665 #endif /* chips */
  52666 
  52667 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52668     defined(BCM_56450_B1)
  52669     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_009_008r */
  52670         soc_block_list[85],
  52671         soc_genreg,
  52672         1,
  52673         0,
  52674         0x2010100,
  52675         0,
  52676         0,
  52677         2,
  52678         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_009_008r_fields,
  52679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52680         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52681         -1,
  52682         -1,
  52683     },
  52684 #endif /* chips */
  52685 
  52686 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52687     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_011_008r */
  52688         soc_block_list[85],
  52689         soc_genreg,
  52690         1,
  52691         0,
  52692         0x2008200,
  52693         0,
  52694         0,
  52695         4,
  52696         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_011_008r_fields,
  52697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52698         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52699         -1,
  52700         -1,
  52701     },
  52702 #endif /* chips */
  52703 
  52704 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52705     defined(BCM_56450_B1)
  52706     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_011_010r */
  52707         soc_block_list[85],
  52708         soc_genreg,
  52709         1,
  52710         0,
  52711         0x2010000,
  52712         0,
  52713         0,
  52714         2,
  52715         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_011_010r_fields,
  52716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52717         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52718         -1,
  52719         -1,
  52720     },
  52721 #endif /* chips */
  52722 
  52723 #if defined(BCM_56270_A0)
  52724     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_011_008_BCM56270_A0r */
  52725         soc_block_list[85],
  52726         soc_genreg,
  52727         1,
  52728         0,
  52729         0x2006a00,
  52730         0,
  52731         0,
  52732         4,
  52733         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_011_008r_fields,
  52734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52735         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52736         -1,
  52737         -1,
  52738     },
  52739 #endif /* chips */
  52740 
  52741 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52742     defined(BCM_56450_B1)
  52743     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_013_012r */
  52744         soc_block_list[85],
  52745         soc_genreg,
  52746         1,
  52747         0,
  52748         0x200ff00,
  52749         0,
  52750         0,
  52751         2,
  52752         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_013_012r_fields,
  52753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52754         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52755         -1,
  52756         -1,
  52757     },
  52758 #endif /* chips */
  52759 
  52760 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52761     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_015_012r */
  52762         soc_block_list[85],
  52763         soc_genreg,
  52764         1,
  52765         0,
  52766         0x2008100,
  52767         0,
  52768         0,
  52769         4,
  52770         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_015_012r_fields,
  52771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52772         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52773         -1,
  52774         -1,
  52775     },
  52776 #endif /* chips */
  52777 
  52778 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52779     defined(BCM_56450_B1)
  52780     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_015_014r */
  52781         soc_block_list[85],
  52782         soc_genreg,
  52783         1,
  52784         0,
  52785         0x200fe00,
  52786         0,
  52787         0,
  52788         2,
  52789         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_015_014r_fields,
  52790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52791         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52792         -1,
  52793         -1,
  52794     },
  52795 #endif /* chips */
  52796 
  52797 #if defined(BCM_56270_A0)
  52798     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_015_012_BCM56270_A0r */
  52799         soc_block_list[85],
  52800         soc_genreg,
  52801         1,
  52802         0,
  52803         0x2006900,
  52804         0,
  52805         0,
  52806         4,
  52807         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_015_012r_fields,
  52808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52809         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52810         -1,
  52811         -1,
  52812     },
  52813 #endif /* chips */
  52814 
  52815 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52816     defined(BCM_56450_B1)
  52817     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_017_016r */
  52818         soc_block_list[85],
  52819         soc_genreg,
  52820         1,
  52821         0,
  52822         0x200fd00,
  52823         0,
  52824         0,
  52825         2,
  52826         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_017_016r_fields,
  52827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52828         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52829         -1,
  52830         -1,
  52831     },
  52832 #endif /* chips */
  52833 
  52834 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52835     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_019_016r */
  52836         soc_block_list[85],
  52837         soc_genreg,
  52838         1,
  52839         0,
  52840         0x2008000,
  52841         0,
  52842         0,
  52843         4,
  52844         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_019_016r_fields,
  52845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52846         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52847         -1,
  52848         -1,
  52849     },
  52850 #endif /* chips */
  52851 
  52852 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52853     defined(BCM_56450_B1)
  52854     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_019_018r */
  52855         soc_block_list[85],
  52856         soc_genreg,
  52857         1,
  52858         0,
  52859         0x200fc00,
  52860         0,
  52861         0,
  52862         2,
  52863         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_019_018r_fields,
  52864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52865         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52866         -1,
  52867         -1,
  52868     },
  52869 #endif /* chips */
  52870 
  52871 #if defined(BCM_56270_A0)
  52872     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_019_016_BCM56270_A0r */
  52873         soc_block_list[85],
  52874         soc_genreg,
  52875         1,
  52876         0,
  52877         0x2006800,
  52878         0,
  52879         0,
  52880         4,
  52881         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_019_016r_fields,
  52882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52883         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52884         -1,
  52885         -1,
  52886     },
  52887 #endif /* chips */
  52888 
  52889 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52890     defined(BCM_56450_B1)
  52891     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_021_020r */
  52892         soc_block_list[85],
  52893         soc_genreg,
  52894         1,
  52895         0,
  52896         0x200fb00,
  52897         0,
  52898         0,
  52899         2,
  52900         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_021_020r_fields,
  52901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52902         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52903         -1,
  52904         -1,
  52905     },
  52906 #endif /* chips */
  52907 
  52908 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52909     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_023_020r */
  52910         soc_block_list[85],
  52911         soc_genreg,
  52912         1,
  52913         0,
  52914         0x2007f00,
  52915         0,
  52916         0,
  52917         4,
  52918         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_023_020r_fields,
  52919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52920         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52921         -1,
  52922         -1,
  52923     },
  52924 #endif /* chips */
  52925 
  52926 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52927     defined(BCM_56450_B1)
  52928     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_023_022r */
  52929         soc_block_list[85],
  52930         soc_genreg,
  52931         1,
  52932         0,
  52933         0x200fa00,
  52934         0,
  52935         0,
  52936         2,
  52937         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_023_022r_fields,
  52938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52939         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52940         -1,
  52941         -1,
  52942     },
  52943 #endif /* chips */
  52944 
  52945 #if defined(BCM_56270_A0)
  52946     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_023_020_BCM56270_A0r */
  52947         soc_block_list[85],
  52948         soc_genreg,
  52949         1,
  52950         0,
  52951         0x2006700,
  52952         0,
  52953         0,
  52954         4,
  52955         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_023_020r_fields,
  52956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52957         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52958         -1,
  52959         -1,
  52960     },
  52961 #endif /* chips */
  52962 
  52963 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  52964     defined(BCM_56450_B1)
  52965     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_025_024r */
  52966         soc_block_list[85],
  52967         soc_genreg,
  52968         1,
  52969         0,
  52970         0x200f900,
  52971         0,
  52972         0,
  52973         2,
  52974         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_025_024r_fields,
  52975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52976         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  52977         -1,
  52978         -1,
  52979     },
  52980 #endif /* chips */
  52981 
  52982 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52983     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_027_024r */
  52984         soc_block_list[85],
  52985         soc_genreg,
  52986         1,
  52987         0,
  52988         0x2007e00,
  52989         0,
  52990         0,
  52991         4,
  52992         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_027_024r_fields,
  52993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52994         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52995         -1,
  52996         -1,
  52997     },
  52998 #endif /* chips */
  52999 
  53000 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53001     defined(BCM_56450_B1)
  53002     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_027_026r */
  53003         soc_block_list[85],
  53004         soc_genreg,
  53005         1,
  53006         0,
  53007         0x200f800,
  53008         0,
  53009         0,
  53010         2,
  53011         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_027_026r_fields,
  53012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53013         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53014         -1,
  53015         -1,
  53016     },
  53017 #endif /* chips */
  53018 
  53019 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53020     defined(BCM_56450_B1)
  53021     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_029_028r */
  53022         soc_block_list[85],
  53023         soc_genreg,
  53024         1,
  53025         0,
  53026         0x200f700,
  53027         0,
  53028         0,
  53029         2,
  53030         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_029_028r_fields,
  53031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53032         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53033         -1,
  53034         -1,
  53035     },
  53036 #endif /* chips */
  53037 
  53038 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  53039     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_031_028r */
  53040         soc_block_list[85],
  53041         soc_genreg,
  53042         1,
  53043         0,
  53044         0x2007d00,
  53045         0,
  53046         0,
  53047         4,
  53048         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_031_028r_fields,
  53049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53050         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  53051         -1,
  53052         -1,
  53053     },
  53054 #endif /* chips */
  53055 
  53056 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53057     defined(BCM_56450_B1)
  53058     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_031_030r */
  53059         soc_block_list[85],
  53060         soc_genreg,
  53061         1,
  53062         0,
  53063         0x200f600,
  53064         0,
  53065         0,
  53066         2,
  53067         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_031_030r_fields,
  53068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53069         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53070         -1,
  53071         -1,
  53072     },
  53073 #endif /* chips */
  53074 
  53075 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53076     defined(BCM_56450_B1)
  53077     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_033_032r */
  53078         soc_block_list[85],
  53079         soc_genreg,
  53080         1,
  53081         0,
  53082         0x200f500,
  53083         0,
  53084         0,
  53085         2,
  53086         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_033_032r_fields,
  53087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53088         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53089         -1,
  53090         -1,
  53091     },
  53092 #endif /* chips */
  53093 
  53094 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53095     defined(BCM_56450_B1)
  53096     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_035_034r */
  53097         soc_block_list[85],
  53098         soc_genreg,
  53099         1,
  53100         0,
  53101         0x200f400,
  53102         0,
  53103         0,
  53104         2,
  53105         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_035_034r_fields,
  53106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53107         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53108         -1,
  53109         -1,
  53110     },
  53111 #endif /* chips */
  53112 
  53113 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53114     defined(BCM_56450_B1)
  53115     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_037_036r */
  53116         soc_block_list[85],
  53117         soc_genreg,
  53118         1,
  53119         0,
  53120         0x200f300,
  53121         0,
  53122         0,
  53123         2,
  53124         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_037_036r_fields,
  53125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53126         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53127         -1,
  53128         -1,
  53129     },
  53130 #endif /* chips */
  53131 
  53132 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53133     defined(BCM_56450_B1)
  53134     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_039_038r */
  53135         soc_block_list[85],
  53136         soc_genreg,
  53137         1,
  53138         0,
  53139         0x200f200,
  53140         0,
  53141         0,
  53142         2,
  53143         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_039_038r_fields,
  53144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53145         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53146         -1,
  53147         -1,
  53148     },
  53149 #endif /* chips */
  53150 
  53151 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53152     defined(BCM_56450_B1)
  53153     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_041_040r */
  53154         soc_block_list[85],
  53155         soc_genreg,
  53156         1,
  53157         0,
  53158         0x200f100,
  53159         0,
  53160         0,
  53161         2,
  53162         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_041_040r_fields,
  53163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53164         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53165         -1,
  53166         -1,
  53167     },
  53168 #endif /* chips */
  53169 
  53170 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53171     defined(BCM_56450_B1)
  53172     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_043_042r */
  53173         soc_block_list[85],
  53174         soc_genreg,
  53175         1,
  53176         0,
  53177         0x200f000,
  53178         0,
  53179         0,
  53180         2,
  53181         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_043_042r_fields,
  53182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53183         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53184         -1,
  53185         -1,
  53186     },
  53187 #endif /* chips */
  53188 
  53189 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53190     defined(BCM_56450_B1)
  53191     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_045_044r */
  53192         soc_block_list[85],
  53193         soc_genreg,
  53194         1,
  53195         0,
  53196         0x200ef00,
  53197         0,
  53198         0,
  53199         2,
  53200         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_045_044r_fields,
  53201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53202         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53203         -1,
  53204         -1,
  53205     },
  53206 #endif /* chips */
  53207 
  53208 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53209     defined(BCM_56450_B1)
  53210     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_047_046r */
  53211         soc_block_list[85],
  53212         soc_genreg,
  53213         1,
  53214         0,
  53215         0x200ee00,
  53216         0,
  53217         0,
  53218         2,
  53219         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_047_046r_fields,
  53220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53221         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53222         -1,
  53223         -1,
  53224     },
  53225 #endif /* chips */
  53226 
  53227 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53228     defined(BCM_56450_B1)
  53229     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_049_048r */
  53230         soc_block_list[85],
  53231         soc_genreg,
  53232         1,
  53233         0,
  53234         0x200ed00,
  53235         0,
  53236         0,
  53237         2,
  53238         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_049_048r_fields,
  53239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53240         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53241         -1,
  53242         -1,
  53243     },
  53244 #endif /* chips */
  53245 
  53246 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53247     defined(BCM_56450_B1)
  53248     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_051_050r */
  53249         soc_block_list[85],
  53250         soc_genreg,
  53251         1,
  53252         0,
  53253         0x200ec00,
  53254         0,
  53255         0,
  53256         2,
  53257         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_051_050r_fields,
  53258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53259         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53260         -1,
  53261         -1,
  53262     },
  53263 #endif /* chips */
  53264 
  53265 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53266     defined(BCM_56450_B1)
  53267     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_053_052r */
  53268         soc_block_list[85],
  53269         soc_genreg,
  53270         1,
  53271         0,
  53272         0x200eb00,
  53273         0,
  53274         0,
  53275         2,
  53276         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_053_052r_fields,
  53277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53278         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53279         -1,
  53280         -1,
  53281     },
  53282 #endif /* chips */
  53283 
  53284 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53285     defined(BCM_56450_B1)
  53286     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_055_054r */
  53287         soc_block_list[85],
  53288         soc_genreg,
  53289         1,
  53290         0,
  53291         0x200ea00,
  53292         0,
  53293         0,
  53294         2,
  53295         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_055_054r_fields,
  53296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53297         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53298         -1,
  53299         -1,
  53300     },
  53301 #endif /* chips */
  53302 
  53303 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53304     defined(BCM_56450_B1)
  53305     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_057_056r */
  53306         soc_block_list[85],
  53307         soc_genreg,
  53308         1,
  53309         0,
  53310         0x200e900,
  53311         0,
  53312         0,
  53313         2,
  53314         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_057_056r_fields,
  53315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53316         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53317         -1,
  53318         -1,
  53319     },
  53320 #endif /* chips */
  53321 
  53322 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53323     defined(BCM_56450_B1)
  53324     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_059_058r */
  53325         soc_block_list[85],
  53326         soc_genreg,
  53327         1,
  53328         0,
  53329         0x200e800,
  53330         0,
  53331         0,
  53332         2,
  53333         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_059_058r_fields,
  53334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53335         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53336         -1,
  53337         -1,
  53338     },
  53339 #endif /* chips */
  53340 
  53341 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53342     defined(BCM_56450_B1)
  53343     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_061_060r */
  53344         soc_block_list[85],
  53345         soc_genreg,
  53346         1,
  53347         0,
  53348         0x200e700,
  53349         0,
  53350         0,
  53351         2,
  53352         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_061_060r_fields,
  53353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53354         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53355         -1,
  53356         -1,
  53357     },
  53358 #endif /* chips */
  53359 
  53360 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53361     defined(BCM_56450_B1)
  53362     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_063_062r */
  53363         soc_block_list[85],
  53364         soc_genreg,
  53365         1,
  53366         0,
  53367         0x200e600,
  53368         0,
  53369         0,
  53370         2,
  53371         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_063_062r_fields,
  53372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53373         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53374         -1,
  53375         -1,
  53376     },
  53377 #endif /* chips */
  53378 
  53379 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53380     defined(BCM_56450_B1)
  53381     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_065_064r */
  53382         soc_block_list[85],
  53383         soc_genreg,
  53384         1,
  53385         0,
  53386         0x200e500,
  53387         0,
  53388         0,
  53389         2,
  53390         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_065_064r_fields,
  53391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53392         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53393         -1,
  53394         -1,
  53395     },
  53396 #endif /* chips */
  53397 
  53398 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53399     defined(BCM_56450_B1)
  53400     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_067_066r */
  53401         soc_block_list[85],
  53402         soc_genreg,
  53403         1,
  53404         0,
  53405         0x200e400,
  53406         0,
  53407         0,
  53408         2,
  53409         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_067_066r_fields,
  53410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53411         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53412         -1,
  53413         -1,
  53414     },
  53415 #endif /* chips */
  53416 
  53417 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53418     defined(BCM_56450_B1)
  53419     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_069_068r */
  53420         soc_block_list[85],
  53421         soc_genreg,
  53422         1,
  53423         0,
  53424         0x200e300,
  53425         0,
  53426         0,
  53427         2,
  53428         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_069_068r_fields,
  53429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53430         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53431         -1,
  53432         -1,
  53433     },
  53434 #endif /* chips */
  53435 
  53436 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53437     defined(BCM_56450_B1)
  53438     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_071_070r */
  53439         soc_block_list[85],
  53440         soc_genreg,
  53441         1,
  53442         0,
  53443         0x200e200,
  53444         0,
  53445         0,
  53446         2,
  53447         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_071_070r_fields,
  53448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53449         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53450         -1,
  53451         -1,
  53452     },
  53453 #endif /* chips */
  53454 
  53455 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53456     defined(BCM_56450_B1)
  53457     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_073_072r */
  53458         soc_block_list[85],
  53459         soc_genreg,
  53460         1,
  53461         0,
  53462         0x200e100,
  53463         0,
  53464         0,
  53465         2,
  53466         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_073_072r_fields,
  53467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53468         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53469         -1,
  53470         -1,
  53471     },
  53472 #endif /* chips */
  53473 
  53474 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53475     defined(BCM_56450_B1)
  53476     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_075_074r */
  53477         soc_block_list[85],
  53478         soc_genreg,
  53479         1,
  53480         0,
  53481         0x200e000,
  53482         0,
  53483         0,
  53484         2,
  53485         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_075_074r_fields,
  53486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53487         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53488         -1,
  53489         -1,
  53490     },
  53491 #endif /* chips */
  53492 
  53493 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53494     defined(BCM_56450_B1)
  53495     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_077_076r */
  53496         soc_block_list[85],
  53497         soc_genreg,
  53498         1,
  53499         0,
  53500         0x200df00,
  53501         0,
  53502         0,
  53503         2,
  53504         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_077_076r_fields,
  53505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53506         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53507         -1,
  53508         -1,
  53509     },
  53510 #endif /* chips */
  53511 
  53512 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53513     defined(BCM_56450_B1)
  53514     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_079_078r */
  53515         soc_block_list[85],
  53516         soc_genreg,
  53517         1,
  53518         0,
  53519         0x200de00,
  53520         0,
  53521         0,
  53522         2,
  53523         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_079_078r_fields,
  53524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53525         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53526         -1,
  53527         -1,
  53528     },
  53529 #endif /* chips */
  53530 
  53531 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53532     defined(BCM_56450_B1)
  53533     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_081_080r */
  53534         soc_block_list[85],
  53535         soc_genreg,
  53536         1,
  53537         0,
  53538         0x200dd00,
  53539         0,
  53540         0,
  53541         2,
  53542         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_081_080r_fields,
  53543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53544         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53545         -1,
  53546         -1,
  53547     },
  53548 #endif /* chips */
  53549 
  53550 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53551     defined(BCM_56450_B1)
  53552     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_083_082r */
  53553         soc_block_list[85],
  53554         soc_genreg,
  53555         1,
  53556         0,
  53557         0x200dc00,
  53558         0,
  53559         0,
  53560         2,
  53561         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_083_082r_fields,
  53562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53563         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53564         -1,
  53565         -1,
  53566     },
  53567 #endif /* chips */
  53568 
  53569 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53570     defined(BCM_56450_B1)
  53571     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_085_084r */
  53572         soc_block_list[85],
  53573         soc_genreg,
  53574         1,
  53575         0,
  53576         0x200db00,
  53577         0,
  53578         0,
  53579         2,
  53580         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_085_084r_fields,
  53581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53582         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53583         -1,
  53584         -1,
  53585     },
  53586 #endif /* chips */
  53587 
  53588 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53589     defined(BCM_56450_B1)
  53590     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_087_086r */
  53591         soc_block_list[85],
  53592         soc_genreg,
  53593         1,
  53594         0,
  53595         0x200da00,
  53596         0,
  53597         0,
  53598         2,
  53599         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_087_086r_fields,
  53600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53601         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53602         -1,
  53603         -1,
  53604     },
  53605 #endif /* chips */
  53606 
  53607 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53608     defined(BCM_56450_B1)
  53609     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_089_088r */
  53610         soc_block_list[85],
  53611         soc_genreg,
  53612         1,
  53613         0,
  53614         0x200d900,
  53615         0,
  53616         0,
  53617         2,
  53618         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_089_088r_fields,
  53619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53620         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53621         -1,
  53622         -1,
  53623     },
  53624 #endif /* chips */
  53625 
  53626 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53627     defined(BCM_56450_B1)
  53628     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_091_090r */
  53629         soc_block_list[85],
  53630         soc_genreg,
  53631         1,
  53632         0,
  53633         0x200d800,
  53634         0,
  53635         0,
  53636         2,
  53637         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_091_090r_fields,
  53638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53639         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53640         -1,
  53641         -1,
  53642     },
  53643 #endif /* chips */
  53644 
  53645 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53646     defined(BCM_56450_B1)
  53647     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_093_092r */
  53648         soc_block_list[85],
  53649         soc_genreg,
  53650         1,
  53651         0,
  53652         0x200d700,
  53653         0,
  53654         0,
  53655         2,
  53656         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_093_092r_fields,
  53657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53658         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53659         -1,
  53660         -1,
  53661     },
  53662 #endif /* chips */
  53663 
  53664 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53665     defined(BCM_56450_B1)
  53666     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_095_094r */
  53667         soc_block_list[85],
  53668         soc_genreg,
  53669         1,
  53670         0,
  53671         0x200d600,
  53672         0,
  53673         0,
  53674         2,
  53675         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_095_094r_fields,
  53676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53677         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53678         -1,
  53679         -1,
  53680     },
  53681 #endif /* chips */
  53682 
  53683 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53684     defined(BCM_56450_B1)
  53685     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_097_096r */
  53686         soc_block_list[85],
  53687         soc_genreg,
  53688         1,
  53689         0,
  53690         0x200d500,
  53691         0,
  53692         0,
  53693         2,
  53694         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_097_096r_fields,
  53695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53696         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53697         -1,
  53698         -1,
  53699     },
  53700 #endif /* chips */
  53701 
  53702 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53703     defined(BCM_56450_B1)
  53704     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_099_098r */
  53705         soc_block_list[85],
  53706         soc_genreg,
  53707         1,
  53708         0,
  53709         0x200d400,
  53710         0,
  53711         0,
  53712         2,
  53713         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_099_098r_fields,
  53714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53715         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53716         -1,
  53717         -1,
  53718     },
  53719 #endif /* chips */
  53720 
  53721 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53722     defined(BCM_56450_B1)
  53723     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_101_100r */
  53724         soc_block_list[85],
  53725         soc_genreg,
  53726         1,
  53727         0,
  53728         0x200d300,
  53729         0,
  53730         0,
  53731         2,
  53732         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_101_100r_fields,
  53733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53734         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53735         -1,
  53736         -1,
  53737     },
  53738 #endif /* chips */
  53739 
  53740 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53741     defined(BCM_56450_B1)
  53742     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_103_102r */
  53743         soc_block_list[85],
  53744         soc_genreg,
  53745         1,
  53746         0,
  53747         0x200d200,
  53748         0,
  53749         0,
  53750         2,
  53751         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_103_102r_fields,
  53752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53753         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53754         -1,
  53755         -1,
  53756     },
  53757 #endif /* chips */
  53758 
  53759 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53760     defined(BCM_56450_B1)
  53761     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_105_104r */
  53762         soc_block_list[85],
  53763         soc_genreg,
  53764         1,
  53765         0,
  53766         0x200d100,
  53767         0,
  53768         0,
  53769         2,
  53770         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_105_104r_fields,
  53771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53772         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53773         -1,
  53774         -1,
  53775     },
  53776 #endif /* chips */
  53777 
  53778 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53779     defined(BCM_56450_B1)
  53780     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_107_106r */
  53781         soc_block_list[85],
  53782         soc_genreg,
  53783         1,
  53784         0,
  53785         0x200d000,
  53786         0,
  53787         0,
  53788         2,
  53789         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_107_106r_fields,
  53790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53791         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53792         -1,
  53793         -1,
  53794     },
  53795 #endif /* chips */
  53796 
  53797 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53798     defined(BCM_56450_B1)
  53799     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_109_108r */
  53800         soc_block_list[85],
  53801         soc_genreg,
  53802         1,
  53803         0,
  53804         0x200cf00,
  53805         0,
  53806         0,
  53807         2,
  53808         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_109_108r_fields,
  53809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53810         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53811         -1,
  53812         -1,
  53813     },
  53814 #endif /* chips */
  53815 
  53816 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53817     defined(BCM_56450_B1)
  53818     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_111_110r */
  53819         soc_block_list[85],
  53820         soc_genreg,
  53821         1,
  53822         0,
  53823         0x200ce00,
  53824         0,
  53825         0,
  53826         2,
  53827         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_111_110r_fields,
  53828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53829         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53830         -1,
  53831         -1,
  53832     },
  53833 #endif /* chips */
  53834 
  53835 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53836     defined(BCM_56450_B1)
  53837     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_113_112r */
  53838         soc_block_list[85],
  53839         soc_genreg,
  53840         1,
  53841         0,
  53842         0x200cd00,
  53843         0,
  53844         0,
  53845         2,
  53846         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_113_112r_fields,
  53847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53848         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53849         -1,
  53850         -1,
  53851     },
  53852 #endif /* chips */
  53853 
  53854 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53855     defined(BCM_56450_B1)
  53856     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_115_114r */
  53857         soc_block_list[85],
  53858         soc_genreg,
  53859         1,
  53860         0,
  53861         0x200cc00,
  53862         0,
  53863         0,
  53864         2,
  53865         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_115_114r_fields,
  53866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53867         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53868         -1,
  53869         -1,
  53870     },
  53871 #endif /* chips */
  53872 
  53873 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53874     defined(BCM_56450_B1)
  53875     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_117_116r */
  53876         soc_block_list[85],
  53877         soc_genreg,
  53878         1,
  53879         0,
  53880         0x200cb00,
  53881         0,
  53882         0,
  53883         2,
  53884         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_117_116r_fields,
  53885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53886         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53887         -1,
  53888         -1,
  53889     },
  53890 #endif /* chips */
  53891 
  53892 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53893     defined(BCM_56450_B1)
  53894     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_119_118r */
  53895         soc_block_list[85],
  53896         soc_genreg,
  53897         1,
  53898         0,
  53899         0x200ca00,
  53900         0,
  53901         0,
  53902         2,
  53903         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_119_118r_fields,
  53904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53905         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53906         -1,
  53907         -1,
  53908     },
  53909 #endif /* chips */
  53910 
  53911 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53912     defined(BCM_56450_B1)
  53913     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_121_120r */
  53914         soc_block_list[85],
  53915         soc_genreg,
  53916         1,
  53917         0,
  53918         0x200c900,
  53919         0,
  53920         0,
  53921         2,
  53922         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_121_120r_fields,
  53923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53924         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53925         -1,
  53926         -1,
  53927     },
  53928 #endif /* chips */
  53929 
  53930 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53931     defined(BCM_56450_B1)
  53932     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_123_122r */
  53933         soc_block_list[85],
  53934         soc_genreg,
  53935         1,
  53936         0,
  53937         0x200c800,
  53938         0,
  53939         0,
  53940         2,
  53941         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_123_122r_fields,
  53942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53943         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53944         -1,
  53945         -1,
  53946     },
  53947 #endif /* chips */
  53948 
  53949 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53950     defined(BCM_56450_B1)
  53951     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_125_124r */
  53952         soc_block_list[85],
  53953         soc_genreg,
  53954         1,
  53955         0,
  53956         0x200c700,
  53957         0,
  53958         0,
  53959         2,
  53960         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_125_124r_fields,
  53961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53962         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53963         -1,
  53964         -1,
  53965     },
  53966 #endif /* chips */
  53967 
  53968 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53969     defined(BCM_56450_B1)
  53970     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_127_126r */
  53971         soc_block_list[85],
  53972         soc_genreg,
  53973         1,
  53974         0,
  53975         0x200c600,
  53976         0,
  53977         0,
  53978         2,
  53979         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_127_126r_fields,
  53980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53981         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  53982         -1,
  53983         -1,
  53984     },
  53985 #endif /* chips */
  53986 
  53987 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  53988     defined(BCM_56450_B1)
  53989     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_129_128r */
  53990         soc_block_list[85],
  53991         soc_genreg,
  53992         1,
  53993         0,
  53994         0x200c500,
  53995         0,
  53996         0,
  53997         2,
  53998         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_129_128r_fields,
  53999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54000         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54001         -1,
  54002         -1,
  54003     },
  54004 #endif /* chips */
  54005 
  54006 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54007     defined(BCM_56450_B1)
  54008     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_131_130r */
  54009         soc_block_list[85],
  54010         soc_genreg,
  54011         1,
  54012         0,
  54013         0x200c400,
  54014         0,
  54015         0,
  54016         2,
  54017         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_131_130r_fields,
  54018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54019         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54020         -1,
  54021         -1,
  54022     },
  54023 #endif /* chips */
  54024 
  54025 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54026     defined(BCM_56450_B1)
  54027     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_133_132r */
  54028         soc_block_list[85],
  54029         soc_genreg,
  54030         1,
  54031         0,
  54032         0x200c300,
  54033         0,
  54034         0,
  54035         2,
  54036         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_133_132r_fields,
  54037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54038         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54039         -1,
  54040         -1,
  54041     },
  54042 #endif /* chips */
  54043 
  54044 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54045     defined(BCM_56450_B1)
  54046     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_135_134r */
  54047         soc_block_list[85],
  54048         soc_genreg,
  54049         1,
  54050         0,
  54051         0x200c200,
  54052         0,
  54053         0,
  54054         2,
  54055         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_135_134r_fields,
  54056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54057         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54058         -1,
  54059         -1,
  54060     },
  54061 #endif /* chips */
  54062 
  54063 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54064     defined(BCM_56450_B1)
  54065     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_137_136r */
  54066         soc_block_list[85],
  54067         soc_genreg,
  54068         1,
  54069         0,
  54070         0x200c100,
  54071         0,
  54072         0,
  54073         2,
  54074         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_137_136r_fields,
  54075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54076         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54077         -1,
  54078         -1,
  54079     },
  54080 #endif /* chips */
  54081 
  54082 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54083     defined(BCM_56450_B1)
  54084     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_139_138r */
  54085         soc_block_list[85],
  54086         soc_genreg,
  54087         1,
  54088         0,
  54089         0x200c000,
  54090         0,
  54091         0,
  54092         2,
  54093         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_139_138r_fields,
  54094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54095         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54096         -1,
  54097         -1,
  54098     },
  54099 #endif /* chips */
  54100 
  54101 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54102     defined(BCM_56450_B1)
  54103     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_141_140r */
  54104         soc_block_list[85],
  54105         soc_genreg,
  54106         1,
  54107         0,
  54108         0x200bf00,
  54109         0,
  54110         0,
  54111         2,
  54112         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_141_140r_fields,
  54113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54114         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54115         -1,
  54116         -1,
  54117     },
  54118 #endif /* chips */
  54119 
  54120 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54121     defined(BCM_56450_B1)
  54122     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_143_142r */
  54123         soc_block_list[85],
  54124         soc_genreg,
  54125         1,
  54126         0,
  54127         0x200be00,
  54128         0,
  54129         0,
  54130         2,
  54131         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_143_142r_fields,
  54132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54133         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54134         -1,
  54135         -1,
  54136     },
  54137 #endif /* chips */
  54138 
  54139 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54140     defined(BCM_56450_B1)
  54141     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_145_144r */
  54142         soc_block_list[85],
  54143         soc_genreg,
  54144         1,
  54145         0,
  54146         0x200bd00,
  54147         0,
  54148         0,
  54149         2,
  54150         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_145_144r_fields,
  54151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54152         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54153         -1,
  54154         -1,
  54155     },
  54156 #endif /* chips */
  54157 
  54158 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54159     defined(BCM_56450_B1)
  54160     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_147_146r */
  54161         soc_block_list[85],
  54162         soc_genreg,
  54163         1,
  54164         0,
  54165         0x200bc00,
  54166         0,
  54167         0,
  54168         2,
  54169         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_147_146r_fields,
  54170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54171         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54172         -1,
  54173         -1,
  54174     },
  54175 #endif /* chips */
  54176 
  54177 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54178     defined(BCM_56450_B1)
  54179     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_149_148r */
  54180         soc_block_list[85],
  54181         soc_genreg,
  54182         1,
  54183         0,
  54184         0x200bb00,
  54185         0,
  54186         0,
  54187         2,
  54188         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_149_148r_fields,
  54189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54190         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54191         -1,
  54192         -1,
  54193     },
  54194 #endif /* chips */
  54195 
  54196 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54197     defined(BCM_56450_B1)
  54198     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_151_150r */
  54199         soc_block_list[85],
  54200         soc_genreg,
  54201         1,
  54202         0,
  54203         0x200ba00,
  54204         0,
  54205         0,
  54206         2,
  54207         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_151_150r_fields,
  54208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54209         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54210         -1,
  54211         -1,
  54212     },
  54213 #endif /* chips */
  54214 
  54215 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54216     defined(BCM_56450_B1)
  54217     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_153_152r */
  54218         soc_block_list[85],
  54219         soc_genreg,
  54220         1,
  54221         0,
  54222         0x200b900,
  54223         0,
  54224         0,
  54225         2,
  54226         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_153_152r_fields,
  54227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54228         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54229         -1,
  54230         -1,
  54231     },
  54232 #endif /* chips */
  54233 
  54234 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54235     defined(BCM_56450_B1)
  54236     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_155_154r */
  54237         soc_block_list[85],
  54238         soc_genreg,
  54239         1,
  54240         0,
  54241         0x200b800,
  54242         0,
  54243         0,
  54244         2,
  54245         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_155_154r_fields,
  54246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54247         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54248         -1,
  54249         -1,
  54250     },
  54251 #endif /* chips */
  54252 
  54253 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54254     defined(BCM_56450_B1)
  54255     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_157_156r */
  54256         soc_block_list[85],
  54257         soc_genreg,
  54258         1,
  54259         0,
  54260         0x200b700,
  54261         0,
  54262         0,
  54263         2,
  54264         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_157_156r_fields,
  54265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54266         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54267         -1,
  54268         -1,
  54269     },
  54270 #endif /* chips */
  54271 
  54272 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54273     defined(BCM_56450_B1)
  54274     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_159_158r */
  54275         soc_block_list[85],
  54276         soc_genreg,
  54277         1,
  54278         0,
  54279         0x200b600,
  54280         0,
  54281         0,
  54282         2,
  54283         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_159_158r_fields,
  54284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54285         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54286         -1,
  54287         -1,
  54288     },
  54289 #endif /* chips */
  54290 
  54291 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54292     defined(BCM_56450_B1)
  54293     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_161_160r */
  54294         soc_block_list[85],
  54295         soc_genreg,
  54296         1,
  54297         0,
  54298         0x200b500,
  54299         0,
  54300         0,
  54301         2,
  54302         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_161_160r_fields,
  54303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54304         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54305         -1,
  54306         -1,
  54307     },
  54308 #endif /* chips */
  54309 
  54310 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54311     defined(BCM_56450_B1)
  54312     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_163_162r */
  54313         soc_block_list[85],
  54314         soc_genreg,
  54315         1,
  54316         0,
  54317         0x200b400,
  54318         0,
  54319         0,
  54320         2,
  54321         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_163_162r_fields,
  54322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54323         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54324         -1,
  54325         -1,
  54326     },
  54327 #endif /* chips */
  54328 
  54329 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54330     defined(BCM_56450_B1)
  54331     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_165_164r */
  54332         soc_block_list[85],
  54333         soc_genreg,
  54334         1,
  54335         0,
  54336         0x200b300,
  54337         0,
  54338         0,
  54339         2,
  54340         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_165_164r_fields,
  54341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54342         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54343         -1,
  54344         -1,
  54345     },
  54346 #endif /* chips */
  54347 
  54348 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54349     defined(BCM_56450_B1)
  54350     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_167_166r */
  54351         soc_block_list[85],
  54352         soc_genreg,
  54353         1,
  54354         0,
  54355         0x200b200,
  54356         0,
  54357         0,
  54358         2,
  54359         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_167_166r_fields,
  54360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54361         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54362         -1,
  54363         -1,
  54364     },
  54365 #endif /* chips */
  54366 
  54367 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54368     defined(BCM_56450_B1)
  54369     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_169_168r */
  54370         soc_block_list[85],
  54371         soc_genreg,
  54372         1,
  54373         0,
  54374         0x200b100,
  54375         0,
  54376         0,
  54377         2,
  54378         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_169_168r_fields,
  54379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54380         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54381         -1,
  54382         -1,
  54383     },
  54384 #endif /* chips */
  54385 
  54386 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54387     defined(BCM_56450_B1)
  54388     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_171_170r */
  54389         soc_block_list[85],
  54390         soc_genreg,
  54391         1,
  54392         0,
  54393         0x200b000,
  54394         0,
  54395         0,
  54396         2,
  54397         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_171_170r_fields,
  54398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54399         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54400         -1,
  54401         -1,
  54402     },
  54403 #endif /* chips */
  54404 
  54405 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54406     defined(BCM_56450_B1)
  54407     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_173_172r */
  54408         soc_block_list[85],
  54409         soc_genreg,
  54410         1,
  54411         0,
  54412         0x200af00,
  54413         0,
  54414         0,
  54415         2,
  54416         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_173_172r_fields,
  54417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54418         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54419         -1,
  54420         -1,
  54421     },
  54422 #endif /* chips */
  54423 
  54424 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54425     defined(BCM_56450_B1)
  54426     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_175_174r */
  54427         soc_block_list[85],
  54428         soc_genreg,
  54429         1,
  54430         0,
  54431         0x200ae00,
  54432         0,
  54433         0,
  54434         2,
  54435         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_175_174r_fields,
  54436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54437         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54438         -1,
  54439         -1,
  54440     },
  54441 #endif /* chips */
  54442 
  54443 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54444     defined(BCM_56450_B1)
  54445     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_177_176r */
  54446         soc_block_list[85],
  54447         soc_genreg,
  54448         1,
  54449         0,
  54450         0x200ad00,
  54451         0,
  54452         0,
  54453         2,
  54454         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_177_176r_fields,
  54455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54456         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54457         -1,
  54458         -1,
  54459     },
  54460 #endif /* chips */
  54461 
  54462 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54463     defined(BCM_56450_B1)
  54464     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_179_178r */
  54465         soc_block_list[85],
  54466         soc_genreg,
  54467         1,
  54468         0,
  54469         0x200ac00,
  54470         0,
  54471         0,
  54472         2,
  54473         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_179_178r_fields,
  54474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54475         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54476         -1,
  54477         -1,
  54478     },
  54479 #endif /* chips */
  54480 
  54481 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54482     defined(BCM_56450_B1)
  54483     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_181_180r */
  54484         soc_block_list[85],
  54485         soc_genreg,
  54486         1,
  54487         0,
  54488         0x200ab00,
  54489         0,
  54490         0,
  54491         2,
  54492         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_181_180r_fields,
  54493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54494         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54495         -1,
  54496         -1,
  54497     },
  54498 #endif /* chips */
  54499 
  54500 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54501     defined(BCM_56450_B1)
  54502     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_183_182r */
  54503         soc_block_list[85],
  54504         soc_genreg,
  54505         1,
  54506         0,
  54507         0x200aa00,
  54508         0,
  54509         0,
  54510         2,
  54511         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_183_182r_fields,
  54512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54513         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54514         -1,
  54515         -1,
  54516     },
  54517 #endif /* chips */
  54518 
  54519 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54520     defined(BCM_56450_B1)
  54521     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_185_184r */
  54522         soc_block_list[85],
  54523         soc_genreg,
  54524         1,
  54525         0,
  54526         0x200a900,
  54527         0,
  54528         0,
  54529         2,
  54530         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_185_184r_fields,
  54531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54532         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54533         -1,
  54534         -1,
  54535     },
  54536 #endif /* chips */
  54537 
  54538 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54539     defined(BCM_56450_B1)
  54540     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_187_186r */
  54541         soc_block_list[85],
  54542         soc_genreg,
  54543         1,
  54544         0,
  54545         0x200a800,
  54546         0,
  54547         0,
  54548         2,
  54549         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_187_186r_fields,
  54550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54551         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54552         -1,
  54553         -1,
  54554     },
  54555 #endif /* chips */
  54556 
  54557 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54558     defined(BCM_56450_B1)
  54559     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_189_188r */
  54560         soc_block_list[85],
  54561         soc_genreg,
  54562         1,
  54563         0,
  54564         0x200a700,
  54565         0,
  54566         0,
  54567         2,
  54568         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_189_188r_fields,
  54569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54570         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54571         -1,
  54572         -1,
  54573     },
  54574 #endif /* chips */
  54575 
  54576 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54577     defined(BCM_56450_B1)
  54578     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_191_190r */
  54579         soc_block_list[85],
  54580         soc_genreg,
  54581         1,
  54582         0,
  54583         0x200a600,
  54584         0,
  54585         0,
  54586         2,
  54587         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_191_190r_fields,
  54588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54589         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54590         -1,
  54591         -1,
  54592     },
  54593 #endif /* chips */
  54594 
  54595 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54596     defined(BCM_56450_B1)
  54597     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_193_192r */
  54598         soc_block_list[85],
  54599         soc_genreg,
  54600         1,
  54601         0,
  54602         0x200a500,
  54603         0,
  54604         0,
  54605         2,
  54606         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_193_192r_fields,
  54607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54608         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54609         -1,
  54610         -1,
  54611     },
  54612 #endif /* chips */
  54613 
  54614 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54615     defined(BCM_56450_B1)
  54616     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_195_194r */
  54617         soc_block_list[85],
  54618         soc_genreg,
  54619         1,
  54620         0,
  54621         0x200a400,
  54622         0,
  54623         0,
  54624         2,
  54625         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_195_194r_fields,
  54626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54627         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54628         -1,
  54629         -1,
  54630     },
  54631 #endif /* chips */
  54632 
  54633 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54634     defined(BCM_56450_B1)
  54635     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_197_196r */
  54636         soc_block_list[85],
  54637         soc_genreg,
  54638         1,
  54639         0,
  54640         0x200a300,
  54641         0,
  54642         0,
  54643         2,
  54644         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_197_196r_fields,
  54645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54646         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54647         -1,
  54648         -1,
  54649     },
  54650 #endif /* chips */
  54651 
  54652 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54653     defined(BCM_56450_B1)
  54654     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_199_198r */
  54655         soc_block_list[85],
  54656         soc_genreg,
  54657         1,
  54658         0,
  54659         0x200a200,
  54660         0,
  54661         0,
  54662         2,
  54663         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_199_198r_fields,
  54664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54665         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54666         -1,
  54667         -1,
  54668     },
  54669 #endif /* chips */
  54670 
  54671 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54672     defined(BCM_56450_B1)
  54673     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_201_200r */
  54674         soc_block_list[85],
  54675         soc_genreg,
  54676         1,
  54677         0,
  54678         0x200a100,
  54679         0,
  54680         0,
  54681         2,
  54682         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_201_200r_fields,
  54683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54684         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54685         -1,
  54686         -1,
  54687     },
  54688 #endif /* chips */
  54689 
  54690 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54691     defined(BCM_56450_B1)
  54692     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_203_202r */
  54693         soc_block_list[85],
  54694         soc_genreg,
  54695         1,
  54696         0,
  54697         0x200a000,
  54698         0,
  54699         0,
  54700         2,
  54701         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_203_202r_fields,
  54702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54703         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54704         -1,
  54705         -1,
  54706     },
  54707 #endif /* chips */
  54708 
  54709 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54710     defined(BCM_56450_B1)
  54711     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_205_204r */
  54712         soc_block_list[85],
  54713         soc_genreg,
  54714         1,
  54715         0,
  54716         0x2009f00,
  54717         0,
  54718         0,
  54719         2,
  54720         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_205_204r_fields,
  54721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54722         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54723         -1,
  54724         -1,
  54725     },
  54726 #endif /* chips */
  54727 
  54728 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54729     defined(BCM_56450_B1)
  54730     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_207_206r */
  54731         soc_block_list[85],
  54732         soc_genreg,
  54733         1,
  54734         0,
  54735         0x2009e00,
  54736         0,
  54737         0,
  54738         2,
  54739         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_207_206r_fields,
  54740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54741         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54742         -1,
  54743         -1,
  54744     },
  54745 #endif /* chips */
  54746 
  54747 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54748     defined(BCM_56450_B1)
  54749     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_209_208r */
  54750         soc_block_list[85],
  54751         soc_genreg,
  54752         1,
  54753         0,
  54754         0x2009d00,
  54755         0,
  54756         0,
  54757         2,
  54758         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_209_208r_fields,
  54759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54760         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54761         -1,
  54762         -1,
  54763     },
  54764 #endif /* chips */
  54765 
  54766 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54767     defined(BCM_56450_B1)
  54768     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_211_210r */
  54769         soc_block_list[85],
  54770         soc_genreg,
  54771         1,
  54772         0,
  54773         0x2009c00,
  54774         0,
  54775         0,
  54776         2,
  54777         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_211_210r_fields,
  54778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54779         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54780         -1,
  54781         -1,
  54782     },
  54783 #endif /* chips */
  54784 
  54785 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54786     defined(BCM_56450_B1)
  54787     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_213_212r */
  54788         soc_block_list[85],
  54789         soc_genreg,
  54790         1,
  54791         0,
  54792         0x2009b00,
  54793         0,
  54794         0,
  54795         2,
  54796         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_213_212r_fields,
  54797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54798         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54799         -1,
  54800         -1,
  54801     },
  54802 #endif /* chips */
  54803 
  54804 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54805     defined(BCM_56450_B1)
  54806     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_215_214r */
  54807         soc_block_list[85],
  54808         soc_genreg,
  54809         1,
  54810         0,
  54811         0x2009a00,
  54812         0,
  54813         0,
  54814         2,
  54815         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_215_214r_fields,
  54816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54817         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54818         -1,
  54819         -1,
  54820     },
  54821 #endif /* chips */
  54822 
  54823 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54824     defined(BCM_56450_B1)
  54825     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_217_216r */
  54826         soc_block_list[85],
  54827         soc_genreg,
  54828         1,
  54829         0,
  54830         0x2009900,
  54831         0,
  54832         0,
  54833         2,
  54834         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_217_216r_fields,
  54835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54836         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54837         -1,
  54838         -1,
  54839     },
  54840 #endif /* chips */
  54841 
  54842 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54843     defined(BCM_56450_B1)
  54844     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_219_218r */
  54845         soc_block_list[85],
  54846         soc_genreg,
  54847         1,
  54848         0,
  54849         0x2009800,
  54850         0,
  54851         0,
  54852         2,
  54853         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_219_218r_fields,
  54854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54855         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54856         -1,
  54857         -1,
  54858     },
  54859 #endif /* chips */
  54860 
  54861 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54862     defined(BCM_56450_B1)
  54863     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_221_220r */
  54864         soc_block_list[85],
  54865         soc_genreg,
  54866         1,
  54867         0,
  54868         0x2009700,
  54869         0,
  54870         0,
  54871         2,
  54872         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_221_220r_fields,
  54873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54874         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54875         -1,
  54876         -1,
  54877     },
  54878 #endif /* chips */
  54879 
  54880 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54881     defined(BCM_56450_B1)
  54882     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_223_222r */
  54883         soc_block_list[85],
  54884         soc_genreg,
  54885         1,
  54886         0,
  54887         0x2009600,
  54888         0,
  54889         0,
  54890         2,
  54891         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_223_222r_fields,
  54892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54893         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54894         -1,
  54895         -1,
  54896     },
  54897 #endif /* chips */
  54898 
  54899 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54900     defined(BCM_56450_B1)
  54901     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_225_224r */
  54902         soc_block_list[85],
  54903         soc_genreg,
  54904         1,
  54905         0,
  54906         0x2009500,
  54907         0,
  54908         0,
  54909         2,
  54910         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_225_224r_fields,
  54911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54912         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54913         -1,
  54914         -1,
  54915     },
  54916 #endif /* chips */
  54917 
  54918 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54919     defined(BCM_56450_B1)
  54920     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_227_226r */
  54921         soc_block_list[85],
  54922         soc_genreg,
  54923         1,
  54924         0,
  54925         0x2009400,
  54926         0,
  54927         0,
  54928         2,
  54929         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_227_226r_fields,
  54930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54931         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54932         -1,
  54933         -1,
  54934     },
  54935 #endif /* chips */
  54936 
  54937 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54938     defined(BCM_56450_B1)
  54939     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_229_228r */
  54940         soc_block_list[85],
  54941         soc_genreg,
  54942         1,
  54943         0,
  54944         0x2009300,
  54945         0,
  54946         0,
  54947         2,
  54948         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_229_228r_fields,
  54949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54950         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54951         -1,
  54952         -1,
  54953     },
  54954 #endif /* chips */
  54955 
  54956 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54957     defined(BCM_56450_B1)
  54958     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_231_230r */
  54959         soc_block_list[85],
  54960         soc_genreg,
  54961         1,
  54962         0,
  54963         0x2009200,
  54964         0,
  54965         0,
  54966         2,
  54967         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_231_230r_fields,
  54968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54969         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54970         -1,
  54971         -1,
  54972     },
  54973 #endif /* chips */
  54974 
  54975 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54976     defined(BCM_56450_B1)
  54977     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_233_232r */
  54978         soc_block_list[85],
  54979         soc_genreg,
  54980         1,
  54981         0,
  54982         0x2009100,
  54983         0,
  54984         0,
  54985         2,
  54986         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_233_232r_fields,
  54987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54988         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  54989         -1,
  54990         -1,
  54991     },
  54992 #endif /* chips */
  54993 
  54994 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  54995     defined(BCM_56450_B1)
  54996     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_235_234r */
  54997         soc_block_list[85],
  54998         soc_genreg,
  54999         1,
  55000         0,
  55001         0x2009000,
  55002         0,
  55003         0,
  55004         2,
  55005         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_235_234r_fields,
  55006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55007         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55008         -1,
  55009         -1,
  55010     },
  55011 #endif /* chips */
  55012 
  55013 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55014     defined(BCM_56450_B1)
  55015     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_237_236r */
  55016         soc_block_list[85],
  55017         soc_genreg,
  55018         1,
  55019         0,
  55020         0x2008f00,
  55021         0,
  55022         0,
  55023         2,
  55024         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_237_236r_fields,
  55025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55026         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55027         -1,
  55028         -1,
  55029     },
  55030 #endif /* chips */
  55031 
  55032 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55033     defined(BCM_56450_B1)
  55034     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_239_238r */
  55035         soc_block_list[85],
  55036         soc_genreg,
  55037         1,
  55038         0,
  55039         0x2008e00,
  55040         0,
  55041         0,
  55042         2,
  55043         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_239_238r_fields,
  55044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55045         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55046         -1,
  55047         -1,
  55048     },
  55049 #endif /* chips */
  55050 
  55051 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55052     defined(BCM_56450_B1)
  55053     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_241_240r */
  55054         soc_block_list[85],
  55055         soc_genreg,
  55056         1,
  55057         0,
  55058         0x2008d00,
  55059         0,
  55060         0,
  55061         2,
  55062         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_241_240r_fields,
  55063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55064         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55065         -1,
  55066         -1,
  55067     },
  55068 #endif /* chips */
  55069 
  55070 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55071     defined(BCM_56450_B1)
  55072     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_243_242r */
  55073         soc_block_list[85],
  55074         soc_genreg,
  55075         1,
  55076         0,
  55077         0x2008c00,
  55078         0,
  55079         0,
  55080         2,
  55081         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_243_242r_fields,
  55082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55083         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55084         -1,
  55085         -1,
  55086     },
  55087 #endif /* chips */
  55088 
  55089 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55090     defined(BCM_56450_B1)
  55091     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_245_244r */
  55092         soc_block_list[85],
  55093         soc_genreg,
  55094         1,
  55095         0,
  55096         0x2008b00,
  55097         0,
  55098         0,
  55099         2,
  55100         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_245_244r_fields,
  55101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55102         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55103         -1,
  55104         -1,
  55105     },
  55106 #endif /* chips */
  55107 
  55108 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55109     defined(BCM_56450_B1)
  55110     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_247_246r */
  55111         soc_block_list[85],
  55112         soc_genreg,
  55113         1,
  55114         0,
  55115         0x2008a00,
  55116         0,
  55117         0,
  55118         2,
  55119         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_247_246r_fields,
  55120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55121         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55122         -1,
  55123         -1,
  55124     },
  55125 #endif /* chips */
  55126 
  55127 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55128     defined(BCM_56450_B1)
  55129     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_249_248r */
  55130         soc_block_list[85],
  55131         soc_genreg,
  55132         1,
  55133         0,
  55134         0x2008900,
  55135         0,
  55136         0,
  55137         2,
  55138         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_249_248r_fields,
  55139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55140         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55141         -1,
  55142         -1,
  55143     },
  55144 #endif /* chips */
  55145 
  55146 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55147     defined(BCM_56450_B1)
  55148     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_251_250r */
  55149         soc_block_list[85],
  55150         soc_genreg,
  55151         1,
  55152         0,
  55153         0x2008800,
  55154         0,
  55155         0,
  55156         2,
  55157         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_251_250r_fields,
  55158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55159         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55160         -1,
  55161         -1,
  55162     },
  55163 #endif /* chips */
  55164 
  55165 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55166     defined(BCM_56450_B1)
  55167     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_253_252r */
  55168         soc_block_list[85],
  55169         soc_genreg,
  55170         1,
  55171         0,
  55172         0x2008700,
  55173         0,
  55174         0,
  55175         2,
  55176         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_253_252r_fields,
  55177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55178         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55179         -1,
  55180         -1,
  55181     },
  55182 #endif /* chips */
  55183 
  55184 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55185     defined(BCM_56450_B1)
  55186     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_255_254r */
  55187         soc_block_list[85],
  55188         soc_genreg,
  55189         1,
  55190         0,
  55191         0x2008600,
  55192         0,
  55193         0,
  55194         2,
  55195         soc_LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_255_254r_fields,
  55196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55197         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  55198         -1,
  55199         -1,
  55200     },
  55201 #endif /* chips */
  55202 
  55203 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  55204     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0r */
  55205         soc_block_list[85],
  55206         soc_genreg,
  55207         1,
  55208         0,
  55209         0x2007c00,
  55210         0,
  55211         0,
  55212         2,
  55213         soc_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0r_fields,
  55214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55215         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  55216         -1,
  55217         -1,
  55218     },
  55219 #endif /* chips */
  55220 
  55221 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55222     defined(BCM_56450_B1)
  55223     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_127_96r */
  55224         soc_block_list[85],
  55225         soc_genreg,
  55226         1,
  55227         0,
  55228         0x2008200,
  55229         0,
  55230         0,
  55231         1,
  55232         soc_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_127_96r_fields,
  55233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55234         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55235         -1,
  55236         -1,
  55237     },
  55238 #endif /* chips */
  55239 
  55240 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55241     defined(BCM_56450_B1)
  55242     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_31_0r */
  55243         soc_block_list[85],
  55244         soc_genreg,
  55245         1,
  55246         0,
  55247         0x2008500,
  55248         0,
  55249         0,
  55250         1,
  55251         soc_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_31_0r_fields,
  55252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55253         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55254         -1,
  55255         -1,
  55256     },
  55257 #endif /* chips */
  55258 
  55259 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55260     defined(BCM_56450_B1)
  55261     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_63_32r */
  55262         soc_block_list[85],
  55263         soc_genreg,
  55264         1,
  55265         0,
  55266         0x2008400,
  55267         0,
  55268         0,
  55269         1,
  55270         soc_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_63_32r_fields,
  55271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55272         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55273         -1,
  55274         -1,
  55275     },
  55276 #endif /* chips */
  55277 
  55278 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55279     defined(BCM_56450_B1)
  55280     { /* SOC_REG_INT_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_95_64r */
  55281         soc_block_list[85],
  55282         soc_genreg,
  55283         1,
  55284         0,
  55285         0x2008300,
  55286         0,
  55287         0,
  55288         1,
  55289         soc_LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_95_64r_fields,
  55290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55291         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55292         -1,
  55293         -1,
  55294     },
  55295 #endif /* chips */
  55296 
  55297 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55298     defined(BCM_56450_B1)
  55299     { /* SOC_REG_INT_LLS_LINKPHY_CPU_READ_S1_CREDITr */
  55300         soc_block_list[85],
  55301         soc_genreg,
  55302         1,
  55303         0,
  55304         0x2010800,
  55305         0,
  55306         0,
  55307         1,
  55308         soc_LLS_LINKPHY_CPU_READ_S1_CREDITr_fields,
  55309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55310         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  55311         -1,
  55312         -1,
  55313     },
  55314 #endif /* chips */
  55315 
  55316 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55317     defined(BCM_56450_B1)
  55318     { /* SOC_REG_INT_LLS_LINKPHY_CREDIT_READ_IDr */
  55319         soc_block_list[85],
  55320         soc_genreg,
  55321         1,
  55322         0,
  55323         0x2010700,
  55324         0,
  55325         0,
  55326         1,
  55327         soc_LLS_LINKPHY_CREDIT_READ_IDr_fields,
  55328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55329         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  55330         -1,
  55331         -1,
  55332     },
  55333 #endif /* chips */
  55334 
  55335 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  55336     { /* SOC_REG_INT_LLS_LINK_PHY_ENABLED_CONFIGr */
  55337         soc_block_list[85],
  55338         soc_genreg,
  55339         1,
  55340         0,
  55341         0x2005d00,
  55342         0,
  55343         0,
  55344         1,
  55345         soc_LLS_LINK_PHY_ENABLED_CONFIGr_fields,
  55346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55347         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55348         -1,
  55349         -1,
  55350     },
  55351 #endif /* chips */
  55352 
  55353 #if defined(BCM_56270_A0)
  55354     { /* SOC_REG_INT_LLS_LINK_PHY_ENABLED_CONFIG_BCM56270_A0r */
  55355         soc_block_list[85],
  55356         soc_genreg,
  55357         1,
  55358         0,
  55359         0x2005900,
  55360         0,
  55361         0,
  55362         1,
  55363         soc_LLS_LINK_PHY_ENABLED_CONFIGr_fields,
  55364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55365         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55366         -1,
  55367         -1,
  55368     },
  55369 #endif /* chips */
  55370 
  55371 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  55372     { /* SOC_REG_INT_LLS_LINK_PHY_SHAPE_S1_CONFIGr */
  55373         soc_block_list[85],
  55374         soc_genreg,
  55375         1,
  55376         0,
  55377         0x2005e00,
  55378         0,
  55379         0,
  55380         1,
  55381         soc_LLS_LINK_PHY_SHAPE_S1_CONFIGr_fields,
  55382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55383         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55384         -1,
  55385         -1,
  55386     },
  55387 #endif /* chips */
  55388 
  55389 #if defined(BCM_56270_A0)
  55390     { /* SOC_REG_INT_LLS_LINK_PHY_SHAPE_S1_CONFIG_BCM56270_A0r */
  55391         soc_block_list[85],
  55392         soc_genreg,
  55393         1,
  55394         0,
  55395         0x2005a00,
  55396         0,
  55397         0,
  55398         1,
  55399         soc_LLS_LINK_PHY_SHAPE_S1_CONFIGr_fields,
  55400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55401         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55402         -1,
  55403         -1,
  55404     },
  55405 #endif /* chips */
  55406 
  55407 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  55408     { /* SOC_REG_INT_LLS_MAX_REFRESH_ENABLEr */
  55409         soc_block_list[85],
  55410         soc_genreg,
  55411         1,
  55412         0,
  55413         0x80016,
  55414         0,
  55415         0,
  55416         4,
  55417         soc_LLS_MAX_REFRESH_ENABLEr_fields,
  55418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55419         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55420         -1,
  55421         -1,
  55422     },
  55423 #endif /* chips */
  55424 
  55425 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  55426     { /* SOC_REG_INT_LLS_MAX_REFRESH_ENABLE_BCM56260_A0r */
  55427         soc_block_list[85],
  55428         soc_genreg,
  55429         1,
  55430         0,
  55431         0x2001b00,
  55432         0,
  55433         0,
  55434         6,
  55435         soc_LLS_MAX_REFRESH_ENABLE_BCM56260_A0r_fields,
  55436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55437         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  55438         -1,
  55439         -1,
  55440     },
  55441 #endif /* chips */
  55442 
  55443 #if defined(BCM_56270_A0)
  55444     { /* SOC_REG_INT_LLS_MAX_REFRESH_ENABLE_BCM56270_A0r */
  55445         soc_block_list[85],
  55446         soc_genreg,
  55447         1,
  55448         0,
  55449         0x2001b00,
  55450         0,
  55451         0,
  55452         5,
  55453         soc_LLS_MAX_REFRESH_ENABLE_BCM56270_A0r_fields,
  55454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55455         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  55456         -1,
  55457         -1,
  55458     },
  55459 #endif /* chips */
  55460 
  55461 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55462     defined(BCM_56450_B1)
  55463     { /* SOC_REG_INT_LLS_MAX_REFRESH_ENABLE_BCM56450_A0r */
  55464         soc_block_list[85],
  55465         soc_genreg,
  55466         1,
  55467         0,
  55468         0x2001a00,
  55469         0,
  55470         0,
  55471         6,
  55472         soc_LLS_MAX_REFRESH_ENABLE_BCM56450_A0r_fields,
  55473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55474         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  55475         -1,
  55476         -1,
  55477     },
  55478 #endif /* chips */
  55479 
  55480 #if defined(BCM_56440_A0)
  55481     { /* SOC_REG_INT_LLS_MEM_DCM_ERRORr */
  55482         soc_block_list[85],
  55483         soc_genreg,
  55484         1,
  55485         0,
  55486         0x80061,
  55487         0,
  55488         0,
  55489         3,
  55490         soc_LLS_MEM_DCM_ERRORr_fields,
  55491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55492         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  55493         -1,
  55494         -1,
  55495     },
  55496 #endif /* chips */
  55497 
  55498 #if defined(BCM_56440_B0)
  55499     { /* SOC_REG_INT_LLS_MEM_DCM_ERROR_BCM56440_B0r */
  55500         soc_block_list[85],
  55501         soc_genreg,
  55502         1,
  55503         0,
  55504         0x80069,
  55505         0,
  55506         0,
  55507         6,
  55508         soc_LLS_MEM_DCM_ERROR_BCM56440_B0r_fields,
  55509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55510         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  55511         -1,
  55512         -1,
  55513     },
  55514 #endif /* chips */
  55515 
  55516 #if defined(BCM_56440_A0)
  55517     { /* SOC_REG_INT_LLS_MEM_DCM_L0r */
  55518         soc_block_list[85],
  55519         soc_genreg,
  55520         1,
  55521         0,
  55522         0x8005e,
  55523         0,
  55524         0,
  55525         14,
  55526         soc_LLS_MEM_DCM_L0r_fields,
  55527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55528         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  55529         -1,
  55530         -1,
  55531     },
  55532 #endif /* chips */
  55533 
  55534 #if defined(BCM_56440_A0)
  55535     { /* SOC_REG_INT_LLS_MEM_DCM_L1r */
  55536         soc_block_list[85],
  55537         soc_genreg,
  55538         1,
  55539         0,
  55540         0x8005f,
  55541         0,
  55542         0,
  55543         14,
  55544         soc_LLS_MEM_DCM_L1r_fields,
  55545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55546         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  55547         -1,
  55548         -1,
  55549     },
  55550 #endif /* chips */
  55551 
  55552 #if defined(BCM_56440_A0)
  55553     { /* SOC_REG_INT_LLS_MEM_DCM_L2r */
  55554         soc_block_list[85],
  55555         soc_genreg,
  55556         1,
  55557         0,
  55558         0x80060,
  55559         0,
  55560         0,
  55561         13,
  55562         soc_LLS_MEM_DCM_L2r_fields,
  55563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55564         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  55565         -1,
  55566         -1,
  55567     },
  55568 #endif /* chips */
  55569 
  55570 #if defined(BCM_56440_B0)
  55571     { /* SOC_REG_INT_LLS_MEM_DCM_L0_BCM56440_B0r */
  55572         soc_block_list[85],
  55573         soc_genreg,
  55574         1,
  55575         0,
  55576         0x80066,
  55577         0,
  55578         0,
  55579         14,
  55580         soc_LLS_MEM_DCM_L0r_fields,
  55581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55582         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  55583         -1,
  55584         -1,
  55585     },
  55586 #endif /* chips */
  55587 
  55588 #if defined(BCM_56440_B0)
  55589     { /* SOC_REG_INT_LLS_MEM_DCM_L1_BCM56440_B0r */
  55590         soc_block_list[85],
  55591         soc_genreg,
  55592         1,
  55593         0,
  55594         0x80067,
  55595         0,
  55596         0,
  55597         14,
  55598         soc_LLS_MEM_DCM_L1r_fields,
  55599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55600         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  55601         -1,
  55602         -1,
  55603     },
  55604 #endif /* chips */
  55605 
  55606 #if defined(BCM_56440_A0)
  55607     { /* SOC_REG_INT_LLS_MEM_DCM_L2_ACTr */
  55608         soc_block_list[85],
  55609         soc_genreg,
  55610         1,
  55611         0,
  55612         0x80062,
  55613         0,
  55614         0,
  55615         3,
  55616         soc_LLS_MEM_DCM_L2_ACTr_fields,
  55617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55618         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  55619         -1,
  55620         -1,
  55621     },
  55622 #endif /* chips */
  55623 
  55624 #if defined(BCM_56440_B0)
  55625     { /* SOC_REG_INT_LLS_MEM_DCM_L2_ACT_BCM56440_B0r */
  55626         soc_block_list[85],
  55627         soc_genreg,
  55628         1,
  55629         0,
  55630         0x8006a,
  55631         0,
  55632         0,
  55633         3,
  55634         soc_LLS_MEM_DCM_L2_ACTr_fields,
  55635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55636         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  55637         -1,
  55638         -1,
  55639     },
  55640 #endif /* chips */
  55641 
  55642 #if defined(BCM_56440_B0)
  55643     { /* SOC_REG_INT_LLS_MEM_DCM_L2_BCM56440_B0r */
  55644         soc_block_list[85],
  55645         soc_genreg,
  55646         1,
  55647         0,
  55648         0x80068,
  55649         0,
  55650         0,
  55651         13,
  55652         soc_LLS_MEM_DCM_L2r_fields,
  55653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55654         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  55655         -1,
  55656         -1,
  55657     },
  55658 #endif /* chips */
  55659 
  55660 #if defined(BCM_56440_A0)
  55661     { /* SOC_REG_INT_LLS_MEM_DCM_PORTr */
  55662         soc_block_list[85],
  55663         soc_genreg,
  55664         1,
  55665         0,
  55666         0x8005d,
  55667         0,
  55668         0,
  55669         2,
  55670         soc_LLS_MEM_DCM_PORTr_fields,
  55671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55672         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  55673         -1,
  55674         -1,
  55675     },
  55676 #endif /* chips */
  55677 
  55678 #if defined(BCM_56440_B0)
  55679     { /* SOC_REG_INT_LLS_MEM_DCM_PORT_BCM56440_B0r */
  55680         soc_block_list[85],
  55681         soc_genreg,
  55682         1,
  55683         0,
  55684         0x80065,
  55685         0,
  55686         0,
  55687         2,
  55688         soc_LLS_MEM_DCM_PORTr_fields,
  55689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55690         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  55691         -1,
  55692         -1,
  55693     },
  55694 #endif /* chips */
  55695 
  55696 #if defined(BCM_56440_A0)
  55697     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_0r */
  55698         soc_block_list[85],
  55699         soc_genreg,
  55700         1,
  55701         0,
  55702         0x8003d,
  55703         0,
  55704         0,
  55705         1,
  55706         soc_LLS_MEM_DEBUG_L0_0r_fields,
  55707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55708         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  55709         -1,
  55710         -1,
  55711     },
  55712 #endif /* chips */
  55713 
  55714 #if defined(BCM_56440_A0)
  55715     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1r */
  55716         soc_block_list[85],
  55717         soc_genreg,
  55718         1,
  55719         0,
  55720         0x8003e,
  55721         0,
  55722         0,
  55723         2,
  55724         soc_LLS_MEM_DEBUG_L0_1r_fields,
  55725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55726         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  55727         -1,
  55728         -1,
  55729     },
  55730 #endif /* chips */
  55731 
  55732 #if defined(BCM_56440_A0)
  55733     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_2r */
  55734         soc_block_list[85],
  55735         soc_genreg,
  55736         1,
  55737         0,
  55738         0x8003f,
  55739         0,
  55740         0,
  55741         1,
  55742         soc_LLS_MEM_DEBUG_L0_2r_fields,
  55743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55744         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  55745         -1,
  55746         -1,
  55747     },
  55748 #endif /* chips */
  55749 
  55750 #if defined(BCM_56440_A0)
  55751     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_3r */
  55752         soc_block_list[85],
  55753         soc_genreg,
  55754         1,
  55755         0,
  55756         0x80040,
  55757         0,
  55758         0,
  55759         1,
  55760         soc_LLS_MEM_DEBUG_L0_3r_fields,
  55761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55762         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  55763         -1,
  55764         -1,
  55765     },
  55766 #endif /* chips */
  55767 
  55768 #if defined(BCM_56440_A0)
  55769     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_4r */
  55770         soc_block_list[85],
  55771         soc_genreg,
  55772         1,
  55773         0,
  55774         0x80041,
  55775         0,
  55776         0,
  55777         2,
  55778         soc_LLS_MEM_DEBUG_L0_4r_fields,
  55779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55780         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  55781         -1,
  55782         -1,
  55783     },
  55784 #endif /* chips */
  55785 
  55786 #if defined(BCM_56440_A0)
  55787     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_5r */
  55788         soc_block_list[85],
  55789         soc_genreg,
  55790         1,
  55791         0,
  55792         0x80042,
  55793         0,
  55794         0,
  55795         1,
  55796         soc_LLS_MEM_DEBUG_L0_5r_fields,
  55797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55798         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  55799         -1,
  55800         -1,
  55801     },
  55802 #endif /* chips */
  55803 
  55804 #if defined(BCM_56440_A0)
  55805     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_6r */
  55806         soc_block_list[85],
  55807         soc_genreg,
  55808         1,
  55809         0,
  55810         0x80043,
  55811         0,
  55812         0,
  55813         1,
  55814         soc_LLS_MEM_DEBUG_L0_6r_fields,
  55815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55816         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  55817         -1,
  55818         -1,
  55819     },
  55820 #endif /* chips */
  55821 
  55822 #if defined(BCM_56440_A0)
  55823     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_7r */
  55824         soc_block_list[85],
  55825         soc_genreg,
  55826         1,
  55827         0,
  55828         0x80044,
  55829         0,
  55830         0,
  55831         3,
  55832         soc_LLS_MEM_DEBUG_L0_7r_fields,
  55833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55834         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  55835         -1,
  55836         -1,
  55837     },
  55838 #endif /* chips */
  55839 
  55840 #if defined(BCM_56440_A0)
  55841     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_8r */
  55842         soc_block_list[85],
  55843         soc_genreg,
  55844         1,
  55845         0,
  55846         0x80045,
  55847         0,
  55848         0,
  55849         2,
  55850         soc_LLS_MEM_DEBUG_L0_8r_fields,
  55851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55852         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  55853         -1,
  55854         -1,
  55855     },
  55856 #endif /* chips */
  55857 
  55858 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  55859     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_0_BCM56260_A0r */
  55860         soc_block_list[85],
  55861         soc_genreg,
  55862         1,
  55863         0,
  55864         0x2009900,
  55865         0,
  55866         0,
  55867         1,
  55868         soc_LLS_MEM_DEBUG_L0_0_BCM56260_A0r_fields,
  55869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55870         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  55871         -1,
  55872         -1,
  55873     },
  55874 #endif /* chips */
  55875 
  55876 #if defined(BCM_56270_A0)
  55877     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_0_BCM56270_A0r */
  55878         soc_block_list[85],
  55879         soc_genreg,
  55880         1,
  55881         0,
  55882         0x2008000,
  55883         0,
  55884         0,
  55885         1,
  55886         soc_LLS_MEM_DEBUG_L0_0_BCM56560_A0r_fields,
  55887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55888         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  55889         -1,
  55890         -1,
  55891     },
  55892 #endif /* chips */
  55893 
  55894 #if defined(BCM_56440_B0)
  55895     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_0_BCM56440_B0r */
  55896         soc_block_list[85],
  55897         soc_genreg,
  55898         1,
  55899         0,
  55900         0x80045,
  55901         0,
  55902         0,
  55903         1,
  55904         soc_LLS_MEM_DEBUG_L0_0r_fields,
  55905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55906         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  55907         -1,
  55908         -1,
  55909     },
  55910 #endif /* chips */
  55911 
  55912 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  55913     defined(BCM_56450_B1)
  55914     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_0_BCM56450_A0r */
  55915         soc_block_list[85],
  55916         soc_genreg,
  55917         1,
  55918         0,
  55919         0x2011c00,
  55920         0,
  55921         0,
  55922         1,
  55923         soc_ES_PIPE0_LLS_MEM_L0_TM_8r_fields,
  55924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55925         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  55926         -1,
  55927         -1,
  55928     },
  55929 #endif /* chips */
  55930 
  55931 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  55932     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_0_BCM56560_A0r */
  55933         soc_block_list[4],
  55934         soc_genreg,
  55935         1,
  55936         0,
  55937         0x62004c00,
  55938         0,
  55939         0,
  55940         1,
  55941         soc_LLS_MEM_DEBUG_L0_0_BCM56560_A0r_fields,
  55942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55943         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  55944         -1,
  55945         -1,
  55946     },
  55947 #endif /* chips */
  55948 
  55949 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  55950     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1Ar */
  55951         soc_block_list[85],
  55952         soc_genreg,
  55953         1,
  55954         0,
  55955         0x2009a00,
  55956         0,
  55957         0,
  55958         1,
  55959         soc_LLS_MEM_DEBUG_L0_1Ar_fields,
  55960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55961         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  55962         -1,
  55963         -1,
  55964     },
  55965 #endif /* chips */
  55966 
  55967 #if defined(BCM_56270_A0)
  55968     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1A_BCM56270_A0r */
  55969         soc_block_list[85],
  55970         soc_genreg,
  55971         1,
  55972         0,
  55973         0x2008100,
  55974         0,
  55975         0,
  55976         1,
  55977         soc_LLS_MEM_DEBUG_L0_1A_BCM56270_A0r_fields,
  55978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55979         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  55980         -1,
  55981         -1,
  55982     },
  55983 #endif /* chips */
  55984 
  55985 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  55986     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1Br */
  55987         soc_block_list[85],
  55988         soc_genreg,
  55989         1,
  55990         0,
  55991         0x2009b00,
  55992         0,
  55993         0,
  55994         1,
  55995         soc_LLS_MEM_DEBUG_L0_1Br_fields,
  55996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55997         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  55998         -1,
  55999         -1,
  56000     },
  56001 #endif /* chips */
  56002 
  56003 #if defined(BCM_56270_A0)
  56004     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1B_BCM56270_A0r */
  56005         soc_block_list[85],
  56006         soc_genreg,
  56007         1,
  56008         0,
  56009         0x2008200,
  56010         0,
  56011         0,
  56012         1,
  56013         soc_LLS_MEM_DEBUG_L0_1B_BCM56270_A0r_fields,
  56014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56015         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56016         -1,
  56017         -1,
  56018     },
  56019 #endif /* chips */
  56020 
  56021 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56022     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1_BCM56260_A0r */
  56023         soc_block_list[85],
  56024         soc_genreg,
  56025         1,
  56026         0,
  56027         0x2009c00,
  56028         0,
  56029         0,
  56030         1,
  56031         soc_LLS_MEM_DEBUG_L0_1_BCM56260_A0r_fields,
  56032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56033         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56034         -1,
  56035         -1,
  56036     },
  56037 #endif /* chips */
  56038 
  56039 #if defined(BCM_56270_A0)
  56040     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1_BCM56270_A0r */
  56041         soc_block_list[85],
  56042         soc_genreg,
  56043         1,
  56044         0,
  56045         0x2008300,
  56046         0,
  56047         0,
  56048         1,
  56049         soc_LLS_MEM_DEBUG_L0_1_BCM56270_A0r_fields,
  56050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56051         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56052         -1,
  56053         -1,
  56054     },
  56055 #endif /* chips */
  56056 
  56057 #if defined(BCM_56440_B0)
  56058     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1_BCM56440_B0r */
  56059         soc_block_list[85],
  56060         soc_genreg,
  56061         1,
  56062         0,
  56063         0x80046,
  56064         0,
  56065         0,
  56066         2,
  56067         soc_LLS_MEM_DEBUG_L0_1r_fields,
  56068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56069         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56070         -1,
  56071         -1,
  56072     },
  56073 #endif /* chips */
  56074 
  56075 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  56076     defined(BCM_56450_B1)
  56077     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1_BCM56450_A0r */
  56078         soc_block_list[85],
  56079         soc_genreg,
  56080         1,
  56081         0,
  56082         0x2011d00,
  56083         0,
  56084         0,
  56085         2,
  56086         soc_LLS_MEM_DEBUG_L0_1_BCM56450_A0r_fields,
  56087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56088         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56089         -1,
  56090         -1,
  56091     },
  56092 #endif /* chips */
  56093 
  56094 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  56095     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_1_BCM56560_A0r */
  56096         soc_block_list[4],
  56097         soc_genreg,
  56098         1,
  56099         0,
  56100         0x62004d00,
  56101         0,
  56102         0,
  56103         1,
  56104         soc_LLS_MEM_DEBUG_L0_1_BCM56560_A0r_fields,
  56105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56106         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  56107         -1,
  56108         -1,
  56109     },
  56110 #endif /* chips */
  56111 
  56112 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56113     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_2_BCM56260_A0r */
  56114         soc_block_list[85],
  56115         soc_genreg,
  56116         1,
  56117         0,
  56118         0x2009d00,
  56119         0,
  56120         0,
  56121         1,
  56122         soc_LLS_MEM_DEBUG_L0_2_BCM56260_A0r_fields,
  56123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56124         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56125         -1,
  56126         -1,
  56127     },
  56128 #endif /* chips */
  56129 
  56130 #if defined(BCM_56270_A0)
  56131     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_2_BCM56270_A0r */
  56132         soc_block_list[85],
  56133         soc_genreg,
  56134         1,
  56135         0,
  56136         0x2008400,
  56137         0,
  56138         0,
  56139         1,
  56140         soc_LLS_MEM_DEBUG_L0_2_BCM56270_A0r_fields,
  56141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56142         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56143         -1,
  56144         -1,
  56145     },
  56146 #endif /* chips */
  56147 
  56148 #if defined(BCM_56440_B0)
  56149     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_2_BCM56440_B0r */
  56150         soc_block_list[85],
  56151         soc_genreg,
  56152         1,
  56153         0,
  56154         0x80047,
  56155         0,
  56156         0,
  56157         1,
  56158         soc_LLS_MEM_DEBUG_L0_2r_fields,
  56159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56160         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56161         -1,
  56162         -1,
  56163     },
  56164 #endif /* chips */
  56165 
  56166 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  56167     defined(BCM_56450_B1)
  56168     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_2_BCM56450_A0r */
  56169         soc_block_list[85],
  56170         soc_genreg,
  56171         1,
  56172         0,
  56173         0x2011e00,
  56174         0,
  56175         0,
  56176         1,
  56177         soc_LLS_MEM_DEBUG_L0_2_BCM56450_A0r_fields,
  56178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56179         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56180         -1,
  56181         -1,
  56182     },
  56183 #endif /* chips */
  56184 
  56185 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  56186     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_2_BCM56560_A0r */
  56187         soc_block_list[4],
  56188         soc_genreg,
  56189         1,
  56190         0,
  56191         0x62004e00,
  56192         0,
  56193         0,
  56194         1,
  56195         soc_LLS_MEM_DEBUG_L0_2_BCM56560_A0r_fields,
  56196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56197         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56198         -1,
  56199         -1,
  56200     },
  56201 #endif /* chips */
  56202 
  56203 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56204     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_3_BCM56260_A0r */
  56205         soc_block_list[85],
  56206         soc_genreg,
  56207         1,
  56208         0,
  56209         0x2009e00,
  56210         0,
  56211         0,
  56212         1,
  56213         soc_LLS_MEM_DEBUG_L0_3_BCM56260_A0r_fields,
  56214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56215         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56216         -1,
  56217         -1,
  56218     },
  56219 #endif /* chips */
  56220 
  56221 #if defined(BCM_56270_A0)
  56222     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_3_BCM56270_A0r */
  56223         soc_block_list[85],
  56224         soc_genreg,
  56225         1,
  56226         0,
  56227         0x2008500,
  56228         0,
  56229         0,
  56230         1,
  56231         soc_LLS_MEM_DEBUG_L0_3_BCM56270_A0r_fields,
  56232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56233         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56234         -1,
  56235         -1,
  56236     },
  56237 #endif /* chips */
  56238 
  56239 #if defined(BCM_56440_B0)
  56240     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_3_BCM56440_B0r */
  56241         soc_block_list[85],
  56242         soc_genreg,
  56243         1,
  56244         0,
  56245         0x80048,
  56246         0,
  56247         0,
  56248         1,
  56249         soc_LLS_MEM_DEBUG_L0_3r_fields,
  56250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56251         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56252         -1,
  56253         -1,
  56254     },
  56255 #endif /* chips */
  56256 
  56257 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  56258     defined(BCM_56450_B1)
  56259     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_3_BCM56450_A0r */
  56260         soc_block_list[85],
  56261         soc_genreg,
  56262         1,
  56263         0,
  56264         0x2011f00,
  56265         0,
  56266         0,
  56267         1,
  56268         soc_LLS_MEM_DEBUG_L0_3_BCM56450_A0r_fields,
  56269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56270         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56271         -1,
  56272         -1,
  56273     },
  56274 #endif /* chips */
  56275 
  56276 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  56277     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_3_BCM56560_A0r */
  56278         soc_block_list[4],
  56279         soc_genreg,
  56280         1,
  56281         0,
  56282         0x62004f00,
  56283         0,
  56284         0,
  56285         1,
  56286         soc_LLS_MEM_DEBUG_L0_3_BCM56560_A0r_fields,
  56287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56288         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56289         -1,
  56290         -1,
  56291     },
  56292 #endif /* chips */
  56293 
  56294 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56295     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_4Ar */
  56296         soc_block_list[85],
  56297         soc_genreg,
  56298         1,
  56299         0,
  56300         0x2009f00,
  56301         0,
  56302         0,
  56303         1,
  56304         soc_LLS_MEM_DEBUG_L0_4Ar_fields,
  56305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56306         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56307         -1,
  56308         -1,
  56309     },
  56310 #endif /* chips */
  56311 
  56312 #if defined(BCM_56270_A0)
  56313     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_4A_BCM56270_A0r */
  56314         soc_block_list[85],
  56315         soc_genreg,
  56316         1,
  56317         0,
  56318         0x2008600,
  56319         0,
  56320         0,
  56321         1,
  56322         soc_LLS_MEM_DEBUG_L0_4A_BCM56270_A0r_fields,
  56323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56324         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56325         -1,
  56326         -1,
  56327     },
  56328 #endif /* chips */
  56329 
  56330 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  56331     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_4Br */
  56332         soc_block_list[4],
  56333         soc_genreg,
  56334         1,
  56335         0,
  56336         0x62005000,
  56337         0,
  56338         0,
  56339         1,
  56340         soc_LLS_MEM_DEBUG_L0_4Br_fields,
  56341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56342         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  56343         -1,
  56344         -1,
  56345     },
  56346 #endif /* chips */
  56347 
  56348 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56349     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_4B_BCM56260_A0r */
  56350         soc_block_list[85],
  56351         soc_genreg,
  56352         1,
  56353         0,
  56354         0x200a000,
  56355         0,
  56356         0,
  56357         1,
  56358         soc_LLS_MEM_DEBUG_L0_4B_BCM56260_A0r_fields,
  56359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56360         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56361         -1,
  56362         -1,
  56363     },
  56364 #endif /* chips */
  56365 
  56366 #if defined(BCM_56270_A0)
  56367     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_4B_BCM56270_A0r */
  56368         soc_block_list[85],
  56369         soc_genreg,
  56370         1,
  56371         0,
  56372         0x2008700,
  56373         0,
  56374         0,
  56375         1,
  56376         soc_LLS_MEM_DEBUG_L0_4B_BCM56270_A0r_fields,
  56377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56378         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56379         -1,
  56380         -1,
  56381     },
  56382 #endif /* chips */
  56383 
  56384 #if defined(BCM_56440_B0)
  56385     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_4_BCM56440_B0r */
  56386         soc_block_list[85],
  56387         soc_genreg,
  56388         1,
  56389         0,
  56390         0x80049,
  56391         0,
  56392         0,
  56393         2,
  56394         soc_LLS_MEM_DEBUG_L0_4r_fields,
  56395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56396         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56397         -1,
  56398         -1,
  56399     },
  56400 #endif /* chips */
  56401 
  56402 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  56403     defined(BCM_56450_B1)
  56404     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_4_BCM56450_A0r */
  56405         soc_block_list[85],
  56406         soc_genreg,
  56407         1,
  56408         0,
  56409         0x2012000,
  56410         0,
  56411         0,
  56412         2,
  56413         soc_LLS_MEM_DEBUG_L0_4_BCM56450_A0r_fields,
  56414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56415         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56416         -1,
  56417         -1,
  56418     },
  56419 #endif /* chips */
  56420 
  56421 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56422     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_5_BCM56260_A0r */
  56423         soc_block_list[85],
  56424         soc_genreg,
  56425         1,
  56426         0,
  56427         0x200a100,
  56428         0,
  56429         0,
  56430         1,
  56431         soc_LLS_MEM_DEBUG_L0_5_BCM56260_A0r_fields,
  56432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56433         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56434         -1,
  56435         -1,
  56436     },
  56437 #endif /* chips */
  56438 
  56439 #if defined(BCM_56270_A0)
  56440     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_5_BCM56270_A0r */
  56441         soc_block_list[85],
  56442         soc_genreg,
  56443         1,
  56444         0,
  56445         0x2008800,
  56446         0,
  56447         0,
  56448         1,
  56449         soc_LLS_MEM_DEBUG_L0_5_BCM56270_A0r_fields,
  56450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56451         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56452         -1,
  56453         -1,
  56454     },
  56455 #endif /* chips */
  56456 
  56457 #if defined(BCM_56440_B0)
  56458     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_5_BCM56440_B0r */
  56459         soc_block_list[85],
  56460         soc_genreg,
  56461         1,
  56462         0,
  56463         0x8004a,
  56464         0,
  56465         0,
  56466         1,
  56467         soc_LLS_MEM_DEBUG_L0_5r_fields,
  56468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56469         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56470         -1,
  56471         -1,
  56472     },
  56473 #endif /* chips */
  56474 
  56475 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  56476     defined(BCM_56450_B1)
  56477     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_5_BCM56450_A0r */
  56478         soc_block_list[85],
  56479         soc_genreg,
  56480         1,
  56481         0,
  56482         0x2012100,
  56483         0,
  56484         0,
  56485         1,
  56486         soc_LLS_MEM_DEBUG_L0_5_BCM56450_A0r_fields,
  56487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56488         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56489         -1,
  56490         -1,
  56491     },
  56492 #endif /* chips */
  56493 
  56494 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  56495     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_5_BCM56560_A0r */
  56496         soc_block_list[4],
  56497         soc_genreg,
  56498         1,
  56499         0,
  56500         0x62005100,
  56501         0,
  56502         0,
  56503         1,
  56504         soc_LLS_MEM_DEBUG_L0_5_BCM56560_A0r_fields,
  56505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56506         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56507         -1,
  56508         -1,
  56509     },
  56510 #endif /* chips */
  56511 
  56512 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56513     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_6_BCM56260_A0r */
  56514         soc_block_list[85],
  56515         soc_genreg,
  56516         1,
  56517         0,
  56518         0x200a200,
  56519         0,
  56520         0,
  56521         1,
  56522         soc_LLS_MEM_DEBUG_L0_6_BCM56260_A0r_fields,
  56523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56524         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56525         -1,
  56526         -1,
  56527     },
  56528 #endif /* chips */
  56529 
  56530 #if defined(BCM_56270_A0)
  56531     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_6_BCM56270_A0r */
  56532         soc_block_list[85],
  56533         soc_genreg,
  56534         1,
  56535         0,
  56536         0x2008900,
  56537         0,
  56538         0,
  56539         1,
  56540         soc_LLS_MEM_DEBUG_L0_6_BCM56270_A0r_fields,
  56541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56542         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56543         -1,
  56544         -1,
  56545     },
  56546 #endif /* chips */
  56547 
  56548 #if defined(BCM_56440_B0)
  56549     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_6_BCM56440_B0r */
  56550         soc_block_list[85],
  56551         soc_genreg,
  56552         1,
  56553         0,
  56554         0x8004b,
  56555         0,
  56556         0,
  56557         1,
  56558         soc_LLS_MEM_DEBUG_L0_6r_fields,
  56559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56560         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56561         -1,
  56562         -1,
  56563     },
  56564 #endif /* chips */
  56565 
  56566 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  56567     defined(BCM_56450_B1)
  56568     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_6_BCM56450_A0r */
  56569         soc_block_list[85],
  56570         soc_genreg,
  56571         1,
  56572         0,
  56573         0x2012200,
  56574         0,
  56575         0,
  56576         1,
  56577         soc_LLS_MEM_DEBUG_L0_6_BCM56450_A0r_fields,
  56578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56579         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56580         -1,
  56581         -1,
  56582     },
  56583 #endif /* chips */
  56584 
  56585 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  56586     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_6_BCM56560_A0r */
  56587         soc_block_list[4],
  56588         soc_genreg,
  56589         1,
  56590         0,
  56591         0x62005200,
  56592         0,
  56593         0,
  56594         1,
  56595         soc_LLS_MEM_DEBUG_L0_6_BCM56560_A0r_fields,
  56596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56597         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  56598         -1,
  56599         -1,
  56600     },
  56601 #endif /* chips */
  56602 
  56603 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56604     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_7_BCM56260_A0r */
  56605         soc_block_list[85],
  56606         soc_genreg,
  56607         1,
  56608         0,
  56609         0x200a300,
  56610         0,
  56611         0,
  56612         1,
  56613         soc_LLS_MEM_DEBUG_L0_7_BCM56260_A0r_fields,
  56614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56615         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56616         -1,
  56617         -1,
  56618     },
  56619 #endif /* chips */
  56620 
  56621 #if defined(BCM_56270_A0)
  56622     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_7_BCM56270_A0r */
  56623         soc_block_list[85],
  56624         soc_genreg,
  56625         1,
  56626         0,
  56627         0x2008a00,
  56628         0,
  56629         0,
  56630         1,
  56631         soc_LLS_MEM_DEBUG_L0_7_BCM56270_A0r_fields,
  56632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56633         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56634         -1,
  56635         -1,
  56636     },
  56637 #endif /* chips */
  56638 
  56639 #if defined(BCM_56440_B0)
  56640     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_7_BCM56440_B0r */
  56641         soc_block_list[85],
  56642         soc_genreg,
  56643         1,
  56644         0,
  56645         0x8004c,
  56646         0,
  56647         0,
  56648         3,
  56649         soc_LLS_MEM_DEBUG_L0_7r_fields,
  56650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56651         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  56652         -1,
  56653         -1,
  56654     },
  56655 #endif /* chips */
  56656 
  56657 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  56658     defined(BCM_56450_B1)
  56659     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_7_BCM56450_A0r */
  56660         soc_block_list[85],
  56661         soc_genreg,
  56662         1,
  56663         0,
  56664         0x2012300,
  56665         0,
  56666         0,
  56667         1,
  56668         soc_LLS_MEM_DEBUG_L0_7_BCM56450_A0r_fields,
  56669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56670         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56671         -1,
  56672         -1,
  56673     },
  56674 #endif /* chips */
  56675 
  56676 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  56677     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_7_BCM56560_A0r */
  56678         soc_block_list[4],
  56679         soc_genreg,
  56680         1,
  56681         0,
  56682         0x62005300,
  56683         0,
  56684         0,
  56685         1,
  56686         soc_LLS_MEM_DEBUG_L0_7_BCM56560_A0r_fields,
  56687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56688         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56689         -1,
  56690         -1,
  56691     },
  56692 #endif /* chips */
  56693 
  56694 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56695     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_8_BCM56260_A0r */
  56696         soc_block_list[85],
  56697         soc_genreg,
  56698         1,
  56699         0,
  56700         0x200a400,
  56701         0,
  56702         0,
  56703         1,
  56704         soc_LLS_MEM_DEBUG_L0_8_BCM56260_A0r_fields,
  56705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56706         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56707         -1,
  56708         -1,
  56709     },
  56710 #endif /* chips */
  56711 
  56712 #if defined(BCM_56270_A0)
  56713     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_8_BCM56270_A0r */
  56714         soc_block_list[85],
  56715         soc_genreg,
  56716         1,
  56717         0,
  56718         0x2008b00,
  56719         0,
  56720         0,
  56721         1,
  56722         soc_LLS_MEM_DEBUG_L0_8_BCM56270_A0r_fields,
  56723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56724         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56725         -1,
  56726         -1,
  56727     },
  56728 #endif /* chips */
  56729 
  56730 #if defined(BCM_56440_B0)
  56731     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_8_BCM56440_B0r */
  56732         soc_block_list[85],
  56733         soc_genreg,
  56734         1,
  56735         0,
  56736         0x8004d,
  56737         0,
  56738         0,
  56739         2,
  56740         soc_LLS_MEM_DEBUG_L0_8r_fields,
  56741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56742         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56743         -1,
  56744         -1,
  56745     },
  56746 #endif /* chips */
  56747 
  56748 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  56749     defined(BCM_56450_B1)
  56750     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_8_BCM56450_A0r */
  56751         soc_block_list[85],
  56752         soc_genreg,
  56753         1,
  56754         0,
  56755         0x2012400,
  56756         0,
  56757         0,
  56758         2,
  56759         soc_LLS_MEM_DEBUG_L0_8_BCM56450_A0r_fields,
  56760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56761         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56762         -1,
  56763         -1,
  56764     },
  56765 #endif /* chips */
  56766 
  56767 #if defined(BCM_56440_A0)
  56768     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_ERRORr */
  56769         soc_block_list[85],
  56770         soc_genreg,
  56771         1,
  56772         0,
  56773         0x8005a,
  56774         0,
  56775         0,
  56776         1,
  56777         soc_LLS_MEM_DEBUG_L0_ERRORr_fields,
  56778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56779         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56780         -1,
  56781         -1,
  56782     },
  56783 #endif /* chips */
  56784 
  56785 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56786     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_ERROR_BCM56260_A0r */
  56787         soc_block_list[85],
  56788         soc_genreg,
  56789         1,
  56790         0,
  56791         0x200b900,
  56792         0,
  56793         0,
  56794         1,
  56795         soc_LLS_MEM_DEBUG_L0_ERROR_BCM56260_A0r_fields,
  56796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56797         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  56798         -1,
  56799         -1,
  56800     },
  56801 #endif /* chips */
  56802 
  56803 #if defined(BCM_56270_A0)
  56804     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_ERROR_BCM56270_A0r */
  56805         soc_block_list[85],
  56806         soc_genreg,
  56807         1,
  56808         0,
  56809         0x200a000,
  56810         0,
  56811         0,
  56812         1,
  56813         soc_LLS_MEM_DEBUG_L0_ERROR_BCM56270_A0r_fields,
  56814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56815         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  56816         -1,
  56817         -1,
  56818     },
  56819 #endif /* chips */
  56820 
  56821 #if defined(BCM_56440_B0)
  56822     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_ERROR_BCM56440_B0r */
  56823         soc_block_list[85],
  56824         soc_genreg,
  56825         1,
  56826         0,
  56827         0x80062,
  56828         0,
  56829         0,
  56830         2,
  56831         soc_LLS_MEM_DEBUG_L0_ERROR_BCM56440_B0r_fields,
  56832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56833         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56834         -1,
  56835         -1,
  56836     },
  56837 #endif /* chips */
  56838 
  56839 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  56840     defined(BCM_56450_B1)
  56841     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_ERROR_BCM56450_A0r */
  56842         soc_block_list[85],
  56843         soc_genreg,
  56844         1,
  56845         0,
  56846         0x2013b00,
  56847         0,
  56848         0,
  56849         1,
  56850         soc_LLS_MEM_DEBUG_L0_ERROR_BCM56450_A0r_fields,
  56851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56852         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56853         -1,
  56854         -1,
  56855     },
  56856 #endif /* chips */
  56857 
  56858 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  56859     { /* SOC_REG_INT_LLS_MEM_DEBUG_L0_ERROR_BCM56560_A0r */
  56860         soc_block_list[4],
  56861         soc_genreg,
  56862         1,
  56863         0,
  56864         0x62006300,
  56865         0,
  56866         0,
  56867         1,
  56868         soc_LLS_MEM_DEBUG_L0_ERROR_BCM56560_A0r_fields,
  56869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56870         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56871         -1,
  56872         -1,
  56873     },
  56874 #endif /* chips */
  56875 
  56876 #if defined(BCM_56440_A0)
  56877     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_2r */
  56878         soc_block_list[85],
  56879         soc_genreg,
  56880         1,
  56881         0,
  56882         0x80049,
  56883         0,
  56884         0,
  56885         1,
  56886         soc_LLS_MEM_DEBUG_L1_2r_fields,
  56887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56888         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56889         -1,
  56890         -1,
  56891     },
  56892 #endif /* chips */
  56893 
  56894 #if defined(BCM_56440_A0)
  56895     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_3r */
  56896         soc_block_list[85],
  56897         soc_genreg,
  56898         1,
  56899         0,
  56900         0x8004a,
  56901         0,
  56902         0,
  56903         1,
  56904         soc_LLS_MEM_DEBUG_L1_3r_fields,
  56905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56906         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56907         -1,
  56908         -1,
  56909     },
  56910 #endif /* chips */
  56911 
  56912 #if defined(BCM_56440_A0)
  56913     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_4r */
  56914         soc_block_list[85],
  56915         soc_genreg,
  56916         1,
  56917         0,
  56918         0x8004b,
  56919         0,
  56920         0,
  56921         2,
  56922         soc_LLS_MEM_DEBUG_L1_4r_fields,
  56923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56924         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56925         -1,
  56926         -1,
  56927     },
  56928 #endif /* chips */
  56929 
  56930 #if defined(BCM_56440_A0)
  56931     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_5r */
  56932         soc_block_list[85],
  56933         soc_genreg,
  56934         1,
  56935         0,
  56936         0x8004c,
  56937         0,
  56938         0,
  56939         1,
  56940         soc_LLS_MEM_DEBUG_L1_5r_fields,
  56941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56942         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56943         -1,
  56944         -1,
  56945     },
  56946 #endif /* chips */
  56947 
  56948 #if defined(BCM_56440_A0)
  56949     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_6r */
  56950         soc_block_list[85],
  56951         soc_genreg,
  56952         1,
  56953         0,
  56954         0x8004d,
  56955         0,
  56956         0,
  56957         1,
  56958         soc_LLS_MEM_DEBUG_L1_6r_fields,
  56959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56960         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56961         -1,
  56962         -1,
  56963     },
  56964 #endif /* chips */
  56965 
  56966 #if defined(BCM_56440_A0)
  56967     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_7r */
  56968         soc_block_list[85],
  56969         soc_genreg,
  56970         1,
  56971         0,
  56972         0x8004e,
  56973         0,
  56974         0,
  56975         3,
  56976         soc_LLS_MEM_DEBUG_L1_7r_fields,
  56977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56978         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  56979         -1,
  56980         -1,
  56981     },
  56982 #endif /* chips */
  56983 
  56984 #if defined(BCM_56440_A0)
  56985     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_8r */
  56986         soc_block_list[85],
  56987         soc_genreg,
  56988         1,
  56989         0,
  56990         0x8004f,
  56991         0,
  56992         0,
  56993         2,
  56994         soc_LLS_MEM_DEBUG_L1_8r_fields,
  56995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56996         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56997         -1,
  56998         -1,
  56999     },
  57000 #endif /* chips */
  57001 
  57002 #if defined(BCM_56440_A0)
  57003     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1Ar */
  57004         soc_block_list[85],
  57005         soc_genreg,
  57006         1,
  57007         0,
  57008         0x80046,
  57009         0,
  57010         0,
  57011         1,
  57012         soc_LLS_MEM_DEBUG_L1_1Ar_fields,
  57013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57014         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57015         -1,
  57016         -1,
  57017     },
  57018 #endif /* chips */
  57019 
  57020 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57021     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1A_BCM56260_A0r */
  57022         soc_block_list[85],
  57023         soc_genreg,
  57024         1,
  57025         0,
  57026         0x200a500,
  57027         0,
  57028         0,
  57029         1,
  57030         soc_LLS_MEM_DEBUG_L1_1A_BCM56260_A0r_fields,
  57031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57032         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57033         -1,
  57034         -1,
  57035     },
  57036 #endif /* chips */
  57037 
  57038 #if defined(BCM_56270_A0)
  57039     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1A_BCM56270_A0r */
  57040         soc_block_list[85],
  57041         soc_genreg,
  57042         1,
  57043         0,
  57044         0x2008c00,
  57045         0,
  57046         0,
  57047         1,
  57048         soc_LLS_MEM_DEBUG_L1_1A_BCM56270_A0r_fields,
  57049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57050         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57051         -1,
  57052         -1,
  57053     },
  57054 #endif /* chips */
  57055 
  57056 #if defined(BCM_56440_B0)
  57057     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1A_BCM56440_B0r */
  57058         soc_block_list[85],
  57059         soc_genreg,
  57060         1,
  57061         0,
  57062         0x8004e,
  57063         0,
  57064         0,
  57065         1,
  57066         soc_LLS_MEM_DEBUG_L1_1Ar_fields,
  57067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57068         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57069         -1,
  57070         -1,
  57071     },
  57072 #endif /* chips */
  57073 
  57074 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  57075     defined(BCM_56450_B1)
  57076     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1A_BCM56450_A0r */
  57077         soc_block_list[85],
  57078         soc_genreg,
  57079         1,
  57080         0,
  57081         0x2012500,
  57082         0,
  57083         0,
  57084         1,
  57085         soc_ES_PIPE0_LLS_MEM_L1_TM_7r_fields,
  57086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57087         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57088         -1,
  57089         -1,
  57090     },
  57091 #endif /* chips */
  57092 
  57093 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  57094     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1A_BCM56560_A0r */
  57095         soc_block_list[4],
  57096         soc_genreg,
  57097         1,
  57098         0,
  57099         0x62005400,
  57100         0,
  57101         0,
  57102         1,
  57103         soc_LLS_MEM_DEBUG_L1_1A_BCM56560_A0r_fields,
  57104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57105         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  57106         -1,
  57107         -1,
  57108     },
  57109 #endif /* chips */
  57110 
  57111 #if defined(BCM_56440_A0)
  57112     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1Br */
  57113         soc_block_list[85],
  57114         soc_genreg,
  57115         1,
  57116         0,
  57117         0x80047,
  57118         0,
  57119         0,
  57120         1,
  57121         soc_LLS_MEM_DEBUG_L1_1Br_fields,
  57122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57123         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57124         -1,
  57125         -1,
  57126     },
  57127 #endif /* chips */
  57128 
  57129 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57130     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1B_BCM56260_A0r */
  57131         soc_block_list[85],
  57132         soc_genreg,
  57133         1,
  57134         0,
  57135         0x200a600,
  57136         0,
  57137         0,
  57138         1,
  57139         soc_LLS_MEM_DEBUG_L1_1B_BCM56260_A0r_fields,
  57140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57141         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57142         -1,
  57143         -1,
  57144     },
  57145 #endif /* chips */
  57146 
  57147 #if defined(BCM_56270_A0)
  57148     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1B_BCM56270_A0r */
  57149         soc_block_list[85],
  57150         soc_genreg,
  57151         1,
  57152         0,
  57153         0x2008d00,
  57154         0,
  57155         0,
  57156         1,
  57157         soc_LLS_MEM_DEBUG_L1_1B_BCM56270_A0r_fields,
  57158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57159         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57160         -1,
  57161         -1,
  57162     },
  57163 #endif /* chips */
  57164 
  57165 #if defined(BCM_56440_B0)
  57166     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1B_BCM56440_B0r */
  57167         soc_block_list[85],
  57168         soc_genreg,
  57169         1,
  57170         0,
  57171         0x8004f,
  57172         0,
  57173         0,
  57174         1,
  57175         soc_LLS_MEM_DEBUG_L1_1Br_fields,
  57176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57177         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57178         -1,
  57179         -1,
  57180     },
  57181 #endif /* chips */
  57182 
  57183 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  57184     defined(BCM_56450_B1)
  57185     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1B_BCM56450_A0r */
  57186         soc_block_list[85],
  57187         soc_genreg,
  57188         1,
  57189         0,
  57190         0x2012600,
  57191         0,
  57192         0,
  57193         1,
  57194         soc_LLS_MEM_L1_TM_0r_fields,
  57195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57196         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57197         -1,
  57198         -1,
  57199     },
  57200 #endif /* chips */
  57201 
  57202 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  57203     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1B_BCM56560_A0r */
  57204         soc_block_list[4],
  57205         soc_genreg,
  57206         1,
  57207         0,
  57208         0x62005500,
  57209         0,
  57210         0,
  57211         2,
  57212         soc_LLS_MEM_DEBUG_L1_1B_BCM56560_A0r_fields,
  57213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57214         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  57215         -1,
  57216         -1,
  57217     },
  57218 #endif /* chips */
  57219 
  57220 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57221     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1Cr */
  57222         soc_block_list[85],
  57223         soc_genreg,
  57224         1,
  57225         0,
  57226         0x200a700,
  57227         0,
  57228         0,
  57229         1,
  57230         soc_LLS_MEM_DEBUG_L1_1Cr_fields,
  57231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57232         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57233         -1,
  57234         -1,
  57235     },
  57236 #endif /* chips */
  57237 
  57238 #if defined(BCM_56270_A0)
  57239     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1C_BCM56270_A0r */
  57240         soc_block_list[85],
  57241         soc_genreg,
  57242         1,
  57243         0,
  57244         0x2008e00,
  57245         0,
  57246         0,
  57247         1,
  57248         soc_LLS_MEM_DEBUG_L1_1C_BCM56270_A0r_fields,
  57249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57250         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57251         -1,
  57252         -1,
  57253     },
  57254 #endif /* chips */
  57255 
  57256 #if defined(BCM_56440_A0)
  57257     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1Dr */
  57258         soc_block_list[85],
  57259         soc_genreg,
  57260         1,
  57261         0,
  57262         0x80048,
  57263         0,
  57264         0,
  57265         1,
  57266         soc_LLS_MEM_DEBUG_L1_1Dr_fields,
  57267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57268         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57269         -1,
  57270         -1,
  57271     },
  57272 #endif /* chips */
  57273 
  57274 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57275     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1D_BCM56260_A0r */
  57276         soc_block_list[85],
  57277         soc_genreg,
  57278         1,
  57279         0,
  57280         0x200a800,
  57281         0,
  57282         0,
  57283         1,
  57284         soc_LLS_MEM_DEBUG_L1_1D_BCM56260_A0r_fields,
  57285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57286         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57287         -1,
  57288         -1,
  57289     },
  57290 #endif /* chips */
  57291 
  57292 #if defined(BCM_56270_A0)
  57293     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1D_BCM56270_A0r */
  57294         soc_block_list[85],
  57295         soc_genreg,
  57296         1,
  57297         0,
  57298         0x2008f00,
  57299         0,
  57300         0,
  57301         1,
  57302         soc_LLS_MEM_DEBUG_L1_1D_BCM56270_A0r_fields,
  57303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57304         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57305         -1,
  57306         -1,
  57307     },
  57308 #endif /* chips */
  57309 
  57310 #if defined(BCM_56440_B0)
  57311     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1D_BCM56440_B0r */
  57312         soc_block_list[85],
  57313         soc_genreg,
  57314         1,
  57315         0,
  57316         0x80050,
  57317         0,
  57318         0,
  57319         1,
  57320         soc_LLS_MEM_DEBUG_L1_1Dr_fields,
  57321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57322         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57323         -1,
  57324         -1,
  57325     },
  57326 #endif /* chips */
  57327 
  57328 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  57329     defined(BCM_56450_B1)
  57330     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_1D_BCM56450_A0r */
  57331         soc_block_list[85],
  57332         soc_genreg,
  57333         1,
  57334         0,
  57335         0x2012700,
  57336         0,
  57337         0,
  57338         1,
  57339         soc_LLS_MEM_DEBUG_L1_1D_BCM56450_A0r_fields,
  57340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57341         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57342         -1,
  57343         -1,
  57344     },
  57345 #endif /* chips */
  57346 
  57347 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57348     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_2_BCM56260_A0r */
  57349         soc_block_list[85],
  57350         soc_genreg,
  57351         1,
  57352         0,
  57353         0x200a900,
  57354         0,
  57355         0,
  57356         1,
  57357         soc_LLS_MEM_DEBUG_L1_2_BCM56260_A0r_fields,
  57358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57359         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57360         -1,
  57361         -1,
  57362     },
  57363 #endif /* chips */
  57364 
  57365 #if defined(BCM_56270_A0)
  57366     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_2_BCM56270_A0r */
  57367         soc_block_list[85],
  57368         soc_genreg,
  57369         1,
  57370         0,
  57371         0x2009000,
  57372         0,
  57373         0,
  57374         1,
  57375         soc_LLS_MEM_DEBUG_L1_2_BCM56270_A0r_fields,
  57376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57377         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57378         -1,
  57379         -1,
  57380     },
  57381 #endif /* chips */
  57382 
  57383 #if defined(BCM_56440_B0)
  57384     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_2_BCM56440_B0r */
  57385         soc_block_list[85],
  57386         soc_genreg,
  57387         1,
  57388         0,
  57389         0x80051,
  57390         0,
  57391         0,
  57392         1,
  57393         soc_LLS_MEM_DEBUG_L1_2r_fields,
  57394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57395         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57396         -1,
  57397         -1,
  57398     },
  57399 #endif /* chips */
  57400 
  57401 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  57402     defined(BCM_56450_B1)
  57403     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_2_BCM56450_A0r */
  57404         soc_block_list[85],
  57405         soc_genreg,
  57406         1,
  57407         0,
  57408         0x2012800,
  57409         0,
  57410         0,
  57411         1,
  57412         soc_LLS_MEM_DEBUG_L1_2_BCM56450_A0r_fields,
  57413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57414         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57415         -1,
  57416         -1,
  57417     },
  57418 #endif /* chips */
  57419 
  57420 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  57421     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_2_BCM56560_A0r */
  57422         soc_block_list[4],
  57423         soc_genreg,
  57424         1,
  57425         0,
  57426         0x62005600,
  57427         0,
  57428         0,
  57429         1,
  57430         soc_LLS_MEM_DEBUG_L1_2_BCM56560_A0r_fields,
  57431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57432         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  57433         -1,
  57434         -1,
  57435     },
  57436 #endif /* chips */
  57437 
  57438 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  57439     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_3Ar */
  57440         soc_block_list[4],
  57441         soc_genreg,
  57442         1,
  57443         0,
  57444         0x62005800,
  57445         0,
  57446         0,
  57447         1,
  57448         soc_LLS_MEM_DEBUG_L1_3Ar_fields,
  57449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57450         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  57451         -1,
  57452         -1,
  57453     },
  57454 #endif /* chips */
  57455 
  57456 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57457     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_3_BCM56260_A0r */
  57458         soc_block_list[85],
  57459         soc_genreg,
  57460         1,
  57461         0,
  57462         0x200aa00,
  57463         0,
  57464         0,
  57465         1,
  57466         soc_LLS_MEM_DEBUG_L1_3_BCM56260_A0r_fields,
  57467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57468         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57469         -1,
  57470         -1,
  57471     },
  57472 #endif /* chips */
  57473 
  57474 #if defined(BCM_56270_A0)
  57475     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_3_BCM56270_A0r */
  57476         soc_block_list[85],
  57477         soc_genreg,
  57478         1,
  57479         0,
  57480         0x2009100,
  57481         0,
  57482         0,
  57483         1,
  57484         soc_LLS_MEM_DEBUG_L1_3_BCM56270_A0r_fields,
  57485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57486         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57487         -1,
  57488         -1,
  57489     },
  57490 #endif /* chips */
  57491 
  57492 #if defined(BCM_56440_B0)
  57493     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_3_BCM56440_B0r */
  57494         soc_block_list[85],
  57495         soc_genreg,
  57496         1,
  57497         0,
  57498         0x80052,
  57499         0,
  57500         0,
  57501         1,
  57502         soc_LLS_MEM_DEBUG_L1_3r_fields,
  57503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57504         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57505         -1,
  57506         -1,
  57507     },
  57508 #endif /* chips */
  57509 
  57510 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  57511     defined(BCM_56450_B1)
  57512     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_3_BCM56450_A0r */
  57513         soc_block_list[85],
  57514         soc_genreg,
  57515         1,
  57516         0,
  57517         0x2012900,
  57518         0,
  57519         0,
  57520         1,
  57521         soc_LLS_MEM_DEBUG_L1_3_BCM56450_A0r_fields,
  57522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57523         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57524         -1,
  57525         -1,
  57526     },
  57527 #endif /* chips */
  57528 
  57529 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  57530     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_3_BCM56560_A0r */
  57531         soc_block_list[4],
  57532         soc_genreg,
  57533         1,
  57534         0,
  57535         0x62005700,
  57536         0,
  57537         0,
  57538         1,
  57539         soc_LLS_MEM_DEBUG_L1_3_BCM56560_A0r_fields,
  57540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57541         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  57542         -1,
  57543         -1,
  57544     },
  57545 #endif /* chips */
  57546 
  57547 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  57548     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_4Ar */
  57549         soc_block_list[4],
  57550         soc_genreg,
  57551         1,
  57552         0,
  57553         0x62005900,
  57554         0,
  57555         0,
  57556         2,
  57557         soc_LLS_MEM_DEBUG_L1_4Ar_fields,
  57558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57559         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  57560         -1,
  57561         -1,
  57562     },
  57563 #endif /* chips */
  57564 
  57565 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57566     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_4A_BCM56260_A0r */
  57567         soc_block_list[85],
  57568         soc_genreg,
  57569         1,
  57570         0,
  57571         0x200ab00,
  57572         0,
  57573         0,
  57574         1,
  57575         soc_LLS_MEM_DEBUG_L1_4A_BCM56260_A0r_fields,
  57576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57577         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57578         -1,
  57579         -1,
  57580     },
  57581 #endif /* chips */
  57582 
  57583 #if defined(BCM_56270_A0)
  57584     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_4A_BCM56270_A0r */
  57585         soc_block_list[85],
  57586         soc_genreg,
  57587         1,
  57588         0,
  57589         0x2009200,
  57590         0,
  57591         0,
  57592         1,
  57593         soc_LLS_MEM_DEBUG_L1_4A_BCM56270_A0r_fields,
  57594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57595         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57596         -1,
  57597         -1,
  57598     },
  57599 #endif /* chips */
  57600 
  57601 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57602     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_4Br */
  57603         soc_block_list[85],
  57604         soc_genreg,
  57605         1,
  57606         0,
  57607         0x200ac00,
  57608         0,
  57609         0,
  57610         1,
  57611         soc_LLS_MEM_DEBUG_L1_4Br_fields,
  57612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57613         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57614         -1,
  57615         -1,
  57616     },
  57617 #endif /* chips */
  57618 
  57619 #if defined(BCM_56270_A0)
  57620     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_4B_BCM56270_A0r */
  57621         soc_block_list[85],
  57622         soc_genreg,
  57623         1,
  57624         0,
  57625         0x2009300,
  57626         0,
  57627         0,
  57628         1,
  57629         soc_LLS_MEM_DEBUG_L1_4B_BCM56270_A0r_fields,
  57630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57631         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57632         -1,
  57633         -1,
  57634     },
  57635 #endif /* chips */
  57636 
  57637 #if defined(BCM_56440_B0)
  57638     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_4_BCM56440_B0r */
  57639         soc_block_list[85],
  57640         soc_genreg,
  57641         1,
  57642         0,
  57643         0x80053,
  57644         0,
  57645         0,
  57646         2,
  57647         soc_LLS_MEM_DEBUG_L1_4r_fields,
  57648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57649         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  57650         -1,
  57651         -1,
  57652     },
  57653 #endif /* chips */
  57654 
  57655 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  57656     defined(BCM_56450_B1)
  57657     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_4_BCM56450_A0r */
  57658         soc_block_list[85],
  57659         soc_genreg,
  57660         1,
  57661         0,
  57662         0x2012a00,
  57663         0,
  57664         0,
  57665         2,
  57666         soc_LLS_MEM_DEBUG_L1_4_BCM56450_A0r_fields,
  57667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57668         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  57669         -1,
  57670         -1,
  57671     },
  57672 #endif /* chips */
  57673 
  57674 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57675     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_5_BCM56260_A0r */
  57676         soc_block_list[85],
  57677         soc_genreg,
  57678         1,
  57679         0,
  57680         0x200ad00,
  57681         0,
  57682         0,
  57683         1,
  57684         soc_LLS_MEM_DEBUG_L1_5_BCM56260_A0r_fields,
  57685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57686         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57687         -1,
  57688         -1,
  57689     },
  57690 #endif /* chips */
  57691 
  57692 #if defined(BCM_56270_A0)
  57693     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_5_BCM56270_A0r */
  57694         soc_block_list[85],
  57695         soc_genreg,
  57696         1,
  57697         0,
  57698         0x2009400,
  57699         0,
  57700         0,
  57701         1,
  57702         soc_LLS_MEM_DEBUG_L1_5_BCM56270_A0r_fields,
  57703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57704         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57705         -1,
  57706         -1,
  57707     },
  57708 #endif /* chips */
  57709 
  57710 #if defined(BCM_56440_B0)
  57711     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_5_BCM56440_B0r */
  57712         soc_block_list[85],
  57713         soc_genreg,
  57714         1,
  57715         0,
  57716         0x80054,
  57717         0,
  57718         0,
  57719         1,
  57720         soc_LLS_MEM_DEBUG_L1_5r_fields,
  57721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57722         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57723         -1,
  57724         -1,
  57725     },
  57726 #endif /* chips */
  57727 
  57728 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  57729     defined(BCM_56450_B1)
  57730     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_5_BCM56450_A0r */
  57731         soc_block_list[85],
  57732         soc_genreg,
  57733         1,
  57734         0,
  57735         0x2012b00,
  57736         0,
  57737         0,
  57738         1,
  57739         soc_LLS_MEM_DEBUG_L1_5_BCM56450_A0r_fields,
  57740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57741         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57742         -1,
  57743         -1,
  57744     },
  57745 #endif /* chips */
  57746 
  57747 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  57748     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_5_BCM56560_A0r */
  57749         soc_block_list[4],
  57750         soc_genreg,
  57751         1,
  57752         0,
  57753         0x62005a00,
  57754         0,
  57755         0,
  57756         1,
  57757         soc_LLS_MEM_DEBUG_L1_5_BCM56560_A0r_fields,
  57758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57759         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  57760         -1,
  57761         -1,
  57762     },
  57763 #endif /* chips */
  57764 
  57765 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57766     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_6_BCM56260_A0r */
  57767         soc_block_list[85],
  57768         soc_genreg,
  57769         1,
  57770         0,
  57771         0x200ae00,
  57772         0,
  57773         0,
  57774         1,
  57775         soc_LLS_MEM_DEBUG_L1_6_BCM56260_A0r_fields,
  57776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57777         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57778         -1,
  57779         -1,
  57780     },
  57781 #endif /* chips */
  57782 
  57783 #if defined(BCM_56270_A0)
  57784     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_6_BCM56270_A0r */
  57785         soc_block_list[85],
  57786         soc_genreg,
  57787         1,
  57788         0,
  57789         0x2009500,
  57790         0,
  57791         0,
  57792         1,
  57793         soc_LLS_MEM_DEBUG_L1_6_BCM56270_A0r_fields,
  57794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57795         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57796         -1,
  57797         -1,
  57798     },
  57799 #endif /* chips */
  57800 
  57801 #if defined(BCM_56440_B0)
  57802     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_6_BCM56440_B0r */
  57803         soc_block_list[85],
  57804         soc_genreg,
  57805         1,
  57806         0,
  57807         0x80055,
  57808         0,
  57809         0,
  57810         1,
  57811         soc_LLS_MEM_DEBUG_L1_6r_fields,
  57812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57813         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57814         -1,
  57815         -1,
  57816     },
  57817 #endif /* chips */
  57818 
  57819 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  57820     defined(BCM_56450_B1)
  57821     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_6_BCM56450_A0r */
  57822         soc_block_list[85],
  57823         soc_genreg,
  57824         1,
  57825         0,
  57826         0x2012c00,
  57827         0,
  57828         0,
  57829         1,
  57830         soc_LLS_MEM_L1_TM_5r_fields,
  57831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57832         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57833         -1,
  57834         -1,
  57835     },
  57836 #endif /* chips */
  57837 
  57838 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  57839     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_6_BCM56560_A0r */
  57840         soc_block_list[4],
  57841         soc_genreg,
  57842         1,
  57843         0,
  57844         0x62005b00,
  57845         0,
  57846         0,
  57847         2,
  57848         soc_LLS_MEM_DEBUG_L1_6_BCM56560_A0r_fields,
  57849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57850         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  57851         -1,
  57852         -1,
  57853     },
  57854 #endif /* chips */
  57855 
  57856 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57857     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_7_BCM56260_A0r */
  57858         soc_block_list[85],
  57859         soc_genreg,
  57860         1,
  57861         0,
  57862         0x200af00,
  57863         0,
  57864         0,
  57865         1,
  57866         soc_LLS_MEM_DEBUG_L1_7_BCM56260_A0r_fields,
  57867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57868         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57869         -1,
  57870         -1,
  57871     },
  57872 #endif /* chips */
  57873 
  57874 #if defined(BCM_56270_A0)
  57875     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_7_BCM56270_A0r */
  57876         soc_block_list[85],
  57877         soc_genreg,
  57878         1,
  57879         0,
  57880         0x2009600,
  57881         0,
  57882         0,
  57883         1,
  57884         soc_LLS_MEM_DEBUG_L1_7_BCM56270_A0r_fields,
  57885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57886         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57887         -1,
  57888         -1,
  57889     },
  57890 #endif /* chips */
  57891 
  57892 #if defined(BCM_56440_B0)
  57893     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_7_BCM56440_B0r */
  57894         soc_block_list[85],
  57895         soc_genreg,
  57896         1,
  57897         0,
  57898         0x80056,
  57899         0,
  57900         0,
  57901         3,
  57902         soc_LLS_MEM_DEBUG_L1_7r_fields,
  57903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57904         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  57905         -1,
  57906         -1,
  57907     },
  57908 #endif /* chips */
  57909 
  57910 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  57911     defined(BCM_56450_B1)
  57912     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_7_BCM56450_A0r */
  57913         soc_block_list[85],
  57914         soc_genreg,
  57915         1,
  57916         0,
  57917         0x2012d00,
  57918         0,
  57919         0,
  57920         1,
  57921         soc_LLS_MEM_DEBUG_L1_7_BCM56450_A0r_fields,
  57922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57923         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57924         -1,
  57925         -1,
  57926     },
  57927 #endif /* chips */
  57928 
  57929 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  57930     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_7_BCM56560_A0r */
  57931         soc_block_list[4],
  57932         soc_genreg,
  57933         1,
  57934         0,
  57935         0x62005c00,
  57936         0,
  57937         0,
  57938         1,
  57939         soc_LLS_MEM_DEBUG_L1_7_BCM56560_A0r_fields,
  57940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57941         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  57942         -1,
  57943         -1,
  57944     },
  57945 #endif /* chips */
  57946 
  57947 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57948     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_8_BCM56260_A0r */
  57949         soc_block_list[85],
  57950         soc_genreg,
  57951         1,
  57952         0,
  57953         0x200b000,
  57954         0,
  57955         0,
  57956         1,
  57957         soc_LLS_MEM_DEBUG_L1_8_BCM56260_A0r_fields,
  57958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57959         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  57960         -1,
  57961         -1,
  57962     },
  57963 #endif /* chips */
  57964 
  57965 #if defined(BCM_56270_A0)
  57966     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_8_BCM56270_A0r */
  57967         soc_block_list[85],
  57968         soc_genreg,
  57969         1,
  57970         0,
  57971         0x2009700,
  57972         0,
  57973         0,
  57974         1,
  57975         soc_LLS_MEM_DEBUG_L1_8_BCM56270_A0r_fields,
  57976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57977         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  57978         -1,
  57979         -1,
  57980     },
  57981 #endif /* chips */
  57982 
  57983 #if defined(BCM_56440_B0)
  57984     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_8_BCM56440_B0r */
  57985         soc_block_list[85],
  57986         soc_genreg,
  57987         1,
  57988         0,
  57989         0x80057,
  57990         0,
  57991         0,
  57992         2,
  57993         soc_LLS_MEM_DEBUG_L1_8r_fields,
  57994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57995         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  57996         -1,
  57997         -1,
  57998     },
  57999 #endif /* chips */
  58000 
  58001 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  58002     defined(BCM_56450_B1)
  58003     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_8_BCM56450_A0r */
  58004         soc_block_list[85],
  58005         soc_genreg,
  58006         1,
  58007         0,
  58008         0x2012e00,
  58009         0,
  58010         0,
  58011         2,
  58012         soc_LLS_MEM_DEBUG_L1_8_BCM56450_A0r_fields,
  58013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58014         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58015         -1,
  58016         -1,
  58017     },
  58018 #endif /* chips */
  58019 
  58020 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58021     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_ACT_MINr */
  58022         soc_block_list[4],
  58023         soc_genreg,
  58024         1,
  58025         0,
  58026         0x62006900,
  58027         0,
  58028         0,
  58029         1,
  58030         soc_LLS_MEM_DEBUG_L1_ACT_MINr_fields,
  58031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58032         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58033         -1,
  58034         -1,
  58035     },
  58036 #endif /* chips */
  58037 
  58038 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58039     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_ACT_SHAPERr */
  58040         soc_block_list[4],
  58041         soc_genreg,
  58042         1,
  58043         0,
  58044         0x62006800,
  58045         0,
  58046         0,
  58047         1,
  58048         soc_LLS_MEM_DEBUG_L1_ACT_SHAPERr_fields,
  58049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58050         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58051         -1,
  58052         -1,
  58053     },
  58054 #endif /* chips */
  58055 
  58056 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58057     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_ACT_XONr */
  58058         soc_block_list[4],
  58059         soc_genreg,
  58060         1,
  58061         0,
  58062         0x62006a00,
  58063         0,
  58064         0,
  58065         1,
  58066         soc_LLS_MEM_DEBUG_L1_ACT_XONr_fields,
  58067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58068         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58069         -1,
  58070         -1,
  58071     },
  58072 #endif /* chips */
  58073 
  58074 #if defined(BCM_56440_A0)
  58075     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_ERRORr */
  58076         soc_block_list[85],
  58077         soc_genreg,
  58078         1,
  58079         0,
  58080         0x8005b,
  58081         0,
  58082         0,
  58083         1,
  58084         soc_LLS_MEM_DEBUG_L1_ERRORr_fields,
  58085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58086         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58087         -1,
  58088         -1,
  58089     },
  58090 #endif /* chips */
  58091 
  58092 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  58093     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_ERROR_BCM56260_A0r */
  58094         soc_block_list[85],
  58095         soc_genreg,
  58096         1,
  58097         0,
  58098         0x200ba00,
  58099         0,
  58100         0,
  58101         1,
  58102         soc_LLS_MEM_DEBUG_L1_ERROR_BCM56260_A0r_fields,
  58103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58104         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  58105         -1,
  58106         -1,
  58107     },
  58108 #endif /* chips */
  58109 
  58110 #if defined(BCM_56270_A0)
  58111     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_ERROR_BCM56270_A0r */
  58112         soc_block_list[85],
  58113         soc_genreg,
  58114         1,
  58115         0,
  58116         0x200a100,
  58117         0,
  58118         0,
  58119         1,
  58120         soc_LLS_MEM_DEBUG_L1_ERROR_BCM56270_A0r_fields,
  58121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58122         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  58123         -1,
  58124         -1,
  58125     },
  58126 #endif /* chips */
  58127 
  58128 #if defined(BCM_56440_B0)
  58129     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_ERROR_BCM56440_B0r */
  58130         soc_block_list[85],
  58131         soc_genreg,
  58132         1,
  58133         0,
  58134         0x80063,
  58135         0,
  58136         0,
  58137         2,
  58138         soc_LLS_MEM_DEBUG_L1_ERROR_BCM56440_B0r_fields,
  58139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58140         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58141         -1,
  58142         -1,
  58143     },
  58144 #endif /* chips */
  58145 
  58146 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  58147     defined(BCM_56450_B1)
  58148     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_ERROR_BCM56450_A0r */
  58149         soc_block_list[85],
  58150         soc_genreg,
  58151         1,
  58152         0,
  58153         0x2013c00,
  58154         0,
  58155         0,
  58156         1,
  58157         soc_LLS_MEM_DEBUG_L1_ERROR_BCM56450_A0r_fields,
  58158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58159         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58160         -1,
  58161         -1,
  58162     },
  58163 #endif /* chips */
  58164 
  58165 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58166     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_ERROR_BCM56560_A0r */
  58167         soc_block_list[4],
  58168         soc_genreg,
  58169         1,
  58170         0,
  58171         0x62006400,
  58172         0,
  58173         0,
  58174         1,
  58175         soc_LLS_MEM_DEBUG_L1_ERROR_BCM56560_A0r_fields,
  58176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58177         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58178         -1,
  58179         -1,
  58180     },
  58181 #endif /* chips */
  58182 
  58183 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58184     { /* SOC_REG_INT_LLS_MEM_DEBUG_L1_XOFFr */
  58185         soc_block_list[4],
  58186         soc_genreg,
  58187         1,
  58188         0,
  58189         0x62006600,
  58190         0,
  58191         0,
  58192         1,
  58193         soc_LLS_MEM_DEBUG_L1_XOFFr_fields,
  58194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58195         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58196         -1,
  58197         -1,
  58198     },
  58199 #endif /* chips */
  58200 
  58201 #if defined(BCM_56440_A0)
  58202     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1r */
  58203         soc_block_list[85],
  58204         soc_genreg,
  58205         1,
  58206         0,
  58207         0x80050,
  58208         0,
  58209         0,
  58210         3,
  58211         soc_LLS_MEM_DEBUG_L2_1r_fields,
  58212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58213         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  58214         -1,
  58215         -1,
  58216     },
  58217 #endif /* chips */
  58218 
  58219 #if defined(BCM_56440_A0)
  58220     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_2r */
  58221         soc_block_list[85],
  58222         soc_genreg,
  58223         1,
  58224         0,
  58225         0x80051,
  58226         0,
  58227         0,
  58228         1,
  58229         soc_LLS_MEM_DEBUG_L2_2r_fields,
  58230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58231         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58232         -1,
  58233         -1,
  58234     },
  58235 #endif /* chips */
  58236 
  58237 #if defined(BCM_56440_A0)
  58238     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_3r */
  58239         soc_block_list[85],
  58240         soc_genreg,
  58241         1,
  58242         0,
  58243         0x80052,
  58244         0,
  58245         0,
  58246         2,
  58247         soc_LLS_MEM_DEBUG_L2_3r_fields,
  58248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58249         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58250         -1,
  58251         -1,
  58252     },
  58253 #endif /* chips */
  58254 
  58255 #if defined(BCM_56440_A0)
  58256     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_4r */
  58257         soc_block_list[85],
  58258         soc_genreg,
  58259         1,
  58260         0,
  58261         0x80053,
  58262         0,
  58263         0,
  58264         2,
  58265         soc_LLS_MEM_DEBUG_L2_4r_fields,
  58266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58267         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58268         -1,
  58269         -1,
  58270     },
  58271 #endif /* chips */
  58272 
  58273 #if defined(BCM_56440_A0)
  58274     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_5r */
  58275         soc_block_list[85],
  58276         soc_genreg,
  58277         1,
  58278         0,
  58279         0x80054,
  58280         0,
  58281         0,
  58282         1,
  58283         soc_LLS_MEM_DEBUG_L2_5r_fields,
  58284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58285         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58286         -1,
  58287         -1,
  58288     },
  58289 #endif /* chips */
  58290 
  58291 #if defined(BCM_56440_A0)
  58292     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_6r */
  58293         soc_block_list[85],
  58294         soc_genreg,
  58295         1,
  58296         0,
  58297         0x80055,
  58298         0,
  58299         0,
  58300         2,
  58301         soc_LLS_MEM_DEBUG_L2_6r_fields,
  58302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58303         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58304         -1,
  58305         -1,
  58306     },
  58307 #endif /* chips */
  58308 
  58309 #if defined(BCM_56440_A0)
  58310     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_7r */
  58311         soc_block_list[85],
  58312         soc_genreg,
  58313         1,
  58314         0,
  58315         0x80056,
  58316         0,
  58317         0,
  58318         2,
  58319         soc_LLS_MEM_DEBUG_L2_7r_fields,
  58320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58321         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58322         -1,
  58323         -1,
  58324     },
  58325 #endif /* chips */
  58326 
  58327 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58328     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1Ar */
  58329         soc_block_list[4],
  58330         soc_genreg,
  58331         1,
  58332         0,
  58333         0x62005d00,
  58334         0,
  58335         0,
  58336         2,
  58337         soc_LLS_MEM_DEBUG_L2_1Ar_fields,
  58338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58339         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  58340         -1,
  58341         -1,
  58342     },
  58343 #endif /* chips */
  58344 
  58345 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  58346     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1A_BCM56260_A0r */
  58347         soc_block_list[85],
  58348         soc_genreg,
  58349         1,
  58350         0,
  58351         0x200b100,
  58352         0,
  58353         0,
  58354         1,
  58355         soc_LLS_MEM_DEBUG_L2_1A_BCM56260_A0r_fields,
  58356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58357         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58358         -1,
  58359         -1,
  58360     },
  58361 #endif /* chips */
  58362 
  58363 #if defined(BCM_56270_A0)
  58364     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1A_BCM56270_A0r */
  58365         soc_block_list[85],
  58366         soc_genreg,
  58367         1,
  58368         0,
  58369         0x2009800,
  58370         0,
  58371         0,
  58372         1,
  58373         soc_LLS_MEM_DEBUG_L2_1A_BCM56270_A0r_fields,
  58374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58375         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  58376         -1,
  58377         -1,
  58378     },
  58379 #endif /* chips */
  58380 
  58381 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  58382     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1Br */
  58383         soc_block_list[85],
  58384         soc_genreg,
  58385         1,
  58386         0,
  58387         0x200b200,
  58388         0,
  58389         0,
  58390         1,
  58391         soc_LLS_MEM_DEBUG_L2_1Br_fields,
  58392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58393         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  58394         -1,
  58395         -1,
  58396     },
  58397 #endif /* chips */
  58398 
  58399 #if defined(BCM_56270_A0)
  58400     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1B_BCM56270_A0r */
  58401         soc_block_list[85],
  58402         soc_genreg,
  58403         1,
  58404         0,
  58405         0x2009900,
  58406         0,
  58407         0,
  58408         1,
  58409         soc_LLS_MEM_DEBUG_L2_1B_BCM56270_A0r_fields,
  58410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58411         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  58412         -1,
  58413         -1,
  58414     },
  58415 #endif /* chips */
  58416 
  58417 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  58418     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1Cr */
  58419         soc_block_list[85],
  58420         soc_genreg,
  58421         1,
  58422         0,
  58423         0x200b300,
  58424         0,
  58425         0,
  58426         1,
  58427         soc_LLS_MEM_DEBUG_L2_1Cr_fields,
  58428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58429         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  58430         -1,
  58431         -1,
  58432     },
  58433 #endif /* chips */
  58434 
  58435 #if defined(BCM_56270_A0)
  58436     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1C_BCM56270_A0r */
  58437         soc_block_list[85],
  58438         soc_genreg,
  58439         1,
  58440         0,
  58441         0x2009a00,
  58442         0,
  58443         0,
  58444         1,
  58445         soc_LLS_MEM_DEBUG_L2_1C_BCM56270_A0r_fields,
  58446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58447         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  58448         -1,
  58449         -1,
  58450     },
  58451 #endif /* chips */
  58452 
  58453 #if defined(BCM_56440_B0)
  58454     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1_BCM56440_B0r */
  58455         soc_block_list[85],
  58456         soc_genreg,
  58457         1,
  58458         0,
  58459         0x80058,
  58460         0,
  58461         0,
  58462         3,
  58463         soc_LLS_MEM_DEBUG_L2_1r_fields,
  58464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58465         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  58466         -1,
  58467         -1,
  58468     },
  58469 #endif /* chips */
  58470 
  58471 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  58472     defined(BCM_56450_B1)
  58473     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_1_BCM56450_A0r */
  58474         soc_block_list[85],
  58475         soc_genreg,
  58476         1,
  58477         0,
  58478         0x2012f00,
  58479         0,
  58480         0,
  58481         3,
  58482         soc_LLS_MEM_DEBUG_L2_1_BCM56450_A0r_fields,
  58483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58484         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  58485         -1,
  58486         -1,
  58487     },
  58488 #endif /* chips */
  58489 
  58490 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58491     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_2Ar */
  58492         soc_block_list[4],
  58493         soc_genreg,
  58494         1,
  58495         0,
  58496         0x62005f00,
  58497         0,
  58498         0,
  58499         1,
  58500         soc_LLS_MEM_DEBUG_L2_2Ar_fields,
  58501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58502         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  58503         -1,
  58504         -1,
  58505     },
  58506 #endif /* chips */
  58507 
  58508 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  58509     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_2_BCM56260_A0r */
  58510         soc_block_list[85],
  58511         soc_genreg,
  58512         1,
  58513         0,
  58514         0x200b400,
  58515         0,
  58516         0,
  58517         1,
  58518         soc_LLS_MEM_DEBUG_L2_2_BCM56260_A0r_fields,
  58519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58520         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  58521         -1,
  58522         -1,
  58523     },
  58524 #endif /* chips */
  58525 
  58526 #if defined(BCM_56270_A0)
  58527     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_2_BCM56270_A0r */
  58528         soc_block_list[85],
  58529         soc_genreg,
  58530         1,
  58531         0,
  58532         0x2009b00,
  58533         0,
  58534         0,
  58535         1,
  58536         soc_LLS_MEM_DEBUG_L2_2_BCM56270_A0r_fields,
  58537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58538         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  58539         -1,
  58540         -1,
  58541     },
  58542 #endif /* chips */
  58543 
  58544 #if defined(BCM_56440_B0)
  58545     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_2_BCM56440_B0r */
  58546         soc_block_list[85],
  58547         soc_genreg,
  58548         1,
  58549         0,
  58550         0x80059,
  58551         0,
  58552         0,
  58553         1,
  58554         soc_LLS_MEM_DEBUG_L2_2r_fields,
  58555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58556         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58557         -1,
  58558         -1,
  58559     },
  58560 #endif /* chips */
  58561 
  58562 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  58563     defined(BCM_56450_B1)
  58564     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_2_BCM56450_A0r */
  58565         soc_block_list[85],
  58566         soc_genreg,
  58567         1,
  58568         0,
  58569         0x2013000,
  58570         0,
  58571         0,
  58572         1,
  58573         soc_LLS_MEM_L2_TM_2r_fields,
  58574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58575         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58576         -1,
  58577         -1,
  58578     },
  58579 #endif /* chips */
  58580 
  58581 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58582     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_2_BCM56560_A0r */
  58583         soc_block_list[4],
  58584         soc_genreg,
  58585         1,
  58586         0,
  58587         0x62005e00,
  58588         0,
  58589         0,
  58590         1,
  58591         soc_LLS_MEM_DEBUG_L2_2_BCM56560_A0r_fields,
  58592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58593         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  58594         -1,
  58595         -1,
  58596     },
  58597 #endif /* chips */
  58598 
  58599 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  58600     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_3_BCM56260_A0r */
  58601         soc_block_list[85],
  58602         soc_genreg,
  58603         1,
  58604         0,
  58605         0x200b500,
  58606         0,
  58607         0,
  58608         1,
  58609         soc_LLS_MEM_DEBUG_L2_3_BCM56260_A0r_fields,
  58610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58611         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  58612         -1,
  58613         -1,
  58614     },
  58615 #endif /* chips */
  58616 
  58617 #if defined(BCM_56270_A0)
  58618     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_3_BCM56270_A0r */
  58619         soc_block_list[85],
  58620         soc_genreg,
  58621         1,
  58622         0,
  58623         0x2009c00,
  58624         0,
  58625         0,
  58626         1,
  58627         soc_LLS_MEM_DEBUG_L2_3_BCM56270_A0r_fields,
  58628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58629         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  58630         -1,
  58631         -1,
  58632     },
  58633 #endif /* chips */
  58634 
  58635 #if defined(BCM_56440_B0)
  58636     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_3_BCM56440_B0r */
  58637         soc_block_list[85],
  58638         soc_genreg,
  58639         1,
  58640         0,
  58641         0x8005a,
  58642         0,
  58643         0,
  58644         2,
  58645         soc_LLS_MEM_DEBUG_L2_3r_fields,
  58646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58647         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58648         -1,
  58649         -1,
  58650     },
  58651 #endif /* chips */
  58652 
  58653 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  58654     defined(BCM_56450_B1)
  58655     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_3_BCM56450_A0r */
  58656         soc_block_list[85],
  58657         soc_genreg,
  58658         1,
  58659         0,
  58660         0x2013100,
  58661         0,
  58662         0,
  58663         1,
  58664         soc_LLS_MEM_DEBUG_L2_3_BCM56450_A0r_fields,
  58665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58666         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58667         -1,
  58668         -1,
  58669     },
  58670 #endif /* chips */
  58671 
  58672 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58673     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_3_BCM56560_A0r */
  58674         soc_block_list[4],
  58675         soc_genreg,
  58676         1,
  58677         0,
  58678         0x62006000,
  58679         0,
  58680         0,
  58681         1,
  58682         soc_LLS_MEM_DEBUG_L2_3_BCM56560_A0r_fields,
  58683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58684         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58685         -1,
  58686         -1,
  58687     },
  58688 #endif /* chips */
  58689 
  58690 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  58691     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_4_BCM56260_A0r */
  58692         soc_block_list[85],
  58693         soc_genreg,
  58694         1,
  58695         0,
  58696         0x200b600,
  58697         0,
  58698         0,
  58699         1,
  58700         soc_LLS_MEM_DEBUG_L2_4_BCM56260_A0r_fields,
  58701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58702         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  58703         -1,
  58704         -1,
  58705     },
  58706 #endif /* chips */
  58707 
  58708 #if defined(BCM_56270_A0)
  58709     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_4_BCM56270_A0r */
  58710         soc_block_list[85],
  58711         soc_genreg,
  58712         1,
  58713         0,
  58714         0x2009d00,
  58715         0,
  58716         0,
  58717         1,
  58718         soc_LLS_MEM_DEBUG_L2_4_BCM56270_A0r_fields,
  58719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58720         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  58721         -1,
  58722         -1,
  58723     },
  58724 #endif /* chips */
  58725 
  58726 #if defined(BCM_56440_B0)
  58727     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_4_BCM56440_B0r */
  58728         soc_block_list[85],
  58729         soc_genreg,
  58730         1,
  58731         0,
  58732         0x8005b,
  58733         0,
  58734         0,
  58735         2,
  58736         soc_LLS_MEM_DEBUG_L2_4r_fields,
  58737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58738         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58739         -1,
  58740         -1,
  58741     },
  58742 #endif /* chips */
  58743 
  58744 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  58745     defined(BCM_56450_B1)
  58746     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_4_BCM56450_A0r */
  58747         soc_block_list[85],
  58748         soc_genreg,
  58749         1,
  58750         0,
  58751         0x2013200,
  58752         0,
  58753         0,
  58754         2,
  58755         soc_LLS_MEM_DEBUG_L2_4_BCM56450_A0r_fields,
  58756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58757         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58758         -1,
  58759         -1,
  58760     },
  58761 #endif /* chips */
  58762 
  58763 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  58764     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_5_BCM56260_A0r */
  58765         soc_block_list[85],
  58766         soc_genreg,
  58767         1,
  58768         0,
  58769         0x200b700,
  58770         0,
  58771         0,
  58772         1,
  58773         soc_LLS_MEM_DEBUG_L2_5_BCM56260_A0r_fields,
  58774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58775         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  58776         -1,
  58777         -1,
  58778     },
  58779 #endif /* chips */
  58780 
  58781 #if defined(BCM_56270_A0)
  58782     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_5_BCM56270_A0r */
  58783         soc_block_list[85],
  58784         soc_genreg,
  58785         1,
  58786         0,
  58787         0x2009e00,
  58788         0,
  58789         0,
  58790         1,
  58791         soc_LLS_MEM_DEBUG_L2_5_BCM56270_A0r_fields,
  58792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58793         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  58794         -1,
  58795         -1,
  58796     },
  58797 #endif /* chips */
  58798 
  58799 #if defined(BCM_56440_B0)
  58800     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_5_BCM56440_B0r */
  58801         soc_block_list[85],
  58802         soc_genreg,
  58803         1,
  58804         0,
  58805         0x8005c,
  58806         0,
  58807         0,
  58808         1,
  58809         soc_LLS_MEM_DEBUG_L2_5r_fields,
  58810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58811         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58812         -1,
  58813         -1,
  58814     },
  58815 #endif /* chips */
  58816 
  58817 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  58818     defined(BCM_56450_B1)
  58819     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_5_BCM56450_A0r */
  58820         soc_block_list[85],
  58821         soc_genreg,
  58822         1,
  58823         0,
  58824         0x2013300,
  58825         0,
  58826         0,
  58827         1,
  58828         soc_LLS_MEM_DEBUG_L2_5_BCM56450_A0r_fields,
  58829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58830         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58831         -1,
  58832         -1,
  58833     },
  58834 #endif /* chips */
  58835 
  58836 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58837     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_5_BCM56560_A0r */
  58838         soc_block_list[4],
  58839         soc_genreg,
  58840         1,
  58841         0,
  58842         0x62006100,
  58843         0,
  58844         0,
  58845         1,
  58846         soc_LLS_MEM_DEBUG_L2_5_BCM56560_A0r_fields,
  58847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58848         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58849         -1,
  58850         -1,
  58851     },
  58852 #endif /* chips */
  58853 
  58854 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  58855     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_6_BCM56260_A0r */
  58856         soc_block_list[85],
  58857         soc_genreg,
  58858         1,
  58859         0,
  58860         0x200b800,
  58861         0,
  58862         0,
  58863         1,
  58864         soc_LLS_MEM_DEBUG_L2_6_BCM56260_A0r_fields,
  58865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58866         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  58867         -1,
  58868         -1,
  58869     },
  58870 #endif /* chips */
  58871 
  58872 #if defined(BCM_56270_A0)
  58873     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_6_BCM56270_A0r */
  58874         soc_block_list[85],
  58875         soc_genreg,
  58876         1,
  58877         0,
  58878         0x2009f00,
  58879         0,
  58880         0,
  58881         1,
  58882         soc_LLS_MEM_DEBUG_L2_6_BCM56270_A0r_fields,
  58883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58884         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  58885         -1,
  58886         -1,
  58887     },
  58888 #endif /* chips */
  58889 
  58890 #if defined(BCM_56440_B0)
  58891     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_6_BCM56440_B0r */
  58892         soc_block_list[85],
  58893         soc_genreg,
  58894         1,
  58895         0,
  58896         0x8005d,
  58897         0,
  58898         0,
  58899         2,
  58900         soc_LLS_MEM_DEBUG_L2_6r_fields,
  58901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58902         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58903         -1,
  58904         -1,
  58905     },
  58906 #endif /* chips */
  58907 
  58908 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  58909     defined(BCM_56450_B1)
  58910     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_6_BCM56450_A0r */
  58911         soc_block_list[85],
  58912         soc_genreg,
  58913         1,
  58914         0,
  58915         0x2013400,
  58916         0,
  58917         0,
  58918         2,
  58919         soc_LLS_MEM_DEBUG_L2_6_BCM56450_A0r_fields,
  58920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58921         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58922         -1,
  58923         -1,
  58924     },
  58925 #endif /* chips */
  58926 
  58927 #if defined(BCM_56440_B0)
  58928     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_7_BCM56440_B0r */
  58929         soc_block_list[85],
  58930         soc_genreg,
  58931         1,
  58932         0,
  58933         0x8005e,
  58934         0,
  58935         0,
  58936         2,
  58937         soc_LLS_MEM_DEBUG_L2_7r_fields,
  58938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58939         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58940         -1,
  58941         -1,
  58942     },
  58943 #endif /* chips */
  58944 
  58945 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  58946     defined(BCM_56450_B1)
  58947     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_7_BCM56450_A0r */
  58948         soc_block_list[85],
  58949         soc_genreg,
  58950         1,
  58951         0,
  58952         0x2013500,
  58953         0,
  58954         0,
  58955         2,
  58956         soc_LLS_MEM_DEBUG_L2_7_BCM56450_A0r_fields,
  58957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58958         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58959         -1,
  58960         -1,
  58961     },
  58962 #endif /* chips */
  58963 
  58964 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  58965     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_ENQr */
  58966         soc_block_list[4],
  58967         soc_genreg,
  58968         1,
  58969         0,
  58970         0x62006e00,
  58971         0,
  58972         0,
  58973         1,
  58974         soc_LLS_MEM_DEBUG_L2_ACT_ENQr_fields,
  58975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58976         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58977         -1,
  58978         -1,
  58979     },
  58980 #endif /* chips */
  58981 
  58982 #if defined(BCM_56440_A0)
  58983     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_MINr */
  58984         soc_block_list[85],
  58985         soc_genreg,
  58986         1,
  58987         0,
  58988         0x80058,
  58989         0,
  58990         0,
  58991         1,
  58992         soc_LLS_MEM_DEBUG_L2_ACT_MINr_fields,
  58993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58994         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58995         -1,
  58996         -1,
  58997     },
  58998 #endif /* chips */
  58999 
  59000 #if defined(BCM_56440_B0)
  59001     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_MIN_BCM56440_B0r */
  59002         soc_block_list[85],
  59003         soc_genreg,
  59004         1,
  59005         0,
  59006         0x80060,
  59007         0,
  59008         0,
  59009         1,
  59010         soc_LLS_MEM_DEBUG_L2_ACT_MINr_fields,
  59011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59012         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59013         -1,
  59014         -1,
  59015     },
  59016 #endif /* chips */
  59017 
  59018 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59019     defined(BCM_56450_B1)
  59020     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_MIN_BCM56450_A0r */
  59021         soc_block_list[85],
  59022         soc_genreg,
  59023         1,
  59024         0,
  59025         0x2013700,
  59026         0,
  59027         0,
  59028         1,
  59029         soc_LLS_MEM_DEBUG_L2_ACT_MIN_BCM56450_A0r_fields,
  59030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59031         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59032         -1,
  59033         -1,
  59034     },
  59035 #endif /* chips */
  59036 
  59037 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59038     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_MIN_BCM56560_A0r */
  59039         soc_block_list[4],
  59040         soc_genreg,
  59041         1,
  59042         0,
  59043         0x62006c00,
  59044         0,
  59045         0,
  59046         1,
  59047         soc_LLS_MEM_DEBUG_L2_ACT_MIN_BCM56560_A0r_fields,
  59048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59049         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59050         -1,
  59051         -1,
  59052     },
  59053 #endif /* chips */
  59054 
  59055 #if defined(BCM_56440_A0)
  59056     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_SHAPERr */
  59057         soc_block_list[85],
  59058         soc_genreg,
  59059         1,
  59060         0,
  59061         0x80057,
  59062         0,
  59063         0,
  59064         1,
  59065         soc_LLS_MEM_DEBUG_L2_ACT_SHAPERr_fields,
  59066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59067         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59068         -1,
  59069         -1,
  59070     },
  59071 #endif /* chips */
  59072 
  59073 #if defined(BCM_56440_B0)
  59074     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_SHAPER_BCM56440_B0r */
  59075         soc_block_list[85],
  59076         soc_genreg,
  59077         1,
  59078         0,
  59079         0x8005f,
  59080         0,
  59081         0,
  59082         1,
  59083         soc_LLS_MEM_DEBUG_L2_ACT_SHAPERr_fields,
  59084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59085         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59086         -1,
  59087         -1,
  59088     },
  59089 #endif /* chips */
  59090 
  59091 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59092     defined(BCM_56450_B1)
  59093     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_SHAPER_BCM56450_A0r */
  59094         soc_block_list[85],
  59095         soc_genreg,
  59096         1,
  59097         0,
  59098         0x2013600,
  59099         0,
  59100         0,
  59101         1,
  59102         soc_LLS_MEM_DEBUG_L2_ACT_SHAPER_BCM56450_A0r_fields,
  59103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59104         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59105         -1,
  59106         -1,
  59107     },
  59108 #endif /* chips */
  59109 
  59110 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59111     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_SHAPER_BCM56560_A0r */
  59112         soc_block_list[4],
  59113         soc_genreg,
  59114         1,
  59115         0,
  59116         0x62006b00,
  59117         0,
  59118         0,
  59119         1,
  59120         soc_LLS_MEM_DEBUG_L2_ACT_SHAPER_BCM56560_A0r_fields,
  59121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59122         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59123         -1,
  59124         -1,
  59125     },
  59126 #endif /* chips */
  59127 
  59128 #if defined(BCM_56440_A0)
  59129     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_XONr */
  59130         soc_block_list[85],
  59131         soc_genreg,
  59132         1,
  59133         0,
  59134         0x80059,
  59135         0,
  59136         0,
  59137         1,
  59138         soc_LLS_MEM_DEBUG_L2_ACT_XONr_fields,
  59139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59140         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59141         -1,
  59142         -1,
  59143     },
  59144 #endif /* chips */
  59145 
  59146 #if defined(BCM_56440_B0)
  59147     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_XON_BCM56440_B0r */
  59148         soc_block_list[85],
  59149         soc_genreg,
  59150         1,
  59151         0,
  59152         0x80061,
  59153         0,
  59154         0,
  59155         1,
  59156         soc_LLS_MEM_DEBUG_L2_ACT_XONr_fields,
  59157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59158         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59159         -1,
  59160         -1,
  59161     },
  59162 #endif /* chips */
  59163 
  59164 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59165     defined(BCM_56450_B1)
  59166     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_XON_BCM56450_A0r */
  59167         soc_block_list[85],
  59168         soc_genreg,
  59169         1,
  59170         0,
  59171         0x2013800,
  59172         0,
  59173         0,
  59174         1,
  59175         soc_LLS_MEM_DEBUG_L2_ACT_XON_BCM56450_A0r_fields,
  59176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59177         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59178         -1,
  59179         -1,
  59180     },
  59181 #endif /* chips */
  59182 
  59183 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59184     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ACT_XON_BCM56560_A0r */
  59185         soc_block_list[4],
  59186         soc_genreg,
  59187         1,
  59188         0,
  59189         0x62006d00,
  59190         0,
  59191         0,
  59192         1,
  59193         soc_LLS_MEM_DEBUG_L2_ACT_XON_BCM56560_A0r_fields,
  59194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59195         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59196         -1,
  59197         -1,
  59198     },
  59199 #endif /* chips */
  59200 
  59201 #if defined(BCM_56440_A0)
  59202     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ERRORr */
  59203         soc_block_list[85],
  59204         soc_genreg,
  59205         1,
  59206         0,
  59207         0x8005c,
  59208         0,
  59209         0,
  59210         1,
  59211         soc_LLS_MEM_DEBUG_L2_ERRORr_fields,
  59212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59213         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59214         -1,
  59215         -1,
  59216     },
  59217 #endif /* chips */
  59218 
  59219 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  59220     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ERROR_BCM56260_A0r */
  59221         soc_block_list[85],
  59222         soc_genreg,
  59223         1,
  59224         0,
  59225         0x200bb00,
  59226         0,
  59227         0,
  59228         1,
  59229         soc_LLS_MEM_DEBUG_L2_ERROR_BCM56260_A0r_fields,
  59230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59231         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  59232         -1,
  59233         -1,
  59234     },
  59235 #endif /* chips */
  59236 
  59237 #if defined(BCM_56270_A0)
  59238     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ERROR_BCM56270_A0r */
  59239         soc_block_list[85],
  59240         soc_genreg,
  59241         1,
  59242         0,
  59243         0x200a200,
  59244         0,
  59245         0,
  59246         1,
  59247         soc_LLS_MEM_DEBUG_L2_ERROR_BCM56270_A0r_fields,
  59248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59249         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  59250         -1,
  59251         -1,
  59252     },
  59253 #endif /* chips */
  59254 
  59255 #if defined(BCM_56440_B0)
  59256     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ERROR_BCM56440_B0r */
  59257         soc_block_list[85],
  59258         soc_genreg,
  59259         1,
  59260         0,
  59261         0x80064,
  59262         0,
  59263         0,
  59264         2,
  59265         soc_LLS_MEM_DEBUG_L2_ERROR_BCM56440_B0r_fields,
  59266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59267         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  59268         -1,
  59269         -1,
  59270     },
  59271 #endif /* chips */
  59272 
  59273 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59274     defined(BCM_56450_B1)
  59275     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ERROR_BCM56450_A0r */
  59276         soc_block_list[85],
  59277         soc_genreg,
  59278         1,
  59279         0,
  59280         0x2013d00,
  59281         0,
  59282         0,
  59283         1,
  59284         soc_LLS_MEM_DEBUG_L2_ERROR_BCM56450_A0r_fields,
  59285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59286         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59287         -1,
  59288         -1,
  59289     },
  59290 #endif /* chips */
  59291 
  59292 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59293     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_ERROR_BCM56560_A0r */
  59294         soc_block_list[4],
  59295         soc_genreg,
  59296         1,
  59297         0,
  59298         0x62006500,
  59299         0,
  59300         0,
  59301         1,
  59302         soc_LLS_MEM_DEBUG_L2_ERROR_BCM56560_A0r_fields,
  59303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59304         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59305         -1,
  59306         -1,
  59307     },
  59308 #endif /* chips */
  59309 
  59310 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59311     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_SHAPER_STATE_MAXr */
  59312         soc_block_list[4],
  59313         soc_genreg,
  59314         1,
  59315         0,
  59316         0x62006f00,
  59317         0,
  59318         0,
  59319         1,
  59320         soc_LLS_MEM_DEBUG_L2_SHAPER_STATE_MAXr_fields,
  59321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59322         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59323         -1,
  59324         -1,
  59325     },
  59326 #endif /* chips */
  59327 
  59328 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59329     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_SHAPER_STATE_MINr */
  59330         soc_block_list[4],
  59331         soc_genreg,
  59332         1,
  59333         0,
  59334         0x62007000,
  59335         0,
  59336         0,
  59337         1,
  59338         soc_LLS_MEM_DEBUG_L2_SHAPER_STATE_MINr_fields,
  59339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59340         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59341         -1,
  59342         -1,
  59343     },
  59344 #endif /* chips */
  59345 
  59346 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59347     { /* SOC_REG_INT_LLS_MEM_DEBUG_L2_XOFFr */
  59348         soc_block_list[4],
  59349         soc_genreg,
  59350         1,
  59351         0,
  59352         0x62006700,
  59353         0,
  59354         0,
  59355         1,
  59356         soc_LLS_MEM_DEBUG_L2_XOFFr_fields,
  59357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59358         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59359         -1,
  59360         -1,
  59361     },
  59362 #endif /* chips */
  59363 
  59364 #if defined(BCM_56440_A0)
  59365     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT1r */
  59366         soc_block_list[85],
  59367         soc_genreg,
  59368         1,
  59369         0,
  59370         0x8003b,
  59371         0,
  59372         0,
  59373         1,
  59374         soc_LLS_MEM_DEBUG_PORT1r_fields,
  59375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59376         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59377         -1,
  59378         -1,
  59379     },
  59380 #endif /* chips */
  59381 
  59382 #if defined(BCM_56440_A0)
  59383     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT4r */
  59384         soc_block_list[85],
  59385         soc_genreg,
  59386         1,
  59387         0,
  59388         0x8003c,
  59389         0,
  59390         0,
  59391         1,
  59392         soc_LLS_MEM_DEBUG_PORT4r_fields,
  59393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59394         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  59395         -1,
  59396         -1,
  59397     },
  59398 #endif /* chips */
  59399 
  59400 #if defined(BCM_56440_B0)
  59401     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT1_BCM56440_B0r */
  59402         soc_block_list[85],
  59403         soc_genreg,
  59404         1,
  59405         0,
  59406         0x80043,
  59407         0,
  59408         0,
  59409         1,
  59410         soc_LLS_MEM_DEBUG_PORT1r_fields,
  59411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59412         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59413         -1,
  59414         -1,
  59415     },
  59416 #endif /* chips */
  59417 
  59418 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59419     defined(BCM_56450_B1)
  59420     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT1_BCM56450_A0r */
  59421         soc_block_list[85],
  59422         soc_genreg,
  59423         1,
  59424         0,
  59425         0x2011800,
  59426         0,
  59427         0,
  59428         1,
  59429         soc_LLS_MEM_DEBUG_PORT1_BCM56450_A0r_fields,
  59430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59431         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59432         -1,
  59433         -1,
  59434     },
  59435 #endif /* chips */
  59436 
  59437 #if defined(BCM_56440_B0)
  59438     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT4_BCM56440_B0r */
  59439         soc_block_list[85],
  59440         soc_genreg,
  59441         1,
  59442         0,
  59443         0x80044,
  59444         0,
  59445         0,
  59446         1,
  59447         soc_LLS_MEM_DEBUG_PORT4r_fields,
  59448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59449         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  59450         -1,
  59451         -1,
  59452     },
  59453 #endif /* chips */
  59454 
  59455 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59456     defined(BCM_56450_B1)
  59457     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT4_BCM56450_A0r */
  59458         soc_block_list[85],
  59459         soc_genreg,
  59460         1,
  59461         0,
  59462         0x2011900,
  59463         0,
  59464         0,
  59465         1,
  59466         soc_ES_PIPE0_LLS_MEM_PORT_TM_1r_fields,
  59467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59468         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59469         -1,
  59470         -1,
  59471     },
  59472 #endif /* chips */
  59473 
  59474 #if defined(BCM_56440_A0)
  59475     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT_TDMr */
  59476         soc_block_list[85],
  59477         soc_genreg,
  59478         1,
  59479         0,
  59480         0x8003a,
  59481         0,
  59482         0,
  59483         1,
  59484         soc_LLS_MEM_DEBUG_PORT_TDMr_fields,
  59485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59486         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  59487         -1,
  59488         -1,
  59489     },
  59490 #endif /* chips */
  59491 
  59492 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  59493     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT_TDM_BCM56260_A0r */
  59494         soc_block_list[85],
  59495         soc_genreg,
  59496         1,
  59497         0,
  59498         0x2009800,
  59499         0,
  59500         0,
  59501         1,
  59502         soc_LLS_MEM_DEBUG_PORT_TDM_BCM56260_A0r_fields,
  59503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59504         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59505         -1,
  59506         -1,
  59507     },
  59508 #endif /* chips */
  59509 
  59510 #if defined(BCM_56270_A0)
  59511     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT_TDM_BCM56270_A0r */
  59512         soc_block_list[85],
  59513         soc_genreg,
  59514         1,
  59515         0,
  59516         0x2007f00,
  59517         0,
  59518         0,
  59519         1,
  59520         soc_LLS_MEM_DEBUG_PORT_TDM_BCM56270_A0r_fields,
  59521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59522         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  59523         -1,
  59524         -1,
  59525     },
  59526 #endif /* chips */
  59527 
  59528 #if defined(BCM_56440_B0)
  59529     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT_TDM_BCM56440_B0r */
  59530         soc_block_list[85],
  59531         soc_genreg,
  59532         1,
  59533         0,
  59534         0x80042,
  59535         0,
  59536         0,
  59537         1,
  59538         soc_LLS_MEM_DEBUG_PORT_TDMr_fields,
  59539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59540         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  59541         -1,
  59542         -1,
  59543     },
  59544 #endif /* chips */
  59545 
  59546 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59547     defined(BCM_56450_B1)
  59548     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT_TDM_BCM56450_A0r */
  59549         soc_block_list[85],
  59550         soc_genreg,
  59551         1,
  59552         0,
  59553         0x2011700,
  59554         0,
  59555         0,
  59556         1,
  59557         soc_LLS_MEM_PORT_TM_0r_fields,
  59558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59559         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  59560         -1,
  59561         -1,
  59562     },
  59563 #endif /* chips */
  59564 
  59565 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59566     { /* SOC_REG_INT_LLS_MEM_DEBUG_PORT_WERR_MAX_SCr */
  59567         soc_block_list[4],
  59568         soc_genreg,
  59569         1,
  59570         0,
  59571         0x62004400,
  59572         0,
  59573         0,
  59574         1,
  59575         soc_LLS_MEM_DEBUG_PORT_WERR_MAX_SCr_fields,
  59576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59577         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  59578         -1,
  59579         -1,
  59580     },
  59581 #endif /* chips */
  59582 
  59583 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59584     defined(BCM_56450_B1)
  59585     { /* SOC_REG_INT_LLS_MEM_DEBUG_S0_0r */
  59586         soc_block_list[85],
  59587         soc_genreg,
  59588         1,
  59589         0,
  59590         0x2011a00,
  59591         0,
  59592         0,
  59593         2,
  59594         soc_LLS_MEM_DEBUG_S0_0r_fields,
  59595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59596         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  59597         -1,
  59598         -1,
  59599     },
  59600 #endif /* chips */
  59601 
  59602 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59603     defined(BCM_56450_B1)
  59604     { /* SOC_REG_INT_LLS_MEM_DEBUG_S0_ERRORr */
  59605         soc_block_list[85],
  59606         soc_genreg,
  59607         1,
  59608         0,
  59609         0x2013900,
  59610         0,
  59611         0,
  59612         1,
  59613         soc_LLS_MEM_DEBUG_S0_ERRORr_fields,
  59614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59615         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59616         -1,
  59617         -1,
  59618     },
  59619 #endif /* chips */
  59620 
  59621 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59622     defined(BCM_56450_B1)
  59623     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_0r */
  59624         soc_block_list[85],
  59625         soc_genreg,
  59626         1,
  59627         0,
  59628         0x2011b00,
  59629         0,
  59630         0,
  59631         3,
  59632         soc_LLS_MEM_DEBUG_S1_0r_fields,
  59633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59634         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  59635         -1,
  59636         -1,
  59637     },
  59638 #endif /* chips */
  59639 
  59640 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59641     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_1r */
  59642         soc_block_list[4],
  59643         soc_genreg,
  59644         1,
  59645         0,
  59646         0x62004500,
  59647         0,
  59648         0,
  59649         1,
  59650         soc_LLS_MEM_DEBUG_S1_1r_fields,
  59651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59652         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  59653         -1,
  59654         -1,
  59655     },
  59656 #endif /* chips */
  59657 
  59658 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59659     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_2r */
  59660         soc_block_list[4],
  59661         soc_genreg,
  59662         1,
  59663         0,
  59664         0x62004600,
  59665         0,
  59666         0,
  59667         1,
  59668         soc_LLS_MEM_DEBUG_S1_2r_fields,
  59669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59670         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59671         -1,
  59672         -1,
  59673     },
  59674 #endif /* chips */
  59675 
  59676 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59677     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_3r */
  59678         soc_block_list[4],
  59679         soc_genreg,
  59680         1,
  59681         0,
  59682         0x62004700,
  59683         0,
  59684         0,
  59685         1,
  59686         soc_LLS_MEM_DEBUG_S1_3r_fields,
  59687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59688         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59689         -1,
  59690         -1,
  59691     },
  59692 #endif /* chips */
  59693 
  59694 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59695     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_4r */
  59696         soc_block_list[4],
  59697         soc_genreg,
  59698         1,
  59699         0,
  59700         0x62004800,
  59701         0,
  59702         0,
  59703         1,
  59704         soc_LLS_MEM_DEBUG_S1_4r_fields,
  59705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59706         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  59707         -1,
  59708         -1,
  59709     },
  59710 #endif /* chips */
  59711 
  59712 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59713     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_5r */
  59714         soc_block_list[4],
  59715         soc_genreg,
  59716         1,
  59717         0,
  59718         0x62004900,
  59719         0,
  59720         0,
  59721         1,
  59722         soc_LLS_MEM_DEBUG_S1_5r_fields,
  59723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59724         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59725         -1,
  59726         -1,
  59727     },
  59728 #endif /* chips */
  59729 
  59730 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59731     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_6r */
  59732         soc_block_list[4],
  59733         soc_genreg,
  59734         1,
  59735         0,
  59736         0x62004a00,
  59737         0,
  59738         0,
  59739         1,
  59740         soc_LLS_MEM_DEBUG_S1_6r_fields,
  59741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59742         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  59743         -1,
  59744         -1,
  59745     },
  59746 #endif /* chips */
  59747 
  59748 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59749     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_7r */
  59750         soc_block_list[4],
  59751         soc_genreg,
  59752         1,
  59753         0,
  59754         0x62004b00,
  59755         0,
  59756         0,
  59757         1,
  59758         soc_LLS_MEM_DEBUG_S1_7r_fields,
  59759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59760         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  59761         -1,
  59762         -1,
  59763     },
  59764 #endif /* chips */
  59765 
  59766 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  59767     defined(BCM_56450_B1)
  59768     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_ERRORr */
  59769         soc_block_list[85],
  59770         soc_genreg,
  59771         1,
  59772         0,
  59773         0x2013a00,
  59774         0,
  59775         0,
  59776         1,
  59777         soc_LLS_MEM_DEBUG_S1_ERRORr_fields,
  59778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59779         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59780         -1,
  59781         -1,
  59782     },
  59783 #endif /* chips */
  59784 
  59785 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  59786     { /* SOC_REG_INT_LLS_MEM_DEBUG_S1_ERROR_BCM56560_A0r */
  59787         soc_block_list[4],
  59788         soc_genreg,
  59789         1,
  59790         0,
  59791         0x62006200,
  59792         0,
  59793         0,
  59794         1,
  59795         soc_LLS_MEM_DEBUG_S1_ERROR_BCM56560_A0r_fields,
  59796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59797         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59798         -1,
  59799         -1,
  59800     },
  59801 #endif /* chips */
  59802 
  59803 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59804     { /* SOC_REG_INT_LLS_MEM_L0_TM_0r */
  59805         soc_block_list[4],
  59806         soc_genreg,
  59807         1,
  59808         0,
  59809         0x5a005c00,
  59810         0,
  59811         0,
  59812         1,
  59813         soc_LLS_MEM_L0_TM_0r_fields,
  59814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59815         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59816         -1,
  59817         -1,
  59818     },
  59819 #endif /* chips */
  59820 
  59821 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59822     { /* SOC_REG_INT_LLS_MEM_L0_TM_1r */
  59823         soc_block_list[4],
  59824         soc_genreg,
  59825         1,
  59826         0,
  59827         0x5a005d00,
  59828         0,
  59829         0,
  59830         1,
  59831         soc_LLS_MEM_L0_TM_1r_fields,
  59832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59833         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59834         -1,
  59835         -1,
  59836     },
  59837 #endif /* chips */
  59838 
  59839 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59840     { /* SOC_REG_INT_LLS_MEM_L0_TM_2r */
  59841         soc_block_list[4],
  59842         soc_genreg,
  59843         1,
  59844         0,
  59845         0x5a005e00,
  59846         0,
  59847         0,
  59848         1,
  59849         soc_LLS_MEM_L0_TM_2r_fields,
  59850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59851         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59852         -1,
  59853         -1,
  59854     },
  59855 #endif /* chips */
  59856 
  59857 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59858     { /* SOC_REG_INT_LLS_MEM_L0_TM_3r */
  59859         soc_block_list[4],
  59860         soc_genreg,
  59861         1,
  59862         0,
  59863         0x5a005f00,
  59864         0,
  59865         0,
  59866         1,
  59867         soc_LLS_MEM_L0_TM_3r_fields,
  59868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59869         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59870         -1,
  59871         -1,
  59872     },
  59873 #endif /* chips */
  59874 
  59875 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59876     { /* SOC_REG_INT_LLS_MEM_L0_TM_4r */
  59877         soc_block_list[4],
  59878         soc_genreg,
  59879         1,
  59880         0,
  59881         0x5a006000,
  59882         0,
  59883         0,
  59884         1,
  59885         soc_LLS_MEM_L0_TM_4r_fields,
  59886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59887         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59888         -1,
  59889         -1,
  59890     },
  59891 #endif /* chips */
  59892 
  59893 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59894     { /* SOC_REG_INT_LLS_MEM_L0_TM_5r */
  59895         soc_block_list[4],
  59896         soc_genreg,
  59897         1,
  59898         0,
  59899         0x5a006100,
  59900         0,
  59901         0,
  59902         1,
  59903         soc_LLS_MEM_L0_TM_5r_fields,
  59904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59905         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59906         -1,
  59907         -1,
  59908     },
  59909 #endif /* chips */
  59910 
  59911 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59912     { /* SOC_REG_INT_LLS_MEM_L0_TM_6r */
  59913         soc_block_list[4],
  59914         soc_genreg,
  59915         1,
  59916         0,
  59917         0x5a006200,
  59918         0,
  59919         0,
  59920         3,
  59921         soc_LLS_MEM_L0_TM_6r_fields,
  59922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59923         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  59924         -1,
  59925         -1,
  59926     },
  59927 #endif /* chips */
  59928 
  59929 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59930     { /* SOC_REG_INT_LLS_MEM_L0_TM_7r */
  59931         soc_block_list[4],
  59932         soc_genreg,
  59933         1,
  59934         0,
  59935         0x5a006300,
  59936         0,
  59937         0,
  59938         1,
  59939         soc_LLS_MEM_L0_TM_7r_fields,
  59940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59941         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59942         -1,
  59943         -1,
  59944     },
  59945 #endif /* chips */
  59946 
  59947 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59948     { /* SOC_REG_INT_LLS_MEM_L0_TM_8r */
  59949         soc_block_list[4],
  59950         soc_genreg,
  59951         1,
  59952         0,
  59953         0x5a006400,
  59954         0,
  59955         0,
  59956         1,
  59957         soc_LLS_MEM_L0_TM_8r_fields,
  59958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59959         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  59960         -1,
  59961         -1,
  59962     },
  59963 #endif /* chips */
  59964 
  59965 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59966     { /* SOC_REG_INT_LLS_MEM_L0_TM_9r */
  59967         soc_block_list[4],
  59968         soc_genreg,
  59969         1,
  59970         0,
  59971         0x5a006500,
  59972         0,
  59973         0,
  59974         1,
  59975         soc_LLS_MEM_L0_TM_9r_fields,
  59976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59977         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59978         -1,
  59979         -1,
  59980     },
  59981 #endif /* chips */
  59982 
  59983 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  59984     { /* SOC_REG_INT_LLS_MEM_L1_TM_0r */
  59985         soc_block_list[4],
  59986         soc_genreg,
  59987         1,
  59988         0,
  59989         0x5a006600,
  59990         0,
  59991         0,
  59992         1,
  59993         soc_LLS_MEM_L1_TM_0r_fields,
  59994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59995         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  59996         -1,
  59997         -1,
  59998     },
  59999 #endif /* chips */
  60000 
  60001 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60002     { /* SOC_REG_INT_LLS_MEM_L1_TM_1r */
  60003         soc_block_list[4],
  60004         soc_genreg,
  60005         1,
  60006         0,
  60007         0x5a006700,
  60008         0,
  60009         0,
  60010         1,
  60011         soc_LLS_MEM_L1_TM_1r_fields,
  60012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60013         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60014         -1,
  60015         -1,
  60016     },
  60017 #endif /* chips */
  60018 
  60019 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60020     { /* SOC_REG_INT_LLS_MEM_L1_TM_2r */
  60021         soc_block_list[4],
  60022         soc_genreg,
  60023         1,
  60024         0,
  60025         0x5a006800,
  60026         0,
  60027         0,
  60028         1,
  60029         soc_LLS_MEM_L1_TM_2r_fields,
  60030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60031         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60032         -1,
  60033         -1,
  60034     },
  60035 #endif /* chips */
  60036 
  60037 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60038     { /* SOC_REG_INT_LLS_MEM_L1_TM_3r */
  60039         soc_block_list[4],
  60040         soc_genreg,
  60041         1,
  60042         0,
  60043         0x5a006900,
  60044         0,
  60045         0,
  60046         1,
  60047         soc_LLS_MEM_L1_TM_3r_fields,
  60048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60049         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  60050         -1,
  60051         -1,
  60052     },
  60053 #endif /* chips */
  60054 
  60055 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60056     { /* SOC_REG_INT_LLS_MEM_L1_TM_4r */
  60057         soc_block_list[4],
  60058         soc_genreg,
  60059         1,
  60060         0,
  60061         0x5a006a00,
  60062         0,
  60063         0,
  60064         1,
  60065         soc_LLS_MEM_L1_TM_4r_fields,
  60066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60067         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60068         -1,
  60069         -1,
  60070     },
  60071 #endif /* chips */
  60072 
  60073 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60074     { /* SOC_REG_INT_LLS_MEM_L1_TM_5r */
  60075         soc_block_list[4],
  60076         soc_genreg,
  60077         1,
  60078         0,
  60079         0x5a006b00,
  60080         0,
  60081         0,
  60082         1,
  60083         soc_LLS_MEM_L1_TM_5r_fields,
  60084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60085         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  60086         -1,
  60087         -1,
  60088     },
  60089 #endif /* chips */
  60090 
  60091 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60092     { /* SOC_REG_INT_LLS_MEM_L1_TM_6r */
  60093         soc_block_list[4],
  60094         soc_genreg,
  60095         1,
  60096         0,
  60097         0x5a006c00,
  60098         0,
  60099         0,
  60100         3,
  60101         soc_LLS_MEM_L1_TM_6r_fields,
  60102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60103         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  60104         -1,
  60105         -1,
  60106     },
  60107 #endif /* chips */
  60108 
  60109 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60110     { /* SOC_REG_INT_LLS_MEM_L1_TM_7r */
  60111         soc_block_list[4],
  60112         soc_genreg,
  60113         1,
  60114         0,
  60115         0x5a006d00,
  60116         0,
  60117         0,
  60118         1,
  60119         soc_LLS_MEM_L1_TM_7r_fields,
  60120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60121         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60122         -1,
  60123         -1,
  60124     },
  60125 #endif /* chips */
  60126 
  60127 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60128     { /* SOC_REG_INT_LLS_MEM_L1_TM_8r */
  60129         soc_block_list[4],
  60130         soc_genreg,
  60131         1,
  60132         0,
  60133         0x5a006e00,
  60134         0,
  60135         0,
  60136         1,
  60137         soc_LLS_MEM_L1_TM_8r_fields,
  60138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60139         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60140         -1,
  60141         -1,
  60142     },
  60143 #endif /* chips */
  60144 
  60145 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60146     { /* SOC_REG_INT_LLS_MEM_L1_TM_9r */
  60147         soc_block_list[4],
  60148         soc_genreg,
  60149         1,
  60150         0,
  60151         0x5a006f00,
  60152         0,
  60153         0,
  60154         1,
  60155         soc_LLS_MEM_L1_TM_5r_fields,
  60156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60157         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  60158         -1,
  60159         -1,
  60160     },
  60161 #endif /* chips */
  60162 
  60163 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60164     { /* SOC_REG_INT_LLS_MEM_L2_TM_0r */
  60165         soc_block_list[4],
  60166         soc_genreg,
  60167         1,
  60168         0,
  60169         0x5a007000,
  60170         0,
  60171         0,
  60172         1,
  60173         soc_LLS_MEM_L2_TM_0r_fields,
  60174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60175         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60176         -1,
  60177         -1,
  60178     },
  60179 #endif /* chips */
  60180 
  60181 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60182     { /* SOC_REG_INT_LLS_MEM_L2_TM_2r */
  60183         soc_block_list[4],
  60184         soc_genreg,
  60185         1,
  60186         0,
  60187         0x5a007100,
  60188         0,
  60189         0,
  60190         1,
  60191         soc_LLS_MEM_L2_TM_2r_fields,
  60192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60193         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  60194         -1,
  60195         -1,
  60196     },
  60197 #endif /* chips */
  60198 
  60199 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60200     { /* SOC_REG_INT_LLS_MEM_L2_TM_3r */
  60201         soc_block_list[4],
  60202         soc_genreg,
  60203         1,
  60204         0,
  60205         0x5a007200,
  60206         0,
  60207         0,
  60208         2,
  60209         soc_LLS_MEM_L2_TM_3r_fields,
  60210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60211         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60212         -1,
  60213         -1,
  60214     },
  60215 #endif /* chips */
  60216 
  60217 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60218     { /* SOC_REG_INT_LLS_MEM_L2_TM_4r */
  60219         soc_block_list[4],
  60220         soc_genreg,
  60221         1,
  60222         0,
  60223         0x5a007300,
  60224         0,
  60225         0,
  60226         1,
  60227         soc_LLS_MEM_L2_TM_4r_fields,
  60228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60229         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60230         -1,
  60231         -1,
  60232     },
  60233 #endif /* chips */
  60234 
  60235 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60236     { /* SOC_REG_INT_LLS_MEM_L2_TM_5r */
  60237         soc_block_list[4],
  60238         soc_genreg,
  60239         1,
  60240         0,
  60241         0x5a007400,
  60242         0,
  60243         0,
  60244         1,
  60245         soc_LLS_MEM_L2_TM_5r_fields,
  60246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60247         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60248         -1,
  60249         -1,
  60250     },
  60251 #endif /* chips */
  60252 
  60253 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60254     { /* SOC_REG_INT_LLS_MEM_L2_TM_6r */
  60255         soc_block_list[4],
  60256         soc_genreg,
  60257         1,
  60258         0,
  60259         0x5a007500,
  60260         0,
  60261         0,
  60262         1,
  60263         soc_LLS_MEM_L2_TM_2r_fields,
  60264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60265         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  60266         -1,
  60267         -1,
  60268     },
  60269 #endif /* chips */
  60270 
  60271 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60272     { /* SOC_REG_INT_LLS_MEM_PORT_TM_0r */
  60273         soc_block_list[4],
  60274         soc_genreg,
  60275         1,
  60276         0,
  60277         0x5a005a00,
  60278         0,
  60279         0,
  60280         1,
  60281         soc_LLS_MEM_PORT_TM_0r_fields,
  60282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60283         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60284         -1,
  60285         -1,
  60286     },
  60287 #endif /* chips */
  60288 
  60289 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60290     { /* SOC_REG_INT_LLS_MEM_PORT_TM_1r */
  60291         soc_block_list[4],
  60292         soc_genreg,
  60293         1,
  60294         0,
  60295         0x5a005b00,
  60296         0,
  60297         0,
  60298         1,
  60299         soc_LLS_MEM_PORT_TM_1r_fields,
  60300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60301         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  60302         -1,
  60303         -1,
  60304     },
  60305 #endif /* chips */
  60306 
  60307 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  60308     { /* SOC_REG_INT_LLS_MIN_CAP_CONFIGr */
  60309         soc_block_list[85],
  60310         soc_genreg,
  60311         1,
  60312         0,
  60313         0x8000a,
  60314         0,
  60315         0,
  60316         4,
  60317         soc_LLS_MIN_CAP_CONFIGr_fields,
  60318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60319         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  60320         -1,
  60321         -1,
  60322     },
  60323 #endif /* chips */
  60324 
  60325 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  60326     defined(BCM_56270_A0)
  60327     { /* SOC_REG_INT_LLS_MIN_CAP_CONFIG_BCM56260_A0r */
  60328         soc_block_list[85],
  60329         soc_genreg,
  60330         1,
  60331         0,
  60332         0x2000d00,
  60333         0,
  60334         0,
  60335         4,
  60336         soc_LLS_MIN_CAP_CONFIG_BCM56260_A0r_fields,
  60337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60338         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  60339         -1,
  60340         -1,
  60341     },
  60342 #endif /* chips */
  60343 
  60344 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  60345     defined(BCM_56450_B1)
  60346     { /* SOC_REG_INT_LLS_MIN_CAP_CONFIG_BCM56450_A0r */
  60347         soc_block_list[85],
  60348         soc_genreg,
  60349         1,
  60350         0,
  60351         0x2000d00,
  60352         0,
  60353         0,
  60354         4,
  60355         soc_LLS_MIN_CAP_CONFIG_BCM56450_A0r_fields,
  60356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60357         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  60358         -1,
  60359         -1,
  60360     },
  60361 #endif /* chips */
  60362 
  60363 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  60364     { /* SOC_REG_INT_LLS_MIN_CONFIGr */
  60365         soc_block_list[85],
  60366         soc_genreg,
  60367         1,
  60368         0,
  60369         0x80014,
  60370         0,
  60371         0,
  60372         9,
  60373         soc_LLS_MIN_CONFIGr_fields,
  60374         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  60375         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  60376         -1,
  60377         -1,
  60378     },
  60379 #endif /* chips */
  60380 
  60381 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  60382     defined(BCM_56270_A0)
  60383     { /* SOC_REG_INT_LLS_MIN_CONFIG_BCM56260_A0r */
  60384         soc_block_list[85],
  60385         soc_genreg,
  60386         1,
  60387         0,
  60388         0x2001900,
  60389         0,
  60390         0,
  60391         9,
  60392         soc_LLS_MIN_CONFIG_BCM56560_A0r_fields,
  60393         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  60394         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  60395         -1,
  60396         -1,
  60397     },
  60398 #endif /* chips */
  60399 
  60400 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  60401     defined(BCM_56450_B1)
  60402     { /* SOC_REG_INT_LLS_MIN_CONFIG_BCM56450_A0r */
  60403         soc_block_list[85],
  60404         soc_genreg,
  60405         1,
  60406         0,
  60407         0x2001800,
  60408         0,
  60409         0,
  60410         9,
  60411         soc_LLS_MIN_CONFIG_BCM56450_A0r_fields,
  60412         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  60413         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  60414         -1,
  60415         -1,
  60416     },
  60417 #endif /* chips */
  60418 
  60419 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  60420     { /* SOC_REG_INT_LLS_MIN_CONFIG_BCM56560_A0r */
  60421         soc_block_list[4],
  60422         soc_genreg,
  60423         1,
  60424         0,
  60425         0x62001300,
  60426         0,
  60427         0,
  60428         9,
  60429         soc_LLS_MIN_CONFIG_BCM56560_A0r_fields,
  60430         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  60431         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  60432         -1,
  60433         -1,
  60434     },
  60435 #endif /* chips */
  60436 
  60437 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  60438     { /* SOC_REG_INT_LLS_MIN_REFRESH_ENABLEr */
  60439         soc_block_list[85],
  60440         soc_genreg,
  60441         1,
  60442         0,
  60443         0x80015,
  60444         0,
  60445         0,
  60446         3,
  60447         soc_LLS_MIN_REFRESH_ENABLEr_fields,
  60448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60449         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  60450         -1,
  60451         -1,
  60452     },
  60453 #endif /* chips */
  60454 
  60455 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  60456     defined(BCM_56270_A0)
  60457     { /* SOC_REG_INT_LLS_MIN_REFRESH_ENABLE_BCM56260_A0r */
  60458         soc_block_list[85],
  60459         soc_genreg,
  60460         1,
  60461         0,
  60462         0x2001a00,
  60463         0,
  60464         0,
  60465         3,
  60466         soc_LLS_MIN_REFRESH_ENABLE_BCM56260_A0r_fields,
  60467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60468         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  60469         -1,
  60470         -1,
  60471     },
  60472 #endif /* chips */
  60473 
  60474 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  60475     defined(BCM_56450_B1)
  60476     { /* SOC_REG_INT_LLS_MIN_REFRESH_ENABLE_BCM56450_A0r */
  60477         soc_block_list[85],
  60478         soc_genreg,
  60479         1,
  60480         0,
  60481         0x2001900,
  60482         0,
  60483         0,
  60484         3,
  60485         soc_LLS_MIN_REFRESH_ENABLE_BCM56450_A0r_fields,
  60486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60487         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  60488         -1,
  60489         -1,
  60490     },
  60491 #endif /* chips */
  60492 
  60493 #if defined(BCM_56440_A0)
  60494     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1r */
  60495         soc_block_list[85],
  60496         soc_genreg,
  60497         1,
  60498         0,
  60499         0x8007b,
  60500         0,
  60501         0,
  60502         12,
  60503         soc_LLS_MISC_ECC_ERROR1r_fields,
  60504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60505         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  60506         -1,
  60507         -1,
  60508     },
  60509 #endif /* chips */
  60510 
  60511 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  60512     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1_BCM56260_A0r */
  60513         soc_block_list[85],
  60514         soc_genreg,
  60515         1,
  60516         0,
  60517         0x200d600,
  60518         0,
  60519         0,
  60520         6,
  60521         soc_LLS_MISC_ECC_ERROR1_BCM56260_A0r_fields,
  60522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60523         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60524         -1,
  60525         -1,
  60526     },
  60527 #endif /* chips */
  60528 
  60529 #if defined(BCM_56270_A0)
  60530     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1_BCM56270_A0r */
  60531         soc_block_list[85],
  60532         soc_genreg,
  60533         1,
  60534         0,
  60535         0x200bd00,
  60536         0,
  60537         0,
  60538         6,
  60539         soc_LLS_MISC_ECC_ERROR1_BCM56260_A0r_fields,
  60540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60541         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60542         -1,
  60543         -1,
  60544     },
  60545 #endif /* chips */
  60546 
  60547 #if defined(BCM_56440_B0)
  60548     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1_BCM56440_B0r */
  60549         soc_block_list[85],
  60550         soc_genreg,
  60551         1,
  60552         0,
  60553         0x80083,
  60554         0,
  60555         0,
  60556         18,
  60557         soc_LLS_MISC_ECC_ERROR1_BCM56440_B0r_fields,
  60558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60559         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  60560         -1,
  60561         -1,
  60562     },
  60563 #endif /* chips */
  60564 
  60565 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  60566     defined(BCM_56450_B1)
  60567     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1_BCM56450_A0r */
  60568         soc_block_list[85],
  60569         soc_genreg,
  60570         1,
  60571         0,
  60572         0x2015800,
  60573         0,
  60574         0,
  60575         22,
  60576         soc_LLS_MISC_ECC_ERROR1_BCM56450_A0r_fields,
  60577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60578         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  60579         -1,
  60580         -1,
  60581     },
  60582 #endif /* chips */
  60583 
  60584 #if defined(BCM_56440_A0)
  60585     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1_MASKr */
  60586         soc_block_list[85],
  60587         soc_genreg,
  60588         1,
  60589         0,
  60590         0x8007c,
  60591         0,
  60592         0,
  60593         12,
  60594         soc_LLS_MISC_ECC_ERROR1_MASKr_fields,
  60595         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  60596         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  60597         -1,
  60598         -1,
  60599     },
  60600 #endif /* chips */
  60601 
  60602 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  60603     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1_MASK_BCM56260_A0r */
  60604         soc_block_list[85],
  60605         soc_genreg,
  60606         1,
  60607         0,
  60608         0x200d700,
  60609         0,
  60610         0,
  60611         6,
  60612         soc_LLS_MISC_ECC_ERROR1_MASK_BCM56260_A0r_fields,
  60613         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  60614         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60615         -1,
  60616         -1,
  60617     },
  60618 #endif /* chips */
  60619 
  60620 #if defined(BCM_56270_A0)
  60621     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1_MASK_BCM56270_A0r */
  60622         soc_block_list[85],
  60623         soc_genreg,
  60624         1,
  60625         0,
  60626         0x200be00,
  60627         0,
  60628         0,
  60629         6,
  60630         soc_LLS_MISC_ECC_ERROR1_MASK_BCM56260_A0r_fields,
  60631         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  60632         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60633         -1,
  60634         -1,
  60635     },
  60636 #endif /* chips */
  60637 
  60638 #if defined(BCM_56440_B0)
  60639     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1_MASK_BCM56440_B0r */
  60640         soc_block_list[85],
  60641         soc_genreg,
  60642         1,
  60643         0,
  60644         0x80084,
  60645         0,
  60646         0,
  60647         18,
  60648         soc_LLS_MISC_ECC_ERROR1_MASK_BCM56440_B0r_fields,
  60649         SOC_RESET_VAL_DEC(0x0003ffff, 0x00000000)
  60650         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  60651         -1,
  60652         -1,
  60653     },
  60654 #endif /* chips */
  60655 
  60656 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  60657     defined(BCM_56450_B1)
  60658     { /* SOC_REG_INT_LLS_MISC_ECC_ERROR1_MASK_BCM56450_A0r */
  60659         soc_block_list[85],
  60660         soc_genreg,
  60661         1,
  60662         0,
  60663         0x2015900,
  60664         0,
  60665         0,
  60666         22,
  60667         soc_LLS_MISC_ECC_ERROR1_MASK_BCM56450_A0r_fields,
  60668         SOC_RESET_VAL_DEC(0x003fffff, 0x00000000)
  60669         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  60670         -1,
  60671         -1,
  60672     },
  60673 #endif /* chips */
  60674 
  60675 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  60676     { /* SOC_REG_INT_LLS_PER_PORT_WRR_PKT_MODE_0r */
  60677         soc_block_list[4],
  60678         soc_genreg,
  60679         1,
  60680         0,
  60681         0x62000700,
  60682         0,
  60683         0,
  60684         1,
  60685         soc_LLS_PER_PORT_WRR_PKT_MODE_0r_fields,
  60686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60687         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60688         -1,
  60689         -1,
  60690     },
  60691 #endif /* chips */
  60692 
  60693 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  60694     { /* SOC_REG_INT_LLS_PER_PORT_WRR_PKT_MODE_1r */
  60695         soc_block_list[4],
  60696         soc_genreg,
  60697         1,
  60698         0,
  60699         0x62000800,
  60700         0,
  60701         0,
  60702         1,
  60703         soc_LLS_PER_PORT_WRR_PKT_MODE_0r_fields,
  60704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60705         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60706         -1,
  60707         -1,
  60708     },
  60709 #endif /* chips */
  60710 
  60711 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  60712     { /* SOC_REG_INT_LLS_PER_PORT_WRR_PKT_MODE_2r */
  60713         soc_block_list[4],
  60714         soc_genreg,
  60715         1,
  60716         0,
  60717         0x62000900,
  60718         0,
  60719         0,
  60720         1,
  60721         soc_LLS_PER_PORT_WRR_PKT_MODE_2r_fields,
  60722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60723         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  60724         -1,
  60725         -1,
  60726     },
  60727 #endif /* chips */
  60728 
  60729 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  60730     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG1r */
  60731         soc_block_list[85],
  60732         soc_genreg,
  60733         1,
  60734         0,
  60735         0x80008,
  60736         0,
  60737         0,
  60738         2,
  60739         soc_LLS_PKT_ACC_CONFIG1r_fields,
  60740         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60742         -1,
  60743         -1,
  60744     },
  60745 #endif /* chips */
  60746 
  60747 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  60748     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG2r */
  60749         soc_block_list[85],
  60750         soc_genreg,
  60751         1,
  60752         0,
  60753         0x80009,
  60754         0,
  60755         0,
  60756         2,
  60757         soc_LLS_PKT_ACC_CONFIG2r_fields,
  60758         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60760         -1,
  60761         -1,
  60762     },
  60763 #endif /* chips */
  60764 
  60765 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  60766     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG3r */
  60767         soc_block_list[4],
  60768         soc_genreg,
  60769         1,
  60770         0,
  60771         0x62000600,
  60772         0,
  60773         0,
  60774         1,
  60775         soc_LLS_PKT_ACC_CONFIG3r_fields,
  60776         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  60777         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  60778         -1,
  60779         -1,
  60780     },
  60781 #endif /* chips */
  60782 
  60783 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  60784     defined(BCM_56270_A0)
  60785     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG1_BCM56260_A0r */
  60786         soc_block_list[85],
  60787         soc_genreg,
  60788         1,
  60789         0,
  60790         0x2000b00,
  60791         0,
  60792         0,
  60793         2,
  60794         soc_LLS_PKT_ACC_CONFIG1_BCM56560_A0r_fields,
  60795         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60797         -1,
  60798         -1,
  60799     },
  60800 #endif /* chips */
  60801 
  60802 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  60803     defined(BCM_56450_B1)
  60804     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG1_BCM56450_A0r */
  60805         soc_block_list[85],
  60806         soc_genreg,
  60807         1,
  60808         0,
  60809         0x2000b00,
  60810         0,
  60811         0,
  60812         2,
  60813         soc_LLS_PKT_ACC_CONFIG1_BCM56640_A0r_fields,
  60814         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60815         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60816         -1,
  60817         -1,
  60818     },
  60819 #endif /* chips */
  60820 
  60821 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  60822     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG1_BCM56560_A0r */
  60823         soc_block_list[4],
  60824         soc_genreg,
  60825         1,
  60826         0,
  60827         0x62000400,
  60828         0,
  60829         0,
  60830         2,
  60831         soc_LLS_PKT_ACC_CONFIG1_BCM56560_A0r_fields,
  60832         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60833         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60834         -1,
  60835         -1,
  60836     },
  60837 #endif /* chips */
  60838 
  60839 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60840     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG1_BCM56640_A0r */
  60841         soc_block_list[4],
  60842         soc_genreg,
  60843         1,
  60844         0,
  60845         0x5a000300,
  60846         0,
  60847         0,
  60848         2,
  60849         soc_LLS_PKT_ACC_CONFIG1_BCM56640_A0r_fields,
  60850         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60851         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60852         -1,
  60853         -1,
  60854     },
  60855 #endif /* chips */
  60856 
  60857 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  60858     defined(BCM_56270_A0)
  60859     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG2_BCM56260_A0r */
  60860         soc_block_list[85],
  60861         soc_genreg,
  60862         1,
  60863         0,
  60864         0x2000c00,
  60865         0,
  60866         0,
  60867         2,
  60868         soc_LLS_PKT_ACC_CONFIG2_BCM56560_A0r_fields,
  60869         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60871         -1,
  60872         -1,
  60873     },
  60874 #endif /* chips */
  60875 
  60876 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  60877     defined(BCM_56450_B1)
  60878     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG2_BCM56450_A0r */
  60879         soc_block_list[85],
  60880         soc_genreg,
  60881         1,
  60882         0,
  60883         0x2000c00,
  60884         0,
  60885         0,
  60886         2,
  60887         soc_LLS_PKT_ACC_CONFIG2_BCM56640_A0r_fields,
  60888         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60889         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60890         -1,
  60891         -1,
  60892     },
  60893 #endif /* chips */
  60894 
  60895 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  60896     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG2_BCM56560_A0r */
  60897         soc_block_list[4],
  60898         soc_genreg,
  60899         1,
  60900         0,
  60901         0x62000500,
  60902         0,
  60903         0,
  60904         2,
  60905         soc_LLS_PKT_ACC_CONFIG2_BCM56560_A0r_fields,
  60906         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60907         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60908         -1,
  60909         -1,
  60910     },
  60911 #endif /* chips */
  60912 
  60913 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  60914     { /* SOC_REG_INT_LLS_PKT_ACC_CONFIG2_BCM56640_A0r */
  60915         soc_block_list[4],
  60916         soc_genreg,
  60917         1,
  60918         0,
  60919         0x5a000400,
  60920         0,
  60921         0,
  60922         2,
  60923         soc_LLS_PKT_ACC_CONFIG2_BCM56640_A0r_fields,
  60924         SOC_RESET_VAL_DEC(0x007d007d, 0x00000000)
  60925         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60926         -1,
  60927         -1,
  60928     },
  60929 #endif /* chips */
  60930 
  60931 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  60932     { /* SOC_REG_INT_LLS_PORT_01_COE_CONFIGr */
  60933         soc_block_list[85],
  60934         soc_genreg,
  60935         1,
  60936         0,
  60937         0x2006000,
  60938         0,
  60939         0,
  60940         2,
  60941         soc_LLS_PORT_01_COE_CONFIGr_fields,
  60942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60943         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  60944         -1,
  60945         -1,
  60946     },
  60947 #endif /* chips */
  60948 
  60949 #if defined(BCM_56270_A0)
  60950     { /* SOC_REG_INT_LLS_PORT_01_COE_CONFIG_BCM56270_A0r */
  60951         soc_block_list[85],
  60952         soc_genreg,
  60953         1,
  60954         0,
  60955         0x2005b00,
  60956         0,
  60957         0,
  60958         2,
  60959         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  60960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60961         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  60962         -1,
  60963         -1,
  60964     },
  60965 #endif /* chips */
  60966 
  60967 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  60968     defined(BCM_56450_B1)
  60969     { /* SOC_REG_INT_LLS_PORT_01_LINKPHY_CONFIGr */
  60970         soc_block_list[85],
  60971         soc_genreg,
  60972         1,
  60973         0,
  60974         0x2005a00,
  60975         0,
  60976         0,
  60977         2,
  60978         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  60979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60980         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  60981         -1,
  60982         -1,
  60983     },
  60984 #endif /* chips */
  60985 
  60986 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  60987     { /* SOC_REG_INT_LLS_PORT_02_COE_CONFIGr */
  60988         soc_block_list[85],
  60989         soc_genreg,
  60990         1,
  60991         0,
  60992         0x2006100,
  60993         0,
  60994         0,
  60995         2,
  60996         soc_LLS_PORT_01_COE_CONFIGr_fields,
  60997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60998         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  60999         -1,
  61000         -1,
  61001     },
  61002 #endif /* chips */
  61003 
  61004 #if defined(BCM_56270_A0)
  61005     { /* SOC_REG_INT_LLS_PORT_02_COE_CONFIG_BCM56270_A0r */
  61006         soc_block_list[85],
  61007         soc_genreg,
  61008         1,
  61009         0,
  61010         0x2005c00,
  61011         0,
  61012         0,
  61013         2,
  61014         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61016         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61017         -1,
  61018         -1,
  61019     },
  61020 #endif /* chips */
  61021 
  61022 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61023     defined(BCM_56450_B1)
  61024     { /* SOC_REG_INT_LLS_PORT_02_LINKPHY_CONFIGr */
  61025         soc_block_list[85],
  61026         soc_genreg,
  61027         1,
  61028         0,
  61029         0x2005b00,
  61030         0,
  61031         0,
  61032         2,
  61033         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61035         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61036         -1,
  61037         -1,
  61038     },
  61039 #endif /* chips */
  61040 
  61041 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61042     { /* SOC_REG_INT_LLS_PORT_03_COE_CONFIGr */
  61043         soc_block_list[85],
  61044         soc_genreg,
  61045         1,
  61046         0,
  61047         0x2006200,
  61048         0,
  61049         0,
  61050         2,
  61051         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61053         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61054         -1,
  61055         -1,
  61056     },
  61057 #endif /* chips */
  61058 
  61059 #if defined(BCM_56270_A0)
  61060     { /* SOC_REG_INT_LLS_PORT_03_COE_CONFIG_BCM56270_A0r */
  61061         soc_block_list[85],
  61062         soc_genreg,
  61063         1,
  61064         0,
  61065         0x2005d00,
  61066         0,
  61067         0,
  61068         2,
  61069         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61071         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61072         -1,
  61073         -1,
  61074     },
  61075 #endif /* chips */
  61076 
  61077 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61078     defined(BCM_56450_B1)
  61079     { /* SOC_REG_INT_LLS_PORT_03_LINKPHY_CONFIGr */
  61080         soc_block_list[85],
  61081         soc_genreg,
  61082         1,
  61083         0,
  61084         0x2005c00,
  61085         0,
  61086         0,
  61087         2,
  61088         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61090         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61091         -1,
  61092         -1,
  61093     },
  61094 #endif /* chips */
  61095 
  61096 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61097     { /* SOC_REG_INT_LLS_PORT_04_COE_CONFIGr */
  61098         soc_block_list[85],
  61099         soc_genreg,
  61100         1,
  61101         0,
  61102         0x2006300,
  61103         0,
  61104         0,
  61105         2,
  61106         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61108         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61109         -1,
  61110         -1,
  61111     },
  61112 #endif /* chips */
  61113 
  61114 #if defined(BCM_56270_A0)
  61115     { /* SOC_REG_INT_LLS_PORT_04_COE_CONFIG_BCM56270_A0r */
  61116         soc_block_list[85],
  61117         soc_genreg,
  61118         1,
  61119         0,
  61120         0x2005e00,
  61121         0,
  61122         0,
  61123         2,
  61124         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61126         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61127         -1,
  61128         -1,
  61129     },
  61130 #endif /* chips */
  61131 
  61132 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61133     defined(BCM_56450_B1)
  61134     { /* SOC_REG_INT_LLS_PORT_04_LINKPHY_CONFIGr */
  61135         soc_block_list[85],
  61136         soc_genreg,
  61137         1,
  61138         0,
  61139         0x2005d00,
  61140         0,
  61141         0,
  61142         2,
  61143         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61145         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61146         -1,
  61147         -1,
  61148     },
  61149 #endif /* chips */
  61150 
  61151 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61152     { /* SOC_REG_INT_LLS_PORT_05_COE_CONFIGr */
  61153         soc_block_list[85],
  61154         soc_genreg,
  61155         1,
  61156         0,
  61157         0x2006400,
  61158         0,
  61159         0,
  61160         2,
  61161         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61163         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61164         -1,
  61165         -1,
  61166     },
  61167 #endif /* chips */
  61168 
  61169 #if defined(BCM_56270_A0)
  61170     { /* SOC_REG_INT_LLS_PORT_05_COE_CONFIG_BCM56270_A0r */
  61171         soc_block_list[85],
  61172         soc_genreg,
  61173         1,
  61174         0,
  61175         0x2005f00,
  61176         0,
  61177         0,
  61178         2,
  61179         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61181         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61182         -1,
  61183         -1,
  61184     },
  61185 #endif /* chips */
  61186 
  61187 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61188     defined(BCM_56450_B1)
  61189     { /* SOC_REG_INT_LLS_PORT_05_LINKPHY_CONFIGr */
  61190         soc_block_list[85],
  61191         soc_genreg,
  61192         1,
  61193         0,
  61194         0x2005e00,
  61195         0,
  61196         0,
  61197         2,
  61198         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61200         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61201         -1,
  61202         -1,
  61203     },
  61204 #endif /* chips */
  61205 
  61206 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61207     { /* SOC_REG_INT_LLS_PORT_06_COE_CONFIGr */
  61208         soc_block_list[85],
  61209         soc_genreg,
  61210         1,
  61211         0,
  61212         0x2006500,
  61213         0,
  61214         0,
  61215         2,
  61216         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61218         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61219         -1,
  61220         -1,
  61221     },
  61222 #endif /* chips */
  61223 
  61224 #if defined(BCM_56270_A0)
  61225     { /* SOC_REG_INT_LLS_PORT_06_COE_CONFIG_BCM56270_A0r */
  61226         soc_block_list[85],
  61227         soc_genreg,
  61228         1,
  61229         0,
  61230         0x2006000,
  61231         0,
  61232         0,
  61233         2,
  61234         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61236         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61237         -1,
  61238         -1,
  61239     },
  61240 #endif /* chips */
  61241 
  61242 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61243     defined(BCM_56450_B1)
  61244     { /* SOC_REG_INT_LLS_PORT_06_LINKPHY_CONFIGr */
  61245         soc_block_list[85],
  61246         soc_genreg,
  61247         1,
  61248         0,
  61249         0x2005f00,
  61250         0,
  61251         0,
  61252         2,
  61253         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61255         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61256         -1,
  61257         -1,
  61258     },
  61259 #endif /* chips */
  61260 
  61261 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61262     { /* SOC_REG_INT_LLS_PORT_07_COE_CONFIGr */
  61263         soc_block_list[85],
  61264         soc_genreg,
  61265         1,
  61266         0,
  61267         0x2006600,
  61268         0,
  61269         0,
  61270         2,
  61271         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61273         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61274         -1,
  61275         -1,
  61276     },
  61277 #endif /* chips */
  61278 
  61279 #if defined(BCM_56270_A0)
  61280     { /* SOC_REG_INT_LLS_PORT_07_COE_CONFIG_BCM56270_A0r */
  61281         soc_block_list[85],
  61282         soc_genreg,
  61283         1,
  61284         0,
  61285         0x2006100,
  61286         0,
  61287         0,
  61288         2,
  61289         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61291         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61292         -1,
  61293         -1,
  61294     },
  61295 #endif /* chips */
  61296 
  61297 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61298     defined(BCM_56450_B1)
  61299     { /* SOC_REG_INT_LLS_PORT_07_LINKPHY_CONFIGr */
  61300         soc_block_list[85],
  61301         soc_genreg,
  61302         1,
  61303         0,
  61304         0x2006000,
  61305         0,
  61306         0,
  61307         2,
  61308         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61310         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61311         -1,
  61312         -1,
  61313     },
  61314 #endif /* chips */
  61315 
  61316 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61317     { /* SOC_REG_INT_LLS_PORT_08_COE_CONFIGr */
  61318         soc_block_list[85],
  61319         soc_genreg,
  61320         1,
  61321         0,
  61322         0x2006700,
  61323         0,
  61324         0,
  61325         2,
  61326         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61328         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61329         -1,
  61330         -1,
  61331     },
  61332 #endif /* chips */
  61333 
  61334 #if defined(BCM_56270_A0)
  61335     { /* SOC_REG_INT_LLS_PORT_08_COE_CONFIG_BCM56270_A0r */
  61336         soc_block_list[85],
  61337         soc_genreg,
  61338         1,
  61339         0,
  61340         0x2006200,
  61341         0,
  61342         0,
  61343         2,
  61344         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61346         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61347         -1,
  61348         -1,
  61349     },
  61350 #endif /* chips */
  61351 
  61352 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61353     defined(BCM_56450_B1)
  61354     { /* SOC_REG_INT_LLS_PORT_08_LINKPHY_CONFIGr */
  61355         soc_block_list[85],
  61356         soc_genreg,
  61357         1,
  61358         0,
  61359         0x2006100,
  61360         0,
  61361         0,
  61362         2,
  61363         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61365         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61366         -1,
  61367         -1,
  61368     },
  61369 #endif /* chips */
  61370 
  61371 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61372     { /* SOC_REG_INT_LLS_PORT_09_COE_CONFIGr */
  61373         soc_block_list[85],
  61374         soc_genreg,
  61375         1,
  61376         0,
  61377         0x2006800,
  61378         0,
  61379         0,
  61380         2,
  61381         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61383         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61384         -1,
  61385         -1,
  61386     },
  61387 #endif /* chips */
  61388 
  61389 #if defined(BCM_56270_A0)
  61390     { /* SOC_REG_INT_LLS_PORT_09_COE_CONFIG_BCM56270_A0r */
  61391         soc_block_list[85],
  61392         soc_genreg,
  61393         1,
  61394         0,
  61395         0x2006300,
  61396         0,
  61397         0,
  61398         2,
  61399         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61401         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61402         -1,
  61403         -1,
  61404     },
  61405 #endif /* chips */
  61406 
  61407 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61408     defined(BCM_56450_B1)
  61409     { /* SOC_REG_INT_LLS_PORT_09_LINKPHY_CONFIGr */
  61410         soc_block_list[85],
  61411         soc_genreg,
  61412         1,
  61413         0,
  61414         0x2006200,
  61415         0,
  61416         0,
  61417         2,
  61418         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61420         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61421         -1,
  61422         -1,
  61423     },
  61424 #endif /* chips */
  61425 
  61426 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61427     { /* SOC_REG_INT_LLS_PORT_0_CREDITr */
  61428         soc_block_list[4],
  61429         soc_genreg,
  61430         1,
  61431         0,
  61432         0x5a001b00,
  61433         0,
  61434         0,
  61435         1,
  61436         soc_LLS_PORT_0_CREDITr_fields,
  61437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61438         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61439         -1,
  61440         -1,
  61441     },
  61442 #endif /* chips */
  61443 
  61444 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61445     { /* SOC_REG_INT_LLS_PORT_10_COE_CONFIGr */
  61446         soc_block_list[85],
  61447         soc_genreg,
  61448         1,
  61449         0,
  61450         0x2006900,
  61451         0,
  61452         0,
  61453         2,
  61454         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61456         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61457         -1,
  61458         -1,
  61459     },
  61460 #endif /* chips */
  61461 
  61462 #if defined(BCM_56270_A0)
  61463     { /* SOC_REG_INT_LLS_PORT_10_COE_CONFIG_BCM56270_A0r */
  61464         soc_block_list[85],
  61465         soc_genreg,
  61466         1,
  61467         0,
  61468         0x2006400,
  61469         0,
  61470         0,
  61471         2,
  61472         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61474         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61475         -1,
  61476         -1,
  61477     },
  61478 #endif /* chips */
  61479 
  61480 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61481     { /* SOC_REG_INT_LLS_PORT_10_CREDITr */
  61482         soc_block_list[4],
  61483         soc_genreg,
  61484         1,
  61485         0,
  61486         0x5a002500,
  61487         0,
  61488         0,
  61489         1,
  61490         soc_LLS_PORT_0_CREDITr_fields,
  61491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61492         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61493         -1,
  61494         -1,
  61495     },
  61496 #endif /* chips */
  61497 
  61498 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61499     defined(BCM_56450_B1)
  61500     { /* SOC_REG_INT_LLS_PORT_10_LINKPHY_CONFIGr */
  61501         soc_block_list[85],
  61502         soc_genreg,
  61503         1,
  61504         0,
  61505         0x2006300,
  61506         0,
  61507         0,
  61508         2,
  61509         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61511         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61512         -1,
  61513         -1,
  61514     },
  61515 #endif /* chips */
  61516 
  61517 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61518     { /* SOC_REG_INT_LLS_PORT_11_COE_CONFIGr */
  61519         soc_block_list[85],
  61520         soc_genreg,
  61521         1,
  61522         0,
  61523         0x2006a00,
  61524         0,
  61525         0,
  61526         2,
  61527         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61529         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61530         -1,
  61531         -1,
  61532     },
  61533 #endif /* chips */
  61534 
  61535 #if defined(BCM_56270_A0)
  61536     { /* SOC_REG_INT_LLS_PORT_11_COE_CONFIG_BCM56270_A0r */
  61537         soc_block_list[85],
  61538         soc_genreg,
  61539         1,
  61540         0,
  61541         0x2006500,
  61542         0,
  61543         0,
  61544         2,
  61545         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61547         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61548         -1,
  61549         -1,
  61550     },
  61551 #endif /* chips */
  61552 
  61553 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61554     { /* SOC_REG_INT_LLS_PORT_11_CREDITr */
  61555         soc_block_list[4],
  61556         soc_genreg,
  61557         1,
  61558         0,
  61559         0x5a002600,
  61560         0,
  61561         0,
  61562         1,
  61563         soc_LLS_PORT_0_CREDITr_fields,
  61564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61565         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61566         -1,
  61567         -1,
  61568     },
  61569 #endif /* chips */
  61570 
  61571 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61572     defined(BCM_56450_B1)
  61573     { /* SOC_REG_INT_LLS_PORT_11_LINKPHY_CONFIGr */
  61574         soc_block_list[85],
  61575         soc_genreg,
  61576         1,
  61577         0,
  61578         0x2006400,
  61579         0,
  61580         0,
  61581         2,
  61582         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61584         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61585         -1,
  61586         -1,
  61587     },
  61588 #endif /* chips */
  61589 
  61590 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61591     { /* SOC_REG_INT_LLS_PORT_12_COE_CONFIGr */
  61592         soc_block_list[85],
  61593         soc_genreg,
  61594         1,
  61595         0,
  61596         0x2006b00,
  61597         0,
  61598         0,
  61599         2,
  61600         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61602         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61603         -1,
  61604         -1,
  61605     },
  61606 #endif /* chips */
  61607 
  61608 #if defined(BCM_56270_A0)
  61609     { /* SOC_REG_INT_LLS_PORT_12_COE_CONFIG_BCM56270_A0r */
  61610         soc_block_list[85],
  61611         soc_genreg,
  61612         1,
  61613         0,
  61614         0x2006600,
  61615         0,
  61616         0,
  61617         2,
  61618         soc_LLS_PORT_01_COE_CONFIG_BCM56270_A0r_fields,
  61619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61620         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  61621         -1,
  61622         -1,
  61623     },
  61624 #endif /* chips */
  61625 
  61626 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61627     { /* SOC_REG_INT_LLS_PORT_12_CREDITr */
  61628         soc_block_list[4],
  61629         soc_genreg,
  61630         1,
  61631         0,
  61632         0x5a002700,
  61633         0,
  61634         0,
  61635         1,
  61636         soc_LLS_PORT_0_CREDITr_fields,
  61637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61638         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61639         -1,
  61640         -1,
  61641     },
  61642 #endif /* chips */
  61643 
  61644 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61645     defined(BCM_56450_B1)
  61646     { /* SOC_REG_INT_LLS_PORT_12_LINKPHY_CONFIGr */
  61647         soc_block_list[85],
  61648         soc_genreg,
  61649         1,
  61650         0,
  61651         0x2006500,
  61652         0,
  61653         0,
  61654         2,
  61655         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61657         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61658         -1,
  61659         -1,
  61660     },
  61661 #endif /* chips */
  61662 
  61663 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61664     { /* SOC_REG_INT_LLS_PORT_13_COE_CONFIGr */
  61665         soc_block_list[85],
  61666         soc_genreg,
  61667         1,
  61668         0,
  61669         0x2006c00,
  61670         0,
  61671         0,
  61672         2,
  61673         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61675         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61676         -1,
  61677         -1,
  61678     },
  61679 #endif /* chips */
  61680 
  61681 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61682     { /* SOC_REG_INT_LLS_PORT_13_CREDITr */
  61683         soc_block_list[4],
  61684         soc_genreg,
  61685         1,
  61686         0,
  61687         0x5a002800,
  61688         0,
  61689         0,
  61690         1,
  61691         soc_LLS_PORT_0_CREDITr_fields,
  61692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61693         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61694         -1,
  61695         -1,
  61696     },
  61697 #endif /* chips */
  61698 
  61699 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61700     defined(BCM_56450_B1)
  61701     { /* SOC_REG_INT_LLS_PORT_13_LINKPHY_CONFIGr */
  61702         soc_block_list[85],
  61703         soc_genreg,
  61704         1,
  61705         0,
  61706         0x2006600,
  61707         0,
  61708         0,
  61709         2,
  61710         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61711         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61712         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61713         -1,
  61714         -1,
  61715     },
  61716 #endif /* chips */
  61717 
  61718 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61719     { /* SOC_REG_INT_LLS_PORT_14_COE_CONFIGr */
  61720         soc_block_list[85],
  61721         soc_genreg,
  61722         1,
  61723         0,
  61724         0x2006d00,
  61725         0,
  61726         0,
  61727         2,
  61728         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61730         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61731         -1,
  61732         -1,
  61733     },
  61734 #endif /* chips */
  61735 
  61736 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61737     { /* SOC_REG_INT_LLS_PORT_14_CREDITr */
  61738         soc_block_list[4],
  61739         soc_genreg,
  61740         1,
  61741         0,
  61742         0x5a002900,
  61743         0,
  61744         0,
  61745         1,
  61746         soc_LLS_PORT_0_CREDITr_fields,
  61747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61748         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61749         -1,
  61750         -1,
  61751     },
  61752 #endif /* chips */
  61753 
  61754 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61755     defined(BCM_56450_B1)
  61756     { /* SOC_REG_INT_LLS_PORT_14_LINKPHY_CONFIGr */
  61757         soc_block_list[85],
  61758         soc_genreg,
  61759         1,
  61760         0,
  61761         0x2006700,
  61762         0,
  61763         0,
  61764         2,
  61765         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61767         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61768         -1,
  61769         -1,
  61770     },
  61771 #endif /* chips */
  61772 
  61773 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61774     { /* SOC_REG_INT_LLS_PORT_15_COE_CONFIGr */
  61775         soc_block_list[85],
  61776         soc_genreg,
  61777         1,
  61778         0,
  61779         0x2006e00,
  61780         0,
  61781         0,
  61782         2,
  61783         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61785         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61786         -1,
  61787         -1,
  61788     },
  61789 #endif /* chips */
  61790 
  61791 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61792     { /* SOC_REG_INT_LLS_PORT_15_CREDITr */
  61793         soc_block_list[4],
  61794         soc_genreg,
  61795         1,
  61796         0,
  61797         0x5a002a00,
  61798         0,
  61799         0,
  61800         1,
  61801         soc_LLS_PORT_0_CREDITr_fields,
  61802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61803         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61804         -1,
  61805         -1,
  61806     },
  61807 #endif /* chips */
  61808 
  61809 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61810     defined(BCM_56450_B1)
  61811     { /* SOC_REG_INT_LLS_PORT_15_LINKPHY_CONFIGr */
  61812         soc_block_list[85],
  61813         soc_genreg,
  61814         1,
  61815         0,
  61816         0x2006800,
  61817         0,
  61818         0,
  61819         2,
  61820         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61822         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61823         -1,
  61824         -1,
  61825     },
  61826 #endif /* chips */
  61827 
  61828 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61829     { /* SOC_REG_INT_LLS_PORT_16_COE_CONFIGr */
  61830         soc_block_list[85],
  61831         soc_genreg,
  61832         1,
  61833         0,
  61834         0x2006f00,
  61835         0,
  61836         0,
  61837         2,
  61838         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61840         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61841         -1,
  61842         -1,
  61843     },
  61844 #endif /* chips */
  61845 
  61846 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61847     { /* SOC_REG_INT_LLS_PORT_16_CREDITr */
  61848         soc_block_list[4],
  61849         soc_genreg,
  61850         1,
  61851         0,
  61852         0x5a002b00,
  61853         0,
  61854         0,
  61855         1,
  61856         soc_LLS_PORT_0_CREDITr_fields,
  61857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61858         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61859         -1,
  61860         -1,
  61861     },
  61862 #endif /* chips */
  61863 
  61864 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61865     defined(BCM_56450_B1)
  61866     { /* SOC_REG_INT_LLS_PORT_16_LINKPHY_CONFIGr */
  61867         soc_block_list[85],
  61868         soc_genreg,
  61869         1,
  61870         0,
  61871         0x2006900,
  61872         0,
  61873         0,
  61874         2,
  61875         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61877         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61878         -1,
  61879         -1,
  61880     },
  61881 #endif /* chips */
  61882 
  61883 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61884     { /* SOC_REG_INT_LLS_PORT_17_COE_CONFIGr */
  61885         soc_block_list[85],
  61886         soc_genreg,
  61887         1,
  61888         0,
  61889         0x2007000,
  61890         0,
  61891         0,
  61892         2,
  61893         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61895         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61896         -1,
  61897         -1,
  61898     },
  61899 #endif /* chips */
  61900 
  61901 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61902     { /* SOC_REG_INT_LLS_PORT_17_CREDITr */
  61903         soc_block_list[4],
  61904         soc_genreg,
  61905         1,
  61906         0,
  61907         0x5a002c00,
  61908         0,
  61909         0,
  61910         1,
  61911         soc_LLS_PORT_0_CREDITr_fields,
  61912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61913         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61914         -1,
  61915         -1,
  61916     },
  61917 #endif /* chips */
  61918 
  61919 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61920     defined(BCM_56450_B1)
  61921     { /* SOC_REG_INT_LLS_PORT_17_LINKPHY_CONFIGr */
  61922         soc_block_list[85],
  61923         soc_genreg,
  61924         1,
  61925         0,
  61926         0x2006a00,
  61927         0,
  61928         0,
  61929         2,
  61930         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61932         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61933         -1,
  61934         -1,
  61935     },
  61936 #endif /* chips */
  61937 
  61938 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61939     { /* SOC_REG_INT_LLS_PORT_18_COE_CONFIGr */
  61940         soc_block_list[85],
  61941         soc_genreg,
  61942         1,
  61943         0,
  61944         0x2007100,
  61945         0,
  61946         0,
  61947         2,
  61948         soc_LLS_PORT_01_COE_CONFIGr_fields,
  61949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61950         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  61951         -1,
  61952         -1,
  61953     },
  61954 #endif /* chips */
  61955 
  61956 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  61957     { /* SOC_REG_INT_LLS_PORT_18_CREDITr */
  61958         soc_block_list[4],
  61959         soc_genreg,
  61960         1,
  61961         0,
  61962         0x5a002d00,
  61963         0,
  61964         0,
  61965         1,
  61966         soc_LLS_PORT_0_CREDITr_fields,
  61967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61968         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61969         -1,
  61970         -1,
  61971     },
  61972 #endif /* chips */
  61973 
  61974 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  61975     defined(BCM_56450_B1)
  61976     { /* SOC_REG_INT_LLS_PORT_18_LINKPHY_CONFIGr */
  61977         soc_block_list[85],
  61978         soc_genreg,
  61979         1,
  61980         0,
  61981         0x2006b00,
  61982         0,
  61983         0,
  61984         2,
  61985         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  61986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61987         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  61988         -1,
  61989         -1,
  61990     },
  61991 #endif /* chips */
  61992 
  61993 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  61994     { /* SOC_REG_INT_LLS_PORT_19_COE_CONFIGr */
  61995         soc_block_list[85],
  61996         soc_genreg,
  61997         1,
  61998         0,
  61999         0x2007200,
  62000         0,
  62001         0,
  62002         2,
  62003         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62005         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62006         -1,
  62007         -1,
  62008     },
  62009 #endif /* chips */
  62010 
  62011 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62012     { /* SOC_REG_INT_LLS_PORT_19_CREDITr */
  62013         soc_block_list[4],
  62014         soc_genreg,
  62015         1,
  62016         0,
  62017         0x5a002e00,
  62018         0,
  62019         0,
  62020         1,
  62021         soc_LLS_PORT_0_CREDITr_fields,
  62022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62023         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62024         -1,
  62025         -1,
  62026     },
  62027 #endif /* chips */
  62028 
  62029 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62030     defined(BCM_56450_B1)
  62031     { /* SOC_REG_INT_LLS_PORT_19_LINKPHY_CONFIGr */
  62032         soc_block_list[85],
  62033         soc_genreg,
  62034         1,
  62035         0,
  62036         0x2006c00,
  62037         0,
  62038         0,
  62039         2,
  62040         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62042         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62043         -1,
  62044         -1,
  62045     },
  62046 #endif /* chips */
  62047 
  62048 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62049     { /* SOC_REG_INT_LLS_PORT_1_CREDITr */
  62050         soc_block_list[4],
  62051         soc_genreg,
  62052         1,
  62053         0,
  62054         0x5a001c00,
  62055         0,
  62056         0,
  62057         1,
  62058         soc_LLS_PORT_0_CREDITr_fields,
  62059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62060         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62061         -1,
  62062         -1,
  62063     },
  62064 #endif /* chips */
  62065 
  62066 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62067     { /* SOC_REG_INT_LLS_PORT_20_COE_CONFIGr */
  62068         soc_block_list[85],
  62069         soc_genreg,
  62070         1,
  62071         0,
  62072         0x2007300,
  62073         0,
  62074         0,
  62075         2,
  62076         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62078         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62079         -1,
  62080         -1,
  62081     },
  62082 #endif /* chips */
  62083 
  62084 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62085     { /* SOC_REG_INT_LLS_PORT_20_CREDITr */
  62086         soc_block_list[4],
  62087         soc_genreg,
  62088         1,
  62089         0,
  62090         0x5a002f00,
  62091         0,
  62092         0,
  62093         1,
  62094         soc_LLS_PORT_0_CREDITr_fields,
  62095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62096         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62097         -1,
  62098         -1,
  62099     },
  62100 #endif /* chips */
  62101 
  62102 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62103     defined(BCM_56450_B1)
  62104     { /* SOC_REG_INT_LLS_PORT_20_LINKPHY_CONFIGr */
  62105         soc_block_list[85],
  62106         soc_genreg,
  62107         1,
  62108         0,
  62109         0x2006d00,
  62110         0,
  62111         0,
  62112         2,
  62113         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62115         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62116         -1,
  62117         -1,
  62118     },
  62119 #endif /* chips */
  62120 
  62121 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62122     { /* SOC_REG_INT_LLS_PORT_21_COE_CONFIGr */
  62123         soc_block_list[85],
  62124         soc_genreg,
  62125         1,
  62126         0,
  62127         0x2007400,
  62128         0,
  62129         0,
  62130         2,
  62131         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62133         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62134         -1,
  62135         -1,
  62136     },
  62137 #endif /* chips */
  62138 
  62139 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62140     { /* SOC_REG_INT_LLS_PORT_21_CREDITr */
  62141         soc_block_list[4],
  62142         soc_genreg,
  62143         1,
  62144         0,
  62145         0x5a003000,
  62146         0,
  62147         0,
  62148         1,
  62149         soc_LLS_PORT_0_CREDITr_fields,
  62150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62151         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62152         -1,
  62153         -1,
  62154     },
  62155 #endif /* chips */
  62156 
  62157 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62158     defined(BCM_56450_B1)
  62159     { /* SOC_REG_INT_LLS_PORT_21_LINKPHY_CONFIGr */
  62160         soc_block_list[85],
  62161         soc_genreg,
  62162         1,
  62163         0,
  62164         0x2006e00,
  62165         0,
  62166         0,
  62167         2,
  62168         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62170         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62171         -1,
  62172         -1,
  62173     },
  62174 #endif /* chips */
  62175 
  62176 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62177     { /* SOC_REG_INT_LLS_PORT_22_COE_CONFIGr */
  62178         soc_block_list[85],
  62179         soc_genreg,
  62180         1,
  62181         0,
  62182         0x2007500,
  62183         0,
  62184         0,
  62185         2,
  62186         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62188         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62189         -1,
  62190         -1,
  62191     },
  62192 #endif /* chips */
  62193 
  62194 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62195     { /* SOC_REG_INT_LLS_PORT_22_CREDITr */
  62196         soc_block_list[4],
  62197         soc_genreg,
  62198         1,
  62199         0,
  62200         0x5a003100,
  62201         0,
  62202         0,
  62203         1,
  62204         soc_LLS_PORT_0_CREDITr_fields,
  62205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62206         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62207         -1,
  62208         -1,
  62209     },
  62210 #endif /* chips */
  62211 
  62212 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62213     defined(BCM_56450_B1)
  62214     { /* SOC_REG_INT_LLS_PORT_22_LINKPHY_CONFIGr */
  62215         soc_block_list[85],
  62216         soc_genreg,
  62217         1,
  62218         0,
  62219         0x2006f00,
  62220         0,
  62221         0,
  62222         2,
  62223         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62225         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62226         -1,
  62227         -1,
  62228     },
  62229 #endif /* chips */
  62230 
  62231 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62232     { /* SOC_REG_INT_LLS_PORT_23_COE_CONFIGr */
  62233         soc_block_list[85],
  62234         soc_genreg,
  62235         1,
  62236         0,
  62237         0x2007600,
  62238         0,
  62239         0,
  62240         2,
  62241         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62243         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62244         -1,
  62245         -1,
  62246     },
  62247 #endif /* chips */
  62248 
  62249 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62250     { /* SOC_REG_INT_LLS_PORT_23_CREDITr */
  62251         soc_block_list[4],
  62252         soc_genreg,
  62253         1,
  62254         0,
  62255         0x5a003200,
  62256         0,
  62257         0,
  62258         1,
  62259         soc_LLS_PORT_0_CREDITr_fields,
  62260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62261         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62262         -1,
  62263         -1,
  62264     },
  62265 #endif /* chips */
  62266 
  62267 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62268     defined(BCM_56450_B1)
  62269     { /* SOC_REG_INT_LLS_PORT_23_LINKPHY_CONFIGr */
  62270         soc_block_list[85],
  62271         soc_genreg,
  62272         1,
  62273         0,
  62274         0x2007000,
  62275         0,
  62276         0,
  62277         2,
  62278         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62280         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62281         -1,
  62282         -1,
  62283     },
  62284 #endif /* chips */
  62285 
  62286 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62287     { /* SOC_REG_INT_LLS_PORT_24_COE_CONFIGr */
  62288         soc_block_list[85],
  62289         soc_genreg,
  62290         1,
  62291         0,
  62292         0x2007700,
  62293         0,
  62294         0,
  62295         2,
  62296         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62298         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62299         -1,
  62300         -1,
  62301     },
  62302 #endif /* chips */
  62303 
  62304 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62305     { /* SOC_REG_INT_LLS_PORT_24_CREDITr */
  62306         soc_block_list[4],
  62307         soc_genreg,
  62308         1,
  62309         0,
  62310         0x5a003300,
  62311         0,
  62312         0,
  62313         1,
  62314         soc_LLS_PORT_0_CREDITr_fields,
  62315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62316         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62317         -1,
  62318         -1,
  62319     },
  62320 #endif /* chips */
  62321 
  62322 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62323     defined(BCM_56450_B1)
  62324     { /* SOC_REG_INT_LLS_PORT_24_LINKPHY_CONFIGr */
  62325         soc_block_list[85],
  62326         soc_genreg,
  62327         1,
  62328         0,
  62329         0x2007100,
  62330         0,
  62331         0,
  62332         2,
  62333         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62335         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62336         -1,
  62337         -1,
  62338     },
  62339 #endif /* chips */
  62340 
  62341 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62342     { /* SOC_REG_INT_LLS_PORT_25_COE_CONFIGr */
  62343         soc_block_list[85],
  62344         soc_genreg,
  62345         1,
  62346         0,
  62347         0x2007800,
  62348         0,
  62349         0,
  62350         2,
  62351         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62353         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62354         -1,
  62355         -1,
  62356     },
  62357 #endif /* chips */
  62358 
  62359 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62360     { /* SOC_REG_INT_LLS_PORT_25_CREDITr */
  62361         soc_block_list[4],
  62362         soc_genreg,
  62363         1,
  62364         0,
  62365         0x5a003400,
  62366         0,
  62367         0,
  62368         1,
  62369         soc_LLS_PORT_0_CREDITr_fields,
  62370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62371         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62372         -1,
  62373         -1,
  62374     },
  62375 #endif /* chips */
  62376 
  62377 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62378     defined(BCM_56450_B1)
  62379     { /* SOC_REG_INT_LLS_PORT_25_LINKPHY_CONFIGr */
  62380         soc_block_list[85],
  62381         soc_genreg,
  62382         1,
  62383         0,
  62384         0x2007200,
  62385         0,
  62386         0,
  62387         2,
  62388         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62390         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62391         -1,
  62392         -1,
  62393     },
  62394 #endif /* chips */
  62395 
  62396 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62397     { /* SOC_REG_INT_LLS_PORT_26_COE_CONFIGr */
  62398         soc_block_list[85],
  62399         soc_genreg,
  62400         1,
  62401         0,
  62402         0x2007900,
  62403         0,
  62404         0,
  62405         2,
  62406         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62408         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62409         -1,
  62410         -1,
  62411     },
  62412 #endif /* chips */
  62413 
  62414 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62415     { /* SOC_REG_INT_LLS_PORT_26_CREDITr */
  62416         soc_block_list[4],
  62417         soc_genreg,
  62418         1,
  62419         0,
  62420         0x5a003500,
  62421         0,
  62422         0,
  62423         1,
  62424         soc_LLS_PORT_0_CREDITr_fields,
  62425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62426         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62427         -1,
  62428         -1,
  62429     },
  62430 #endif /* chips */
  62431 
  62432 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62433     defined(BCM_56450_B1)
  62434     { /* SOC_REG_INT_LLS_PORT_26_LINKPHY_CONFIGr */
  62435         soc_block_list[85],
  62436         soc_genreg,
  62437         1,
  62438         0,
  62439         0x2007300,
  62440         0,
  62441         0,
  62442         2,
  62443         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62445         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62446         -1,
  62447         -1,
  62448     },
  62449 #endif /* chips */
  62450 
  62451 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62452     { /* SOC_REG_INT_LLS_PORT_27_COE_CONFIGr */
  62453         soc_block_list[85],
  62454         soc_genreg,
  62455         1,
  62456         0,
  62457         0x2007a00,
  62458         0,
  62459         0,
  62460         2,
  62461         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62463         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62464         -1,
  62465         -1,
  62466     },
  62467 #endif /* chips */
  62468 
  62469 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62470     { /* SOC_REG_INT_LLS_PORT_27_CREDITr */
  62471         soc_block_list[4],
  62472         soc_genreg,
  62473         1,
  62474         0,
  62475         0x5a003600,
  62476         0,
  62477         0,
  62478         1,
  62479         soc_LLS_PORT_0_CREDITr_fields,
  62480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62481         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62482         -1,
  62483         -1,
  62484     },
  62485 #endif /* chips */
  62486 
  62487 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62488     defined(BCM_56450_B1)
  62489     { /* SOC_REG_INT_LLS_PORT_27_LINKPHY_CONFIGr */
  62490         soc_block_list[85],
  62491         soc_genreg,
  62492         1,
  62493         0,
  62494         0x2007400,
  62495         0,
  62496         0,
  62497         4,
  62498         soc_LLS_PORT_27_LINKPHY_CONFIGr_fields,
  62499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62500         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  62501         -1,
  62502         -1,
  62503     },
  62504 #endif /* chips */
  62505 
  62506 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62507     { /* SOC_REG_INT_LLS_PORT_28_COE_CONFIGr */
  62508         soc_block_list[85],
  62509         soc_genreg,
  62510         1,
  62511         0,
  62512         0x2007b00,
  62513         0,
  62514         0,
  62515         2,
  62516         soc_LLS_PORT_01_COE_CONFIGr_fields,
  62517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62518         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  62519         -1,
  62520         -1,
  62521     },
  62522 #endif /* chips */
  62523 
  62524 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62525     { /* SOC_REG_INT_LLS_PORT_28_CREDITr */
  62526         soc_block_list[4],
  62527         soc_genreg,
  62528         1,
  62529         0,
  62530         0x5a003700,
  62531         0,
  62532         0,
  62533         1,
  62534         soc_LLS_PORT_0_CREDITr_fields,
  62535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62536         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62537         -1,
  62538         -1,
  62539     },
  62540 #endif /* chips */
  62541 
  62542 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62543     defined(BCM_56450_B1)
  62544     { /* SOC_REG_INT_LLS_PORT_28_LINKPHY_CONFIGr */
  62545         soc_block_list[85],
  62546         soc_genreg,
  62547         1,
  62548         0,
  62549         0x2007500,
  62550         0,
  62551         0,
  62552         4,
  62553         soc_LLS_PORT_27_LINKPHY_CONFIGr_fields,
  62554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62555         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  62556         -1,
  62557         -1,
  62558     },
  62559 #endif /* chips */
  62560 
  62561 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62562     { /* SOC_REG_INT_LLS_PORT_29_CREDITr */
  62563         soc_block_list[4],
  62564         soc_genreg,
  62565         1,
  62566         0,
  62567         0x5a003800,
  62568         0,
  62569         0,
  62570         1,
  62571         soc_LLS_PORT_0_CREDITr_fields,
  62572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62573         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62574         -1,
  62575         -1,
  62576     },
  62577 #endif /* chips */
  62578 
  62579 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62580     defined(BCM_56450_B1)
  62581     { /* SOC_REG_INT_LLS_PORT_29_LINKPHY_CONFIGr */
  62582         soc_block_list[85],
  62583         soc_genreg,
  62584         1,
  62585         0,
  62586         0x2007600,
  62587         0,
  62588         0,
  62589         4,
  62590         soc_LLS_PORT_27_LINKPHY_CONFIGr_fields,
  62591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62592         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  62593         -1,
  62594         -1,
  62595     },
  62596 #endif /* chips */
  62597 
  62598 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62599     { /* SOC_REG_INT_LLS_PORT_2_CREDITr */
  62600         soc_block_list[4],
  62601         soc_genreg,
  62602         1,
  62603         0,
  62604         0x5a001d00,
  62605         0,
  62606         0,
  62607         1,
  62608         soc_LLS_PORT_0_CREDITr_fields,
  62609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62610         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62611         -1,
  62612         -1,
  62613     },
  62614 #endif /* chips */
  62615 
  62616 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62617     { /* SOC_REG_INT_LLS_PORT_30_CREDITr */
  62618         soc_block_list[4],
  62619         soc_genreg,
  62620         1,
  62621         0,
  62622         0x5a003900,
  62623         0,
  62624         0,
  62625         1,
  62626         soc_LLS_PORT_0_CREDITr_fields,
  62627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62628         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62629         -1,
  62630         -1,
  62631     },
  62632 #endif /* chips */
  62633 
  62634 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62635     defined(BCM_56450_B1)
  62636     { /* SOC_REG_INT_LLS_PORT_30_LINKPHY_CONFIGr */
  62637         soc_block_list[85],
  62638         soc_genreg,
  62639         1,
  62640         0,
  62641         0x2007700,
  62642         0,
  62643         0,
  62644         4,
  62645         soc_LLS_PORT_27_LINKPHY_CONFIGr_fields,
  62646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62647         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  62648         -1,
  62649         -1,
  62650     },
  62651 #endif /* chips */
  62652 
  62653 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62654     { /* SOC_REG_INT_LLS_PORT_31_CREDITr */
  62655         soc_block_list[4],
  62656         soc_genreg,
  62657         1,
  62658         0,
  62659         0x5a003a00,
  62660         0,
  62661         0,
  62662         1,
  62663         soc_LLS_PORT_0_CREDITr_fields,
  62664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62665         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62666         -1,
  62667         -1,
  62668     },
  62669 #endif /* chips */
  62670 
  62671 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62672     defined(BCM_56450_B1)
  62673     { /* SOC_REG_INT_LLS_PORT_31_LINKPHY_CONFIGr */
  62674         soc_block_list[85],
  62675         soc_genreg,
  62676         1,
  62677         0,
  62678         0x2007800,
  62679         0,
  62680         0,
  62681         4,
  62682         soc_LLS_PORT_27_LINKPHY_CONFIGr_fields,
  62683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62684         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  62685         -1,
  62686         -1,
  62687     },
  62688 #endif /* chips */
  62689 
  62690 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62691     { /* SOC_REG_INT_LLS_PORT_32_CREDITr */
  62692         soc_block_list[4],
  62693         soc_genreg,
  62694         1,
  62695         0,
  62696         0x5a003b00,
  62697         0,
  62698         0,
  62699         1,
  62700         soc_LLS_PORT_0_CREDITr_fields,
  62701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62702         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62703         -1,
  62704         -1,
  62705     },
  62706 #endif /* chips */
  62707 
  62708 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62709     defined(BCM_56450_B1)
  62710     { /* SOC_REG_INT_LLS_PORT_32_LINKPHY_CONFIGr */
  62711         soc_block_list[85],
  62712         soc_genreg,
  62713         1,
  62714         0,
  62715         0x2007900,
  62716         0,
  62717         0,
  62718         4,
  62719         soc_LLS_PORT_27_LINKPHY_CONFIGr_fields,
  62720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62721         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  62722         -1,
  62723         -1,
  62724     },
  62725 #endif /* chips */
  62726 
  62727 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62728     { /* SOC_REG_INT_LLS_PORT_33_CREDITr */
  62729         soc_block_list[4],
  62730         soc_genreg,
  62731         1,
  62732         0,
  62733         0x5a003c00,
  62734         0,
  62735         0,
  62736         1,
  62737         soc_LLS_PORT_0_CREDITr_fields,
  62738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62739         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62740         -1,
  62741         -1,
  62742     },
  62743 #endif /* chips */
  62744 
  62745 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62746     defined(BCM_56450_B1)
  62747     { /* SOC_REG_INT_LLS_PORT_33_LINKPHY_CONFIGr */
  62748         soc_block_list[85],
  62749         soc_genreg,
  62750         1,
  62751         0,
  62752         0x2007a00,
  62753         0,
  62754         0,
  62755         4,
  62756         soc_LLS_PORT_27_LINKPHY_CONFIGr_fields,
  62757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62758         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  62759         -1,
  62760         -1,
  62761     },
  62762 #endif /* chips */
  62763 
  62764 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62765     { /* SOC_REG_INT_LLS_PORT_34_CREDITr */
  62766         soc_block_list[4],
  62767         soc_genreg,
  62768         1,
  62769         0,
  62770         0x5a003d00,
  62771         0,
  62772         0,
  62773         1,
  62774         soc_LLS_PORT_0_CREDITr_fields,
  62775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62776         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62777         -1,
  62778         -1,
  62779     },
  62780 #endif /* chips */
  62781 
  62782 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62783     defined(BCM_56450_B1)
  62784     { /* SOC_REG_INT_LLS_PORT_34_LINKPHY_CONFIGr */
  62785         soc_block_list[85],
  62786         soc_genreg,
  62787         1,
  62788         0,
  62789         0x2007b00,
  62790         0,
  62791         0,
  62792         4,
  62793         soc_LLS_PORT_27_LINKPHY_CONFIGr_fields,
  62794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62795         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  62796         -1,
  62797         -1,
  62798     },
  62799 #endif /* chips */
  62800 
  62801 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62802     { /* SOC_REG_INT_LLS_PORT_35_CREDITr */
  62803         soc_block_list[4],
  62804         soc_genreg,
  62805         1,
  62806         0,
  62807         0x5a003e00,
  62808         0,
  62809         0,
  62810         1,
  62811         soc_LLS_PORT_0_CREDITr_fields,
  62812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62813         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62814         -1,
  62815         -1,
  62816     },
  62817 #endif /* chips */
  62818 
  62819 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62820     defined(BCM_56450_B1)
  62821     { /* SOC_REG_INT_LLS_PORT_35_LINKPHY_CONFIGr */
  62822         soc_block_list[85],
  62823         soc_genreg,
  62824         1,
  62825         0,
  62826         0x2007c00,
  62827         0,
  62828         0,
  62829         2,
  62830         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62832         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62833         -1,
  62834         -1,
  62835     },
  62836 #endif /* chips */
  62837 
  62838 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62839     { /* SOC_REG_INT_LLS_PORT_36_CREDITr */
  62840         soc_block_list[4],
  62841         soc_genreg,
  62842         1,
  62843         0,
  62844         0x5a003f00,
  62845         0,
  62846         0,
  62847         1,
  62848         soc_LLS_PORT_0_CREDITr_fields,
  62849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62850         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62851         -1,
  62852         -1,
  62853     },
  62854 #endif /* chips */
  62855 
  62856 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62857     defined(BCM_56450_B1)
  62858     { /* SOC_REG_INT_LLS_PORT_36_LINKPHY_CONFIGr */
  62859         soc_block_list[85],
  62860         soc_genreg,
  62861         1,
  62862         0,
  62863         0x2007d00,
  62864         0,
  62865         0,
  62866         2,
  62867         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62869         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62870         -1,
  62871         -1,
  62872     },
  62873 #endif /* chips */
  62874 
  62875 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62876     { /* SOC_REG_INT_LLS_PORT_37_CREDITr */
  62877         soc_block_list[4],
  62878         soc_genreg,
  62879         1,
  62880         0,
  62881         0x5a004000,
  62882         0,
  62883         0,
  62884         1,
  62885         soc_LLS_PORT_0_CREDITr_fields,
  62886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62887         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62888         -1,
  62889         -1,
  62890     },
  62891 #endif /* chips */
  62892 
  62893 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62894     defined(BCM_56450_B1)
  62895     { /* SOC_REG_INT_LLS_PORT_37_LINKPHY_CONFIGr */
  62896         soc_block_list[85],
  62897         soc_genreg,
  62898         1,
  62899         0,
  62900         0x2007e00,
  62901         0,
  62902         0,
  62903         2,
  62904         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62906         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62907         -1,
  62908         -1,
  62909     },
  62910 #endif /* chips */
  62911 
  62912 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62913     { /* SOC_REG_INT_LLS_PORT_38_CREDITr */
  62914         soc_block_list[4],
  62915         soc_genreg,
  62916         1,
  62917         0,
  62918         0x5a004100,
  62919         0,
  62920         0,
  62921         1,
  62922         soc_LLS_PORT_0_CREDITr_fields,
  62923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62924         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62925         -1,
  62926         -1,
  62927     },
  62928 #endif /* chips */
  62929 
  62930 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62931     defined(BCM_56450_B1)
  62932     { /* SOC_REG_INT_LLS_PORT_38_LINKPHY_CONFIGr */
  62933         soc_block_list[85],
  62934         soc_genreg,
  62935         1,
  62936         0,
  62937         0x2007f00,
  62938         0,
  62939         0,
  62940         2,
  62941         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62943         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62944         -1,
  62945         -1,
  62946     },
  62947 #endif /* chips */
  62948 
  62949 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62950     { /* SOC_REG_INT_LLS_PORT_39_CREDITr */
  62951         soc_block_list[4],
  62952         soc_genreg,
  62953         1,
  62954         0,
  62955         0x5a004200,
  62956         0,
  62957         0,
  62958         1,
  62959         soc_LLS_PORT_0_CREDITr_fields,
  62960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62961         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62962         -1,
  62963         -1,
  62964     },
  62965 #endif /* chips */
  62966 
  62967 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  62968     defined(BCM_56450_B1)
  62969     { /* SOC_REG_INT_LLS_PORT_39_LINKPHY_CONFIGr */
  62970         soc_block_list[85],
  62971         soc_genreg,
  62972         1,
  62973         0,
  62974         0x2008000,
  62975         0,
  62976         0,
  62977         2,
  62978         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  62979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62980         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  62981         -1,
  62982         -1,
  62983     },
  62984 #endif /* chips */
  62985 
  62986 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  62987     { /* SOC_REG_INT_LLS_PORT_3_CREDITr */
  62988         soc_block_list[4],
  62989         soc_genreg,
  62990         1,
  62991         0,
  62992         0x5a001e00,
  62993         0,
  62994         0,
  62995         1,
  62996         soc_LLS_PORT_0_CREDITr_fields,
  62997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62998         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62999         -1,
  63000         -1,
  63001     },
  63002 #endif /* chips */
  63003 
  63004 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63005     { /* SOC_REG_INT_LLS_PORT_40_CREDITr */
  63006         soc_block_list[4],
  63007         soc_genreg,
  63008         1,
  63009         0,
  63010         0x5a004300,
  63011         0,
  63012         0,
  63013         1,
  63014         soc_LLS_PORT_0_CREDITr_fields,
  63015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63016         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63017         -1,
  63018         -1,
  63019     },
  63020 #endif /* chips */
  63021 
  63022 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  63023     defined(BCM_56450_B1)
  63024     { /* SOC_REG_INT_LLS_PORT_40_LINKPHY_CONFIGr */
  63025         soc_block_list[85],
  63026         soc_genreg,
  63027         1,
  63028         0,
  63029         0x2008100,
  63030         0,
  63031         0,
  63032         2,
  63033         soc_LLS_PORT_01_LINKPHY_CONFIGr_fields,
  63034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63035         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  63036         -1,
  63037         -1,
  63038     },
  63039 #endif /* chips */
  63040 
  63041 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63042     { /* SOC_REG_INT_LLS_PORT_41_CREDITr */
  63043         soc_block_list[4],
  63044         soc_genreg,
  63045         1,
  63046         0,
  63047         0x5a004400,
  63048         0,
  63049         0,
  63050         1,
  63051         soc_LLS_PORT_0_CREDITr_fields,
  63052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63053         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63054         -1,
  63055         -1,
  63056     },
  63057 #endif /* chips */
  63058 
  63059 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63060     { /* SOC_REG_INT_LLS_PORT_42_CREDITr */
  63061         soc_block_list[4],
  63062         soc_genreg,
  63063         1,
  63064         0,
  63065         0x5a004500,
  63066         0,
  63067         0,
  63068         1,
  63069         soc_LLS_PORT_0_CREDITr_fields,
  63070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63071         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63072         -1,
  63073         -1,
  63074     },
  63075 #endif /* chips */
  63076 
  63077 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63078     { /* SOC_REG_INT_LLS_PORT_43_CREDITr */
  63079         soc_block_list[4],
  63080         soc_genreg,
  63081         1,
  63082         0,
  63083         0x5a004600,
  63084         0,
  63085         0,
  63086         1,
  63087         soc_LLS_PORT_0_CREDITr_fields,
  63088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63089         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63090         -1,
  63091         -1,
  63092     },
  63093 #endif /* chips */
  63094 
  63095 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63096     { /* SOC_REG_INT_LLS_PORT_44_CREDITr */
  63097         soc_block_list[4],
  63098         soc_genreg,
  63099         1,
  63100         0,
  63101         0x5a004700,
  63102         0,
  63103         0,
  63104         1,
  63105         soc_LLS_PORT_0_CREDITr_fields,
  63106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63107         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63108         -1,
  63109         -1,
  63110     },
  63111 #endif /* chips */
  63112 
  63113 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63114     { /* SOC_REG_INT_LLS_PORT_45_CREDITr */
  63115         soc_block_list[4],
  63116         soc_genreg,
  63117         1,
  63118         0,
  63119         0x5a004800,
  63120         0,
  63121         0,
  63122         1,
  63123         soc_LLS_PORT_0_CREDITr_fields,
  63124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63125         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63126         -1,
  63127         -1,
  63128     },
  63129 #endif /* chips */
  63130 
  63131 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63132     { /* SOC_REG_INT_LLS_PORT_46_CREDITr */
  63133         soc_block_list[4],
  63134         soc_genreg,
  63135         1,
  63136         0,
  63137         0x5a004900,
  63138         0,
  63139         0,
  63140         1,
  63141         soc_LLS_PORT_0_CREDITr_fields,
  63142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63143         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63144         -1,
  63145         -1,
  63146     },
  63147 #endif /* chips */
  63148 
  63149 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63150     { /* SOC_REG_INT_LLS_PORT_47_CREDITr */
  63151         soc_block_list[4],
  63152         soc_genreg,
  63153         1,
  63154         0,
  63155         0x5a004a00,
  63156         0,
  63157         0,
  63158         1,
  63159         soc_LLS_PORT_0_CREDITr_fields,
  63160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63161         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63162         -1,
  63163         -1,
  63164     },
  63165 #endif /* chips */
  63166 
  63167 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63168     { /* SOC_REG_INT_LLS_PORT_48_CREDITr */
  63169         soc_block_list[4],
  63170         soc_genreg,
  63171         1,
  63172         0,
  63173         0x5a004b00,
  63174         0,
  63175         0,
  63176         1,
  63177         soc_LLS_PORT_0_CREDITr_fields,
  63178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63179         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63180         -1,
  63181         -1,
  63182     },
  63183 #endif /* chips */
  63184 
  63185 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63186     { /* SOC_REG_INT_LLS_PORT_49_CREDITr */
  63187         soc_block_list[4],
  63188         soc_genreg,
  63189         1,
  63190         0,
  63191         0x5a004c00,
  63192         0,
  63193         0,
  63194         1,
  63195         soc_LLS_PORT_0_CREDITr_fields,
  63196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63197         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63198         -1,
  63199         -1,
  63200     },
  63201 #endif /* chips */
  63202 
  63203 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63204     { /* SOC_REG_INT_LLS_PORT_4_CREDITr */
  63205         soc_block_list[4],
  63206         soc_genreg,
  63207         1,
  63208         0,
  63209         0x5a001f00,
  63210         0,
  63211         0,
  63212         1,
  63213         soc_LLS_PORT_0_CREDITr_fields,
  63214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63215         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63216         -1,
  63217         -1,
  63218     },
  63219 #endif /* chips */
  63220 
  63221 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63222     { /* SOC_REG_INT_LLS_PORT_50_CREDITr */
  63223         soc_block_list[4],
  63224         soc_genreg,
  63225         1,
  63226         0,
  63227         0x5a004d00,
  63228         0,
  63229         0,
  63230         1,
  63231         soc_LLS_PORT_0_CREDITr_fields,
  63232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63233         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63234         -1,
  63235         -1,
  63236     },
  63237 #endif /* chips */
  63238 
  63239 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63240     { /* SOC_REG_INT_LLS_PORT_51_CREDITr */
  63241         soc_block_list[4],
  63242         soc_genreg,
  63243         1,
  63244         0,
  63245         0x5a004e00,
  63246         0,
  63247         0,
  63248         1,
  63249         soc_LLS_PORT_0_CREDITr_fields,
  63250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63251         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63252         -1,
  63253         -1,
  63254     },
  63255 #endif /* chips */
  63256 
  63257 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63258     { /* SOC_REG_INT_LLS_PORT_52_CREDITr */
  63259         soc_block_list[4],
  63260         soc_genreg,
  63261         1,
  63262         0,
  63263         0x5a004f00,
  63264         0,
  63265         0,
  63266         1,
  63267         soc_LLS_PORT_0_CREDITr_fields,
  63268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63269         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63270         -1,
  63271         -1,
  63272     },
  63273 #endif /* chips */
  63274 
  63275 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63276     { /* SOC_REG_INT_LLS_PORT_53_CREDITr */
  63277         soc_block_list[4],
  63278         soc_genreg,
  63279         1,
  63280         0,
  63281         0x5a005000,
  63282         0,
  63283         0,
  63284         1,
  63285         soc_LLS_PORT_0_CREDITr_fields,
  63286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63287         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63288         -1,
  63289         -1,
  63290     },
  63291 #endif /* chips */
  63292 
  63293 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63294     { /* SOC_REG_INT_LLS_PORT_54_CREDITr */
  63295         soc_block_list[4],
  63296         soc_genreg,
  63297         1,
  63298         0,
  63299         0x5a005100,
  63300         0,
  63301         0,
  63302         1,
  63303         soc_LLS_PORT_0_CREDITr_fields,
  63304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63305         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63306         -1,
  63307         -1,
  63308     },
  63309 #endif /* chips */
  63310 
  63311 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63312     { /* SOC_REG_INT_LLS_PORT_55_CREDITr */
  63313         soc_block_list[4],
  63314         soc_genreg,
  63315         1,
  63316         0,
  63317         0x5a005200,
  63318         0,
  63319         0,
  63320         1,
  63321         soc_LLS_PORT_0_CREDITr_fields,
  63322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63323         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63324         -1,
  63325         -1,
  63326     },
  63327 #endif /* chips */
  63328 
  63329 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63330     { /* SOC_REG_INT_LLS_PORT_56_CREDITr */
  63331         soc_block_list[4],
  63332         soc_genreg,
  63333         1,
  63334         0,
  63335         0x5a005300,
  63336         0,
  63337         0,
  63338         1,
  63339         soc_LLS_PORT_0_CREDITr_fields,
  63340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63341         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63342         -1,
  63343         -1,
  63344     },
  63345 #endif /* chips */
  63346 
  63347 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63348     { /* SOC_REG_INT_LLS_PORT_57_CREDITr */
  63349         soc_block_list[4],
  63350         soc_genreg,
  63351         1,
  63352         0,
  63353         0x5a005400,
  63354         0,
  63355         0,
  63356         1,
  63357         soc_LLS_PORT_0_CREDITr_fields,
  63358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63359         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63360         -1,
  63361         -1,
  63362     },
  63363 #endif /* chips */
  63364 
  63365 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63366     { /* SOC_REG_INT_LLS_PORT_58_CREDITr */
  63367         soc_block_list[4],
  63368         soc_genreg,
  63369         1,
  63370         0,
  63371         0x5a005500,
  63372         0,
  63373         0,
  63374         1,
  63375         soc_LLS_PORT_0_CREDITr_fields,
  63376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63377         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63378         -1,
  63379         -1,
  63380     },
  63381 #endif /* chips */
  63382 
  63383 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63384     { /* SOC_REG_INT_LLS_PORT_59_CREDITr */
  63385         soc_block_list[4],
  63386         soc_genreg,
  63387         1,
  63388         0,
  63389         0x5a005600,
  63390         0,
  63391         0,
  63392         1,
  63393         soc_LLS_PORT_0_CREDITr_fields,
  63394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63395         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63396         -1,
  63397         -1,
  63398     },
  63399 #endif /* chips */
  63400 
  63401 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63402     { /* SOC_REG_INT_LLS_PORT_5_CREDITr */
  63403         soc_block_list[4],
  63404         soc_genreg,
  63405         1,
  63406         0,
  63407         0x5a002000,
  63408         0,
  63409         0,
  63410         1,
  63411         soc_LLS_PORT_0_CREDITr_fields,
  63412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63413         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63414         -1,
  63415         -1,
  63416     },
  63417 #endif /* chips */
  63418 
  63419 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63420     { /* SOC_REG_INT_LLS_PORT_60_CREDITr */
  63421         soc_block_list[4],
  63422         soc_genreg,
  63423         1,
  63424         0,
  63425         0x5a005700,
  63426         0,
  63427         0,
  63428         1,
  63429         soc_LLS_PORT_0_CREDITr_fields,
  63430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63431         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63432         -1,
  63433         -1,
  63434     },
  63435 #endif /* chips */
  63436 
  63437 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63438     { /* SOC_REG_INT_LLS_PORT_61_CREDITr */
  63439         soc_block_list[4],
  63440         soc_genreg,
  63441         1,
  63442         0,
  63443         0x5a005800,
  63444         0,
  63445         0,
  63446         1,
  63447         soc_LLS_PORT_0_CREDITr_fields,
  63448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63449         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63450         -1,
  63451         -1,
  63452     },
  63453 #endif /* chips */
  63454 
  63455 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63456     { /* SOC_REG_INT_LLS_PORT_62_CREDITr */
  63457         soc_block_list[4],
  63458         soc_genreg,
  63459         1,
  63460         0,
  63461         0x5a005900,
  63462         0,
  63463         0,
  63464         1,
  63465         soc_LLS_PORT_0_CREDITr_fields,
  63466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63467         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63468         -1,
  63469         -1,
  63470     },
  63471 #endif /* chips */
  63472 
  63473 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63474     { /* SOC_REG_INT_LLS_PORT_6_CREDITr */
  63475         soc_block_list[4],
  63476         soc_genreg,
  63477         1,
  63478         0,
  63479         0x5a002100,
  63480         0,
  63481         0,
  63482         1,
  63483         soc_LLS_PORT_0_CREDITr_fields,
  63484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63485         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63486         -1,
  63487         -1,
  63488     },
  63489 #endif /* chips */
  63490 
  63491 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63492     { /* SOC_REG_INT_LLS_PORT_7_CREDITr */
  63493         soc_block_list[4],
  63494         soc_genreg,
  63495         1,
  63496         0,
  63497         0x5a002200,
  63498         0,
  63499         0,
  63500         1,
  63501         soc_LLS_PORT_0_CREDITr_fields,
  63502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63503         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63504         -1,
  63505         -1,
  63506     },
  63507 #endif /* chips */
  63508 
  63509 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63510     { /* SOC_REG_INT_LLS_PORT_8_CREDITr */
  63511         soc_block_list[4],
  63512         soc_genreg,
  63513         1,
  63514         0,
  63515         0x5a002300,
  63516         0,
  63517         0,
  63518         1,
  63519         soc_LLS_PORT_0_CREDITr_fields,
  63520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63521         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63522         -1,
  63523         -1,
  63524     },
  63525 #endif /* chips */
  63526 
  63527 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63528     { /* SOC_REG_INT_LLS_PORT_9_CREDITr */
  63529         soc_block_list[4],
  63530         soc_genreg,
  63531         1,
  63532         0,
  63533         0x5a002400,
  63534         0,
  63535         0,
  63536         1,
  63537         soc_LLS_PORT_0_CREDITr_fields,
  63538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63539         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  63540         -1,
  63541         -1,
  63542     },
  63543 #endif /* chips */
  63544 
  63545 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  63546     { /* SOC_REG_INT_LLS_PORT_COE_ENABLEr */
  63547         soc_block_list[85],
  63548         soc_genreg,
  63549         1,
  63550         0,
  63551         0x2005b00,
  63552         0,
  63553         0,
  63554         29,
  63555         soc_LLS_PORT_COE_ENABLEr_fields,
  63556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63557         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  63558         -1,
  63559         -1,
  63560     },
  63561 #endif /* chips */
  63562 
  63563 #if defined(BCM_56270_A0)
  63564     { /* SOC_REG_INT_LLS_PORT_COE_ENABLE_BCM56270_A0r */
  63565         soc_block_list[85],
  63566         soc_genreg,
  63567         1,
  63568         0,
  63569         0x2005700,
  63570         0,
  63571         0,
  63572         13,
  63573         soc_LLS_PORT_COE_ENABLE_BCM56270_A0r_fields,
  63574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63575         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  63576         -1,
  63577         -1,
  63578     },
  63579 #endif /* chips */
  63580 
  63581 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  63582     defined(BCM_56450_B1)
  63583     { /* SOC_REG_INT_LLS_PORT_COE_LINKPHY_ENABLE_LOWERr */
  63584         soc_block_list[85],
  63585         soc_genreg,
  63586         1,
  63587         0,
  63588         0x2005800,
  63589         0,
  63590         0,
  63591         32,
  63592         soc_LLS_PORT_COE_LINKPHY_ENABLE_LOWERr_fields,
  63593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63594         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  63595         -1,
  63596         -1,
  63597     },
  63598 #endif /* chips */
  63599 
  63600 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  63601     defined(BCM_56450_B1)
  63602     { /* SOC_REG_INT_LLS_PORT_COE_LINKPHY_ENABLE_UPPERr */
  63603         soc_block_list[85],
  63604         soc_genreg,
  63605         1,
  63606         0,
  63607         0x2005700,
  63608         0,
  63609         0,
  63610         9,
  63611         soc_LLS_PORT_COE_LINKPHY_ENABLE_UPPERr_fields,
  63612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63613         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  63614         -1,
  63615         -1,
  63616     },
  63617 #endif /* chips */
  63618 
  63619 #if defined(BCM_56440_A0)
  63620     { /* SOC_REG_INT_LLS_PORT_ECC_1B_COUNTERr */
  63621         soc_block_list[85],
  63622         soc_genreg,
  63623         1,
  63624         0,
  63625         0x80063,
  63626         0,
  63627         0,
  63628         1,
  63629         soc_LLS_PORT_ECC_1B_COUNTERr_fields,
  63630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63631         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63632         -1,
  63633         -1,
  63634     },
  63635 #endif /* chips */
  63636 
  63637 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  63638     { /* SOC_REG_INT_LLS_PORT_ECC_1B_COUNTER_BCM56260_A0r */
  63639         soc_block_list[85],
  63640         soc_genreg,
  63641         1,
  63642         0,
  63643         0x200bc00,
  63644         0,
  63645         0,
  63646         1,
  63647         soc_LLS_PORT_ECC_1B_COUNTER_BCM56260_A0r_fields,
  63648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63649         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63650         -1,
  63651         -1,
  63652     },
  63653 #endif /* chips */
  63654 
  63655 #if defined(BCM_56270_A0)
  63656     { /* SOC_REG_INT_LLS_PORT_ECC_1B_COUNTER_BCM56270_A0r */
  63657         soc_block_list[85],
  63658         soc_genreg,
  63659         1,
  63660         0,
  63661         0x200a300,
  63662         0,
  63663         0,
  63664         1,
  63665         soc_LLS_PORT_ECC_1B_COUNTER_BCM56260_A0r_fields,
  63666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63667         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63668         -1,
  63669         -1,
  63670     },
  63671 #endif /* chips */
  63672 
  63673 #if defined(BCM_56440_B0)
  63674     { /* SOC_REG_INT_LLS_PORT_ECC_1B_COUNTER_BCM56440_B0r */
  63675         soc_block_list[85],
  63676         soc_genreg,
  63677         1,
  63678         0,
  63679         0x8006b,
  63680         0,
  63681         0,
  63682         1,
  63683         soc_LLS_PORT_ECC_1B_COUNTERr_fields,
  63684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63685         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63686         -1,
  63687         -1,
  63688     },
  63689 #endif /* chips */
  63690 
  63691 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  63692     defined(BCM_56450_B1)
  63693     { /* SOC_REG_INT_LLS_PORT_ECC_1B_COUNTER_BCM56450_A0r */
  63694         soc_block_list[85],
  63695         soc_genreg,
  63696         1,
  63697         0,
  63698         0x2013e00,
  63699         0,
  63700         0,
  63701         1,
  63702         soc_LLS_PORT_ECC_1B_COUNTER_BCM56450_A0r_fields,
  63703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63704         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63705         -1,
  63706         -1,
  63707     },
  63708 #endif /* chips */
  63709 
  63710 #if defined(BCM_56440_A0)
  63711     { /* SOC_REG_INT_LLS_PORT_ECC_2B_COUNTERr */
  63712         soc_block_list[85],
  63713         soc_genreg,
  63714         1,
  63715         0,
  63716         0x80064,
  63717         0,
  63718         0,
  63719         1,
  63720         soc_LLS_PORT_ECC_2B_COUNTERr_fields,
  63721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63722         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63723         -1,
  63724         -1,
  63725     },
  63726 #endif /* chips */
  63727 
  63728 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  63729     { /* SOC_REG_INT_LLS_PORT_ECC_2B_COUNTER_BCM56260_A0r */
  63730         soc_block_list[85],
  63731         soc_genreg,
  63732         1,
  63733         0,
  63734         0x200bd00,
  63735         0,
  63736         0,
  63737         1,
  63738         soc_LLS_PORT_ECC_2B_COUNTER_BCM56260_A0r_fields,
  63739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63740         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63741         -1,
  63742         -1,
  63743     },
  63744 #endif /* chips */
  63745 
  63746 #if defined(BCM_56270_A0)
  63747     { /* SOC_REG_INT_LLS_PORT_ECC_2B_COUNTER_BCM56270_A0r */
  63748         soc_block_list[85],
  63749         soc_genreg,
  63750         1,
  63751         0,
  63752         0x200a400,
  63753         0,
  63754         0,
  63755         1,
  63756         soc_LLS_PORT_ECC_2B_COUNTER_BCM56260_A0r_fields,
  63757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63758         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63759         -1,
  63760         -1,
  63761     },
  63762 #endif /* chips */
  63763 
  63764 #if defined(BCM_56440_B0)
  63765     { /* SOC_REG_INT_LLS_PORT_ECC_2B_COUNTER_BCM56440_B0r */
  63766         soc_block_list[85],
  63767         soc_genreg,
  63768         1,
  63769         0,
  63770         0x8006c,
  63771         0,
  63772         0,
  63773         1,
  63774         soc_LLS_PORT_ECC_2B_COUNTERr_fields,
  63775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63776         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63777         -1,
  63778         -1,
  63779     },
  63780 #endif /* chips */
  63781 
  63782 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  63783     defined(BCM_56450_B1)
  63784     { /* SOC_REG_INT_LLS_PORT_ECC_2B_COUNTER_BCM56450_A0r */
  63785         soc_block_list[85],
  63786         soc_genreg,
  63787         1,
  63788         0,
  63789         0x2013f00,
  63790         0,
  63791         0,
  63792         1,
  63793         soc_LLS_PORT_ECC_2B_COUNTER_BCM56450_A0r_fields,
  63794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63795         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63796         -1,
  63797         -1,
  63798     },
  63799 #endif /* chips */
  63800 
  63801 #if defined(BCM_56440_A0)
  63802     { /* SOC_REG_INT_LLS_PORT_ECC_DEBUGr */
  63803         soc_block_list[85],
  63804         soc_genreg,
  63805         1,
  63806         0,
  63807         0x8006b,
  63808         0,
  63809         0,
  63810         6,
  63811         soc_LLS_PORT_ECC_DEBUGr_fields,
  63812         SOC_RESET_VAL_DEC(0x00000015, 0x00000000)
  63813         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63814         -1,
  63815         -1,
  63816     },
  63817 #endif /* chips */
  63818 
  63819 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  63820     { /* SOC_REG_INT_LLS_PORT_ECC_DEBUG_BCM56260_A0r */
  63821         soc_block_list[85],
  63822         soc_genreg,
  63823         1,
  63824         0,
  63825         0x200c600,
  63826         0,
  63827         0,
  63828         2,
  63829         soc_LLS_PORT_ECC_DEBUG_BCM56260_A0r_fields,
  63830         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  63831         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63832         -1,
  63833         -1,
  63834     },
  63835 #endif /* chips */
  63836 
  63837 #if defined(BCM_56270_A0)
  63838     { /* SOC_REG_INT_LLS_PORT_ECC_DEBUG_BCM56270_A0r */
  63839         soc_block_list[85],
  63840         soc_genreg,
  63841         1,
  63842         0,
  63843         0x200ad00,
  63844         0,
  63845         0,
  63846         2,
  63847         soc_LLS_PORT_ECC_DEBUG_BCM56260_A0r_fields,
  63848         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  63849         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63850         -1,
  63851         -1,
  63852     },
  63853 #endif /* chips */
  63854 
  63855 #if defined(BCM_56440_B0)
  63856     { /* SOC_REG_INT_LLS_PORT_ECC_DEBUG_BCM56440_B0r */
  63857         soc_block_list[85],
  63858         soc_genreg,
  63859         1,
  63860         0,
  63861         0x80073,
  63862         0,
  63863         0,
  63864         6,
  63865         soc_LLS_PORT_ECC_DEBUGr_fields,
  63866         SOC_RESET_VAL_DEC(0x00000015, 0x00000000)
  63867         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63868         -1,
  63869         -1,
  63870     },
  63871 #endif /* chips */
  63872 
  63873 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  63874     defined(BCM_56450_B1)
  63875     { /* SOC_REG_INT_LLS_PORT_ECC_DEBUG_BCM56450_A0r */
  63876         soc_block_list[85],
  63877         soc_genreg,
  63878         1,
  63879         0,
  63880         0x2014800,
  63881         0,
  63882         0,
  63883         16,
  63884         soc_LLS_PORT_ECC_DEBUG_BCM56450_A0r_fields,
  63885         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  63886         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63887         -1,
  63888         -1,
  63889     },
  63890 #endif /* chips */
  63891 
  63892 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  63893     { /* SOC_REG_INT_LLS_PORT_ECC_DEBUG_BCM56640_A0r */
  63894         soc_block_list[4],
  63895         soc_genreg,
  63896         1,
  63897         0,
  63898         0x5a007600,
  63899         0,
  63900         0,
  63901         2,
  63902         soc_LLS_PORT_ECC_DEBUG_BCM56640_A0r_fields,
  63903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63904         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  63905         -1,
  63906         -1,
  63907     },
  63908 #endif /* chips */
  63909 
  63910 #if defined(BCM_56440_A0)
  63911     { /* SOC_REG_INT_LLS_PORT_ECC_ERRORr */
  63912         soc_block_list[85],
  63913         soc_genreg,
  63914         1,
  63915         0,
  63916         0x80073,
  63917         0,
  63918         0,
  63919         6,
  63920         soc_LLS_PORT_ECC_ERRORr_fields,
  63921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63922         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63923         -1,
  63924         -1,
  63925     },
  63926 #endif /* chips */
  63927 
  63928 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  63929     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_BCM56260_A0r */
  63930         soc_block_list[85],
  63931         soc_genreg,
  63932         1,
  63933         0,
  63934         0x200ce00,
  63935         0,
  63936         0,
  63937         2,
  63938         soc_LLS_PORT_ECC_ERROR_BCM56260_A0r_fields,
  63939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63940         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  63941         -1,
  63942         -1,
  63943     },
  63944 #endif /* chips */
  63945 
  63946 #if defined(BCM_56270_A0)
  63947     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_BCM56270_A0r */
  63948         soc_block_list[85],
  63949         soc_genreg,
  63950         1,
  63951         0,
  63952         0x200b500,
  63953         0,
  63954         0,
  63955         2,
  63956         soc_LLS_PORT_ECC_ERROR_BCM56260_A0r_fields,
  63957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63958         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  63959         -1,
  63960         -1,
  63961     },
  63962 #endif /* chips */
  63963 
  63964 #if defined(BCM_56440_B0)
  63965     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_BCM56440_B0r */
  63966         soc_block_list[85],
  63967         soc_genreg,
  63968         1,
  63969         0,
  63970         0x8007b,
  63971         0,
  63972         0,
  63973         6,
  63974         soc_LLS_PORT_ECC_ERRORr_fields,
  63975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63976         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  63977         -1,
  63978         -1,
  63979     },
  63980 #endif /* chips */
  63981 
  63982 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  63983     defined(BCM_56450_B1)
  63984     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_BCM56450_A0r */
  63985         soc_block_list[85],
  63986         soc_genreg,
  63987         1,
  63988         0,
  63989         0x2015000,
  63990         0,
  63991         0,
  63992         16,
  63993         soc_LLS_PORT_ECC_ERROR_BCM56450_A0r_fields,
  63994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63995         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  63996         -1,
  63997         -1,
  63998     },
  63999 #endif /* chips */
  64000 
  64001 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  64002     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_BCM56640_A0r */
  64003         soc_block_list[4],
  64004         soc_genreg,
  64005         1,
  64006         0,
  64007         0x5a007a00,
  64008         0,
  64009         0,
  64010         4,
  64011         soc_LLS_PORT_ECC_ERROR_BCM56640_A0r_fields,
  64012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64013         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  64014         -1,
  64015         -1,
  64016     },
  64017 #endif /* chips */
  64018 
  64019 #if defined(BCM_56440_A0)
  64020     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_MASKr */
  64021         soc_block_list[85],
  64022         soc_genreg,
  64023         1,
  64024         0,
  64025         0x80074,
  64026         0,
  64027         0,
  64028         6,
  64029         soc_LLS_PORT_ECC_ERROR_MASKr_fields,
  64030         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  64031         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64032         -1,
  64033         -1,
  64034     },
  64035 #endif /* chips */
  64036 
  64037 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64038     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_MASK_BCM56260_A0r */
  64039         soc_block_list[85],
  64040         soc_genreg,
  64041         1,
  64042         0,
  64043         0x200cf00,
  64044         0,
  64045         0,
  64046         2,
  64047         soc_LLS_PORT_ECC_ERROR_MASK_BCM56260_A0r_fields,
  64048         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  64049         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  64050         -1,
  64051         -1,
  64052     },
  64053 #endif /* chips */
  64054 
  64055 #if defined(BCM_56270_A0)
  64056     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_MASK_BCM56270_A0r */
  64057         soc_block_list[85],
  64058         soc_genreg,
  64059         1,
  64060         0,
  64061         0x200b600,
  64062         0,
  64063         0,
  64064         2,
  64065         soc_LLS_PORT_ECC_ERROR_MASK_BCM56260_A0r_fields,
  64066         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  64067         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  64068         -1,
  64069         -1,
  64070     },
  64071 #endif /* chips */
  64072 
  64073 #if defined(BCM_56440_B0)
  64074     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_MASK_BCM56440_B0r */
  64075         soc_block_list[85],
  64076         soc_genreg,
  64077         1,
  64078         0,
  64079         0x8007c,
  64080         0,
  64081         0,
  64082         6,
  64083         soc_LLS_PORT_ECC_ERROR_MASKr_fields,
  64084         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  64085         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64086         -1,
  64087         -1,
  64088     },
  64089 #endif /* chips */
  64090 
  64091 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64092     defined(BCM_56450_B1)
  64093     { /* SOC_REG_INT_LLS_PORT_ECC_ERROR_MASK_BCM56450_A0r */
  64094         soc_block_list[85],
  64095         soc_genreg,
  64096         1,
  64097         0,
  64098         0x2015100,
  64099         0,
  64100         0,
  64101         16,
  64102         soc_LLS_PORT_ECC_ERROR_MASK_BCM56450_A0r_fields,
  64103         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  64104         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  64105         -1,
  64106         -1,
  64107     },
  64108 #endif /* chips */
  64109 
  64110 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64111     defined(BCM_56450_B1)
  64112     { /* SOC_REG_INT_LLS_PORT_EMPTY_SEEN_STATUSr */
  64113         soc_block_list[85],
  64114         soc_genreg,
  64115         1,
  64116         0,
  64117         0x2010e00,
  64118         0,
  64119         0,
  64120         1,
  64121         soc_LLS_PORT_EMPTY_SEEN_STATUSr_fields,
  64122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64123         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64124         -1,
  64125         -1,
  64126     },
  64127 #endif /* chips */
  64128 
  64129 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64130     { /* SOC_REG_INT_LLS_PORT_EMPTY_SEEN_STATUS_BCM56260_A0r */
  64131         soc_block_list[85],
  64132         soc_genreg,
  64133         1,
  64134         0,
  64135         0x2008f00,
  64136         0,
  64137         0,
  64138         1,
  64139         soc_LLS_PORT_EMPTY_SEEN_STATUS_BCM56260_A0r_fields,
  64140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64141         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  64142         -1,
  64143         -1,
  64144     },
  64145 #endif /* chips */
  64146 
  64147 #if defined(BCM_56270_A0)
  64148     { /* SOC_REG_INT_LLS_PORT_EMPTY_SEEN_STATUS_BCM56270_A0r */
  64149         soc_block_list[85],
  64150         soc_genreg,
  64151         1,
  64152         0,
  64153         0x2007600,
  64154         0,
  64155         0,
  64156         1,
  64157         soc_LLS_PORT_EMPTY_SEEN_STATUS_BCM56270_A0r_fields,
  64158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64159         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  64160         -1,
  64161         -1,
  64162     },
  64163 #endif /* chips */
  64164 
  64165 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  64166     { /* SOC_REG_INT_LLS_PORT_EMPTY_SEEN_STATUS_BCM56560_A0r */
  64167         soc_block_list[4],
  64168         soc_genreg,
  64169         1,
  64170         0,
  64171         0x62003e00,
  64172         0,
  64173         0,
  64174         1,
  64175         soc_LLS_PORT_EMPTY_SEEN_STATUS_BCM56560_A0r_fields,
  64176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64177         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  64178         -1,
  64179         -1,
  64180     },
  64181 #endif /* chips */
  64182 
  64183 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64184     defined(BCM_56450_B1)
  64185     { /* SOC_REG_INT_LLS_PORT_L2_COUNT_CPU_ADDRr */
  64186         soc_block_list[85],
  64187         soc_genreg,
  64188         1,
  64189         0,
  64190         0x2002400,
  64191         0,
  64192         0,
  64193         1,
  64194         soc_LLS_PORT_L2_COUNT_CPU_ADDRr_fields,
  64195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64196         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64197         -1,
  64198         -1,
  64199     },
  64200 #endif /* chips */
  64201 
  64202 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64203     { /* SOC_REG_INT_LLS_PORT_L2_COUNT_CPU_ADDR_BCM56260_A0r */
  64204         soc_block_list[85],
  64205         soc_genreg,
  64206         1,
  64207         0,
  64208         0x2002500,
  64209         0,
  64210         0,
  64211         1,
  64212         soc_LLS_PORT_L2_COUNT_CPU_ADDR_BCM56260_A0r_fields,
  64213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64214         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  64215         -1,
  64216         -1,
  64217     },
  64218 #endif /* chips */
  64219 
  64220 #if defined(BCM_56270_A0)
  64221     { /* SOC_REG_INT_LLS_PORT_L2_COUNT_CPU_ADDR_BCM56270_A0r */
  64222         soc_block_list[85],
  64223         soc_genreg,
  64224         1,
  64225         0,
  64226         0x2002500,
  64227         0,
  64228         0,
  64229         1,
  64230         soc_LLS_PORT_L2_COUNT_CPU_ADDR_BCM56270_A0r_fields,
  64231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64232         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  64233         -1,
  64234         -1,
  64235     },
  64236 #endif /* chips */
  64237 
  64238 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  64239     { /* SOC_REG_INT_LLS_PORT_L2_COUNT_CPU_ADDR_BCM56560_A0r */
  64240         soc_block_list[4],
  64241         soc_genreg,
  64242         1,
  64243         0,
  64244         0x62001d00,
  64245         0,
  64246         0,
  64247         1,
  64248         soc_LLS_PORT_L2_COUNT_CPU_ADDR_BCM56560_A0r_fields,
  64249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64250         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  64251         -1,
  64252         -1,
  64253     },
  64254 #endif /* chips */
  64255 
  64256 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64257     defined(BCM_56450_B1)
  64258     { /* SOC_REG_INT_LLS_PORT_L2_COUNT_CPU_DATAr */
  64259         soc_block_list[85],
  64260         soc_genreg,
  64261         1,
  64262         0,
  64263         0x2002500,
  64264         0,
  64265         0,
  64266         1,
  64267         soc_LLS_PORT_L2_COUNT_CPU_DATAr_fields,
  64268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64269         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  64270         -1,
  64271         -1,
  64272     },
  64273 #endif /* chips */
  64274 
  64275 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64276     { /* SOC_REG_INT_LLS_PORT_L2_COUNT_CPU_DATA_BCM56260_A0r */
  64277         soc_block_list[85],
  64278         soc_genreg,
  64279         1,
  64280         0,
  64281         0x2002600,
  64282         0,
  64283         0,
  64284         1,
  64285         soc_LLS_PORT_L2_COUNT_CPU_DATA_BCM56260_A0r_fields,
  64286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64287         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  64288         -1,
  64289         -1,
  64290     },
  64291 #endif /* chips */
  64292 
  64293 #if defined(BCM_56270_A0)
  64294     { /* SOC_REG_INT_LLS_PORT_L2_COUNT_CPU_DATA_BCM56270_A0r */
  64295         soc_block_list[85],
  64296         soc_genreg,
  64297         1,
  64298         0,
  64299         0x2002600,
  64300         0,
  64301         0,
  64302         1,
  64303         soc_LLS_PORT_L2_COUNT_CPU_DATA_BCM56270_A0r_fields,
  64304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64305         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  64306         -1,
  64307         -1,
  64308     },
  64309 #endif /* chips */
  64310 
  64311 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  64312     { /* SOC_REG_INT_LLS_PORT_L2_COUNT_CPU_DATA_BCM56560_A0r */
  64313         soc_block_list[4],
  64314         soc_genreg,
  64315         1,
  64316         0,
  64317         0x62001e00,
  64318         0,
  64319         0,
  64320         1,
  64321         soc_LLS_PORT_L2_COUNT_CPU_DATA_BCM56560_A0r_fields,
  64322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64323         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  64324         -1,
  64325         -1,
  64326     },
  64327 #endif /* chips */
  64328 
  64329 #if defined(BCM_56440_A0)
  64330     { /* SOC_REG_INT_LLS_PORT_SHAPER_CONFIG_C_ECC_STATUSr */
  64331         soc_block_list[85],
  64332         soc_genreg,
  64333         1,
  64334         0,
  64335         0x8007d,
  64336         0,
  64337         0,
  64338         1,
  64339         soc_LLS_PORT_SHAPER_CONFIG_C_ECC_STATUSr_fields,
  64340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64341         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64342         -1,
  64343         -1,
  64344     },
  64345 #endif /* chips */
  64346 
  64347 #if defined(BCM_56440_B0)
  64348     { /* SOC_REG_INT_LLS_PORT_SHAPER_CONFIG_C_ECC_STATUS_BCM56440_B0r */
  64349         soc_block_list[85],
  64350         soc_genreg,
  64351         1,
  64352         0,
  64353         0x80085,
  64354         0,
  64355         0,
  64356         1,
  64357         soc_LLS_PORT_SHAPER_CONFIG_C_ECC_STATUSr_fields,
  64358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64359         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64360         -1,
  64361         -1,
  64362     },
  64363 #endif /* chips */
  64364 
  64365 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64366     defined(BCM_56450_B1)
  64367     { /* SOC_REG_INT_LLS_PORT_SHAPER_CONFIG_C_ECC_STATUS_BCM56450_A0r */
  64368         soc_block_list[85],
  64369         soc_genreg,
  64370         1,
  64371         0,
  64372         0x2015f00,
  64373         0,
  64374         0,
  64375         1,
  64376         soc_LLS_PORT_SHAPER_CONFIG_C_ECC_STATUS_BCM56450_A0r_fields,
  64377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64378         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64379         -1,
  64380         -1,
  64381     },
  64382 #endif /* chips */
  64383 
  64384 #if defined(BCM_56440_A0)
  64385     { /* SOC_REG_INT_LLS_PORT_TDM_ECC_STATUSr */
  64386         soc_block_list[85],
  64387         soc_genreg,
  64388         1,
  64389         0,
  64390         0x800ae,
  64391         0,
  64392         0,
  64393         1,
  64394         soc_LLS_PORT_TDM_ECC_STATUSr_fields,
  64395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64396         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  64397         -1,
  64398         -1,
  64399     },
  64400 #endif /* chips */
  64401 
  64402 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64403     { /* SOC_REG_INT_LLS_PORT_TDM_ECC_STATUS_BCM56260_A0r */
  64404         soc_block_list[85],
  64405         soc_genreg,
  64406         1,
  64407         0,
  64408         0x2010000,
  64409         0,
  64410         0,
  64411         1,
  64412         soc_LLS_PORT_TDM_ECC_STATUS_BCM56260_A0r_fields,
  64413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64414         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  64415         -1,
  64416         -1,
  64417     },
  64418 #endif /* chips */
  64419 
  64420 #if defined(BCM_56270_A0)
  64421     { /* SOC_REG_INT_LLS_PORT_TDM_ECC_STATUS_BCM56270_A0r */
  64422         soc_block_list[85],
  64423         soc_genreg,
  64424         1,
  64425         0,
  64426         0x200e700,
  64427         0,
  64428         0,
  64429         1,
  64430         soc_LLS_PORT_TDM_ECC_STATUS_BCM56260_A0r_fields,
  64431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64432         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  64433         -1,
  64434         -1,
  64435     },
  64436 #endif /* chips */
  64437 
  64438 #if defined(BCM_56440_B0)
  64439     { /* SOC_REG_INT_LLS_PORT_TDM_ECC_STATUS_BCM56440_B0r */
  64440         soc_block_list[85],
  64441         soc_genreg,
  64442         1,
  64443         0,
  64444         0x800b9,
  64445         0,
  64446         0,
  64447         1,
  64448         soc_LLS_PORT_TDM_ECC_STATUSr_fields,
  64449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64450         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  64451         -1,
  64452         -1,
  64453     },
  64454 #endif /* chips */
  64455 
  64456 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64457     defined(BCM_56450_B1)
  64458     { /* SOC_REG_INT_LLS_PORT_TDM_ECC_STATUS_BCM56450_A0r */
  64459         soc_block_list[85],
  64460         soc_genreg,
  64461         1,
  64462         0,
  64463         0x2019500,
  64464         0,
  64465         0,
  64466         1,
  64467         soc_LLS_PORT_TDM_ECC_STATUS_BCM56450_A0r_fields,
  64468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64469         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  64470         -1,
  64471         -1,
  64472     },
  64473 #endif /* chips */
  64474 
  64475 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  64476     { /* SOC_REG_INT_LLS_PORT_TDM_ECC_STATUS_BCM56640_A0r */
  64477         soc_block_list[4],
  64478         soc_genreg,
  64479         1,
  64480         0,
  64481         0x5a007f00,
  64482         0,
  64483         0,
  64484         1,
  64485         soc_LLS_PORT_TDM_ECC_STATUS_BCM56640_A0r_fields,
  64486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64487         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  64488         -1,
  64489         -1,
  64490     },
  64491 #endif /* chips */
  64492 
  64493 #if defined(BCM_56440_A0)
  64494     { /* SOC_REG_INT_LLS_PORT_WERR_MAX_SC_ECC_STATUSr */
  64495         soc_block_list[85],
  64496         soc_genreg,
  64497         1,
  64498         0,
  64499         0x8007e,
  64500         0,
  64501         0,
  64502         1,
  64503         soc_LLS_PORT_WERR_MAX_SC_ECC_STATUSr_fields,
  64504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64505         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64506         -1,
  64507         -1,
  64508     },
  64509 #endif /* chips */
  64510 
  64511 #if defined(BCM_56440_B0)
  64512     { /* SOC_REG_INT_LLS_PORT_WERR_MAX_SC_ECC_STATUS_BCM56440_B0r */
  64513         soc_block_list[85],
  64514         soc_genreg,
  64515         1,
  64516         0,
  64517         0x80086,
  64518         0,
  64519         0,
  64520         1,
  64521         soc_LLS_PORT_WERR_MAX_SC_ECC_STATUSr_fields,
  64522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64523         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64524         -1,
  64525         -1,
  64526     },
  64527 #endif /* chips */
  64528 
  64529 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64530     defined(BCM_56450_B1)
  64531     { /* SOC_REG_INT_LLS_PORT_WERR_MAX_SC_ECC_STATUS_BCM56450_A0r */
  64532         soc_block_list[85],
  64533         soc_genreg,
  64534         1,
  64535         0,
  64536         0x2016000,
  64537         0,
  64538         0,
  64539         1,
  64540         soc_LLS_PORT_WERR_MAX_SC_ECC_STATUS_BCM56450_A0r_fields,
  64541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64542         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  64543         -1,
  64544         -1,
  64545     },
  64546 #endif /* chips */
  64547 
  64548 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  64549     { /* SOC_REG_INT_LLS_PORT_WERR_MAX_SC_ECC_STATUS_BCM56640_A0r */
  64550         soc_block_list[4],
  64551         soc_genreg,
  64552         1,
  64553         0,
  64554         0x5a007e00,
  64555         0,
  64556         0,
  64557         1,
  64558         soc_LLS_PORT_WERR_MAX_SC_ECC_STATUS_BCM56640_A0r_fields,
  64559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64560         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64561         -1,
  64562         -1,
  64563     },
  64564 #endif /* chips */
  64565 
  64566 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64567     defined(BCM_56450_B1)
  64568     { /* SOC_REG_INT_LLS_S0S1_ECC_1B_COUNTERr */
  64569         soc_block_list[85],
  64570         soc_genreg,
  64571         1,
  64572         0,
  64573         0x2014000,
  64574         0,
  64575         0,
  64576         1,
  64577         soc_LLS_S0S1_ECC_1B_COUNTERr_fields,
  64578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64579         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  64580         -1,
  64581         -1,
  64582     },
  64583 #endif /* chips */
  64584 
  64585 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64586     { /* SOC_REG_INT_LLS_S0S1_ECC_1B_COUNTER_BCM56260_A0r */
  64587         soc_block_list[85],
  64588         soc_genreg,
  64589         1,
  64590         0,
  64591         0x200be00,
  64592         0,
  64593         0,
  64594         1,
  64595         soc_LLS_S0S1_ECC_1B_COUNTER_BCM56260_A0r_fields,
  64596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64597         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  64598         -1,
  64599         -1,
  64600     },
  64601 #endif /* chips */
  64602 
  64603 #if defined(BCM_56270_A0)
  64604     { /* SOC_REG_INT_LLS_S0S1_ECC_1B_COUNTER_BCM56270_A0r */
  64605         soc_block_list[85],
  64606         soc_genreg,
  64607         1,
  64608         0,
  64609         0x200a500,
  64610         0,
  64611         0,
  64612         1,
  64613         soc_LLS_S0S1_ECC_1B_COUNTER_BCM56260_A0r_fields,
  64614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64615         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  64616         -1,
  64617         -1,
  64618     },
  64619 #endif /* chips */
  64620 
  64621 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64622     defined(BCM_56450_B1)
  64623     { /* SOC_REG_INT_LLS_S0S1_ECC_2B_COUNTERr */
  64624         soc_block_list[85],
  64625         soc_genreg,
  64626         1,
  64627         0,
  64628         0x2014100,
  64629         0,
  64630         0,
  64631         1,
  64632         soc_LLS_S0S1_ECC_2B_COUNTERr_fields,
  64633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64634         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  64635         -1,
  64636         -1,
  64637     },
  64638 #endif /* chips */
  64639 
  64640 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64641     { /* SOC_REG_INT_LLS_S0S1_ECC_2B_COUNTER_BCM56260_A0r */
  64642         soc_block_list[85],
  64643         soc_genreg,
  64644         1,
  64645         0,
  64646         0x200bf00,
  64647         0,
  64648         0,
  64649         1,
  64650         soc_LLS_S0S1_ECC_2B_COUNTER_BCM56260_A0r_fields,
  64651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64652         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  64653         -1,
  64654         -1,
  64655     },
  64656 #endif /* chips */
  64657 
  64658 #if defined(BCM_56270_A0)
  64659     { /* SOC_REG_INT_LLS_S0S1_ECC_2B_COUNTER_BCM56270_A0r */
  64660         soc_block_list[85],
  64661         soc_genreg,
  64662         1,
  64663         0,
  64664         0x200a600,
  64665         0,
  64666         0,
  64667         1,
  64668         soc_LLS_S0S1_ECC_2B_COUNTER_BCM56260_A0r_fields,
  64669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64670         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  64671         -1,
  64672         -1,
  64673     },
  64674 #endif /* chips */
  64675 
  64676 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64677     defined(BCM_56450_B1)
  64678     { /* SOC_REG_INT_LLS_S0_ERROR_ECC_STATUSr */
  64679         soc_block_list[85],
  64680         soc_genreg,
  64681         1,
  64682         0,
  64683         0x2018b00,
  64684         0,
  64685         0,
  64686         1,
  64687         soc_LLS_S0_ERROR_ECC_STATUSr_fields,
  64688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64689         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  64690         -1,
  64691         -1,
  64692     },
  64693 #endif /* chips */
  64694 
  64695 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64696     defined(BCM_56450_B1)
  64697     { /* SOC_REG_INT_LLS_S0_SHAPER_BUCKET_ECC_STATUSr */
  64698         soc_block_list[85],
  64699         soc_genreg,
  64700         1,
  64701         0,
  64702         0x2015d00,
  64703         0,
  64704         0,
  64705         1,
  64706         soc_LLS_S0_SHAPER_BUCKET_ECC_STATUSr_fields,
  64707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64708         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  64709         -1,
  64710         -1,
  64711     },
  64712 #endif /* chips */
  64713 
  64714 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64715     defined(BCM_56450_B1)
  64716     { /* SOC_REG_INT_LLS_S0_SHAPER_CONFIG_C_ECC_STATUSr */
  64717         soc_block_list[85],
  64718         soc_genreg,
  64719         1,
  64720         0,
  64721         0x2015e00,
  64722         0,
  64723         0,
  64724         1,
  64725         soc_LLS_S0_SHAPER_CONFIG_C_ECC_STATUSr_fields,
  64726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64727         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  64728         -1,
  64729         -1,
  64730     },
  64731 #endif /* chips */
  64732 
  64733 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  64734     { /* SOC_REG_INT_LLS_S1_ECC_DEBUGr */
  64735         soc_block_list[4],
  64736         soc_genreg,
  64737         1,
  64738         0,
  64739         0x62007100,
  64740         0,
  64741         0,
  64742         16,
  64743         soc_LLS_S1_ECC_DEBUGr_fields,
  64744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64745         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  64746         -1,
  64747         -1,
  64748     },
  64749 #endif /* chips */
  64750 
  64751 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64752     defined(BCM_56450_B1)
  64753     { /* SOC_REG_INT_LLS_S1_ERROR_ECC_STATUSr */
  64754         soc_block_list[85],
  64755         soc_genreg,
  64756         1,
  64757         0,
  64758         0x2018a00,
  64759         0,
  64760         0,
  64761         1,
  64762         soc_LLS_S1_ERROR_ECC_STATUSr_fields,
  64763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64764         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  64765         -1,
  64766         -1,
  64767     },
  64768 #endif /* chips */
  64769 
  64770 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64771     defined(BCM_56450_B1)
  64772     { /* SOC_REG_INT_LLS_S1_SHAPER_BUCKET_ECC_STATUSr */
  64773         soc_block_list[85],
  64774         soc_genreg,
  64775         1,
  64776         0,
  64777         0x2015b00,
  64778         0,
  64779         0,
  64780         1,
  64781         soc_LLS_S1_SHAPER_BUCKET_ECC_STATUSr_fields,
  64782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64783         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  64784         -1,
  64785         -1,
  64786     },
  64787 #endif /* chips */
  64788 
  64789 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64790     defined(BCM_56450_B1)
  64791     { /* SOC_REG_INT_LLS_S1_SHAPER_CONFIG_C_ECC_STATUSr */
  64792         soc_block_list[85],
  64793         soc_genreg,
  64794         1,
  64795         0,
  64796         0x2015c00,
  64797         0,
  64798         0,
  64799         1,
  64800         soc_LLS_S1_SHAPER_CONFIG_C_ECC_STATUSr_fields,
  64801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64802         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  64803         -1,
  64804         -1,
  64805     },
  64806 #endif /* chips */
  64807 
  64808 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64809     defined(BCM_56450_B1)
  64810     { /* SOC_REG_INT_LLS_S1_TAILS_ECC_STATUSr */
  64811         soc_block_list[85],
  64812         soc_genreg,
  64813         1,
  64814         0,
  64815         0x2015a00,
  64816         0,
  64817         0,
  64818         1,
  64819         soc_LLS_S1_TAILS_ECC_STATUSr_fields,
  64820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64821         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  64822         -1,
  64823         -1,
  64824     },
  64825 #endif /* chips */
  64826 
  64827 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64828     defined(BCM_56450_B1)
  64829     { /* SOC_REG_INT_LLS_SHAPER_CONFIG_CALC_REORDERr */
  64830         soc_block_list[85],
  64831         soc_genreg,
  64832         1,
  64833         0,
  64834         0x2000a00,
  64835         0,
  64836         0,
  64837         9,
  64838         soc_LLS_SHAPER_CONFIG_CALC_REORDERr_fields,
  64839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64840         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  64841         -1,
  64842         -1,
  64843     },
  64844 #endif /* chips */
  64845 
  64846 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64847     { /* SOC_REG_INT_LLS_SHAPER_CONFIG_CALC_REORDER_BCM56260_A0r */
  64848         soc_block_list[85],
  64849         soc_genreg,
  64850         1,
  64851         0,
  64852         0x2000a00,
  64853         0,
  64854         0,
  64855         9,
  64856         soc_LLS_SHAPER_CONFIG_CALC_REORDER_BCM56260_A0r_fields,
  64857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64858         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  64859         -1,
  64860         -1,
  64861     },
  64862 #endif /* chips */
  64863 
  64864 #if defined(BCM_56270_A0)
  64865     { /* SOC_REG_INT_LLS_SHAPER_CONFIG_CALC_REORDER_BCM56270_A0r */
  64866         soc_block_list[85],
  64867         soc_genreg,
  64868         1,
  64869         0,
  64870         0x2000a00,
  64871         0,
  64872         0,
  64873         8,
  64874         soc_LLS_SHAPER_CONFIG_CALC_REORDER_BCM56270_A0r_fields,
  64875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64876         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  64877         -1,
  64878         -1,
  64879     },
  64880 #endif /* chips */
  64881 
  64882 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  64883     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG0r */
  64884         soc_block_list[85],
  64885         soc_genreg,
  64886         1,
  64887         0,
  64888         0x80005,
  64889         0,
  64890         0,
  64891         3,
  64892         soc_LLS_SHAPER_LAST_ADDR_CONFIG0r_fields,
  64893         SOC_RESET_VAL_DEC(0x003fffe3, 0x00000000)
  64894         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  64895         -1,
  64896         -1,
  64897     },
  64898 #endif /* chips */
  64899 
  64900 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  64901     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG1r */
  64902         soc_block_list[85],
  64903         soc_genreg,
  64904         1,
  64905         0,
  64906         0x80006,
  64907         0,
  64908         0,
  64909         3,
  64910         soc_LLS_SHAPER_LAST_ADDR_CONFIG1r_fields,
  64911         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  64912         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  64913         -1,
  64914         -1,
  64915     },
  64916 #endif /* chips */
  64917 
  64918 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  64919     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG2r */
  64920         soc_block_list[85],
  64921         soc_genreg,
  64922         1,
  64923         0,
  64924         0x80007,
  64925         0,
  64926         0,
  64927         3,
  64928         soc_LLS_SHAPER_LAST_ADDR_CONFIG2r_fields,
  64929         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  64930         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  64931         -1,
  64932         -1,
  64933     },
  64934 #endif /* chips */
  64935 
  64936 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64937     defined(BCM_56450_B1)
  64938     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG3r */
  64939         soc_block_list[85],
  64940         soc_genreg,
  64941         1,
  64942         0,
  64943         0x2000900,
  64944         0,
  64945         0,
  64946         2,
  64947         soc_LLS_SHAPER_LAST_ADDR_CONFIG3r_fields,
  64948         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  64949         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  64950         -1,
  64951         -1,
  64952     },
  64953 #endif /* chips */
  64954 
  64955 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64956     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG0_BCM56260_A0r */
  64957         soc_block_list[85],
  64958         soc_genreg,
  64959         1,
  64960         0,
  64961         0x2000600,
  64962         0,
  64963         0,
  64964         3,
  64965         soc_LLS_SHAPER_LAST_ADDR_CONFIG0_BCM56260_A0r_fields,
  64966         SOC_RESET_VAL_DEC(0x0007fffd, 0x00000000)
  64967         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  64968         -1,
  64969         -1,
  64970     },
  64971 #endif /* chips */
  64972 
  64973 #if defined(BCM_56270_A0)
  64974     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG0_BCM56270_A0r */
  64975         soc_block_list[85],
  64976         soc_genreg,
  64977         1,
  64978         0,
  64979         0x2000600,
  64980         0,
  64981         0,
  64982         3,
  64983         soc_LLS_SHAPER_LAST_ADDR_CONFIG0_BCM56270_A0r_fields,
  64984         SOC_RESET_VAL_DEC(0x0000fffd, 0x00000000)
  64985         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  64986         -1,
  64987         -1,
  64988     },
  64989 #endif /* chips */
  64990 
  64991 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  64992     defined(BCM_56450_B1)
  64993     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG0_BCM56450_A0r */
  64994         soc_block_list[85],
  64995         soc_genreg,
  64996         1,
  64997         0,
  64998         0x2000600,
  64999         0,
  65000         0,
  65001         3,
  65002         soc_LLS_SHAPER_LAST_ADDR_CONFIG0_BCM56450_A0r_fields,
  65003         SOC_RESET_VAL_DEC(0x00ffffe9, 0x00000000)
  65004         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  65005         -1,
  65006         -1,
  65007     },
  65008 #endif /* chips */
  65009 
  65010 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65011     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG1_BCM56260_A0r */
  65012         soc_block_list[85],
  65013         soc_genreg,
  65014         1,
  65015         0,
  65016         0x2000700,
  65017         0,
  65018         0,
  65019         2,
  65020         soc_LLS_SHAPER_LAST_ADDR_CONFIG1_BCM56260_A0r_fields,
  65021         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  65022         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  65023         -1,
  65024         -1,
  65025     },
  65026 #endif /* chips */
  65027 
  65028 #if defined(BCM_56270_A0)
  65029     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG1_BCM56270_A0r */
  65030         soc_block_list[85],
  65031         soc_genreg,
  65032         1,
  65033         0,
  65034         0x2000700,
  65035         0,
  65036         0,
  65037         2,
  65038         soc_LLS_SHAPER_LAST_ADDR_CONFIG1_BCM56270_A0r_fields,
  65039         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
  65040         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  65041         -1,
  65042         -1,
  65043     },
  65044 #endif /* chips */
  65045 
  65046 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65047     defined(BCM_56450_B1)
  65048     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG1_BCM56450_A0r */
  65049         soc_block_list[85],
  65050         soc_genreg,
  65051         1,
  65052         0,
  65053         0x2000700,
  65054         0,
  65055         0,
  65056         3,
  65057         soc_LLS_SHAPER_LAST_ADDR_CONFIG1_BCM56450_A0r_fields,
  65058         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  65059         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  65060         -1,
  65061         -1,
  65062     },
  65063 #endif /* chips */
  65064 
  65065 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65066     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG2_BCM56260_A0r */
  65067         soc_block_list[85],
  65068         soc_genreg,
  65069         1,
  65070         0,
  65071         0x2000800,
  65072         0,
  65073         0,
  65074         2,
  65075         soc_LLS_SHAPER_LAST_ADDR_CONFIG2_BCM56260_A0r_fields,
  65076         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  65077         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  65078         -1,
  65079         -1,
  65080     },
  65081 #endif /* chips */
  65082 
  65083 #if defined(BCM_56270_A0)
  65084     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG2_BCM56270_A0r */
  65085         soc_block_list[85],
  65086         soc_genreg,
  65087         1,
  65088         0,
  65089         0x2000800,
  65090         0,
  65091         0,
  65092         2,
  65093         soc_LLS_SHAPER_LAST_ADDR_CONFIG2_BCM56270_A0r_fields,
  65094         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
  65095         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  65096         -1,
  65097         -1,
  65098     },
  65099 #endif /* chips */
  65100 
  65101 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65102     defined(BCM_56450_B1)
  65103     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG2_BCM56450_A0r */
  65104         soc_block_list[85],
  65105         soc_genreg,
  65106         1,
  65107         0,
  65108         0x2000800,
  65109         0,
  65110         0,
  65111         3,
  65112         soc_LLS_SHAPER_LAST_ADDR_CONFIG2_BCM56450_A0r_fields,
  65113         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  65114         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  65115         -1,
  65116         -1,
  65117     },
  65118 #endif /* chips */
  65119 
  65120 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65121     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG3_BCM56260_A0r */
  65122         soc_block_list[85],
  65123         soc_genreg,
  65124         1,
  65125         0,
  65126         0x2000900,
  65127         0,
  65128         0,
  65129         2,
  65130         soc_LLS_SHAPER_LAST_ADDR_CONFIG3_BCM56260_A0r_fields,
  65131         SOC_RESET_VAL_DEC(0x000003ff, 0x00000000)
  65132         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  65133         -1,
  65134         -1,
  65135     },
  65136 #endif /* chips */
  65137 
  65138 #if defined(BCM_56270_A0)
  65139     { /* SOC_REG_INT_LLS_SHAPER_LAST_ADDR_CONFIG3_BCM56270_A0r */
  65140         soc_block_list[85],
  65141         soc_genreg,
  65142         1,
  65143         0,
  65144         0x2000900,
  65145         0,
  65146         0,
  65147         1,
  65148         soc_LLS_SHAPER_LAST_ADDR_CONFIG3_BCM56270_A0r_fields,
  65149         SOC_RESET_VAL_DEC(0x00000017, 0x00000000)
  65150         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  65151         -1,
  65152         -1,
  65153     },
  65154 #endif /* chips */
  65155 
  65156 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  65157     { /* SOC_REG_INT_LLS_SHAPER_REFRESH_CONFIGr */
  65158         soc_block_list[85],
  65159         soc_genreg,
  65160         1,
  65161         0,
  65162         0x80004,
  65163         0,
  65164         0,
  65165         9,
  65166         soc_LLS_SHAPER_REFRESH_CONFIGr_fields,
  65167         SOC_RESET_VAL_DEC(0x04924924, 0x00000000)
  65168         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  65169         -1,
  65170         -1,
  65171     },
  65172 #endif /* chips */
  65173 
  65174 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65175     defined(BCM_56450_B1)
  65176     { /* SOC_REG_INT_LLS_SHAPER_REFRESH_CONFIG1r */
  65177         soc_block_list[85],
  65178         soc_genreg,
  65179         1,
  65180         0,
  65181         0x2000400,
  65182         0,
  65183         0,
  65184         2,
  65185         soc_LLS_SHAPER_REFRESH_CONFIG1r_fields,
  65186         SOC_RESET_VAL_DEC(0x00000024, 0x00000000)
  65187         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65188         -1,
  65189         -1,
  65190     },
  65191 #endif /* chips */
  65192 
  65193 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65194     { /* SOC_REG_INT_LLS_SHAPER_REFRESH_CONFIG1_BCM56260_A0r */
  65195         soc_block_list[85],
  65196         soc_genreg,
  65197         1,
  65198         0,
  65199         0x2000400,
  65200         0,
  65201         0,
  65202         2,
  65203         soc_LLS_SHAPER_REFRESH_CONFIG1_BCM56260_A0r_fields,
  65204         SOC_RESET_VAL_DEC(0x00000044, 0x00000000)
  65205         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  65206         -1,
  65207         -1,
  65208     },
  65209 #endif /* chips */
  65210 
  65211 #if defined(BCM_56270_A0)
  65212     { /* SOC_REG_INT_LLS_SHAPER_REFRESH_CONFIG1_BCM56270_A0r */
  65213         soc_block_list[85],
  65214         soc_genreg,
  65215         1,
  65216         0,
  65217         0x2000400,
  65218         0,
  65219         0,
  65220         1,
  65221         soc_LLS_SHAPER_REFRESH_CONFIG1_BCM56270_A0r_fields,
  65222         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  65223         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  65224         -1,
  65225         -1,
  65226     },
  65227 #endif /* chips */
  65228 
  65229 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  65230     defined(BCM_56270_A0)
  65231     { /* SOC_REG_INT_LLS_SHAPER_REFRESH_CONFIG_BCM56260_A0r */
  65232         soc_block_list[85],
  65233         soc_genreg,
  65234         1,
  65235         0,
  65236         0x2000500,
  65237         0,
  65238         0,
  65239         7,
  65240         soc_LLS_SHAPER_REFRESH_CONFIG_BCM56260_A0r_fields,
  65241         SOC_RESET_VAL_DEC(0x04444444, 0x00000000)
  65242         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  65243         -1,
  65244         -1,
  65245     },
  65246 #endif /* chips */
  65247 
  65248 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65249     defined(BCM_56450_B1)
  65250     { /* SOC_REG_INT_LLS_SHAPER_REFRESH_CONFIG_BCM56450_A0r */
  65251         soc_block_list[85],
  65252         soc_genreg,
  65253         1,
  65254         0,
  65255         0x2000500,
  65256         0,
  65257         0,
  65258         9,
  65259         soc_LLS_SHAPER_REFRESH_CONFIG_BCM56450_A0r_fields,
  65260         SOC_RESET_VAL_DEC(0x04924924, 0x00000000)
  65261         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  65262         -1,
  65263         -1,
  65264     },
  65265 #endif /* chips */
  65266 
  65267 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65268     defined(BCM_56450_B1)
  65269     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_0_CFGr */
  65270         soc_block_list[85],
  65271         soc_genreg,
  65272         1,
  65273         0,
  65274         0x2011500,
  65275         0,
  65276         0,
  65277         3,
  65278         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFGr_fields,
  65279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65280         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  65281         -1,
  65282         -1,
  65283     },
  65284 #endif /* chips */
  65285 
  65286 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65287     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56260_A0r */
  65288         soc_block_list[85],
  65289         soc_genreg,
  65290         1,
  65291         0,
  65292         0x2009600,
  65293         0,
  65294         0,
  65295         3,
  65296         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56260_A0r_fields,
  65297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65298         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  65299         -1,
  65300         -1,
  65301     },
  65302 #endif /* chips */
  65303 
  65304 #if defined(BCM_56270_A0)
  65305     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56270_A0r */
  65306         soc_block_list[85],
  65307         soc_genreg,
  65308         1,
  65309         0,
  65310         0x2007d00,
  65311         0,
  65312         0,
  65313         3,
  65314         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56270_A0r_fields,
  65315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65316         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  65317         -1,
  65318         -1,
  65319     },
  65320 #endif /* chips */
  65321 
  65322 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65323     defined(BCM_56450_B1)
  65324     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_1_CFGr */
  65325         soc_block_list[85],
  65326         soc_genreg,
  65327         1,
  65328         0,
  65329         0x2011400,
  65330         0,
  65331         0,
  65332         3,
  65333         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFGr_fields,
  65334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65335         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  65336         -1,
  65337         -1,
  65338     },
  65339 #endif /* chips */
  65340 
  65341 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65342     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_1_CFG_BCM56260_A0r */
  65343         soc_block_list[85],
  65344         soc_genreg,
  65345         1,
  65346         0,
  65347         0x2009500,
  65348         0,
  65349         0,
  65350         3,
  65351         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56260_A0r_fields,
  65352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65353         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  65354         -1,
  65355         -1,
  65356     },
  65357 #endif /* chips */
  65358 
  65359 #if defined(BCM_56270_A0)
  65360     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_1_CFG_BCM56270_A0r */
  65361         soc_block_list[85],
  65362         soc_genreg,
  65363         1,
  65364         0,
  65365         0x2007c00,
  65366         0,
  65367         0,
  65368         3,
  65369         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56270_A0r_fields,
  65370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65371         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  65372         -1,
  65373         -1,
  65374     },
  65375 #endif /* chips */
  65376 
  65377 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65378     defined(BCM_56450_B1)
  65379     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_2_CFGr */
  65380         soc_block_list[85],
  65381         soc_genreg,
  65382         1,
  65383         0,
  65384         0x2011300,
  65385         0,
  65386         0,
  65387         3,
  65388         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFGr_fields,
  65389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65390         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  65391         -1,
  65392         -1,
  65393     },
  65394 #endif /* chips */
  65395 
  65396 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65397     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_2_CFG_BCM56260_A0r */
  65398         soc_block_list[85],
  65399         soc_genreg,
  65400         1,
  65401         0,
  65402         0x2009400,
  65403         0,
  65404         0,
  65405         3,
  65406         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56260_A0r_fields,
  65407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65408         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  65409         -1,
  65410         -1,
  65411     },
  65412 #endif /* chips */
  65413 
  65414 #if defined(BCM_56270_A0)
  65415     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_2_CFG_BCM56270_A0r */
  65416         soc_block_list[85],
  65417         soc_genreg,
  65418         1,
  65419         0,
  65420         0x2007b00,
  65421         0,
  65422         0,
  65423         3,
  65424         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56270_A0r_fields,
  65425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65426         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  65427         -1,
  65428         -1,
  65429     },
  65430 #endif /* chips */
  65431 
  65432 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65433     defined(BCM_56450_B1)
  65434     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_3_CFGr */
  65435         soc_block_list[85],
  65436         soc_genreg,
  65437         1,
  65438         0,
  65439         0x2011200,
  65440         0,
  65441         0,
  65442         3,
  65443         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFGr_fields,
  65444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65445         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  65446         -1,
  65447         -1,
  65448     },
  65449 #endif /* chips */
  65450 
  65451 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65452     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_3_CFG_BCM56260_A0r */
  65453         soc_block_list[85],
  65454         soc_genreg,
  65455         1,
  65456         0,
  65457         0x2009300,
  65458         0,
  65459         0,
  65460         3,
  65461         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56260_A0r_fields,
  65462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65463         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  65464         -1,
  65465         -1,
  65466     },
  65467 #endif /* chips */
  65468 
  65469 #if defined(BCM_56270_A0)
  65470     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_3_CFG_BCM56270_A0r */
  65471         soc_block_list[85],
  65472         soc_genreg,
  65473         1,
  65474         0,
  65475         0x2007a00,
  65476         0,
  65477         0,
  65478         3,
  65479         soc_LLS_SHAPER_UNDERRUN_MONITOR_0_CFG_BCM56270_A0r_fields,
  65480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65481         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  65482         -1,
  65483         -1,
  65484     },
  65485 #endif /* chips */
  65486 
  65487 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65488     defined(BCM_56450_B1)
  65489     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_SEENr */
  65490         soc_block_list[85],
  65491         soc_genreg,
  65492         1,
  65493         0,
  65494         0x2011600,
  65495         0,
  65496         0,
  65497         8,
  65498         soc_LLS_SHAPER_UNDERRUN_MONITOR_SEENr_fields,
  65499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65500         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  65501         -1,
  65502         -1,
  65503     },
  65504 #endif /* chips */
  65505 
  65506 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65507     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_SEEN_BCM56260_A0r */
  65508         soc_block_list[85],
  65509         soc_genreg,
  65510         1,
  65511         0,
  65512         0x2009700,
  65513         0,
  65514         0,
  65515         8,
  65516         soc_LLS_SHAPER_UNDERRUN_MONITOR_SEEN_BCM56260_A0r_fields,
  65517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65518         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  65519         -1,
  65520         -1,
  65521     },
  65522 #endif /* chips */
  65523 
  65524 #if defined(BCM_56270_A0)
  65525     { /* SOC_REG_INT_LLS_SHAPER_UNDERRUN_MONITOR_SEEN_BCM56270_A0r */
  65526         soc_block_list[85],
  65527         soc_genreg,
  65528         1,
  65529         0,
  65530         0x2007e00,
  65531         0,
  65532         0,
  65533         8,
  65534         soc_LLS_SHAPER_UNDERRUN_MONITOR_SEEN_BCM56260_A0r_fields,
  65535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65536         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  65537         -1,
  65538         -1,
  65539     },
  65540 #endif /* chips */
  65541 
  65542 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  65543     { /* SOC_REG_INT_LLS_SOFT_RESETr */
  65544         soc_block_list[85],
  65545         soc_genreg,
  65546         1,
  65547         0,
  65548         0x80001,
  65549         0,
  65550         0,
  65551         1,
  65552         soc_LLS_SOFT_RESETr_fields,
  65553         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65554         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65555         -1,
  65556         -1,
  65557     },
  65558 #endif /* chips */
  65559 
  65560 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  65561     defined(BCM_56270_A0)
  65562     { /* SOC_REG_INT_LLS_SOFT_RESET_BCM56260_A0r */
  65563         soc_block_list[85],
  65564         soc_genreg,
  65565         1,
  65566         0,
  65567         0x2000100,
  65568         0,
  65569         0,
  65570         1,
  65571         soc_LLS_SOFT_RESET_BCM56260_A0r_fields,
  65572         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65573         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65574         -1,
  65575         -1,
  65576     },
  65577 #endif /* chips */
  65578 
  65579 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65580     defined(BCM_56450_B1)
  65581     { /* SOC_REG_INT_LLS_SOFT_RESET_BCM56450_A0r */
  65582         soc_block_list[85],
  65583         soc_genreg,
  65584         1,
  65585         0,
  65586         0x2000100,
  65587         0,
  65588         0,
  65589         1,
  65590         soc_LLS_SOFT_RESET_BCM56640_A0r_fields,
  65591         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65592         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65593         -1,
  65594         -1,
  65595     },
  65596 #endif /* chips */
  65597 
  65598 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  65599     { /* SOC_REG_INT_LLS_SOFT_RESET_BCM56640_A0r */
  65600         soc_block_list[4],
  65601         soc_genreg,
  65602         1,
  65603         0,
  65604         0x5a000000,
  65605         0,
  65606         0,
  65607         1,
  65608         soc_LLS_SOFT_RESET_BCM56640_A0r_fields,
  65609         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65610         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65611         -1,
  65612         -1,
  65613     },
  65614 #endif /* chips */
  65615 
  65616 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65617     defined(BCM_56450_B1)
  65618     { /* SOC_REG_INT_LLS_SPARE_REGS1r */
  65619         soc_block_list[85],
  65620         soc_genreg,
  65621         1,
  65622         0,
  65623         0x2019600,
  65624         0,
  65625         0,
  65626         1,
  65627         soc_LLS_SPARE_REGS1r_fields,
  65628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65629         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65630         -1,
  65631         -1,
  65632     },
  65633 #endif /* chips */
  65634 
  65635 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65636     defined(BCM_56450_B1)
  65637     { /* SOC_REG_INT_LLS_SPARE_REGS2r */
  65638         soc_block_list[85],
  65639         soc_genreg,
  65640         1,
  65641         0,
  65642         0x2019700,
  65643         0,
  65644         0,
  65645         1,
  65646         soc_LLS_SPARE_REGS1r_fields,
  65647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65649         -1,
  65650         -1,
  65651     },
  65652 #endif /* chips */
  65653 
  65654 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65655     { /* SOC_REG_INT_LLS_SPARE_REGS1_BCM56260_A0r */
  65656         soc_block_list[85],
  65657         soc_genreg,
  65658         1,
  65659         0,
  65660         0x2010100,
  65661         0,
  65662         0,
  65663         1,
  65664         soc_LLS_SPARE_REGS1_BCM56560_A0r_fields,
  65665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65667         -1,
  65668         -1,
  65669     },
  65670 #endif /* chips */
  65671 
  65672 #if defined(BCM_56270_A0)
  65673     { /* SOC_REG_INT_LLS_SPARE_REGS1_BCM56270_A0r */
  65674         soc_block_list[85],
  65675         soc_genreg,
  65676         1,
  65677         0,
  65678         0x200e800,
  65679         0,
  65680         0,
  65681         1,
  65682         soc_LLS_SPARE_REGS1_BCM56560_A0r_fields,
  65683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65685         -1,
  65686         -1,
  65687     },
  65688 #endif /* chips */
  65689 
  65690 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  65691     { /* SOC_REG_INT_LLS_SPARE_REGS1_BCM56560_A0r */
  65692         soc_block_list[4],
  65693         soc_genreg,
  65694         1,
  65695         0,
  65696         0x62007e00,
  65697         0,
  65698         0,
  65699         1,
  65700         soc_LLS_SPARE_REGS1_BCM56560_A0r_fields,
  65701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65703         -1,
  65704         -1,
  65705     },
  65706 #endif /* chips */
  65707 
  65708 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65709     { /* SOC_REG_INT_LLS_SPARE_REGS2_BCM56260_A0r */
  65710         soc_block_list[85],
  65711         soc_genreg,
  65712         1,
  65713         0,
  65714         0x2010200,
  65715         0,
  65716         0,
  65717         1,
  65718         soc_LLS_SPARE_REGS1_BCM56560_A0r_fields,
  65719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65721         -1,
  65722         -1,
  65723     },
  65724 #endif /* chips */
  65725 
  65726 #if defined(BCM_56270_A0)
  65727     { /* SOC_REG_INT_LLS_SPARE_REGS2_BCM56270_A0r */
  65728         soc_block_list[85],
  65729         soc_genreg,
  65730         1,
  65731         0,
  65732         0x200e900,
  65733         0,
  65734         0,
  65735         1,
  65736         soc_LLS_SPARE_REGS1_BCM56560_A0r_fields,
  65737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65739         -1,
  65740         -1,
  65741     },
  65742 #endif /* chips */
  65743 
  65744 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  65745     { /* SOC_REG_INT_LLS_SPARE_REGS2_BCM56560_A0r */
  65746         soc_block_list[4],
  65747         soc_genreg,
  65748         1,
  65749         0,
  65750         0x62007f00,
  65751         0,
  65752         0,
  65753         1,
  65754         soc_LLS_SPARE_REGS1_BCM56560_A0r_fields,
  65755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65757         -1,
  65758         -1,
  65759     },
  65760 #endif /* chips */
  65761 
  65762 #if defined(BCM_56640_A0)
  65763     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0r */
  65764         soc_block_list[4],
  65765         soc_genreg,
  65766         1,
  65767         0,
  65768         0x5a00b600,
  65769         0,
  65770         0,
  65771         1,
  65772         soc_LLS_SP_WERR_DYN_CHANGE_0r_fields,
  65773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65774         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65775         -1,
  65776         -1,
  65777     },
  65778 #endif /* chips */
  65779 
  65780 #if defined(BCM_56640_A0)
  65781     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1r */
  65782         soc_block_list[4],
  65783         soc_genreg,
  65784         1,
  65785         0,
  65786         0x5a00b300,
  65787         0,
  65788         0,
  65789         1,
  65790         soc_LLS_SP_WERR_DYN_CHANGE_0r_fields,
  65791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65792         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65793         -1,
  65794         -1,
  65795     },
  65796 #endif /* chips */
  65797 
  65798 #if defined(BCM_56640_A0)
  65799     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2r */
  65800         soc_block_list[4],
  65801         soc_genreg,
  65802         1,
  65803         0,
  65804         0x5a00b000,
  65805         0,
  65806         0,
  65807         1,
  65808         soc_LLS_SP_WERR_DYN_CHANGE_0r_fields,
  65809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65810         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65811         -1,
  65812         -1,
  65813     },
  65814 #endif /* chips */
  65815 
  65816 #if defined(BCM_56640_A0)
  65817     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3r */
  65818         soc_block_list[4],
  65819         soc_genreg,
  65820         1,
  65821         0,
  65822         0x5a00ad00,
  65823         0,
  65824         0,
  65825         1,
  65826         soc_LLS_SP_WERR_DYN_CHANGE_0r_fields,
  65827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65828         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65829         -1,
  65830         -1,
  65831     },
  65832 #endif /* chips */
  65833 
  65834 #if defined(BCM_56440_B0)
  65835     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0Ar */
  65836         soc_block_list[85],
  65837         soc_genreg,
  65838         1,
  65839         0,
  65840         0x8003d,
  65841         0,
  65842         0,
  65843         4,
  65844         soc_LLS_SP_WERR_DYN_CHANGE_0Ar_fields,
  65845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65846         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  65847         -1,
  65848         -1,
  65849     },
  65850 #endif /* chips */
  65851 
  65852 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65853     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0A_BCM56260_A0r */
  65854         soc_block_list[85],
  65855         soc_genreg,
  65856         1,
  65857         0,
  65858         0x2005800,
  65859         0,
  65860         0,
  65861         6,
  65862         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56260_A0r_fields,
  65863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65864         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  65865         -1,
  65866         -1,
  65867     },
  65868 #endif /* chips */
  65869 
  65870 #if defined(BCM_56270_A0)
  65871     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0A_BCM56270_A0r */
  65872         soc_block_list[85],
  65873         soc_genreg,
  65874         1,
  65875         0,
  65876         0x2005400,
  65877         0,
  65878         0,
  65879         6,
  65880         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56270_A0r_fields,
  65881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65882         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  65883         -1,
  65884         -1,
  65885     },
  65886 #endif /* chips */
  65887 
  65888 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65889     defined(BCM_56450_B1)
  65890     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0A_BCM56450_A0r */
  65891         soc_block_list[85],
  65892         soc_genreg,
  65893         1,
  65894         0,
  65895         0x2005400,
  65896         0,
  65897         0,
  65898         6,
  65899         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56450_A0r_fields,
  65900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65901         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  65902         -1,
  65903         -1,
  65904     },
  65905 #endif /* chips */
  65906 
  65907 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  65908     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0A_BCM56560_A0r */
  65909         soc_block_list[4],
  65910         soc_genreg,
  65911         1,
  65912         0,
  65913         0x62003400,
  65914         0,
  65915         0,
  65916         5,
  65917         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56560_A0r_fields,
  65918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65919         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65920         -1,
  65921         -1,
  65922     },
  65923 #endif /* chips */
  65924 
  65925 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  65926     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0A_BCM56640_A0r */
  65927         soc_block_list[4],
  65928         soc_genreg,
  65929         1,
  65930         0,
  65931         0x5a00b700,
  65932         0,
  65933         0,
  65934         4,
  65935         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56640_A0r_fields,
  65936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65937         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  65938         -1,
  65939         -1,
  65940     },
  65941 #endif /* chips */
  65942 
  65943 #if defined(BCM_56440_B0)
  65944     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0Br */
  65945         soc_block_list[85],
  65946         soc_genreg,
  65947         1,
  65948         0,
  65949         0x8003e,
  65950         0,
  65951         0,
  65952         1,
  65953         soc_LLS_SP_WERR_DYN_CHANGE_0Br_fields,
  65954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65955         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  65956         -1,
  65957         -1,
  65958     },
  65959 #endif /* chips */
  65960 
  65961 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65962     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0B_BCM56260_A0r */
  65963         soc_block_list[85],
  65964         soc_genreg,
  65965         1,
  65966         0,
  65967         0x2005900,
  65968         0,
  65969         0,
  65970         1,
  65971         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56260_A0r_fields,
  65972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65973         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  65974         -1,
  65975         -1,
  65976     },
  65977 #endif /* chips */
  65978 
  65979 #if defined(BCM_56270_A0)
  65980     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0B_BCM56270_A0r */
  65981         soc_block_list[85],
  65982         soc_genreg,
  65983         1,
  65984         0,
  65985         0x2005500,
  65986         0,
  65987         0,
  65988         1,
  65989         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56270_A0r_fields,
  65990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65991         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  65992         -1,
  65993         -1,
  65994     },
  65995 #endif /* chips */
  65996 
  65997 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  65998     defined(BCM_56450_B1)
  65999     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0B_BCM56450_A0r */
  66000         soc_block_list[85],
  66001         soc_genreg,
  66002         1,
  66003         0,
  66004         0x2005500,
  66005         0,
  66006         0,
  66007         1,
  66008         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56450_A0r_fields,
  66009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66010         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66011         -1,
  66012         -1,
  66013     },
  66014 #endif /* chips */
  66015 
  66016 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66017     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0B_BCM56560_A0r */
  66018         soc_block_list[4],
  66019         soc_genreg,
  66020         1,
  66021         0,
  66022         0x62003500,
  66023         0,
  66024         0,
  66025         3,
  66026         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56560_A0r_fields,
  66027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66028         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66029         -1,
  66030         -1,
  66031     },
  66032 #endif /* chips */
  66033 
  66034 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  66035     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0B_BCM56640_A0r */
  66036         soc_block_list[4],
  66037         soc_genreg,
  66038         1,
  66039         0,
  66040         0x5a00b800,
  66041         0,
  66042         0,
  66043         1,
  66044         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56640_A0r_fields,
  66045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66046         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66047         -1,
  66048         -1,
  66049     },
  66050 #endif /* chips */
  66051 
  66052 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66053     defined(BCM_56450_B1)
  66054     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0Cr */
  66055         soc_block_list[85],
  66056         soc_genreg,
  66057         1,
  66058         0,
  66059         0x2005600,
  66060         0,
  66061         0,
  66062         1,
  66063         soc_LLS_SP_WERR_DYN_CHANGE_0Cr_fields,
  66064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66065         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66066         -1,
  66067         -1,
  66068     },
  66069 #endif /* chips */
  66070 
  66071 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66072     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0C_BCM56260_A0r */
  66073         soc_block_list[85],
  66074         soc_genreg,
  66075         1,
  66076         0,
  66077         0x2005a00,
  66078         0,
  66079         0,
  66080         1,
  66081         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  66082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66083         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66084         -1,
  66085         -1,
  66086     },
  66087 #endif /* chips */
  66088 
  66089 #if defined(BCM_56270_A0)
  66090     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0C_BCM56270_A0r */
  66091         soc_block_list[85],
  66092         soc_genreg,
  66093         1,
  66094         0,
  66095         0x2005600,
  66096         0,
  66097         0,
  66098         1,
  66099         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  66100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66102         -1,
  66103         -1,
  66104     },
  66105 #endif /* chips */
  66106 
  66107 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66108     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r */
  66109         soc_block_list[4],
  66110         soc_genreg,
  66111         1,
  66112         0,
  66113         0x62003600,
  66114         0,
  66115         0,
  66116         1,
  66117         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  66118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66120         -1,
  66121         -1,
  66122     },
  66123 #endif /* chips */
  66124 
  66125 #if defined(BCM_56340_A0)
  66126     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_0_BCM56340_A0r */
  66127         soc_block_list[4],
  66128         soc_genreg,
  66129         1,
  66130         0,
  66131         0x5a00b600,
  66132         0,
  66133         0,
  66134         1,
  66135         soc_LLS_SP_WERR_DYN_CHANGE_0_BCM56340_A0r_fields,
  66136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66137         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66138         -1,
  66139         -1,
  66140     },
  66141 #endif /* chips */
  66142 
  66143 #if defined(BCM_56440_B0)
  66144     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1Ar */
  66145         soc_block_list[85],
  66146         soc_genreg,
  66147         1,
  66148         0,
  66149         0x8003b,
  66150         0,
  66151         0,
  66152         4,
  66153         soc_LLS_SP_WERR_DYN_CHANGE_0Ar_fields,
  66154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66155         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  66156         -1,
  66157         -1,
  66158     },
  66159 #endif /* chips */
  66160 
  66161 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66162     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1A_BCM56260_A0r */
  66163         soc_block_list[85],
  66164         soc_genreg,
  66165         1,
  66166         0,
  66167         0x2005500,
  66168         0,
  66169         0,
  66170         6,
  66171         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56260_A0r_fields,
  66172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66173         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66174         -1,
  66175         -1,
  66176     },
  66177 #endif /* chips */
  66178 
  66179 #if defined(BCM_56270_A0)
  66180     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1A_BCM56270_A0r */
  66181         soc_block_list[85],
  66182         soc_genreg,
  66183         1,
  66184         0,
  66185         0x2005100,
  66186         0,
  66187         0,
  66188         6,
  66189         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56270_A0r_fields,
  66190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66191         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  66192         -1,
  66193         -1,
  66194     },
  66195 #endif /* chips */
  66196 
  66197 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66198     defined(BCM_56450_B1)
  66199     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1A_BCM56450_A0r */
  66200         soc_block_list[85],
  66201         soc_genreg,
  66202         1,
  66203         0,
  66204         0x2005100,
  66205         0,
  66206         0,
  66207         6,
  66208         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56450_A0r_fields,
  66209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66210         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  66211         -1,
  66212         -1,
  66213     },
  66214 #endif /* chips */
  66215 
  66216 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66217     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1A_BCM56560_A0r */
  66218         soc_block_list[4],
  66219         soc_genreg,
  66220         1,
  66221         0,
  66222         0x62003100,
  66223         0,
  66224         0,
  66225         5,
  66226         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56560_A0r_fields,
  66227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66228         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66229         -1,
  66230         -1,
  66231     },
  66232 #endif /* chips */
  66233 
  66234 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  66235     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1A_BCM56640_A0r */
  66236         soc_block_list[4],
  66237         soc_genreg,
  66238         1,
  66239         0,
  66240         0x5a00b400,
  66241         0,
  66242         0,
  66243         4,
  66244         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56640_A0r_fields,
  66245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66246         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66247         -1,
  66248         -1,
  66249     },
  66250 #endif /* chips */
  66251 
  66252 #if defined(BCM_56440_B0)
  66253     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1Br */
  66254         soc_block_list[85],
  66255         soc_genreg,
  66256         1,
  66257         0,
  66258         0x8003c,
  66259         0,
  66260         0,
  66261         1,
  66262         soc_LLS_SP_WERR_DYN_CHANGE_0Br_fields,
  66263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66264         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  66265         -1,
  66266         -1,
  66267     },
  66268 #endif /* chips */
  66269 
  66270 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66271     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1B_BCM56260_A0r */
  66272         soc_block_list[85],
  66273         soc_genreg,
  66274         1,
  66275         0,
  66276         0x2005600,
  66277         0,
  66278         0,
  66279         1,
  66280         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56260_A0r_fields,
  66281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66282         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  66283         -1,
  66284         -1,
  66285     },
  66286 #endif /* chips */
  66287 
  66288 #if defined(BCM_56270_A0)
  66289     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1B_BCM56270_A0r */
  66290         soc_block_list[85],
  66291         soc_genreg,
  66292         1,
  66293         0,
  66294         0x2005200,
  66295         0,
  66296         0,
  66297         1,
  66298         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56270_A0r_fields,
  66299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66300         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66301         -1,
  66302         -1,
  66303     },
  66304 #endif /* chips */
  66305 
  66306 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66307     defined(BCM_56450_B1)
  66308     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1B_BCM56450_A0r */
  66309         soc_block_list[85],
  66310         soc_genreg,
  66311         1,
  66312         0,
  66313         0x2005200,
  66314         0,
  66315         0,
  66316         1,
  66317         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56450_A0r_fields,
  66318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66319         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66320         -1,
  66321         -1,
  66322     },
  66323 #endif /* chips */
  66324 
  66325 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66326     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1B_BCM56560_A0r */
  66327         soc_block_list[4],
  66328         soc_genreg,
  66329         1,
  66330         0,
  66331         0x62003200,
  66332         0,
  66333         0,
  66334         3,
  66335         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56560_A0r_fields,
  66336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66337         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66338         -1,
  66339         -1,
  66340     },
  66341 #endif /* chips */
  66342 
  66343 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  66344     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1B_BCM56640_A0r */
  66345         soc_block_list[4],
  66346         soc_genreg,
  66347         1,
  66348         0,
  66349         0x5a00b500,
  66350         0,
  66351         0,
  66352         1,
  66353         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56640_A0r_fields,
  66354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66355         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66356         -1,
  66357         -1,
  66358     },
  66359 #endif /* chips */
  66360 
  66361 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66362     defined(BCM_56450_B1)
  66363     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1Cr */
  66364         soc_block_list[85],
  66365         soc_genreg,
  66366         1,
  66367         0,
  66368         0x2005300,
  66369         0,
  66370         0,
  66371         1,
  66372         soc_LLS_SP_WERR_DYN_CHANGE_0Cr_fields,
  66373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66374         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66375         -1,
  66376         -1,
  66377     },
  66378 #endif /* chips */
  66379 
  66380 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66381     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1C_BCM56260_A0r */
  66382         soc_block_list[85],
  66383         soc_genreg,
  66384         1,
  66385         0,
  66386         0x2005700,
  66387         0,
  66388         0,
  66389         1,
  66390         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  66391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66392         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66393         -1,
  66394         -1,
  66395     },
  66396 #endif /* chips */
  66397 
  66398 #if defined(BCM_56270_A0)
  66399     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1C_BCM56270_A0r */
  66400         soc_block_list[85],
  66401         soc_genreg,
  66402         1,
  66403         0,
  66404         0x2005300,
  66405         0,
  66406         0,
  66407         1,
  66408         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  66409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66410         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66411         -1,
  66412         -1,
  66413     },
  66414 #endif /* chips */
  66415 
  66416 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66417     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1C_BCM56560_A0r */
  66418         soc_block_list[4],
  66419         soc_genreg,
  66420         1,
  66421         0,
  66422         0x62003300,
  66423         0,
  66424         0,
  66425         1,
  66426         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  66427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66428         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66429         -1,
  66430         -1,
  66431     },
  66432 #endif /* chips */
  66433 
  66434 #if defined(BCM_56340_A0)
  66435     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_1_BCM56340_A0r */
  66436         soc_block_list[4],
  66437         soc_genreg,
  66438         1,
  66439         0,
  66440         0x5a00b300,
  66441         0,
  66442         0,
  66443         1,
  66444         soc_LLS_SP_WERR_DYN_CHANGE_0_BCM56340_A0r_fields,
  66445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66446         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66447         -1,
  66448         -1,
  66449     },
  66450 #endif /* chips */
  66451 
  66452 #if defined(BCM_56440_B0)
  66453     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2Ar */
  66454         soc_block_list[85],
  66455         soc_genreg,
  66456         1,
  66457         0,
  66458         0x80039,
  66459         0,
  66460         0,
  66461         4,
  66462         soc_LLS_SP_WERR_DYN_CHANGE_0Ar_fields,
  66463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66464         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  66465         -1,
  66466         -1,
  66467     },
  66468 #endif /* chips */
  66469 
  66470 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66471     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2A_BCM56260_A0r */
  66472         soc_block_list[85],
  66473         soc_genreg,
  66474         1,
  66475         0,
  66476         0x2005200,
  66477         0,
  66478         0,
  66479         6,
  66480         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56260_A0r_fields,
  66481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66482         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66483         -1,
  66484         -1,
  66485     },
  66486 #endif /* chips */
  66487 
  66488 #if defined(BCM_56270_A0)
  66489     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2A_BCM56270_A0r */
  66490         soc_block_list[85],
  66491         soc_genreg,
  66492         1,
  66493         0,
  66494         0x2004e00,
  66495         0,
  66496         0,
  66497         6,
  66498         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56270_A0r_fields,
  66499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66500         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  66501         -1,
  66502         -1,
  66503     },
  66504 #endif /* chips */
  66505 
  66506 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66507     defined(BCM_56450_B1)
  66508     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2A_BCM56450_A0r */
  66509         soc_block_list[85],
  66510         soc_genreg,
  66511         1,
  66512         0,
  66513         0x2004e00,
  66514         0,
  66515         0,
  66516         6,
  66517         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56450_A0r_fields,
  66518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66519         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  66520         -1,
  66521         -1,
  66522     },
  66523 #endif /* chips */
  66524 
  66525 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66526     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2A_BCM56560_A0r */
  66527         soc_block_list[4],
  66528         soc_genreg,
  66529         1,
  66530         0,
  66531         0x62002e00,
  66532         0,
  66533         0,
  66534         5,
  66535         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56560_A0r_fields,
  66536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66538         -1,
  66539         -1,
  66540     },
  66541 #endif /* chips */
  66542 
  66543 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  66544     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2A_BCM56640_A0r */
  66545         soc_block_list[4],
  66546         soc_genreg,
  66547         1,
  66548         0,
  66549         0x5a00b100,
  66550         0,
  66551         0,
  66552         4,
  66553         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56640_A0r_fields,
  66554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66555         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66556         -1,
  66557         -1,
  66558     },
  66559 #endif /* chips */
  66560 
  66561 #if defined(BCM_56440_B0)
  66562     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2Br */
  66563         soc_block_list[85],
  66564         soc_genreg,
  66565         1,
  66566         0,
  66567         0x8003a,
  66568         0,
  66569         0,
  66570         1,
  66571         soc_LLS_SP_WERR_DYN_CHANGE_0Br_fields,
  66572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66573         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  66574         -1,
  66575         -1,
  66576     },
  66577 #endif /* chips */
  66578 
  66579 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66580     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2B_BCM56260_A0r */
  66581         soc_block_list[85],
  66582         soc_genreg,
  66583         1,
  66584         0,
  66585         0x2005300,
  66586         0,
  66587         0,
  66588         1,
  66589         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56260_A0r_fields,
  66590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66591         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  66592         -1,
  66593         -1,
  66594     },
  66595 #endif /* chips */
  66596 
  66597 #if defined(BCM_56270_A0)
  66598     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2B_BCM56270_A0r */
  66599         soc_block_list[85],
  66600         soc_genreg,
  66601         1,
  66602         0,
  66603         0x2004f00,
  66604         0,
  66605         0,
  66606         1,
  66607         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56270_A0r_fields,
  66608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66609         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66610         -1,
  66611         -1,
  66612     },
  66613 #endif /* chips */
  66614 
  66615 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66616     defined(BCM_56450_B1)
  66617     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2B_BCM56450_A0r */
  66618         soc_block_list[85],
  66619         soc_genreg,
  66620         1,
  66621         0,
  66622         0x2004f00,
  66623         0,
  66624         0,
  66625         1,
  66626         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56450_A0r_fields,
  66627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66628         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66629         -1,
  66630         -1,
  66631     },
  66632 #endif /* chips */
  66633 
  66634 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66635     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2B_BCM56560_A0r */
  66636         soc_block_list[4],
  66637         soc_genreg,
  66638         1,
  66639         0,
  66640         0x62002f00,
  66641         0,
  66642         0,
  66643         3,
  66644         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56560_A0r_fields,
  66645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66646         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66647         -1,
  66648         -1,
  66649     },
  66650 #endif /* chips */
  66651 
  66652 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  66653     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2B_BCM56640_A0r */
  66654         soc_block_list[4],
  66655         soc_genreg,
  66656         1,
  66657         0,
  66658         0x5a00b200,
  66659         0,
  66660         0,
  66661         1,
  66662         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56640_A0r_fields,
  66663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66664         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66665         -1,
  66666         -1,
  66667     },
  66668 #endif /* chips */
  66669 
  66670 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66671     defined(BCM_56450_B1)
  66672     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2Cr */
  66673         soc_block_list[85],
  66674         soc_genreg,
  66675         1,
  66676         0,
  66677         0x2005000,
  66678         0,
  66679         0,
  66680         1,
  66681         soc_LLS_SP_WERR_DYN_CHANGE_0Cr_fields,
  66682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66684         -1,
  66685         -1,
  66686     },
  66687 #endif /* chips */
  66688 
  66689 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66690     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2C_BCM56260_A0r */
  66691         soc_block_list[85],
  66692         soc_genreg,
  66693         1,
  66694         0,
  66695         0x2005400,
  66696         0,
  66697         0,
  66698         1,
  66699         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  66700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66702         -1,
  66703         -1,
  66704     },
  66705 #endif /* chips */
  66706 
  66707 #if defined(BCM_56270_A0)
  66708     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2C_BCM56270_A0r */
  66709         soc_block_list[85],
  66710         soc_genreg,
  66711         1,
  66712         0,
  66713         0x2005000,
  66714         0,
  66715         0,
  66716         1,
  66717         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  66718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66719         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66720         -1,
  66721         -1,
  66722     },
  66723 #endif /* chips */
  66724 
  66725 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66726     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2C_BCM56560_A0r */
  66727         soc_block_list[4],
  66728         soc_genreg,
  66729         1,
  66730         0,
  66731         0x62003000,
  66732         0,
  66733         0,
  66734         1,
  66735         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  66736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66738         -1,
  66739         -1,
  66740     },
  66741 #endif /* chips */
  66742 
  66743 #if defined(BCM_56340_A0)
  66744     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_2_BCM56340_A0r */
  66745         soc_block_list[4],
  66746         soc_genreg,
  66747         1,
  66748         0,
  66749         0x5a00b000,
  66750         0,
  66751         0,
  66752         1,
  66753         soc_LLS_SP_WERR_DYN_CHANGE_0_BCM56340_A0r_fields,
  66754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66755         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66756         -1,
  66757         -1,
  66758     },
  66759 #endif /* chips */
  66760 
  66761 #if defined(BCM_56440_B0)
  66762     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3Ar */
  66763         soc_block_list[85],
  66764         soc_genreg,
  66765         1,
  66766         0,
  66767         0x80037,
  66768         0,
  66769         0,
  66770         4,
  66771         soc_LLS_SP_WERR_DYN_CHANGE_0Ar_fields,
  66772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66773         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  66774         -1,
  66775         -1,
  66776     },
  66777 #endif /* chips */
  66778 
  66779 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66780     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3A_BCM56260_A0r */
  66781         soc_block_list[85],
  66782         soc_genreg,
  66783         1,
  66784         0,
  66785         0x2004f00,
  66786         0,
  66787         0,
  66788         6,
  66789         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56260_A0r_fields,
  66790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66791         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66792         -1,
  66793         -1,
  66794     },
  66795 #endif /* chips */
  66796 
  66797 #if defined(BCM_56270_A0)
  66798     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3A_BCM56270_A0r */
  66799         soc_block_list[85],
  66800         soc_genreg,
  66801         1,
  66802         0,
  66803         0x2004b00,
  66804         0,
  66805         0,
  66806         6,
  66807         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56270_A0r_fields,
  66808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66809         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  66810         -1,
  66811         -1,
  66812     },
  66813 #endif /* chips */
  66814 
  66815 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66816     defined(BCM_56450_B1)
  66817     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3A_BCM56450_A0r */
  66818         soc_block_list[85],
  66819         soc_genreg,
  66820         1,
  66821         0,
  66822         0x2004b00,
  66823         0,
  66824         0,
  66825         6,
  66826         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56450_A0r_fields,
  66827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66828         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  66829         -1,
  66830         -1,
  66831     },
  66832 #endif /* chips */
  66833 
  66834 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66835     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3A_BCM56560_A0r */
  66836         soc_block_list[4],
  66837         soc_genreg,
  66838         1,
  66839         0,
  66840         0x62002b00,
  66841         0,
  66842         0,
  66843         5,
  66844         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56560_A0r_fields,
  66845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66846         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66847         -1,
  66848         -1,
  66849     },
  66850 #endif /* chips */
  66851 
  66852 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  66853     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3A_BCM56640_A0r */
  66854         soc_block_list[4],
  66855         soc_genreg,
  66856         1,
  66857         0,
  66858         0x5a00ae00,
  66859         0,
  66860         0,
  66861         4,
  66862         soc_LLS_SP_WERR_DYN_CHANGE_0A_BCM56640_A0r_fields,
  66863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66864         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66865         -1,
  66866         -1,
  66867     },
  66868 #endif /* chips */
  66869 
  66870 #if defined(BCM_56440_B0)
  66871     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3Br */
  66872         soc_block_list[85],
  66873         soc_genreg,
  66874         1,
  66875         0,
  66876         0x80038,
  66877         0,
  66878         0,
  66879         1,
  66880         soc_LLS_SP_WERR_DYN_CHANGE_0Br_fields,
  66881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66882         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  66883         -1,
  66884         -1,
  66885     },
  66886 #endif /* chips */
  66887 
  66888 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66889     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3B_BCM56260_A0r */
  66890         soc_block_list[85],
  66891         soc_genreg,
  66892         1,
  66893         0,
  66894         0x2005000,
  66895         0,
  66896         0,
  66897         1,
  66898         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56260_A0r_fields,
  66899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66900         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  66901         -1,
  66902         -1,
  66903     },
  66904 #endif /* chips */
  66905 
  66906 #if defined(BCM_56270_A0)
  66907     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3B_BCM56270_A0r */
  66908         soc_block_list[85],
  66909         soc_genreg,
  66910         1,
  66911         0,
  66912         0x2004c00,
  66913         0,
  66914         0,
  66915         1,
  66916         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56270_A0r_fields,
  66917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66918         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66919         -1,
  66920         -1,
  66921     },
  66922 #endif /* chips */
  66923 
  66924 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66925     defined(BCM_56450_B1)
  66926     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3B_BCM56450_A0r */
  66927         soc_block_list[85],
  66928         soc_genreg,
  66929         1,
  66930         0,
  66931         0x2004c00,
  66932         0,
  66933         0,
  66934         1,
  66935         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56450_A0r_fields,
  66936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66937         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  66938         -1,
  66939         -1,
  66940     },
  66941 #endif /* chips */
  66942 
  66943 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  66944     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3B_BCM56560_A0r */
  66945         soc_block_list[4],
  66946         soc_genreg,
  66947         1,
  66948         0,
  66949         0x62002c00,
  66950         0,
  66951         0,
  66952         3,
  66953         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56560_A0r_fields,
  66954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66955         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66956         -1,
  66957         -1,
  66958     },
  66959 #endif /* chips */
  66960 
  66961 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  66962     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3B_BCM56640_A0r */
  66963         soc_block_list[4],
  66964         soc_genreg,
  66965         1,
  66966         0,
  66967         0x5a00af00,
  66968         0,
  66969         0,
  66970         1,
  66971         soc_LLS_SP_WERR_DYN_CHANGE_0B_BCM56640_A0r_fields,
  66972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66973         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66974         -1,
  66975         -1,
  66976     },
  66977 #endif /* chips */
  66978 
  66979 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  66980     defined(BCM_56450_B1)
  66981     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3Cr */
  66982         soc_block_list[85],
  66983         soc_genreg,
  66984         1,
  66985         0,
  66986         0x2004d00,
  66987         0,
  66988         0,
  66989         1,
  66990         soc_LLS_SP_WERR_DYN_CHANGE_0Cr_fields,
  66991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66993         -1,
  66994         -1,
  66995     },
  66996 #endif /* chips */
  66997 
  66998 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  66999     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3C_BCM56260_A0r */
  67000         soc_block_list[85],
  67001         soc_genreg,
  67002         1,
  67003         0,
  67004         0x2005100,
  67005         0,
  67006         0,
  67007         1,
  67008         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  67009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67010         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67011         -1,
  67012         -1,
  67013     },
  67014 #endif /* chips */
  67015 
  67016 #if defined(BCM_56270_A0)
  67017     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3C_BCM56270_A0r */
  67018         soc_block_list[85],
  67019         soc_genreg,
  67020         1,
  67021         0,
  67022         0x2004d00,
  67023         0,
  67024         0,
  67025         1,
  67026         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  67027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67028         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67029         -1,
  67030         -1,
  67031     },
  67032 #endif /* chips */
  67033 
  67034 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67035     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3C_BCM56560_A0r */
  67036         soc_block_list[4],
  67037         soc_genreg,
  67038         1,
  67039         0,
  67040         0x62002d00,
  67041         0,
  67042         0,
  67043         1,
  67044         soc_LLS_SP_WERR_DYN_CHANGE_0C_BCM56560_A0r_fields,
  67045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67046         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67047         -1,
  67048         -1,
  67049     },
  67050 #endif /* chips */
  67051 
  67052 #if defined(BCM_56340_A0)
  67053     { /* SOC_REG_INT_LLS_SP_WERR_DYN_CHANGE_3_BCM56340_A0r */
  67054         soc_block_list[4],
  67055         soc_genreg,
  67056         1,
  67057         0,
  67058         0x5a00ad00,
  67059         0,
  67060         0,
  67061         1,
  67062         soc_LLS_SP_WERR_DYN_CHANGE_0_BCM56340_A0r_fields,
  67063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67064         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67065         -1,
  67066         -1,
  67067     },
  67068 #endif /* chips */
  67069 
  67070 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67071     { /* SOC_REG_INT_LLS_TDM_AXP_SCHEDULINGr */
  67072         soc_block_list[4],
  67073         soc_genreg,
  67074         1,
  67075         0,
  67076         0x5a001900,
  67077         0,
  67078         0,
  67079         1,
  67080         soc_LLS_TDM_AXP_SCHEDULINGr_fields,
  67081         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  67082         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67083         -1,
  67084         -1,
  67085     },
  67086 #endif /* chips */
  67087 
  67088 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67089     { /* SOC_REG_INT_LLS_TDM_CAL_CFGr */
  67090         soc_block_list[85],
  67091         soc_genreg,
  67092         1,
  67093         0,
  67094         0x80012,
  67095         0,
  67096         0,
  67097         5,
  67098         soc_LLS_TDM_CAL_CFGr_fields,
  67099         SOC_RESET_VAL_DEC(0x001f8000, 0x00000000)
  67100         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  67101         -1,
  67102         -1,
  67103     },
  67104 #endif /* chips */
  67105 
  67106 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  67107     defined(BCM_56270_A0)
  67108     { /* SOC_REG_INT_LLS_TDM_CAL_CFG_BCM56260_A0r */
  67109         soc_block_list[85],
  67110         soc_genreg,
  67111         1,
  67112         0,
  67113         0x2001700,
  67114         0,
  67115         0,
  67116         5,
  67117         soc_LLS_TDM_CAL_CFG_BCM56260_A0r_fields,
  67118         SOC_RESET_VAL_DEC(0x01f80000, 0x00000000)
  67119         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67120         -1,
  67121         -1,
  67122     },
  67123 #endif /* chips */
  67124 
  67125 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67126     defined(BCM_56450_B1)
  67127     { /* SOC_REG_INT_LLS_TDM_CAL_CFG_BCM56450_A0r */
  67128         soc_block_list[85],
  67129         soc_genreg,
  67130         1,
  67131         0,
  67132         0x2001600,
  67133         0,
  67134         0,
  67135         5,
  67136         soc_LLS_TDM_CAL_CFG_BCM56450_A0r_fields,
  67137         SOC_RESET_VAL_DEC(0x007e0000, 0x00000000)
  67138         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  67139         -1,
  67140         -1,
  67141     },
  67142 #endif /* chips */
  67143 
  67144 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67145     { /* SOC_REG_INT_LLS_TDM_CAL_CFG_BCM56640_A0r */
  67146         soc_block_list[4],
  67147         soc_genreg,
  67148         1,
  67149         0,
  67150         0x5a001600,
  67151         0,
  67152         0,
  67153         6,
  67154         soc_LLS_TDM_CAL_CFG_BCM56640_A0r_fields,
  67155         SOC_RESET_VAL_DEC(0x03f00000, 0x00000000)
  67156         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  67157         -1,
  67158         -1,
  67159     },
  67160 #endif /* chips */
  67161 
  67162 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67163     { /* SOC_REG_INT_LLS_TDM_CAL_CFG_SWITCHr */
  67164         soc_block_list[85],
  67165         soc_genreg,
  67166         1,
  67167         0,
  67168         0x80013,
  67169         0,
  67170         0,
  67171         1,
  67172         soc_LLS_TDM_CAL_CFG_SWITCHr_fields,
  67173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67174         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67175         -1,
  67176         -1,
  67177     },
  67178 #endif /* chips */
  67179 
  67180 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  67181     defined(BCM_56270_A0)
  67182     { /* SOC_REG_INT_LLS_TDM_CAL_CFG_SWITCH_BCM56260_A0r */
  67183         soc_block_list[85],
  67184         soc_genreg,
  67185         1,
  67186         0,
  67187         0x2001800,
  67188         0,
  67189         0,
  67190         1,
  67191         soc_LLS_TDM_CAL_CFG_SWITCH_BCM56260_A0r_fields,
  67192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67193         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67194         -1,
  67195         -1,
  67196     },
  67197 #endif /* chips */
  67198 
  67199 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67200     defined(BCM_56450_B1)
  67201     { /* SOC_REG_INT_LLS_TDM_CAL_CFG_SWITCH_BCM56450_A0r */
  67202         soc_block_list[85],
  67203         soc_genreg,
  67204         1,
  67205         0,
  67206         0x2001700,
  67207         0,
  67208         0,
  67209         1,
  67210         soc_LLS_TDM_CAL_CFG_SWITCH_BCM56450_A0r_fields,
  67211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67212         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67213         -1,
  67214         -1,
  67215     },
  67216 #endif /* chips */
  67217 
  67218 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67219     { /* SOC_REG_INT_LLS_TDM_CAL_CFG_SWITCH_BCM56640_A0r */
  67220         soc_block_list[4],
  67221         soc_genreg,
  67222         1,
  67223         0,
  67224         0x5a001700,
  67225         0,
  67226         0,
  67227         1,
  67228         soc_LLS_TDM_CAL_CFG_SWITCH_BCM56640_A0r_fields,
  67229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67230         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67231         -1,
  67232         -1,
  67233     },
  67234 #endif /* chips */
  67235 
  67236 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67237     { /* SOC_REG_INT_LLS_TDM_OPPORTUNISTIC_SPACINGr */
  67238         soc_block_list[4],
  67239         soc_genreg,
  67240         1,
  67241         0,
  67242         0x5a001a00,
  67243         0,
  67244         0,
  67245         1,
  67246         soc_LLS_TDM_OPPORTUNISTIC_SPACINGr_fields,
  67247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67248         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67249         -1,
  67250         -1,
  67251     },
  67252 #endif /* chips */
  67253 
  67254 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67255     { /* SOC_REG_INT_LLS_TDM_STATUSr */
  67256         soc_block_list[4],
  67257         soc_genreg,
  67258         1,
  67259         0,
  67260         0x5a001800,
  67261         0,
  67262         0,
  67263         1,
  67264         soc_LLS_TDM_STATUSr_fields,
  67265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67266         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67267         -1,
  67268         -1,
  67269     },
  67270 #endif /* chips */
  67271 
  67272 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67273     { /* SOC_REG_INT_LLS_TREX2_DEBUG_ENABLEr */
  67274         soc_block_list[85],
  67275         soc_genreg,
  67276         1,
  67277         0,
  67278         0x80000,
  67279         0,
  67280         0,
  67281         1,
  67282         soc_LLS_TREX2_DEBUG_ENABLEr_fields,
  67283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67284         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67285         -1,
  67286         -1,
  67287     },
  67288 #endif /* chips */
  67289 
  67290 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  67291     defined(BCM_56270_A0)
  67292     { /* SOC_REG_INT_LLS_TREX2_DEBUG_ENABLE_BCM56260_A0r */
  67293         soc_block_list[85],
  67294         soc_genreg,
  67295         1,
  67296         0,
  67297         0x2000000,
  67298         0,
  67299         0,
  67300         1,
  67301         soc_LLS_TREX2_DEBUG_ENABLE_BCM56560_A0r_fields,
  67302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67303         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67304         -1,
  67305         -1,
  67306     },
  67307 #endif /* chips */
  67308 
  67309 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67310     defined(BCM_56450_B1)
  67311     { /* SOC_REG_INT_LLS_TREX2_DEBUG_ENABLE_BCM56450_A0r */
  67312         soc_block_list[85],
  67313         soc_genreg,
  67314         1,
  67315         0,
  67316         0x2000000,
  67317         0,
  67318         0,
  67319         1,
  67320         soc_LLS_TREX2_DEBUG_ENABLE_BCM56450_A0r_fields,
  67321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67322         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67323         -1,
  67324         -1,
  67325     },
  67326 #endif /* chips */
  67327 
  67328 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67329     { /* SOC_REG_INT_LLS_TREX2_DEBUG_ENABLE_BCM56560_A0r */
  67330         soc_block_list[4],
  67331         soc_genreg,
  67332         1,
  67333         0,
  67334         0x62000000,
  67335         0,
  67336         0,
  67337         1,
  67338         soc_LLS_TREX2_DEBUG_ENABLE_BCM56560_A0r_fields,
  67339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67340         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67341         -1,
  67342         -1,
  67343     },
  67344 #endif /* chips */
  67345 
  67346 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  67347     { /* SOC_REG_INT_LLS_TWO_S1S_IN_S0_CONFIGr */
  67348         soc_block_list[85],
  67349         soc_genreg,
  67350         1,
  67351         0,
  67352         0x2005f00,
  67353         0,
  67354         0,
  67355         1,
  67356         soc_LLS_TWO_S1S_IN_S0_CONFIGr_fields,
  67357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67358         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  67359         -1,
  67360         -1,
  67361     },
  67362 #endif /* chips */
  67363 
  67364 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  67365     { /* SOC_REG_INT_LLS_XOFF_ECC_DEBUGr */
  67366         soc_block_list[4],
  67367         soc_genreg,
  67368         1,
  67369         0,
  67370         0x62007800,
  67371         0,
  67372         0,
  67373         4,
  67374         soc_LLS_XOFF_ECC_DEBUGr_fields,
  67375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67376         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  67377         -1,
  67378         -1,
  67379     },
  67380 #endif /* chips */
  67381 
  67382 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67383     { /* SOC_REG_INT_LMEP_1_PARITY_CONTROLr */
  67384         soc_block_list[5],
  67385         soc_genreg,
  67386         1,
  67387         0,
  67388         0x80316,
  67389         0,
  67390         0,
  67391         1,
  67392         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  67393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67394         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67395         -1,
  67396         -1,
  67397     },
  67398 #endif /* chips */
  67399 
  67400 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67401     defined(BCM_56450_B1)
  67402     { /* SOC_REG_INT_LMEP_1_PARITY_CONTROL_BCM56450_A0r */
  67403         soc_block_list[5],
  67404         soc_genreg,
  67405         1,
  67406         0,
  67407         0x2011400,
  67408         0,
  67409         0,
  67410         1,
  67411         soc_FT_CNTR_SER_CONTROLr_fields,
  67412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67413         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67414         -1,
  67415         -1,
  67416     },
  67417 #endif /* chips */
  67418 
  67419 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67420     { /* SOC_REG_INT_LMEP_1_PARITY_STATUS_INTRr */
  67421         soc_block_list[5],
  67422         soc_genreg,
  67423         1,
  67424         0,
  67425         0x80317,
  67426         0,
  67427         0,
  67428         3,
  67429         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
  67430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67431         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67432         -1,
  67433         -1,
  67434     },
  67435 #endif /* chips */
  67436 
  67437 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67438     defined(BCM_56450_B1)
  67439     { /* SOC_REG_INT_LMEP_1_PARITY_STATUS_INTR_BCM56450_A0r */
  67440         soc_block_list[5],
  67441         soc_genreg,
  67442         1,
  67443         0,
  67444         0x2011500,
  67445         0,
  67446         0,
  67447         3,
  67448         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  67449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67450         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67451         -1,
  67452         -1,
  67453     },
  67454 #endif /* chips */
  67455 
  67456 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67457     { /* SOC_REG_INT_LMEP_1_PARITY_STATUS_NACKr */
  67458         soc_block_list[5],
  67459         soc_genreg,
  67460         1,
  67461         0,
  67462         0x80318,
  67463         0,
  67464         0,
  67465         3,
  67466         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
  67467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67468         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67469         -1,
  67470         -1,
  67471     },
  67472 #endif /* chips */
  67473 
  67474 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67475     defined(BCM_56450_B1)
  67476     { /* SOC_REG_INT_LMEP_1_PARITY_STATUS_NACK_BCM56450_A0r */
  67477         soc_block_list[5],
  67478         soc_genreg,
  67479         1,
  67480         0,
  67481         0x2011600,
  67482         0,
  67483         0,
  67484         3,
  67485         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  67486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67488         -1,
  67489         -1,
  67490     },
  67491 #endif /* chips */
  67492 
  67493 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67494     { /* SOC_REG_INT_LMEP_COMMONr */
  67495         soc_block_list[5],
  67496         soc_genreg,
  67497         1,
  67498         0,
  67499         0x2000000,
  67500         0,
  67501         0,
  67502         3,
  67503         soc_LMEP_COMMONr_fields,
  67504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67505         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  67506         -1,
  67507         -1,
  67508     },
  67509 #endif /* chips */
  67510 
  67511 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  67512     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  67513     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  67514     { /* SOC_REG_INT_LMEP_COMMON_1r */
  67515         soc_block_list[5],
  67516         soc_genreg,
  67517         1,
  67518         0,
  67519         0x80010,
  67520         0,
  67521         0,
  67522         1,
  67523         soc_LMEP_COMMON_1r_fields,
  67524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67526         -1,
  67527         -1,
  67528     },
  67529 #endif /* chips */
  67530 
  67531 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  67532     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  67533     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  67534     { /* SOC_REG_INT_LMEP_COMMON_2r */
  67535         soc_block_list[5],
  67536         soc_genreg,
  67537         1,
  67538         0,
  67539         0x80011,
  67540         0,
  67541         0,
  67542         4,
  67543         soc_LMEP_COMMON_2r_fields,
  67544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67545         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67546         -1,
  67547         -1,
  67548     },
  67549 #endif /* chips */
  67550 
  67551 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  67552     { /* SOC_REG_INT_LMEP_COMMON_1_BCM56334_A0r */
  67553         soc_block_list[5],
  67554         soc_genreg,
  67555         1,
  67556         0,
  67557         0x80010,
  67558         0,
  67559         0,
  67560         1,
  67561         soc_LMEP_COMMON_1_BCM56334_A0r_fields,
  67562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67564         -1,
  67565         -1,
  67566     },
  67567 #endif /* chips */
  67568 
  67569 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  67570     { /* SOC_REG_INT_LMEP_COMMON_1_BCM56840_A0r */
  67571         soc_block_list[5],
  67572         soc_genreg,
  67573         1,
  67574         0,
  67575         0x8030d,
  67576         0,
  67577         0,
  67578         1,
  67579         soc_LMEP_COMMON_1r_fields,
  67580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67582         -1,
  67583         -1,
  67584     },
  67585 #endif /* chips */
  67586 
  67587 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  67588     { /* SOC_REG_INT_LMEP_COMMON_2_BCM56334_A0r */
  67589         soc_block_list[5],
  67590         soc_genreg,
  67591         1,
  67592         0,
  67593         0x80011,
  67594         0,
  67595         0,
  67596         4,
  67597         soc_LMEP_COMMON_2_BCM56334_A0r_fields,
  67598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67599         SOC_RESET_MASK_DEC(0x007f0007, 0x00000000)
  67600         -1,
  67601         -1,
  67602     },
  67603 #endif /* chips */
  67604 
  67605 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67606     { /* SOC_REG_INT_LMEP_COMMON_2_BCM56440_A0r */
  67607         soc_block_list[5],
  67608         soc_genreg,
  67609         1,
  67610         0,
  67611         0x80310,
  67612         0,
  67613         0,
  67614         4,
  67615         soc_LMEP_COMMON_2_BCM56840_A0r_fields,
  67616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67617         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  67618         -1,
  67619         -1,
  67620     },
  67621 #endif /* chips */
  67622 
  67623 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  67624     { /* SOC_REG_INT_LMEP_COMMON_2_BCM56840_A0r */
  67625         soc_block_list[5],
  67626         soc_genreg,
  67627         1,
  67628         0,
  67629         0x8030e,
  67630         0,
  67631         0,
  67632         4,
  67633         soc_LMEP_COMMON_2_BCM56840_A0r_fields,
  67634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67635         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  67636         -1,
  67637         -1,
  67638     },
  67639 #endif /* chips */
  67640 
  67641 #if defined(BCM_53400_A0)
  67642     { /* SOC_REG_INT_LMEP_COMMON_BCM53400_A0r */
  67643         soc_block_list[5],
  67644         soc_genreg,
  67645         1,
  67646         0,
  67647         0x2000e00,
  67648         0,
  67649         0,
  67650         3,
  67651         soc_LMEP_COMMON_BCM53400_A0r_fields,
  67652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67653         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  67654         -1,
  67655         -1,
  67656     },
  67657 #endif /* chips */
  67658 
  67659 #if defined(BCM_56150_A0)
  67660     { /* SOC_REG_INT_LMEP_COMMON_BCM56150_A0r */
  67661         soc_block_list[5],
  67662         soc_genreg,
  67663         1,
  67664         0,
  67665         0x2000e00,
  67666         0,
  67667         0,
  67668         3,
  67669         soc_LMEP_COMMON_BCM56150_A0r_fields,
  67670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67671         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  67672         -1,
  67673         -1,
  67674     },
  67675 #endif /* chips */
  67676 
  67677 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  67678     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  67679     { /* SOC_REG_INT_LMEP_COMMON_BCM56160_A0r */
  67680         soc_block_list[5],
  67681         soc_genreg,
  67682         1,
  67683         0,
  67684         0x2000e00,
  67685         0,
  67686         0,
  67687         3,
  67688         soc_LMEP_COMMON_BCM56160_A0r_fields,
  67689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67690         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  67691         -1,
  67692         -1,
  67693     },
  67694 #endif /* chips */
  67695 
  67696 #if defined(BCM_56850_A0)
  67697     { /* SOC_REG_INT_LMEP_COMMON_BCM56850_A0r */
  67698         soc_block_list[5],
  67699         soc_genreg,
  67700         1,
  67701         0,
  67702         0x770c0000,
  67703         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  67704         0,
  67705         3,
  67706         soc_LMEP_COMMON_BCM56850_A0r_fields,
  67707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67708         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67709         -1,
  67710         -1,
  67711     },
  67712 #endif /* chips */
  67713 
  67714 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  67715     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  67716     defined(BCM_56160_A0)
  67717     { /* SOC_REG_INT_LMEP_DA_PARITY_CONTROLr */
  67718         soc_block_list[5],
  67719         soc_genreg,
  67720         1,
  67721         0,
  67722         0x2010400,
  67723         0,
  67724         0,
  67725         1,
  67726         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  67727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67728         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67729         -1,
  67730         -1,
  67731     },
  67732 #endif /* chips */
  67733 
  67734 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  67735     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  67736     defined(BCM_56160_A0)
  67737     { /* SOC_REG_INT_LMEP_DA_PARITY_STATUSr */
  67738         soc_block_list[5],
  67739         soc_genreg,
  67740         1,
  67741         0,
  67742         0x2010500,
  67743         0,
  67744         0,
  67745         3,
  67746         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
  67747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67748         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  67749         -1,
  67750         -1,
  67751     },
  67752 #endif /* chips */
  67753 
  67754 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  67755     { /* SOC_REG_INT_LMEP_DA_PDA_CONTROLr */
  67756         soc_block_list[5],
  67757         soc_genreg,
  67758         1,
  67759         0,
  67760         0x2011200,
  67761         0,
  67762         0,
  67763         1,
  67764         soc_LMEP_DA_PDA_CONTROLr_fields,
  67765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67766         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67767         -1,
  67768         -1,
  67769     },
  67770 #endif /* chips */
  67771 
  67772 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  67773     defined(BCM_56334_B0) || defined(BCM_56524_A0) || \
  67774     defined(BCM_56524_B0) || defined(BCM_56634_A0) || \
  67775     defined(BCM_56634_B0) || defined(BCM_56685_A0) || \
  67776     defined(BCM_56685_B0)
  67777     { /* SOC_REG_INT_LMEP_PARITY_CONTROLr */
  67778         soc_block_list[5],
  67779         soc_genreg,
  67780         1,
  67781         0,
  67782         0x80101,
  67783         0,
  67784         0,
  67785         1,
  67786         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  67787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67788         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67789         -1,
  67790         -1,
  67791     },
  67792 #endif /* chips */
  67793 
  67794 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  67795     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  67796     defined(BCM_56160_A0)
  67797     { /* SOC_REG_INT_LMEP_PARITY_CONTROL_BCM53400_A0r */
  67798         soc_block_list[5],
  67799         soc_genreg,
  67800         1,
  67801         0,
  67802         0x2010200,
  67803         0,
  67804         0,
  67805         1,
  67806         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  67807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67808         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67809         -1,
  67810         -1,
  67811     },
  67812 #endif /* chips */
  67813 
  67814 #if defined(BCM_56150_A0)
  67815     { /* SOC_REG_INT_LMEP_PARITY_CONTROL_BCM56150_A0r */
  67816         soc_block_list[5],
  67817         soc_genreg,
  67818         1,
  67819         0,
  67820         0x2010100,
  67821         0,
  67822         0,
  67823         1,
  67824         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  67825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67826         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  67827         -1,
  67828         -1,
  67829     },
  67830 #endif /* chips */
  67831 
  67832 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67833     defined(BCM_56450_B1)
  67834     { /* SOC_REG_INT_LMEP_PARITY_CONTROL_BCM56450_A0r */
  67835         soc_block_list[5],
  67836         soc_genreg,
  67837         1,
  67838         0,
  67839         0x2011100,
  67840         0,
  67841         0,
  67842         1,
  67843         soc_FT_CNTR_SER_CONTROLr_fields,
  67844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67845         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67846         -1,
  67847         -1,
  67848     },
  67849 #endif /* chips */
  67850 
  67851 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  67852     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  67853     { /* SOC_REG_INT_LMEP_PARITY_CONTROL_BCM56840_A0r */
  67854         soc_block_list[5],
  67855         soc_genreg,
  67856         1,
  67857         0,
  67858         0x80313,
  67859         0,
  67860         0,
  67861         1,
  67862         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  67863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67864         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67865         -1,
  67866         -1,
  67867     },
  67868 #endif /* chips */
  67869 
  67870 #if defined(BCM_56150_A0)
  67871     { /* SOC_REG_INT_LMEP_PARITY_STATUSr */
  67872         soc_block_list[5],
  67873         soc_genreg,
  67874         1,
  67875         0,
  67876         0x2010200,
  67877         0,
  67878         0,
  67879         3,
  67880         soc_EGR_FP_COUNTER_PARITY_STATUSr_fields,
  67881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67882         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  67883         -1,
  67884         -1,
  67885     },
  67886 #endif /* chips */
  67887 
  67888 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  67889     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  67890     defined(BCM_56160_A0)
  67891     { /* SOC_REG_INT_LMEP_PARITY_STATUS_BCM53400_A0r */
  67892         soc_block_list[5],
  67893         soc_genreg,
  67894         1,
  67895         0,
  67896         0x2010300,
  67897         0,
  67898         0,
  67899         3,
  67900         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
  67901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67902         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  67903         -1,
  67904         -1,
  67905     },
  67906 #endif /* chips */
  67907 
  67908 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  67909     defined(BCM_56334_B0) || defined(BCM_56524_A0) || \
  67910     defined(BCM_56524_B0) || defined(BCM_56634_A0) || \
  67911     defined(BCM_56634_B0) || defined(BCM_56685_A0) || \
  67912     defined(BCM_56685_B0)
  67913     { /* SOC_REG_INT_LMEP_PARITY_STATUS_INTRr */
  67914         soc_block_list[5],
  67915         soc_genreg,
  67916         1,
  67917         0,
  67918         0x80102,
  67919         0,
  67920         0,
  67921         3,
  67922         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  67923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67924         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  67925         -1,
  67926         -1,
  67927     },
  67928 #endif /* chips */
  67929 
  67930 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  67931     { /* SOC_REG_INT_LMEP_PARITY_STATUS_INTR_BCM56440_A0r */
  67932         soc_block_list[5],
  67933         soc_genreg,
  67934         1,
  67935         0,
  67936         0x80314,
  67937         0,
  67938         0,
  67939         3,
  67940         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
  67941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67942         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67943         -1,
  67944         -1,
  67945     },
  67946 #endif /* chips */
  67947 
  67948 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  67949     defined(BCM_56450_B1)
  67950     { /* SOC_REG_INT_LMEP_PARITY_STATUS_INTR_BCM56450_A0r */
  67951         soc_block_list[5],
  67952         soc_genreg,
  67953         1,
  67954         0,
  67955         0x2011200,
  67956         0,
  67957         0,
  67958         3,
  67959         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  67960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67961         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67962         -1,
  67963         -1,
  67964     },
  67965 #endif /* chips */
  67966 
  67967 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  67968     { /* SOC_REG_INT_LMEP_PARITY_STATUS_INTR_BCM56840_A0r */
  67969         soc_block_list[5],
  67970         soc_genreg,
  67971         1,
  67972         0,
  67973         0x80314,
  67974         0,
  67975         0,
  67976         3,
  67977         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  67978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67979         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  67980         -1,
  67981         -1,
  67982     },
  67983 #endif /* chips */
  67984 
  67985 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  67986     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  67987     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  67988     { /* SOC_REG_INT_LMEP_PARITY_STATUS_NACKr */
  67989         soc_block_list[5],
  67990         soc_genreg,
  67991         1,
  67992         0,
  67993         0x80103,
  67994         0,
  67995         0,
  67996         3,
  67997         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  67998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67999         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  68000         -1,
  68001         -1,
  68002     },
  68003 #endif /* chips */
  68004 
  68005 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  68006     { /* SOC_REG_INT_LMEP_PARITY_STATUS_NACK_BCM56440_A0r */
  68007         soc_block_list[5],
  68008         soc_genreg,
  68009         1,
  68010         0,
  68011         0x80315,
  68012         0,
  68013         0,
  68014         3,
  68015         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
  68016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68017         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68018         -1,
  68019         -1,
  68020     },
  68021 #endif /* chips */
  68022 
  68023 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68024     defined(BCM_56450_B1)
  68025     { /* SOC_REG_INT_LMEP_PARITY_STATUS_NACK_BCM56450_A0r */
  68026         soc_block_list[5],
  68027         soc_genreg,
  68028         1,
  68029         0,
  68030         0x2011300,
  68031         0,
  68032         0,
  68033         3,
  68034         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  68035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68036         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68037         -1,
  68038         -1,
  68039     },
  68040 #endif /* chips */
  68041 
  68042 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  68043     { /* SOC_REG_INT_LMEP_PARITY_STATUS_NACK_BCM56840_A0r */
  68044         soc_block_list[5],
  68045         soc_genreg,
  68046         1,
  68047         0,
  68048         0x80315,
  68049         0,
  68050         0,
  68051         3,
  68052         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  68053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68054         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68055         -1,
  68056         -1,
  68057     },
  68058 #endif /* chips */
  68059 
  68060 #if defined(BCM_56640_A0)
  68061     { /* SOC_REG_INT_LMEP_PDA_CONTROLr */
  68062         soc_block_list[5],
  68063         soc_genreg,
  68064         1,
  68065         0,
  68066         0x2011100,
  68067         SOC_REG_FLAG_64_BITS,
  68068         0,
  68069         3,
  68070         soc_LMEP_PDA_CONTROLr_fields,
  68071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68072         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68073         -1,
  68074         -1,
  68075     },
  68076 #endif /* chips */
  68077 
  68078 #if defined(BCM_56340_A0)
  68079     { /* SOC_REG_INT_LMEP_PDA_CONTROL_BCM56340_A0r */
  68080         soc_block_list[5],
  68081         soc_genreg,
  68082         1,
  68083         0,
  68084         0x2011100,
  68085         SOC_REG_FLAG_64_BITS,
  68086         0,
  68087         3,
  68088         soc_LMEP_PDA_CONTROL_BCM56340_A0r_fields,
  68089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68091         -1,
  68092         -1,
  68093     },
  68094 #endif /* chips */
  68095 
  68096 #if defined(BCM_88732_A0)
  68097     { /* SOC_REG_INT_LOADING_BAND_THRESHOLDr */
  68098         soc_block_list[5],
  68099         soc_genreg,
  68100         7,
  68101         0,
  68102         0x6080061,
  68103         SOC_REG_FLAG_ARRAY,
  68104         0,
  68105         1,
  68106         soc_LOADING_BAND_THRESHOLDr_fields,
  68107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68108         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  68109         -1,
  68110         -1,
  68111     },
  68112 #endif /* chips */
  68113 
  68114 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  68115     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  68116     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  68117     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRLr */
  68118         soc_block_list[5],
  68119         soc_portreg,
  68120         1,
  68121         0,
  68122         0x11000066,
  68123         0,
  68124         0,
  68125         3,
  68126         soc_LOCAL_SW_DISABLE_CTRLr_fields,
  68127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68128         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68129         -1,
  68130         -1,
  68131     },
  68132 #endif /* chips */
  68133 
  68134 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  68135     defined(BCM_56160_A0)
  68136     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r */
  68137         soc_block_list[5],
  68138         soc_portreg,
  68139         1,
  68140         0,
  68141         0x40001f00,
  68142         0,
  68143         0,
  68144         3,
  68145         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68147         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68148         -1,
  68149         -1,
  68150     },
  68151 #endif /* chips */
  68152 
  68153 #if defined(BCM_53570_A0)
  68154     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM53570_A0r */
  68155         soc_block_list[5],
  68156         soc_portreg,
  68157         1,
  68158         0,
  68159         0x40005000,
  68160         0,
  68161         0,
  68162         3,
  68163         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68165         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68166         -1,
  68167         -1,
  68168     },
  68169 #endif /* chips */
  68170 
  68171 #if defined(BCM_53570_B0)
  68172     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM53570_B0r */
  68173         soc_block_list[5],
  68174         soc_portreg,
  68175         1,
  68176         0,
  68177         0x40005400,
  68178         0,
  68179         0,
  68180         3,
  68181         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68183         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68184         -1,
  68185         -1,
  68186     },
  68187 #endif /* chips */
  68188 
  68189 #if defined(BCM_56142_A0)
  68190     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56142_A0r */
  68191         soc_block_list[5],
  68192         soc_portreg,
  68193         1,
  68194         0,
  68195         0x11000083,
  68196         0,
  68197         0,
  68198         3,
  68199         soc_LOCAL_SW_DISABLE_CTRLr_fields,
  68200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68201         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68202         -1,
  68203         -1,
  68204     },
  68205 #endif /* chips */
  68206 
  68207 #if defined(BCM_56150_A0)
  68208     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56150_A0r */
  68209         soc_block_list[5],
  68210         soc_portreg,
  68211         1,
  68212         0,
  68213         0x44001f00,
  68214         0,
  68215         0,
  68216         3,
  68217         soc_LOCAL_SW_DISABLE_CTRL_BCM56640_A0r_fields,
  68218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68219         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68220         -1,
  68221         -1,
  68222     },
  68223 #endif /* chips */
  68224 
  68225 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  68226     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56260_A0r */
  68227         soc_block_list[5],
  68228         soc_ppportreg,
  68229         1,
  68230         0,
  68231         0x3c004400,
  68232         0,
  68233         0,
  68234         3,
  68235         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68237         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68238         -1,
  68239         87,
  68240     },
  68241 #endif /* chips */
  68242 
  68243 #if defined(BCM_56270_A0)
  68244     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56270_A0r */
  68245         soc_block_list[5],
  68246         soc_ppportreg,
  68247         1,
  68248         0,
  68249         0x3c004400,
  68250         0,
  68251         0,
  68252         3,
  68253         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68255         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68256         -1,
  68257         90,
  68258     },
  68259 #endif /* chips */
  68260 
  68261 #if defined(BCM_56370_A0)
  68262     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56370_A0r */
  68263         soc_block_list[5],
  68264         soc_portreg,
  68265         1,
  68266         0,
  68267         0x80000200,
  68268         0,
  68269         0,
  68270         3,
  68271         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68273         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68274         -1,
  68275         -1,
  68276         3,
  68277     },
  68278 #endif /* chips */
  68279 
  68280 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68281     defined(BCM_56450_B1)
  68282     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56450_A0r */
  68283         soc_block_list[5],
  68284         soc_ppportreg,
  68285         1,
  68286         0,
  68287         0x3c004400,
  68288         0,
  68289         0,
  68290         3,
  68291         soc_LOCAL_SW_DISABLE_CTRL_BCM56640_A0r_fields,
  68292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68293         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68294         -1,
  68295         74,
  68296     },
  68297 #endif /* chips */
  68298 
  68299 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  68300     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  68301     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56560_A0r */
  68302         soc_block_list[5],
  68303         soc_portreg,
  68304         1,
  68305         0,
  68306         0x54006600,
  68307         0,
  68308         0,
  68309         3,
  68310         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68312         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68313         -1,
  68314         -1,
  68315     },
  68316 #endif /* chips */
  68317 
  68318 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  68319     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  68320     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  68321     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56634_A0r */
  68322         soc_block_list[5],
  68323         soc_portreg,
  68324         1,
  68325         0,
  68326         0xe000066,
  68327         0,
  68328         0,
  68329         3,
  68330         soc_LOCAL_SW_DISABLE_CTRLr_fields,
  68331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68332         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68333         -1,
  68334         -1,
  68335     },
  68336 #endif /* chips */
  68337 
  68338 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  68339     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56640_A0r */
  68340         soc_block_list[5],
  68341         soc_portreg,
  68342         1,
  68343         0,
  68344         0x38000400,
  68345         0,
  68346         0,
  68347         3,
  68348         soc_LOCAL_SW_DISABLE_CTRL_BCM56640_A0r_fields,
  68349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68350         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68351         -1,
  68352         -1,
  68353     },
  68354 #endif /* chips */
  68355 
  68356 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  68357     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56820_A0r */
  68358         soc_block_list[5],
  68359         soc_portreg,
  68360         1,
  68361         0,
  68362         0xf000066,
  68363         0,
  68364         0,
  68365         3,
  68366         soc_LOCAL_SW_DISABLE_CTRLr_fields,
  68367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68368         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68369         -1,
  68370         -1,
  68371     },
  68372 #endif /* chips */
  68373 
  68374 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  68375     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  68376     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56840_A0r */
  68377         soc_block_list[5],
  68378         soc_portreg,
  68379         1,
  68380         0,
  68381         0xf000666,
  68382         0,
  68383         0,
  68384         3,
  68385         soc_LOCAL_SW_DISABLE_CTRLr_fields,
  68386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68387         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68388         -1,
  68389         -1,
  68390     },
  68391 #endif /* chips */
  68392 
  68393 #if defined(BCM_56850_A0)
  68394     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56850_A0r */
  68395         soc_block_list[5],
  68396         soc_portreg,
  68397         1,
  68398         0,
  68399         0x44006600,
  68400         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68401         0,
  68402         3,
  68403         soc_LOCAL_SW_DISABLE_CTRL_BCM56640_A0r_fields,
  68404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68405         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68406         -1,
  68407         -1,
  68408     },
  68409 #endif /* chips */
  68410 
  68411 #if defined(BCM_56860_A0)
  68412     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56860_A0r */
  68413         soc_block_list[5],
  68414         soc_portreg,
  68415         1,
  68416         0,
  68417         0x54006600,
  68418         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68419         0,
  68420         3,
  68421         soc_LOCAL_SW_DISABLE_CTRL_BCM56640_A0r_fields,
  68422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68423         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68424         -1,
  68425         -1,
  68426     },
  68427 #endif /* chips */
  68428 
  68429 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  68430     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56870_A0r */
  68431         soc_block_list[5],
  68432         soc_portreg,
  68433         1,
  68434         0,
  68435         0x80000200,
  68436         (12 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68437         0,
  68438         3,
  68439         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68441         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68442         -1,
  68443         -1,
  68444         3,
  68445     },
  68446 #endif /* chips */
  68447 
  68448 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  68449     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56960_A0r */
  68450         soc_block_list[5],
  68451         soc_portreg,
  68452         1,
  68453         0,
  68454         0x50000200,
  68455         (12 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68456         0,
  68457         3,
  68458         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68460         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68461         -1,
  68462         -1,
  68463         3,
  68464     },
  68465 #endif /* chips */
  68466 
  68467 #if defined(BCM_56970_A0)
  68468     { /* SOC_REG_INT_LOCAL_SW_DISABLE_CTRL_BCM56970_A0r */
  68469         soc_block_list[5],
  68470         soc_portreg,
  68471         1,
  68472         0,
  68473         0x90000200,
  68474         (12 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  68475         0,
  68476         3,
  68477         soc_LOCAL_SW_DISABLE_CTRL_BCM53400_A0r_fields,
  68478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68479         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68480         -1,
  68481         -1,
  68482         3,
  68483     },
  68484 #endif /* chips */
  68485 
  68486 #if defined(BCM_56800_A0)
  68487     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBMr */
  68488         soc_block_list[5],
  68489         soc_portreg,
  68490         1,
  68491         0,
  68492         0xe000048,
  68493         0,
  68494         0,
  68495         1,
  68496         soc_EPC_LINK_BMAP_BCM56800_A0r_fields,
  68497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68498         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  68499         -1,
  68500         -1,
  68501     },
  68502 #endif /* chips */
  68503 
  68504 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  68505     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  68506     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_64r */
  68507         soc_block_list[5],
  68508         soc_portreg,
  68509         1,
  68510         0,
  68511         0x11000048,
  68512         SOC_REG_FLAG_64_BITS,
  68513         0,
  68514         3,
  68515         soc_EPC_LINK_BMAP_64r_fields,
  68516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68517         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  68518         -1,
  68519         -1,
  68520     },
  68521 #endif /* chips */
  68522 
  68523 #if defined(BCM_53400_A0)
  68524     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM53400_A0r */
  68525         soc_block_list[5],
  68526         soc_portreg,
  68527         1,
  68528         0,
  68529         0x40001000,
  68530         0,
  68531         0,
  68532         2,
  68533         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM53400_A0r_fields,
  68534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68535         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68536         -1,
  68537         -1,
  68538     },
  68539 #endif /* chips */
  68540 
  68541 #if defined(BCM_56142_A0)
  68542     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM56142_A0r */
  68543         soc_block_list[5],
  68544         soc_portreg,
  68545         1,
  68546         0,
  68547         0x11000068,
  68548         0,
  68549         0,
  68550         2,
  68551         soc_EPC_LINK_BMAP_64_BCM56334_A0r_fields,
  68552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68553         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  68554         -1,
  68555         -1,
  68556     },
  68557 #endif /* chips */
  68558 
  68559 #if defined(BCM_56150_A0)
  68560     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM56150_A0r */
  68561         soc_block_list[5],
  68562         soc_portreg,
  68563         1,
  68564         0,
  68565         0x44001000,
  68566         0,
  68567         0,
  68568         2,
  68569         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM56150_A0r_fields,
  68570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68572         -1,
  68573         -1,
  68574     },
  68575 #endif /* chips */
  68576 
  68577 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  68578     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM56160_A0r */
  68579         soc_block_list[5],
  68580         soc_portreg,
  68581         1,
  68582         0,
  68583         0x40001000,
  68584         0,
  68585         0,
  68586         2,
  68587         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM56160_A0r_fields,
  68588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68589         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68590         -1,
  68591         -1,
  68592     },
  68593 #endif /* chips */
  68594 
  68595 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  68596     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM56334_A0r */
  68597         soc_block_list[5],
  68598         soc_portreg,
  68599         1,
  68600         0,
  68601         0x11000048,
  68602         0,
  68603         0,
  68604         2,
  68605         soc_EPC_LINK_BMAP_64_BCM56334_A0r_fields,
  68606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68607         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  68608         -1,
  68609         -1,
  68610     },
  68611 #endif /* chips */
  68612 
  68613 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  68614     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  68615     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  68616     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM56634_A0r */
  68617         soc_block_list[5],
  68618         soc_portreg,
  68619         1,
  68620         0,
  68621         0xe000048,
  68622         SOC_REG_FLAG_64_BITS,
  68623         0,
  68624         4,
  68625         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_64r_fields,
  68626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68627         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  68628         -1,
  68629         -1,
  68630     },
  68631 #endif /* chips */
  68632 
  68633 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  68634     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_BCM53314_A0r */
  68635         soc_block_list[5],
  68636         soc_portreg,
  68637         1,
  68638         0,
  68639         0xf000136,
  68640         0,
  68641         0,
  68642         1,
  68643         soc_E2E_HOL_PBM_BCM56820_A0r_fields,
  68644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68645         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  68646         -1,
  68647         -1,
  68648     },
  68649 #endif /* chips */
  68650 
  68651 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  68652     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_BCM56224_A0r */
  68653         soc_block_list[5],
  68654         soc_portreg,
  68655         1,
  68656         0,
  68657         0xf000136,
  68658         0,
  68659         0,
  68660         1,
  68661         soc_EPC_LINK_BMAP_BCM56224_A0r_fields,
  68662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68663         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  68664         -1,
  68665         -1,
  68666     },
  68667 #endif /* chips */
  68668 
  68669 #if defined(BCM_56514_A0)
  68670     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_BCM56514_A0r */
  68671         soc_block_list[5],
  68672         soc_portreg,
  68673         1,
  68674         0,
  68675         0xe000136,
  68676         0,
  68677         0,
  68678         1,
  68679         soc_EPC_LINK_BMAPr_fields,
  68680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68681         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  68682         -1,
  68683         -1,
  68684     },
  68685 #endif /* chips */
  68686 
  68687 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  68688     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_BCM56820_A0r */
  68689         soc_block_list[5],
  68690         soc_portreg,
  68691         1,
  68692         0,
  68693         0xf000048,
  68694         0,
  68695         0,
  68696         1,
  68697         soc_EPC_LINK_BMAPr_fields,
  68698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68699         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  68700         -1,
  68701         -1,
  68702     },
  68703 #endif /* chips */
  68704 
  68705 #if defined(BCM_53570_A0)
  68706     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_HIr */
  68707         soc_block_list[5],
  68708         soc_portreg,
  68709         1,
  68710         0,
  68711         0x40003900,
  68712         SOC_REG_FLAG_64_BITS,
  68713         0,
  68714         5,
  68715         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_HIr_fields,
  68716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68717         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68718         -1,
  68719         -1,
  68720     },
  68721 #endif /* chips */
  68722 
  68723 #if defined(BCM_53570_B0)
  68724     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_HI_BCM53570_B0r */
  68725         soc_block_list[5],
  68726         soc_portreg,
  68727         1,
  68728         0,
  68729         0x40003d00,
  68730         SOC_REG_FLAG_64_BITS,
  68731         0,
  68732         5,
  68733         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_HIr_fields,
  68734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68735         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68736         -1,
  68737         -1,
  68738     },
  68739 #endif /* chips */
  68740 
  68741 #if defined(BCM_53570_A0)
  68742     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_LOr */
  68743         soc_block_list[5],
  68744         soc_portreg,
  68745         1,
  68746         0,
  68747         0x40003800,
  68748         SOC_REG_FLAG_64_BITS,
  68749         0,
  68750         4,
  68751         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_LOr_fields,
  68752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68753         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68754         -1,
  68755         -1,
  68756     },
  68757 #endif /* chips */
  68758 
  68759 #if defined(BCM_53570_B0)
  68760     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_LO_BCM53570_B0r */
  68761         soc_block_list[5],
  68762         soc_portreg,
  68763         1,
  68764         0,
  68765         0x40003c00,
  68766         SOC_REG_FLAG_64_BITS,
  68767         0,
  68768         4,
  68769         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_LOr_fields,
  68770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68771         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68772         -1,
  68773         -1,
  68774     },
  68775 #endif /* chips */
  68776 
  68777 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  68778     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRRr */
  68779         soc_block_list[5],
  68780         soc_portreg,
  68781         1,
  68782         0,
  68783         0xf00004b,
  68784         0,
  68785         0,
  68786         1,
  68787         soc_EPC_LINK_BMAPr_fields,
  68788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68789         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  68790         -1,
  68791         -1,
  68792     },
  68793 #endif /* chips */
  68794 
  68795 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  68796     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  68797     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_64r */
  68798         soc_block_list[5],
  68799         soc_portreg,
  68800         1,
  68801         0,
  68802         0x1100004b,
  68803         SOC_REG_FLAG_64_BITS,
  68804         0,
  68805         3,
  68806         soc_EPC_LINK_BMAP_64r_fields,
  68807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68808         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  68809         -1,
  68810         -1,
  68811     },
  68812 #endif /* chips */
  68813 
  68814 #if defined(BCM_53400_A0)
  68815     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_64_BCM53400_A0r */
  68816         soc_block_list[5],
  68817         soc_portreg,
  68818         1,
  68819         0,
  68820         0x40001600,
  68821         0,
  68822         0,
  68823         2,
  68824         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM53400_A0r_fields,
  68825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68826         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68827         -1,
  68828         -1,
  68829     },
  68830 #endif /* chips */
  68831 
  68832 #if defined(BCM_56142_A0)
  68833     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_64_BCM56142_A0r */
  68834         soc_block_list[5],
  68835         soc_portreg,
  68836         1,
  68837         0,
  68838         0x1100006b,
  68839         0,
  68840         0,
  68841         2,
  68842         soc_EPC_LINK_BMAP_64_BCM56334_A0r_fields,
  68843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68844         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  68845         -1,
  68846         -1,
  68847     },
  68848 #endif /* chips */
  68849 
  68850 #if defined(BCM_56150_A0)
  68851     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_64_BCM56150_A0r */
  68852         soc_block_list[5],
  68853         soc_portreg,
  68854         1,
  68855         0,
  68856         0x44001600,
  68857         0,
  68858         0,
  68859         2,
  68860         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM56150_A0r_fields,
  68861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68862         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68863         -1,
  68864         -1,
  68865     },
  68866 #endif /* chips */
  68867 
  68868 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  68869     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_64_BCM56160_A0r */
  68870         soc_block_list[5],
  68871         soc_portreg,
  68872         1,
  68873         0,
  68874         0x40001600,
  68875         0,
  68876         0,
  68877         2,
  68878         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_64_BCM56160_A0r_fields,
  68879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68880         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  68881         -1,
  68882         -1,
  68883     },
  68884 #endif /* chips */
  68885 
  68886 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  68887     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_64_BCM56334_A0r */
  68888         soc_block_list[5],
  68889         soc_portreg,
  68890         1,
  68891         0,
  68892         0x1100004b,
  68893         0,
  68894         0,
  68895         2,
  68896         soc_EPC_LINK_BMAP_64_BCM56334_A0r_fields,
  68897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68898         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  68899         -1,
  68900         -1,
  68901     },
  68902 #endif /* chips */
  68903 
  68904 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  68905     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  68906     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  68907     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_64_BCM56634_A0r */
  68908         soc_block_list[5],
  68909         soc_portreg,
  68910         1,
  68911         0,
  68912         0xe00004b,
  68913         SOC_REG_FLAG_64_BITS,
  68914         0,
  68915         4,
  68916         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_64r_fields,
  68917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68918         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  68919         -1,
  68920         -1,
  68921     },
  68922 #endif /* chips */
  68923 
  68924 #if defined(BCM_53570_A0)
  68925     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_HIr */
  68926         soc_block_list[5],
  68927         soc_portreg,
  68928         1,
  68929         0,
  68930         0x40004500,
  68931         SOC_REG_FLAG_64_BITS,
  68932         0,
  68933         5,
  68934         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_HIr_fields,
  68935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68936         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68937         -1,
  68938         -1,
  68939     },
  68940 #endif /* chips */
  68941 
  68942 #if defined(BCM_53570_B0)
  68943     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_HI_BCM53570_B0r */
  68944         soc_block_list[5],
  68945         soc_portreg,
  68946         1,
  68947         0,
  68948         0x40004900,
  68949         SOC_REG_FLAG_64_BITS,
  68950         0,
  68951         5,
  68952         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_HIr_fields,
  68953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68954         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68955         -1,
  68956         -1,
  68957     },
  68958 #endif /* chips */
  68959 
  68960 #if defined(BCM_53570_A0)
  68961     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_LOr */
  68962         soc_block_list[5],
  68963         soc_portreg,
  68964         1,
  68965         0,
  68966         0x40004400,
  68967         SOC_REG_FLAG_64_BITS,
  68968         0,
  68969         4,
  68970         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_LOr_fields,
  68971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68972         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68973         -1,
  68974         -1,
  68975     },
  68976 #endif /* chips */
  68977 
  68978 #if defined(BCM_53570_B0)
  68979     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_LO_BCM53570_B0r */
  68980         soc_block_list[5],
  68981         soc_portreg,
  68982         1,
  68983         0,
  68984         0x40004800,
  68985         SOC_REG_FLAG_64_BITS,
  68986         0,
  68987         4,
  68988         soc_ILOCAL_SW_DISABLE_DEFAULT_PBM_LOr_fields,
  68989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68990         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  68991         -1,
  68992         -1,
  68993     },
  68994 #endif /* chips */
  68995 
  68996 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  68997     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  68998     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  68999     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROLr */
  69000         soc_block_list[5],
  69001         soc_genreg,
  69002         1,
  69003         0,
  69004         0xe080285,
  69005         0,
  69006         0,
  69007         1,
  69008         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  69009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69010         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69011         -1,
  69012         -1,
  69013     },
  69014 #endif /* chips */
  69015 
  69016 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  69017     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROL_BCM56260_A0r */
  69018         soc_block_list[5],
  69019         soc_genreg,
  69020         1,
  69021         0,
  69022         0x3e015500,
  69023         0,
  69024         0,
  69025         1,
  69026         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  69027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69028         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69029         -1,
  69030         -1,
  69031     },
  69032 #endif /* chips */
  69033 
  69034 #if defined(BCM_56270_A0)
  69035     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROL_BCM56270_A0r */
  69036         soc_block_list[5],
  69037         soc_genreg,
  69038         1,
  69039         0,
  69040         0x3e014500,
  69041         0,
  69042         0,
  69043         1,
  69044         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  69045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69046         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69047         -1,
  69048         -1,
  69049     },
  69050 #endif /* chips */
  69051 
  69052 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69053     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROL_BCM56440_A0r */
  69054         soc_block_list[5],
  69055         soc_genreg,
  69056         1,
  69057         0,
  69058         0xf080d54,
  69059         0,
  69060         0,
  69061         1,
  69062         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  69063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69064         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69065         -1,
  69066         -1,
  69067     },
  69068 #endif /* chips */
  69069 
  69070 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69071     defined(BCM_56450_B1)
  69072     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROL_BCM56450_A0r */
  69073         soc_block_list[5],
  69074         soc_genreg,
  69075         1,
  69076         0,
  69077         0x3e015400,
  69078         0,
  69079         0,
  69080         1,
  69081         soc_FT_CNTR_SER_CONTROLr_fields,
  69082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69084         -1,
  69085         -1,
  69086     },
  69087 #endif /* chips */
  69088 
  69089 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  69090     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROL_BCM56840_A0r */
  69091         soc_block_list[5],
  69092         soc_genreg,
  69093         1,
  69094         0,
  69095         0xf080d55,
  69096         0,
  69097         0,
  69098         1,
  69099         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  69100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69101         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69102         -1,
  69103         -1,
  69104     },
  69105 #endif /* chips */
  69106 
  69107 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  69108     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  69109     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  69110     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_INTRr */
  69111         soc_block_list[5],
  69112         soc_genreg,
  69113         1,
  69114         0,
  69115         0xe080286,
  69116         0,
  69117         0,
  69118         3,
  69119         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  69120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69121         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69122         -1,
  69123         -1,
  69124     },
  69125 #endif /* chips */
  69126 
  69127 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69128     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_INTR_BCM56440_A0r */
  69129         soc_block_list[5],
  69130         soc_genreg,
  69131         1,
  69132         0,
  69133         0xf080d55,
  69134         0,
  69135         0,
  69136         3,
  69137         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  69138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69139         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69140         -1,
  69141         -1,
  69142     },
  69143 #endif /* chips */
  69144 
  69145 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69146     defined(BCM_56450_B1)
  69147     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_INTR_BCM56450_A0r */
  69148         soc_block_list[5],
  69149         soc_genreg,
  69150         1,
  69151         0,
  69152         0x3e015500,
  69153         0,
  69154         0,
  69155         3,
  69156         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  69157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69159         -1,
  69160         -1,
  69161     },
  69162 #endif /* chips */
  69163 
  69164 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  69165     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_INTR_BCM56840_A0r */
  69166         soc_block_list[5],
  69167         soc_genreg,
  69168         1,
  69169         0,
  69170         0xf080d56,
  69171         0,
  69172         0,
  69173         3,
  69174         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  69175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69176         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69177         -1,
  69178         -1,
  69179     },
  69180 #endif /* chips */
  69181 
  69182 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  69183     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  69184     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  69185     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_NACKr */
  69186         soc_block_list[5],
  69187         soc_genreg,
  69188         1,
  69189         0,
  69190         0xe080287,
  69191         0,
  69192         0,
  69193         3,
  69194         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  69195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69196         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69197         -1,
  69198         -1,
  69199     },
  69200 #endif /* chips */
  69201 
  69202 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69203     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_NACK_BCM56440_A0r */
  69204         soc_block_list[5],
  69205         soc_genreg,
  69206         1,
  69207         0,
  69208         0xf080d56,
  69209         0,
  69210         0,
  69211         3,
  69212         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  69213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69214         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69215         -1,
  69216         -1,
  69217     },
  69218 #endif /* chips */
  69219 
  69220 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69221     defined(BCM_56450_B1)
  69222     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_NACK_BCM56450_A0r */
  69223         soc_block_list[5],
  69224         soc_genreg,
  69225         1,
  69226         0,
  69227         0x3e015600,
  69228         0,
  69229         0,
  69230         3,
  69231         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  69232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69233         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69234         -1,
  69235         -1,
  69236     },
  69237 #endif /* chips */
  69238 
  69239 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  69240     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_NACK_BCM56840_A0r */
  69241         soc_block_list[5],
  69242         soc_genreg,
  69243         1,
  69244         0,
  69245         0xf080d57,
  69246         0,
  69247         0,
  69248         3,
  69249         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  69250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69252         -1,
  69253         -1,
  69254     },
  69255 #endif /* chips */
  69256 
  69257 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  69258     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  69259     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  69260     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROLr */
  69261         soc_block_list[5],
  69262         soc_genreg,
  69263         1,
  69264         0,
  69265         0xe080282,
  69266         0,
  69267         0,
  69268         1,
  69269         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  69270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69271         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69272         -1,
  69273         -1,
  69274     },
  69275 #endif /* chips */
  69276 
  69277 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  69278     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROL_BCM56260_A0r */
  69279         soc_block_list[5],
  69280         soc_genreg,
  69281         1,
  69282         0,
  69283         0x3e015200,
  69284         0,
  69285         0,
  69286         1,
  69287         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  69288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69289         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69290         -1,
  69291         -1,
  69292     },
  69293 #endif /* chips */
  69294 
  69295 #if defined(BCM_56270_A0)
  69296     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROL_BCM56270_A0r */
  69297         soc_block_list[5],
  69298         soc_genreg,
  69299         1,
  69300         0,
  69301         0x3e014200,
  69302         0,
  69303         0,
  69304         1,
  69305         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  69306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69308         -1,
  69309         -1,
  69310     },
  69311 #endif /* chips */
  69312 
  69313 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69314     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROL_BCM56440_A0r */
  69315         soc_block_list[5],
  69316         soc_genreg,
  69317         1,
  69318         0,
  69319         0xf080d51,
  69320         0,
  69321         0,
  69322         1,
  69323         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  69324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69326         -1,
  69327         -1,
  69328     },
  69329 #endif /* chips */
  69330 
  69331 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69332     defined(BCM_56450_B1)
  69333     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROL_BCM56450_A0r */
  69334         soc_block_list[5],
  69335         soc_genreg,
  69336         1,
  69337         0,
  69338         0x3e015100,
  69339         0,
  69340         0,
  69341         1,
  69342         soc_FT_CNTR_SER_CONTROLr_fields,
  69343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69345         -1,
  69346         -1,
  69347     },
  69348 #endif /* chips */
  69349 
  69350 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  69351     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROL_BCM56840_A0r */
  69352         soc_block_list[5],
  69353         soc_genreg,
  69354         1,
  69355         0,
  69356         0xf080d52,
  69357         0,
  69358         0,
  69359         1,
  69360         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  69361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69362         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69363         -1,
  69364         -1,
  69365     },
  69366 #endif /* chips */
  69367 
  69368 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  69369     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  69370     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  69371     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_INTRr */
  69372         soc_block_list[5],
  69373         soc_genreg,
  69374         1,
  69375         0,
  69376         0xe080283,
  69377         0,
  69378         0,
  69379         3,
  69380         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  69381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69382         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69383         -1,
  69384         -1,
  69385     },
  69386 #endif /* chips */
  69387 
  69388 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69389     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_INTR_BCM56440_A0r */
  69390         soc_block_list[5],
  69391         soc_genreg,
  69392         1,
  69393         0,
  69394         0xf080d52,
  69395         0,
  69396         0,
  69397         3,
  69398         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  69399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69400         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69401         -1,
  69402         -1,
  69403     },
  69404 #endif /* chips */
  69405 
  69406 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69407     defined(BCM_56450_B1)
  69408     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_INTR_BCM56450_A0r */
  69409         soc_block_list[5],
  69410         soc_genreg,
  69411         1,
  69412         0,
  69413         0x3e015200,
  69414         0,
  69415         0,
  69416         3,
  69417         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  69418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69419         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69420         -1,
  69421         -1,
  69422     },
  69423 #endif /* chips */
  69424 
  69425 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  69426     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_INTR_BCM56840_A0r */
  69427         soc_block_list[5],
  69428         soc_genreg,
  69429         1,
  69430         0,
  69431         0xf080d53,
  69432         0,
  69433         0,
  69434         3,
  69435         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  69436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69438         -1,
  69439         -1,
  69440     },
  69441 #endif /* chips */
  69442 
  69443 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  69444     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  69445     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  69446     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_NACKr */
  69447         soc_block_list[5],
  69448         soc_genreg,
  69449         1,
  69450         0,
  69451         0xe080284,
  69452         0,
  69453         0,
  69454         3,
  69455         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  69456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69457         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69458         -1,
  69459         -1,
  69460     },
  69461 #endif /* chips */
  69462 
  69463 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69464     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_NACK_BCM56440_A0r */
  69465         soc_block_list[5],
  69466         soc_genreg,
  69467         1,
  69468         0,
  69469         0xf080d53,
  69470         0,
  69471         0,
  69472         3,
  69473         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  69474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69475         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69476         -1,
  69477         -1,
  69478     },
  69479 #endif /* chips */
  69480 
  69481 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69482     defined(BCM_56450_B1)
  69483     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_NACK_BCM56450_A0r */
  69484         soc_block_list[5],
  69485         soc_genreg,
  69486         1,
  69487         0,
  69488         0x3e015300,
  69489         0,
  69490         0,
  69491         3,
  69492         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  69493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69494         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69495         -1,
  69496         -1,
  69497     },
  69498 #endif /* chips */
  69499 
  69500 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  69501     { /* SOC_REG_INT_LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_NACK_BCM56840_A0r */
  69502         soc_block_list[5],
  69503         soc_genreg,
  69504         1,
  69505         0,
  69506         0xf080d54,
  69507         0,
  69508         0,
  69509         3,
  69510         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  69511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69512         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69513         -1,
  69514         -1,
  69515     },
  69516 #endif /* chips */
  69517 
  69518 #if defined(BCM_56150_A0)
  69519     { /* SOC_REG_INT_LOG_TO_PHY_PORT_MAPPINGr */
  69520         soc_block_list[4],
  69521         soc_portreg,
  69522         1,
  69523         0,
  69524         0x86000,
  69525         0,
  69526         0,
  69527         1,
  69528         soc_LOG_TO_PHY_PORT_MAPPINGr_fields,
  69529         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  69530         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  69531         -1,
  69532         79,
  69533     },
  69534 #endif /* chips */
  69535 
  69536 #if defined(BCM_53400_A0)
  69537     { /* SOC_REG_INT_LOG_TO_PHY_PORT_MAPPING_BCM53400_A0r */
  69538         soc_block_list[4],
  69539         soc_portreg,
  69540         1,
  69541         0,
  69542         0x86000,
  69543         0,
  69544         0,
  69545         1,
  69546         soc_LOG_TO_PHY_PORT_MAPPING_BCM53400_A0r_fields,
  69547         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  69548         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  69549         -1,
  69550         79,
  69551     },
  69552 #endif /* chips */
  69553 
  69554 #if defined(BCM_53540_A0)
  69555     { /* SOC_REG_INT_LOG_TO_PHY_PORT_MAPPING_BCM53540_A0r */
  69556         soc_block_list[4],
  69557         soc_portreg,
  69558         1,
  69559         0,
  69560         0x5e000,
  69561         0,
  69562         0,
  69563         1,
  69564         soc_LOG_TO_PHY_PORT_MAPPING_BCM53540_A0r_fields,
  69565         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  69566         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  69567         -1,
  69568         91,
  69569     },
  69570 #endif /* chips */
  69571 
  69572 #if defined(BCM_56160_A0)
  69573     { /* SOC_REG_INT_LOG_TO_PHY_PORT_MAPPING_BCM56160_A0r */
  69574         soc_block_list[4],
  69575         soc_portreg,
  69576         1,
  69577         0,
  69578         0x86000,
  69579         0,
  69580         0,
  69581         1,
  69582         soc_LOG_TO_PHY_PORT_MAPPING_BCM53400_A0r_fields,
  69583         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  69584         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  69585         -1,
  69586         91,
  69587     },
  69588 #endif /* chips */
  69589 
  69590 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69591     { /* SOC_REG_INT_LOPSTHr */
  69592         soc_block_list[81],
  69593         soc_genreg,
  69594         1,
  69595         0,
  69596         0x80940,
  69597         0,
  69598         0,
  69599         2,
  69600         soc_LOPSTHr_fields,
  69601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69602         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69603         -1,
  69604         -1,
  69605     },
  69606 #endif /* chips */
  69607 
  69608 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  69609     { /* SOC_REG_INT_LPM_LOG_TO_PHY_BANK_MAPr */
  69610         soc_block_list[5],
  69611         soc_genreg,
  69612         1,
  69613         0,
  69614         0x3a000700,
  69615         0,
  69616         0,
  69617         1,
  69618         soc_ISS_LOG_TO_PHY_BANK_MAP_2_BCM56560_A0r_fields,
  69619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69620         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69621         -1,
  69622         -1,
  69623     },
  69624 #endif /* chips */
  69625 
  69626 #if defined(BCM_56640_A0)
  69627     { /* SOC_REG_INT_LPM_MEMORY_DBGCTRLr */
  69628         soc_block_list[5],
  69629         soc_genreg,
  69630         1,
  69631         0,
  69632         0x22010e00,
  69633         0,
  69634         0,
  69635         6,
  69636         soc_LPM_MEMORY_DBGCTRLr_fields,
  69637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69638         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69639         -1,
  69640         -1,
  69641     },
  69642 #endif /* chips */
  69643 
  69644 #if defined(BCM_56340_A0)
  69645     { /* SOC_REG_INT_LPM_MEMORY_DBGCTRL_BCM56340_A0r */
  69646         soc_block_list[5],
  69647         soc_genreg,
  69648         1,
  69649         0,
  69650         0x22012500,
  69651         0,
  69652         0,
  69653         6,
  69654         soc_LPM_MEMORY_DBGCTRLr_fields,
  69655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69656         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69657         -1,
  69658         -1,
  69659     },
  69660 #endif /* chips */
  69661 
  69662 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  69663     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  69664     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  69665     { /* SOC_REG_INT_LPORT_ECC_CONTROLr */
  69666         soc_block_list[5],
  69667         soc_genreg,
  69668         1,
  69669         0,
  69670         0x208012e,
  69671         0,
  69672         0,
  69673         1,
  69674         soc_EGR_INITBUF_ECC_CONTROLr_fields,
  69675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69676         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69677         -1,
  69678         -1,
  69679     },
  69680 #endif /* chips */
  69681 
  69682 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  69683     defined(BCM_56270_A0)
  69684     { /* SOC_REG_INT_LPORT_ECC_CONTROL_BCM56260_A0r */
  69685         soc_block_list[5],
  69686         soc_genreg,
  69687         1,
  69688         0,
  69689         0xa012500,
  69690         0,
  69691         0,
  69692         2,
  69693         soc_EGR_MASK_ECC_CONTROLr_fields,
  69694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69695         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69696         -1,
  69697         -1,
  69698     },
  69699 #endif /* chips */
  69700 
  69701 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69702     defined(BCM_56450_B1)
  69703     { /* SOC_REG_INT_LPORT_ECC_CONTROL_BCM56450_A0r */
  69704         soc_block_list[5],
  69705         soc_genreg,
  69706         1,
  69707         0,
  69708         0xa011b00,
  69709         0,
  69710         0,
  69711         1,
  69712         soc_IARB_HDR_ECC_CONTROL_BCM56450_A0r_fields,
  69713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69714         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69715         -1,
  69716         -1,
  69717     },
  69718 #endif /* chips */
  69719 
  69720 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  69721     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  69722     { /* SOC_REG_INT_LPORT_ECC_CONTROL_BCM56840_A0r */
  69723         soc_block_list[5],
  69724         soc_genreg,
  69725         1,
  69726         0,
  69727         0x2080d1b,
  69728         0,
  69729         0,
  69730         1,
  69731         soc_IARB_HDR_ECC_CONTROLr_fields,
  69732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69734         -1,
  69735         -1,
  69736     },
  69737 #endif /* chips */
  69738 
  69739 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  69740     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  69741     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  69742     { /* SOC_REG_INT_LPORT_ECC_STATUS_INTRr */
  69743         soc_block_list[5],
  69744         soc_genreg,
  69745         1,
  69746         0,
  69747         0x208012f,
  69748         0,
  69749         0,
  69750         4,
  69751         soc_IARB_HDR_ECC_STATUS_INTRr_fields,
  69752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69753         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  69754         -1,
  69755         -1,
  69756     },
  69757 #endif /* chips */
  69758 
  69759 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69760     defined(BCM_56450_B1)
  69761     { /* SOC_REG_INT_LPORT_ECC_STATUS_INTR_BCM56450_A0r */
  69762         soc_block_list[5],
  69763         soc_genreg,
  69764         1,
  69765         0,
  69766         0xa011c00,
  69767         0,
  69768         0,
  69769         4,
  69770         soc_PORT_TABLE_ECC_STATUS_NACKr_fields,
  69771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69773         -1,
  69774         -1,
  69775     },
  69776 #endif /* chips */
  69777 
  69778 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  69779     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  69780     { /* SOC_REG_INT_LPORT_ECC_STATUS_INTR_BCM56840_A0r */
  69781         soc_block_list[5],
  69782         soc_genreg,
  69783         1,
  69784         0,
  69785         0x2080d1c,
  69786         0,
  69787         0,
  69788         4,
  69789         soc_IARB_HDR_ECC_STATUS_INTR_BCM56840_A0r_fields,
  69790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69792         -1,
  69793         -1,
  69794     },
  69795 #endif /* chips */
  69796 
  69797 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  69798     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  69799     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  69800     { /* SOC_REG_INT_LPORT_ECC_STATUS_NACKr */
  69801         soc_block_list[5],
  69802         soc_genreg,
  69803         1,
  69804         0,
  69805         0x2080130,
  69806         0,
  69807         0,
  69808         4,
  69809         soc_IARB_HDR_ECC_STATUS_INTRr_fields,
  69810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69811         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  69812         -1,
  69813         -1,
  69814     },
  69815 #endif /* chips */
  69816 
  69817 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69818     defined(BCM_56450_B1)
  69819     { /* SOC_REG_INT_LPORT_ECC_STATUS_NACK_BCM56450_A0r */
  69820         soc_block_list[5],
  69821         soc_genreg,
  69822         1,
  69823         0,
  69824         0xa011d00,
  69825         0,
  69826         0,
  69827         4,
  69828         soc_PORT_TABLE_ECC_STATUS_NACKr_fields,
  69829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69830         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69831         -1,
  69832         -1,
  69833     },
  69834 #endif /* chips */
  69835 
  69836 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  69837     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  69838     { /* SOC_REG_INT_LPORT_ECC_STATUS_NACK_BCM56840_A0r */
  69839         soc_block_list[5],
  69840         soc_genreg,
  69841         1,
  69842         0,
  69843         0x2080d1d,
  69844         0,
  69845         0,
  69846         4,
  69847         soc_IARB_HDR_ECC_STATUS_INTR_BCM56840_A0r_fields,
  69848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69850         -1,
  69851         -1,
  69852     },
  69853 #endif /* chips */
  69854 
  69855 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  69856     { /* SOC_REG_INT_LPORT_FLEX_COUNTER_STRENGTHr */
  69857         soc_block_list[5],
  69858         soc_genreg,
  69859         1,
  69860         0,
  69861         0xa00a900,
  69862         0,
  69863         0,
  69864         1,
  69865         soc_L2_ENTRY_FLEX_COUNTER_STRENGTHr_fields,
  69866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69867         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  69868         -1,
  69869         -1,
  69870     },
  69871 #endif /* chips */
  69872 
  69873 #if defined(BCM_53400_A0)
  69874     { /* SOC_REG_INT_LPORT_TABLE_ECC_CONTROLr */
  69875         soc_block_list[5],
  69876         soc_genreg,
  69877         1,
  69878         0,
  69879         0xa011000,
  69880         0,
  69881         0,
  69882         1,
  69883         soc_EGR_INITBUF_ECC_CONTROL_BCM53400_A0r_fields,
  69884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69885         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69886         -1,
  69887         -1,
  69888     },
  69889 #endif /* chips */
  69890 
  69891 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  69892     { /* SOC_REG_INT_LPORT_TABLE_ECC_CONTROL_BCM53570_A0r */
  69893         soc_block_list[5],
  69894         soc_genreg,
  69895         1,
  69896         0,
  69897         0xa011500,
  69898         0,
  69899         0,
  69900         1,
  69901         soc_EGR_INITBUF_ECC_CONTROL_BCM53400_A0r_fields,
  69902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69903         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69904         -1,
  69905         -1,
  69906     },
  69907 #endif /* chips */
  69908 
  69909 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  69910     { /* SOC_REG_INT_LPORT_TABLE_ECC_CONTROL_BCM56160_A0r */
  69911         soc_block_list[5],
  69912         soc_genreg,
  69913         1,
  69914         0,
  69915         0xa011300,
  69916         0,
  69917         0,
  69918         1,
  69919         soc_EGR_INITBUF_ECC_CONTROL_BCM53400_A0r_fields,
  69920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69921         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69922         -1,
  69923         -1,
  69924     },
  69925 #endif /* chips */
  69926 
  69927 #if defined(BCM_53400_A0)
  69928     { /* SOC_REG_INT_LPORT_TABLE_ECC_STATUS_INTRr */
  69929         soc_block_list[5],
  69930         soc_genreg,
  69931         1,
  69932         0,
  69933         0xa011100,
  69934         0,
  69935         0,
  69936         4,
  69937         soc_LPORT_TABLE_ECC_STATUS_INTRr_fields,
  69938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69939         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69940         -1,
  69941         -1,
  69942     },
  69943 #endif /* chips */
  69944 
  69945 #if defined(BCM_53540_A0)
  69946     { /* SOC_REG_INT_LPORT_TABLE_ECC_STATUS_INTR_BCM53540_A0r */
  69947         soc_block_list[5],
  69948         soc_genreg,
  69949         1,
  69950         0,
  69951         0xa011400,
  69952         0,
  69953         0,
  69954         4,
  69955         soc_SR_MAC_PROXY_PROFILE_ECC_STATUS_INTRr_fields,
  69956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69957         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69958         -1,
  69959         -1,
  69960     },
  69961 #endif /* chips */
  69962 
  69963 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  69964     { /* SOC_REG_INT_LPORT_TABLE_ECC_STATUS_INTR_BCM53570_A0r */
  69965         soc_block_list[5],
  69966         soc_genreg,
  69967         1,
  69968         0,
  69969         0xa011600,
  69970         0,
  69971         0,
  69972         4,
  69973         soc_LPORT_TABLE_ECC_STATUS_INTR_BCM53570_A0r_fields,
  69974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69975         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  69976         -1,
  69977         -1,
  69978     },
  69979 #endif /* chips */
  69980 
  69981 #if defined(BCM_56160_A0)
  69982     { /* SOC_REG_INT_LPORT_TABLE_ECC_STATUS_INTR_BCM56160_A0r */
  69983         soc_block_list[5],
  69984         soc_genreg,
  69985         1,
  69986         0,
  69987         0xa011400,
  69988         0,
  69989         0,
  69990         4,
  69991         soc_LPORT_TABLE_ECC_STATUS_INTRr_fields,
  69992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69993         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  69994         -1,
  69995         -1,
  69996     },
  69997 #endif /* chips */
  69998 
  69999 #if defined(BCM_53400_A0)
  70000     { /* SOC_REG_INT_LPORT_TABLE_PARITY_STATUSr */
  70001         soc_block_list[5],
  70002         soc_genreg,
  70003         1,
  70004         0,
  70005         0xa011200,
  70006         0,
  70007         0,
  70008         3,
  70009         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUSr_fields,
  70010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70011         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  70012         -1,
  70013         -1,
  70014     },
  70015 #endif /* chips */
  70016 
  70017 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  70018     { /* SOC_REG_INT_LPORT_TABLE_PARITY_STATUS_BCM53570_A0r */
  70019         soc_block_list[5],
  70020         soc_genreg,
  70021         1,
  70022         0,
  70023         0xa011700,
  70024         0,
  70025         0,
  70026         3,
  70027         soc_EGR_XP0_DBITS_PARITY_STATUSr_fields,
  70028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70029         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  70030         -1,
  70031         -1,
  70032     },
  70033 #endif /* chips */
  70034 
  70035 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  70036     { /* SOC_REG_INT_LPORT_TABLE_PARITY_STATUS_BCM56160_A0r */
  70037         soc_block_list[5],
  70038         soc_genreg,
  70039         1,
  70040         0,
  70041         0xa011500,
  70042         0,
  70043         0,
  70044         3,
  70045         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUSr_fields,
  70046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70047         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  70048         -1,
  70049         -1,
  70050     },
  70051 #endif /* chips */
  70052 
  70053 #if defined(BCM_56504_A0) || defined(BCM_56504_B0)
  70054     { /* SOC_REG_INT_LWMCOSCELLSETLIMITr */
  70055         soc_block_list[4],
  70056         soc_portreg,
  70057         8,
  70058         0,
  70059         0x30,
  70060         SOC_REG_FLAG_ARRAY,
  70061         0,
  70062         2,
  70063         soc_LWMCOSCELLSETLIMITr_fields,
  70064         SOC_RESET_VAL_DEC(0x00004100, 0x00000000)
  70065         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70066         -1,
  70067         -1,
  70068     },
  70069 #endif /* chips */
  70070 
  70071 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  70072     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM53314_A0r */
  70073         soc_block_list[4],
  70074         soc_portreg,
  70075         4,
  70076         0,
  70077         0x3c,
  70078         SOC_REG_FLAG_ARRAY,
  70079         0,
  70080         2,
  70081         soc_LWMCOSCELLSETLIMIT_BCM53314_A0r_fields,
  70082         SOC_RESET_VAL_DEC(0x0000c00c, 0x00000000)
  70083         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  70084         -1,
  70085         -1,
  70086     },
  70087 #endif /* chips */
  70088 
  70089 #if defined(BCM_53400_A0)
  70090     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM53400_A0r */
  70091         soc_block_list[4],
  70092         soc_portreg,
  70093         8,
  70094         0,
  70095         0xcd00,
  70096         SOC_REG_FLAG_ARRAY,
  70097         0,
  70098         2,
  70099         soc_LWMCOSCELLSETLIMIT_BCM53400_A0r_fields,
  70100         SOC_RESET_VAL_DEC(0x00044020, 0x00000000)
  70101         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  70102         -1,
  70103         79,
  70104     },
  70105 #endif /* chips */
  70106 
  70107 #if defined(BCM_53540_A0)
  70108     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM53540_A0r */
  70109         soc_block_list[4],
  70110         soc_portreg,
  70111         8,
  70112         0,
  70113         0xf000,
  70114         SOC_REG_FLAG_ARRAY,
  70115         0,
  70116         2,
  70117         soc_LWMCOSCELLSETLIMIT_BCM53540_A0r_fields,
  70118         SOC_RESET_VAL_DEC(0x0000a00f, 0x00000000)
  70119         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  70120         -1,
  70121         91,
  70122     },
  70123 #endif /* chips */
  70124 
  70125 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  70126     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM53570_A0r */
  70127         soc_block_list[4],
  70128         soc_portreg,
  70129         8,
  70130         0,
  70131         0xf800,
  70132         SOC_REG_FLAG_ARRAY,
  70133         0,
  70134         2,
  70135         soc_LWMCOSCELLSETLIMIT_BCM53570_A0r_fields,
  70136         SOC_RESET_VAL_DEC(0x00088020, 0x00000000)
  70137         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  70138         -1,
  70139         102,
  70140     },
  70141 #endif /* chips */
  70142 
  70143 #if defined(BCM_56142_A0)
  70144     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM56142_A0r */
  70145         soc_block_list[4],
  70146         soc_portreg,
  70147         8,
  70148         0,
  70149         0xcd,
  70150         SOC_REG_FLAG_ARRAY,
  70151         0,
  70152         2,
  70153         soc_LWMCOSCELLSETLIMIT_BCM56224_A0r_fields,
  70154         SOC_RESET_VAL_DEC(0x00044020, 0x00000000)
  70155         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  70156         -1,
  70157         -1,
  70158     },
  70159 #endif /* chips */
  70160 
  70161 #if defined(BCM_56150_A0)
  70162     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM56150_A0r */
  70163         soc_block_list[4],
  70164         soc_portreg,
  70165         8,
  70166         0,
  70167         0xcd00,
  70168         SOC_REG_FLAG_ARRAY,
  70169         0,
  70170         2,
  70171         soc_LWMCOSCELLSETLIMIT_BCM56150_A0r_fields,
  70172         SOC_RESET_VAL_DEC(0x00044020, 0x00000000)
  70173         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  70174         -1,
  70175         79,
  70176     },
  70177 #endif /* chips */
  70178 
  70179 #if defined(BCM_56160_A0)
  70180     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM56160_A0r */
  70181         soc_block_list[4],
  70182         soc_portreg,
  70183         8,
  70184         0,
  70185         0xcd00,
  70186         SOC_REG_FLAG_ARRAY,
  70187         0,
  70188         2,
  70189         soc_LWMCOSCELLSETLIMIT_BCM53400_A0r_fields,
  70190         SOC_RESET_VAL_DEC(0x00044020, 0x00000000)
  70191         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  70192         -1,
  70193         91,
  70194     },
  70195 #endif /* chips */
  70196 
  70197 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  70198     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM56224_A0r */
  70199         soc_block_list[4],
  70200         soc_portreg,
  70201         8,
  70202         0,
  70203         0x3c,
  70204         SOC_REG_FLAG_ARRAY,
  70205         0,
  70206         2,
  70207         soc_LWMCOSCELLSETLIMIT_BCM56224_A0r_fields,
  70208         SOC_RESET_VAL_DEC(0x00044020, 0x00000000)
  70209         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  70210         -1,
  70211         -1,
  70212     },
  70213 #endif /* chips */
  70214 
  70215 #if defined(BCM_56314_A0)
  70216     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM56314_A0r */
  70217         soc_block_list[4],
  70218         soc_portreg,
  70219         8,
  70220         0,
  70221         0x30,
  70222         SOC_REG_FLAG_ARRAY,
  70223         0,
  70224         2,
  70225         soc_LWMCOSCELLSETLIMIT_BCM56314_A0r_fields,
  70226         SOC_RESET_VAL_DEC(0x001c0100, 0x00000000)
  70227         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  70228         -1,
  70229         -1,
  70230     },
  70231 #endif /* chips */
  70232 
  70233 #if defined(BCM_56514_A0)
  70234     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_BCM56514_A0r */
  70235         soc_block_list[4],
  70236         soc_portreg,
  70237         8,
  70238         0,
  70239         0x30,
  70240         SOC_REG_FLAG_ARRAY,
  70241         0,
  70242         2,
  70243         soc_LWMCOSCELLSETLIMIT_BCM56514_A0r_fields,
  70244         SOC_RESET_VAL_DEC(0x00300100, 0x00000000)
  70245         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  70246         -1,
  70247         -1,
  70248     },
  70249 #endif /* chips */
  70250 
  70251 #if defined(BCM_53570_A0)
  70252     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_QLAYERr */
  70253         soc_block_list[4],
  70254         soc_portreg,
  70255         64,
  70256         0,
  70257         0xc0e00,
  70258         SOC_REG_FLAG_ARRAY,
  70259         0,
  70260         2,
  70261         soc_LWMCOSCELLSETLIMIT_BCM53570_A0r_fields,
  70262         SOC_RESET_VAL_DEC(0x00088020, 0x00000000)
  70263         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  70264         -1,
  70265         99,
  70266     },
  70267 #endif /* chips */
  70268 
  70269 #if defined(BCM_53570_B0)
  70270     { /* SOC_REG_INT_LWMCOSCELLSETLIMIT_QLAYER_BCM53570_B0r */
  70271         soc_block_list[4],
  70272         soc_portreg,
  70273         64,
  70274         0,
  70275         0xc1100,
  70276         SOC_REG_FLAG_ARRAY,
  70277         0,
  70278         2,
  70279         soc_LWMCOSCELLSETLIMIT_BCM53570_A0r_fields,
  70280         SOC_RESET_VAL_DEC(0x00088020, 0x00000000)
  70281         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  70282         -1,
  70283         99,
  70284     },
  70285 #endif /* chips */
  70286
	openbcm Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM
	git clone git://git.finwo.net/mirror/broadcom/openbcm
	Log \| Files \| Refs \| README