allregs_k.i - openbcm - Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM

allregs_k.i (340313B)
      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_k.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_88680_A0)
     16     { /* SOC_REG_INT_KAPS_BBS_BB_DEBUGr */
     17         soc_block_list[151],
     18         soc_genreg,
     19         1,
     20         0,
     21         0x10f,
     22         SOC_REG_FLAG_ABOVE_64_BITS |
     23                           SOC_REG_FLAG_RO,
     24         0,
     25         32,
     26         soc_KAPS_BBS_BB_DEBUGr_fields,
     27         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     28         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     29         -1,
     30         -1,
     31     },
     32 #endif /* chips */
     33 
     34 #if defined(BCM_88680_A0)
     35     { /* SOC_REG_INT_KAPS_BBS_BB_GLOBAL_CONFIGr */
     36         soc_block_list[151],
     37         soc_genreg,
     38         8,
     39         0,
     40         0x103,
     41         SOC_REG_FLAG_ARRAY |
     42                           SOC_REG_FLAG_REG_ARRAY,
     43         0,
     44         4,
     45         soc_KAPS_BBS_BB_GLOBAL_CONFIGr_fields,
     46         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     47         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
     48         -1,
     49         -1,
     50     },
     51 #endif /* chips */
     52 
     53 #if defined(BCM_88680_A0)
     54     { /* SOC_REG_INT_KAPS_BBS_BB_INIT_DONEr */
     55         soc_block_list[151],
     56         soc_genreg,
     57         1,
     58         0,
     59         0x115,
     60         SOC_REG_FLAG_RO,
     61         0,
     62         8,
     63         soc_KAPS_BBS_BB_INIT_DONEr_fields,
     64         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     65         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
     66         -1,
     67         -1,
     68     },
     69 #endif /* chips */
     70 
     71 #if defined(BCM_88680_A0)
     72     { /* SOC_REG_INT_KAPS_BBS_BRR_BB_DEBUGr */
     73         soc_block_list[151],
     74         soc_genreg,
     75         4,
     76         0,
     77         0x10b,
     78         SOC_REG_FLAG_ARRAY |
     79                           SOC_REG_FLAG_RO |
     80                           SOC_REG_FLAG_REG_ARRAY,
     81         0,
     82         3,
     83         soc_KAPS_BBS_BRR_BB_DEBUGr_fields,
     84         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     85         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
     86         -1,
     87         -1,
     88     },
     89 #endif /* chips */
     90 
     91 #if defined(BCM_88680_A0)
     92     { /* SOC_REG_INT_KAPS_BBS_ECC_1B_ERR_CNTr */
     93         soc_block_list[151],
     94         soc_genreg,
     95         1,
     96         0,
     97         0x94,
     98         SOC_REG_FLAG_64_BITS |
     99                           SOC_REG_FLAG_RO,
    100         0,
    101         4,
    102         soc_KAPS_BBS_ECC_1B_ERR_CNTr_fields,
    103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    104         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
    105         -1,
    106         -1,
    107     },
    108 #endif /* chips */
    109 
    110 #if defined(BCM_88680_A0)
    111     { /* SOC_REG_INT_KAPS_BBS_ECC_2B_ERR_CNTr */
    112         soc_block_list[151],
    113         soc_genreg,
    114         1,
    115         0,
    116         0x96,
    117         SOC_REG_FLAG_64_BITS |
    118                           SOC_REG_FLAG_RO,
    119         0,
    120         4,
    121         soc_KAPS_BBS_ECC_2B_ERR_CNTr_fields,
    122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    123         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
    124         -1,
    125         -1,
    126     },
    127 #endif /* chips */
    128 
    129 #if defined(BCM_88680_A0)
    130     { /* SOC_REG_INT_KAPS_BBS_ECC_ERR_1B_INITIATEr */
    131         soc_block_list[151],
    132         soc_genreg,
    133         1,
    134         0,
    135         0xa4,
    136         0,
    137         0,
    138         8,
    139         soc_KAPS_BBS_ECC_ERR_1B_INITIATEr_fields,
    140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    141         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    142         -1,
    143         -1,
    144     },
    145 #endif /* chips */
    146 
    147 #if defined(BCM_88680_A0)
    148     { /* SOC_REG_INT_KAPS_BBS_ECC_ERR_1B_MONITOR_MEM_MASKr */
    149         soc_block_list[151],
    150         soc_genreg,
    151         1,
    152         0,
    153         0x9a,
    154         0,
    155         0,
    156         8,
    157         soc_KAPS_BBS_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
    158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    159         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    160         -1,
    161         -1,
    162     },
    163 #endif /* chips */
    164 
    165 #if defined(BCM_88680_A0)
    166     { /* SOC_REG_INT_KAPS_BBS_ECC_ERR_2B_INITIATEr */
    167         soc_block_list[151],
    168         soc_genreg,
    169         1,
    170         0,
    171         0xa6,
    172         0,
    173         0,
    174         8,
    175         soc_KAPS_BBS_ECC_ERR_2B_INITIATEr_fields,
    176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    177         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    178         -1,
    179         -1,
    180     },
    181 #endif /* chips */
    182 
    183 #if defined(BCM_88680_A0)
    184     { /* SOC_REG_INT_KAPS_BBS_ECC_ERR_2B_MONITOR_MEM_MASKr */
    185         soc_block_list[151],
    186         soc_genreg,
    187         1,
    188         0,
    189         0x9c,
    190         0,
    191         0,
    192         8,
    193         soc_KAPS_BBS_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
    194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    195         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    196         -1,
    197         -1,
    198     },
    199 #endif /* chips */
    200 
    201 #if defined(BCM_88680_A0)
    202     { /* SOC_REG_INT_KAPS_BBS_ECC_INTERRUPT_REGISTERr */
    203         soc_block_list[151],
    204         soc_genreg,
    205         1,
    206         0,
    207         0x7,
    208         SOC_REG_FLAG_INTERRUPT,
    209         0,
    210         3,
    211         soc_KAPS_BBS_ECC_INTERRUPT_REGISTERr_fields,
    212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    213         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    214         -1,
    215         -1,
    216     },
    217 #endif /* chips */
    218 
    219 #if defined(BCM_88680_A0)
    220     { /* SOC_REG_INT_KAPS_BBS_ECC_INTERRUPT_REGISTER_MASKr */
    221         soc_block_list[151],
    222         soc_genreg,
    223         1,
    224         0,
    225         0x17,
    226         0,
    227         0,
    228         3,
    229         soc_KAPS_BBS_ECC_INTERRUPT_REGISTER_MASKr_fields,
    230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    231         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    232         -1,
    233         -1,
    234     },
    235 #endif /* chips */
    236 
    237 #if defined(BCM_88680_A0)
    238     { /* SOC_REG_INT_KAPS_BBS_ECC_INTERRUPT_REGISTER_TESTr */
    239         soc_block_list[151],
    240         soc_genreg,
    241         1,
    242         0,
    243         0x1f,
    244         0,
    245         0,
    246         1,
    247         soc_KAPS_BBS_ECC_INTERRUPT_REGISTER_TESTr_fields,
    248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    249         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    250         -1,
    251         -1,
    252     },
    253 #endif /* chips */
    254 
    255 #if defined(BCM_88680_A0)
    256     { /* SOC_REG_INT_KAPS_BBS_ENABLE_DYNAMIC_MEMORY_ACCESSr */
    257         soc_block_list[151],
    258         soc_genreg,
    259         1,
    260         0,
    261         0x84,
    262         0,
    263         0,
    264         1,
    265         soc_KAPS_BBS_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
    266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    267         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    268         -1,
    269         -1,
    270     },
    271 #endif /* chips */
    272 
    273 #if defined(BCM_88680_A0)
    274     { /* SOC_REG_INT_KAPS_BBS_ERROR_INITIATION_DATAr */
    275         soc_block_list[151],
    276         soc_genreg,
    277         1,
    278         0,
    279         0xa3,
    280         0,
    281         0,
    282         1,
    283         soc_KAPS_BBS_ERROR_INITIATION_DATAr_fields,
    284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    285         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    286         -1,
    287         -1,
    288     },
    289 #endif /* chips */
    290 
    291 #if defined(BCM_88680_A0)
    292     { /* SOC_REG_INT_KAPS_BBS_GLOBAL_MEM_OPTIONSr */
    293         soc_block_list[151],
    294         soc_genreg,
    295         1,
    296         0,
    297         0xc0,
    298         0,
    299         0,
    300         4,
    301         soc_KAPS_BBS_GLOBAL_MEM_OPTIONSr_fields,
    302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    303         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    304         -1,
    305         -1,
    306     },
    307 #endif /* chips */
    308 
    309 #if defined(BCM_88680_A0)
    310     { /* SOC_REG_INT_KAPS_BBS_GTIMER_CONFIGURATIONr */
    311         soc_block_list[151],
    312         soc_genreg,
    313         1,
    314         0,
    315         0x88,
    316         0,
    317         0,
    318         3,
    319         soc_KAPS_BBS_GTIMER_CONFIGURATIONr_fields,
    320         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
    321         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    322         -1,
    323         -1,
    324     },
    325 #endif /* chips */
    326 
    327 #if defined(BCM_88680_A0)
    328     { /* SOC_REG_INT_KAPS_BBS_GTIMER_TRIGGERr */
    329         soc_block_list[151],
    330         soc_genreg,
    331         1,
    332         0,
    333         0x89,
    334         SOC_REG_FLAG_RO,
    335         0,
    336         1,
    337         soc_KAPS_BBS_GTIMER_TRIGGERr_fields,
    338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    339         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    340         -1,
    341         -1,
    342     },
    343 #endif /* chips */
    344 
    345 #if defined(BCM_88680_A0)
    346     { /* SOC_REG_INT_KAPS_BBS_INDIRECT_COMMANDr */
    347         soc_block_list[151],
    348         soc_genreg,
    349         1,
    350         0,
    351         0x80,
    352         0,
    353         0,
    354         5,
    355         soc_KAPS_BBS_INDIRECT_COMMANDr_fields,
    356         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
    357         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    358         -1,
    359         -1,
    360     },
    361 #endif /* chips */
    362 
    363 #if defined(BCM_88680_A0)
    364     { /* SOC_REG_INT_KAPS_BBS_INDIRECT_COMMAND_ADDRESSr */
    365         soc_block_list[151],
    366         soc_genreg,
    367         1,
    368         0,
    369         0x81,
    370         0,
    371         0,
    372         2,
    373         soc_KAPS_BBS_INDIRECT_COMMAND_ADDRESSr_fields,
    374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    375         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    376         -1,
    377         -1,
    378     },
    379 #endif /* chips */
    380 
    381 #if defined(BCM_88680_A0)
    382     { /* SOC_REG_INT_KAPS_BBS_INDIRECT_COMMAND_DATA_INCREMENTr */
    383         soc_block_list[151],
    384         soc_genreg,
    385         1,
    386         0,
    387         0x82,
    388         SOC_REG_FLAG_64_BITS,
    389         0,
    390         1,
    391         soc_KAPS_BBS_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
    392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    393         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
    394         -1,
    395         -1,
    396     },
    397 #endif /* chips */
    398 
    399 #if defined(BCM_88680_A0)
    400     { /* SOC_REG_INT_KAPS_BBS_INDIRECT_COMMAND_RD_DATAr */
    401         soc_block_list[151],
    402         soc_genreg,
    403         1,
    404         0,
    405         0x60,
    406         SOC_REG_FLAG_ABOVE_64_BITS |
    407                           SOC_REG_FLAG_RO |
    408                           SOC_REG_FLAG_SIGNAL,
    409         0,
    410         1,
    411         soc_KAPS_BBS_INDIRECT_COMMAND_RD_DATAr_fields,
    412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    413         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    414         -1,
    415         -1,
    416     },
    417 #endif /* chips */
    418 
    419 #if defined(BCM_88680_A0)
    420     { /* SOC_REG_INT_KAPS_BBS_INDIRECT_COMMAND_WIDE_MEMr */
    421         soc_block_list[151],
    422         soc_genreg,
    423         1,
    424         0,
    425         0x41,
    426         0,
    427         0,
    428         1,
    429         soc_KAPS_BBS_INDIRECT_COMMAND_WIDE_MEMr_fields,
    430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    431         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    432         -1,
    433         -1,
    434     },
    435 #endif /* chips */
    436 
    437 #if defined(BCM_88680_A0)
    438     { /* SOC_REG_INT_KAPS_BBS_INDIRECT_COMMAND_WR_DATAr */
    439         soc_block_list[151],
    440         soc_genreg,
    441         1,
    442         0,
    443         0x20,
    444         SOC_REG_FLAG_ABOVE_64_BITS,
    445         0,
    446         1,
    447         soc_KAPS_BBS_INDIRECT_COMMAND_WR_DATAr_fields,
    448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    449         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    450         -1,
    451         -1,
    452     },
    453 #endif /* chips */
    454 
    455 #if defined(BCM_88680_A0)
    456     { /* SOC_REG_INT_KAPS_BBS_INDIRECT_FORCE_BUBBLEr */
    457         soc_block_list[151],
    458         soc_genreg,
    459         1,
    460         0,
    461         0x83,
    462         0,
    463         0,
    464         4,
    465         soc_KAPS_BBS_INDIRECT_FORCE_BUBBLEr_fields,
    466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    467         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
    468         -1,
    469         -1,
    470     },
    471 #endif /* chips */
    472 
    473 #if defined(BCM_88680_A0)
    474     { /* SOC_REG_INT_KAPS_BBS_INDIRECT_WR_MASKr */
    475         soc_block_list[151],
    476         soc_genreg,
    477         1,
    478         0,
    479         0x40,
    480         SOC_REG_FLAG_ABOVE_64_BITS,
    481         0,
    482         1,
    483         soc_KAPS_BBS_INDIRECT_WR_MASKr_fields,
    484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    486         -1,
    487         -1,
    488     },
    489 #endif /* chips */
    490 
    491 #if defined(BCM_88680_A0)
    492     { /* SOC_REG_INT_KAPS_BBS_INTERRUPT_MASK_REGISTERr */
    493         soc_block_list[151],
    494         soc_genreg,
    495         1,
    496         0,
    497         0x10,
    498         0,
    499         0,
    500         2,
    501         soc_KAPS_BBS_INTERRUPT_MASK_REGISTERr_fields,
    502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    503         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    504         -1,
    505         -1,
    506     },
    507 #endif /* chips */
    508 
    509 #if defined(BCM_88680_A0)
    510     { /* SOC_REG_INT_KAPS_BBS_INTERRUPT_REGISTERr */
    511         soc_block_list[151],
    512         soc_genreg,
    513         1,
    514         0,
    515         0,
    516         SOC_REG_FLAG_RO |
    517                           SOC_REG_FLAG_INTERRUPT,
    518         0,
    519         2,
    520         soc_KAPS_BBS_INTERRUPT_REGISTERr_fields,
    521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    522         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    523         -1,
    524         -1,
    525     },
    526 #endif /* chips */
    527 
    528 #if defined(BCM_88680_A0)
    529     { /* SOC_REG_INT_KAPS_BBS_INTERRUPT_REGISTER_TESTr */
    530         soc_block_list[151],
    531         soc_genreg,
    532         1,
    533         0,
    534         0x18,
    535         0,
    536         0,
    537         1,
    538         soc_KAPS_BBS_INTERRUPT_REGISTER_TESTr_fields,
    539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    540         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    541         -1,
    542         -1,
    543     },
    544 #endif /* chips */
    545 
    546 #if defined(BCM_88680_A0)
    547     { /* SOC_REG_INT_KAPS_BBS_KAPS_BB_ERROR_REGISTERr */
    548         soc_block_list[151],
    549         soc_genreg,
    550         1,
    551         0,
    552         0x100,
    553         0,
    554         0,
    555         2,
    556         soc_KAPS_BBS_KAPS_BB_ERROR_REGISTERr_fields,
    557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    558         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    559         -1,
    560         -1,
    561     },
    562 #endif /* chips */
    563 
    564 #if defined(BCM_88680_A0)
    565     { /* SOC_REG_INT_KAPS_BBS_KAPS_BB_ERROR_REGISTER_MASKr */
    566         soc_block_list[151],
    567         soc_genreg,
    568         1,
    569         0,
    570         0x101,
    571         0,
    572         0,
    573         2,
    574         soc_KAPS_BBS_KAPS_BB_ERROR_REGISTER_MASKr_fields,
    575         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
    576         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    577         -1,
    578         -1,
    579     },
    580 #endif /* chips */
    581 
    582 #if defined(BCM_88680_A0)
    583     { /* SOC_REG_INT_KAPS_BBS_KAPS_BB_ERROR_REGISTER_TESTr */
    584         soc_block_list[151],
    585         soc_genreg,
    586         1,
    587         0,
    588         0x102,
    589         0,
    590         0,
    591         1,
    592         soc_KAPS_BBS_KAPS_BB_ERROR_REGISTER_TESTr_fields,
    593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    594         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    595         -1,
    596         -1,
    597     },
    598 #endif /* chips */
    599 
    600 #if defined(BCM_88680_A0)
    601     { /* SOC_REG_INT_KAPS_BBS_PARITY_ERR_CNTr */
    602         soc_block_list[151],
    603         soc_genreg,
    604         1,
    605         0,
    606         0x98,
    607         SOC_REG_FLAG_64_BITS |
    608                           SOC_REG_FLAG_RO,
    609         0,
    610         4,
    611         soc_KAPS_BBS_PARITY_ERR_CNTr_fields,
    612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    613         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
    614         -1,
    615         -1,
    616     },
    617 #endif /* chips */
    618 
    619 #if defined(BCM_88680_A0)
    620     { /* SOC_REG_INT_KAPS_BBS_PAR_ERR_INITIATEr */
    621         soc_block_list[151],
    622         soc_genreg,
    623         1,
    624         0,
    625         0xaa,
    626         0,
    627         0,
    628         1,
    629         soc_KAPS_BBS_PAR_ERR_INITIATEr_fields,
    630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    631         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    632         -1,
    633         -1,
    634     },
    635 #endif /* chips */
    636 
    637 #if defined(BCM_88680_A0)
    638     { /* SOC_REG_INT_KAPS_BBS_PAR_ERR_MEM_MASKr */
    639         soc_block_list[151],
    640         soc_genreg,
    641         1,
    642         0,
    643         0xa0,
    644         0,
    645         0,
    646         1,
    647         soc_KAPS_BBS_PAR_ERR_MEM_MASKr_fields,
    648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    649         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    650         -1,
    651         -1,
    652     },
    653 #endif /* chips */
    654 
    655 #if defined(BCM_88680_A0)
    656     { /* SOC_REG_INT_KAPS_BBS_RESERVED_MIRROR_ADDRr */
    657         soc_block_list[151],
    658         soc_genreg,
    659         1,
    660         0,
    661         0x85,
    662         0,
    663         0,
    664         2,
    665         soc_KAPS_BBS_RESERVED_MIRROR_ADDRr_fields,
    666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    667         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
    668         -1,
    669         -1,
    670     },
    671 #endif /* chips */
    672 
    673 #if defined(BCM_88680_A0)
    674     { /* SOC_REG_INT_KAPS_BBS_RESERVED_MTCDr */
    675         soc_block_list[151],
    676         soc_genreg,
    677         1,
    678         0,
    679         0xae,
    680         0,
    681         0,
    682         6,
    683         soc_KAPS_BBS_RESERVED_MTCDr_fields,
    684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    685         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
    686         -1,
    687         -1,
    688     },
    689 #endif /* chips */
    690 
    691 #if defined(BCM_88680_A0)
    692     { /* SOC_REG_INT_KAPS_BBS_RESERVED_MTCPr */
    693         soc_block_list[151],
    694         soc_genreg,
    695         1,
    696         0,
    697         0xad,
    698         SOC_REG_FLAG_64_BITS,
    699         0,
    700         17,
    701         soc_KAPS_BBS_RESERVED_MTCPr_fields,
    702         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
    703         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
    704         -1,
    705         -1,
    706     },
    707 #endif /* chips */
    708 
    709 #if defined(BCM_88680_A0)
    710     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_0r */
    711         soc_block_list[151],
    712         soc_genreg,
    713         1,
    714         0,
    715         0xb0,
    716         0,
    717         0,
    718         1,
    719         soc_KAPS_BBS_RESERVED_PCMI_0r_fields,
    720         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
    721         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    722         -1,
    723         -1,
    724     },
    725 #endif /* chips */
    726 
    727 #if defined(BCM_88680_A0)
    728     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_1r */
    729         soc_block_list[151],
    730         soc_genreg,
    731         1,
    732         0,
    733         0xb3,
    734         0,
    735         0,
    736         1,
    737         soc_KAPS_BBS_RESERVED_PCMI_1r_fields,
    738         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
    739         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    740         -1,
    741         -1,
    742     },
    743 #endif /* chips */
    744 
    745 #if defined(BCM_88680_A0)
    746     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_2r */
    747         soc_block_list[151],
    748         soc_genreg,
    749         1,
    750         0,
    751         0xb6,
    752         0,
    753         0,
    754         1,
    755         soc_KAPS_BBS_RESERVED_PCMI_2r_fields,
    756         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
    757         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    758         -1,
    759         -1,
    760     },
    761 #endif /* chips */
    762 
    763 #if defined(BCM_88680_A0)
    764     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_3r */
    765         soc_block_list[151],
    766         soc_genreg,
    767         1,
    768         0,
    769         0xb9,
    770         0,
    771         0,
    772         1,
    773         soc_KAPS_BBS_RESERVED_PCMI_3r_fields,
    774         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
    775         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    776         -1,
    777         -1,
    778     },
    779 #endif /* chips */
    780 
    781 #if defined(BCM_88680_A0)
    782     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_4r */
    783         soc_block_list[151],
    784         soc_genreg,
    785         1,
    786         0,
    787         0xbc,
    788         0,
    789         0,
    790         1,
    791         soc_KAPS_BBS_RESERVED_PCMI_4r_fields,
    792         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
    793         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    794         -1,
    795         -1,
    796     },
    797 #endif /* chips */
    798 
    799 #if defined(BCM_88680_A0)
    800     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_0_Sr */
    801         soc_block_list[151],
    802         soc_genreg,
    803         1,
    804         0,
    805         0xb1,
    806         SOC_REG_FLAG_RO,
    807         0,
    808         3,
    809         soc_KAPS_BBS_RESERVED_PCMI_0_Sr_fields,
    810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    811         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    812         -1,
    813         -1,
    814     },
    815 #endif /* chips */
    816 
    817 #if defined(BCM_88680_A0)
    818     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_0_Tr */
    819         soc_block_list[151],
    820         soc_genreg,
    821         1,
    822         0,
    823         0xb2,
    824         0,
    825         0,
    826         2,
    827         soc_KAPS_BBS_RESERVED_PCMI_0_Tr_fields,
    828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    829         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
    830         -1,
    831         -1,
    832     },
    833 #endif /* chips */
    834 
    835 #if defined(BCM_88680_A0)
    836     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_1_Sr */
    837         soc_block_list[151],
    838         soc_genreg,
    839         1,
    840         0,
    841         0xb4,
    842         SOC_REG_FLAG_RO,
    843         0,
    844         3,
    845         soc_KAPS_BBS_RESERVED_PCMI_1_Sr_fields,
    846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    847         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    848         -1,
    849         -1,
    850     },
    851 #endif /* chips */
    852 
    853 #if defined(BCM_88680_A0)
    854     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_1_Tr */
    855         soc_block_list[151],
    856         soc_genreg,
    857         1,
    858         0,
    859         0xb5,
    860         0,
    861         0,
    862         2,
    863         soc_KAPS_BBS_RESERVED_PCMI_1_Tr_fields,
    864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    865         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
    866         -1,
    867         -1,
    868     },
    869 #endif /* chips */
    870 
    871 #if defined(BCM_88680_A0)
    872     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_2_Sr */
    873         soc_block_list[151],
    874         soc_genreg,
    875         1,
    876         0,
    877         0xb7,
    878         SOC_REG_FLAG_RO,
    879         0,
    880         3,
    881         soc_KAPS_BBS_RESERVED_PCMI_2_Sr_fields,
    882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    883         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    884         -1,
    885         -1,
    886     },
    887 #endif /* chips */
    888 
    889 #if defined(BCM_88680_A0)
    890     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_2_Tr */
    891         soc_block_list[151],
    892         soc_genreg,
    893         1,
    894         0,
    895         0xb8,
    896         0,
    897         0,
    898         2,
    899         soc_KAPS_BBS_RESERVED_PCMI_2_Tr_fields,
    900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    901         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
    902         -1,
    903         -1,
    904     },
    905 #endif /* chips */
    906 
    907 #if defined(BCM_88680_A0)
    908     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_3_Sr */
    909         soc_block_list[151],
    910         soc_genreg,
    911         1,
    912         0,
    913         0xba,
    914         SOC_REG_FLAG_RO,
    915         0,
    916         3,
    917         soc_KAPS_BBS_RESERVED_PCMI_3_Sr_fields,
    918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    919         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    920         -1,
    921         -1,
    922     },
    923 #endif /* chips */
    924 
    925 #if defined(BCM_88680_A0)
    926     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_3_Tr */
    927         soc_block_list[151],
    928         soc_genreg,
    929         1,
    930         0,
    931         0xbb,
    932         0,
    933         0,
    934         2,
    935         soc_KAPS_BBS_RESERVED_PCMI_3_Tr_fields,
    936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    937         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
    938         -1,
    939         -1,
    940     },
    941 #endif /* chips */
    942 
    943 #if defined(BCM_88680_A0)
    944     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_4_Sr */
    945         soc_block_list[151],
    946         soc_genreg,
    947         1,
    948         0,
    949         0xbd,
    950         SOC_REG_FLAG_RO,
    951         0,
    952         3,
    953         soc_KAPS_BBS_RESERVED_PCMI_4_Sr_fields,
    954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    956         -1,
    957         -1,
    958     },
    959 #endif /* chips */
    960 
    961 #if defined(BCM_88680_A0)
    962     { /* SOC_REG_INT_KAPS_BBS_RESERVED_PCMI_4_Tr */
    963         soc_block_list[151],
    964         soc_genreg,
    965         1,
    966         0,
    967         0xbe,
    968         0,
    969         0,
    970         2,
    971         soc_KAPS_BBS_RESERVED_PCMI_4_Tr_fields,
    972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    973         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
    974         -1,
    975         -1,
    976     },
    977 #endif /* chips */
    978 
    979 #if defined(BCM_88680_A0)
    980     { /* SOC_REG_INT_KAPS_BBS_RESERVED_SPARE_0r */
    981         soc_block_list[151],
    982         soc_genreg,
    983         1,
    984         0,
    985         0x90,
    986         0,
    987         0,
    988         1,
    989         soc_KAPS_BBS_RESERVED_SPARE_0r_fields,
    990         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    991         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    992         -1,
    993         -1,
    994     },
    995 #endif /* chips */
    996 
    997 #if defined(BCM_88680_A0)
    998     { /* SOC_REG_INT_KAPS_BBS_RESERVED_SPARE_1r */
    999         soc_block_list[151],
   1000         soc_genreg,
   1001         1,
   1002         0,
   1003         0x91,
   1004         0,
   1005         0,
   1006         1,
   1007         soc_KAPS_BBS_RESERVED_SPARE_1r_fields,
   1008         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   1009         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1010         -1,
   1011         -1,
   1012     },
   1013 #endif /* chips */
   1014 
   1015 #if defined(BCM_88680_A0)
   1016     { /* SOC_REG_INT_KAPS_BBS_RESERVED_SPARE_2r */
   1017         soc_block_list[151],
   1018         soc_genreg,
   1019         1,
   1020         0,
   1021         0x92,
   1022         0,
   1023         0,
   1024         1,
   1025         soc_KAPS_BBS_RESERVED_SPARE_2r_fields,
   1026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1028         -1,
   1029         -1,
   1030     },
   1031 #endif /* chips */
   1032 
   1033 #if defined(BCM_88680_A0)
   1034     { /* SOC_REG_INT_KAPS_BBS_RESERVED_SPARE_3r */
   1035         soc_block_list[151],
   1036         soc_genreg,
   1037         1,
   1038         0,
   1039         0x93,
   1040         0,
   1041         0,
   1042         1,
   1043         soc_KAPS_BBS_RESERVED_SPARE_3r_fields,
   1044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1046         -1,
   1047         -1,
   1048     },
   1049 #endif /* chips */
   1050 
   1051 #if defined(BCM_88680_A0)
   1052     { /* SOC_REG_INT_KAPS_BBS_SBUS_BROADCAST_IDr */
   1053         soc_block_list[151],
   1054         soc_genreg,
   1055         1,
   1056         0,
   1057         0x86,
   1058         0,
   1059         0,
   1060         1,
   1061         soc_KAPS_BBS_SBUS_BROADCAST_IDr_fields,
   1062         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
   1063         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   1064         -1,
   1065         -1,
   1066     },
   1067 #endif /* chips */
   1068 
   1069 #if defined(BCM_88680_A0)
   1070     { /* SOC_REG_INT_KAPS_BBS_SBUS_LAST_IN_CHAINr */
   1071         soc_block_list[151],
   1072         soc_genreg,
   1073         1,
   1074         0,
   1075         0x87,
   1076         0,
   1077         0,
   1078         1,
   1079         soc_KAPS_BBS_SBUS_LAST_IN_CHAINr_fields,
   1080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1081         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1082         -1,
   1083         -1,
   1084     },
   1085 #endif /* chips */
   1086 
   1087 #if defined(BCM_88470_A0)
   1088     { /* SOC_REG_INT_KAPS_BB_DEBUGr */
   1089         soc_block_list[73],
   1090         soc_genreg,
   1091         1,
   1092         0,
   1093         0x13a,
   1094         SOC_REG_FLAG_ABOVE_64_BITS |
   1095                           SOC_REG_FLAG_RO,
   1096         0,
   1097         32,
   1098         soc_KAPS_BB_DEBUGr_fields,
   1099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1100         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1101         -1,
   1102         -1,
   1103     },
   1104 #endif /* chips */
   1105 
   1106 #if defined(BCM_88270_A0)
   1107     { /* SOC_REG_INT_KAPS_BB_DEBUG_BCM88270_A0r */
   1108         soc_block_list[73],
   1109         soc_genreg,
   1110         1,
   1111         0,
   1112         0x13a,
   1113         SOC_REG_FLAG_ABOVE_64_BITS |
   1114                           SOC_REG_FLAG_RO,
   1115         0,
   1116         32,
   1117         soc_KAPS_BB_DEBUG_BCM88270_A0r_fields,
   1118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1119         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1120         -1,
   1121         -1,
   1122     },
   1123 #endif /* chips */
   1124 
   1125 #if defined(BCM_88470_B0)
   1126     { /* SOC_REG_INT_KAPS_BB_DEBUG_BCM88470_B0r */
   1127         soc_block_list[73],
   1128         soc_genreg,
   1129         1,
   1130         0,
   1131         0x13a,
   1132         SOC_REG_FLAG_ABOVE_64_BITS |
   1133                           SOC_REG_FLAG_RO,
   1134         0,
   1135         32,
   1136         soc_KAPS_BB_DEBUG_BCM88470_B0r_fields,
   1137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1138         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1139         -1,
   1140         -1,
   1141     },
   1142 #endif /* chips */
   1143 
   1144 #if defined(BCM_88680_A0)
   1145     { /* SOC_REG_INT_KAPS_BB_DEBUG_BCM88680_A0r */
   1146         soc_block_list[73],
   1147         soc_genreg,
   1148         1,
   1149         0,
   1150         0x10f,
   1151         SOC_REG_FLAG_ABOVE_64_BITS |
   1152                           SOC_REG_FLAG_RO,
   1153         0,
   1154         32,
   1155         soc_KAPS_BB_DEBUG_BCM88680_A0r_fields,
   1156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1157         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1158         -1,
   1159         -1,
   1160     },
   1161 #endif /* chips */
   1162 
   1163 #if defined(BCM_88470_A0)
   1164     { /* SOC_REG_INT_KAPS_BB_GLOBAL_CONFIGr */
   1165         soc_block_list[73],
   1166         soc_genreg,
   1167         16,
   1168         0,
   1169         0x128,
   1170         SOC_REG_FLAG_ARRAY |
   1171                           SOC_REG_FLAG_REG_ARRAY,
   1172         0,
   1173         4,
   1174         soc_KAPS_BB_GLOBAL_CONFIGr_fields,
   1175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1176         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   1177         -1,
   1178         -1,
   1179     },
   1180 #endif /* chips */
   1181 
   1182 #if defined(BCM_88270_A0)
   1183     { /* SOC_REG_INT_KAPS_BB_GLOBAL_CONFIG_BCM88270_A0r */
   1184         soc_block_list[73],
   1185         soc_genreg,
   1186         16,
   1187         0,
   1188         0x128,
   1189         SOC_REG_FLAG_ARRAY |
   1190                           SOC_REG_FLAG_REG_ARRAY,
   1191         0,
   1192         4,
   1193         soc_KAPS_BB_GLOBAL_CONFIG_BCM88270_A0r_fields,
   1194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1195         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   1196         -1,
   1197         -1,
   1198     },
   1199 #endif /* chips */
   1200 
   1201 #if defined(BCM_88470_B0)
   1202     { /* SOC_REG_INT_KAPS_BB_GLOBAL_CONFIG_BCM88470_B0r */
   1203         soc_block_list[73],
   1204         soc_genreg,
   1205         16,
   1206         0,
   1207         0x128,
   1208         SOC_REG_FLAG_ARRAY |
   1209                           SOC_REG_FLAG_REG_ARRAY,
   1210         0,
   1211         4,
   1212         soc_KAPS_BB_GLOBAL_CONFIG_BCM88470_B0r_fields,
   1213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1214         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   1215         -1,
   1216         -1,
   1217     },
   1218 #endif /* chips */
   1219 
   1220 #if defined(BCM_88680_A0)
   1221     { /* SOC_REG_INT_KAPS_BB_GLOBAL_CONFIG_BCM88680_A0r */
   1222         soc_block_list[73],
   1223         soc_genreg,
   1224         8,
   1225         0,
   1226         0x103,
   1227         SOC_REG_FLAG_ARRAY |
   1228                           SOC_REG_FLAG_REG_ARRAY,
   1229         0,
   1230         4,
   1231         soc_KAPS_BB_GLOBAL_CONFIG_BCM88680_A0r_fields,
   1232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1233         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1234         -1,
   1235         -1,
   1236     },
   1237 #endif /* chips */
   1238 
   1239 #if defined(BCM_88690_A0)
   1240     { /* SOC_REG_INT_KAPS_BB_GLOBAL_CONFIG_BCM88690_A0r */
   1241         soc_block_list[73],
   1242         soc_genreg,
   1243         16,
   1244         0,
   1245         0x129,
   1246         SOC_REG_FLAG_ARRAY |
   1247                           SOC_REG_FLAG_REG_ARRAY,
   1248         0,
   1249         3,
   1250         soc_KAPS_BB_GLOBAL_CONFIG_BCM88690_A0r_fields,
   1251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1252         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1253         -1,
   1254         -1,
   1255     },
   1256 #endif /* chips */
   1257 
   1258 #if defined(BCM_88690_B0)
   1259     { /* SOC_REG_INT_KAPS_BB_GLOBAL_CONFIG_BCM88690_B0r */
   1260         soc_block_list[73],
   1261         soc_genreg,
   1262         16,
   1263         0,
   1264         0x129,
   1265         SOC_REG_FLAG_ARRAY |
   1266                           SOC_REG_FLAG_REG_ARRAY,
   1267         0,
   1268         3,
   1269         soc_KAPS_BB_GLOBAL_CONFIG_BCM88690_B0r_fields,
   1270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1271         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1272         -1,
   1273         -1,
   1274     },
   1275 #endif /* chips */
   1276 
   1277 #if defined(BCM_88680_A0)
   1278     { /* SOC_REG_INT_KAPS_BB_INIT_DONEr */
   1279         soc_block_list[73],
   1280         soc_genreg,
   1281         1,
   1282         0,
   1283         0x115,
   1284         SOC_REG_FLAG_RO,
   1285         0,
   1286         8,
   1287         soc_KAPS_BB_INIT_DONEr_fields,
   1288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1289         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   1290         -1,
   1291         -1,
   1292     },
   1293 #endif /* chips */
   1294 
   1295 #if defined(BCM_88690_A0)
   1296     { /* SOC_REG_INT_KAPS_BB_LAST_SELECTEDr */
   1297         soc_block_list[73],
   1298         soc_genreg,
   1299         1,
   1300         0,
   1301         0x13d,
   1302         SOC_REG_FLAG_ABOVE_64_BITS |
   1303                           SOC_REG_FLAG_RO |
   1304                           SOC_REG_FLAG_SIGNAL,
   1305         0,
   1306         4,
   1307         soc_KAPS_BB_LAST_SELECTEDr_fields,
   1308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1309         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1310         -1,
   1311         -1,
   1312     },
   1313 #endif /* chips */
   1314 
   1315 #if defined(BCM_88690_B0)
   1316     { /* SOC_REG_INT_KAPS_BB_LAST_SELECTED_BCM88690_B0r */
   1317         soc_block_list[73],
   1318         soc_genreg,
   1319         1,
   1320         0,
   1321         0x13d,
   1322         SOC_REG_FLAG_ABOVE_64_BITS |
   1323                           SOC_REG_FLAG_RO |
   1324                           SOC_REG_FLAG_SIGNAL,
   1325         0,
   1326         4,
   1327         soc_KAPS_BB_LAST_SELECTED_BCM88690_B0r_fields,
   1328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1329         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1330         -1,
   1331         -1,
   1332     },
   1333 #endif /* chips */
   1334 
   1335 #if defined(BCM_88680_A0)
   1336     { /* SOC_REG_INT_KAPS_BRR_BB_DEBUGr */
   1337         soc_block_list[73],
   1338         soc_genreg,
   1339         4,
   1340         0,
   1341         0x10b,
   1342         SOC_REG_FLAG_ARRAY |
   1343                           SOC_REG_FLAG_RO |
   1344                           SOC_REG_FLAG_REG_ARRAY,
   1345         0,
   1346         3,
   1347         soc_KAPS_BRR_BB_DEBUGr_fields,
   1348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1349         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   1350         -1,
   1351         -1,
   1352     },
   1353 #endif /* chips */
   1354 
   1355 #if defined(BCM_88470_A0)
   1356     { /* SOC_REG_INT_KAPS_BRR_DEBUGr */
   1357         soc_block_list[73],
   1358         soc_genreg,
   1359         2,
   1360         0,
   1361         0x138,
   1362         SOC_REG_FLAG_ARRAY |
   1363                           SOC_REG_FLAG_RO |
   1364                           SOC_REG_FLAG_REG_ARRAY,
   1365         0,
   1366         3,
   1367         soc_KAPS_BRR_DEBUGr_fields,
   1368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1369         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   1370         -1,
   1371         -1,
   1372     },
   1373 #endif /* chips */
   1374 
   1375 #if defined(BCM_88270_A0)
   1376     { /* SOC_REG_INT_KAPS_BRR_DEBUG_BCM88270_A0r */
   1377         soc_block_list[73],
   1378         soc_genreg,
   1379         2,
   1380         0,
   1381         0x138,
   1382         SOC_REG_FLAG_ARRAY |
   1383                           SOC_REG_FLAG_RO |
   1384                           SOC_REG_FLAG_REG_ARRAY,
   1385         0,
   1386         3,
   1387         soc_KAPS_BRR_DEBUG_BCM88270_A0r_fields,
   1388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1389         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   1390         -1,
   1391         -1,
   1392     },
   1393 #endif /* chips */
   1394 
   1395 #if defined(BCM_88470_B0)
   1396     { /* SOC_REG_INT_KAPS_BRR_DEBUG_BCM88470_B0r */
   1397         soc_block_list[73],
   1398         soc_genreg,
   1399         2,
   1400         0,
   1401         0x138,
   1402         SOC_REG_FLAG_ARRAY |
   1403                           SOC_REG_FLAG_RO |
   1404                           SOC_REG_FLAG_REG_ARRAY,
   1405         0,
   1406         3,
   1407         soc_KAPS_BRR_DEBUG_BCM88470_B0r_fields,
   1408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1409         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   1410         -1,
   1411         -1,
   1412     },
   1413 #endif /* chips */
   1414 
   1415 #if defined(BCM_88680_A0)
   1416     { /* SOC_REG_INT_KAPS_BRR_DEBUG_BCM88680_A0r */
   1417         soc_block_list[73],
   1418         soc_genreg,
   1419         4,
   1420         0,
   1421         0x182,
   1422         SOC_REG_FLAG_ARRAY |
   1423                           SOC_REG_FLAG_RO |
   1424                           SOC_REG_FLAG_REG_ARRAY,
   1425         0,
   1426         3,
   1427         soc_KAPS_BRR_DEBUG_BCM88680_A0r_fields,
   1428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1429         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   1430         -1,
   1431         -1,
   1432     },
   1433 #endif /* chips */
   1434 
   1435 #if defined(BCM_88690_A0)
   1436     { /* SOC_REG_INT_KAPS_BRR_DEBUG_BCM88690_A0r */
   1437         soc_block_list[73],
   1438         soc_genreg,
   1439         2,
   1440         0,
   1441         0x139,
   1442         SOC_REG_FLAG_64_BITS |
   1443                           SOC_REG_FLAG_ARRAY |
   1444                           SOC_REG_FLAG_RO |
   1445                           SOC_REG_FLAG_REG_ARRAY,
   1446         0,
   1447         6,
   1448         soc_KAPS_BRR_DEBUG_BCM88690_A0r_fields,
   1449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1450         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
   1451         -1,
   1452         -1,
   1453     },
   1454 #endif /* chips */
   1455 
   1456 #if defined(BCM_88690_B0)
   1457     { /* SOC_REG_INT_KAPS_BRR_DEBUG_BCM88690_B0r */
   1458         soc_block_list[73],
   1459         soc_genreg,
   1460         2,
   1461         0,
   1462         0x139,
   1463         SOC_REG_FLAG_64_BITS |
   1464                           SOC_REG_FLAG_ARRAY |
   1465                           SOC_REG_FLAG_RO |
   1466                           SOC_REG_FLAG_REG_ARRAY,
   1467         0,
   1468         6,
   1469         soc_KAPS_BRR_DEBUG_BCM88690_B0r_fields,
   1470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1471         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
   1472         -1,
   1473         -1,
   1474     },
   1475 #endif /* chips */
   1476 
   1477 #if defined(BCM_88675_A0)
   1478     { /* SOC_REG_INT_KAPS_CONFIGr */
   1479         soc_block_list[73],
   1480         soc_genreg,
   1481         1,
   1482         0,
   1483         0x100,
   1484         0,
   1485         0,
   1486         1,
   1487         soc_KAPS_CONFIGr_fields,
   1488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1489         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   1490         -1,
   1491         -1,
   1492     },
   1493 #endif /* chips */
   1494 
   1495 #if defined(BCM_88375_A0)
   1496     { /* SOC_REG_INT_KAPS_CONFIG_BCM88375_A0r */
   1497         soc_block_list[73],
   1498         soc_genreg,
   1499         1,
   1500         0,
   1501         0x100,
   1502         0,
   1503         0,
   1504         1,
   1505         soc_KAPS_CONFIG_BCM88375_A0r_fields,
   1506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1507         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   1508         -1,
   1509         -1,
   1510     },
   1511 #endif /* chips */
   1512 
   1513 #if defined(BCM_88375_B0)
   1514     { /* SOC_REG_INT_KAPS_CONFIG_BCM88375_B0r */
   1515         soc_block_list[73],
   1516         soc_genreg,
   1517         1,
   1518         0,
   1519         0x100,
   1520         0,
   1521         0,
   1522         1,
   1523         soc_KAPS_CONFIG_BCM88375_B0r_fields,
   1524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1525         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   1526         -1,
   1527         -1,
   1528     },
   1529 #endif /* chips */
   1530 
   1531 #if defined(BCM_88675_B0)
   1532     { /* SOC_REG_INT_KAPS_CONFIG_BCM88675_B0r */
   1533         soc_block_list[73],
   1534         soc_genreg,
   1535         1,
   1536         0,
   1537         0x100,
   1538         0,
   1539         0,
   1540         1,
   1541         soc_KAPS_CONFIG_BCM88675_B0r_fields,
   1542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1543         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   1544         -1,
   1545         -1,
   1546     },
   1547 #endif /* chips */
   1548 
   1549 #if defined(BCM_88675_A0)
   1550     { /* SOC_REG_INT_KAPS_CONFIG_CFIFOr */
   1551         soc_block_list[73],
   1552         soc_genreg,
   1553         4,
   1554         0,
   1555         0x2700,
   1556         SOC_REG_FLAG_ARRAY |
   1557                           SOC_REG_FLAG_REG_ARRAY,
   1558         0,
   1559         4,
   1560         soc_KAPS_CONFIG_CFIFOr_fields,
   1561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1562         SOC_RESET_MASK_DEC(0xffff03ff, 0x00000000)
   1563         -1,
   1564         -1,
   1565     },
   1566 #endif /* chips */
   1567 
   1568 #if defined(BCM_88375_A0)
   1569     { /* SOC_REG_INT_KAPS_CONFIG_CFIFO_BCM88375_A0r */
   1570         soc_block_list[73],
   1571         soc_genreg,
   1572         4,
   1573         0,
   1574         0x2700,
   1575         SOC_REG_FLAG_ARRAY |
   1576                           SOC_REG_FLAG_REG_ARRAY,
   1577         0,
   1578         4,
   1579         soc_KAPS_CONFIG_CFIFO_BCM88375_A0r_fields,
   1580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1581         SOC_RESET_MASK_DEC(0xffff03ff, 0x00000000)
   1582         -1,
   1583         -1,
   1584     },
   1585 #endif /* chips */
   1586 
   1587 #if defined(BCM_88375_B0)
   1588     { /* SOC_REG_INT_KAPS_CONFIG_CFIFO_BCM88375_B0r */
   1589         soc_block_list[73],
   1590         soc_genreg,
   1591         4,
   1592         0,
   1593         0x2700,
   1594         SOC_REG_FLAG_ARRAY |
   1595                           SOC_REG_FLAG_REG_ARRAY,
   1596         0,
   1597         4,
   1598         soc_KAPS_CONFIG_CFIFO_BCM88375_B0r_fields,
   1599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1600         SOC_RESET_MASK_DEC(0xffff03ff, 0x00000000)
   1601         -1,
   1602         -1,
   1603     },
   1604 #endif /* chips */
   1605 
   1606 #if defined(BCM_88675_B0)
   1607     { /* SOC_REG_INT_KAPS_CONFIG_CFIFO_BCM88675_B0r */
   1608         soc_block_list[73],
   1609         soc_genreg,
   1610         4,
   1611         0,
   1612         0x2700,
   1613         SOC_REG_FLAG_ARRAY |
   1614                           SOC_REG_FLAG_REG_ARRAY,
   1615         0,
   1616         4,
   1617         soc_KAPS_CONFIG_CFIFO_BCM88675_B0r_fields,
   1618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1619         SOC_RESET_MASK_DEC(0xffff03ff, 0x00000000)
   1620         -1,
   1621         -1,
   1622     },
   1623 #endif /* chips */
   1624 
   1625 #if defined(BCM_88675_A0)
   1626     { /* SOC_REG_INT_KAPS_CONFIG_CFIFO_THRESHr */
   1627         soc_block_list[73],
   1628         soc_genreg,
   1629         4,
   1630         0,
   1631         0x2b00,
   1632         SOC_REG_FLAG_ARRAY |
   1633                           SOC_REG_FLAG_REG_ARRAY,
   1634         0,
   1635         1,
   1636         soc_KAPS_CONFIG_CFIFO_THRESHr_fields,
   1637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1638         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1639         -1,
   1640         -1,
   1641     },
   1642 #endif /* chips */
   1643 
   1644 #if defined(BCM_88375_A0)
   1645     { /* SOC_REG_INT_KAPS_CONFIG_CFIFO_THRESH_BCM88375_A0r */
   1646         soc_block_list[73],
   1647         soc_genreg,
   1648         4,
   1649         0,
   1650         0x2b00,
   1651         SOC_REG_FLAG_ARRAY |
   1652                           SOC_REG_FLAG_REG_ARRAY,
   1653         0,
   1654         1,
   1655         soc_KAPS_CONFIG_CFIFO_THRESH_BCM88375_A0r_fields,
   1656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1657         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1658         -1,
   1659         -1,
   1660     },
   1661 #endif /* chips */
   1662 
   1663 #if defined(BCM_88375_B0)
   1664     { /* SOC_REG_INT_KAPS_CONFIG_CFIFO_THRESH_BCM88375_B0r */
   1665         soc_block_list[73],
   1666         soc_genreg,
   1667         4,
   1668         0,
   1669         0x2b00,
   1670         SOC_REG_FLAG_ARRAY |
   1671                           SOC_REG_FLAG_REG_ARRAY,
   1672         0,
   1673         1,
   1674         soc_KAPS_CONFIG_CFIFO_THRESH_BCM88375_B0r_fields,
   1675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1676         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1677         -1,
   1678         -1,
   1679     },
   1680 #endif /* chips */
   1681 
   1682 #if defined(BCM_88675_B0)
   1683     { /* SOC_REG_INT_KAPS_CONFIG_CFIFO_THRESH_BCM88675_B0r */
   1684         soc_block_list[73],
   1685         soc_genreg,
   1686         4,
   1687         0,
   1688         0x2b00,
   1689         SOC_REG_FLAG_ARRAY |
   1690                           SOC_REG_FLAG_REG_ARRAY,
   1691         0,
   1692         1,
   1693         soc_KAPS_CONFIG_CFIFO_THRESH_BCM88675_B0r_fields,
   1694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1695         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1696         -1,
   1697         -1,
   1698     },
   1699 #endif /* chips */
   1700 
   1701 #if defined(BCM_88675_A0)
   1702     { /* SOC_REG_INT_KAPS_CONFIG_FIFO_MONr */
   1703         soc_block_list[73],
   1704         soc_genreg,
   1705         1,
   1706         0,
   1707         0x3b00,
   1708         0,
   1709         0,
   1710         3,
   1711         soc_KAPS_CONFIG_FIFO_MONr_fields,
   1712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1713         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1714         -1,
   1715         -1,
   1716     },
   1717 #endif /* chips */
   1718 
   1719 #if defined(BCM_88375_A0)
   1720     { /* SOC_REG_INT_KAPS_CONFIG_FIFO_MON_BCM88375_A0r */
   1721         soc_block_list[73],
   1722         soc_genreg,
   1723         1,
   1724         0,
   1725         0x3b00,
   1726         0,
   1727         0,
   1728         3,
   1729         soc_KAPS_CONFIG_FIFO_MON_BCM88375_A0r_fields,
   1730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1731         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1732         -1,
   1733         -1,
   1734     },
   1735 #endif /* chips */
   1736 
   1737 #if defined(BCM_88375_B0)
   1738     { /* SOC_REG_INT_KAPS_CONFIG_FIFO_MON_BCM88375_B0r */
   1739         soc_block_list[73],
   1740         soc_genreg,
   1741         1,
   1742         0,
   1743         0x3b00,
   1744         0,
   1745         0,
   1746         3,
   1747         soc_KAPS_CONFIG_FIFO_MON_BCM88375_B0r_fields,
   1748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1749         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1750         -1,
   1751         -1,
   1752     },
   1753 #endif /* chips */
   1754 
   1755 #if defined(BCM_88675_B0)
   1756     { /* SOC_REG_INT_KAPS_CONFIG_FIFO_MON_BCM88675_B0r */
   1757         soc_block_list[73],
   1758         soc_genreg,
   1759         1,
   1760         0,
   1761         0x3b00,
   1762         0,
   1763         0,
   1764         3,
   1765         soc_KAPS_CONFIG_FIFO_MON_BCM88675_B0r_fields,
   1766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1767         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1768         -1,
   1769         -1,
   1770     },
   1771 #endif /* chips */
   1772 
   1773 #if defined(BCM_88675_A0)
   1774     { /* SOC_REG_INT_KAPS_CONFIG_RFIFOr */
   1775         soc_block_list[73],
   1776         soc_genreg,
   1777         4,
   1778         0,
   1779         0x3300,
   1780         SOC_REG_FLAG_ARRAY |
   1781                           SOC_REG_FLAG_REG_ARRAY,
   1782         0,
   1783         4,
   1784         soc_KAPS_CONFIG_RFIFOr_fields,
   1785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1786         SOC_RESET_MASK_DEC(0xffff03ff, 0x00000000)
   1787         -1,
   1788         -1,
   1789     },
   1790 #endif /* chips */
   1791 
   1792 #if defined(BCM_88375_A0)
   1793     { /* SOC_REG_INT_KAPS_CONFIG_RFIFO_BCM88375_A0r */
   1794         soc_block_list[73],
   1795         soc_genreg,
   1796         4,
   1797         0,
   1798         0x3300,
   1799         SOC_REG_FLAG_ARRAY |
   1800                           SOC_REG_FLAG_REG_ARRAY,
   1801         0,
   1802         4,
   1803         soc_KAPS_CONFIG_RFIFO_BCM88375_A0r_fields,
   1804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1805         SOC_RESET_MASK_DEC(0xffff03ff, 0x00000000)
   1806         -1,
   1807         -1,
   1808     },
   1809 #endif /* chips */
   1810 
   1811 #if defined(BCM_88375_B0)
   1812     { /* SOC_REG_INT_KAPS_CONFIG_RFIFO_BCM88375_B0r */
   1813         soc_block_list[73],
   1814         soc_genreg,
   1815         4,
   1816         0,
   1817         0x3300,
   1818         SOC_REG_FLAG_ARRAY |
   1819                           SOC_REG_FLAG_REG_ARRAY,
   1820         0,
   1821         4,
   1822         soc_KAPS_CONFIG_RFIFO_BCM88375_B0r_fields,
   1823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1824         SOC_RESET_MASK_DEC(0xffff03ff, 0x00000000)
   1825         -1,
   1826         -1,
   1827     },
   1828 #endif /* chips */
   1829 
   1830 #if defined(BCM_88675_B0)
   1831     { /* SOC_REG_INT_KAPS_CONFIG_RFIFO_BCM88675_B0r */
   1832         soc_block_list[73],
   1833         soc_genreg,
   1834         4,
   1835         0,
   1836         0x3300,
   1837         SOC_REG_FLAG_ARRAY |
   1838                           SOC_REG_FLAG_REG_ARRAY,
   1839         0,
   1840         4,
   1841         soc_KAPS_CONFIG_RFIFO_BCM88675_B0r_fields,
   1842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1843         SOC_RESET_MASK_DEC(0xffff03ff, 0x00000000)
   1844         -1,
   1845         -1,
   1846     },
   1847 #endif /* chips */
   1848 
   1849 #if defined(BCM_88270_A0)
   1850     { /* SOC_REG_INT_KAPS_CYCLES_OUT_OF_IDLE_0_CNTr */
   1851         soc_block_list[73],
   1852         soc_genreg,
   1853         1,
   1854         0,
   1855         0x147,
   1856         SOC_REG_FLAG_RO,
   1857         0,
   1858         2,
   1859         soc_KAPS_CYCLES_OUT_OF_IDLE_0_CNTr_fields,
   1860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1861         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1862         -1,
   1863         -1,
   1864     },
   1865 #endif /* chips */
   1866 
   1867 #if defined(BCM_88680_A0)
   1868     { /* SOC_REG_INT_KAPS_CYCLES_OUT_OF_IDLE_0_CNT_BCM88680_A0r */
   1869         soc_block_list[73],
   1870         soc_genreg,
   1871         1,
   1872         0,
   1873         0x18d,
   1874         SOC_REG_FLAG_RO,
   1875         0,
   1876         2,
   1877         soc_KAPS_CYCLES_OUT_OF_IDLE_0_CNT_BCM88680_A0r_fields,
   1878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1879         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1880         -1,
   1881         -1,
   1882     },
   1883 #endif /* chips */
   1884 
   1885 #if defined(BCM_88270_A0)
   1886     { /* SOC_REG_INT_KAPS_CYCLES_OUT_OF_IDLE_1_CNTr */
   1887         soc_block_list[73],
   1888         soc_genreg,
   1889         1,
   1890         0,
   1891         0x148,
   1892         SOC_REG_FLAG_RO,
   1893         0,
   1894         2,
   1895         soc_KAPS_CYCLES_OUT_OF_IDLE_1_CNTr_fields,
   1896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1898         -1,
   1899         -1,
   1900     },
   1901 #endif /* chips */
   1902 
   1903 #if defined(BCM_88680_A0)
   1904     { /* SOC_REG_INT_KAPS_CYCLES_OUT_OF_IDLE_1_CNT_BCM88680_A0r */
   1905         soc_block_list[73],
   1906         soc_genreg,
   1907         1,
   1908         0,
   1909         0x18e,
   1910         SOC_REG_FLAG_RO,
   1911         0,
   1912         2,
   1913         soc_KAPS_CYCLES_OUT_OF_IDLE_1_CNT_BCM88680_A0r_fields,
   1914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1916         -1,
   1917         -1,
   1918     },
   1919 #endif /* chips */
   1920 
   1921 #if defined(BCM_88470_A0)
   1922     { /* SOC_REG_INT_KAPS_ECC_1B_ERR_CNTr */
   1923         soc_block_list[73],
   1924         soc_genreg,
   1925         1,
   1926         0,
   1927         0x94,
   1928         SOC_REG_FLAG_64_BITS |
   1929                           SOC_REG_FLAG_RO,
   1930         0,
   1931         4,
   1932         soc_KAPS_ECC_1B_ERR_CNTr_fields,
   1933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1934         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1935         -1,
   1936         -1,
   1937     },
   1938 #endif /* chips */
   1939 
   1940 #if defined(BCM_88270_A0)
   1941     { /* SOC_REG_INT_KAPS_ECC_1B_ERR_CNT_BCM88270_A0r */
   1942         soc_block_list[73],
   1943         soc_genreg,
   1944         1,
   1945         0,
   1946         0x94,
   1947         SOC_REG_FLAG_64_BITS |
   1948                           SOC_REG_FLAG_RO,
   1949         0,
   1950         4,
   1951         soc_KAPS_ECC_1B_ERR_CNT_BCM88270_A0r_fields,
   1952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1953         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1954         -1,
   1955         -1,
   1956     },
   1957 #endif /* chips */
   1958 
   1959 #if defined(BCM_88470_B0)
   1960     { /* SOC_REG_INT_KAPS_ECC_1B_ERR_CNT_BCM88470_B0r */
   1961         soc_block_list[73],
   1962         soc_genreg,
   1963         1,
   1964         0,
   1965         0x94,
   1966         SOC_REG_FLAG_64_BITS |
   1967                           SOC_REG_FLAG_RO,
   1968         0,
   1969         4,
   1970         soc_KAPS_ECC_1B_ERR_CNT_BCM88470_B0r_fields,
   1971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1972         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1973         -1,
   1974         -1,
   1975     },
   1976 #endif /* chips */
   1977 
   1978 #if defined(BCM_88680_A0)
   1979     { /* SOC_REG_INT_KAPS_ECC_1B_ERR_CNT_BCM88680_A0r */
   1980         soc_block_list[73],
   1981         soc_genreg,
   1982         1,
   1983         0,
   1984         0x94,
   1985         SOC_REG_FLAG_64_BITS |
   1986                           SOC_REG_FLAG_RO,
   1987         0,
   1988         4,
   1989         soc_KAPS_ECC_1B_ERR_CNT_BCM88680_A0r_fields,
   1990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1991         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1992         -1,
   1993         -1,
   1994     },
   1995 #endif /* chips */
   1996 
   1997 #if defined(BCM_88690_A0)
   1998     { /* SOC_REG_INT_KAPS_ECC_1B_ERR_CNT_BCM88690_A0r */
   1999         soc_block_list[73],
   2000         soc_genreg,
   2001         1,
   2002         0,
   2003         0x94,
   2004         SOC_REG_FLAG_64_BITS |
   2005                           SOC_REG_FLAG_RO,
   2006         SOC_REG_FLAG_COUNTER_FEILDS |
   2007                           SOC_REG_FLAG_INIT_ON_READ,
   2008         4,
   2009         soc_KAPS_ECC_1B_ERR_CNT_BCM88690_A0r_fields,
   2010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2011         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2012         -1,
   2013         -1,
   2014     },
   2015 #endif /* chips */
   2016 
   2017 #if defined(BCM_88690_B0)
   2018     { /* SOC_REG_INT_KAPS_ECC_1B_ERR_CNT_BCM88690_B0r */
   2019         soc_block_list[73],
   2020         soc_genreg,
   2021         1,
   2022         0,
   2023         0x94,
   2024         SOC_REG_FLAG_64_BITS |
   2025                           SOC_REG_FLAG_RO,
   2026         SOC_REG_FLAG_COUNTER_FEILDS |
   2027                           SOC_REG_FLAG_INIT_ON_READ,
   2028         4,
   2029         soc_KAPS_ECC_1B_ERR_CNT_BCM88690_B0r_fields,
   2030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2031         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2032         -1,
   2033         -1,
   2034     },
   2035 #endif /* chips */
   2036 
   2037 #if defined(BCM_88470_A0)
   2038     { /* SOC_REG_INT_KAPS_ECC_2B_ERR_CNTr */
   2039         soc_block_list[73],
   2040         soc_genreg,
   2041         1,
   2042         0,
   2043         0x96,
   2044         SOC_REG_FLAG_64_BITS |
   2045                           SOC_REG_FLAG_RO,
   2046         0,
   2047         4,
   2048         soc_KAPS_ECC_2B_ERR_CNTr_fields,
   2049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2050         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2051         -1,
   2052         -1,
   2053     },
   2054 #endif /* chips */
   2055 
   2056 #if defined(BCM_88270_A0)
   2057     { /* SOC_REG_INT_KAPS_ECC_2B_ERR_CNT_BCM88270_A0r */
   2058         soc_block_list[73],
   2059         soc_genreg,
   2060         1,
   2061         0,
   2062         0x96,
   2063         SOC_REG_FLAG_64_BITS |
   2064                           SOC_REG_FLAG_RO,
   2065         0,
   2066         4,
   2067         soc_KAPS_ECC_2B_ERR_CNT_BCM88270_A0r_fields,
   2068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2069         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2070         -1,
   2071         -1,
   2072     },
   2073 #endif /* chips */
   2074 
   2075 #if defined(BCM_88470_B0)
   2076     { /* SOC_REG_INT_KAPS_ECC_2B_ERR_CNT_BCM88470_B0r */
   2077         soc_block_list[73],
   2078         soc_genreg,
   2079         1,
   2080         0,
   2081         0x96,
   2082         SOC_REG_FLAG_64_BITS |
   2083                           SOC_REG_FLAG_RO,
   2084         0,
   2085         4,
   2086         soc_KAPS_ECC_2B_ERR_CNT_BCM88470_B0r_fields,
   2087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2088         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2089         -1,
   2090         -1,
   2091     },
   2092 #endif /* chips */
   2093 
   2094 #if defined(BCM_88680_A0)
   2095     { /* SOC_REG_INT_KAPS_ECC_2B_ERR_CNT_BCM88680_A0r */
   2096         soc_block_list[73],
   2097         soc_genreg,
   2098         1,
   2099         0,
   2100         0x96,
   2101         SOC_REG_FLAG_64_BITS |
   2102                           SOC_REG_FLAG_RO,
   2103         0,
   2104         4,
   2105         soc_KAPS_ECC_2B_ERR_CNT_BCM88680_A0r_fields,
   2106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2107         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2108         -1,
   2109         -1,
   2110     },
   2111 #endif /* chips */
   2112 
   2113 #if defined(BCM_88690_A0)
   2114     { /* SOC_REG_INT_KAPS_ECC_2B_ERR_CNT_BCM88690_A0r */
   2115         soc_block_list[73],
   2116         soc_genreg,
   2117         1,
   2118         0,
   2119         0x96,
   2120         SOC_REG_FLAG_64_BITS |
   2121                           SOC_REG_FLAG_RO,
   2122         SOC_REG_FLAG_COUNTER_FEILDS |
   2123                           SOC_REG_FLAG_INIT_ON_READ,
   2124         4,
   2125         soc_KAPS_ECC_2B_ERR_CNT_BCM88690_A0r_fields,
   2126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2127         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2128         -1,
   2129         -1,
   2130     },
   2131 #endif /* chips */
   2132 
   2133 #if defined(BCM_88690_B0)
   2134     { /* SOC_REG_INT_KAPS_ECC_2B_ERR_CNT_BCM88690_B0r */
   2135         soc_block_list[73],
   2136         soc_genreg,
   2137         1,
   2138         0,
   2139         0x96,
   2140         SOC_REG_FLAG_64_BITS |
   2141                           SOC_REG_FLAG_RO,
   2142         SOC_REG_FLAG_COUNTER_FEILDS |
   2143                           SOC_REG_FLAG_INIT_ON_READ,
   2144         4,
   2145         soc_KAPS_ECC_2B_ERR_CNT_BCM88690_B0r_fields,
   2146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2147         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2148         -1,
   2149         -1,
   2150     },
   2151 #endif /* chips */
   2152 
   2153 #if defined(BCM_88470_A0)
   2154     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_INITIATEr */
   2155         soc_block_list[73],
   2156         soc_genreg,
   2157         1,
   2158         0,
   2159         0xa4,
   2160         SOC_REG_FLAG_64_BITS,
   2161         0,
   2162         34,
   2163         soc_KAPS_ECC_ERR_1B_INITIATEr_fields,
   2164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2165         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
   2166         -1,
   2167         -1,
   2168     },
   2169 #endif /* chips */
   2170 
   2171 #if defined(BCM_88270_A0)
   2172     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_INITIATE_BCM88270_A0r */
   2173         soc_block_list[73],
   2174         soc_genreg,
   2175         1,
   2176         0,
   2177         0xa4,
   2178         0,
   2179         0,
   2180         18,
   2181         soc_KAPS_ECC_ERR_1B_INITIATE_BCM88270_A0r_fields,
   2182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2183         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2184         -1,
   2185         -1,
   2186     },
   2187 #endif /* chips */
   2188 
   2189 #if defined(BCM_88470_B0)
   2190     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_INITIATE_BCM88470_B0r */
   2191         soc_block_list[73],
   2192         soc_genreg,
   2193         1,
   2194         0,
   2195         0xa4,
   2196         SOC_REG_FLAG_64_BITS,
   2197         0,
   2198         34,
   2199         soc_KAPS_ECC_ERR_1B_INITIATE_BCM88470_B0r_fields,
   2200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2201         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
   2202         -1,
   2203         -1,
   2204     },
   2205 #endif /* chips */
   2206 
   2207 #if defined(BCM_88680_A0)
   2208     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_INITIATE_BCM88680_A0r */
   2209         soc_block_list[73],
   2210         soc_genreg,
   2211         1,
   2212         0,
   2213         0xa4,
   2214         0,
   2215         0,
   2216         12,
   2217         soc_KAPS_ECC_ERR_1B_INITIATE_BCM88680_A0r_fields,
   2218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2219         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   2220         -1,
   2221         -1,
   2222     },
   2223 #endif /* chips */
   2224 
   2225 #if defined(BCM_88470_A0)
   2226     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_MONITOR_MEM_MASKr */
   2227         soc_block_list[73],
   2228         soc_genreg,
   2229         1,
   2230         0,
   2231         0x9a,
   2232         SOC_REG_FLAG_64_BITS,
   2233         0,
   2234         34,
   2235         soc_KAPS_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
   2236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
   2238         -1,
   2239         -1,
   2240     },
   2241 #endif /* chips */
   2242 
   2243 #if defined(BCM_88270_A0)
   2244     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88270_A0r */
   2245         soc_block_list[73],
   2246         soc_genreg,
   2247         1,
   2248         0,
   2249         0x9a,
   2250         0,
   2251         0,
   2252         18,
   2253         soc_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88270_A0r_fields,
   2254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2255         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2256         -1,
   2257         -1,
   2258     },
   2259 #endif /* chips */
   2260 
   2261 #if defined(BCM_88470_B0)
   2262     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_B0r */
   2263         soc_block_list[73],
   2264         soc_genreg,
   2265         1,
   2266         0,
   2267         0x9a,
   2268         SOC_REG_FLAG_64_BITS,
   2269         0,
   2270         34,
   2271         soc_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_B0r_fields,
   2272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2273         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
   2274         -1,
   2275         -1,
   2276     },
   2277 #endif /* chips */
   2278 
   2279 #if defined(BCM_88680_A0)
   2280     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r */
   2281         soc_block_list[73],
   2282         soc_genreg,
   2283         1,
   2284         0,
   2285         0x9a,
   2286         0,
   2287         0,
   2288         12,
   2289         soc_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
   2290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2291         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   2292         -1,
   2293         -1,
   2294     },
   2295 #endif /* chips */
   2296 
   2297 #if defined(BCM_88690_A0)
   2298     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r */
   2299         soc_block_list[73],
   2300         soc_genreg,
   2301         1,
   2302         0,
   2303         0x9a,
   2304         0,
   2305         0,
   2306         18,
   2307         soc_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
   2308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2309         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2310         -1,
   2311         -1,
   2312     },
   2313 #endif /* chips */
   2314 
   2315 #if defined(BCM_88690_B0)
   2316     { /* SOC_REG_INT_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r */
   2317         soc_block_list[73],
   2318         soc_genreg,
   2319         1,
   2320         0,
   2321         0x9a,
   2322         0,
   2323         0,
   2324         18,
   2325         soc_KAPS_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
   2326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2327         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2328         -1,
   2329         -1,
   2330     },
   2331 #endif /* chips */
   2332 
   2333 #if defined(BCM_88470_A0)
   2334     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_INITIATEr */
   2335         soc_block_list[73],
   2336         soc_genreg,
   2337         1,
   2338         0,
   2339         0xa6,
   2340         SOC_REG_FLAG_64_BITS,
   2341         0,
   2342         34,
   2343         soc_KAPS_ECC_ERR_2B_INITIATEr_fields,
   2344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
   2346         -1,
   2347         -1,
   2348     },
   2349 #endif /* chips */
   2350 
   2351 #if defined(BCM_88270_A0)
   2352     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_INITIATE_BCM88270_A0r */
   2353         soc_block_list[73],
   2354         soc_genreg,
   2355         1,
   2356         0,
   2357         0xa6,
   2358         0,
   2359         0,
   2360         18,
   2361         soc_KAPS_ECC_ERR_2B_INITIATE_BCM88270_A0r_fields,
   2362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2363         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2364         -1,
   2365         -1,
   2366     },
   2367 #endif /* chips */
   2368 
   2369 #if defined(BCM_88470_B0)
   2370     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_INITIATE_BCM88470_B0r */
   2371         soc_block_list[73],
   2372         soc_genreg,
   2373         1,
   2374         0,
   2375         0xa6,
   2376         SOC_REG_FLAG_64_BITS,
   2377         0,
   2378         34,
   2379         soc_KAPS_ECC_ERR_2B_INITIATE_BCM88470_B0r_fields,
   2380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
   2382         -1,
   2383         -1,
   2384     },
   2385 #endif /* chips */
   2386 
   2387 #if defined(BCM_88680_A0)
   2388     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_INITIATE_BCM88680_A0r */
   2389         soc_block_list[73],
   2390         soc_genreg,
   2391         1,
   2392         0,
   2393         0xa6,
   2394         0,
   2395         0,
   2396         12,
   2397         soc_KAPS_ECC_ERR_2B_INITIATE_BCM88680_A0r_fields,
   2398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2399         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   2400         -1,
   2401         -1,
   2402     },
   2403 #endif /* chips */
   2404 
   2405 #if defined(BCM_88470_A0)
   2406     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_MONITOR_MEM_MASKr */
   2407         soc_block_list[73],
   2408         soc_genreg,
   2409         1,
   2410         0,
   2411         0x9c,
   2412         SOC_REG_FLAG_64_BITS,
   2413         0,
   2414         34,
   2415         soc_KAPS_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
   2416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
   2418         -1,
   2419         -1,
   2420     },
   2421 #endif /* chips */
   2422 
   2423 #if defined(BCM_88270_A0)
   2424     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88270_A0r */
   2425         soc_block_list[73],
   2426         soc_genreg,
   2427         1,
   2428         0,
   2429         0x9c,
   2430         0,
   2431         0,
   2432         18,
   2433         soc_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88270_A0r_fields,
   2434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2435         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2436         -1,
   2437         -1,
   2438     },
   2439 #endif /* chips */
   2440 
   2441 #if defined(BCM_88470_B0)
   2442     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_B0r */
   2443         soc_block_list[73],
   2444         soc_genreg,
   2445         1,
   2446         0,
   2447         0x9c,
   2448         SOC_REG_FLAG_64_BITS,
   2449         0,
   2450         34,
   2451         soc_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_B0r_fields,
   2452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
   2454         -1,
   2455         -1,
   2456     },
   2457 #endif /* chips */
   2458 
   2459 #if defined(BCM_88680_A0)
   2460     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r */
   2461         soc_block_list[73],
   2462         soc_genreg,
   2463         1,
   2464         0,
   2465         0x9c,
   2466         0,
   2467         0,
   2468         12,
   2469         soc_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
   2470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2471         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   2472         -1,
   2473         -1,
   2474     },
   2475 #endif /* chips */
   2476 
   2477 #if defined(BCM_88690_A0)
   2478     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r */
   2479         soc_block_list[73],
   2480         soc_genreg,
   2481         1,
   2482         0,
   2483         0x9c,
   2484         0,
   2485         0,
   2486         18,
   2487         soc_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
   2488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2489         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2490         -1,
   2491         -1,
   2492     },
   2493 #endif /* chips */
   2494 
   2495 #if defined(BCM_88690_B0)
   2496     { /* SOC_REG_INT_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r */
   2497         soc_block_list[73],
   2498         soc_genreg,
   2499         1,
   2500         0,
   2501         0x9c,
   2502         0,
   2503         0,
   2504         18,
   2505         soc_KAPS_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
   2506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2507         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2508         -1,
   2509         -1,
   2510     },
   2511 #endif /* chips */
   2512 
   2513 #if defined(BCM_88470_A0)
   2514     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTERr */
   2515         soc_block_list[73],
   2516         soc_genreg,
   2517         1,
   2518         0,
   2519         0x7,
   2520         SOC_REG_FLAG_INTERRUPT |
   2521                           SOC_REG_FLAG_SIGNAL,
   2522         0,
   2523         3,
   2524         soc_KAPS_ECC_INTERRUPT_REGISTERr_fields,
   2525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2526         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2527         -1,
   2528         -1,
   2529     },
   2530 #endif /* chips */
   2531 
   2532 #if defined(BCM_88270_A0)
   2533     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_BCM88270_A0r */
   2534         soc_block_list[73],
   2535         soc_genreg,
   2536         1,
   2537         0,
   2538         0x7,
   2539         SOC_REG_FLAG_INTERRUPT |
   2540                           SOC_REG_FLAG_SIGNAL,
   2541         0,
   2542         3,
   2543         soc_KAPS_ECC_INTERRUPT_REGISTER_BCM88270_A0r_fields,
   2544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2545         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2546         -1,
   2547         -1,
   2548     },
   2549 #endif /* chips */
   2550 
   2551 #if defined(BCM_88470_B0)
   2552     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_BCM88470_B0r */
   2553         soc_block_list[73],
   2554         soc_genreg,
   2555         1,
   2556         0,
   2557         0x7,
   2558         SOC_REG_FLAG_INTERRUPT |
   2559                           SOC_REG_FLAG_SIGNAL,
   2560         0,
   2561         3,
   2562         soc_KAPS_ECC_INTERRUPT_REGISTER_BCM88470_B0r_fields,
   2563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2564         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2565         -1,
   2566         -1,
   2567     },
   2568 #endif /* chips */
   2569 
   2570 #if defined(BCM_88680_A0)
   2571     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_BCM88680_A0r */
   2572         soc_block_list[73],
   2573         soc_genreg,
   2574         1,
   2575         0,
   2576         0x7,
   2577         SOC_REG_FLAG_INTERRUPT,
   2578         0,
   2579         3,
   2580         soc_KAPS_ECC_INTERRUPT_REGISTER_BCM88680_A0r_fields,
   2581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2582         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2583         -1,
   2584         -1,
   2585     },
   2586 #endif /* chips */
   2587 
   2588 #if defined(BCM_88690_A0)
   2589     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_BCM88690_A0r */
   2590         soc_block_list[73],
   2591         soc_genreg,
   2592         1,
   2593         0,
   2594         0x7,
   2595         SOC_REG_FLAG_INTERRUPT |
   2596                           SOC_REG_FLAG_SIGNAL,
   2597         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   2598         3,
   2599         soc_KAPS_ECC_INTERRUPT_REGISTER_BCM88690_A0r_fields,
   2600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2601         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2602         -1,
   2603         -1,
   2604     },
   2605 #endif /* chips */
   2606 
   2607 #if defined(BCM_88690_B0)
   2608     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
   2609         soc_block_list[73],
   2610         soc_genreg,
   2611         1,
   2612         0,
   2613         0x7,
   2614         SOC_REG_FLAG_INTERRUPT |
   2615                           SOC_REG_FLAG_SIGNAL,
   2616         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   2617         3,
   2618         soc_KAPS_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   2619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2620         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2621         -1,
   2622         -1,
   2623     },
   2624 #endif /* chips */
   2625 
   2626 #if defined(BCM_88470_A0)
   2627     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_MASKr */
   2628         soc_block_list[73],
   2629         soc_genreg,
   2630         1,
   2631         0,
   2632         0x17,
   2633         0,
   2634         0,
   2635         3,
   2636         soc_KAPS_ECC_INTERRUPT_REGISTER_MASKr_fields,
   2637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2638         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2639         -1,
   2640         -1,
   2641     },
   2642 #endif /* chips */
   2643 
   2644 #if defined(BCM_88270_A0)
   2645     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88270_A0r */
   2646         soc_block_list[73],
   2647         soc_genreg,
   2648         1,
   2649         0,
   2650         0x17,
   2651         0,
   2652         0,
   2653         3,
   2654         soc_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88270_A0r_fields,
   2655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2656         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2657         -1,
   2658         -1,
   2659     },
   2660 #endif /* chips */
   2661 
   2662 #if defined(BCM_88470_B0)
   2663     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88470_B0r */
   2664         soc_block_list[73],
   2665         soc_genreg,
   2666         1,
   2667         0,
   2668         0x17,
   2669         0,
   2670         0,
   2671         3,
   2672         soc_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88470_B0r_fields,
   2673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2674         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2675         -1,
   2676         -1,
   2677     },
   2678 #endif /* chips */
   2679 
   2680 #if defined(BCM_88680_A0)
   2681     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r */
   2682         soc_block_list[73],
   2683         soc_genreg,
   2684         1,
   2685         0,
   2686         0x17,
   2687         0,
   2688         0,
   2689         3,
   2690         soc_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r_fields,
   2691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2692         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2693         -1,
   2694         -1,
   2695     },
   2696 #endif /* chips */
   2697 
   2698 #if defined(BCM_88690_A0)
   2699     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r */
   2700         soc_block_list[73],
   2701         soc_genreg,
   2702         1,
   2703         0,
   2704         0x17,
   2705         0,
   2706         0,
   2707         3,
   2708         soc_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r_fields,
   2709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2710         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2711         -1,
   2712         -1,
   2713     },
   2714 #endif /* chips */
   2715 
   2716 #if defined(BCM_88690_B0)
   2717     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
   2718         soc_block_list[73],
   2719         soc_genreg,
   2720         1,
   2721         0,
   2722         0x17,
   2723         0,
   2724         0,
   2725         3,
   2726         soc_KAPS_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
   2727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2728         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2729         -1,
   2730         -1,
   2731     },
   2732 #endif /* chips */
   2733 
   2734 #if defined(BCM_88470_A0)
   2735     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_TESTr */
   2736         soc_block_list[73],
   2737         soc_genreg,
   2738         1,
   2739         0,
   2740         0x1f,
   2741         0,
   2742         0,
   2743         1,
   2744         soc_KAPS_ECC_INTERRUPT_REGISTER_TESTr_fields,
   2745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2746         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2747         -1,
   2748         -1,
   2749     },
   2750 #endif /* chips */
   2751 
   2752 #if defined(BCM_88270_A0)
   2753     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88270_A0r */
   2754         soc_block_list[73],
   2755         soc_genreg,
   2756         1,
   2757         0,
   2758         0x1f,
   2759         0,
   2760         0,
   2761         1,
   2762         soc_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88270_A0r_fields,
   2763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2764         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2765         -1,
   2766         -1,
   2767     },
   2768 #endif /* chips */
   2769 
   2770 #if defined(BCM_88470_B0)
   2771     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88470_B0r */
   2772         soc_block_list[73],
   2773         soc_genreg,
   2774         1,
   2775         0,
   2776         0x1f,
   2777         0,
   2778         0,
   2779         1,
   2780         soc_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88470_B0r_fields,
   2781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2782         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2783         -1,
   2784         -1,
   2785     },
   2786 #endif /* chips */
   2787 
   2788 #if defined(BCM_88680_A0)
   2789     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
   2790         soc_block_list[73],
   2791         soc_genreg,
   2792         1,
   2793         0,
   2794         0x1f,
   2795         0,
   2796         0,
   2797         1,
   2798         soc_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
   2799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2801         -1,
   2802         -1,
   2803     },
   2804 #endif /* chips */
   2805 
   2806 #if defined(BCM_88690_A0)
   2807     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
   2808         soc_block_list[73],
   2809         soc_genreg,
   2810         1,
   2811         0,
   2812         0x1f,
   2813         0,
   2814         0,
   2815         1,
   2816         soc_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
   2817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2818         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2819         -1,
   2820         -1,
   2821     },
   2822 #endif /* chips */
   2823 
   2824 #if defined(BCM_88690_B0)
   2825     { /* SOC_REG_INT_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   2826         soc_block_list[73],
   2827         soc_genreg,
   2828         1,
   2829         0,
   2830         0x1f,
   2831         0,
   2832         0,
   2833         1,
   2834         soc_KAPS_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   2835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2836         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2837         -1,
   2838         -1,
   2839     },
   2840 #endif /* chips */
   2841 
   2842 #if defined(BCM_88470_A0)
   2843     { /* SOC_REG_INT_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESSr */
   2844         soc_block_list[73],
   2845         soc_genreg,
   2846         1,
   2847         0,
   2848         0x84,
   2849         0,
   2850         0,
   2851         1,
   2852         soc_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
   2853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2854         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2855         -1,
   2856         -1,
   2857     },
   2858 #endif /* chips */
   2859 
   2860 #if defined(BCM_88270_A0)
   2861     { /* SOC_REG_INT_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88270_A0r */
   2862         soc_block_list[73],
   2863         soc_genreg,
   2864         1,
   2865         0,
   2866         0x84,
   2867         0,
   2868         0,
   2869         1,
   2870         soc_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88270_A0r_fields,
   2871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2872         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2873         -1,
   2874         -1,
   2875     },
   2876 #endif /* chips */
   2877 
   2878 #if defined(BCM_88470_B0)
   2879     { /* SOC_REG_INT_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_B0r */
   2880         soc_block_list[73],
   2881         soc_genreg,
   2882         1,
   2883         0,
   2884         0x84,
   2885         0,
   2886         0,
   2887         1,
   2888         soc_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88470_B0r_fields,
   2889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2890         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2891         -1,
   2892         -1,
   2893     },
   2894 #endif /* chips */
   2895 
   2896 #if defined(BCM_88680_A0)
   2897     { /* SOC_REG_INT_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r */
   2898         soc_block_list[73],
   2899         soc_genreg,
   2900         1,
   2901         0,
   2902         0x84,
   2903         0,
   2904         0,
   2905         1,
   2906         soc_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r_fields,
   2907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2908         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2909         -1,
   2910         -1,
   2911     },
   2912 #endif /* chips */
   2913 
   2914 #if defined(BCM_88690_A0)
   2915     { /* SOC_REG_INT_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r */
   2916         soc_block_list[73],
   2917         soc_genreg,
   2918         1,
   2919         0,
   2920         0x84,
   2921         0,
   2922         0,
   2923         1,
   2924         soc_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r_fields,
   2925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2926         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2927         -1,
   2928         -1,
   2929     },
   2930 #endif /* chips */
   2931 
   2932 #if defined(BCM_88690_B0)
   2933     { /* SOC_REG_INT_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r */
   2934         soc_block_list[73],
   2935         soc_genreg,
   2936         1,
   2937         0,
   2938         0x84,
   2939         0,
   2940         0,
   2941         1,
   2942         soc_KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r_fields,
   2943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2944         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2945         -1,
   2946         -1,
   2947     },
   2948 #endif /* chips */
   2949 
   2950 #if defined(BCM_88470_A0)
   2951     { /* SOC_REG_INT_KAPS_ERROR_INITIATION_DATAr */
   2952         soc_block_list[73],
   2953         soc_genreg,
   2954         1,
   2955         0,
   2956         0xa3,
   2957         0,
   2958         0,
   2959         1,
   2960         soc_KAPS_ERROR_INITIATION_DATAr_fields,
   2961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2962         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2963         -1,
   2964         -1,
   2965     },
   2966 #endif /* chips */
   2967 
   2968 #if defined(BCM_88270_A0)
   2969     { /* SOC_REG_INT_KAPS_ERROR_INITIATION_DATA_BCM88270_A0r */
   2970         soc_block_list[73],
   2971         soc_genreg,
   2972         1,
   2973         0,
   2974         0xa3,
   2975         0,
   2976         0,
   2977         1,
   2978         soc_KAPS_ERROR_INITIATION_DATA_BCM88270_A0r_fields,
   2979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2980         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2981         -1,
   2982         -1,
   2983     },
   2984 #endif /* chips */
   2985 
   2986 #if defined(BCM_88470_B0)
   2987     { /* SOC_REG_INT_KAPS_ERROR_INITIATION_DATA_BCM88470_B0r */
   2988         soc_block_list[73],
   2989         soc_genreg,
   2990         1,
   2991         0,
   2992         0xa3,
   2993         0,
   2994         0,
   2995         1,
   2996         soc_KAPS_ERROR_INITIATION_DATA_BCM88470_B0r_fields,
   2997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2998         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2999         -1,
   3000         -1,
   3001     },
   3002 #endif /* chips */
   3003 
   3004 #if defined(BCM_88680_A0)
   3005     { /* SOC_REG_INT_KAPS_ERROR_INITIATION_DATA_BCM88680_A0r */
   3006         soc_block_list[73],
   3007         soc_genreg,
   3008         1,
   3009         0,
   3010         0xa3,
   3011         0,
   3012         0,
   3013         1,
   3014         soc_KAPS_ERROR_INITIATION_DATA_BCM88680_A0r_fields,
   3015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3016         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3017         -1,
   3018         -1,
   3019     },
   3020 #endif /* chips */
   3021 
   3022 #if defined(BCM_88690_A0)
   3023     { /* SOC_REG_INT_KAPS_ERROR_INITIATION_DATA_BCM88690_A0r */
   3024         soc_block_list[73],
   3025         soc_genreg,
   3026         1,
   3027         0,
   3028         0xa3,
   3029         0,
   3030         0,
   3031         1,
   3032         soc_KAPS_ERROR_INITIATION_DATA_BCM88690_A0r_fields,
   3033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3034         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3035         -1,
   3036         -1,
   3037     },
   3038 #endif /* chips */
   3039 
   3040 #if defined(BCM_88690_B0)
   3041     { /* SOC_REG_INT_KAPS_ERROR_INITIATION_DATA_BCM88690_B0r */
   3042         soc_block_list[73],
   3043         soc_genreg,
   3044         1,
   3045         0,
   3046         0xa3,
   3047         0,
   3048         0,
   3049         1,
   3050         soc_KAPS_ERROR_INITIATION_DATA_BCM88690_B0r_fields,
   3051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3052         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3053         -1,
   3054         -1,
   3055     },
   3056 #endif /* chips */
   3057 
   3058 #if defined(BCM_88675_A0)
   3059     { /* SOC_REG_INT_KAPS_GLOBAL_DEBUGr */
   3060         soc_block_list[73],
   3061         soc_genreg,
   3062         1,
   3063         0,
   3064         0x8500,
   3065         0,
   3066         0,
   3067         1,
   3068         soc_KAPS_GLOBAL_DEBUGr_fields,
   3069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3070         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3071         -1,
   3072         -1,
   3073     },
   3074 #endif /* chips */
   3075 
   3076 #if defined(BCM_88375_A0)
   3077     { /* SOC_REG_INT_KAPS_GLOBAL_DEBUG_BCM88375_A0r */
   3078         soc_block_list[73],
   3079         soc_genreg,
   3080         1,
   3081         0,
   3082         0x8500,
   3083         0,
   3084         0,
   3085         1,
   3086         soc_KAPS_GLOBAL_DEBUG_BCM88375_A0r_fields,
   3087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3088         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3089         -1,
   3090         -1,
   3091     },
   3092 #endif /* chips */
   3093 
   3094 #if defined(BCM_88375_B0)
   3095     { /* SOC_REG_INT_KAPS_GLOBAL_DEBUG_BCM88375_B0r */
   3096         soc_block_list[73],
   3097         soc_genreg,
   3098         1,
   3099         0,
   3100         0x8500,
   3101         0,
   3102         0,
   3103         1,
   3104         soc_KAPS_GLOBAL_DEBUG_BCM88375_B0r_fields,
   3105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3106         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3107         -1,
   3108         -1,
   3109     },
   3110 #endif /* chips */
   3111 
   3112 #if defined(BCM_88675_B0)
   3113     { /* SOC_REG_INT_KAPS_GLOBAL_DEBUG_BCM88675_B0r */
   3114         soc_block_list[73],
   3115         soc_genreg,
   3116         1,
   3117         0,
   3118         0x8500,
   3119         0,
   3120         0,
   3121         1,
   3122         soc_KAPS_GLOBAL_DEBUG_BCM88675_B0r_fields,
   3123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3124         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3125         -1,
   3126         -1,
   3127     },
   3128 #endif /* chips */
   3129 
   3130 #if defined(BCM_88675_A0)
   3131     { /* SOC_REG_INT_KAPS_GLOBAL_EVENTr */
   3132         soc_block_list[73],
   3133         soc_genreg,
   3134         1,
   3135         0,
   3136         0x300,
   3137         0,
   3138         0,
   3139         24,
   3140         soc_KAPS_GLOBAL_EVENTr_fields,
   3141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3142         SOC_RESET_MASK_DEC(0x1fffc1ff, 0x00000000)
   3143         -1,
   3144         -1,
   3145     },
   3146 #endif /* chips */
   3147 
   3148 #if defined(BCM_88375_A0)
   3149     { /* SOC_REG_INT_KAPS_GLOBAL_EVENT_BCM88375_A0r */
   3150         soc_block_list[73],
   3151         soc_genreg,
   3152         1,
   3153         0,
   3154         0x300,
   3155         0,
   3156         0,
   3157         24,
   3158         soc_KAPS_GLOBAL_EVENT_BCM88375_A0r_fields,
   3159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3160         SOC_RESET_MASK_DEC(0x1fffc1ff, 0x00000000)
   3161         -1,
   3162         -1,
   3163     },
   3164 #endif /* chips */
   3165 
   3166 #if defined(BCM_88375_B0)
   3167     { /* SOC_REG_INT_KAPS_GLOBAL_EVENT_BCM88375_B0r */
   3168         soc_block_list[73],
   3169         soc_genreg,
   3170         1,
   3171         0,
   3172         0x300,
   3173         0,
   3174         0,
   3175         24,
   3176         soc_KAPS_GLOBAL_EVENT_BCM88375_B0r_fields,
   3177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3178         SOC_RESET_MASK_DEC(0x1fffc1ff, 0x00000000)
   3179         -1,
   3180         -1,
   3181     },
   3182 #endif /* chips */
   3183 
   3184 #if defined(BCM_88675_B0)
   3185     { /* SOC_REG_INT_KAPS_GLOBAL_EVENT_BCM88675_B0r */
   3186         soc_block_list[73],
   3187         soc_genreg,
   3188         1,
   3189         0,
   3190         0x300,
   3191         0,
   3192         0,
   3193         24,
   3194         soc_KAPS_GLOBAL_EVENT_BCM88675_B0r_fields,
   3195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3196         SOC_RESET_MASK_DEC(0x1fffc1ff, 0x00000000)
   3197         -1,
   3198         -1,
   3199     },
   3200 #endif /* chips */
   3201 
   3202 #if defined(BCM_88675_A0)
   3203     { /* SOC_REG_INT_KAPS_GLOBAL_EVENT_MASKr */
   3204         soc_block_list[73],
   3205         soc_genreg,
   3206         1,
   3207         0,
   3208         0x400,
   3209         0,
   3210         0,
   3211         24,
   3212         soc_KAPS_GLOBAL_EVENT_MASKr_fields,
   3213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3214         SOC_RESET_MASK_DEC(0x1fffc1ff, 0x00000000)
   3215         -1,
   3216         -1,
   3217     },
   3218 #endif /* chips */
   3219 
   3220 #if defined(BCM_88375_A0)
   3221     { /* SOC_REG_INT_KAPS_GLOBAL_EVENT_MASK_BCM88375_A0r */
   3222         soc_block_list[73],
   3223         soc_genreg,
   3224         1,
   3225         0,
   3226         0x400,
   3227         0,
   3228         0,
   3229         24,
   3230         soc_KAPS_GLOBAL_EVENT_MASK_BCM88375_A0r_fields,
   3231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3232         SOC_RESET_MASK_DEC(0x1fffc1ff, 0x00000000)
   3233         -1,
   3234         -1,
   3235     },
   3236 #endif /* chips */
   3237 
   3238 #if defined(BCM_88375_B0)
   3239     { /* SOC_REG_INT_KAPS_GLOBAL_EVENT_MASK_BCM88375_B0r */
   3240         soc_block_list[73],
   3241         soc_genreg,
   3242         1,
   3243         0,
   3244         0x400,
   3245         0,
   3246         0,
   3247         24,
   3248         soc_KAPS_GLOBAL_EVENT_MASK_BCM88375_B0r_fields,
   3249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3250         SOC_RESET_MASK_DEC(0x1fffc1ff, 0x00000000)
   3251         -1,
   3252         -1,
   3253     },
   3254 #endif /* chips */
   3255 
   3256 #if defined(BCM_88675_B0)
   3257     { /* SOC_REG_INT_KAPS_GLOBAL_EVENT_MASK_BCM88675_B0r */
   3258         soc_block_list[73],
   3259         soc_genreg,
   3260         1,
   3261         0,
   3262         0x400,
   3263         0,
   3264         0,
   3265         24,
   3266         soc_KAPS_GLOBAL_EVENT_MASK_BCM88675_B0r_fields,
   3267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3268         SOC_RESET_MASK_DEC(0x1fffc1ff, 0x00000000)
   3269         -1,
   3270         -1,
   3271     },
   3272 #endif /* chips */
   3273 
   3274 #if defined(BCM_88470_A0)
   3275     { /* SOC_REG_INT_KAPS_GLOBAL_MEM_OPTIONSr */
   3276         soc_block_list[73],
   3277         soc_genreg,
   3278         1,
   3279         0,
   3280         0xc0,
   3281         0,
   3282         0,
   3283         6,
   3284         soc_KAPS_GLOBAL_MEM_OPTIONSr_fields,
   3285         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   3286         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3287         -1,
   3288         -1,
   3289     },
   3290 #endif /* chips */
   3291 
   3292 #if defined(BCM_88270_A0)
   3293     { /* SOC_REG_INT_KAPS_GLOBAL_MEM_OPTIONS_BCM88270_A0r */
   3294         soc_block_list[73],
   3295         soc_genreg,
   3296         1,
   3297         0,
   3298         0xc0,
   3299         0,
   3300         0,
   3301         6,
   3302         soc_KAPS_GLOBAL_MEM_OPTIONS_BCM88270_A0r_fields,
   3303         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   3304         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3305         -1,
   3306         -1,
   3307     },
   3308 #endif /* chips */
   3309 
   3310 #if defined(BCM_88470_B0)
   3311     { /* SOC_REG_INT_KAPS_GLOBAL_MEM_OPTIONS_BCM88470_B0r */
   3312         soc_block_list[73],
   3313         soc_genreg,
   3314         1,
   3315         0,
   3316         0xc0,
   3317         0,
   3318         0,
   3319         6,
   3320         soc_KAPS_GLOBAL_MEM_OPTIONS_BCM88470_B0r_fields,
   3321         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   3322         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3323         -1,
   3324         -1,
   3325     },
   3326 #endif /* chips */
   3327 
   3328 #if defined(BCM_88680_A0)
   3329     { /* SOC_REG_INT_KAPS_GLOBAL_MEM_OPTIONS_BCM88680_A0r */
   3330         soc_block_list[73],
   3331         soc_genreg,
   3332         1,
   3333         0,
   3334         0xc0,
   3335         0,
   3336         0,
   3337         4,
   3338         soc_KAPS_GLOBAL_MEM_OPTIONS_BCM88680_A0r_fields,
   3339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3340         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3341         -1,
   3342         -1,
   3343     },
   3344 #endif /* chips */
   3345 
   3346 #if defined(BCM_88470_A0)
   3347     { /* SOC_REG_INT_KAPS_GTIMER_CONFIGURATIONr */
   3348         soc_block_list[73],
   3349         soc_genreg,
   3350         1,
   3351         0,
   3352         0x88,
   3353         SOC_REG_FLAG_64_BITS,
   3354         0,
   3355         4,
   3356         soc_KAPS_GTIMER_CONFIGURATIONr_fields,
   3357         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   3358         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   3359         -1,
   3360         -1,
   3361     },
   3362 #endif /* chips */
   3363 
   3364 #if defined(BCM_88270_A0)
   3365     { /* SOC_REG_INT_KAPS_GTIMER_CONFIGURATION_BCM88270_A0r */
   3366         soc_block_list[73],
   3367         soc_genreg,
   3368         1,
   3369         0,
   3370         0x88,
   3371         SOC_REG_FLAG_64_BITS,
   3372         0,
   3373         4,
   3374         soc_KAPS_GTIMER_CONFIGURATION_BCM88270_A0r_fields,
   3375         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   3376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   3377         -1,
   3378         -1,
   3379     },
   3380 #endif /* chips */
   3381 
   3382 #if defined(BCM_88470_B0)
   3383     { /* SOC_REG_INT_KAPS_GTIMER_CONFIGURATION_BCM88470_B0r */
   3384         soc_block_list[73],
   3385         soc_genreg,
   3386         1,
   3387         0,
   3388         0x88,
   3389         SOC_REG_FLAG_64_BITS,
   3390         0,
   3391         4,
   3392         soc_KAPS_GTIMER_CONFIGURATION_BCM88470_B0r_fields,
   3393         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   3394         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   3395         -1,
   3396         -1,
   3397     },
   3398 #endif /* chips */
   3399 
   3400 #if defined(BCM_88680_A0)
   3401     { /* SOC_REG_INT_KAPS_GTIMER_CONFIGURATION_BCM88680_A0r */
   3402         soc_block_list[73],
   3403         soc_genreg,
   3404         1,
   3405         0,
   3406         0x88,
   3407         0,
   3408         0,
   3409         3,
   3410         soc_KAPS_GTIMER_CONFIGURATION_BCM88680_A0r_fields,
   3411         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   3412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3413         -1,
   3414         -1,
   3415     },
   3416 #endif /* chips */
   3417 
   3418 #if defined(BCM_88690_A0)
   3419     { /* SOC_REG_INT_KAPS_GTIMER_CONFIGURATION_BCM88690_A0r */
   3420         soc_block_list[73],
   3421         soc_genreg,
   3422         1,
   3423         0,
   3424         0x89,
   3425         0,
   3426         0,
   3427         3,
   3428         soc_KAPS_GTIMER_CONFIGURATION_BCM88690_A0r_fields,
   3429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3430         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3431         -1,
   3432         -1,
   3433     },
   3434 #endif /* chips */
   3435 
   3436 #if defined(BCM_88690_B0)
   3437     { /* SOC_REG_INT_KAPS_GTIMER_CONFIGURATION_BCM88690_B0r */
   3438         soc_block_list[73],
   3439         soc_genreg,
   3440         1,
   3441         0,
   3442         0x89,
   3443         0,
   3444         0,
   3445         3,
   3446         soc_KAPS_GTIMER_CONFIGURATION_BCM88690_B0r_fields,
   3447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3448         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3449         -1,
   3450         -1,
   3451     },
   3452 #endif /* chips */
   3453 
   3454 #if defined(BCM_88690_A0)
   3455     { /* SOC_REG_INT_KAPS_GTIMER_CYCLEr */
   3456         soc_block_list[73],
   3457         soc_genreg,
   3458         1,
   3459         0,
   3460         0x88,
   3461         0,
   3462         0,
   3463         1,
   3464         soc_KAPS_GTIMER_CYCLEr_fields,
   3465         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   3466         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3467         -1,
   3468         -1,
   3469     },
   3470 #endif /* chips */
   3471 
   3472 #if defined(BCM_88690_B0)
   3473     { /* SOC_REG_INT_KAPS_GTIMER_CYCLE_BCM88690_B0r */
   3474         soc_block_list[73],
   3475         soc_genreg,
   3476         1,
   3477         0,
   3478         0x88,
   3479         0,
   3480         0,
   3481         1,
   3482         soc_KAPS_GTIMER_CYCLE_BCM88690_B0r_fields,
   3483         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   3484         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3485         -1,
   3486         -1,
   3487     },
   3488 #endif /* chips */
   3489 
   3490 #if defined(BCM_88680_A0)
   3491     { /* SOC_REG_INT_KAPS_GTIMER_TRIGGERr */
   3492         soc_block_list[73],
   3493         soc_genreg,
   3494         1,
   3495         0,
   3496         0x89,
   3497         SOC_REG_FLAG_RO,
   3498         0,
   3499         1,
   3500         soc_KAPS_GTIMER_TRIGGERr_fields,
   3501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3502         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3503         -1,
   3504         -1,
   3505     },
   3506 #endif /* chips */
   3507 
   3508 #if defined(BCM_88270_A0)
   3509     { /* SOC_REG_INT_KAPS_HITBIT_COMMANDS_LINEr */
   3510         soc_block_list[73],
   3511         soc_genreg,
   3512         1,
   3513         0,
   3514         0x140,
   3515         SOC_REG_FLAG_ABOVE_64_BITS |
   3516                           SOC_REG_FLAG_SIGNAL,
   3517         0,
   3518         14,
   3519         soc_KAPS_HITBIT_COMMANDS_LINEr_fields,
   3520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3522         -1,
   3523         -1,
   3524     },
   3525 #endif /* chips */
   3526 
   3527 #if defined(BCM_88680_A0)
   3528     { /* SOC_REG_INT_KAPS_HITBIT_COMMANDS_LINE_BCM88680_A0r */
   3529         soc_block_list[73],
   3530         soc_genreg,
   3531         1,
   3532         0,
   3533         0x186,
   3534         SOC_REG_FLAG_ABOVE_64_BITS |
   3535                           SOC_REG_FLAG_SIGNAL,
   3536         0,
   3537         14,
   3538         soc_KAPS_HITBIT_COMMANDS_LINE_BCM88680_A0r_fields,
   3539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3540         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3541         -1,
   3542         -1,
   3543     },
   3544 #endif /* chips */
   3545 
   3546 #if defined(BCM_88270_A0)
   3547     { /* SOC_REG_INT_KAPS_HITBIT_CONTROLr */
   3548         soc_block_list[73],
   3549         soc_genreg,
   3550         1,
   3551         0,
   3552         0x142,
   3553         0,
   3554         0,
   3555         3,
   3556         soc_KAPS_HITBIT_CONTROLr_fields,
   3557         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
   3558         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3559         -1,
   3560         -1,
   3561     },
   3562 #endif /* chips */
   3563 
   3564 #if defined(BCM_88680_A0)
   3565     { /* SOC_REG_INT_KAPS_HITBIT_CONTROL_BCM88680_A0r */
   3566         soc_block_list[73],
   3567         soc_genreg,
   3568         1,
   3569         0,
   3570         0x188,
   3571         0,
   3572         0,
   3573         3,
   3574         soc_KAPS_HITBIT_CONTROL_BCM88680_A0r_fields,
   3575         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
   3576         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3577         -1,
   3578         -1,
   3579     },
   3580 #endif /* chips */
   3581 
   3582 #if defined(BCM_88270_A0)
   3583     { /* SOC_REG_INT_KAPS_HITBIT_REPLYS_LINEr */
   3584         soc_block_list[73],
   3585         soc_genreg,
   3586         1,
   3587         0,
   3588         0x141,
   3589         SOC_REG_FLAG_ABOVE_64_BITS |
   3590                           SOC_REG_FLAG_RO |
   3591                           SOC_REG_FLAG_SIGNAL,
   3592         0,
   3593         1,
   3594         soc_KAPS_HITBIT_REPLYS_LINEr_fields,
   3595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3596         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3597         -1,
   3598         -1,
   3599     },
   3600 #endif /* chips */
   3601 
   3602 #if defined(BCM_88680_A0)
   3603     { /* SOC_REG_INT_KAPS_HITBIT_REPLYS_LINE_BCM88680_A0r */
   3604         soc_block_list[73],
   3605         soc_genreg,
   3606         1,
   3607         0,
   3608         0x187,
   3609         SOC_REG_FLAG_ABOVE_64_BITS |
   3610                           SOC_REG_FLAG_RO |
   3611                           SOC_REG_FLAG_SIGNAL,
   3612         0,
   3613         1,
   3614         soc_KAPS_HITBIT_REPLYS_LINE_BCM88680_A0r_fields,
   3615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3616         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3617         -1,
   3618         -1,
   3619     },
   3620 #endif /* chips */
   3621 
   3622 #if defined(BCM_88270_A0)
   3623     { /* SOC_REG_INT_KAPS_HITBIT_STM_LAST_CMD_DEBUGr */
   3624         soc_block_list[73],
   3625         soc_genreg,
   3626         2,
   3627         0,
   3628         0x143,
   3629         SOC_REG_FLAG_ABOVE_64_BITS |
   3630                           SOC_REG_FLAG_ARRAY |
   3631                           SOC_REG_FLAG_RO |
   3632                           SOC_REG_FLAG_REG_ARRAY |
   3633                           SOC_REG_FLAG_SIGNAL,
   3634         0,
   3635         22,
   3636         soc_KAPS_HITBIT_STM_LAST_CMD_DEBUGr_fields,
   3637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3638         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3639         -1,
   3640         -1,
   3641     },
   3642 #endif /* chips */
   3643 
   3644 #if defined(BCM_88680_A0)
   3645     { /* SOC_REG_INT_KAPS_HITBIT_STM_LAST_CMD_DEBUG_BCM88680_A0r */
   3646         soc_block_list[73],
   3647         soc_genreg,
   3648         2,
   3649         0,
   3650         0x189,
   3651         SOC_REG_FLAG_ABOVE_64_BITS |
   3652                           SOC_REG_FLAG_ARRAY |
   3653                           SOC_REG_FLAG_RO |
   3654                           SOC_REG_FLAG_REG_ARRAY |
   3655                           SOC_REG_FLAG_SIGNAL,
   3656         0,
   3657         22,
   3658         soc_KAPS_HITBIT_STM_LAST_CMD_DEBUG_BCM88680_A0r_fields,
   3659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3661         -1,
   3662         -1,
   3663     },
   3664 #endif /* chips */
   3665 
   3666 #if defined(BCM_88675_A0)
   3667     { /* SOC_REG_INT_KAPS_IBC_COMMAND_DATAr */
   3668         soc_block_list[73],
   3669         soc_genreg,
   3670         15,
   3671         0,
   3672         0x4000,
   3673         SOC_REG_FLAG_ARRAY |
   3674                           SOC_REG_FLAG_REG_ARRAY,
   3675         0,
   3676         1,
   3677         soc_KAPS_IBC_COMMAND_DATAr_fields,
   3678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3680         -1,
   3681         -1,
   3682     },
   3683 #endif /* chips */
   3684 
   3685 #if defined(BCM_88375_A0)
   3686     { /* SOC_REG_INT_KAPS_IBC_COMMAND_DATA_BCM88375_A0r */
   3687         soc_block_list[73],
   3688         soc_genreg,
   3689         15,
   3690         0,
   3691         0x4000,
   3692         SOC_REG_FLAG_ARRAY |
   3693                           SOC_REG_FLAG_REG_ARRAY,
   3694         0,
   3695         1,
   3696         soc_KAPS_IBC_COMMAND_DATA_BCM88375_A0r_fields,
   3697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3698         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3699         -1,
   3700         -1,
   3701     },
   3702 #endif /* chips */
   3703 
   3704 #if defined(BCM_88375_B0)
   3705     { /* SOC_REG_INT_KAPS_IBC_COMMAND_DATA_BCM88375_B0r */
   3706         soc_block_list[73],
   3707         soc_genreg,
   3708         15,
   3709         0,
   3710         0x4000,
   3711         SOC_REG_FLAG_ARRAY |
   3712                           SOC_REG_FLAG_REG_ARRAY,
   3713         0,
   3714         1,
   3715         soc_KAPS_IBC_COMMAND_DATA_BCM88375_B0r_fields,
   3716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3718         -1,
   3719         -1,
   3720     },
   3721 #endif /* chips */
   3722 
   3723 #if defined(BCM_88675_B0)
   3724     { /* SOC_REG_INT_KAPS_IBC_COMMAND_DATA_BCM88675_B0r */
   3725         soc_block_list[73],
   3726         soc_genreg,
   3727         15,
   3728         0,
   3729         0x4000,
   3730         SOC_REG_FLAG_ARRAY |
   3731                           SOC_REG_FLAG_REG_ARRAY,
   3732         0,
   3733         1,
   3734         soc_KAPS_IBC_COMMAND_DATA_BCM88675_B0r_fields,
   3735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3736         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3737         -1,
   3738         -1,
   3739     },
   3740 #endif /* chips */
   3741 
   3742 #if defined(BCM_88675_A0)
   3743     { /* SOC_REG_INT_KAPS_IBC_COMMAND_WORDr */
   3744         soc_block_list[73],
   3745         soc_genreg,
   3746         1,
   3747         0,
   3748         0x4f00,
   3749         0,
   3750         0,
   3751         4,
   3752         soc_KAPS_IBC_COMMAND_WORDr_fields,
   3753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3754         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3755         -1,
   3756         -1,
   3757     },
   3758 #endif /* chips */
   3759 
   3760 #if defined(BCM_88375_A0)
   3761     { /* SOC_REG_INT_KAPS_IBC_COMMAND_WORD_BCM88375_A0r */
   3762         soc_block_list[73],
   3763         soc_genreg,
   3764         1,
   3765         0,
   3766         0x4f00,
   3767         0,
   3768         0,
   3769         4,
   3770         soc_KAPS_IBC_COMMAND_WORD_BCM88375_A0r_fields,
   3771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3772         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3773         -1,
   3774         -1,
   3775     },
   3776 #endif /* chips */
   3777 
   3778 #if defined(BCM_88375_B0)
   3779     { /* SOC_REG_INT_KAPS_IBC_COMMAND_WORD_BCM88375_B0r */
   3780         soc_block_list[73],
   3781         soc_genreg,
   3782         1,
   3783         0,
   3784         0x4f00,
   3785         0,
   3786         0,
   3787         4,
   3788         soc_KAPS_IBC_COMMAND_WORD_BCM88375_B0r_fields,
   3789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3791         -1,
   3792         -1,
   3793     },
   3794 #endif /* chips */
   3795 
   3796 #if defined(BCM_88675_B0)
   3797     { /* SOC_REG_INT_KAPS_IBC_COMMAND_WORD_BCM88675_B0r */
   3798         soc_block_list[73],
   3799         soc_genreg,
   3800         1,
   3801         0,
   3802         0x4f00,
   3803         0,
   3804         0,
   3805         4,
   3806         soc_KAPS_IBC_COMMAND_WORD_BCM88675_B0r_fields,
   3807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3808         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3809         -1,
   3810         -1,
   3811     },
   3812 #endif /* chips */
   3813 
   3814 #if defined(BCM_88675_A0)
   3815     { /* SOC_REG_INT_KAPS_IBC_CONFIGr */
   3816         soc_block_list[73],
   3817         soc_genreg,
   3818         1,
   3819         0,
   3820         0x200,
   3821         0,
   3822         0,
   3823         2,
   3824         soc_KAPS_IBC_CONFIGr_fields,
   3825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3826         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   3827         -1,
   3828         -1,
   3829     },
   3830 #endif /* chips */
   3831 
   3832 #if defined(BCM_88375_A0)
   3833     { /* SOC_REG_INT_KAPS_IBC_CONFIG_BCM88375_A0r */
   3834         soc_block_list[73],
   3835         soc_genreg,
   3836         1,
   3837         0,
   3838         0x200,
   3839         0,
   3840         0,
   3841         2,
   3842         soc_KAPS_IBC_CONFIG_BCM88375_A0r_fields,
   3843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3844         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   3845         -1,
   3846         -1,
   3847     },
   3848 #endif /* chips */
   3849 
   3850 #if defined(BCM_88375_B0)
   3851     { /* SOC_REG_INT_KAPS_IBC_CONFIG_BCM88375_B0r */
   3852         soc_block_list[73],
   3853         soc_genreg,
   3854         1,
   3855         0,
   3856         0x200,
   3857         0,
   3858         0,
   3859         2,
   3860         soc_KAPS_IBC_CONFIG_BCM88375_B0r_fields,
   3861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3862         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   3863         -1,
   3864         -1,
   3865     },
   3866 #endif /* chips */
   3867 
   3868 #if defined(BCM_88675_B0)
   3869     { /* SOC_REG_INT_KAPS_IBC_CONFIG_BCM88675_B0r */
   3870         soc_block_list[73],
   3871         soc_genreg,
   3872         1,
   3873         0,
   3874         0x200,
   3875         0,
   3876         0,
   3877         2,
   3878         soc_KAPS_IBC_CONFIG_BCM88675_B0r_fields,
   3879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3880         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   3881         -1,
   3882         -1,
   3883     },
   3884 #endif /* chips */
   3885 
   3886 #if defined(BCM_88675_A0)
   3887     { /* SOC_REG_INT_KAPS_IBC_FIFO_CORRECTABLE_STATUSr */
   3888         soc_block_list[73],
   3889         soc_genreg,
   3890         1,
   3891         0,
   3892         0x6300,
   3893         SOC_REG_FLAG_RO,
   3894         0,
   3895         3,
   3896         soc_KAPS_IBC_FIFO_CORRECTABLE_STATUSr_fields,
   3897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3898         SOC_RESET_MASK_DEC(0x400007ff, 0x00000000)
   3899         -1,
   3900         -1,
   3901     },
   3902 #endif /* chips */
   3903 
   3904 #if defined(BCM_88375_A0)
   3905     { /* SOC_REG_INT_KAPS_IBC_FIFO_CORRECTABLE_STATUS_BCM88375_A0r */
   3906         soc_block_list[73],
   3907         soc_genreg,
   3908         1,
   3909         0,
   3910         0x6300,
   3911         SOC_REG_FLAG_RO,
   3912         0,
   3913         3,
   3914         soc_KAPS_IBC_FIFO_CORRECTABLE_STATUS_BCM88375_A0r_fields,
   3915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3916         SOC_RESET_MASK_DEC(0x400007ff, 0x00000000)
   3917         -1,
   3918         -1,
   3919     },
   3920 #endif /* chips */
   3921 
   3922 #if defined(BCM_88375_B0)
   3923     { /* SOC_REG_INT_KAPS_IBC_FIFO_CORRECTABLE_STATUS_BCM88375_B0r */
   3924         soc_block_list[73],
   3925         soc_genreg,
   3926         1,
   3927         0,
   3928         0x6300,
   3929         SOC_REG_FLAG_RO,
   3930         0,
   3931         3,
   3932         soc_KAPS_IBC_FIFO_CORRECTABLE_STATUS_BCM88375_B0r_fields,
   3933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3934         SOC_RESET_MASK_DEC(0x400007ff, 0x00000000)
   3935         -1,
   3936         -1,
   3937     },
   3938 #endif /* chips */
   3939 
   3940 #if defined(BCM_88675_B0)
   3941     { /* SOC_REG_INT_KAPS_IBC_FIFO_CORRECTABLE_STATUS_BCM88675_B0r */
   3942         soc_block_list[73],
   3943         soc_genreg,
   3944         1,
   3945         0,
   3946         0x6300,
   3947         SOC_REG_FLAG_RO,
   3948         0,
   3949         3,
   3950         soc_KAPS_IBC_FIFO_CORRECTABLE_STATUS_BCM88675_B0r_fields,
   3951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3952         SOC_RESET_MASK_DEC(0x400007ff, 0x00000000)
   3953         -1,
   3954         -1,
   3955     },
   3956 #endif /* chips */
   3957 
   3958 #if defined(BCM_88675_A0)
   3959     { /* SOC_REG_INT_KAPS_IBC_FIFO_ECC_DEBUGr */
   3960         soc_block_list[73],
   3961         soc_genreg,
   3962         1,
   3963         0,
   3964         0x6200,
   3965         0,
   3966         0,
   3967         4,
   3968         soc_KAPS_IBC_FIFO_ECC_DEBUGr_fields,
   3969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3970         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3971         -1,
   3972         -1,
   3973     },
   3974 #endif /* chips */
   3975 
   3976 #if defined(BCM_88375_A0)
   3977     { /* SOC_REG_INT_KAPS_IBC_FIFO_ECC_DEBUG_BCM88375_A0r */
   3978         soc_block_list[73],
   3979         soc_genreg,
   3980         1,
   3981         0,
   3982         0x6200,
   3983         0,
   3984         0,
   3985         4,
   3986         soc_KAPS_IBC_FIFO_ECC_DEBUG_BCM88375_A0r_fields,
   3987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3988         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3989         -1,
   3990         -1,
   3991     },
   3992 #endif /* chips */
   3993 
   3994 #if defined(BCM_88375_B0)
   3995     { /* SOC_REG_INT_KAPS_IBC_FIFO_ECC_DEBUG_BCM88375_B0r */
   3996         soc_block_list[73],
   3997         soc_genreg,
   3998         1,
   3999         0,
   4000         0x6200,
   4001         0,
   4002         0,
   4003         4,
   4004         soc_KAPS_IBC_FIFO_ECC_DEBUG_BCM88375_B0r_fields,
   4005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4006         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   4007         -1,
   4008         -1,
   4009     },
   4010 #endif /* chips */
   4011 
   4012 #if defined(BCM_88675_B0)
   4013     { /* SOC_REG_INT_KAPS_IBC_FIFO_ECC_DEBUG_BCM88675_B0r */
   4014         soc_block_list[73],
   4015         soc_genreg,
   4016         1,
   4017         0,
   4018         0x6200,
   4019         0,
   4020         0,
   4021         4,
   4022         soc_KAPS_IBC_FIFO_ECC_DEBUG_BCM88675_B0r_fields,
   4023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4024         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   4025         -1,
   4026         -1,
   4027     },
   4028 #endif /* chips */
   4029 
   4030 #if defined(BCM_88675_A0)
   4031     { /* SOC_REG_INT_KAPS_IBC_FIFO_MEM_CONTROLr */
   4032         soc_block_list[73],
   4033         soc_genreg,
   4034         1,
   4035         0,
   4036         0x6100,
   4037         0,
   4038         0,
   4039         4,
   4040         soc_KAPS_IBC_FIFO_MEM_CONTROLr_fields,
   4041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4042         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4043         -1,
   4044         -1,
   4045     },
   4046 #endif /* chips */
   4047 
   4048 #if defined(BCM_88375_A0)
   4049     { /* SOC_REG_INT_KAPS_IBC_FIFO_MEM_CONTROL_BCM88375_A0r */
   4050         soc_block_list[73],
   4051         soc_genreg,
   4052         1,
   4053         0,
   4054         0x6100,
   4055         0,
   4056         0,
   4057         4,
   4058         soc_KAPS_IBC_FIFO_MEM_CONTROL_BCM88375_A0r_fields,
   4059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4060         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4061         -1,
   4062         -1,
   4063     },
   4064 #endif /* chips */
   4065 
   4066 #if defined(BCM_88375_B0)
   4067     { /* SOC_REG_INT_KAPS_IBC_FIFO_MEM_CONTROL_BCM88375_B0r */
   4068         soc_block_list[73],
   4069         soc_genreg,
   4070         1,
   4071         0,
   4072         0x6100,
   4073         0,
   4074         0,
   4075         4,
   4076         soc_KAPS_IBC_FIFO_MEM_CONTROL_BCM88375_B0r_fields,
   4077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4078         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4079         -1,
   4080         -1,
   4081     },
   4082 #endif /* chips */
   4083 
   4084 #if defined(BCM_88675_B0)
   4085     { /* SOC_REG_INT_KAPS_IBC_FIFO_MEM_CONTROL_BCM88675_B0r */
   4086         soc_block_list[73],
   4087         soc_genreg,
   4088         1,
   4089         0,
   4090         0x6100,
   4091         0,
   4092         0,
   4093         4,
   4094         soc_KAPS_IBC_FIFO_MEM_CONTROL_BCM88675_B0r_fields,
   4095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4096         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4097         -1,
   4098         -1,
   4099     },
   4100 #endif /* chips */
   4101 
   4102 #if defined(BCM_88675_A0)
   4103     { /* SOC_REG_INT_KAPS_IBC_FIFO_TM_TEST_CTRLr */
   4104         soc_block_list[73],
   4105         soc_genreg,
   4106         1,
   4107         0,
   4108         0x8700,
   4109         0,
   4110         0,
   4111         1,
   4112         soc_KAPS_IBC_FIFO_TM_TEST_CTRLr_fields,
   4113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4114         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   4115         -1,
   4116         -1,
   4117     },
   4118 #endif /* chips */
   4119 
   4120 #if defined(BCM_88375_A0)
   4121     { /* SOC_REG_INT_KAPS_IBC_FIFO_TM_TEST_CTRL_BCM88375_A0r */
   4122         soc_block_list[73],
   4123         soc_genreg,
   4124         1,
   4125         0,
   4126         0x8700,
   4127         0,
   4128         0,
   4129         1,
   4130         soc_KAPS_IBC_FIFO_TM_TEST_CTRL_BCM88375_A0r_fields,
   4131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4132         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   4133         -1,
   4134         -1,
   4135     },
   4136 #endif /* chips */
   4137 
   4138 #if defined(BCM_88375_B0)
   4139     { /* SOC_REG_INT_KAPS_IBC_FIFO_TM_TEST_CTRL_BCM88375_B0r */
   4140         soc_block_list[73],
   4141         soc_genreg,
   4142         1,
   4143         0,
   4144         0x8700,
   4145         0,
   4146         0,
   4147         1,
   4148         soc_KAPS_IBC_FIFO_TM_TEST_CTRL_BCM88375_B0r_fields,
   4149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4150         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   4151         -1,
   4152         -1,
   4153     },
   4154 #endif /* chips */
   4155 
   4156 #if defined(BCM_88675_B0)
   4157     { /* SOC_REG_INT_KAPS_IBC_FIFO_TM_TEST_CTRL_BCM88675_B0r */
   4158         soc_block_list[73],
   4159         soc_genreg,
   4160         1,
   4161         0,
   4162         0x8700,
   4163         0,
   4164         0,
   4165         1,
   4166         soc_KAPS_IBC_FIFO_TM_TEST_CTRL_BCM88675_B0r_fields,
   4167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4168         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   4169         -1,
   4170         -1,
   4171     },
   4172 #endif /* chips */
   4173 
   4174 #if defined(BCM_88675_A0)
   4175     { /* SOC_REG_INT_KAPS_IBC_FIFO_UNCORRECTABLE_STATUSr */
   4176         soc_block_list[73],
   4177         soc_genreg,
   4178         1,
   4179         0,
   4180         0x6400,
   4181         SOC_REG_FLAG_RO,
   4182         0,
   4183         3,
   4184         soc_KAPS_IBC_FIFO_UNCORRECTABLE_STATUSr_fields,
   4185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4186         SOC_RESET_MASK_DEC(0x400007ff, 0x00000000)
   4187         -1,
   4188         -1,
   4189     },
   4190 #endif /* chips */
   4191 
   4192 #if defined(BCM_88375_A0)
   4193     { /* SOC_REG_INT_KAPS_IBC_FIFO_UNCORRECTABLE_STATUS_BCM88375_A0r */
   4194         soc_block_list[73],
   4195         soc_genreg,
   4196         1,
   4197         0,
   4198         0x6400,
   4199         SOC_REG_FLAG_RO,
   4200         0,
   4201         3,
   4202         soc_KAPS_IBC_FIFO_UNCORRECTABLE_STATUS_BCM88375_A0r_fields,
   4203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4204         SOC_RESET_MASK_DEC(0x400007ff, 0x00000000)
   4205         -1,
   4206         -1,
   4207     },
   4208 #endif /* chips */
   4209 
   4210 #if defined(BCM_88375_B0)
   4211     { /* SOC_REG_INT_KAPS_IBC_FIFO_UNCORRECTABLE_STATUS_BCM88375_B0r */
   4212         soc_block_list[73],
   4213         soc_genreg,
   4214         1,
   4215         0,
   4216         0x6400,
   4217         SOC_REG_FLAG_RO,
   4218         0,
   4219         3,
   4220         soc_KAPS_IBC_FIFO_UNCORRECTABLE_STATUS_BCM88375_B0r_fields,
   4221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4222         SOC_RESET_MASK_DEC(0x400007ff, 0x00000000)
   4223         -1,
   4224         -1,
   4225     },
   4226 #endif /* chips */
   4227 
   4228 #if defined(BCM_88675_B0)
   4229     { /* SOC_REG_INT_KAPS_IBC_FIFO_UNCORRECTABLE_STATUS_BCM88675_B0r */
   4230         soc_block_list[73],
   4231         soc_genreg,
   4232         1,
   4233         0,
   4234         0x6400,
   4235         SOC_REG_FLAG_RO,
   4236         0,
   4237         3,
   4238         soc_KAPS_IBC_FIFO_UNCORRECTABLE_STATUS_BCM88675_B0r_fields,
   4239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4240         SOC_RESET_MASK_DEC(0x400007ff, 0x00000000)
   4241         -1,
   4242         -1,
   4243     },
   4244 #endif /* chips */
   4245 
   4246 #if defined(BCM_88675_A0)
   4247     { /* SOC_REG_INT_KAPS_IBC_QUEUE_STATUSr */
   4248         soc_block_list[73],
   4249         soc_genreg,
   4250         1,
   4251         0,
   4252         0x6000,
   4253         SOC_REG_FLAG_RO,
   4254         0,
   4255         2,
   4256         soc_KAPS_IBC_QUEUE_STATUSr_fields,
   4257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4258         SOC_RESET_MASK_DEC(0x007f007f, 0x00000000)
   4259         -1,
   4260         -1,
   4261     },
   4262 #endif /* chips */
   4263 
   4264 #if defined(BCM_88375_A0)
   4265     { /* SOC_REG_INT_KAPS_IBC_QUEUE_STATUS_BCM88375_A0r */
   4266         soc_block_list[73],
   4267         soc_genreg,
   4268         1,
   4269         0,
   4270         0x6000,
   4271         SOC_REG_FLAG_RO,
   4272         0,
   4273         2,
   4274         soc_KAPS_IBC_QUEUE_STATUS_BCM88375_A0r_fields,
   4275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4276         SOC_RESET_MASK_DEC(0x007f007f, 0x00000000)
   4277         -1,
   4278         -1,
   4279     },
   4280 #endif /* chips */
   4281 
   4282 #if defined(BCM_88375_B0)
   4283     { /* SOC_REG_INT_KAPS_IBC_QUEUE_STATUS_BCM88375_B0r */
   4284         soc_block_list[73],
   4285         soc_genreg,
   4286         1,
   4287         0,
   4288         0x6000,
   4289         SOC_REG_FLAG_RO,
   4290         0,
   4291         2,
   4292         soc_KAPS_IBC_QUEUE_STATUS_BCM88375_B0r_fields,
   4293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4294         SOC_RESET_MASK_DEC(0x007f007f, 0x00000000)
   4295         -1,
   4296         -1,
   4297     },
   4298 #endif /* chips */
   4299 
   4300 #if defined(BCM_88675_B0)
   4301     { /* SOC_REG_INT_KAPS_IBC_QUEUE_STATUS_BCM88675_B0r */
   4302         soc_block_list[73],
   4303         soc_genreg,
   4304         1,
   4305         0,
   4306         0x6000,
   4307         SOC_REG_FLAG_RO,
   4308         0,
   4309         2,
   4310         soc_KAPS_IBC_QUEUE_STATUS_BCM88675_B0r_fields,
   4311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4312         SOC_RESET_MASK_DEC(0x007f007f, 0x00000000)
   4313         -1,
   4314         -1,
   4315     },
   4316 #endif /* chips */
   4317 
   4318 #if defined(BCM_88675_A0)
   4319     { /* SOC_REG_INT_KAPS_IBC_RESPONSE_DATAr */
   4320         soc_block_list[73],
   4321         soc_genreg,
   4322         15,
   4323         0,
   4324         0x5000,
   4325         SOC_REG_FLAG_ARRAY |
   4326                           SOC_REG_FLAG_RO |
   4327                           SOC_REG_FLAG_REG_ARRAY,
   4328         0,
   4329         1,
   4330         soc_KAPS_IBC_RESPONSE_DATAr_fields,
   4331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4333         -1,
   4334         -1,
   4335     },
   4336 #endif /* chips */
   4337 
   4338 #if defined(BCM_88375_A0)
   4339     { /* SOC_REG_INT_KAPS_IBC_RESPONSE_DATA_BCM88375_A0r */
   4340         soc_block_list[73],
   4341         soc_genreg,
   4342         15,
   4343         0,
   4344         0x5000,
   4345         SOC_REG_FLAG_ARRAY |
   4346                           SOC_REG_FLAG_RO |
   4347                           SOC_REG_FLAG_REG_ARRAY,
   4348         0,
   4349         1,
   4350         soc_KAPS_IBC_RESPONSE_DATA_BCM88375_A0r_fields,
   4351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4352         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4353         -1,
   4354         -1,
   4355     },
   4356 #endif /* chips */
   4357 
   4358 #if defined(BCM_88375_B0)
   4359     { /* SOC_REG_INT_KAPS_IBC_RESPONSE_DATA_BCM88375_B0r */
   4360         soc_block_list[73],
   4361         soc_genreg,
   4362         15,
   4363         0,
   4364         0x5000,
   4365         SOC_REG_FLAG_ARRAY |
   4366                           SOC_REG_FLAG_RO |
   4367                           SOC_REG_FLAG_REG_ARRAY,
   4368         0,
   4369         1,
   4370         soc_KAPS_IBC_RESPONSE_DATA_BCM88375_B0r_fields,
   4371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4372         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4373         -1,
   4374         -1,
   4375     },
   4376 #endif /* chips */
   4377 
   4378 #if defined(BCM_88675_B0)
   4379     { /* SOC_REG_INT_KAPS_IBC_RESPONSE_DATA_BCM88675_B0r */
   4380         soc_block_list[73],
   4381         soc_genreg,
   4382         15,
   4383         0,
   4384         0x5000,
   4385         SOC_REG_FLAG_ARRAY |
   4386                           SOC_REG_FLAG_RO |
   4387                           SOC_REG_FLAG_REG_ARRAY,
   4388         0,
   4389         1,
   4390         soc_KAPS_IBC_RESPONSE_DATA_BCM88675_B0r_fields,
   4391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4392         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4393         -1,
   4394         -1,
   4395     },
   4396 #endif /* chips */
   4397 
   4398 #if defined(BCM_88675_A0)
   4399     { /* SOC_REG_INT_KAPS_IBC_RESPONSE_WORDr */
   4400         soc_block_list[73],
   4401         soc_genreg,
   4402         1,
   4403         0,
   4404         0x5f00,
   4405         0,
   4406         0,
   4407         4,
   4408         soc_KAPS_IBC_RESPONSE_WORDr_fields,
   4409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4410         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4411         -1,
   4412         -1,
   4413     },
   4414 #endif /* chips */
   4415 
   4416 #if defined(BCM_88375_A0)
   4417     { /* SOC_REG_INT_KAPS_IBC_RESPONSE_WORD_BCM88375_A0r */
   4418         soc_block_list[73],
   4419         soc_genreg,
   4420         1,
   4421         0,
   4422         0x5f00,
   4423         0,
   4424         0,
   4425         4,
   4426         soc_KAPS_IBC_RESPONSE_WORD_BCM88375_A0r_fields,
   4427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4428         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4429         -1,
   4430         -1,
   4431     },
   4432 #endif /* chips */
   4433 
   4434 #if defined(BCM_88375_B0)
   4435     { /* SOC_REG_INT_KAPS_IBC_RESPONSE_WORD_BCM88375_B0r */
   4436         soc_block_list[73],
   4437         soc_genreg,
   4438         1,
   4439         0,
   4440         0x5f00,
   4441         0,
   4442         0,
   4443         4,
   4444         soc_KAPS_IBC_RESPONSE_WORD_BCM88375_B0r_fields,
   4445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4446         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4447         -1,
   4448         -1,
   4449     },
   4450 #endif /* chips */
   4451 
   4452 #if defined(BCM_88675_B0)
   4453     { /* SOC_REG_INT_KAPS_IBC_RESPONSE_WORD_BCM88675_B0r */
   4454         soc_block_list[73],
   4455         soc_genreg,
   4456         1,
   4457         0,
   4458         0x5f00,
   4459         0,
   4460         0,
   4461         4,
   4462         soc_KAPS_IBC_RESPONSE_WORD_BCM88675_B0r_fields,
   4463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4464         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4465         -1,
   4466         -1,
   4467     },
   4468 #endif /* chips */
   4469 
   4470 #if defined(BCM_88470_A0)
   4471     { /* SOC_REG_INT_KAPS_INDIRECT_COMMANDr */
   4472         soc_block_list[73],
   4473         soc_genreg,
   4474         1,
   4475         0,
   4476         0x80,
   4477         0,
   4478         0,
   4479         5,
   4480         soc_KAPS_INDIRECT_COMMANDr_fields,
   4481         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
   4482         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4483         -1,
   4484         -1,
   4485     },
   4486 #endif /* chips */
   4487 
   4488 #if defined(BCM_88470_A0)
   4489     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_ADDRESSr */
   4490         soc_block_list[73],
   4491         soc_genreg,
   4492         1,
   4493         0,
   4494         0x81,
   4495         0,
   4496         0,
   4497         2,
   4498         soc_KAPS_INDIRECT_COMMAND_ADDRESSr_fields,
   4499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4501         -1,
   4502         -1,
   4503     },
   4504 #endif /* chips */
   4505 
   4506 #if defined(BCM_88270_A0)
   4507     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88270_A0r */
   4508         soc_block_list[73],
   4509         soc_genreg,
   4510         1,
   4511         0,
   4512         0x81,
   4513         0,
   4514         0,
   4515         2,
   4516         soc_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88270_A0r_fields,
   4517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4518         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4519         -1,
   4520         -1,
   4521     },
   4522 #endif /* chips */
   4523 
   4524 #if defined(BCM_88470_B0)
   4525     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88470_B0r */
   4526         soc_block_list[73],
   4527         soc_genreg,
   4528         1,
   4529         0,
   4530         0x81,
   4531         0,
   4532         0,
   4533         2,
   4534         soc_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88470_B0r_fields,
   4535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4536         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4537         -1,
   4538         -1,
   4539     },
   4540 #endif /* chips */
   4541 
   4542 #if defined(BCM_88680_A0)
   4543     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r */
   4544         soc_block_list[73],
   4545         soc_genreg,
   4546         1,
   4547         0,
   4548         0x81,
   4549         0,
   4550         0,
   4551         2,
   4552         soc_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r_fields,
   4553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4554         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4555         -1,
   4556         -1,
   4557     },
   4558 #endif /* chips */
   4559 
   4560 #if defined(BCM_88690_A0)
   4561     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r */
   4562         soc_block_list[73],
   4563         soc_genreg,
   4564         1,
   4565         0,
   4566         0x81,
   4567         0,
   4568         0,
   4569         2,
   4570         soc_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r_fields,
   4571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4572         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4573         -1,
   4574         -1,
   4575     },
   4576 #endif /* chips */
   4577 
   4578 #if defined(BCM_88690_B0)
   4579     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r */
   4580         soc_block_list[73],
   4581         soc_genreg,
   4582         1,
   4583         0,
   4584         0x81,
   4585         0,
   4586         0,
   4587         2,
   4588         soc_KAPS_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r_fields,
   4589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4590         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4591         -1,
   4592         -1,
   4593     },
   4594 #endif /* chips */
   4595 
   4596 #if defined(BCM_88270_A0)
   4597     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_BCM88270_A0r */
   4598         soc_block_list[73],
   4599         soc_genreg,
   4600         1,
   4601         0,
   4602         0x80,
   4603         0,
   4604         0,
   4605         5,
   4606         soc_KAPS_INDIRECT_COMMAND_BCM88270_A0r_fields,
   4607         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
   4608         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4609         -1,
   4610         -1,
   4611     },
   4612 #endif /* chips */
   4613 
   4614 #if defined(BCM_88470_B0)
   4615     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_BCM88470_B0r */
   4616         soc_block_list[73],
   4617         soc_genreg,
   4618         1,
   4619         0,
   4620         0x80,
   4621         0,
   4622         0,
   4623         5,
   4624         soc_KAPS_INDIRECT_COMMAND_BCM88470_B0r_fields,
   4625         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
   4626         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4627         -1,
   4628         -1,
   4629     },
   4630 #endif /* chips */
   4631 
   4632 #if defined(BCM_88680_A0)
   4633     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_BCM88680_A0r */
   4634         soc_block_list[73],
   4635         soc_genreg,
   4636         1,
   4637         0,
   4638         0x80,
   4639         0,
   4640         0,
   4641         5,
   4642         soc_KAPS_INDIRECT_COMMAND_BCM88680_A0r_fields,
   4643         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
   4644         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4645         -1,
   4646         -1,
   4647     },
   4648 #endif /* chips */
   4649 
   4650 #if defined(BCM_88690_A0)
   4651     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_BCM88690_A0r */
   4652         soc_block_list[73],
   4653         soc_genreg,
   4654         1,
   4655         0,
   4656         0x80,
   4657         0,
   4658         0,
   4659         5,
   4660         soc_KAPS_INDIRECT_COMMAND_BCM88690_A0r_fields,
   4661         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
   4662         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4663         -1,
   4664         -1,
   4665     },
   4666 #endif /* chips */
   4667 
   4668 #if defined(BCM_88690_B0)
   4669     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_BCM88690_B0r */
   4670         soc_block_list[73],
   4671         soc_genreg,
   4672         1,
   4673         0,
   4674         0x80,
   4675         0,
   4676         0,
   4677         5,
   4678         soc_KAPS_INDIRECT_COMMAND_BCM88690_B0r_fields,
   4679         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
   4680         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4681         -1,
   4682         -1,
   4683     },
   4684 #endif /* chips */
   4685 
   4686 #if defined(BCM_88470_A0)
   4687     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_DATA_INCREMENTr */
   4688         soc_block_list[73],
   4689         soc_genreg,
   4690         1,
   4691         0,
   4692         0x82,
   4693         SOC_REG_FLAG_64_BITS,
   4694         0,
   4695         1,
   4696         soc_KAPS_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
   4697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4698         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   4699         -1,
   4700         -1,
   4701     },
   4702 #endif /* chips */
   4703 
   4704 #if defined(BCM_88270_A0)
   4705     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_DATA_INCREMENT_BCM88270_A0r */
   4706         soc_block_list[73],
   4707         soc_genreg,
   4708         1,
   4709         0,
   4710         0x82,
   4711         SOC_REG_FLAG_64_BITS,
   4712         0,
   4713         1,
   4714         soc_KAPS_INDIRECT_COMMAND_DATA_INCREMENT_BCM88270_A0r_fields,
   4715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4716         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   4717         -1,
   4718         -1,
   4719     },
   4720 #endif /* chips */
   4721 
   4722 #if defined(BCM_88470_B0)
   4723     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_B0r */
   4724         soc_block_list[73],
   4725         soc_genreg,
   4726         1,
   4727         0,
   4728         0x82,
   4729         SOC_REG_FLAG_64_BITS,
   4730         0,
   4731         1,
   4732         soc_KAPS_INDIRECT_COMMAND_DATA_INCREMENT_BCM88470_B0r_fields,
   4733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4734         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   4735         -1,
   4736         -1,
   4737     },
   4738 #endif /* chips */
   4739 
   4740 #if defined(BCM_88680_A0)
   4741     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r */
   4742         soc_block_list[73],
   4743         soc_genreg,
   4744         1,
   4745         0,
   4746         0x82,
   4747         SOC_REG_FLAG_64_BITS,
   4748         0,
   4749         1,
   4750         soc_KAPS_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r_fields,
   4751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4752         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   4753         -1,
   4754         -1,
   4755     },
   4756 #endif /* chips */
   4757 
   4758 #if defined(BCM_88470_A0)
   4759     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_RD_DATAr */
   4760         soc_block_list[73],
   4761         soc_genreg,
   4762         1,
   4763         0,
   4764         0x60,
   4765         SOC_REG_FLAG_ABOVE_64_BITS |
   4766                           SOC_REG_FLAG_RO |
   4767                           SOC_REG_FLAG_SIGNAL,
   4768         0,
   4769         1,
   4770         soc_KAPS_INDIRECT_COMMAND_RD_DATAr_fields,
   4771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4773         -1,
   4774         -1,
   4775     },
   4776 #endif /* chips */
   4777 
   4778 #if defined(BCM_88270_A0)
   4779     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88270_A0r */
   4780         soc_block_list[73],
   4781         soc_genreg,
   4782         1,
   4783         0,
   4784         0x60,
   4785         SOC_REG_FLAG_ABOVE_64_BITS |
   4786                           SOC_REG_FLAG_RO |
   4787                           SOC_REG_FLAG_SIGNAL,
   4788         0,
   4789         1,
   4790         soc_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88270_A0r_fields,
   4791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4792         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4793         -1,
   4794         -1,
   4795     },
   4796 #endif /* chips */
   4797 
   4798 #if defined(BCM_88470_B0)
   4799     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88470_B0r */
   4800         soc_block_list[73],
   4801         soc_genreg,
   4802         1,
   4803         0,
   4804         0x60,
   4805         SOC_REG_FLAG_ABOVE_64_BITS |
   4806                           SOC_REG_FLAG_RO |
   4807                           SOC_REG_FLAG_SIGNAL,
   4808         0,
   4809         1,
   4810         soc_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88470_B0r_fields,
   4811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4812         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4813         -1,
   4814         -1,
   4815     },
   4816 #endif /* chips */
   4817 
   4818 #if defined(BCM_88680_A0)
   4819     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88680_A0r */
   4820         soc_block_list[73],
   4821         soc_genreg,
   4822         1,
   4823         0,
   4824         0x60,
   4825         SOC_REG_FLAG_ABOVE_64_BITS |
   4826                           SOC_REG_FLAG_RO |
   4827                           SOC_REG_FLAG_SIGNAL,
   4828         0,
   4829         1,
   4830         soc_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88680_A0r_fields,
   4831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4833         -1,
   4834         -1,
   4835     },
   4836 #endif /* chips */
   4837 
   4838 #if defined(BCM_88690_A0)
   4839     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88690_A0r */
   4840         soc_block_list[73],
   4841         soc_genreg,
   4842         1,
   4843         0,
   4844         0x60,
   4845         SOC_REG_FLAG_ABOVE_64_BITS |
   4846                           SOC_REG_FLAG_RO |
   4847                           SOC_REG_FLAG_SIGNAL,
   4848         0,
   4849         1,
   4850         soc_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88690_A0r_fields,
   4851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4852         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4853         -1,
   4854         -1,
   4855     },
   4856 #endif /* chips */
   4857 
   4858 #if defined(BCM_88690_B0)
   4859     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r */
   4860         soc_block_list[73],
   4861         soc_genreg,
   4862         1,
   4863         0,
   4864         0x60,
   4865         SOC_REG_FLAG_ABOVE_64_BITS |
   4866                           SOC_REG_FLAG_RO |
   4867                           SOC_REG_FLAG_SIGNAL,
   4868         0,
   4869         1,
   4870         soc_KAPS_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r_fields,
   4871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4873         -1,
   4874         -1,
   4875     },
   4876 #endif /* chips */
   4877 
   4878 #if defined(BCM_88470_A0)
   4879     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WIDE_MEMr */
   4880         soc_block_list[73],
   4881         soc_genreg,
   4882         1,
   4883         0,
   4884         0x41,
   4885         0,
   4886         0,
   4887         1,
   4888         soc_KAPS_INDIRECT_COMMAND_WIDE_MEMr_fields,
   4889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4890         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4891         -1,
   4892         -1,
   4893     },
   4894 #endif /* chips */
   4895 
   4896 #if defined(BCM_88270_A0)
   4897     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WIDE_MEM_BCM88270_A0r */
   4898         soc_block_list[73],
   4899         soc_genreg,
   4900         1,
   4901         0,
   4902         0x41,
   4903         0,
   4904         0,
   4905         1,
   4906         soc_KAPS_INDIRECT_COMMAND_WIDE_MEM_BCM88270_A0r_fields,
   4907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4908         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4909         -1,
   4910         -1,
   4911     },
   4912 #endif /* chips */
   4913 
   4914 #if defined(BCM_88470_B0)
   4915     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WIDE_MEM_BCM88470_B0r */
   4916         soc_block_list[73],
   4917         soc_genreg,
   4918         1,
   4919         0,
   4920         0x41,
   4921         0,
   4922         0,
   4923         1,
   4924         soc_KAPS_INDIRECT_COMMAND_WIDE_MEM_BCM88470_B0r_fields,
   4925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4926         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4927         -1,
   4928         -1,
   4929     },
   4930 #endif /* chips */
   4931 
   4932 #if defined(BCM_88680_A0)
   4933     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r */
   4934         soc_block_list[73],
   4935         soc_genreg,
   4936         1,
   4937         0,
   4938         0x41,
   4939         0,
   4940         0,
   4941         1,
   4942         soc_KAPS_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r_fields,
   4943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4944         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4945         -1,
   4946         -1,
   4947     },
   4948 #endif /* chips */
   4949 
   4950 #if defined(BCM_88470_A0)
   4951     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WR_DATAr */
   4952         soc_block_list[73],
   4953         soc_genreg,
   4954         1,
   4955         0,
   4956         0x20,
   4957         SOC_REG_FLAG_ABOVE_64_BITS,
   4958         0,
   4959         1,
   4960         soc_KAPS_INDIRECT_COMMAND_WR_DATAr_fields,
   4961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4962         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4963         -1,
   4964         -1,
   4965     },
   4966 #endif /* chips */
   4967 
   4968 #if defined(BCM_88270_A0)
   4969     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88270_A0r */
   4970         soc_block_list[73],
   4971         soc_genreg,
   4972         1,
   4973         0,
   4974         0x20,
   4975         SOC_REG_FLAG_ABOVE_64_BITS,
   4976         0,
   4977         1,
   4978         soc_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88270_A0r_fields,
   4979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4980         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4981         -1,
   4982         -1,
   4983     },
   4984 #endif /* chips */
   4985 
   4986 #if defined(BCM_88470_B0)
   4987     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88470_B0r */
   4988         soc_block_list[73],
   4989         soc_genreg,
   4990         1,
   4991         0,
   4992         0x20,
   4993         SOC_REG_FLAG_ABOVE_64_BITS,
   4994         0,
   4995         1,
   4996         soc_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88470_B0r_fields,
   4997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4998         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4999         -1,
   5000         -1,
   5001     },
   5002 #endif /* chips */
   5003 
   5004 #if defined(BCM_88680_A0)
   5005     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r */
   5006         soc_block_list[73],
   5007         soc_genreg,
   5008         1,
   5009         0,
   5010         0x20,
   5011         SOC_REG_FLAG_ABOVE_64_BITS,
   5012         0,
   5013         1,
   5014         soc_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r_fields,
   5015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5016         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5017         -1,
   5018         -1,
   5019     },
   5020 #endif /* chips */
   5021 
   5022 #if defined(BCM_88690_A0)
   5023     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r */
   5024         soc_block_list[73],
   5025         soc_genreg,
   5026         1,
   5027         0,
   5028         0x20,
   5029         SOC_REG_FLAG_ABOVE_64_BITS,
   5030         0,
   5031         1,
   5032         soc_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r_fields,
   5033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5034         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5035         -1,
   5036         -1,
   5037     },
   5038 #endif /* chips */
   5039 
   5040 #if defined(BCM_88690_B0)
   5041     { /* SOC_REG_INT_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r */
   5042         soc_block_list[73],
   5043         soc_genreg,
   5044         1,
   5045         0,
   5046         0x20,
   5047         SOC_REG_FLAG_ABOVE_64_BITS,
   5048         0,
   5049         1,
   5050         soc_KAPS_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r_fields,
   5051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5052         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5053         -1,
   5054         -1,
   5055     },
   5056 #endif /* chips */
   5057 
   5058 #if defined(BCM_88470_A0)
   5059     { /* SOC_REG_INT_KAPS_INDIRECT_FORCE_BUBBLEr */
   5060         soc_block_list[73],
   5061         soc_genreg,
   5062         1,
   5063         0,
   5064         0x83,
   5065         0,
   5066         0,
   5067         4,
   5068         soc_KAPS_INDIRECT_FORCE_BUBBLEr_fields,
   5069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5070         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   5071         -1,
   5072         -1,
   5073     },
   5074 #endif /* chips */
   5075 
   5076 #if defined(BCM_88270_A0)
   5077     { /* SOC_REG_INT_KAPS_INDIRECT_FORCE_BUBBLE_BCM88270_A0r */
   5078         soc_block_list[73],
   5079         soc_genreg,
   5080         1,
   5081         0,
   5082         0x83,
   5083         0,
   5084         0,
   5085         4,
   5086         soc_KAPS_INDIRECT_FORCE_BUBBLE_BCM88270_A0r_fields,
   5087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5088         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   5089         -1,
   5090         -1,
   5091     },
   5092 #endif /* chips */
   5093 
   5094 #if defined(BCM_88470_B0)
   5095     { /* SOC_REG_INT_KAPS_INDIRECT_FORCE_BUBBLE_BCM88470_B0r */
   5096         soc_block_list[73],
   5097         soc_genreg,
   5098         1,
   5099         0,
   5100         0x83,
   5101         0,
   5102         0,
   5103         4,
   5104         soc_KAPS_INDIRECT_FORCE_BUBBLE_BCM88470_B0r_fields,
   5105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5106         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   5107         -1,
   5108         -1,
   5109     },
   5110 #endif /* chips */
   5111 
   5112 #if defined(BCM_88680_A0)
   5113     { /* SOC_REG_INT_KAPS_INDIRECT_FORCE_BUBBLE_BCM88680_A0r */
   5114         soc_block_list[73],
   5115         soc_genreg,
   5116         1,
   5117         0,
   5118         0x83,
   5119         0,
   5120         0,
   5121         4,
   5122         soc_KAPS_INDIRECT_FORCE_BUBBLE_BCM88680_A0r_fields,
   5123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5124         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
   5125         -1,
   5126         -1,
   5127     },
   5128 #endif /* chips */
   5129 
   5130 #if defined(BCM_88690_A0)
   5131     { /* SOC_REG_INT_KAPS_INDIRECT_FORCE_BUBBLE_BCM88690_A0r */
   5132         soc_block_list[73],
   5133         soc_genreg,
   5134         1,
   5135         0,
   5136         0x83,
   5137         0,
   5138         0,
   5139         4,
   5140         soc_KAPS_INDIRECT_FORCE_BUBBLE_BCM88690_A0r_fields,
   5141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5142         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   5143         -1,
   5144         -1,
   5145     },
   5146 #endif /* chips */
   5147 
   5148 #if defined(BCM_88690_B0)
   5149     { /* SOC_REG_INT_KAPS_INDIRECT_FORCE_BUBBLE_BCM88690_B0r */
   5150         soc_block_list[73],
   5151         soc_genreg,
   5152         1,
   5153         0,
   5154         0x83,
   5155         0,
   5156         0,
   5157         4,
   5158         soc_KAPS_INDIRECT_FORCE_BUBBLE_BCM88690_B0r_fields,
   5159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5160         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   5161         -1,
   5162         -1,
   5163     },
   5164 #endif /* chips */
   5165 
   5166 #if defined(BCM_88470_A0)
   5167     { /* SOC_REG_INT_KAPS_INDIRECT_WR_MASKr */
   5168         soc_block_list[73],
   5169         soc_genreg,
   5170         1,
   5171         0,
   5172         0x40,
   5173         0,
   5174         0,
   5175         1,
   5176         soc_KAPS_INDIRECT_WR_MASKr_fields,
   5177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5178         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5179         -1,
   5180         -1,
   5181     },
   5182 #endif /* chips */
   5183 
   5184 #if defined(BCM_88270_A0)
   5185     { /* SOC_REG_INT_KAPS_INDIRECT_WR_MASK_BCM88270_A0r */
   5186         soc_block_list[73],
   5187         soc_genreg,
   5188         1,
   5189         0,
   5190         0x40,
   5191         0,
   5192         0,
   5193         1,
   5194         soc_KAPS_INDIRECT_WR_MASK_BCM88270_A0r_fields,
   5195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5196         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5197         -1,
   5198         -1,
   5199     },
   5200 #endif /* chips */
   5201 
   5202 #if defined(BCM_88470_B0)
   5203     { /* SOC_REG_INT_KAPS_INDIRECT_WR_MASK_BCM88470_B0r */
   5204         soc_block_list[73],
   5205         soc_genreg,
   5206         1,
   5207         0,
   5208         0x40,
   5209         0,
   5210         0,
   5211         1,
   5212         soc_KAPS_INDIRECT_WR_MASK_BCM88470_B0r_fields,
   5213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5214         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5215         -1,
   5216         -1,
   5217     },
   5218 #endif /* chips */
   5219 
   5220 #if defined(BCM_88680_A0)
   5221     { /* SOC_REG_INT_KAPS_INDIRECT_WR_MASK_BCM88680_A0r */
   5222         soc_block_list[73],
   5223         soc_genreg,
   5224         1,
   5225         0,
   5226         0x40,
   5227         SOC_REG_FLAG_ABOVE_64_BITS,
   5228         0,
   5229         1,
   5230         soc_KAPS_INDIRECT_WR_MASK_BCM88680_A0r_fields,
   5231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5233         -1,
   5234         -1,
   5235     },
   5236 #endif /* chips */
   5237 
   5238 #if defined(BCM_88690_A0)
   5239     { /* SOC_REG_INT_KAPS_INDIRECT_WR_MASK_BCM88690_A0r */
   5240         soc_block_list[73],
   5241         soc_genreg,
   5242         1,
   5243         0,
   5244         0x40,
   5245         0,
   5246         0,
   5247         1,
   5248         soc_KAPS_INDIRECT_WR_MASK_BCM88690_A0r_fields,
   5249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5250         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5251         -1,
   5252         -1,
   5253     },
   5254 #endif /* chips */
   5255 
   5256 #if defined(BCM_88690_B0)
   5257     { /* SOC_REG_INT_KAPS_INDIRECT_WR_MASK_BCM88690_B0r */
   5258         soc_block_list[73],
   5259         soc_genreg,
   5260         1,
   5261         0,
   5262         0x40,
   5263         0,
   5264         0,
   5265         1,
   5266         soc_KAPS_INDIRECT_WR_MASK_BCM88690_B0r_fields,
   5267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5268         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5269         -1,
   5270         -1,
   5271     },
   5272 #endif /* chips */
   5273 
   5274 #if defined(BCM_88470_A0)
   5275     { /* SOC_REG_INT_KAPS_INTERRUPT_MASK_REGISTERr */
   5276         soc_block_list[73],
   5277         soc_genreg,
   5278         1,
   5279         0,
   5280         0x10,
   5281         0,
   5282         0,
   5283         2,
   5284         soc_KAPS_INTERRUPT_MASK_REGISTERr_fields,
   5285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5286         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5287         -1,
   5288         -1,
   5289     },
   5290 #endif /* chips */
   5291 
   5292 #if defined(BCM_88270_A0)
   5293     { /* SOC_REG_INT_KAPS_INTERRUPT_MASK_REGISTER_BCM88270_A0r */
   5294         soc_block_list[73],
   5295         soc_genreg,
   5296         1,
   5297         0,
   5298         0x10,
   5299         0,
   5300         0,
   5301         2,
   5302         soc_KAPS_INTERRUPT_MASK_REGISTER_BCM88270_A0r_fields,
   5303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5304         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5305         -1,
   5306         -1,
   5307     },
   5308 #endif /* chips */
   5309 
   5310 #if defined(BCM_88470_B0)
   5311     { /* SOC_REG_INT_KAPS_INTERRUPT_MASK_REGISTER_BCM88470_B0r */
   5312         soc_block_list[73],
   5313         soc_genreg,
   5314         1,
   5315         0,
   5316         0x10,
   5317         0,
   5318         0,
   5319         2,
   5320         soc_KAPS_INTERRUPT_MASK_REGISTER_BCM88470_B0r_fields,
   5321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5322         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5323         -1,
   5324         -1,
   5325     },
   5326 #endif /* chips */
   5327 
   5328 #if defined(BCM_88680_A0)
   5329     { /* SOC_REG_INT_KAPS_INTERRUPT_MASK_REGISTER_BCM88680_A0r */
   5330         soc_block_list[73],
   5331         soc_genreg,
   5332         1,
   5333         0,
   5334         0x10,
   5335         0,
   5336         0,
   5337         3,
   5338         soc_KAPS_INTERRUPT_MASK_REGISTER_BCM88680_A0r_fields,
   5339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5340         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5341         -1,
   5342         -1,
   5343     },
   5344 #endif /* chips */
   5345 
   5346 #if defined(BCM_88690_A0)
   5347     { /* SOC_REG_INT_KAPS_INTERRUPT_MASK_REGISTER_BCM88690_A0r */
   5348         soc_block_list[73],
   5349         soc_genreg,
   5350         1,
   5351         0,
   5352         0x10,
   5353         0,
   5354         0,
   5355         9,
   5356         soc_KAPS_INTERRUPT_MASK_REGISTER_BCM88690_A0r_fields,
   5357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5358         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   5359         -1,
   5360         -1,
   5361     },
   5362 #endif /* chips */
   5363 
   5364 #if defined(BCM_88690_B0)
   5365     { /* SOC_REG_INT_KAPS_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
   5366         soc_block_list[73],
   5367         soc_genreg,
   5368         1,
   5369         0,
   5370         0x10,
   5371         0,
   5372         0,
   5373         9,
   5374         soc_KAPS_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
   5375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5376         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   5377         -1,
   5378         -1,
   5379     },
   5380 #endif /* chips */
   5381 
   5382 #if defined(BCM_88470_A0)
   5383     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTERr */
   5384         soc_block_list[73],
   5385         soc_genreg,
   5386         1,
   5387         0,
   5388         0,
   5389         SOC_REG_FLAG_RO |
   5390                           SOC_REG_FLAG_INTERRUPT |
   5391                           SOC_REG_FLAG_SIGNAL,
   5392         0,
   5393         2,
   5394         soc_KAPS_INTERRUPT_REGISTERr_fields,
   5395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5396         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5397         -1,
   5398         -1,
   5399     },
   5400 #endif /* chips */
   5401 
   5402 #if defined(BCM_88270_A0)
   5403     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_BCM88270_A0r */
   5404         soc_block_list[73],
   5405         soc_genreg,
   5406         1,
   5407         0,
   5408         0,
   5409         SOC_REG_FLAG_RO |
   5410                           SOC_REG_FLAG_INTERRUPT |
   5411                           SOC_REG_FLAG_SIGNAL,
   5412         0,
   5413         2,
   5414         soc_KAPS_INTERRUPT_REGISTER_BCM88270_A0r_fields,
   5415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5416         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5417         -1,
   5418         -1,
   5419     },
   5420 #endif /* chips */
   5421 
   5422 #if defined(BCM_88470_B0)
   5423     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_BCM88470_B0r */
   5424         soc_block_list[73],
   5425         soc_genreg,
   5426         1,
   5427         0,
   5428         0,
   5429         SOC_REG_FLAG_RO |
   5430                           SOC_REG_FLAG_INTERRUPT |
   5431                           SOC_REG_FLAG_SIGNAL,
   5432         0,
   5433         2,
   5434         soc_KAPS_INTERRUPT_REGISTER_BCM88470_B0r_fields,
   5435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5436         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5437         -1,
   5438         -1,
   5439     },
   5440 #endif /* chips */
   5441 
   5442 #if defined(BCM_88680_A0)
   5443     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_BCM88680_A0r */
   5444         soc_block_list[73],
   5445         soc_genreg,
   5446         1,
   5447         0,
   5448         0,
   5449         SOC_REG_FLAG_RO |
   5450                           SOC_REG_FLAG_INTERRUPT,
   5451         0,
   5452         3,
   5453         soc_KAPS_INTERRUPT_REGISTER_BCM88680_A0r_fields,
   5454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5455         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5456         -1,
   5457         -1,
   5458     },
   5459 #endif /* chips */
   5460 
   5461 #if defined(BCM_88690_A0)
   5462     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_BCM88690_A0r */
   5463         soc_block_list[73],
   5464         soc_genreg,
   5465         1,
   5466         0,
   5467         0,
   5468         SOC_REG_FLAG_INTERRUPT |
   5469                           SOC_REG_FLAG_SIGNAL,
   5470         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   5471         9,
   5472         soc_KAPS_INTERRUPT_REGISTER_BCM88690_A0r_fields,
   5473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5474         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   5475         -1,
   5476         -1,
   5477     },
   5478 #endif /* chips */
   5479 
   5480 #if defined(BCM_88690_B0)
   5481     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_BCM88690_B0r */
   5482         soc_block_list[73],
   5483         soc_genreg,
   5484         1,
   5485         0,
   5486         0,
   5487         SOC_REG_FLAG_INTERRUPT |
   5488                           SOC_REG_FLAG_SIGNAL,
   5489         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   5490         9,
   5491         soc_KAPS_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   5492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5493         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   5494         -1,
   5495         -1,
   5496     },
   5497 #endif /* chips */
   5498 
   5499 #if defined(BCM_88470_A0)
   5500     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_TESTr */
   5501         soc_block_list[73],
   5502         soc_genreg,
   5503         1,
   5504         0,
   5505         0x18,
   5506         0,
   5507         0,
   5508         1,
   5509         soc_KAPS_INTERRUPT_REGISTER_TESTr_fields,
   5510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5511         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5512         -1,
   5513         -1,
   5514     },
   5515 #endif /* chips */
   5516 
   5517 #if defined(BCM_88270_A0)
   5518     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_TEST_BCM88270_A0r */
   5519         soc_block_list[73],
   5520         soc_genreg,
   5521         1,
   5522         0,
   5523         0x18,
   5524         0,
   5525         0,
   5526         1,
   5527         soc_KAPS_INTERRUPT_REGISTER_TEST_BCM88270_A0r_fields,
   5528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5529         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5530         -1,
   5531         -1,
   5532     },
   5533 #endif /* chips */
   5534 
   5535 #if defined(BCM_88470_B0)
   5536     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_TEST_BCM88470_B0r */
   5537         soc_block_list[73],
   5538         soc_genreg,
   5539         1,
   5540         0,
   5541         0x18,
   5542         0,
   5543         0,
   5544         1,
   5545         soc_KAPS_INTERRUPT_REGISTER_TEST_BCM88470_B0r_fields,
   5546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5547         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5548         -1,
   5549         -1,
   5550     },
   5551 #endif /* chips */
   5552 
   5553 #if defined(BCM_88680_A0)
   5554     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
   5555         soc_block_list[73],
   5556         soc_genreg,
   5557         1,
   5558         0,
   5559         0x18,
   5560         0,
   5561         0,
   5562         1,
   5563         soc_KAPS_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
   5564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5565         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5566         -1,
   5567         -1,
   5568     },
   5569 #endif /* chips */
   5570 
   5571 #if defined(BCM_88690_A0)
   5572     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
   5573         soc_block_list[73],
   5574         soc_genreg,
   5575         1,
   5576         0,
   5577         0x18,
   5578         0,
   5579         0,
   5580         1,
   5581         soc_KAPS_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
   5582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5583         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   5584         -1,
   5585         -1,
   5586     },
   5587 #endif /* chips */
   5588 
   5589 #if defined(BCM_88690_B0)
   5590     { /* SOC_REG_INT_KAPS_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   5591         soc_block_list[73],
   5592         soc_genreg,
   5593         1,
   5594         0,
   5595         0x18,
   5596         0,
   5597         0,
   5598         1,
   5599         soc_KAPS_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   5600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5601         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   5602         -1,
   5603         -1,
   5604     },
   5605 #endif /* chips */
   5606 
   5607 #if defined(BCM_88680_A0)
   5608     { /* SOC_REG_INT_KAPS_KAPS_BB_ERROR_REGISTERr */
   5609         soc_block_list[73],
   5610         soc_genreg,
   5611         1,
   5612         0,
   5613         0x100,
   5614         0,
   5615         0,
   5616         2,
   5617         soc_KAPS_KAPS_BB_ERROR_REGISTERr_fields,
   5618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5619         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5620         -1,
   5621         -1,
   5622     },
   5623 #endif /* chips */
   5624 
   5625 #if defined(BCM_88680_A0)
   5626     { /* SOC_REG_INT_KAPS_KAPS_BB_ERROR_REGISTER_MASKr */
   5627         soc_block_list[73],
   5628         soc_genreg,
   5629         1,
   5630         0,
   5631         0x101,
   5632         0,
   5633         0,
   5634         2,
   5635         soc_KAPS_KAPS_BB_ERROR_REGISTER_MASKr_fields,
   5636         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   5637         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5638         -1,
   5639         -1,
   5640     },
   5641 #endif /* chips */
   5642 
   5643 #if defined(BCM_88680_A0)
   5644     { /* SOC_REG_INT_KAPS_KAPS_BB_ERROR_REGISTER_TESTr */
   5645         soc_block_list[73],
   5646         soc_genreg,
   5647         1,
   5648         0,
   5649         0x102,
   5650         0,
   5651         0,
   5652         1,
   5653         soc_KAPS_KAPS_BB_ERROR_REGISTER_TESTr_fields,
   5654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5655         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5656         -1,
   5657         -1,
   5658     },
   5659 #endif /* chips */
   5660 
   5661 #if defined(BCM_88470_A0)
   5662     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTERr */
   5663         soc_block_list[73],
   5664         soc_genreg,
   5665         1,
   5666         0,
   5667         0x100,
   5668         SOC_REG_FLAG_INTERRUPT |
   5669                           SOC_REG_FLAG_SIGNAL,
   5670         0,
   5671         3,
   5672         soc_KAPS_KAPS_ERROR_REGISTERr_fields,
   5673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5674         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5675         -1,
   5676         -1,
   5677     },
   5678 #endif /* chips */
   5679 
   5680 #if defined(BCM_88270_A0)
   5681     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_BCM88270_A0r */
   5682         soc_block_list[73],
   5683         soc_genreg,
   5684         1,
   5685         0,
   5686         0x100,
   5687         SOC_REG_FLAG_INTERRUPT |
   5688                           SOC_REG_FLAG_SIGNAL,
   5689         0,
   5690         3,
   5691         soc_KAPS_KAPS_ERROR_REGISTER_BCM88270_A0r_fields,
   5692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5693         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5694         -1,
   5695         -1,
   5696     },
   5697 #endif /* chips */
   5698 
   5699 #if defined(BCM_88470_B0)
   5700     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_BCM88470_B0r */
   5701         soc_block_list[73],
   5702         soc_genreg,
   5703         1,
   5704         0,
   5705         0x100,
   5706         SOC_REG_FLAG_INTERRUPT |
   5707                           SOC_REG_FLAG_SIGNAL,
   5708         0,
   5709         3,
   5710         soc_KAPS_KAPS_ERROR_REGISTER_BCM88470_B0r_fields,
   5711         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5712         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5713         -1,
   5714         -1,
   5715     },
   5716 #endif /* chips */
   5717 
   5718 #if defined(BCM_88680_A0)
   5719     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_BCM88680_A0r */
   5720         soc_block_list[73],
   5721         soc_genreg,
   5722         1,
   5723         0,
   5724         0x136,
   5725         0,
   5726         0,
   5727         4,
   5728         soc_KAPS_KAPS_ERROR_REGISTER_BCM88680_A0r_fields,
   5729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5730         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5731         -1,
   5732         -1,
   5733     },
   5734 #endif /* chips */
   5735 
   5736 #if defined(BCM_88470_A0)
   5737     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_MASKr */
   5738         soc_block_list[73],
   5739         soc_genreg,
   5740         1,
   5741         0,
   5742         0x101,
   5743         0,
   5744         0,
   5745         3,
   5746         soc_KAPS_KAPS_ERROR_REGISTER_MASKr_fields,
   5747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5748         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5749         -1,
   5750         -1,
   5751     },
   5752 #endif /* chips */
   5753 
   5754 #if defined(BCM_88270_A0)
   5755     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_MASK_BCM88270_A0r */
   5756         soc_block_list[73],
   5757         soc_genreg,
   5758         1,
   5759         0,
   5760         0x101,
   5761         0,
   5762         0,
   5763         3,
   5764         soc_KAPS_KAPS_ERROR_REGISTER_MASK_BCM88270_A0r_fields,
   5765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5766         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5767         -1,
   5768         -1,
   5769     },
   5770 #endif /* chips */
   5771 
   5772 #if defined(BCM_88470_B0)
   5773     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_MASK_BCM88470_B0r */
   5774         soc_block_list[73],
   5775         soc_genreg,
   5776         1,
   5777         0,
   5778         0x101,
   5779         0,
   5780         0,
   5781         3,
   5782         soc_KAPS_KAPS_ERROR_REGISTER_MASK_BCM88470_B0r_fields,
   5783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5784         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5785         -1,
   5786         -1,
   5787     },
   5788 #endif /* chips */
   5789 
   5790 #if defined(BCM_88680_A0)
   5791     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_MASK_BCM88680_A0r */
   5792         soc_block_list[73],
   5793         soc_genreg,
   5794         1,
   5795         0,
   5796         0x137,
   5797         0,
   5798         0,
   5799         4,
   5800         soc_KAPS_KAPS_ERROR_REGISTER_MASK_BCM88680_A0r_fields,
   5801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5802         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5803         -1,
   5804         -1,
   5805     },
   5806 #endif /* chips */
   5807 
   5808 #if defined(BCM_88470_A0)
   5809     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_TESTr */
   5810         soc_block_list[73],
   5811         soc_genreg,
   5812         1,
   5813         0,
   5814         0x102,
   5815         0,
   5816         0,
   5817         1,
   5818         soc_KAPS_KAPS_ERROR_REGISTER_TESTr_fields,
   5819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5820         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5821         -1,
   5822         -1,
   5823     },
   5824 #endif /* chips */
   5825 
   5826 #if defined(BCM_88270_A0)
   5827     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_TEST_BCM88270_A0r */
   5828         soc_block_list[73],
   5829         soc_genreg,
   5830         1,
   5831         0,
   5832         0x102,
   5833         0,
   5834         0,
   5835         1,
   5836         soc_KAPS_KAPS_ERROR_REGISTER_TEST_BCM88270_A0r_fields,
   5837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5838         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5839         -1,
   5840         -1,
   5841     },
   5842 #endif /* chips */
   5843 
   5844 #if defined(BCM_88470_B0)
   5845     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_TEST_BCM88470_B0r */
   5846         soc_block_list[73],
   5847         soc_genreg,
   5848         1,
   5849         0,
   5850         0x102,
   5851         0,
   5852         0,
   5853         1,
   5854         soc_KAPS_KAPS_ERROR_REGISTER_TEST_BCM88470_B0r_fields,
   5855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5856         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5857         -1,
   5858         -1,
   5859     },
   5860 #endif /* chips */
   5861 
   5862 #if defined(BCM_88680_A0)
   5863     { /* SOC_REG_INT_KAPS_KAPS_ERROR_REGISTER_TEST_BCM88680_A0r */
   5864         soc_block_list[73],
   5865         soc_genreg,
   5866         1,
   5867         0,
   5868         0x138,
   5869         0,
   5870         0,
   5871         1,
   5872         soc_KAPS_KAPS_ERROR_REGISTER_TEST_BCM88680_A0r_fields,
   5873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5874         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5875         -1,
   5876         -1,
   5877     },
   5878 #endif /* chips */
   5879 
   5880 #if defined(BCM_88470_A0)
   5881     { /* SOC_REG_INT_KAPS_KAPS_REVISIONr */
   5882         soc_block_list[73],
   5883         soc_genreg,
   5884         1,
   5885         0,
   5886         0x103,
   5887         SOC_REG_FLAG_RO,
   5888         0,
   5889         2,
   5890         soc_KAPS_KAPS_REVISIONr_fields,
   5891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5893         -1,
   5894         -1,
   5895     },
   5896 #endif /* chips */
   5897 
   5898 #if defined(BCM_88270_A0)
   5899     { /* SOC_REG_INT_KAPS_KAPS_REVISION_BCM88270_A0r */
   5900         soc_block_list[73],
   5901         soc_genreg,
   5902         1,
   5903         0,
   5904         0x103,
   5905         SOC_REG_FLAG_RO,
   5906         0,
   5907         2,
   5908         soc_KAPS_KAPS_REVISION_BCM88270_A0r_fields,
   5909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5910         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5911         -1,
   5912         -1,
   5913     },
   5914 #endif /* chips */
   5915 
   5916 #if defined(BCM_88470_B0)
   5917     { /* SOC_REG_INT_KAPS_KAPS_REVISION_BCM88470_B0r */
   5918         soc_block_list[73],
   5919         soc_genreg,
   5920         1,
   5921         0,
   5922         0x103,
   5923         SOC_REG_FLAG_RO,
   5924         0,
   5925         2,
   5926         soc_KAPS_KAPS_REVISION_BCM88470_B0r_fields,
   5927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5928         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5929         -1,
   5930         -1,
   5931     },
   5932 #endif /* chips */
   5933 
   5934 #if defined(BCM_88680_A0)
   5935     { /* SOC_REG_INT_KAPS_KAPS_REVISION_BCM88680_A0r */
   5936         soc_block_list[73],
   5937         soc_genreg,
   5938         1,
   5939         0,
   5940         0x139,
   5941         SOC_REG_FLAG_RO,
   5942         0,
   5943         2,
   5944         soc_KAPS_KAPS_REVISION_BCM88680_A0r_fields,
   5945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5946         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5947         -1,
   5948         -1,
   5949     },
   5950 #endif /* chips */
   5951 
   5952 #if defined(BCM_88675_A0)
   5953     { /* SOC_REG_INT_KAPS_MEMORY_A_ERRORr */
   5954         soc_block_list[73],
   5955         soc_genreg,
   5956         1,
   5957         0,
   5958         0x1b00,
   5959         0,
   5960         0,
   5961         2,
   5962         soc_KAPS_MEMORY_A_ERRORr_fields,
   5963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5964         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5965         -1,
   5966         -1,
   5967     },
   5968 #endif /* chips */
   5969 
   5970 #if defined(BCM_88375_A0)
   5971     { /* SOC_REG_INT_KAPS_MEMORY_A_ERROR_BCM88375_A0r */
   5972         soc_block_list[73],
   5973         soc_genreg,
   5974         1,
   5975         0,
   5976         0x1b00,
   5977         0,
   5978         0,
   5979         2,
   5980         soc_KAPS_MEMORY_A_ERROR_BCM88375_A0r_fields,
   5981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5982         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5983         -1,
   5984         -1,
   5985     },
   5986 #endif /* chips */
   5987 
   5988 #if defined(BCM_88375_B0)
   5989     { /* SOC_REG_INT_KAPS_MEMORY_A_ERROR_BCM88375_B0r */
   5990         soc_block_list[73],
   5991         soc_genreg,
   5992         1,
   5993         0,
   5994         0x1b00,
   5995         0,
   5996         0,
   5997         2,
   5998         soc_KAPS_MEMORY_A_ERROR_BCM88375_B0r_fields,
   5999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6000         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6001         -1,
   6002         -1,
   6003     },
   6004 #endif /* chips */
   6005 
   6006 #if defined(BCM_88675_B0)
   6007     { /* SOC_REG_INT_KAPS_MEMORY_A_ERROR_BCM88675_B0r */
   6008         soc_block_list[73],
   6009         soc_genreg,
   6010         1,
   6011         0,
   6012         0x1b00,
   6013         0,
   6014         0,
   6015         2,
   6016         soc_KAPS_MEMORY_A_ERROR_BCM88675_B0r_fields,
   6017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6018         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6019         -1,
   6020         -1,
   6021     },
   6022 #endif /* chips */
   6023 
   6024 #if defined(BCM_88675_A0)
   6025     { /* SOC_REG_INT_KAPS_MEMORY_A_ERROR_MASKr */
   6026         soc_block_list[73],
   6027         soc_genreg,
   6028         1,
   6029         0,
   6030         0x1e00,
   6031         0,
   6032         0,
   6033         2,
   6034         soc_KAPS_MEMORY_A_ERROR_MASKr_fields,
   6035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6036         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6037         -1,
   6038         -1,
   6039     },
   6040 #endif /* chips */
   6041 
   6042 #if defined(BCM_88375_A0)
   6043     { /* SOC_REG_INT_KAPS_MEMORY_A_ERROR_MASK_BCM88375_A0r */
   6044         soc_block_list[73],
   6045         soc_genreg,
   6046         1,
   6047         0,
   6048         0x1e00,
   6049         0,
   6050         0,
   6051         2,
   6052         soc_KAPS_MEMORY_A_ERROR_MASK_BCM88375_A0r_fields,
   6053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6054         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6055         -1,
   6056         -1,
   6057     },
   6058 #endif /* chips */
   6059 
   6060 #if defined(BCM_88375_B0)
   6061     { /* SOC_REG_INT_KAPS_MEMORY_A_ERROR_MASK_BCM88375_B0r */
   6062         soc_block_list[73],
   6063         soc_genreg,
   6064         1,
   6065         0,
   6066         0x1e00,
   6067         0,
   6068         0,
   6069         2,
   6070         soc_KAPS_MEMORY_A_ERROR_MASK_BCM88375_B0r_fields,
   6071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6072         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6073         -1,
   6074         -1,
   6075     },
   6076 #endif /* chips */
   6077 
   6078 #if defined(BCM_88675_B0)
   6079     { /* SOC_REG_INT_KAPS_MEMORY_A_ERROR_MASK_BCM88675_B0r */
   6080         soc_block_list[73],
   6081         soc_genreg,
   6082         1,
   6083         0,
   6084         0x1e00,
   6085         0,
   6086         0,
   6087         2,
   6088         soc_KAPS_MEMORY_A_ERROR_MASK_BCM88675_B0r_fields,
   6089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6090         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6091         -1,
   6092         -1,
   6093     },
   6094 #endif /* chips */
   6095 
   6096 #if defined(BCM_88675_A0)
   6097     { /* SOC_REG_INT_KAPS_MEMORY_B_ERRORr */
   6098         soc_block_list[73],
   6099         soc_genreg,
   6100         1,
   6101         0,
   6102         0x1c00,
   6103         0,
   6104         0,
   6105         2,
   6106         soc_KAPS_MEMORY_B_ERRORr_fields,
   6107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6108         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6109         -1,
   6110         -1,
   6111     },
   6112 #endif /* chips */
   6113 
   6114 #if defined(BCM_88375_A0)
   6115     { /* SOC_REG_INT_KAPS_MEMORY_B_ERROR_BCM88375_A0r */
   6116         soc_block_list[73],
   6117         soc_genreg,
   6118         1,
   6119         0,
   6120         0x1c00,
   6121         0,
   6122         0,
   6123         2,
   6124         soc_KAPS_MEMORY_B_ERROR_BCM88375_A0r_fields,
   6125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6126         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6127         -1,
   6128         -1,
   6129     },
   6130 #endif /* chips */
   6131 
   6132 #if defined(BCM_88375_B0)
   6133     { /* SOC_REG_INT_KAPS_MEMORY_B_ERROR_BCM88375_B0r */
   6134         soc_block_list[73],
   6135         soc_genreg,
   6136         1,
   6137         0,
   6138         0x1c00,
   6139         0,
   6140         0,
   6141         2,
   6142         soc_KAPS_MEMORY_B_ERROR_BCM88375_B0r_fields,
   6143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6144         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6145         -1,
   6146         -1,
   6147     },
   6148 #endif /* chips */
   6149 
   6150 #if defined(BCM_88675_B0)
   6151     { /* SOC_REG_INT_KAPS_MEMORY_B_ERROR_BCM88675_B0r */
   6152         soc_block_list[73],
   6153         soc_genreg,
   6154         1,
   6155         0,
   6156         0x1c00,
   6157         0,
   6158         0,
   6159         2,
   6160         soc_KAPS_MEMORY_B_ERROR_BCM88675_B0r_fields,
   6161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6162         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6163         -1,
   6164         -1,
   6165     },
   6166 #endif /* chips */
   6167 
   6168 #if defined(BCM_88675_A0)
   6169     { /* SOC_REG_INT_KAPS_MEMORY_B_ERROR_MASKr */
   6170         soc_block_list[73],
   6171         soc_genreg,
   6172         1,
   6173         0,
   6174         0x1f00,
   6175         0,
   6176         0,
   6177         2,
   6178         soc_KAPS_MEMORY_B_ERROR_MASKr_fields,
   6179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6180         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6181         -1,
   6182         -1,
   6183     },
   6184 #endif /* chips */
   6185 
   6186 #if defined(BCM_88375_A0)
   6187     { /* SOC_REG_INT_KAPS_MEMORY_B_ERROR_MASK_BCM88375_A0r */
   6188         soc_block_list[73],
   6189         soc_genreg,
   6190         1,
   6191         0,
   6192         0x1f00,
   6193         0,
   6194         0,
   6195         2,
   6196         soc_KAPS_MEMORY_B_ERROR_MASK_BCM88375_A0r_fields,
   6197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6198         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6199         -1,
   6200         -1,
   6201     },
   6202 #endif /* chips */
   6203 
   6204 #if defined(BCM_88375_B0)
   6205     { /* SOC_REG_INT_KAPS_MEMORY_B_ERROR_MASK_BCM88375_B0r */
   6206         soc_block_list[73],
   6207         soc_genreg,
   6208         1,
   6209         0,
   6210         0x1f00,
   6211         0,
   6212         0,
   6213         2,
   6214         soc_KAPS_MEMORY_B_ERROR_MASK_BCM88375_B0r_fields,
   6215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6216         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6217         -1,
   6218         -1,
   6219     },
   6220 #endif /* chips */
   6221 
   6222 #if defined(BCM_88675_B0)
   6223     { /* SOC_REG_INT_KAPS_MEMORY_B_ERROR_MASK_BCM88675_B0r */
   6224         soc_block_list[73],
   6225         soc_genreg,
   6226         1,
   6227         0,
   6228         0x1f00,
   6229         0,
   6230         0,
   6231         2,
   6232         soc_KAPS_MEMORY_B_ERROR_MASK_BCM88675_B0r_fields,
   6233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6234         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6235         -1,
   6236         -1,
   6237     },
   6238 #endif /* chips */
   6239 
   6240 #if defined(BCM_88470_A0)
   6241     { /* SOC_REG_INT_KAPS_PARITY_ERR_CNTr */
   6242         soc_block_list[73],
   6243         soc_genreg,
   6244         1,
   6245         0,
   6246         0x98,
   6247         SOC_REG_FLAG_64_BITS |
   6248                           SOC_REG_FLAG_RO,
   6249         0,
   6250         4,
   6251         soc_KAPS_PARITY_ERR_CNTr_fields,
   6252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6253         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6254         -1,
   6255         -1,
   6256     },
   6257 #endif /* chips */
   6258 
   6259 #if defined(BCM_88270_A0)
   6260     { /* SOC_REG_INT_KAPS_PARITY_ERR_CNT_BCM88270_A0r */
   6261         soc_block_list[73],
   6262         soc_genreg,
   6263         1,
   6264         0,
   6265         0x98,
   6266         SOC_REG_FLAG_64_BITS |
   6267                           SOC_REG_FLAG_RO,
   6268         0,
   6269         4,
   6270         soc_KAPS_PARITY_ERR_CNT_BCM88270_A0r_fields,
   6271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6272         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6273         -1,
   6274         -1,
   6275     },
   6276 #endif /* chips */
   6277 
   6278 #if defined(BCM_88470_B0)
   6279     { /* SOC_REG_INT_KAPS_PARITY_ERR_CNT_BCM88470_B0r */
   6280         soc_block_list[73],
   6281         soc_genreg,
   6282         1,
   6283         0,
   6284         0x98,
   6285         SOC_REG_FLAG_64_BITS |
   6286                           SOC_REG_FLAG_RO,
   6287         0,
   6288         4,
   6289         soc_KAPS_PARITY_ERR_CNT_BCM88470_B0r_fields,
   6290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6291         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6292         -1,
   6293         -1,
   6294     },
   6295 #endif /* chips */
   6296 
   6297 #if defined(BCM_88680_A0)
   6298     { /* SOC_REG_INT_KAPS_PARITY_ERR_CNT_BCM88680_A0r */
   6299         soc_block_list[73],
   6300         soc_genreg,
   6301         1,
   6302         0,
   6303         0x98,
   6304         SOC_REG_FLAG_64_BITS |
   6305                           SOC_REG_FLAG_RO,
   6306         0,
   6307         4,
   6308         soc_KAPS_PARITY_ERR_CNT_BCM88680_A0r_fields,
   6309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6310         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   6311         -1,
   6312         -1,
   6313     },
   6314 #endif /* chips */
   6315 
   6316 #if defined(BCM_88470_A0)
   6317     { /* SOC_REG_INT_KAPS_PAR_ERR_INITIATEr */
   6318         soc_block_list[73],
   6319         soc_genreg,
   6320         1,
   6321         0,
   6322         0xaa,
   6323         0,
   6324         0,
   6325         1,
   6326         soc_KAPS_PAR_ERR_INITIATEr_fields,
   6327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6328         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6329         -1,
   6330         -1,
   6331     },
   6332 #endif /* chips */
   6333 
   6334 #if defined(BCM_88270_A0)
   6335     { /* SOC_REG_INT_KAPS_PAR_ERR_INITIATE_BCM88270_A0r */
   6336         soc_block_list[73],
   6337         soc_genreg,
   6338         1,
   6339         0,
   6340         0xaa,
   6341         0,
   6342         0,
   6343         1,
   6344         soc_KAPS_PAR_ERR_INITIATE_BCM88270_A0r_fields,
   6345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6346         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6347         -1,
   6348         -1,
   6349     },
   6350 #endif /* chips */
   6351 
   6352 #if defined(BCM_88470_B0)
   6353     { /* SOC_REG_INT_KAPS_PAR_ERR_INITIATE_BCM88470_B0r */
   6354         soc_block_list[73],
   6355         soc_genreg,
   6356         1,
   6357         0,
   6358         0xaa,
   6359         0,
   6360         0,
   6361         1,
   6362         soc_KAPS_PAR_ERR_INITIATE_BCM88470_B0r_fields,
   6363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6364         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6365         -1,
   6366         -1,
   6367     },
   6368 #endif /* chips */
   6369 
   6370 #if defined(BCM_88680_A0)
   6371     { /* SOC_REG_INT_KAPS_PAR_ERR_INITIATE_BCM88680_A0r */
   6372         soc_block_list[73],
   6373         soc_genreg,
   6374         1,
   6375         0,
   6376         0xaa,
   6377         0,
   6378         0,
   6379         1,
   6380         soc_KAPS_PAR_ERR_INITIATE_BCM88680_A0r_fields,
   6381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6382         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6383         -1,
   6384         -1,
   6385     },
   6386 #endif /* chips */
   6387 
   6388 #if defined(BCM_88470_A0)
   6389     { /* SOC_REG_INT_KAPS_PAR_ERR_MEM_MASKr */
   6390         soc_block_list[73],
   6391         soc_genreg,
   6392         1,
   6393         0,
   6394         0xa0,
   6395         0,
   6396         0,
   6397         1,
   6398         soc_KAPS_PAR_ERR_MEM_MASKr_fields,
   6399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6400         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6401         -1,
   6402         -1,
   6403     },
   6404 #endif /* chips */
   6405 
   6406 #if defined(BCM_88270_A0)
   6407     { /* SOC_REG_INT_KAPS_PAR_ERR_MEM_MASK_BCM88270_A0r */
   6408         soc_block_list[73],
   6409         soc_genreg,
   6410         1,
   6411         0,
   6412         0xa0,
   6413         0,
   6414         0,
   6415         1,
   6416         soc_KAPS_PAR_ERR_MEM_MASK_BCM88270_A0r_fields,
   6417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6418         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6419         -1,
   6420         -1,
   6421     },
   6422 #endif /* chips */
   6423 
   6424 #if defined(BCM_88470_B0)
   6425     { /* SOC_REG_INT_KAPS_PAR_ERR_MEM_MASK_BCM88470_B0r */
   6426         soc_block_list[73],
   6427         soc_genreg,
   6428         1,
   6429         0,
   6430         0xa0,
   6431         0,
   6432         0,
   6433         1,
   6434         soc_KAPS_PAR_ERR_MEM_MASK_BCM88470_B0r_fields,
   6435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6436         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6437         -1,
   6438         -1,
   6439     },
   6440 #endif /* chips */
   6441 
   6442 #if defined(BCM_88680_A0)
   6443     { /* SOC_REG_INT_KAPS_PAR_ERR_MEM_MASK_BCM88680_A0r */
   6444         soc_block_list[73],
   6445         soc_genreg,
   6446         1,
   6447         0,
   6448         0xa0,
   6449         0,
   6450         0,
   6451         1,
   6452         soc_KAPS_PAR_ERR_MEM_MASK_BCM88680_A0r_fields,
   6453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6454         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6455         -1,
   6456         -1,
   6457     },
   6458 #endif /* chips */
   6459 
   6460 #if defined(BCM_88690_A0)
   6461     { /* SOC_REG_INT_KAPS_PCMI_0r */
   6462         soc_block_list[73],
   6463         soc_genreg,
   6464         1,
   6465         0,
   6466         0xb0,
   6467         0,
   6468         0,
   6469         1,
   6470         soc_KAPS_PCMI_0r_fields,
   6471         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6472         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6473         -1,
   6474         -1,
   6475     },
   6476 #endif /* chips */
   6477 
   6478 #if defined(BCM_88690_A0)
   6479     { /* SOC_REG_INT_KAPS_PCMI_1r */
   6480         soc_block_list[73],
   6481         soc_genreg,
   6482         1,
   6483         0,
   6484         0xb3,
   6485         0,
   6486         0,
   6487         1,
   6488         soc_KAPS_PCMI_1r_fields,
   6489         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6490         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6491         -1,
   6492         -1,
   6493     },
   6494 #endif /* chips */
   6495 
   6496 #if defined(BCM_88690_A0)
   6497     { /* SOC_REG_INT_KAPS_PCMI_2r */
   6498         soc_block_list[73],
   6499         soc_genreg,
   6500         1,
   6501         0,
   6502         0xb6,
   6503         0,
   6504         0,
   6505         1,
   6506         soc_KAPS_PCMI_2r_fields,
   6507         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6508         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6509         -1,
   6510         -1,
   6511     },
   6512 #endif /* chips */
   6513 
   6514 #if defined(BCM_88690_A0)
   6515     { /* SOC_REG_INT_KAPS_PCMI_3r */
   6516         soc_block_list[73],
   6517         soc_genreg,
   6518         1,
   6519         0,
   6520         0xb9,
   6521         0,
   6522         0,
   6523         1,
   6524         soc_KAPS_PCMI_3r_fields,
   6525         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6526         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6527         -1,
   6528         -1,
   6529     },
   6530 #endif /* chips */
   6531 
   6532 #if defined(BCM_88690_A0)
   6533     { /* SOC_REG_INT_KAPS_PCMI_4r */
   6534         soc_block_list[73],
   6535         soc_genreg,
   6536         1,
   6537         0,
   6538         0xbc,
   6539         0,
   6540         0,
   6541         1,
   6542         soc_KAPS_PCMI_4r_fields,
   6543         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6544         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6545         -1,
   6546         -1,
   6547     },
   6548 #endif /* chips */
   6549 
   6550 #if defined(BCM_88690_B0)
   6551     { /* SOC_REG_INT_KAPS_PCMI_0_BCM88690_B0r */
   6552         soc_block_list[73],
   6553         soc_genreg,
   6554         1,
   6555         0,
   6556         0xb0,
   6557         0,
   6558         0,
   6559         1,
   6560         soc_KAPS_PCMI_0_BCM88690_B0r_fields,
   6561         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6562         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6563         -1,
   6564         -1,
   6565     },
   6566 #endif /* chips */
   6567 
   6568 #if defined(BCM_88690_A0)
   6569     { /* SOC_REG_INT_KAPS_PCMI_0_Sr */
   6570         soc_block_list[73],
   6571         soc_genreg,
   6572         1,
   6573         0,
   6574         0xb1,
   6575         SOC_REG_FLAG_RO,
   6576         0,
   6577         3,
   6578         soc_KAPS_PCMI_0_Sr_fields,
   6579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6580         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6581         -1,
   6582         -1,
   6583     },
   6584 #endif /* chips */
   6585 
   6586 #if defined(BCM_88690_B0)
   6587     { /* SOC_REG_INT_KAPS_PCMI_0_S_BCM88690_B0r */
   6588         soc_block_list[73],
   6589         soc_genreg,
   6590         1,
   6591         0,
   6592         0xb1,
   6593         SOC_REG_FLAG_RO,
   6594         0,
   6595         3,
   6596         soc_KAPS_PCMI_0_S_BCM88690_B0r_fields,
   6597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6598         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6599         -1,
   6600         -1,
   6601     },
   6602 #endif /* chips */
   6603 
   6604 #if defined(BCM_88690_A0)
   6605     { /* SOC_REG_INT_KAPS_PCMI_0_Tr */
   6606         soc_block_list[73],
   6607         soc_genreg,
   6608         1,
   6609         0,
   6610         0xb2,
   6611         0,
   6612         0,
   6613         2,
   6614         soc_KAPS_PCMI_0_Tr_fields,
   6615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6616         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6617         -1,
   6618         -1,
   6619     },
   6620 #endif /* chips */
   6621 
   6622 #if defined(BCM_88690_B0)
   6623     { /* SOC_REG_INT_KAPS_PCMI_0_T_BCM88690_B0r */
   6624         soc_block_list[73],
   6625         soc_genreg,
   6626         1,
   6627         0,
   6628         0xb2,
   6629         0,
   6630         0,
   6631         2,
   6632         soc_KAPS_PCMI_0_T_BCM88690_B0r_fields,
   6633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6634         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6635         -1,
   6636         -1,
   6637     },
   6638 #endif /* chips */
   6639 
   6640 #if defined(BCM_88690_B0)
   6641     { /* SOC_REG_INT_KAPS_PCMI_1_BCM88690_B0r */
   6642         soc_block_list[73],
   6643         soc_genreg,
   6644         1,
   6645         0,
   6646         0xb3,
   6647         0,
   6648         0,
   6649         1,
   6650         soc_KAPS_PCMI_1_BCM88690_B0r_fields,
   6651         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6652         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6653         -1,
   6654         -1,
   6655     },
   6656 #endif /* chips */
   6657 
   6658 #if defined(BCM_88690_A0)
   6659     { /* SOC_REG_INT_KAPS_PCMI_1_Sr */
   6660         soc_block_list[73],
   6661         soc_genreg,
   6662         1,
   6663         0,
   6664         0xb4,
   6665         SOC_REG_FLAG_RO,
   6666         0,
   6667         3,
   6668         soc_KAPS_PCMI_1_Sr_fields,
   6669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6670         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6671         -1,
   6672         -1,
   6673     },
   6674 #endif /* chips */
   6675 
   6676 #if defined(BCM_88690_B0)
   6677     { /* SOC_REG_INT_KAPS_PCMI_1_S_BCM88690_B0r */
   6678         soc_block_list[73],
   6679         soc_genreg,
   6680         1,
   6681         0,
   6682         0xb4,
   6683         SOC_REG_FLAG_RO,
   6684         0,
   6685         3,
   6686         soc_KAPS_PCMI_1_S_BCM88690_B0r_fields,
   6687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6689         -1,
   6690         -1,
   6691     },
   6692 #endif /* chips */
   6693 
   6694 #if defined(BCM_88690_A0)
   6695     { /* SOC_REG_INT_KAPS_PCMI_1_Tr */
   6696         soc_block_list[73],
   6697         soc_genreg,
   6698         1,
   6699         0,
   6700         0xb5,
   6701         0,
   6702         0,
   6703         2,
   6704         soc_KAPS_PCMI_1_Tr_fields,
   6705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6706         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6707         -1,
   6708         -1,
   6709     },
   6710 #endif /* chips */
   6711 
   6712 #if defined(BCM_88690_B0)
   6713     { /* SOC_REG_INT_KAPS_PCMI_1_T_BCM88690_B0r */
   6714         soc_block_list[73],
   6715         soc_genreg,
   6716         1,
   6717         0,
   6718         0xb5,
   6719         0,
   6720         0,
   6721         2,
   6722         soc_KAPS_PCMI_1_T_BCM88690_B0r_fields,
   6723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6724         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6725         -1,
   6726         -1,
   6727     },
   6728 #endif /* chips */
   6729 
   6730 #if defined(BCM_88690_B0)
   6731     { /* SOC_REG_INT_KAPS_PCMI_2_BCM88690_B0r */
   6732         soc_block_list[73],
   6733         soc_genreg,
   6734         1,
   6735         0,
   6736         0xb6,
   6737         0,
   6738         0,
   6739         1,
   6740         soc_KAPS_PCMI_2_BCM88690_B0r_fields,
   6741         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6743         -1,
   6744         -1,
   6745     },
   6746 #endif /* chips */
   6747 
   6748 #if defined(BCM_88690_A0)
   6749     { /* SOC_REG_INT_KAPS_PCMI_2_Sr */
   6750         soc_block_list[73],
   6751         soc_genreg,
   6752         1,
   6753         0,
   6754         0xb7,
   6755         SOC_REG_FLAG_RO,
   6756         0,
   6757         3,
   6758         soc_KAPS_PCMI_2_Sr_fields,
   6759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6760         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6761         -1,
   6762         -1,
   6763     },
   6764 #endif /* chips */
   6765 
   6766 #if defined(BCM_88690_B0)
   6767     { /* SOC_REG_INT_KAPS_PCMI_2_S_BCM88690_B0r */
   6768         soc_block_list[73],
   6769         soc_genreg,
   6770         1,
   6771         0,
   6772         0xb7,
   6773         SOC_REG_FLAG_RO,
   6774         0,
   6775         3,
   6776         soc_KAPS_PCMI_2_S_BCM88690_B0r_fields,
   6777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6778         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6779         -1,
   6780         -1,
   6781     },
   6782 #endif /* chips */
   6783 
   6784 #if defined(BCM_88690_A0)
   6785     { /* SOC_REG_INT_KAPS_PCMI_2_Tr */
   6786         soc_block_list[73],
   6787         soc_genreg,
   6788         1,
   6789         0,
   6790         0xb8,
   6791         0,
   6792         0,
   6793         2,
   6794         soc_KAPS_PCMI_2_Tr_fields,
   6795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6796         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6797         -1,
   6798         -1,
   6799     },
   6800 #endif /* chips */
   6801 
   6802 #if defined(BCM_88690_B0)
   6803     { /* SOC_REG_INT_KAPS_PCMI_2_T_BCM88690_B0r */
   6804         soc_block_list[73],
   6805         soc_genreg,
   6806         1,
   6807         0,
   6808         0xb8,
   6809         0,
   6810         0,
   6811         2,
   6812         soc_KAPS_PCMI_2_T_BCM88690_B0r_fields,
   6813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6814         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6815         -1,
   6816         -1,
   6817     },
   6818 #endif /* chips */
   6819 
   6820 #if defined(BCM_88690_B0)
   6821     { /* SOC_REG_INT_KAPS_PCMI_3_BCM88690_B0r */
   6822         soc_block_list[73],
   6823         soc_genreg,
   6824         1,
   6825         0,
   6826         0xb9,
   6827         0,
   6828         0,
   6829         1,
   6830         soc_KAPS_PCMI_3_BCM88690_B0r_fields,
   6831         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6832         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6833         -1,
   6834         -1,
   6835     },
   6836 #endif /* chips */
   6837 
   6838 #if defined(BCM_88690_A0)
   6839     { /* SOC_REG_INT_KAPS_PCMI_3_Sr */
   6840         soc_block_list[73],
   6841         soc_genreg,
   6842         1,
   6843         0,
   6844         0xba,
   6845         SOC_REG_FLAG_RO,
   6846         0,
   6847         3,
   6848         soc_KAPS_PCMI_3_Sr_fields,
   6849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6851         -1,
   6852         -1,
   6853     },
   6854 #endif /* chips */
   6855 
   6856 #if defined(BCM_88690_B0)
   6857     { /* SOC_REG_INT_KAPS_PCMI_3_S_BCM88690_B0r */
   6858         soc_block_list[73],
   6859         soc_genreg,
   6860         1,
   6861         0,
   6862         0xba,
   6863         SOC_REG_FLAG_RO,
   6864         0,
   6865         3,
   6866         soc_KAPS_PCMI_3_S_BCM88690_B0r_fields,
   6867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6868         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6869         -1,
   6870         -1,
   6871     },
   6872 #endif /* chips */
   6873 
   6874 #if defined(BCM_88690_A0)
   6875     { /* SOC_REG_INT_KAPS_PCMI_3_Tr */
   6876         soc_block_list[73],
   6877         soc_genreg,
   6878         1,
   6879         0,
   6880         0xbb,
   6881         0,
   6882         0,
   6883         2,
   6884         soc_KAPS_PCMI_3_Tr_fields,
   6885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6886         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6887         -1,
   6888         -1,
   6889     },
   6890 #endif /* chips */
   6891 
   6892 #if defined(BCM_88690_B0)
   6893     { /* SOC_REG_INT_KAPS_PCMI_3_T_BCM88690_B0r */
   6894         soc_block_list[73],
   6895         soc_genreg,
   6896         1,
   6897         0,
   6898         0xbb,
   6899         0,
   6900         0,
   6901         2,
   6902         soc_KAPS_PCMI_3_T_BCM88690_B0r_fields,
   6903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6904         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6905         -1,
   6906         -1,
   6907     },
   6908 #endif /* chips */
   6909 
   6910 #if defined(BCM_88690_B0)
   6911     { /* SOC_REG_INT_KAPS_PCMI_4_BCM88690_B0r */
   6912         soc_block_list[73],
   6913         soc_genreg,
   6914         1,
   6915         0,
   6916         0xbc,
   6917         0,
   6918         0,
   6919         1,
   6920         soc_KAPS_PCMI_4_BCM88690_B0r_fields,
   6921         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   6922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6923         -1,
   6924         -1,
   6925     },
   6926 #endif /* chips */
   6927 
   6928 #if defined(BCM_88690_A0)
   6929     { /* SOC_REG_INT_KAPS_PCMI_4_Sr */
   6930         soc_block_list[73],
   6931         soc_genreg,
   6932         1,
   6933         0,
   6934         0xbd,
   6935         SOC_REG_FLAG_RO,
   6936         0,
   6937         3,
   6938         soc_KAPS_PCMI_4_Sr_fields,
   6939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6941         -1,
   6942         -1,
   6943     },
   6944 #endif /* chips */
   6945 
   6946 #if defined(BCM_88690_B0)
   6947     { /* SOC_REG_INT_KAPS_PCMI_4_S_BCM88690_B0r */
   6948         soc_block_list[73],
   6949         soc_genreg,
   6950         1,
   6951         0,
   6952         0xbd,
   6953         SOC_REG_FLAG_RO,
   6954         0,
   6955         3,
   6956         soc_KAPS_PCMI_4_S_BCM88690_B0r_fields,
   6957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6959         -1,
   6960         -1,
   6961     },
   6962 #endif /* chips */
   6963 
   6964 #if defined(BCM_88690_A0)
   6965     { /* SOC_REG_INT_KAPS_PCMI_4_Tr */
   6966         soc_block_list[73],
   6967         soc_genreg,
   6968         1,
   6969         0,
   6970         0xbe,
   6971         0,
   6972         0,
   6973         2,
   6974         soc_KAPS_PCMI_4_Tr_fields,
   6975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6976         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6977         -1,
   6978         -1,
   6979     },
   6980 #endif /* chips */
   6981 
   6982 #if defined(BCM_88690_B0)
   6983     { /* SOC_REG_INT_KAPS_PCMI_4_T_BCM88690_B0r */
   6984         soc_block_list[73],
   6985         soc_genreg,
   6986         1,
   6987         0,
   6988         0xbe,
   6989         0,
   6990         0,
   6991         2,
   6992         soc_KAPS_PCMI_4_T_BCM88690_B0r_fields,
   6993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6994         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   6995         -1,
   6996         -1,
   6997     },
   6998 #endif /* chips */
   6999 
   7000 #if defined(BCM_88675_A0)
   7001     { /* SOC_REG_INT_KAPS_PD_ASSIST_DEBUGr */
   7002         soc_block_list[73],
   7003         soc_genreg,
   7004         1,
   7005         0,
   7006         0x8800,
   7007         0,
   7008         0,
   7009         2,
   7010         soc_KAPS_PD_ASSIST_DEBUGr_fields,
   7011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7012         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7013         -1,
   7014         -1,
   7015     },
   7016 #endif /* chips */
   7017 
   7018 #if defined(BCM_88375_A0)
   7019     { /* SOC_REG_INT_KAPS_PD_ASSIST_DEBUG_BCM88375_A0r */
   7020         soc_block_list[73],
   7021         soc_genreg,
   7022         1,
   7023         0,
   7024         0x8800,
   7025         0,
   7026         0,
   7027         2,
   7028         soc_KAPS_PD_ASSIST_DEBUG_BCM88375_A0r_fields,
   7029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7030         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7031         -1,
   7032         -1,
   7033     },
   7034 #endif /* chips */
   7035 
   7036 #if defined(BCM_88375_B0)
   7037     { /* SOC_REG_INT_KAPS_PD_ASSIST_DEBUG_BCM88375_B0r */
   7038         soc_block_list[73],
   7039         soc_genreg,
   7040         1,
   7041         0,
   7042         0x8800,
   7043         0,
   7044         0,
   7045         2,
   7046         soc_KAPS_PD_ASSIST_DEBUG_BCM88375_B0r_fields,
   7047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7048         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7049         -1,
   7050         -1,
   7051     },
   7052 #endif /* chips */
   7053 
   7054 #if defined(BCM_88675_B0)
   7055     { /* SOC_REG_INT_KAPS_PD_ASSIST_DEBUG_BCM88675_B0r */
   7056         soc_block_list[73],
   7057         soc_genreg,
   7058         1,
   7059         0,
   7060         0x8800,
   7061         0,
   7062         0,
   7063         2,
   7064         soc_KAPS_PD_ASSIST_DEBUG_BCM88675_B0r_fields,
   7065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7066         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7067         -1,
   7068         -1,
   7069     },
   7070 #endif /* chips */
   7071 
   7072 #if defined(BCM_88270_A0)
   7073     { /* SOC_REG_INT_KAPS_READ_DUMP_SINGLE_CMD_CNTr */
   7074         soc_block_list[73],
   7075         soc_genreg,
   7076         1,
   7077         0,
   7078         0x146,
   7079         SOC_REG_FLAG_RO,
   7080         0,
   7081         2,
   7082         soc_KAPS_READ_DUMP_SINGLE_CMD_CNTr_fields,
   7083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7084         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7085         -1,
   7086         -1,
   7087     },
   7088 #endif /* chips */
   7089 
   7090 #if defined(BCM_88680_A0)
   7091     { /* SOC_REG_INT_KAPS_READ_DUMP_SINGLE_CMD_CNT_BCM88680_A0r */
   7092         soc_block_list[73],
   7093         soc_genreg,
   7094         1,
   7095         0,
   7096         0x18c,
   7097         SOC_REG_FLAG_RO,
   7098         0,
   7099         2,
   7100         soc_KAPS_READ_DUMP_SINGLE_CMD_CNT_BCM88680_A0r_fields,
   7101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7102         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7103         -1,
   7104         -1,
   7105     },
   7106 #endif /* chips */
   7107 
   7108 #if defined(BCM_88690_A0)
   7109     { /* SOC_REG_INT_KAPS_REG_0041r */
   7110         soc_block_list[73],
   7111         soc_genreg,
   7112         1,
   7113         0,
   7114         0x41,
   7115         0,
   7116         0,
   7117         1,
   7118         soc_KAPS_REG_0041r_fields,
   7119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7120         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7121         -1,
   7122         -1,
   7123     },
   7124 #endif /* chips */
   7125 
   7126 #if defined(BCM_88690_A0)
   7127     { /* SOC_REG_INT_KAPS_REG_0149r */
   7128         soc_block_list[73],
   7129         soc_genreg,
   7130         1,
   7131         0,
   7132         0x149,
   7133         SOC_REG_FLAG_ABOVE_64_BITS,
   7134         0,
   7135         15,
   7136         soc_KAPS_REG_0149r_fields,
   7137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7138         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7139         -1,
   7140         -1,
   7141     },
   7142 #endif /* chips */
   7143 
   7144 #if defined(BCM_88690_B0)
   7145     { /* SOC_REG_INT_KAPS_REG_0041_BCM88690_B0r */
   7146         soc_block_list[73],
   7147         soc_genreg,
   7148         1,
   7149         0,
   7150         0x41,
   7151         0,
   7152         0,
   7153         1,
   7154         soc_KAPS_REG_0041_BCM88690_B0r_fields,
   7155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7156         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7157         -1,
   7158         -1,
   7159     },
   7160 #endif /* chips */
   7161 
   7162 #if defined(BCM_88690_A0)
   7163     { /* SOC_REG_INT_KAPS_REG_00A4r */
   7164         soc_block_list[73],
   7165         soc_genreg,
   7166         1,
   7167         0,
   7168         0xa4,
   7169         0,
   7170         0,
   7171         18,
   7172         soc_KAPS_REG_00A4r_fields,
   7173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7174         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   7175         -1,
   7176         -1,
   7177     },
   7178 #endif /* chips */
   7179 
   7180 #if defined(BCM_88690_A0)
   7181     { /* SOC_REG_INT_KAPS_REG_00A6r */
   7182         soc_block_list[73],
   7183         soc_genreg,
   7184         1,
   7185         0,
   7186         0xa6,
   7187         0,
   7188         0,
   7189         18,
   7190         soc_KAPS_REG_00A6r_fields,
   7191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7192         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   7193         -1,
   7194         -1,
   7195     },
   7196 #endif /* chips */
   7197 
   7198 #if defined(BCM_88690_B0)
   7199     { /* SOC_REG_INT_KAPS_REG_00A4_BCM88690_B0r */
   7200         soc_block_list[73],
   7201         soc_genreg,
   7202         1,
   7203         0,
   7204         0xa4,
   7205         0,
   7206         0,
   7207         18,
   7208         soc_KAPS_REG_00A4_BCM88690_B0r_fields,
   7209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7210         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   7211         -1,
   7212         -1,
   7213     },
   7214 #endif /* chips */
   7215 
   7216 #if defined(BCM_88690_B0)
   7217     { /* SOC_REG_INT_KAPS_REG_00A6_BCM88690_B0r */
   7218         soc_block_list[73],
   7219         soc_genreg,
   7220         1,
   7221         0,
   7222         0xa6,
   7223         0,
   7224         0,
   7225         18,
   7226         soc_KAPS_REG_00A6_BCM88690_B0r_fields,
   7227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7228         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   7229         -1,
   7230         -1,
   7231     },
   7232 #endif /* chips */
   7233 
   7234 #if defined(BCM_88690_A0)
   7235     { /* SOC_REG_INT_KAPS_REG_00C2r */
   7236         soc_block_list[73],
   7237         soc_genreg,
   7238         1,
   7239         0,
   7240         0xc2,
   7241         0,
   7242         0,
   7243         6,
   7244         soc_KAPS_REG_00C2r_fields,
   7245         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   7246         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   7247         -1,
   7248         -1,
   7249     },
   7250 #endif /* chips */
   7251 
   7252 #if defined(BCM_88690_B0)
   7253     { /* SOC_REG_INT_KAPS_REG_00C2_BCM88690_B0r */
   7254         soc_block_list[73],
   7255         soc_genreg,
   7256         1,
   7257         0,
   7258         0xc2,
   7259         0,
   7260         0,
   7261         6,
   7262         soc_KAPS_REG_00C2_BCM88690_B0r_fields,
   7263         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   7264         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   7265         -1,
   7266         -1,
   7267     },
   7268 #endif /* chips */
   7269 
   7270 #if defined(BCM_88690_B0)
   7271     { /* SOC_REG_INT_KAPS_REG_0149_BCM88690_B0r */
   7272         soc_block_list[73],
   7273         soc_genreg,
   7274         1,
   7275         0,
   7276         0x149,
   7277         SOC_REG_FLAG_ABOVE_64_BITS,
   7278         0,
   7279         15,
   7280         soc_KAPS_REG_0149_BCM88690_B0r_fields,
   7281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7282         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7283         -1,
   7284         -1,
   7285     },
   7286 #endif /* chips */
   7287 
   7288 #if defined(BCM_88690_A0)
   7289     { /* SOC_REG_INT_KAPS_REG_014Dr */
   7290         soc_block_list[73],
   7291         soc_genreg,
   7292         1,
   7293         0,
   7294         0x14d,
   7295         SOC_REG_FLAG_64_BITS |
   7296                           SOC_REG_FLAG_RO,
   7297         0,
   7298         3,
   7299         soc_KAPS_REG_014Dr_fields,
   7300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7301         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
   7302         -1,
   7303         -1,
   7304     },
   7305 #endif /* chips */
   7306 
   7307 #if defined(BCM_88690_B0)
   7308     { /* SOC_REG_INT_KAPS_REG_014D_BCM88690_B0r */
   7309         soc_block_list[73],
   7310         soc_genreg,
   7311         1,
   7312         0,
   7313         0x14d,
   7314         SOC_REG_FLAG_64_BITS |
   7315                           SOC_REG_FLAG_RO,
   7316         0,
   7317         3,
   7318         soc_KAPS_REG_014D_BCM88690_B0r_fields,
   7319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7320         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
   7321         -1,
   7322         -1,
   7323     },
   7324 #endif /* chips */
   7325 
   7326 #if defined(BCM_88470_A0)
   7327     { /* SOC_REG_INT_KAPS_RESERVED_MIRROR_ADDRr */
   7328         soc_block_list[73],
   7329         soc_genreg,
   7330         1,
   7331         0,
   7332         0x85,
   7333         0,
   7334         0,
   7335         2,
   7336         soc_KAPS_RESERVED_MIRROR_ADDRr_fields,
   7337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7338         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   7339         -1,
   7340         -1,
   7341     },
   7342 #endif /* chips */
   7343 
   7344 #if defined(BCM_88270_A0)
   7345     { /* SOC_REG_INT_KAPS_RESERVED_MIRROR_ADDR_BCM88270_A0r */
   7346         soc_block_list[73],
   7347         soc_genreg,
   7348         1,
   7349         0,
   7350         0x85,
   7351         0,
   7352         0,
   7353         2,
   7354         soc_KAPS_RESERVED_MIRROR_ADDR_BCM88270_A0r_fields,
   7355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7356         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   7357         -1,
   7358         -1,
   7359     },
   7360 #endif /* chips */
   7361 
   7362 #if defined(BCM_88470_B0)
   7363     { /* SOC_REG_INT_KAPS_RESERVED_MIRROR_ADDR_BCM88470_B0r */
   7364         soc_block_list[73],
   7365         soc_genreg,
   7366         1,
   7367         0,
   7368         0x85,
   7369         0,
   7370         0,
   7371         2,
   7372         soc_KAPS_RESERVED_MIRROR_ADDR_BCM88470_B0r_fields,
   7373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7374         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   7375         -1,
   7376         -1,
   7377     },
   7378 #endif /* chips */
   7379 
   7380 #if defined(BCM_88680_A0)
   7381     { /* SOC_REG_INT_KAPS_RESERVED_MIRROR_ADDR_BCM88680_A0r */
   7382         soc_block_list[73],
   7383         soc_genreg,
   7384         1,
   7385         0,
   7386         0x85,
   7387         0,
   7388         0,
   7389         2,
   7390         soc_KAPS_RESERVED_MIRROR_ADDR_BCM88680_A0r_fields,
   7391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7392         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   7393         -1,
   7394         -1,
   7395     },
   7396 #endif /* chips */
   7397 
   7398 #if defined(BCM_88690_A0)
   7399     { /* SOC_REG_INT_KAPS_RESERVED_MIRROR_ADDR_BCM88690_A0r */
   7400         soc_block_list[73],
   7401         soc_genreg,
   7402         1,
   7403         0,
   7404         0x85,
   7405         0,
   7406         0,
   7407         2,
   7408         soc_KAPS_RESERVED_MIRROR_ADDR_BCM88690_A0r_fields,
   7409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7410         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   7411         -1,
   7412         -1,
   7413     },
   7414 #endif /* chips */
   7415 
   7416 #if defined(BCM_88690_B0)
   7417     { /* SOC_REG_INT_KAPS_RESERVED_MIRROR_ADDR_BCM88690_B0r */
   7418         soc_block_list[73],
   7419         soc_genreg,
   7420         1,
   7421         0,
   7422         0x85,
   7423         0,
   7424         0,
   7425         2,
   7426         soc_KAPS_RESERVED_MIRROR_ADDR_BCM88690_B0r_fields,
   7427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7428         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   7429         -1,
   7430         -1,
   7431     },
   7432 #endif /* chips */
   7433 
   7434 #if defined(BCM_88470_A0)
   7435     { /* SOC_REG_INT_KAPS_RESERVED_MTCDr */
   7436         soc_block_list[73],
   7437         soc_genreg,
   7438         1,
   7439         0,
   7440         0xae,
   7441         0,
   7442         0,
   7443         6,
   7444         soc_KAPS_RESERVED_MTCDr_fields,
   7445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7446         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   7447         -1,
   7448         -1,
   7449     },
   7450 #endif /* chips */
   7451 
   7452 #if defined(BCM_88270_A0)
   7453     { /* SOC_REG_INT_KAPS_RESERVED_MTCD_BCM88270_A0r */
   7454         soc_block_list[73],
   7455         soc_genreg,
   7456         1,
   7457         0,
   7458         0xae,
   7459         0,
   7460         0,
   7461         6,
   7462         soc_KAPS_RESERVED_MTCD_BCM88270_A0r_fields,
   7463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7464         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   7465         -1,
   7466         -1,
   7467     },
   7468 #endif /* chips */
   7469 
   7470 #if defined(BCM_88470_B0)
   7471     { /* SOC_REG_INT_KAPS_RESERVED_MTCD_BCM88470_B0r */
   7472         soc_block_list[73],
   7473         soc_genreg,
   7474         1,
   7475         0,
   7476         0xae,
   7477         0,
   7478         0,
   7479         6,
   7480         soc_KAPS_RESERVED_MTCD_BCM88470_B0r_fields,
   7481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7482         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   7483         -1,
   7484         -1,
   7485     },
   7486 #endif /* chips */
   7487 
   7488 #if defined(BCM_88680_A0)
   7489     { /* SOC_REG_INT_KAPS_RESERVED_MTCD_BCM88680_A0r */
   7490         soc_block_list[73],
   7491         soc_genreg,
   7492         1,
   7493         0,
   7494         0xae,
   7495         0,
   7496         0,
   7497         6,
   7498         soc_KAPS_RESERVED_MTCD_BCM88680_A0r_fields,
   7499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7500         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   7501         -1,
   7502         -1,
   7503     },
   7504 #endif /* chips */
   7505 
   7506 #if defined(BCM_88690_A0)
   7507     { /* SOC_REG_INT_KAPS_RESERVED_MTCD_BCM88690_A0r */
   7508         soc_block_list[73],
   7509         soc_genreg,
   7510         1,
   7511         0,
   7512         0xae,
   7513         0,
   7514         0,
   7515         6,
   7516         soc_KAPS_RESERVED_MTCD_BCM88690_A0r_fields,
   7517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7518         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   7519         -1,
   7520         -1,
   7521     },
   7522 #endif /* chips */
   7523 
   7524 #if defined(BCM_88690_B0)
   7525     { /* SOC_REG_INT_KAPS_RESERVED_MTCD_BCM88690_B0r */
   7526         soc_block_list[73],
   7527         soc_genreg,
   7528         1,
   7529         0,
   7530         0xae,
   7531         0,
   7532         0,
   7533         6,
   7534         soc_KAPS_RESERVED_MTCD_BCM88690_B0r_fields,
   7535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7536         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   7537         -1,
   7538         -1,
   7539     },
   7540 #endif /* chips */
   7541 
   7542 #if defined(BCM_88470_A0)
   7543     { /* SOC_REG_INT_KAPS_RESERVED_MTCPr */
   7544         soc_block_list[73],
   7545         soc_genreg,
   7546         1,
   7547         0,
   7548         0xad,
   7549         SOC_REG_FLAG_64_BITS,
   7550         0,
   7551         17,
   7552         soc_KAPS_RESERVED_MTCPr_fields,
   7553         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   7554         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   7555         -1,
   7556         -1,
   7557     },
   7558 #endif /* chips */
   7559 
   7560 #if defined(BCM_88270_A0)
   7561     { /* SOC_REG_INT_KAPS_RESERVED_MTCP_BCM88270_A0r */
   7562         soc_block_list[73],
   7563         soc_genreg,
   7564         1,
   7565         0,
   7566         0xad,
   7567         SOC_REG_FLAG_64_BITS,
   7568         0,
   7569         17,
   7570         soc_KAPS_RESERVED_MTCP_BCM88270_A0r_fields,
   7571         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   7572         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   7573         -1,
   7574         -1,
   7575     },
   7576 #endif /* chips */
   7577 
   7578 #if defined(BCM_88470_B0)
   7579     { /* SOC_REG_INT_KAPS_RESERVED_MTCP_BCM88470_B0r */
   7580         soc_block_list[73],
   7581         soc_genreg,
   7582         1,
   7583         0,
   7584         0xad,
   7585         SOC_REG_FLAG_64_BITS,
   7586         0,
   7587         17,
   7588         soc_KAPS_RESERVED_MTCP_BCM88470_B0r_fields,
   7589         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   7590         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   7591         -1,
   7592         -1,
   7593     },
   7594 #endif /* chips */
   7595 
   7596 #if defined(BCM_88680_A0)
   7597     { /* SOC_REG_INT_KAPS_RESERVED_MTCP_BCM88680_A0r */
   7598         soc_block_list[73],
   7599         soc_genreg,
   7600         1,
   7601         0,
   7602         0xad,
   7603         SOC_REG_FLAG_64_BITS,
   7604         0,
   7605         17,
   7606         soc_KAPS_RESERVED_MTCP_BCM88680_A0r_fields,
   7607         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   7608         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   7609         -1,
   7610         -1,
   7611     },
   7612 #endif /* chips */
   7613 
   7614 #if defined(BCM_88690_A0)
   7615     { /* SOC_REG_INT_KAPS_RESERVED_MTCP_BCM88690_A0r */
   7616         soc_block_list[73],
   7617         soc_genreg,
   7618         1,
   7619         0,
   7620         0xad,
   7621         SOC_REG_FLAG_64_BITS,
   7622         0,
   7623         17,
   7624         soc_KAPS_RESERVED_MTCP_BCM88690_A0r_fields,
   7625         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   7626         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   7627         -1,
   7628         -1,
   7629     },
   7630 #endif /* chips */
   7631 
   7632 #if defined(BCM_88690_B0)
   7633     { /* SOC_REG_INT_KAPS_RESERVED_MTCP_BCM88690_B0r */
   7634         soc_block_list[73],
   7635         soc_genreg,
   7636         1,
   7637         0,
   7638         0xad,
   7639         SOC_REG_FLAG_64_BITS,
   7640         0,
   7641         17,
   7642         soc_KAPS_RESERVED_MTCP_BCM88690_B0r_fields,
   7643         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   7644         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   7645         -1,
   7646         -1,
   7647     },
   7648 #endif /* chips */
   7649 
   7650 #if defined(BCM_88470_A0)
   7651     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_0r */
   7652         soc_block_list[73],
   7653         soc_genreg,
   7654         1,
   7655         0,
   7656         0xb0,
   7657         0,
   7658         0,
   7659         1,
   7660         soc_KAPS_RESERVED_PCMI_0r_fields,
   7661         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7662         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7663         -1,
   7664         -1,
   7665     },
   7666 #endif /* chips */
   7667 
   7668 #if defined(BCM_88470_A0)
   7669     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_1r */
   7670         soc_block_list[73],
   7671         soc_genreg,
   7672         1,
   7673         0,
   7674         0xb3,
   7675         0,
   7676         0,
   7677         1,
   7678         soc_KAPS_RESERVED_PCMI_1r_fields,
   7679         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7680         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7681         -1,
   7682         -1,
   7683     },
   7684 #endif /* chips */
   7685 
   7686 #if defined(BCM_88470_A0)
   7687     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_2r */
   7688         soc_block_list[73],
   7689         soc_genreg,
   7690         1,
   7691         0,
   7692         0xb6,
   7693         0,
   7694         0,
   7695         1,
   7696         soc_KAPS_RESERVED_PCMI_2r_fields,
   7697         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7698         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7699         -1,
   7700         -1,
   7701     },
   7702 #endif /* chips */
   7703 
   7704 #if defined(BCM_88470_A0)
   7705     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_3r */
   7706         soc_block_list[73],
   7707         soc_genreg,
   7708         1,
   7709         0,
   7710         0xb9,
   7711         0,
   7712         0,
   7713         1,
   7714         soc_KAPS_RESERVED_PCMI_3r_fields,
   7715         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7716         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7717         -1,
   7718         -1,
   7719     },
   7720 #endif /* chips */
   7721 
   7722 #if defined(BCM_88470_A0)
   7723     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_4r */
   7724         soc_block_list[73],
   7725         soc_genreg,
   7726         1,
   7727         0,
   7728         0xbc,
   7729         0,
   7730         0,
   7731         1,
   7732         soc_KAPS_RESERVED_PCMI_4r_fields,
   7733         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7734         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7735         -1,
   7736         -1,
   7737     },
   7738 #endif /* chips */
   7739 
   7740 #if defined(BCM_88470_B0)
   7741     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_0_BCM88470_B0r */
   7742         soc_block_list[73],
   7743         soc_genreg,
   7744         1,
   7745         0,
   7746         0xb0,
   7747         0,
   7748         0,
   7749         1,
   7750         soc_KAPS_RESERVED_PCMI_0_BCM88470_B0r_fields,
   7751         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7752         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7753         -1,
   7754         -1,
   7755     },
   7756 #endif /* chips */
   7757 
   7758 #if defined(BCM_88680_A0)
   7759     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_0_BCM88680_A0r */
   7760         soc_block_list[73],
   7761         soc_genreg,
   7762         1,
   7763         0,
   7764         0xb0,
   7765         0,
   7766         0,
   7767         1,
   7768         soc_KAPS_RESERVED_PCMI_0_BCM88680_A0r_fields,
   7769         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7770         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7771         -1,
   7772         -1,
   7773     },
   7774 #endif /* chips */
   7775 
   7776 #if defined(BCM_88470_A0)
   7777     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_0_Sr */
   7778         soc_block_list[73],
   7779         soc_genreg,
   7780         1,
   7781         0,
   7782         0xb1,
   7783         SOC_REG_FLAG_RO,
   7784         0,
   7785         3,
   7786         soc_KAPS_RESERVED_PCMI_0_Sr_fields,
   7787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7788         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7789         -1,
   7790         -1,
   7791     },
   7792 #endif /* chips */
   7793 
   7794 #if defined(BCM_88470_B0)
   7795     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_0_S_BCM88470_B0r */
   7796         soc_block_list[73],
   7797         soc_genreg,
   7798         1,
   7799         0,
   7800         0xb1,
   7801         SOC_REG_FLAG_RO,
   7802         0,
   7803         3,
   7804         soc_KAPS_RESERVED_PCMI_0_S_BCM88470_B0r_fields,
   7805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7806         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7807         -1,
   7808         -1,
   7809     },
   7810 #endif /* chips */
   7811 
   7812 #if defined(BCM_88680_A0)
   7813     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_0_S_BCM88680_A0r */
   7814         soc_block_list[73],
   7815         soc_genreg,
   7816         1,
   7817         0,
   7818         0xb1,
   7819         SOC_REG_FLAG_RO,
   7820         0,
   7821         3,
   7822         soc_KAPS_RESERVED_PCMI_0_S_BCM88680_A0r_fields,
   7823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7824         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7825         -1,
   7826         -1,
   7827     },
   7828 #endif /* chips */
   7829 
   7830 #if defined(BCM_88470_A0)
   7831     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_0_Tr */
   7832         soc_block_list[73],
   7833         soc_genreg,
   7834         1,
   7835         0,
   7836         0xb2,
   7837         0,
   7838         0,
   7839         2,
   7840         soc_KAPS_RESERVED_PCMI_0_Tr_fields,
   7841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7842         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   7843         -1,
   7844         -1,
   7845     },
   7846 #endif /* chips */
   7847 
   7848 #if defined(BCM_88470_B0)
   7849     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_0_T_BCM88470_B0r */
   7850         soc_block_list[73],
   7851         soc_genreg,
   7852         1,
   7853         0,
   7854         0xb2,
   7855         0,
   7856         0,
   7857         2,
   7858         soc_KAPS_RESERVED_PCMI_0_T_BCM88470_B0r_fields,
   7859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7860         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   7861         -1,
   7862         -1,
   7863     },
   7864 #endif /* chips */
   7865 
   7866 #if defined(BCM_88680_A0)
   7867     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_0_T_BCM88680_A0r */
   7868         soc_block_list[73],
   7869         soc_genreg,
   7870         1,
   7871         0,
   7872         0xb2,
   7873         0,
   7874         0,
   7875         2,
   7876         soc_KAPS_RESERVED_PCMI_0_T_BCM88680_A0r_fields,
   7877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7878         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   7879         -1,
   7880         -1,
   7881     },
   7882 #endif /* chips */
   7883 
   7884 #if defined(BCM_88470_B0)
   7885     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_1_BCM88470_B0r */
   7886         soc_block_list[73],
   7887         soc_genreg,
   7888         1,
   7889         0,
   7890         0xb3,
   7891         0,
   7892         0,
   7893         1,
   7894         soc_KAPS_RESERVED_PCMI_1_BCM88470_B0r_fields,
   7895         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7896         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7897         -1,
   7898         -1,
   7899     },
   7900 #endif /* chips */
   7901 
   7902 #if defined(BCM_88680_A0)
   7903     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_1_BCM88680_A0r */
   7904         soc_block_list[73],
   7905         soc_genreg,
   7906         1,
   7907         0,
   7908         0xb3,
   7909         0,
   7910         0,
   7911         1,
   7912         soc_KAPS_RESERVED_PCMI_1_BCM88680_A0r_fields,
   7913         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7915         -1,
   7916         -1,
   7917     },
   7918 #endif /* chips */
   7919 
   7920 #if defined(BCM_88470_A0)
   7921     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_1_Sr */
   7922         soc_block_list[73],
   7923         soc_genreg,
   7924         1,
   7925         0,
   7926         0xb4,
   7927         SOC_REG_FLAG_RO,
   7928         0,
   7929         3,
   7930         soc_KAPS_RESERVED_PCMI_1_Sr_fields,
   7931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7932         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7933         -1,
   7934         -1,
   7935     },
   7936 #endif /* chips */
   7937 
   7938 #if defined(BCM_88470_B0)
   7939     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_1_S_BCM88470_B0r */
   7940         soc_block_list[73],
   7941         soc_genreg,
   7942         1,
   7943         0,
   7944         0xb4,
   7945         SOC_REG_FLAG_RO,
   7946         0,
   7947         3,
   7948         soc_KAPS_RESERVED_PCMI_1_S_BCM88470_B0r_fields,
   7949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7950         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7951         -1,
   7952         -1,
   7953     },
   7954 #endif /* chips */
   7955 
   7956 #if defined(BCM_88680_A0)
   7957     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_1_S_BCM88680_A0r */
   7958         soc_block_list[73],
   7959         soc_genreg,
   7960         1,
   7961         0,
   7962         0xb4,
   7963         SOC_REG_FLAG_RO,
   7964         0,
   7965         3,
   7966         soc_KAPS_RESERVED_PCMI_1_S_BCM88680_A0r_fields,
   7967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7968         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7969         -1,
   7970         -1,
   7971     },
   7972 #endif /* chips */
   7973 
   7974 #if defined(BCM_88470_A0)
   7975     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_1_Tr */
   7976         soc_block_list[73],
   7977         soc_genreg,
   7978         1,
   7979         0,
   7980         0xb5,
   7981         0,
   7982         0,
   7983         2,
   7984         soc_KAPS_RESERVED_PCMI_1_Tr_fields,
   7985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7986         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   7987         -1,
   7988         -1,
   7989     },
   7990 #endif /* chips */
   7991 
   7992 #if defined(BCM_88470_B0)
   7993     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_1_T_BCM88470_B0r */
   7994         soc_block_list[73],
   7995         soc_genreg,
   7996         1,
   7997         0,
   7998         0xb5,
   7999         0,
   8000         0,
   8001         2,
   8002         soc_KAPS_RESERVED_PCMI_1_T_BCM88470_B0r_fields,
   8003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8004         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8005         -1,
   8006         -1,
   8007     },
   8008 #endif /* chips */
   8009 
   8010 #if defined(BCM_88680_A0)
   8011     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_1_T_BCM88680_A0r */
   8012         soc_block_list[73],
   8013         soc_genreg,
   8014         1,
   8015         0,
   8016         0xb5,
   8017         0,
   8018         0,
   8019         2,
   8020         soc_KAPS_RESERVED_PCMI_1_T_BCM88680_A0r_fields,
   8021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8022         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8023         -1,
   8024         -1,
   8025     },
   8026 #endif /* chips */
   8027 
   8028 #if defined(BCM_88470_B0)
   8029     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_2_BCM88470_B0r */
   8030         soc_block_list[73],
   8031         soc_genreg,
   8032         1,
   8033         0,
   8034         0xb6,
   8035         0,
   8036         0,
   8037         1,
   8038         soc_KAPS_RESERVED_PCMI_2_BCM88470_B0r_fields,
   8039         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   8040         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8041         -1,
   8042         -1,
   8043     },
   8044 #endif /* chips */
   8045 
   8046 #if defined(BCM_88680_A0)
   8047     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_2_BCM88680_A0r */
   8048         soc_block_list[73],
   8049         soc_genreg,
   8050         1,
   8051         0,
   8052         0xb6,
   8053         0,
   8054         0,
   8055         1,
   8056         soc_KAPS_RESERVED_PCMI_2_BCM88680_A0r_fields,
   8057         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   8058         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8059         -1,
   8060         -1,
   8061     },
   8062 #endif /* chips */
   8063 
   8064 #if defined(BCM_88470_A0)
   8065     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_2_Sr */
   8066         soc_block_list[73],
   8067         soc_genreg,
   8068         1,
   8069         0,
   8070         0xb7,
   8071         SOC_REG_FLAG_RO,
   8072         0,
   8073         3,
   8074         soc_KAPS_RESERVED_PCMI_2_Sr_fields,
   8075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8076         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8077         -1,
   8078         -1,
   8079     },
   8080 #endif /* chips */
   8081 
   8082 #if defined(BCM_88470_B0)
   8083     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_2_S_BCM88470_B0r */
   8084         soc_block_list[73],
   8085         soc_genreg,
   8086         1,
   8087         0,
   8088         0xb7,
   8089         SOC_REG_FLAG_RO,
   8090         0,
   8091         3,
   8092         soc_KAPS_RESERVED_PCMI_2_S_BCM88470_B0r_fields,
   8093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8094         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8095         -1,
   8096         -1,
   8097     },
   8098 #endif /* chips */
   8099 
   8100 #if defined(BCM_88680_A0)
   8101     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_2_S_BCM88680_A0r */
   8102         soc_block_list[73],
   8103         soc_genreg,
   8104         1,
   8105         0,
   8106         0xb7,
   8107         SOC_REG_FLAG_RO,
   8108         0,
   8109         3,
   8110         soc_KAPS_RESERVED_PCMI_2_S_BCM88680_A0r_fields,
   8111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8112         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8113         -1,
   8114         -1,
   8115     },
   8116 #endif /* chips */
   8117 
   8118 #if defined(BCM_88470_A0)
   8119     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_2_Tr */
   8120         soc_block_list[73],
   8121         soc_genreg,
   8122         1,
   8123         0,
   8124         0xb8,
   8125         0,
   8126         0,
   8127         2,
   8128         soc_KAPS_RESERVED_PCMI_2_Tr_fields,
   8129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8130         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8131         -1,
   8132         -1,
   8133     },
   8134 #endif /* chips */
   8135 
   8136 #if defined(BCM_88470_B0)
   8137     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_2_T_BCM88470_B0r */
   8138         soc_block_list[73],
   8139         soc_genreg,
   8140         1,
   8141         0,
   8142         0xb8,
   8143         0,
   8144         0,
   8145         2,
   8146         soc_KAPS_RESERVED_PCMI_2_T_BCM88470_B0r_fields,
   8147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8148         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8149         -1,
   8150         -1,
   8151     },
   8152 #endif /* chips */
   8153 
   8154 #if defined(BCM_88680_A0)
   8155     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_2_T_BCM88680_A0r */
   8156         soc_block_list[73],
   8157         soc_genreg,
   8158         1,
   8159         0,
   8160         0xb8,
   8161         0,
   8162         0,
   8163         2,
   8164         soc_KAPS_RESERVED_PCMI_2_T_BCM88680_A0r_fields,
   8165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8166         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8167         -1,
   8168         -1,
   8169     },
   8170 #endif /* chips */
   8171 
   8172 #if defined(BCM_88470_B0)
   8173     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_3_BCM88470_B0r */
   8174         soc_block_list[73],
   8175         soc_genreg,
   8176         1,
   8177         0,
   8178         0xb9,
   8179         0,
   8180         0,
   8181         1,
   8182         soc_KAPS_RESERVED_PCMI_3_BCM88470_B0r_fields,
   8183         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   8184         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8185         -1,
   8186         -1,
   8187     },
   8188 #endif /* chips */
   8189 
   8190 #if defined(BCM_88680_A0)
   8191     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_3_BCM88680_A0r */
   8192         soc_block_list[73],
   8193         soc_genreg,
   8194         1,
   8195         0,
   8196         0xb9,
   8197         0,
   8198         0,
   8199         1,
   8200         soc_KAPS_RESERVED_PCMI_3_BCM88680_A0r_fields,
   8201         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   8202         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8203         -1,
   8204         -1,
   8205     },
   8206 #endif /* chips */
   8207 
   8208 #if defined(BCM_88470_A0)
   8209     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_3_Sr */
   8210         soc_block_list[73],
   8211         soc_genreg,
   8212         1,
   8213         0,
   8214         0xba,
   8215         SOC_REG_FLAG_RO,
   8216         0,
   8217         3,
   8218         soc_KAPS_RESERVED_PCMI_3_Sr_fields,
   8219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8220         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8221         -1,
   8222         -1,
   8223     },
   8224 #endif /* chips */
   8225 
   8226 #if defined(BCM_88470_B0)
   8227     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_3_S_BCM88470_B0r */
   8228         soc_block_list[73],
   8229         soc_genreg,
   8230         1,
   8231         0,
   8232         0xba,
   8233         SOC_REG_FLAG_RO,
   8234         0,
   8235         3,
   8236         soc_KAPS_RESERVED_PCMI_3_S_BCM88470_B0r_fields,
   8237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8238         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8239         -1,
   8240         -1,
   8241     },
   8242 #endif /* chips */
   8243 
   8244 #if defined(BCM_88680_A0)
   8245     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_3_S_BCM88680_A0r */
   8246         soc_block_list[73],
   8247         soc_genreg,
   8248         1,
   8249         0,
   8250         0xba,
   8251         SOC_REG_FLAG_RO,
   8252         0,
   8253         3,
   8254         soc_KAPS_RESERVED_PCMI_3_S_BCM88680_A0r_fields,
   8255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8256         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8257         -1,
   8258         -1,
   8259     },
   8260 #endif /* chips */
   8261 
   8262 #if defined(BCM_88470_A0)
   8263     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_3_Tr */
   8264         soc_block_list[73],
   8265         soc_genreg,
   8266         1,
   8267         0,
   8268         0xbb,
   8269         0,
   8270         0,
   8271         2,
   8272         soc_KAPS_RESERVED_PCMI_3_Tr_fields,
   8273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8274         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8275         -1,
   8276         -1,
   8277     },
   8278 #endif /* chips */
   8279 
   8280 #if defined(BCM_88470_B0)
   8281     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_3_T_BCM88470_B0r */
   8282         soc_block_list[73],
   8283         soc_genreg,
   8284         1,
   8285         0,
   8286         0xbb,
   8287         0,
   8288         0,
   8289         2,
   8290         soc_KAPS_RESERVED_PCMI_3_T_BCM88470_B0r_fields,
   8291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8292         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8293         -1,
   8294         -1,
   8295     },
   8296 #endif /* chips */
   8297 
   8298 #if defined(BCM_88680_A0)
   8299     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_3_T_BCM88680_A0r */
   8300         soc_block_list[73],
   8301         soc_genreg,
   8302         1,
   8303         0,
   8304         0xbb,
   8305         0,
   8306         0,
   8307         2,
   8308         soc_KAPS_RESERVED_PCMI_3_T_BCM88680_A0r_fields,
   8309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8310         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8311         -1,
   8312         -1,
   8313     },
   8314 #endif /* chips */
   8315 
   8316 #if defined(BCM_88470_B0)
   8317     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_4_BCM88470_B0r */
   8318         soc_block_list[73],
   8319         soc_genreg,
   8320         1,
   8321         0,
   8322         0xbc,
   8323         0,
   8324         0,
   8325         1,
   8326         soc_KAPS_RESERVED_PCMI_4_BCM88470_B0r_fields,
   8327         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   8328         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8329         -1,
   8330         -1,
   8331     },
   8332 #endif /* chips */
   8333 
   8334 #if defined(BCM_88680_A0)
   8335     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_4_BCM88680_A0r */
   8336         soc_block_list[73],
   8337         soc_genreg,
   8338         1,
   8339         0,
   8340         0xbc,
   8341         0,
   8342         0,
   8343         1,
   8344         soc_KAPS_RESERVED_PCMI_4_BCM88680_A0r_fields,
   8345         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   8346         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8347         -1,
   8348         -1,
   8349     },
   8350 #endif /* chips */
   8351 
   8352 #if defined(BCM_88470_A0)
   8353     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_4_Sr */
   8354         soc_block_list[73],
   8355         soc_genreg,
   8356         1,
   8357         0,
   8358         0xbd,
   8359         SOC_REG_FLAG_RO,
   8360         0,
   8361         3,
   8362         soc_KAPS_RESERVED_PCMI_4_Sr_fields,
   8363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8364         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8365         -1,
   8366         -1,
   8367     },
   8368 #endif /* chips */
   8369 
   8370 #if defined(BCM_88470_B0)
   8371     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_4_S_BCM88470_B0r */
   8372         soc_block_list[73],
   8373         soc_genreg,
   8374         1,
   8375         0,
   8376         0xbd,
   8377         SOC_REG_FLAG_RO,
   8378         0,
   8379         3,
   8380         soc_KAPS_RESERVED_PCMI_4_S_BCM88470_B0r_fields,
   8381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8383         -1,
   8384         -1,
   8385     },
   8386 #endif /* chips */
   8387 
   8388 #if defined(BCM_88680_A0)
   8389     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_4_S_BCM88680_A0r */
   8390         soc_block_list[73],
   8391         soc_genreg,
   8392         1,
   8393         0,
   8394         0xbd,
   8395         SOC_REG_FLAG_RO,
   8396         0,
   8397         3,
   8398         soc_KAPS_RESERVED_PCMI_4_S_BCM88680_A0r_fields,
   8399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8400         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8401         -1,
   8402         -1,
   8403     },
   8404 #endif /* chips */
   8405 
   8406 #if defined(BCM_88470_A0)
   8407     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_4_Tr */
   8408         soc_block_list[73],
   8409         soc_genreg,
   8410         1,
   8411         0,
   8412         0xbe,
   8413         0,
   8414         0,
   8415         2,
   8416         soc_KAPS_RESERVED_PCMI_4_Tr_fields,
   8417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8418         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8419         -1,
   8420         -1,
   8421     },
   8422 #endif /* chips */
   8423 
   8424 #if defined(BCM_88470_B0)
   8425     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_4_T_BCM88470_B0r */
   8426         soc_block_list[73],
   8427         soc_genreg,
   8428         1,
   8429         0,
   8430         0xbe,
   8431         0,
   8432         0,
   8433         2,
   8434         soc_KAPS_RESERVED_PCMI_4_T_BCM88470_B0r_fields,
   8435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8436         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8437         -1,
   8438         -1,
   8439     },
   8440 #endif /* chips */
   8441 
   8442 #if defined(BCM_88680_A0)
   8443     { /* SOC_REG_INT_KAPS_RESERVED_PCMI_4_T_BCM88680_A0r */
   8444         soc_block_list[73],
   8445         soc_genreg,
   8446         1,
   8447         0,
   8448         0xbe,
   8449         0,
   8450         0,
   8451         2,
   8452         soc_KAPS_RESERVED_PCMI_4_T_BCM88680_A0r_fields,
   8453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8454         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   8455         -1,
   8456         -1,
   8457     },
   8458 #endif /* chips */
   8459 
   8460 #if defined(BCM_88470_A0)
   8461     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_0r */
   8462         soc_block_list[73],
   8463         soc_genreg,
   8464         1,
   8465         0,
   8466         0x90,
   8467         0,
   8468         0,
   8469         1,
   8470         soc_KAPS_RESERVED_SPARE_0r_fields,
   8471         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8472         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8473         -1,
   8474         -1,
   8475     },
   8476 #endif /* chips */
   8477 
   8478 #if defined(BCM_88470_A0)
   8479     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_1r */
   8480         soc_block_list[73],
   8481         soc_genreg,
   8482         1,
   8483         0,
   8484         0x91,
   8485         0,
   8486         0,
   8487         1,
   8488         soc_KAPS_RESERVED_SPARE_1r_fields,
   8489         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8490         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8491         -1,
   8492         -1,
   8493     },
   8494 #endif /* chips */
   8495 
   8496 #if defined(BCM_88470_A0)
   8497     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_2r */
   8498         soc_block_list[73],
   8499         soc_genreg,
   8500         1,
   8501         0,
   8502         0x92,
   8503         0,
   8504         0,
   8505         1,
   8506         soc_KAPS_RESERVED_SPARE_2r_fields,
   8507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8508         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8509         -1,
   8510         -1,
   8511     },
   8512 #endif /* chips */
   8513 
   8514 #if defined(BCM_88470_A0)
   8515     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_3r */
   8516         soc_block_list[73],
   8517         soc_genreg,
   8518         1,
   8519         0,
   8520         0x93,
   8521         0,
   8522         0,
   8523         1,
   8524         soc_KAPS_RESERVED_SPARE_3r_fields,
   8525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8526         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8527         -1,
   8528         -1,
   8529     },
   8530 #endif /* chips */
   8531 
   8532 #if defined(BCM_88270_A0)
   8533     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_0_BCM88270_A0r */
   8534         soc_block_list[73],
   8535         soc_genreg,
   8536         1,
   8537         0,
   8538         0x90,
   8539         0,
   8540         0,
   8541         1,
   8542         soc_KAPS_RESERVED_SPARE_0_BCM88270_A0r_fields,
   8543         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8544         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8545         -1,
   8546         -1,
   8547     },
   8548 #endif /* chips */
   8549 
   8550 #if defined(BCM_88470_B0)
   8551     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_0_BCM88470_B0r */
   8552         soc_block_list[73],
   8553         soc_genreg,
   8554         1,
   8555         0,
   8556         0x90,
   8557         0,
   8558         0,
   8559         1,
   8560         soc_KAPS_RESERVED_SPARE_0_BCM88470_B0r_fields,
   8561         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8562         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8563         -1,
   8564         -1,
   8565     },
   8566 #endif /* chips */
   8567 
   8568 #if defined(BCM_88680_A0)
   8569     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_0_BCM88680_A0r */
   8570         soc_block_list[73],
   8571         soc_genreg,
   8572         1,
   8573         0,
   8574         0x90,
   8575         0,
   8576         0,
   8577         1,
   8578         soc_KAPS_RESERVED_SPARE_0_BCM88680_A0r_fields,
   8579         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8580         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8581         -1,
   8582         -1,
   8583     },
   8584 #endif /* chips */
   8585 
   8586 #if defined(BCM_88690_A0)
   8587     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_0_BCM88690_A0r */
   8588         soc_block_list[73],
   8589         soc_genreg,
   8590         1,
   8591         0,
   8592         0x90,
   8593         0,
   8594         0,
   8595         1,
   8596         soc_KAPS_RESERVED_SPARE_0_BCM88690_A0r_fields,
   8597         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8598         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8599         -1,
   8600         -1,
   8601     },
   8602 #endif /* chips */
   8603 
   8604 #if defined(BCM_88690_B0)
   8605     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_0_BCM88690_B0r */
   8606         soc_block_list[73],
   8607         soc_genreg,
   8608         1,
   8609         0,
   8610         0x90,
   8611         0,
   8612         0,
   8613         1,
   8614         soc_KAPS_RESERVED_SPARE_0_BCM88690_B0r_fields,
   8615         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8616         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8617         -1,
   8618         -1,
   8619     },
   8620 #endif /* chips */
   8621 
   8622 #if defined(BCM_88270_A0)
   8623     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_1_BCM88270_A0r */
   8624         soc_block_list[73],
   8625         soc_genreg,
   8626         1,
   8627         0,
   8628         0x91,
   8629         0,
   8630         0,
   8631         1,
   8632         soc_KAPS_RESERVED_SPARE_1_BCM88270_A0r_fields,
   8633         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8634         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8635         -1,
   8636         -1,
   8637     },
   8638 #endif /* chips */
   8639 
   8640 #if defined(BCM_88470_B0)
   8641     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_1_BCM88470_B0r */
   8642         soc_block_list[73],
   8643         soc_genreg,
   8644         1,
   8645         0,
   8646         0x91,
   8647         0,
   8648         0,
   8649         1,
   8650         soc_KAPS_RESERVED_SPARE_1_BCM88470_B0r_fields,
   8651         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8652         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8653         -1,
   8654         -1,
   8655     },
   8656 #endif /* chips */
   8657 
   8658 #if defined(BCM_88680_A0)
   8659     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_1_BCM88680_A0r */
   8660         soc_block_list[73],
   8661         soc_genreg,
   8662         1,
   8663         0,
   8664         0x91,
   8665         0,
   8666         0,
   8667         1,
   8668         soc_KAPS_RESERVED_SPARE_1_BCM88680_A0r_fields,
   8669         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8670         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8671         -1,
   8672         -1,
   8673     },
   8674 #endif /* chips */
   8675 
   8676 #if defined(BCM_88690_A0)
   8677     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_1_BCM88690_A0r */
   8678         soc_block_list[73],
   8679         soc_genreg,
   8680         1,
   8681         0,
   8682         0x91,
   8683         0,
   8684         0,
   8685         1,
   8686         soc_KAPS_RESERVED_SPARE_1_BCM88690_A0r_fields,
   8687         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8689         -1,
   8690         -1,
   8691     },
   8692 #endif /* chips */
   8693 
   8694 #if defined(BCM_88690_B0)
   8695     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_1_BCM88690_B0r */
   8696         soc_block_list[73],
   8697         soc_genreg,
   8698         1,
   8699         0,
   8700         0x91,
   8701         0,
   8702         0,
   8703         1,
   8704         soc_KAPS_RESERVED_SPARE_1_BCM88690_B0r_fields,
   8705         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8707         -1,
   8708         -1,
   8709     },
   8710 #endif /* chips */
   8711 
   8712 #if defined(BCM_88270_A0)
   8713     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_2_BCM88270_A0r */
   8714         soc_block_list[73],
   8715         soc_genreg,
   8716         1,
   8717         0,
   8718         0x92,
   8719         0,
   8720         0,
   8721         1,
   8722         soc_KAPS_RESERVED_SPARE_2_BCM88270_A0r_fields,
   8723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8724         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8725         -1,
   8726         -1,
   8727     },
   8728 #endif /* chips */
   8729 
   8730 #if defined(BCM_88470_B0)
   8731     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_2_BCM88470_B0r */
   8732         soc_block_list[73],
   8733         soc_genreg,
   8734         1,
   8735         0,
   8736         0x92,
   8737         0,
   8738         0,
   8739         1,
   8740         soc_KAPS_RESERVED_SPARE_2_BCM88470_B0r_fields,
   8741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8743         -1,
   8744         -1,
   8745     },
   8746 #endif /* chips */
   8747 
   8748 #if defined(BCM_88680_A0)
   8749     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_2_BCM88680_A0r */
   8750         soc_block_list[73],
   8751         soc_genreg,
   8752         1,
   8753         0,
   8754         0x92,
   8755         0,
   8756         0,
   8757         1,
   8758         soc_KAPS_RESERVED_SPARE_2_BCM88680_A0r_fields,
   8759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8760         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8761         -1,
   8762         -1,
   8763     },
   8764 #endif /* chips */
   8765 
   8766 #if defined(BCM_88690_A0)
   8767     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_2_BCM88690_A0r */
   8768         soc_block_list[73],
   8769         soc_genreg,
   8770         1,
   8771         0,
   8772         0x92,
   8773         0,
   8774         0,
   8775         1,
   8776         soc_KAPS_RESERVED_SPARE_2_BCM88690_A0r_fields,
   8777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8778         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8779         -1,
   8780         -1,
   8781     },
   8782 #endif /* chips */
   8783 
   8784 #if defined(BCM_88690_B0)
   8785     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_2_BCM88690_B0r */
   8786         soc_block_list[73],
   8787         soc_genreg,
   8788         1,
   8789         0,
   8790         0x92,
   8791         0,
   8792         0,
   8793         1,
   8794         soc_KAPS_RESERVED_SPARE_2_BCM88690_B0r_fields,
   8795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8797         -1,
   8798         -1,
   8799     },
   8800 #endif /* chips */
   8801 
   8802 #if defined(BCM_88270_A0)
   8803     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_3_BCM88270_A0r */
   8804         soc_block_list[73],
   8805         soc_genreg,
   8806         1,
   8807         0,
   8808         0x93,
   8809         0,
   8810         0,
   8811         1,
   8812         soc_KAPS_RESERVED_SPARE_3_BCM88270_A0r_fields,
   8813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8814         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8815         -1,
   8816         -1,
   8817     },
   8818 #endif /* chips */
   8819 
   8820 #if defined(BCM_88470_B0)
   8821     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_3_BCM88470_B0r */
   8822         soc_block_list[73],
   8823         soc_genreg,
   8824         1,
   8825         0,
   8826         0x93,
   8827         0,
   8828         0,
   8829         1,
   8830         soc_KAPS_RESERVED_SPARE_3_BCM88470_B0r_fields,
   8831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8832         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8833         -1,
   8834         -1,
   8835     },
   8836 #endif /* chips */
   8837 
   8838 #if defined(BCM_88680_A0)
   8839     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_3_BCM88680_A0r */
   8840         soc_block_list[73],
   8841         soc_genreg,
   8842         1,
   8843         0,
   8844         0x93,
   8845         0,
   8846         0,
   8847         1,
   8848         soc_KAPS_RESERVED_SPARE_3_BCM88680_A0r_fields,
   8849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8851         -1,
   8852         -1,
   8853     },
   8854 #endif /* chips */
   8855 
   8856 #if defined(BCM_88690_A0)
   8857     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_3_BCM88690_A0r */
   8858         soc_block_list[73],
   8859         soc_genreg,
   8860         1,
   8861         0,
   8862         0x93,
   8863         0,
   8864         0,
   8865         1,
   8866         soc_KAPS_RESERVED_SPARE_3_BCM88690_A0r_fields,
   8867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8868         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8869         -1,
   8870         -1,
   8871     },
   8872 #endif /* chips */
   8873 
   8874 #if defined(BCM_88690_B0)
   8875     { /* SOC_REG_INT_KAPS_RESERVED_SPARE_3_BCM88690_B0r */
   8876         soc_block_list[73],
   8877         soc_genreg,
   8878         1,
   8879         0,
   8880         0x93,
   8881         0,
   8882         0,
   8883         1,
   8884         soc_KAPS_RESERVED_SPARE_3_BCM88690_B0r_fields,
   8885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8886         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8887         -1,
   8888         -1,
   8889     },
   8890 #endif /* chips */
   8891 
   8892 #if defined(BCM_88675_A0)
   8893     { /* SOC_REG_INT_KAPS_REVISIONr */
   8894         soc_block_list[73],
   8895         soc_genreg,
   8896         1,
   8897         0,
   8898         0,
   8899         SOC_REG_FLAG_RO,
   8900         0,
   8901         2,
   8902         soc_KAPS_REVISIONr_fields,
   8903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8904         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8905         -1,
   8906         -1,
   8907     },
   8908 #endif /* chips */
   8909 
   8910 #if defined(BCM_88375_A0)
   8911     { /* SOC_REG_INT_KAPS_REVISION_BCM88375_A0r */
   8912         soc_block_list[73],
   8913         soc_genreg,
   8914         1,
   8915         0,
   8916         0,
   8917         SOC_REG_FLAG_RO,
   8918         0,
   8919         2,
   8920         soc_KAPS_REVISION_BCM88375_A0r_fields,
   8921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8923         -1,
   8924         -1,
   8925     },
   8926 #endif /* chips */
   8927 
   8928 #if defined(BCM_88375_B0)
   8929     { /* SOC_REG_INT_KAPS_REVISION_BCM88375_B0r */
   8930         soc_block_list[73],
   8931         soc_genreg,
   8932         1,
   8933         0,
   8934         0,
   8935         SOC_REG_FLAG_RO,
   8936         0,
   8937         2,
   8938         soc_KAPS_REVISION_BCM88375_B0r_fields,
   8939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8941         -1,
   8942         -1,
   8943     },
   8944 #endif /* chips */
   8945 
   8946 #if defined(BCM_88675_B0)
   8947     { /* SOC_REG_INT_KAPS_REVISION_BCM88675_B0r */
   8948         soc_block_list[73],
   8949         soc_genreg,
   8950         1,
   8951         0,
   8952         0,
   8953         SOC_REG_FLAG_RO,
   8954         0,
   8955         2,
   8956         soc_KAPS_REVISION_BCM88675_B0r_fields,
   8957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8959         -1,
   8960         -1,
   8961     },
   8962 #endif /* chips */
   8963 
   8964 #if defined(BCM_88690_A0)
   8965     { /* SOC_REG_INT_KAPS_REVISION_BCM88690_A0r */
   8966         soc_block_list[73],
   8967         soc_genreg,
   8968         1,
   8969         0,
   8970         0x100,
   8971         SOC_REG_FLAG_RO,
   8972         0,
   8973         2,
   8974         soc_KAPS_REVISION_BCM88690_A0r_fields,
   8975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8976         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8977         -1,
   8978         -1,
   8979     },
   8980 #endif /* chips */
   8981 
   8982 #if defined(BCM_88690_B0)
   8983     { /* SOC_REG_INT_KAPS_REVISION_BCM88690_B0r */
   8984         soc_block_list[73],
   8985         soc_genreg,
   8986         1,
   8987         0,
   8988         0x100,
   8989         SOC_REG_FLAG_RO,
   8990         0,
   8991         2,
   8992         soc_KAPS_REVISION_BCM88690_B0r_fields,
   8993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8994         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8995         -1,
   8996         -1,
   8997     },
   8998 #endif /* chips */
   8999 
   9000 #if defined(BCM_88470_A0)
   9001     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_CONFIGr */
   9002         soc_block_list[73],
   9003         soc_genreg,
   9004         2,
   9005         0,
   9006         0x118,
   9007         SOC_REG_FLAG_ARRAY |
   9008                           SOC_REG_FLAG_REG_ARRAY,
   9009         0,
   9010         2,
   9011         soc_KAPS_RPB_CAM_BIST_CONFIGr_fields,
   9012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9013         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9014         -1,
   9015         -1,
   9016     },
   9017 #endif /* chips */
   9018 
   9019 #if defined(BCM_88270_A0)
   9020     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_CONFIG_BCM88270_A0r */
   9021         soc_block_list[73],
   9022         soc_genreg,
   9023         2,
   9024         0,
   9025         0x118,
   9026         SOC_REG_FLAG_ARRAY |
   9027                           SOC_REG_FLAG_REG_ARRAY,
   9028         0,
   9029         2,
   9030         soc_KAPS_RPB_CAM_BIST_CONFIG_BCM88270_A0r_fields,
   9031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9032         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9033         -1,
   9034         -1,
   9035     },
   9036 #endif /* chips */
   9037 
   9038 #if defined(BCM_88470_B0)
   9039     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_CONFIG_BCM88470_B0r */
   9040         soc_block_list[73],
   9041         soc_genreg,
   9042         2,
   9043         0,
   9044         0x118,
   9045         SOC_REG_FLAG_ARRAY |
   9046                           SOC_REG_FLAG_REG_ARRAY,
   9047         0,
   9048         2,
   9049         soc_KAPS_RPB_CAM_BIST_CONFIG_BCM88470_B0r_fields,
   9050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9051         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9052         -1,
   9053         -1,
   9054     },
   9055 #endif /* chips */
   9056 
   9057 #if defined(BCM_88680_A0)
   9058     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_CONFIG_BCM88680_A0r */
   9059         soc_block_list[73],
   9060         soc_genreg,
   9061         4,
   9062         0,
   9063         0x162,
   9064         SOC_REG_FLAG_ARRAY |
   9065                           SOC_REG_FLAG_REG_ARRAY,
   9066         0,
   9067         2,
   9068         soc_KAPS_RPB_CAM_BIST_CONFIG_BCM88680_A0r_fields,
   9069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9070         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9071         -1,
   9072         -1,
   9073     },
   9074 #endif /* chips */
   9075 
   9076 #if defined(BCM_88470_A0)
   9077     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_CONTROLr */
   9078         soc_block_list[73],
   9079         soc_genreg,
   9080         2,
   9081         0,
   9082         0x114,
   9083         SOC_REG_FLAG_ARRAY |
   9084                           SOC_REG_FLAG_REG_ARRAY,
   9085         0,
   9086         4,
   9087         soc_KAPS_RPB_CAM_BIST_CONTROLr_fields,
   9088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9089         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9090         -1,
   9091         -1,
   9092     },
   9093 #endif /* chips */
   9094 
   9095 #if defined(BCM_88270_A0)
   9096     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_CONTROL_BCM88270_A0r */
   9097         soc_block_list[73],
   9098         soc_genreg,
   9099         2,
   9100         0,
   9101         0x114,
   9102         SOC_REG_FLAG_ARRAY |
   9103                           SOC_REG_FLAG_REG_ARRAY,
   9104         0,
   9105         4,
   9106         soc_KAPS_RPB_CAM_BIST_CONTROL_BCM88270_A0r_fields,
   9107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9108         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9109         -1,
   9110         -1,
   9111     },
   9112 #endif /* chips */
   9113 
   9114 #if defined(BCM_88470_B0)
   9115     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_CONTROL_BCM88470_B0r */
   9116         soc_block_list[73],
   9117         soc_genreg,
   9118         2,
   9119         0,
   9120         0x114,
   9121         SOC_REG_FLAG_ARRAY |
   9122                           SOC_REG_FLAG_REG_ARRAY,
   9123         0,
   9124         4,
   9125         soc_KAPS_RPB_CAM_BIST_CONTROL_BCM88470_B0r_fields,
   9126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9127         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9128         -1,
   9129         -1,
   9130     },
   9131 #endif /* chips */
   9132 
   9133 #if defined(BCM_88680_A0)
   9134     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_CONTROL_BCM88680_A0r */
   9135         soc_block_list[73],
   9136         soc_genreg,
   9137         4,
   9138         0,
   9139         0x15a,
   9140         SOC_REG_FLAG_ARRAY |
   9141                           SOC_REG_FLAG_REG_ARRAY,
   9142         0,
   9143         4,
   9144         soc_KAPS_RPB_CAM_BIST_CONTROL_BCM88680_A0r_fields,
   9145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9146         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9147         -1,
   9148         -1,
   9149     },
   9150 #endif /* chips */
   9151 
   9152 #if defined(BCM_88470_A0)
   9153     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_DBG_DATAr */
   9154         soc_block_list[73],
   9155         soc_genreg,
   9156         2,
   9157         0,
   9158         0x11a,
   9159         SOC_REG_FLAG_ARRAY |
   9160                           SOC_REG_FLAG_REG_ARRAY,
   9161         0,
   9162         1,
   9163         soc_KAPS_RPB_CAM_BIST_DBG_DATAr_fields,
   9164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9165         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9166         -1,
   9167         -1,
   9168     },
   9169 #endif /* chips */
   9170 
   9171 #if defined(BCM_88270_A0)
   9172     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_DBG_DATA_BCM88270_A0r */
   9173         soc_block_list[73],
   9174         soc_genreg,
   9175         2,
   9176         0,
   9177         0x11a,
   9178         SOC_REG_FLAG_ARRAY |
   9179                           SOC_REG_FLAG_REG_ARRAY,
   9180         0,
   9181         1,
   9182         soc_KAPS_RPB_CAM_BIST_DBG_DATA_BCM88270_A0r_fields,
   9183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9184         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9185         -1,
   9186         -1,
   9187     },
   9188 #endif /* chips */
   9189 
   9190 #if defined(BCM_88470_B0)
   9191     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_DBG_DATA_BCM88470_B0r */
   9192         soc_block_list[73],
   9193         soc_genreg,
   9194         2,
   9195         0,
   9196         0x11a,
   9197         SOC_REG_FLAG_ARRAY |
   9198                           SOC_REG_FLAG_REG_ARRAY,
   9199         0,
   9200         1,
   9201         soc_KAPS_RPB_CAM_BIST_DBG_DATA_BCM88470_B0r_fields,
   9202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9204         -1,
   9205         -1,
   9206     },
   9207 #endif /* chips */
   9208 
   9209 #if defined(BCM_88680_A0)
   9210     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_DBG_DATA_BCM88680_A0r */
   9211         soc_block_list[73],
   9212         soc_genreg,
   9213         4,
   9214         0,
   9215         0x166,
   9216         SOC_REG_FLAG_ARRAY |
   9217                           SOC_REG_FLAG_REG_ARRAY,
   9218         0,
   9219         1,
   9220         soc_KAPS_RPB_CAM_BIST_DBG_DATA_BCM88680_A0r_fields,
   9221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9222         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9223         -1,
   9224         -1,
   9225     },
   9226 #endif /* chips */
   9227 
   9228 #if defined(BCM_88470_A0)
   9229     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_STATUSr */
   9230         soc_block_list[73],
   9231         soc_genreg,
   9232         2,
   9233         0,
   9234         0x116,
   9235         SOC_REG_FLAG_ARRAY |
   9236                           SOC_REG_FLAG_RO |
   9237                           SOC_REG_FLAG_REG_ARRAY,
   9238         0,
   9239         1,
   9240         soc_KAPS_RPB_CAM_BIST_STATUSr_fields,
   9241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9242         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9243         -1,
   9244         -1,
   9245     },
   9246 #endif /* chips */
   9247 
   9248 #if defined(BCM_88270_A0)
   9249     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_STATUS_BCM88270_A0r */
   9250         soc_block_list[73],
   9251         soc_genreg,
   9252         2,
   9253         0,
   9254         0x116,
   9255         SOC_REG_FLAG_ARRAY |
   9256                           SOC_REG_FLAG_RO |
   9257                           SOC_REG_FLAG_REG_ARRAY,
   9258         0,
   9259         1,
   9260         soc_KAPS_RPB_CAM_BIST_STATUS_BCM88270_A0r_fields,
   9261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9262         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9263         -1,
   9264         -1,
   9265     },
   9266 #endif /* chips */
   9267 
   9268 #if defined(BCM_88470_B0)
   9269     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_STATUS_BCM88470_B0r */
   9270         soc_block_list[73],
   9271         soc_genreg,
   9272         2,
   9273         0,
   9274         0x116,
   9275         SOC_REG_FLAG_ARRAY |
   9276                           SOC_REG_FLAG_RO |
   9277                           SOC_REG_FLAG_REG_ARRAY,
   9278         0,
   9279         1,
   9280         soc_KAPS_RPB_CAM_BIST_STATUS_BCM88470_B0r_fields,
   9281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9282         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9283         -1,
   9284         -1,
   9285     },
   9286 #endif /* chips */
   9287 
   9288 #if defined(BCM_88680_A0)
   9289     { /* SOC_REG_INT_KAPS_RPB_CAM_BIST_STATUS_BCM88680_A0r */
   9290         soc_block_list[73],
   9291         soc_genreg,
   9292         4,
   9293         0,
   9294         0x15e,
   9295         SOC_REG_FLAG_ARRAY |
   9296                           SOC_REG_FLAG_RO |
   9297                           SOC_REG_FLAG_REG_ARRAY,
   9298         0,
   9299         1,
   9300         soc_KAPS_RPB_CAM_BIST_STATUS_BCM88680_A0r_fields,
   9301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9302         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9303         -1,
   9304         -1,
   9305     },
   9306 #endif /* chips */
   9307 
   9308 #if defined(BCM_88470_A0)
   9309     { /* SOC_REG_INT_KAPS_RPB_DEBUGr */
   9310         soc_block_list[73],
   9311         soc_genreg,
   9312         2,
   9313         0,
   9314         0x11c,
   9315         SOC_REG_FLAG_ABOVE_64_BITS |
   9316                           SOC_REG_FLAG_ARRAY |
   9317                           SOC_REG_FLAG_RO |
   9318                           SOC_REG_FLAG_REG_ARRAY,
   9319         0,
   9320         3,
   9321         soc_KAPS_RPB_DEBUGr_fields,
   9322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9323         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9324         -1,
   9325         -1,
   9326     },
   9327 #endif /* chips */
   9328 
   9329 #if defined(BCM_88270_A0)
   9330     { /* SOC_REG_INT_KAPS_RPB_DEBUG_BCM88270_A0r */
   9331         soc_block_list[73],
   9332         soc_genreg,
   9333         2,
   9334         0,
   9335         0x11c,
   9336         SOC_REG_FLAG_ABOVE_64_BITS |
   9337                           SOC_REG_FLAG_ARRAY |
   9338                           SOC_REG_FLAG_RO |
   9339                           SOC_REG_FLAG_REG_ARRAY,
   9340         0,
   9341         3,
   9342         soc_KAPS_RPB_DEBUG_BCM88270_A0r_fields,
   9343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9345         -1,
   9346         -1,
   9347     },
   9348 #endif /* chips */
   9349 
   9350 #if defined(BCM_88470_B0)
   9351     { /* SOC_REG_INT_KAPS_RPB_DEBUG_BCM88470_B0r */
   9352         soc_block_list[73],
   9353         soc_genreg,
   9354         2,
   9355         0,
   9356         0x11c,
   9357         SOC_REG_FLAG_ABOVE_64_BITS |
   9358                           SOC_REG_FLAG_ARRAY |
   9359                           SOC_REG_FLAG_RO |
   9360                           SOC_REG_FLAG_REG_ARRAY,
   9361         0,
   9362         3,
   9363         soc_KAPS_RPB_DEBUG_BCM88470_B0r_fields,
   9364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9365         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9366         -1,
   9367         -1,
   9368     },
   9369 #endif /* chips */
   9370 
   9371 #if defined(BCM_88680_A0)
   9372     { /* SOC_REG_INT_KAPS_RPB_DEBUG_BCM88680_A0r */
   9373         soc_block_list[73],
   9374         soc_genreg,
   9375         4,
   9376         0,
   9377         0x16a,
   9378         SOC_REG_FLAG_ABOVE_64_BITS |
   9379                           SOC_REG_FLAG_ARRAY |
   9380                           SOC_REG_FLAG_RO |
   9381                           SOC_REG_FLAG_REG_ARRAY,
   9382         0,
   9383         3,
   9384         soc_KAPS_RPB_DEBUG_BCM88680_A0r_fields,
   9385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9386         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9387         -1,
   9388         -1,
   9389     },
   9390 #endif /* chips */
   9391 
   9392 #if defined(BCM_88690_A0)
   9393     { /* SOC_REG_INT_KAPS_RPB_DEBUG_BCM88690_A0r */
   9394         soc_block_list[73],
   9395         soc_genreg,
   9396         2,
   9397         0,
   9398         0x111,
   9399         SOC_REG_FLAG_ABOVE_64_BITS |
   9400                           SOC_REG_FLAG_ARRAY |
   9401                           SOC_REG_FLAG_RO |
   9402                           SOC_REG_FLAG_REG_ARRAY,
   9403         0,
   9404         6,
   9405         soc_KAPS_RPB_DEBUG_BCM88690_A0r_fields,
   9406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9408         -1,
   9409         -1,
   9410     },
   9411 #endif /* chips */
   9412 
   9413 #if defined(BCM_88690_B0)
   9414     { /* SOC_REG_INT_KAPS_RPB_DEBUG_BCM88690_B0r */
   9415         soc_block_list[73],
   9416         soc_genreg,
   9417         2,
   9418         0,
   9419         0x111,
   9420         SOC_REG_FLAG_ABOVE_64_BITS |
   9421                           SOC_REG_FLAG_ARRAY |
   9422                           SOC_REG_FLAG_RO |
   9423                           SOC_REG_FLAG_REG_ARRAY,
   9424         0,
   9425         6,
   9426         soc_KAPS_RPB_DEBUG_BCM88690_B0r_fields,
   9427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9429         -1,
   9430         -1,
   9431     },
   9432 #endif /* chips */
   9433 
   9434 #if defined(BCM_88470_A0)
   9435     { /* SOC_REG_INT_KAPS_RPB_GLOBAL_CONFIGr */
   9436         soc_block_list[73],
   9437         soc_genreg,
   9438         2,
   9439         0,
   9440         0x104,
   9441         SOC_REG_FLAG_ARRAY |
   9442                           SOC_REG_FLAG_REG_ARRAY,
   9443         0,
   9444         1,
   9445         soc_KAPS_RPB_GLOBAL_CONFIGr_fields,
   9446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9447         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9448         -1,
   9449         -1,
   9450     },
   9451 #endif /* chips */
   9452 
   9453 #if defined(BCM_88270_A0)
   9454     { /* SOC_REG_INT_KAPS_RPB_GLOBAL_CONFIG_BCM88270_A0r */
   9455         soc_block_list[73],
   9456         soc_genreg,
   9457         2,
   9458         0,
   9459         0x104,
   9460         SOC_REG_FLAG_ARRAY |
   9461                           SOC_REG_FLAG_REG_ARRAY,
   9462         0,
   9463         1,
   9464         soc_KAPS_RPB_GLOBAL_CONFIG_BCM88270_A0r_fields,
   9465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9466         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9467         -1,
   9468         -1,
   9469     },
   9470 #endif /* chips */
   9471 
   9472 #if defined(BCM_88470_B0)
   9473     { /* SOC_REG_INT_KAPS_RPB_GLOBAL_CONFIG_BCM88470_B0r */
   9474         soc_block_list[73],
   9475         soc_genreg,
   9476         2,
   9477         0,
   9478         0x104,
   9479         SOC_REG_FLAG_ARRAY |
   9480                           SOC_REG_FLAG_REG_ARRAY,
   9481         0,
   9482         1,
   9483         soc_KAPS_RPB_GLOBAL_CONFIG_BCM88470_B0r_fields,
   9484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9485         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9486         -1,
   9487         -1,
   9488     },
   9489 #endif /* chips */
   9490 
   9491 #if defined(BCM_88680_A0)
   9492     { /* SOC_REG_INT_KAPS_RPB_GLOBAL_CONFIG_BCM88680_A0r */
   9493         soc_block_list[73],
   9494         soc_genreg,
   9495         4,
   9496         0,
   9497         0x13a,
   9498         SOC_REG_FLAG_ARRAY |
   9499                           SOC_REG_FLAG_REG_ARRAY,
   9500         0,
   9501         1,
   9502         soc_KAPS_RPB_GLOBAL_CONFIG_BCM88680_A0r_fields,
   9503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9504         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9505         -1,
   9506         -1,
   9507     },
   9508 #endif /* chips */
   9509 
   9510 #if defined(BCM_88690_A0)
   9511     { /* SOC_REG_INT_KAPS_RPB_GLOBAL_CONFIG_BCM88690_A0r */
   9512         soc_block_list[73],
   9513         soc_genreg,
   9514         2,
   9515         0,
   9516         0x101,
   9517         SOC_REG_FLAG_ARRAY |
   9518                           SOC_REG_FLAG_REG_ARRAY,
   9519         0,
   9520         4,
   9521         soc_KAPS_RPB_GLOBAL_CONFIG_BCM88690_A0r_fields,
   9522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9523         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   9524         -1,
   9525         -1,
   9526     },
   9527 #endif /* chips */
   9528 
   9529 #if defined(BCM_88690_B0)
   9530     { /* SOC_REG_INT_KAPS_RPB_GLOBAL_CONFIG_BCM88690_B0r */
   9531         soc_block_list[73],
   9532         soc_genreg,
   9533         2,
   9534         0,
   9535         0x101,
   9536         SOC_REG_FLAG_ARRAY |
   9537                           SOC_REG_FLAG_REG_ARRAY,
   9538         0,
   9539         4,
   9540         soc_KAPS_RPB_GLOBAL_CONFIG_BCM88690_B0r_fields,
   9541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9542         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   9543         -1,
   9544         -1,
   9545     },
   9546 #endif /* chips */
   9547 
   9548 #if defined(BCM_88470_A0)
   9549     { /* SOC_REG_INT_KAPS_RPB_MEM_CONFIGr */
   9550         soc_block_list[73],
   9551         soc_genreg,
   9552         2,
   9553         0,
   9554         0x106,
   9555         SOC_REG_FLAG_ARRAY |
   9556                           SOC_REG_FLAG_REG_ARRAY,
   9557         0,
   9558         1,
   9559         soc_KAPS_RPB_MEM_CONFIGr_fields,
   9560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9561         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   9562         -1,
   9563         -1,
   9564     },
   9565 #endif /* chips */
   9566 
   9567 #if defined(BCM_88270_A0)
   9568     { /* SOC_REG_INT_KAPS_RPB_MEM_CONFIG_BCM88270_A0r */
   9569         soc_block_list[73],
   9570         soc_genreg,
   9571         2,
   9572         0,
   9573         0x106,
   9574         SOC_REG_FLAG_ARRAY |
   9575                           SOC_REG_FLAG_REG_ARRAY,
   9576         0,
   9577         1,
   9578         soc_KAPS_RPB_MEM_CONFIG_BCM88270_A0r_fields,
   9579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9580         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   9581         -1,
   9582         -1,
   9583     },
   9584 #endif /* chips */
   9585 
   9586 #if defined(BCM_88470_B0)
   9587     { /* SOC_REG_INT_KAPS_RPB_MEM_CONFIG_BCM88470_B0r */
   9588         soc_block_list[73],
   9589         soc_genreg,
   9590         2,
   9591         0,
   9592         0x106,
   9593         SOC_REG_FLAG_ARRAY |
   9594                           SOC_REG_FLAG_REG_ARRAY,
   9595         0,
   9596         1,
   9597         soc_KAPS_RPB_MEM_CONFIG_BCM88470_B0r_fields,
   9598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9599         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   9600         -1,
   9601         -1,
   9602     },
   9603 #endif /* chips */
   9604 
   9605 #if defined(BCM_88680_A0)
   9606     { /* SOC_REG_INT_KAPS_RPB_MEM_CONFIG_BCM88680_A0r */
   9607         soc_block_list[73],
   9608         soc_genreg,
   9609         4,
   9610         0,
   9611         0x13e,
   9612         SOC_REG_FLAG_ARRAY |
   9613                           SOC_REG_FLAG_REG_ARRAY,
   9614         0,
   9615         1,
   9616         soc_KAPS_RPB_MEM_CONFIG_BCM88680_A0r_fields,
   9617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9618         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   9619         -1,
   9620         -1,
   9621     },
   9622 #endif /* chips */
   9623 
   9624 #if defined(BCM_88690_A0)
   9625     { /* SOC_REG_INT_KAPS_RPB_MEM_CONFIG_BCM88690_A0r */
   9626         soc_block_list[73],
   9627         soc_genreg,
   9628         2,
   9629         0,
   9630         0x103,
   9631         SOC_REG_FLAG_ARRAY |
   9632                           SOC_REG_FLAG_REG_ARRAY,
   9633         0,
   9634         1,
   9635         soc_KAPS_RPB_MEM_CONFIG_BCM88690_A0r_fields,
   9636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9637         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   9638         -1,
   9639         -1,
   9640     },
   9641 #endif /* chips */
   9642 
   9643 #if defined(BCM_88690_B0)
   9644     { /* SOC_REG_INT_KAPS_RPB_MEM_CONFIG_BCM88690_B0r */
   9645         soc_block_list[73],
   9646         soc_genreg,
   9647         2,
   9648         0,
   9649         0x103,
   9650         SOC_REG_FLAG_ARRAY |
   9651                           SOC_REG_FLAG_REG_ARRAY,
   9652         0,
   9653         1,
   9654         soc_KAPS_RPB_MEM_CONFIG_BCM88690_B0r_fields,
   9655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9656         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   9657         -1,
   9658         -1,
   9659     },
   9660 #endif /* chips */
   9661 
   9662 #if defined(BCM_88690_A0)
   9663     { /* SOC_REG_INT_KAPS_RPB_TCAM_A_SCAN_PAUSEr */
   9664         soc_block_list[73],
   9665         soc_genreg,
   9666         2,
   9667         0,
   9668         0x10b,
   9669         SOC_REG_FLAG_ARRAY |
   9670                           SOC_REG_FLAG_RO |
   9671                           SOC_REG_FLAG_REG_ARRAY,
   9672         SOC_REG_FLAG_INIT_ON_READ,
   9673         1,
   9674         soc_KAPS_RPB_TCAM_A_SCAN_PAUSEr_fields,
   9675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9676         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9677         -1,
   9678         -1,
   9679     },
   9680 #endif /* chips */
   9681 
   9682 #if defined(BCM_88690_B0)
   9683     { /* SOC_REG_INT_KAPS_RPB_TCAM_A_SCAN_PAUSE_BCM88690_B0r */
   9684         soc_block_list[73],
   9685         soc_genreg,
   9686         2,
   9687         0,
   9688         0x10b,
   9689         SOC_REG_FLAG_ARRAY |
   9690                           SOC_REG_FLAG_RO |
   9691                           SOC_REG_FLAG_REG_ARRAY,
   9692         SOC_REG_FLAG_INIT_ON_READ,
   9693         1,
   9694         soc_KAPS_RPB_TCAM_A_SCAN_PAUSE_BCM88690_B0r_fields,
   9695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9696         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9697         -1,
   9698         -1,
   9699     },
   9700 #endif /* chips */
   9701 
   9702 #if defined(BCM_88690_A0)
   9703     { /* SOC_REG_INT_KAPS_RPB_TCAM_B_SCAN_PAUSEr */
   9704         soc_block_list[73],
   9705         soc_genreg,
   9706         2,
   9707         0,
   9708         0x10d,
   9709         SOC_REG_FLAG_ARRAY |
   9710                           SOC_REG_FLAG_RO |
   9711                           SOC_REG_FLAG_REG_ARRAY,
   9712         SOC_REG_FLAG_INIT_ON_READ,
   9713         1,
   9714         soc_KAPS_RPB_TCAM_B_SCAN_PAUSEr_fields,
   9715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9716         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9717         -1,
   9718         -1,
   9719     },
   9720 #endif /* chips */
   9721 
   9722 #if defined(BCM_88690_B0)
   9723     { /* SOC_REG_INT_KAPS_RPB_TCAM_B_SCAN_PAUSE_BCM88690_B0r */
   9724         soc_block_list[73],
   9725         soc_genreg,
   9726         2,
   9727         0,
   9728         0x10d,
   9729         SOC_REG_FLAG_ARRAY |
   9730                           SOC_REG_FLAG_RO |
   9731                           SOC_REG_FLAG_REG_ARRAY,
   9732         SOC_REG_FLAG_INIT_ON_READ,
   9733         1,
   9734         soc_KAPS_RPB_TCAM_B_SCAN_PAUSE_BCM88690_B0r_fields,
   9735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9736         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9737         -1,
   9738         -1,
   9739     },
   9740 #endif /* chips */
   9741 
   9742 #if defined(BCM_88470_A0)
   9743     { /* SOC_REG_INT_KAPS_RPB_TCAM_ECC_CONFIGr */
   9744         soc_block_list[73],
   9745         soc_genreg,
   9746         2,
   9747         0,
   9748         0x108,
   9749         SOC_REG_FLAG_ARRAY |
   9750                           SOC_REG_FLAG_REG_ARRAY,
   9751         0,
   9752         2,
   9753         soc_KAPS_RPB_TCAM_ECC_CONFIGr_fields,
   9754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9755         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9756         -1,
   9757         -1,
   9758     },
   9759 #endif /* chips */
   9760 
   9761 #if defined(BCM_88270_A0)
   9762     { /* SOC_REG_INT_KAPS_RPB_TCAM_ECC_CONFIG_BCM88270_A0r */
   9763         soc_block_list[73],
   9764         soc_genreg,
   9765         2,
   9766         0,
   9767         0x108,
   9768         SOC_REG_FLAG_ARRAY |
   9769                           SOC_REG_FLAG_REG_ARRAY,
   9770         0,
   9771         2,
   9772         soc_KAPS_RPB_TCAM_ECC_CONFIG_BCM88270_A0r_fields,
   9773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9774         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9775         -1,
   9776         -1,
   9777     },
   9778 #endif /* chips */
   9779 
   9780 #if defined(BCM_88470_B0)
   9781     { /* SOC_REG_INT_KAPS_RPB_TCAM_ECC_CONFIG_BCM88470_B0r */
   9782         soc_block_list[73],
   9783         soc_genreg,
   9784         2,
   9785         0,
   9786         0x108,
   9787         SOC_REG_FLAG_ARRAY |
   9788                           SOC_REG_FLAG_REG_ARRAY,
   9789         0,
   9790         2,
   9791         soc_KAPS_RPB_TCAM_ECC_CONFIG_BCM88470_B0r_fields,
   9792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9793         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9794         -1,
   9795         -1,
   9796     },
   9797 #endif /* chips */
   9798 
   9799 #if defined(BCM_88680_A0)
   9800     { /* SOC_REG_INT_KAPS_RPB_TCAM_ECC_CONFIG_BCM88680_A0r */
   9801         soc_block_list[73],
   9802         soc_genreg,
   9803         4,
   9804         0,
   9805         0x142,
   9806         SOC_REG_FLAG_ARRAY |
   9807                           SOC_REG_FLAG_REG_ARRAY,
   9808         0,
   9809         2,
   9810         soc_KAPS_RPB_TCAM_ECC_CONFIG_BCM88680_A0r_fields,
   9811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9812         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9813         -1,
   9814         -1,
   9815     },
   9816 #endif /* chips */
   9817 
   9818 #if defined(BCM_88690_A0)
   9819     { /* SOC_REG_INT_KAPS_RPB_TCAM_ECC_CONFIG_BCM88690_A0r */
   9820         soc_block_list[73],
   9821         soc_genreg,
   9822         2,
   9823         0,
   9824         0x105,
   9825         SOC_REG_FLAG_ARRAY |
   9826                           SOC_REG_FLAG_REG_ARRAY,
   9827         0,
   9828         2,
   9829         soc_KAPS_RPB_TCAM_ECC_CONFIG_BCM88690_A0r_fields,
   9830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9831         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9832         -1,
   9833         -1,
   9834     },
   9835 #endif /* chips */
   9836 
   9837 #if defined(BCM_88690_B0)
   9838     { /* SOC_REG_INT_KAPS_RPB_TCAM_ECC_CONFIG_BCM88690_B0r */
   9839         soc_block_list[73],
   9840         soc_genreg,
   9841         2,
   9842         0,
   9843         0x105,
   9844         SOC_REG_FLAG_ARRAY |
   9845                           SOC_REG_FLAG_REG_ARRAY,
   9846         0,
   9847         2,
   9848         soc_KAPS_RPB_TCAM_ECC_CONFIG_BCM88690_B0r_fields,
   9849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9850         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9851         -1,
   9852         -1,
   9853     },
   9854 #endif /* chips */
   9855 
   9856 #if defined(BCM_88690_A0)
   9857     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_CFGSr */
   9858         soc_block_list[73],
   9859         soc_genreg,
   9860         2,
   9861         0,
   9862         0x107,
   9863         SOC_REG_FLAG_64_BITS |
   9864                           SOC_REG_FLAG_ARRAY |
   9865                           SOC_REG_FLAG_REG_ARRAY,
   9866         0,
   9867         5,
   9868         soc_KAPS_RPB_TCAM_SCAN_CFGSr_fields,
   9869         SOC_RESET_VAL_DEC(0x0000001b, 0x00000000)
   9870         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
   9871         -1,
   9872         -1,
   9873     },
   9874 #endif /* chips */
   9875 
   9876 #if defined(BCM_88690_B0)
   9877     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_CFGS_BCM88690_B0r */
   9878         soc_block_list[73],
   9879         soc_genreg,
   9880         2,
   9881         0,
   9882         0x107,
   9883         SOC_REG_FLAG_64_BITS |
   9884                           SOC_REG_FLAG_ARRAY |
   9885                           SOC_REG_FLAG_REG_ARRAY,
   9886         0,
   9887         5,
   9888         soc_KAPS_RPB_TCAM_SCAN_CFGS_BCM88690_B0r_fields,
   9889         SOC_RESET_VAL_DEC(0x0000001b, 0x00000000)
   9890         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
   9891         -1,
   9892         -1,
   9893     },
   9894 #endif /* chips */
   9895 
   9896 #if defined(BCM_88470_A0)
   9897     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_DEBUG_0r */
   9898         soc_block_list[73],
   9899         soc_genreg,
   9900         2,
   9901         0,
   9902         0x10a,
   9903         SOC_REG_FLAG_ARRAY |
   9904                           SOC_REG_FLAG_REG_ARRAY,
   9905         0,
   9906         2,
   9907         soc_KAPS_RPB_TCAM_SCAN_DEBUG_0r_fields,
   9908         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9909         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9910         -1,
   9911         -1,
   9912     },
   9913 #endif /* chips */
   9914 
   9915 #if defined(BCM_88470_A0)
   9916     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_DEBUG_1r */
   9917         soc_block_list[73],
   9918         soc_genreg,
   9919         2,
   9920         0,
   9921         0x10c,
   9922         SOC_REG_FLAG_ARRAY |
   9923                           SOC_REG_FLAG_REG_ARRAY,
   9924         0,
   9925         1,
   9926         soc_KAPS_RPB_TCAM_SCAN_DEBUG_1r_fields,
   9927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9928         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9929         -1,
   9930         -1,
   9931     },
   9932 #endif /* chips */
   9933 
   9934 #if defined(BCM_88270_A0)
   9935     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_DEBUG_0_BCM88270_A0r */
   9936         soc_block_list[73],
   9937         soc_genreg,
   9938         2,
   9939         0,
   9940         0x10a,
   9941         SOC_REG_FLAG_ARRAY |
   9942                           SOC_REG_FLAG_REG_ARRAY,
   9943         0,
   9944         2,
   9945         soc_KAPS_RPB_TCAM_SCAN_DEBUG_0_BCM88270_A0r_fields,
   9946         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9947         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9948         -1,
   9949         -1,
   9950     },
   9951 #endif /* chips */
   9952 
   9953 #if defined(BCM_88470_B0)
   9954     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_DEBUG_0_BCM88470_B0r */
   9955         soc_block_list[73],
   9956         soc_genreg,
   9957         2,
   9958         0,
   9959         0x10a,
   9960         SOC_REG_FLAG_ARRAY |
   9961                           SOC_REG_FLAG_REG_ARRAY,
   9962         0,
   9963         2,
   9964         soc_KAPS_RPB_TCAM_SCAN_DEBUG_0_BCM88470_B0r_fields,
   9965         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9966         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9967         -1,
   9968         -1,
   9969     },
   9970 #endif /* chips */
   9971 
   9972 #if defined(BCM_88680_A0)
   9973     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_DEBUG_0_BCM88680_A0r */
   9974         soc_block_list[73],
   9975         soc_genreg,
   9976         4,
   9977         0,
   9978         0x146,
   9979         SOC_REG_FLAG_ARRAY |
   9980                           SOC_REG_FLAG_REG_ARRAY,
   9981         0,
   9982         2,
   9983         soc_KAPS_RPB_TCAM_SCAN_DEBUG_0_BCM88680_A0r_fields,
   9984         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9985         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9986         -1,
   9987         -1,
   9988     },
   9989 #endif /* chips */
   9990 
   9991 #if defined(BCM_88270_A0)
   9992     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_DEBUG_1_BCM88270_A0r */
   9993         soc_block_list[73],
   9994         soc_genreg,
   9995         2,
   9996         0,
   9997         0x10c,
   9998         SOC_REG_FLAG_ARRAY |
   9999                           SOC_REG_FLAG_REG_ARRAY,
  10000         0,
  10001         1,
  10002         soc_KAPS_RPB_TCAM_SCAN_DEBUG_1_BCM88270_A0r_fields,
  10003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10004         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10005         -1,
  10006         -1,
  10007     },
  10008 #endif /* chips */
  10009 
  10010 #if defined(BCM_88470_B0)
  10011     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_DEBUG_1_BCM88470_B0r */
  10012         soc_block_list[73],
  10013         soc_genreg,
  10014         2,
  10015         0,
  10016         0x10c,
  10017         SOC_REG_FLAG_ARRAY |
  10018                           SOC_REG_FLAG_REG_ARRAY,
  10019         0,
  10020         1,
  10021         soc_KAPS_RPB_TCAM_SCAN_DEBUG_1_BCM88470_B0r_fields,
  10022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10023         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10024         -1,
  10025         -1,
  10026     },
  10027 #endif /* chips */
  10028 
  10029 #if defined(BCM_88680_A0)
  10030     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_DEBUG_1_BCM88680_A0r */
  10031         soc_block_list[73],
  10032         soc_genreg,
  10033         4,
  10034         0,
  10035         0x14a,
  10036         SOC_REG_FLAG_ARRAY |
  10037                           SOC_REG_FLAG_REG_ARRAY,
  10038         0,
  10039         1,
  10040         soc_KAPS_RPB_TCAM_SCAN_DEBUG_1_BCM88680_A0r_fields,
  10041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10042         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10043         -1,
  10044         -1,
  10045     },
  10046 #endif /* chips */
  10047 
  10048 #if defined(BCM_88470_A0)
  10049     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_ERRORr */
  10050         soc_block_list[73],
  10051         soc_genreg,
  10052         2,
  10053         0,
  10054         0x10e,
  10055         SOC_REG_FLAG_ARRAY |
  10056                           SOC_REG_FLAG_RO |
  10057                           SOC_REG_FLAG_REG_ARRAY,
  10058         0,
  10059         2,
  10060         soc_KAPS_RPB_TCAM_SCAN_ERRORr_fields,
  10061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10062         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10063         -1,
  10064         -1,
  10065     },
  10066 #endif /* chips */
  10067 
  10068 #if defined(BCM_88270_A0)
  10069     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_ERROR_BCM88270_A0r */
  10070         soc_block_list[73],
  10071         soc_genreg,
  10072         2,
  10073         0,
  10074         0x10e,
  10075         SOC_REG_FLAG_ARRAY |
  10076                           SOC_REG_FLAG_RO |
  10077                           SOC_REG_FLAG_REG_ARRAY,
  10078         0,
  10079         2,
  10080         soc_KAPS_RPB_TCAM_SCAN_ERROR_BCM88270_A0r_fields,
  10081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10082         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10083         -1,
  10084         -1,
  10085     },
  10086 #endif /* chips */
  10087 
  10088 #if defined(BCM_88470_B0)
  10089     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_ERROR_BCM88470_B0r */
  10090         soc_block_list[73],
  10091         soc_genreg,
  10092         2,
  10093         0,
  10094         0x10e,
  10095         SOC_REG_FLAG_ARRAY |
  10096                           SOC_REG_FLAG_RO |
  10097                           SOC_REG_FLAG_REG_ARRAY,
  10098         0,
  10099         2,
  10100         soc_KAPS_RPB_TCAM_SCAN_ERROR_BCM88470_B0r_fields,
  10101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10102         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10103         -1,
  10104         -1,
  10105     },
  10106 #endif /* chips */
  10107 
  10108 #if defined(BCM_88680_A0)
  10109     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_ERROR_BCM88680_A0r */
  10110         soc_block_list[73],
  10111         soc_genreg,
  10112         4,
  10113         0,
  10114         0x14e,
  10115         SOC_REG_FLAG_ARRAY |
  10116                           SOC_REG_FLAG_RO |
  10117                           SOC_REG_FLAG_REG_ARRAY,
  10118         0,
  10119         2,
  10120         soc_KAPS_RPB_TCAM_SCAN_ERROR_BCM88680_A0r_fields,
  10121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10122         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10123         -1,
  10124         -1,
  10125     },
  10126 #endif /* chips */
  10127 
  10128 #if defined(BCM_88470_A0)
  10129     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_ERROR_MASKr */
  10130         soc_block_list[73],
  10131         soc_genreg,
  10132         2,
  10133         0,
  10134         0x110,
  10135         SOC_REG_FLAG_ARRAY |
  10136                           SOC_REG_FLAG_REG_ARRAY,
  10137         0,
  10138         2,
  10139         soc_KAPS_RPB_TCAM_SCAN_ERROR_MASKr_fields,
  10140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10141         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10142         -1,
  10143         -1,
  10144     },
  10145 #endif /* chips */
  10146 
  10147 #if defined(BCM_88270_A0)
  10148     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_ERROR_MASK_BCM88270_A0r */
  10149         soc_block_list[73],
  10150         soc_genreg,
  10151         2,
  10152         0,
  10153         0x110,
  10154         SOC_REG_FLAG_ARRAY |
  10155                           SOC_REG_FLAG_REG_ARRAY,
  10156         0,
  10157         2,
  10158         soc_KAPS_RPB_TCAM_SCAN_ERROR_MASK_BCM88270_A0r_fields,
  10159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10160         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10161         -1,
  10162         -1,
  10163     },
  10164 #endif /* chips */
  10165 
  10166 #if defined(BCM_88470_B0)
  10167     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_ERROR_MASK_BCM88470_B0r */
  10168         soc_block_list[73],
  10169         soc_genreg,
  10170         2,
  10171         0,
  10172         0x110,
  10173         SOC_REG_FLAG_ARRAY |
  10174                           SOC_REG_FLAG_REG_ARRAY,
  10175         0,
  10176         2,
  10177         soc_KAPS_RPB_TCAM_SCAN_ERROR_MASK_BCM88470_B0r_fields,
  10178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10179         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10180         -1,
  10181         -1,
  10182     },
  10183 #endif /* chips */
  10184 
  10185 #if defined(BCM_88680_A0)
  10186     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_ERROR_MASK_BCM88680_A0r */
  10187         soc_block_list[73],
  10188         soc_genreg,
  10189         4,
  10190         0,
  10191         0x152,
  10192         SOC_REG_FLAG_ARRAY |
  10193                           SOC_REG_FLAG_REG_ARRAY,
  10194         0,
  10195         2,
  10196         soc_KAPS_RPB_TCAM_SCAN_ERROR_MASK_BCM88680_A0r_fields,
  10197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10198         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10199         -1,
  10200         -1,
  10201     },
  10202 #endif /* chips */
  10203 
  10204 #if defined(BCM_88690_A0)
  10205     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_INDEXr */
  10206         soc_block_list[73],
  10207         soc_genreg,
  10208         2,
  10209         0,
  10210         0x10f,
  10211         SOC_REG_FLAG_ARRAY |
  10212                           SOC_REG_FLAG_RO |
  10213                           SOC_REG_FLAG_REG_ARRAY,
  10214         0,
  10215         2,
  10216         soc_KAPS_RPB_TCAM_SCAN_INDEXr_fields,
  10217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10218         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  10219         -1,
  10220         -1,
  10221     },
  10222 #endif /* chips */
  10223 
  10224 #if defined(BCM_88690_B0)
  10225     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_INDEX_BCM88690_B0r */
  10226         soc_block_list[73],
  10227         soc_genreg,
  10228         2,
  10229         0,
  10230         0x10f,
  10231         SOC_REG_FLAG_ARRAY |
  10232                           SOC_REG_FLAG_RO |
  10233                           SOC_REG_FLAG_REG_ARRAY,
  10234         0,
  10235         2,
  10236         soc_KAPS_RPB_TCAM_SCAN_INDEX_BCM88690_B0r_fields,
  10237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10238         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  10239         -1,
  10240         -1,
  10241     },
  10242 #endif /* chips */
  10243 
  10244 #if defined(BCM_88470_A0)
  10245     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_STATUSr */
  10246         soc_block_list[73],
  10247         soc_genreg,
  10248         2,
  10249         0,
  10250         0x112,
  10251         SOC_REG_FLAG_ARRAY |
  10252                           SOC_REG_FLAG_RO |
  10253                           SOC_REG_FLAG_REG_ARRAY,
  10254         0,
  10255         2,
  10256         soc_KAPS_RPB_TCAM_SCAN_STATUSr_fields,
  10257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10258         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  10259         -1,
  10260         -1,
  10261     },
  10262 #endif /* chips */
  10263 
  10264 #if defined(BCM_88270_A0)
  10265     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_STATUS_BCM88270_A0r */
  10266         soc_block_list[73],
  10267         soc_genreg,
  10268         2,
  10269         0,
  10270         0x112,
  10271         SOC_REG_FLAG_ARRAY |
  10272                           SOC_REG_FLAG_RO |
  10273                           SOC_REG_FLAG_REG_ARRAY,
  10274         0,
  10275         2,
  10276         soc_KAPS_RPB_TCAM_SCAN_STATUS_BCM88270_A0r_fields,
  10277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10278         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  10279         -1,
  10280         -1,
  10281     },
  10282 #endif /* chips */
  10283 
  10284 #if defined(BCM_88470_B0)
  10285     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_STATUS_BCM88470_B0r */
  10286         soc_block_list[73],
  10287         soc_genreg,
  10288         2,
  10289         0,
  10290         0x112,
  10291         SOC_REG_FLAG_ARRAY |
  10292                           SOC_REG_FLAG_RO |
  10293                           SOC_REG_FLAG_REG_ARRAY,
  10294         0,
  10295         2,
  10296         soc_KAPS_RPB_TCAM_SCAN_STATUS_BCM88470_B0r_fields,
  10297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10298         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  10299         -1,
  10300         -1,
  10301     },
  10302 #endif /* chips */
  10303 
  10304 #if defined(BCM_88680_A0)
  10305     { /* SOC_REG_INT_KAPS_RPB_TCAM_SCAN_STATUS_BCM88680_A0r */
  10306         soc_block_list[73],
  10307         soc_genreg,
  10308         4,
  10309         0,
  10310         0x156,
  10311         SOC_REG_FLAG_ARRAY |
  10312                           SOC_REG_FLAG_RO |
  10313                           SOC_REG_FLAG_REG_ARRAY,
  10314         0,
  10315         2,
  10316         soc_KAPS_RPB_TCAM_SCAN_STATUS_BCM88680_A0r_fields,
  10317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10318         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  10319         -1,
  10320         -1,
  10321     },
  10322 #endif /* chips */
  10323 
  10324 #if defined(BCM_88675_A0)
  10325     { /* SOC_REG_INT_KAPS_R_5_ATTNr */
  10326         soc_block_list[73],
  10327         soc_genreg,
  10328         4,
  10329         0,
  10330         0x700,
  10331         SOC_REG_FLAG_ARRAY |
  10332                           SOC_REG_FLAG_REG_ARRAY,
  10333         0,
  10334         1,
  10335         soc_KAPS_R_5_ATTNr_fields,
  10336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10338         -1,
  10339         -1,
  10340     },
  10341 #endif /* chips */
  10342 
  10343 #if defined(BCM_88375_A0)
  10344     { /* SOC_REG_INT_KAPS_R_5_ATTN_BCM88375_A0r */
  10345         soc_block_list[73],
  10346         soc_genreg,
  10347         4,
  10348         0,
  10349         0x700,
  10350         SOC_REG_FLAG_ARRAY |
  10351                           SOC_REG_FLAG_REG_ARRAY,
  10352         0,
  10353         1,
  10354         soc_KAPS_R_5_ATTN_BCM88375_A0r_fields,
  10355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10357         -1,
  10358         -1,
  10359     },
  10360 #endif /* chips */
  10361 
  10362 #if defined(BCM_88375_B0)
  10363     { /* SOC_REG_INT_KAPS_R_5_ATTN_BCM88375_B0r */
  10364         soc_block_list[73],
  10365         soc_genreg,
  10366         4,
  10367         0,
  10368         0x700,
  10369         SOC_REG_FLAG_ARRAY |
  10370                           SOC_REG_FLAG_REG_ARRAY,
  10371         0,
  10372         1,
  10373         soc_KAPS_R_5_ATTN_BCM88375_B0r_fields,
  10374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10375         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10376         -1,
  10377         -1,
  10378     },
  10379 #endif /* chips */
  10380 
  10381 #if defined(BCM_88675_B0)
  10382     { /* SOC_REG_INT_KAPS_R_5_ATTN_BCM88675_B0r */
  10383         soc_block_list[73],
  10384         soc_genreg,
  10385         4,
  10386         0,
  10387         0x700,
  10388         SOC_REG_FLAG_ARRAY |
  10389                           SOC_REG_FLAG_REG_ARRAY,
  10390         0,
  10391         1,
  10392         soc_KAPS_R_5_ATTN_BCM88675_B0r_fields,
  10393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10394         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10395         -1,
  10396         -1,
  10397     },
  10398 #endif /* chips */
  10399 
  10400 #if defined(BCM_88675_A0)
  10401     { /* SOC_REG_INT_KAPS_R_5_AXI_CONFIGr */
  10402         soc_block_list[73],
  10403         soc_genreg,
  10404         1,
  10405         0,
  10406         0x7200,
  10407         0,
  10408         0,
  10409         6,
  10410         soc_KAPS_R_5_AXI_CONFIGr_fields,
  10411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10412         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  10413         -1,
  10414         -1,
  10415     },
  10416 #endif /* chips */
  10417 
  10418 #if defined(BCM_88375_A0)
  10419     { /* SOC_REG_INT_KAPS_R_5_AXI_CONFIG_BCM88375_A0r */
  10420         soc_block_list[73],
  10421         soc_genreg,
  10422         1,
  10423         0,
  10424         0x7200,
  10425         0,
  10426         0,
  10427         6,
  10428         soc_KAPS_R_5_AXI_CONFIG_BCM88375_A0r_fields,
  10429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10430         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  10431         -1,
  10432         -1,
  10433     },
  10434 #endif /* chips */
  10435 
  10436 #if defined(BCM_88375_B0)
  10437     { /* SOC_REG_INT_KAPS_R_5_AXI_CONFIG_BCM88375_B0r */
  10438         soc_block_list[73],
  10439         soc_genreg,
  10440         1,
  10441         0,
  10442         0x7200,
  10443         0,
  10444         0,
  10445         6,
  10446         soc_KAPS_R_5_AXI_CONFIG_BCM88375_B0r_fields,
  10447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10448         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  10449         -1,
  10450         -1,
  10451     },
  10452 #endif /* chips */
  10453 
  10454 #if defined(BCM_88675_B0)
  10455     { /* SOC_REG_INT_KAPS_R_5_AXI_CONFIG_BCM88675_B0r */
  10456         soc_block_list[73],
  10457         soc_genreg,
  10458         1,
  10459         0,
  10460         0x7200,
  10461         0,
  10462         0,
  10463         6,
  10464         soc_KAPS_R_5_AXI_CONFIG_BCM88675_B0r_fields,
  10465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10466         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  10467         -1,
  10468         -1,
  10469     },
  10470 #endif /* chips */
  10471 
  10472 #if defined(BCM_88675_A0)
  10473     { /* SOC_REG_INT_KAPS_R_5_AXI_ERROR_STATUS_0r */
  10474         soc_block_list[73],
  10475         soc_genreg,
  10476         1,
  10477         0,
  10478         0x7300,
  10479         0,
  10480         0,
  10481         7,
  10482         soc_KAPS_R_5_AXI_ERROR_STATUS_0r_fields,
  10483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10484         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10485         -1,
  10486         -1,
  10487     },
  10488 #endif /* chips */
  10489 
  10490 #if defined(BCM_88675_A0)
  10491     { /* SOC_REG_INT_KAPS_R_5_AXI_ERROR_STATUS_1r */
  10492         soc_block_list[73],
  10493         soc_genreg,
  10494         1,
  10495         0,
  10496         0x7400,
  10497         SOC_REG_FLAG_RO,
  10498         0,
  10499         1,
  10500         soc_KAPS_R_5_AXI_ERROR_STATUS_1r_fields,
  10501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10502         SOC_RESET_MASK_DEC(0x007ffff8, 0x00000000)
  10503         -1,
  10504         -1,
  10505     },
  10506 #endif /* chips */
  10507 
  10508 #if defined(BCM_88375_A0)
  10509     { /* SOC_REG_INT_KAPS_R_5_AXI_ERROR_STATUS_0_BCM88375_A0r */
  10510         soc_block_list[73],
  10511         soc_genreg,
  10512         1,
  10513         0,
  10514         0x7300,
  10515         0,
  10516         0,
  10517         7,
  10518         soc_KAPS_R_5_AXI_ERROR_STATUS_0_BCM88375_A0r_fields,
  10519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10520         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10521         -1,
  10522         -1,
  10523     },
  10524 #endif /* chips */
  10525 
  10526 #if defined(BCM_88375_B0)
  10527     { /* SOC_REG_INT_KAPS_R_5_AXI_ERROR_STATUS_0_BCM88375_B0r */
  10528         soc_block_list[73],
  10529         soc_genreg,
  10530         1,
  10531         0,
  10532         0x7300,
  10533         0,
  10534         0,
  10535         7,
  10536         soc_KAPS_R_5_AXI_ERROR_STATUS_0_BCM88375_B0r_fields,
  10537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10538         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10539         -1,
  10540         -1,
  10541     },
  10542 #endif /* chips */
  10543 
  10544 #if defined(BCM_88675_B0)
  10545     { /* SOC_REG_INT_KAPS_R_5_AXI_ERROR_STATUS_0_BCM88675_B0r */
  10546         soc_block_list[73],
  10547         soc_genreg,
  10548         1,
  10549         0,
  10550         0x7300,
  10551         0,
  10552         0,
  10553         7,
  10554         soc_KAPS_R_5_AXI_ERROR_STATUS_0_BCM88675_B0r_fields,
  10555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10556         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10557         -1,
  10558         -1,
  10559     },
  10560 #endif /* chips */
  10561 
  10562 #if defined(BCM_88375_A0)
  10563     { /* SOC_REG_INT_KAPS_R_5_AXI_ERROR_STATUS_1_BCM88375_A0r */
  10564         soc_block_list[73],
  10565         soc_genreg,
  10566         1,
  10567         0,
  10568         0x7400,
  10569         SOC_REG_FLAG_RO,
  10570         0,
  10571         1,
  10572         soc_KAPS_R_5_AXI_ERROR_STATUS_1_BCM88375_A0r_fields,
  10573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10574         SOC_RESET_MASK_DEC(0x007ffff8, 0x00000000)
  10575         -1,
  10576         -1,
  10577     },
  10578 #endif /* chips */
  10579 
  10580 #if defined(BCM_88375_B0)
  10581     { /* SOC_REG_INT_KAPS_R_5_AXI_ERROR_STATUS_1_BCM88375_B0r */
  10582         soc_block_list[73],
  10583         soc_genreg,
  10584         1,
  10585         0,
  10586         0x7400,
  10587         SOC_REG_FLAG_RO,
  10588         0,
  10589         1,
  10590         soc_KAPS_R_5_AXI_ERROR_STATUS_1_BCM88375_B0r_fields,
  10591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10592         SOC_RESET_MASK_DEC(0x007ffff8, 0x00000000)
  10593         -1,
  10594         -1,
  10595     },
  10596 #endif /* chips */
  10597 
  10598 #if defined(BCM_88675_B0)
  10599     { /* SOC_REG_INT_KAPS_R_5_AXI_ERROR_STATUS_1_BCM88675_B0r */
  10600         soc_block_list[73],
  10601         soc_genreg,
  10602         1,
  10603         0,
  10604         0x7400,
  10605         SOC_REG_FLAG_RO,
  10606         0,
  10607         1,
  10608         soc_KAPS_R_5_AXI_ERROR_STATUS_1_BCM88675_B0r_fields,
  10609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10610         SOC_RESET_MASK_DEC(0x007ffff8, 0x00000000)
  10611         -1,
  10612         -1,
  10613     },
  10614 #endif /* chips */
  10615 
  10616 #if defined(BCM_88675_A0)
  10617     { /* SOC_REG_INT_KAPS_R_5_CONFIGAr */
  10618         soc_block_list[73],
  10619         soc_genreg,
  10620         1,
  10621         0,
  10622         0x7700,
  10623         0,
  10624         0,
  10625         2,
  10626         soc_KAPS_R_5_CONFIGAr_fields,
  10627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10628         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  10629         -1,
  10630         -1,
  10631     },
  10632 #endif /* chips */
  10633 
  10634 #if defined(BCM_88375_A0)
  10635     { /* SOC_REG_INT_KAPS_R_5_CONFIGA_BCM88375_A0r */
  10636         soc_block_list[73],
  10637         soc_genreg,
  10638         1,
  10639         0,
  10640         0x7700,
  10641         0,
  10642         0,
  10643         2,
  10644         soc_KAPS_R_5_CONFIGA_BCM88375_A0r_fields,
  10645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10646         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  10647         -1,
  10648         -1,
  10649     },
  10650 #endif /* chips */
  10651 
  10652 #if defined(BCM_88375_B0)
  10653     { /* SOC_REG_INT_KAPS_R_5_CONFIGA_BCM88375_B0r */
  10654         soc_block_list[73],
  10655         soc_genreg,
  10656         1,
  10657         0,
  10658         0x7700,
  10659         0,
  10660         0,
  10661         2,
  10662         soc_KAPS_R_5_CONFIGA_BCM88375_B0r_fields,
  10663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10664         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  10665         -1,
  10666         -1,
  10667     },
  10668 #endif /* chips */
  10669 
  10670 #if defined(BCM_88675_B0)
  10671     { /* SOC_REG_INT_KAPS_R_5_CONFIGA_BCM88675_B0r */
  10672         soc_block_list[73],
  10673         soc_genreg,
  10674         1,
  10675         0,
  10676         0x7700,
  10677         0,
  10678         0,
  10679         2,
  10680         soc_KAPS_R_5_CONFIGA_BCM88675_B0r_fields,
  10681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10682         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  10683         -1,
  10684         -1,
  10685     },
  10686 #endif /* chips */
  10687 
  10688 #if defined(BCM_88675_A0)
  10689     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGAr */
  10690         soc_block_list[73],
  10691         soc_genreg,
  10692         1,
  10693         0,
  10694         0x6d00,
  10695         0,
  10696         0,
  10697         16,
  10698         soc_KAPS_R_5_CORE_CONFIGAr_fields,
  10699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10700         SOC_RESET_MASK_DEC(0xfefff773, 0x00000000)
  10701         -1,
  10702         -1,
  10703     },
  10704 #endif /* chips */
  10705 
  10706 #if defined(BCM_88375_A0)
  10707     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGA_BCM88375_A0r */
  10708         soc_block_list[73],
  10709         soc_genreg,
  10710         1,
  10711         0,
  10712         0x6d00,
  10713         0,
  10714         0,
  10715         16,
  10716         soc_KAPS_R_5_CORE_CONFIGA_BCM88375_A0r_fields,
  10717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10718         SOC_RESET_MASK_DEC(0xfefff773, 0x00000000)
  10719         -1,
  10720         -1,
  10721     },
  10722 #endif /* chips */
  10723 
  10724 #if defined(BCM_88375_B0)
  10725     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGA_BCM88375_B0r */
  10726         soc_block_list[73],
  10727         soc_genreg,
  10728         1,
  10729         0,
  10730         0x6d00,
  10731         0,
  10732         0,
  10733         16,
  10734         soc_KAPS_R_5_CORE_CONFIGA_BCM88375_B0r_fields,
  10735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10736         SOC_RESET_MASK_DEC(0xfefff773, 0x00000000)
  10737         -1,
  10738         -1,
  10739     },
  10740 #endif /* chips */
  10741 
  10742 #if defined(BCM_88675_B0)
  10743     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGA_BCM88675_B0r */
  10744         soc_block_list[73],
  10745         soc_genreg,
  10746         1,
  10747         0,
  10748         0x6d00,
  10749         0,
  10750         0,
  10751         16,
  10752         soc_KAPS_R_5_CORE_CONFIGA_BCM88675_B0r_fields,
  10753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10754         SOC_RESET_MASK_DEC(0xfefff773, 0x00000000)
  10755         -1,
  10756         -1,
  10757     },
  10758 #endif /* chips */
  10759 
  10760 #if defined(BCM_88675_A0)
  10761     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGBr */
  10762         soc_block_list[73],
  10763         soc_genreg,
  10764         1,
  10765         0,
  10766         0x6e00,
  10767         0,
  10768         0,
  10769         3,
  10770         soc_KAPS_R_5_CORE_CONFIGBr_fields,
  10771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10772         SOC_RESET_MASK_DEC(0xfffff11f, 0x00000000)
  10773         -1,
  10774         -1,
  10775     },
  10776 #endif /* chips */
  10777 
  10778 #if defined(BCM_88375_A0)
  10779     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGB_BCM88375_A0r */
  10780         soc_block_list[73],
  10781         soc_genreg,
  10782         1,
  10783         0,
  10784         0x6e00,
  10785         0,
  10786         0,
  10787         3,
  10788         soc_KAPS_R_5_CORE_CONFIGB_BCM88375_A0r_fields,
  10789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10790         SOC_RESET_MASK_DEC(0xfffff11f, 0x00000000)
  10791         -1,
  10792         -1,
  10793     },
  10794 #endif /* chips */
  10795 
  10796 #if defined(BCM_88375_B0)
  10797     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGB_BCM88375_B0r */
  10798         soc_block_list[73],
  10799         soc_genreg,
  10800         1,
  10801         0,
  10802         0x6e00,
  10803         0,
  10804         0,
  10805         3,
  10806         soc_KAPS_R_5_CORE_CONFIGB_BCM88375_B0r_fields,
  10807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10808         SOC_RESET_MASK_DEC(0xfffff11f, 0x00000000)
  10809         -1,
  10810         -1,
  10811     },
  10812 #endif /* chips */
  10813 
  10814 #if defined(BCM_88675_B0)
  10815     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGB_BCM88675_B0r */
  10816         soc_block_list[73],
  10817         soc_genreg,
  10818         1,
  10819         0,
  10820         0x6e00,
  10821         0,
  10822         0,
  10823         3,
  10824         soc_KAPS_R_5_CORE_CONFIGB_BCM88675_B0r_fields,
  10825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10826         SOC_RESET_MASK_DEC(0xfffff11f, 0x00000000)
  10827         -1,
  10828         -1,
  10829     },
  10830 #endif /* chips */
  10831 
  10832 #if defined(BCM_88675_A0)
  10833     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGCr */
  10834         soc_block_list[73],
  10835         soc_genreg,
  10836         1,
  10837         0,
  10838         0x6f00,
  10839         0,
  10840         0,
  10841         3,
  10842         soc_KAPS_R_5_CORE_CONFIGCr_fields,
  10843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10844         SOC_RESET_MASK_DEC(0xfffff11f, 0x00000000)
  10845         -1,
  10846         -1,
  10847     },
  10848 #endif /* chips */
  10849 
  10850 #if defined(BCM_88375_A0)
  10851     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGC_BCM88375_A0r */
  10852         soc_block_list[73],
  10853         soc_genreg,
  10854         1,
  10855         0,
  10856         0x6f00,
  10857         0,
  10858         0,
  10859         3,
  10860         soc_KAPS_R_5_CORE_CONFIGC_BCM88375_A0r_fields,
  10861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10862         SOC_RESET_MASK_DEC(0xfffff11f, 0x00000000)
  10863         -1,
  10864         -1,
  10865     },
  10866 #endif /* chips */
  10867 
  10868 #if defined(BCM_88375_B0)
  10869     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGC_BCM88375_B0r */
  10870         soc_block_list[73],
  10871         soc_genreg,
  10872         1,
  10873         0,
  10874         0x6f00,
  10875         0,
  10876         0,
  10877         3,
  10878         soc_KAPS_R_5_CORE_CONFIGC_BCM88375_B0r_fields,
  10879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10880         SOC_RESET_MASK_DEC(0xfffff11f, 0x00000000)
  10881         -1,
  10882         -1,
  10883     },
  10884 #endif /* chips */
  10885 
  10886 #if defined(BCM_88675_B0)
  10887     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGC_BCM88675_B0r */
  10888         soc_block_list[73],
  10889         soc_genreg,
  10890         1,
  10891         0,
  10892         0x6f00,
  10893         0,
  10894         0,
  10895         3,
  10896         soc_KAPS_R_5_CORE_CONFIGC_BCM88675_B0r_fields,
  10897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10898         SOC_RESET_MASK_DEC(0xfffff11f, 0x00000000)
  10899         -1,
  10900         -1,
  10901     },
  10902 #endif /* chips */
  10903 
  10904 #if defined(BCM_88675_A0)
  10905     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGDr */
  10906         soc_block_list[73],
  10907         soc_genreg,
  10908         1,
  10909         0,
  10910         0x7000,
  10911         0,
  10912         0,
  10913         2,
  10914         soc_KAPS_R_5_CORE_CONFIGDr_fields,
  10915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10916         SOC_RESET_MASK_DEC(0xfffff01f, 0x00000000)
  10917         -1,
  10918         -1,
  10919     },
  10920 #endif /* chips */
  10921 
  10922 #if defined(BCM_88375_A0)
  10923     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGD_BCM88375_A0r */
  10924         soc_block_list[73],
  10925         soc_genreg,
  10926         1,
  10927         0,
  10928         0x7000,
  10929         0,
  10930         0,
  10931         2,
  10932         soc_KAPS_R_5_CORE_CONFIGD_BCM88375_A0r_fields,
  10933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10934         SOC_RESET_MASK_DEC(0xfffff01f, 0x00000000)
  10935         -1,
  10936         -1,
  10937     },
  10938 #endif /* chips */
  10939 
  10940 #if defined(BCM_88375_B0)
  10941     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGD_BCM88375_B0r */
  10942         soc_block_list[73],
  10943         soc_genreg,
  10944         1,
  10945         0,
  10946         0x7000,
  10947         0,
  10948         0,
  10949         2,
  10950         soc_KAPS_R_5_CORE_CONFIGD_BCM88375_B0r_fields,
  10951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10952         SOC_RESET_MASK_DEC(0xfffff01f, 0x00000000)
  10953         -1,
  10954         -1,
  10955     },
  10956 #endif /* chips */
  10957 
  10958 #if defined(BCM_88675_B0)
  10959     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGD_BCM88675_B0r */
  10960         soc_block_list[73],
  10961         soc_genreg,
  10962         1,
  10963         0,
  10964         0x7000,
  10965         0,
  10966         0,
  10967         2,
  10968         soc_KAPS_R_5_CORE_CONFIGD_BCM88675_B0r_fields,
  10969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10970         SOC_RESET_MASK_DEC(0xfffff01f, 0x00000000)
  10971         -1,
  10972         -1,
  10973     },
  10974 #endif /* chips */
  10975 
  10976 #if defined(BCM_88675_A0)
  10977     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGEr */
  10978         soc_block_list[73],
  10979         soc_genreg,
  10980         1,
  10981         0,
  10982         0x7100,
  10983         0,
  10984         0,
  10985         1,
  10986         soc_KAPS_R_5_CORE_CONFIGEr_fields,
  10987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10988         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  10989         -1,
  10990         -1,
  10991     },
  10992 #endif /* chips */
  10993 
  10994 #if defined(BCM_88375_A0)
  10995     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGE_BCM88375_A0r */
  10996         soc_block_list[73],
  10997         soc_genreg,
  10998         1,
  10999         0,
  11000         0x7100,
  11001         0,
  11002         0,
  11003         1,
  11004         soc_KAPS_R_5_CORE_CONFIGE_BCM88375_A0r_fields,
  11005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11006         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  11007         -1,
  11008         -1,
  11009     },
  11010 #endif /* chips */
  11011 
  11012 #if defined(BCM_88375_B0)
  11013     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGE_BCM88375_B0r */
  11014         soc_block_list[73],
  11015         soc_genreg,
  11016         1,
  11017         0,
  11018         0x7100,
  11019         0,
  11020         0,
  11021         1,
  11022         soc_KAPS_R_5_CORE_CONFIGE_BCM88375_B0r_fields,
  11023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11024         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  11025         -1,
  11026         -1,
  11027     },
  11028 #endif /* chips */
  11029 
  11030 #if defined(BCM_88675_B0)
  11031     { /* SOC_REG_INT_KAPS_R_5_CORE_CONFIGE_BCM88675_B0r */
  11032         soc_block_list[73],
  11033         soc_genreg,
  11034         1,
  11035         0,
  11036         0x7100,
  11037         0,
  11038         0,
  11039         1,
  11040         soc_KAPS_R_5_CORE_CONFIGE_BCM88675_B0r_fields,
  11041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11042         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  11043         -1,
  11044         -1,
  11045     },
  11046 #endif /* chips */
  11047 
  11048 #if defined(BCM_88675_A0)
  11049     { /* SOC_REG_INT_KAPS_R_5_CORE_CONTROLr */
  11050         soc_block_list[73],
  11051         soc_genreg,
  11052         1,
  11053         0,
  11054         0x6500,
  11055         0,
  11056         0,
  11057         7,
  11058         soc_KAPS_R_5_CORE_CONTROLr_fields,
  11059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11060         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11061         -1,
  11062         -1,
  11063     },
  11064 #endif /* chips */
  11065 
  11066 #if defined(BCM_88375_A0)
  11067     { /* SOC_REG_INT_KAPS_R_5_CORE_CONTROL_BCM88375_A0r */
  11068         soc_block_list[73],
  11069         soc_genreg,
  11070         1,
  11071         0,
  11072         0x6500,
  11073         0,
  11074         0,
  11075         7,
  11076         soc_KAPS_R_5_CORE_CONTROL_BCM88375_A0r_fields,
  11077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11078         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11079         -1,
  11080         -1,
  11081     },
  11082 #endif /* chips */
  11083 
  11084 #if defined(BCM_88375_B0)
  11085     { /* SOC_REG_INT_KAPS_R_5_CORE_CONTROL_BCM88375_B0r */
  11086         soc_block_list[73],
  11087         soc_genreg,
  11088         1,
  11089         0,
  11090         0x6500,
  11091         0,
  11092         0,
  11093         7,
  11094         soc_KAPS_R_5_CORE_CONTROL_BCM88375_B0r_fields,
  11095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11096         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11097         -1,
  11098         -1,
  11099     },
  11100 #endif /* chips */
  11101 
  11102 #if defined(BCM_88675_B0)
  11103     { /* SOC_REG_INT_KAPS_R_5_CORE_CONTROL_BCM88675_B0r */
  11104         soc_block_list[73],
  11105         soc_genreg,
  11106         1,
  11107         0,
  11108         0x6500,
  11109         0,
  11110         0,
  11111         7,
  11112         soc_KAPS_R_5_CORE_CONTROL_BCM88675_B0r_fields,
  11113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11114         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11115         -1,
  11116         -1,
  11117     },
  11118 #endif /* chips */
  11119 
  11120 #if defined(BCM_88675_A0)
  11121     { /* SOC_REG_INT_KAPS_R_5_CORE_MEM_CONTROLr */
  11122         soc_block_list[73],
  11123         soc_genreg,
  11124         1,
  11125         0,
  11126         0x6600,
  11127         0,
  11128         0,
  11129         12,
  11130         soc_KAPS_R_5_CORE_MEM_CONTROLr_fields,
  11131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11132         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  11133         -1,
  11134         -1,
  11135     },
  11136 #endif /* chips */
  11137 
  11138 #if defined(BCM_88375_A0)
  11139     { /* SOC_REG_INT_KAPS_R_5_CORE_MEM_CONTROL_BCM88375_A0r */
  11140         soc_block_list[73],
  11141         soc_genreg,
  11142         1,
  11143         0,
  11144         0x6600,
  11145         0,
  11146         0,
  11147         12,
  11148         soc_KAPS_R_5_CORE_MEM_CONTROL_BCM88375_A0r_fields,
  11149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11150         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  11151         -1,
  11152         -1,
  11153     },
  11154 #endif /* chips */
  11155 
  11156 #if defined(BCM_88375_B0)
  11157     { /* SOC_REG_INT_KAPS_R_5_CORE_MEM_CONTROL_BCM88375_B0r */
  11158         soc_block_list[73],
  11159         soc_genreg,
  11160         1,
  11161         0,
  11162         0x6600,
  11163         0,
  11164         0,
  11165         12,
  11166         soc_KAPS_R_5_CORE_MEM_CONTROL_BCM88375_B0r_fields,
  11167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11168         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  11169         -1,
  11170         -1,
  11171     },
  11172 #endif /* chips */
  11173 
  11174 #if defined(BCM_88675_B0)
  11175     { /* SOC_REG_INT_KAPS_R_5_CORE_MEM_CONTROL_BCM88675_B0r */
  11176         soc_block_list[73],
  11177         soc_genreg,
  11178         1,
  11179         0,
  11180         0x6600,
  11181         0,
  11182         0,
  11183         12,
  11184         soc_KAPS_R_5_CORE_MEM_CONTROL_BCM88675_B0r_fields,
  11185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11186         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  11187         -1,
  11188         -1,
  11189     },
  11190 #endif /* chips */
  11191 
  11192 #if defined(BCM_88675_A0)
  11193     { /* SOC_REG_INT_KAPS_R_5_COUNTERSr */
  11194         soc_block_list[73],
  11195         soc_genreg,
  11196         16,
  11197         0,
  11198         0xb00,
  11199         SOC_REG_FLAG_ARRAY |
  11200                           SOC_REG_FLAG_RO |
  11201                           SOC_REG_FLAG_REG_ARRAY,
  11202         0,
  11203         1,
  11204         soc_KAPS_R_5_COUNTERSr_fields,
  11205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11206         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11207         -1,
  11208         -1,
  11209     },
  11210 #endif /* chips */
  11211 
  11212 #if defined(BCM_88375_A0)
  11213     { /* SOC_REG_INT_KAPS_R_5_COUNTERS_BCM88375_A0r */
  11214         soc_block_list[73],
  11215         soc_genreg,
  11216         16,
  11217         0,
  11218         0xb00,
  11219         SOC_REG_FLAG_ARRAY |
  11220                           SOC_REG_FLAG_RO |
  11221                           SOC_REG_FLAG_REG_ARRAY,
  11222         0,
  11223         1,
  11224         soc_KAPS_R_5_COUNTERS_BCM88375_A0r_fields,
  11225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11226         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11227         -1,
  11228         -1,
  11229     },
  11230 #endif /* chips */
  11231 
  11232 #if defined(BCM_88375_B0)
  11233     { /* SOC_REG_INT_KAPS_R_5_COUNTERS_BCM88375_B0r */
  11234         soc_block_list[73],
  11235         soc_genreg,
  11236         16,
  11237         0,
  11238         0xb00,
  11239         SOC_REG_FLAG_ARRAY |
  11240                           SOC_REG_FLAG_RO |
  11241                           SOC_REG_FLAG_REG_ARRAY,
  11242         0,
  11243         1,
  11244         soc_KAPS_R_5_COUNTERS_BCM88375_B0r_fields,
  11245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11246         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11247         -1,
  11248         -1,
  11249     },
  11250 #endif /* chips */
  11251 
  11252 #if defined(BCM_88675_B0)
  11253     { /* SOC_REG_INT_KAPS_R_5_COUNTERS_BCM88675_B0r */
  11254         soc_block_list[73],
  11255         soc_genreg,
  11256         16,
  11257         0,
  11258         0xb00,
  11259         SOC_REG_FLAG_ARRAY |
  11260                           SOC_REG_FLAG_RO |
  11261                           SOC_REG_FLAG_REG_ARRAY,
  11262         0,
  11263         1,
  11264         soc_KAPS_R_5_COUNTERS_BCM88675_B0r_fields,
  11265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11266         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11267         -1,
  11268         -1,
  11269     },
  11270 #endif /* chips */
  11271 
  11272 #if defined(BCM_88675_A0)
  11273     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_ADDRr */
  11274         soc_block_list[73],
  11275         soc_genreg,
  11276         1,
  11277         0,
  11278         0x8200,
  11279         0,
  11280         0,
  11281         1,
  11282         soc_KAPS_R_5_DAP_APB_ADDRr_fields,
  11283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11284         SOC_RESET_MASK_DEC(0x7ffffffc, 0x00000000)
  11285         -1,
  11286         -1,
  11287     },
  11288 #endif /* chips */
  11289 
  11290 #if defined(BCM_88375_A0)
  11291     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_ADDR_BCM88375_A0r */
  11292         soc_block_list[73],
  11293         soc_genreg,
  11294         1,
  11295         0,
  11296         0x8200,
  11297         0,
  11298         0,
  11299         1,
  11300         soc_KAPS_R_5_DAP_APB_ADDR_BCM88375_A0r_fields,
  11301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11302         SOC_RESET_MASK_DEC(0x7ffffffc, 0x00000000)
  11303         -1,
  11304         -1,
  11305     },
  11306 #endif /* chips */
  11307 
  11308 #if defined(BCM_88375_B0)
  11309     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_ADDR_BCM88375_B0r */
  11310         soc_block_list[73],
  11311         soc_genreg,
  11312         1,
  11313         0,
  11314         0x8200,
  11315         0,
  11316         0,
  11317         1,
  11318         soc_KAPS_R_5_DAP_APB_ADDR_BCM88375_B0r_fields,
  11319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11320         SOC_RESET_MASK_DEC(0x7ffffffc, 0x00000000)
  11321         -1,
  11322         -1,
  11323     },
  11324 #endif /* chips */
  11325 
  11326 #if defined(BCM_88675_B0)
  11327     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_ADDR_BCM88675_B0r */
  11328         soc_block_list[73],
  11329         soc_genreg,
  11330         1,
  11331         0,
  11332         0x8200,
  11333         0,
  11334         0,
  11335         1,
  11336         soc_KAPS_R_5_DAP_APB_ADDR_BCM88675_B0r_fields,
  11337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11338         SOC_RESET_MASK_DEC(0x7ffffffc, 0x00000000)
  11339         -1,
  11340         -1,
  11341     },
  11342 #endif /* chips */
  11343 
  11344 #if defined(BCM_88675_A0)
  11345     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_CTRLr */
  11346         soc_block_list[73],
  11347         soc_genreg,
  11348         1,
  11349         0,
  11350         0x8100,
  11351         0,
  11352         0,
  11353         6,
  11354         soc_KAPS_R_5_DAP_APB_CTRLr_fields,
  11355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11356         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11357         -1,
  11358         -1,
  11359     },
  11360 #endif /* chips */
  11361 
  11362 #if defined(BCM_88375_A0)
  11363     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_CTRL_BCM88375_A0r */
  11364         soc_block_list[73],
  11365         soc_genreg,
  11366         1,
  11367         0,
  11368         0x8100,
  11369         0,
  11370         0,
  11371         6,
  11372         soc_KAPS_R_5_DAP_APB_CTRL_BCM88375_A0r_fields,
  11373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11374         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11375         -1,
  11376         -1,
  11377     },
  11378 #endif /* chips */
  11379 
  11380 #if defined(BCM_88375_B0)
  11381     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_CTRL_BCM88375_B0r */
  11382         soc_block_list[73],
  11383         soc_genreg,
  11384         1,
  11385         0,
  11386         0x8100,
  11387         0,
  11388         0,
  11389         6,
  11390         soc_KAPS_R_5_DAP_APB_CTRL_BCM88375_B0r_fields,
  11391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11392         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11393         -1,
  11394         -1,
  11395     },
  11396 #endif /* chips */
  11397 
  11398 #if defined(BCM_88675_B0)
  11399     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_CTRL_BCM88675_B0r */
  11400         soc_block_list[73],
  11401         soc_genreg,
  11402         1,
  11403         0,
  11404         0x8100,
  11405         0,
  11406         0,
  11407         6,
  11408         soc_KAPS_R_5_DAP_APB_CTRL_BCM88675_B0r_fields,
  11409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11410         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11411         -1,
  11412         -1,
  11413     },
  11414 #endif /* chips */
  11415 
  11416 #if defined(BCM_88675_A0)
  11417     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_RDATAr */
  11418         soc_block_list[73],
  11419         soc_genreg,
  11420         1,
  11421         0,
  11422         0x8400,
  11423         SOC_REG_FLAG_RO,
  11424         0,
  11425         1,
  11426         soc_KAPS_R_5_DAP_APB_RDATAr_fields,
  11427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11428         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11429         -1,
  11430         -1,
  11431     },
  11432 #endif /* chips */
  11433 
  11434 #if defined(BCM_88375_A0)
  11435     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_RDATA_BCM88375_A0r */
  11436         soc_block_list[73],
  11437         soc_genreg,
  11438         1,
  11439         0,
  11440         0x8400,
  11441         SOC_REG_FLAG_RO,
  11442         0,
  11443         1,
  11444         soc_KAPS_R_5_DAP_APB_RDATA_BCM88375_A0r_fields,
  11445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11446         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11447         -1,
  11448         -1,
  11449     },
  11450 #endif /* chips */
  11451 
  11452 #if defined(BCM_88375_B0)
  11453     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_RDATA_BCM88375_B0r */
  11454         soc_block_list[73],
  11455         soc_genreg,
  11456         1,
  11457         0,
  11458         0x8400,
  11459         SOC_REG_FLAG_RO,
  11460         0,
  11461         1,
  11462         soc_KAPS_R_5_DAP_APB_RDATA_BCM88375_B0r_fields,
  11463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11464         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11465         -1,
  11466         -1,
  11467     },
  11468 #endif /* chips */
  11469 
  11470 #if defined(BCM_88675_B0)
  11471     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_RDATA_BCM88675_B0r */
  11472         soc_block_list[73],
  11473         soc_genreg,
  11474         1,
  11475         0,
  11476         0x8400,
  11477         SOC_REG_FLAG_RO,
  11478         0,
  11479         1,
  11480         soc_KAPS_R_5_DAP_APB_RDATA_BCM88675_B0r_fields,
  11481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11482         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11483         -1,
  11484         -1,
  11485     },
  11486 #endif /* chips */
  11487 
  11488 #if defined(BCM_88675_A0)
  11489     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_WDATAr */
  11490         soc_block_list[73],
  11491         soc_genreg,
  11492         1,
  11493         0,
  11494         0x8300,
  11495         0,
  11496         0,
  11497         1,
  11498         soc_KAPS_R_5_DAP_APB_WDATAr_fields,
  11499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11501         -1,
  11502         -1,
  11503     },
  11504 #endif /* chips */
  11505 
  11506 #if defined(BCM_88375_A0)
  11507     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_WDATA_BCM88375_A0r */
  11508         soc_block_list[73],
  11509         soc_genreg,
  11510         1,
  11511         0,
  11512         0x8300,
  11513         0,
  11514         0,
  11515         1,
  11516         soc_KAPS_R_5_DAP_APB_WDATA_BCM88375_A0r_fields,
  11517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11518         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11519         -1,
  11520         -1,
  11521     },
  11522 #endif /* chips */
  11523 
  11524 #if defined(BCM_88375_B0)
  11525     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_WDATA_BCM88375_B0r */
  11526         soc_block_list[73],
  11527         soc_genreg,
  11528         1,
  11529         0,
  11530         0x8300,
  11531         0,
  11532         0,
  11533         1,
  11534         soc_KAPS_R_5_DAP_APB_WDATA_BCM88375_B0r_fields,
  11535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11536         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11537         -1,
  11538         -1,
  11539     },
  11540 #endif /* chips */
  11541 
  11542 #if defined(BCM_88675_B0)
  11543     { /* SOC_REG_INT_KAPS_R_5_DAP_APB_WDATA_BCM88675_B0r */
  11544         soc_block_list[73],
  11545         soc_genreg,
  11546         1,
  11547         0,
  11548         0x8300,
  11549         0,
  11550         0,
  11551         1,
  11552         soc_KAPS_R_5_DAP_APB_WDATA_BCM88675_B0r_fields,
  11553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11554         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11555         -1,
  11556         -1,
  11557     },
  11558 #endif /* chips */
  11559 
  11560 #if defined(BCM_88675_A0)
  11561     { /* SOC_REG_INT_KAPS_R_5_DEBUG_CONFIGAr */
  11562         soc_block_list[73],
  11563         soc_genreg,
  11564         1,
  11565         0,
  11566         0x7500,
  11567         0,
  11568         0,
  11569         14,
  11570         soc_KAPS_R_5_DEBUG_CONFIGAr_fields,
  11571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11572         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  11573         -1,
  11574         -1,
  11575     },
  11576 #endif /* chips */
  11577 
  11578 #if defined(BCM_88375_A0)
  11579     { /* SOC_REG_INT_KAPS_R_5_DEBUG_CONFIGA_BCM88375_A0r */
  11580         soc_block_list[73],
  11581         soc_genreg,
  11582         1,
  11583         0,
  11584         0x7500,
  11585         0,
  11586         0,
  11587         14,
  11588         soc_KAPS_R_5_DEBUG_CONFIGA_BCM88375_A0r_fields,
  11589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11590         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  11591         -1,
  11592         -1,
  11593     },
  11594 #endif /* chips */
  11595 
  11596 #if defined(BCM_88375_B0)
  11597     { /* SOC_REG_INT_KAPS_R_5_DEBUG_CONFIGA_BCM88375_B0r */
  11598         soc_block_list[73],
  11599         soc_genreg,
  11600         1,
  11601         0,
  11602         0x7500,
  11603         0,
  11604         0,
  11605         14,
  11606         soc_KAPS_R_5_DEBUG_CONFIGA_BCM88375_B0r_fields,
  11607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11608         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  11609         -1,
  11610         -1,
  11611     },
  11612 #endif /* chips */
  11613 
  11614 #if defined(BCM_88675_B0)
  11615     { /* SOC_REG_INT_KAPS_R_5_DEBUG_CONFIGA_BCM88675_B0r */
  11616         soc_block_list[73],
  11617         soc_genreg,
  11618         1,
  11619         0,
  11620         0x7500,
  11621         0,
  11622         0,
  11623         14,
  11624         soc_KAPS_R_5_DEBUG_CONFIGA_BCM88675_B0r_fields,
  11625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11626         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  11627         -1,
  11628         -1,
  11629     },
  11630 #endif /* chips */
  11631 
  11632 #if defined(BCM_88675_A0)
  11633     { /* SOC_REG_INT_KAPS_R_5_DEBUG_CONFIGBr */
  11634         soc_block_list[73],
  11635         soc_genreg,
  11636         1,
  11637         0,
  11638         0x7600,
  11639         0,
  11640         0,
  11641         2,
  11642         soc_KAPS_R_5_DEBUG_CONFIGBr_fields,
  11643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11644         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  11645         -1,
  11646         -1,
  11647     },
  11648 #endif /* chips */
  11649 
  11650 #if defined(BCM_88375_A0)
  11651     { /* SOC_REG_INT_KAPS_R_5_DEBUG_CONFIGB_BCM88375_A0r */
  11652         soc_block_list[73],
  11653         soc_genreg,
  11654         1,
  11655         0,
  11656         0x7600,
  11657         0,
  11658         0,
  11659         2,
  11660         soc_KAPS_R_5_DEBUG_CONFIGB_BCM88375_A0r_fields,
  11661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11662         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  11663         -1,
  11664         -1,
  11665     },
  11666 #endif /* chips */
  11667 
  11668 #if defined(BCM_88375_B0)
  11669     { /* SOC_REG_INT_KAPS_R_5_DEBUG_CONFIGB_BCM88375_B0r */
  11670         soc_block_list[73],
  11671         soc_genreg,
  11672         1,
  11673         0,
  11674         0x7600,
  11675         0,
  11676         0,
  11677         2,
  11678         soc_KAPS_R_5_DEBUG_CONFIGB_BCM88375_B0r_fields,
  11679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11680         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  11681         -1,
  11682         -1,
  11683     },
  11684 #endif /* chips */
  11685 
  11686 #if defined(BCM_88675_B0)
  11687     { /* SOC_REG_INT_KAPS_R_5_DEBUG_CONFIGB_BCM88675_B0r */
  11688         soc_block_list[73],
  11689         soc_genreg,
  11690         1,
  11691         0,
  11692         0x7600,
  11693         0,
  11694         0,
  11695         2,
  11696         soc_KAPS_R_5_DEBUG_CONFIGB_BCM88675_B0r_fields,
  11697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11698         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  11699         -1,
  11700         -1,
  11701     },
  11702 #endif /* chips */
  11703 
  11704 #if defined(BCM_88675_A0)
  11705     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_0r */
  11706         soc_block_list[73],
  11707         soc_genreg,
  11708         1,
  11709         0,
  11710         0x7d00,
  11711         0,
  11712         0,
  11713         1,
  11714         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_0r_fields,
  11715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11716         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11717         -1,
  11718         -1,
  11719     },
  11720 #endif /* chips */
  11721 
  11722 #if defined(BCM_88675_A0)
  11723     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_1r */
  11724         soc_block_list[73],
  11725         soc_genreg,
  11726         1,
  11727         0,
  11728         0x7e00,
  11729         0,
  11730         0,
  11731         1,
  11732         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_1r_fields,
  11733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11734         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11735         -1,
  11736         -1,
  11737     },
  11738 #endif /* chips */
  11739 
  11740 #if defined(BCM_88375_A0)
  11741     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_0_BCM88375_A0r */
  11742         soc_block_list[73],
  11743         soc_genreg,
  11744         1,
  11745         0,
  11746         0x7d00,
  11747         0,
  11748         0,
  11749         1,
  11750         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_0_BCM88375_A0r_fields,
  11751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11752         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11753         -1,
  11754         -1,
  11755     },
  11756 #endif /* chips */
  11757 
  11758 #if defined(BCM_88375_B0)
  11759     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_0_BCM88375_B0r */
  11760         soc_block_list[73],
  11761         soc_genreg,
  11762         1,
  11763         0,
  11764         0x7d00,
  11765         0,
  11766         0,
  11767         1,
  11768         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_0_BCM88375_B0r_fields,
  11769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11770         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11771         -1,
  11772         -1,
  11773     },
  11774 #endif /* chips */
  11775 
  11776 #if defined(BCM_88675_B0)
  11777     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_0_BCM88675_B0r */
  11778         soc_block_list[73],
  11779         soc_genreg,
  11780         1,
  11781         0,
  11782         0x7d00,
  11783         0,
  11784         0,
  11785         1,
  11786         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_0_BCM88675_B0r_fields,
  11787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11788         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11789         -1,
  11790         -1,
  11791     },
  11792 #endif /* chips */
  11793 
  11794 #if defined(BCM_88675_A0)
  11795     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASKr */
  11796         soc_block_list[73],
  11797         soc_genreg,
  11798         1,
  11799         0,
  11800         0x7f00,
  11801         0,
  11802         0,
  11803         1,
  11804         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASKr_fields,
  11805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11806         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11807         -1,
  11808         -1,
  11809     },
  11810 #endif /* chips */
  11811 
  11812 #if defined(BCM_88375_A0)
  11813     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASK_BCM88375_A0r */
  11814         soc_block_list[73],
  11815         soc_genreg,
  11816         1,
  11817         0,
  11818         0x7f00,
  11819         0,
  11820         0,
  11821         1,
  11822         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASK_BCM88375_A0r_fields,
  11823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11824         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11825         -1,
  11826         -1,
  11827     },
  11828 #endif /* chips */
  11829 
  11830 #if defined(BCM_88375_B0)
  11831     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASK_BCM88375_B0r */
  11832         soc_block_list[73],
  11833         soc_genreg,
  11834         1,
  11835         0,
  11836         0x7f00,
  11837         0,
  11838         0,
  11839         1,
  11840         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASK_BCM88375_B0r_fields,
  11841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11842         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11843         -1,
  11844         -1,
  11845     },
  11846 #endif /* chips */
  11847 
  11848 #if defined(BCM_88675_B0)
  11849     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASK_BCM88675_B0r */
  11850         soc_block_list[73],
  11851         soc_genreg,
  11852         1,
  11853         0,
  11854         0x7f00,
  11855         0,
  11856         0,
  11857         1,
  11858         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASK_BCM88675_B0r_fields,
  11859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11860         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11861         -1,
  11862         -1,
  11863     },
  11864 #endif /* chips */
  11865 
  11866 #if defined(BCM_88375_A0)
  11867     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_1_BCM88375_A0r */
  11868         soc_block_list[73],
  11869         soc_genreg,
  11870         1,
  11871         0,
  11872         0x7e00,
  11873         0,
  11874         0,
  11875         1,
  11876         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_1_BCM88375_A0r_fields,
  11877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11878         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11879         -1,
  11880         -1,
  11881     },
  11882 #endif /* chips */
  11883 
  11884 #if defined(BCM_88375_B0)
  11885     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_1_BCM88375_B0r */
  11886         soc_block_list[73],
  11887         soc_genreg,
  11888         1,
  11889         0,
  11890         0x7e00,
  11891         0,
  11892         0,
  11893         1,
  11894         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_1_BCM88375_B0r_fields,
  11895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11896         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11897         -1,
  11898         -1,
  11899     },
  11900 #endif /* chips */
  11901 
  11902 #if defined(BCM_88675_B0)
  11903     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_1_BCM88675_B0r */
  11904         soc_block_list[73],
  11905         soc_genreg,
  11906         1,
  11907         0,
  11908         0x7e00,
  11909         0,
  11910         0,
  11911         1,
  11912         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_1_BCM88675_B0r_fields,
  11913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11914         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11915         -1,
  11916         -1,
  11917     },
  11918 #endif /* chips */
  11919 
  11920 #if defined(BCM_88675_A0)
  11921     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASKr */
  11922         soc_block_list[73],
  11923         soc_genreg,
  11924         1,
  11925         0,
  11926         0x8000,
  11927         0,
  11928         0,
  11929         1,
  11930         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASKr_fields,
  11931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11932         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11933         -1,
  11934         -1,
  11935     },
  11936 #endif /* chips */
  11937 
  11938 #if defined(BCM_88375_A0)
  11939     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASK_BCM88375_A0r */
  11940         soc_block_list[73],
  11941         soc_genreg,
  11942         1,
  11943         0,
  11944         0x8000,
  11945         0,
  11946         0,
  11947         1,
  11948         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASK_BCM88375_A0r_fields,
  11949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11950         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11951         -1,
  11952         -1,
  11953     },
  11954 #endif /* chips */
  11955 
  11956 #if defined(BCM_88375_B0)
  11957     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASK_BCM88375_B0r */
  11958         soc_block_list[73],
  11959         soc_genreg,
  11960         1,
  11961         0,
  11962         0x8000,
  11963         0,
  11964         0,
  11965         1,
  11966         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASK_BCM88375_B0r_fields,
  11967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11968         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11969         -1,
  11970         -1,
  11971     },
  11972 #endif /* chips */
  11973 
  11974 #if defined(BCM_88675_B0)
  11975     { /* SOC_REG_INT_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASK_BCM88675_B0r */
  11976         soc_block_list[73],
  11977         soc_genreg,
  11978         1,
  11979         0,
  11980         0x8000,
  11981         0,
  11982         0,
  11983         1,
  11984         soc_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASK_BCM88675_B0r_fields,
  11985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11986         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11987         -1,
  11988         -1,
  11989     },
  11990 #endif /* chips */
  11991 
  11992 #if defined(BCM_88675_A0)
  11993     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUSr */
  11994         soc_block_list[73],
  11995         soc_genreg,
  11996         1,
  11997         0,
  11998         0x7800,
  11999         0,
  12000         0,
  12001         16,
  12002         soc_KAPS_R_5_DEBUG_STATUSr_fields,
  12003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12004         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12005         -1,
  12006         -1,
  12007     },
  12008 #endif /* chips */
  12009 
  12010 #if defined(BCM_88375_A0)
  12011     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_BCM88375_A0r */
  12012         soc_block_list[73],
  12013         soc_genreg,
  12014         1,
  12015         0,
  12016         0x7800,
  12017         0,
  12018         0,
  12019         16,
  12020         soc_KAPS_R_5_DEBUG_STATUS_BCM88375_A0r_fields,
  12021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12022         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12023         -1,
  12024         -1,
  12025     },
  12026 #endif /* chips */
  12027 
  12028 #if defined(BCM_88375_B0)
  12029     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_BCM88375_B0r */
  12030         soc_block_list[73],
  12031         soc_genreg,
  12032         1,
  12033         0,
  12034         0x7800,
  12035         0,
  12036         0,
  12037         16,
  12038         soc_KAPS_R_5_DEBUG_STATUS_BCM88375_B0r_fields,
  12039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12040         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12041         -1,
  12042         -1,
  12043     },
  12044 #endif /* chips */
  12045 
  12046 #if defined(BCM_88675_B0)
  12047     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_BCM88675_B0r */
  12048         soc_block_list[73],
  12049         soc_genreg,
  12050         1,
  12051         0,
  12052         0x7800,
  12053         0,
  12054         0,
  12055         16,
  12056         soc_KAPS_R_5_DEBUG_STATUS_BCM88675_B0r_fields,
  12057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12058         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12059         -1,
  12060         -1,
  12061     },
  12062 #endif /* chips */
  12063 
  12064 #if defined(BCM_88675_A0)
  12065     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0r */
  12066         soc_block_list[73],
  12067         soc_genreg,
  12068         1,
  12069         0,
  12070         0x7900,
  12071         0,
  12072         0,
  12073         32,
  12074         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0r_fields,
  12075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12076         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12077         -1,
  12078         -1,
  12079     },
  12080 #endif /* chips */
  12081 
  12082 #if defined(BCM_88675_A0)
  12083     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1r */
  12084         soc_block_list[73],
  12085         soc_genreg,
  12086         1,
  12087         0,
  12088         0x7b00,
  12089         0,
  12090         0,
  12091         23,
  12092         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1r_fields,
  12093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12094         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  12095         -1,
  12096         -1,
  12097     },
  12098 #endif /* chips */
  12099 
  12100 #if defined(BCM_88375_A0)
  12101     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_BCM88375_A0r */
  12102         soc_block_list[73],
  12103         soc_genreg,
  12104         1,
  12105         0,
  12106         0x7900,
  12107         0,
  12108         0,
  12109         32,
  12110         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_BCM88375_A0r_fields,
  12111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12112         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12113         -1,
  12114         -1,
  12115     },
  12116 #endif /* chips */
  12117 
  12118 #if defined(BCM_88375_B0)
  12119     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_BCM88375_B0r */
  12120         soc_block_list[73],
  12121         soc_genreg,
  12122         1,
  12123         0,
  12124         0x7900,
  12125         0,
  12126         0,
  12127         32,
  12128         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_BCM88375_B0r_fields,
  12129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12130         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12131         -1,
  12132         -1,
  12133     },
  12134 #endif /* chips */
  12135 
  12136 #if defined(BCM_88675_B0)
  12137     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_BCM88675_B0r */
  12138         soc_block_list[73],
  12139         soc_genreg,
  12140         1,
  12141         0,
  12142         0x7900,
  12143         0,
  12144         0,
  12145         32,
  12146         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_BCM88675_B0r_fields,
  12147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12149         -1,
  12150         -1,
  12151     },
  12152 #endif /* chips */
  12153 
  12154 #if defined(BCM_88675_A0)
  12155     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASKr */
  12156         soc_block_list[73],
  12157         soc_genreg,
  12158         1,
  12159         0,
  12160         0x7a00,
  12161         0,
  12162         0,
  12163         32,
  12164         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASKr_fields,
  12165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12166         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12167         -1,
  12168         -1,
  12169     },
  12170 #endif /* chips */
  12171 
  12172 #if defined(BCM_88375_A0)
  12173     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASK_BCM88375_A0r */
  12174         soc_block_list[73],
  12175         soc_genreg,
  12176         1,
  12177         0,
  12178         0x7a00,
  12179         0,
  12180         0,
  12181         32,
  12182         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASK_BCM88375_A0r_fields,
  12183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12184         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12185         -1,
  12186         -1,
  12187     },
  12188 #endif /* chips */
  12189 
  12190 #if defined(BCM_88375_B0)
  12191     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASK_BCM88375_B0r */
  12192         soc_block_list[73],
  12193         soc_genreg,
  12194         1,
  12195         0,
  12196         0x7a00,
  12197         0,
  12198         0,
  12199         32,
  12200         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASK_BCM88375_B0r_fields,
  12201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12202         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12203         -1,
  12204         -1,
  12205     },
  12206 #endif /* chips */
  12207 
  12208 #if defined(BCM_88675_B0)
  12209     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASK_BCM88675_B0r */
  12210         soc_block_list[73],
  12211         soc_genreg,
  12212         1,
  12213         0,
  12214         0x7a00,
  12215         0,
  12216         0,
  12217         32,
  12218         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASK_BCM88675_B0r_fields,
  12219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12220         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12221         -1,
  12222         -1,
  12223     },
  12224 #endif /* chips */
  12225 
  12226 #if defined(BCM_88375_A0)
  12227     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_BCM88375_A0r */
  12228         soc_block_list[73],
  12229         soc_genreg,
  12230         1,
  12231         0,
  12232         0x7b00,
  12233         0,
  12234         0,
  12235         23,
  12236         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_BCM88375_A0r_fields,
  12237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12238         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  12239         -1,
  12240         -1,
  12241     },
  12242 #endif /* chips */
  12243 
  12244 #if defined(BCM_88375_B0)
  12245     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_BCM88375_B0r */
  12246         soc_block_list[73],
  12247         soc_genreg,
  12248         1,
  12249         0,
  12250         0x7b00,
  12251         0,
  12252         0,
  12253         23,
  12254         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_BCM88375_B0r_fields,
  12255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12256         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  12257         -1,
  12258         -1,
  12259     },
  12260 #endif /* chips */
  12261 
  12262 #if defined(BCM_88675_B0)
  12263     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_BCM88675_B0r */
  12264         soc_block_list[73],
  12265         soc_genreg,
  12266         1,
  12267         0,
  12268         0x7b00,
  12269         0,
  12270         0,
  12271         23,
  12272         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_BCM88675_B0r_fields,
  12273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12274         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  12275         -1,
  12276         -1,
  12277     },
  12278 #endif /* chips */
  12279 
  12280 #if defined(BCM_88675_A0)
  12281     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASKr */
  12282         soc_block_list[73],
  12283         soc_genreg,
  12284         1,
  12285         0,
  12286         0x7c00,
  12287         0,
  12288         0,
  12289         23,
  12290         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASKr_fields,
  12291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12292         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  12293         -1,
  12294         -1,
  12295     },
  12296 #endif /* chips */
  12297 
  12298 #if defined(BCM_88375_A0)
  12299     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASK_BCM88375_A0r */
  12300         soc_block_list[73],
  12301         soc_genreg,
  12302         1,
  12303         0,
  12304         0x7c00,
  12305         0,
  12306         0,
  12307         23,
  12308         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASK_BCM88375_A0r_fields,
  12309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12310         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  12311         -1,
  12312         -1,
  12313     },
  12314 #endif /* chips */
  12315 
  12316 #if defined(BCM_88375_B0)
  12317     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASK_BCM88375_B0r */
  12318         soc_block_list[73],
  12319         soc_genreg,
  12320         1,
  12321         0,
  12322         0x7c00,
  12323         0,
  12324         0,
  12325         23,
  12326         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASK_BCM88375_B0r_fields,
  12327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12328         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  12329         -1,
  12330         -1,
  12331     },
  12332 #endif /* chips */
  12333 
  12334 #if defined(BCM_88675_B0)
  12335     { /* SOC_REG_INT_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASK_BCM88675_B0r */
  12336         soc_block_list[73],
  12337         soc_genreg,
  12338         1,
  12339         0,
  12340         0x7c00,
  12341         0,
  12342         0,
  12343         23,
  12344         soc_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASK_BCM88675_B0r_fields,
  12345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12346         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  12347         -1,
  12348         -1,
  12349     },
  12350 #endif /* chips */
  12351 
  12352 #if defined(BCM_88675_A0)
  12353     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_Ar */
  12354         soc_block_list[73],
  12355         soc_genreg,
  12356         1,
  12357         0,
  12358         0x6a00,
  12359         0,
  12360         0,
  12361         4,
  12362         soc_KAPS_R_5_ECC_ERR_RD_TCM_Ar_fields,
  12363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12364         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12365         -1,
  12366         -1,
  12367     },
  12368 #endif /* chips */
  12369 
  12370 #if defined(BCM_88375_A0)
  12371     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_A_BCM88375_A0r */
  12372         soc_block_list[73],
  12373         soc_genreg,
  12374         1,
  12375         0,
  12376         0x6a00,
  12377         0,
  12378         0,
  12379         4,
  12380         soc_KAPS_R_5_ECC_ERR_RD_TCM_A_BCM88375_A0r_fields,
  12381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12382         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12383         -1,
  12384         -1,
  12385     },
  12386 #endif /* chips */
  12387 
  12388 #if defined(BCM_88375_B0)
  12389     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_A_BCM88375_B0r */
  12390         soc_block_list[73],
  12391         soc_genreg,
  12392         1,
  12393         0,
  12394         0x6a00,
  12395         0,
  12396         0,
  12397         4,
  12398         soc_KAPS_R_5_ECC_ERR_RD_TCM_A_BCM88375_B0r_fields,
  12399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12400         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12401         -1,
  12402         -1,
  12403     },
  12404 #endif /* chips */
  12405 
  12406 #if defined(BCM_88675_B0)
  12407     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_A_BCM88675_B0r */
  12408         soc_block_list[73],
  12409         soc_genreg,
  12410         1,
  12411         0,
  12412         0x6a00,
  12413         0,
  12414         0,
  12415         4,
  12416         soc_KAPS_R_5_ECC_ERR_RD_TCM_A_BCM88675_B0r_fields,
  12417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12418         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12419         -1,
  12420         -1,
  12421     },
  12422 #endif /* chips */
  12423 
  12424 #if defined(BCM_88675_A0)
  12425     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_B_0r */
  12426         soc_block_list[73],
  12427         soc_genreg,
  12428         1,
  12429         0,
  12430         0x6b00,
  12431         0,
  12432         0,
  12433         4,
  12434         soc_KAPS_R_5_ECC_ERR_RD_TCM_B_0r_fields,
  12435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12436         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12437         -1,
  12438         -1,
  12439     },
  12440 #endif /* chips */
  12441 
  12442 #if defined(BCM_88675_A0)
  12443     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_B_1r */
  12444         soc_block_list[73],
  12445         soc_genreg,
  12446         1,
  12447         0,
  12448         0x6c00,
  12449         0,
  12450         0,
  12451         4,
  12452         soc_KAPS_R_5_ECC_ERR_RD_TCM_B_1r_fields,
  12453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12454         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12455         -1,
  12456         -1,
  12457     },
  12458 #endif /* chips */
  12459 
  12460 #if defined(BCM_88375_A0)
  12461     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_B_0_BCM88375_A0r */
  12462         soc_block_list[73],
  12463         soc_genreg,
  12464         1,
  12465         0,
  12466         0x6b00,
  12467         0,
  12468         0,
  12469         4,
  12470         soc_KAPS_R_5_ECC_ERR_RD_TCM_B_0_BCM88375_A0r_fields,
  12471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12472         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12473         -1,
  12474         -1,
  12475     },
  12476 #endif /* chips */
  12477 
  12478 #if defined(BCM_88375_B0)
  12479     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_B_0_BCM88375_B0r */
  12480         soc_block_list[73],
  12481         soc_genreg,
  12482         1,
  12483         0,
  12484         0x6b00,
  12485         0,
  12486         0,
  12487         4,
  12488         soc_KAPS_R_5_ECC_ERR_RD_TCM_B_0_BCM88375_B0r_fields,
  12489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12490         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12491         -1,
  12492         -1,
  12493     },
  12494 #endif /* chips */
  12495 
  12496 #if defined(BCM_88675_B0)
  12497     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_B_0_BCM88675_B0r */
  12498         soc_block_list[73],
  12499         soc_genreg,
  12500         1,
  12501         0,
  12502         0x6b00,
  12503         0,
  12504         0,
  12505         4,
  12506         soc_KAPS_R_5_ECC_ERR_RD_TCM_B_0_BCM88675_B0r_fields,
  12507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12508         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12509         -1,
  12510         -1,
  12511     },
  12512 #endif /* chips */
  12513 
  12514 #if defined(BCM_88375_A0)
  12515     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_B_1_BCM88375_A0r */
  12516         soc_block_list[73],
  12517         soc_genreg,
  12518         1,
  12519         0,
  12520         0x6c00,
  12521         0,
  12522         0,
  12523         4,
  12524         soc_KAPS_R_5_ECC_ERR_RD_TCM_B_1_BCM88375_A0r_fields,
  12525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12526         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12527         -1,
  12528         -1,
  12529     },
  12530 #endif /* chips */
  12531 
  12532 #if defined(BCM_88375_B0)
  12533     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_B_1_BCM88375_B0r */
  12534         soc_block_list[73],
  12535         soc_genreg,
  12536         1,
  12537         0,
  12538         0x6c00,
  12539         0,
  12540         0,
  12541         4,
  12542         soc_KAPS_R_5_ECC_ERR_RD_TCM_B_1_BCM88375_B0r_fields,
  12543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12544         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12545         -1,
  12546         -1,
  12547     },
  12548 #endif /* chips */
  12549 
  12550 #if defined(BCM_88675_B0)
  12551     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_RD_TCM_B_1_BCM88675_B0r */
  12552         soc_block_list[73],
  12553         soc_genreg,
  12554         1,
  12555         0,
  12556         0x6c00,
  12557         0,
  12558         0,
  12559         4,
  12560         soc_KAPS_R_5_ECC_ERR_RD_TCM_B_1_BCM88675_B0r_fields,
  12561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12562         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12563         -1,
  12564         -1,
  12565     },
  12566 #endif /* chips */
  12567 
  12568 #if defined(BCM_88675_A0)
  12569     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_Ar */
  12570         soc_block_list[73],
  12571         soc_genreg,
  12572         1,
  12573         0,
  12574         0x6700,
  12575         0,
  12576         0,
  12577         4,
  12578         soc_KAPS_R_5_ECC_ERR_WR_TCM_Ar_fields,
  12579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12580         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12581         -1,
  12582         -1,
  12583     },
  12584 #endif /* chips */
  12585 
  12586 #if defined(BCM_88375_A0)
  12587     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_A_BCM88375_A0r */
  12588         soc_block_list[73],
  12589         soc_genreg,
  12590         1,
  12591         0,
  12592         0x6700,
  12593         0,
  12594         0,
  12595         4,
  12596         soc_KAPS_R_5_ECC_ERR_WR_TCM_A_BCM88375_A0r_fields,
  12597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12598         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12599         -1,
  12600         -1,
  12601     },
  12602 #endif /* chips */
  12603 
  12604 #if defined(BCM_88375_B0)
  12605     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_A_BCM88375_B0r */
  12606         soc_block_list[73],
  12607         soc_genreg,
  12608         1,
  12609         0,
  12610         0x6700,
  12611         0,
  12612         0,
  12613         4,
  12614         soc_KAPS_R_5_ECC_ERR_WR_TCM_A_BCM88375_B0r_fields,
  12615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12616         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12617         -1,
  12618         -1,
  12619     },
  12620 #endif /* chips */
  12621 
  12622 #if defined(BCM_88675_B0)
  12623     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_A_BCM88675_B0r */
  12624         soc_block_list[73],
  12625         soc_genreg,
  12626         1,
  12627         0,
  12628         0x6700,
  12629         0,
  12630         0,
  12631         4,
  12632         soc_KAPS_R_5_ECC_ERR_WR_TCM_A_BCM88675_B0r_fields,
  12633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12634         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12635         -1,
  12636         -1,
  12637     },
  12638 #endif /* chips */
  12639 
  12640 #if defined(BCM_88675_A0)
  12641     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_B_0r */
  12642         soc_block_list[73],
  12643         soc_genreg,
  12644         1,
  12645         0,
  12646         0x6800,
  12647         0,
  12648         0,
  12649         4,
  12650         soc_KAPS_R_5_ECC_ERR_WR_TCM_B_0r_fields,
  12651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12652         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12653         -1,
  12654         -1,
  12655     },
  12656 #endif /* chips */
  12657 
  12658 #if defined(BCM_88675_A0)
  12659     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_B_1r */
  12660         soc_block_list[73],
  12661         soc_genreg,
  12662         1,
  12663         0,
  12664         0x6900,
  12665         0,
  12666         0,
  12667         4,
  12668         soc_KAPS_R_5_ECC_ERR_WR_TCM_B_1r_fields,
  12669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12670         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12671         -1,
  12672         -1,
  12673     },
  12674 #endif /* chips */
  12675 
  12676 #if defined(BCM_88375_A0)
  12677     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_B_0_BCM88375_A0r */
  12678         soc_block_list[73],
  12679         soc_genreg,
  12680         1,
  12681         0,
  12682         0x6800,
  12683         0,
  12684         0,
  12685         4,
  12686         soc_KAPS_R_5_ECC_ERR_WR_TCM_B_0_BCM88375_A0r_fields,
  12687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12688         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12689         -1,
  12690         -1,
  12691     },
  12692 #endif /* chips */
  12693 
  12694 #if defined(BCM_88375_B0)
  12695     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_B_0_BCM88375_B0r */
  12696         soc_block_list[73],
  12697         soc_genreg,
  12698         1,
  12699         0,
  12700         0x6800,
  12701         0,
  12702         0,
  12703         4,
  12704         soc_KAPS_R_5_ECC_ERR_WR_TCM_B_0_BCM88375_B0r_fields,
  12705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12706         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12707         -1,
  12708         -1,
  12709     },
  12710 #endif /* chips */
  12711 
  12712 #if defined(BCM_88675_B0)
  12713     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_B_0_BCM88675_B0r */
  12714         soc_block_list[73],
  12715         soc_genreg,
  12716         1,
  12717         0,
  12718         0x6800,
  12719         0,
  12720         0,
  12721         4,
  12722         soc_KAPS_R_5_ECC_ERR_WR_TCM_B_0_BCM88675_B0r_fields,
  12723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12724         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12725         -1,
  12726         -1,
  12727     },
  12728 #endif /* chips */
  12729 
  12730 #if defined(BCM_88375_A0)
  12731     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_B_1_BCM88375_A0r */
  12732         soc_block_list[73],
  12733         soc_genreg,
  12734         1,
  12735         0,
  12736         0x6900,
  12737         0,
  12738         0,
  12739         4,
  12740         soc_KAPS_R_5_ECC_ERR_WR_TCM_B_1_BCM88375_A0r_fields,
  12741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12742         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12743         -1,
  12744         -1,
  12745     },
  12746 #endif /* chips */
  12747 
  12748 #if defined(BCM_88375_B0)
  12749     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_B_1_BCM88375_B0r */
  12750         soc_block_list[73],
  12751         soc_genreg,
  12752         1,
  12753         0,
  12754         0x6900,
  12755         0,
  12756         0,
  12757         4,
  12758         soc_KAPS_R_5_ECC_ERR_WR_TCM_B_1_BCM88375_B0r_fields,
  12759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12760         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12761         -1,
  12762         -1,
  12763     },
  12764 #endif /* chips */
  12765 
  12766 #if defined(BCM_88675_B0)
  12767     { /* SOC_REG_INT_KAPS_R_5_ECC_ERR_WR_TCM_B_1_BCM88675_B0r */
  12768         soc_block_list[73],
  12769         soc_genreg,
  12770         1,
  12771         0,
  12772         0x6900,
  12773         0,
  12774         0,
  12775         4,
  12776         soc_KAPS_R_5_ECC_ERR_WR_TCM_B_1_BCM88675_B0r_fields,
  12777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12778         SOC_RESET_MASK_DEC(0xfffffff8, 0x00000000)
  12779         -1,
  12780         -1,
  12781     },
  12782 #endif /* chips */
  12783 
  12784 #if defined(BCM_88675_A0)
  12785     { /* SOC_REG_INT_KAPS_R_5_FIFO_MON_EVENTr */
  12786         soc_block_list[73],
  12787         soc_genreg,
  12788         1,
  12789         0,
  12790         0x500,
  12791         0,
  12792         0,
  12793         16,
  12794         soc_KAPS_R_5_FIFO_MON_EVENTr_fields,
  12795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12796         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12797         -1,
  12798         -1,
  12799     },
  12800 #endif /* chips */
  12801 
  12802 #if defined(BCM_88375_A0)
  12803     { /* SOC_REG_INT_KAPS_R_5_FIFO_MON_EVENT_BCM88375_A0r */
  12804         soc_block_list[73],
  12805         soc_genreg,
  12806         1,
  12807         0,
  12808         0x500,
  12809         0,
  12810         0,
  12811         16,
  12812         soc_KAPS_R_5_FIFO_MON_EVENT_BCM88375_A0r_fields,
  12813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12814         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12815         -1,
  12816         -1,
  12817     },
  12818 #endif /* chips */
  12819 
  12820 #if defined(BCM_88375_B0)
  12821     { /* SOC_REG_INT_KAPS_R_5_FIFO_MON_EVENT_BCM88375_B0r */
  12822         soc_block_list[73],
  12823         soc_genreg,
  12824         1,
  12825         0,
  12826         0x500,
  12827         0,
  12828         0,
  12829         16,
  12830         soc_KAPS_R_5_FIFO_MON_EVENT_BCM88375_B0r_fields,
  12831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12832         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12833         -1,
  12834         -1,
  12835     },
  12836 #endif /* chips */
  12837 
  12838 #if defined(BCM_88675_B0)
  12839     { /* SOC_REG_INT_KAPS_R_5_FIFO_MON_EVENT_BCM88675_B0r */
  12840         soc_block_list[73],
  12841         soc_genreg,
  12842         1,
  12843         0,
  12844         0x500,
  12845         0,
  12846         0,
  12847         16,
  12848         soc_KAPS_R_5_FIFO_MON_EVENT_BCM88675_B0r_fields,
  12849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12850         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12851         -1,
  12852         -1,
  12853     },
  12854 #endif /* chips */
  12855 
  12856 #if defined(BCM_88675_A0)
  12857     { /* SOC_REG_INT_KAPS_R_5_FIFO_MON_EVENT_MASKr */
  12858         soc_block_list[73],
  12859         soc_genreg,
  12860         1,
  12861         0,
  12862         0x600,
  12863         0,
  12864         0,
  12865         16,
  12866         soc_KAPS_R_5_FIFO_MON_EVENT_MASKr_fields,
  12867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12868         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12869         -1,
  12870         -1,
  12871     },
  12872 #endif /* chips */
  12873 
  12874 #if defined(BCM_88375_A0)
  12875     { /* SOC_REG_INT_KAPS_R_5_FIFO_MON_EVENT_MASK_BCM88375_A0r */
  12876         soc_block_list[73],
  12877         soc_genreg,
  12878         1,
  12879         0,
  12880         0x600,
  12881         0,
  12882         0,
  12883         16,
  12884         soc_KAPS_R_5_FIFO_MON_EVENT_MASK_BCM88375_A0r_fields,
  12885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12886         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12887         -1,
  12888         -1,
  12889     },
  12890 #endif /* chips */
  12891 
  12892 #if defined(BCM_88375_B0)
  12893     { /* SOC_REG_INT_KAPS_R_5_FIFO_MON_EVENT_MASK_BCM88375_B0r */
  12894         soc_block_list[73],
  12895         soc_genreg,
  12896         1,
  12897         0,
  12898         0x600,
  12899         0,
  12900         0,
  12901         16,
  12902         soc_KAPS_R_5_FIFO_MON_EVENT_MASK_BCM88375_B0r_fields,
  12903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12904         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12905         -1,
  12906         -1,
  12907     },
  12908 #endif /* chips */
  12909 
  12910 #if defined(BCM_88675_B0)
  12911     { /* SOC_REG_INT_KAPS_R_5_FIFO_MON_EVENT_MASK_BCM88675_B0r */
  12912         soc_block_list[73],
  12913         soc_genreg,
  12914         1,
  12915         0,
  12916         0x600,
  12917         0,
  12918         0,
  12919         16,
  12920         soc_KAPS_R_5_FIFO_MON_EVENT_MASK_BCM88675_B0r_fields,
  12921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12922         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12923         -1,
  12924         -1,
  12925     },
  12926 #endif /* chips */
  12927 
  12928 #if defined(BCM_88675_A0)
  12929     { /* SOC_REG_INT_KAPS_R_5_TM_TEST_CTRLr */
  12930         soc_block_list[73],
  12931         soc_genreg,
  12932         1,
  12933         0,
  12934         0x8600,
  12935         0,
  12936         0,
  12937         1,
  12938         soc_KAPS_R_5_TM_TEST_CTRLr_fields,
  12939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12940         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  12941         -1,
  12942         -1,
  12943     },
  12944 #endif /* chips */
  12945 
  12946 #if defined(BCM_88375_A0)
  12947     { /* SOC_REG_INT_KAPS_R_5_TM_TEST_CTRL_BCM88375_A0r */
  12948         soc_block_list[73],
  12949         soc_genreg,
  12950         1,
  12951         0,
  12952         0x8600,
  12953         0,
  12954         0,
  12955         1,
  12956         soc_KAPS_R_5_TM_TEST_CTRL_BCM88375_A0r_fields,
  12957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12958         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  12959         -1,
  12960         -1,
  12961     },
  12962 #endif /* chips */
  12963 
  12964 #if defined(BCM_88375_B0)
  12965     { /* SOC_REG_INT_KAPS_R_5_TM_TEST_CTRL_BCM88375_B0r */
  12966         soc_block_list[73],
  12967         soc_genreg,
  12968         1,
  12969         0,
  12970         0x8600,
  12971         0,
  12972         0,
  12973         1,
  12974         soc_KAPS_R_5_TM_TEST_CTRL_BCM88375_B0r_fields,
  12975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12976         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  12977         -1,
  12978         -1,
  12979     },
  12980 #endif /* chips */
  12981 
  12982 #if defined(BCM_88675_B0)
  12983     { /* SOC_REG_INT_KAPS_R_5_TM_TEST_CTRL_BCM88675_B0r */
  12984         soc_block_list[73],
  12985         soc_genreg,
  12986         1,
  12987         0,
  12988         0x8600,
  12989         0,
  12990         0,
  12991         1,
  12992         soc_KAPS_R_5_TM_TEST_CTRL_BCM88675_B0r_fields,
  12993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12994         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  12995         -1,
  12996         -1,
  12997     },
  12998 #endif /* chips */
  12999 
  13000 #if defined(BCM_88470_A0)
  13001     { /* SOC_REG_INT_KAPS_SBUS_BROADCAST_IDr */
  13002         soc_block_list[73],
  13003         soc_genreg,
  13004         1,
  13005         0,
  13006         0x86,
  13007         0,
  13008         0,
  13009         1,
  13010         soc_KAPS_SBUS_BROADCAST_IDr_fields,
  13011         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  13012         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  13013         -1,
  13014         -1,
  13015     },
  13016 #endif /* chips */
  13017 
  13018 #if defined(BCM_88270_A0)
  13019     { /* SOC_REG_INT_KAPS_SBUS_BROADCAST_ID_BCM88270_A0r */
  13020         soc_block_list[73],
  13021         soc_genreg,
  13022         1,
  13023         0,
  13024         0x86,
  13025         0,
  13026         0,
  13027         1,
  13028         soc_KAPS_SBUS_BROADCAST_ID_BCM88270_A0r_fields,
  13029         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  13030         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  13031         -1,
  13032         -1,
  13033     },
  13034 #endif /* chips */
  13035 
  13036 #if defined(BCM_88470_B0)
  13037     { /* SOC_REG_INT_KAPS_SBUS_BROADCAST_ID_BCM88470_B0r */
  13038         soc_block_list[73],
  13039         soc_genreg,
  13040         1,
  13041         0,
  13042         0x86,
  13043         0,
  13044         0,
  13045         1,
  13046         soc_KAPS_SBUS_BROADCAST_ID_BCM88470_B0r_fields,
  13047         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  13048         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  13049         -1,
  13050         -1,
  13051     },
  13052 #endif /* chips */
  13053 
  13054 #if defined(BCM_88680_A0)
  13055     { /* SOC_REG_INT_KAPS_SBUS_BROADCAST_ID_BCM88680_A0r */
  13056         soc_block_list[73],
  13057         soc_genreg,
  13058         1,
  13059         0,
  13060         0x86,
  13061         0,
  13062         0,
  13063         1,
  13064         soc_KAPS_SBUS_BROADCAST_ID_BCM88680_A0r_fields,
  13065         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  13066         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  13067         -1,
  13068         -1,
  13069     },
  13070 #endif /* chips */
  13071 
  13072 #if defined(BCM_88690_A0)
  13073     { /* SOC_REG_INT_KAPS_SBUS_BROADCAST_ID_BCM88690_A0r */
  13074         soc_block_list[73],
  13075         soc_genreg,
  13076         1,
  13077         0,
  13078         0x86,
  13079         0,
  13080         0,
  13081         1,
  13082         soc_KAPS_SBUS_BROADCAST_ID_BCM88690_A0r_fields,
  13083         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  13084         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13085         -1,
  13086         -1,
  13087     },
  13088 #endif /* chips */
  13089 
  13090 #if defined(BCM_88690_B0)
  13091     { /* SOC_REG_INT_KAPS_SBUS_BROADCAST_ID_BCM88690_B0r */
  13092         soc_block_list[73],
  13093         soc_genreg,
  13094         1,
  13095         0,
  13096         0x86,
  13097         0,
  13098         0,
  13099         1,
  13100         soc_KAPS_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
  13101         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  13102         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13103         -1,
  13104         -1,
  13105     },
  13106 #endif /* chips */
  13107 
  13108 #if defined(BCM_88470_A0)
  13109     { /* SOC_REG_INT_KAPS_SBUS_LAST_IN_CHAINr */
  13110         soc_block_list[73],
  13111         soc_genreg,
  13112         1,
  13113         0,
  13114         0x87,
  13115         0,
  13116         0,
  13117         1,
  13118         soc_KAPS_SBUS_LAST_IN_CHAINr_fields,
  13119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13120         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13121         -1,
  13122         -1,
  13123     },
  13124 #endif /* chips */
  13125 
  13126 #if defined(BCM_88270_A0)
  13127     { /* SOC_REG_INT_KAPS_SBUS_LAST_IN_CHAIN_BCM88270_A0r */
  13128         soc_block_list[73],
  13129         soc_genreg,
  13130         1,
  13131         0,
  13132         0x87,
  13133         0,
  13134         0,
  13135         1,
  13136         soc_KAPS_SBUS_LAST_IN_CHAIN_BCM88270_A0r_fields,
  13137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13138         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13139         -1,
  13140         -1,
  13141     },
  13142 #endif /* chips */
  13143 
  13144 #if defined(BCM_88470_B0)
  13145     { /* SOC_REG_INT_KAPS_SBUS_LAST_IN_CHAIN_BCM88470_B0r */
  13146         soc_block_list[73],
  13147         soc_genreg,
  13148         1,
  13149         0,
  13150         0x87,
  13151         0,
  13152         0,
  13153         1,
  13154         soc_KAPS_SBUS_LAST_IN_CHAIN_BCM88470_B0r_fields,
  13155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13156         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13157         -1,
  13158         -1,
  13159     },
  13160 #endif /* chips */
  13161 
  13162 #if defined(BCM_88680_A0)
  13163     { /* SOC_REG_INT_KAPS_SBUS_LAST_IN_CHAIN_BCM88680_A0r */
  13164         soc_block_list[73],
  13165         soc_genreg,
  13166         1,
  13167         0,
  13168         0x87,
  13169         0,
  13170         0,
  13171         1,
  13172         soc_KAPS_SBUS_LAST_IN_CHAIN_BCM88680_A0r_fields,
  13173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13174         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13175         -1,
  13176         -1,
  13177     },
  13178 #endif /* chips */
  13179 
  13180 #if defined(BCM_88690_A0)
  13181     { /* SOC_REG_INT_KAPS_SBUS_LAST_IN_CHAIN_BCM88690_A0r */
  13182         soc_block_list[73],
  13183         soc_genreg,
  13184         1,
  13185         0,
  13186         0x87,
  13187         0,
  13188         0,
  13189         1,
  13190         soc_KAPS_SBUS_LAST_IN_CHAIN_BCM88690_A0r_fields,
  13191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13192         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13193         -1,
  13194         -1,
  13195     },
  13196 #endif /* chips */
  13197 
  13198 #if defined(BCM_88690_B0)
  13199     { /* SOC_REG_INT_KAPS_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
  13200         soc_block_list[73],
  13201         soc_genreg,
  13202         1,
  13203         0,
  13204         0x87,
  13205         0,
  13206         0,
  13207         1,
  13208         soc_KAPS_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
  13209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13210         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13211         -1,
  13212         -1,
  13213     },
  13214 #endif /* chips */
  13215 
  13216 #if defined(BCM_88675_A0)
  13217     { /* SOC_REG_INT_KAPS_SEARCH_0A_ERRORr */
  13218         soc_block_list[73],
  13219         soc_genreg,
  13220         1,
  13221         0,
  13222         0x1d00,
  13223         0,
  13224         0,
  13225         3,
  13226         soc_KAPS_SEARCH_0A_ERRORr_fields,
  13227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13228         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13229         -1,
  13230         -1,
  13231     },
  13232 #endif /* chips */
  13233 
  13234 #if defined(BCM_88375_A0)
  13235     { /* SOC_REG_INT_KAPS_SEARCH_0A_ERROR_BCM88375_A0r */
  13236         soc_block_list[73],
  13237         soc_genreg,
  13238         1,
  13239         0,
  13240         0x1d00,
  13241         0,
  13242         0,
  13243         3,
  13244         soc_KAPS_SEARCH_0A_ERROR_BCM88375_A0r_fields,
  13245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13246         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13247         -1,
  13248         -1,
  13249     },
  13250 #endif /* chips */
  13251 
  13252 #if defined(BCM_88375_B0)
  13253     { /* SOC_REG_INT_KAPS_SEARCH_0A_ERROR_BCM88375_B0r */
  13254         soc_block_list[73],
  13255         soc_genreg,
  13256         1,
  13257         0,
  13258         0x1d00,
  13259         0,
  13260         0,
  13261         3,
  13262         soc_KAPS_SEARCH_0A_ERROR_BCM88375_B0r_fields,
  13263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13264         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13265         -1,
  13266         -1,
  13267     },
  13268 #endif /* chips */
  13269 
  13270 #if defined(BCM_88675_B0)
  13271     { /* SOC_REG_INT_KAPS_SEARCH_0A_ERROR_BCM88675_B0r */
  13272         soc_block_list[73],
  13273         soc_genreg,
  13274         1,
  13275         0,
  13276         0x1d00,
  13277         0,
  13278         0,
  13279         3,
  13280         soc_KAPS_SEARCH_0A_ERROR_BCM88675_B0r_fields,
  13281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13282         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13283         -1,
  13284         -1,
  13285     },
  13286 #endif /* chips */
  13287 
  13288 #if defined(BCM_88675_A0)
  13289     { /* SOC_REG_INT_KAPS_SEARCH_0A_ERROR_MASKr */
  13290         soc_block_list[73],
  13291         soc_genreg,
  13292         1,
  13293         0,
  13294         0x2000,
  13295         0,
  13296         0,
  13297         3,
  13298         soc_KAPS_SEARCH_0A_ERROR_MASKr_fields,
  13299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13300         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13301         -1,
  13302         -1,
  13303     },
  13304 #endif /* chips */
  13305 
  13306 #if defined(BCM_88375_A0)
  13307     { /* SOC_REG_INT_KAPS_SEARCH_0A_ERROR_MASK_BCM88375_A0r */
  13308         soc_block_list[73],
  13309         soc_genreg,
  13310         1,
  13311         0,
  13312         0x2000,
  13313         0,
  13314         0,
  13315         3,
  13316         soc_KAPS_SEARCH_0A_ERROR_MASK_BCM88375_A0r_fields,
  13317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13318         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13319         -1,
  13320         -1,
  13321     },
  13322 #endif /* chips */
  13323 
  13324 #if defined(BCM_88375_B0)
  13325     { /* SOC_REG_INT_KAPS_SEARCH_0A_ERROR_MASK_BCM88375_B0r */
  13326         soc_block_list[73],
  13327         soc_genreg,
  13328         1,
  13329         0,
  13330         0x2000,
  13331         0,
  13332         0,
  13333         3,
  13334         soc_KAPS_SEARCH_0A_ERROR_MASK_BCM88375_B0r_fields,
  13335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13336         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13337         -1,
  13338         -1,
  13339     },
  13340 #endif /* chips */
  13341 
  13342 #if defined(BCM_88675_B0)
  13343     { /* SOC_REG_INT_KAPS_SEARCH_0A_ERROR_MASK_BCM88675_B0r */
  13344         soc_block_list[73],
  13345         soc_genreg,
  13346         1,
  13347         0,
  13348         0x2000,
  13349         0,
  13350         0,
  13351         3,
  13352         soc_KAPS_SEARCH_0A_ERROR_MASK_BCM88675_B0r_fields,
  13353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13354         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13355         -1,
  13356         -1,
  13357     },
  13358 #endif /* chips */
  13359 
  13360 #if defined(BCM_88675_A0)
  13361     { /* SOC_REG_INT_KAPS_SEARCH_0B_ERRORr */
  13362         soc_block_list[73],
  13363         soc_genreg,
  13364         1,
  13365         0,
  13366         0x2300,
  13367         0,
  13368         0,
  13369         3,
  13370         soc_KAPS_SEARCH_0B_ERRORr_fields,
  13371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13372         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13373         -1,
  13374         -1,
  13375     },
  13376 #endif /* chips */
  13377 
  13378 #if defined(BCM_88375_A0)
  13379     { /* SOC_REG_INT_KAPS_SEARCH_0B_ERROR_BCM88375_A0r */
  13380         soc_block_list[73],
  13381         soc_genreg,
  13382         1,
  13383         0,
  13384         0x2300,
  13385         0,
  13386         0,
  13387         3,
  13388         soc_KAPS_SEARCH_0B_ERROR_BCM88375_A0r_fields,
  13389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13390         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13391         -1,
  13392         -1,
  13393     },
  13394 #endif /* chips */
  13395 
  13396 #if defined(BCM_88375_B0)
  13397     { /* SOC_REG_INT_KAPS_SEARCH_0B_ERROR_BCM88375_B0r */
  13398         soc_block_list[73],
  13399         soc_genreg,
  13400         1,
  13401         0,
  13402         0x2300,
  13403         0,
  13404         0,
  13405         3,
  13406         soc_KAPS_SEARCH_0B_ERROR_BCM88375_B0r_fields,
  13407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13408         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13409         -1,
  13410         -1,
  13411     },
  13412 #endif /* chips */
  13413 
  13414 #if defined(BCM_88675_B0)
  13415     { /* SOC_REG_INT_KAPS_SEARCH_0B_ERROR_BCM88675_B0r */
  13416         soc_block_list[73],
  13417         soc_genreg,
  13418         1,
  13419         0,
  13420         0x2300,
  13421         0,
  13422         0,
  13423         3,
  13424         soc_KAPS_SEARCH_0B_ERROR_BCM88675_B0r_fields,
  13425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13426         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13427         -1,
  13428         -1,
  13429     },
  13430 #endif /* chips */
  13431 
  13432 #if defined(BCM_88675_A0)
  13433     { /* SOC_REG_INT_KAPS_SEARCH_0B_ERROR_MASKr */
  13434         soc_block_list[73],
  13435         soc_genreg,
  13436         1,
  13437         0,
  13438         0x2400,
  13439         0,
  13440         0,
  13441         3,
  13442         soc_KAPS_SEARCH_0B_ERROR_MASKr_fields,
  13443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13444         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13445         -1,
  13446         -1,
  13447     },
  13448 #endif /* chips */
  13449 
  13450 #if defined(BCM_88375_A0)
  13451     { /* SOC_REG_INT_KAPS_SEARCH_0B_ERROR_MASK_BCM88375_A0r */
  13452         soc_block_list[73],
  13453         soc_genreg,
  13454         1,
  13455         0,
  13456         0x2400,
  13457         0,
  13458         0,
  13459         3,
  13460         soc_KAPS_SEARCH_0B_ERROR_MASK_BCM88375_A0r_fields,
  13461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13462         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13463         -1,
  13464         -1,
  13465     },
  13466 #endif /* chips */
  13467 
  13468 #if defined(BCM_88375_B0)
  13469     { /* SOC_REG_INT_KAPS_SEARCH_0B_ERROR_MASK_BCM88375_B0r */
  13470         soc_block_list[73],
  13471         soc_genreg,
  13472         1,
  13473         0,
  13474         0x2400,
  13475         0,
  13476         0,
  13477         3,
  13478         soc_KAPS_SEARCH_0B_ERROR_MASK_BCM88375_B0r_fields,
  13479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13480         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13481         -1,
  13482         -1,
  13483     },
  13484 #endif /* chips */
  13485 
  13486 #if defined(BCM_88675_B0)
  13487     { /* SOC_REG_INT_KAPS_SEARCH_0B_ERROR_MASK_BCM88675_B0r */
  13488         soc_block_list[73],
  13489         soc_genreg,
  13490         1,
  13491         0,
  13492         0x2400,
  13493         0,
  13494         0,
  13495         3,
  13496         soc_KAPS_SEARCH_0B_ERROR_MASK_BCM88675_B0r_fields,
  13497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13498         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13499         -1,
  13500         -1,
  13501     },
  13502 #endif /* chips */
  13503 
  13504 #if defined(BCM_88675_A0)
  13505     { /* SOC_REG_INT_KAPS_SEARCH_1A_ERRORr */
  13506         soc_block_list[73],
  13507         soc_genreg,
  13508         1,
  13509         0,
  13510         0x2100,
  13511         0,
  13512         0,
  13513         3,
  13514         soc_KAPS_SEARCH_1A_ERRORr_fields,
  13515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13516         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13517         -1,
  13518         -1,
  13519     },
  13520 #endif /* chips */
  13521 
  13522 #if defined(BCM_88375_A0)
  13523     { /* SOC_REG_INT_KAPS_SEARCH_1A_ERROR_BCM88375_A0r */
  13524         soc_block_list[73],
  13525         soc_genreg,
  13526         1,
  13527         0,
  13528         0x2100,
  13529         0,
  13530         0,
  13531         3,
  13532         soc_KAPS_SEARCH_1A_ERROR_BCM88375_A0r_fields,
  13533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13534         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13535         -1,
  13536         -1,
  13537     },
  13538 #endif /* chips */
  13539 
  13540 #if defined(BCM_88375_B0)
  13541     { /* SOC_REG_INT_KAPS_SEARCH_1A_ERROR_BCM88375_B0r */
  13542         soc_block_list[73],
  13543         soc_genreg,
  13544         1,
  13545         0,
  13546         0x2100,
  13547         0,
  13548         0,
  13549         3,
  13550         soc_KAPS_SEARCH_1A_ERROR_BCM88375_B0r_fields,
  13551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13552         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13553         -1,
  13554         -1,
  13555     },
  13556 #endif /* chips */
  13557 
  13558 #if defined(BCM_88675_B0)
  13559     { /* SOC_REG_INT_KAPS_SEARCH_1A_ERROR_BCM88675_B0r */
  13560         soc_block_list[73],
  13561         soc_genreg,
  13562         1,
  13563         0,
  13564         0x2100,
  13565         0,
  13566         0,
  13567         3,
  13568         soc_KAPS_SEARCH_1A_ERROR_BCM88675_B0r_fields,
  13569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13570         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13571         -1,
  13572         -1,
  13573     },
  13574 #endif /* chips */
  13575 
  13576 #if defined(BCM_88675_A0)
  13577     { /* SOC_REG_INT_KAPS_SEARCH_1A_ERROR_MASKr */
  13578         soc_block_list[73],
  13579         soc_genreg,
  13580         1,
  13581         0,
  13582         0x2200,
  13583         0,
  13584         0,
  13585         3,
  13586         soc_KAPS_SEARCH_1A_ERROR_MASKr_fields,
  13587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13588         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13589         -1,
  13590         -1,
  13591     },
  13592 #endif /* chips */
  13593 
  13594 #if defined(BCM_88375_A0)
  13595     { /* SOC_REG_INT_KAPS_SEARCH_1A_ERROR_MASK_BCM88375_A0r */
  13596         soc_block_list[73],
  13597         soc_genreg,
  13598         1,
  13599         0,
  13600         0x2200,
  13601         0,
  13602         0,
  13603         3,
  13604         soc_KAPS_SEARCH_1A_ERROR_MASK_BCM88375_A0r_fields,
  13605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13606         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13607         -1,
  13608         -1,
  13609     },
  13610 #endif /* chips */
  13611 
  13612 #if defined(BCM_88375_B0)
  13613     { /* SOC_REG_INT_KAPS_SEARCH_1A_ERROR_MASK_BCM88375_B0r */
  13614         soc_block_list[73],
  13615         soc_genreg,
  13616         1,
  13617         0,
  13618         0x2200,
  13619         0,
  13620         0,
  13621         3,
  13622         soc_KAPS_SEARCH_1A_ERROR_MASK_BCM88375_B0r_fields,
  13623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13624         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13625         -1,
  13626         -1,
  13627     },
  13628 #endif /* chips */
  13629 
  13630 #if defined(BCM_88675_B0)
  13631     { /* SOC_REG_INT_KAPS_SEARCH_1A_ERROR_MASK_BCM88675_B0r */
  13632         soc_block_list[73],
  13633         soc_genreg,
  13634         1,
  13635         0,
  13636         0x2200,
  13637         0,
  13638         0,
  13639         3,
  13640         soc_KAPS_SEARCH_1A_ERROR_MASK_BCM88675_B0r_fields,
  13641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13642         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13643         -1,
  13644         -1,
  13645     },
  13646 #endif /* chips */
  13647 
  13648 #if defined(BCM_88675_A0)
  13649     { /* SOC_REG_INT_KAPS_SEARCH_1B_ERRORr */
  13650         soc_block_list[73],
  13651         soc_genreg,
  13652         1,
  13653         0,
  13654         0x2500,
  13655         0,
  13656         0,
  13657         3,
  13658         soc_KAPS_SEARCH_1B_ERRORr_fields,
  13659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13660         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13661         -1,
  13662         -1,
  13663     },
  13664 #endif /* chips */
  13665 
  13666 #if defined(BCM_88375_A0)
  13667     { /* SOC_REG_INT_KAPS_SEARCH_1B_ERROR_BCM88375_A0r */
  13668         soc_block_list[73],
  13669         soc_genreg,
  13670         1,
  13671         0,
  13672         0x2500,
  13673         0,
  13674         0,
  13675         3,
  13676         soc_KAPS_SEARCH_1B_ERROR_BCM88375_A0r_fields,
  13677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13678         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13679         -1,
  13680         -1,
  13681     },
  13682 #endif /* chips */
  13683 
  13684 #if defined(BCM_88375_B0)
  13685     { /* SOC_REG_INT_KAPS_SEARCH_1B_ERROR_BCM88375_B0r */
  13686         soc_block_list[73],
  13687         soc_genreg,
  13688         1,
  13689         0,
  13690         0x2500,
  13691         0,
  13692         0,
  13693         3,
  13694         soc_KAPS_SEARCH_1B_ERROR_BCM88375_B0r_fields,
  13695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13696         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13697         -1,
  13698         -1,
  13699     },
  13700 #endif /* chips */
  13701 
  13702 #if defined(BCM_88675_B0)
  13703     { /* SOC_REG_INT_KAPS_SEARCH_1B_ERROR_BCM88675_B0r */
  13704         soc_block_list[73],
  13705         soc_genreg,
  13706         1,
  13707         0,
  13708         0x2500,
  13709         0,
  13710         0,
  13711         3,
  13712         soc_KAPS_SEARCH_1B_ERROR_BCM88675_B0r_fields,
  13713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13714         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13715         -1,
  13716         -1,
  13717     },
  13718 #endif /* chips */
  13719 
  13720 #if defined(BCM_88675_A0)
  13721     { /* SOC_REG_INT_KAPS_SEARCH_1B_ERROR_MASKr */
  13722         soc_block_list[73],
  13723         soc_genreg,
  13724         1,
  13725         0,
  13726         0x2600,
  13727         0,
  13728         0,
  13729         3,
  13730         soc_KAPS_SEARCH_1B_ERROR_MASKr_fields,
  13731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13732         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13733         -1,
  13734         -1,
  13735     },
  13736 #endif /* chips */
  13737 
  13738 #if defined(BCM_88375_A0)
  13739     { /* SOC_REG_INT_KAPS_SEARCH_1B_ERROR_MASK_BCM88375_A0r */
  13740         soc_block_list[73],
  13741         soc_genreg,
  13742         1,
  13743         0,
  13744         0x2600,
  13745         0,
  13746         0,
  13747         3,
  13748         soc_KAPS_SEARCH_1B_ERROR_MASK_BCM88375_A0r_fields,
  13749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13750         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13751         -1,
  13752         -1,
  13753     },
  13754 #endif /* chips */
  13755 
  13756 #if defined(BCM_88375_B0)
  13757     { /* SOC_REG_INT_KAPS_SEARCH_1B_ERROR_MASK_BCM88375_B0r */
  13758         soc_block_list[73],
  13759         soc_genreg,
  13760         1,
  13761         0,
  13762         0x2600,
  13763         0,
  13764         0,
  13765         3,
  13766         soc_KAPS_SEARCH_1B_ERROR_MASK_BCM88375_B0r_fields,
  13767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13768         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13769         -1,
  13770         -1,
  13771     },
  13772 #endif /* chips */
  13773 
  13774 #if defined(BCM_88675_B0)
  13775     { /* SOC_REG_INT_KAPS_SEARCH_1B_ERROR_MASK_BCM88675_B0r */
  13776         soc_block_list[73],
  13777         soc_genreg,
  13778         1,
  13779         0,
  13780         0x2600,
  13781         0,
  13782         0,
  13783         3,
  13784         soc_KAPS_SEARCH_1B_ERROR_MASK_BCM88675_B0r_fields,
  13785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13786         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13787         -1,
  13788         -1,
  13789     },
  13790 #endif /* chips */
  13791 
  13792 #if defined(BCM_88270_A0)
  13793     { /* SOC_REG_INT_KAPS_SINGLE_CMD_CNTr */
  13794         soc_block_list[73],
  13795         soc_genreg,
  13796         1,
  13797         0,
  13798         0x145,
  13799         SOC_REG_FLAG_RO,
  13800         0,
  13801         2,
  13802         soc_KAPS_SINGLE_CMD_CNTr_fields,
  13803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13804         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13805         -1,
  13806         -1,
  13807     },
  13808 #endif /* chips */
  13809 
  13810 #if defined(BCM_88680_A0)
  13811     { /* SOC_REG_INT_KAPS_SINGLE_CMD_CNT_BCM88680_A0r */
  13812         soc_block_list[73],
  13813         soc_genreg,
  13814         1,
  13815         0,
  13816         0x18b,
  13817         SOC_REG_FLAG_RO,
  13818         0,
  13819         2,
  13820         soc_KAPS_SINGLE_CMD_CNT_BCM88680_A0r_fields,
  13821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13822         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13823         -1,
  13824         -1,
  13825     },
  13826 #endif /* chips */
  13827 
  13828 #if defined(BCM_88675_A0)
  13829     { /* SOC_REG_INT_KAPS_STATUS_CFIFOr */
  13830         soc_block_list[73],
  13831         soc_genreg,
  13832         4,
  13833         0,
  13834         0x2f00,
  13835         SOC_REG_FLAG_ARRAY |
  13836                           SOC_REG_FLAG_RO |
  13837                           SOC_REG_FLAG_REG_ARRAY,
  13838         0,
  13839         2,
  13840         soc_KAPS_STATUS_CFIFOr_fields,
  13841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13842         SOC_RESET_MASK_DEC(0x0fff0fff, 0x00000000)
  13843         -1,
  13844         -1,
  13845     },
  13846 #endif /* chips */
  13847 
  13848 #if defined(BCM_88375_A0)
  13849     { /* SOC_REG_INT_KAPS_STATUS_CFIFO_BCM88375_A0r */
  13850         soc_block_list[73],
  13851         soc_genreg,
  13852         4,
  13853         0,
  13854         0x2f00,
  13855         SOC_REG_FLAG_ARRAY |
  13856                           SOC_REG_FLAG_RO |
  13857                           SOC_REG_FLAG_REG_ARRAY,
  13858         0,
  13859         2,
  13860         soc_KAPS_STATUS_CFIFO_BCM88375_A0r_fields,
  13861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13862         SOC_RESET_MASK_DEC(0x0fff0fff, 0x00000000)
  13863         -1,
  13864         -1,
  13865     },
  13866 #endif /* chips */
  13867 
  13868 #if defined(BCM_88375_B0)
  13869     { /* SOC_REG_INT_KAPS_STATUS_CFIFO_BCM88375_B0r */
  13870         soc_block_list[73],
  13871         soc_genreg,
  13872         4,
  13873         0,
  13874         0x2f00,
  13875         SOC_REG_FLAG_ARRAY |
  13876                           SOC_REG_FLAG_RO |
  13877                           SOC_REG_FLAG_REG_ARRAY,
  13878         0,
  13879         2,
  13880         soc_KAPS_STATUS_CFIFO_BCM88375_B0r_fields,
  13881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13882         SOC_RESET_MASK_DEC(0x0fff0fff, 0x00000000)
  13883         -1,
  13884         -1,
  13885     },
  13886 #endif /* chips */
  13887 
  13888 #if defined(BCM_88675_B0)
  13889     { /* SOC_REG_INT_KAPS_STATUS_CFIFO_BCM88675_B0r */
  13890         soc_block_list[73],
  13891         soc_genreg,
  13892         4,
  13893         0,
  13894         0x2f00,
  13895         SOC_REG_FLAG_ARRAY |
  13896                           SOC_REG_FLAG_RO |
  13897                           SOC_REG_FLAG_REG_ARRAY,
  13898         0,
  13899         2,
  13900         soc_KAPS_STATUS_CFIFO_BCM88675_B0r_fields,
  13901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13902         SOC_RESET_MASK_DEC(0x0fff0fff, 0x00000000)
  13903         -1,
  13904         -1,
  13905     },
  13906 #endif /* chips */
  13907 
  13908 #if defined(BCM_88675_A0)
  13909     { /* SOC_REG_INT_KAPS_STATUS_RFIFOr */
  13910         soc_block_list[73],
  13911         soc_genreg,
  13912         4,
  13913         0,
  13914         0x3700,
  13915         SOC_REG_FLAG_ARRAY |
  13916                           SOC_REG_FLAG_RO |
  13917                           SOC_REG_FLAG_REG_ARRAY,
  13918         0,
  13919         2,
  13920         soc_KAPS_STATUS_RFIFOr_fields,
  13921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13922         SOC_RESET_MASK_DEC(0x0fff0fff, 0x00000000)
  13923         -1,
  13924         -1,
  13925     },
  13926 #endif /* chips */
  13927 
  13928 #if defined(BCM_88375_A0)
  13929     { /* SOC_REG_INT_KAPS_STATUS_RFIFO_BCM88375_A0r */
  13930         soc_block_list[73],
  13931         soc_genreg,
  13932         4,
  13933         0,
  13934         0x3700,
  13935         SOC_REG_FLAG_ARRAY |
  13936                           SOC_REG_FLAG_RO |
  13937                           SOC_REG_FLAG_REG_ARRAY,
  13938         0,
  13939         2,
  13940         soc_KAPS_STATUS_RFIFO_BCM88375_A0r_fields,
  13941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13942         SOC_RESET_MASK_DEC(0x0fff0fff, 0x00000000)
  13943         -1,
  13944         -1,
  13945     },
  13946 #endif /* chips */
  13947 
  13948 #if defined(BCM_88375_B0)
  13949     { /* SOC_REG_INT_KAPS_STATUS_RFIFO_BCM88375_B0r */
  13950         soc_block_list[73],
  13951         soc_genreg,
  13952         4,
  13953         0,
  13954         0x3700,
  13955         SOC_REG_FLAG_ARRAY |
  13956                           SOC_REG_FLAG_RO |
  13957                           SOC_REG_FLAG_REG_ARRAY,
  13958         0,
  13959         2,
  13960         soc_KAPS_STATUS_RFIFO_BCM88375_B0r_fields,
  13961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13962         SOC_RESET_MASK_DEC(0x0fff0fff, 0x00000000)
  13963         -1,
  13964         -1,
  13965     },
  13966 #endif /* chips */
  13967 
  13968 #if defined(BCM_88675_B0)
  13969     { /* SOC_REG_INT_KAPS_STATUS_RFIFO_BCM88675_B0r */
  13970         soc_block_list[73],
  13971         soc_genreg,
  13972         4,
  13973         0,
  13974         0x3700,
  13975         SOC_REG_FLAG_ARRAY |
  13976                           SOC_REG_FLAG_RO |
  13977                           SOC_REG_FLAG_REG_ARRAY,
  13978         0,
  13979         2,
  13980         soc_KAPS_STATUS_RFIFO_BCM88675_B0r_fields,
  13981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13982         SOC_RESET_MASK_DEC(0x0fff0fff, 0x00000000)
  13983         -1,
  13984         -1,
  13985     },
  13986 #endif /* chips */
  13987 
  13988 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  13989     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASKr */
  13990         soc_block_list[5],
  13991         soc_portreg,
  13992         1,
  13993         0,
  13994         0xf000049,
  13995         0,
  13996         0,
  13997         1,
  13998         soc_BCAST_BLOCK_MASKr_fields,
  13999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14000         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  14001         -1,
  14002         -1,
  14003     },
  14004 #endif /* chips */
  14005 
  14006 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  14007     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  14008     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_64r */
  14009         soc_block_list[5],
  14010         soc_portreg,
  14011         1,
  14012         0,
  14013         0x11000049,
  14014         SOC_REG_FLAG_64_BITS,
  14015         0,
  14016         3,
  14017         soc_IKNOWN_MCAST_BLOCK_MASK_64r_fields,
  14018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14019         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  14020         -1,
  14021         -1,
  14022     },
  14023 #endif /* chips */
  14024 
  14025 #if defined(BCM_53400_A0)
  14026     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_64_BCM53400_A0r */
  14027         soc_block_list[5],
  14028         soc_portreg,
  14029         1,
  14030         0,
  14031         0x40001200,
  14032         0,
  14033         0,
  14034         2,
  14035         soc_IKNOWN_MCAST_BLOCK_MASK_64_BCM53400_A0r_fields,
  14036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14037         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14038         -1,
  14039         -1,
  14040     },
  14041 #endif /* chips */
  14042 
  14043 #if defined(BCM_56142_A0)
  14044     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_64_BCM56142_A0r */
  14045         soc_block_list[5],
  14046         soc_portreg,
  14047         1,
  14048         0,
  14049         0x11000069,
  14050         0,
  14051         0,
  14052         2,
  14053         soc_IKNOWN_MCAST_BLOCK_MASK_64_BCM56334_A0r_fields,
  14054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14055         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  14056         -1,
  14057         -1,
  14058     },
  14059 #endif /* chips */
  14060 
  14061 #if defined(BCM_56150_A0)
  14062     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_64_BCM56150_A0r */
  14063         soc_block_list[5],
  14064         soc_portreg,
  14065         1,
  14066         0,
  14067         0x44001200,
  14068         0,
  14069         0,
  14070         2,
  14071         soc_IKNOWN_MCAST_BLOCK_MASK_64_BCM56150_A0r_fields,
  14072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14073         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14074         -1,
  14075         -1,
  14076     },
  14077 #endif /* chips */
  14078 
  14079 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  14080     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_64_BCM56160_A0r */
  14081         soc_block_list[5],
  14082         soc_portreg,
  14083         1,
  14084         0,
  14085         0x40001200,
  14086         0,
  14087         0,
  14088         2,
  14089         soc_IKNOWN_MCAST_BLOCK_MASK_64_BCM56160_A0r_fields,
  14090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14092         -1,
  14093         -1,
  14094     },
  14095 #endif /* chips */
  14096 
  14097 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  14098     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_64_BCM56334_A0r */
  14099         soc_block_list[5],
  14100         soc_portreg,
  14101         1,
  14102         0,
  14103         0x11000049,
  14104         0,
  14105         0,
  14106         2,
  14107         soc_IKNOWN_MCAST_BLOCK_MASK_64_BCM56334_A0r_fields,
  14108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14109         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  14110         -1,
  14111         -1,
  14112     },
  14113 #endif /* chips */
  14114 
  14115 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  14116     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  14117     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  14118     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_64_BCM56634_A0r */
  14119         soc_block_list[5],
  14120         soc_portreg,
  14121         1,
  14122         0,
  14123         0xe000049,
  14124         SOC_REG_FLAG_64_BITS,
  14125         0,
  14126         4,
  14127         soc_IKNOWN_MCAST_BLOCK_MASK_64_BCM56634_A0r_fields,
  14128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14129         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  14130         -1,
  14131         -1,
  14132     },
  14133 #endif /* chips */
  14134 
  14135 #if defined(BCM_53570_A0)
  14136     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_HIr */
  14137         soc_block_list[5],
  14138         soc_portreg,
  14139         1,
  14140         0,
  14141         0x40003d00,
  14142         SOC_REG_FLAG_64_BITS,
  14143         0,
  14144         5,
  14145         soc_IKNOWN_MCAST_BLOCK_MASK_HIr_fields,
  14146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14147         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14148         -1,
  14149         -1,
  14150     },
  14151 #endif /* chips */
  14152 
  14153 #if defined(BCM_53570_B0)
  14154     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_HI_BCM53570_B0r */
  14155         soc_block_list[5],
  14156         soc_portreg,
  14157         1,
  14158         0,
  14159         0x40004100,
  14160         SOC_REG_FLAG_64_BITS,
  14161         0,
  14162         5,
  14163         soc_IKNOWN_MCAST_BLOCK_MASK_HIr_fields,
  14164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14165         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14166         -1,
  14167         -1,
  14168     },
  14169 #endif /* chips */
  14170 
  14171 #if defined(BCM_53570_A0)
  14172     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_LOr */
  14173         soc_block_list[5],
  14174         soc_portreg,
  14175         1,
  14176         0,
  14177         0x40003c00,
  14178         SOC_REG_FLAG_64_BITS,
  14179         0,
  14180         4,
  14181         soc_IKNOWN_MCAST_BLOCK_MASK_LOr_fields,
  14182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14183         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14184         -1,
  14185         -1,
  14186     },
  14187 #endif /* chips */
  14188 
  14189 #if defined(BCM_53570_B0)
  14190     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_LO_BCM53570_B0r */
  14191         soc_block_list[5],
  14192         soc_portreg,
  14193         1,
  14194         0,
  14195         0x40004000,
  14196         SOC_REG_FLAG_64_BITS,
  14197         0,
  14198         4,
  14199         soc_IKNOWN_MCAST_BLOCK_MASK_LOr_fields,
  14200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14201         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14202         -1,
  14203         -1,
  14204     },
  14205 #endif /* chips */
  14206 
  14207 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  14208     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  14209     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  14210     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr */
  14211         soc_block_list[5],
  14212         soc_genreg,
  14213         1,
  14214         0,
  14215         0xe080297,
  14216         0,
  14217         0,
  14218         1,
  14219         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  14220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14221         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  14222         -1,
  14223         -1,
  14224     },
  14225 #endif /* chips */
  14226 
  14227 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  14228     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56260_A0r */
  14229         soc_block_list[5],
  14230         soc_genreg,
  14231         1,
  14232         0,
  14233         0x3e016700,
  14234         0,
  14235         0,
  14236         1,
  14237         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  14238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14239         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14240         -1,
  14241         -1,
  14242     },
  14243 #endif /* chips */
  14244 
  14245 #if defined(BCM_56270_A0)
  14246     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56270_A0r */
  14247         soc_block_list[5],
  14248         soc_genreg,
  14249         1,
  14250         0,
  14251         0x3e015700,
  14252         0,
  14253         0,
  14254         1,
  14255         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  14256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14257         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14258         -1,
  14259         -1,
  14260     },
  14261 #endif /* chips */
  14262 
  14263 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  14264     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56440_A0r */
  14265         soc_block_list[5],
  14266         soc_genreg,
  14267         1,
  14268         0,
  14269         0xf080d66,
  14270         0,
  14271         0,
  14272         1,
  14273         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  14274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14275         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14276         -1,
  14277         -1,
  14278     },
  14279 #endif /* chips */
  14280 
  14281 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14282     defined(BCM_56450_B1)
  14283     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56450_A0r */
  14284         soc_block_list[5],
  14285         soc_genreg,
  14286         1,
  14287         0,
  14288         0x3e016600,
  14289         0,
  14290         0,
  14291         1,
  14292         soc_FT_CNTR_SER_CONTROLr_fields,
  14293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14294         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14295         -1,
  14296         -1,
  14297     },
  14298 #endif /* chips */
  14299 
  14300 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  14301     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56840_A0r */
  14302         soc_block_list[5],
  14303         soc_genreg,
  14304         1,
  14305         0,
  14306         0xf080d67,
  14307         0,
  14308         0,
  14309         1,
  14310         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  14311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14312         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14313         -1,
  14314         -1,
  14315     },
  14316 #endif /* chips */
  14317 
  14318 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  14319     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  14320     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  14321     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTRr */
  14322         soc_block_list[5],
  14323         soc_genreg,
  14324         1,
  14325         0,
  14326         0xe080298,
  14327         0,
  14328         0,
  14329         3,
  14330         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  14331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14332         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14333         -1,
  14334         -1,
  14335     },
  14336 #endif /* chips */
  14337 
  14338 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  14339     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56440_A0r */
  14340         soc_block_list[5],
  14341         soc_genreg,
  14342         1,
  14343         0,
  14344         0xf080d67,
  14345         0,
  14346         0,
  14347         3,
  14348         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  14349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14351         -1,
  14352         -1,
  14353     },
  14354 #endif /* chips */
  14355 
  14356 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14357     defined(BCM_56450_B1)
  14358     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56450_A0r */
  14359         soc_block_list[5],
  14360         soc_genreg,
  14361         1,
  14362         0,
  14363         0x3e016700,
  14364         0,
  14365         0,
  14366         3,
  14367         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  14368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14370         -1,
  14371         -1,
  14372     },
  14373 #endif /* chips */
  14374 
  14375 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  14376     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r */
  14377         soc_block_list[5],
  14378         soc_genreg,
  14379         1,
  14380         0,
  14381         0xf080d68,
  14382         0,
  14383         0,
  14384         3,
  14385         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  14386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14387         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14388         -1,
  14389         -1,
  14390     },
  14391 #endif /* chips */
  14392 
  14393 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  14394     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  14395     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  14396     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACKr */
  14397         soc_block_list[5],
  14398         soc_genreg,
  14399         1,
  14400         0,
  14401         0xe080299,
  14402         0,
  14403         0,
  14404         3,
  14405         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  14406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14407         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14408         -1,
  14409         -1,
  14410     },
  14411 #endif /* chips */
  14412 
  14413 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  14414     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56440_A0r */
  14415         soc_block_list[5],
  14416         soc_genreg,
  14417         1,
  14418         0,
  14419         0xf080d68,
  14420         0,
  14421         0,
  14422         3,
  14423         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  14424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14426         -1,
  14427         -1,
  14428     },
  14429 #endif /* chips */
  14430 
  14431 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14432     defined(BCM_56450_B1)
  14433     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56450_A0r */
  14434         soc_block_list[5],
  14435         soc_genreg,
  14436         1,
  14437         0,
  14438         0x3e016800,
  14439         0,
  14440         0,
  14441         3,
  14442         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  14443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14444         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14445         -1,
  14446         -1,
  14447     },
  14448 #endif /* chips */
  14449 
  14450 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  14451     { /* SOC_REG_INT_KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56840_A0r */
  14452         soc_block_list[5],
  14453         soc_genreg,
  14454         1,
  14455         0,
  14456         0xf080d69,
  14457         0,
  14458         0,
  14459         3,
  14460         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  14461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14462         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14463         -1,
  14464         -1,
  14465     },
  14466 #endif /* chips */
  14467
	openbcm Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM
	git clone git://git.finwo.net/mirror/broadcom/openbcm
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