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allregs_j.i (312337B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_j.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
     16     { /* SOC_REG_INT_JBCASCFG_CHID_0r */
     17         soc_block_list[81],
     18         soc_genreg,
     19         1,
     20         0,
     21         0x80960,
     22         0,
     23         0,
     24         2,
     25         soc_JBCASCFG_CHID_0r_fields,
     26         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     27         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     28         -1,
     29         -1,
     30     },
     31 #endif /* chips */
     32 
     33 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
     34     { /* SOC_REG_INT_JBCASCFG_CHID_1r */
     35         soc_block_list[81],
     36         soc_genreg,
     37         1,
     38         0,
     39         0x81960,
     40         0,
     41         0,
     42         2,
     43         soc_JBCASCFG_CHID_0r_fields,
     44         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     45         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     46         -1,
     47         -1,
     48     },
     49 #endif /* chips */
     50 
     51 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
     52     { /* SOC_REG_INT_JBCASCFG_CHID_2r */
     53         soc_block_list[81],
     54         soc_genreg,
     55         1,
     56         0,
     57         0x82960,
     58         0,
     59         0,
     60         2,
     61         soc_JBCASCFG_CHID_0r_fields,
     62         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     63         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     64         -1,
     65         -1,
     66     },
     67 #endif /* chips */
     68 
     69 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
     70     { /* SOC_REG_INT_JBCASCFG_CHID_3r */
     71         soc_block_list[81],
     72         soc_genreg,
     73         1,
     74         0,
     75         0x83960,
     76         0,
     77         0,
     78         2,
     79         soc_JBCASCFG_CHID_0r_fields,
     80         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     81         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     82         -1,
     83         -1,
     84     },
     85 #endif /* chips */
     86 
     87 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
     88     { /* SOC_REG_INT_JBCASCFG_CHID_4r */
     89         soc_block_list[81],
     90         soc_genreg,
     91         1,
     92         0,
     93         0x84960,
     94         0,
     95         0,
     96         2,
     97         soc_JBCASCFG_CHID_0r_fields,
     98         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     99         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    100         -1,
    101         -1,
    102     },
    103 #endif /* chips */
    104 
    105 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    106     { /* SOC_REG_INT_JBCASCFG_CHID_5r */
    107         soc_block_list[81],
    108         soc_genreg,
    109         1,
    110         0,
    111         0x85960,
    112         0,
    113         0,
    114         2,
    115         soc_JBCASCFG_CHID_0r_fields,
    116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    118         -1,
    119         -1,
    120     },
    121 #endif /* chips */
    122 
    123 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    124     { /* SOC_REG_INT_JBCASCFG_CHID_6r */
    125         soc_block_list[81],
    126         soc_genreg,
    127         1,
    128         0,
    129         0x86960,
    130         0,
    131         0,
    132         2,
    133         soc_JBCASCFG_CHID_0r_fields,
    134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    136         -1,
    137         -1,
    138     },
    139 #endif /* chips */
    140 
    141 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    142     { /* SOC_REG_INT_JBCASCFG_CHID_7r */
    143         soc_block_list[81],
    144         soc_genreg,
    145         1,
    146         0,
    147         0x87960,
    148         0,
    149         0,
    150         2,
    151         soc_JBCASCFG_CHID_0r_fields,
    152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    153         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    154         -1,
    155         -1,
    156     },
    157 #endif /* chips */
    158 
    159 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    160     { /* SOC_REG_INT_JBCASCFG_CHID_8r */
    161         soc_block_list[81],
    162         soc_genreg,
    163         1,
    164         0,
    165         0x88960,
    166         0,
    167         0,
    168         2,
    169         soc_JBCASCFG_CHID_0r_fields,
    170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    171         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    172         -1,
    173         -1,
    174     },
    175 #endif /* chips */
    176 
    177 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    178     { /* SOC_REG_INT_JBCASCFG_CHID_9r */
    179         soc_block_list[81],
    180         soc_genreg,
    181         1,
    182         0,
    183         0x89960,
    184         0,
    185         0,
    186         2,
    187         soc_JBCASCFG_CHID_0r_fields,
    188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    189         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    190         -1,
    191         -1,
    192     },
    193 #endif /* chips */
    194 
    195 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    196     { /* SOC_REG_INT_JBCASCFG_CHID_10r */
    197         soc_block_list[81],
    198         soc_genreg,
    199         1,
    200         0,
    201         0x8a960,
    202         0,
    203         0,
    204         2,
    205         soc_JBCASCFG_CHID_0r_fields,
    206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    207         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    208         -1,
    209         -1,
    210     },
    211 #endif /* chips */
    212 
    213 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    214     { /* SOC_REG_INT_JBCASCFG_CHID_11r */
    215         soc_block_list[81],
    216         soc_genreg,
    217         1,
    218         0,
    219         0x8b960,
    220         0,
    221         0,
    222         2,
    223         soc_JBCASCFG_CHID_0r_fields,
    224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    225         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    226         -1,
    227         -1,
    228     },
    229 #endif /* chips */
    230 
    231 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    232     { /* SOC_REG_INT_JBCASCFG_CHID_12r */
    233         soc_block_list[81],
    234         soc_genreg,
    235         1,
    236         0,
    237         0x8c960,
    238         0,
    239         0,
    240         2,
    241         soc_JBCASCFG_CHID_0r_fields,
    242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    243         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    244         -1,
    245         -1,
    246     },
    247 #endif /* chips */
    248 
    249 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    250     { /* SOC_REG_INT_JBCASCFG_CHID_13r */
    251         soc_block_list[81],
    252         soc_genreg,
    253         1,
    254         0,
    255         0x8d960,
    256         0,
    257         0,
    258         2,
    259         soc_JBCASCFG_CHID_0r_fields,
    260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    261         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    262         -1,
    263         -1,
    264     },
    265 #endif /* chips */
    266 
    267 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    268     { /* SOC_REG_INT_JBCASCFG_CHID_14r */
    269         soc_block_list[81],
    270         soc_genreg,
    271         1,
    272         0,
    273         0x8e960,
    274         0,
    275         0,
    276         2,
    277         soc_JBCASCFG_CHID_0r_fields,
    278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    279         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    280         -1,
    281         -1,
    282     },
    283 #endif /* chips */
    284 
    285 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    286     { /* SOC_REG_INT_JBCASCFG_CHID_15r */
    287         soc_block_list[81],
    288         soc_genreg,
    289         1,
    290         0,
    291         0x8f960,
    292         0,
    293         0,
    294         2,
    295         soc_JBCASCFG_CHID_0r_fields,
    296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    297         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    298         -1,
    299         -1,
    300     },
    301 #endif /* chips */
    302 
    303 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    304     { /* SOC_REG_INT_JBCASCFG_CHID_16r */
    305         soc_block_list[81],
    306         soc_genreg,
    307         1,
    308         0,
    309         0x90960,
    310         0,
    311         0,
    312         2,
    313         soc_JBCASCFG_CHID_0r_fields,
    314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    315         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    316         -1,
    317         -1,
    318     },
    319 #endif /* chips */
    320 
    321 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    322     { /* SOC_REG_INT_JBCASCFG_CHID_17r */
    323         soc_block_list[81],
    324         soc_genreg,
    325         1,
    326         0,
    327         0x91960,
    328         0,
    329         0,
    330         2,
    331         soc_JBCASCFG_CHID_0r_fields,
    332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    334         -1,
    335         -1,
    336     },
    337 #endif /* chips */
    338 
    339 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    340     { /* SOC_REG_INT_JBCASCFG_CHID_18r */
    341         soc_block_list[81],
    342         soc_genreg,
    343         1,
    344         0,
    345         0x92960,
    346         0,
    347         0,
    348         2,
    349         soc_JBCASCFG_CHID_0r_fields,
    350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    351         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    352         -1,
    353         -1,
    354     },
    355 #endif /* chips */
    356 
    357 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    358     { /* SOC_REG_INT_JBCASCFG_CHID_19r */
    359         soc_block_list[81],
    360         soc_genreg,
    361         1,
    362         0,
    363         0x93960,
    364         0,
    365         0,
    366         2,
    367         soc_JBCASCFG_CHID_0r_fields,
    368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    370         -1,
    371         -1,
    372     },
    373 #endif /* chips */
    374 
    375 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    376     { /* SOC_REG_INT_JBCASCFG_CHID_20r */
    377         soc_block_list[81],
    378         soc_genreg,
    379         1,
    380         0,
    381         0x94960,
    382         0,
    383         0,
    384         2,
    385         soc_JBCASCFG_CHID_0r_fields,
    386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    387         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    388         -1,
    389         -1,
    390     },
    391 #endif /* chips */
    392 
    393 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    394     { /* SOC_REG_INT_JBCASCFG_CHID_21r */
    395         soc_block_list[81],
    396         soc_genreg,
    397         1,
    398         0,
    399         0x95960,
    400         0,
    401         0,
    402         2,
    403         soc_JBCASCFG_CHID_0r_fields,
    404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    405         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    406         -1,
    407         -1,
    408     },
    409 #endif /* chips */
    410 
    411 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    412     { /* SOC_REG_INT_JBCASCFG_CHID_22r */
    413         soc_block_list[81],
    414         soc_genreg,
    415         1,
    416         0,
    417         0x96960,
    418         0,
    419         0,
    420         2,
    421         soc_JBCASCFG_CHID_0r_fields,
    422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    423         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    424         -1,
    425         -1,
    426     },
    427 #endif /* chips */
    428 
    429 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    430     { /* SOC_REG_INT_JBCASCFG_CHID_23r */
    431         soc_block_list[81],
    432         soc_genreg,
    433         1,
    434         0,
    435         0x97960,
    436         0,
    437         0,
    438         2,
    439         soc_JBCASCFG_CHID_0r_fields,
    440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    441         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    442         -1,
    443         -1,
    444     },
    445 #endif /* chips */
    446 
    447 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    448     { /* SOC_REG_INT_JBCASCFG_CHID_24r */
    449         soc_block_list[81],
    450         soc_genreg,
    451         1,
    452         0,
    453         0x98960,
    454         0,
    455         0,
    456         2,
    457         soc_JBCASCFG_CHID_0r_fields,
    458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    459         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    460         -1,
    461         -1,
    462     },
    463 #endif /* chips */
    464 
    465 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    466     { /* SOC_REG_INT_JBCASCFG_CHID_25r */
    467         soc_block_list[81],
    468         soc_genreg,
    469         1,
    470         0,
    471         0x99960,
    472         0,
    473         0,
    474         2,
    475         soc_JBCASCFG_CHID_0r_fields,
    476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    477         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    478         -1,
    479         -1,
    480     },
    481 #endif /* chips */
    482 
    483 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    484     { /* SOC_REG_INT_JBCASCFG_CHID_26r */
    485         soc_block_list[81],
    486         soc_genreg,
    487         1,
    488         0,
    489         0x9a960,
    490         0,
    491         0,
    492         2,
    493         soc_JBCASCFG_CHID_0r_fields,
    494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    495         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    496         -1,
    497         -1,
    498     },
    499 #endif /* chips */
    500 
    501 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    502     { /* SOC_REG_INT_JBCASCFG_CHID_27r */
    503         soc_block_list[81],
    504         soc_genreg,
    505         1,
    506         0,
    507         0x9b960,
    508         0,
    509         0,
    510         2,
    511         soc_JBCASCFG_CHID_0r_fields,
    512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    514         -1,
    515         -1,
    516     },
    517 #endif /* chips */
    518 
    519 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    520     { /* SOC_REG_INT_JBCASCFG_CHID_28r */
    521         soc_block_list[81],
    522         soc_genreg,
    523         1,
    524         0,
    525         0x9c960,
    526         0,
    527         0,
    528         2,
    529         soc_JBCASCFG_CHID_0r_fields,
    530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    531         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    532         -1,
    533         -1,
    534     },
    535 #endif /* chips */
    536 
    537 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    538     { /* SOC_REG_INT_JBCASCFG_CHID_29r */
    539         soc_block_list[81],
    540         soc_genreg,
    541         1,
    542         0,
    543         0x9d960,
    544         0,
    545         0,
    546         2,
    547         soc_JBCASCFG_CHID_0r_fields,
    548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    549         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    550         -1,
    551         -1,
    552     },
    553 #endif /* chips */
    554 
    555 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    556     { /* SOC_REG_INT_JBCASCFG_CHID_30r */
    557         soc_block_list[81],
    558         soc_genreg,
    559         1,
    560         0,
    561         0x9e960,
    562         0,
    563         0,
    564         2,
    565         soc_JBCASCFG_CHID_0r_fields,
    566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    567         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    568         -1,
    569         -1,
    570     },
    571 #endif /* chips */
    572 
    573 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    574     { /* SOC_REG_INT_JBCASCFG_CHID_31r */
    575         soc_block_list[81],
    576         soc_genreg,
    577         1,
    578         0,
    579         0x9f960,
    580         0,
    581         0,
    582         2,
    583         soc_JBCASCFG_CHID_0r_fields,
    584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    585         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    586         -1,
    587         -1,
    588     },
    589 #endif /* chips */
    590 
    591 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    592     { /* SOC_REG_INT_JBCASCFG_CHID_32r */
    593         soc_block_list[81],
    594         soc_genreg,
    595         1,
    596         0,
    597         0xa0960,
    598         0,
    599         0,
    600         2,
    601         soc_JBCASCFG_CHID_0r_fields,
    602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    603         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    604         -1,
    605         -1,
    606     },
    607 #endif /* chips */
    608 
    609 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    610     { /* SOC_REG_INT_JBCASCFG_CHID_33r */
    611         soc_block_list[81],
    612         soc_genreg,
    613         1,
    614         0,
    615         0xa1960,
    616         0,
    617         0,
    618         2,
    619         soc_JBCASCFG_CHID_0r_fields,
    620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    622         -1,
    623         -1,
    624     },
    625 #endif /* chips */
    626 
    627 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    628     { /* SOC_REG_INT_JBCASCFG_CHID_34r */
    629         soc_block_list[81],
    630         soc_genreg,
    631         1,
    632         0,
    633         0xa2960,
    634         0,
    635         0,
    636         2,
    637         soc_JBCASCFG_CHID_0r_fields,
    638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    639         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    640         -1,
    641         -1,
    642     },
    643 #endif /* chips */
    644 
    645 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    646     { /* SOC_REG_INT_JBCASCFG_CHID_35r */
    647         soc_block_list[81],
    648         soc_genreg,
    649         1,
    650         0,
    651         0xa3960,
    652         0,
    653         0,
    654         2,
    655         soc_JBCASCFG_CHID_0r_fields,
    656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    657         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    658         -1,
    659         -1,
    660     },
    661 #endif /* chips */
    662 
    663 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    664     { /* SOC_REG_INT_JBCASCFG_CHID_36r */
    665         soc_block_list[81],
    666         soc_genreg,
    667         1,
    668         0,
    669         0xa4960,
    670         0,
    671         0,
    672         2,
    673         soc_JBCASCFG_CHID_0r_fields,
    674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    676         -1,
    677         -1,
    678     },
    679 #endif /* chips */
    680 
    681 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    682     { /* SOC_REG_INT_JBCASCFG_CHID_37r */
    683         soc_block_list[81],
    684         soc_genreg,
    685         1,
    686         0,
    687         0xa5960,
    688         0,
    689         0,
    690         2,
    691         soc_JBCASCFG_CHID_0r_fields,
    692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    693         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    694         -1,
    695         -1,
    696     },
    697 #endif /* chips */
    698 
    699 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    700     { /* SOC_REG_INT_JBCASCFG_CHID_38r */
    701         soc_block_list[81],
    702         soc_genreg,
    703         1,
    704         0,
    705         0xa6960,
    706         0,
    707         0,
    708         2,
    709         soc_JBCASCFG_CHID_0r_fields,
    710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    711         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    712         -1,
    713         -1,
    714     },
    715 #endif /* chips */
    716 
    717 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    718     { /* SOC_REG_INT_JBCASCFG_CHID_39r */
    719         soc_block_list[81],
    720         soc_genreg,
    721         1,
    722         0,
    723         0xa7960,
    724         0,
    725         0,
    726         2,
    727         soc_JBCASCFG_CHID_0r_fields,
    728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    729         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    730         -1,
    731         -1,
    732     },
    733 #endif /* chips */
    734 
    735 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    736     { /* SOC_REG_INT_JBCASCFG_CHID_40r */
    737         soc_block_list[81],
    738         soc_genreg,
    739         1,
    740         0,
    741         0xa8960,
    742         0,
    743         0,
    744         2,
    745         soc_JBCASCFG_CHID_0r_fields,
    746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    747         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    748         -1,
    749         -1,
    750     },
    751 #endif /* chips */
    752 
    753 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    754     { /* SOC_REG_INT_JBCASCFG_CHID_41r */
    755         soc_block_list[81],
    756         soc_genreg,
    757         1,
    758         0,
    759         0xa9960,
    760         0,
    761         0,
    762         2,
    763         soc_JBCASCFG_CHID_0r_fields,
    764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    765         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    766         -1,
    767         -1,
    768     },
    769 #endif /* chips */
    770 
    771 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    772     { /* SOC_REG_INT_JBCASCFG_CHID_42r */
    773         soc_block_list[81],
    774         soc_genreg,
    775         1,
    776         0,
    777         0xaa960,
    778         0,
    779         0,
    780         2,
    781         soc_JBCASCFG_CHID_0r_fields,
    782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    783         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    784         -1,
    785         -1,
    786     },
    787 #endif /* chips */
    788 
    789 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    790     { /* SOC_REG_INT_JBCASCFG_CHID_43r */
    791         soc_block_list[81],
    792         soc_genreg,
    793         1,
    794         0,
    795         0xab960,
    796         0,
    797         0,
    798         2,
    799         soc_JBCASCFG_CHID_0r_fields,
    800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    801         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    802         -1,
    803         -1,
    804     },
    805 #endif /* chips */
    806 
    807 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    808     { /* SOC_REG_INT_JBCASCFG_CHID_44r */
    809         soc_block_list[81],
    810         soc_genreg,
    811         1,
    812         0,
    813         0xac960,
    814         0,
    815         0,
    816         2,
    817         soc_JBCASCFG_CHID_0r_fields,
    818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    819         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    820         -1,
    821         -1,
    822     },
    823 #endif /* chips */
    824 
    825 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    826     { /* SOC_REG_INT_JBCASCFG_CHID_45r */
    827         soc_block_list[81],
    828         soc_genreg,
    829         1,
    830         0,
    831         0xad960,
    832         0,
    833         0,
    834         2,
    835         soc_JBCASCFG_CHID_0r_fields,
    836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    838         -1,
    839         -1,
    840     },
    841 #endif /* chips */
    842 
    843 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    844     { /* SOC_REG_INT_JBCASCFG_CHID_46r */
    845         soc_block_list[81],
    846         soc_genreg,
    847         1,
    848         0,
    849         0xae960,
    850         0,
    851         0,
    852         2,
    853         soc_JBCASCFG_CHID_0r_fields,
    854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    855         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    856         -1,
    857         -1,
    858     },
    859 #endif /* chips */
    860 
    861 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    862     { /* SOC_REG_INT_JBCASCFG_CHID_47r */
    863         soc_block_list[81],
    864         soc_genreg,
    865         1,
    866         0,
    867         0xaf960,
    868         0,
    869         0,
    870         2,
    871         soc_JBCASCFG_CHID_0r_fields,
    872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    874         -1,
    875         -1,
    876     },
    877 #endif /* chips */
    878 
    879 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    880     { /* SOC_REG_INT_JBCASCFG_CHID_48r */
    881         soc_block_list[81],
    882         soc_genreg,
    883         1,
    884         0,
    885         0xb0960,
    886         0,
    887         0,
    888         2,
    889         soc_JBCASCFG_CHID_0r_fields,
    890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    892         -1,
    893         -1,
    894     },
    895 #endif /* chips */
    896 
    897 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    898     { /* SOC_REG_INT_JBCASCFG_CHID_49r */
    899         soc_block_list[81],
    900         soc_genreg,
    901         1,
    902         0,
    903         0xb1960,
    904         0,
    905         0,
    906         2,
    907         soc_JBCASCFG_CHID_0r_fields,
    908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    909         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    910         -1,
    911         -1,
    912     },
    913 #endif /* chips */
    914 
    915 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    916     { /* SOC_REG_INT_JBCASCFG_CHID_50r */
    917         soc_block_list[81],
    918         soc_genreg,
    919         1,
    920         0,
    921         0xb2960,
    922         0,
    923         0,
    924         2,
    925         soc_JBCASCFG_CHID_0r_fields,
    926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    927         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    928         -1,
    929         -1,
    930     },
    931 #endif /* chips */
    932 
    933 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    934     { /* SOC_REG_INT_JBCASCFG_CHID_51r */
    935         soc_block_list[81],
    936         soc_genreg,
    937         1,
    938         0,
    939         0xb3960,
    940         0,
    941         0,
    942         2,
    943         soc_JBCASCFG_CHID_0r_fields,
    944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    945         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    946         -1,
    947         -1,
    948     },
    949 #endif /* chips */
    950 
    951 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    952     { /* SOC_REG_INT_JBCASCFG_CHID_52r */
    953         soc_block_list[81],
    954         soc_genreg,
    955         1,
    956         0,
    957         0xb4960,
    958         0,
    959         0,
    960         2,
    961         soc_JBCASCFG_CHID_0r_fields,
    962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    963         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    964         -1,
    965         -1,
    966     },
    967 #endif /* chips */
    968 
    969 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    970     { /* SOC_REG_INT_JBCASCFG_CHID_53r */
    971         soc_block_list[81],
    972         soc_genreg,
    973         1,
    974         0,
    975         0xb5960,
    976         0,
    977         0,
    978         2,
    979         soc_JBCASCFG_CHID_0r_fields,
    980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    981         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    982         -1,
    983         -1,
    984     },
    985 #endif /* chips */
    986 
    987 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    988     { /* SOC_REG_INT_JBCASCFG_CHID_54r */
    989         soc_block_list[81],
    990         soc_genreg,
    991         1,
    992         0,
    993         0xb6960,
    994         0,
    995         0,
    996         2,
    997         soc_JBCASCFG_CHID_0r_fields,
    998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    999         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1000         -1,
   1001         -1,
   1002     },
   1003 #endif /* chips */
   1004 
   1005 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1006     { /* SOC_REG_INT_JBCASCFG_CHID_55r */
   1007         soc_block_list[81],
   1008         soc_genreg,
   1009         1,
   1010         0,
   1011         0xb7960,
   1012         0,
   1013         0,
   1014         2,
   1015         soc_JBCASCFG_CHID_0r_fields,
   1016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1017         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1018         -1,
   1019         -1,
   1020     },
   1021 #endif /* chips */
   1022 
   1023 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1024     { /* SOC_REG_INT_JBCASCFG_CHID_56r */
   1025         soc_block_list[81],
   1026         soc_genreg,
   1027         1,
   1028         0,
   1029         0xb8960,
   1030         0,
   1031         0,
   1032         2,
   1033         soc_JBCASCFG_CHID_0r_fields,
   1034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1035         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1036         -1,
   1037         -1,
   1038     },
   1039 #endif /* chips */
   1040 
   1041 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1042     { /* SOC_REG_INT_JBCASCFG_CHID_57r */
   1043         soc_block_list[81],
   1044         soc_genreg,
   1045         1,
   1046         0,
   1047         0xb9960,
   1048         0,
   1049         0,
   1050         2,
   1051         soc_JBCASCFG_CHID_0r_fields,
   1052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1053         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1054         -1,
   1055         -1,
   1056     },
   1057 #endif /* chips */
   1058 
   1059 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1060     { /* SOC_REG_INT_JBCASCFG_CHID_58r */
   1061         soc_block_list[81],
   1062         soc_genreg,
   1063         1,
   1064         0,
   1065         0xba960,
   1066         0,
   1067         0,
   1068         2,
   1069         soc_JBCASCFG_CHID_0r_fields,
   1070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1072         -1,
   1073         -1,
   1074     },
   1075 #endif /* chips */
   1076 
   1077 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1078     { /* SOC_REG_INT_JBCASCFG_CHID_59r */
   1079         soc_block_list[81],
   1080         soc_genreg,
   1081         1,
   1082         0,
   1083         0xbb960,
   1084         0,
   1085         0,
   1086         2,
   1087         soc_JBCASCFG_CHID_0r_fields,
   1088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1089         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1090         -1,
   1091         -1,
   1092     },
   1093 #endif /* chips */
   1094 
   1095 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1096     { /* SOC_REG_INT_JBCASCFG_CHID_60r */
   1097         soc_block_list[81],
   1098         soc_genreg,
   1099         1,
   1100         0,
   1101         0xbc960,
   1102         0,
   1103         0,
   1104         2,
   1105         soc_JBCASCFG_CHID_0r_fields,
   1106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1107         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1108         -1,
   1109         -1,
   1110     },
   1111 #endif /* chips */
   1112 
   1113 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1114     { /* SOC_REG_INT_JBCASCFG_CHID_61r */
   1115         soc_block_list[81],
   1116         soc_genreg,
   1117         1,
   1118         0,
   1119         0xbd960,
   1120         0,
   1121         0,
   1122         2,
   1123         soc_JBCASCFG_CHID_0r_fields,
   1124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1125         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1126         -1,
   1127         -1,
   1128     },
   1129 #endif /* chips */
   1130 
   1131 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1132     { /* SOC_REG_INT_JBCASCFG_CHID_62r */
   1133         soc_block_list[81],
   1134         soc_genreg,
   1135         1,
   1136         0,
   1137         0xbe960,
   1138         0,
   1139         0,
   1140         2,
   1141         soc_JBCASCFG_CHID_0r_fields,
   1142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1143         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1144         -1,
   1145         -1,
   1146     },
   1147 #endif /* chips */
   1148 
   1149 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1150     { /* SOC_REG_INT_JBCASCFG_CHID_63r */
   1151         soc_block_list[81],
   1152         soc_genreg,
   1153         1,
   1154         0,
   1155         0xbf960,
   1156         0,
   1157         0,
   1158         2,
   1159         soc_JBCASCFG_CHID_0r_fields,
   1160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1162         -1,
   1163         -1,
   1164     },
   1165 #endif /* chips */
   1166 
   1167 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1168     { /* SOC_REG_INT_JBCASWINr */
   1169         soc_block_list[81],
   1170         soc_genreg,
   1171         1,
   1172         0,
   1173         0x80962,
   1174         0,
   1175         0,
   1176         2,
   1177         soc_JBCASWINr_fields,
   1178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1179         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1180         -1,
   1181         -1,
   1182     },
   1183 #endif /* chips */
   1184 
   1185 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1186     { /* SOC_REG_INT_JBCHCFG1_CHID_0r */
   1187         soc_block_list[81],
   1188         soc_genreg,
   1189         1,
   1190         0,
   1191         0x80900,
   1192         0,
   1193         0,
   1194         3,
   1195         soc_JBCHCFG1_CHID_0r_fields,
   1196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1197         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1198         -1,
   1199         -1,
   1200     },
   1201 #endif /* chips */
   1202 
   1203 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1204     { /* SOC_REG_INT_JBCHCFG1_CHID_1r */
   1205         soc_block_list[81],
   1206         soc_genreg,
   1207         1,
   1208         0,
   1209         0x81900,
   1210         0,
   1211         0,
   1212         3,
   1213         soc_JBCHCFG1_CHID_0r_fields,
   1214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1215         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1216         -1,
   1217         -1,
   1218     },
   1219 #endif /* chips */
   1220 
   1221 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1222     { /* SOC_REG_INT_JBCHCFG1_CHID_2r */
   1223         soc_block_list[81],
   1224         soc_genreg,
   1225         1,
   1226         0,
   1227         0x82900,
   1228         0,
   1229         0,
   1230         3,
   1231         soc_JBCHCFG1_CHID_0r_fields,
   1232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1233         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1234         -1,
   1235         -1,
   1236     },
   1237 #endif /* chips */
   1238 
   1239 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1240     { /* SOC_REG_INT_JBCHCFG1_CHID_3r */
   1241         soc_block_list[81],
   1242         soc_genreg,
   1243         1,
   1244         0,
   1245         0x83900,
   1246         0,
   1247         0,
   1248         3,
   1249         soc_JBCHCFG1_CHID_0r_fields,
   1250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1252         -1,
   1253         -1,
   1254     },
   1255 #endif /* chips */
   1256 
   1257 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1258     { /* SOC_REG_INT_JBCHCFG1_CHID_4r */
   1259         soc_block_list[81],
   1260         soc_genreg,
   1261         1,
   1262         0,
   1263         0x84900,
   1264         0,
   1265         0,
   1266         3,
   1267         soc_JBCHCFG1_CHID_0r_fields,
   1268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1269         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1270         -1,
   1271         -1,
   1272     },
   1273 #endif /* chips */
   1274 
   1275 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1276     { /* SOC_REG_INT_JBCHCFG1_CHID_5r */
   1277         soc_block_list[81],
   1278         soc_genreg,
   1279         1,
   1280         0,
   1281         0x85900,
   1282         0,
   1283         0,
   1284         3,
   1285         soc_JBCHCFG1_CHID_0r_fields,
   1286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1288         -1,
   1289         -1,
   1290     },
   1291 #endif /* chips */
   1292 
   1293 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1294     { /* SOC_REG_INT_JBCHCFG1_CHID_6r */
   1295         soc_block_list[81],
   1296         soc_genreg,
   1297         1,
   1298         0,
   1299         0x86900,
   1300         0,
   1301         0,
   1302         3,
   1303         soc_JBCHCFG1_CHID_0r_fields,
   1304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1305         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1306         -1,
   1307         -1,
   1308     },
   1309 #endif /* chips */
   1310 
   1311 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1312     { /* SOC_REG_INT_JBCHCFG1_CHID_7r */
   1313         soc_block_list[81],
   1314         soc_genreg,
   1315         1,
   1316         0,
   1317         0x87900,
   1318         0,
   1319         0,
   1320         3,
   1321         soc_JBCHCFG1_CHID_0r_fields,
   1322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1323         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1324         -1,
   1325         -1,
   1326     },
   1327 #endif /* chips */
   1328 
   1329 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1330     { /* SOC_REG_INT_JBCHCFG1_CHID_8r */
   1331         soc_block_list[81],
   1332         soc_genreg,
   1333         1,
   1334         0,
   1335         0x88900,
   1336         0,
   1337         0,
   1338         3,
   1339         soc_JBCHCFG1_CHID_0r_fields,
   1340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1341         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1342         -1,
   1343         -1,
   1344     },
   1345 #endif /* chips */
   1346 
   1347 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1348     { /* SOC_REG_INT_JBCHCFG1_CHID_9r */
   1349         soc_block_list[81],
   1350         soc_genreg,
   1351         1,
   1352         0,
   1353         0x89900,
   1354         0,
   1355         0,
   1356         3,
   1357         soc_JBCHCFG1_CHID_0r_fields,
   1358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1359         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1360         -1,
   1361         -1,
   1362     },
   1363 #endif /* chips */
   1364 
   1365 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1366     { /* SOC_REG_INT_JBCHCFG1_CHID_10r */
   1367         soc_block_list[81],
   1368         soc_genreg,
   1369         1,
   1370         0,
   1371         0x8a900,
   1372         0,
   1373         0,
   1374         3,
   1375         soc_JBCHCFG1_CHID_0r_fields,
   1376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1378         -1,
   1379         -1,
   1380     },
   1381 #endif /* chips */
   1382 
   1383 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1384     { /* SOC_REG_INT_JBCHCFG1_CHID_11r */
   1385         soc_block_list[81],
   1386         soc_genreg,
   1387         1,
   1388         0,
   1389         0x8b900,
   1390         0,
   1391         0,
   1392         3,
   1393         soc_JBCHCFG1_CHID_0r_fields,
   1394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1395         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1396         -1,
   1397         -1,
   1398     },
   1399 #endif /* chips */
   1400 
   1401 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1402     { /* SOC_REG_INT_JBCHCFG1_CHID_12r */
   1403         soc_block_list[81],
   1404         soc_genreg,
   1405         1,
   1406         0,
   1407         0x8c900,
   1408         0,
   1409         0,
   1410         3,
   1411         soc_JBCHCFG1_CHID_0r_fields,
   1412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1413         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1414         -1,
   1415         -1,
   1416     },
   1417 #endif /* chips */
   1418 
   1419 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1420     { /* SOC_REG_INT_JBCHCFG1_CHID_13r */
   1421         soc_block_list[81],
   1422         soc_genreg,
   1423         1,
   1424         0,
   1425         0x8d900,
   1426         0,
   1427         0,
   1428         3,
   1429         soc_JBCHCFG1_CHID_0r_fields,
   1430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1431         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1432         -1,
   1433         -1,
   1434     },
   1435 #endif /* chips */
   1436 
   1437 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1438     { /* SOC_REG_INT_JBCHCFG1_CHID_14r */
   1439         soc_block_list[81],
   1440         soc_genreg,
   1441         1,
   1442         0,
   1443         0x8e900,
   1444         0,
   1445         0,
   1446         3,
   1447         soc_JBCHCFG1_CHID_0r_fields,
   1448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1449         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1450         -1,
   1451         -1,
   1452     },
   1453 #endif /* chips */
   1454 
   1455 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1456     { /* SOC_REG_INT_JBCHCFG1_CHID_15r */
   1457         soc_block_list[81],
   1458         soc_genreg,
   1459         1,
   1460         0,
   1461         0x8f900,
   1462         0,
   1463         0,
   1464         3,
   1465         soc_JBCHCFG1_CHID_0r_fields,
   1466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1467         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1468         -1,
   1469         -1,
   1470     },
   1471 #endif /* chips */
   1472 
   1473 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1474     { /* SOC_REG_INT_JBCHCFG1_CHID_16r */
   1475         soc_block_list[81],
   1476         soc_genreg,
   1477         1,
   1478         0,
   1479         0x90900,
   1480         0,
   1481         0,
   1482         3,
   1483         soc_JBCHCFG1_CHID_0r_fields,
   1484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1486         -1,
   1487         -1,
   1488     },
   1489 #endif /* chips */
   1490 
   1491 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1492     { /* SOC_REG_INT_JBCHCFG1_CHID_17r */
   1493         soc_block_list[81],
   1494         soc_genreg,
   1495         1,
   1496         0,
   1497         0x91900,
   1498         0,
   1499         0,
   1500         3,
   1501         soc_JBCHCFG1_CHID_0r_fields,
   1502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1503         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1504         -1,
   1505         -1,
   1506     },
   1507 #endif /* chips */
   1508 
   1509 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1510     { /* SOC_REG_INT_JBCHCFG1_CHID_18r */
   1511         soc_block_list[81],
   1512         soc_genreg,
   1513         1,
   1514         0,
   1515         0x92900,
   1516         0,
   1517         0,
   1518         3,
   1519         soc_JBCHCFG1_CHID_0r_fields,
   1520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1522         -1,
   1523         -1,
   1524     },
   1525 #endif /* chips */
   1526 
   1527 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1528     { /* SOC_REG_INT_JBCHCFG1_CHID_19r */
   1529         soc_block_list[81],
   1530         soc_genreg,
   1531         1,
   1532         0,
   1533         0x93900,
   1534         0,
   1535         0,
   1536         3,
   1537         soc_JBCHCFG1_CHID_0r_fields,
   1538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1540         -1,
   1541         -1,
   1542     },
   1543 #endif /* chips */
   1544 
   1545 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1546     { /* SOC_REG_INT_JBCHCFG1_CHID_20r */
   1547         soc_block_list[81],
   1548         soc_genreg,
   1549         1,
   1550         0,
   1551         0x94900,
   1552         0,
   1553         0,
   1554         3,
   1555         soc_JBCHCFG1_CHID_0r_fields,
   1556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1558         -1,
   1559         -1,
   1560     },
   1561 #endif /* chips */
   1562 
   1563 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1564     { /* SOC_REG_INT_JBCHCFG1_CHID_21r */
   1565         soc_block_list[81],
   1566         soc_genreg,
   1567         1,
   1568         0,
   1569         0x95900,
   1570         0,
   1571         0,
   1572         3,
   1573         soc_JBCHCFG1_CHID_0r_fields,
   1574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1576         -1,
   1577         -1,
   1578     },
   1579 #endif /* chips */
   1580 
   1581 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1582     { /* SOC_REG_INT_JBCHCFG1_CHID_22r */
   1583         soc_block_list[81],
   1584         soc_genreg,
   1585         1,
   1586         0,
   1587         0x96900,
   1588         0,
   1589         0,
   1590         3,
   1591         soc_JBCHCFG1_CHID_0r_fields,
   1592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1594         -1,
   1595         -1,
   1596     },
   1597 #endif /* chips */
   1598 
   1599 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1600     { /* SOC_REG_INT_JBCHCFG1_CHID_23r */
   1601         soc_block_list[81],
   1602         soc_genreg,
   1603         1,
   1604         0,
   1605         0x97900,
   1606         0,
   1607         0,
   1608         3,
   1609         soc_JBCHCFG1_CHID_0r_fields,
   1610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1612         -1,
   1613         -1,
   1614     },
   1615 #endif /* chips */
   1616 
   1617 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1618     { /* SOC_REG_INT_JBCHCFG1_CHID_24r */
   1619         soc_block_list[81],
   1620         soc_genreg,
   1621         1,
   1622         0,
   1623         0x98900,
   1624         0,
   1625         0,
   1626         3,
   1627         soc_JBCHCFG1_CHID_0r_fields,
   1628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1630         -1,
   1631         -1,
   1632     },
   1633 #endif /* chips */
   1634 
   1635 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1636     { /* SOC_REG_INT_JBCHCFG1_CHID_25r */
   1637         soc_block_list[81],
   1638         soc_genreg,
   1639         1,
   1640         0,
   1641         0x99900,
   1642         0,
   1643         0,
   1644         3,
   1645         soc_JBCHCFG1_CHID_0r_fields,
   1646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1647         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1648         -1,
   1649         -1,
   1650     },
   1651 #endif /* chips */
   1652 
   1653 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1654     { /* SOC_REG_INT_JBCHCFG1_CHID_26r */
   1655         soc_block_list[81],
   1656         soc_genreg,
   1657         1,
   1658         0,
   1659         0x9a900,
   1660         0,
   1661         0,
   1662         3,
   1663         soc_JBCHCFG1_CHID_0r_fields,
   1664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1665         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1666         -1,
   1667         -1,
   1668     },
   1669 #endif /* chips */
   1670 
   1671 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1672     { /* SOC_REG_INT_JBCHCFG1_CHID_27r */
   1673         soc_block_list[81],
   1674         soc_genreg,
   1675         1,
   1676         0,
   1677         0x9b900,
   1678         0,
   1679         0,
   1680         3,
   1681         soc_JBCHCFG1_CHID_0r_fields,
   1682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1683         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1684         -1,
   1685         -1,
   1686     },
   1687 #endif /* chips */
   1688 
   1689 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1690     { /* SOC_REG_INT_JBCHCFG1_CHID_28r */
   1691         soc_block_list[81],
   1692         soc_genreg,
   1693         1,
   1694         0,
   1695         0x9c900,
   1696         0,
   1697         0,
   1698         3,
   1699         soc_JBCHCFG1_CHID_0r_fields,
   1700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1701         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1702         -1,
   1703         -1,
   1704     },
   1705 #endif /* chips */
   1706 
   1707 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1708     { /* SOC_REG_INT_JBCHCFG1_CHID_29r */
   1709         soc_block_list[81],
   1710         soc_genreg,
   1711         1,
   1712         0,
   1713         0x9d900,
   1714         0,
   1715         0,
   1716         3,
   1717         soc_JBCHCFG1_CHID_0r_fields,
   1718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1719         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1720         -1,
   1721         -1,
   1722     },
   1723 #endif /* chips */
   1724 
   1725 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1726     { /* SOC_REG_INT_JBCHCFG1_CHID_30r */
   1727         soc_block_list[81],
   1728         soc_genreg,
   1729         1,
   1730         0,
   1731         0x9e900,
   1732         0,
   1733         0,
   1734         3,
   1735         soc_JBCHCFG1_CHID_0r_fields,
   1736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1737         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1738         -1,
   1739         -1,
   1740     },
   1741 #endif /* chips */
   1742 
   1743 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1744     { /* SOC_REG_INT_JBCHCFG1_CHID_31r */
   1745         soc_block_list[81],
   1746         soc_genreg,
   1747         1,
   1748         0,
   1749         0x9f900,
   1750         0,
   1751         0,
   1752         3,
   1753         soc_JBCHCFG1_CHID_0r_fields,
   1754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1755         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1756         -1,
   1757         -1,
   1758     },
   1759 #endif /* chips */
   1760 
   1761 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1762     { /* SOC_REG_INT_JBCHCFG1_CHID_32r */
   1763         soc_block_list[81],
   1764         soc_genreg,
   1765         1,
   1766         0,
   1767         0xa0900,
   1768         0,
   1769         0,
   1770         3,
   1771         soc_JBCHCFG1_CHID_0r_fields,
   1772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1774         -1,
   1775         -1,
   1776     },
   1777 #endif /* chips */
   1778 
   1779 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1780     { /* SOC_REG_INT_JBCHCFG1_CHID_33r */
   1781         soc_block_list[81],
   1782         soc_genreg,
   1783         1,
   1784         0,
   1785         0xa1900,
   1786         0,
   1787         0,
   1788         3,
   1789         soc_JBCHCFG1_CHID_0r_fields,
   1790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1792         -1,
   1793         -1,
   1794     },
   1795 #endif /* chips */
   1796 
   1797 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1798     { /* SOC_REG_INT_JBCHCFG1_CHID_34r */
   1799         soc_block_list[81],
   1800         soc_genreg,
   1801         1,
   1802         0,
   1803         0xa2900,
   1804         0,
   1805         0,
   1806         3,
   1807         soc_JBCHCFG1_CHID_0r_fields,
   1808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1810         -1,
   1811         -1,
   1812     },
   1813 #endif /* chips */
   1814 
   1815 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1816     { /* SOC_REG_INT_JBCHCFG1_CHID_35r */
   1817         soc_block_list[81],
   1818         soc_genreg,
   1819         1,
   1820         0,
   1821         0xa3900,
   1822         0,
   1823         0,
   1824         3,
   1825         soc_JBCHCFG1_CHID_0r_fields,
   1826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1828         -1,
   1829         -1,
   1830     },
   1831 #endif /* chips */
   1832 
   1833 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1834     { /* SOC_REG_INT_JBCHCFG1_CHID_36r */
   1835         soc_block_list[81],
   1836         soc_genreg,
   1837         1,
   1838         0,
   1839         0xa4900,
   1840         0,
   1841         0,
   1842         3,
   1843         soc_JBCHCFG1_CHID_0r_fields,
   1844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1845         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1846         -1,
   1847         -1,
   1848     },
   1849 #endif /* chips */
   1850 
   1851 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1852     { /* SOC_REG_INT_JBCHCFG1_CHID_37r */
   1853         soc_block_list[81],
   1854         soc_genreg,
   1855         1,
   1856         0,
   1857         0xa5900,
   1858         0,
   1859         0,
   1860         3,
   1861         soc_JBCHCFG1_CHID_0r_fields,
   1862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1863         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1864         -1,
   1865         -1,
   1866     },
   1867 #endif /* chips */
   1868 
   1869 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1870     { /* SOC_REG_INT_JBCHCFG1_CHID_38r */
   1871         soc_block_list[81],
   1872         soc_genreg,
   1873         1,
   1874         0,
   1875         0xa6900,
   1876         0,
   1877         0,
   1878         3,
   1879         soc_JBCHCFG1_CHID_0r_fields,
   1880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1882         -1,
   1883         -1,
   1884     },
   1885 #endif /* chips */
   1886 
   1887 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1888     { /* SOC_REG_INT_JBCHCFG1_CHID_39r */
   1889         soc_block_list[81],
   1890         soc_genreg,
   1891         1,
   1892         0,
   1893         0xa7900,
   1894         0,
   1895         0,
   1896         3,
   1897         soc_JBCHCFG1_CHID_0r_fields,
   1898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1899         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1900         -1,
   1901         -1,
   1902     },
   1903 #endif /* chips */
   1904 
   1905 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1906     { /* SOC_REG_INT_JBCHCFG1_CHID_40r */
   1907         soc_block_list[81],
   1908         soc_genreg,
   1909         1,
   1910         0,
   1911         0xa8900,
   1912         0,
   1913         0,
   1914         3,
   1915         soc_JBCHCFG1_CHID_0r_fields,
   1916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1918         -1,
   1919         -1,
   1920     },
   1921 #endif /* chips */
   1922 
   1923 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1924     { /* SOC_REG_INT_JBCHCFG1_CHID_41r */
   1925         soc_block_list[81],
   1926         soc_genreg,
   1927         1,
   1928         0,
   1929         0xa9900,
   1930         0,
   1931         0,
   1932         3,
   1933         soc_JBCHCFG1_CHID_0r_fields,
   1934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1936         -1,
   1937         -1,
   1938     },
   1939 #endif /* chips */
   1940 
   1941 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1942     { /* SOC_REG_INT_JBCHCFG1_CHID_42r */
   1943         soc_block_list[81],
   1944         soc_genreg,
   1945         1,
   1946         0,
   1947         0xaa900,
   1948         0,
   1949         0,
   1950         3,
   1951         soc_JBCHCFG1_CHID_0r_fields,
   1952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1953         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1954         -1,
   1955         -1,
   1956     },
   1957 #endif /* chips */
   1958 
   1959 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1960     { /* SOC_REG_INT_JBCHCFG1_CHID_43r */
   1961         soc_block_list[81],
   1962         soc_genreg,
   1963         1,
   1964         0,
   1965         0xab900,
   1966         0,
   1967         0,
   1968         3,
   1969         soc_JBCHCFG1_CHID_0r_fields,
   1970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1971         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1972         -1,
   1973         -1,
   1974     },
   1975 #endif /* chips */
   1976 
   1977 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1978     { /* SOC_REG_INT_JBCHCFG1_CHID_44r */
   1979         soc_block_list[81],
   1980         soc_genreg,
   1981         1,
   1982         0,
   1983         0xac900,
   1984         0,
   1985         0,
   1986         3,
   1987         soc_JBCHCFG1_CHID_0r_fields,
   1988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1990         -1,
   1991         -1,
   1992     },
   1993 #endif /* chips */
   1994 
   1995 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1996     { /* SOC_REG_INT_JBCHCFG1_CHID_45r */
   1997         soc_block_list[81],
   1998         soc_genreg,
   1999         1,
   2000         0,
   2001         0xad900,
   2002         0,
   2003         0,
   2004         3,
   2005         soc_JBCHCFG1_CHID_0r_fields,
   2006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2007         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2008         -1,
   2009         -1,
   2010     },
   2011 #endif /* chips */
   2012 
   2013 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2014     { /* SOC_REG_INT_JBCHCFG1_CHID_46r */
   2015         soc_block_list[81],
   2016         soc_genreg,
   2017         1,
   2018         0,
   2019         0xae900,
   2020         0,
   2021         0,
   2022         3,
   2023         soc_JBCHCFG1_CHID_0r_fields,
   2024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2026         -1,
   2027         -1,
   2028     },
   2029 #endif /* chips */
   2030 
   2031 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2032     { /* SOC_REG_INT_JBCHCFG1_CHID_47r */
   2033         soc_block_list[81],
   2034         soc_genreg,
   2035         1,
   2036         0,
   2037         0xaf900,
   2038         0,
   2039         0,
   2040         3,
   2041         soc_JBCHCFG1_CHID_0r_fields,
   2042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2044         -1,
   2045         -1,
   2046     },
   2047 #endif /* chips */
   2048 
   2049 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2050     { /* SOC_REG_INT_JBCHCFG1_CHID_48r */
   2051         soc_block_list[81],
   2052         soc_genreg,
   2053         1,
   2054         0,
   2055         0xb0900,
   2056         0,
   2057         0,
   2058         3,
   2059         soc_JBCHCFG1_CHID_0r_fields,
   2060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2061         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2062         -1,
   2063         -1,
   2064     },
   2065 #endif /* chips */
   2066 
   2067 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2068     { /* SOC_REG_INT_JBCHCFG1_CHID_49r */
   2069         soc_block_list[81],
   2070         soc_genreg,
   2071         1,
   2072         0,
   2073         0xb1900,
   2074         0,
   2075         0,
   2076         3,
   2077         soc_JBCHCFG1_CHID_0r_fields,
   2078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2079         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2080         -1,
   2081         -1,
   2082     },
   2083 #endif /* chips */
   2084 
   2085 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2086     { /* SOC_REG_INT_JBCHCFG1_CHID_50r */
   2087         soc_block_list[81],
   2088         soc_genreg,
   2089         1,
   2090         0,
   2091         0xb2900,
   2092         0,
   2093         0,
   2094         3,
   2095         soc_JBCHCFG1_CHID_0r_fields,
   2096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2097         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2098         -1,
   2099         -1,
   2100     },
   2101 #endif /* chips */
   2102 
   2103 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2104     { /* SOC_REG_INT_JBCHCFG1_CHID_51r */
   2105         soc_block_list[81],
   2106         soc_genreg,
   2107         1,
   2108         0,
   2109         0xb3900,
   2110         0,
   2111         0,
   2112         3,
   2113         soc_JBCHCFG1_CHID_0r_fields,
   2114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2115         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2116         -1,
   2117         -1,
   2118     },
   2119 #endif /* chips */
   2120 
   2121 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2122     { /* SOC_REG_INT_JBCHCFG1_CHID_52r */
   2123         soc_block_list[81],
   2124         soc_genreg,
   2125         1,
   2126         0,
   2127         0xb4900,
   2128         0,
   2129         0,
   2130         3,
   2131         soc_JBCHCFG1_CHID_0r_fields,
   2132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2133         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2134         -1,
   2135         -1,
   2136     },
   2137 #endif /* chips */
   2138 
   2139 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2140     { /* SOC_REG_INT_JBCHCFG1_CHID_53r */
   2141         soc_block_list[81],
   2142         soc_genreg,
   2143         1,
   2144         0,
   2145         0xb5900,
   2146         0,
   2147         0,
   2148         3,
   2149         soc_JBCHCFG1_CHID_0r_fields,
   2150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2151         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2152         -1,
   2153         -1,
   2154     },
   2155 #endif /* chips */
   2156 
   2157 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2158     { /* SOC_REG_INT_JBCHCFG1_CHID_54r */
   2159         soc_block_list[81],
   2160         soc_genreg,
   2161         1,
   2162         0,
   2163         0xb6900,
   2164         0,
   2165         0,
   2166         3,
   2167         soc_JBCHCFG1_CHID_0r_fields,
   2168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2169         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2170         -1,
   2171         -1,
   2172     },
   2173 #endif /* chips */
   2174 
   2175 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2176     { /* SOC_REG_INT_JBCHCFG1_CHID_55r */
   2177         soc_block_list[81],
   2178         soc_genreg,
   2179         1,
   2180         0,
   2181         0xb7900,
   2182         0,
   2183         0,
   2184         3,
   2185         soc_JBCHCFG1_CHID_0r_fields,
   2186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2188         -1,
   2189         -1,
   2190     },
   2191 #endif /* chips */
   2192 
   2193 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2194     { /* SOC_REG_INT_JBCHCFG1_CHID_56r */
   2195         soc_block_list[81],
   2196         soc_genreg,
   2197         1,
   2198         0,
   2199         0xb8900,
   2200         0,
   2201         0,
   2202         3,
   2203         soc_JBCHCFG1_CHID_0r_fields,
   2204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2206         -1,
   2207         -1,
   2208     },
   2209 #endif /* chips */
   2210 
   2211 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2212     { /* SOC_REG_INT_JBCHCFG1_CHID_57r */
   2213         soc_block_list[81],
   2214         soc_genreg,
   2215         1,
   2216         0,
   2217         0xb9900,
   2218         0,
   2219         0,
   2220         3,
   2221         soc_JBCHCFG1_CHID_0r_fields,
   2222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2224         -1,
   2225         -1,
   2226     },
   2227 #endif /* chips */
   2228 
   2229 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2230     { /* SOC_REG_INT_JBCHCFG1_CHID_58r */
   2231         soc_block_list[81],
   2232         soc_genreg,
   2233         1,
   2234         0,
   2235         0xba900,
   2236         0,
   2237         0,
   2238         3,
   2239         soc_JBCHCFG1_CHID_0r_fields,
   2240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2241         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2242         -1,
   2243         -1,
   2244     },
   2245 #endif /* chips */
   2246 
   2247 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2248     { /* SOC_REG_INT_JBCHCFG1_CHID_59r */
   2249         soc_block_list[81],
   2250         soc_genreg,
   2251         1,
   2252         0,
   2253         0xbb900,
   2254         0,
   2255         0,
   2256         3,
   2257         soc_JBCHCFG1_CHID_0r_fields,
   2258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2259         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2260         -1,
   2261         -1,
   2262     },
   2263 #endif /* chips */
   2264 
   2265 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2266     { /* SOC_REG_INT_JBCHCFG1_CHID_60r */
   2267         soc_block_list[81],
   2268         soc_genreg,
   2269         1,
   2270         0,
   2271         0xbc900,
   2272         0,
   2273         0,
   2274         3,
   2275         soc_JBCHCFG1_CHID_0r_fields,
   2276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2277         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2278         -1,
   2279         -1,
   2280     },
   2281 #endif /* chips */
   2282 
   2283 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2284     { /* SOC_REG_INT_JBCHCFG1_CHID_61r */
   2285         soc_block_list[81],
   2286         soc_genreg,
   2287         1,
   2288         0,
   2289         0xbd900,
   2290         0,
   2291         0,
   2292         3,
   2293         soc_JBCHCFG1_CHID_0r_fields,
   2294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2296         -1,
   2297         -1,
   2298     },
   2299 #endif /* chips */
   2300 
   2301 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2302     { /* SOC_REG_INT_JBCHCFG1_CHID_62r */
   2303         soc_block_list[81],
   2304         soc_genreg,
   2305         1,
   2306         0,
   2307         0xbe900,
   2308         0,
   2309         0,
   2310         3,
   2311         soc_JBCHCFG1_CHID_0r_fields,
   2312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2313         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2314         -1,
   2315         -1,
   2316     },
   2317 #endif /* chips */
   2318 
   2319 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2320     { /* SOC_REG_INT_JBCHCFG1_CHID_63r */
   2321         soc_block_list[81],
   2322         soc_genreg,
   2323         1,
   2324         0,
   2325         0xbf900,
   2326         0,
   2327         0,
   2328         3,
   2329         soc_JBCHCFG1_CHID_0r_fields,
   2330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2332         -1,
   2333         -1,
   2334     },
   2335 #endif /* chips */
   2336 
   2337 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2338     { /* SOC_REG_INT_JBCHCFG2_CHID_0r */
   2339         soc_block_list[81],
   2340         soc_genreg,
   2341         1,
   2342         0,
   2343         0x80902,
   2344         0,
   2345         0,
   2346         4,
   2347         soc_JBCHCFG2_CHID_0r_fields,
   2348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2349         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2350         -1,
   2351         -1,
   2352     },
   2353 #endif /* chips */
   2354 
   2355 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2356     { /* SOC_REG_INT_JBCHCFG2_CHID_1r */
   2357         soc_block_list[81],
   2358         soc_genreg,
   2359         1,
   2360         0,
   2361         0x81902,
   2362         0,
   2363         0,
   2364         4,
   2365         soc_JBCHCFG2_CHID_0r_fields,
   2366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2367         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2368         -1,
   2369         -1,
   2370     },
   2371 #endif /* chips */
   2372 
   2373 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2374     { /* SOC_REG_INT_JBCHCFG2_CHID_2r */
   2375         soc_block_list[81],
   2376         soc_genreg,
   2377         1,
   2378         0,
   2379         0x82902,
   2380         0,
   2381         0,
   2382         4,
   2383         soc_JBCHCFG2_CHID_0r_fields,
   2384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2385         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2386         -1,
   2387         -1,
   2388     },
   2389 #endif /* chips */
   2390 
   2391 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2392     { /* SOC_REG_INT_JBCHCFG2_CHID_3r */
   2393         soc_block_list[81],
   2394         soc_genreg,
   2395         1,
   2396         0,
   2397         0x83902,
   2398         0,
   2399         0,
   2400         4,
   2401         soc_JBCHCFG2_CHID_0r_fields,
   2402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2403         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2404         -1,
   2405         -1,
   2406     },
   2407 #endif /* chips */
   2408 
   2409 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2410     { /* SOC_REG_INT_JBCHCFG2_CHID_4r */
   2411         soc_block_list[81],
   2412         soc_genreg,
   2413         1,
   2414         0,
   2415         0x84902,
   2416         0,
   2417         0,
   2418         4,
   2419         soc_JBCHCFG2_CHID_0r_fields,
   2420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2421         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2422         -1,
   2423         -1,
   2424     },
   2425 #endif /* chips */
   2426 
   2427 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2428     { /* SOC_REG_INT_JBCHCFG2_CHID_5r */
   2429         soc_block_list[81],
   2430         soc_genreg,
   2431         1,
   2432         0,
   2433         0x85902,
   2434         0,
   2435         0,
   2436         4,
   2437         soc_JBCHCFG2_CHID_0r_fields,
   2438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2439         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2440         -1,
   2441         -1,
   2442     },
   2443 #endif /* chips */
   2444 
   2445 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2446     { /* SOC_REG_INT_JBCHCFG2_CHID_6r */
   2447         soc_block_list[81],
   2448         soc_genreg,
   2449         1,
   2450         0,
   2451         0x86902,
   2452         0,
   2453         0,
   2454         4,
   2455         soc_JBCHCFG2_CHID_0r_fields,
   2456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2457         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2458         -1,
   2459         -1,
   2460     },
   2461 #endif /* chips */
   2462 
   2463 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2464     { /* SOC_REG_INT_JBCHCFG2_CHID_7r */
   2465         soc_block_list[81],
   2466         soc_genreg,
   2467         1,
   2468         0,
   2469         0x87902,
   2470         0,
   2471         0,
   2472         4,
   2473         soc_JBCHCFG2_CHID_0r_fields,
   2474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2475         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2476         -1,
   2477         -1,
   2478     },
   2479 #endif /* chips */
   2480 
   2481 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2482     { /* SOC_REG_INT_JBCHCFG2_CHID_8r */
   2483         soc_block_list[81],
   2484         soc_genreg,
   2485         1,
   2486         0,
   2487         0x88902,
   2488         0,
   2489         0,
   2490         4,
   2491         soc_JBCHCFG2_CHID_0r_fields,
   2492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2493         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2494         -1,
   2495         -1,
   2496     },
   2497 #endif /* chips */
   2498 
   2499 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2500     { /* SOC_REG_INT_JBCHCFG2_CHID_9r */
   2501         soc_block_list[81],
   2502         soc_genreg,
   2503         1,
   2504         0,
   2505         0x89902,
   2506         0,
   2507         0,
   2508         4,
   2509         soc_JBCHCFG2_CHID_0r_fields,
   2510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2511         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2512         -1,
   2513         -1,
   2514     },
   2515 #endif /* chips */
   2516 
   2517 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2518     { /* SOC_REG_INT_JBCHCFG2_CHID_10r */
   2519         soc_block_list[81],
   2520         soc_genreg,
   2521         1,
   2522         0,
   2523         0x8a902,
   2524         0,
   2525         0,
   2526         4,
   2527         soc_JBCHCFG2_CHID_0r_fields,
   2528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2529         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2530         -1,
   2531         -1,
   2532     },
   2533 #endif /* chips */
   2534 
   2535 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2536     { /* SOC_REG_INT_JBCHCFG2_CHID_11r */
   2537         soc_block_list[81],
   2538         soc_genreg,
   2539         1,
   2540         0,
   2541         0x8b902,
   2542         0,
   2543         0,
   2544         4,
   2545         soc_JBCHCFG2_CHID_0r_fields,
   2546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2547         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2548         -1,
   2549         -1,
   2550     },
   2551 #endif /* chips */
   2552 
   2553 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2554     { /* SOC_REG_INT_JBCHCFG2_CHID_12r */
   2555         soc_block_list[81],
   2556         soc_genreg,
   2557         1,
   2558         0,
   2559         0x8c902,
   2560         0,
   2561         0,
   2562         4,
   2563         soc_JBCHCFG2_CHID_0r_fields,
   2564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2565         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2566         -1,
   2567         -1,
   2568     },
   2569 #endif /* chips */
   2570 
   2571 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2572     { /* SOC_REG_INT_JBCHCFG2_CHID_13r */
   2573         soc_block_list[81],
   2574         soc_genreg,
   2575         1,
   2576         0,
   2577         0x8d902,
   2578         0,
   2579         0,
   2580         4,
   2581         soc_JBCHCFG2_CHID_0r_fields,
   2582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2584         -1,
   2585         -1,
   2586     },
   2587 #endif /* chips */
   2588 
   2589 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2590     { /* SOC_REG_INT_JBCHCFG2_CHID_14r */
   2591         soc_block_list[81],
   2592         soc_genreg,
   2593         1,
   2594         0,
   2595         0x8e902,
   2596         0,
   2597         0,
   2598         4,
   2599         soc_JBCHCFG2_CHID_0r_fields,
   2600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2602         -1,
   2603         -1,
   2604     },
   2605 #endif /* chips */
   2606 
   2607 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2608     { /* SOC_REG_INT_JBCHCFG2_CHID_15r */
   2609         soc_block_list[81],
   2610         soc_genreg,
   2611         1,
   2612         0,
   2613         0x8f902,
   2614         0,
   2615         0,
   2616         4,
   2617         soc_JBCHCFG2_CHID_0r_fields,
   2618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2619         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2620         -1,
   2621         -1,
   2622     },
   2623 #endif /* chips */
   2624 
   2625 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2626     { /* SOC_REG_INT_JBCHCFG2_CHID_16r */
   2627         soc_block_list[81],
   2628         soc_genreg,
   2629         1,
   2630         0,
   2631         0x90902,
   2632         0,
   2633         0,
   2634         4,
   2635         soc_JBCHCFG2_CHID_0r_fields,
   2636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2637         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2638         -1,
   2639         -1,
   2640     },
   2641 #endif /* chips */
   2642 
   2643 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2644     { /* SOC_REG_INT_JBCHCFG2_CHID_17r */
   2645         soc_block_list[81],
   2646         soc_genreg,
   2647         1,
   2648         0,
   2649         0x91902,
   2650         0,
   2651         0,
   2652         4,
   2653         soc_JBCHCFG2_CHID_0r_fields,
   2654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2655         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2656         -1,
   2657         -1,
   2658     },
   2659 #endif /* chips */
   2660 
   2661 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2662     { /* SOC_REG_INT_JBCHCFG2_CHID_18r */
   2663         soc_block_list[81],
   2664         soc_genreg,
   2665         1,
   2666         0,
   2667         0x92902,
   2668         0,
   2669         0,
   2670         4,
   2671         soc_JBCHCFG2_CHID_0r_fields,
   2672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2673         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2674         -1,
   2675         -1,
   2676     },
   2677 #endif /* chips */
   2678 
   2679 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2680     { /* SOC_REG_INT_JBCHCFG2_CHID_19r */
   2681         soc_block_list[81],
   2682         soc_genreg,
   2683         1,
   2684         0,
   2685         0x93902,
   2686         0,
   2687         0,
   2688         4,
   2689         soc_JBCHCFG2_CHID_0r_fields,
   2690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2692         -1,
   2693         -1,
   2694     },
   2695 #endif /* chips */
   2696 
   2697 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2698     { /* SOC_REG_INT_JBCHCFG2_CHID_20r */
   2699         soc_block_list[81],
   2700         soc_genreg,
   2701         1,
   2702         0,
   2703         0x94902,
   2704         0,
   2705         0,
   2706         4,
   2707         soc_JBCHCFG2_CHID_0r_fields,
   2708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2710         -1,
   2711         -1,
   2712     },
   2713 #endif /* chips */
   2714 
   2715 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2716     { /* SOC_REG_INT_JBCHCFG2_CHID_21r */
   2717         soc_block_list[81],
   2718         soc_genreg,
   2719         1,
   2720         0,
   2721         0x95902,
   2722         0,
   2723         0,
   2724         4,
   2725         soc_JBCHCFG2_CHID_0r_fields,
   2726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2727         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2728         -1,
   2729         -1,
   2730     },
   2731 #endif /* chips */
   2732 
   2733 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2734     { /* SOC_REG_INT_JBCHCFG2_CHID_22r */
   2735         soc_block_list[81],
   2736         soc_genreg,
   2737         1,
   2738         0,
   2739         0x96902,
   2740         0,
   2741         0,
   2742         4,
   2743         soc_JBCHCFG2_CHID_0r_fields,
   2744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2745         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2746         -1,
   2747         -1,
   2748     },
   2749 #endif /* chips */
   2750 
   2751 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2752     { /* SOC_REG_INT_JBCHCFG2_CHID_23r */
   2753         soc_block_list[81],
   2754         soc_genreg,
   2755         1,
   2756         0,
   2757         0x97902,
   2758         0,
   2759         0,
   2760         4,
   2761         soc_JBCHCFG2_CHID_0r_fields,
   2762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2764         -1,
   2765         -1,
   2766     },
   2767 #endif /* chips */
   2768 
   2769 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2770     { /* SOC_REG_INT_JBCHCFG2_CHID_24r */
   2771         soc_block_list[81],
   2772         soc_genreg,
   2773         1,
   2774         0,
   2775         0x98902,
   2776         0,
   2777         0,
   2778         4,
   2779         soc_JBCHCFG2_CHID_0r_fields,
   2780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2782         -1,
   2783         -1,
   2784     },
   2785 #endif /* chips */
   2786 
   2787 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2788     { /* SOC_REG_INT_JBCHCFG2_CHID_25r */
   2789         soc_block_list[81],
   2790         soc_genreg,
   2791         1,
   2792         0,
   2793         0x99902,
   2794         0,
   2795         0,
   2796         4,
   2797         soc_JBCHCFG2_CHID_0r_fields,
   2798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2800         -1,
   2801         -1,
   2802     },
   2803 #endif /* chips */
   2804 
   2805 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2806     { /* SOC_REG_INT_JBCHCFG2_CHID_26r */
   2807         soc_block_list[81],
   2808         soc_genreg,
   2809         1,
   2810         0,
   2811         0x9a902,
   2812         0,
   2813         0,
   2814         4,
   2815         soc_JBCHCFG2_CHID_0r_fields,
   2816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2818         -1,
   2819         -1,
   2820     },
   2821 #endif /* chips */
   2822 
   2823 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2824     { /* SOC_REG_INT_JBCHCFG2_CHID_27r */
   2825         soc_block_list[81],
   2826         soc_genreg,
   2827         1,
   2828         0,
   2829         0x9b902,
   2830         0,
   2831         0,
   2832         4,
   2833         soc_JBCHCFG2_CHID_0r_fields,
   2834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2835         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2836         -1,
   2837         -1,
   2838     },
   2839 #endif /* chips */
   2840 
   2841 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2842     { /* SOC_REG_INT_JBCHCFG2_CHID_28r */
   2843         soc_block_list[81],
   2844         soc_genreg,
   2845         1,
   2846         0,
   2847         0x9c902,
   2848         0,
   2849         0,
   2850         4,
   2851         soc_JBCHCFG2_CHID_0r_fields,
   2852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2854         -1,
   2855         -1,
   2856     },
   2857 #endif /* chips */
   2858 
   2859 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2860     { /* SOC_REG_INT_JBCHCFG2_CHID_29r */
   2861         soc_block_list[81],
   2862         soc_genreg,
   2863         1,
   2864         0,
   2865         0x9d902,
   2866         0,
   2867         0,
   2868         4,
   2869         soc_JBCHCFG2_CHID_0r_fields,
   2870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2872         -1,
   2873         -1,
   2874     },
   2875 #endif /* chips */
   2876 
   2877 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2878     { /* SOC_REG_INT_JBCHCFG2_CHID_30r */
   2879         soc_block_list[81],
   2880         soc_genreg,
   2881         1,
   2882         0,
   2883         0x9e902,
   2884         0,
   2885         0,
   2886         4,
   2887         soc_JBCHCFG2_CHID_0r_fields,
   2888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2889         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2890         -1,
   2891         -1,
   2892     },
   2893 #endif /* chips */
   2894 
   2895 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2896     { /* SOC_REG_INT_JBCHCFG2_CHID_31r */
   2897         soc_block_list[81],
   2898         soc_genreg,
   2899         1,
   2900         0,
   2901         0x9f902,
   2902         0,
   2903         0,
   2904         4,
   2905         soc_JBCHCFG2_CHID_0r_fields,
   2906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2907         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2908         -1,
   2909         -1,
   2910     },
   2911 #endif /* chips */
   2912 
   2913 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2914     { /* SOC_REG_INT_JBCHCFG2_CHID_32r */
   2915         soc_block_list[81],
   2916         soc_genreg,
   2917         1,
   2918         0,
   2919         0xa0902,
   2920         0,
   2921         0,
   2922         4,
   2923         soc_JBCHCFG2_CHID_0r_fields,
   2924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2926         -1,
   2927         -1,
   2928     },
   2929 #endif /* chips */
   2930 
   2931 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2932     { /* SOC_REG_INT_JBCHCFG2_CHID_33r */
   2933         soc_block_list[81],
   2934         soc_genreg,
   2935         1,
   2936         0,
   2937         0xa1902,
   2938         0,
   2939         0,
   2940         4,
   2941         soc_JBCHCFG2_CHID_0r_fields,
   2942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2943         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2944         -1,
   2945         -1,
   2946     },
   2947 #endif /* chips */
   2948 
   2949 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2950     { /* SOC_REG_INT_JBCHCFG2_CHID_34r */
   2951         soc_block_list[81],
   2952         soc_genreg,
   2953         1,
   2954         0,
   2955         0xa2902,
   2956         0,
   2957         0,
   2958         4,
   2959         soc_JBCHCFG2_CHID_0r_fields,
   2960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2961         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2962         -1,
   2963         -1,
   2964     },
   2965 #endif /* chips */
   2966 
   2967 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2968     { /* SOC_REG_INT_JBCHCFG2_CHID_35r */
   2969         soc_block_list[81],
   2970         soc_genreg,
   2971         1,
   2972         0,
   2973         0xa3902,
   2974         0,
   2975         0,
   2976         4,
   2977         soc_JBCHCFG2_CHID_0r_fields,
   2978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2979         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2980         -1,
   2981         -1,
   2982     },
   2983 #endif /* chips */
   2984 
   2985 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2986     { /* SOC_REG_INT_JBCHCFG2_CHID_36r */
   2987         soc_block_list[81],
   2988         soc_genreg,
   2989         1,
   2990         0,
   2991         0xa4902,
   2992         0,
   2993         0,
   2994         4,
   2995         soc_JBCHCFG2_CHID_0r_fields,
   2996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2997         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2998         -1,
   2999         -1,
   3000     },
   3001 #endif /* chips */
   3002 
   3003 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3004     { /* SOC_REG_INT_JBCHCFG2_CHID_37r */
   3005         soc_block_list[81],
   3006         soc_genreg,
   3007         1,
   3008         0,
   3009         0xa5902,
   3010         0,
   3011         0,
   3012         4,
   3013         soc_JBCHCFG2_CHID_0r_fields,
   3014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3015         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3016         -1,
   3017         -1,
   3018     },
   3019 #endif /* chips */
   3020 
   3021 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3022     { /* SOC_REG_INT_JBCHCFG2_CHID_38r */
   3023         soc_block_list[81],
   3024         soc_genreg,
   3025         1,
   3026         0,
   3027         0xa6902,
   3028         0,
   3029         0,
   3030         4,
   3031         soc_JBCHCFG2_CHID_0r_fields,
   3032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3034         -1,
   3035         -1,
   3036     },
   3037 #endif /* chips */
   3038 
   3039 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3040     { /* SOC_REG_INT_JBCHCFG2_CHID_39r */
   3041         soc_block_list[81],
   3042         soc_genreg,
   3043         1,
   3044         0,
   3045         0xa7902,
   3046         0,
   3047         0,
   3048         4,
   3049         soc_JBCHCFG2_CHID_0r_fields,
   3050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3052         -1,
   3053         -1,
   3054     },
   3055 #endif /* chips */
   3056 
   3057 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3058     { /* SOC_REG_INT_JBCHCFG2_CHID_40r */
   3059         soc_block_list[81],
   3060         soc_genreg,
   3061         1,
   3062         0,
   3063         0xa8902,
   3064         0,
   3065         0,
   3066         4,
   3067         soc_JBCHCFG2_CHID_0r_fields,
   3068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3070         -1,
   3071         -1,
   3072     },
   3073 #endif /* chips */
   3074 
   3075 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3076     { /* SOC_REG_INT_JBCHCFG2_CHID_41r */
   3077         soc_block_list[81],
   3078         soc_genreg,
   3079         1,
   3080         0,
   3081         0xa9902,
   3082         0,
   3083         0,
   3084         4,
   3085         soc_JBCHCFG2_CHID_0r_fields,
   3086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3088         -1,
   3089         -1,
   3090     },
   3091 #endif /* chips */
   3092 
   3093 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3094     { /* SOC_REG_INT_JBCHCFG2_CHID_42r */
   3095         soc_block_list[81],
   3096         soc_genreg,
   3097         1,
   3098         0,
   3099         0xaa902,
   3100         0,
   3101         0,
   3102         4,
   3103         soc_JBCHCFG2_CHID_0r_fields,
   3104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3105         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3106         -1,
   3107         -1,
   3108     },
   3109 #endif /* chips */
   3110 
   3111 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3112     { /* SOC_REG_INT_JBCHCFG2_CHID_43r */
   3113         soc_block_list[81],
   3114         soc_genreg,
   3115         1,
   3116         0,
   3117         0xab902,
   3118         0,
   3119         0,
   3120         4,
   3121         soc_JBCHCFG2_CHID_0r_fields,
   3122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3124         -1,
   3125         -1,
   3126     },
   3127 #endif /* chips */
   3128 
   3129 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3130     { /* SOC_REG_INT_JBCHCFG2_CHID_44r */
   3131         soc_block_list[81],
   3132         soc_genreg,
   3133         1,
   3134         0,
   3135         0xac902,
   3136         0,
   3137         0,
   3138         4,
   3139         soc_JBCHCFG2_CHID_0r_fields,
   3140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3142         -1,
   3143         -1,
   3144     },
   3145 #endif /* chips */
   3146 
   3147 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3148     { /* SOC_REG_INT_JBCHCFG2_CHID_45r */
   3149         soc_block_list[81],
   3150         soc_genreg,
   3151         1,
   3152         0,
   3153         0xad902,
   3154         0,
   3155         0,
   3156         4,
   3157         soc_JBCHCFG2_CHID_0r_fields,
   3158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3160         -1,
   3161         -1,
   3162     },
   3163 #endif /* chips */
   3164 
   3165 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3166     { /* SOC_REG_INT_JBCHCFG2_CHID_46r */
   3167         soc_block_list[81],
   3168         soc_genreg,
   3169         1,
   3170         0,
   3171         0xae902,
   3172         0,
   3173         0,
   3174         4,
   3175         soc_JBCHCFG2_CHID_0r_fields,
   3176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3178         -1,
   3179         -1,
   3180     },
   3181 #endif /* chips */
   3182 
   3183 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3184     { /* SOC_REG_INT_JBCHCFG2_CHID_47r */
   3185         soc_block_list[81],
   3186         soc_genreg,
   3187         1,
   3188         0,
   3189         0xaf902,
   3190         0,
   3191         0,
   3192         4,
   3193         soc_JBCHCFG2_CHID_0r_fields,
   3194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3195         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3196         -1,
   3197         -1,
   3198     },
   3199 #endif /* chips */
   3200 
   3201 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3202     { /* SOC_REG_INT_JBCHCFG2_CHID_48r */
   3203         soc_block_list[81],
   3204         soc_genreg,
   3205         1,
   3206         0,
   3207         0xb0902,
   3208         0,
   3209         0,
   3210         4,
   3211         soc_JBCHCFG2_CHID_0r_fields,
   3212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3213         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3214         -1,
   3215         -1,
   3216     },
   3217 #endif /* chips */
   3218 
   3219 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3220     { /* SOC_REG_INT_JBCHCFG2_CHID_49r */
   3221         soc_block_list[81],
   3222         soc_genreg,
   3223         1,
   3224         0,
   3225         0xb1902,
   3226         0,
   3227         0,
   3228         4,
   3229         soc_JBCHCFG2_CHID_0r_fields,
   3230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3232         -1,
   3233         -1,
   3234     },
   3235 #endif /* chips */
   3236 
   3237 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3238     { /* SOC_REG_INT_JBCHCFG2_CHID_50r */
   3239         soc_block_list[81],
   3240         soc_genreg,
   3241         1,
   3242         0,
   3243         0xb2902,
   3244         0,
   3245         0,
   3246         4,
   3247         soc_JBCHCFG2_CHID_0r_fields,
   3248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3250         -1,
   3251         -1,
   3252     },
   3253 #endif /* chips */
   3254 
   3255 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3256     { /* SOC_REG_INT_JBCHCFG2_CHID_51r */
   3257         soc_block_list[81],
   3258         soc_genreg,
   3259         1,
   3260         0,
   3261         0xb3902,
   3262         0,
   3263         0,
   3264         4,
   3265         soc_JBCHCFG2_CHID_0r_fields,
   3266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3267         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3268         -1,
   3269         -1,
   3270     },
   3271 #endif /* chips */
   3272 
   3273 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3274     { /* SOC_REG_INT_JBCHCFG2_CHID_52r */
   3275         soc_block_list[81],
   3276         soc_genreg,
   3277         1,
   3278         0,
   3279         0xb4902,
   3280         0,
   3281         0,
   3282         4,
   3283         soc_JBCHCFG2_CHID_0r_fields,
   3284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3285         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3286         -1,
   3287         -1,
   3288     },
   3289 #endif /* chips */
   3290 
   3291 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3292     { /* SOC_REG_INT_JBCHCFG2_CHID_53r */
   3293         soc_block_list[81],
   3294         soc_genreg,
   3295         1,
   3296         0,
   3297         0xb5902,
   3298         0,
   3299         0,
   3300         4,
   3301         soc_JBCHCFG2_CHID_0r_fields,
   3302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3303         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3304         -1,
   3305         -1,
   3306     },
   3307 #endif /* chips */
   3308 
   3309 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3310     { /* SOC_REG_INT_JBCHCFG2_CHID_54r */
   3311         soc_block_list[81],
   3312         soc_genreg,
   3313         1,
   3314         0,
   3315         0xb6902,
   3316         0,
   3317         0,
   3318         4,
   3319         soc_JBCHCFG2_CHID_0r_fields,
   3320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3321         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3322         -1,
   3323         -1,
   3324     },
   3325 #endif /* chips */
   3326 
   3327 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3328     { /* SOC_REG_INT_JBCHCFG2_CHID_55r */
   3329         soc_block_list[81],
   3330         soc_genreg,
   3331         1,
   3332         0,
   3333         0xb7902,
   3334         0,
   3335         0,
   3336         4,
   3337         soc_JBCHCFG2_CHID_0r_fields,
   3338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3339         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3340         -1,
   3341         -1,
   3342     },
   3343 #endif /* chips */
   3344 
   3345 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3346     { /* SOC_REG_INT_JBCHCFG2_CHID_56r */
   3347         soc_block_list[81],
   3348         soc_genreg,
   3349         1,
   3350         0,
   3351         0xb8902,
   3352         0,
   3353         0,
   3354         4,
   3355         soc_JBCHCFG2_CHID_0r_fields,
   3356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3358         -1,
   3359         -1,
   3360     },
   3361 #endif /* chips */
   3362 
   3363 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3364     { /* SOC_REG_INT_JBCHCFG2_CHID_57r */
   3365         soc_block_list[81],
   3366         soc_genreg,
   3367         1,
   3368         0,
   3369         0xb9902,
   3370         0,
   3371         0,
   3372         4,
   3373         soc_JBCHCFG2_CHID_0r_fields,
   3374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3375         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3376         -1,
   3377         -1,
   3378     },
   3379 #endif /* chips */
   3380 
   3381 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3382     { /* SOC_REG_INT_JBCHCFG2_CHID_58r */
   3383         soc_block_list[81],
   3384         soc_genreg,
   3385         1,
   3386         0,
   3387         0xba902,
   3388         0,
   3389         0,
   3390         4,
   3391         soc_JBCHCFG2_CHID_0r_fields,
   3392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3393         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3394         -1,
   3395         -1,
   3396     },
   3397 #endif /* chips */
   3398 
   3399 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3400     { /* SOC_REG_INT_JBCHCFG2_CHID_59r */
   3401         soc_block_list[81],
   3402         soc_genreg,
   3403         1,
   3404         0,
   3405         0xbb902,
   3406         0,
   3407         0,
   3408         4,
   3409         soc_JBCHCFG2_CHID_0r_fields,
   3410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3411         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3412         -1,
   3413         -1,
   3414     },
   3415 #endif /* chips */
   3416 
   3417 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3418     { /* SOC_REG_INT_JBCHCFG2_CHID_60r */
   3419         soc_block_list[81],
   3420         soc_genreg,
   3421         1,
   3422         0,
   3423         0xbc902,
   3424         0,
   3425         0,
   3426         4,
   3427         soc_JBCHCFG2_CHID_0r_fields,
   3428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3429         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3430         -1,
   3431         -1,
   3432     },
   3433 #endif /* chips */
   3434 
   3435 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3436     { /* SOC_REG_INT_JBCHCFG2_CHID_61r */
   3437         soc_block_list[81],
   3438         soc_genreg,
   3439         1,
   3440         0,
   3441         0xbd902,
   3442         0,
   3443         0,
   3444         4,
   3445         soc_JBCHCFG2_CHID_0r_fields,
   3446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3448         -1,
   3449         -1,
   3450     },
   3451 #endif /* chips */
   3452 
   3453 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3454     { /* SOC_REG_INT_JBCHCFG2_CHID_62r */
   3455         soc_block_list[81],
   3456         soc_genreg,
   3457         1,
   3458         0,
   3459         0xbe902,
   3460         0,
   3461         0,
   3462         4,
   3463         soc_JBCHCFG2_CHID_0r_fields,
   3464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3465         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3466         -1,
   3467         -1,
   3468     },
   3469 #endif /* chips */
   3470 
   3471 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3472     { /* SOC_REG_INT_JBCHCFG2_CHID_63r */
   3473         soc_block_list[81],
   3474         soc_genreg,
   3475         1,
   3476         0,
   3477         0xbf902,
   3478         0,
   3479         0,
   3480         4,
   3481         soc_JBCHCFG2_CHID_0r_fields,
   3482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3484         -1,
   3485         -1,
   3486     },
   3487 #endif /* chips */
   3488 
   3489 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3490     { /* SOC_REG_INT_JBCSTAT_CHID_0r */
   3491         soc_block_list[81],
   3492         soc_genreg,
   3493         1,
   3494         0,
   3495         0x8091e,
   3496         SOC_REG_FLAG_RO,
   3497         0,
   3498         3,
   3499         soc_JBCSTAT_CHID_0r_fields,
   3500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3502         -1,
   3503         -1,
   3504     },
   3505 #endif /* chips */
   3506 
   3507 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3508     { /* SOC_REG_INT_JBCSTAT_CHID_1r */
   3509         soc_block_list[81],
   3510         soc_genreg,
   3511         1,
   3512         0,
   3513         0x8191e,
   3514         SOC_REG_FLAG_RO,
   3515         0,
   3516         3,
   3517         soc_JBCSTAT_CHID_0r_fields,
   3518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3519         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3520         -1,
   3521         -1,
   3522     },
   3523 #endif /* chips */
   3524 
   3525 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3526     { /* SOC_REG_INT_JBCSTAT_CHID_2r */
   3527         soc_block_list[81],
   3528         soc_genreg,
   3529         1,
   3530         0,
   3531         0x8291e,
   3532         SOC_REG_FLAG_RO,
   3533         0,
   3534         3,
   3535         soc_JBCSTAT_CHID_0r_fields,
   3536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3538         -1,
   3539         -1,
   3540     },
   3541 #endif /* chips */
   3542 
   3543 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3544     { /* SOC_REG_INT_JBCSTAT_CHID_3r */
   3545         soc_block_list[81],
   3546         soc_genreg,
   3547         1,
   3548         0,
   3549         0x8391e,
   3550         SOC_REG_FLAG_RO,
   3551         0,
   3552         3,
   3553         soc_JBCSTAT_CHID_0r_fields,
   3554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3556         -1,
   3557         -1,
   3558     },
   3559 #endif /* chips */
   3560 
   3561 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3562     { /* SOC_REG_INT_JBCSTAT_CHID_4r */
   3563         soc_block_list[81],
   3564         soc_genreg,
   3565         1,
   3566         0,
   3567         0x8491e,
   3568         SOC_REG_FLAG_RO,
   3569         0,
   3570         3,
   3571         soc_JBCSTAT_CHID_0r_fields,
   3572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3574         -1,
   3575         -1,
   3576     },
   3577 #endif /* chips */
   3578 
   3579 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3580     { /* SOC_REG_INT_JBCSTAT_CHID_5r */
   3581         soc_block_list[81],
   3582         soc_genreg,
   3583         1,
   3584         0,
   3585         0x8591e,
   3586         SOC_REG_FLAG_RO,
   3587         0,
   3588         3,
   3589         soc_JBCSTAT_CHID_0r_fields,
   3590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3592         -1,
   3593         -1,
   3594     },
   3595 #endif /* chips */
   3596 
   3597 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3598     { /* SOC_REG_INT_JBCSTAT_CHID_6r */
   3599         soc_block_list[81],
   3600         soc_genreg,
   3601         1,
   3602         0,
   3603         0x8691e,
   3604         SOC_REG_FLAG_RO,
   3605         0,
   3606         3,
   3607         soc_JBCSTAT_CHID_0r_fields,
   3608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3609         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3610         -1,
   3611         -1,
   3612     },
   3613 #endif /* chips */
   3614 
   3615 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3616     { /* SOC_REG_INT_JBCSTAT_CHID_7r */
   3617         soc_block_list[81],
   3618         soc_genreg,
   3619         1,
   3620         0,
   3621         0x8791e,
   3622         SOC_REG_FLAG_RO,
   3623         0,
   3624         3,
   3625         soc_JBCSTAT_CHID_0r_fields,
   3626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3628         -1,
   3629         -1,
   3630     },
   3631 #endif /* chips */
   3632 
   3633 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3634     { /* SOC_REG_INT_JBCSTAT_CHID_8r */
   3635         soc_block_list[81],
   3636         soc_genreg,
   3637         1,
   3638         0,
   3639         0x8891e,
   3640         SOC_REG_FLAG_RO,
   3641         0,
   3642         3,
   3643         soc_JBCSTAT_CHID_0r_fields,
   3644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3646         -1,
   3647         -1,
   3648     },
   3649 #endif /* chips */
   3650 
   3651 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3652     { /* SOC_REG_INT_JBCSTAT_CHID_9r */
   3653         soc_block_list[81],
   3654         soc_genreg,
   3655         1,
   3656         0,
   3657         0x8991e,
   3658         SOC_REG_FLAG_RO,
   3659         0,
   3660         3,
   3661         soc_JBCSTAT_CHID_0r_fields,
   3662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3663         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3664         -1,
   3665         -1,
   3666     },
   3667 #endif /* chips */
   3668 
   3669 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3670     { /* SOC_REG_INT_JBCSTAT_CHID_10r */
   3671         soc_block_list[81],
   3672         soc_genreg,
   3673         1,
   3674         0,
   3675         0x8a91e,
   3676         SOC_REG_FLAG_RO,
   3677         0,
   3678         3,
   3679         soc_JBCSTAT_CHID_0r_fields,
   3680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3682         -1,
   3683         -1,
   3684     },
   3685 #endif /* chips */
   3686 
   3687 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3688     { /* SOC_REG_INT_JBCSTAT_CHID_11r */
   3689         soc_block_list[81],
   3690         soc_genreg,
   3691         1,
   3692         0,
   3693         0x8b91e,
   3694         SOC_REG_FLAG_RO,
   3695         0,
   3696         3,
   3697         soc_JBCSTAT_CHID_0r_fields,
   3698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3700         -1,
   3701         -1,
   3702     },
   3703 #endif /* chips */
   3704 
   3705 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3706     { /* SOC_REG_INT_JBCSTAT_CHID_12r */
   3707         soc_block_list[81],
   3708         soc_genreg,
   3709         1,
   3710         0,
   3711         0x8c91e,
   3712         SOC_REG_FLAG_RO,
   3713         0,
   3714         3,
   3715         soc_JBCSTAT_CHID_0r_fields,
   3716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3718         -1,
   3719         -1,
   3720     },
   3721 #endif /* chips */
   3722 
   3723 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3724     { /* SOC_REG_INT_JBCSTAT_CHID_13r */
   3725         soc_block_list[81],
   3726         soc_genreg,
   3727         1,
   3728         0,
   3729         0x8d91e,
   3730         SOC_REG_FLAG_RO,
   3731         0,
   3732         3,
   3733         soc_JBCSTAT_CHID_0r_fields,
   3734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3736         -1,
   3737         -1,
   3738     },
   3739 #endif /* chips */
   3740 
   3741 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3742     { /* SOC_REG_INT_JBCSTAT_CHID_14r */
   3743         soc_block_list[81],
   3744         soc_genreg,
   3745         1,
   3746         0,
   3747         0x8e91e,
   3748         SOC_REG_FLAG_RO,
   3749         0,
   3750         3,
   3751         soc_JBCSTAT_CHID_0r_fields,
   3752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3754         -1,
   3755         -1,
   3756     },
   3757 #endif /* chips */
   3758 
   3759 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3760     { /* SOC_REG_INT_JBCSTAT_CHID_15r */
   3761         soc_block_list[81],
   3762         soc_genreg,
   3763         1,
   3764         0,
   3765         0x8f91e,
   3766         SOC_REG_FLAG_RO,
   3767         0,
   3768         3,
   3769         soc_JBCSTAT_CHID_0r_fields,
   3770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3772         -1,
   3773         -1,
   3774     },
   3775 #endif /* chips */
   3776 
   3777 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3778     { /* SOC_REG_INT_JBCSTAT_CHID_16r */
   3779         soc_block_list[81],
   3780         soc_genreg,
   3781         1,
   3782         0,
   3783         0x9091e,
   3784         SOC_REG_FLAG_RO,
   3785         0,
   3786         3,
   3787         soc_JBCSTAT_CHID_0r_fields,
   3788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3790         -1,
   3791         -1,
   3792     },
   3793 #endif /* chips */
   3794 
   3795 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3796     { /* SOC_REG_INT_JBCSTAT_CHID_17r */
   3797         soc_block_list[81],
   3798         soc_genreg,
   3799         1,
   3800         0,
   3801         0x9191e,
   3802         SOC_REG_FLAG_RO,
   3803         0,
   3804         3,
   3805         soc_JBCSTAT_CHID_0r_fields,
   3806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3808         -1,
   3809         -1,
   3810     },
   3811 #endif /* chips */
   3812 
   3813 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3814     { /* SOC_REG_INT_JBCSTAT_CHID_18r */
   3815         soc_block_list[81],
   3816         soc_genreg,
   3817         1,
   3818         0,
   3819         0x9291e,
   3820         SOC_REG_FLAG_RO,
   3821         0,
   3822         3,
   3823         soc_JBCSTAT_CHID_0r_fields,
   3824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3825         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3826         -1,
   3827         -1,
   3828     },
   3829 #endif /* chips */
   3830 
   3831 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3832     { /* SOC_REG_INT_JBCSTAT_CHID_19r */
   3833         soc_block_list[81],
   3834         soc_genreg,
   3835         1,
   3836         0,
   3837         0x9391e,
   3838         SOC_REG_FLAG_RO,
   3839         0,
   3840         3,
   3841         soc_JBCSTAT_CHID_0r_fields,
   3842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3843         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3844         -1,
   3845         -1,
   3846     },
   3847 #endif /* chips */
   3848 
   3849 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3850     { /* SOC_REG_INT_JBCSTAT_CHID_20r */
   3851         soc_block_list[81],
   3852         soc_genreg,
   3853         1,
   3854         0,
   3855         0x9491e,
   3856         SOC_REG_FLAG_RO,
   3857         0,
   3858         3,
   3859         soc_JBCSTAT_CHID_0r_fields,
   3860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3861         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3862         -1,
   3863         -1,
   3864     },
   3865 #endif /* chips */
   3866 
   3867 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3868     { /* SOC_REG_INT_JBCSTAT_CHID_21r */
   3869         soc_block_list[81],
   3870         soc_genreg,
   3871         1,
   3872         0,
   3873         0x9591e,
   3874         SOC_REG_FLAG_RO,
   3875         0,
   3876         3,
   3877         soc_JBCSTAT_CHID_0r_fields,
   3878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3879         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3880         -1,
   3881         -1,
   3882     },
   3883 #endif /* chips */
   3884 
   3885 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3886     { /* SOC_REG_INT_JBCSTAT_CHID_22r */
   3887         soc_block_list[81],
   3888         soc_genreg,
   3889         1,
   3890         0,
   3891         0x9691e,
   3892         SOC_REG_FLAG_RO,
   3893         0,
   3894         3,
   3895         soc_JBCSTAT_CHID_0r_fields,
   3896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3898         -1,
   3899         -1,
   3900     },
   3901 #endif /* chips */
   3902 
   3903 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3904     { /* SOC_REG_INT_JBCSTAT_CHID_23r */
   3905         soc_block_list[81],
   3906         soc_genreg,
   3907         1,
   3908         0,
   3909         0x9791e,
   3910         SOC_REG_FLAG_RO,
   3911         0,
   3912         3,
   3913         soc_JBCSTAT_CHID_0r_fields,
   3914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3916         -1,
   3917         -1,
   3918     },
   3919 #endif /* chips */
   3920 
   3921 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3922     { /* SOC_REG_INT_JBCSTAT_CHID_24r */
   3923         soc_block_list[81],
   3924         soc_genreg,
   3925         1,
   3926         0,
   3927         0x9891e,
   3928         SOC_REG_FLAG_RO,
   3929         0,
   3930         3,
   3931         soc_JBCSTAT_CHID_0r_fields,
   3932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3934         -1,
   3935         -1,
   3936     },
   3937 #endif /* chips */
   3938 
   3939 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3940     { /* SOC_REG_INT_JBCSTAT_CHID_25r */
   3941         soc_block_list[81],
   3942         soc_genreg,
   3943         1,
   3944         0,
   3945         0x9991e,
   3946         SOC_REG_FLAG_RO,
   3947         0,
   3948         3,
   3949         soc_JBCSTAT_CHID_0r_fields,
   3950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3952         -1,
   3953         -1,
   3954     },
   3955 #endif /* chips */
   3956 
   3957 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3958     { /* SOC_REG_INT_JBCSTAT_CHID_26r */
   3959         soc_block_list[81],
   3960         soc_genreg,
   3961         1,
   3962         0,
   3963         0x9a91e,
   3964         SOC_REG_FLAG_RO,
   3965         0,
   3966         3,
   3967         soc_JBCSTAT_CHID_0r_fields,
   3968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3970         -1,
   3971         -1,
   3972     },
   3973 #endif /* chips */
   3974 
   3975 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3976     { /* SOC_REG_INT_JBCSTAT_CHID_27r */
   3977         soc_block_list[81],
   3978         soc_genreg,
   3979         1,
   3980         0,
   3981         0x9b91e,
   3982         SOC_REG_FLAG_RO,
   3983         0,
   3984         3,
   3985         soc_JBCSTAT_CHID_0r_fields,
   3986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3987         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3988         -1,
   3989         -1,
   3990     },
   3991 #endif /* chips */
   3992 
   3993 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3994     { /* SOC_REG_INT_JBCSTAT_CHID_28r */
   3995         soc_block_list[81],
   3996         soc_genreg,
   3997         1,
   3998         0,
   3999         0x9c91e,
   4000         SOC_REG_FLAG_RO,
   4001         0,
   4002         3,
   4003         soc_JBCSTAT_CHID_0r_fields,
   4004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4006         -1,
   4007         -1,
   4008     },
   4009 #endif /* chips */
   4010 
   4011 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4012     { /* SOC_REG_INT_JBCSTAT_CHID_29r */
   4013         soc_block_list[81],
   4014         soc_genreg,
   4015         1,
   4016         0,
   4017         0x9d91e,
   4018         SOC_REG_FLAG_RO,
   4019         0,
   4020         3,
   4021         soc_JBCSTAT_CHID_0r_fields,
   4022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4023         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4024         -1,
   4025         -1,
   4026     },
   4027 #endif /* chips */
   4028 
   4029 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4030     { /* SOC_REG_INT_JBCSTAT_CHID_30r */
   4031         soc_block_list[81],
   4032         soc_genreg,
   4033         1,
   4034         0,
   4035         0x9e91e,
   4036         SOC_REG_FLAG_RO,
   4037         0,
   4038         3,
   4039         soc_JBCSTAT_CHID_0r_fields,
   4040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4041         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4042         -1,
   4043         -1,
   4044     },
   4045 #endif /* chips */
   4046 
   4047 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4048     { /* SOC_REG_INT_JBCSTAT_CHID_31r */
   4049         soc_block_list[81],
   4050         soc_genreg,
   4051         1,
   4052         0,
   4053         0x9f91e,
   4054         SOC_REG_FLAG_RO,
   4055         0,
   4056         3,
   4057         soc_JBCSTAT_CHID_0r_fields,
   4058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4059         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4060         -1,
   4061         -1,
   4062     },
   4063 #endif /* chips */
   4064 
   4065 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4066     { /* SOC_REG_INT_JBCSTAT_CHID_32r */
   4067         soc_block_list[81],
   4068         soc_genreg,
   4069         1,
   4070         0,
   4071         0xa091e,
   4072         SOC_REG_FLAG_RO,
   4073         0,
   4074         3,
   4075         soc_JBCSTAT_CHID_0r_fields,
   4076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4077         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4078         -1,
   4079         -1,
   4080     },
   4081 #endif /* chips */
   4082 
   4083 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4084     { /* SOC_REG_INT_JBCSTAT_CHID_33r */
   4085         soc_block_list[81],
   4086         soc_genreg,
   4087         1,
   4088         0,
   4089         0xa191e,
   4090         SOC_REG_FLAG_RO,
   4091         0,
   4092         3,
   4093         soc_JBCSTAT_CHID_0r_fields,
   4094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4095         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4096         -1,
   4097         -1,
   4098     },
   4099 #endif /* chips */
   4100 
   4101 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4102     { /* SOC_REG_INT_JBCSTAT_CHID_34r */
   4103         soc_block_list[81],
   4104         soc_genreg,
   4105         1,
   4106         0,
   4107         0xa291e,
   4108         SOC_REG_FLAG_RO,
   4109         0,
   4110         3,
   4111         soc_JBCSTAT_CHID_0r_fields,
   4112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4113         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4114         -1,
   4115         -1,
   4116     },
   4117 #endif /* chips */
   4118 
   4119 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4120     { /* SOC_REG_INT_JBCSTAT_CHID_35r */
   4121         soc_block_list[81],
   4122         soc_genreg,
   4123         1,
   4124         0,
   4125         0xa391e,
   4126         SOC_REG_FLAG_RO,
   4127         0,
   4128         3,
   4129         soc_JBCSTAT_CHID_0r_fields,
   4130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4131         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4132         -1,
   4133         -1,
   4134     },
   4135 #endif /* chips */
   4136 
   4137 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4138     { /* SOC_REG_INT_JBCSTAT_CHID_36r */
   4139         soc_block_list[81],
   4140         soc_genreg,
   4141         1,
   4142         0,
   4143         0xa491e,
   4144         SOC_REG_FLAG_RO,
   4145         0,
   4146         3,
   4147         soc_JBCSTAT_CHID_0r_fields,
   4148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4150         -1,
   4151         -1,
   4152     },
   4153 #endif /* chips */
   4154 
   4155 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4156     { /* SOC_REG_INT_JBCSTAT_CHID_37r */
   4157         soc_block_list[81],
   4158         soc_genreg,
   4159         1,
   4160         0,
   4161         0xa591e,
   4162         SOC_REG_FLAG_RO,
   4163         0,
   4164         3,
   4165         soc_JBCSTAT_CHID_0r_fields,
   4166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4167         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4168         -1,
   4169         -1,
   4170     },
   4171 #endif /* chips */
   4172 
   4173 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4174     { /* SOC_REG_INT_JBCSTAT_CHID_38r */
   4175         soc_block_list[81],
   4176         soc_genreg,
   4177         1,
   4178         0,
   4179         0xa691e,
   4180         SOC_REG_FLAG_RO,
   4181         0,
   4182         3,
   4183         soc_JBCSTAT_CHID_0r_fields,
   4184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4186         -1,
   4187         -1,
   4188     },
   4189 #endif /* chips */
   4190 
   4191 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4192     { /* SOC_REG_INT_JBCSTAT_CHID_39r */
   4193         soc_block_list[81],
   4194         soc_genreg,
   4195         1,
   4196         0,
   4197         0xa791e,
   4198         SOC_REG_FLAG_RO,
   4199         0,
   4200         3,
   4201         soc_JBCSTAT_CHID_0r_fields,
   4202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4203         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4204         -1,
   4205         -1,
   4206     },
   4207 #endif /* chips */
   4208 
   4209 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4210     { /* SOC_REG_INT_JBCSTAT_CHID_40r */
   4211         soc_block_list[81],
   4212         soc_genreg,
   4213         1,
   4214         0,
   4215         0xa891e,
   4216         SOC_REG_FLAG_RO,
   4217         0,
   4218         3,
   4219         soc_JBCSTAT_CHID_0r_fields,
   4220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4221         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4222         -1,
   4223         -1,
   4224     },
   4225 #endif /* chips */
   4226 
   4227 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4228     { /* SOC_REG_INT_JBCSTAT_CHID_41r */
   4229         soc_block_list[81],
   4230         soc_genreg,
   4231         1,
   4232         0,
   4233         0xa991e,
   4234         SOC_REG_FLAG_RO,
   4235         0,
   4236         3,
   4237         soc_JBCSTAT_CHID_0r_fields,
   4238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4239         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4240         -1,
   4241         -1,
   4242     },
   4243 #endif /* chips */
   4244 
   4245 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4246     { /* SOC_REG_INT_JBCSTAT_CHID_42r */
   4247         soc_block_list[81],
   4248         soc_genreg,
   4249         1,
   4250         0,
   4251         0xaa91e,
   4252         SOC_REG_FLAG_RO,
   4253         0,
   4254         3,
   4255         soc_JBCSTAT_CHID_0r_fields,
   4256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4257         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4258         -1,
   4259         -1,
   4260     },
   4261 #endif /* chips */
   4262 
   4263 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4264     { /* SOC_REG_INT_JBCSTAT_CHID_43r */
   4265         soc_block_list[81],
   4266         soc_genreg,
   4267         1,
   4268         0,
   4269         0xab91e,
   4270         SOC_REG_FLAG_RO,
   4271         0,
   4272         3,
   4273         soc_JBCSTAT_CHID_0r_fields,
   4274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4275         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4276         -1,
   4277         -1,
   4278     },
   4279 #endif /* chips */
   4280 
   4281 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4282     { /* SOC_REG_INT_JBCSTAT_CHID_44r */
   4283         soc_block_list[81],
   4284         soc_genreg,
   4285         1,
   4286         0,
   4287         0xac91e,
   4288         SOC_REG_FLAG_RO,
   4289         0,
   4290         3,
   4291         soc_JBCSTAT_CHID_0r_fields,
   4292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4293         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4294         -1,
   4295         -1,
   4296     },
   4297 #endif /* chips */
   4298 
   4299 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4300     { /* SOC_REG_INT_JBCSTAT_CHID_45r */
   4301         soc_block_list[81],
   4302         soc_genreg,
   4303         1,
   4304         0,
   4305         0xad91e,
   4306         SOC_REG_FLAG_RO,
   4307         0,
   4308         3,
   4309         soc_JBCSTAT_CHID_0r_fields,
   4310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4312         -1,
   4313         -1,
   4314     },
   4315 #endif /* chips */
   4316 
   4317 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4318     { /* SOC_REG_INT_JBCSTAT_CHID_46r */
   4319         soc_block_list[81],
   4320         soc_genreg,
   4321         1,
   4322         0,
   4323         0xae91e,
   4324         SOC_REG_FLAG_RO,
   4325         0,
   4326         3,
   4327         soc_JBCSTAT_CHID_0r_fields,
   4328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4329         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4330         -1,
   4331         -1,
   4332     },
   4333 #endif /* chips */
   4334 
   4335 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4336     { /* SOC_REG_INT_JBCSTAT_CHID_47r */
   4337         soc_block_list[81],
   4338         soc_genreg,
   4339         1,
   4340         0,
   4341         0xaf91e,
   4342         SOC_REG_FLAG_RO,
   4343         0,
   4344         3,
   4345         soc_JBCSTAT_CHID_0r_fields,
   4346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4347         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4348         -1,
   4349         -1,
   4350     },
   4351 #endif /* chips */
   4352 
   4353 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4354     { /* SOC_REG_INT_JBCSTAT_CHID_48r */
   4355         soc_block_list[81],
   4356         soc_genreg,
   4357         1,
   4358         0,
   4359         0xb091e,
   4360         SOC_REG_FLAG_RO,
   4361         0,
   4362         3,
   4363         soc_JBCSTAT_CHID_0r_fields,
   4364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4365         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4366         -1,
   4367         -1,
   4368     },
   4369 #endif /* chips */
   4370 
   4371 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4372     { /* SOC_REG_INT_JBCSTAT_CHID_49r */
   4373         soc_block_list[81],
   4374         soc_genreg,
   4375         1,
   4376         0,
   4377         0xb191e,
   4378         SOC_REG_FLAG_RO,
   4379         0,
   4380         3,
   4381         soc_JBCSTAT_CHID_0r_fields,
   4382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4384         -1,
   4385         -1,
   4386     },
   4387 #endif /* chips */
   4388 
   4389 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4390     { /* SOC_REG_INT_JBCSTAT_CHID_50r */
   4391         soc_block_list[81],
   4392         soc_genreg,
   4393         1,
   4394         0,
   4395         0xb291e,
   4396         SOC_REG_FLAG_RO,
   4397         0,
   4398         3,
   4399         soc_JBCSTAT_CHID_0r_fields,
   4400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4402         -1,
   4403         -1,
   4404     },
   4405 #endif /* chips */
   4406 
   4407 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4408     { /* SOC_REG_INT_JBCSTAT_CHID_51r */
   4409         soc_block_list[81],
   4410         soc_genreg,
   4411         1,
   4412         0,
   4413         0xb391e,
   4414         SOC_REG_FLAG_RO,
   4415         0,
   4416         3,
   4417         soc_JBCSTAT_CHID_0r_fields,
   4418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4419         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4420         -1,
   4421         -1,
   4422     },
   4423 #endif /* chips */
   4424 
   4425 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4426     { /* SOC_REG_INT_JBCSTAT_CHID_52r */
   4427         soc_block_list[81],
   4428         soc_genreg,
   4429         1,
   4430         0,
   4431         0xb491e,
   4432         SOC_REG_FLAG_RO,
   4433         0,
   4434         3,
   4435         soc_JBCSTAT_CHID_0r_fields,
   4436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4438         -1,
   4439         -1,
   4440     },
   4441 #endif /* chips */
   4442 
   4443 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4444     { /* SOC_REG_INT_JBCSTAT_CHID_53r */
   4445         soc_block_list[81],
   4446         soc_genreg,
   4447         1,
   4448         0,
   4449         0xb591e,
   4450         SOC_REG_FLAG_RO,
   4451         0,
   4452         3,
   4453         soc_JBCSTAT_CHID_0r_fields,
   4454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4455         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4456         -1,
   4457         -1,
   4458     },
   4459 #endif /* chips */
   4460 
   4461 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4462     { /* SOC_REG_INT_JBCSTAT_CHID_54r */
   4463         soc_block_list[81],
   4464         soc_genreg,
   4465         1,
   4466         0,
   4467         0xb691e,
   4468         SOC_REG_FLAG_RO,
   4469         0,
   4470         3,
   4471         soc_JBCSTAT_CHID_0r_fields,
   4472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4473         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4474         -1,
   4475         -1,
   4476     },
   4477 #endif /* chips */
   4478 
   4479 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4480     { /* SOC_REG_INT_JBCSTAT_CHID_55r */
   4481         soc_block_list[81],
   4482         soc_genreg,
   4483         1,
   4484         0,
   4485         0xb791e,
   4486         SOC_REG_FLAG_RO,
   4487         0,
   4488         3,
   4489         soc_JBCSTAT_CHID_0r_fields,
   4490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4491         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4492         -1,
   4493         -1,
   4494     },
   4495 #endif /* chips */
   4496 
   4497 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4498     { /* SOC_REG_INT_JBCSTAT_CHID_56r */
   4499         soc_block_list[81],
   4500         soc_genreg,
   4501         1,
   4502         0,
   4503         0xb891e,
   4504         SOC_REG_FLAG_RO,
   4505         0,
   4506         3,
   4507         soc_JBCSTAT_CHID_0r_fields,
   4508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4509         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4510         -1,
   4511         -1,
   4512     },
   4513 #endif /* chips */
   4514 
   4515 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4516     { /* SOC_REG_INT_JBCSTAT_CHID_57r */
   4517         soc_block_list[81],
   4518         soc_genreg,
   4519         1,
   4520         0,
   4521         0xb991e,
   4522         SOC_REG_FLAG_RO,
   4523         0,
   4524         3,
   4525         soc_JBCSTAT_CHID_0r_fields,
   4526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4527         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4528         -1,
   4529         -1,
   4530     },
   4531 #endif /* chips */
   4532 
   4533 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4534     { /* SOC_REG_INT_JBCSTAT_CHID_58r */
   4535         soc_block_list[81],
   4536         soc_genreg,
   4537         1,
   4538         0,
   4539         0xba91e,
   4540         SOC_REG_FLAG_RO,
   4541         0,
   4542         3,
   4543         soc_JBCSTAT_CHID_0r_fields,
   4544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4545         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4546         -1,
   4547         -1,
   4548     },
   4549 #endif /* chips */
   4550 
   4551 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4552     { /* SOC_REG_INT_JBCSTAT_CHID_59r */
   4553         soc_block_list[81],
   4554         soc_genreg,
   4555         1,
   4556         0,
   4557         0xbb91e,
   4558         SOC_REG_FLAG_RO,
   4559         0,
   4560         3,
   4561         soc_JBCSTAT_CHID_0r_fields,
   4562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4564         -1,
   4565         -1,
   4566     },
   4567 #endif /* chips */
   4568 
   4569 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4570     { /* SOC_REG_INT_JBCSTAT_CHID_60r */
   4571         soc_block_list[81],
   4572         soc_genreg,
   4573         1,
   4574         0,
   4575         0xbc91e,
   4576         SOC_REG_FLAG_RO,
   4577         0,
   4578         3,
   4579         soc_JBCSTAT_CHID_0r_fields,
   4580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4582         -1,
   4583         -1,
   4584     },
   4585 #endif /* chips */
   4586 
   4587 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4588     { /* SOC_REG_INT_JBCSTAT_CHID_61r */
   4589         soc_block_list[81],
   4590         soc_genreg,
   4591         1,
   4592         0,
   4593         0xbd91e,
   4594         SOC_REG_FLAG_RO,
   4595         0,
   4596         3,
   4597         soc_JBCSTAT_CHID_0r_fields,
   4598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4600         -1,
   4601         -1,
   4602     },
   4603 #endif /* chips */
   4604 
   4605 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4606     { /* SOC_REG_INT_JBCSTAT_CHID_62r */
   4607         soc_block_list[81],
   4608         soc_genreg,
   4609         1,
   4610         0,
   4611         0xbe91e,
   4612         SOC_REG_FLAG_RO,
   4613         0,
   4614         3,
   4615         soc_JBCSTAT_CHID_0r_fields,
   4616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4617         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4618         -1,
   4619         -1,
   4620     },
   4621 #endif /* chips */
   4622 
   4623 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4624     { /* SOC_REG_INT_JBCSTAT_CHID_63r */
   4625         soc_block_list[81],
   4626         soc_genreg,
   4627         1,
   4628         0,
   4629         0xbf91e,
   4630         SOC_REG_FLAG_RO,
   4631         0,
   4632         3,
   4633         soc_JBCSTAT_CHID_0r_fields,
   4634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4635         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4636         -1,
   4637         -1,
   4638     },
   4639 #endif /* chips */
   4640 
   4641 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4642     { /* SOC_REG_INT_JBDEPC_TCID_0r */
   4643         soc_block_list[81],
   4644         soc_genreg,
   4645         1,
   4646         0,
   4647         0x80c40,
   4648         SOC_REG_FLAG_RO,
   4649         0,
   4650         1,
   4651         soc_JBDEPC_TCID_0r_fields,
   4652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4654         -1,
   4655         -1,
   4656     },
   4657 #endif /* chips */
   4658 
   4659 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4660     { /* SOC_REG_INT_JBDEPC_TCID_1r */
   4661         soc_block_list[81],
   4662         soc_genreg,
   4663         1,
   4664         0,
   4665         0x81c40,
   4666         SOC_REG_FLAG_RO,
   4667         0,
   4668         1,
   4669         soc_JBDEPC_TCID_0r_fields,
   4670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4671         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4672         -1,
   4673         -1,
   4674     },
   4675 #endif /* chips */
   4676 
   4677 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4678     { /* SOC_REG_INT_JBDEPC_TCID_2r */
   4679         soc_block_list[81],
   4680         soc_genreg,
   4681         1,
   4682         0,
   4683         0x82c40,
   4684         SOC_REG_FLAG_RO,
   4685         0,
   4686         1,
   4687         soc_JBDEPC_TCID_0r_fields,
   4688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4690         -1,
   4691         -1,
   4692     },
   4693 #endif /* chips */
   4694 
   4695 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4696     { /* SOC_REG_INT_JBDEPC_TCID_3r */
   4697         soc_block_list[81],
   4698         soc_genreg,
   4699         1,
   4700         0,
   4701         0x83c40,
   4702         SOC_REG_FLAG_RO,
   4703         0,
   4704         1,
   4705         soc_JBDEPC_TCID_0r_fields,
   4706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4707         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4708         -1,
   4709         -1,
   4710     },
   4711 #endif /* chips */
   4712 
   4713 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4714     { /* SOC_REG_INT_JBDEPC_TCID_4r */
   4715         soc_block_list[81],
   4716         soc_genreg,
   4717         1,
   4718         0,
   4719         0x84c40,
   4720         SOC_REG_FLAG_RO,
   4721         0,
   4722         1,
   4723         soc_JBDEPC_TCID_0r_fields,
   4724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4725         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4726         -1,
   4727         -1,
   4728     },
   4729 #endif /* chips */
   4730 
   4731 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4732     { /* SOC_REG_INT_JBDEPC_TCID_5r */
   4733         soc_block_list[81],
   4734         soc_genreg,
   4735         1,
   4736         0,
   4737         0x85c40,
   4738         SOC_REG_FLAG_RO,
   4739         0,
   4740         1,
   4741         soc_JBDEPC_TCID_0r_fields,
   4742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4744         -1,
   4745         -1,
   4746     },
   4747 #endif /* chips */
   4748 
   4749 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4750     { /* SOC_REG_INT_JBDEPC_TCID_6r */
   4751         soc_block_list[81],
   4752         soc_genreg,
   4753         1,
   4754         0,
   4755         0x86c40,
   4756         SOC_REG_FLAG_RO,
   4757         0,
   4758         1,
   4759         soc_JBDEPC_TCID_0r_fields,
   4760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4762         -1,
   4763         -1,
   4764     },
   4765 #endif /* chips */
   4766 
   4767 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4768     { /* SOC_REG_INT_JBDEPC_TCID_7r */
   4769         soc_block_list[81],
   4770         soc_genreg,
   4771         1,
   4772         0,
   4773         0x87c40,
   4774         SOC_REG_FLAG_RO,
   4775         0,
   4776         1,
   4777         soc_JBDEPC_TCID_0r_fields,
   4778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4779         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4780         -1,
   4781         -1,
   4782     },
   4783 #endif /* chips */
   4784 
   4785 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4786     { /* SOC_REG_INT_JBDEPC_TCID_8r */
   4787         soc_block_list[81],
   4788         soc_genreg,
   4789         1,
   4790         0,
   4791         0x88c40,
   4792         SOC_REG_FLAG_RO,
   4793         0,
   4794         1,
   4795         soc_JBDEPC_TCID_0r_fields,
   4796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4797         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4798         -1,
   4799         -1,
   4800     },
   4801 #endif /* chips */
   4802 
   4803 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4804     { /* SOC_REG_INT_JBDEPC_TCID_9r */
   4805         soc_block_list[81],
   4806         soc_genreg,
   4807         1,
   4808         0,
   4809         0x89c40,
   4810         SOC_REG_FLAG_RO,
   4811         0,
   4812         1,
   4813         soc_JBDEPC_TCID_0r_fields,
   4814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4815         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4816         -1,
   4817         -1,
   4818     },
   4819 #endif /* chips */
   4820 
   4821 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4822     { /* SOC_REG_INT_JBDEPC_TCID_10r */
   4823         soc_block_list[81],
   4824         soc_genreg,
   4825         1,
   4826         0,
   4827         0x8ac40,
   4828         SOC_REG_FLAG_RO,
   4829         0,
   4830         1,
   4831         soc_JBDEPC_TCID_0r_fields,
   4832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4833         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4834         -1,
   4835         -1,
   4836     },
   4837 #endif /* chips */
   4838 
   4839 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4840     { /* SOC_REG_INT_JBDEPC_TCID_11r */
   4841         soc_block_list[81],
   4842         soc_genreg,
   4843         1,
   4844         0,
   4845         0x8bc40,
   4846         SOC_REG_FLAG_RO,
   4847         0,
   4848         1,
   4849         soc_JBDEPC_TCID_0r_fields,
   4850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4851         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4852         -1,
   4853         -1,
   4854     },
   4855 #endif /* chips */
   4856 
   4857 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4858     { /* SOC_REG_INT_JBDEPC_TCID_12r */
   4859         soc_block_list[81],
   4860         soc_genreg,
   4861         1,
   4862         0,
   4863         0x8cc40,
   4864         SOC_REG_FLAG_RO,
   4865         0,
   4866         1,
   4867         soc_JBDEPC_TCID_0r_fields,
   4868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4870         -1,
   4871         -1,
   4872     },
   4873 #endif /* chips */
   4874 
   4875 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4876     { /* SOC_REG_INT_JBDEPC_TCID_13r */
   4877         soc_block_list[81],
   4878         soc_genreg,
   4879         1,
   4880         0,
   4881         0x8dc40,
   4882         SOC_REG_FLAG_RO,
   4883         0,
   4884         1,
   4885         soc_JBDEPC_TCID_0r_fields,
   4886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4887         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4888         -1,
   4889         -1,
   4890     },
   4891 #endif /* chips */
   4892 
   4893 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4894     { /* SOC_REG_INT_JBDEPC_TCID_14r */
   4895         soc_block_list[81],
   4896         soc_genreg,
   4897         1,
   4898         0,
   4899         0x8ec40,
   4900         SOC_REG_FLAG_RO,
   4901         0,
   4902         1,
   4903         soc_JBDEPC_TCID_0r_fields,
   4904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4905         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4906         -1,
   4907         -1,
   4908     },
   4909 #endif /* chips */
   4910 
   4911 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4912     { /* SOC_REG_INT_JBDEPC_TCID_15r */
   4913         soc_block_list[81],
   4914         soc_genreg,
   4915         1,
   4916         0,
   4917         0x8fc40,
   4918         SOC_REG_FLAG_RO,
   4919         0,
   4920         1,
   4921         soc_JBDEPC_TCID_0r_fields,
   4922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4923         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4924         -1,
   4925         -1,
   4926     },
   4927 #endif /* chips */
   4928 
   4929 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4930     { /* SOC_REG_INT_JBDMAX1_CHID_0r */
   4931         soc_block_list[81],
   4932         soc_genreg,
   4933         1,
   4934         0,
   4935         0x80914,
   4936         SOC_REG_FLAG_RO,
   4937         0,
   4938         1,
   4939         soc_JBDMAX1_CHID_0r_fields,
   4940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4941         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4942         -1,
   4943         -1,
   4944     },
   4945 #endif /* chips */
   4946 
   4947 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4948     { /* SOC_REG_INT_JBDMAX1_CHID_1r */
   4949         soc_block_list[81],
   4950         soc_genreg,
   4951         1,
   4952         0,
   4953         0x81914,
   4954         SOC_REG_FLAG_RO,
   4955         0,
   4956         1,
   4957         soc_JBDMAX1_CHID_0r_fields,
   4958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4959         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4960         -1,
   4961         -1,
   4962     },
   4963 #endif /* chips */
   4964 
   4965 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4966     { /* SOC_REG_INT_JBDMAX1_CHID_2r */
   4967         soc_block_list[81],
   4968         soc_genreg,
   4969         1,
   4970         0,
   4971         0x82914,
   4972         SOC_REG_FLAG_RO,
   4973         0,
   4974         1,
   4975         soc_JBDMAX1_CHID_0r_fields,
   4976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4977         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4978         -1,
   4979         -1,
   4980     },
   4981 #endif /* chips */
   4982 
   4983 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4984     { /* SOC_REG_INT_JBDMAX1_CHID_3r */
   4985         soc_block_list[81],
   4986         soc_genreg,
   4987         1,
   4988         0,
   4989         0x83914,
   4990         SOC_REG_FLAG_RO,
   4991         0,
   4992         1,
   4993         soc_JBDMAX1_CHID_0r_fields,
   4994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4995         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4996         -1,
   4997         -1,
   4998     },
   4999 #endif /* chips */
   5000 
   5001 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5002     { /* SOC_REG_INT_JBDMAX1_CHID_4r */
   5003         soc_block_list[81],
   5004         soc_genreg,
   5005         1,
   5006         0,
   5007         0x84914,
   5008         SOC_REG_FLAG_RO,
   5009         0,
   5010         1,
   5011         soc_JBDMAX1_CHID_0r_fields,
   5012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5013         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5014         -1,
   5015         -1,
   5016     },
   5017 #endif /* chips */
   5018 
   5019 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5020     { /* SOC_REG_INT_JBDMAX1_CHID_5r */
   5021         soc_block_list[81],
   5022         soc_genreg,
   5023         1,
   5024         0,
   5025         0x85914,
   5026         SOC_REG_FLAG_RO,
   5027         0,
   5028         1,
   5029         soc_JBDMAX1_CHID_0r_fields,
   5030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5032         -1,
   5033         -1,
   5034     },
   5035 #endif /* chips */
   5036 
   5037 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5038     { /* SOC_REG_INT_JBDMAX1_CHID_6r */
   5039         soc_block_list[81],
   5040         soc_genreg,
   5041         1,
   5042         0,
   5043         0x86914,
   5044         SOC_REG_FLAG_RO,
   5045         0,
   5046         1,
   5047         soc_JBDMAX1_CHID_0r_fields,
   5048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5050         -1,
   5051         -1,
   5052     },
   5053 #endif /* chips */
   5054 
   5055 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5056     { /* SOC_REG_INT_JBDMAX1_CHID_7r */
   5057         soc_block_list[81],
   5058         soc_genreg,
   5059         1,
   5060         0,
   5061         0x87914,
   5062         SOC_REG_FLAG_RO,
   5063         0,
   5064         1,
   5065         soc_JBDMAX1_CHID_0r_fields,
   5066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5067         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5068         -1,
   5069         -1,
   5070     },
   5071 #endif /* chips */
   5072 
   5073 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5074     { /* SOC_REG_INT_JBDMAX1_CHID_8r */
   5075         soc_block_list[81],
   5076         soc_genreg,
   5077         1,
   5078         0,
   5079         0x88914,
   5080         SOC_REG_FLAG_RO,
   5081         0,
   5082         1,
   5083         soc_JBDMAX1_CHID_0r_fields,
   5084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5086         -1,
   5087         -1,
   5088     },
   5089 #endif /* chips */
   5090 
   5091 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5092     { /* SOC_REG_INT_JBDMAX1_CHID_9r */
   5093         soc_block_list[81],
   5094         soc_genreg,
   5095         1,
   5096         0,
   5097         0x89914,
   5098         SOC_REG_FLAG_RO,
   5099         0,
   5100         1,
   5101         soc_JBDMAX1_CHID_0r_fields,
   5102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5103         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5104         -1,
   5105         -1,
   5106     },
   5107 #endif /* chips */
   5108 
   5109 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5110     { /* SOC_REG_INT_JBDMAX1_CHID_10r */
   5111         soc_block_list[81],
   5112         soc_genreg,
   5113         1,
   5114         0,
   5115         0x8a914,
   5116         SOC_REG_FLAG_RO,
   5117         0,
   5118         1,
   5119         soc_JBDMAX1_CHID_0r_fields,
   5120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5121         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5122         -1,
   5123         -1,
   5124     },
   5125 #endif /* chips */
   5126 
   5127 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5128     { /* SOC_REG_INT_JBDMAX1_CHID_11r */
   5129         soc_block_list[81],
   5130         soc_genreg,
   5131         1,
   5132         0,
   5133         0x8b914,
   5134         SOC_REG_FLAG_RO,
   5135         0,
   5136         1,
   5137         soc_JBDMAX1_CHID_0r_fields,
   5138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5139         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5140         -1,
   5141         -1,
   5142     },
   5143 #endif /* chips */
   5144 
   5145 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5146     { /* SOC_REG_INT_JBDMAX1_CHID_12r */
   5147         soc_block_list[81],
   5148         soc_genreg,
   5149         1,
   5150         0,
   5151         0x8c914,
   5152         SOC_REG_FLAG_RO,
   5153         0,
   5154         1,
   5155         soc_JBDMAX1_CHID_0r_fields,
   5156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5157         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5158         -1,
   5159         -1,
   5160     },
   5161 #endif /* chips */
   5162 
   5163 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5164     { /* SOC_REG_INT_JBDMAX1_CHID_13r */
   5165         soc_block_list[81],
   5166         soc_genreg,
   5167         1,
   5168         0,
   5169         0x8d914,
   5170         SOC_REG_FLAG_RO,
   5171         0,
   5172         1,
   5173         soc_JBDMAX1_CHID_0r_fields,
   5174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5175         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5176         -1,
   5177         -1,
   5178     },
   5179 #endif /* chips */
   5180 
   5181 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5182     { /* SOC_REG_INT_JBDMAX1_CHID_14r */
   5183         soc_block_list[81],
   5184         soc_genreg,
   5185         1,
   5186         0,
   5187         0x8e914,
   5188         SOC_REG_FLAG_RO,
   5189         0,
   5190         1,
   5191         soc_JBDMAX1_CHID_0r_fields,
   5192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5193         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5194         -1,
   5195         -1,
   5196     },
   5197 #endif /* chips */
   5198 
   5199 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5200     { /* SOC_REG_INT_JBDMAX1_CHID_15r */
   5201         soc_block_list[81],
   5202         soc_genreg,
   5203         1,
   5204         0,
   5205         0x8f914,
   5206         SOC_REG_FLAG_RO,
   5207         0,
   5208         1,
   5209         soc_JBDMAX1_CHID_0r_fields,
   5210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5212         -1,
   5213         -1,
   5214     },
   5215 #endif /* chips */
   5216 
   5217 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5218     { /* SOC_REG_INT_JBDMAX1_CHID_16r */
   5219         soc_block_list[81],
   5220         soc_genreg,
   5221         1,
   5222         0,
   5223         0x90914,
   5224         SOC_REG_FLAG_RO,
   5225         0,
   5226         1,
   5227         soc_JBDMAX1_CHID_0r_fields,
   5228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5229         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5230         -1,
   5231         -1,
   5232     },
   5233 #endif /* chips */
   5234 
   5235 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5236     { /* SOC_REG_INT_JBDMAX1_CHID_17r */
   5237         soc_block_list[81],
   5238         soc_genreg,
   5239         1,
   5240         0,
   5241         0x91914,
   5242         SOC_REG_FLAG_RO,
   5243         0,
   5244         1,
   5245         soc_JBDMAX1_CHID_0r_fields,
   5246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5247         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5248         -1,
   5249         -1,
   5250     },
   5251 #endif /* chips */
   5252 
   5253 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5254     { /* SOC_REG_INT_JBDMAX1_CHID_18r */
   5255         soc_block_list[81],
   5256         soc_genreg,
   5257         1,
   5258         0,
   5259         0x92914,
   5260         SOC_REG_FLAG_RO,
   5261         0,
   5262         1,
   5263         soc_JBDMAX1_CHID_0r_fields,
   5264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5265         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5266         -1,
   5267         -1,
   5268     },
   5269 #endif /* chips */
   5270 
   5271 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5272     { /* SOC_REG_INT_JBDMAX1_CHID_19r */
   5273         soc_block_list[81],
   5274         soc_genreg,
   5275         1,
   5276         0,
   5277         0x93914,
   5278         SOC_REG_FLAG_RO,
   5279         0,
   5280         1,
   5281         soc_JBDMAX1_CHID_0r_fields,
   5282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5284         -1,
   5285         -1,
   5286     },
   5287 #endif /* chips */
   5288 
   5289 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5290     { /* SOC_REG_INT_JBDMAX1_CHID_20r */
   5291         soc_block_list[81],
   5292         soc_genreg,
   5293         1,
   5294         0,
   5295         0x94914,
   5296         SOC_REG_FLAG_RO,
   5297         0,
   5298         1,
   5299         soc_JBDMAX1_CHID_0r_fields,
   5300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5302         -1,
   5303         -1,
   5304     },
   5305 #endif /* chips */
   5306 
   5307 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5308     { /* SOC_REG_INT_JBDMAX1_CHID_21r */
   5309         soc_block_list[81],
   5310         soc_genreg,
   5311         1,
   5312         0,
   5313         0x95914,
   5314         SOC_REG_FLAG_RO,
   5315         0,
   5316         1,
   5317         soc_JBDMAX1_CHID_0r_fields,
   5318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5319         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5320         -1,
   5321         -1,
   5322     },
   5323 #endif /* chips */
   5324 
   5325 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5326     { /* SOC_REG_INT_JBDMAX1_CHID_22r */
   5327         soc_block_list[81],
   5328         soc_genreg,
   5329         1,
   5330         0,
   5331         0x96914,
   5332         SOC_REG_FLAG_RO,
   5333         0,
   5334         1,
   5335         soc_JBDMAX1_CHID_0r_fields,
   5336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5337         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5338         -1,
   5339         -1,
   5340     },
   5341 #endif /* chips */
   5342 
   5343 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5344     { /* SOC_REG_INT_JBDMAX1_CHID_23r */
   5345         soc_block_list[81],
   5346         soc_genreg,
   5347         1,
   5348         0,
   5349         0x97914,
   5350         SOC_REG_FLAG_RO,
   5351         0,
   5352         1,
   5353         soc_JBDMAX1_CHID_0r_fields,
   5354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5355         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5356         -1,
   5357         -1,
   5358     },
   5359 #endif /* chips */
   5360 
   5361 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5362     { /* SOC_REG_INT_JBDMAX1_CHID_24r */
   5363         soc_block_list[81],
   5364         soc_genreg,
   5365         1,
   5366         0,
   5367         0x98914,
   5368         SOC_REG_FLAG_RO,
   5369         0,
   5370         1,
   5371         soc_JBDMAX1_CHID_0r_fields,
   5372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5373         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5374         -1,
   5375         -1,
   5376     },
   5377 #endif /* chips */
   5378 
   5379 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5380     { /* SOC_REG_INT_JBDMAX1_CHID_25r */
   5381         soc_block_list[81],
   5382         soc_genreg,
   5383         1,
   5384         0,
   5385         0x99914,
   5386         SOC_REG_FLAG_RO,
   5387         0,
   5388         1,
   5389         soc_JBDMAX1_CHID_0r_fields,
   5390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5391         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5392         -1,
   5393         -1,
   5394     },
   5395 #endif /* chips */
   5396 
   5397 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5398     { /* SOC_REG_INT_JBDMAX1_CHID_26r */
   5399         soc_block_list[81],
   5400         soc_genreg,
   5401         1,
   5402         0,
   5403         0x9a914,
   5404         SOC_REG_FLAG_RO,
   5405         0,
   5406         1,
   5407         soc_JBDMAX1_CHID_0r_fields,
   5408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5409         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5410         -1,
   5411         -1,
   5412     },
   5413 #endif /* chips */
   5414 
   5415 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5416     { /* SOC_REG_INT_JBDMAX1_CHID_27r */
   5417         soc_block_list[81],
   5418         soc_genreg,
   5419         1,
   5420         0,
   5421         0x9b914,
   5422         SOC_REG_FLAG_RO,
   5423         0,
   5424         1,
   5425         soc_JBDMAX1_CHID_0r_fields,
   5426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5427         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5428         -1,
   5429         -1,
   5430     },
   5431 #endif /* chips */
   5432 
   5433 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5434     { /* SOC_REG_INT_JBDMAX1_CHID_28r */
   5435         soc_block_list[81],
   5436         soc_genreg,
   5437         1,
   5438         0,
   5439         0x9c914,
   5440         SOC_REG_FLAG_RO,
   5441         0,
   5442         1,
   5443         soc_JBDMAX1_CHID_0r_fields,
   5444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5446         -1,
   5447         -1,
   5448     },
   5449 #endif /* chips */
   5450 
   5451 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5452     { /* SOC_REG_INT_JBDMAX1_CHID_29r */
   5453         soc_block_list[81],
   5454         soc_genreg,
   5455         1,
   5456         0,
   5457         0x9d914,
   5458         SOC_REG_FLAG_RO,
   5459         0,
   5460         1,
   5461         soc_JBDMAX1_CHID_0r_fields,
   5462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5464         -1,
   5465         -1,
   5466     },
   5467 #endif /* chips */
   5468 
   5469 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5470     { /* SOC_REG_INT_JBDMAX1_CHID_30r */
   5471         soc_block_list[81],
   5472         soc_genreg,
   5473         1,
   5474         0,
   5475         0x9e914,
   5476         SOC_REG_FLAG_RO,
   5477         0,
   5478         1,
   5479         soc_JBDMAX1_CHID_0r_fields,
   5480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5482         -1,
   5483         -1,
   5484     },
   5485 #endif /* chips */
   5486 
   5487 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5488     { /* SOC_REG_INT_JBDMAX1_CHID_31r */
   5489         soc_block_list[81],
   5490         soc_genreg,
   5491         1,
   5492         0,
   5493         0x9f914,
   5494         SOC_REG_FLAG_RO,
   5495         0,
   5496         1,
   5497         soc_JBDMAX1_CHID_0r_fields,
   5498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5499         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5500         -1,
   5501         -1,
   5502     },
   5503 #endif /* chips */
   5504 
   5505 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5506     { /* SOC_REG_INT_JBDMAX1_CHID_32r */
   5507         soc_block_list[81],
   5508         soc_genreg,
   5509         1,
   5510         0,
   5511         0xa0914,
   5512         SOC_REG_FLAG_RO,
   5513         0,
   5514         1,
   5515         soc_JBDMAX1_CHID_0r_fields,
   5516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5517         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5518         -1,
   5519         -1,
   5520     },
   5521 #endif /* chips */
   5522 
   5523 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5524     { /* SOC_REG_INT_JBDMAX1_CHID_33r */
   5525         soc_block_list[81],
   5526         soc_genreg,
   5527         1,
   5528         0,
   5529         0xa1914,
   5530         SOC_REG_FLAG_RO,
   5531         0,
   5532         1,
   5533         soc_JBDMAX1_CHID_0r_fields,
   5534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5535         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5536         -1,
   5537         -1,
   5538     },
   5539 #endif /* chips */
   5540 
   5541 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5542     { /* SOC_REG_INT_JBDMAX1_CHID_34r */
   5543         soc_block_list[81],
   5544         soc_genreg,
   5545         1,
   5546         0,
   5547         0xa2914,
   5548         SOC_REG_FLAG_RO,
   5549         0,
   5550         1,
   5551         soc_JBDMAX1_CHID_0r_fields,
   5552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5554         -1,
   5555         -1,
   5556     },
   5557 #endif /* chips */
   5558 
   5559 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5560     { /* SOC_REG_INT_JBDMAX1_CHID_35r */
   5561         soc_block_list[81],
   5562         soc_genreg,
   5563         1,
   5564         0,
   5565         0xa3914,
   5566         SOC_REG_FLAG_RO,
   5567         0,
   5568         1,
   5569         soc_JBDMAX1_CHID_0r_fields,
   5570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5572         -1,
   5573         -1,
   5574     },
   5575 #endif /* chips */
   5576 
   5577 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5578     { /* SOC_REG_INT_JBDMAX1_CHID_36r */
   5579         soc_block_list[81],
   5580         soc_genreg,
   5581         1,
   5582         0,
   5583         0xa4914,
   5584         SOC_REG_FLAG_RO,
   5585         0,
   5586         1,
   5587         soc_JBDMAX1_CHID_0r_fields,
   5588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5589         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5590         -1,
   5591         -1,
   5592     },
   5593 #endif /* chips */
   5594 
   5595 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5596     { /* SOC_REG_INT_JBDMAX1_CHID_37r */
   5597         soc_block_list[81],
   5598         soc_genreg,
   5599         1,
   5600         0,
   5601         0xa5914,
   5602         SOC_REG_FLAG_RO,
   5603         0,
   5604         1,
   5605         soc_JBDMAX1_CHID_0r_fields,
   5606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5607         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5608         -1,
   5609         -1,
   5610     },
   5611 #endif /* chips */
   5612 
   5613 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5614     { /* SOC_REG_INT_JBDMAX1_CHID_38r */
   5615         soc_block_list[81],
   5616         soc_genreg,
   5617         1,
   5618         0,
   5619         0xa6914,
   5620         SOC_REG_FLAG_RO,
   5621         0,
   5622         1,
   5623         soc_JBDMAX1_CHID_0r_fields,
   5624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5625         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5626         -1,
   5627         -1,
   5628     },
   5629 #endif /* chips */
   5630 
   5631 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5632     { /* SOC_REG_INT_JBDMAX1_CHID_39r */
   5633         soc_block_list[81],
   5634         soc_genreg,
   5635         1,
   5636         0,
   5637         0xa7914,
   5638         SOC_REG_FLAG_RO,
   5639         0,
   5640         1,
   5641         soc_JBDMAX1_CHID_0r_fields,
   5642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5643         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5644         -1,
   5645         -1,
   5646     },
   5647 #endif /* chips */
   5648 
   5649 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5650     { /* SOC_REG_INT_JBDMAX1_CHID_40r */
   5651         soc_block_list[81],
   5652         soc_genreg,
   5653         1,
   5654         0,
   5655         0xa8914,
   5656         SOC_REG_FLAG_RO,
   5657         0,
   5658         1,
   5659         soc_JBDMAX1_CHID_0r_fields,
   5660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5661         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5662         -1,
   5663         -1,
   5664     },
   5665 #endif /* chips */
   5666 
   5667 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5668     { /* SOC_REG_INT_JBDMAX1_CHID_41r */
   5669         soc_block_list[81],
   5670         soc_genreg,
   5671         1,
   5672         0,
   5673         0xa9914,
   5674         SOC_REG_FLAG_RO,
   5675         0,
   5676         1,
   5677         soc_JBDMAX1_CHID_0r_fields,
   5678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5679         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5680         -1,
   5681         -1,
   5682     },
   5683 #endif /* chips */
   5684 
   5685 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5686     { /* SOC_REG_INT_JBDMAX1_CHID_42r */
   5687         soc_block_list[81],
   5688         soc_genreg,
   5689         1,
   5690         0,
   5691         0xaa914,
   5692         SOC_REG_FLAG_RO,
   5693         0,
   5694         1,
   5695         soc_JBDMAX1_CHID_0r_fields,
   5696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5697         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5698         -1,
   5699         -1,
   5700     },
   5701 #endif /* chips */
   5702 
   5703 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5704     { /* SOC_REG_INT_JBDMAX1_CHID_43r */
   5705         soc_block_list[81],
   5706         soc_genreg,
   5707         1,
   5708         0,
   5709         0xab914,
   5710         SOC_REG_FLAG_RO,
   5711         0,
   5712         1,
   5713         soc_JBDMAX1_CHID_0r_fields,
   5714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5715         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5716         -1,
   5717         -1,
   5718     },
   5719 #endif /* chips */
   5720 
   5721 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5722     { /* SOC_REG_INT_JBDMAX1_CHID_44r */
   5723         soc_block_list[81],
   5724         soc_genreg,
   5725         1,
   5726         0,
   5727         0xac914,
   5728         SOC_REG_FLAG_RO,
   5729         0,
   5730         1,
   5731         soc_JBDMAX1_CHID_0r_fields,
   5732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5734         -1,
   5735         -1,
   5736     },
   5737 #endif /* chips */
   5738 
   5739 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5740     { /* SOC_REG_INT_JBDMAX1_CHID_45r */
   5741         soc_block_list[81],
   5742         soc_genreg,
   5743         1,
   5744         0,
   5745         0xad914,
   5746         SOC_REG_FLAG_RO,
   5747         0,
   5748         1,
   5749         soc_JBDMAX1_CHID_0r_fields,
   5750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5751         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5752         -1,
   5753         -1,
   5754     },
   5755 #endif /* chips */
   5756 
   5757 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5758     { /* SOC_REG_INT_JBDMAX1_CHID_46r */
   5759         soc_block_list[81],
   5760         soc_genreg,
   5761         1,
   5762         0,
   5763         0xae914,
   5764         SOC_REG_FLAG_RO,
   5765         0,
   5766         1,
   5767         soc_JBDMAX1_CHID_0r_fields,
   5768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5769         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5770         -1,
   5771         -1,
   5772     },
   5773 #endif /* chips */
   5774 
   5775 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5776     { /* SOC_REG_INT_JBDMAX1_CHID_47r */
   5777         soc_block_list[81],
   5778         soc_genreg,
   5779         1,
   5780         0,
   5781         0xaf914,
   5782         SOC_REG_FLAG_RO,
   5783         0,
   5784         1,
   5785         soc_JBDMAX1_CHID_0r_fields,
   5786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5787         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5788         -1,
   5789         -1,
   5790     },
   5791 #endif /* chips */
   5792 
   5793 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5794     { /* SOC_REG_INT_JBDMAX1_CHID_48r */
   5795         soc_block_list[81],
   5796         soc_genreg,
   5797         1,
   5798         0,
   5799         0xb0914,
   5800         SOC_REG_FLAG_RO,
   5801         0,
   5802         1,
   5803         soc_JBDMAX1_CHID_0r_fields,
   5804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5805         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5806         -1,
   5807         -1,
   5808     },
   5809 #endif /* chips */
   5810 
   5811 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5812     { /* SOC_REG_INT_JBDMAX1_CHID_49r */
   5813         soc_block_list[81],
   5814         soc_genreg,
   5815         1,
   5816         0,
   5817         0xb1914,
   5818         SOC_REG_FLAG_RO,
   5819         0,
   5820         1,
   5821         soc_JBDMAX1_CHID_0r_fields,
   5822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5823         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5824         -1,
   5825         -1,
   5826     },
   5827 #endif /* chips */
   5828 
   5829 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5830     { /* SOC_REG_INT_JBDMAX1_CHID_50r */
   5831         soc_block_list[81],
   5832         soc_genreg,
   5833         1,
   5834         0,
   5835         0xb2914,
   5836         SOC_REG_FLAG_RO,
   5837         0,
   5838         1,
   5839         soc_JBDMAX1_CHID_0r_fields,
   5840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5841         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5842         -1,
   5843         -1,
   5844     },
   5845 #endif /* chips */
   5846 
   5847 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5848     { /* SOC_REG_INT_JBDMAX1_CHID_51r */
   5849         soc_block_list[81],
   5850         soc_genreg,
   5851         1,
   5852         0,
   5853         0xb3914,
   5854         SOC_REG_FLAG_RO,
   5855         0,
   5856         1,
   5857         soc_JBDMAX1_CHID_0r_fields,
   5858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5859         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5860         -1,
   5861         -1,
   5862     },
   5863 #endif /* chips */
   5864 
   5865 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5866     { /* SOC_REG_INT_JBDMAX1_CHID_52r */
   5867         soc_block_list[81],
   5868         soc_genreg,
   5869         1,
   5870         0,
   5871         0xb4914,
   5872         SOC_REG_FLAG_RO,
   5873         0,
   5874         1,
   5875         soc_JBDMAX1_CHID_0r_fields,
   5876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5877         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5878         -1,
   5879         -1,
   5880     },
   5881 #endif /* chips */
   5882 
   5883 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5884     { /* SOC_REG_INT_JBDMAX1_CHID_53r */
   5885         soc_block_list[81],
   5886         soc_genreg,
   5887         1,
   5888         0,
   5889         0xb5914,
   5890         SOC_REG_FLAG_RO,
   5891         0,
   5892         1,
   5893         soc_JBDMAX1_CHID_0r_fields,
   5894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5895         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5896         -1,
   5897         -1,
   5898     },
   5899 #endif /* chips */
   5900 
   5901 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5902     { /* SOC_REG_INT_JBDMAX1_CHID_54r */
   5903         soc_block_list[81],
   5904         soc_genreg,
   5905         1,
   5906         0,
   5907         0xb6914,
   5908         SOC_REG_FLAG_RO,
   5909         0,
   5910         1,
   5911         soc_JBDMAX1_CHID_0r_fields,
   5912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5913         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5914         -1,
   5915         -1,
   5916     },
   5917 #endif /* chips */
   5918 
   5919 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5920     { /* SOC_REG_INT_JBDMAX1_CHID_55r */
   5921         soc_block_list[81],
   5922         soc_genreg,
   5923         1,
   5924         0,
   5925         0xb7914,
   5926         SOC_REG_FLAG_RO,
   5927         0,
   5928         1,
   5929         soc_JBDMAX1_CHID_0r_fields,
   5930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5931         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5932         -1,
   5933         -1,
   5934     },
   5935 #endif /* chips */
   5936 
   5937 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5938     { /* SOC_REG_INT_JBDMAX1_CHID_56r */
   5939         soc_block_list[81],
   5940         soc_genreg,
   5941         1,
   5942         0,
   5943         0xb8914,
   5944         SOC_REG_FLAG_RO,
   5945         0,
   5946         1,
   5947         soc_JBDMAX1_CHID_0r_fields,
   5948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5949         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5950         -1,
   5951         -1,
   5952     },
   5953 #endif /* chips */
   5954 
   5955 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5956     { /* SOC_REG_INT_JBDMAX1_CHID_57r */
   5957         soc_block_list[81],
   5958         soc_genreg,
   5959         1,
   5960         0,
   5961         0xb9914,
   5962         SOC_REG_FLAG_RO,
   5963         0,
   5964         1,
   5965         soc_JBDMAX1_CHID_0r_fields,
   5966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5967         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5968         -1,
   5969         -1,
   5970     },
   5971 #endif /* chips */
   5972 
   5973 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5974     { /* SOC_REG_INT_JBDMAX1_CHID_58r */
   5975         soc_block_list[81],
   5976         soc_genreg,
   5977         1,
   5978         0,
   5979         0xba914,
   5980         SOC_REG_FLAG_RO,
   5981         0,
   5982         1,
   5983         soc_JBDMAX1_CHID_0r_fields,
   5984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5985         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5986         -1,
   5987         -1,
   5988     },
   5989 #endif /* chips */
   5990 
   5991 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5992     { /* SOC_REG_INT_JBDMAX1_CHID_59r */
   5993         soc_block_list[81],
   5994         soc_genreg,
   5995         1,
   5996         0,
   5997         0xbb914,
   5998         SOC_REG_FLAG_RO,
   5999         0,
   6000         1,
   6001         soc_JBDMAX1_CHID_0r_fields,
   6002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6003         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6004         -1,
   6005         -1,
   6006     },
   6007 #endif /* chips */
   6008 
   6009 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6010     { /* SOC_REG_INT_JBDMAX1_CHID_60r */
   6011         soc_block_list[81],
   6012         soc_genreg,
   6013         1,
   6014         0,
   6015         0xbc914,
   6016         SOC_REG_FLAG_RO,
   6017         0,
   6018         1,
   6019         soc_JBDMAX1_CHID_0r_fields,
   6020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6021         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6022         -1,
   6023         -1,
   6024     },
   6025 #endif /* chips */
   6026 
   6027 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6028     { /* SOC_REG_INT_JBDMAX1_CHID_61r */
   6029         soc_block_list[81],
   6030         soc_genreg,
   6031         1,
   6032         0,
   6033         0xbd914,
   6034         SOC_REG_FLAG_RO,
   6035         0,
   6036         1,
   6037         soc_JBDMAX1_CHID_0r_fields,
   6038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6040         -1,
   6041         -1,
   6042     },
   6043 #endif /* chips */
   6044 
   6045 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6046     { /* SOC_REG_INT_JBDMAX1_CHID_62r */
   6047         soc_block_list[81],
   6048         soc_genreg,
   6049         1,
   6050         0,
   6051         0xbe914,
   6052         SOC_REG_FLAG_RO,
   6053         0,
   6054         1,
   6055         soc_JBDMAX1_CHID_0r_fields,
   6056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6057         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6058         -1,
   6059         -1,
   6060     },
   6061 #endif /* chips */
   6062 
   6063 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6064     { /* SOC_REG_INT_JBDMAX1_CHID_63r */
   6065         soc_block_list[81],
   6066         soc_genreg,
   6067         1,
   6068         0,
   6069         0xbf914,
   6070         SOC_REG_FLAG_RO,
   6071         0,
   6072         1,
   6073         soc_JBDMAX1_CHID_0r_fields,
   6074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6075         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6076         -1,
   6077         -1,
   6078     },
   6079 #endif /* chips */
   6080 
   6081 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6082     { /* SOC_REG_INT_JBDMAX2_CHID_0r */
   6083         soc_block_list[81],
   6084         soc_genreg,
   6085         1,
   6086         0,
   6087         0x80916,
   6088         SOC_REG_FLAG_RO,
   6089         0,
   6090         1,
   6091         soc_JBDMAX1_CHID_0r_fields,
   6092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6093         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6094         -1,
   6095         -1,
   6096     },
   6097 #endif /* chips */
   6098 
   6099 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6100     { /* SOC_REG_INT_JBDMAX2_CHID_1r */
   6101         soc_block_list[81],
   6102         soc_genreg,
   6103         1,
   6104         0,
   6105         0x81916,
   6106         SOC_REG_FLAG_RO,
   6107         0,
   6108         1,
   6109         soc_JBDMAX1_CHID_0r_fields,
   6110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6112         -1,
   6113         -1,
   6114     },
   6115 #endif /* chips */
   6116 
   6117 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6118     { /* SOC_REG_INT_JBDMAX2_CHID_2r */
   6119         soc_block_list[81],
   6120         soc_genreg,
   6121         1,
   6122         0,
   6123         0x82916,
   6124         SOC_REG_FLAG_RO,
   6125         0,
   6126         1,
   6127         soc_JBDMAX1_CHID_0r_fields,
   6128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6129         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6130         -1,
   6131         -1,
   6132     },
   6133 #endif /* chips */
   6134 
   6135 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6136     { /* SOC_REG_INT_JBDMAX2_CHID_3r */
   6137         soc_block_list[81],
   6138         soc_genreg,
   6139         1,
   6140         0,
   6141         0x83916,
   6142         SOC_REG_FLAG_RO,
   6143         0,
   6144         1,
   6145         soc_JBDMAX1_CHID_0r_fields,
   6146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6148         -1,
   6149         -1,
   6150     },
   6151 #endif /* chips */
   6152 
   6153 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6154     { /* SOC_REG_INT_JBDMAX2_CHID_4r */
   6155         soc_block_list[81],
   6156         soc_genreg,
   6157         1,
   6158         0,
   6159         0x84916,
   6160         SOC_REG_FLAG_RO,
   6161         0,
   6162         1,
   6163         soc_JBDMAX1_CHID_0r_fields,
   6164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6165         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6166         -1,
   6167         -1,
   6168     },
   6169 #endif /* chips */
   6170 
   6171 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6172     { /* SOC_REG_INT_JBDMAX2_CHID_5r */
   6173         soc_block_list[81],
   6174         soc_genreg,
   6175         1,
   6176         0,
   6177         0x85916,
   6178         SOC_REG_FLAG_RO,
   6179         0,
   6180         1,
   6181         soc_JBDMAX1_CHID_0r_fields,
   6182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6183         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6184         -1,
   6185         -1,
   6186     },
   6187 #endif /* chips */
   6188 
   6189 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6190     { /* SOC_REG_INT_JBDMAX2_CHID_6r */
   6191         soc_block_list[81],
   6192         soc_genreg,
   6193         1,
   6194         0,
   6195         0x86916,
   6196         SOC_REG_FLAG_RO,
   6197         0,
   6198         1,
   6199         soc_JBDMAX1_CHID_0r_fields,
   6200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6201         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6202         -1,
   6203         -1,
   6204     },
   6205 #endif /* chips */
   6206 
   6207 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6208     { /* SOC_REG_INT_JBDMAX2_CHID_7r */
   6209         soc_block_list[81],
   6210         soc_genreg,
   6211         1,
   6212         0,
   6213         0x87916,
   6214         SOC_REG_FLAG_RO,
   6215         0,
   6216         1,
   6217         soc_JBDMAX1_CHID_0r_fields,
   6218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6219         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6220         -1,
   6221         -1,
   6222     },
   6223 #endif /* chips */
   6224 
   6225 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6226     { /* SOC_REG_INT_JBDMAX2_CHID_8r */
   6227         soc_block_list[81],
   6228         soc_genreg,
   6229         1,
   6230         0,
   6231         0x88916,
   6232         SOC_REG_FLAG_RO,
   6233         0,
   6234         1,
   6235         soc_JBDMAX1_CHID_0r_fields,
   6236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6237         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6238         -1,
   6239         -1,
   6240     },
   6241 #endif /* chips */
   6242 
   6243 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6244     { /* SOC_REG_INT_JBDMAX2_CHID_9r */
   6245         soc_block_list[81],
   6246         soc_genreg,
   6247         1,
   6248         0,
   6249         0x89916,
   6250         SOC_REG_FLAG_RO,
   6251         0,
   6252         1,
   6253         soc_JBDMAX1_CHID_0r_fields,
   6254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6255         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6256         -1,
   6257         -1,
   6258     },
   6259 #endif /* chips */
   6260 
   6261 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6262     { /* SOC_REG_INT_JBDMAX2_CHID_10r */
   6263         soc_block_list[81],
   6264         soc_genreg,
   6265         1,
   6266         0,
   6267         0x8a916,
   6268         SOC_REG_FLAG_RO,
   6269         0,
   6270         1,
   6271         soc_JBDMAX1_CHID_0r_fields,
   6272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6273         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6274         -1,
   6275         -1,
   6276     },
   6277 #endif /* chips */
   6278 
   6279 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6280     { /* SOC_REG_INT_JBDMAX2_CHID_11r */
   6281         soc_block_list[81],
   6282         soc_genreg,
   6283         1,
   6284         0,
   6285         0x8b916,
   6286         SOC_REG_FLAG_RO,
   6287         0,
   6288         1,
   6289         soc_JBDMAX1_CHID_0r_fields,
   6290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6291         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6292         -1,
   6293         -1,
   6294     },
   6295 #endif /* chips */
   6296 
   6297 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6298     { /* SOC_REG_INT_JBDMAX2_CHID_12r */
   6299         soc_block_list[81],
   6300         soc_genreg,
   6301         1,
   6302         0,
   6303         0x8c916,
   6304         SOC_REG_FLAG_RO,
   6305         0,
   6306         1,
   6307         soc_JBDMAX1_CHID_0r_fields,
   6308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6309         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6310         -1,
   6311         -1,
   6312     },
   6313 #endif /* chips */
   6314 
   6315 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6316     { /* SOC_REG_INT_JBDMAX2_CHID_13r */
   6317         soc_block_list[81],
   6318         soc_genreg,
   6319         1,
   6320         0,
   6321         0x8d916,
   6322         SOC_REG_FLAG_RO,
   6323         0,
   6324         1,
   6325         soc_JBDMAX1_CHID_0r_fields,
   6326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6328         -1,
   6329         -1,
   6330     },
   6331 #endif /* chips */
   6332 
   6333 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6334     { /* SOC_REG_INT_JBDMAX2_CHID_14r */
   6335         soc_block_list[81],
   6336         soc_genreg,
   6337         1,
   6338         0,
   6339         0x8e916,
   6340         SOC_REG_FLAG_RO,
   6341         0,
   6342         1,
   6343         soc_JBDMAX1_CHID_0r_fields,
   6344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6346         -1,
   6347         -1,
   6348     },
   6349 #endif /* chips */
   6350 
   6351 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6352     { /* SOC_REG_INT_JBDMAX2_CHID_15r */
   6353         soc_block_list[81],
   6354         soc_genreg,
   6355         1,
   6356         0,
   6357         0x8f916,
   6358         SOC_REG_FLAG_RO,
   6359         0,
   6360         1,
   6361         soc_JBDMAX1_CHID_0r_fields,
   6362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6364         -1,
   6365         -1,
   6366     },
   6367 #endif /* chips */
   6368 
   6369 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6370     { /* SOC_REG_INT_JBDMAX2_CHID_16r */
   6371         soc_block_list[81],
   6372         soc_genreg,
   6373         1,
   6374         0,
   6375         0x90916,
   6376         SOC_REG_FLAG_RO,
   6377         0,
   6378         1,
   6379         soc_JBDMAX1_CHID_0r_fields,
   6380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6381         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6382         -1,
   6383         -1,
   6384     },
   6385 #endif /* chips */
   6386 
   6387 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6388     { /* SOC_REG_INT_JBDMAX2_CHID_17r */
   6389         soc_block_list[81],
   6390         soc_genreg,
   6391         1,
   6392         0,
   6393         0x91916,
   6394         SOC_REG_FLAG_RO,
   6395         0,
   6396         1,
   6397         soc_JBDMAX1_CHID_0r_fields,
   6398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6399         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6400         -1,
   6401         -1,
   6402     },
   6403 #endif /* chips */
   6404 
   6405 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6406     { /* SOC_REG_INT_JBDMAX2_CHID_18r */
   6407         soc_block_list[81],
   6408         soc_genreg,
   6409         1,
   6410         0,
   6411         0x92916,
   6412         SOC_REG_FLAG_RO,
   6413         0,
   6414         1,
   6415         soc_JBDMAX1_CHID_0r_fields,
   6416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6417         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6418         -1,
   6419         -1,
   6420     },
   6421 #endif /* chips */
   6422 
   6423 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6424     { /* SOC_REG_INT_JBDMAX2_CHID_19r */
   6425         soc_block_list[81],
   6426         soc_genreg,
   6427         1,
   6428         0,
   6429         0x93916,
   6430         SOC_REG_FLAG_RO,
   6431         0,
   6432         1,
   6433         soc_JBDMAX1_CHID_0r_fields,
   6434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6435         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6436         -1,
   6437         -1,
   6438     },
   6439 #endif /* chips */
   6440 
   6441 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6442     { /* SOC_REG_INT_JBDMAX2_CHID_20r */
   6443         soc_block_list[81],
   6444         soc_genreg,
   6445         1,
   6446         0,
   6447         0x94916,
   6448         SOC_REG_FLAG_RO,
   6449         0,
   6450         1,
   6451         soc_JBDMAX1_CHID_0r_fields,
   6452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6453         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6454         -1,
   6455         -1,
   6456     },
   6457 #endif /* chips */
   6458 
   6459 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6460     { /* SOC_REG_INT_JBDMAX2_CHID_21r */
   6461         soc_block_list[81],
   6462         soc_genreg,
   6463         1,
   6464         0,
   6465         0x95916,
   6466         SOC_REG_FLAG_RO,
   6467         0,
   6468         1,
   6469         soc_JBDMAX1_CHID_0r_fields,
   6470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6472         -1,
   6473         -1,
   6474     },
   6475 #endif /* chips */
   6476 
   6477 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6478     { /* SOC_REG_INT_JBDMAX2_CHID_22r */
   6479         soc_block_list[81],
   6480         soc_genreg,
   6481         1,
   6482         0,
   6483         0x96916,
   6484         SOC_REG_FLAG_RO,
   6485         0,
   6486         1,
   6487         soc_JBDMAX1_CHID_0r_fields,
   6488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6490         -1,
   6491         -1,
   6492     },
   6493 #endif /* chips */
   6494 
   6495 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6496     { /* SOC_REG_INT_JBDMAX2_CHID_23r */
   6497         soc_block_list[81],
   6498         soc_genreg,
   6499         1,
   6500         0,
   6501         0x97916,
   6502         SOC_REG_FLAG_RO,
   6503         0,
   6504         1,
   6505         soc_JBDMAX1_CHID_0r_fields,
   6506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6508         -1,
   6509         -1,
   6510     },
   6511 #endif /* chips */
   6512 
   6513 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6514     { /* SOC_REG_INT_JBDMAX2_CHID_24r */
   6515         soc_block_list[81],
   6516         soc_genreg,
   6517         1,
   6518         0,
   6519         0x98916,
   6520         SOC_REG_FLAG_RO,
   6521         0,
   6522         1,
   6523         soc_JBDMAX1_CHID_0r_fields,
   6524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6525         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6526         -1,
   6527         -1,
   6528     },
   6529 #endif /* chips */
   6530 
   6531 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6532     { /* SOC_REG_INT_JBDMAX2_CHID_25r */
   6533         soc_block_list[81],
   6534         soc_genreg,
   6535         1,
   6536         0,
   6537         0x99916,
   6538         SOC_REG_FLAG_RO,
   6539         0,
   6540         1,
   6541         soc_JBDMAX1_CHID_0r_fields,
   6542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6544         -1,
   6545         -1,
   6546     },
   6547 #endif /* chips */
   6548 
   6549 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6550     { /* SOC_REG_INT_JBDMAX2_CHID_26r */
   6551         soc_block_list[81],
   6552         soc_genreg,
   6553         1,
   6554         0,
   6555         0x9a916,
   6556         SOC_REG_FLAG_RO,
   6557         0,
   6558         1,
   6559         soc_JBDMAX1_CHID_0r_fields,
   6560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6562         -1,
   6563         -1,
   6564     },
   6565 #endif /* chips */
   6566 
   6567 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6568     { /* SOC_REG_INT_JBDMAX2_CHID_27r */
   6569         soc_block_list[81],
   6570         soc_genreg,
   6571         1,
   6572         0,
   6573         0x9b916,
   6574         SOC_REG_FLAG_RO,
   6575         0,
   6576         1,
   6577         soc_JBDMAX1_CHID_0r_fields,
   6578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6580         -1,
   6581         -1,
   6582     },
   6583 #endif /* chips */
   6584 
   6585 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6586     { /* SOC_REG_INT_JBDMAX2_CHID_28r */
   6587         soc_block_list[81],
   6588         soc_genreg,
   6589         1,
   6590         0,
   6591         0x9c916,
   6592         SOC_REG_FLAG_RO,
   6593         0,
   6594         1,
   6595         soc_JBDMAX1_CHID_0r_fields,
   6596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6598         -1,
   6599         -1,
   6600     },
   6601 #endif /* chips */
   6602 
   6603 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6604     { /* SOC_REG_INT_JBDMAX2_CHID_29r */
   6605         soc_block_list[81],
   6606         soc_genreg,
   6607         1,
   6608         0,
   6609         0x9d916,
   6610         SOC_REG_FLAG_RO,
   6611         0,
   6612         1,
   6613         soc_JBDMAX1_CHID_0r_fields,
   6614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6616         -1,
   6617         -1,
   6618     },
   6619 #endif /* chips */
   6620 
   6621 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6622     { /* SOC_REG_INT_JBDMAX2_CHID_30r */
   6623         soc_block_list[81],
   6624         soc_genreg,
   6625         1,
   6626         0,
   6627         0x9e916,
   6628         SOC_REG_FLAG_RO,
   6629         0,
   6630         1,
   6631         soc_JBDMAX1_CHID_0r_fields,
   6632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6634         -1,
   6635         -1,
   6636     },
   6637 #endif /* chips */
   6638 
   6639 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6640     { /* SOC_REG_INT_JBDMAX2_CHID_31r */
   6641         soc_block_list[81],
   6642         soc_genreg,
   6643         1,
   6644         0,
   6645         0x9f916,
   6646         SOC_REG_FLAG_RO,
   6647         0,
   6648         1,
   6649         soc_JBDMAX1_CHID_0r_fields,
   6650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6652         -1,
   6653         -1,
   6654     },
   6655 #endif /* chips */
   6656 
   6657 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6658     { /* SOC_REG_INT_JBDMAX2_CHID_32r */
   6659         soc_block_list[81],
   6660         soc_genreg,
   6661         1,
   6662         0,
   6663         0xa0916,
   6664         SOC_REG_FLAG_RO,
   6665         0,
   6666         1,
   6667         soc_JBDMAX1_CHID_0r_fields,
   6668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6670         -1,
   6671         -1,
   6672     },
   6673 #endif /* chips */
   6674 
   6675 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6676     { /* SOC_REG_INT_JBDMAX2_CHID_33r */
   6677         soc_block_list[81],
   6678         soc_genreg,
   6679         1,
   6680         0,
   6681         0xa1916,
   6682         SOC_REG_FLAG_RO,
   6683         0,
   6684         1,
   6685         soc_JBDMAX1_CHID_0r_fields,
   6686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6687         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6688         -1,
   6689         -1,
   6690     },
   6691 #endif /* chips */
   6692 
   6693 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6694     { /* SOC_REG_INT_JBDMAX2_CHID_34r */
   6695         soc_block_list[81],
   6696         soc_genreg,
   6697         1,
   6698         0,
   6699         0xa2916,
   6700         SOC_REG_FLAG_RO,
   6701         0,
   6702         1,
   6703         soc_JBDMAX1_CHID_0r_fields,
   6704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6706         -1,
   6707         -1,
   6708     },
   6709 #endif /* chips */
   6710 
   6711 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6712     { /* SOC_REG_INT_JBDMAX2_CHID_35r */
   6713         soc_block_list[81],
   6714         soc_genreg,
   6715         1,
   6716         0,
   6717         0xa3916,
   6718         SOC_REG_FLAG_RO,
   6719         0,
   6720         1,
   6721         soc_JBDMAX1_CHID_0r_fields,
   6722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6724         -1,
   6725         -1,
   6726     },
   6727 #endif /* chips */
   6728 
   6729 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6730     { /* SOC_REG_INT_JBDMAX2_CHID_36r */
   6731         soc_block_list[81],
   6732         soc_genreg,
   6733         1,
   6734         0,
   6735         0xa4916,
   6736         SOC_REG_FLAG_RO,
   6737         0,
   6738         1,
   6739         soc_JBDMAX1_CHID_0r_fields,
   6740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6742         -1,
   6743         -1,
   6744     },
   6745 #endif /* chips */
   6746 
   6747 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6748     { /* SOC_REG_INT_JBDMAX2_CHID_37r */
   6749         soc_block_list[81],
   6750         soc_genreg,
   6751         1,
   6752         0,
   6753         0xa5916,
   6754         SOC_REG_FLAG_RO,
   6755         0,
   6756         1,
   6757         soc_JBDMAX1_CHID_0r_fields,
   6758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6760         -1,
   6761         -1,
   6762     },
   6763 #endif /* chips */
   6764 
   6765 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6766     { /* SOC_REG_INT_JBDMAX2_CHID_38r */
   6767         soc_block_list[81],
   6768         soc_genreg,
   6769         1,
   6770         0,
   6771         0xa6916,
   6772         SOC_REG_FLAG_RO,
   6773         0,
   6774         1,
   6775         soc_JBDMAX1_CHID_0r_fields,
   6776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6778         -1,
   6779         -1,
   6780     },
   6781 #endif /* chips */
   6782 
   6783 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6784     { /* SOC_REG_INT_JBDMAX2_CHID_39r */
   6785         soc_block_list[81],
   6786         soc_genreg,
   6787         1,
   6788         0,
   6789         0xa7916,
   6790         SOC_REG_FLAG_RO,
   6791         0,
   6792         1,
   6793         soc_JBDMAX1_CHID_0r_fields,
   6794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6796         -1,
   6797         -1,
   6798     },
   6799 #endif /* chips */
   6800 
   6801 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6802     { /* SOC_REG_INT_JBDMAX2_CHID_40r */
   6803         soc_block_list[81],
   6804         soc_genreg,
   6805         1,
   6806         0,
   6807         0xa8916,
   6808         SOC_REG_FLAG_RO,
   6809         0,
   6810         1,
   6811         soc_JBDMAX1_CHID_0r_fields,
   6812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6814         -1,
   6815         -1,
   6816     },
   6817 #endif /* chips */
   6818 
   6819 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6820     { /* SOC_REG_INT_JBDMAX2_CHID_41r */
   6821         soc_block_list[81],
   6822         soc_genreg,
   6823         1,
   6824         0,
   6825         0xa9916,
   6826         SOC_REG_FLAG_RO,
   6827         0,
   6828         1,
   6829         soc_JBDMAX1_CHID_0r_fields,
   6830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6832         -1,
   6833         -1,
   6834     },
   6835 #endif /* chips */
   6836 
   6837 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6838     { /* SOC_REG_INT_JBDMAX2_CHID_42r */
   6839         soc_block_list[81],
   6840         soc_genreg,
   6841         1,
   6842         0,
   6843         0xaa916,
   6844         SOC_REG_FLAG_RO,
   6845         0,
   6846         1,
   6847         soc_JBDMAX1_CHID_0r_fields,
   6848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6850         -1,
   6851         -1,
   6852     },
   6853 #endif /* chips */
   6854 
   6855 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6856     { /* SOC_REG_INT_JBDMAX2_CHID_43r */
   6857         soc_block_list[81],
   6858         soc_genreg,
   6859         1,
   6860         0,
   6861         0xab916,
   6862         SOC_REG_FLAG_RO,
   6863         0,
   6864         1,
   6865         soc_JBDMAX1_CHID_0r_fields,
   6866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6867         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6868         -1,
   6869         -1,
   6870     },
   6871 #endif /* chips */
   6872 
   6873 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6874     { /* SOC_REG_INT_JBDMAX2_CHID_44r */
   6875         soc_block_list[81],
   6876         soc_genreg,
   6877         1,
   6878         0,
   6879         0xac916,
   6880         SOC_REG_FLAG_RO,
   6881         0,
   6882         1,
   6883         soc_JBDMAX1_CHID_0r_fields,
   6884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6886         -1,
   6887         -1,
   6888     },
   6889 #endif /* chips */
   6890 
   6891 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6892     { /* SOC_REG_INT_JBDMAX2_CHID_45r */
   6893         soc_block_list[81],
   6894         soc_genreg,
   6895         1,
   6896         0,
   6897         0xad916,
   6898         SOC_REG_FLAG_RO,
   6899         0,
   6900         1,
   6901         soc_JBDMAX1_CHID_0r_fields,
   6902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6904         -1,
   6905         -1,
   6906     },
   6907 #endif /* chips */
   6908 
   6909 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6910     { /* SOC_REG_INT_JBDMAX2_CHID_46r */
   6911         soc_block_list[81],
   6912         soc_genreg,
   6913         1,
   6914         0,
   6915         0xae916,
   6916         SOC_REG_FLAG_RO,
   6917         0,
   6918         1,
   6919         soc_JBDMAX1_CHID_0r_fields,
   6920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6922         -1,
   6923         -1,
   6924     },
   6925 #endif /* chips */
   6926 
   6927 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6928     { /* SOC_REG_INT_JBDMAX2_CHID_47r */
   6929         soc_block_list[81],
   6930         soc_genreg,
   6931         1,
   6932         0,
   6933         0xaf916,
   6934         SOC_REG_FLAG_RO,
   6935         0,
   6936         1,
   6937         soc_JBDMAX1_CHID_0r_fields,
   6938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6940         -1,
   6941         -1,
   6942     },
   6943 #endif /* chips */
   6944 
   6945 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6946     { /* SOC_REG_INT_JBDMAX2_CHID_48r */
   6947         soc_block_list[81],
   6948         soc_genreg,
   6949         1,
   6950         0,
   6951         0xb0916,
   6952         SOC_REG_FLAG_RO,
   6953         0,
   6954         1,
   6955         soc_JBDMAX1_CHID_0r_fields,
   6956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6958         -1,
   6959         -1,
   6960     },
   6961 #endif /* chips */
   6962 
   6963 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6964     { /* SOC_REG_INT_JBDMAX2_CHID_49r */
   6965         soc_block_list[81],
   6966         soc_genreg,
   6967         1,
   6968         0,
   6969         0xb1916,
   6970         SOC_REG_FLAG_RO,
   6971         0,
   6972         1,
   6973         soc_JBDMAX1_CHID_0r_fields,
   6974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6976         -1,
   6977         -1,
   6978     },
   6979 #endif /* chips */
   6980 
   6981 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6982     { /* SOC_REG_INT_JBDMAX2_CHID_50r */
   6983         soc_block_list[81],
   6984         soc_genreg,
   6985         1,
   6986         0,
   6987         0xb2916,
   6988         SOC_REG_FLAG_RO,
   6989         0,
   6990         1,
   6991         soc_JBDMAX1_CHID_0r_fields,
   6992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6994         -1,
   6995         -1,
   6996     },
   6997 #endif /* chips */
   6998 
   6999 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7000     { /* SOC_REG_INT_JBDMAX2_CHID_51r */
   7001         soc_block_list[81],
   7002         soc_genreg,
   7003         1,
   7004         0,
   7005         0xb3916,
   7006         SOC_REG_FLAG_RO,
   7007         0,
   7008         1,
   7009         soc_JBDMAX1_CHID_0r_fields,
   7010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7012         -1,
   7013         -1,
   7014     },
   7015 #endif /* chips */
   7016 
   7017 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7018     { /* SOC_REG_INT_JBDMAX2_CHID_52r */
   7019         soc_block_list[81],
   7020         soc_genreg,
   7021         1,
   7022         0,
   7023         0xb4916,
   7024         SOC_REG_FLAG_RO,
   7025         0,
   7026         1,
   7027         soc_JBDMAX1_CHID_0r_fields,
   7028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7030         -1,
   7031         -1,
   7032     },
   7033 #endif /* chips */
   7034 
   7035 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7036     { /* SOC_REG_INT_JBDMAX2_CHID_53r */
   7037         soc_block_list[81],
   7038         soc_genreg,
   7039         1,
   7040         0,
   7041         0xb5916,
   7042         SOC_REG_FLAG_RO,
   7043         0,
   7044         1,
   7045         soc_JBDMAX1_CHID_0r_fields,
   7046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7048         -1,
   7049         -1,
   7050     },
   7051 #endif /* chips */
   7052 
   7053 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7054     { /* SOC_REG_INT_JBDMAX2_CHID_54r */
   7055         soc_block_list[81],
   7056         soc_genreg,
   7057         1,
   7058         0,
   7059         0xb6916,
   7060         SOC_REG_FLAG_RO,
   7061         0,
   7062         1,
   7063         soc_JBDMAX1_CHID_0r_fields,
   7064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7065         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7066         -1,
   7067         -1,
   7068     },
   7069 #endif /* chips */
   7070 
   7071 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7072     { /* SOC_REG_INT_JBDMAX2_CHID_55r */
   7073         soc_block_list[81],
   7074         soc_genreg,
   7075         1,
   7076         0,
   7077         0xb7916,
   7078         SOC_REG_FLAG_RO,
   7079         0,
   7080         1,
   7081         soc_JBDMAX1_CHID_0r_fields,
   7082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7084         -1,
   7085         -1,
   7086     },
   7087 #endif /* chips */
   7088 
   7089 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7090     { /* SOC_REG_INT_JBDMAX2_CHID_56r */
   7091         soc_block_list[81],
   7092         soc_genreg,
   7093         1,
   7094         0,
   7095         0xb8916,
   7096         SOC_REG_FLAG_RO,
   7097         0,
   7098         1,
   7099         soc_JBDMAX1_CHID_0r_fields,
   7100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7101         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7102         -1,
   7103         -1,
   7104     },
   7105 #endif /* chips */
   7106 
   7107 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7108     { /* SOC_REG_INT_JBDMAX2_CHID_57r */
   7109         soc_block_list[81],
   7110         soc_genreg,
   7111         1,
   7112         0,
   7113         0xb9916,
   7114         SOC_REG_FLAG_RO,
   7115         0,
   7116         1,
   7117         soc_JBDMAX1_CHID_0r_fields,
   7118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7119         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7120         -1,
   7121         -1,
   7122     },
   7123 #endif /* chips */
   7124 
   7125 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7126     { /* SOC_REG_INT_JBDMAX2_CHID_58r */
   7127         soc_block_list[81],
   7128         soc_genreg,
   7129         1,
   7130         0,
   7131         0xba916,
   7132         SOC_REG_FLAG_RO,
   7133         0,
   7134         1,
   7135         soc_JBDMAX1_CHID_0r_fields,
   7136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7137         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7138         -1,
   7139         -1,
   7140     },
   7141 #endif /* chips */
   7142 
   7143 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7144     { /* SOC_REG_INT_JBDMAX2_CHID_59r */
   7145         soc_block_list[81],
   7146         soc_genreg,
   7147         1,
   7148         0,
   7149         0xbb916,
   7150         SOC_REG_FLAG_RO,
   7151         0,
   7152         1,
   7153         soc_JBDMAX1_CHID_0r_fields,
   7154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7155         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7156         -1,
   7157         -1,
   7158     },
   7159 #endif /* chips */
   7160 
   7161 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7162     { /* SOC_REG_INT_JBDMAX2_CHID_60r */
   7163         soc_block_list[81],
   7164         soc_genreg,
   7165         1,
   7166         0,
   7167         0xbc916,
   7168         SOC_REG_FLAG_RO,
   7169         0,
   7170         1,
   7171         soc_JBDMAX1_CHID_0r_fields,
   7172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7174         -1,
   7175         -1,
   7176     },
   7177 #endif /* chips */
   7178 
   7179 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7180     { /* SOC_REG_INT_JBDMAX2_CHID_61r */
   7181         soc_block_list[81],
   7182         soc_genreg,
   7183         1,
   7184         0,
   7185         0xbd916,
   7186         SOC_REG_FLAG_RO,
   7187         0,
   7188         1,
   7189         soc_JBDMAX1_CHID_0r_fields,
   7190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7192         -1,
   7193         -1,
   7194     },
   7195 #endif /* chips */
   7196 
   7197 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7198     { /* SOC_REG_INT_JBDMAX2_CHID_62r */
   7199         soc_block_list[81],
   7200         soc_genreg,
   7201         1,
   7202         0,
   7203         0xbe916,
   7204         SOC_REG_FLAG_RO,
   7205         0,
   7206         1,
   7207         soc_JBDMAX1_CHID_0r_fields,
   7208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7209         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7210         -1,
   7211         -1,
   7212     },
   7213 #endif /* chips */
   7214 
   7215 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7216     { /* SOC_REG_INT_JBDMAX2_CHID_63r */
   7217         soc_block_list[81],
   7218         soc_genreg,
   7219         1,
   7220         0,
   7221         0xbf916,
   7222         SOC_REG_FLAG_RO,
   7223         0,
   7224         1,
   7225         soc_JBDMAX1_CHID_0r_fields,
   7226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7227         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7228         -1,
   7229         -1,
   7230     },
   7231 #endif /* chips */
   7232 
   7233 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7234     { /* SOC_REG_INT_JBDMIN1_CHID_0r */
   7235         soc_block_list[81],
   7236         soc_genreg,
   7237         1,
   7238         0,
   7239         0x80910,
   7240         SOC_REG_FLAG_RO,
   7241         0,
   7242         1,
   7243         soc_JBDMIN1_CHID_0r_fields,
   7244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7245         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7246         -1,
   7247         -1,
   7248     },
   7249 #endif /* chips */
   7250 
   7251 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7252     { /* SOC_REG_INT_JBDMIN1_CHID_1r */
   7253         soc_block_list[81],
   7254         soc_genreg,
   7255         1,
   7256         0,
   7257         0x81910,
   7258         SOC_REG_FLAG_RO,
   7259         0,
   7260         1,
   7261         soc_JBDMIN1_CHID_0r_fields,
   7262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7264         -1,
   7265         -1,
   7266     },
   7267 #endif /* chips */
   7268 
   7269 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7270     { /* SOC_REG_INT_JBDMIN1_CHID_2r */
   7271         soc_block_list[81],
   7272         soc_genreg,
   7273         1,
   7274         0,
   7275         0x82910,
   7276         SOC_REG_FLAG_RO,
   7277         0,
   7278         1,
   7279         soc_JBDMIN1_CHID_0r_fields,
   7280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7281         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7282         -1,
   7283         -1,
   7284     },
   7285 #endif /* chips */
   7286 
   7287 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7288     { /* SOC_REG_INT_JBDMIN1_CHID_3r */
   7289         soc_block_list[81],
   7290         soc_genreg,
   7291         1,
   7292         0,
   7293         0x83910,
   7294         SOC_REG_FLAG_RO,
   7295         0,
   7296         1,
   7297         soc_JBDMIN1_CHID_0r_fields,
   7298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7300         -1,
   7301         -1,
   7302     },
   7303 #endif /* chips */
   7304 
   7305 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7306     { /* SOC_REG_INT_JBDMIN1_CHID_4r */
   7307         soc_block_list[81],
   7308         soc_genreg,
   7309         1,
   7310         0,
   7311         0x84910,
   7312         SOC_REG_FLAG_RO,
   7313         0,
   7314         1,
   7315         soc_JBDMIN1_CHID_0r_fields,
   7316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7317         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7318         -1,
   7319         -1,
   7320     },
   7321 #endif /* chips */
   7322 
   7323 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7324     { /* SOC_REG_INT_JBDMIN1_CHID_5r */
   7325         soc_block_list[81],
   7326         soc_genreg,
   7327         1,
   7328         0,
   7329         0x85910,
   7330         SOC_REG_FLAG_RO,
   7331         0,
   7332         1,
   7333         soc_JBDMIN1_CHID_0r_fields,
   7334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7335         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7336         -1,
   7337         -1,
   7338     },
   7339 #endif /* chips */
   7340 
   7341 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7342     { /* SOC_REG_INT_JBDMIN1_CHID_6r */
   7343         soc_block_list[81],
   7344         soc_genreg,
   7345         1,
   7346         0,
   7347         0x86910,
   7348         SOC_REG_FLAG_RO,
   7349         0,
   7350         1,
   7351         soc_JBDMIN1_CHID_0r_fields,
   7352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7353         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7354         -1,
   7355         -1,
   7356     },
   7357 #endif /* chips */
   7358 
   7359 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7360     { /* SOC_REG_INT_JBDMIN1_CHID_7r */
   7361         soc_block_list[81],
   7362         soc_genreg,
   7363         1,
   7364         0,
   7365         0x87910,
   7366         SOC_REG_FLAG_RO,
   7367         0,
   7368         1,
   7369         soc_JBDMIN1_CHID_0r_fields,
   7370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7372         -1,
   7373         -1,
   7374     },
   7375 #endif /* chips */
   7376 
   7377 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7378     { /* SOC_REG_INT_JBDMIN1_CHID_8r */
   7379         soc_block_list[81],
   7380         soc_genreg,
   7381         1,
   7382         0,
   7383         0x88910,
   7384         SOC_REG_FLAG_RO,
   7385         0,
   7386         1,
   7387         soc_JBDMIN1_CHID_0r_fields,
   7388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7389         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7390         -1,
   7391         -1,
   7392     },
   7393 #endif /* chips */
   7394 
   7395 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7396     { /* SOC_REG_INT_JBDMIN1_CHID_9r */
   7397         soc_block_list[81],
   7398         soc_genreg,
   7399         1,
   7400         0,
   7401         0x89910,
   7402         SOC_REG_FLAG_RO,
   7403         0,
   7404         1,
   7405         soc_JBDMIN1_CHID_0r_fields,
   7406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7408         -1,
   7409         -1,
   7410     },
   7411 #endif /* chips */
   7412 
   7413 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7414     { /* SOC_REG_INT_JBDMIN1_CHID_10r */
   7415         soc_block_list[81],
   7416         soc_genreg,
   7417         1,
   7418         0,
   7419         0x8a910,
   7420         SOC_REG_FLAG_RO,
   7421         0,
   7422         1,
   7423         soc_JBDMIN1_CHID_0r_fields,
   7424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7426         -1,
   7427         -1,
   7428     },
   7429 #endif /* chips */
   7430 
   7431 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7432     { /* SOC_REG_INT_JBDMIN1_CHID_11r */
   7433         soc_block_list[81],
   7434         soc_genreg,
   7435         1,
   7436         0,
   7437         0x8b910,
   7438         SOC_REG_FLAG_RO,
   7439         0,
   7440         1,
   7441         soc_JBDMIN1_CHID_0r_fields,
   7442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7443         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7444         -1,
   7445         -1,
   7446     },
   7447 #endif /* chips */
   7448 
   7449 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7450     { /* SOC_REG_INT_JBDMIN1_CHID_12r */
   7451         soc_block_list[81],
   7452         soc_genreg,
   7453         1,
   7454         0,
   7455         0x8c910,
   7456         SOC_REG_FLAG_RO,
   7457         0,
   7458         1,
   7459         soc_JBDMIN1_CHID_0r_fields,
   7460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7461         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7462         -1,
   7463         -1,
   7464     },
   7465 #endif /* chips */
   7466 
   7467 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7468     { /* SOC_REG_INT_JBDMIN1_CHID_13r */
   7469         soc_block_list[81],
   7470         soc_genreg,
   7471         1,
   7472         0,
   7473         0x8d910,
   7474         SOC_REG_FLAG_RO,
   7475         0,
   7476         1,
   7477         soc_JBDMIN1_CHID_0r_fields,
   7478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7479         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7480         -1,
   7481         -1,
   7482     },
   7483 #endif /* chips */
   7484 
   7485 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7486     { /* SOC_REG_INT_JBDMIN1_CHID_14r */
   7487         soc_block_list[81],
   7488         soc_genreg,
   7489         1,
   7490         0,
   7491         0x8e910,
   7492         SOC_REG_FLAG_RO,
   7493         0,
   7494         1,
   7495         soc_JBDMIN1_CHID_0r_fields,
   7496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7497         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7498         -1,
   7499         -1,
   7500     },
   7501 #endif /* chips */
   7502 
   7503 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7504     { /* SOC_REG_INT_JBDMIN1_CHID_15r */
   7505         soc_block_list[81],
   7506         soc_genreg,
   7507         1,
   7508         0,
   7509         0x8f910,
   7510         SOC_REG_FLAG_RO,
   7511         0,
   7512         1,
   7513         soc_JBDMIN1_CHID_0r_fields,
   7514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7515         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7516         -1,
   7517         -1,
   7518     },
   7519 #endif /* chips */
   7520 
   7521 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7522     { /* SOC_REG_INT_JBDMIN1_CHID_16r */
   7523         soc_block_list[81],
   7524         soc_genreg,
   7525         1,
   7526         0,
   7527         0x90910,
   7528         SOC_REG_FLAG_RO,
   7529         0,
   7530         1,
   7531         soc_JBDMIN1_CHID_0r_fields,
   7532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7533         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7534         -1,
   7535         -1,
   7536     },
   7537 #endif /* chips */
   7538 
   7539 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7540     { /* SOC_REG_INT_JBDMIN1_CHID_17r */
   7541         soc_block_list[81],
   7542         soc_genreg,
   7543         1,
   7544         0,
   7545         0x91910,
   7546         SOC_REG_FLAG_RO,
   7547         0,
   7548         1,
   7549         soc_JBDMIN1_CHID_0r_fields,
   7550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7551         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7552         -1,
   7553         -1,
   7554     },
   7555 #endif /* chips */
   7556 
   7557 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7558     { /* SOC_REG_INT_JBDMIN1_CHID_18r */
   7559         soc_block_list[81],
   7560         soc_genreg,
   7561         1,
   7562         0,
   7563         0x92910,
   7564         SOC_REG_FLAG_RO,
   7565         0,
   7566         1,
   7567         soc_JBDMIN1_CHID_0r_fields,
   7568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7569         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7570         -1,
   7571         -1,
   7572     },
   7573 #endif /* chips */
   7574 
   7575 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7576     { /* SOC_REG_INT_JBDMIN1_CHID_19r */
   7577         soc_block_list[81],
   7578         soc_genreg,
   7579         1,
   7580         0,
   7581         0x93910,
   7582         SOC_REG_FLAG_RO,
   7583         0,
   7584         1,
   7585         soc_JBDMIN1_CHID_0r_fields,
   7586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7587         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7588         -1,
   7589         -1,
   7590     },
   7591 #endif /* chips */
   7592 
   7593 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7594     { /* SOC_REG_INT_JBDMIN1_CHID_20r */
   7595         soc_block_list[81],
   7596         soc_genreg,
   7597         1,
   7598         0,
   7599         0x94910,
   7600         SOC_REG_FLAG_RO,
   7601         0,
   7602         1,
   7603         soc_JBDMIN1_CHID_0r_fields,
   7604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7605         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7606         -1,
   7607         -1,
   7608     },
   7609 #endif /* chips */
   7610 
   7611 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7612     { /* SOC_REG_INT_JBDMIN1_CHID_21r */
   7613         soc_block_list[81],
   7614         soc_genreg,
   7615         1,
   7616         0,
   7617         0x95910,
   7618         SOC_REG_FLAG_RO,
   7619         0,
   7620         1,
   7621         soc_JBDMIN1_CHID_0r_fields,
   7622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7623         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7624         -1,
   7625         -1,
   7626     },
   7627 #endif /* chips */
   7628 
   7629 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7630     { /* SOC_REG_INT_JBDMIN1_CHID_22r */
   7631         soc_block_list[81],
   7632         soc_genreg,
   7633         1,
   7634         0,
   7635         0x96910,
   7636         SOC_REG_FLAG_RO,
   7637         0,
   7638         1,
   7639         soc_JBDMIN1_CHID_0r_fields,
   7640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7641         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7642         -1,
   7643         -1,
   7644     },
   7645 #endif /* chips */
   7646 
   7647 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7648     { /* SOC_REG_INT_JBDMIN1_CHID_23r */
   7649         soc_block_list[81],
   7650         soc_genreg,
   7651         1,
   7652         0,
   7653         0x97910,
   7654         SOC_REG_FLAG_RO,
   7655         0,
   7656         1,
   7657         soc_JBDMIN1_CHID_0r_fields,
   7658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7659         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7660         -1,
   7661         -1,
   7662     },
   7663 #endif /* chips */
   7664 
   7665 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7666     { /* SOC_REG_INT_JBDMIN1_CHID_24r */
   7667         soc_block_list[81],
   7668         soc_genreg,
   7669         1,
   7670         0,
   7671         0x98910,
   7672         SOC_REG_FLAG_RO,
   7673         0,
   7674         1,
   7675         soc_JBDMIN1_CHID_0r_fields,
   7676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7677         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7678         -1,
   7679         -1,
   7680     },
   7681 #endif /* chips */
   7682 
   7683 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7684     { /* SOC_REG_INT_JBDMIN1_CHID_25r */
   7685         soc_block_list[81],
   7686         soc_genreg,
   7687         1,
   7688         0,
   7689         0x99910,
   7690         SOC_REG_FLAG_RO,
   7691         0,
   7692         1,
   7693         soc_JBDMIN1_CHID_0r_fields,
   7694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7695         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7696         -1,
   7697         -1,
   7698     },
   7699 #endif /* chips */
   7700 
   7701 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7702     { /* SOC_REG_INT_JBDMIN1_CHID_26r */
   7703         soc_block_list[81],
   7704         soc_genreg,
   7705         1,
   7706         0,
   7707         0x9a910,
   7708         SOC_REG_FLAG_RO,
   7709         0,
   7710         1,
   7711         soc_JBDMIN1_CHID_0r_fields,
   7712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7713         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7714         -1,
   7715         -1,
   7716     },
   7717 #endif /* chips */
   7718 
   7719 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7720     { /* SOC_REG_INT_JBDMIN1_CHID_27r */
   7721         soc_block_list[81],
   7722         soc_genreg,
   7723         1,
   7724         0,
   7725         0x9b910,
   7726         SOC_REG_FLAG_RO,
   7727         0,
   7728         1,
   7729         soc_JBDMIN1_CHID_0r_fields,
   7730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7731         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7732         -1,
   7733         -1,
   7734     },
   7735 #endif /* chips */
   7736 
   7737 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7738     { /* SOC_REG_INT_JBDMIN1_CHID_28r */
   7739         soc_block_list[81],
   7740         soc_genreg,
   7741         1,
   7742         0,
   7743         0x9c910,
   7744         SOC_REG_FLAG_RO,
   7745         0,
   7746         1,
   7747         soc_JBDMIN1_CHID_0r_fields,
   7748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7749         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7750         -1,
   7751         -1,
   7752     },
   7753 #endif /* chips */
   7754 
   7755 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7756     { /* SOC_REG_INT_JBDMIN1_CHID_29r */
   7757         soc_block_list[81],
   7758         soc_genreg,
   7759         1,
   7760         0,
   7761         0x9d910,
   7762         SOC_REG_FLAG_RO,
   7763         0,
   7764         1,
   7765         soc_JBDMIN1_CHID_0r_fields,
   7766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7767         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7768         -1,
   7769         -1,
   7770     },
   7771 #endif /* chips */
   7772 
   7773 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7774     { /* SOC_REG_INT_JBDMIN1_CHID_30r */
   7775         soc_block_list[81],
   7776         soc_genreg,
   7777         1,
   7778         0,
   7779         0x9e910,
   7780         SOC_REG_FLAG_RO,
   7781         0,
   7782         1,
   7783         soc_JBDMIN1_CHID_0r_fields,
   7784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7785         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7786         -1,
   7787         -1,
   7788     },
   7789 #endif /* chips */
   7790 
   7791 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7792     { /* SOC_REG_INT_JBDMIN1_CHID_31r */
   7793         soc_block_list[81],
   7794         soc_genreg,
   7795         1,
   7796         0,
   7797         0x9f910,
   7798         SOC_REG_FLAG_RO,
   7799         0,
   7800         1,
   7801         soc_JBDMIN1_CHID_0r_fields,
   7802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7803         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7804         -1,
   7805         -1,
   7806     },
   7807 #endif /* chips */
   7808 
   7809 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7810     { /* SOC_REG_INT_JBDMIN1_CHID_32r */
   7811         soc_block_list[81],
   7812         soc_genreg,
   7813         1,
   7814         0,
   7815         0xa0910,
   7816         SOC_REG_FLAG_RO,
   7817         0,
   7818         1,
   7819         soc_JBDMIN1_CHID_0r_fields,
   7820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7821         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7822         -1,
   7823         -1,
   7824     },
   7825 #endif /* chips */
   7826 
   7827 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7828     { /* SOC_REG_INT_JBDMIN1_CHID_33r */
   7829         soc_block_list[81],
   7830         soc_genreg,
   7831         1,
   7832         0,
   7833         0xa1910,
   7834         SOC_REG_FLAG_RO,
   7835         0,
   7836         1,
   7837         soc_JBDMIN1_CHID_0r_fields,
   7838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7840         -1,
   7841         -1,
   7842     },
   7843 #endif /* chips */
   7844 
   7845 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7846     { /* SOC_REG_INT_JBDMIN1_CHID_34r */
   7847         soc_block_list[81],
   7848         soc_genreg,
   7849         1,
   7850         0,
   7851         0xa2910,
   7852         SOC_REG_FLAG_RO,
   7853         0,
   7854         1,
   7855         soc_JBDMIN1_CHID_0r_fields,
   7856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7857         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7858         -1,
   7859         -1,
   7860     },
   7861 #endif /* chips */
   7862 
   7863 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7864     { /* SOC_REG_INT_JBDMIN1_CHID_35r */
   7865         soc_block_list[81],
   7866         soc_genreg,
   7867         1,
   7868         0,
   7869         0xa3910,
   7870         SOC_REG_FLAG_RO,
   7871         0,
   7872         1,
   7873         soc_JBDMIN1_CHID_0r_fields,
   7874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7875         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7876         -1,
   7877         -1,
   7878     },
   7879 #endif /* chips */
   7880 
   7881 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7882     { /* SOC_REG_INT_JBDMIN1_CHID_36r */
   7883         soc_block_list[81],
   7884         soc_genreg,
   7885         1,
   7886         0,
   7887         0xa4910,
   7888         SOC_REG_FLAG_RO,
   7889         0,
   7890         1,
   7891         soc_JBDMIN1_CHID_0r_fields,
   7892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7893         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7894         -1,
   7895         -1,
   7896     },
   7897 #endif /* chips */
   7898 
   7899 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7900     { /* SOC_REG_INT_JBDMIN1_CHID_37r */
   7901         soc_block_list[81],
   7902         soc_genreg,
   7903         1,
   7904         0,
   7905         0xa5910,
   7906         SOC_REG_FLAG_RO,
   7907         0,
   7908         1,
   7909         soc_JBDMIN1_CHID_0r_fields,
   7910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7912         -1,
   7913         -1,
   7914     },
   7915 #endif /* chips */
   7916 
   7917 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7918     { /* SOC_REG_INT_JBDMIN1_CHID_38r */
   7919         soc_block_list[81],
   7920         soc_genreg,
   7921         1,
   7922         0,
   7923         0xa6910,
   7924         SOC_REG_FLAG_RO,
   7925         0,
   7926         1,
   7927         soc_JBDMIN1_CHID_0r_fields,
   7928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7929         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7930         -1,
   7931         -1,
   7932     },
   7933 #endif /* chips */
   7934 
   7935 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7936     { /* SOC_REG_INT_JBDMIN1_CHID_39r */
   7937         soc_block_list[81],
   7938         soc_genreg,
   7939         1,
   7940         0,
   7941         0xa7910,
   7942         SOC_REG_FLAG_RO,
   7943         0,
   7944         1,
   7945         soc_JBDMIN1_CHID_0r_fields,
   7946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7947         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7948         -1,
   7949         -1,
   7950     },
   7951 #endif /* chips */
   7952 
   7953 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7954     { /* SOC_REG_INT_JBDMIN1_CHID_40r */
   7955         soc_block_list[81],
   7956         soc_genreg,
   7957         1,
   7958         0,
   7959         0xa8910,
   7960         SOC_REG_FLAG_RO,
   7961         0,
   7962         1,
   7963         soc_JBDMIN1_CHID_0r_fields,
   7964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7965         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7966         -1,
   7967         -1,
   7968     },
   7969 #endif /* chips */
   7970 
   7971 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7972     { /* SOC_REG_INT_JBDMIN1_CHID_41r */
   7973         soc_block_list[81],
   7974         soc_genreg,
   7975         1,
   7976         0,
   7977         0xa9910,
   7978         SOC_REG_FLAG_RO,
   7979         0,
   7980         1,
   7981         soc_JBDMIN1_CHID_0r_fields,
   7982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7983         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7984         -1,
   7985         -1,
   7986     },
   7987 #endif /* chips */
   7988 
   7989 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7990     { /* SOC_REG_INT_JBDMIN1_CHID_42r */
   7991         soc_block_list[81],
   7992         soc_genreg,
   7993         1,
   7994         0,
   7995         0xaa910,
   7996         SOC_REG_FLAG_RO,
   7997         0,
   7998         1,
   7999         soc_JBDMIN1_CHID_0r_fields,
   8000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8001         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8002         -1,
   8003         -1,
   8004     },
   8005 #endif /* chips */
   8006 
   8007 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8008     { /* SOC_REG_INT_JBDMIN1_CHID_43r */
   8009         soc_block_list[81],
   8010         soc_genreg,
   8011         1,
   8012         0,
   8013         0xab910,
   8014         SOC_REG_FLAG_RO,
   8015         0,
   8016         1,
   8017         soc_JBDMIN1_CHID_0r_fields,
   8018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8019         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8020         -1,
   8021         -1,
   8022     },
   8023 #endif /* chips */
   8024 
   8025 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8026     { /* SOC_REG_INT_JBDMIN1_CHID_44r */
   8027         soc_block_list[81],
   8028         soc_genreg,
   8029         1,
   8030         0,
   8031         0xac910,
   8032         SOC_REG_FLAG_RO,
   8033         0,
   8034         1,
   8035         soc_JBDMIN1_CHID_0r_fields,
   8036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8037         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8038         -1,
   8039         -1,
   8040     },
   8041 #endif /* chips */
   8042 
   8043 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8044     { /* SOC_REG_INT_JBDMIN1_CHID_45r */
   8045         soc_block_list[81],
   8046         soc_genreg,
   8047         1,
   8048         0,
   8049         0xad910,
   8050         SOC_REG_FLAG_RO,
   8051         0,
   8052         1,
   8053         soc_JBDMIN1_CHID_0r_fields,
   8054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8055         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8056         -1,
   8057         -1,
   8058     },
   8059 #endif /* chips */
   8060 
   8061 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8062     { /* SOC_REG_INT_JBDMIN1_CHID_46r */
   8063         soc_block_list[81],
   8064         soc_genreg,
   8065         1,
   8066         0,
   8067         0xae910,
   8068         SOC_REG_FLAG_RO,
   8069         0,
   8070         1,
   8071         soc_JBDMIN1_CHID_0r_fields,
   8072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8073         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8074         -1,
   8075         -1,
   8076     },
   8077 #endif /* chips */
   8078 
   8079 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8080     { /* SOC_REG_INT_JBDMIN1_CHID_47r */
   8081         soc_block_list[81],
   8082         soc_genreg,
   8083         1,
   8084         0,
   8085         0xaf910,
   8086         SOC_REG_FLAG_RO,
   8087         0,
   8088         1,
   8089         soc_JBDMIN1_CHID_0r_fields,
   8090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8092         -1,
   8093         -1,
   8094     },
   8095 #endif /* chips */
   8096 
   8097 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8098     { /* SOC_REG_INT_JBDMIN1_CHID_48r */
   8099         soc_block_list[81],
   8100         soc_genreg,
   8101         1,
   8102         0,
   8103         0xb0910,
   8104         SOC_REG_FLAG_RO,
   8105         0,
   8106         1,
   8107         soc_JBDMIN1_CHID_0r_fields,
   8108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8110         -1,
   8111         -1,
   8112     },
   8113 #endif /* chips */
   8114 
   8115 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8116     { /* SOC_REG_INT_JBDMIN1_CHID_49r */
   8117         soc_block_list[81],
   8118         soc_genreg,
   8119         1,
   8120         0,
   8121         0xb1910,
   8122         SOC_REG_FLAG_RO,
   8123         0,
   8124         1,
   8125         soc_JBDMIN1_CHID_0r_fields,
   8126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8127         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8128         -1,
   8129         -1,
   8130     },
   8131 #endif /* chips */
   8132 
   8133 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8134     { /* SOC_REG_INT_JBDMIN1_CHID_50r */
   8135         soc_block_list[81],
   8136         soc_genreg,
   8137         1,
   8138         0,
   8139         0xb2910,
   8140         SOC_REG_FLAG_RO,
   8141         0,
   8142         1,
   8143         soc_JBDMIN1_CHID_0r_fields,
   8144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8145         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8146         -1,
   8147         -1,
   8148     },
   8149 #endif /* chips */
   8150 
   8151 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8152     { /* SOC_REG_INT_JBDMIN1_CHID_51r */
   8153         soc_block_list[81],
   8154         soc_genreg,
   8155         1,
   8156         0,
   8157         0xb3910,
   8158         SOC_REG_FLAG_RO,
   8159         0,
   8160         1,
   8161         soc_JBDMIN1_CHID_0r_fields,
   8162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8163         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8164         -1,
   8165         -1,
   8166     },
   8167 #endif /* chips */
   8168 
   8169 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8170     { /* SOC_REG_INT_JBDMIN1_CHID_52r */
   8171         soc_block_list[81],
   8172         soc_genreg,
   8173         1,
   8174         0,
   8175         0xb4910,
   8176         SOC_REG_FLAG_RO,
   8177         0,
   8178         1,
   8179         soc_JBDMIN1_CHID_0r_fields,
   8180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8182         -1,
   8183         -1,
   8184     },
   8185 #endif /* chips */
   8186 
   8187 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8188     { /* SOC_REG_INT_JBDMIN1_CHID_53r */
   8189         soc_block_list[81],
   8190         soc_genreg,
   8191         1,
   8192         0,
   8193         0xb5910,
   8194         SOC_REG_FLAG_RO,
   8195         0,
   8196         1,
   8197         soc_JBDMIN1_CHID_0r_fields,
   8198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8200         -1,
   8201         -1,
   8202     },
   8203 #endif /* chips */
   8204 
   8205 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8206     { /* SOC_REG_INT_JBDMIN1_CHID_54r */
   8207         soc_block_list[81],
   8208         soc_genreg,
   8209         1,
   8210         0,
   8211         0xb6910,
   8212         SOC_REG_FLAG_RO,
   8213         0,
   8214         1,
   8215         soc_JBDMIN1_CHID_0r_fields,
   8216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8217         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8218         -1,
   8219         -1,
   8220     },
   8221 #endif /* chips */
   8222 
   8223 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8224     { /* SOC_REG_INT_JBDMIN1_CHID_55r */
   8225         soc_block_list[81],
   8226         soc_genreg,
   8227         1,
   8228         0,
   8229         0xb7910,
   8230         SOC_REG_FLAG_RO,
   8231         0,
   8232         1,
   8233         soc_JBDMIN1_CHID_0r_fields,
   8234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8235         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8236         -1,
   8237         -1,
   8238     },
   8239 #endif /* chips */
   8240 
   8241 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8242     { /* SOC_REG_INT_JBDMIN1_CHID_56r */
   8243         soc_block_list[81],
   8244         soc_genreg,
   8245         1,
   8246         0,
   8247         0xb8910,
   8248         SOC_REG_FLAG_RO,
   8249         0,
   8250         1,
   8251         soc_JBDMIN1_CHID_0r_fields,
   8252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8253         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8254         -1,
   8255         -1,
   8256     },
   8257 #endif /* chips */
   8258 
   8259 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8260     { /* SOC_REG_INT_JBDMIN1_CHID_57r */
   8261         soc_block_list[81],
   8262         soc_genreg,
   8263         1,
   8264         0,
   8265         0xb9910,
   8266         SOC_REG_FLAG_RO,
   8267         0,
   8268         1,
   8269         soc_JBDMIN1_CHID_0r_fields,
   8270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8272         -1,
   8273         -1,
   8274     },
   8275 #endif /* chips */
   8276 
   8277 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8278     { /* SOC_REG_INT_JBDMIN1_CHID_58r */
   8279         soc_block_list[81],
   8280         soc_genreg,
   8281         1,
   8282         0,
   8283         0xba910,
   8284         SOC_REG_FLAG_RO,
   8285         0,
   8286         1,
   8287         soc_JBDMIN1_CHID_0r_fields,
   8288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8289         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8290         -1,
   8291         -1,
   8292     },
   8293 #endif /* chips */
   8294 
   8295 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8296     { /* SOC_REG_INT_JBDMIN1_CHID_59r */
   8297         soc_block_list[81],
   8298         soc_genreg,
   8299         1,
   8300         0,
   8301         0xbb910,
   8302         SOC_REG_FLAG_RO,
   8303         0,
   8304         1,
   8305         soc_JBDMIN1_CHID_0r_fields,
   8306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8308         -1,
   8309         -1,
   8310     },
   8311 #endif /* chips */
   8312 
   8313 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8314     { /* SOC_REG_INT_JBDMIN1_CHID_60r */
   8315         soc_block_list[81],
   8316         soc_genreg,
   8317         1,
   8318         0,
   8319         0xbc910,
   8320         SOC_REG_FLAG_RO,
   8321         0,
   8322         1,
   8323         soc_JBDMIN1_CHID_0r_fields,
   8324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8326         -1,
   8327         -1,
   8328     },
   8329 #endif /* chips */
   8330 
   8331 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8332     { /* SOC_REG_INT_JBDMIN1_CHID_61r */
   8333         soc_block_list[81],
   8334         soc_genreg,
   8335         1,
   8336         0,
   8337         0xbd910,
   8338         SOC_REG_FLAG_RO,
   8339         0,
   8340         1,
   8341         soc_JBDMIN1_CHID_0r_fields,
   8342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8343         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8344         -1,
   8345         -1,
   8346     },
   8347 #endif /* chips */
   8348 
   8349 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8350     { /* SOC_REG_INT_JBDMIN1_CHID_62r */
   8351         soc_block_list[81],
   8352         soc_genreg,
   8353         1,
   8354         0,
   8355         0xbe910,
   8356         SOC_REG_FLAG_RO,
   8357         0,
   8358         1,
   8359         soc_JBDMIN1_CHID_0r_fields,
   8360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8361         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8362         -1,
   8363         -1,
   8364     },
   8365 #endif /* chips */
   8366 
   8367 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8368     { /* SOC_REG_INT_JBDMIN1_CHID_63r */
   8369         soc_block_list[81],
   8370         soc_genreg,
   8371         1,
   8372         0,
   8373         0xbf910,
   8374         SOC_REG_FLAG_RO,
   8375         0,
   8376         1,
   8377         soc_JBDMIN1_CHID_0r_fields,
   8378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8379         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8380         -1,
   8381         -1,
   8382     },
   8383 #endif /* chips */
   8384 
   8385 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8386     { /* SOC_REG_INT_JBDMIN2_CHID_0r */
   8387         soc_block_list[81],
   8388         soc_genreg,
   8389         1,
   8390         0,
   8391         0x80912,
   8392         SOC_REG_FLAG_RO,
   8393         0,
   8394         1,
   8395         soc_JBDMIN1_CHID_0r_fields,
   8396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8397         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8398         -1,
   8399         -1,
   8400     },
   8401 #endif /* chips */
   8402 
   8403 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8404     { /* SOC_REG_INT_JBDMIN2_CHID_1r */
   8405         soc_block_list[81],
   8406         soc_genreg,
   8407         1,
   8408         0,
   8409         0x81912,
   8410         SOC_REG_FLAG_RO,
   8411         0,
   8412         1,
   8413         soc_JBDMIN1_CHID_0r_fields,
   8414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8415         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8416         -1,
   8417         -1,
   8418     },
   8419 #endif /* chips */
   8420 
   8421 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8422     { /* SOC_REG_INT_JBDMIN2_CHID_2r */
   8423         soc_block_list[81],
   8424         soc_genreg,
   8425         1,
   8426         0,
   8427         0x82912,
   8428         SOC_REG_FLAG_RO,
   8429         0,
   8430         1,
   8431         soc_JBDMIN1_CHID_0r_fields,
   8432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8433         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8434         -1,
   8435         -1,
   8436     },
   8437 #endif /* chips */
   8438 
   8439 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8440     { /* SOC_REG_INT_JBDMIN2_CHID_3r */
   8441         soc_block_list[81],
   8442         soc_genreg,
   8443         1,
   8444         0,
   8445         0x83912,
   8446         SOC_REG_FLAG_RO,
   8447         0,
   8448         1,
   8449         soc_JBDMIN1_CHID_0r_fields,
   8450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8451         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8452         -1,
   8453         -1,
   8454     },
   8455 #endif /* chips */
   8456 
   8457 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8458     { /* SOC_REG_INT_JBDMIN2_CHID_4r */
   8459         soc_block_list[81],
   8460         soc_genreg,
   8461         1,
   8462         0,
   8463         0x84912,
   8464         SOC_REG_FLAG_RO,
   8465         0,
   8466         1,
   8467         soc_JBDMIN1_CHID_0r_fields,
   8468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8469         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8470         -1,
   8471         -1,
   8472     },
   8473 #endif /* chips */
   8474 
   8475 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8476     { /* SOC_REG_INT_JBDMIN2_CHID_5r */
   8477         soc_block_list[81],
   8478         soc_genreg,
   8479         1,
   8480         0,
   8481         0x85912,
   8482         SOC_REG_FLAG_RO,
   8483         0,
   8484         1,
   8485         soc_JBDMIN1_CHID_0r_fields,
   8486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8488         -1,
   8489         -1,
   8490     },
   8491 #endif /* chips */
   8492 
   8493 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8494     { /* SOC_REG_INT_JBDMIN2_CHID_6r */
   8495         soc_block_list[81],
   8496         soc_genreg,
   8497         1,
   8498         0,
   8499         0x86912,
   8500         SOC_REG_FLAG_RO,
   8501         0,
   8502         1,
   8503         soc_JBDMIN1_CHID_0r_fields,
   8504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8505         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8506         -1,
   8507         -1,
   8508     },
   8509 #endif /* chips */
   8510 
   8511 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8512     { /* SOC_REG_INT_JBDMIN2_CHID_7r */
   8513         soc_block_list[81],
   8514         soc_genreg,
   8515         1,
   8516         0,
   8517         0x87912,
   8518         SOC_REG_FLAG_RO,
   8519         0,
   8520         1,
   8521         soc_JBDMIN1_CHID_0r_fields,
   8522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8524         -1,
   8525         -1,
   8526     },
   8527 #endif /* chips */
   8528 
   8529 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8530     { /* SOC_REG_INT_JBDMIN2_CHID_8r */
   8531         soc_block_list[81],
   8532         soc_genreg,
   8533         1,
   8534         0,
   8535         0x88912,
   8536         SOC_REG_FLAG_RO,
   8537         0,
   8538         1,
   8539         soc_JBDMIN1_CHID_0r_fields,
   8540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8541         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8542         -1,
   8543         -1,
   8544     },
   8545 #endif /* chips */
   8546 
   8547 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8548     { /* SOC_REG_INT_JBDMIN2_CHID_9r */
   8549         soc_block_list[81],
   8550         soc_genreg,
   8551         1,
   8552         0,
   8553         0x89912,
   8554         SOC_REG_FLAG_RO,
   8555         0,
   8556         1,
   8557         soc_JBDMIN1_CHID_0r_fields,
   8558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8559         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8560         -1,
   8561         -1,
   8562     },
   8563 #endif /* chips */
   8564 
   8565 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8566     { /* SOC_REG_INT_JBDMIN2_CHID_10r */
   8567         soc_block_list[81],
   8568         soc_genreg,
   8569         1,
   8570         0,
   8571         0x8a912,
   8572         SOC_REG_FLAG_RO,
   8573         0,
   8574         1,
   8575         soc_JBDMIN1_CHID_0r_fields,
   8576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8577         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8578         -1,
   8579         -1,
   8580     },
   8581 #endif /* chips */
   8582 
   8583 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8584     { /* SOC_REG_INT_JBDMIN2_CHID_11r */
   8585         soc_block_list[81],
   8586         soc_genreg,
   8587         1,
   8588         0,
   8589         0x8b912,
   8590         SOC_REG_FLAG_RO,
   8591         0,
   8592         1,
   8593         soc_JBDMIN1_CHID_0r_fields,
   8594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8595         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8596         -1,
   8597         -1,
   8598     },
   8599 #endif /* chips */
   8600 
   8601 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8602     { /* SOC_REG_INT_JBDMIN2_CHID_12r */
   8603         soc_block_list[81],
   8604         soc_genreg,
   8605         1,
   8606         0,
   8607         0x8c912,
   8608         SOC_REG_FLAG_RO,
   8609         0,
   8610         1,
   8611         soc_JBDMIN1_CHID_0r_fields,
   8612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8613         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8614         -1,
   8615         -1,
   8616     },
   8617 #endif /* chips */
   8618 
   8619 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8620     { /* SOC_REG_INT_JBDMIN2_CHID_13r */
   8621         soc_block_list[81],
   8622         soc_genreg,
   8623         1,
   8624         0,
   8625         0x8d912,
   8626         SOC_REG_FLAG_RO,
   8627         0,
   8628         1,
   8629         soc_JBDMIN1_CHID_0r_fields,
   8630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8632         -1,
   8633         -1,
   8634     },
   8635 #endif /* chips */
   8636 
   8637 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8638     { /* SOC_REG_INT_JBDMIN2_CHID_14r */
   8639         soc_block_list[81],
   8640         soc_genreg,
   8641         1,
   8642         0,
   8643         0x8e912,
   8644         SOC_REG_FLAG_RO,
   8645         0,
   8646         1,
   8647         soc_JBDMIN1_CHID_0r_fields,
   8648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8649         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8650         -1,
   8651         -1,
   8652     },
   8653 #endif /* chips */
   8654 
   8655 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8656     { /* SOC_REG_INT_JBDMIN2_CHID_15r */
   8657         soc_block_list[81],
   8658         soc_genreg,
   8659         1,
   8660         0,
   8661         0x8f912,
   8662         SOC_REG_FLAG_RO,
   8663         0,
   8664         1,
   8665         soc_JBDMIN1_CHID_0r_fields,
   8666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8667         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8668         -1,
   8669         -1,
   8670     },
   8671 #endif /* chips */
   8672 
   8673 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8674     { /* SOC_REG_INT_JBDMIN2_CHID_16r */
   8675         soc_block_list[81],
   8676         soc_genreg,
   8677         1,
   8678         0,
   8679         0x90912,
   8680         SOC_REG_FLAG_RO,
   8681         0,
   8682         1,
   8683         soc_JBDMIN1_CHID_0r_fields,
   8684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8685         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8686         -1,
   8687         -1,
   8688     },
   8689 #endif /* chips */
   8690 
   8691 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8692     { /* SOC_REG_INT_JBDMIN2_CHID_17r */
   8693         soc_block_list[81],
   8694         soc_genreg,
   8695         1,
   8696         0,
   8697         0x91912,
   8698         SOC_REG_FLAG_RO,
   8699         0,
   8700         1,
   8701         soc_JBDMIN1_CHID_0r_fields,
   8702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8703         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8704         -1,
   8705         -1,
   8706     },
   8707 #endif /* chips */
   8708 
   8709 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8710     { /* SOC_REG_INT_JBDMIN2_CHID_18r */
   8711         soc_block_list[81],
   8712         soc_genreg,
   8713         1,
   8714         0,
   8715         0x92912,
   8716         SOC_REG_FLAG_RO,
   8717         0,
   8718         1,
   8719         soc_JBDMIN1_CHID_0r_fields,
   8720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8722         -1,
   8723         -1,
   8724     },
   8725 #endif /* chips */
   8726 
   8727 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8728     { /* SOC_REG_INT_JBDMIN2_CHID_19r */
   8729         soc_block_list[81],
   8730         soc_genreg,
   8731         1,
   8732         0,
   8733         0x93912,
   8734         SOC_REG_FLAG_RO,
   8735         0,
   8736         1,
   8737         soc_JBDMIN1_CHID_0r_fields,
   8738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8739         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8740         -1,
   8741         -1,
   8742     },
   8743 #endif /* chips */
   8744 
   8745 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8746     { /* SOC_REG_INT_JBDMIN2_CHID_20r */
   8747         soc_block_list[81],
   8748         soc_genreg,
   8749         1,
   8750         0,
   8751         0x94912,
   8752         SOC_REG_FLAG_RO,
   8753         0,
   8754         1,
   8755         soc_JBDMIN1_CHID_0r_fields,
   8756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8758         -1,
   8759         -1,
   8760     },
   8761 #endif /* chips */
   8762 
   8763 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8764     { /* SOC_REG_INT_JBDMIN2_CHID_21r */
   8765         soc_block_list[81],
   8766         soc_genreg,
   8767         1,
   8768         0,
   8769         0x95912,
   8770         SOC_REG_FLAG_RO,
   8771         0,
   8772         1,
   8773         soc_JBDMIN1_CHID_0r_fields,
   8774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8775         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8776         -1,
   8777         -1,
   8778     },
   8779 #endif /* chips */
   8780 
   8781 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8782     { /* SOC_REG_INT_JBDMIN2_CHID_22r */
   8783         soc_block_list[81],
   8784         soc_genreg,
   8785         1,
   8786         0,
   8787         0x96912,
   8788         SOC_REG_FLAG_RO,
   8789         0,
   8790         1,
   8791         soc_JBDMIN1_CHID_0r_fields,
   8792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8793         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8794         -1,
   8795         -1,
   8796     },
   8797 #endif /* chips */
   8798 
   8799 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8800     { /* SOC_REG_INT_JBDMIN2_CHID_23r */
   8801         soc_block_list[81],
   8802         soc_genreg,
   8803         1,
   8804         0,
   8805         0x97912,
   8806         SOC_REG_FLAG_RO,
   8807         0,
   8808         1,
   8809         soc_JBDMIN1_CHID_0r_fields,
   8810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8811         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8812         -1,
   8813         -1,
   8814     },
   8815 #endif /* chips */
   8816 
   8817 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8818     { /* SOC_REG_INT_JBDMIN2_CHID_24r */
   8819         soc_block_list[81],
   8820         soc_genreg,
   8821         1,
   8822         0,
   8823         0x98912,
   8824         SOC_REG_FLAG_RO,
   8825         0,
   8826         1,
   8827         soc_JBDMIN1_CHID_0r_fields,
   8828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8829         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8830         -1,
   8831         -1,
   8832     },
   8833 #endif /* chips */
   8834 
   8835 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8836     { /* SOC_REG_INT_JBDMIN2_CHID_25r */
   8837         soc_block_list[81],
   8838         soc_genreg,
   8839         1,
   8840         0,
   8841         0x99912,
   8842         SOC_REG_FLAG_RO,
   8843         0,
   8844         1,
   8845         soc_JBDMIN1_CHID_0r_fields,
   8846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8847         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8848         -1,
   8849         -1,
   8850     },
   8851 #endif /* chips */
   8852 
   8853 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8854     { /* SOC_REG_INT_JBDMIN2_CHID_26r */
   8855         soc_block_list[81],
   8856         soc_genreg,
   8857         1,
   8858         0,
   8859         0x9a912,
   8860         SOC_REG_FLAG_RO,
   8861         0,
   8862         1,
   8863         soc_JBDMIN1_CHID_0r_fields,
   8864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8865         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8866         -1,
   8867         -1,
   8868     },
   8869 #endif /* chips */
   8870 
   8871 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8872     { /* SOC_REG_INT_JBDMIN2_CHID_27r */
   8873         soc_block_list[81],
   8874         soc_genreg,
   8875         1,
   8876         0,
   8877         0x9b912,
   8878         SOC_REG_FLAG_RO,
   8879         0,
   8880         1,
   8881         soc_JBDMIN1_CHID_0r_fields,
   8882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8883         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8884         -1,
   8885         -1,
   8886     },
   8887 #endif /* chips */
   8888 
   8889 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8890     { /* SOC_REG_INT_JBDMIN2_CHID_28r */
   8891         soc_block_list[81],
   8892         soc_genreg,
   8893         1,
   8894         0,
   8895         0x9c912,
   8896         SOC_REG_FLAG_RO,
   8897         0,
   8898         1,
   8899         soc_JBDMIN1_CHID_0r_fields,
   8900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8901         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8902         -1,
   8903         -1,
   8904     },
   8905 #endif /* chips */
   8906 
   8907 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8908     { /* SOC_REG_INT_JBDMIN2_CHID_29r */
   8909         soc_block_list[81],
   8910         soc_genreg,
   8911         1,
   8912         0,
   8913         0x9d912,
   8914         SOC_REG_FLAG_RO,
   8915         0,
   8916         1,
   8917         soc_JBDMIN1_CHID_0r_fields,
   8918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8919         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8920         -1,
   8921         -1,
   8922     },
   8923 #endif /* chips */
   8924 
   8925 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8926     { /* SOC_REG_INT_JBDMIN2_CHID_30r */
   8927         soc_block_list[81],
   8928         soc_genreg,
   8929         1,
   8930         0,
   8931         0x9e912,
   8932         SOC_REG_FLAG_RO,
   8933         0,
   8934         1,
   8935         soc_JBDMIN1_CHID_0r_fields,
   8936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8938         -1,
   8939         -1,
   8940     },
   8941 #endif /* chips */
   8942 
   8943 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8944     { /* SOC_REG_INT_JBDMIN2_CHID_31r */
   8945         soc_block_list[81],
   8946         soc_genreg,
   8947         1,
   8948         0,
   8949         0x9f912,
   8950         SOC_REG_FLAG_RO,
   8951         0,
   8952         1,
   8953         soc_JBDMIN1_CHID_0r_fields,
   8954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8956         -1,
   8957         -1,
   8958     },
   8959 #endif /* chips */
   8960 
   8961 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8962     { /* SOC_REG_INT_JBDMIN2_CHID_32r */
   8963         soc_block_list[81],
   8964         soc_genreg,
   8965         1,
   8966         0,
   8967         0xa0912,
   8968         SOC_REG_FLAG_RO,
   8969         0,
   8970         1,
   8971         soc_JBDMIN1_CHID_0r_fields,
   8972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8973         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8974         -1,
   8975         -1,
   8976     },
   8977 #endif /* chips */
   8978 
   8979 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8980     { /* SOC_REG_INT_JBDMIN2_CHID_33r */
   8981         soc_block_list[81],
   8982         soc_genreg,
   8983         1,
   8984         0,
   8985         0xa1912,
   8986         SOC_REG_FLAG_RO,
   8987         0,
   8988         1,
   8989         soc_JBDMIN1_CHID_0r_fields,
   8990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8992         -1,
   8993         -1,
   8994     },
   8995 #endif /* chips */
   8996 
   8997 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8998     { /* SOC_REG_INT_JBDMIN2_CHID_34r */
   8999         soc_block_list[81],
   9000         soc_genreg,
   9001         1,
   9002         0,
   9003         0xa2912,
   9004         SOC_REG_FLAG_RO,
   9005         0,
   9006         1,
   9007         soc_JBDMIN1_CHID_0r_fields,
   9008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9010         -1,
   9011         -1,
   9012     },
   9013 #endif /* chips */
   9014 
   9015 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9016     { /* SOC_REG_INT_JBDMIN2_CHID_35r */
   9017         soc_block_list[81],
   9018         soc_genreg,
   9019         1,
   9020         0,
   9021         0xa3912,
   9022         SOC_REG_FLAG_RO,
   9023         0,
   9024         1,
   9025         soc_JBDMIN1_CHID_0r_fields,
   9026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9027         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9028         -1,
   9029         -1,
   9030     },
   9031 #endif /* chips */
   9032 
   9033 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9034     { /* SOC_REG_INT_JBDMIN2_CHID_36r */
   9035         soc_block_list[81],
   9036         soc_genreg,
   9037         1,
   9038         0,
   9039         0xa4912,
   9040         SOC_REG_FLAG_RO,
   9041         0,
   9042         1,
   9043         soc_JBDMIN1_CHID_0r_fields,
   9044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9046         -1,
   9047         -1,
   9048     },
   9049 #endif /* chips */
   9050 
   9051 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9052     { /* SOC_REG_INT_JBDMIN2_CHID_37r */
   9053         soc_block_list[81],
   9054         soc_genreg,
   9055         1,
   9056         0,
   9057         0xa5912,
   9058         SOC_REG_FLAG_RO,
   9059         0,
   9060         1,
   9061         soc_JBDMIN1_CHID_0r_fields,
   9062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9064         -1,
   9065         -1,
   9066     },
   9067 #endif /* chips */
   9068 
   9069 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9070     { /* SOC_REG_INT_JBDMIN2_CHID_38r */
   9071         soc_block_list[81],
   9072         soc_genreg,
   9073         1,
   9074         0,
   9075         0xa6912,
   9076         SOC_REG_FLAG_RO,
   9077         0,
   9078         1,
   9079         soc_JBDMIN1_CHID_0r_fields,
   9080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9081         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9082         -1,
   9083         -1,
   9084     },
   9085 #endif /* chips */
   9086 
   9087 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9088     { /* SOC_REG_INT_JBDMIN2_CHID_39r */
   9089         soc_block_list[81],
   9090         soc_genreg,
   9091         1,
   9092         0,
   9093         0xa7912,
   9094         SOC_REG_FLAG_RO,
   9095         0,
   9096         1,
   9097         soc_JBDMIN1_CHID_0r_fields,
   9098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9100         -1,
   9101         -1,
   9102     },
   9103 #endif /* chips */
   9104 
   9105 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9106     { /* SOC_REG_INT_JBDMIN2_CHID_40r */
   9107         soc_block_list[81],
   9108         soc_genreg,
   9109         1,
   9110         0,
   9111         0xa8912,
   9112         SOC_REG_FLAG_RO,
   9113         0,
   9114         1,
   9115         soc_JBDMIN1_CHID_0r_fields,
   9116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9118         -1,
   9119         -1,
   9120     },
   9121 #endif /* chips */
   9122 
   9123 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9124     { /* SOC_REG_INT_JBDMIN2_CHID_41r */
   9125         soc_block_list[81],
   9126         soc_genreg,
   9127         1,
   9128         0,
   9129         0xa9912,
   9130         SOC_REG_FLAG_RO,
   9131         0,
   9132         1,
   9133         soc_JBDMIN1_CHID_0r_fields,
   9134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9136         -1,
   9137         -1,
   9138     },
   9139 #endif /* chips */
   9140 
   9141 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9142     { /* SOC_REG_INT_JBDMIN2_CHID_42r */
   9143         soc_block_list[81],
   9144         soc_genreg,
   9145         1,
   9146         0,
   9147         0xaa912,
   9148         SOC_REG_FLAG_RO,
   9149         0,
   9150         1,
   9151         soc_JBDMIN1_CHID_0r_fields,
   9152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9153         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9154         -1,
   9155         -1,
   9156     },
   9157 #endif /* chips */
   9158 
   9159 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9160     { /* SOC_REG_INT_JBDMIN2_CHID_43r */
   9161         soc_block_list[81],
   9162         soc_genreg,
   9163         1,
   9164         0,
   9165         0xab912,
   9166         SOC_REG_FLAG_RO,
   9167         0,
   9168         1,
   9169         soc_JBDMIN1_CHID_0r_fields,
   9170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9171         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9172         -1,
   9173         -1,
   9174     },
   9175 #endif /* chips */
   9176 
   9177 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9178     { /* SOC_REG_INT_JBDMIN2_CHID_44r */
   9179         soc_block_list[81],
   9180         soc_genreg,
   9181         1,
   9182         0,
   9183         0xac912,
   9184         SOC_REG_FLAG_RO,
   9185         0,
   9186         1,
   9187         soc_JBDMIN1_CHID_0r_fields,
   9188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9189         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9190         -1,
   9191         -1,
   9192     },
   9193 #endif /* chips */
   9194 
   9195 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9196     { /* SOC_REG_INT_JBDMIN2_CHID_45r */
   9197         soc_block_list[81],
   9198         soc_genreg,
   9199         1,
   9200         0,
   9201         0xad912,
   9202         SOC_REG_FLAG_RO,
   9203         0,
   9204         1,
   9205         soc_JBDMIN1_CHID_0r_fields,
   9206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9207         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9208         -1,
   9209         -1,
   9210     },
   9211 #endif /* chips */
   9212 
   9213 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9214     { /* SOC_REG_INT_JBDMIN2_CHID_46r */
   9215         soc_block_list[81],
   9216         soc_genreg,
   9217         1,
   9218         0,
   9219         0xae912,
   9220         SOC_REG_FLAG_RO,
   9221         0,
   9222         1,
   9223         soc_JBDMIN1_CHID_0r_fields,
   9224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9225         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9226         -1,
   9227         -1,
   9228     },
   9229 #endif /* chips */
   9230 
   9231 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9232     { /* SOC_REG_INT_JBDMIN2_CHID_47r */
   9233         soc_block_list[81],
   9234         soc_genreg,
   9235         1,
   9236         0,
   9237         0xaf912,
   9238         SOC_REG_FLAG_RO,
   9239         0,
   9240         1,
   9241         soc_JBDMIN1_CHID_0r_fields,
   9242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9243         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9244         -1,
   9245         -1,
   9246     },
   9247 #endif /* chips */
   9248 
   9249 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9250     { /* SOC_REG_INT_JBDMIN2_CHID_48r */
   9251         soc_block_list[81],
   9252         soc_genreg,
   9253         1,
   9254         0,
   9255         0xb0912,
   9256         SOC_REG_FLAG_RO,
   9257         0,
   9258         1,
   9259         soc_JBDMIN1_CHID_0r_fields,
   9260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9261         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9262         -1,
   9263         -1,
   9264     },
   9265 #endif /* chips */
   9266 
   9267 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9268     { /* SOC_REG_INT_JBDMIN2_CHID_49r */
   9269         soc_block_list[81],
   9270         soc_genreg,
   9271         1,
   9272         0,
   9273         0xb1912,
   9274         SOC_REG_FLAG_RO,
   9275         0,
   9276         1,
   9277         soc_JBDMIN1_CHID_0r_fields,
   9278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9279         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9280         -1,
   9281         -1,
   9282     },
   9283 #endif /* chips */
   9284 
   9285 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9286     { /* SOC_REG_INT_JBDMIN2_CHID_50r */
   9287         soc_block_list[81],
   9288         soc_genreg,
   9289         1,
   9290         0,
   9291         0xb2912,
   9292         SOC_REG_FLAG_RO,
   9293         0,
   9294         1,
   9295         soc_JBDMIN1_CHID_0r_fields,
   9296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9297         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9298         -1,
   9299         -1,
   9300     },
   9301 #endif /* chips */
   9302 
   9303 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9304     { /* SOC_REG_INT_JBDMIN2_CHID_51r */
   9305         soc_block_list[81],
   9306         soc_genreg,
   9307         1,
   9308         0,
   9309         0xb3912,
   9310         SOC_REG_FLAG_RO,
   9311         0,
   9312         1,
   9313         soc_JBDMIN1_CHID_0r_fields,
   9314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9315         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9316         -1,
   9317         -1,
   9318     },
   9319 #endif /* chips */
   9320 
   9321 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9322     { /* SOC_REG_INT_JBDMIN2_CHID_52r */
   9323         soc_block_list[81],
   9324         soc_genreg,
   9325         1,
   9326         0,
   9327         0xb4912,
   9328         SOC_REG_FLAG_RO,
   9329         0,
   9330         1,
   9331         soc_JBDMIN1_CHID_0r_fields,
   9332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9334         -1,
   9335         -1,
   9336     },
   9337 #endif /* chips */
   9338 
   9339 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9340     { /* SOC_REG_INT_JBDMIN2_CHID_53r */
   9341         soc_block_list[81],
   9342         soc_genreg,
   9343         1,
   9344         0,
   9345         0xb5912,
   9346         SOC_REG_FLAG_RO,
   9347         0,
   9348         1,
   9349         soc_JBDMIN1_CHID_0r_fields,
   9350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9351         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9352         -1,
   9353         -1,
   9354     },
   9355 #endif /* chips */
   9356 
   9357 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9358     { /* SOC_REG_INT_JBDMIN2_CHID_54r */
   9359         soc_block_list[81],
   9360         soc_genreg,
   9361         1,
   9362         0,
   9363         0xb6912,
   9364         SOC_REG_FLAG_RO,
   9365         0,
   9366         1,
   9367         soc_JBDMIN1_CHID_0r_fields,
   9368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9370         -1,
   9371         -1,
   9372     },
   9373 #endif /* chips */
   9374 
   9375 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9376     { /* SOC_REG_INT_JBDMIN2_CHID_55r */
   9377         soc_block_list[81],
   9378         soc_genreg,
   9379         1,
   9380         0,
   9381         0xb7912,
   9382         SOC_REG_FLAG_RO,
   9383         0,
   9384         1,
   9385         soc_JBDMIN1_CHID_0r_fields,
   9386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9387         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9388         -1,
   9389         -1,
   9390     },
   9391 #endif /* chips */
   9392 
   9393 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9394     { /* SOC_REG_INT_JBDMIN2_CHID_56r */
   9395         soc_block_list[81],
   9396         soc_genreg,
   9397         1,
   9398         0,
   9399         0xb8912,
   9400         SOC_REG_FLAG_RO,
   9401         0,
   9402         1,
   9403         soc_JBDMIN1_CHID_0r_fields,
   9404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9405         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9406         -1,
   9407         -1,
   9408     },
   9409 #endif /* chips */
   9410 
   9411 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9412     { /* SOC_REG_INT_JBDMIN2_CHID_57r */
   9413         soc_block_list[81],
   9414         soc_genreg,
   9415         1,
   9416         0,
   9417         0xb9912,
   9418         SOC_REG_FLAG_RO,
   9419         0,
   9420         1,
   9421         soc_JBDMIN1_CHID_0r_fields,
   9422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9423         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9424         -1,
   9425         -1,
   9426     },
   9427 #endif /* chips */
   9428 
   9429 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9430     { /* SOC_REG_INT_JBDMIN2_CHID_58r */
   9431         soc_block_list[81],
   9432         soc_genreg,
   9433         1,
   9434         0,
   9435         0xba912,
   9436         SOC_REG_FLAG_RO,
   9437         0,
   9438         1,
   9439         soc_JBDMIN1_CHID_0r_fields,
   9440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9441         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9442         -1,
   9443         -1,
   9444     },
   9445 #endif /* chips */
   9446 
   9447 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9448     { /* SOC_REG_INT_JBDMIN2_CHID_59r */
   9449         soc_block_list[81],
   9450         soc_genreg,
   9451         1,
   9452         0,
   9453         0xbb912,
   9454         SOC_REG_FLAG_RO,
   9455         0,
   9456         1,
   9457         soc_JBDMIN1_CHID_0r_fields,
   9458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9459         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9460         -1,
   9461         -1,
   9462     },
   9463 #endif /* chips */
   9464 
   9465 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9466     { /* SOC_REG_INT_JBDMIN2_CHID_60r */
   9467         soc_block_list[81],
   9468         soc_genreg,
   9469         1,
   9470         0,
   9471         0xbc912,
   9472         SOC_REG_FLAG_RO,
   9473         0,
   9474         1,
   9475         soc_JBDMIN1_CHID_0r_fields,
   9476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9477         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9478         -1,
   9479         -1,
   9480     },
   9481 #endif /* chips */
   9482 
   9483 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9484     { /* SOC_REG_INT_JBDMIN2_CHID_61r */
   9485         soc_block_list[81],
   9486         soc_genreg,
   9487         1,
   9488         0,
   9489         0xbd912,
   9490         SOC_REG_FLAG_RO,
   9491         0,
   9492         1,
   9493         soc_JBDMIN1_CHID_0r_fields,
   9494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9495         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9496         -1,
   9497         -1,
   9498     },
   9499 #endif /* chips */
   9500 
   9501 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9502     { /* SOC_REG_INT_JBDMIN2_CHID_62r */
   9503         soc_block_list[81],
   9504         soc_genreg,
   9505         1,
   9506         0,
   9507         0xbe912,
   9508         SOC_REG_FLAG_RO,
   9509         0,
   9510         1,
   9511         soc_JBDMIN1_CHID_0r_fields,
   9512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9514         -1,
   9515         -1,
   9516     },
   9517 #endif /* chips */
   9518 
   9519 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9520     { /* SOC_REG_INT_JBDMIN2_CHID_63r */
   9521         soc_block_list[81],
   9522         soc_genreg,
   9523         1,
   9524         0,
   9525         0xbf912,
   9526         SOC_REG_FLAG_RO,
   9527         0,
   9528         1,
   9529         soc_JBDMIN1_CHID_0r_fields,
   9530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9531         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9532         -1,
   9533         -1,
   9534     },
   9535 #endif /* chips */
   9536 
   9537 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9538     { /* SOC_REG_INT_JBDSUM1_TCID_0r */
   9539         soc_block_list[81],
   9540         soc_genreg,
   9541         1,
   9542         0,
   9543         0x80c44,
   9544         SOC_REG_FLAG_RO,
   9545         0,
   9546         1,
   9547         soc_JBDSUM1_TCID_0r_fields,
   9548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9549         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9550         -1,
   9551         -1,
   9552     },
   9553 #endif /* chips */
   9554 
   9555 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9556     { /* SOC_REG_INT_JBDSUM1_TCID_1r */
   9557         soc_block_list[81],
   9558         soc_genreg,
   9559         1,
   9560         0,
   9561         0x81c44,
   9562         SOC_REG_FLAG_RO,
   9563         0,
   9564         1,
   9565         soc_JBDSUM1_TCID_0r_fields,
   9566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9567         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9568         -1,
   9569         -1,
   9570     },
   9571 #endif /* chips */
   9572 
   9573 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9574     { /* SOC_REG_INT_JBDSUM1_TCID_2r */
   9575         soc_block_list[81],
   9576         soc_genreg,
   9577         1,
   9578         0,
   9579         0x82c44,
   9580         SOC_REG_FLAG_RO,
   9581         0,
   9582         1,
   9583         soc_JBDSUM1_TCID_0r_fields,
   9584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9585         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9586         -1,
   9587         -1,
   9588     },
   9589 #endif /* chips */
   9590 
   9591 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9592     { /* SOC_REG_INT_JBDSUM1_TCID_3r */
   9593         soc_block_list[81],
   9594         soc_genreg,
   9595         1,
   9596         0,
   9597         0x83c44,
   9598         SOC_REG_FLAG_RO,
   9599         0,
   9600         1,
   9601         soc_JBDSUM1_TCID_0r_fields,
   9602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9603         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9604         -1,
   9605         -1,
   9606     },
   9607 #endif /* chips */
   9608 
   9609 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9610     { /* SOC_REG_INT_JBDSUM1_TCID_4r */
   9611         soc_block_list[81],
   9612         soc_genreg,
   9613         1,
   9614         0,
   9615         0x84c44,
   9616         SOC_REG_FLAG_RO,
   9617         0,
   9618         1,
   9619         soc_JBDSUM1_TCID_0r_fields,
   9620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9622         -1,
   9623         -1,
   9624     },
   9625 #endif /* chips */
   9626 
   9627 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9628     { /* SOC_REG_INT_JBDSUM1_TCID_5r */
   9629         soc_block_list[81],
   9630         soc_genreg,
   9631         1,
   9632         0,
   9633         0x85c44,
   9634         SOC_REG_FLAG_RO,
   9635         0,
   9636         1,
   9637         soc_JBDSUM1_TCID_0r_fields,
   9638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9639         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9640         -1,
   9641         -1,
   9642     },
   9643 #endif /* chips */
   9644 
   9645 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9646     { /* SOC_REG_INT_JBDSUM1_TCID_6r */
   9647         soc_block_list[81],
   9648         soc_genreg,
   9649         1,
   9650         0,
   9651         0x86c44,
   9652         SOC_REG_FLAG_RO,
   9653         0,
   9654         1,
   9655         soc_JBDSUM1_TCID_0r_fields,
   9656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9657         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9658         -1,
   9659         -1,
   9660     },
   9661 #endif /* chips */
   9662 
   9663 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9664     { /* SOC_REG_INT_JBDSUM1_TCID_7r */
   9665         soc_block_list[81],
   9666         soc_genreg,
   9667         1,
   9668         0,
   9669         0x87c44,
   9670         SOC_REG_FLAG_RO,
   9671         0,
   9672         1,
   9673         soc_JBDSUM1_TCID_0r_fields,
   9674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9676         -1,
   9677         -1,
   9678     },
   9679 #endif /* chips */
   9680 
   9681 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9682     { /* SOC_REG_INT_JBDSUM1_TCID_8r */
   9683         soc_block_list[81],
   9684         soc_genreg,
   9685         1,
   9686         0,
   9687         0x88c44,
   9688         SOC_REG_FLAG_RO,
   9689         0,
   9690         1,
   9691         soc_JBDSUM1_TCID_0r_fields,
   9692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9693         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9694         -1,
   9695         -1,
   9696     },
   9697 #endif /* chips */
   9698 
   9699 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9700     { /* SOC_REG_INT_JBDSUM1_TCID_9r */
   9701         soc_block_list[81],
   9702         soc_genreg,
   9703         1,
   9704         0,
   9705         0x89c44,
   9706         SOC_REG_FLAG_RO,
   9707         0,
   9708         1,
   9709         soc_JBDSUM1_TCID_0r_fields,
   9710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9711         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9712         -1,
   9713         -1,
   9714     },
   9715 #endif /* chips */
   9716 
   9717 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9718     { /* SOC_REG_INT_JBDSUM1_TCID_10r */
   9719         soc_block_list[81],
   9720         soc_genreg,
   9721         1,
   9722         0,
   9723         0x8ac44,
   9724         SOC_REG_FLAG_RO,
   9725         0,
   9726         1,
   9727         soc_JBDSUM1_TCID_0r_fields,
   9728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9729         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9730         -1,
   9731         -1,
   9732     },
   9733 #endif /* chips */
   9734 
   9735 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9736     { /* SOC_REG_INT_JBDSUM1_TCID_11r */
   9737         soc_block_list[81],
   9738         soc_genreg,
   9739         1,
   9740         0,
   9741         0x8bc44,
   9742         SOC_REG_FLAG_RO,
   9743         0,
   9744         1,
   9745         soc_JBDSUM1_TCID_0r_fields,
   9746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9747         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9748         -1,
   9749         -1,
   9750     },
   9751 #endif /* chips */
   9752 
   9753 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9754     { /* SOC_REG_INT_JBDSUM1_TCID_12r */
   9755         soc_block_list[81],
   9756         soc_genreg,
   9757         1,
   9758         0,
   9759         0x8cc44,
   9760         SOC_REG_FLAG_RO,
   9761         0,
   9762         1,
   9763         soc_JBDSUM1_TCID_0r_fields,
   9764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9765         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9766         -1,
   9767         -1,
   9768     },
   9769 #endif /* chips */
   9770 
   9771 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9772     { /* SOC_REG_INT_JBDSUM1_TCID_13r */
   9773         soc_block_list[81],
   9774         soc_genreg,
   9775         1,
   9776         0,
   9777         0x8dc44,
   9778         SOC_REG_FLAG_RO,
   9779         0,
   9780         1,
   9781         soc_JBDSUM1_TCID_0r_fields,
   9782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9783         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9784         -1,
   9785         -1,
   9786     },
   9787 #endif /* chips */
   9788 
   9789 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9790     { /* SOC_REG_INT_JBDSUM1_TCID_14r */
   9791         soc_block_list[81],
   9792         soc_genreg,
   9793         1,
   9794         0,
   9795         0x8ec44,
   9796         SOC_REG_FLAG_RO,
   9797         0,
   9798         1,
   9799         soc_JBDSUM1_TCID_0r_fields,
   9800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9801         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9802         -1,
   9803         -1,
   9804     },
   9805 #endif /* chips */
   9806 
   9807 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9808     { /* SOC_REG_INT_JBDSUM1_TCID_15r */
   9809         soc_block_list[81],
   9810         soc_genreg,
   9811         1,
   9812         0,
   9813         0x8fc44,
   9814         SOC_REG_FLAG_RO,
   9815         0,
   9816         1,
   9817         soc_JBDSUM1_TCID_0r_fields,
   9818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9819         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9820         -1,
   9821         -1,
   9822     },
   9823 #endif /* chips */
   9824 
   9825 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9826     { /* SOC_REG_INT_JBDSUM2_TCID_0r */
   9827         soc_block_list[81],
   9828         soc_genreg,
   9829         1,
   9830         0,
   9831         0x80c46,
   9832         SOC_REG_FLAG_RO,
   9833         0,
   9834         1,
   9835         soc_JBDSUM1_TCID_0r_fields,
   9836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9838         -1,
   9839         -1,
   9840     },
   9841 #endif /* chips */
   9842 
   9843 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9844     { /* SOC_REG_INT_JBDSUM2_TCID_1r */
   9845         soc_block_list[81],
   9846         soc_genreg,
   9847         1,
   9848         0,
   9849         0x81c46,
   9850         SOC_REG_FLAG_RO,
   9851         0,
   9852         1,
   9853         soc_JBDSUM1_TCID_0r_fields,
   9854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9855         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9856         -1,
   9857         -1,
   9858     },
   9859 #endif /* chips */
   9860 
   9861 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9862     { /* SOC_REG_INT_JBDSUM2_TCID_2r */
   9863         soc_block_list[81],
   9864         soc_genreg,
   9865         1,
   9866         0,
   9867         0x82c46,
   9868         SOC_REG_FLAG_RO,
   9869         0,
   9870         1,
   9871         soc_JBDSUM1_TCID_0r_fields,
   9872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9874         -1,
   9875         -1,
   9876     },
   9877 #endif /* chips */
   9878 
   9879 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9880     { /* SOC_REG_INT_JBDSUM2_TCID_3r */
   9881         soc_block_list[81],
   9882         soc_genreg,
   9883         1,
   9884         0,
   9885         0x83c46,
   9886         SOC_REG_FLAG_RO,
   9887         0,
   9888         1,
   9889         soc_JBDSUM1_TCID_0r_fields,
   9890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9892         -1,
   9893         -1,
   9894     },
   9895 #endif /* chips */
   9896 
   9897 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9898     { /* SOC_REG_INT_JBDSUM2_TCID_4r */
   9899         soc_block_list[81],
   9900         soc_genreg,
   9901         1,
   9902         0,
   9903         0x84c46,
   9904         SOC_REG_FLAG_RO,
   9905         0,
   9906         1,
   9907         soc_JBDSUM1_TCID_0r_fields,
   9908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9909         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9910         -1,
   9911         -1,
   9912     },
   9913 #endif /* chips */
   9914 
   9915 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9916     { /* SOC_REG_INT_JBDSUM2_TCID_5r */
   9917         soc_block_list[81],
   9918         soc_genreg,
   9919         1,
   9920         0,
   9921         0x85c46,
   9922         SOC_REG_FLAG_RO,
   9923         0,
   9924         1,
   9925         soc_JBDSUM1_TCID_0r_fields,
   9926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9927         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9928         -1,
   9929         -1,
   9930     },
   9931 #endif /* chips */
   9932 
   9933 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9934     { /* SOC_REG_INT_JBDSUM2_TCID_6r */
   9935         soc_block_list[81],
   9936         soc_genreg,
   9937         1,
   9938         0,
   9939         0x86c46,
   9940         SOC_REG_FLAG_RO,
   9941         0,
   9942         1,
   9943         soc_JBDSUM1_TCID_0r_fields,
   9944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9945         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9946         -1,
   9947         -1,
   9948     },
   9949 #endif /* chips */
   9950 
   9951 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9952     { /* SOC_REG_INT_JBDSUM2_TCID_7r */
   9953         soc_block_list[81],
   9954         soc_genreg,
   9955         1,
   9956         0,
   9957         0x87c46,
   9958         SOC_REG_FLAG_RO,
   9959         0,
   9960         1,
   9961         soc_JBDSUM1_TCID_0r_fields,
   9962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9963         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9964         -1,
   9965         -1,
   9966     },
   9967 #endif /* chips */
   9968 
   9969 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9970     { /* SOC_REG_INT_JBDSUM2_TCID_8r */
   9971         soc_block_list[81],
   9972         soc_genreg,
   9973         1,
   9974         0,
   9975         0x88c46,
   9976         SOC_REG_FLAG_RO,
   9977         0,
   9978         1,
   9979         soc_JBDSUM1_TCID_0r_fields,
   9980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9981         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9982         -1,
   9983         -1,
   9984     },
   9985 #endif /* chips */
   9986 
   9987 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9988     { /* SOC_REG_INT_JBDSUM2_TCID_9r */
   9989         soc_block_list[81],
   9990         soc_genreg,
   9991         1,
   9992         0,
   9993         0x89c46,
   9994         SOC_REG_FLAG_RO,
   9995         0,
   9996         1,
   9997         soc_JBDSUM1_TCID_0r_fields,
   9998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9999         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10000         -1,
  10001         -1,
  10002     },
  10003 #endif /* chips */
  10004 
  10005 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10006     { /* SOC_REG_INT_JBDSUM2_TCID_10r */
  10007         soc_block_list[81],
  10008         soc_genreg,
  10009         1,
  10010         0,
  10011         0x8ac46,
  10012         SOC_REG_FLAG_RO,
  10013         0,
  10014         1,
  10015         soc_JBDSUM1_TCID_0r_fields,
  10016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10017         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10018         -1,
  10019         -1,
  10020     },
  10021 #endif /* chips */
  10022 
  10023 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10024     { /* SOC_REG_INT_JBDSUM2_TCID_11r */
  10025         soc_block_list[81],
  10026         soc_genreg,
  10027         1,
  10028         0,
  10029         0x8bc46,
  10030         SOC_REG_FLAG_RO,
  10031         0,
  10032         1,
  10033         soc_JBDSUM1_TCID_0r_fields,
  10034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10035         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10036         -1,
  10037         -1,
  10038     },
  10039 #endif /* chips */
  10040 
  10041 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10042     { /* SOC_REG_INT_JBDSUM2_TCID_12r */
  10043         soc_block_list[81],
  10044         soc_genreg,
  10045         1,
  10046         0,
  10047         0x8cc46,
  10048         SOC_REG_FLAG_RO,
  10049         0,
  10050         1,
  10051         soc_JBDSUM1_TCID_0r_fields,
  10052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10053         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10054         -1,
  10055         -1,
  10056     },
  10057 #endif /* chips */
  10058 
  10059 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10060     { /* SOC_REG_INT_JBDSUM2_TCID_13r */
  10061         soc_block_list[81],
  10062         soc_genreg,
  10063         1,
  10064         0,
  10065         0x8dc46,
  10066         SOC_REG_FLAG_RO,
  10067         0,
  10068         1,
  10069         soc_JBDSUM1_TCID_0r_fields,
  10070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10072         -1,
  10073         -1,
  10074     },
  10075 #endif /* chips */
  10076 
  10077 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10078     { /* SOC_REG_INT_JBDSUM2_TCID_14r */
  10079         soc_block_list[81],
  10080         soc_genreg,
  10081         1,
  10082         0,
  10083         0x8ec46,
  10084         SOC_REG_FLAG_RO,
  10085         0,
  10086         1,
  10087         soc_JBDSUM1_TCID_0r_fields,
  10088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10089         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10090         -1,
  10091         -1,
  10092     },
  10093 #endif /* chips */
  10094 
  10095 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10096     { /* SOC_REG_INT_JBDSUM2_TCID_15r */
  10097         soc_block_list[81],
  10098         soc_genreg,
  10099         1,
  10100         0,
  10101         0x8fc46,
  10102         SOC_REG_FLAG_RO,
  10103         0,
  10104         1,
  10105         soc_JBDSUM1_TCID_0r_fields,
  10106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10107         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10108         -1,
  10109         -1,
  10110     },
  10111 #endif /* chips */
  10112 
  10113 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10114     { /* SOC_REG_INT_JBMISSPC_CHID_0r */
  10115         soc_block_list[81],
  10116         soc_genreg,
  10117         1,
  10118         0,
  10119         0x80918,
  10120         SOC_REG_FLAG_RO,
  10121         0,
  10122         1,
  10123         soc_JBMISSPC_CHID_0r_fields,
  10124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10125         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10126         -1,
  10127         -1,
  10128     },
  10129 #endif /* chips */
  10130 
  10131 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10132     { /* SOC_REG_INT_JBMISSPC_CHID_1r */
  10133         soc_block_list[81],
  10134         soc_genreg,
  10135         1,
  10136         0,
  10137         0x81918,
  10138         SOC_REG_FLAG_RO,
  10139         0,
  10140         1,
  10141         soc_JBMISSPC_CHID_0r_fields,
  10142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10143         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10144         -1,
  10145         -1,
  10146     },
  10147 #endif /* chips */
  10148 
  10149 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10150     { /* SOC_REG_INT_JBMISSPC_CHID_2r */
  10151         soc_block_list[81],
  10152         soc_genreg,
  10153         1,
  10154         0,
  10155         0x82918,
  10156         SOC_REG_FLAG_RO,
  10157         0,
  10158         1,
  10159         soc_JBMISSPC_CHID_0r_fields,
  10160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10162         -1,
  10163         -1,
  10164     },
  10165 #endif /* chips */
  10166 
  10167 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10168     { /* SOC_REG_INT_JBMISSPC_CHID_3r */
  10169         soc_block_list[81],
  10170         soc_genreg,
  10171         1,
  10172         0,
  10173         0x83918,
  10174         SOC_REG_FLAG_RO,
  10175         0,
  10176         1,
  10177         soc_JBMISSPC_CHID_0r_fields,
  10178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10179         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10180         -1,
  10181         -1,
  10182     },
  10183 #endif /* chips */
  10184 
  10185 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10186     { /* SOC_REG_INT_JBMISSPC_CHID_4r */
  10187         soc_block_list[81],
  10188         soc_genreg,
  10189         1,
  10190         0,
  10191         0x84918,
  10192         SOC_REG_FLAG_RO,
  10193         0,
  10194         1,
  10195         soc_JBMISSPC_CHID_0r_fields,
  10196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10197         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10198         -1,
  10199         -1,
  10200     },
  10201 #endif /* chips */
  10202 
  10203 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10204     { /* SOC_REG_INT_JBMISSPC_CHID_5r */
  10205         soc_block_list[81],
  10206         soc_genreg,
  10207         1,
  10208         0,
  10209         0x85918,
  10210         SOC_REG_FLAG_RO,
  10211         0,
  10212         1,
  10213         soc_JBMISSPC_CHID_0r_fields,
  10214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10215         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10216         -1,
  10217         -1,
  10218     },
  10219 #endif /* chips */
  10220 
  10221 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10222     { /* SOC_REG_INT_JBMISSPC_CHID_6r */
  10223         soc_block_list[81],
  10224         soc_genreg,
  10225         1,
  10226         0,
  10227         0x86918,
  10228         SOC_REG_FLAG_RO,
  10229         0,
  10230         1,
  10231         soc_JBMISSPC_CHID_0r_fields,
  10232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10233         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10234         -1,
  10235         -1,
  10236     },
  10237 #endif /* chips */
  10238 
  10239 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10240     { /* SOC_REG_INT_JBMISSPC_CHID_7r */
  10241         soc_block_list[81],
  10242         soc_genreg,
  10243         1,
  10244         0,
  10245         0x87918,
  10246         SOC_REG_FLAG_RO,
  10247         0,
  10248         1,
  10249         soc_JBMISSPC_CHID_0r_fields,
  10250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10252         -1,
  10253         -1,
  10254     },
  10255 #endif /* chips */
  10256 
  10257 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10258     { /* SOC_REG_INT_JBMISSPC_CHID_8r */
  10259         soc_block_list[81],
  10260         soc_genreg,
  10261         1,
  10262         0,
  10263         0x88918,
  10264         SOC_REG_FLAG_RO,
  10265         0,
  10266         1,
  10267         soc_JBMISSPC_CHID_0r_fields,
  10268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10269         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10270         -1,
  10271         -1,
  10272     },
  10273 #endif /* chips */
  10274 
  10275 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10276     { /* SOC_REG_INT_JBMISSPC_CHID_9r */
  10277         soc_block_list[81],
  10278         soc_genreg,
  10279         1,
  10280         0,
  10281         0x89918,
  10282         SOC_REG_FLAG_RO,
  10283         0,
  10284         1,
  10285         soc_JBMISSPC_CHID_0r_fields,
  10286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10288         -1,
  10289         -1,
  10290     },
  10291 #endif /* chips */
  10292 
  10293 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10294     { /* SOC_REG_INT_JBMISSPC_CHID_10r */
  10295         soc_block_list[81],
  10296         soc_genreg,
  10297         1,
  10298         0,
  10299         0x8a918,
  10300         SOC_REG_FLAG_RO,
  10301         0,
  10302         1,
  10303         soc_JBMISSPC_CHID_0r_fields,
  10304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10305         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10306         -1,
  10307         -1,
  10308     },
  10309 #endif /* chips */
  10310 
  10311 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10312     { /* SOC_REG_INT_JBMISSPC_CHID_11r */
  10313         soc_block_list[81],
  10314         soc_genreg,
  10315         1,
  10316         0,
  10317         0x8b918,
  10318         SOC_REG_FLAG_RO,
  10319         0,
  10320         1,
  10321         soc_JBMISSPC_CHID_0r_fields,
  10322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10323         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10324         -1,
  10325         -1,
  10326     },
  10327 #endif /* chips */
  10328 
  10329 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10330     { /* SOC_REG_INT_JBMISSPC_CHID_12r */
  10331         soc_block_list[81],
  10332         soc_genreg,
  10333         1,
  10334         0,
  10335         0x8c918,
  10336         SOC_REG_FLAG_RO,
  10337         0,
  10338         1,
  10339         soc_JBMISSPC_CHID_0r_fields,
  10340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10341         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10342         -1,
  10343         -1,
  10344     },
  10345 #endif /* chips */
  10346 
  10347 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10348     { /* SOC_REG_INT_JBMISSPC_CHID_13r */
  10349         soc_block_list[81],
  10350         soc_genreg,
  10351         1,
  10352         0,
  10353         0x8d918,
  10354         SOC_REG_FLAG_RO,
  10355         0,
  10356         1,
  10357         soc_JBMISSPC_CHID_0r_fields,
  10358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10359         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10360         -1,
  10361         -1,
  10362     },
  10363 #endif /* chips */
  10364 
  10365 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10366     { /* SOC_REG_INT_JBMISSPC_CHID_14r */
  10367         soc_block_list[81],
  10368         soc_genreg,
  10369         1,
  10370         0,
  10371         0x8e918,
  10372         SOC_REG_FLAG_RO,
  10373         0,
  10374         1,
  10375         soc_JBMISSPC_CHID_0r_fields,
  10376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10378         -1,
  10379         -1,
  10380     },
  10381 #endif /* chips */
  10382 
  10383 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10384     { /* SOC_REG_INT_JBMISSPC_CHID_15r */
  10385         soc_block_list[81],
  10386         soc_genreg,
  10387         1,
  10388         0,
  10389         0x8f918,
  10390         SOC_REG_FLAG_RO,
  10391         0,
  10392         1,
  10393         soc_JBMISSPC_CHID_0r_fields,
  10394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10395         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10396         -1,
  10397         -1,
  10398     },
  10399 #endif /* chips */
  10400 
  10401 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10402     { /* SOC_REG_INT_JBMISSPC_CHID_16r */
  10403         soc_block_list[81],
  10404         soc_genreg,
  10405         1,
  10406         0,
  10407         0x90918,
  10408         SOC_REG_FLAG_RO,
  10409         0,
  10410         1,
  10411         soc_JBMISSPC_CHID_0r_fields,
  10412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10413         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10414         -1,
  10415         -1,
  10416     },
  10417 #endif /* chips */
  10418 
  10419 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10420     { /* SOC_REG_INT_JBMISSPC_CHID_17r */
  10421         soc_block_list[81],
  10422         soc_genreg,
  10423         1,
  10424         0,
  10425         0x91918,
  10426         SOC_REG_FLAG_RO,
  10427         0,
  10428         1,
  10429         soc_JBMISSPC_CHID_0r_fields,
  10430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10431         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10432         -1,
  10433         -1,
  10434     },
  10435 #endif /* chips */
  10436 
  10437 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10438     { /* SOC_REG_INT_JBMISSPC_CHID_18r */
  10439         soc_block_list[81],
  10440         soc_genreg,
  10441         1,
  10442         0,
  10443         0x92918,
  10444         SOC_REG_FLAG_RO,
  10445         0,
  10446         1,
  10447         soc_JBMISSPC_CHID_0r_fields,
  10448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10449         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10450         -1,
  10451         -1,
  10452     },
  10453 #endif /* chips */
  10454 
  10455 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10456     { /* SOC_REG_INT_JBMISSPC_CHID_19r */
  10457         soc_block_list[81],
  10458         soc_genreg,
  10459         1,
  10460         0,
  10461         0x93918,
  10462         SOC_REG_FLAG_RO,
  10463         0,
  10464         1,
  10465         soc_JBMISSPC_CHID_0r_fields,
  10466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10467         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10468         -1,
  10469         -1,
  10470     },
  10471 #endif /* chips */
  10472 
  10473 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10474     { /* SOC_REG_INT_JBMISSPC_CHID_20r */
  10475         soc_block_list[81],
  10476         soc_genreg,
  10477         1,
  10478         0,
  10479         0x94918,
  10480         SOC_REG_FLAG_RO,
  10481         0,
  10482         1,
  10483         soc_JBMISSPC_CHID_0r_fields,
  10484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10486         -1,
  10487         -1,
  10488     },
  10489 #endif /* chips */
  10490 
  10491 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10492     { /* SOC_REG_INT_JBMISSPC_CHID_21r */
  10493         soc_block_list[81],
  10494         soc_genreg,
  10495         1,
  10496         0,
  10497         0x95918,
  10498         SOC_REG_FLAG_RO,
  10499         0,
  10500         1,
  10501         soc_JBMISSPC_CHID_0r_fields,
  10502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10503         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10504         -1,
  10505         -1,
  10506     },
  10507 #endif /* chips */
  10508 
  10509 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10510     { /* SOC_REG_INT_JBMISSPC_CHID_22r */
  10511         soc_block_list[81],
  10512         soc_genreg,
  10513         1,
  10514         0,
  10515         0x96918,
  10516         SOC_REG_FLAG_RO,
  10517         0,
  10518         1,
  10519         soc_JBMISSPC_CHID_0r_fields,
  10520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10522         -1,
  10523         -1,
  10524     },
  10525 #endif /* chips */
  10526 
  10527 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10528     { /* SOC_REG_INT_JBMISSPC_CHID_23r */
  10529         soc_block_list[81],
  10530         soc_genreg,
  10531         1,
  10532         0,
  10533         0x97918,
  10534         SOC_REG_FLAG_RO,
  10535         0,
  10536         1,
  10537         soc_JBMISSPC_CHID_0r_fields,
  10538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10540         -1,
  10541         -1,
  10542     },
  10543 #endif /* chips */
  10544 
  10545 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10546     { /* SOC_REG_INT_JBMISSPC_CHID_24r */
  10547         soc_block_list[81],
  10548         soc_genreg,
  10549         1,
  10550         0,
  10551         0x98918,
  10552         SOC_REG_FLAG_RO,
  10553         0,
  10554         1,
  10555         soc_JBMISSPC_CHID_0r_fields,
  10556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10558         -1,
  10559         -1,
  10560     },
  10561 #endif /* chips */
  10562 
  10563 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10564     { /* SOC_REG_INT_JBMISSPC_CHID_25r */
  10565         soc_block_list[81],
  10566         soc_genreg,
  10567         1,
  10568         0,
  10569         0x99918,
  10570         SOC_REG_FLAG_RO,
  10571         0,
  10572         1,
  10573         soc_JBMISSPC_CHID_0r_fields,
  10574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10576         -1,
  10577         -1,
  10578     },
  10579 #endif /* chips */
  10580 
  10581 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10582     { /* SOC_REG_INT_JBMISSPC_CHID_26r */
  10583         soc_block_list[81],
  10584         soc_genreg,
  10585         1,
  10586         0,
  10587         0x9a918,
  10588         SOC_REG_FLAG_RO,
  10589         0,
  10590         1,
  10591         soc_JBMISSPC_CHID_0r_fields,
  10592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10594         -1,
  10595         -1,
  10596     },
  10597 #endif /* chips */
  10598 
  10599 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10600     { /* SOC_REG_INT_JBMISSPC_CHID_27r */
  10601         soc_block_list[81],
  10602         soc_genreg,
  10603         1,
  10604         0,
  10605         0x9b918,
  10606         SOC_REG_FLAG_RO,
  10607         0,
  10608         1,
  10609         soc_JBMISSPC_CHID_0r_fields,
  10610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10612         -1,
  10613         -1,
  10614     },
  10615 #endif /* chips */
  10616 
  10617 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10618     { /* SOC_REG_INT_JBMISSPC_CHID_28r */
  10619         soc_block_list[81],
  10620         soc_genreg,
  10621         1,
  10622         0,
  10623         0x9c918,
  10624         SOC_REG_FLAG_RO,
  10625         0,
  10626         1,
  10627         soc_JBMISSPC_CHID_0r_fields,
  10628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10630         -1,
  10631         -1,
  10632     },
  10633 #endif /* chips */
  10634 
  10635 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10636     { /* SOC_REG_INT_JBMISSPC_CHID_29r */
  10637         soc_block_list[81],
  10638         soc_genreg,
  10639         1,
  10640         0,
  10641         0x9d918,
  10642         SOC_REG_FLAG_RO,
  10643         0,
  10644         1,
  10645         soc_JBMISSPC_CHID_0r_fields,
  10646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10647         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10648         -1,
  10649         -1,
  10650     },
  10651 #endif /* chips */
  10652 
  10653 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10654     { /* SOC_REG_INT_JBMISSPC_CHID_30r */
  10655         soc_block_list[81],
  10656         soc_genreg,
  10657         1,
  10658         0,
  10659         0x9e918,
  10660         SOC_REG_FLAG_RO,
  10661         0,
  10662         1,
  10663         soc_JBMISSPC_CHID_0r_fields,
  10664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10665         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10666         -1,
  10667         -1,
  10668     },
  10669 #endif /* chips */
  10670 
  10671 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10672     { /* SOC_REG_INT_JBMISSPC_CHID_31r */
  10673         soc_block_list[81],
  10674         soc_genreg,
  10675         1,
  10676         0,
  10677         0x9f918,
  10678         SOC_REG_FLAG_RO,
  10679         0,
  10680         1,
  10681         soc_JBMISSPC_CHID_0r_fields,
  10682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10683         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10684         -1,
  10685         -1,
  10686     },
  10687 #endif /* chips */
  10688 
  10689 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10690     { /* SOC_REG_INT_JBMISSPC_CHID_32r */
  10691         soc_block_list[81],
  10692         soc_genreg,
  10693         1,
  10694         0,
  10695         0xa0918,
  10696         SOC_REG_FLAG_RO,
  10697         0,
  10698         1,
  10699         soc_JBMISSPC_CHID_0r_fields,
  10700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10701         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10702         -1,
  10703         -1,
  10704     },
  10705 #endif /* chips */
  10706 
  10707 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10708     { /* SOC_REG_INT_JBMISSPC_CHID_33r */
  10709         soc_block_list[81],
  10710         soc_genreg,
  10711         1,
  10712         0,
  10713         0xa1918,
  10714         SOC_REG_FLAG_RO,
  10715         0,
  10716         1,
  10717         soc_JBMISSPC_CHID_0r_fields,
  10718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10719         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10720         -1,
  10721         -1,
  10722     },
  10723 #endif /* chips */
  10724 
  10725 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10726     { /* SOC_REG_INT_JBMISSPC_CHID_34r */
  10727         soc_block_list[81],
  10728         soc_genreg,
  10729         1,
  10730         0,
  10731         0xa2918,
  10732         SOC_REG_FLAG_RO,
  10733         0,
  10734         1,
  10735         soc_JBMISSPC_CHID_0r_fields,
  10736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10737         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10738         -1,
  10739         -1,
  10740     },
  10741 #endif /* chips */
  10742 
  10743 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10744     { /* SOC_REG_INT_JBMISSPC_CHID_35r */
  10745         soc_block_list[81],
  10746         soc_genreg,
  10747         1,
  10748         0,
  10749         0xa3918,
  10750         SOC_REG_FLAG_RO,
  10751         0,
  10752         1,
  10753         soc_JBMISSPC_CHID_0r_fields,
  10754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10755         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10756         -1,
  10757         -1,
  10758     },
  10759 #endif /* chips */
  10760 
  10761 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10762     { /* SOC_REG_INT_JBMISSPC_CHID_36r */
  10763         soc_block_list[81],
  10764         soc_genreg,
  10765         1,
  10766         0,
  10767         0xa4918,
  10768         SOC_REG_FLAG_RO,
  10769         0,
  10770         1,
  10771         soc_JBMISSPC_CHID_0r_fields,
  10772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10774         -1,
  10775         -1,
  10776     },
  10777 #endif /* chips */
  10778 
  10779 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10780     { /* SOC_REG_INT_JBMISSPC_CHID_37r */
  10781         soc_block_list[81],
  10782         soc_genreg,
  10783         1,
  10784         0,
  10785         0xa5918,
  10786         SOC_REG_FLAG_RO,
  10787         0,
  10788         1,
  10789         soc_JBMISSPC_CHID_0r_fields,
  10790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10792         -1,
  10793         -1,
  10794     },
  10795 #endif /* chips */
  10796 
  10797 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10798     { /* SOC_REG_INT_JBMISSPC_CHID_38r */
  10799         soc_block_list[81],
  10800         soc_genreg,
  10801         1,
  10802         0,
  10803         0xa6918,
  10804         SOC_REG_FLAG_RO,
  10805         0,
  10806         1,
  10807         soc_JBMISSPC_CHID_0r_fields,
  10808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10810         -1,
  10811         -1,
  10812     },
  10813 #endif /* chips */
  10814 
  10815 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10816     { /* SOC_REG_INT_JBMISSPC_CHID_39r */
  10817         soc_block_list[81],
  10818         soc_genreg,
  10819         1,
  10820         0,
  10821         0xa7918,
  10822         SOC_REG_FLAG_RO,
  10823         0,
  10824         1,
  10825         soc_JBMISSPC_CHID_0r_fields,
  10826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10828         -1,
  10829         -1,
  10830     },
  10831 #endif /* chips */
  10832 
  10833 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10834     { /* SOC_REG_INT_JBMISSPC_CHID_40r */
  10835         soc_block_list[81],
  10836         soc_genreg,
  10837         1,
  10838         0,
  10839         0xa8918,
  10840         SOC_REG_FLAG_RO,
  10841         0,
  10842         1,
  10843         soc_JBMISSPC_CHID_0r_fields,
  10844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10845         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10846         -1,
  10847         -1,
  10848     },
  10849 #endif /* chips */
  10850 
  10851 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10852     { /* SOC_REG_INT_JBMISSPC_CHID_41r */
  10853         soc_block_list[81],
  10854         soc_genreg,
  10855         1,
  10856         0,
  10857         0xa9918,
  10858         SOC_REG_FLAG_RO,
  10859         0,
  10860         1,
  10861         soc_JBMISSPC_CHID_0r_fields,
  10862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10863         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10864         -1,
  10865         -1,
  10866     },
  10867 #endif /* chips */
  10868 
  10869 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10870     { /* SOC_REG_INT_JBMISSPC_CHID_42r */
  10871         soc_block_list[81],
  10872         soc_genreg,
  10873         1,
  10874         0,
  10875         0xaa918,
  10876         SOC_REG_FLAG_RO,
  10877         0,
  10878         1,
  10879         soc_JBMISSPC_CHID_0r_fields,
  10880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10882         -1,
  10883         -1,
  10884     },
  10885 #endif /* chips */
  10886 
  10887 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10888     { /* SOC_REG_INT_JBMISSPC_CHID_43r */
  10889         soc_block_list[81],
  10890         soc_genreg,
  10891         1,
  10892         0,
  10893         0xab918,
  10894         SOC_REG_FLAG_RO,
  10895         0,
  10896         1,
  10897         soc_JBMISSPC_CHID_0r_fields,
  10898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10899         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10900         -1,
  10901         -1,
  10902     },
  10903 #endif /* chips */
  10904 
  10905 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10906     { /* SOC_REG_INT_JBMISSPC_CHID_44r */
  10907         soc_block_list[81],
  10908         soc_genreg,
  10909         1,
  10910         0,
  10911         0xac918,
  10912         SOC_REG_FLAG_RO,
  10913         0,
  10914         1,
  10915         soc_JBMISSPC_CHID_0r_fields,
  10916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10918         -1,
  10919         -1,
  10920     },
  10921 #endif /* chips */
  10922 
  10923 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10924     { /* SOC_REG_INT_JBMISSPC_CHID_45r */
  10925         soc_block_list[81],
  10926         soc_genreg,
  10927         1,
  10928         0,
  10929         0xad918,
  10930         SOC_REG_FLAG_RO,
  10931         0,
  10932         1,
  10933         soc_JBMISSPC_CHID_0r_fields,
  10934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10936         -1,
  10937         -1,
  10938     },
  10939 #endif /* chips */
  10940 
  10941 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10942     { /* SOC_REG_INT_JBMISSPC_CHID_46r */
  10943         soc_block_list[81],
  10944         soc_genreg,
  10945         1,
  10946         0,
  10947         0xae918,
  10948         SOC_REG_FLAG_RO,
  10949         0,
  10950         1,
  10951         soc_JBMISSPC_CHID_0r_fields,
  10952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10953         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10954         -1,
  10955         -1,
  10956     },
  10957 #endif /* chips */
  10958 
  10959 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10960     { /* SOC_REG_INT_JBMISSPC_CHID_47r */
  10961         soc_block_list[81],
  10962         soc_genreg,
  10963         1,
  10964         0,
  10965         0xaf918,
  10966         SOC_REG_FLAG_RO,
  10967         0,
  10968         1,
  10969         soc_JBMISSPC_CHID_0r_fields,
  10970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10971         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10972         -1,
  10973         -1,
  10974     },
  10975 #endif /* chips */
  10976 
  10977 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10978     { /* SOC_REG_INT_JBMISSPC_CHID_48r */
  10979         soc_block_list[81],
  10980         soc_genreg,
  10981         1,
  10982         0,
  10983         0xb0918,
  10984         SOC_REG_FLAG_RO,
  10985         0,
  10986         1,
  10987         soc_JBMISSPC_CHID_0r_fields,
  10988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10990         -1,
  10991         -1,
  10992     },
  10993 #endif /* chips */
  10994 
  10995 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10996     { /* SOC_REG_INT_JBMISSPC_CHID_49r */
  10997         soc_block_list[81],
  10998         soc_genreg,
  10999         1,
  11000         0,
  11001         0xb1918,
  11002         SOC_REG_FLAG_RO,
  11003         0,
  11004         1,
  11005         soc_JBMISSPC_CHID_0r_fields,
  11006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11007         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11008         -1,
  11009         -1,
  11010     },
  11011 #endif /* chips */
  11012 
  11013 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11014     { /* SOC_REG_INT_JBMISSPC_CHID_50r */
  11015         soc_block_list[81],
  11016         soc_genreg,
  11017         1,
  11018         0,
  11019         0xb2918,
  11020         SOC_REG_FLAG_RO,
  11021         0,
  11022         1,
  11023         soc_JBMISSPC_CHID_0r_fields,
  11024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11026         -1,
  11027         -1,
  11028     },
  11029 #endif /* chips */
  11030 
  11031 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11032     { /* SOC_REG_INT_JBMISSPC_CHID_51r */
  11033         soc_block_list[81],
  11034         soc_genreg,
  11035         1,
  11036         0,
  11037         0xb3918,
  11038         SOC_REG_FLAG_RO,
  11039         0,
  11040         1,
  11041         soc_JBMISSPC_CHID_0r_fields,
  11042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11044         -1,
  11045         -1,
  11046     },
  11047 #endif /* chips */
  11048 
  11049 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11050     { /* SOC_REG_INT_JBMISSPC_CHID_52r */
  11051         soc_block_list[81],
  11052         soc_genreg,
  11053         1,
  11054         0,
  11055         0xb4918,
  11056         SOC_REG_FLAG_RO,
  11057         0,
  11058         1,
  11059         soc_JBMISSPC_CHID_0r_fields,
  11060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11061         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11062         -1,
  11063         -1,
  11064     },
  11065 #endif /* chips */
  11066 
  11067 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11068     { /* SOC_REG_INT_JBMISSPC_CHID_53r */
  11069         soc_block_list[81],
  11070         soc_genreg,
  11071         1,
  11072         0,
  11073         0xb5918,
  11074         SOC_REG_FLAG_RO,
  11075         0,
  11076         1,
  11077         soc_JBMISSPC_CHID_0r_fields,
  11078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11079         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11080         -1,
  11081         -1,
  11082     },
  11083 #endif /* chips */
  11084 
  11085 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11086     { /* SOC_REG_INT_JBMISSPC_CHID_54r */
  11087         soc_block_list[81],
  11088         soc_genreg,
  11089         1,
  11090         0,
  11091         0xb6918,
  11092         SOC_REG_FLAG_RO,
  11093         0,
  11094         1,
  11095         soc_JBMISSPC_CHID_0r_fields,
  11096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11097         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11098         -1,
  11099         -1,
  11100     },
  11101 #endif /* chips */
  11102 
  11103 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11104     { /* SOC_REG_INT_JBMISSPC_CHID_55r */
  11105         soc_block_list[81],
  11106         soc_genreg,
  11107         1,
  11108         0,
  11109         0xb7918,
  11110         SOC_REG_FLAG_RO,
  11111         0,
  11112         1,
  11113         soc_JBMISSPC_CHID_0r_fields,
  11114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11115         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11116         -1,
  11117         -1,
  11118     },
  11119 #endif /* chips */
  11120 
  11121 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11122     { /* SOC_REG_INT_JBMISSPC_CHID_56r */
  11123         soc_block_list[81],
  11124         soc_genreg,
  11125         1,
  11126         0,
  11127         0xb8918,
  11128         SOC_REG_FLAG_RO,
  11129         0,
  11130         1,
  11131         soc_JBMISSPC_CHID_0r_fields,
  11132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11133         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11134         -1,
  11135         -1,
  11136     },
  11137 #endif /* chips */
  11138 
  11139 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11140     { /* SOC_REG_INT_JBMISSPC_CHID_57r */
  11141         soc_block_list[81],
  11142         soc_genreg,
  11143         1,
  11144         0,
  11145         0xb9918,
  11146         SOC_REG_FLAG_RO,
  11147         0,
  11148         1,
  11149         soc_JBMISSPC_CHID_0r_fields,
  11150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11151         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11152         -1,
  11153         -1,
  11154     },
  11155 #endif /* chips */
  11156 
  11157 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11158     { /* SOC_REG_INT_JBMISSPC_CHID_58r */
  11159         soc_block_list[81],
  11160         soc_genreg,
  11161         1,
  11162         0,
  11163         0xba918,
  11164         SOC_REG_FLAG_RO,
  11165         0,
  11166         1,
  11167         soc_JBMISSPC_CHID_0r_fields,
  11168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11169         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11170         -1,
  11171         -1,
  11172     },
  11173 #endif /* chips */
  11174 
  11175 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11176     { /* SOC_REG_INT_JBMISSPC_CHID_59r */
  11177         soc_block_list[81],
  11178         soc_genreg,
  11179         1,
  11180         0,
  11181         0xbb918,
  11182         SOC_REG_FLAG_RO,
  11183         0,
  11184         1,
  11185         soc_JBMISSPC_CHID_0r_fields,
  11186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11188         -1,
  11189         -1,
  11190     },
  11191 #endif /* chips */
  11192 
  11193 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11194     { /* SOC_REG_INT_JBMISSPC_CHID_60r */
  11195         soc_block_list[81],
  11196         soc_genreg,
  11197         1,
  11198         0,
  11199         0xbc918,
  11200         SOC_REG_FLAG_RO,
  11201         0,
  11202         1,
  11203         soc_JBMISSPC_CHID_0r_fields,
  11204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11206         -1,
  11207         -1,
  11208     },
  11209 #endif /* chips */
  11210 
  11211 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11212     { /* SOC_REG_INT_JBMISSPC_CHID_61r */
  11213         soc_block_list[81],
  11214         soc_genreg,
  11215         1,
  11216         0,
  11217         0xbd918,
  11218         SOC_REG_FLAG_RO,
  11219         0,
  11220         1,
  11221         soc_JBMISSPC_CHID_0r_fields,
  11222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11224         -1,
  11225         -1,
  11226     },
  11227 #endif /* chips */
  11228 
  11229 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11230     { /* SOC_REG_INT_JBMISSPC_CHID_62r */
  11231         soc_block_list[81],
  11232         soc_genreg,
  11233         1,
  11234         0,
  11235         0xbe918,
  11236         SOC_REG_FLAG_RO,
  11237         0,
  11238         1,
  11239         soc_JBMISSPC_CHID_0r_fields,
  11240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11241         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11242         -1,
  11243         -1,
  11244     },
  11245 #endif /* chips */
  11246 
  11247 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11248     { /* SOC_REG_INT_JBMISSPC_CHID_63r */
  11249         soc_block_list[81],
  11250         soc_genreg,
  11251         1,
  11252         0,
  11253         0xbf918,
  11254         SOC_REG_FLAG_RO,
  11255         0,
  11256         1,
  11257         soc_JBMISSPC_CHID_0r_fields,
  11258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11259         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11260         -1,
  11261         -1,
  11262     },
  11263 #endif /* chips */
  11264 
  11265 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11266     { /* SOC_REG_INT_JBRSTRT_CHID_0r */
  11267         soc_block_list[81],
  11268         soc_genreg,
  11269         1,
  11270         0,
  11271         0x8091c,
  11272         SOC_REG_FLAG_RO,
  11273         0,
  11274         2,
  11275         soc_JBRSTRT_CHID_0r_fields,
  11276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11277         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11278         -1,
  11279         -1,
  11280     },
  11281 #endif /* chips */
  11282 
  11283 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11284     { /* SOC_REG_INT_JBRSTRT_CHID_1r */
  11285         soc_block_list[81],
  11286         soc_genreg,
  11287         1,
  11288         0,
  11289         0x8191c,
  11290         SOC_REG_FLAG_RO,
  11291         0,
  11292         2,
  11293         soc_JBRSTRT_CHID_0r_fields,
  11294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11296         -1,
  11297         -1,
  11298     },
  11299 #endif /* chips */
  11300 
  11301 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11302     { /* SOC_REG_INT_JBRSTRT_CHID_2r */
  11303         soc_block_list[81],
  11304         soc_genreg,
  11305         1,
  11306         0,
  11307         0x8291c,
  11308         SOC_REG_FLAG_RO,
  11309         0,
  11310         2,
  11311         soc_JBRSTRT_CHID_0r_fields,
  11312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11313         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11314         -1,
  11315         -1,
  11316     },
  11317 #endif /* chips */
  11318 
  11319 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11320     { /* SOC_REG_INT_JBRSTRT_CHID_3r */
  11321         soc_block_list[81],
  11322         soc_genreg,
  11323         1,
  11324         0,
  11325         0x8391c,
  11326         SOC_REG_FLAG_RO,
  11327         0,
  11328         2,
  11329         soc_JBRSTRT_CHID_0r_fields,
  11330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11332         -1,
  11333         -1,
  11334     },
  11335 #endif /* chips */
  11336 
  11337 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11338     { /* SOC_REG_INT_JBRSTRT_CHID_4r */
  11339         soc_block_list[81],
  11340         soc_genreg,
  11341         1,
  11342         0,
  11343         0x8491c,
  11344         SOC_REG_FLAG_RO,
  11345         0,
  11346         2,
  11347         soc_JBRSTRT_CHID_0r_fields,
  11348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11349         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11350         -1,
  11351         -1,
  11352     },
  11353 #endif /* chips */
  11354 
  11355 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11356     { /* SOC_REG_INT_JBRSTRT_CHID_5r */
  11357         soc_block_list[81],
  11358         soc_genreg,
  11359         1,
  11360         0,
  11361         0x8591c,
  11362         SOC_REG_FLAG_RO,
  11363         0,
  11364         2,
  11365         soc_JBRSTRT_CHID_0r_fields,
  11366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11367         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11368         -1,
  11369         -1,
  11370     },
  11371 #endif /* chips */
  11372 
  11373 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11374     { /* SOC_REG_INT_JBRSTRT_CHID_6r */
  11375         soc_block_list[81],
  11376         soc_genreg,
  11377         1,
  11378         0,
  11379         0x8691c,
  11380         SOC_REG_FLAG_RO,
  11381         0,
  11382         2,
  11383         soc_JBRSTRT_CHID_0r_fields,
  11384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11385         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11386         -1,
  11387         -1,
  11388     },
  11389 #endif /* chips */
  11390 
  11391 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11392     { /* SOC_REG_INT_JBRSTRT_CHID_7r */
  11393         soc_block_list[81],
  11394         soc_genreg,
  11395         1,
  11396         0,
  11397         0x8791c,
  11398         SOC_REG_FLAG_RO,
  11399         0,
  11400         2,
  11401         soc_JBRSTRT_CHID_0r_fields,
  11402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11403         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11404         -1,
  11405         -1,
  11406     },
  11407 #endif /* chips */
  11408 
  11409 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11410     { /* SOC_REG_INT_JBRSTRT_CHID_8r */
  11411         soc_block_list[81],
  11412         soc_genreg,
  11413         1,
  11414         0,
  11415         0x8891c,
  11416         SOC_REG_FLAG_RO,
  11417         0,
  11418         2,
  11419         soc_JBRSTRT_CHID_0r_fields,
  11420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11421         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11422         -1,
  11423         -1,
  11424     },
  11425 #endif /* chips */
  11426 
  11427 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11428     { /* SOC_REG_INT_JBRSTRT_CHID_9r */
  11429         soc_block_list[81],
  11430         soc_genreg,
  11431         1,
  11432         0,
  11433         0x8991c,
  11434         SOC_REG_FLAG_RO,
  11435         0,
  11436         2,
  11437         soc_JBRSTRT_CHID_0r_fields,
  11438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11439         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11440         -1,
  11441         -1,
  11442     },
  11443 #endif /* chips */
  11444 
  11445 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11446     { /* SOC_REG_INT_JBRSTRT_CHID_10r */
  11447         soc_block_list[81],
  11448         soc_genreg,
  11449         1,
  11450         0,
  11451         0x8a91c,
  11452         SOC_REG_FLAG_RO,
  11453         0,
  11454         2,
  11455         soc_JBRSTRT_CHID_0r_fields,
  11456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11457         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11458         -1,
  11459         -1,
  11460     },
  11461 #endif /* chips */
  11462 
  11463 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11464     { /* SOC_REG_INT_JBRSTRT_CHID_11r */
  11465         soc_block_list[81],
  11466         soc_genreg,
  11467         1,
  11468         0,
  11469         0x8b91c,
  11470         SOC_REG_FLAG_RO,
  11471         0,
  11472         2,
  11473         soc_JBRSTRT_CHID_0r_fields,
  11474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11475         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11476         -1,
  11477         -1,
  11478     },
  11479 #endif /* chips */
  11480 
  11481 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11482     { /* SOC_REG_INT_JBRSTRT_CHID_12r */
  11483         soc_block_list[81],
  11484         soc_genreg,
  11485         1,
  11486         0,
  11487         0x8c91c,
  11488         SOC_REG_FLAG_RO,
  11489         0,
  11490         2,
  11491         soc_JBRSTRT_CHID_0r_fields,
  11492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11493         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11494         -1,
  11495         -1,
  11496     },
  11497 #endif /* chips */
  11498 
  11499 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11500     { /* SOC_REG_INT_JBRSTRT_CHID_13r */
  11501         soc_block_list[81],
  11502         soc_genreg,
  11503         1,
  11504         0,
  11505         0x8d91c,
  11506         SOC_REG_FLAG_RO,
  11507         0,
  11508         2,
  11509         soc_JBRSTRT_CHID_0r_fields,
  11510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11511         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11512         -1,
  11513         -1,
  11514     },
  11515 #endif /* chips */
  11516 
  11517 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11518     { /* SOC_REG_INT_JBRSTRT_CHID_14r */
  11519         soc_block_list[81],
  11520         soc_genreg,
  11521         1,
  11522         0,
  11523         0x8e91c,
  11524         SOC_REG_FLAG_RO,
  11525         0,
  11526         2,
  11527         soc_JBRSTRT_CHID_0r_fields,
  11528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11529         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11530         -1,
  11531         -1,
  11532     },
  11533 #endif /* chips */
  11534 
  11535 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11536     { /* SOC_REG_INT_JBRSTRT_CHID_15r */
  11537         soc_block_list[81],
  11538         soc_genreg,
  11539         1,
  11540         0,
  11541         0x8f91c,
  11542         SOC_REG_FLAG_RO,
  11543         0,
  11544         2,
  11545         soc_JBRSTRT_CHID_0r_fields,
  11546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11547         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11548         -1,
  11549         -1,
  11550     },
  11551 #endif /* chips */
  11552 
  11553 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11554     { /* SOC_REG_INT_JBRSTRT_CHID_16r */
  11555         soc_block_list[81],
  11556         soc_genreg,
  11557         1,
  11558         0,
  11559         0x9091c,
  11560         SOC_REG_FLAG_RO,
  11561         0,
  11562         2,
  11563         soc_JBRSTRT_CHID_0r_fields,
  11564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11565         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11566         -1,
  11567         -1,
  11568     },
  11569 #endif /* chips */
  11570 
  11571 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11572     { /* SOC_REG_INT_JBRSTRT_CHID_17r */
  11573         soc_block_list[81],
  11574         soc_genreg,
  11575         1,
  11576         0,
  11577         0x9191c,
  11578         SOC_REG_FLAG_RO,
  11579         0,
  11580         2,
  11581         soc_JBRSTRT_CHID_0r_fields,
  11582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11584         -1,
  11585         -1,
  11586     },
  11587 #endif /* chips */
  11588 
  11589 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11590     { /* SOC_REG_INT_JBRSTRT_CHID_18r */
  11591         soc_block_list[81],
  11592         soc_genreg,
  11593         1,
  11594         0,
  11595         0x9291c,
  11596         SOC_REG_FLAG_RO,
  11597         0,
  11598         2,
  11599         soc_JBRSTRT_CHID_0r_fields,
  11600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11602         -1,
  11603         -1,
  11604     },
  11605 #endif /* chips */
  11606 
  11607 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11608     { /* SOC_REG_INT_JBRSTRT_CHID_19r */
  11609         soc_block_list[81],
  11610         soc_genreg,
  11611         1,
  11612         0,
  11613         0x9391c,
  11614         SOC_REG_FLAG_RO,
  11615         0,
  11616         2,
  11617         soc_JBRSTRT_CHID_0r_fields,
  11618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11619         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11620         -1,
  11621         -1,
  11622     },
  11623 #endif /* chips */
  11624 
  11625 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11626     { /* SOC_REG_INT_JBRSTRT_CHID_20r */
  11627         soc_block_list[81],
  11628         soc_genreg,
  11629         1,
  11630         0,
  11631         0x9491c,
  11632         SOC_REG_FLAG_RO,
  11633         0,
  11634         2,
  11635         soc_JBRSTRT_CHID_0r_fields,
  11636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11637         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11638         -1,
  11639         -1,
  11640     },
  11641 #endif /* chips */
  11642 
  11643 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11644     { /* SOC_REG_INT_JBRSTRT_CHID_21r */
  11645         soc_block_list[81],
  11646         soc_genreg,
  11647         1,
  11648         0,
  11649         0x9591c,
  11650         SOC_REG_FLAG_RO,
  11651         0,
  11652         2,
  11653         soc_JBRSTRT_CHID_0r_fields,
  11654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11655         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11656         -1,
  11657         -1,
  11658     },
  11659 #endif /* chips */
  11660 
  11661 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11662     { /* SOC_REG_INT_JBRSTRT_CHID_22r */
  11663         soc_block_list[81],
  11664         soc_genreg,
  11665         1,
  11666         0,
  11667         0x9691c,
  11668         SOC_REG_FLAG_RO,
  11669         0,
  11670         2,
  11671         soc_JBRSTRT_CHID_0r_fields,
  11672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11673         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11674         -1,
  11675         -1,
  11676     },
  11677 #endif /* chips */
  11678 
  11679 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11680     { /* SOC_REG_INT_JBRSTRT_CHID_23r */
  11681         soc_block_list[81],
  11682         soc_genreg,
  11683         1,
  11684         0,
  11685         0x9791c,
  11686         SOC_REG_FLAG_RO,
  11687         0,
  11688         2,
  11689         soc_JBRSTRT_CHID_0r_fields,
  11690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11692         -1,
  11693         -1,
  11694     },
  11695 #endif /* chips */
  11696 
  11697 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11698     { /* SOC_REG_INT_JBRSTRT_CHID_24r */
  11699         soc_block_list[81],
  11700         soc_genreg,
  11701         1,
  11702         0,
  11703         0x9891c,
  11704         SOC_REG_FLAG_RO,
  11705         0,
  11706         2,
  11707         soc_JBRSTRT_CHID_0r_fields,
  11708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11710         -1,
  11711         -1,
  11712     },
  11713 #endif /* chips */
  11714 
  11715 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11716     { /* SOC_REG_INT_JBRSTRT_CHID_25r */
  11717         soc_block_list[81],
  11718         soc_genreg,
  11719         1,
  11720         0,
  11721         0x9991c,
  11722         SOC_REG_FLAG_RO,
  11723         0,
  11724         2,
  11725         soc_JBRSTRT_CHID_0r_fields,
  11726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11727         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11728         -1,
  11729         -1,
  11730     },
  11731 #endif /* chips */
  11732 
  11733 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11734     { /* SOC_REG_INT_JBRSTRT_CHID_26r */
  11735         soc_block_list[81],
  11736         soc_genreg,
  11737         1,
  11738         0,
  11739         0x9a91c,
  11740         SOC_REG_FLAG_RO,
  11741         0,
  11742         2,
  11743         soc_JBRSTRT_CHID_0r_fields,
  11744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11745         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11746         -1,
  11747         -1,
  11748     },
  11749 #endif /* chips */
  11750 
  11751 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11752     { /* SOC_REG_INT_JBRSTRT_CHID_27r */
  11753         soc_block_list[81],
  11754         soc_genreg,
  11755         1,
  11756         0,
  11757         0x9b91c,
  11758         SOC_REG_FLAG_RO,
  11759         0,
  11760         2,
  11761         soc_JBRSTRT_CHID_0r_fields,
  11762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11764         -1,
  11765         -1,
  11766     },
  11767 #endif /* chips */
  11768 
  11769 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11770     { /* SOC_REG_INT_JBRSTRT_CHID_28r */
  11771         soc_block_list[81],
  11772         soc_genreg,
  11773         1,
  11774         0,
  11775         0x9c91c,
  11776         SOC_REG_FLAG_RO,
  11777         0,
  11778         2,
  11779         soc_JBRSTRT_CHID_0r_fields,
  11780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11782         -1,
  11783         -1,
  11784     },
  11785 #endif /* chips */
  11786 
  11787 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11788     { /* SOC_REG_INT_JBRSTRT_CHID_29r */
  11789         soc_block_list[81],
  11790         soc_genreg,
  11791         1,
  11792         0,
  11793         0x9d91c,
  11794         SOC_REG_FLAG_RO,
  11795         0,
  11796         2,
  11797         soc_JBRSTRT_CHID_0r_fields,
  11798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11800         -1,
  11801         -1,
  11802     },
  11803 #endif /* chips */
  11804 
  11805 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11806     { /* SOC_REG_INT_JBRSTRT_CHID_30r */
  11807         soc_block_list[81],
  11808         soc_genreg,
  11809         1,
  11810         0,
  11811         0x9e91c,
  11812         SOC_REG_FLAG_RO,
  11813         0,
  11814         2,
  11815         soc_JBRSTRT_CHID_0r_fields,
  11816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11818         -1,
  11819         -1,
  11820     },
  11821 #endif /* chips */
  11822 
  11823 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11824     { /* SOC_REG_INT_JBRSTRT_CHID_31r */
  11825         soc_block_list[81],
  11826         soc_genreg,
  11827         1,
  11828         0,
  11829         0x9f91c,
  11830         SOC_REG_FLAG_RO,
  11831         0,
  11832         2,
  11833         soc_JBRSTRT_CHID_0r_fields,
  11834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11835         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11836         -1,
  11837         -1,
  11838     },
  11839 #endif /* chips */
  11840 
  11841 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11842     { /* SOC_REG_INT_JBRSTRT_CHID_32r */
  11843         soc_block_list[81],
  11844         soc_genreg,
  11845         1,
  11846         0,
  11847         0xa091c,
  11848         SOC_REG_FLAG_RO,
  11849         0,
  11850         2,
  11851         soc_JBRSTRT_CHID_0r_fields,
  11852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11854         -1,
  11855         -1,
  11856     },
  11857 #endif /* chips */
  11858 
  11859 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11860     { /* SOC_REG_INT_JBRSTRT_CHID_33r */
  11861         soc_block_list[81],
  11862         soc_genreg,
  11863         1,
  11864         0,
  11865         0xa191c,
  11866         SOC_REG_FLAG_RO,
  11867         0,
  11868         2,
  11869         soc_JBRSTRT_CHID_0r_fields,
  11870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11872         -1,
  11873         -1,
  11874     },
  11875 #endif /* chips */
  11876 
  11877 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11878     { /* SOC_REG_INT_JBRSTRT_CHID_34r */
  11879         soc_block_list[81],
  11880         soc_genreg,
  11881         1,
  11882         0,
  11883         0xa291c,
  11884         SOC_REG_FLAG_RO,
  11885         0,
  11886         2,
  11887         soc_JBRSTRT_CHID_0r_fields,
  11888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11889         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11890         -1,
  11891         -1,
  11892     },
  11893 #endif /* chips */
  11894 
  11895 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11896     { /* SOC_REG_INT_JBRSTRT_CHID_35r */
  11897         soc_block_list[81],
  11898         soc_genreg,
  11899         1,
  11900         0,
  11901         0xa391c,
  11902         SOC_REG_FLAG_RO,
  11903         0,
  11904         2,
  11905         soc_JBRSTRT_CHID_0r_fields,
  11906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11907         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11908         -1,
  11909         -1,
  11910     },
  11911 #endif /* chips */
  11912 
  11913 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11914     { /* SOC_REG_INT_JBRSTRT_CHID_36r */
  11915         soc_block_list[81],
  11916         soc_genreg,
  11917         1,
  11918         0,
  11919         0xa491c,
  11920         SOC_REG_FLAG_RO,
  11921         0,
  11922         2,
  11923         soc_JBRSTRT_CHID_0r_fields,
  11924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11926         -1,
  11927         -1,
  11928     },
  11929 #endif /* chips */
  11930 
  11931 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11932     { /* SOC_REG_INT_JBRSTRT_CHID_37r */
  11933         soc_block_list[81],
  11934         soc_genreg,
  11935         1,
  11936         0,
  11937         0xa591c,
  11938         SOC_REG_FLAG_RO,
  11939         0,
  11940         2,
  11941         soc_JBRSTRT_CHID_0r_fields,
  11942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11943         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11944         -1,
  11945         -1,
  11946     },
  11947 #endif /* chips */
  11948 
  11949 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11950     { /* SOC_REG_INT_JBRSTRT_CHID_38r */
  11951         soc_block_list[81],
  11952         soc_genreg,
  11953         1,
  11954         0,
  11955         0xa691c,
  11956         SOC_REG_FLAG_RO,
  11957         0,
  11958         2,
  11959         soc_JBRSTRT_CHID_0r_fields,
  11960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11961         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11962         -1,
  11963         -1,
  11964     },
  11965 #endif /* chips */
  11966 
  11967 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11968     { /* SOC_REG_INT_JBRSTRT_CHID_39r */
  11969         soc_block_list[81],
  11970         soc_genreg,
  11971         1,
  11972         0,
  11973         0xa791c,
  11974         SOC_REG_FLAG_RO,
  11975         0,
  11976         2,
  11977         soc_JBRSTRT_CHID_0r_fields,
  11978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11979         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11980         -1,
  11981         -1,
  11982     },
  11983 #endif /* chips */
  11984 
  11985 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11986     { /* SOC_REG_INT_JBRSTRT_CHID_40r */
  11987         soc_block_list[81],
  11988         soc_genreg,
  11989         1,
  11990         0,
  11991         0xa891c,
  11992         SOC_REG_FLAG_RO,
  11993         0,
  11994         2,
  11995         soc_JBRSTRT_CHID_0r_fields,
  11996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11997         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11998         -1,
  11999         -1,
  12000     },
  12001 #endif /* chips */
  12002 
  12003 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12004     { /* SOC_REG_INT_JBRSTRT_CHID_41r */
  12005         soc_block_list[81],
  12006         soc_genreg,
  12007         1,
  12008         0,
  12009         0xa991c,
  12010         SOC_REG_FLAG_RO,
  12011         0,
  12012         2,
  12013         soc_JBRSTRT_CHID_0r_fields,
  12014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12015         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12016         -1,
  12017         -1,
  12018     },
  12019 #endif /* chips */
  12020 
  12021 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12022     { /* SOC_REG_INT_JBRSTRT_CHID_42r */
  12023         soc_block_list[81],
  12024         soc_genreg,
  12025         1,
  12026         0,
  12027         0xaa91c,
  12028         SOC_REG_FLAG_RO,
  12029         0,
  12030         2,
  12031         soc_JBRSTRT_CHID_0r_fields,
  12032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12034         -1,
  12035         -1,
  12036     },
  12037 #endif /* chips */
  12038 
  12039 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12040     { /* SOC_REG_INT_JBRSTRT_CHID_43r */
  12041         soc_block_list[81],
  12042         soc_genreg,
  12043         1,
  12044         0,
  12045         0xab91c,
  12046         SOC_REG_FLAG_RO,
  12047         0,
  12048         2,
  12049         soc_JBRSTRT_CHID_0r_fields,
  12050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12052         -1,
  12053         -1,
  12054     },
  12055 #endif /* chips */
  12056 
  12057 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12058     { /* SOC_REG_INT_JBRSTRT_CHID_44r */
  12059         soc_block_list[81],
  12060         soc_genreg,
  12061         1,
  12062         0,
  12063         0xac91c,
  12064         SOC_REG_FLAG_RO,
  12065         0,
  12066         2,
  12067         soc_JBRSTRT_CHID_0r_fields,
  12068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12070         -1,
  12071         -1,
  12072     },
  12073 #endif /* chips */
  12074 
  12075 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12076     { /* SOC_REG_INT_JBRSTRT_CHID_45r */
  12077         soc_block_list[81],
  12078         soc_genreg,
  12079         1,
  12080         0,
  12081         0xad91c,
  12082         SOC_REG_FLAG_RO,
  12083         0,
  12084         2,
  12085         soc_JBRSTRT_CHID_0r_fields,
  12086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12088         -1,
  12089         -1,
  12090     },
  12091 #endif /* chips */
  12092 
  12093 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12094     { /* SOC_REG_INT_JBRSTRT_CHID_46r */
  12095         soc_block_list[81],
  12096         soc_genreg,
  12097         1,
  12098         0,
  12099         0xae91c,
  12100         SOC_REG_FLAG_RO,
  12101         0,
  12102         2,
  12103         soc_JBRSTRT_CHID_0r_fields,
  12104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12105         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12106         -1,
  12107         -1,
  12108     },
  12109 #endif /* chips */
  12110 
  12111 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12112     { /* SOC_REG_INT_JBRSTRT_CHID_47r */
  12113         soc_block_list[81],
  12114         soc_genreg,
  12115         1,
  12116         0,
  12117         0xaf91c,
  12118         SOC_REG_FLAG_RO,
  12119         0,
  12120         2,
  12121         soc_JBRSTRT_CHID_0r_fields,
  12122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12124         -1,
  12125         -1,
  12126     },
  12127 #endif /* chips */
  12128 
  12129 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12130     { /* SOC_REG_INT_JBRSTRT_CHID_48r */
  12131         soc_block_list[81],
  12132         soc_genreg,
  12133         1,
  12134         0,
  12135         0xb091c,
  12136         SOC_REG_FLAG_RO,
  12137         0,
  12138         2,
  12139         soc_JBRSTRT_CHID_0r_fields,
  12140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12142         -1,
  12143         -1,
  12144     },
  12145 #endif /* chips */
  12146 
  12147 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12148     { /* SOC_REG_INT_JBRSTRT_CHID_49r */
  12149         soc_block_list[81],
  12150         soc_genreg,
  12151         1,
  12152         0,
  12153         0xb191c,
  12154         SOC_REG_FLAG_RO,
  12155         0,
  12156         2,
  12157         soc_JBRSTRT_CHID_0r_fields,
  12158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12160         -1,
  12161         -1,
  12162     },
  12163 #endif /* chips */
  12164 
  12165 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12166     { /* SOC_REG_INT_JBRSTRT_CHID_50r */
  12167         soc_block_list[81],
  12168         soc_genreg,
  12169         1,
  12170         0,
  12171         0xb291c,
  12172         SOC_REG_FLAG_RO,
  12173         0,
  12174         2,
  12175         soc_JBRSTRT_CHID_0r_fields,
  12176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12178         -1,
  12179         -1,
  12180     },
  12181 #endif /* chips */
  12182 
  12183 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12184     { /* SOC_REG_INT_JBRSTRT_CHID_51r */
  12185         soc_block_list[81],
  12186         soc_genreg,
  12187         1,
  12188         0,
  12189         0xb391c,
  12190         SOC_REG_FLAG_RO,
  12191         0,
  12192         2,
  12193         soc_JBRSTRT_CHID_0r_fields,
  12194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12195         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12196         -1,
  12197         -1,
  12198     },
  12199 #endif /* chips */
  12200 
  12201 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12202     { /* SOC_REG_INT_JBRSTRT_CHID_52r */
  12203         soc_block_list[81],
  12204         soc_genreg,
  12205         1,
  12206         0,
  12207         0xb491c,
  12208         SOC_REG_FLAG_RO,
  12209         0,
  12210         2,
  12211         soc_JBRSTRT_CHID_0r_fields,
  12212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12213         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12214         -1,
  12215         -1,
  12216     },
  12217 #endif /* chips */
  12218 
  12219 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12220     { /* SOC_REG_INT_JBRSTRT_CHID_53r */
  12221         soc_block_list[81],
  12222         soc_genreg,
  12223         1,
  12224         0,
  12225         0xb591c,
  12226         SOC_REG_FLAG_RO,
  12227         0,
  12228         2,
  12229         soc_JBRSTRT_CHID_0r_fields,
  12230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12232         -1,
  12233         -1,
  12234     },
  12235 #endif /* chips */
  12236 
  12237 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12238     { /* SOC_REG_INT_JBRSTRT_CHID_54r */
  12239         soc_block_list[81],
  12240         soc_genreg,
  12241         1,
  12242         0,
  12243         0xb691c,
  12244         SOC_REG_FLAG_RO,
  12245         0,
  12246         2,
  12247         soc_JBRSTRT_CHID_0r_fields,
  12248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12250         -1,
  12251         -1,
  12252     },
  12253 #endif /* chips */
  12254 
  12255 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12256     { /* SOC_REG_INT_JBRSTRT_CHID_55r */
  12257         soc_block_list[81],
  12258         soc_genreg,
  12259         1,
  12260         0,
  12261         0xb791c,
  12262         SOC_REG_FLAG_RO,
  12263         0,
  12264         2,
  12265         soc_JBRSTRT_CHID_0r_fields,
  12266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12267         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12268         -1,
  12269         -1,
  12270     },
  12271 #endif /* chips */
  12272 
  12273 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12274     { /* SOC_REG_INT_JBRSTRT_CHID_56r */
  12275         soc_block_list[81],
  12276         soc_genreg,
  12277         1,
  12278         0,
  12279         0xb891c,
  12280         SOC_REG_FLAG_RO,
  12281         0,
  12282         2,
  12283         soc_JBRSTRT_CHID_0r_fields,
  12284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12285         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12286         -1,
  12287         -1,
  12288     },
  12289 #endif /* chips */
  12290 
  12291 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12292     { /* SOC_REG_INT_JBRSTRT_CHID_57r */
  12293         soc_block_list[81],
  12294         soc_genreg,
  12295         1,
  12296         0,
  12297         0xb991c,
  12298         SOC_REG_FLAG_RO,
  12299         0,
  12300         2,
  12301         soc_JBRSTRT_CHID_0r_fields,
  12302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12303         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12304         -1,
  12305         -1,
  12306     },
  12307 #endif /* chips */
  12308 
  12309 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12310     { /* SOC_REG_INT_JBRSTRT_CHID_58r */
  12311         soc_block_list[81],
  12312         soc_genreg,
  12313         1,
  12314         0,
  12315         0xba91c,
  12316         SOC_REG_FLAG_RO,
  12317         0,
  12318         2,
  12319         soc_JBRSTRT_CHID_0r_fields,
  12320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12321         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12322         -1,
  12323         -1,
  12324     },
  12325 #endif /* chips */
  12326 
  12327 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12328     { /* SOC_REG_INT_JBRSTRT_CHID_59r */
  12329         soc_block_list[81],
  12330         soc_genreg,
  12331         1,
  12332         0,
  12333         0xbb91c,
  12334         SOC_REG_FLAG_RO,
  12335         0,
  12336         2,
  12337         soc_JBRSTRT_CHID_0r_fields,
  12338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12339         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12340         -1,
  12341         -1,
  12342     },
  12343 #endif /* chips */
  12344 
  12345 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12346     { /* SOC_REG_INT_JBRSTRT_CHID_60r */
  12347         soc_block_list[81],
  12348         soc_genreg,
  12349         1,
  12350         0,
  12351         0xbc91c,
  12352         SOC_REG_FLAG_RO,
  12353         0,
  12354         2,
  12355         soc_JBRSTRT_CHID_0r_fields,
  12356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12358         -1,
  12359         -1,
  12360     },
  12361 #endif /* chips */
  12362 
  12363 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12364     { /* SOC_REG_INT_JBRSTRT_CHID_61r */
  12365         soc_block_list[81],
  12366         soc_genreg,
  12367         1,
  12368         0,
  12369         0xbd91c,
  12370         SOC_REG_FLAG_RO,
  12371         0,
  12372         2,
  12373         soc_JBRSTRT_CHID_0r_fields,
  12374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12375         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12376         -1,
  12377         -1,
  12378     },
  12379 #endif /* chips */
  12380 
  12381 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12382     { /* SOC_REG_INT_JBRSTRT_CHID_62r */
  12383         soc_block_list[81],
  12384         soc_genreg,
  12385         1,
  12386         0,
  12387         0xbe91c,
  12388         SOC_REG_FLAG_RO,
  12389         0,
  12390         2,
  12391         soc_JBRSTRT_CHID_0r_fields,
  12392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12393         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12394         -1,
  12395         -1,
  12396     },
  12397 #endif /* chips */
  12398 
  12399 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12400     { /* SOC_REG_INT_JBRSTRT_CHID_63r */
  12401         soc_block_list[81],
  12402         soc_genreg,
  12403         1,
  12404         0,
  12405         0xbf91c,
  12406         SOC_REG_FLAG_RO,
  12407         0,
  12408         2,
  12409         soc_JBRSTRT_CHID_0r_fields,
  12410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12411         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12412         -1,
  12413         -1,
  12414     },
  12415 #endif /* chips */
  12416 
  12417 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12418     { /* SOC_REG_INT_JBSLPCFGr */
  12419         soc_block_list[81],
  12420         soc_genreg,
  12421         1,
  12422         0,
  12423         0x80922,
  12424         0,
  12425         0,
  12426         3,
  12427         soc_JBSLPCFGr_fields,
  12428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12429         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12430         -1,
  12431         -1,
  12432     },
  12433 #endif /* chips */
  12434 
  12435 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12436     { /* SOC_REG_INT_JBSLPCMDr */
  12437         soc_block_list[81],
  12438         soc_genreg,
  12439         1,
  12440         0,
  12441         0x80920,
  12442         0,
  12443         0,
  12444         6,
  12445         soc_JBSLPCMDr_fields,
  12446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12448         -1,
  12449         -1,
  12450     },
  12451 #endif /* chips */
  12452 
  12453 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12454     { /* SOC_REG_INT_JBUNDRPC_CHID_0r */
  12455         soc_block_list[81],
  12456         soc_genreg,
  12457         1,
  12458         0,
  12459         0x8091a,
  12460         SOC_REG_FLAG_RO,
  12461         0,
  12462         1,
  12463         soc_JBUNDRPC_CHID_0r_fields,
  12464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12465         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12466         -1,
  12467         -1,
  12468     },
  12469 #endif /* chips */
  12470 
  12471 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12472     { /* SOC_REG_INT_JBUNDRPC_CHID_1r */
  12473         soc_block_list[81],
  12474         soc_genreg,
  12475         1,
  12476         0,
  12477         0x8191a,
  12478         SOC_REG_FLAG_RO,
  12479         0,
  12480         1,
  12481         soc_JBUNDRPC_CHID_0r_fields,
  12482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12484         -1,
  12485         -1,
  12486     },
  12487 #endif /* chips */
  12488 
  12489 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12490     { /* SOC_REG_INT_JBUNDRPC_CHID_2r */
  12491         soc_block_list[81],
  12492         soc_genreg,
  12493         1,
  12494         0,
  12495         0x8291a,
  12496         SOC_REG_FLAG_RO,
  12497         0,
  12498         1,
  12499         soc_JBUNDRPC_CHID_0r_fields,
  12500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12502         -1,
  12503         -1,
  12504     },
  12505 #endif /* chips */
  12506 
  12507 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12508     { /* SOC_REG_INT_JBUNDRPC_CHID_3r */
  12509         soc_block_list[81],
  12510         soc_genreg,
  12511         1,
  12512         0,
  12513         0x8391a,
  12514         SOC_REG_FLAG_RO,
  12515         0,
  12516         1,
  12517         soc_JBUNDRPC_CHID_0r_fields,
  12518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12519         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12520         -1,
  12521         -1,
  12522     },
  12523 #endif /* chips */
  12524 
  12525 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12526     { /* SOC_REG_INT_JBUNDRPC_CHID_4r */
  12527         soc_block_list[81],
  12528         soc_genreg,
  12529         1,
  12530         0,
  12531         0x8491a,
  12532         SOC_REG_FLAG_RO,
  12533         0,
  12534         1,
  12535         soc_JBUNDRPC_CHID_0r_fields,
  12536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12538         -1,
  12539         -1,
  12540     },
  12541 #endif /* chips */
  12542 
  12543 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12544     { /* SOC_REG_INT_JBUNDRPC_CHID_5r */
  12545         soc_block_list[81],
  12546         soc_genreg,
  12547         1,
  12548         0,
  12549         0x8591a,
  12550         SOC_REG_FLAG_RO,
  12551         0,
  12552         1,
  12553         soc_JBUNDRPC_CHID_0r_fields,
  12554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12556         -1,
  12557         -1,
  12558     },
  12559 #endif /* chips */
  12560 
  12561 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12562     { /* SOC_REG_INT_JBUNDRPC_CHID_6r */
  12563         soc_block_list[81],
  12564         soc_genreg,
  12565         1,
  12566         0,
  12567         0x8691a,
  12568         SOC_REG_FLAG_RO,
  12569         0,
  12570         1,
  12571         soc_JBUNDRPC_CHID_0r_fields,
  12572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12574         -1,
  12575         -1,
  12576     },
  12577 #endif /* chips */
  12578 
  12579 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12580     { /* SOC_REG_INT_JBUNDRPC_CHID_7r */
  12581         soc_block_list[81],
  12582         soc_genreg,
  12583         1,
  12584         0,
  12585         0x8791a,
  12586         SOC_REG_FLAG_RO,
  12587         0,
  12588         1,
  12589         soc_JBUNDRPC_CHID_0r_fields,
  12590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12592         -1,
  12593         -1,
  12594     },
  12595 #endif /* chips */
  12596 
  12597 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12598     { /* SOC_REG_INT_JBUNDRPC_CHID_8r */
  12599         soc_block_list[81],
  12600         soc_genreg,
  12601         1,
  12602         0,
  12603         0x8891a,
  12604         SOC_REG_FLAG_RO,
  12605         0,
  12606         1,
  12607         soc_JBUNDRPC_CHID_0r_fields,
  12608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12609         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12610         -1,
  12611         -1,
  12612     },
  12613 #endif /* chips */
  12614 
  12615 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12616     { /* SOC_REG_INT_JBUNDRPC_CHID_9r */
  12617         soc_block_list[81],
  12618         soc_genreg,
  12619         1,
  12620         0,
  12621         0x8991a,
  12622         SOC_REG_FLAG_RO,
  12623         0,
  12624         1,
  12625         soc_JBUNDRPC_CHID_0r_fields,
  12626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12628         -1,
  12629         -1,
  12630     },
  12631 #endif /* chips */
  12632 
  12633 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12634     { /* SOC_REG_INT_JBUNDRPC_CHID_10r */
  12635         soc_block_list[81],
  12636         soc_genreg,
  12637         1,
  12638         0,
  12639         0x8a91a,
  12640         SOC_REG_FLAG_RO,
  12641         0,
  12642         1,
  12643         soc_JBUNDRPC_CHID_0r_fields,
  12644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12646         -1,
  12647         -1,
  12648     },
  12649 #endif /* chips */
  12650 
  12651 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12652     { /* SOC_REG_INT_JBUNDRPC_CHID_11r */
  12653         soc_block_list[81],
  12654         soc_genreg,
  12655         1,
  12656         0,
  12657         0x8b91a,
  12658         SOC_REG_FLAG_RO,
  12659         0,
  12660         1,
  12661         soc_JBUNDRPC_CHID_0r_fields,
  12662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12663         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12664         -1,
  12665         -1,
  12666     },
  12667 #endif /* chips */
  12668 
  12669 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12670     { /* SOC_REG_INT_JBUNDRPC_CHID_12r */
  12671         soc_block_list[81],
  12672         soc_genreg,
  12673         1,
  12674         0,
  12675         0x8c91a,
  12676         SOC_REG_FLAG_RO,
  12677         0,
  12678         1,
  12679         soc_JBUNDRPC_CHID_0r_fields,
  12680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12682         -1,
  12683         -1,
  12684     },
  12685 #endif /* chips */
  12686 
  12687 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12688     { /* SOC_REG_INT_JBUNDRPC_CHID_13r */
  12689         soc_block_list[81],
  12690         soc_genreg,
  12691         1,
  12692         0,
  12693         0x8d91a,
  12694         SOC_REG_FLAG_RO,
  12695         0,
  12696         1,
  12697         soc_JBUNDRPC_CHID_0r_fields,
  12698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12700         -1,
  12701         -1,
  12702     },
  12703 #endif /* chips */
  12704 
  12705 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12706     { /* SOC_REG_INT_JBUNDRPC_CHID_14r */
  12707         soc_block_list[81],
  12708         soc_genreg,
  12709         1,
  12710         0,
  12711         0x8e91a,
  12712         SOC_REG_FLAG_RO,
  12713         0,
  12714         1,
  12715         soc_JBUNDRPC_CHID_0r_fields,
  12716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12718         -1,
  12719         -1,
  12720     },
  12721 #endif /* chips */
  12722 
  12723 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12724     { /* SOC_REG_INT_JBUNDRPC_CHID_15r */
  12725         soc_block_list[81],
  12726         soc_genreg,
  12727         1,
  12728         0,
  12729         0x8f91a,
  12730         SOC_REG_FLAG_RO,
  12731         0,
  12732         1,
  12733         soc_JBUNDRPC_CHID_0r_fields,
  12734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12736         -1,
  12737         -1,
  12738     },
  12739 #endif /* chips */
  12740 
  12741 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12742     { /* SOC_REG_INT_JBUNDRPC_CHID_16r */
  12743         soc_block_list[81],
  12744         soc_genreg,
  12745         1,
  12746         0,
  12747         0x9091a,
  12748         SOC_REG_FLAG_RO,
  12749         0,
  12750         1,
  12751         soc_JBUNDRPC_CHID_0r_fields,
  12752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12754         -1,
  12755         -1,
  12756     },
  12757 #endif /* chips */
  12758 
  12759 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12760     { /* SOC_REG_INT_JBUNDRPC_CHID_17r */
  12761         soc_block_list[81],
  12762         soc_genreg,
  12763         1,
  12764         0,
  12765         0x9191a,
  12766         SOC_REG_FLAG_RO,
  12767         0,
  12768         1,
  12769         soc_JBUNDRPC_CHID_0r_fields,
  12770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12772         -1,
  12773         -1,
  12774     },
  12775 #endif /* chips */
  12776 
  12777 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12778     { /* SOC_REG_INT_JBUNDRPC_CHID_18r */
  12779         soc_block_list[81],
  12780         soc_genreg,
  12781         1,
  12782         0,
  12783         0x9291a,
  12784         SOC_REG_FLAG_RO,
  12785         0,
  12786         1,
  12787         soc_JBUNDRPC_CHID_0r_fields,
  12788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12790         -1,
  12791         -1,
  12792     },
  12793 #endif /* chips */
  12794 
  12795 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12796     { /* SOC_REG_INT_JBUNDRPC_CHID_19r */
  12797         soc_block_list[81],
  12798         soc_genreg,
  12799         1,
  12800         0,
  12801         0x9391a,
  12802         SOC_REG_FLAG_RO,
  12803         0,
  12804         1,
  12805         soc_JBUNDRPC_CHID_0r_fields,
  12806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12808         -1,
  12809         -1,
  12810     },
  12811 #endif /* chips */
  12812 
  12813 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12814     { /* SOC_REG_INT_JBUNDRPC_CHID_20r */
  12815         soc_block_list[81],
  12816         soc_genreg,
  12817         1,
  12818         0,
  12819         0x9491a,
  12820         SOC_REG_FLAG_RO,
  12821         0,
  12822         1,
  12823         soc_JBUNDRPC_CHID_0r_fields,
  12824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12825         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12826         -1,
  12827         -1,
  12828     },
  12829 #endif /* chips */
  12830 
  12831 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12832     { /* SOC_REG_INT_JBUNDRPC_CHID_21r */
  12833         soc_block_list[81],
  12834         soc_genreg,
  12835         1,
  12836         0,
  12837         0x9591a,
  12838         SOC_REG_FLAG_RO,
  12839         0,
  12840         1,
  12841         soc_JBUNDRPC_CHID_0r_fields,
  12842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12843         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12844         -1,
  12845         -1,
  12846     },
  12847 #endif /* chips */
  12848 
  12849 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12850     { /* SOC_REG_INT_JBUNDRPC_CHID_22r */
  12851         soc_block_list[81],
  12852         soc_genreg,
  12853         1,
  12854         0,
  12855         0x9691a,
  12856         SOC_REG_FLAG_RO,
  12857         0,
  12858         1,
  12859         soc_JBUNDRPC_CHID_0r_fields,
  12860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12861         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12862         -1,
  12863         -1,
  12864     },
  12865 #endif /* chips */
  12866 
  12867 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12868     { /* SOC_REG_INT_JBUNDRPC_CHID_23r */
  12869         soc_block_list[81],
  12870         soc_genreg,
  12871         1,
  12872         0,
  12873         0x9791a,
  12874         SOC_REG_FLAG_RO,
  12875         0,
  12876         1,
  12877         soc_JBUNDRPC_CHID_0r_fields,
  12878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12879         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12880         -1,
  12881         -1,
  12882     },
  12883 #endif /* chips */
  12884 
  12885 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12886     { /* SOC_REG_INT_JBUNDRPC_CHID_24r */
  12887         soc_block_list[81],
  12888         soc_genreg,
  12889         1,
  12890         0,
  12891         0x9891a,
  12892         SOC_REG_FLAG_RO,
  12893         0,
  12894         1,
  12895         soc_JBUNDRPC_CHID_0r_fields,
  12896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12898         -1,
  12899         -1,
  12900     },
  12901 #endif /* chips */
  12902 
  12903 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12904     { /* SOC_REG_INT_JBUNDRPC_CHID_25r */
  12905         soc_block_list[81],
  12906         soc_genreg,
  12907         1,
  12908         0,
  12909         0x9991a,
  12910         SOC_REG_FLAG_RO,
  12911         0,
  12912         1,
  12913         soc_JBUNDRPC_CHID_0r_fields,
  12914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12916         -1,
  12917         -1,
  12918     },
  12919 #endif /* chips */
  12920 
  12921 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12922     { /* SOC_REG_INT_JBUNDRPC_CHID_26r */
  12923         soc_block_list[81],
  12924         soc_genreg,
  12925         1,
  12926         0,
  12927         0x9a91a,
  12928         SOC_REG_FLAG_RO,
  12929         0,
  12930         1,
  12931         soc_JBUNDRPC_CHID_0r_fields,
  12932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12934         -1,
  12935         -1,
  12936     },
  12937 #endif /* chips */
  12938 
  12939 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12940     { /* SOC_REG_INT_JBUNDRPC_CHID_27r */
  12941         soc_block_list[81],
  12942         soc_genreg,
  12943         1,
  12944         0,
  12945         0x9b91a,
  12946         SOC_REG_FLAG_RO,
  12947         0,
  12948         1,
  12949         soc_JBUNDRPC_CHID_0r_fields,
  12950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12952         -1,
  12953         -1,
  12954     },
  12955 #endif /* chips */
  12956 
  12957 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12958     { /* SOC_REG_INT_JBUNDRPC_CHID_28r */
  12959         soc_block_list[81],
  12960         soc_genreg,
  12961         1,
  12962         0,
  12963         0x9c91a,
  12964         SOC_REG_FLAG_RO,
  12965         0,
  12966         1,
  12967         soc_JBUNDRPC_CHID_0r_fields,
  12968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12970         -1,
  12971         -1,
  12972     },
  12973 #endif /* chips */
  12974 
  12975 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12976     { /* SOC_REG_INT_JBUNDRPC_CHID_29r */
  12977         soc_block_list[81],
  12978         soc_genreg,
  12979         1,
  12980         0,
  12981         0x9d91a,
  12982         SOC_REG_FLAG_RO,
  12983         0,
  12984         1,
  12985         soc_JBUNDRPC_CHID_0r_fields,
  12986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12987         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12988         -1,
  12989         -1,
  12990     },
  12991 #endif /* chips */
  12992 
  12993 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12994     { /* SOC_REG_INT_JBUNDRPC_CHID_30r */
  12995         soc_block_list[81],
  12996         soc_genreg,
  12997         1,
  12998         0,
  12999         0x9e91a,
  13000         SOC_REG_FLAG_RO,
  13001         0,
  13002         1,
  13003         soc_JBUNDRPC_CHID_0r_fields,
  13004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13006         -1,
  13007         -1,
  13008     },
  13009 #endif /* chips */
  13010 
  13011 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13012     { /* SOC_REG_INT_JBUNDRPC_CHID_31r */
  13013         soc_block_list[81],
  13014         soc_genreg,
  13015         1,
  13016         0,
  13017         0x9f91a,
  13018         SOC_REG_FLAG_RO,
  13019         0,
  13020         1,
  13021         soc_JBUNDRPC_CHID_0r_fields,
  13022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13023         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13024         -1,
  13025         -1,
  13026     },
  13027 #endif /* chips */
  13028 
  13029 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13030     { /* SOC_REG_INT_JBUNDRPC_CHID_32r */
  13031         soc_block_list[81],
  13032         soc_genreg,
  13033         1,
  13034         0,
  13035         0xa091a,
  13036         SOC_REG_FLAG_RO,
  13037         0,
  13038         1,
  13039         soc_JBUNDRPC_CHID_0r_fields,
  13040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13041         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13042         -1,
  13043         -1,
  13044     },
  13045 #endif /* chips */
  13046 
  13047 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13048     { /* SOC_REG_INT_JBUNDRPC_CHID_33r */
  13049         soc_block_list[81],
  13050         soc_genreg,
  13051         1,
  13052         0,
  13053         0xa191a,
  13054         SOC_REG_FLAG_RO,
  13055         0,
  13056         1,
  13057         soc_JBUNDRPC_CHID_0r_fields,
  13058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13059         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13060         -1,
  13061         -1,
  13062     },
  13063 #endif /* chips */
  13064 
  13065 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13066     { /* SOC_REG_INT_JBUNDRPC_CHID_34r */
  13067         soc_block_list[81],
  13068         soc_genreg,
  13069         1,
  13070         0,
  13071         0xa291a,
  13072         SOC_REG_FLAG_RO,
  13073         0,
  13074         1,
  13075         soc_JBUNDRPC_CHID_0r_fields,
  13076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13077         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13078         -1,
  13079         -1,
  13080     },
  13081 #endif /* chips */
  13082 
  13083 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13084     { /* SOC_REG_INT_JBUNDRPC_CHID_35r */
  13085         soc_block_list[81],
  13086         soc_genreg,
  13087         1,
  13088         0,
  13089         0xa391a,
  13090         SOC_REG_FLAG_RO,
  13091         0,
  13092         1,
  13093         soc_JBUNDRPC_CHID_0r_fields,
  13094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13095         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13096         -1,
  13097         -1,
  13098     },
  13099 #endif /* chips */
  13100 
  13101 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13102     { /* SOC_REG_INT_JBUNDRPC_CHID_36r */
  13103         soc_block_list[81],
  13104         soc_genreg,
  13105         1,
  13106         0,
  13107         0xa491a,
  13108         SOC_REG_FLAG_RO,
  13109         0,
  13110         1,
  13111         soc_JBUNDRPC_CHID_0r_fields,
  13112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13113         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13114         -1,
  13115         -1,
  13116     },
  13117 #endif /* chips */
  13118 
  13119 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13120     { /* SOC_REG_INT_JBUNDRPC_CHID_37r */
  13121         soc_block_list[81],
  13122         soc_genreg,
  13123         1,
  13124         0,
  13125         0xa591a,
  13126         SOC_REG_FLAG_RO,
  13127         0,
  13128         1,
  13129         soc_JBUNDRPC_CHID_0r_fields,
  13130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13131         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13132         -1,
  13133         -1,
  13134     },
  13135 #endif /* chips */
  13136 
  13137 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13138     { /* SOC_REG_INT_JBUNDRPC_CHID_38r */
  13139         soc_block_list[81],
  13140         soc_genreg,
  13141         1,
  13142         0,
  13143         0xa691a,
  13144         SOC_REG_FLAG_RO,
  13145         0,
  13146         1,
  13147         soc_JBUNDRPC_CHID_0r_fields,
  13148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13150         -1,
  13151         -1,
  13152     },
  13153 #endif /* chips */
  13154 
  13155 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13156     { /* SOC_REG_INT_JBUNDRPC_CHID_39r */
  13157         soc_block_list[81],
  13158         soc_genreg,
  13159         1,
  13160         0,
  13161         0xa791a,
  13162         SOC_REG_FLAG_RO,
  13163         0,
  13164         1,
  13165         soc_JBUNDRPC_CHID_0r_fields,
  13166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13167         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13168         -1,
  13169         -1,
  13170     },
  13171 #endif /* chips */
  13172 
  13173 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13174     { /* SOC_REG_INT_JBUNDRPC_CHID_40r */
  13175         soc_block_list[81],
  13176         soc_genreg,
  13177         1,
  13178         0,
  13179         0xa891a,
  13180         SOC_REG_FLAG_RO,
  13181         0,
  13182         1,
  13183         soc_JBUNDRPC_CHID_0r_fields,
  13184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13186         -1,
  13187         -1,
  13188     },
  13189 #endif /* chips */
  13190 
  13191 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13192     { /* SOC_REG_INT_JBUNDRPC_CHID_41r */
  13193         soc_block_list[81],
  13194         soc_genreg,
  13195         1,
  13196         0,
  13197         0xa991a,
  13198         SOC_REG_FLAG_RO,
  13199         0,
  13200         1,
  13201         soc_JBUNDRPC_CHID_0r_fields,
  13202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13203         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13204         -1,
  13205         -1,
  13206     },
  13207 #endif /* chips */
  13208 
  13209 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13210     { /* SOC_REG_INT_JBUNDRPC_CHID_42r */
  13211         soc_block_list[81],
  13212         soc_genreg,
  13213         1,
  13214         0,
  13215         0xaa91a,
  13216         SOC_REG_FLAG_RO,
  13217         0,
  13218         1,
  13219         soc_JBUNDRPC_CHID_0r_fields,
  13220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13221         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13222         -1,
  13223         -1,
  13224     },
  13225 #endif /* chips */
  13226 
  13227 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13228     { /* SOC_REG_INT_JBUNDRPC_CHID_43r */
  13229         soc_block_list[81],
  13230         soc_genreg,
  13231         1,
  13232         0,
  13233         0xab91a,
  13234         SOC_REG_FLAG_RO,
  13235         0,
  13236         1,
  13237         soc_JBUNDRPC_CHID_0r_fields,
  13238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13239         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13240         -1,
  13241         -1,
  13242     },
  13243 #endif /* chips */
  13244 
  13245 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13246     { /* SOC_REG_INT_JBUNDRPC_CHID_44r */
  13247         soc_block_list[81],
  13248         soc_genreg,
  13249         1,
  13250         0,
  13251         0xac91a,
  13252         SOC_REG_FLAG_RO,
  13253         0,
  13254         1,
  13255         soc_JBUNDRPC_CHID_0r_fields,
  13256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13257         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13258         -1,
  13259         -1,
  13260     },
  13261 #endif /* chips */
  13262 
  13263 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13264     { /* SOC_REG_INT_JBUNDRPC_CHID_45r */
  13265         soc_block_list[81],
  13266         soc_genreg,
  13267         1,
  13268         0,
  13269         0xad91a,
  13270         SOC_REG_FLAG_RO,
  13271         0,
  13272         1,
  13273         soc_JBUNDRPC_CHID_0r_fields,
  13274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13275         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13276         -1,
  13277         -1,
  13278     },
  13279 #endif /* chips */
  13280 
  13281 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13282     { /* SOC_REG_INT_JBUNDRPC_CHID_46r */
  13283         soc_block_list[81],
  13284         soc_genreg,
  13285         1,
  13286         0,
  13287         0xae91a,
  13288         SOC_REG_FLAG_RO,
  13289         0,
  13290         1,
  13291         soc_JBUNDRPC_CHID_0r_fields,
  13292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13293         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13294         -1,
  13295         -1,
  13296     },
  13297 #endif /* chips */
  13298 
  13299 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13300     { /* SOC_REG_INT_JBUNDRPC_CHID_47r */
  13301         soc_block_list[81],
  13302         soc_genreg,
  13303         1,
  13304         0,
  13305         0xaf91a,
  13306         SOC_REG_FLAG_RO,
  13307         0,
  13308         1,
  13309         soc_JBUNDRPC_CHID_0r_fields,
  13310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13312         -1,
  13313         -1,
  13314     },
  13315 #endif /* chips */
  13316 
  13317 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13318     { /* SOC_REG_INT_JBUNDRPC_CHID_48r */
  13319         soc_block_list[81],
  13320         soc_genreg,
  13321         1,
  13322         0,
  13323         0xb091a,
  13324         SOC_REG_FLAG_RO,
  13325         0,
  13326         1,
  13327         soc_JBUNDRPC_CHID_0r_fields,
  13328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13329         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13330         -1,
  13331         -1,
  13332     },
  13333 #endif /* chips */
  13334 
  13335 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13336     { /* SOC_REG_INT_JBUNDRPC_CHID_49r */
  13337         soc_block_list[81],
  13338         soc_genreg,
  13339         1,
  13340         0,
  13341         0xb191a,
  13342         SOC_REG_FLAG_RO,
  13343         0,
  13344         1,
  13345         soc_JBUNDRPC_CHID_0r_fields,
  13346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13347         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13348         -1,
  13349         -1,
  13350     },
  13351 #endif /* chips */
  13352 
  13353 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13354     { /* SOC_REG_INT_JBUNDRPC_CHID_50r */
  13355         soc_block_list[81],
  13356         soc_genreg,
  13357         1,
  13358         0,
  13359         0xb291a,
  13360         SOC_REG_FLAG_RO,
  13361         0,
  13362         1,
  13363         soc_JBUNDRPC_CHID_0r_fields,
  13364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13365         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13366         -1,
  13367         -1,
  13368     },
  13369 #endif /* chips */
  13370 
  13371 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13372     { /* SOC_REG_INT_JBUNDRPC_CHID_51r */
  13373         soc_block_list[81],
  13374         soc_genreg,
  13375         1,
  13376         0,
  13377         0xb391a,
  13378         SOC_REG_FLAG_RO,
  13379         0,
  13380         1,
  13381         soc_JBUNDRPC_CHID_0r_fields,
  13382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13384         -1,
  13385         -1,
  13386     },
  13387 #endif /* chips */
  13388 
  13389 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13390     { /* SOC_REG_INT_JBUNDRPC_CHID_52r */
  13391         soc_block_list[81],
  13392         soc_genreg,
  13393         1,
  13394         0,
  13395         0xb491a,
  13396         SOC_REG_FLAG_RO,
  13397         0,
  13398         1,
  13399         soc_JBUNDRPC_CHID_0r_fields,
  13400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13402         -1,
  13403         -1,
  13404     },
  13405 #endif /* chips */
  13406 
  13407 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13408     { /* SOC_REG_INT_JBUNDRPC_CHID_53r */
  13409         soc_block_list[81],
  13410         soc_genreg,
  13411         1,
  13412         0,
  13413         0xb591a,
  13414         SOC_REG_FLAG_RO,
  13415         0,
  13416         1,
  13417         soc_JBUNDRPC_CHID_0r_fields,
  13418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13419         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13420         -1,
  13421         -1,
  13422     },
  13423 #endif /* chips */
  13424 
  13425 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13426     { /* SOC_REG_INT_JBUNDRPC_CHID_54r */
  13427         soc_block_list[81],
  13428         soc_genreg,
  13429         1,
  13430         0,
  13431         0xb691a,
  13432         SOC_REG_FLAG_RO,
  13433         0,
  13434         1,
  13435         soc_JBUNDRPC_CHID_0r_fields,
  13436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13438         -1,
  13439         -1,
  13440     },
  13441 #endif /* chips */
  13442 
  13443 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13444     { /* SOC_REG_INT_JBUNDRPC_CHID_55r */
  13445         soc_block_list[81],
  13446         soc_genreg,
  13447         1,
  13448         0,
  13449         0xb791a,
  13450         SOC_REG_FLAG_RO,
  13451         0,
  13452         1,
  13453         soc_JBUNDRPC_CHID_0r_fields,
  13454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13455         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13456         -1,
  13457         -1,
  13458     },
  13459 #endif /* chips */
  13460 
  13461 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13462     { /* SOC_REG_INT_JBUNDRPC_CHID_56r */
  13463         soc_block_list[81],
  13464         soc_genreg,
  13465         1,
  13466         0,
  13467         0xb891a,
  13468         SOC_REG_FLAG_RO,
  13469         0,
  13470         1,
  13471         soc_JBUNDRPC_CHID_0r_fields,
  13472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13473         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13474         -1,
  13475         -1,
  13476     },
  13477 #endif /* chips */
  13478 
  13479 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13480     { /* SOC_REG_INT_JBUNDRPC_CHID_57r */
  13481         soc_block_list[81],
  13482         soc_genreg,
  13483         1,
  13484         0,
  13485         0xb991a,
  13486         SOC_REG_FLAG_RO,
  13487         0,
  13488         1,
  13489         soc_JBUNDRPC_CHID_0r_fields,
  13490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13491         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13492         -1,
  13493         -1,
  13494     },
  13495 #endif /* chips */
  13496 
  13497 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13498     { /* SOC_REG_INT_JBUNDRPC_CHID_58r */
  13499         soc_block_list[81],
  13500         soc_genreg,
  13501         1,
  13502         0,
  13503         0xba91a,
  13504         SOC_REG_FLAG_RO,
  13505         0,
  13506         1,
  13507         soc_JBUNDRPC_CHID_0r_fields,
  13508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13509         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13510         -1,
  13511         -1,
  13512     },
  13513 #endif /* chips */
  13514 
  13515 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13516     { /* SOC_REG_INT_JBUNDRPC_CHID_59r */
  13517         soc_block_list[81],
  13518         soc_genreg,
  13519         1,
  13520         0,
  13521         0xbb91a,
  13522         SOC_REG_FLAG_RO,
  13523         0,
  13524         1,
  13525         soc_JBUNDRPC_CHID_0r_fields,
  13526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13527         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13528         -1,
  13529         -1,
  13530     },
  13531 #endif /* chips */
  13532 
  13533 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13534     { /* SOC_REG_INT_JBUNDRPC_CHID_60r */
  13535         soc_block_list[81],
  13536         soc_genreg,
  13537         1,
  13538         0,
  13539         0xbc91a,
  13540         SOC_REG_FLAG_RO,
  13541         0,
  13542         1,
  13543         soc_JBUNDRPC_CHID_0r_fields,
  13544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13545         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13546         -1,
  13547         -1,
  13548     },
  13549 #endif /* chips */
  13550 
  13551 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13552     { /* SOC_REG_INT_JBUNDRPC_CHID_61r */
  13553         soc_block_list[81],
  13554         soc_genreg,
  13555         1,
  13556         0,
  13557         0xbd91a,
  13558         SOC_REG_FLAG_RO,
  13559         0,
  13560         1,
  13561         soc_JBUNDRPC_CHID_0r_fields,
  13562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13564         -1,
  13565         -1,
  13566     },
  13567 #endif /* chips */
  13568 
  13569 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13570     { /* SOC_REG_INT_JBUNDRPC_CHID_62r */
  13571         soc_block_list[81],
  13572         soc_genreg,
  13573         1,
  13574         0,
  13575         0xbe91a,
  13576         SOC_REG_FLAG_RO,
  13577         0,
  13578         1,
  13579         soc_JBUNDRPC_CHID_0r_fields,
  13580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13582         -1,
  13583         -1,
  13584     },
  13585 #endif /* chips */
  13586 
  13587 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13588     { /* SOC_REG_INT_JBUNDRPC_CHID_63r */
  13589         soc_block_list[81],
  13590         soc_genreg,
  13591         1,
  13592         0,
  13593         0xbf91a,
  13594         SOC_REG_FLAG_RO,
  13595         0,
  13596         1,
  13597         soc_JBUNDRPC_CHID_0r_fields,
  13598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13600         -1,
  13601         -1,
  13602     },
  13603 #endif /* chips */
  13604 
  13605 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13606     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13607     defined(BCM_56450_B1)
  13608     { /* SOC_REG_INT_JTAG_M0_IDM_IDM_INTERRUPT_STATUSr */
  13609         soc_block_list[61],
  13610         soc_iprocreg,
  13611         1,
  13612         0,
  13613         0x18130a00,
  13614         SOC_REG_FLAG_RO,
  13615         0,
  13616         3,
  13617         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM56450_A0r_fields,
  13618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13619         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13620         -1,
  13621         -1,
  13622     },
  13623 #endif /* chips */
  13624 
  13625 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13626     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13627     defined(BCM_56450_B1)
  13628     { /* SOC_REG_INT_JTAG_M0_IDM_IDM_RESET_CONTROLr */
  13629         soc_block_list[61],
  13630         soc_iprocreg,
  13631         1,
  13632         0,
  13633         0x18130800,
  13634         0,
  13635         0,
  13636         2,
  13637         soc_A9JTAG_M0_IDM_RESET_CONTROL_BCM56450_A0r_fields,
  13638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13639         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13640         -1,
  13641         -1,
  13642     },
  13643 #endif /* chips */
  13644 
  13645 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13646     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13647     defined(BCM_56450_B1)
  13648     { /* SOC_REG_INT_JTAG_M0_IDM_IDM_RESET_STATUSr */
  13649         soc_block_list[61],
  13650         soc_iprocreg,
  13651         1,
  13652         0,
  13653         0x18130804,
  13654         SOC_REG_FLAG_RO,
  13655         0,
  13656         5,
  13657         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM56450_A0r_fields,
  13658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13659         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13660         -1,
  13661         -1,
  13662     },
  13663 #endif /* chips */
  13664