allregs_h.i - openbcm - Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM

allregs_h.i (347666B)
      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_h.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_56504_A0)
     16     { /* SOC_REG_INT_HASH_CONTROLr */
     17         soc_block_list[5],
     18         soc_genreg,
     19         1,
     20         0,
     21         0x1080003,
     22         0,
     23         0,
     24         11,
     25         soc_HASH_CONTROLr_fields,
     26         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
     27         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
     28         -1,
     29         -1,
     30     },
     31 #endif /* chips */
     32 
     33 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
     34     { /* SOC_REG_INT_HASH_CONTROL_BCM53314_A0r */
     35         soc_block_list[5],
     36         soc_genreg,
     37         1,
     38         0,
     39         0x1080004,
     40         0,
     41         0,
     42         12,
     43         soc_HASH_CONTROL_BCM53314_A0r_fields,
     44         SOC_RESET_VAL_DEC(0x01014000, 0x00000000)
     45         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
     46         -1,
     47         -1,
     48     },
     49 #endif /* chips */
     50 
     51 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
     52     defined(BCM_56160_A0)
     53     { /* SOC_REG_INT_HASH_CONTROL_BCM53400_A0r */
     54         soc_block_list[5],
     55         soc_genreg,
     56         1,
     57         0,
     58         0x6000400,
     59         0,
     60         0,
     61         11,
     62         soc_HASH_CONTROL_BCM53400_A0r_fields,
     63         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
     64         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
     65         -1,
     66         -1,
     67     },
     68 #endif /* chips */
     69 
     70 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
     71     { /* SOC_REG_INT_HASH_CONTROL_BCM53570_A0r */
     72         soc_block_list[5],
     73         soc_genreg,
     74         1,
     75         0,
     76         0x6000400,
     77         0,
     78         0,
     79         14,
     80         soc_HASH_CONTROL_BCM56960_A0r_fields,
     81         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
     82         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
     83         -1,
     84         -1,
     85     },
     86 #endif /* chips */
     87 
     88 #if defined(BCM_56142_A0)
     89     { /* SOC_REG_INT_HASH_CONTROL_BCM56142_A0r */
     90         soc_block_list[5],
     91         soc_genreg,
     92         1,
     93         0,
     94         0x1080004,
     95         0,
     96         0,
     97         8,
     98         soc_HASH_CONTROL_BCM56142_A0r_fields,
     99         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
    100         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
    101         -1,
    102         -1,
    103     },
    104 #endif /* chips */
    105 
    106 #if defined(BCM_56150_A0)
    107     { /* SOC_REG_INT_HASH_CONTROL_BCM56150_A0r */
    108         soc_block_list[5],
    109         soc_genreg,
    110         1,
    111         0,
    112         0x6000400,
    113         0,
    114         0,
    115         8,
    116         soc_HASH_CONTROL_BCM56150_A0r_fields,
    117         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
    118         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
    119         -1,
    120         -1,
    121     },
    122 #endif /* chips */
    123 
    124 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
    125     { /* SOC_REG_INT_HASH_CONTROL_BCM56224_A0r */
    126         soc_block_list[5],
    127         soc_genreg,
    128         1,
    129         0,
    130         0x1080004,
    131         0,
    132         0,
    133         12,
    134         soc_HASH_CONTROL_BCM56224_A0r_fields,
    135         SOC_RESET_VAL_DEC(0x01014000, 0x00000000)
    136         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
    137         -1,
    138         -1,
    139     },
    140 #endif /* chips */
    141 
    142 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
    143     defined(BCM_56270_A0)
    144     { /* SOC_REG_INT_HASH_CONTROL_BCM56260_A0r */
    145         soc_block_list[5],
    146         soc_genreg,
    147         1,
    148         0,
    149         0x16002200,
    150         0,
    151         0,
    152         14,
    153         soc_HASH_CONTROL_BCM56260_A0r_fields,
    154         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
    155         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
    156         -1,
    157         -1,
    158     },
    159 #endif /* chips */
    160 
    161 #if defined(BCM_56370_A0)
    162     { /* SOC_REG_INT_HASH_CONTROL_BCM56370_A0r */
    163         soc_block_list[5],
    164         soc_genreg,
    165         1,
    166         0,
    167         0x6a000300,
    168         0,
    169         0,
    170         15,
    171         soc_HASH_CONTROL_BCM56370_A0r_fields,
    172         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
    173         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
    174         -1,
    175         -1,
    176         3,
    177     },
    178 #endif /* chips */
    179 
    180 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    181     defined(BCM_56450_B1)
    182     { /* SOC_REG_INT_HASH_CONTROL_BCM56450_A0r */
    183         soc_block_list[5],
    184         soc_genreg,
    185         1,
    186         0,
    187         0x16002200,
    188         0,
    189         0,
    190         14,
    191         soc_HASH_CONTROL_BCM56450_A0r_fields,
    192         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
    193         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
    194         -1,
    195         -1,
    196     },
    197 #endif /* chips */
    198 
    199 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
    200     defined(BCM_56514_A0)
    201     { /* SOC_REG_INT_HASH_CONTROL_BCM56504_B0r */
    202         soc_block_list[5],
    203         soc_genreg,
    204         1,
    205         0,
    206         0x1080004,
    207         0,
    208         0,
    209         11,
    210         soc_HASH_CONTROLr_fields,
    211         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
    212         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
    213         -1,
    214         -1,
    215     },
    216 #endif /* chips */
    217 
    218 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
    219     defined(BCM_56670_A0) || defined(BCM_56670_B0)
    220     { /* SOC_REG_INT_HASH_CONTROL_BCM56560_A0r */
    221         soc_block_list[5],
    222         soc_genreg,
    223         1,
    224         0,
    225         0x16004000,
    226         0,
    227         0,
    228         15,
    229         soc_HASH_CONTROL_BCM56560_A0r_fields,
    230         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
    231         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
    232         -1,
    233         -1,
    234     },
    235 #endif /* chips */
    236 
    237 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
    238     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    239     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    240     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    241     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
    242     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    243     { /* SOC_REG_INT_HASH_CONTROL_BCM56624_A0r */
    244         soc_block_list[5],
    245         soc_genreg,
    246         1,
    247         0,
    248         0x1080004,
    249         0,
    250         0,
    251         13,
    252         soc_HASH_CONTROL_BCM56800_A0r_fields,
    253         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
    254         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
    255         -1,
    256         -1,
    257     },
    258 #endif /* chips */
    259 
    260 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    261     { /* SOC_REG_INT_HASH_CONTROL_BCM56640_A0r */
    262         soc_block_list[5],
    263         soc_genreg,
    264         1,
    265         0,
    266         0x16002600,
    267         0,
    268         0,
    269         12,
    270         soc_HASH_CONTROL_BCM56640_A0r_fields,
    271         SOC_RESET_VAL_DEC(0x00004000, 0x00000000)
    272         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
    273         -1,
    274         -1,
    275     },
    276 #endif /* chips */
    277 
    278 #if defined(BCM_56770_A0)
    279     { /* SOC_REG_INT_HASH_CONTROL_BCM56770_A0r */
    280         soc_block_list[5],
    281         soc_genreg,
    282         1,
    283         0,
    284         0x6a000300,
    285         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    286         0,
    287         16,
    288         soc_HASH_CONTROL_BCM56770_A0r_fields,
    289         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
    290         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
    291         -1,
    292         -1,
    293         3,
    294     },
    295 #endif /* chips */
    296 
    297 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
    298     defined(BCM_56820_A0)
    299     { /* SOC_REG_INT_HASH_CONTROL_BCM56800_A0r */
    300         soc_block_list[5],
    301         soc_genreg,
    302         1,
    303         0,
    304         0x1080604,
    305         0,
    306         0,
    307         13,
    308         soc_HASH_CONTROL_BCM56800_A0r_fields,
    309         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
    310         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
    311         -1,
    312         -1,
    313     },
    314 #endif /* chips */
    315 
    316 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
    317     defined(BCM_56840_A0)
    318     { /* SOC_REG_INT_HASH_CONTROL_BCM56840_A0r */
    319         soc_block_list[5],
    320         soc_genreg,
    321         1,
    322         0,
    323         0x5080640,
    324         0,
    325         0,
    326         13,
    327         soc_HASH_CONTROL_BCM56800_A0r_fields,
    328         SOC_RESET_VAL_DEC(0x00094000, 0x00000000)
    329         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
    330         -1,
    331         -1,
    332     },
    333 #endif /* chips */
    334 
    335 #if defined(BCM_56840_B0)
    336     { /* SOC_REG_INT_HASH_CONTROL_BCM56840_B0r */
    337         soc_block_list[5],
    338         soc_genreg,
    339         1,
    340         0,
    341         0x5080640,
    342         0,
    343         0,
    344         14,
    345         soc_HASH_CONTROL_BCM56840_B0r_fields,
    346         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
    347         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
    348         -1,
    349         -1,
    350     },
    351 #endif /* chips */
    352 
    353 #if defined(BCM_56850_A0)
    354     { /* SOC_REG_INT_HASH_CONTROL_BCM56850_A0r */
    355         soc_block_list[5],
    356         soc_genreg,
    357         1,
    358         0,
    359         0x16004000,
    360         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    361         0,
    362         14,
    363         soc_HASH_CONTROL_BCM56850_A0r_fields,
    364         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
    365         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
    366         -1,
    367         -1,
    368     },
    369 #endif /* chips */
    370 
    371 #if defined(BCM_56860_A0)
    372     { /* SOC_REG_INT_HASH_CONTROL_BCM56860_A0r */
    373         soc_block_list[5],
    374         soc_genreg,
    375         1,
    376         0,
    377         0x16004000,
    378         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    379         0,
    380         15,
    381         soc_HASH_CONTROL_BCM56860_A0r_fields,
    382         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
    383         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
    384         -1,
    385         -1,
    386     },
    387 #endif /* chips */
    388 
    389 #if defined(BCM_56870_A0)
    390     { /* SOC_REG_INT_HASH_CONTROL_BCM56870_A0r */
    391         soc_block_list[5],
    392         soc_genreg,
    393         1,
    394         0,
    395         0x6a000300,
    396         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    397         0,
    398         15,
    399         soc_HASH_CONTROL_BCM56870_A0r_fields,
    400         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
    401         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
    402         -1,
    403         -1,
    404         3,
    405     },
    406 #endif /* chips */
    407 
    408 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
    409     { /* SOC_REG_INT_HASH_CONTROL_BCM56960_A0r */
    410         soc_block_list[5],
    411         soc_genreg,
    412         1,
    413         0,
    414         0x3a001700,
    415         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    416         0,
    417         14,
    418         soc_HASH_CONTROL_BCM56960_A0r_fields,
    419         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
    420         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
    421         -1,
    422         -1,
    423         3,
    424     },
    425 #endif /* chips */
    426 
    427 #if defined(BCM_56970_A0)
    428     { /* SOC_REG_INT_HASH_CONTROL_BCM56970_A0r */
    429         soc_block_list[5],
    430         soc_genreg,
    431         1,
    432         0,
    433         0x5e001700,
    434         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    435         0,
    436         14,
    437         soc_HASH_CONTROL_BCM56960_A0r_fields,
    438         SOC_RESET_VAL_DEC(0x0c094000, 0x00000000)
    439         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
    440         -1,
    441         -1,
    442         3,
    443     },
    444 #endif /* chips */
    445 
    446 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
    447     { /* SOC_REG_INT_HASH_CONTROL_BCM56980_A0r */
    448         soc_block_list[5],
    449         soc_genreg,
    450         1,
    451         0,
    452         0xe000500,
    453         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    454         0,
    455         10,
    456         soc_HASH_CONTROL_BCM56980_A0r_fields,
    457         SOC_RESET_VAL_DEC(0x00000016, 0x00000000)
    458         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
    459         -1,
    460         -1,
    461         3,
    462     },
    463 #endif /* chips */
    464 
    465 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    466     { /* SOC_REG_INT_HASH_TABLE_PARITY_CONTROLr */
    467         soc_block_list[87],
    468         soc_genreg,
    469         1,
    470         0,
    471         0xfe001a00,
    472         0,
    473         0,
    474         5,
    475         soc_HASH_TABLE_PARITY_CONTROLr_fields,
    476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    477         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
    478         -1,
    479         -1,
    480     },
    481 #endif /* chips */
    482 
    483 #if defined(BCM_88690_A0)
    484     { /* SOC_REG_INT_HBC_BIST_ADDR_CONFIGr */
    485         soc_block_list[165],
    486         soc_genreg,
    487         1,
    488         0,
    489         0x1c2,
    490         SOC_REG_FLAG_ABOVE_64_BITS,
    491         0,
    492         12,
    493         soc_HBC_BIST_ADDR_CONFIGr_fields,
    494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    495         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    496         -1,
    497         -1,
    498     },
    499 #endif /* chips */
    500 
    501 #if defined(BCM_88690_B0)
    502     { /* SOC_REG_INT_HBC_BIST_ADDR_CONFIG_BCM88690_B0r */
    503         soc_block_list[165],
    504         soc_genreg,
    505         1,
    506         0,
    507         0x1a1,
    508         SOC_REG_FLAG_ABOVE_64_BITS,
    509         0,
    510         12,
    511         soc_HBC_BIST_ADDR_CONFIG_BCM88690_B0r_fields,
    512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    514         -1,
    515         -1,
    516     },
    517 #endif /* chips */
    518 
    519 #if defined(BCM_88690_A0)
    520     { /* SOC_REG_INT_HBC_BIST_BANK_REORDERr */
    521         soc_block_list[165],
    522         soc_genreg,
    523         1,
    524         0,
    525         0x1c5,
    526         0,
    527         0,
    528         5,
    529         soc_HBC_BIST_BANK_REORDERr_fields,
    530         SOC_RESET_VAL_DEC(0x00000463, 0x00000000)
    531         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
    532         -1,
    533         -1,
    534     },
    535 #endif /* chips */
    536 
    537 #if defined(BCM_88690_B0)
    538     { /* SOC_REG_INT_HBC_BIST_BANK_REORDER_BCM88690_B0r */
    539         soc_block_list[165],
    540         soc_genreg,
    541         1,
    542         0,
    543         0x1a4,
    544         0,
    545         0,
    546         5,
    547         soc_HBC_BIST_BANK_REORDER_BCM88690_B0r_fields,
    548         SOC_RESET_VAL_DEC(0x00000463, 0x00000000)
    549         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
    550         -1,
    551         -1,
    552     },
    553 #endif /* chips */
    554 
    555 #if defined(BCM_88690_A0)
    556     { /* SOC_REG_INT_HBC_BIST_COMMAND_CONFIGr */
    557         soc_block_list[165],
    558         soc_genreg,
    559         1,
    560         0,
    561         0x1bf,
    562         SOC_REG_FLAG_ABOVE_64_BITS,
    563         0,
    564         4,
    565         soc_HBC_BIST_COMMAND_CONFIGr_fields,
    566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    567         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    568         -1,
    569         -1,
    570     },
    571 #endif /* chips */
    572 
    573 #if defined(BCM_88690_B0)
    574     { /* SOC_REG_INT_HBC_BIST_COMMAND_CONFIG_BCM88690_B0r */
    575         soc_block_list[165],
    576         soc_genreg,
    577         1,
    578         0,
    579         0x19e,
    580         SOC_REG_FLAG_ABOVE_64_BITS,
    581         0,
    582         4,
    583         soc_HBC_BIST_COMMAND_CONFIG_BCM88690_B0r_fields,
    584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    585         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    586         -1,
    587         -1,
    588     },
    589 #endif /* chips */
    590 
    591 #if defined(BCM_88690_A0)
    592     { /* SOC_REG_INT_HBC_BIST_CONTROLr */
    593         soc_block_list[165],
    594         soc_genreg,
    595         1,
    596         0,
    597         0x1ba,
    598         0,
    599         0,
    600         3,
    601         soc_HBC_BIST_CONTROLr_fields,
    602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    603         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    604         -1,
    605         -1,
    606     },
    607 #endif /* chips */
    608 
    609 #if defined(BCM_88690_B0)
    610     { /* SOC_REG_INT_HBC_BIST_CONTROL_BCM88690_B0r */
    611         soc_block_list[165],
    612         soc_genreg,
    613         1,
    614         0,
    615         0x199,
    616         0,
    617         0,
    618         3,
    619         soc_HBC_BIST_CONTROL_BCM88690_B0r_fields,
    620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    621         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    622         -1,
    623         -1,
    624     },
    625 #endif /* chips */
    626 
    627 #if defined(BCM_88690_A0)
    628     { /* SOC_REG_INT_HBC_BIST_DATA_CONFIGr */
    629         soc_block_list[165],
    630         soc_genreg,
    631         1,
    632         0,
    633         0x1c6,
    634         0,
    635         0,
    636         3,
    637         soc_HBC_BIST_DATA_CONFIGr_fields,
    638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    639         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    640         -1,
    641         -1,
    642     },
    643 #endif /* chips */
    644 
    645 #if defined(BCM_88690_B0)
    646     { /* SOC_REG_INT_HBC_BIST_DATA_CONFIG_BCM88690_B0r */
    647         soc_block_list[165],
    648         soc_genreg,
    649         1,
    650         0,
    651         0x1a5,
    652         0,
    653         0,
    654         3,
    655         soc_HBC_BIST_DATA_CONFIG_BCM88690_B0r_fields,
    656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    657         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    658         -1,
    659         -1,
    660     },
    661 #endif /* chips */
    662 
    663 #if defined(BCM_88690_A0)
    664     { /* SOC_REG_INT_HBC_BIST_DATA_MISR_MAPr */
    665         soc_block_list[165],
    666         soc_genreg,
    667         1,
    668         0,
    669         0x21f,
    670         SOC_REG_FLAG_ABOVE_64_BITS,
    671         0,
    672         20,
    673         soc_HBC_BIST_DATA_MISR_MAPr_fields,
    674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    676         -1,
    677         -1,
    678     },
    679 #endif /* chips */
    680 
    681 #if defined(BCM_88690_A0)
    682     { /* SOC_REG_INT_HBC_BIST_DATA_PRESETr */
    683         soc_block_list[165],
    684         soc_genreg,
    685         16,
    686         0,
    687         0x20f,
    688         SOC_REG_FLAG_ARRAY |
    689                           SOC_REG_FLAG_REG_ARRAY,
    690         0,
    691         1,
    692         soc_HBC_BIST_DATA_PRESETr_fields,
    693         SOC_RESET_VAL_DEC(0x000aaaaa, 0x00000000)
    694         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
    695         -1,
    696         -1,
    697     },
    698 #endif /* chips */
    699 
    700 #if defined(BCM_88690_B0)
    701     { /* SOC_REG_INT_HBC_BIST_DATA_PRESET_BCM88690_B0r */
    702         soc_block_list[165],
    703         soc_genreg,
    704         16,
    705         0,
    706         0x1ee,
    707         SOC_REG_FLAG_ARRAY |
    708                           SOC_REG_FLAG_REG_ARRAY,
    709         0,
    710         1,
    711         soc_HBC_BIST_DATA_PRESET_BCM88690_B0r_fields,
    712         SOC_RESET_VAL_DEC(0x000aaaaa, 0x00000000)
    713         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
    714         -1,
    715         -1,
    716     },
    717 #endif /* chips */
    718 
    719 #if defined(BCM_88690_A0)
    720     { /* SOC_REG_INT_HBC_BIST_DWORD_MISR_STATEr */
    721         soc_block_list[165],
    722         soc_genreg,
    723         1,
    724         0,
    725         0x22b,
    726         SOC_REG_FLAG_ABOVE_64_BITS |
    727                           SOC_REG_FLAG_RO,
    728         0,
    729         1,
    730         soc_HBC_BIST_DWORD_MISR_STATEr_fields,
    731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    732         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    733         -1,
    734         -1,
    735     },
    736 #endif /* chips */
    737 
    738 #if defined(BCM_88690_B0)
    739     { /* SOC_REG_INT_HBC_BIST_DWORD_MISR_STATE_BCM88690_B0r */
    740         soc_block_list[165],
    741         soc_genreg,
    742         1,
    743         0,
    744         0x206,
    745         SOC_REG_FLAG_ABOVE_64_BITS |
    746                           SOC_REG_FLAG_RO,
    747         0,
    748         1,
    749         soc_HBC_BIST_DWORD_MISR_STATE_BCM88690_B0r_fields,
    750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    751         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    752         -1,
    753         -1,
    754     },
    755 #endif /* chips */
    756 
    757 #if defined(BCM_88690_A0)
    758     { /* SOC_REG_INT_HBC_BIST_ERR_COUNTERSr */
    759         soc_block_list[165],
    760         soc_genreg,
    761         1,
    762         0,
    763         0x223,
    764         SOC_REG_FLAG_ABOVE_64_BITS |
    765                           SOC_REG_FLAG_RO,
    766         SOC_REG_FLAG_COUNTER_FEILDS |
    767                           SOC_REG_FLAG_INIT_ON_READ,
    768         6,
    769         soc_HBC_BIST_ERR_COUNTERSr_fields,
    770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    772         -1,
    773         -1,
    774     },
    775 #endif /* chips */
    776 
    777 #if defined(BCM_88690_B0)
    778     { /* SOC_REG_INT_HBC_BIST_ERR_COUNTERS_BCM88690_B0r */
    779         soc_block_list[165],
    780         soc_genreg,
    781         1,
    782         0,
    783         0x1fe,
    784         SOC_REG_FLAG_ABOVE_64_BITS |
    785                           SOC_REG_FLAG_RO,
    786         SOC_REG_FLAG_COUNTER_FEILDS |
    787                           SOC_REG_FLAG_INIT_ON_READ,
    788         6,
    789         soc_HBC_BIST_ERR_COUNTERS_BCM88690_B0r_fields,
    790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    792         -1,
    793         -1,
    794     },
    795 #endif /* chips */
    796 
    797 #if defined(BCM_88690_A0)
    798     { /* SOC_REG_INT_HBC_BIST_PATTERNr */
    799         soc_block_list[165],
    800         soc_genreg,
    801         8,
    802         0,
    803         0x1c7,
    804         SOC_REG_FLAG_ABOVE_64_BITS |
    805                           SOC_REG_FLAG_ARRAY |
    806                           SOC_REG_FLAG_REG_ARRAY,
    807         0,
    808         2,
    809         soc_HBC_BIST_PATTERNr_fields,
    810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    811         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    812         -1,
    813         -1,
    814     },
    815 #endif /* chips */
    816 
    817 #if defined(BCM_88690_B0)
    818     { /* SOC_REG_INT_HBC_BIST_PATTERN_BCM88690_B0r */
    819         soc_block_list[165],
    820         soc_genreg,
    821         8,
    822         0,
    823         0x1a6,
    824         SOC_REG_FLAG_ABOVE_64_BITS |
    825                           SOC_REG_FLAG_ARRAY |
    826                           SOC_REG_FLAG_REG_ARRAY,
    827         0,
    828         2,
    829         soc_HBC_BIST_PATTERN_BCM88690_B0r_fields,
    830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    832         -1,
    833         -1,
    834     },
    835 #endif /* chips */
    836 
    837 #if defined(BCM_88690_A0)
    838     { /* SOC_REG_INT_HBC_BIST_STATUSr */
    839         soc_block_list[165],
    840         soc_genreg,
    841         1,
    842         0,
    843         0x1bb,
    844         SOC_REG_FLAG_ABOVE_64_BITS |
    845                           SOC_REG_FLAG_RO,
    846         SOC_REG_FLAG_COUNTER_FEILDS |
    847                           SOC_REG_FLAG_INIT_ON_READ,
    848         5,
    849         soc_HBC_BIST_STATUSr_fields,
    850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    851         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    852         -1,
    853         -1,
    854     },
    855 #endif /* chips */
    856 
    857 #if defined(BCM_88690_B0)
    858     { /* SOC_REG_INT_HBC_BIST_STATUS_BCM88690_B0r */
    859         soc_block_list[165],
    860         soc_genreg,
    861         1,
    862         0,
    863         0x19a,
    864         SOC_REG_FLAG_ABOVE_64_BITS |
    865                           SOC_REG_FLAG_RO,
    866         SOC_REG_FLAG_COUNTER_FEILDS |
    867                           SOC_REG_FLAG_INIT_ON_READ,
    868         5,
    869         soc_HBC_BIST_STATUS_BCM88690_B0r_fields,
    870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    872         -1,
    873         -1,
    874     },
    875 #endif /* chips */
    876 
    877 #if defined(BCM_88690_A0)
    878     { /* SOC_REG_INT_HBC_BLOCKED_BY_COHERENCY_CNTr */
    879         soc_block_list[165],
    880         soc_genreg,
    881         32,
    882         0,
    883         0x13a,
    884         SOC_REG_FLAG_ARRAY |
    885                           SOC_REG_FLAG_RO |
    886                           SOC_REG_FLAG_REG_ARRAY,
    887         SOC_REG_FLAG_COUNTER_FEILDS,
    888         1,
    889         soc_HBC_BLOCKED_BY_COHERENCY_CNTr_fields,
    890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    891         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    892         -1,
    893         -1,
    894     },
    895 #endif /* chips */
    896 
    897 #if defined(BCM_88690_A0)
    898     { /* SOC_REG_INT_HBC_DATA_SOURCE_CONFIGr */
    899         soc_block_list[165],
    900         soc_genreg,
    901         2,
    902         0,
    903         0x110,
    904         SOC_REG_FLAG_ARRAY |
    905                           SOC_REG_FLAG_REG_ARRAY,
    906         0,
    907         2,
    908         soc_HBC_DATA_SOURCE_CONFIGr_fields,
    909         SOC_RESET_VAL_DEC(0x0003e9f4, 0x00000000)
    910         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    911         -1,
    912         -1,
    913     },
    914 #endif /* chips */
    915 
    916 #if defined(BCM_88690_B0)
    917     { /* SOC_REG_INT_HBC_DATA_SOURCE_CONFIG_BCM88690_B0r */
    918         soc_block_list[165],
    919         soc_genreg,
    920         2,
    921         0,
    922         0x10f,
    923         SOC_REG_FLAG_ARRAY |
    924                           SOC_REG_FLAG_REG_ARRAY,
    925         0,
    926         2,
    927         soc_HBC_DATA_SOURCE_CONFIG_BCM88690_B0r_fields,
    928         SOC_RESET_VAL_DEC(0x0003e9f4, 0x00000000)
    929         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    930         -1,
    931         -1,
    932     },
    933 #endif /* chips */
    934 
    935 #if defined(BCM_88690_A0)
    936     { /* SOC_REG_INT_HBC_DRAM_CHANNEL_BLOCKED_CONFIGr */
    937         soc_block_list[165],
    938         soc_genreg,
    939         1,
    940         0,
    941         0x176,
    942         SOC_REG_FLAG_64_BITS,
    943         0,
    944         4,
    945         soc_HBC_DRAM_CHANNEL_BLOCKED_CONFIGr_fields,
    946         SOC_RESET_VAL_DEC(0x3ec02711, 0x00006401)
    947         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
    948         -1,
    949         -1,
    950     },
    951 #endif /* chips */
    952 
    953 #if defined(BCM_88690_B0)
    954     { /* SOC_REG_INT_HBC_DRAM_CHANNEL_BLOCKED_CONFIG_BCM88690_B0r */
    955         soc_block_list[165],
    956         soc_genreg,
    957         1,
    958         0,
    959         0x155,
    960         SOC_REG_FLAG_64_BITS,
    961         0,
    962         4,
    963         soc_HBC_DRAM_CHANNEL_BLOCKED_CONFIG_BCM88690_B0r_fields,
    964         SOC_RESET_VAL_DEC(0x3ec02711, 0x00006401)
    965         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
    966         -1,
    967         -1,
    968     },
    969 #endif /* chips */
    970 
    971 #if defined(BCM_88690_A0)
    972     { /* SOC_REG_INT_HBC_DRAM_CHANNEL_BLOCKED_STATUSr */
    973         soc_block_list[165],
    974         soc_genreg,
    975         1,
    976         0,
    977         0x178,
    978         SOC_REG_FLAG_ABOVE_64_BITS |
    979                           SOC_REG_FLAG_RO,
    980         SOC_REG_FLAG_COUNTER_FEILDS |
    981                           SOC_REG_FLAG_INIT_ON_READ,
    982         3,
    983         soc_HBC_DRAM_CHANNEL_BLOCKED_STATUSr_fields,
    984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    985         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    986         -1,
    987         -1,
    988     },
    989 #endif /* chips */
    990 
    991 #if defined(BCM_88690_B0)
    992     { /* SOC_REG_INT_HBC_DRAM_CHANNEL_BLOCKED_STATUS_BCM88690_B0r */
    993         soc_block_list[165],
    994         soc_genreg,
    995         1,
    996         0,
    997         0x157,
    998         SOC_REG_FLAG_ABOVE_64_BITS |
    999                           SOC_REG_FLAG_RO,
   1000         SOC_REG_FLAG_COUNTER_FEILDS |
   1001                           SOC_REG_FLAG_INIT_ON_READ,
   1002         3,
   1003         soc_HBC_DRAM_CHANNEL_BLOCKED_STATUS_BCM88690_B0r_fields,
   1004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1006         -1,
   1007         -1,
   1008     },
   1009 #endif /* chips */
   1010 
   1011 #if defined(BCM_88690_A0)
   1012     { /* SOC_REG_INT_HBC_DSI_ASYNC_FIFO_CONFIGr */
   1013         soc_block_list[165],
   1014         soc_genreg,
   1015         2,
   1016         0,
   1017         0x112,
   1018         SOC_REG_FLAG_ARRAY |
   1019                           SOC_REG_FLAG_REG_ARRAY,
   1020         0,
   1021         16,
   1022         soc_HBC_DSI_ASYNC_FIFO_CONFIGr_fields,
   1023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1024         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1025         -1,
   1026         -1,
   1027     },
   1028 #endif /* chips */
   1029 
   1030 #if defined(BCM_88690_B0)
   1031     { /* SOC_REG_INT_HBC_DSI_ASYNC_FIFO_CONFIG_BCM88690_B0r */
   1032         soc_block_list[165],
   1033         soc_genreg,
   1034         2,
   1035         0,
   1036         0x111,
   1037         SOC_REG_FLAG_ARRAY |
   1038                           SOC_REG_FLAG_REG_ARRAY,
   1039         0,
   1040         16,
   1041         soc_HBC_DSI_ASYNC_FIFO_CONFIG_BCM88690_B0r_fields,
   1042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1043         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1044         -1,
   1045         -1,
   1046     },
   1047 #endif /* chips */
   1048 
   1049 #if defined(BCM_88690_A0)
   1050     { /* SOC_REG_INT_HBC_DSI_INTERRUPT_MASK_REGISTERr */
   1051         soc_block_list[165],
   1052         soc_genreg,
   1053         1,
   1054         0,
   1055         0x102,
   1056         SOC_REG_FLAG_64_BITS,
   1057         0,
   1058         36,
   1059         soc_HBC_DSI_INTERRUPT_MASK_REGISTERr_fields,
   1060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1061         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
   1062         -1,
   1063         -1,
   1064     },
   1065 #endif /* chips */
   1066 
   1067 #if defined(BCM_88690_B0)
   1068     { /* SOC_REG_INT_HBC_DSI_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
   1069         soc_block_list[165],
   1070         soc_genreg,
   1071         1,
   1072         0,
   1073         0x101,
   1074         0,
   1075         0,
   1076         26,
   1077         soc_HBC_DSI_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
   1078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1079         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   1080         -1,
   1081         -1,
   1082     },
   1083 #endif /* chips */
   1084 
   1085 #if defined(BCM_88690_A0)
   1086     { /* SOC_REG_INT_HBC_DSI_INTERRUPT_REGISTERr */
   1087         soc_block_list[165],
   1088         soc_genreg,
   1089         1,
   1090         0,
   1091         0x100,
   1092         SOC_REG_FLAG_64_BITS |
   1093                           SOC_REG_FLAG_INTERRUPT |
   1094                           SOC_REG_FLAG_SIGNAL,
   1095         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   1096         36,
   1097         soc_HBC_DSI_INTERRUPT_REGISTERr_fields,
   1098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1099         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
   1100         -1,
   1101         -1,
   1102     },
   1103 #endif /* chips */
   1104 
   1105 #if defined(BCM_88690_B0)
   1106     { /* SOC_REG_INT_HBC_DSI_INTERRUPT_REGISTER_BCM88690_B0r */
   1107         soc_block_list[165],
   1108         soc_genreg,
   1109         1,
   1110         0,
   1111         0x100,
   1112         SOC_REG_FLAG_INTERRUPT |
   1113                           SOC_REG_FLAG_SIGNAL,
   1114         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   1115         26,
   1116         soc_HBC_DSI_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   1117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1118         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   1119         -1,
   1120         -1,
   1121     },
   1122 #endif /* chips */
   1123 
   1124 #if defined(BCM_88690_A0)
   1125     { /* SOC_REG_INT_HBC_DSI_INTERRUPT_REGISTER_TESTr */
   1126         soc_block_list[165],
   1127         soc_genreg,
   1128         1,
   1129         0,
   1130         0x103,
   1131         SOC_REG_FLAG_64_BITS,
   1132         0,
   1133         1,
   1134         soc_HBC_DSI_INTERRUPT_REGISTER_TESTr_fields,
   1135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1136         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
   1137         -1,
   1138         -1,
   1139     },
   1140 #endif /* chips */
   1141 
   1142 #if defined(BCM_88690_B0)
   1143     { /* SOC_REG_INT_HBC_DSI_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   1144         soc_block_list[165],
   1145         soc_genreg,
   1146         1,
   1147         0,
   1148         0x102,
   1149         0,
   1150         0,
   1151         1,
   1152         soc_HBC_DSI_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   1153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1154         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   1155         -1,
   1156         -1,
   1157     },
   1158 #endif /* chips */
   1159 
   1160 #if defined(BCM_88690_A0)
   1161     { /* SOC_REG_INT_HBC_ECC_1B_ERR_CNTr */
   1162         soc_block_list[165],
   1163         soc_genreg,
   1164         1,
   1165         0,
   1166         0x94,
   1167         SOC_REG_FLAG_64_BITS |
   1168                           SOC_REG_FLAG_RO,
   1169         SOC_REG_FLAG_COUNTER_FEILDS |
   1170                           SOC_REG_FLAG_INIT_ON_READ,
   1171         4,
   1172         soc_HBC_ECC_1B_ERR_CNTr_fields,
   1173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1174         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1175         -1,
   1176         -1,
   1177     },
   1178 #endif /* chips */
   1179 
   1180 #if defined(BCM_88690_B0)
   1181     { /* SOC_REG_INT_HBC_ECC_1B_ERR_CNT_BCM88690_B0r */
   1182         soc_block_list[165],
   1183         soc_genreg,
   1184         1,
   1185         0,
   1186         0x94,
   1187         SOC_REG_FLAG_64_BITS |
   1188                           SOC_REG_FLAG_RO,
   1189         SOC_REG_FLAG_COUNTER_FEILDS |
   1190                           SOC_REG_FLAG_INIT_ON_READ,
   1191         4,
   1192         soc_HBC_ECC_1B_ERR_CNT_BCM88690_B0r_fields,
   1193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1194         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1195         -1,
   1196         -1,
   1197     },
   1198 #endif /* chips */
   1199 
   1200 #if defined(BCM_88690_A0)
   1201     { /* SOC_REG_INT_HBC_ECC_2B_ERR_CNTr */
   1202         soc_block_list[165],
   1203         soc_genreg,
   1204         1,
   1205         0,
   1206         0x96,
   1207         SOC_REG_FLAG_64_BITS |
   1208                           SOC_REG_FLAG_RO,
   1209         SOC_REG_FLAG_COUNTER_FEILDS |
   1210                           SOC_REG_FLAG_INIT_ON_READ,
   1211         4,
   1212         soc_HBC_ECC_2B_ERR_CNTr_fields,
   1213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1214         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1215         -1,
   1216         -1,
   1217     },
   1218 #endif /* chips */
   1219 
   1220 #if defined(BCM_88690_B0)
   1221     { /* SOC_REG_INT_HBC_ECC_2B_ERR_CNT_BCM88690_B0r */
   1222         soc_block_list[165],
   1223         soc_genreg,
   1224         1,
   1225         0,
   1226         0x96,
   1227         SOC_REG_FLAG_64_BITS |
   1228                           SOC_REG_FLAG_RO,
   1229         SOC_REG_FLAG_COUNTER_FEILDS |
   1230                           SOC_REG_FLAG_INIT_ON_READ,
   1231         4,
   1232         soc_HBC_ECC_2B_ERR_CNT_BCM88690_B0r_fields,
   1233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1234         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   1235         -1,
   1236         -1,
   1237     },
   1238 #endif /* chips */
   1239 
   1240 #if defined(BCM_88690_A0)
   1241     { /* SOC_REG_INT_HBC_ECC_ERR_1B_MONITOR_MEM_MASKr */
   1242         soc_block_list[165],
   1243         soc_genreg,
   1244         1,
   1245         0,
   1246         0x9a,
   1247         0,
   1248         0,
   1249         11,
   1250         soc_HBC_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
   1251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1252         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   1253         -1,
   1254         -1,
   1255     },
   1256 #endif /* chips */
   1257 
   1258 #if defined(BCM_88690_B0)
   1259     { /* SOC_REG_INT_HBC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r */
   1260         soc_block_list[165],
   1261         soc_genreg,
   1262         1,
   1263         0,
   1264         0x9a,
   1265         0,
   1266         0,
   1267         11,
   1268         soc_HBC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
   1269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1270         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   1271         -1,
   1272         -1,
   1273     },
   1274 #endif /* chips */
   1275 
   1276 #if defined(BCM_88690_A0)
   1277     { /* SOC_REG_INT_HBC_ECC_ERR_2B_MONITOR_MEM_MASKr */
   1278         soc_block_list[165],
   1279         soc_genreg,
   1280         1,
   1281         0,
   1282         0x9c,
   1283         0,
   1284         0,
   1285         11,
   1286         soc_HBC_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
   1287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1288         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   1289         -1,
   1290         -1,
   1291     },
   1292 #endif /* chips */
   1293 
   1294 #if defined(BCM_88690_B0)
   1295     { /* SOC_REG_INT_HBC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r */
   1296         soc_block_list[165],
   1297         soc_genreg,
   1298         1,
   1299         0,
   1300         0x9c,
   1301         0,
   1302         0,
   1303         11,
   1304         soc_HBC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
   1305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1306         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   1307         -1,
   1308         -1,
   1309     },
   1310 #endif /* chips */
   1311 
   1312 #if defined(BCM_88690_A0)
   1313     { /* SOC_REG_INT_HBC_ECC_INTERRUPT_REGISTERr */
   1314         soc_block_list[165],
   1315         soc_genreg,
   1316         1,
   1317         0,
   1318         0x7,
   1319         SOC_REG_FLAG_INTERRUPT |
   1320                           SOC_REG_FLAG_SIGNAL,
   1321         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   1322         3,
   1323         soc_HBC_ECC_INTERRUPT_REGISTERr_fields,
   1324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1325         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1326         -1,
   1327         -1,
   1328     },
   1329 #endif /* chips */
   1330 
   1331 #if defined(BCM_88690_B0)
   1332     { /* SOC_REG_INT_HBC_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
   1333         soc_block_list[165],
   1334         soc_genreg,
   1335         1,
   1336         0,
   1337         0x7,
   1338         SOC_REG_FLAG_INTERRUPT |
   1339                           SOC_REG_FLAG_SIGNAL,
   1340         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   1341         3,
   1342         soc_HBC_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   1343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1344         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1345         -1,
   1346         -1,
   1347     },
   1348 #endif /* chips */
   1349 
   1350 #if defined(BCM_88690_A0)
   1351     { /* SOC_REG_INT_HBC_ECC_INTERRUPT_REGISTER_MASKr */
   1352         soc_block_list[165],
   1353         soc_genreg,
   1354         1,
   1355         0,
   1356         0x17,
   1357         0,
   1358         0,
   1359         3,
   1360         soc_HBC_ECC_INTERRUPT_REGISTER_MASKr_fields,
   1361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1362         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1363         -1,
   1364         -1,
   1365     },
   1366 #endif /* chips */
   1367 
   1368 #if defined(BCM_88690_B0)
   1369     { /* SOC_REG_INT_HBC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
   1370         soc_block_list[165],
   1371         soc_genreg,
   1372         1,
   1373         0,
   1374         0x17,
   1375         0,
   1376         0,
   1377         3,
   1378         soc_HBC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
   1379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1380         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1381         -1,
   1382         -1,
   1383     },
   1384 #endif /* chips */
   1385 
   1386 #if defined(BCM_88690_A0)
   1387     { /* SOC_REG_INT_HBC_ECC_INTERRUPT_REGISTER_TESTr */
   1388         soc_block_list[165],
   1389         soc_genreg,
   1390         1,
   1391         0,
   1392         0x1f,
   1393         0,
   1394         0,
   1395         1,
   1396         soc_HBC_ECC_INTERRUPT_REGISTER_TESTr_fields,
   1397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1398         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1399         -1,
   1400         -1,
   1401     },
   1402 #endif /* chips */
   1403 
   1404 #if defined(BCM_88690_B0)
   1405     { /* SOC_REG_INT_HBC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   1406         soc_block_list[165],
   1407         soc_genreg,
   1408         1,
   1409         0,
   1410         0x1f,
   1411         0,
   1412         0,
   1413         1,
   1414         soc_HBC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   1415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1416         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1417         -1,
   1418         -1,
   1419     },
   1420 #endif /* chips */
   1421 
   1422 #if defined(BCM_88690_A0)
   1423     { /* SOC_REG_INT_HBC_ENABLE_DYNAMIC_MEMORY_ACCESSr */
   1424         soc_block_list[165],
   1425         soc_genreg,
   1426         1,
   1427         0,
   1428         0x84,
   1429         0,
   1430         0,
   1431         1,
   1432         soc_HBC_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
   1433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1434         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1435         -1,
   1436         -1,
   1437     },
   1438 #endif /* chips */
   1439 
   1440 #if defined(BCM_88690_B0)
   1441     { /* SOC_REG_INT_HBC_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r */
   1442         soc_block_list[165],
   1443         soc_genreg,
   1444         1,
   1445         0,
   1446         0x84,
   1447         0,
   1448         0,
   1449         1,
   1450         soc_HBC_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r_fields,
   1451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1452         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1453         -1,
   1454         -1,
   1455     },
   1456 #endif /* chips */
   1457 
   1458 #if defined(BCM_88690_A0)
   1459     { /* SOC_REG_INT_HBC_ERROR_INITIATION_DATAr */
   1460         soc_block_list[165],
   1461         soc_genreg,
   1462         1,
   1463         0,
   1464         0xa3,
   1465         0,
   1466         0,
   1467         1,
   1468         soc_HBC_ERROR_INITIATION_DATAr_fields,
   1469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1470         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1471         -1,
   1472         -1,
   1473     },
   1474 #endif /* chips */
   1475 
   1476 #if defined(BCM_88690_A0)
   1477     { /* SOC_REG_INT_HBC_GTIMER_CONFIGURATIONr */
   1478         soc_block_list[165],
   1479         soc_genreg,
   1480         1,
   1481         0,
   1482         0x89,
   1483         0,
   1484         0,
   1485         3,
   1486         soc_HBC_GTIMER_CONFIGURATIONr_fields,
   1487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1488         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1489         -1,
   1490         -1,
   1491     },
   1492 #endif /* chips */
   1493 
   1494 #if defined(BCM_88690_B0)
   1495     { /* SOC_REG_INT_HBC_GTIMER_CONFIGURATION_BCM88690_B0r */
   1496         soc_block_list[165],
   1497         soc_genreg,
   1498         1,
   1499         0,
   1500         0x89,
   1501         0,
   1502         0,
   1503         3,
   1504         soc_HBC_GTIMER_CONFIGURATION_BCM88690_B0r_fields,
   1505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1506         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1507         -1,
   1508         -1,
   1509     },
   1510 #endif /* chips */
   1511 
   1512 #if defined(BCM_88690_A0)
   1513     { /* SOC_REG_INT_HBC_GTIMER_CYCLEr */
   1514         soc_block_list[165],
   1515         soc_genreg,
   1516         1,
   1517         0,
   1518         0x88,
   1519         0,
   1520         0,
   1521         1,
   1522         soc_HBC_GTIMER_CYCLEr_fields,
   1523         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1524         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1525         -1,
   1526         -1,
   1527     },
   1528 #endif /* chips */
   1529 
   1530 #if defined(BCM_88690_B0)
   1531     { /* SOC_REG_INT_HBC_GTIMER_CYCLE_BCM88690_B0r */
   1532         soc_block_list[165],
   1533         soc_genreg,
   1534         1,
   1535         0,
   1536         0x88,
   1537         0,
   1538         0,
   1539         1,
   1540         soc_HBC_GTIMER_CYCLE_BCM88690_B0r_fields,
   1541         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1542         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1543         -1,
   1544         -1,
   1545     },
   1546 #endif /* chips */
   1547 
   1548 #if defined(BCM_88690_A0)
   1549     { /* SOC_REG_INT_HBC_HBM_COLUMN_ACCESS_TIMINGSr */
   1550         soc_block_list[165],
   1551         soc_genreg,
   1552         1,
   1553         0,
   1554         0x161,
   1555         SOC_REG_FLAG_64_BITS,
   1556         0,
   1557         6,
   1558         soc_HBC_HBM_COLUMN_ACCESS_TIMINGSr_fields,
   1559         SOC_RESET_VAL_DEC(0x83204084, 0x00000002)
   1560         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
   1561         -1,
   1562         -1,
   1563     },
   1564 #endif /* chips */
   1565 
   1566 #if defined(BCM_88690_B0)
   1567     { /* SOC_REG_INT_HBC_HBM_COLUMN_ACCESS_TIMINGS_BCM88690_B0r */
   1568         soc_block_list[165],
   1569         soc_genreg,
   1570         1,
   1571         0,
   1572         0x140,
   1573         SOC_REG_FLAG_64_BITS,
   1574         0,
   1575         6,
   1576         soc_HBC_HBM_COLUMN_ACCESS_TIMINGS_BCM88690_B0r_fields,
   1577         SOC_RESET_VAL_DEC(0x83204084, 0x00000002)
   1578         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
   1579         -1,
   1580         -1,
   1581     },
   1582 #endif /* chips */
   1583 
   1584 #if defined(BCM_88690_A0)
   1585     { /* SOC_REG_INT_HBC_HBM_COMMAND_COUNTERSr */
   1586         soc_block_list[165],
   1587         soc_genreg,
   1588         1,
   1589         0,
   1590         0x19c,
   1591         SOC_REG_FLAG_ABOVE_64_BITS |
   1592                           SOC_REG_FLAG_RO,
   1593         SOC_REG_FLAG_COUNTER_FEILDS,
   1594         7,
   1595         soc_HBC_HBM_COMMAND_COUNTERSr_fields,
   1596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1598         -1,
   1599         -1,
   1600     },
   1601 #endif /* chips */
   1602 
   1603 #if defined(BCM_88690_B0)
   1604     { /* SOC_REG_INT_HBC_HBM_COMMAND_COUNTERS_BCM88690_B0r */
   1605         soc_block_list[165],
   1606         soc_genreg,
   1607         1,
   1608         0,
   1609         0x17b,
   1610         SOC_REG_FLAG_ABOVE_64_BITS |
   1611                           SOC_REG_FLAG_RO,
   1612         SOC_REG_FLAG_COUNTER_FEILDS,
   1613         7,
   1614         soc_HBC_HBM_COMMAND_COUNTERS_BCM88690_B0r_fields,
   1615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1616         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1617         -1,
   1618         -1,
   1619     },
   1620 #endif /* chips */
   1621 
   1622 #if defined(BCM_88690_A0)
   1623     { /* SOC_REG_INT_HBC_HBM_CONFIGr */
   1624         soc_block_list[165],
   1625         soc_genreg,
   1626         1,
   1627         0,
   1628         0x10a,
   1629         0,
   1630         0,
   1631         13,
   1632         soc_HBC_HBM_CONFIGr_fields,
   1633         SOC_RESET_VAL_DEC(0x001301d4, 0x00000000)
   1634         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1635         -1,
   1636         -1,
   1637     },
   1638 #endif /* chips */
   1639 
   1640 #if defined(BCM_88690_B0)
   1641     { /* SOC_REG_INT_HBC_HBM_CONFIG_BCM88690_B0r */
   1642         soc_block_list[165],
   1643         soc_genreg,
   1644         1,
   1645         0,
   1646         0x109,
   1647         0,
   1648         0,
   1649         13,
   1650         soc_HBC_HBM_CONFIG_BCM88690_B0r_fields,
   1651         SOC_RESET_VAL_DEC(0x001301d4, 0x00000000)
   1652         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   1653         -1,
   1654         -1,
   1655     },
   1656 #endif /* chips */
   1657 
   1658 #if defined(BCM_88690_A0)
   1659     { /* SOC_REG_INT_HBC_HBM_CPU_CONTROLr */
   1660         soc_block_list[165],
   1661         soc_genreg,
   1662         1,
   1663         0,
   1664         0x180,
   1665         SOC_REG_FLAG_64_BITS,
   1666         0,
   1667         21,
   1668         soc_HBC_HBM_CPU_CONTROLr_fields,
   1669         SOC_RESET_VAL_DEC(0x0000000c, 0x0ff00c00)
   1670         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
   1671         -1,
   1672         -1,
   1673     },
   1674 #endif /* chips */
   1675 
   1676 #if defined(BCM_88690_B0)
   1677     { /* SOC_REG_INT_HBC_HBM_CPU_CONTROL_BCM88690_B0r */
   1678         soc_block_list[165],
   1679         soc_genreg,
   1680         1,
   1681         0,
   1682         0x15f,
   1683         SOC_REG_FLAG_64_BITS,
   1684         0,
   1685         21,
   1686         soc_HBC_HBM_CPU_CONTROL_BCM88690_B0r_fields,
   1687         SOC_RESET_VAL_DEC(0x0000000c, 0x0ff00c00)
   1688         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
   1689         -1,
   1690         -1,
   1691     },
   1692 #endif /* chips */
   1693 
   1694 #if defined(BCM_88690_A0)
   1695     { /* SOC_REG_INT_HBC_HBM_ECC_ERR_INFOr */
   1696         soc_block_list[165],
   1697         soc_genreg,
   1698         1,
   1699         0,
   1700         0x192,
   1701         SOC_REG_FLAG_ABOVE_64_BITS |
   1702                           SOC_REG_FLAG_RO,
   1703         0,
   1704         7,
   1705         soc_HBC_HBM_ECC_ERR_INFOr_fields,
   1706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1707         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1708         -1,
   1709         -1,
   1710     },
   1711 #endif /* chips */
   1712 
   1713 #if defined(BCM_88690_B0)
   1714     { /* SOC_REG_INT_HBC_HBM_ECC_ERR_INFO_BCM88690_B0r */
   1715         soc_block_list[165],
   1716         soc_genreg,
   1717         1,
   1718         0,
   1719         0x171,
   1720         SOC_REG_FLAG_ABOVE_64_BITS |
   1721                           SOC_REG_FLAG_RO,
   1722         0,
   1723         7,
   1724         soc_HBC_HBM_ECC_ERR_INFO_BCM88690_B0r_fields,
   1725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1726         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1727         -1,
   1728         -1,
   1729     },
   1730 #endif /* chips */
   1731 
   1732 #if defined(BCM_88690_A0)
   1733     { /* SOC_REG_INT_HBC_HBM_ERR_COUNTERSr */
   1734         soc_block_list[165],
   1735         soc_genreg,
   1736         1,
   1737         0,
   1738         0x182,
   1739         SOC_REG_FLAG_ABOVE_64_BITS |
   1740                           SOC_REG_FLAG_RO,
   1741         SOC_REG_FLAG_COUNTER_FEILDS,
   1742         13,
   1743         soc_HBC_HBM_ERR_COUNTERSr_fields,
   1744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1745         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1746         -1,
   1747         -1,
   1748     },
   1749 #endif /* chips */
   1750 
   1751 #if defined(BCM_88690_B0)
   1752     { /* SOC_REG_INT_HBC_HBM_ERR_COUNTERS_BCM88690_B0r */
   1753         soc_block_list[165],
   1754         soc_genreg,
   1755         1,
   1756         0,
   1757         0x161,
   1758         SOC_REG_FLAG_ABOVE_64_BITS |
   1759                           SOC_REG_FLAG_RO,
   1760         SOC_REG_FLAG_COUNTER_FEILDS,
   1761         13,
   1762         soc_HBC_HBM_ERR_COUNTERS_BCM88690_B0r_fields,
   1763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1764         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1765         -1,
   1766         -1,
   1767     },
   1768 #endif /* chips */
   1769 
   1770 #if defined(BCM_88690_A0)
   1771     { /* SOC_REG_INT_HBC_HBM_GENERAL_TIMINGSr */
   1772         soc_block_list[165],
   1773         soc_genreg,
   1774         1,
   1775         0,
   1776         0x164,
   1777         0,
   1778         0,
   1779         2,
   1780         soc_HBC_HBM_GENERAL_TIMINGSr_fields,
   1781         SOC_RESET_VAL_DEC(0x000003c8, 0x00000000)
   1782         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1783         -1,
   1784         -1,
   1785     },
   1786 #endif /* chips */
   1787 
   1788 #if defined(BCM_88690_B0)
   1789     { /* SOC_REG_INT_HBC_HBM_GENERAL_TIMINGS_BCM88690_B0r */
   1790         soc_block_list[165],
   1791         soc_genreg,
   1792         1,
   1793         0,
   1794         0x143,
   1795         0,
   1796         0,
   1797         2,
   1798         soc_HBC_HBM_GENERAL_TIMINGS_BCM88690_B0r_fields,
   1799         SOC_RESET_VAL_DEC(0x000003c8, 0x00000000)
   1800         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1801         -1,
   1802         -1,
   1803     },
   1804 #endif /* chips */
   1805 
   1806 #if defined(BCM_88690_A0)
   1807     { /* SOC_REG_INT_HBC_HBM_MODE_REGISTERSr */
   1808         soc_block_list[165],
   1809         soc_genreg,
   1810         1,
   1811         0,
   1812         0x10b,
   1813         SOC_REG_FLAG_ABOVE_64_BITS,
   1814         0,
   1815         16,
   1816         soc_HBC_HBM_MODE_REGISTERSr_fields,
   1817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1819         -1,
   1820         -1,
   1821     },
   1822 #endif /* chips */
   1823 
   1824 #if defined(BCM_88690_B0)
   1825     { /* SOC_REG_INT_HBC_HBM_MODE_REGISTERS_BCM88690_B0r */
   1826         soc_block_list[165],
   1827         soc_genreg,
   1828         1,
   1829         0,
   1830         0x10a,
   1831         SOC_REG_FLAG_ABOVE_64_BITS,
   1832         0,
   1833         16,
   1834         soc_HBC_HBM_MODE_REGISTERS_BCM88690_B0r_fields,
   1835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1836         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1837         -1,
   1838         -1,
   1839     },
   1840 #endif /* chips */
   1841 
   1842 #if defined(BCM_88690_A0)
   1843     { /* SOC_REG_INT_HBC_HBM_MODE_REGISTER_MANAGER_CONFIGr */
   1844         soc_block_list[165],
   1845         soc_genreg,
   1846         1,
   1847         0,
   1848         0x10f,
   1849         0,
   1850         0,
   1851         2,
   1852         soc_HBC_HBM_MODE_REGISTER_MANAGER_CONFIGr_fields,
   1853         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
   1854         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1855         -1,
   1856         -1,
   1857     },
   1858 #endif /* chips */
   1859 
   1860 #if defined(BCM_88690_B0)
   1861     { /* SOC_REG_INT_HBC_HBM_MODE_REGISTER_MANAGER_CONFIG_BCM88690_B0r */
   1862         soc_block_list[165],
   1863         soc_genreg,
   1864         1,
   1865         0,
   1866         0x10e,
   1867         0,
   1868         0,
   1869         2,
   1870         soc_HBC_HBM_MODE_REGISTER_MANAGER_CONFIG_BCM88690_B0r_fields,
   1871         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
   1872         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1873         -1,
   1874         -1,
   1875     },
   1876 #endif /* chips */
   1877 
   1878 #if defined(BCM_88690_A0)
   1879     { /* SOC_REG_INT_HBC_HBM_PHY_CH_REGISTER_ACCESS_ERRORr */
   1880         soc_block_list[165],
   1881         soc_genreg,
   1882         1,
   1883         0,
   1884         0x235,
   1885         SOC_REG_FLAG_RO,
   1886         SOC_REG_FLAG_INIT_ON_READ,
   1887         1,
   1888         soc_HBC_HBM_PHY_CH_REGISTER_ACCESS_ERRORr_fields,
   1889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1890         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1891         -1,
   1892         -1,
   1893     },
   1894 #endif /* chips */
   1895 
   1896 #if defined(BCM_88690_B0)
   1897     { /* SOC_REG_INT_HBC_HBM_PHY_CH_REGISTER_ACCESS_ERROR_BCM88690_B0r */
   1898         soc_block_list[165],
   1899         soc_genreg,
   1900         1,
   1901         0,
   1902         0x210,
   1903         SOC_REG_FLAG_RO,
   1904         SOC_REG_FLAG_INIT_ON_READ,
   1905         1,
   1906         soc_HBC_HBM_PHY_CH_REGISTER_ACCESS_ERROR_BCM88690_B0r_fields,
   1907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1908         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1909         -1,
   1910         -1,
   1911     },
   1912 #endif /* chips */
   1913 
   1914 #if defined(BCM_88690_A0)
   1915     { /* SOC_REG_INT_HBC_HBM_REFRESH_INTERVALSr */
   1916         soc_block_list[165],
   1917         soc_genreg,
   1918         8,
   1919         0,
   1920         0x165,
   1921         SOC_REG_FLAG_ARRAY |
   1922                           SOC_REG_FLAG_REG_ARRAY,
   1923         0,
   1924         2,
   1925         soc_HBC_HBM_REFRESH_INTERVALSr_fields,
   1926         SOC_RESET_VAL_DEC(0x003d0f3c, 0x00000000)
   1927         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   1928         -1,
   1929         -1,
   1930     },
   1931 #endif /* chips */
   1932 
   1933 #if defined(BCM_88690_B0)
   1934     { /* SOC_REG_INT_HBC_HBM_REFRESH_INTERVALS_BCM88690_B0r */
   1935         soc_block_list[165],
   1936         soc_genreg,
   1937         8,
   1938         0,
   1939         0x144,
   1940         SOC_REG_FLAG_ARRAY |
   1941                           SOC_REG_FLAG_REG_ARRAY,
   1942         0,
   1943         2,
   1944         soc_HBC_HBM_REFRESH_INTERVALS_BCM88690_B0r_fields,
   1945         SOC_RESET_VAL_DEC(0x003d0f3c, 0x00000000)
   1946         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   1947         -1,
   1948         -1,
   1949     },
   1950 #endif /* chips */
   1951 
   1952 #if defined(BCM_88690_A0)
   1953     { /* SOC_REG_INT_HBC_HBM_REFRESH_TIMINGSr */
   1954         soc_block_list[165],
   1955         soc_genreg,
   1956         1,
   1957         0,
   1958         0x163,
   1959         0,
   1960         0,
   1961         3,
   1962         soc_HBC_HBM_REFRESH_TIMINGSr_fields,
   1963         SOC_RESET_VAL_DEC(0x00a28104, 0x00000000)
   1964         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   1965         -1,
   1966         -1,
   1967     },
   1968 #endif /* chips */
   1969 
   1970 #if defined(BCM_88690_B0)
   1971     { /* SOC_REG_INT_HBC_HBM_REFRESH_TIMINGS_BCM88690_B0r */
   1972         soc_block_list[165],
   1973         soc_genreg,
   1974         1,
   1975         0,
   1976         0x142,
   1977         0,
   1978         0,
   1979         3,
   1980         soc_HBC_HBM_REFRESH_TIMINGS_BCM88690_B0r_fields,
   1981         SOC_RESET_VAL_DEC(0x00a28104, 0x00000000)
   1982         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   1983         -1,
   1984         -1,
   1985     },
   1986 #endif /* chips */
   1987 
   1988 #if defined(BCM_88690_A0)
   1989     { /* SOC_REG_INT_HBC_HBM_ROW_ACCESS_TIMINGSr */
   1990         soc_block_list[165],
   1991         soc_genreg,
   1992         1,
   1993         0,
   1994         0x15e,
   1995         SOC_REG_FLAG_ABOVE_64_BITS,
   1996         0,
   1997         11,
   1998         soc_HBC_HBM_ROW_ACCESS_TIMINGSr_fields,
   1999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2000         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2001         -1,
   2002         -1,
   2003     },
   2004 #endif /* chips */
   2005 
   2006 #if defined(BCM_88690_B0)
   2007     { /* SOC_REG_INT_HBC_HBM_ROW_ACCESS_TIMINGS_BCM88690_B0r */
   2008         soc_block_list[165],
   2009         soc_genreg,
   2010         1,
   2011         0,
   2012         0x13d,
   2013         SOC_REG_FLAG_ABOVE_64_BITS,
   2014         0,
   2015         11,
   2016         soc_HBC_HBM_ROW_ACCESS_TIMINGS_BCM88690_B0r_fields,
   2017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2018         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2019         -1,
   2020         -1,
   2021     },
   2022 #endif /* chips */
   2023 
   2024 #if defined(BCM_88690_A0)
   2025     { /* SOC_REG_INT_HBC_INDIRECT_COMMANDr */
   2026         soc_block_list[165],
   2027         soc_genreg,
   2028         1,
   2029         0,
   2030         0x80,
   2031         0,
   2032         0,
   2033         5,
   2034         soc_HBC_INDIRECT_COMMANDr_fields,
   2035         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
   2036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2037         -1,
   2038         -1,
   2039     },
   2040 #endif /* chips */
   2041 
   2042 #if defined(BCM_88690_A0)
   2043     { /* SOC_REG_INT_HBC_INDIRECT_COMMAND_ADDRESSr */
   2044         soc_block_list[165],
   2045         soc_genreg,
   2046         1,
   2047         0,
   2048         0x81,
   2049         0,
   2050         0,
   2051         2,
   2052         soc_HBC_INDIRECT_COMMAND_ADDRESSr_fields,
   2053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2054         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2055         -1,
   2056         -1,
   2057     },
   2058 #endif /* chips */
   2059 
   2060 #if defined(BCM_88690_B0)
   2061     { /* SOC_REG_INT_HBC_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r */
   2062         soc_block_list[165],
   2063         soc_genreg,
   2064         1,
   2065         0,
   2066         0x81,
   2067         0,
   2068         0,
   2069         2,
   2070         soc_HBC_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r_fields,
   2071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2072         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2073         -1,
   2074         -1,
   2075     },
   2076 #endif /* chips */
   2077 
   2078 #if defined(BCM_88690_B0)
   2079     { /* SOC_REG_INT_HBC_INDIRECT_COMMAND_BCM88690_B0r */
   2080         soc_block_list[165],
   2081         soc_genreg,
   2082         1,
   2083         0,
   2084         0x80,
   2085         0,
   2086         0,
   2087         5,
   2088         soc_HBC_INDIRECT_COMMAND_BCM88690_B0r_fields,
   2089         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
   2090         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2091         -1,
   2092         -1,
   2093     },
   2094 #endif /* chips */
   2095 
   2096 #if defined(BCM_88690_A0)
   2097     { /* SOC_REG_INT_HBC_INDIRECT_COMMAND_RD_DATAr */
   2098         soc_block_list[165],
   2099         soc_genreg,
   2100         1,
   2101         0,
   2102         0x60,
   2103         SOC_REG_FLAG_ABOVE_64_BITS |
   2104                           SOC_REG_FLAG_RO |
   2105                           SOC_REG_FLAG_SIGNAL,
   2106         0,
   2107         1,
   2108         soc_HBC_INDIRECT_COMMAND_RD_DATAr_fields,
   2109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2110         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2111         -1,
   2112         -1,
   2113     },
   2114 #endif /* chips */
   2115 
   2116 #if defined(BCM_88690_B0)
   2117     { /* SOC_REG_INT_HBC_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r */
   2118         soc_block_list[165],
   2119         soc_genreg,
   2120         1,
   2121         0,
   2122         0x60,
   2123         SOC_REG_FLAG_ABOVE_64_BITS |
   2124                           SOC_REG_FLAG_RO |
   2125                           SOC_REG_FLAG_SIGNAL,
   2126         0,
   2127         1,
   2128         soc_HBC_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r_fields,
   2129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2130         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2131         -1,
   2132         -1,
   2133     },
   2134 #endif /* chips */
   2135 
   2136 #if defined(BCM_88690_A0)
   2137     { /* SOC_REG_INT_HBC_INDIRECT_COMMAND_WR_DATAr */
   2138         soc_block_list[165],
   2139         soc_genreg,
   2140         1,
   2141         0,
   2142         0x20,
   2143         SOC_REG_FLAG_ABOVE_64_BITS,
   2144         0,
   2145         1,
   2146         soc_HBC_INDIRECT_COMMAND_WR_DATAr_fields,
   2147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2148         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2149         -1,
   2150         -1,
   2151     },
   2152 #endif /* chips */
   2153 
   2154 #if defined(BCM_88690_B0)
   2155     { /* SOC_REG_INT_HBC_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r */
   2156         soc_block_list[165],
   2157         soc_genreg,
   2158         1,
   2159         0,
   2160         0x20,
   2161         SOC_REG_FLAG_ABOVE_64_BITS,
   2162         0,
   2163         1,
   2164         soc_HBC_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r_fields,
   2165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2166         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2167         -1,
   2168         -1,
   2169     },
   2170 #endif /* chips */
   2171 
   2172 #if defined(BCM_88690_A0)
   2173     { /* SOC_REG_INT_HBC_INDIRECT_FORCE_BUBBLEr */
   2174         soc_block_list[165],
   2175         soc_genreg,
   2176         1,
   2177         0,
   2178         0x83,
   2179         0,
   2180         0,
   2181         4,
   2182         soc_HBC_INDIRECT_FORCE_BUBBLEr_fields,
   2183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2184         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   2185         -1,
   2186         -1,
   2187     },
   2188 #endif /* chips */
   2189 
   2190 #if defined(BCM_88690_B0)
   2191     { /* SOC_REG_INT_HBC_INDIRECT_FORCE_BUBBLE_BCM88690_B0r */
   2192         soc_block_list[165],
   2193         soc_genreg,
   2194         1,
   2195         0,
   2196         0x83,
   2197         0,
   2198         0,
   2199         4,
   2200         soc_HBC_INDIRECT_FORCE_BUBBLE_BCM88690_B0r_fields,
   2201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2202         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   2203         -1,
   2204         -1,
   2205     },
   2206 #endif /* chips */
   2207 
   2208 #if defined(BCM_88690_A0)
   2209     { /* SOC_REG_INT_HBC_INTERRUPT_MASK_REGISTERr */
   2210         soc_block_list[165],
   2211         soc_genreg,
   2212         1,
   2213         0,
   2214         0x10,
   2215         0,
   2216         0,
   2217         6,
   2218         soc_HBC_INTERRUPT_MASK_REGISTERr_fields,
   2219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2220         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2221         -1,
   2222         -1,
   2223     },
   2224 #endif /* chips */
   2225 
   2226 #if defined(BCM_88690_B0)
   2227     { /* SOC_REG_INT_HBC_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
   2228         soc_block_list[165],
   2229         soc_genreg,
   2230         1,
   2231         0,
   2232         0x10,
   2233         0,
   2234         0,
   2235         6,
   2236         soc_HBC_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
   2237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2238         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2239         -1,
   2240         -1,
   2241     },
   2242 #endif /* chips */
   2243 
   2244 #if defined(BCM_88690_A0)
   2245     { /* SOC_REG_INT_HBC_INTERRUPT_REGISTERr */
   2246         soc_block_list[165],
   2247         soc_genreg,
   2248         1,
   2249         0,
   2250         0,
   2251         SOC_REG_FLAG_INTERRUPT |
   2252                           SOC_REG_FLAG_SIGNAL,
   2253         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   2254         6,
   2255         soc_HBC_INTERRUPT_REGISTERr_fields,
   2256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2257         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2258         -1,
   2259         -1,
   2260     },
   2261 #endif /* chips */
   2262 
   2263 #if defined(BCM_88690_B0)
   2264     { /* SOC_REG_INT_HBC_INTERRUPT_REGISTER_BCM88690_B0r */
   2265         soc_block_list[165],
   2266         soc_genreg,
   2267         1,
   2268         0,
   2269         0,
   2270         SOC_REG_FLAG_INTERRUPT |
   2271                           SOC_REG_FLAG_SIGNAL,
   2272         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   2273         6,
   2274         soc_HBC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   2275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2276         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2277         -1,
   2278         -1,
   2279     },
   2280 #endif /* chips */
   2281 
   2282 #if defined(BCM_88690_A0)
   2283     { /* SOC_REG_INT_HBC_INTERRUPT_REGISTER_TESTr */
   2284         soc_block_list[165],
   2285         soc_genreg,
   2286         1,
   2287         0,
   2288         0x18,
   2289         0,
   2290         0,
   2291         1,
   2292         soc_HBC_INTERRUPT_REGISTER_TESTr_fields,
   2293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2294         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2295         -1,
   2296         -1,
   2297     },
   2298 #endif /* chips */
   2299 
   2300 #if defined(BCM_88690_B0)
   2301     { /* SOC_REG_INT_HBC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   2302         soc_block_list[165],
   2303         soc_genreg,
   2304         1,
   2305         0,
   2306         0x18,
   2307         0,
   2308         0,
   2309         1,
   2310         soc_HBC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   2311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2312         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2313         -1,
   2314         -1,
   2315     },
   2316 #endif /* chips */
   2317 
   2318 #if defined(BCM_88690_A0)
   2319     { /* SOC_REG_INT_HBC_LAST_RETURNED_DATAr */
   2320         soc_block_list[165],
   2321         soc_genreg,
   2322         4,
   2323         0,
   2324         0x1a5,
   2325         SOC_REG_FLAG_ABOVE_64_BITS |
   2326                           SOC_REG_FLAG_ARRAY |
   2327                           SOC_REG_FLAG_RO |
   2328                           SOC_REG_FLAG_REG_ARRAY,
   2329         0,
   2330         4,
   2331         soc_HBC_LAST_RETURNED_DATAr_fields,
   2332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2334         -1,
   2335         -1,
   2336     },
   2337 #endif /* chips */
   2338 
   2339 #if defined(BCM_88690_B0)
   2340     { /* SOC_REG_INT_HBC_LAST_RETURNED_DATA_BCM88690_B0r */
   2341         soc_block_list[165],
   2342         soc_genreg,
   2343         4,
   2344         0,
   2345         0x184,
   2346         SOC_REG_FLAG_ABOVE_64_BITS |
   2347                           SOC_REG_FLAG_ARRAY |
   2348                           SOC_REG_FLAG_RO |
   2349                           SOC_REG_FLAG_REG_ARRAY,
   2350         0,
   2351         4,
   2352         soc_HBC_LAST_RETURNED_DATA_BCM88690_B0r_fields,
   2353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2354         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2355         -1,
   2356         -1,
   2357     },
   2358 #endif /* chips */
   2359 
   2360 #if defined(BCM_88690_A0)
   2361     { /* SOC_REG_INT_HBC_PARITY_ERR_CNTr */
   2362         soc_block_list[165],
   2363         soc_genreg,
   2364         1,
   2365         0,
   2366         0x98,
   2367         SOC_REG_FLAG_64_BITS |
   2368                           SOC_REG_FLAG_RO,
   2369         SOC_REG_FLAG_COUNTER_FEILDS |
   2370                           SOC_REG_FLAG_INIT_ON_READ,
   2371         4,
   2372         soc_HBC_PARITY_ERR_CNTr_fields,
   2373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2374         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2375         -1,
   2376         -1,
   2377     },
   2378 #endif /* chips */
   2379 
   2380 #if defined(BCM_88690_B0)
   2381     { /* SOC_REG_INT_HBC_PARITY_ERR_CNT_BCM88690_B0r */
   2382         soc_block_list[165],
   2383         soc_genreg,
   2384         1,
   2385         0,
   2386         0x98,
   2387         SOC_REG_FLAG_64_BITS |
   2388                           SOC_REG_FLAG_RO,
   2389         SOC_REG_FLAG_COUNTER_FEILDS |
   2390                           SOC_REG_FLAG_INIT_ON_READ,
   2391         4,
   2392         soc_HBC_PARITY_ERR_CNT_BCM88690_B0r_fields,
   2393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2394         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2395         -1,
   2396         -1,
   2397     },
   2398 #endif /* chips */
   2399 
   2400 #if defined(BCM_88690_A0)
   2401     { /* SOC_REG_INT_HBC_PAR_ERR_MEM_MASKr */
   2402         soc_block_list[165],
   2403         soc_genreg,
   2404         1,
   2405         0,
   2406         0xa0,
   2407         0,
   2408         0,
   2409         22,
   2410         soc_HBC_PAR_ERR_MEM_MASKr_fields,
   2411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2412         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
   2413         -1,
   2414         -1,
   2415     },
   2416 #endif /* chips */
   2417 
   2418 #if defined(BCM_88690_B0)
   2419     { /* SOC_REG_INT_HBC_PAR_ERR_MEM_MASK_BCM88690_B0r */
   2420         soc_block_list[165],
   2421         soc_genreg,
   2422         1,
   2423         0,
   2424         0xa0,
   2425         0,
   2426         0,
   2427         20,
   2428         soc_HBC_PAR_ERR_MEM_MASK_BCM88690_B0r_fields,
   2429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2430         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   2431         -1,
   2432         -1,
   2433     },
   2434 #endif /* chips */
   2435 
   2436 #if defined(BCM_88690_A0)
   2437     { /* SOC_REG_INT_HBC_PIPELINES_BANK_REMAPPINGr */
   2438         soc_block_list[165],
   2439         soc_genreg,
   2440         1,
   2441         0,
   2442         0x17e,
   2443         0,
   2444         0,
   2445         5,
   2446         soc_HBC_PIPELINES_BANK_REMAPPINGr_fields,
   2447         SOC_RESET_VAL_DEC(0x00004688, 0x00000000)
   2448         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   2449         -1,
   2450         -1,
   2451     },
   2452 #endif /* chips */
   2453 
   2454 #if defined(BCM_88690_B0)
   2455     { /* SOC_REG_INT_HBC_PIPELINES_BANK_REMAPPING_BCM88690_B0r */
   2456         soc_block_list[165],
   2457         soc_genreg,
   2458         1,
   2459         0,
   2460         0x15d,
   2461         0,
   2462         0,
   2463         5,
   2464         soc_HBC_PIPELINES_BANK_REMAPPING_BCM88690_B0r_fields,
   2465         SOC_RESET_VAL_DEC(0x00004688, 0x00000000)
   2466         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   2467         -1,
   2468         -1,
   2469     },
   2470 #endif /* chips */
   2471 
   2472 #if defined(BCM_88690_A0)
   2473     { /* SOC_REG_INT_HBC_PIPELINES_COMMAND_PIN_MUXr */
   2474         soc_block_list[165],
   2475         soc_genreg,
   2476         1,
   2477         0,
   2478         0x17c,
   2479         SOC_REG_FLAG_64_BITS,
   2480         0,
   2481         14,
   2482         soc_HBC_PIPELINES_COMMAND_PIN_MUXr_fields,
   2483         SOC_RESET_VAL_DEC(0x76543210, 0x00dcba98)
   2484         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
   2485         -1,
   2486         -1,
   2487     },
   2488 #endif /* chips */
   2489 
   2490 #if defined(BCM_88690_B0)
   2491     { /* SOC_REG_INT_HBC_PIPELINES_COMMAND_PIN_MUX_BCM88690_B0r */
   2492         soc_block_list[165],
   2493         soc_genreg,
   2494         1,
   2495         0,
   2496         0x15b,
   2497         SOC_REG_FLAG_64_BITS,
   2498         0,
   2499         14,
   2500         soc_HBC_PIPELINES_COMMAND_PIN_MUX_BCM88690_B0r_fields,
   2501         SOC_RESET_VAL_DEC(0x76543210, 0x00dcba98)
   2502         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
   2503         -1,
   2504         -1,
   2505     },
   2506 #endif /* chips */
   2507 
   2508 #if defined(BCM_88690_A0)
   2509     { /* SOC_REG_INT_HBC_PIPELINES_CONFIGr */
   2510         soc_block_list[165],
   2511         soc_genreg,
   2512         1,
   2513         0,
   2514         0x17b,
   2515         0,
   2516         0,
   2517         12,
   2518         soc_HBC_PIPELINES_CONFIGr_fields,
   2519         SOC_RESET_VAL_DEC(0x000508cc, 0x00000000)
   2520         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   2521         -1,
   2522         -1,
   2523     },
   2524 #endif /* chips */
   2525 
   2526 #if defined(BCM_88690_B0)
   2527     { /* SOC_REG_INT_HBC_PIPELINES_CONFIG_BCM88690_B0r */
   2528         soc_block_list[165],
   2529         soc_genreg,
   2530         1,
   2531         0,
   2532         0x15a,
   2533         0,
   2534         0,
   2535         12,
   2536         soc_HBC_PIPELINES_CONFIG_BCM88690_B0r_fields,
   2537         SOC_RESET_VAL_DEC(0x000508cc, 0x00000000)
   2538         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   2539         -1,
   2540         -1,
   2541     },
   2542 #endif /* chips */
   2543 
   2544 #if defined(BCM_88690_A0)
   2545     { /* SOC_REG_INT_HBC_PIPELINES_DEBUGr */
   2546         soc_block_list[165],
   2547         soc_genreg,
   2548         1,
   2549         0,
   2550         0x1b9,
   2551         SOC_REG_FLAG_RO,
   2552         SOC_REG_FLAG_INIT_ON_READ,
   2553         8,
   2554         soc_HBC_PIPELINES_DEBUGr_fields,
   2555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2556         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2557         -1,
   2558         -1,
   2559     },
   2560 #endif /* chips */
   2561 
   2562 #if defined(BCM_88690_B0)
   2563     { /* SOC_REG_INT_HBC_PIPELINES_DEBUG_BCM88690_B0r */
   2564         soc_block_list[165],
   2565         soc_genreg,
   2566         1,
   2567         0,
   2568         0x198,
   2569         SOC_REG_FLAG_RO,
   2570         SOC_REG_FLAG_INIT_ON_READ,
   2571         8,
   2572         soc_HBC_PIPELINES_DEBUG_BCM88690_B0r_fields,
   2573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2574         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2575         -1,
   2576         -1,
   2577     },
   2578 #endif /* chips */
   2579 
   2580 #if defined(BCM_88690_A0)
   2581     { /* SOC_REG_INT_HBC_PIPELINES_INTERRUPT_MASK_REGISTERr */
   2582         soc_block_list[165],
   2583         soc_genreg,
   2584         1,
   2585         0,
   2586         0x108,
   2587         0,
   2588         0,
   2589         14,
   2590         soc_HBC_PIPELINES_INTERRUPT_MASK_REGISTERr_fields,
   2591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2592         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   2593         -1,
   2594         -1,
   2595     },
   2596 #endif /* chips */
   2597 
   2598 #if defined(BCM_88690_B0)
   2599     { /* SOC_REG_INT_HBC_PIPELINES_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
   2600         soc_block_list[165],
   2601         soc_genreg,
   2602         1,
   2603         0,
   2604         0x107,
   2605         0,
   2606         0,
   2607         14,
   2608         soc_HBC_PIPELINES_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
   2609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2610         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   2611         -1,
   2612         -1,
   2613     },
   2614 #endif /* chips */
   2615 
   2616 #if defined(BCM_88690_A0)
   2617     { /* SOC_REG_INT_HBC_PIPELINES_INTERRUPT_REGISTERr */
   2618         soc_block_list[165],
   2619         soc_genreg,
   2620         1,
   2621         0,
   2622         0x107,
   2623         SOC_REG_FLAG_INTERRUPT |
   2624                           SOC_REG_FLAG_SIGNAL,
   2625         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   2626         14,
   2627         soc_HBC_PIPELINES_INTERRUPT_REGISTERr_fields,
   2628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2629         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   2630         -1,
   2631         -1,
   2632     },
   2633 #endif /* chips */
   2634 
   2635 #if defined(BCM_88690_B0)
   2636     { /* SOC_REG_INT_HBC_PIPELINES_INTERRUPT_REGISTER_BCM88690_B0r */
   2637         soc_block_list[165],
   2638         soc_genreg,
   2639         1,
   2640         0,
   2641         0x106,
   2642         SOC_REG_FLAG_INTERRUPT |
   2643                           SOC_REG_FLAG_SIGNAL,
   2644         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   2645         14,
   2646         soc_HBC_PIPELINES_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   2647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2648         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   2649         -1,
   2650         -1,
   2651     },
   2652 #endif /* chips */
   2653 
   2654 #if defined(BCM_88690_A0)
   2655     { /* SOC_REG_INT_HBC_PIPELINES_INTERRUPT_REGISTER_TESTr */
   2656         soc_block_list[165],
   2657         soc_genreg,
   2658         1,
   2659         0,
   2660         0x109,
   2661         0,
   2662         0,
   2663         1,
   2664         soc_HBC_PIPELINES_INTERRUPT_REGISTER_TESTr_fields,
   2665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2666         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   2667         -1,
   2668         -1,
   2669     },
   2670 #endif /* chips */
   2671 
   2672 #if defined(BCM_88690_B0)
   2673     { /* SOC_REG_INT_HBC_PIPELINES_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   2674         soc_block_list[165],
   2675         soc_genreg,
   2676         1,
   2677         0,
   2678         0x108,
   2679         0,
   2680         0,
   2681         1,
   2682         soc_HBC_PIPELINES_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   2683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2684         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   2685         -1,
   2686         -1,
   2687     },
   2688 #endif /* chips */
   2689 
   2690 #if defined(BCM_88690_A0)
   2691     { /* SOC_REG_INT_HBC_PIPELINES_PHY_RCMDr */
   2692         soc_block_list[165],
   2693         soc_genreg,
   2694         1,
   2695         0,
   2696         0x17f,
   2697         0,
   2698         0,
   2699         4,
   2700         soc_HBC_PIPELINES_PHY_RCMDr_fields,
   2701         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   2702         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2703         -1,
   2704         -1,
   2705     },
   2706 #endif /* chips */
   2707 
   2708 #if defined(BCM_88690_B0)
   2709     { /* SOC_REG_INT_HBC_PIPELINES_PHY_RCMD_BCM88690_B0r */
   2710         soc_block_list[165],
   2711         soc_genreg,
   2712         1,
   2713         0,
   2714         0x15e,
   2715         0,
   2716         0,
   2717         4,
   2718         soc_HBC_PIPELINES_PHY_RCMD_BCM88690_B0r_fields,
   2719         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
   2720         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2721         -1,
   2722         -1,
   2723     },
   2724 #endif /* chips */
   2725 
   2726 #if defined(BCM_88690_A0)
   2727     { /* SOC_REG_INT_HBC_RDR_DS_TRANS_CNTr */
   2728         soc_block_list[165],
   2729         soc_genreg,
   2730         2,
   2731         0,
   2732         0x15b,
   2733         SOC_REG_FLAG_ARRAY |
   2734                           SOC_REG_FLAG_RO |
   2735                           SOC_REG_FLAG_REG_ARRAY,
   2736         SOC_REG_FLAG_COUNTER_FEILDS,
   2737         1,
   2738         soc_HBC_RDR_DS_TRANS_CNTr_fields,
   2739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2741         -1,
   2742         -1,
   2743     },
   2744 #endif /* chips */
   2745 
   2746 #if defined(BCM_88690_B0)
   2747     { /* SOC_REG_INT_HBC_RDR_DS_TRANS_CNT_BCM88690_B0r */
   2748         soc_block_list[165],
   2749         soc_genreg,
   2750         2,
   2751         0,
   2752         0x13a,
   2753         SOC_REG_FLAG_ARRAY |
   2754                           SOC_REG_FLAG_RO |
   2755                           SOC_REG_FLAG_REG_ARRAY,
   2756         SOC_REG_FLAG_COUNTER_FEILDS,
   2757         1,
   2758         soc_HBC_RDR_DS_TRANS_CNT_BCM88690_B0r_fields,
   2759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2760         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2761         -1,
   2762         -1,
   2763     },
   2764 #endif /* chips */
   2765 
   2766 #if defined(BCM_88690_A0)
   2767     { /* SOC_REG_INT_HBC_RDR_INTERRUPT_MASK_REGISTERr */
   2768         soc_block_list[165],
   2769         soc_genreg,
   2770         1,
   2771         0,
   2772         0x105,
   2773         0,
   2774         0,
   2775         2,
   2776         soc_HBC_RDR_INTERRUPT_MASK_REGISTERr_fields,
   2777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2778         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2779         -1,
   2780         -1,
   2781     },
   2782 #endif /* chips */
   2783 
   2784 #if defined(BCM_88690_B0)
   2785     { /* SOC_REG_INT_HBC_RDR_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
   2786         soc_block_list[165],
   2787         soc_genreg,
   2788         1,
   2789         0,
   2790         0x104,
   2791         0,
   2792         0,
   2793         2,
   2794         soc_HBC_RDR_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
   2795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2796         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2797         -1,
   2798         -1,
   2799     },
   2800 #endif /* chips */
   2801 
   2802 #if defined(BCM_88690_A0)
   2803     { /* SOC_REG_INT_HBC_RDR_INTERRUPT_REGISTERr */
   2804         soc_block_list[165],
   2805         soc_genreg,
   2806         1,
   2807         0,
   2808         0x104,
   2809         SOC_REG_FLAG_INTERRUPT |
   2810                           SOC_REG_FLAG_SIGNAL,
   2811         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   2812         2,
   2813         soc_HBC_RDR_INTERRUPT_REGISTERr_fields,
   2814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2815         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2816         -1,
   2817         -1,
   2818     },
   2819 #endif /* chips */
   2820 
   2821 #if defined(BCM_88690_B0)
   2822     { /* SOC_REG_INT_HBC_RDR_INTERRUPT_REGISTER_BCM88690_B0r */
   2823         soc_block_list[165],
   2824         soc_genreg,
   2825         1,
   2826         0,
   2827         0x103,
   2828         SOC_REG_FLAG_INTERRUPT |
   2829                           SOC_REG_FLAG_SIGNAL,
   2830         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   2831         2,
   2832         soc_HBC_RDR_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   2833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2834         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2835         -1,
   2836         -1,
   2837     },
   2838 #endif /* chips */
   2839 
   2840 #if defined(BCM_88690_A0)
   2841     { /* SOC_REG_INT_HBC_RDR_INTERRUPT_REGISTER_TESTr */
   2842         soc_block_list[165],
   2843         soc_genreg,
   2844         1,
   2845         0,
   2846         0x106,
   2847         0,
   2848         0,
   2849         1,
   2850         soc_HBC_RDR_INTERRUPT_REGISTER_TESTr_fields,
   2851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2852         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2853         -1,
   2854         -1,
   2855     },
   2856 #endif /* chips */
   2857 
   2858 #if defined(BCM_88690_B0)
   2859     { /* SOC_REG_INT_HBC_RDR_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   2860         soc_block_list[165],
   2861         soc_genreg,
   2862         1,
   2863         0,
   2864         0x105,
   2865         0,
   2866         0,
   2867         1,
   2868         soc_HBC_RDR_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   2869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2870         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2871         -1,
   2872         -1,
   2873     },
   2874 #endif /* chips */
   2875 
   2876 #if defined(BCM_88690_A0)
   2877     { /* SOC_REG_INT_HBC_RDR_RD_INFO_WMKr */
   2878         soc_block_list[165],
   2879         soc_genreg,
   2880         1,
   2881         0,
   2882         0x15d,
   2883         SOC_REG_FLAG_RO,
   2884         SOC_REG_FLAG_INIT_ON_READ,
   2885         1,
   2886         soc_HBC_RDR_RD_INFO_WMKr_fields,
   2887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2888         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2889         -1,
   2890         -1,
   2891     },
   2892 #endif /* chips */
   2893 
   2894 #if defined(BCM_88690_B0)
   2895     { /* SOC_REG_INT_HBC_RDR_RD_INFO_WMK_BCM88690_B0r */
   2896         soc_block_list[165],
   2897         soc_genreg,
   2898         1,
   2899         0,
   2900         0x13c,
   2901         SOC_REG_FLAG_RO,
   2902         SOC_REG_FLAG_INIT_ON_READ,
   2903         1,
   2904         soc_HBC_RDR_RD_INFO_WMK_BCM88690_B0r_fields,
   2905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2906         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2907         -1,
   2908         -1,
   2909     },
   2910 #endif /* chips */
   2911 
   2912 #if defined(BCM_88690_A0)
   2913     { /* SOC_REG_INT_HBC_RDR_TOT_TRANS_CNTr */
   2914         soc_block_list[165],
   2915         soc_genreg,
   2916         1,
   2917         0,
   2918         0x15a,
   2919         SOC_REG_FLAG_RO,
   2920         SOC_REG_FLAG_COUNTER_FEILDS,
   2921         1,
   2922         soc_HBC_RDR_TOT_TRANS_CNTr_fields,
   2923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2925         -1,
   2926         -1,
   2927     },
   2928 #endif /* chips */
   2929 
   2930 #if defined(BCM_88690_B0)
   2931     { /* SOC_REG_INT_HBC_RDR_TOT_TRANS_CNT_BCM88690_B0r */
   2932         soc_block_list[165],
   2933         soc_genreg,
   2934         1,
   2935         0,
   2936         0x139,
   2937         SOC_REG_FLAG_RO,
   2938         SOC_REG_FLAG_COUNTER_FEILDS,
   2939         1,
   2940         soc_HBC_RDR_TOT_TRANS_CNT_BCM88690_B0r_fields,
   2941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2943         -1,
   2944         -1,
   2945     },
   2946 #endif /* chips */
   2947 
   2948 #if defined(BCM_88690_A0)
   2949     { /* SOC_REG_INT_HBC_READ_DATA_REORDER_STATUSr */
   2950         soc_block_list[165],
   2951         soc_genreg,
   2952         2,
   2953         0,
   2954         0x114,
   2955         SOC_REG_FLAG_ABOVE_64_BITS |
   2956                           SOC_REG_FLAG_ARRAY |
   2957                           SOC_REG_FLAG_RO |
   2958                           SOC_REG_FLAG_REG_ARRAY,
   2959         0,
   2960         2,
   2961         soc_HBC_READ_DATA_REORDER_STATUSr_fields,
   2962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2963         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2964         -1,
   2965         -1,
   2966     },
   2967 #endif /* chips */
   2968 
   2969 #if defined(BCM_88690_B0)
   2970     { /* SOC_REG_INT_HBC_READ_DATA_REORDER_STATUS_BCM88690_B0r */
   2971         soc_block_list[165],
   2972         soc_genreg,
   2973         2,
   2974         0,
   2975         0x113,
   2976         SOC_REG_FLAG_ABOVE_64_BITS |
   2977                           SOC_REG_FLAG_ARRAY |
   2978                           SOC_REG_FLAG_RO |
   2979                           SOC_REG_FLAG_REG_ARRAY,
   2980         0,
   2981         2,
   2982         soc_HBC_READ_DATA_REORDER_STATUS_BCM88690_B0r_fields,
   2983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2984         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2985         -1,
   2986         -1,
   2987     },
   2988 #endif /* chips */
   2989 
   2990 #if defined(BCM_88690_A0)
   2991     { /* SOC_REG_INT_HBC_REG_0041r */
   2992         soc_block_list[165],
   2993         soc_genreg,
   2994         1,
   2995         0,
   2996         0x41,
   2997         0,
   2998         0,
   2999         1,
   3000         soc_HBC_REG_0041r_fields,
   3001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3002         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3003         -1,
   3004         -1,
   3005     },
   3006 #endif /* chips */
   3007 
   3008 #if defined(BCM_88690_B0)
   3009     { /* SOC_REG_INT_HBC_REG_0041_BCM88690_B0r */
   3010         soc_block_list[165],
   3011         soc_genreg,
   3012         1,
   3013         0,
   3014         0x41,
   3015         0,
   3016         0,
   3017         1,
   3018         soc_HBC_REG_0041_BCM88690_B0r_fields,
   3019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3020         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3021         -1,
   3022         -1,
   3023     },
   3024 #endif /* chips */
   3025 
   3026 #if defined(BCM_88690_A0)
   3027     { /* SOC_REG_INT_HBC_REG_00A4r */
   3028         soc_block_list[165],
   3029         soc_genreg,
   3030         1,
   3031         0,
   3032         0xa4,
   3033         0,
   3034         0,
   3035         11,
   3036         soc_HBC_REG_00A4r_fields,
   3037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3038         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   3039         -1,
   3040         -1,
   3041     },
   3042 #endif /* chips */
   3043 
   3044 #if defined(BCM_88690_A0)
   3045     { /* SOC_REG_INT_HBC_REG_00A6r */
   3046         soc_block_list[165],
   3047         soc_genreg,
   3048         1,
   3049         0,
   3050         0xa6,
   3051         0,
   3052         0,
   3053         11,
   3054         soc_HBC_REG_00A6r_fields,
   3055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3056         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   3057         -1,
   3058         -1,
   3059     },
   3060 #endif /* chips */
   3061 
   3062 #if defined(BCM_88690_A0)
   3063     { /* SOC_REG_INT_HBC_REG_00AAr */
   3064         soc_block_list[165],
   3065         soc_genreg,
   3066         1,
   3067         0,
   3068         0xaa,
   3069         0,
   3070         0,
   3071         22,
   3072         soc_HBC_REG_00AAr_fields,
   3073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3074         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
   3075         -1,
   3076         -1,
   3077     },
   3078 #endif /* chips */
   3079 
   3080 #if defined(BCM_88690_A0)
   3081     { /* SOC_REG_INT_HBC_REG_00C2r */
   3082         soc_block_list[165],
   3083         soc_genreg,
   3084         1,
   3085         0,
   3086         0xc2,
   3087         0,
   3088         0,
   3089         6,
   3090         soc_HBC_REG_00C2r_fields,
   3091         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   3092         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3093         -1,
   3094         -1,
   3095     },
   3096 #endif /* chips */
   3097 
   3098 #if defined(BCM_88690_B0)
   3099     { /* SOC_REG_INT_HBC_REG_00C2_BCM88690_B0r */
   3100         soc_block_list[165],
   3101         soc_genreg,
   3102         1,
   3103         0,
   3104         0xc2,
   3105         0,
   3106         0,
   3107         6,
   3108         soc_HBC_REG_00C2_BCM88690_B0r_fields,
   3109         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   3110         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3111         -1,
   3112         -1,
   3113     },
   3114 #endif /* chips */
   3115 
   3116 #if defined(BCM_88690_A0)
   3117     { /* SOC_REG_INT_HBC_RESERVED_MIRROR_ADDRr */
   3118         soc_block_list[165],
   3119         soc_genreg,
   3120         1,
   3121         0,
   3122         0x85,
   3123         0,
   3124         0,
   3125         2,
   3126         soc_HBC_RESERVED_MIRROR_ADDRr_fields,
   3127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3128         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   3129         -1,
   3130         -1,
   3131     },
   3132 #endif /* chips */
   3133 
   3134 #if defined(BCM_88690_B0)
   3135     { /* SOC_REG_INT_HBC_RESERVED_MIRROR_ADDR_BCM88690_B0r */
   3136         soc_block_list[165],
   3137         soc_genreg,
   3138         1,
   3139         0,
   3140         0x85,
   3141         0,
   3142         0,
   3143         2,
   3144         soc_HBC_RESERVED_MIRROR_ADDR_BCM88690_B0r_fields,
   3145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3146         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   3147         -1,
   3148         -1,
   3149     },
   3150 #endif /* chips */
   3151 
   3152 #if defined(BCM_88690_A0)
   3153     { /* SOC_REG_INT_HBC_RESERVED_MTCDr */
   3154         soc_block_list[165],
   3155         soc_genreg,
   3156         1,
   3157         0,
   3158         0xae,
   3159         0,
   3160         0,
   3161         6,
   3162         soc_HBC_RESERVED_MTCDr_fields,
   3163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3164         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3165         -1,
   3166         -1,
   3167     },
   3168 #endif /* chips */
   3169 
   3170 #if defined(BCM_88690_B0)
   3171     { /* SOC_REG_INT_HBC_RESERVED_MTCD_BCM88690_B0r */
   3172         soc_block_list[165],
   3173         soc_genreg,
   3174         1,
   3175         0,
   3176         0xae,
   3177         0,
   3178         0,
   3179         6,
   3180         soc_HBC_RESERVED_MTCD_BCM88690_B0r_fields,
   3181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3182         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3183         -1,
   3184         -1,
   3185     },
   3186 #endif /* chips */
   3187 
   3188 #if defined(BCM_88690_A0)
   3189     { /* SOC_REG_INT_HBC_RESERVED_MTCPr */
   3190         soc_block_list[165],
   3191         soc_genreg,
   3192         1,
   3193         0,
   3194         0xad,
   3195         SOC_REG_FLAG_64_BITS,
   3196         0,
   3197         17,
   3198         soc_HBC_RESERVED_MTCPr_fields,
   3199         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   3200         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   3201         -1,
   3202         -1,
   3203     },
   3204 #endif /* chips */
   3205 
   3206 #if defined(BCM_88690_B0)
   3207     { /* SOC_REG_INT_HBC_RESERVED_MTCP_BCM88690_B0r */
   3208         soc_block_list[165],
   3209         soc_genreg,
   3210         1,
   3211         0,
   3212         0xad,
   3213         SOC_REG_FLAG_64_BITS,
   3214         0,
   3215         17,
   3216         soc_HBC_RESERVED_MTCP_BCM88690_B0r_fields,
   3217         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   3218         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   3219         -1,
   3220         -1,
   3221     },
   3222 #endif /* chips */
   3223 
   3224 #if defined(BCM_88690_A0)
   3225     { /* SOC_REG_INT_HBC_RESERVED_SPARE_0r */
   3226         soc_block_list[165],
   3227         soc_genreg,
   3228         1,
   3229         0,
   3230         0x90,
   3231         0,
   3232         0,
   3233         1,
   3234         soc_HBC_RESERVED_SPARE_0r_fields,
   3235         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3236         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3237         -1,
   3238         -1,
   3239     },
   3240 #endif /* chips */
   3241 
   3242 #if defined(BCM_88690_A0)
   3243     { /* SOC_REG_INT_HBC_RESERVED_SPARE_1r */
   3244         soc_block_list[165],
   3245         soc_genreg,
   3246         1,
   3247         0,
   3248         0x91,
   3249         0,
   3250         0,
   3251         1,
   3252         soc_HBC_RESERVED_SPARE_1r_fields,
   3253         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3254         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3255         -1,
   3256         -1,
   3257     },
   3258 #endif /* chips */
   3259 
   3260 #if defined(BCM_88690_A0)
   3261     { /* SOC_REG_INT_HBC_RESERVED_SPARE_2r */
   3262         soc_block_list[165],
   3263         soc_genreg,
   3264         1,
   3265         0,
   3266         0x92,
   3267         0,
   3268         0,
   3269         1,
   3270         soc_HBC_RESERVED_SPARE_2r_fields,
   3271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3272         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3273         -1,
   3274         -1,
   3275     },
   3276 #endif /* chips */
   3277 
   3278 #if defined(BCM_88690_A0)
   3279     { /* SOC_REG_INT_HBC_RESERVED_SPARE_3r */
   3280         soc_block_list[165],
   3281         soc_genreg,
   3282         1,
   3283         0,
   3284         0x93,
   3285         0,
   3286         0,
   3287         1,
   3288         soc_HBC_RESERVED_SPARE_3r_fields,
   3289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3290         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3291         -1,
   3292         -1,
   3293     },
   3294 #endif /* chips */
   3295 
   3296 #if defined(BCM_88690_B0)
   3297     { /* SOC_REG_INT_HBC_RESERVED_SPARE_0_BCM88690_B0r */
   3298         soc_block_list[165],
   3299         soc_genreg,
   3300         1,
   3301         0,
   3302         0x90,
   3303         0,
   3304         0,
   3305         1,
   3306         soc_HBC_RESERVED_SPARE_0_BCM88690_B0r_fields,
   3307         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3308         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3309         -1,
   3310         -1,
   3311     },
   3312 #endif /* chips */
   3313 
   3314 #if defined(BCM_88690_B0)
   3315     { /* SOC_REG_INT_HBC_RESERVED_SPARE_1_BCM88690_B0r */
   3316         soc_block_list[165],
   3317         soc_genreg,
   3318         1,
   3319         0,
   3320         0x91,
   3321         0,
   3322         0,
   3323         1,
   3324         soc_HBC_RESERVED_SPARE_1_BCM88690_B0r_fields,
   3325         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3326         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3327         -1,
   3328         -1,
   3329     },
   3330 #endif /* chips */
   3331 
   3332 #if defined(BCM_88690_B0)
   3333     { /* SOC_REG_INT_HBC_RESERVED_SPARE_2_BCM88690_B0r */
   3334         soc_block_list[165],
   3335         soc_genreg,
   3336         1,
   3337         0,
   3338         0x92,
   3339         0,
   3340         0,
   3341         1,
   3342         soc_HBC_RESERVED_SPARE_2_BCM88690_B0r_fields,
   3343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3344         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3345         -1,
   3346         -1,
   3347     },
   3348 #endif /* chips */
   3349 
   3350 #if defined(BCM_88690_B0)
   3351     { /* SOC_REG_INT_HBC_RESERVED_SPARE_3_BCM88690_B0r */
   3352         soc_block_list[165],
   3353         soc_genreg,
   3354         1,
   3355         0,
   3356         0x93,
   3357         0,
   3358         0,
   3359         1,
   3360         soc_HBC_RESERVED_SPARE_3_BCM88690_B0r_fields,
   3361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3362         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3363         -1,
   3364         -1,
   3365     },
   3366 #endif /* chips */
   3367 
   3368 #if defined(BCM_88690_A0)
   3369     { /* SOC_REG_INT_HBC_RPBQ_CONFIGr */
   3370         soc_block_list[165],
   3371         soc_genreg,
   3372         1,
   3373         0,
   3374         0x131,
   3375         0,
   3376         0,
   3377         2,
   3378         soc_HBC_RPBQ_CONFIGr_fields,
   3379         SOC_RESET_VAL_DEC(0x00000108, 0x00000000)
   3380         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   3381         -1,
   3382         -1,
   3383     },
   3384 #endif /* chips */
   3385 
   3386 #if defined(BCM_88690_B0)
   3387     { /* SOC_REG_INT_HBC_RPBQ_CONFIG_BCM88690_B0r */
   3388         soc_block_list[165],
   3389         soc_genreg,
   3390         1,
   3391         0,
   3392         0x130,
   3393         0,
   3394         0,
   3395         2,
   3396         soc_HBC_RPBQ_CONFIG_BCM88690_B0r_fields,
   3397         SOC_RESET_VAL_DEC(0x00000108, 0x00000000)
   3398         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   3399         -1,
   3400         -1,
   3401     },
   3402 #endif /* chips */
   3403 
   3404 #if defined(BCM_88690_A0)
   3405     { /* SOC_REG_INT_HBC_RPBQ_STATUSr */
   3406         soc_block_list[165],
   3407         soc_genreg,
   3408         1,
   3409         0,
   3410         0x132,
   3411         SOC_REG_FLAG_ABOVE_64_BITS |
   3412                           SOC_REG_FLAG_RO |
   3413                           SOC_REG_FLAG_SIGNAL,
   3414         0,
   3415         1,
   3416         soc_HBC_RPBQ_STATUSr_fields,
   3417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3418         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3419         -1,
   3420         -1,
   3421     },
   3422 #endif /* chips */
   3423 
   3424 #if defined(BCM_88690_B0)
   3425     { /* SOC_REG_INT_HBC_RPBQ_STATUS_BCM88690_B0r */
   3426         soc_block_list[165],
   3427         soc_genreg,
   3428         1,
   3429         0,
   3430         0x131,
   3431         SOC_REG_FLAG_ABOVE_64_BITS |
   3432                           SOC_REG_FLAG_RO |
   3433                           SOC_REG_FLAG_SIGNAL,
   3434         0,
   3435         1,
   3436         soc_HBC_RPBQ_STATUS_BCM88690_B0r_fields,
   3437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3438         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3439         -1,
   3440         -1,
   3441     },
   3442 #endif /* chips */
   3443 
   3444 #if defined(BCM_88690_A0)
   3445     { /* SOC_REG_INT_HBC_SBUS_BROADCAST_IDr */
   3446         soc_block_list[165],
   3447         soc_genreg,
   3448         1,
   3449         0,
   3450         0x86,
   3451         0,
   3452         0,
   3453         1,
   3454         soc_HBC_SBUS_BROADCAST_IDr_fields,
   3455         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
   3456         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   3457         -1,
   3458         -1,
   3459     },
   3460 #endif /* chips */
   3461 
   3462 #if defined(BCM_88690_B0)
   3463     { /* SOC_REG_INT_HBC_SBUS_BROADCAST_ID_BCM88690_B0r */
   3464         soc_block_list[165],
   3465         soc_genreg,
   3466         1,
   3467         0,
   3468         0x86,
   3469         0,
   3470         0,
   3471         1,
   3472         soc_HBC_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
   3473         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
   3474         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   3475         -1,
   3476         -1,
   3477     },
   3478 #endif /* chips */
   3479 
   3480 #if defined(BCM_88690_A0)
   3481     { /* SOC_REG_INT_HBC_SBUS_LAST_IN_CHAINr */
   3482         soc_block_list[165],
   3483         soc_genreg,
   3484         1,
   3485         0,
   3486         0x87,
   3487         0,
   3488         0,
   3489         1,
   3490         soc_HBC_SBUS_LAST_IN_CHAINr_fields,
   3491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3492         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3493         -1,
   3494         -1,
   3495     },
   3496 #endif /* chips */
   3497 
   3498 #if defined(BCM_88690_B0)
   3499     { /* SOC_REG_INT_HBC_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
   3500         soc_block_list[165],
   3501         soc_genreg,
   3502         1,
   3503         0,
   3504         0x87,
   3505         0,
   3506         0,
   3507         1,
   3508         soc_HBC_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
   3509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3510         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3511         -1,
   3512         -1,
   3513     },
   3514 #endif /* chips */
   3515 
   3516 #if defined(BCM_88690_B0)
   3517     { /* SOC_REG_INT_HBC_SPECIAL_CLOCK_CONTROLSr */
   3518         soc_block_list[165],
   3519         soc_genreg,
   3520         1,
   3521         0,
   3522         0xc1,
   3523         0,
   3524         0,
   3525         1,
   3526         soc_HBC_SPECIAL_CLOCK_CONTROLSr_fields,
   3527         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   3528         SOC_RESET_MASK_DEC(0x00000002, 0x00000000)
   3529         -1,
   3530         -1,
   3531     },
   3532 #endif /* chips */
   3533 
   3534 #if defined(BCM_88690_A0)
   3535     { /* SOC_REG_INT_HBC_TSM_CONFIGr */
   3536         soc_block_list[165],
   3537         soc_genreg,
   3538         1,
   3539         0,
   3540         0x16d,
   3541         SOC_REG_FLAG_64_BITS,
   3542         0,
   3543         7,
   3544         soc_HBC_TSM_CONFIGr_fields,
   3545         SOC_RESET_VAL_DEC(0xffffffff, 0x00008106)
   3546         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
   3547         -1,
   3548         -1,
   3549     },
   3550 #endif /* chips */
   3551 
   3552 #if defined(BCM_88690_B0)
   3553     { /* SOC_REG_INT_HBC_TSM_CONFIG_BCM88690_B0r */
   3554         soc_block_list[165],
   3555         soc_genreg,
   3556         1,
   3557         0,
   3558         0x14c,
   3559         SOC_REG_FLAG_64_BITS,
   3560         0,
   3561         7,
   3562         soc_HBC_TSM_CONFIG_BCM88690_B0r_fields,
   3563         SOC_RESET_VAL_DEC(0xffffffff, 0x00008106)
   3564         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
   3565         -1,
   3566         -1,
   3567     },
   3568 #endif /* chips */
   3569 
   3570 #if defined(BCM_88690_A0)
   3571     { /* SOC_REG_INT_HBC_TSM_DEBUGr */
   3572         soc_block_list[165],
   3573         soc_genreg,
   3574         1,
   3575         0,
   3576         0x172,
   3577         SOC_REG_FLAG_ABOVE_64_BITS |
   3578                           SOC_REG_FLAG_RO,
   3579         SOC_REG_FLAG_COUNTER_FEILDS |
   3580                           SOC_REG_FLAG_INIT_ON_READ,
   3581         4,
   3582         soc_HBC_TSM_DEBUGr_fields,
   3583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3584         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3585         -1,
   3586         -1,
   3587     },
   3588 #endif /* chips */
   3589 
   3590 #if defined(BCM_88690_B0)
   3591     { /* SOC_REG_INT_HBC_TSM_DEBUG_BCM88690_B0r */
   3592         soc_block_list[165],
   3593         soc_genreg,
   3594         1,
   3595         0,
   3596         0x151,
   3597         SOC_REG_FLAG_ABOVE_64_BITS |
   3598                           SOC_REG_FLAG_RO,
   3599         SOC_REG_FLAG_COUNTER_FEILDS |
   3600                           SOC_REG_FLAG_INIT_ON_READ,
   3601         4,
   3602         soc_HBC_TSM_DEBUG_BCM88690_B0r_fields,
   3603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3604         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3605         -1,
   3606         -1,
   3607     },
   3608 #endif /* chips */
   3609 
   3610 #if defined(BCM_88690_A0)
   3611     { /* SOC_REG_INT_HBC_TSM_READ_WRITE_SWITCH_CONFIGr */
   3612         soc_block_list[165],
   3613         soc_genreg,
   3614         1,
   3615         0,
   3616         0x16f,
   3617         SOC_REG_FLAG_ABOVE_64_BITS,
   3618         0,
   3619         11,
   3620         soc_HBC_TSM_READ_WRITE_SWITCH_CONFIGr_fields,
   3621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3622         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3623         -1,
   3624         -1,
   3625     },
   3626 #endif /* chips */
   3627 
   3628 #if defined(BCM_88690_B0)
   3629     { /* SOC_REG_INT_HBC_TSM_READ_WRITE_SWITCH_CONFIG_BCM88690_B0r */
   3630         soc_block_list[165],
   3631         soc_genreg,
   3632         1,
   3633         0,
   3634         0x14e,
   3635         SOC_REG_FLAG_ABOVE_64_BITS,
   3636         0,
   3637         11,
   3638         soc_HBC_TSM_READ_WRITE_SWITCH_CONFIG_BCM88690_B0r_fields,
   3639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3640         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3641         -1,
   3642         -1,
   3643     },
   3644 #endif /* chips */
   3645 
   3646 #if defined(BCM_88690_A0)
   3647     { /* SOC_REG_INT_HBC_WDB_STATUSr */
   3648         soc_block_list[165],
   3649         soc_genreg,
   3650         1,
   3651         0,
   3652         0x126,
   3653         SOC_REG_FLAG_64_BITS |
   3654                           SOC_REG_FLAG_RO,
   3655         SOC_REG_FLAG_COUNTER_FEILDS |
   3656                           SOC_REG_FLAG_INIT_ON_READ,
   3657         3,
   3658         soc_HBC_WDB_STATUSr_fields,
   3659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3660         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
   3661         -1,
   3662         -1,
   3663     },
   3664 #endif /* chips */
   3665 
   3666 #if defined(BCM_88690_B0)
   3667     { /* SOC_REG_INT_HBC_WDB_STATUS_BCM88690_B0r */
   3668         soc_block_list[165],
   3669         soc_genreg,
   3670         1,
   3671         0,
   3672         0x125,
   3673         SOC_REG_FLAG_64_BITS |
   3674                           SOC_REG_FLAG_RO,
   3675         SOC_REG_FLAG_COUNTER_FEILDS |
   3676                           SOC_REG_FLAG_INIT_ON_READ,
   3677         3,
   3678         soc_HBC_WDB_STATUS_BCM88690_B0r_fields,
   3679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3680         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
   3681         -1,
   3682         -1,
   3683     },
   3684 #endif /* chips */
   3685 
   3686 #if defined(BCM_88690_A0)
   3687     { /* SOC_REG_INT_HBC_WPBQ_CONFIGr */
   3688         soc_block_list[165],
   3689         soc_genreg,
   3690         1,
   3691         0,
   3692         0x128,
   3693         0,
   3694         0,
   3695         1,
   3696         soc_HBC_WPBQ_CONFIGr_fields,
   3697         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   3698         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   3699         -1,
   3700         -1,
   3701     },
   3702 #endif /* chips */
   3703 
   3704 #if defined(BCM_88690_B0)
   3705     { /* SOC_REG_INT_HBC_WPBQ_CONFIG_BCM88690_B0r */
   3706         soc_block_list[165],
   3707         soc_genreg,
   3708         1,
   3709         0,
   3710         0x127,
   3711         0,
   3712         0,
   3713         1,
   3714         soc_HBC_WPBQ_CONFIG_BCM88690_B0r_fields,
   3715         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   3716         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   3717         -1,
   3718         -1,
   3719     },
   3720 #endif /* chips */
   3721 
   3722 #if defined(BCM_88690_A0)
   3723     { /* SOC_REG_INT_HBC_WPBQ_STATUSr */
   3724         soc_block_list[165],
   3725         soc_genreg,
   3726         1,
   3727         0,
   3728         0x129,
   3729         SOC_REG_FLAG_ABOVE_64_BITS |
   3730                           SOC_REG_FLAG_RO |
   3731                           SOC_REG_FLAG_SIGNAL,
   3732         0,
   3733         1,
   3734         soc_HBC_WPBQ_STATUSr_fields,
   3735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3736         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3737         -1,
   3738         -1,
   3739     },
   3740 #endif /* chips */
   3741 
   3742 #if defined(BCM_88690_B0)
   3743     { /* SOC_REG_INT_HBC_WPBQ_STATUS_BCM88690_B0r */
   3744         soc_block_list[165],
   3745         soc_genreg,
   3746         1,
   3747         0,
   3748         0x128,
   3749         SOC_REG_FLAG_ABOVE_64_BITS |
   3750                           SOC_REG_FLAG_RO |
   3751                           SOC_REG_FLAG_SIGNAL,
   3752         0,
   3753         1,
   3754         soc_HBC_WPBQ_STATUS_BCM88690_B0r_fields,
   3755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3756         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3757         -1,
   3758         -1,
   3759     },
   3760 #endif /* chips */
   3761 
   3762 #if defined(BCM_88690_A0)
   3763     { /* SOC_REG_INT_HBMC_ECC_INTERRUPT_REGISTERr */
   3764         soc_block_list[186],
   3765         soc_genreg,
   3766         1,
   3767         0,
   3768         0x7,
   3769         SOC_REG_FLAG_INTERRUPT |
   3770                           SOC_REG_FLAG_SIGNAL,
   3771         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   3772         3,
   3773         soc_HBMC_ECC_INTERRUPT_REGISTERr_fields,
   3774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3775         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3776         -1,
   3777         -1,
   3778     },
   3779 #endif /* chips */
   3780 
   3781 #if defined(BCM_88690_B0)
   3782     { /* SOC_REG_INT_HBMC_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
   3783         soc_block_list[186],
   3784         soc_genreg,
   3785         1,
   3786         0,
   3787         0x7,
   3788         SOC_REG_FLAG_INTERRUPT |
   3789                           SOC_REG_FLAG_SIGNAL,
   3790         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   3791         3,
   3792         soc_HBMC_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   3793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3794         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3795         -1,
   3796         -1,
   3797     },
   3798 #endif /* chips */
   3799 
   3800 #if defined(BCM_88690_A0)
   3801     { /* SOC_REG_INT_HBMC_ECC_INTERRUPT_REGISTER_MASKr */
   3802         soc_block_list[186],
   3803         soc_genreg,
   3804         1,
   3805         0,
   3806         0x17,
   3807         0,
   3808         0,
   3809         3,
   3810         soc_HBMC_ECC_INTERRUPT_REGISTER_MASKr_fields,
   3811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3812         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3813         -1,
   3814         -1,
   3815     },
   3816 #endif /* chips */
   3817 
   3818 #if defined(BCM_88690_B0)
   3819     { /* SOC_REG_INT_HBMC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
   3820         soc_block_list[186],
   3821         soc_genreg,
   3822         1,
   3823         0,
   3824         0x17,
   3825         0,
   3826         0,
   3827         3,
   3828         soc_HBMC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
   3829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3830         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3831         -1,
   3832         -1,
   3833     },
   3834 #endif /* chips */
   3835 
   3836 #if defined(BCM_88690_A0)
   3837     { /* SOC_REG_INT_HBMC_ECC_INTERRUPT_REGISTER_TESTr */
   3838         soc_block_list[186],
   3839         soc_genreg,
   3840         1,
   3841         0,
   3842         0x1f,
   3843         0,
   3844         0,
   3845         1,
   3846         soc_HBMC_ECC_INTERRUPT_REGISTER_TESTr_fields,
   3847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3848         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3849         -1,
   3850         -1,
   3851     },
   3852 #endif /* chips */
   3853 
   3854 #if defined(BCM_88690_B0)
   3855     { /* SOC_REG_INT_HBMC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   3856         soc_block_list[186],
   3857         soc_genreg,
   3858         1,
   3859         0,
   3860         0x1f,
   3861         0,
   3862         0,
   3863         1,
   3864         soc_HBMC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   3865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3866         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3867         -1,
   3868         -1,
   3869     },
   3870 #endif /* chips */
   3871 
   3872 #if defined(BCM_88690_A0)
   3873     { /* SOC_REG_INT_HBMC_ENABLE_DYNAMIC_MEMORY_ACCESSr */
   3874         soc_block_list[186],
   3875         soc_genreg,
   3876         1,
   3877         0,
   3878         0x84,
   3879         0,
   3880         0,
   3881         1,
   3882         soc_HBMC_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
   3883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3884         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3885         -1,
   3886         -1,
   3887     },
   3888 #endif /* chips */
   3889 
   3890 #if defined(BCM_88690_B0)
   3891     { /* SOC_REG_INT_HBMC_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r */
   3892         soc_block_list[186],
   3893         soc_genreg,
   3894         1,
   3895         0,
   3896         0x84,
   3897         0,
   3898         0,
   3899         1,
   3900         soc_HBMC_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r_fields,
   3901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3902         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3903         -1,
   3904         -1,
   3905     },
   3906 #endif /* chips */
   3907 
   3908 #if defined(BCM_88690_A0)
   3909     { /* SOC_REG_INT_HBMC_HBM_PHY_CHANNEL_CONTROLr */
   3910         soc_block_list[186],
   3911         soc_genreg,
   3912         9,
   3913         0,
   3914         0x10c,
   3915         SOC_REG_FLAG_ARRAY |
   3916                           SOC_REG_FLAG_REG_ARRAY,
   3917         0,
   3918         2,
   3919         soc_HBMC_HBM_PHY_CHANNEL_CONTROLr_fields,
   3920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3921         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3922         -1,
   3923         -1,
   3924     },
   3925 #endif /* chips */
   3926 
   3927 #if defined(BCM_88690_B0)
   3928     { /* SOC_REG_INT_HBMC_HBM_PHY_CHANNEL_CONTROL_BCM88690_B0r */
   3929         soc_block_list[186],
   3930         soc_genreg,
   3931         9,
   3932         0,
   3933         0x10c,
   3934         SOC_REG_FLAG_ARRAY |
   3935                           SOC_REG_FLAG_REG_ARRAY,
   3936         0,
   3937         2,
   3938         soc_HBMC_HBM_PHY_CHANNEL_CONTROL_BCM88690_B0r_fields,
   3939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3940         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3941         -1,
   3942         -1,
   3943     },
   3944 #endif /* chips */
   3945 
   3946 #if defined(BCM_88690_A0)
   3947     { /* SOC_REG_INT_HBMC_HBM_PHY_CHM_REGISTER_ACCESS_ERRORr */
   3948         soc_block_list[186],
   3949         soc_genreg,
   3950         1,
   3951         0,
   3952         0x116,
   3953         SOC_REG_FLAG_RO,
   3954         SOC_REG_FLAG_INIT_ON_READ,
   3955         1,
   3956         soc_HBMC_HBM_PHY_CHM_REGISTER_ACCESS_ERRORr_fields,
   3957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3958         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3959         -1,
   3960         -1,
   3961     },
   3962 #endif /* chips */
   3963 
   3964 #if defined(BCM_88690_B0)
   3965     { /* SOC_REG_INT_HBMC_HBM_PHY_CHM_REGISTER_ACCESS_ERROR_BCM88690_B0r */
   3966         soc_block_list[186],
   3967         soc_genreg,
   3968         1,
   3969         0,
   3970         0x116,
   3971         SOC_REG_FLAG_RO,
   3972         SOC_REG_FLAG_INIT_ON_READ,
   3973         1,
   3974         soc_HBMC_HBM_PHY_CHM_REGISTER_ACCESS_ERROR_BCM88690_B0r_fields,
   3975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3976         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3977         -1,
   3978         -1,
   3979     },
   3980 #endif /* chips */
   3981 
   3982 #if defined(BCM_88690_A0)
   3983     { /* SOC_REG_INT_HBMC_HBM_PHY_CONTROLr */
   3984         soc_block_list[186],
   3985         soc_genreg,
   3986         1,
   3987         0,
   3988         0x10b,
   3989         0,
   3990         0,
   3991         3,
   3992         soc_HBMC_HBM_PHY_CONTROLr_fields,
   3993         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3994         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3995         -1,
   3996         -1,
   3997     },
   3998 #endif /* chips */
   3999 
   4000 #if defined(BCM_88690_B0)
   4001     { /* SOC_REG_INT_HBMC_HBM_PHY_CONTROL_BCM88690_B0r */
   4002         soc_block_list[186],
   4003         soc_genreg,
   4004         1,
   4005         0,
   4006         0x10b,
   4007         0,
   4008         0,
   4009         3,
   4010         soc_HBMC_HBM_PHY_CONTROL_BCM88690_B0r_fields,
   4011         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   4012         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4013         -1,
   4014         -1,
   4015     },
   4016 #endif /* chips */
   4017 
   4018 #if defined(BCM_88690_A0)
   4019     { /* SOC_REG_INT_HBMC_HBM_PLL_CONFIGr */
   4020         soc_block_list[186],
   4021         soc_genreg,
   4022         1,
   4023         0,
   4024         0x100,
   4025         SOC_REG_FLAG_ABOVE_64_BITS,
   4026         0,
   4027         74,
   4028         soc_HBMC_HBM_PLL_CONFIGr_fields,
   4029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4030         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4031         -1,
   4032         -1,
   4033     },
   4034 #endif /* chips */
   4035 
   4036 #if defined(BCM_88690_B0)
   4037     { /* SOC_REG_INT_HBMC_HBM_PLL_CONFIG_BCM88690_B0r */
   4038         soc_block_list[186],
   4039         soc_genreg,
   4040         1,
   4041         0,
   4042         0x100,
   4043         SOC_REG_FLAG_ABOVE_64_BITS,
   4044         0,
   4045         74,
   4046         soc_HBMC_HBM_PLL_CONFIG_BCM88690_B0r_fields,
   4047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4048         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4049         -1,
   4050         -1,
   4051     },
   4052 #endif /* chips */
   4053 
   4054 #if defined(BCM_88690_A0)
   4055     { /* SOC_REG_INT_HBMC_HBM_PLL_STATUSr */
   4056         soc_block_list[186],
   4057         soc_genreg,
   4058         1,
   4059         0,
   4060         0x109,
   4061         SOC_REG_FLAG_RO |
   4062                           SOC_REG_FLAG_SIGNAL,
   4063         0,
   4064         5,
   4065         soc_HBMC_HBM_PLL_STATUSr_fields,
   4066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4067         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   4068         -1,
   4069         -1,
   4070     },
   4071 #endif /* chips */
   4072 
   4073 #if defined(BCM_88690_B0)
   4074     { /* SOC_REG_INT_HBMC_HBM_PLL_STATUS_BCM88690_B0r */
   4075         soc_block_list[186],
   4076         soc_genreg,
   4077         1,
   4078         0,
   4079         0x109,
   4080         SOC_REG_FLAG_RO |
   4081                           SOC_REG_FLAG_SIGNAL,
   4082         0,
   4083         5,
   4084         soc_HBMC_HBM_PLL_STATUS_BCM88690_B0r_fields,
   4085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4086         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   4087         -1,
   4088         -1,
   4089     },
   4090 #endif /* chips */
   4091 
   4092 #if defined(BCM_88690_A0)
   4093     { /* SOC_REG_INT_HBMC_HBM_REPAIR_CONTROLr */
   4094         soc_block_list[186],
   4095         soc_genreg,
   4096         1,
   4097         0,
   4098         0x117,
   4099         0,
   4100         0,
   4101         1,
   4102         soc_HBMC_HBM_REPAIR_CONTROLr_fields,
   4103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4104         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4105         -1,
   4106         -1,
   4107     },
   4108 #endif /* chips */
   4109 
   4110 #if defined(BCM_88690_B0)
   4111     { /* SOC_REG_INT_HBMC_HBM_REPAIR_CONTROL_BCM88690_B0r */
   4112         soc_block_list[186],
   4113         soc_genreg,
   4114         1,
   4115         0,
   4116         0x117,
   4117         0,
   4118         0,
   4119         1,
   4120         soc_HBMC_HBM_REPAIR_CONTROL_BCM88690_B0r_fields,
   4121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4122         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4123         -1,
   4124         -1,
   4125     },
   4126 #endif /* chips */
   4127 
   4128 #if defined(BCM_88690_A0)
   4129     { /* SOC_REG_INT_HBMC_HBM_REPAIR_STATUSr */
   4130         soc_block_list[186],
   4131         soc_genreg,
   4132         1,
   4133         0,
   4134         0x118,
   4135         SOC_REG_FLAG_RO,
   4136         0,
   4137         4,
   4138         soc_HBMC_HBM_REPAIR_STATUSr_fields,
   4139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4140         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4141         -1,
   4142         -1,
   4143     },
   4144 #endif /* chips */
   4145 
   4146 #if defined(BCM_88690_B0)
   4147     { /* SOC_REG_INT_HBMC_HBM_REPAIR_STATUS_BCM88690_B0r */
   4148         soc_block_list[186],
   4149         soc_genreg,
   4150         1,
   4151         0,
   4152         0x118,
   4153         SOC_REG_FLAG_RO,
   4154         0,
   4155         4,
   4156         soc_HBMC_HBM_REPAIR_STATUS_BCM88690_B0r_fields,
   4157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4158         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4159         -1,
   4160         -1,
   4161     },
   4162 #endif /* chips */
   4163 
   4164 #if defined(BCM_88690_A0)
   4165     { /* SOC_REG_INT_HBMC_HBM_RESET_CONTROLr */
   4166         soc_block_list[186],
   4167         soc_genreg,
   4168         1,
   4169         0,
   4170         0x10a,
   4171         0,
   4172         0,
   4173         3,
   4174         soc_HBMC_HBM_RESET_CONTROLr_fields,
   4175         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
   4176         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4177         -1,
   4178         -1,
   4179     },
   4180 #endif /* chips */
   4181 
   4182 #if defined(BCM_88690_B0)
   4183     { /* SOC_REG_INT_HBMC_HBM_RESET_CONTROL_BCM88690_B0r */
   4184         soc_block_list[186],
   4185         soc_genreg,
   4186         1,
   4187         0,
   4188         0x10a,
   4189         0,
   4190         0,
   4191         5,
   4192         soc_HBMC_HBM_RESET_CONTROL_BCM88690_B0r_fields,
   4193         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   4194         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   4195         -1,
   4196         -1,
   4197     },
   4198 #endif /* chips */
   4199 
   4200 #if defined(BCM_88690_A0)
   4201     { /* SOC_REG_INT_HBMC_HBM_STATUSr */
   4202         soc_block_list[186],
   4203         soc_genreg,
   4204         1,
   4205         0,
   4206         0x115,
   4207         SOC_REG_FLAG_RO,
   4208         0,
   4209         1,
   4210         soc_HBMC_HBM_STATUSr_fields,
   4211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4212         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4213         -1,
   4214         -1,
   4215     },
   4216 #endif /* chips */
   4217 
   4218 #if defined(BCM_88690_B0)
   4219     { /* SOC_REG_INT_HBMC_HBM_STATUS_BCM88690_B0r */
   4220         soc_block_list[186],
   4221         soc_genreg,
   4222         1,
   4223         0,
   4224         0x115,
   4225         SOC_REG_FLAG_RO,
   4226         0,
   4227         2,
   4228         soc_HBMC_HBM_STATUS_BCM88690_B0r_fields,
   4229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4230         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   4231         -1,
   4232         -1,
   4233     },
   4234 #endif /* chips */
   4235 
   4236 #if defined(BCM_88690_A0)
   4237     { /* SOC_REG_INT_HBMC_INDIRECT_COMMANDr */
   4238         soc_block_list[186],
   4239         soc_genreg,
   4240         1,
   4241         0,
   4242         0x80,
   4243         0,
   4244         0,
   4245         5,
   4246         soc_HBMC_INDIRECT_COMMANDr_fields,
   4247         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
   4248         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4249         -1,
   4250         -1,
   4251     },
   4252 #endif /* chips */
   4253 
   4254 #if defined(BCM_88690_A0)
   4255     { /* SOC_REG_INT_HBMC_INDIRECT_COMMAND_ADDRESSr */
   4256         soc_block_list[186],
   4257         soc_genreg,
   4258         1,
   4259         0,
   4260         0x81,
   4261         0,
   4262         0,
   4263         2,
   4264         soc_HBMC_INDIRECT_COMMAND_ADDRESSr_fields,
   4265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4266         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4267         -1,
   4268         -1,
   4269     },
   4270 #endif /* chips */
   4271 
   4272 #if defined(BCM_88690_B0)
   4273     { /* SOC_REG_INT_HBMC_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r */
   4274         soc_block_list[186],
   4275         soc_genreg,
   4276         1,
   4277         0,
   4278         0x81,
   4279         0,
   4280         0,
   4281         2,
   4282         soc_HBMC_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r_fields,
   4283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4284         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4285         -1,
   4286         -1,
   4287     },
   4288 #endif /* chips */
   4289 
   4290 #if defined(BCM_88690_B0)
   4291     { /* SOC_REG_INT_HBMC_INDIRECT_COMMAND_BCM88690_B0r */
   4292         soc_block_list[186],
   4293         soc_genreg,
   4294         1,
   4295         0,
   4296         0x80,
   4297         0,
   4298         0,
   4299         5,
   4300         soc_HBMC_INDIRECT_COMMAND_BCM88690_B0r_fields,
   4301         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
   4302         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4303         -1,
   4304         -1,
   4305     },
   4306 #endif /* chips */
   4307 
   4308 #if defined(BCM_88690_A0)
   4309     { /* SOC_REG_INT_HBMC_INDIRECT_COMMAND_RD_DATAr */
   4310         soc_block_list[186],
   4311         soc_genreg,
   4312         1,
   4313         0,
   4314         0x60,
   4315         SOC_REG_FLAG_RO |
   4316                           SOC_REG_FLAG_SIGNAL,
   4317         0,
   4318         1,
   4319         soc_HBMC_INDIRECT_COMMAND_RD_DATAr_fields,
   4320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4321         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4322         -1,
   4323         -1,
   4324     },
   4325 #endif /* chips */
   4326 
   4327 #if defined(BCM_88690_B0)
   4328     { /* SOC_REG_INT_HBMC_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r */
   4329         soc_block_list[186],
   4330         soc_genreg,
   4331         1,
   4332         0,
   4333         0x60,
   4334         SOC_REG_FLAG_RO |
   4335                           SOC_REG_FLAG_SIGNAL,
   4336         0,
   4337         1,
   4338         soc_HBMC_INDIRECT_COMMAND_RD_DATA_BCM88690_B0r_fields,
   4339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4340         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4341         -1,
   4342         -1,
   4343     },
   4344 #endif /* chips */
   4345 
   4346 #if defined(BCM_88690_A0)
   4347     { /* SOC_REG_INT_HBMC_INDIRECT_COMMAND_WR_DATAr */
   4348         soc_block_list[186],
   4349         soc_genreg,
   4350         1,
   4351         0,
   4352         0x20,
   4353         0,
   4354         0,
   4355         1,
   4356         soc_HBMC_INDIRECT_COMMAND_WR_DATAr_fields,
   4357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4358         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4359         -1,
   4360         -1,
   4361     },
   4362 #endif /* chips */
   4363 
   4364 #if defined(BCM_88690_B0)
   4365     { /* SOC_REG_INT_HBMC_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r */
   4366         soc_block_list[186],
   4367         soc_genreg,
   4368         1,
   4369         0,
   4370         0x20,
   4371         0,
   4372         0,
   4373         1,
   4374         soc_HBMC_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r_fields,
   4375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4377         -1,
   4378         -1,
   4379     },
   4380 #endif /* chips */
   4381 
   4382 #if defined(BCM_88690_A0)
   4383     { /* SOC_REG_INT_HBMC_INDIRECT_FORCE_BUBBLEr */
   4384         soc_block_list[186],
   4385         soc_genreg,
   4386         1,
   4387         0,
   4388         0x83,
   4389         0,
   4390         0,
   4391         4,
   4392         soc_HBMC_INDIRECT_FORCE_BUBBLEr_fields,
   4393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4394         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   4395         -1,
   4396         -1,
   4397     },
   4398 #endif /* chips */
   4399 
   4400 #if defined(BCM_88690_B0)
   4401     { /* SOC_REG_INT_HBMC_INDIRECT_FORCE_BUBBLE_BCM88690_B0r */
   4402         soc_block_list[186],
   4403         soc_genreg,
   4404         1,
   4405         0,
   4406         0x83,
   4407         0,
   4408         0,
   4409         4,
   4410         soc_HBMC_INDIRECT_FORCE_BUBBLE_BCM88690_B0r_fields,
   4411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4412         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   4413         -1,
   4414         -1,
   4415     },
   4416 #endif /* chips */
   4417 
   4418 #if defined(BCM_88690_A0)
   4419     { /* SOC_REG_INT_HBMC_INTERRUPT_MASK_REGISTERr */
   4420         soc_block_list[186],
   4421         soc_genreg,
   4422         1,
   4423         0,
   4424         0x10,
   4425         0,
   4426         0,
   4427         2,
   4428         soc_HBMC_INTERRUPT_MASK_REGISTERr_fields,
   4429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4430         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4431         -1,
   4432         -1,
   4433     },
   4434 #endif /* chips */
   4435 
   4436 #if defined(BCM_88690_B0)
   4437     { /* SOC_REG_INT_HBMC_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
   4438         soc_block_list[186],
   4439         soc_genreg,
   4440         1,
   4441         0,
   4442         0x10,
   4443         0,
   4444         0,
   4445         3,
   4446         soc_HBMC_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
   4447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4448         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4449         -1,
   4450         -1,
   4451     },
   4452 #endif /* chips */
   4453 
   4454 #if defined(BCM_88690_A0)
   4455     { /* SOC_REG_INT_HBMC_INTERRUPT_REGISTERr */
   4456         soc_block_list[186],
   4457         soc_genreg,
   4458         1,
   4459         0,
   4460         0,
   4461         SOC_REG_FLAG_INTERRUPT |
   4462                           SOC_REG_FLAG_SIGNAL,
   4463         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   4464         2,
   4465         soc_HBMC_INTERRUPT_REGISTERr_fields,
   4466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4467         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4468         -1,
   4469         -1,
   4470     },
   4471 #endif /* chips */
   4472 
   4473 #if defined(BCM_88690_B0)
   4474     { /* SOC_REG_INT_HBMC_INTERRUPT_REGISTER_BCM88690_B0r */
   4475         soc_block_list[186],
   4476         soc_genreg,
   4477         1,
   4478         0,
   4479         0,
   4480         SOC_REG_FLAG_INTERRUPT |
   4481                           SOC_REG_FLAG_SIGNAL,
   4482         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   4483         3,
   4484         soc_HBMC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   4485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4486         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4487         -1,
   4488         -1,
   4489     },
   4490 #endif /* chips */
   4491 
   4492 #if defined(BCM_88690_A0)
   4493     { /* SOC_REG_INT_HBMC_INTERRUPT_REGISTER_TESTr */
   4494         soc_block_list[186],
   4495         soc_genreg,
   4496         1,
   4497         0,
   4498         0x18,
   4499         0,
   4500         0,
   4501         1,
   4502         soc_HBMC_INTERRUPT_REGISTER_TESTr_fields,
   4503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4504         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4505         -1,
   4506         -1,
   4507     },
   4508 #endif /* chips */
   4509 
   4510 #if defined(BCM_88690_B0)
   4511     { /* SOC_REG_INT_HBMC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   4512         soc_block_list[186],
   4513         soc_genreg,
   4514         1,
   4515         0,
   4516         0x18,
   4517         0,
   4518         0,
   4519         1,
   4520         soc_HBMC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   4521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4522         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4523         -1,
   4524         -1,
   4525     },
   4526 #endif /* chips */
   4527 
   4528 #if defined(BCM_88690_A0)
   4529     { /* SOC_REG_INT_HBMC_REG_0041r */
   4530         soc_block_list[186],
   4531         soc_genreg,
   4532         1,
   4533         0,
   4534         0x41,
   4535         0,
   4536         0,
   4537         1,
   4538         soc_HBMC_REG_0041r_fields,
   4539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4540         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4541         -1,
   4542         -1,
   4543     },
   4544 #endif /* chips */
   4545 
   4546 #if defined(BCM_88690_B0)
   4547     { /* SOC_REG_INT_HBMC_REG_0041_BCM88690_B0r */
   4548         soc_block_list[186],
   4549         soc_genreg,
   4550         1,
   4551         0,
   4552         0x41,
   4553         0,
   4554         0,
   4555         1,
   4556         soc_HBMC_REG_0041_BCM88690_B0r_fields,
   4557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4558         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4559         -1,
   4560         -1,
   4561     },
   4562 #endif /* chips */
   4563 
   4564 #if defined(BCM_88690_A0)
   4565     { /* SOC_REG_INT_HBMC_REG_009Ar */
   4566         soc_block_list[186],
   4567         soc_genreg,
   4568         1,
   4569         0,
   4570         0x9a,
   4571         0,
   4572         0,
   4573         1,
   4574         soc_HBMC_REG_009Ar_fields,
   4575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4576         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4577         -1,
   4578         -1,
   4579     },
   4580 #endif /* chips */
   4581 
   4582 #if defined(BCM_88690_B0)
   4583     { /* SOC_REG_INT_HBMC_REG_009A_BCM88690_B0r */
   4584         soc_block_list[186],
   4585         soc_genreg,
   4586         1,
   4587         0,
   4588         0x9a,
   4589         0,
   4590         0,
   4591         1,
   4592         soc_HBMC_REG_009A_BCM88690_B0r_fields,
   4593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4594         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4595         -1,
   4596         -1,
   4597     },
   4598 #endif /* chips */
   4599 
   4600 #if defined(BCM_88690_A0)
   4601     { /* SOC_REG_INT_HBMC_REG_009Cr */
   4602         soc_block_list[186],
   4603         soc_genreg,
   4604         1,
   4605         0,
   4606         0x9c,
   4607         0,
   4608         0,
   4609         1,
   4610         soc_HBMC_REG_009Cr_fields,
   4611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4612         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4613         -1,
   4614         -1,
   4615     },
   4616 #endif /* chips */
   4617 
   4618 #if defined(BCM_88690_B0)
   4619     { /* SOC_REG_INT_HBMC_REG_009C_BCM88690_B0r */
   4620         soc_block_list[186],
   4621         soc_genreg,
   4622         1,
   4623         0,
   4624         0x9c,
   4625         0,
   4626         0,
   4627         1,
   4628         soc_HBMC_REG_009C_BCM88690_B0r_fields,
   4629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4630         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4631         -1,
   4632         -1,
   4633     },
   4634 #endif /* chips */
   4635 
   4636 #if defined(BCM_88690_A0)
   4637     { /* SOC_REG_INT_HBMC_REG_00A4r */
   4638         soc_block_list[186],
   4639         soc_genreg,
   4640         1,
   4641         0,
   4642         0xa4,
   4643         0,
   4644         0,
   4645         1,
   4646         soc_HBMC_REG_00A4r_fields,
   4647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4648         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4649         -1,
   4650         -1,
   4651     },
   4652 #endif /* chips */
   4653 
   4654 #if defined(BCM_88690_A0)
   4655     { /* SOC_REG_INT_HBMC_REG_00A6r */
   4656         soc_block_list[186],
   4657         soc_genreg,
   4658         1,
   4659         0,
   4660         0xa6,
   4661         0,
   4662         0,
   4663         1,
   4664         soc_HBMC_REG_00A6r_fields,
   4665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4666         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4667         -1,
   4668         -1,
   4669     },
   4670 #endif /* chips */
   4671 
   4672 #if defined(BCM_88690_A0)
   4673     { /* SOC_REG_INT_HBMC_RESERVED_MIRROR_ADDRr */
   4674         soc_block_list[186],
   4675         soc_genreg,
   4676         1,
   4677         0,
   4678         0x85,
   4679         0,
   4680         0,
   4681         2,
   4682         soc_HBMC_RESERVED_MIRROR_ADDRr_fields,
   4683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4684         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   4685         -1,
   4686         -1,
   4687     },
   4688 #endif /* chips */
   4689 
   4690 #if defined(BCM_88690_B0)
   4691     { /* SOC_REG_INT_HBMC_RESERVED_MIRROR_ADDR_BCM88690_B0r */
   4692         soc_block_list[186],
   4693         soc_genreg,
   4694         1,
   4695         0,
   4696         0x85,
   4697         0,
   4698         0,
   4699         2,
   4700         soc_HBMC_RESERVED_MIRROR_ADDR_BCM88690_B0r_fields,
   4701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4702         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   4703         -1,
   4704         -1,
   4705     },
   4706 #endif /* chips */
   4707 
   4708 #if defined(BCM_88690_A0)
   4709     { /* SOC_REG_INT_HBMC_RESERVED_MTCDr */
   4710         soc_block_list[186],
   4711         soc_genreg,
   4712         1,
   4713         0,
   4714         0xae,
   4715         0,
   4716         0,
   4717         6,
   4718         soc_HBMC_RESERVED_MTCDr_fields,
   4719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4720         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   4721         -1,
   4722         -1,
   4723     },
   4724 #endif /* chips */
   4725 
   4726 #if defined(BCM_88690_B0)
   4727     { /* SOC_REG_INT_HBMC_RESERVED_MTCD_BCM88690_B0r */
   4728         soc_block_list[186],
   4729         soc_genreg,
   4730         1,
   4731         0,
   4732         0xae,
   4733         0,
   4734         0,
   4735         6,
   4736         soc_HBMC_RESERVED_MTCD_BCM88690_B0r_fields,
   4737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4738         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   4739         -1,
   4740         -1,
   4741     },
   4742 #endif /* chips */
   4743 
   4744 #if defined(BCM_88690_A0)
   4745     { /* SOC_REG_INT_HBMC_RESERVED_MTCPr */
   4746         soc_block_list[186],
   4747         soc_genreg,
   4748         1,
   4749         0,
   4750         0xad,
   4751         SOC_REG_FLAG_64_BITS,
   4752         0,
   4753         17,
   4754         soc_HBMC_RESERVED_MTCPr_fields,
   4755         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   4756         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   4757         -1,
   4758         -1,
   4759     },
   4760 #endif /* chips */
   4761 
   4762 #if defined(BCM_88690_B0)
   4763     { /* SOC_REG_INT_HBMC_RESERVED_MTCP_BCM88690_B0r */
   4764         soc_block_list[186],
   4765         soc_genreg,
   4766         1,
   4767         0,
   4768         0xad,
   4769         SOC_REG_FLAG_64_BITS,
   4770         0,
   4771         17,
   4772         soc_HBMC_RESERVED_MTCP_BCM88690_B0r_fields,
   4773         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   4774         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   4775         -1,
   4776         -1,
   4777     },
   4778 #endif /* chips */
   4779 
   4780 #if defined(BCM_88690_A0)
   4781     { /* SOC_REG_INT_HBMC_RESERVED_SPARE_0r */
   4782         soc_block_list[186],
   4783         soc_genreg,
   4784         1,
   4785         0,
   4786         0x90,
   4787         0,
   4788         0,
   4789         1,
   4790         soc_HBMC_RESERVED_SPARE_0r_fields,
   4791         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4792         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4793         -1,
   4794         -1,
   4795     },
   4796 #endif /* chips */
   4797 
   4798 #if defined(BCM_88690_A0)
   4799     { /* SOC_REG_INT_HBMC_RESERVED_SPARE_1r */
   4800         soc_block_list[186],
   4801         soc_genreg,
   4802         1,
   4803         0,
   4804         0x91,
   4805         0,
   4806         0,
   4807         1,
   4808         soc_HBMC_RESERVED_SPARE_1r_fields,
   4809         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4810         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4811         -1,
   4812         -1,
   4813     },
   4814 #endif /* chips */
   4815 
   4816 #if defined(BCM_88690_A0)
   4817     { /* SOC_REG_INT_HBMC_RESERVED_SPARE_2r */
   4818         soc_block_list[186],
   4819         soc_genreg,
   4820         1,
   4821         0,
   4822         0x92,
   4823         0,
   4824         0,
   4825         1,
   4826         soc_HBMC_RESERVED_SPARE_2r_fields,
   4827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4828         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4829         -1,
   4830         -1,
   4831     },
   4832 #endif /* chips */
   4833 
   4834 #if defined(BCM_88690_A0)
   4835     { /* SOC_REG_INT_HBMC_RESERVED_SPARE_3r */
   4836         soc_block_list[186],
   4837         soc_genreg,
   4838         1,
   4839         0,
   4840         0x93,
   4841         0,
   4842         0,
   4843         1,
   4844         soc_HBMC_RESERVED_SPARE_3r_fields,
   4845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4846         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4847         -1,
   4848         -1,
   4849     },
   4850 #endif /* chips */
   4851 
   4852 #if defined(BCM_88690_B0)
   4853     { /* SOC_REG_INT_HBMC_RESERVED_SPARE_0_BCM88690_B0r */
   4854         soc_block_list[186],
   4855         soc_genreg,
   4856         1,
   4857         0,
   4858         0x90,
   4859         0,
   4860         0,
   4861         1,
   4862         soc_HBMC_RESERVED_SPARE_0_BCM88690_B0r_fields,
   4863         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4864         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4865         -1,
   4866         -1,
   4867     },
   4868 #endif /* chips */
   4869 
   4870 #if defined(BCM_88690_B0)
   4871     { /* SOC_REG_INT_HBMC_RESERVED_SPARE_1_BCM88690_B0r */
   4872         soc_block_list[186],
   4873         soc_genreg,
   4874         1,
   4875         0,
   4876         0x91,
   4877         0,
   4878         0,
   4879         1,
   4880         soc_HBMC_RESERVED_SPARE_1_BCM88690_B0r_fields,
   4881         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4882         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4883         -1,
   4884         -1,
   4885     },
   4886 #endif /* chips */
   4887 
   4888 #if defined(BCM_88690_B0)
   4889     { /* SOC_REG_INT_HBMC_RESERVED_SPARE_2_BCM88690_B0r */
   4890         soc_block_list[186],
   4891         soc_genreg,
   4892         1,
   4893         0,
   4894         0x92,
   4895         0,
   4896         0,
   4897         1,
   4898         soc_HBMC_RESERVED_SPARE_2_BCM88690_B0r_fields,
   4899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4900         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4901         -1,
   4902         -1,
   4903     },
   4904 #endif /* chips */
   4905 
   4906 #if defined(BCM_88690_B0)
   4907     { /* SOC_REG_INT_HBMC_RESERVED_SPARE_3_BCM88690_B0r */
   4908         soc_block_list[186],
   4909         soc_genreg,
   4910         1,
   4911         0,
   4912         0x93,
   4913         0,
   4914         0,
   4915         1,
   4916         soc_HBMC_RESERVED_SPARE_3_BCM88690_B0r_fields,
   4917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4918         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4919         -1,
   4920         -1,
   4921     },
   4922 #endif /* chips */
   4923 
   4924 #if defined(BCM_88690_A0)
   4925     { /* SOC_REG_INT_HBMC_SBUS_BROADCAST_IDr */
   4926         soc_block_list[186],
   4927         soc_genreg,
   4928         1,
   4929         0,
   4930         0x86,
   4931         0,
   4932         0,
   4933         1,
   4934         soc_HBMC_SBUS_BROADCAST_IDr_fields,
   4935         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
   4936         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   4937         -1,
   4938         -1,
   4939     },
   4940 #endif /* chips */
   4941 
   4942 #if defined(BCM_88690_B0)
   4943     { /* SOC_REG_INT_HBMC_SBUS_BROADCAST_ID_BCM88690_B0r */
   4944         soc_block_list[186],
   4945         soc_genreg,
   4946         1,
   4947         0,
   4948         0x86,
   4949         0,
   4950         0,
   4951         1,
   4952         soc_HBMC_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
   4953         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
   4954         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   4955         -1,
   4956         -1,
   4957     },
   4958 #endif /* chips */
   4959 
   4960 #if defined(BCM_88690_A0)
   4961     { /* SOC_REG_INT_HBMC_SBUS_LAST_IN_CHAINr */
   4962         soc_block_list[186],
   4963         soc_genreg,
   4964         1,
   4965         0,
   4966         0x87,
   4967         0,
   4968         0,
   4969         1,
   4970         soc_HBMC_SBUS_LAST_IN_CHAINr_fields,
   4971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4972         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4973         -1,
   4974         -1,
   4975     },
   4976 #endif /* chips */
   4977 
   4978 #if defined(BCM_88690_B0)
   4979     { /* SOC_REG_INT_HBMC_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
   4980         soc_block_list[186],
   4981         soc_genreg,
   4982         1,
   4983         0,
   4984         0x87,
   4985         0,
   4986         0,
   4987         1,
   4988         soc_HBMC_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
   4989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4990         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4991         -1,
   4992         -1,
   4993     },
   4994 #endif /* chips */
   4995 
   4996 #if defined(BCM_88690_B0)
   4997     { /* SOC_REG_INT_HBMC_SPECIAL_CLOCK_CONTROLSr */
   4998         soc_block_list[186],
   4999         soc_genreg,
   5000         1,
   5001         0,
   5002         0xc1,
   5003         0,
   5004         0,
   5005         1,
   5006         soc_HBMC_SPECIAL_CLOCK_CONTROLSr_fields,
   5007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5008         SOC_RESET_MASK_DEC(0x00000002, 0x00000000)
   5009         -1,
   5010         -1,
   5011     },
   5012 #endif /* chips */
   5013 
   5014 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5015     { /* SOC_REG_INT_HCFC_ERRr */
   5016         soc_block_list[4],
   5017         soc_genreg,
   5018         1,
   5019         0,
   5020         0x52002100,
   5021         0,
   5022         0,
   5023         1,
   5024         soc_HCFC_ERRr_fields,
   5025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5026         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5027         -1,
   5028         -1,
   5029     },
   5030 #endif /* chips */
   5031 
   5032 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   5033     defined(BCM_56270_A0)
   5034     { /* SOC_REG_INT_HCFC_ERR_BCM56260_A0r */
   5035         soc_block_list[4],
   5036         soc_genreg,
   5037         1,
   5038         0,
   5039         0x56001300,
   5040         0,
   5041         0,
   5042         1,
   5043         soc_HCFC_ERR_BCM56560_A0r_fields,
   5044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5045         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5046         -1,
   5047         -1,
   5048     },
   5049 #endif /* chips */
   5050 
   5051 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5052     defined(BCM_56450_B1)
   5053     { /* SOC_REG_INT_HCFC_ERR_BCM56450_A0r */
   5054         soc_block_list[4],
   5055         soc_genreg,
   5056         1,
   5057         0,
   5058         0x56002300,
   5059         0,
   5060         0,
   5061         1,
   5062         soc_HCFC_ERRr_fields,
   5063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5064         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5065         -1,
   5066         -1,
   5067     },
   5068 #endif /* chips */
   5069 
   5070 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   5071     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   5072     { /* SOC_REG_INT_HCFC_ERR_BCM56560_A0r */
   5073         soc_block_list[4],
   5074         soc_genreg,
   5075         4,
   5076         0,
   5077         0x56003100,
   5078         SOC_REG_FLAG_ARRAY,
   5079         0,
   5080         1,
   5081         soc_HCFC_ERR_BCM56560_A0r_fields,
   5082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5083         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5084         -1,
   5085         -1,
   5086     },
   5087 #endif /* chips */
   5088 
   5089 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   5090     { /* SOC_REG_INT_HCFC_ERR_BCM56850_A0r */
   5091         soc_block_list[4],
   5092         soc_genreg,
   5093         4,
   5094         0,
   5095         0x56003100,
   5096         SOC_REG_FLAG_ARRAY,
   5097         0,
   5098         1,
   5099         soc_HCFC_ERRr_fields,
   5100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5101         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5102         -1,
   5103         -1,
   5104     },
   5105 #endif /* chips */
   5106 
   5107 #if defined(BCM_88732_A0)
   5108     { /* SOC_REG_INT_HDR_CAPTURE_CONTROLr */
   5109         soc_block_list[5],
   5110         soc_genreg,
   5111         1,
   5112         0,
   5113         0x8011e,
   5114         0,
   5115         0,
   5116         3,
   5117         soc_HDR_CAPTURE_CONTROLr_fields,
   5118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5119         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   5120         -1,
   5121         -1,
   5122     },
   5123 #endif /* chips */
   5124 
   5125 #if defined(BCM_88732_A0)
   5126     { /* SOC_REG_INT_HDR_CAPTURE_DATAr */
   5127         soc_block_list[5],
   5128         soc_genreg,
   5129         32,
   5130         0,
   5131         0x8011f,
   5132         SOC_REG_FLAG_64_BITS |
   5133                           SOC_REG_FLAG_ARRAY,
   5134         0,
   5135         1,
   5136         soc_HDR_CAPTURE_DATAr_fields,
   5137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5138         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5139         -1,
   5140         -1,
   5141     },
   5142 #endif /* chips */
   5143 
   5144 #if defined(BCM_88732_A0)
   5145     { /* SOC_REG_INT_HDR_CAPTURE_MDATA0r */
   5146         soc_block_list[5],
   5147         soc_genreg,
   5148         1,
   5149         0,
   5150         0x8013f,
   5151         0,
   5152         0,
   5153         10,
   5154         soc_HDR_CAPTURE_MDATA0r_fields,
   5155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5156         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   5157         -1,
   5158         -1,
   5159     },
   5160 #endif /* chips */
   5161 
   5162 #if defined(BCM_88732_A0)
   5163     { /* SOC_REG_INT_HDR_CAPTURE_MDATA1r */
   5164         soc_block_list[5],
   5165         soc_genreg,
   5166         1,
   5167         0,
   5168         0x80140,
   5169         SOC_REG_FLAG_64_BITS,
   5170         0,
   5171         4,
   5172         soc_HDR_CAPTURE_MDATA1r_fields,
   5173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5174         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
   5175         -1,
   5176         -1,
   5177     },
   5178 #endif /* chips */
   5179 
   5180 #if defined(BCM_56640_A0)
   5181     { /* SOC_REG_INT_HES_L0_CONFIGr */
   5182         soc_block_list[4],
   5183         soc_portreg,
   5184         1,
   5185         0,
   5186         0x18002b00,
   5187         0,
   5188         0,
   5189         2,
   5190         soc_HES_L0_CONFIGr_fields,
   5191         SOC_RESET_VAL_DEC(0x000003ff, 0x00000000)
   5192         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   5193         -1,
   5194         58,
   5195     },
   5196 #endif /* chips */
   5197 
   5198 #if defined(BCM_56640_A0)
   5199     { /* SOC_REG_INT_HES_PORT_CONFIGr */
   5200         soc_block_list[4],
   5201         soc_portreg,
   5202         1,
   5203         0,
   5204         0x18000100,
   5205         0,
   5206         0,
   5207         5,
   5208         soc_HES_PORT_CONFIGr_fields,
   5209         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5210         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   5211         -1,
   5212         58,
   5213     },
   5214 #endif /* chips */
   5215 
   5216 #if defined(BCM_56640_A0)
   5217     { /* SOC_REG_INT_HES_Q_COSMASKr */
   5218         soc_block_list[4],
   5219         soc_portreg,
   5220         1,
   5221         0,
   5222         0x18002f00,
   5223         0,
   5224         0,
   5225         1,
   5226         soc_HES_Q_COSMASKr_fields,
   5227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5228         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5229         -1,
   5230         58,
   5231     },
   5232 #endif /* chips */
   5233 
   5234 #if defined(BCM_56640_A0)
   5235     { /* SOC_REG_INT_HES_Q_COSWEIGHTSr */
   5236         soc_block_list[4],
   5237         soc_portreg,
   5238         20,
   5239         0,
   5240         0x18003100,
   5241         SOC_REG_FLAG_ARRAY,
   5242         0,
   5243         1,
   5244         soc_HES_Q_COSWEIGHTSr_fields,
   5245         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   5246         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   5247         -1,
   5248         58,
   5249     },
   5250 #endif /* chips */
   5251 
   5252 #if defined(BCM_56640_A0)
   5253     { /* SOC_REG_INT_HES_Q_MINSPr */
   5254         soc_block_list[4],
   5255         soc_portreg,
   5256         1,
   5257         0,
   5258         0x18002d00,
   5259         0,
   5260         0,
   5261         1,
   5262         soc_HES_Q_MINSPr_fields,
   5263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5264         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5265         -1,
   5266         58,
   5267     },
   5268 #endif /* chips */
   5269 
   5270 #if defined(BCM_56640_A0)
   5271     { /* SOC_REG_INT_HES_Q_WERRCOUNTr */
   5272         soc_block_list[4],
   5273         soc_portreg,
   5274         20,
   5275         0,
   5276         0x18005900,
   5277         SOC_REG_FLAG_ARRAY,
   5278         0,
   5279         2,
   5280         soc_HES_Q_WERRCOUNTr_fields,
   5281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5282         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   5283         -1,
   5284         58,
   5285     },
   5286 #endif /* chips */
   5287 
   5288 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5289     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5290     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5291     { /* SOC_REG_INT_HG_COUNTERS_PARITY_CONTROLr */
   5292         soc_block_list[5],
   5293         soc_genreg,
   5294         1,
   5295         0,
   5296         0xe0802bb,
   5297         0,
   5298         0,
   5299         1,
   5300         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   5301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5302         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5303         -1,
   5304         -1,
   5305     },
   5306 #endif /* chips */
   5307 
   5308 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   5309     { /* SOC_REG_INT_HG_COUNTERS_PARITY_CONTROL_BCM56260_A0r */
   5310         soc_block_list[5],
   5311         soc_genreg,
   5312         1,
   5313         0,
   5314         0x3e019900,
   5315         0,
   5316         0,
   5317         1,
   5318         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
   5319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5321         -1,
   5322         -1,
   5323     },
   5324 #endif /* chips */
   5325 
   5326 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5327     defined(BCM_56450_B1)
   5328     { /* SOC_REG_INT_HG_COUNTERS_PARITY_CONTROL_BCM56450_A0r */
   5329         soc_block_list[5],
   5330         soc_genreg,
   5331         1,
   5332         0,
   5333         0x3e018f00,
   5334         0,
   5335         0,
   5336         1,
   5337         soc_FT_CNTR_SER_CONTROLr_fields,
   5338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5339         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5340         -1,
   5341         -1,
   5342     },
   5343 #endif /* chips */
   5344 
   5345 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   5346     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5347     { /* SOC_REG_INT_HG_COUNTERS_PARITY_CONTROL_BCM56840_A0r */
   5348         soc_block_list[5],
   5349         soc_genreg,
   5350         1,
   5351         0,
   5352         0xf080d8d,
   5353         0,
   5354         0,
   5355         1,
   5356         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
   5357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5358         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5359         -1,
   5360         -1,
   5361     },
   5362 #endif /* chips */
   5363 
   5364 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5365     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5366     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5367     { /* SOC_REG_INT_HG_COUNTERS_PARITY_STATUS_INTRr */
   5368         soc_block_list[5],
   5369         soc_genreg,
   5370         1,
   5371         0,
   5372         0xe0802bc,
   5373         0,
   5374         0,
   5375         5,
   5376         soc_EGR_STATS_COUNTER_TABLE_STATUS_INTRr_fields,
   5377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5378         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5379         -1,
   5380         -1,
   5381     },
   5382 #endif /* chips */
   5383 
   5384 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5385     { /* SOC_REG_INT_HG_COUNTERS_PARITY_STATUS_INTR_BCM56440_A0r */
   5386         soc_block_list[5],
   5387         soc_genreg,
   5388         1,
   5389         0,
   5390         0xf080d8b,
   5391         0,
   5392         0,
   5393         5,
   5394         soc_EGR_STATS_COUNTER_TABLE_PARITY_STATUS_INTR_BCM56440_A0r_fields,
   5395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5397         -1,
   5398         -1,
   5399     },
   5400 #endif /* chips */
   5401 
   5402 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5403     defined(BCM_56450_B1)
   5404     { /* SOC_REG_INT_HG_COUNTERS_PARITY_STATUS_INTR_BCM56450_A0r */
   5405         soc_block_list[5],
   5406         soc_genreg,
   5407         1,
   5408         0,
   5409         0x3e019000,
   5410         0,
   5411         0,
   5412         5,
   5413         soc_HG_COUNTERS_PARITY_STATUS_INTRr_fields,
   5414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5415         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5416         -1,
   5417         -1,
   5418     },
   5419 #endif /* chips */
   5420 
   5421 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5422     { /* SOC_REG_INT_HG_COUNTERS_PARITY_STATUS_INTR_BCM56840_A0r */
   5423         soc_block_list[5],
   5424         soc_genreg,
   5425         1,
   5426         0,
   5427         0xf080d8e,
   5428         0,
   5429         0,
   5430         5,
   5431         soc_EGR_STATS_COUNTER_TABLE_PARITY_STATUS_INTRr_fields,
   5432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5433         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5434         -1,
   5435         -1,
   5436     },
   5437 #endif /* chips */
   5438 
   5439 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5440     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5441     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5442     { /* SOC_REG_INT_HG_COUNTERS_PARITY_STATUS_NACKr */
   5443         soc_block_list[5],
   5444         soc_genreg,
   5445         1,
   5446         0,
   5447         0xe0802bd,
   5448         0,
   5449         0,
   5450         5,
   5451         soc_EGR_STATS_COUNTER_TABLE_STATUS_INTRr_fields,
   5452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5453         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5454         -1,
   5455         -1,
   5456     },
   5457 #endif /* chips */
   5458 
   5459 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5460     { /* SOC_REG_INT_HG_COUNTERS_PARITY_STATUS_NACK_BCM56440_A0r */
   5461         soc_block_list[5],
   5462         soc_genreg,
   5463         1,
   5464         0,
   5465         0xf080d8c,
   5466         0,
   5467         0,
   5468         5,
   5469         soc_EGR_STATS_COUNTER_TABLE_PARITY_STATUS_INTR_BCM56440_A0r_fields,
   5470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5472         -1,
   5473         -1,
   5474     },
   5475 #endif /* chips */
   5476 
   5477 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5478     defined(BCM_56450_B1)
   5479     { /* SOC_REG_INT_HG_COUNTERS_PARITY_STATUS_NACK_BCM56450_A0r */
   5480         soc_block_list[5],
   5481         soc_genreg,
   5482         1,
   5483         0,
   5484         0x3e019100,
   5485         0,
   5486         0,
   5487         5,
   5488         soc_HG_COUNTERS_PARITY_STATUS_INTRr_fields,
   5489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5490         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5491         -1,
   5492         -1,
   5493     },
   5494 #endif /* chips */
   5495 
   5496 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5497     { /* SOC_REG_INT_HG_COUNTERS_PARITY_STATUS_NACK_BCM56840_A0r */
   5498         soc_block_list[5],
   5499         soc_genreg,
   5500         1,
   5501         0,
   5502         0xf080d8f,
   5503         0,
   5504         0,
   5505         5,
   5506         soc_EGR_STATS_COUNTER_TABLE_PARITY_STATUS_INTRr_fields,
   5507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5508         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5509         -1,
   5510         -1,
   5511     },
   5512 #endif /* chips */
   5513 
   5514 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5515     { /* SOC_REG_INT_HG_EH_CONTROLr */
   5516         soc_block_list[5],
   5517         soc_genreg,
   5518         1,
   5519         0,
   5520         0xa004200,
   5521         0,
   5522         0,
   5523         1,
   5524         soc_HG_EH_CONTROLr_fields,
   5525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5526         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5527         -1,
   5528         -1,
   5529     },
   5530 #endif /* chips */
   5531 
   5532 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   5533     defined(BCM_56270_A0)
   5534     { /* SOC_REG_INT_HG_EH_CONTROL_BCM56260_A0r */
   5535         soc_block_list[5],
   5536         soc_genreg,
   5537         1,
   5538         0,
   5539         0xa002800,
   5540         0,
   5541         0,
   5542         1,
   5543         soc_HG_EH_CONTROL_BCM56960_A0r_fields,
   5544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5545         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5546         -1,
   5547         -1,
   5548     },
   5549 #endif /* chips */
   5550 
   5551 #if defined(BCM_56370_A0)
   5552     { /* SOC_REG_INT_HG_EH_CONTROL_BCM56370_A0r */
   5553         soc_block_list[5],
   5554         soc_genreg,
   5555         1,
   5556         0,
   5557         0x4e018d00,
   5558         0,
   5559         0,
   5560         1,
   5561         soc_HG_EH_CONTROL_BCM56960_A0r_fields,
   5562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5563         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5564         -1,
   5565         -1,
   5566         3,
   5567     },
   5568 #endif /* chips */
   5569 
   5570 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5571     defined(BCM_56450_B1)
   5572     { /* SOC_REG_INT_HG_EH_CONTROL_BCM56450_A0r */
   5573         soc_block_list[5],
   5574         soc_genreg,
   5575         1,
   5576         0,
   5577         0xa002800,
   5578         0,
   5579         0,
   5580         1,
   5581         soc_HG_EH_CONTROLr_fields,
   5582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5583         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5584         -1,
   5585         -1,
   5586     },
   5587 #endif /* chips */
   5588 
   5589 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   5590     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   5591     { /* SOC_REG_INT_HG_EH_CONTROL_BCM56560_A0r */
   5592         soc_block_list[5],
   5593         soc_genreg,
   5594         1,
   5595         0,
   5596         0xa009800,
   5597         0,
   5598         0,
   5599         1,
   5600         soc_HG_EH_CONTROL_BCM56960_A0r_fields,
   5601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5602         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5603         -1,
   5604         -1,
   5605     },
   5606 #endif /* chips */
   5607 
   5608 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   5609     { /* SOC_REG_INT_HG_EH_CONTROL_BCM56850_A0r */
   5610         soc_block_list[5],
   5611         soc_genreg,
   5612         1,
   5613         0,
   5614         0xa009800,
   5615         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5616         0,
   5617         1,
   5618         soc_HG_EH_CONTROLr_fields,
   5619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5620         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5621         -1,
   5622         -1,
   5623     },
   5624 #endif /* chips */
   5625 
   5626 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
   5627     { /* SOC_REG_INT_HG_EH_CONTROL_BCM56870_A0r */
   5628         soc_block_list[5],
   5629         soc_genreg,
   5630         1,
   5631         0,
   5632         0x4e018d00,
   5633         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5634         0,
   5635         1,
   5636         soc_HG_EH_CONTROL_BCM56960_A0r_fields,
   5637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5638         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5639         -1,
   5640         -1,
   5641         3,
   5642     },
   5643 #endif /* chips */
   5644 
   5645 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5646     { /* SOC_REG_INT_HG_EH_CONTROL_BCM56960_A0r */
   5647         soc_block_list[5],
   5648         soc_genreg,
   5649         1,
   5650         0,
   5651         0x2e001e00,
   5652         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5653         0,
   5654         1,
   5655         soc_HG_EH_CONTROL_BCM56960_A0r_fields,
   5656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5657         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5658         -1,
   5659         -1,
   5660         3,
   5661     },
   5662 #endif /* chips */
   5663 
   5664 #if defined(BCM_56970_A0)
   5665     { /* SOC_REG_INT_HG_EH_CONTROL_BCM56970_A0r */
   5666         soc_block_list[5],
   5667         soc_genreg,
   5668         1,
   5669         0,
   5670         0x52001e00,
   5671         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5672         0,
   5673         1,
   5674         soc_HG_EH_CONTROL_BCM56960_A0r_fields,
   5675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5676         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5677         -1,
   5678         -1,
   5679         3,
   5680     },
   5681 #endif /* chips */
   5682 
   5683 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   5684     defined(BCM_56334_B0) || defined(BCM_56624_A0) || \
   5685     defined(BCM_56624_B0) || defined(BCM_56680_A0) || \
   5686     defined(BCM_56680_B0)
   5687     { /* SOC_REG_INT_HG_LOOKUP_DESTINATIONr */
   5688         soc_block_list[5],
   5689         soc_genreg,
   5690         1,
   5691         0,
   5692         0x2080008,
   5693         0,
   5694         0,
   5695         2,
   5696         soc_HG_LOOKUP_DESTINATIONr_fields,
   5697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5698         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   5699         -1,
   5700         -1,
   5701     },
   5702 #endif /* chips */
   5703 
   5704 #if defined(BCM_53400_A0)
   5705     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM53400_A0r */
   5706         soc_block_list[5],
   5707         soc_genreg,
   5708         1,
   5709         0,
   5710         0xa000200,
   5711         0,
   5712         0,
   5713         2,
   5714         soc_HG_LOOKUP_DESTINATION_BCM53400_A0r_fields,
   5715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5716         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   5717         -1,
   5718         -1,
   5719     },
   5720 #endif /* chips */
   5721 
   5722 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5723     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM53570_A0r */
   5724         soc_block_list[5],
   5725         soc_genreg,
   5726         1,
   5727         0,
   5728         0xa000200,
   5729         0,
   5730         0,
   5731         2,
   5732         soc_HG_LOOKUP_DESTINATION_BCM53570_A0r_fields,
   5733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5734         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5735         -1,
   5736         -1,
   5737     },
   5738 #endif /* chips */
   5739 
   5740 #if defined(BCM_56150_A0)
   5741     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56150_A0r */
   5742         soc_block_list[5],
   5743         soc_genreg,
   5744         1,
   5745         0,
   5746         0xa000200,
   5747         0,
   5748         0,
   5749         2,
   5750         soc_HG_LOOKUP_DESTINATION_BCM56150_A0r_fields,
   5751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5752         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   5753         -1,
   5754         -1,
   5755     },
   5756 #endif /* chips */
   5757 
   5758 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
   5759     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56160_A0r */
   5760         soc_block_list[5],
   5761         soc_genreg,
   5762         1,
   5763         0,
   5764         0xa000200,
   5765         0,
   5766         0,
   5767         2,
   5768         soc_HG_LOOKUP_DESTINATION_BCM56160_A0r_fields,
   5769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5770         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   5771         -1,
   5772         -1,
   5773     },
   5774 #endif /* chips */
   5775 
   5776 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   5777     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56260_A0r */
   5778         soc_block_list[5],
   5779         soc_ppportreg,
   5780         1,
   5781         0,
   5782         0x8000200,
   5783         0,
   5784         0,
   5785         3,
   5786         soc_HG_LOOKUP_DESTINATION_BCM56560_A0r_fields,
   5787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5788         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5789         -1,
   5790         87,
   5791     },
   5792 #endif /* chips */
   5793 
   5794 #if defined(BCM_56270_A0)
   5795     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56270_A0r */
   5796         soc_block_list[5],
   5797         soc_ppportreg,
   5798         1,
   5799         0,
   5800         0x8000200,
   5801         0,
   5802         0,
   5803         3,
   5804         soc_HG_LOOKUP_DESTINATION_BCM56560_A0r_fields,
   5805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5806         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5807         -1,
   5808         90,
   5809     },
   5810 #endif /* chips */
   5811 
   5812 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5813     defined(BCM_56450_B1)
   5814     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56450_A0r */
   5815         soc_block_list[5],
   5816         soc_ppportreg,
   5817         1,
   5818         0,
   5819         0x8000200,
   5820         0,
   5821         0,
   5822         3,
   5823         soc_HG_LOOKUP_DESTINATION_BCM56640_A0r_fields,
   5824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5825         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5826         -1,
   5827         74,
   5828     },
   5829 #endif /* chips */
   5830 
   5831 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   5832     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   5833     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56560_A0r */
   5834         soc_block_list[5],
   5835         soc_portreg,
   5836         1,
   5837         0,
   5838         0x8000800,
   5839         0,
   5840         0,
   5841         3,
   5842         soc_HG_LOOKUP_DESTINATION_BCM56560_A0r_fields,
   5843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5844         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5845         -1,
   5846         -1,
   5847     },
   5848 #endif /* chips */
   5849 
   5850 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5851     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5852     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5853     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56634_A0r */
   5854         soc_block_list[5],
   5855         soc_portreg,
   5856         1,
   5857         0,
   5858         0x2000008,
   5859         0,
   5860         0,
   5861         3,
   5862         soc_HG_LOOKUP_DESTINATION_BCM56634_A0r_fields,
   5863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5864         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   5865         -1,
   5866         -1,
   5867     },
   5868 #endif /* chips */
   5869 
   5870 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5871     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56640_A0r */
   5872         soc_block_list[5],
   5873         soc_portreg,
   5874         1,
   5875         0,
   5876         0x8000200,
   5877         0,
   5878         0,
   5879         3,
   5880         soc_HG_LOOKUP_DESTINATION_BCM56640_A0r_fields,
   5881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5882         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5883         -1,
   5884         -1,
   5885     },
   5886 #endif /* chips */
   5887 
   5888 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   5889     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56820_A0r */
   5890         soc_block_list[5],
   5891         soc_genreg,
   5892         1,
   5893         0,
   5894         0x2080608,
   5895         0,
   5896         0,
   5897         2,
   5898         soc_HG_LOOKUP_DESTINATION_BCM56820_A0r_fields,
   5899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5900         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   5901         -1,
   5902         -1,
   5903     },
   5904 #endif /* chips */
   5905 
   5906 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   5907     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5908     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56840_A0r */
   5909         soc_block_list[5],
   5910         soc_portreg,
   5911         1,
   5912         0,
   5913         0x2000608,
   5914         0,
   5915         0,
   5916         3,
   5917         soc_HG_LOOKUP_DESTINATION_BCM56840_A0r_fields,
   5918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5919         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5920         -1,
   5921         -1,
   5922     },
   5923 #endif /* chips */
   5924 
   5925 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   5926     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56850_A0r */
   5927         soc_block_list[5],
   5928         soc_portreg,
   5929         1,
   5930         0,
   5931         0x8000800,
   5932         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5933         0,
   5934         3,
   5935         soc_HG_LOOKUP_DESTINATION_BCM56640_A0r_fields,
   5936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5937         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5938         -1,
   5939         -1,
   5940     },
   5941 #endif /* chips */
   5942 
   5943 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5944     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56960_A0r */
   5945         soc_block_list[5],
   5946         soc_portreg,
   5947         1,
   5948         0,
   5949         0x2c000100,
   5950         (12 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5951         0,
   5952         3,
   5953         soc_HG_LOOKUP_DESTINATION_BCM56960_A0r_fields,
   5954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5955         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5956         -1,
   5957         -1,
   5958         3,
   5959     },
   5960 #endif /* chips */
   5961 
   5962 #if defined(BCM_56970_A0)
   5963     { /* SOC_REG_INT_HG_LOOKUP_DESTINATION_BCM56970_A0r */
   5964         soc_block_list[5],
   5965         soc_portreg,
   5966         1,
   5967         0,
   5968         0x50000100,
   5969         (12 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5970         0,
   5971         3,
   5972         soc_HG_LOOKUP_DESTINATION_BCM56960_A0r_fields,
   5973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5974         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5975         -1,
   5976         -1,
   5977         3,
   5978     },
   5979 #endif /* chips */
   5980 
   5981 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
   5982     { /* SOC_REG_INT_HG_PKT_SIGNATURE_1r */
   5983         soc_block_list[5],
   5984         soc_portreg,
   5985         1,
   5986         0,
   5987         0x4c018500,
   5988         SOC_REG_FLAG_64_BITS |
   5989                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5990         0,
   5991         9,
   5992         soc_HG_PKT_SIGNATURE_1r_fields,
   5993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5994         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5995         -1,
   5996         -1,
   5997         3,
   5998     },
   5999 #endif /* chips */
   6000 
   6001 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
   6002     { /* SOC_REG_INT_HG_PKT_SIGNATURE_2r */
   6003         soc_block_list[5],
   6004         soc_portreg,
   6005         1,
   6006         0,
   6007         0x4c018600,
   6008         SOC_REG_FLAG_64_BITS |
   6009                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6010         0,
   6011         9,
   6012         soc_HG_PKT_SIGNATURE_1r_fields,
   6013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6014         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6015         -1,
   6016         -1,
   6017         3,
   6018     },
   6019 #endif /* chips */
   6020 
   6021 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
   6022     { /* SOC_REG_INT_HG_PKT_SIGNATURE_3r */
   6023         soc_block_list[5],
   6024         soc_portreg,
   6025         1,
   6026         0,
   6027         0x4c018700,
   6028         SOC_REG_FLAG_64_BITS |
   6029                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6030         0,
   6031         9,
   6032         soc_HG_PKT_SIGNATURE_1r_fields,
   6033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6034         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6035         -1,
   6036         -1,
   6037         3,
   6038     },
   6039 #endif /* chips */
   6040 
   6041 #if defined(BCM_56370_A0)
   6042     { /* SOC_REG_INT_HG_PKT_SIGNATURE_1_BCM56370_A0r */
   6043         soc_block_list[5],
   6044         soc_portreg,
   6045         1,
   6046         0,
   6047         0x4c018500,
   6048         SOC_REG_FLAG_64_BITS,
   6049         0,
   6050         9,
   6051         soc_HG_PKT_SIGNATURE_1r_fields,
   6052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6053         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6054         -1,
   6055         -1,
   6056         3,
   6057     },
   6058 #endif /* chips */
   6059 
   6060 #if defined(BCM_56370_A0)
   6061     { /* SOC_REG_INT_HG_PKT_SIGNATURE_2_BCM56370_A0r */
   6062         soc_block_list[5],
   6063         soc_portreg,
   6064         1,
   6065         0,
   6066         0x4c018600,
   6067         SOC_REG_FLAG_64_BITS,
   6068         0,
   6069         9,
   6070         soc_HG_PKT_SIGNATURE_1r_fields,
   6071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6072         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6073         -1,
   6074         -1,
   6075         3,
   6076     },
   6077 #endif /* chips */
   6078 
   6079 #if defined(BCM_56370_A0)
   6080     { /* SOC_REG_INT_HG_PKT_SIGNATURE_3_BCM56370_A0r */
   6081         soc_block_list[5],
   6082         soc_portreg,
   6083         1,
   6084         0,
   6085         0x4c018700,
   6086         SOC_REG_FLAG_64_BITS,
   6087         0,
   6088         9,
   6089         soc_HG_PKT_SIGNATURE_1r_fields,
   6090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6092         -1,
   6093         -1,
   6094         3,
   6095     },
   6096 #endif /* chips */
   6097 
   6098 #if defined(BCM_56800_A0)
   6099     { /* SOC_REG_INT_HG_TRUNK_BITMAPr */
   6100         soc_block_list[5],
   6101         soc_genreg,
   6102         8,
   6103         0,
   6104         0xe080628,
   6105         SOC_REG_FLAG_ARRAY,
   6106         0,
   6107         1,
   6108         soc_HG_TRUNK_BITMAPr_fields,
   6109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6110         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   6111         -1,
   6112         -1,
   6113     },
   6114 #endif /* chips */
   6115 
   6116 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6117     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6118     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6119     { /* SOC_REG_INT_HG_TRUNK_BITMAP_64r */
   6120         soc_block_list[5],
   6121         soc_genreg,
   6122         16,
   6123         0,
   6124         0xe080028,
   6125         SOC_REG_FLAG_64_BITS |
   6126                           SOC_REG_FLAG_ARRAY,
   6127         0,
   6128         3,
   6129         soc_HG_TRUNK_BITMAP_64r_fields,
   6130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6131         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
   6132         -1,
   6133         -1,
   6134     },
   6135 #endif /* chips */
   6136 
   6137 #if defined(BCM_53400_A0)
   6138     { /* SOC_REG_INT_HG_TRUNK_BITMAP_BCM53400_A0r */
   6139         soc_block_list[5],
   6140         soc_genreg,
   6141         8,
   6142         0,
   6143         0x42006900,
   6144         SOC_REG_FLAG_ARRAY,
   6145         0,
   6146         1,
   6147         soc_HG_TRUNK_BITMAP_BCM53400_A0r_fields,
   6148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6149         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6150         -1,
   6151         -1,
   6152     },
   6153 #endif /* chips */
   6154 
   6155 #if defined(BCM_53540_A0)
   6156     { /* SOC_REG_INT_HG_TRUNK_BITMAP_BCM53540_A0r */
   6157         soc_block_list[5],
   6158         soc_genreg,
   6159         1,
   6160         0,
   6161         0x42006900,
   6162         0,
   6163         0,
   6164         1,
   6165         soc_HG_TRUNK_BITMAP_BCM56160_A0r_fields,
   6166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6168         -1,
   6169         -1,
   6170     },
   6171 #endif /* chips */
   6172 
   6173 #if defined(BCM_56142_A0)
   6174     { /* SOC_REG_INT_HG_TRUNK_BITMAP_BCM56142_A0r */
   6175         soc_block_list[5],
   6176         soc_genreg,
   6177         2,
   6178         0,
   6179         0x1108008f,
   6180         SOC_REG_FLAG_ARRAY,
   6181         0,
   6182         1,
   6183         soc_HG_TRUNK_BITMAP_BCM56334_A0r_fields,
   6184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6185         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6186         -1,
   6187         -1,
   6188     },
   6189 #endif /* chips */
   6190 
   6191 #if defined(BCM_56150_A0)
   6192     { /* SOC_REG_INT_HG_TRUNK_BITMAP_BCM56150_A0r */
   6193         soc_block_list[5],
   6194         soc_genreg,
   6195         2,
   6196         0,
   6197         0x46006900,
   6198         SOC_REG_FLAG_ARRAY,
   6199         0,
   6200         1,
   6201         soc_HG_TRUNK_BITMAP_BCM56150_A0r_fields,
   6202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6203         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6204         -1,
   6205         -1,
   6206     },
   6207 #endif /* chips */
   6208 
   6209 #if defined(BCM_56160_A0)
   6210     { /* SOC_REG_INT_HG_TRUNK_BITMAP_BCM56160_A0r */
   6211         soc_block_list[5],
   6212         soc_genreg,
   6213         8,
   6214         0,
   6215         0x42006900,
   6216         SOC_REG_FLAG_ARRAY,
   6217         0,
   6218         1,
   6219         soc_HG_TRUNK_BITMAP_BCM56160_A0r_fields,
   6220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6221         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6222         -1,
   6223         -1,
   6224     },
   6225 #endif /* chips */
   6226 
   6227 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   6228     { /* SOC_REG_INT_HG_TRUNK_BITMAP_BCM56334_A0r */
   6229         soc_block_list[5],
   6230         soc_genreg,
   6231         2,
   6232         0,
   6233         0x11080028,
   6234         SOC_REG_FLAG_ARRAY,
   6235         0,
   6236         1,
   6237         soc_HG_TRUNK_BITMAP_BCM56334_A0r_fields,
   6238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6239         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6240         -1,
   6241         -1,
   6242     },
   6243 #endif /* chips */
   6244 
   6245 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6246     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   6247     { /* SOC_REG_INT_HG_TRUNK_BITMAP_BCM56624_A0r */
   6248         soc_block_list[5],
   6249         soc_genreg,
   6250         8,
   6251         0,
   6252         0x11080028,
   6253         SOC_REG_FLAG_ARRAY,
   6254         0,
   6255         1,
   6256         soc_HG_TRUNK_BITMAP_BCM56624_A0r_fields,
   6257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6258         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6259         -1,
   6260         -1,
   6261     },
   6262 #endif /* chips */
   6263 
   6264 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6265     { /* SOC_REG_INT_HG_TRUNK_BITMAP_BCM56820_A0r */
   6266         soc_block_list[5],
   6267         soc_genreg,
   6268         8,
   6269         0,
   6270         0xf0806b8,
   6271         SOC_REG_FLAG_ARRAY,
   6272         0,
   6273         1,
   6274         soc_HG_TRUNK_BITMAP_BCM56820_A0r_fields,
   6275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6276         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   6277         -1,
   6278         -1,
   6279     },
   6280 #endif /* chips */
   6281 
   6282 #if defined(BCM_88732_A0)
   6283     { /* SOC_REG_INT_HG_TRUNK_BITMAP_BCM88732_A0r */
   6284         soc_block_list[5],
   6285         soc_genreg,
   6286         2,
   6287         0,
   6288         0x8080075,
   6289         SOC_REG_FLAG_ARRAY,
   6290         0,
   6291         1,
   6292         soc_HG_TRUNK_BITMAP_BCM88732_A0r_fields,
   6293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6294         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   6295         -1,
   6296         -1,
   6297     },
   6298 #endif /* chips */
   6299 
   6300 #if defined(BCM_53570_A0)
   6301     { /* SOC_REG_INT_HG_TRUNK_BITMAP_HIr */
   6302         soc_block_list[5],
   6303         soc_genreg,
   6304         8,
   6305         0,
   6306         0x4200a300,
   6307         SOC_REG_FLAG_64_BITS |
   6308                           SOC_REG_FLAG_ARRAY,
   6309         0,
   6310         2,
   6311         soc_HG_TRUNK_BITMAP_HIr_fields,
   6312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6313         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   6314         -1,
   6315         -1,
   6316     },
   6317 #endif /* chips */
   6318 
   6319 #if defined(BCM_53570_B0)
   6320     { /* SOC_REG_INT_HG_TRUNK_BITMAP_HI_BCM53570_B0r */
   6321         soc_block_list[5],
   6322         soc_genreg,
   6323         8,
   6324         0,
   6325         0x4200a700,
   6326         SOC_REG_FLAG_64_BITS |
   6327                           SOC_REG_FLAG_ARRAY,
   6328         0,
   6329         2,
   6330         soc_HG_TRUNK_BITMAP_HIr_fields,
   6331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6332         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   6333         -1,
   6334         -1,
   6335     },
   6336 #endif /* chips */
   6337 
   6338 #if defined(BCM_53570_A0)
   6339     { /* SOC_REG_INT_HG_TRUNK_BITMAP_LOr */
   6340         soc_block_list[5],
   6341         soc_genreg,
   6342         8,
   6343         0,
   6344         0x42009a00,
   6345         SOC_REG_FLAG_64_BITS |
   6346                           SOC_REG_FLAG_ARRAY,
   6347         0,
   6348         1,
   6349         soc_HG_TRUNK_BITMAP_LOr_fields,
   6350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6351         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   6352         -1,
   6353         -1,
   6354     },
   6355 #endif /* chips */
   6356 
   6357 #if defined(BCM_53570_B0)
   6358     { /* SOC_REG_INT_HG_TRUNK_BITMAP_LO_BCM53570_B0r */
   6359         soc_block_list[5],
   6360         soc_genreg,
   6361         8,
   6362         0,
   6363         0x42009e00,
   6364         SOC_REG_FLAG_64_BITS |
   6365                           SOC_REG_FLAG_ARRAY,
   6366         0,
   6367         1,
   6368         soc_HG_TRUNK_BITMAP_LOr_fields,
   6369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6370         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   6371         -1,
   6372         -1,
   6373     },
   6374 #endif /* chips */
   6375 
   6376 #if defined(BCM_56800_A0)
   6377     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLEr */
   6378         soc_block_list[5],
   6379         soc_genreg,
   6380         1,
   6381         0,
   6382         0xe080638,
   6383         0,
   6384         0,
   6385         1,
   6386         soc_TDBGC0_SELECTr_fields,
   6387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6388         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   6389         -1,
   6390         -1,
   6391     },
   6392 #endif /* chips */
   6393 
   6394 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6395     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6396     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6397     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_64r */
   6398         soc_block_list[5],
   6399         soc_genreg,
   6400         1,
   6401         0,
   6402         0xe080048,
   6403         SOC_REG_FLAG_64_BITS,
   6404         0,
   6405         3,
   6406         soc_EMIRROR_CONTROL_64r_fields,
   6407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6408         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   6409         -1,
   6410         -1,
   6411     },
   6412 #endif /* chips */
   6413 
   6414 #if defined(BCM_53400_A0)
   6415     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_BCM53400_A0r */
   6416         soc_block_list[5],
   6417         soc_genreg,
   6418         1,
   6419         0,
   6420         0x42002b00,
   6421         0,
   6422         0,
   6423         1,
   6424         soc_HG_TRUNK_FAILOVER_ENABLE_BCM53400_A0r_fields,
   6425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6426         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6427         -1,
   6428         -1,
   6429     },
   6430 #endif /* chips */
   6431 
   6432 #if defined(BCM_56142_A0)
   6433     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_BCM56142_A0r */
   6434         soc_block_list[5],
   6435         soc_genreg,
   6436         1,
   6437         0,
   6438         0x11080093,
   6439         0,
   6440         0,
   6441         1,
   6442         soc_IMIRROR_BITMAPr_fields,
   6443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6444         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6445         -1,
   6446         -1,
   6447     },
   6448 #endif /* chips */
   6449 
   6450 #if defined(BCM_56150_A0)
   6451     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_BCM56150_A0r */
   6452         soc_block_list[5],
   6453         soc_genreg,
   6454         1,
   6455         0,
   6456         0x46002b00,
   6457         0,
   6458         0,
   6459         1,
   6460         soc_HG_TRUNK_FAILOVER_ENABLE_BCM56150_A0r_fields,
   6461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6462         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6463         -1,
   6464         -1,
   6465     },
   6466 #endif /* chips */
   6467 
   6468 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
   6469     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_BCM56160_A0r */
   6470         soc_block_list[5],
   6471         soc_genreg,
   6472         1,
   6473         0,
   6474         0x42002b00,
   6475         0,
   6476         0,
   6477         1,
   6478         soc_CMIC_MIIM_PROTOCOL_MAP_0_BCM88950_A0r_fields,
   6479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6480         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6481         -1,
   6482         -1,
   6483     },
   6484 #endif /* chips */
   6485 
   6486 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   6487     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_BCM56334_A0r */
   6488         soc_block_list[5],
   6489         soc_genreg,
   6490         1,
   6491         0,
   6492         0x11080038,
   6493         0,
   6494         0,
   6495         1,
   6496         soc_IMIRROR_BITMAPr_fields,
   6497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6498         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6499         -1,
   6500         -1,
   6501     },
   6502 #endif /* chips */
   6503 
   6504 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6505     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   6506     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_BCM56624_A0r */
   6507         soc_block_list[5],
   6508         soc_genreg,
   6509         1,
   6510         0,
   6511         0x11080038,
   6512         0,
   6513         0,
   6514         1,
   6515         soc_HG_TRUNK_FAILOVER_ENABLEr_fields,
   6516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6517         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6518         -1,
   6519         -1,
   6520     },
   6521 #endif /* chips */
   6522 
   6523 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6524     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_BCM56820_A0r */
   6525         soc_block_list[5],
   6526         soc_genreg,
   6527         1,
   6528         0,
   6529         0xf080686,
   6530         0,
   6531         0,
   6532         1,
   6533         soc_EMIRROR_CONTROLr_fields,
   6534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6535         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   6536         -1,
   6537         -1,
   6538     },
   6539 #endif /* chips */
   6540 
   6541 #if defined(BCM_53570_A0)
   6542     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_HIr */
   6543         soc_block_list[5],
   6544         soc_genreg,
   6545         1,
   6546         0,
   6547         0x42006000,
   6548         SOC_REG_FLAG_64_BITS,
   6549         0,
   6550         2,
   6551         soc_HG_TRUNK_FAILOVER_ENABLE_HIr_fields,
   6552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6553         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   6554         -1,
   6555         -1,
   6556     },
   6557 #endif /* chips */
   6558 
   6559 #if defined(BCM_53570_B0)
   6560     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_HI_BCM53570_B0r */
   6561         soc_block_list[5],
   6562         soc_genreg,
   6563         1,
   6564         0,
   6565         0x42006400,
   6566         SOC_REG_FLAG_64_BITS,
   6567         0,
   6568         2,
   6569         soc_HG_TRUNK_FAILOVER_ENABLE_HIr_fields,
   6570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6571         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   6572         -1,
   6573         -1,
   6574     },
   6575 #endif /* chips */
   6576 
   6577 #if defined(BCM_53570_A0)
   6578     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_LOr */
   6579         soc_block_list[5],
   6580         soc_genreg,
   6581         1,
   6582         0,
   6583         0x42005f00,
   6584         SOC_REG_FLAG_64_BITS,
   6585         0,
   6586         1,
   6587         soc_HG_TRUNK_FAILOVER_ENABLE_LOr_fields,
   6588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6589         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   6590         -1,
   6591         -1,
   6592     },
   6593 #endif /* chips */
   6594 
   6595 #if defined(BCM_53570_B0)
   6596     { /* SOC_REG_INT_HG_TRUNK_FAILOVER_ENABLE_LO_BCM53570_B0r */
   6597         soc_block_list[5],
   6598         soc_genreg,
   6599         1,
   6600         0,
   6601         0x42006300,
   6602         SOC_REG_FLAG_64_BITS,
   6603         0,
   6604         1,
   6605         soc_HG_TRUNK_FAILOVER_ENABLE_LOr_fields,
   6606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6607         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   6608         -1,
   6609         -1,
   6610     },
   6611 #endif /* chips */
   6612 
   6613 #if defined(BCM_56800_A0)
   6614     { /* SOC_REG_INT_HG_TRUNK_GROUPr */
   6615         soc_block_list[5],
   6616         soc_genreg,
   6617         8,
   6618         0,
   6619         0xe080630,
   6620         SOC_REG_FLAG_64_BITS |
   6621                           SOC_REG_FLAG_ARRAY,
   6622         0,
   6623         11,
   6624         soc_HG_TRUNK_GROUPr_fields,
   6625         SOC_RESET_VAL_DEC(0x0ffffff8, 0x00007fff)
   6626         SOC_RESET_MASK_DEC(0xffffffff, 0x0003ffff)
   6627         -1,
   6628         -1,
   6629     },
   6630 #endif /* chips */
   6631 
   6632 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
   6633     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM53400_A0r */
   6634         soc_block_list[5],
   6635         soc_genreg,
   6636         8,
   6637         0,
   6638         0x42007100,
   6639         SOC_REG_FLAG_64_BITS |
   6640                           SOC_REG_FLAG_ARRAY,
   6641         0,
   6642         10,
   6643         soc_HG_TRUNK_GROUP_BCM53400_A0r_fields,
   6644         SOC_RESET_VAL_DEC(0x01084210, 0x00010842)
   6645         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
   6646         -1,
   6647         -1,
   6648     },
   6649 #endif /* chips */
   6650 
   6651 #if defined(BCM_53540_A0)
   6652     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM53540_A0r */
   6653         soc_block_list[5],
   6654         soc_genreg,
   6655         1,
   6656         0,
   6657         0x42007100,
   6658         SOC_REG_FLAG_64_BITS,
   6659         0,
   6660         7,
   6661         soc_HG_TRUNK_GROUP_BCM53540_A0r_fields,
   6662         SOC_RESET_VAL_DEC(0x01084210, 0x00000000)
   6663         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
   6664         -1,
   6665         -1,
   6666     },
   6667 #endif /* chips */
   6668 
   6669 #if defined(BCM_53570_A0)
   6670     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM53570_A0r */
   6671         soc_block_list[5],
   6672         soc_genreg,
   6673         8,
   6674         0,
   6675         0x4200ab00,
   6676         SOC_REG_FLAG_64_BITS |
   6677                           SOC_REG_FLAG_ARRAY,
   6678         0,
   6679         10,
   6680         soc_HG_TRUNK_GROUP_BCM53570_A0r_fields,
   6681         SOC_RESET_VAL_DEC(0x02040810, 0x00408102)
   6682         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
   6683         -1,
   6684         -1,
   6685     },
   6686 #endif /* chips */
   6687 
   6688 #if defined(BCM_53570_B0)
   6689     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM53570_B0r */
   6690         soc_block_list[5],
   6691         soc_genreg,
   6692         8,
   6693         0,
   6694         0x4200af00,
   6695         SOC_REG_FLAG_64_BITS |
   6696                           SOC_REG_FLAG_ARRAY,
   6697         0,
   6698         11,
   6699         soc_HG_TRUNK_GROUP_BCM53570_B0r_fields,
   6700         SOC_RESET_VAL_DEC(0x02040810, 0x00408102)
   6701         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
   6702         -1,
   6703         -1,
   6704     },
   6705 #endif /* chips */
   6706 
   6707 #if defined(BCM_56142_A0)
   6708     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM56142_A0r */
   6709         soc_block_list[5],
   6710         soc_genreg,
   6711         2,
   6712         0,
   6713         0x11080091,
   6714         SOC_REG_FLAG_ARRAY,
   6715         0,
   6716         5,
   6717         soc_HG_TRUNK_GROUP_BCM56142_A0r_fields,
   6718         SOC_RESET_VAL_DEC(0x006b5ad0, 0x00000000)
   6719         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   6720         -1,
   6721         -1,
   6722     },
   6723 #endif /* chips */
   6724 
   6725 #if defined(BCM_56150_A0)
   6726     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM56150_A0r */
   6727         soc_block_list[5],
   6728         soc_genreg,
   6729         2,
   6730         0,
   6731         0x46006b00,
   6732         SOC_REG_FLAG_ARRAY,
   6733         0,
   6734         5,
   6735         soc_HG_TRUNK_GROUP_BCM56150_A0r_fields,
   6736         SOC_RESET_VAL_DEC(0x006b5ad0, 0x00000000)
   6737         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   6738         -1,
   6739         -1,
   6740     },
   6741 #endif /* chips */
   6742 
   6743 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   6744     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM56334_A0r */
   6745         soc_block_list[5],
   6746         soc_genreg,
   6747         2,
   6748         0,
   6749         0x11080030,
   6750         SOC_REG_FLAG_ARRAY,
   6751         0,
   6752         7,
   6753         soc_HG_TRUNK_GROUP_BCM56334_A0r_fields,
   6754         SOC_RESET_VAL_DEC(0x006b5ad0, 0x00000000)
   6755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6756         -1,
   6757         -1,
   6758     },
   6759 #endif /* chips */
   6760 
   6761 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6762     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   6763     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM56624_A0r */
   6764         soc_block_list[5],
   6765         soc_genreg,
   6766         8,
   6767         0,
   6768         0x11080030,
   6769         SOC_REG_FLAG_64_BITS |
   6770                           SOC_REG_FLAG_ARRAY,
   6771         0,
   6772         11,
   6773         soc_HG_TRUNK_GROUP_BCM56624_A0r_fields,
   6774         SOC_RESET_VAL_DEC(0x07fffff8, 0x00ffffff)
   6775         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
   6776         -1,
   6777         -1,
   6778     },
   6779 #endif /* chips */
   6780 
   6781 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6782     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6783     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6784     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM56634_A0r */
   6785         soc_block_list[5],
   6786         soc_genreg,
   6787         16,
   6788         0,
   6789         0xe080038,
   6790         SOC_REG_FLAG_64_BITS |
   6791                           SOC_REG_FLAG_ARRAY,
   6792         0,
   6793         11,
   6794         soc_HG_TRUNK_GROUP_BCM56624_A0r_fields,
   6795         SOC_RESET_VAL_DEC(0x07fffff8, 0x00ffffff)
   6796         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
   6797         -1,
   6798         -1,
   6799     },
   6800 #endif /* chips */
   6801 
   6802 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6803     { /* SOC_REG_INT_HG_TRUNK_GROUP_BCM56820_A0r */
   6804         soc_block_list[5],
   6805         soc_genreg,
   6806         8,
   6807         0,
   6808         0xf0806c0,
   6809         SOC_REG_FLAG_64_BITS |
   6810                           SOC_REG_FLAG_ARRAY,
   6811         0,
   6812         11,
   6813         soc_HG_TRUNK_GROUP_BCM56820_A0r_fields,
   6814         SOC_RESET_VAL_DEC(0x0ffffff8, 0x00007fff)
   6815         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
   6816         -1,
   6817         -1,
   6818     },
   6819 #endif /* chips */
   6820 
   6821 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6822     { /* SOC_REG_INT_HG_TRUNK_GROUP_HIr */
   6823         soc_block_list[5],
   6824         soc_genreg,
   6825         8,
   6826         0,
   6827         0xf0806c8,
   6828         SOC_REG_FLAG_64_BITS |
   6829                           SOC_REG_FLAG_ARRAY,
   6830         0,
   6831         10,
   6832         soc_HG_TRUNK_GROUP_HIr_fields,
   6833         SOC_RESET_VAL_DEC(0x0ffffff8, 0x00007fff)
   6834         SOC_RESET_MASK_DEC(0xffffffff, 0x00007fff)
   6835         -1,
   6836         -1,
   6837     },
   6838 #endif /* chips */
   6839 
   6840 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6841     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEEDr */
   6842         soc_block_list[5],
   6843         soc_genreg,
   6844         1,
   6845         0,
   6846         0x52000a00,
   6847         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6848         0,
   6849         1,
   6850         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   6851         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   6852         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6853         -1,
   6854         -1,
   6855         3,
   6856     },
   6857 #endif /* chips */
   6858 
   6859 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   6860     defined(BCM_56870_A0)
   6861     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_BCM56870_A0r */
   6862         soc_block_list[5],
   6863         soc_genreg,
   6864         1,
   6865         0,
   6866         0x82000a00,
   6867         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6868         0,
   6869         1,
   6870         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   6871         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   6872         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6873         -1,
   6874         -1,
   6875         3,
   6876     },
   6877 #endif /* chips */
   6878 
   6879 #if defined(BCM_56970_A0)
   6880     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_BCM56970_A0r */
   6881         soc_block_list[5],
   6882         soc_genreg,
   6883         1,
   6884         0,
   6885         0x92000a00,
   6886         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6887         0,
   6888         1,
   6889         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   6890         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   6891         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6892         -1,
   6893         -1,
   6894         3,
   6895     },
   6896 #endif /* chips */
   6897 
   6898 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6899     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE0r */
   6900         soc_block_list[5],
   6901         soc_genreg,
   6902         1,
   6903         0,
   6904         0x52000a00,
   6905         0,
   6906         0,
   6907         1,
   6908         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   6909         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   6910         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6911         -1,
   6912         -1,
   6913         3,
   6914     },
   6915 #endif /* chips */
   6916 
   6917 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6918     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE1r */
   6919         soc_block_list[5],
   6920         soc_genreg,
   6921         1,
   6922         0,
   6923         0x52000a00,
   6924         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6925         0,
   6926         1,
   6927         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   6928         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   6929         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6930         -1,
   6931         -1,
   6932         3,
   6933     },
   6934 #endif /* chips */
   6935 
   6936 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6937     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE2r */
   6938         soc_block_list[5],
   6939         soc_genreg,
   6940         1,
   6941         0,
   6942         0x52000a00,
   6943         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6944         0,
   6945         1,
   6946         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   6947         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   6948         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6949         -1,
   6950         -1,
   6951         3,
   6952     },
   6953 #endif /* chips */
   6954 
   6955 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6956     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE3r */
   6957         soc_block_list[5],
   6958         soc_genreg,
   6959         1,
   6960         0,
   6961         0x52000a00,
   6962         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6963         0,
   6964         1,
   6965         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   6966         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   6967         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6968         -1,
   6969         -1,
   6970         3,
   6971     },
   6972 #endif /* chips */
   6973 
   6974 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   6975     defined(BCM_56870_A0)
   6976     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE0_BCM56870_A0r */
   6977         soc_block_list[5],
   6978         soc_genreg,
   6979         1,
   6980         0,
   6981         0x82000a00,
   6982         0,
   6983         0,
   6984         1,
   6985         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   6986         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   6987         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   6988         -1,
   6989         -1,
   6990         3,
   6991     },
   6992 #endif /* chips */
   6993 
   6994 #if defined(BCM_56970_A0)
   6995     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE0_BCM56970_A0r */
   6996         soc_block_list[5],
   6997         soc_genreg,
   6998         1,
   6999         0,
   7000         0x92000a00,
   7001         0,
   7002         0,
   7003         1,
   7004         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   7005         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   7006         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7007         -1,
   7008         -1,
   7009         3,
   7010     },
   7011 #endif /* chips */
   7012 
   7013 #if defined(BCM_56870_A0)
   7014     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE1_BCM56870_A0r */
   7015         soc_block_list[5],
   7016         soc_genreg,
   7017         1,
   7018         0,
   7019         0x82000a00,
   7020         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7021         0,
   7022         1,
   7023         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   7024         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   7025         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7026         -1,
   7027         -1,
   7028         3,
   7029     },
   7030 #endif /* chips */
   7031 
   7032 #if defined(BCM_56970_A0)
   7033     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE1_BCM56970_A0r */
   7034         soc_block_list[5],
   7035         soc_genreg,
   7036         1,
   7037         0,
   7038         0x92000a00,
   7039         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7040         0,
   7041         1,
   7042         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   7043         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   7044         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7045         -1,
   7046         -1,
   7047         3,
   7048     },
   7049 #endif /* chips */
   7050 
   7051 #if defined(BCM_56970_A0)
   7052     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE2_BCM56970_A0r */
   7053         soc_block_list[5],
   7054         soc_genreg,
   7055         1,
   7056         0,
   7057         0x92000a00,
   7058         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7059         0,
   7060         1,
   7061         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   7062         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   7063         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7064         -1,
   7065         -1,
   7066         3,
   7067     },
   7068 #endif /* chips */
   7069 
   7070 #if defined(BCM_56970_A0)
   7071     { /* SOC_REG_INT_HG_TRUNK_RAND_LB_SEED_PIPE3_BCM56970_A0r */
   7072         soc_block_list[5],
   7073         soc_genreg,
   7074         1,
   7075         0,
   7076         0x92000a00,
   7077         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7078         0,
   7079         1,
   7080         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
   7081         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   7082         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7083         -1,
   7084         -1,
   7085         3,
   7086     },
   7087 #endif /* chips */
   7088 
   7089 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7090     defined(BCM_56450_B1)
   7091     { /* SOC_REG_INT_HIGH_SPEED_PORT_BMP_0r */
   7092         soc_block_list[4],
   7093         soc_genreg,
   7094         1,
   7095         0,
   7096         0x32000b00,
   7097         0,
   7098         0,
   7099         1,
   7100         soc_HIGH_SPEED_PORT_BMP_0r_fields,
   7101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7102         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7103         -1,
   7104         -1,
   7105     },
   7106 #endif /* chips */
   7107 
   7108 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7109     defined(BCM_56450_B1)
   7110     { /* SOC_REG_INT_HIGH_SPEED_PORT_BMP_1r */
   7111         soc_block_list[4],
   7112         soc_genreg,
   7113         1,
   7114         0,
   7115         0x32000c00,
   7116         0,
   7117         0,
   7118         1,
   7119         soc_HIGH_SPEED_PORT_BMP_1r_fields,
   7120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7121         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7122         -1,
   7123         -1,
   7124     },
   7125 #endif /* chips */
   7126 
   7127 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   7128     { /* SOC_REG_INT_HIGH_SPEED_PORT_BMP_0_BCM56260_A0r */
   7129         soc_block_list[4],
   7130         soc_genreg,
   7131         1,
   7132         0,
   7133         0x32000900,
   7134         0,
   7135         0,
   7136         1,
   7137         soc_HIGH_SPEED_PORT_BMP_0_BCM56260_A0r_fields,
   7138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7139         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   7140         -1,
   7141         -1,
   7142     },
   7143 #endif /* chips */
   7144 
   7145 #if defined(BCM_53570_B0)
   7146     { /* SOC_REG_INT_HIGIGPORTBITMAP_0r */
   7147         soc_block_list[4],
   7148         soc_genreg,
   7149         1,
   7150         0,
   7151         0x2081800,
   7152         0,
   7153         0,
   7154         1,
   7155         soc_HIGIGPORTBITMAP_0r_fields,
   7156         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   7157         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7158         -1,
   7159         -1,
   7160     },
   7161 #endif /* chips */
   7162 
   7163 #if defined(BCM_53570_B0)
   7164     { /* SOC_REG_INT_HIGIGPORTBITMAP_1r */
   7165         soc_block_list[4],
   7166         soc_genreg,
   7167         1,
   7168         0,
   7169         0x2081900,
   7170         0,
   7171         0,
   7172         1,
   7173         soc_HIGIGPORTBITMAP_0r_fields,
   7174         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   7175         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7176         -1,
   7177         -1,
   7178     },
   7179 #endif /* chips */
   7180 
   7181 #if defined(BCM_53570_B0)
   7182     { /* SOC_REG_INT_HIGIGPORTBITMAP_2r */
   7183         soc_block_list[4],
   7184         soc_genreg,
   7185         1,
   7186         0,
   7187         0x2081a00,
   7188         0,
   7189         0,
   7190         1,
   7191         soc_HIGIGPORTBITMAP_2r_fields,
   7192         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   7193         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   7194         -1,
   7195         -1,
   7196     },
   7197 #endif /* chips */
   7198 
   7199 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
   7200     { /* SOC_REG_INT_HIGIG_AUX_HDR_BITMAP_PRIORITY_MASKr */
   7201         soc_block_list[5],
   7202         soc_genreg,
   7203         1,
   7204         0,
   7205         0x86008a00,
   7206         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7207         0,
   7208         1,
   7209         soc_VRF_MASK_BCM56560_A0r_fields,
   7210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7211         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   7212         -1,
   7213         -1,
   7214         3,
   7215     },
   7216 #endif /* chips */
   7217 
   7218 #if defined(BCM_56370_A0)
   7219     { /* SOC_REG_INT_HIGIG_AUX_HDR_BITMAP_PRIORITY_MASK_BCM56370_A0r */
   7220         soc_block_list[5],
   7221         soc_genreg,
   7222         1,
   7223         0,
   7224         0x86009c00,
   7225         0,
   7226         0,
   7227         1,
   7228         soc_VRF_MASK_BCM56560_A0r_fields,
   7229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7230         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   7231         -1,
   7232         -1,
   7233         3,
   7234     },
   7235 #endif /* chips */
   7236 
   7237 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   7238     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   7239     { /* SOC_REG_INT_HIGIG_BITMAPr */
   7240         soc_block_list[5],
   7241         soc_genreg,
   7242         1,
   7243         0,
   7244         0x11080054,
   7245         0,
   7246         0,
   7247         1,
   7248         soc_HG_TRUNK_FAILOVER_ENABLEr_fields,
   7249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7250         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7251         -1,
   7252         -1,
   7253     },
   7254 #endif /* chips */
   7255 
   7256 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   7257     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   7258     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   7259     { /* SOC_REG_INT_HIGIG_BITMAP_64r */
   7260         soc_block_list[5],
   7261         soc_genreg,
   7262         1,
   7263         0,
   7264         0xe080064,
   7265         SOC_REG_FLAG_64_BITS,
   7266         0,
   7267         1,
   7268         soc_HIGIG_BITMAP_64r_fields,
   7269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7270         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   7271         -1,
   7272         -1,
   7273     },
   7274 #endif /* chips */
   7275 
   7276 #if defined(BCM_53400_A0)
   7277     { /* SOC_REG_INT_HIGIG_BITMAP_BCM53400_A0r */
   7278         soc_block_list[5],
   7279         soc_genreg,
   7280         1,
   7281         0,
   7282         0x42003300,
   7283         0,
   7284         0,
   7285         1,
   7286         soc_HG_TRUNK_FAILOVER_ENABLE_BCM53400_A0r_fields,
   7287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7288         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   7289         -1,
   7290         -1,
   7291     },
   7292 #endif /* chips */
   7293 
   7294 #if defined(BCM_56142_A0)
   7295     { /* SOC_REG_INT_HIGIG_BITMAP_BCM56142_A0r */
   7296         soc_block_list[5],
   7297         soc_genreg,
   7298         1,
   7299         0,
   7300         0x1108009f,
   7301         0,
   7302         0,
   7303         1,
   7304         soc_IMIRROR_BITMAPr_fields,
   7305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7306         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7307         -1,
   7308         -1,
   7309     },
   7310 #endif /* chips */
   7311 
   7312 #if defined(BCM_56150_A0)
   7313     { /* SOC_REG_INT_HIGIG_BITMAP_BCM56150_A0r */
   7314         soc_block_list[5],
   7315         soc_genreg,
   7316         1,
   7317         0,
   7318         0x46003300,
   7319         0,
   7320         0,
   7321         1,
   7322         soc_HG_TRUNK_FAILOVER_ENABLE_BCM56150_A0r_fields,
   7323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7324         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7325         -1,
   7326         -1,
   7327     },
   7328 #endif /* chips */
   7329 
   7330 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
   7331     { /* SOC_REG_INT_HIGIG_BITMAP_BCM56160_A0r */
   7332         soc_block_list[5],
   7333         soc_genreg,
   7334         1,
   7335         0,
   7336         0x42003300,
   7337         0,
   7338         0,
   7339         1,
   7340         soc_CMIC_MIIM_PROTOCOL_MAP_0_BCM88950_A0r_fields,
   7341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7342         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7343         -1,
   7344         -1,
   7345     },
   7346 #endif /* chips */
   7347 
   7348 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   7349     { /* SOC_REG_INT_HIGIG_BITMAP_BCM56334_A0r */
   7350         soc_block_list[5],
   7351         soc_genreg,
   7352         1,
   7353         0,
   7354         0x11080055,
   7355         0,
   7356         0,
   7357         1,
   7358         soc_IMIRROR_BITMAPr_fields,
   7359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7360         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7361         -1,
   7362         -1,
   7363     },
   7364 #endif /* chips */
   7365 
   7366 #if defined(BCM_53570_A0)
   7367     { /* SOC_REG_INT_HIGIG_BITMAP_HIr */
   7368         soc_block_list[5],
   7369         soc_genreg,
   7370         1,
   7371         0,
   7372         0x42006b00,
   7373         SOC_REG_FLAG_64_BITS,
   7374         0,
   7375         2,
   7376         soc_HG_TRUNK_FAILOVER_ENABLE_HIr_fields,
   7377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7378         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7379         -1,
   7380         -1,
   7381     },
   7382 #endif /* chips */
   7383 
   7384 #if defined(BCM_53570_B0)
   7385     { /* SOC_REG_INT_HIGIG_BITMAP_HI_BCM53570_B0r */
   7386         soc_block_list[5],
   7387         soc_genreg,
   7388         1,
   7389         0,
   7390         0x42006f00,
   7391         SOC_REG_FLAG_64_BITS,
   7392         0,
   7393         2,
   7394         soc_HG_TRUNK_FAILOVER_ENABLE_HIr_fields,
   7395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7396         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7397         -1,
   7398         -1,
   7399     },
   7400 #endif /* chips */
   7401 
   7402 #if defined(BCM_53570_A0)
   7403     { /* SOC_REG_INT_HIGIG_BITMAP_LOr */
   7404         soc_block_list[5],
   7405         soc_genreg,
   7406         1,
   7407         0,
   7408         0x42006a00,
   7409         SOC_REG_FLAG_64_BITS,
   7410         0,
   7411         1,
   7412         soc_HG_TRUNK_FAILOVER_ENABLE_LOr_fields,
   7413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7414         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7415         -1,
   7416         -1,
   7417     },
   7418 #endif /* chips */
   7419 
   7420 #if defined(BCM_53570_B0)
   7421     { /* SOC_REG_INT_HIGIG_BITMAP_LO_BCM53570_B0r */
   7422         soc_block_list[5],
   7423         soc_genreg,
   7424         1,
   7425         0,
   7426         0x42006e00,
   7427         SOC_REG_FLAG_64_BITS,
   7428         0,
   7429         1,
   7430         soc_HG_TRUNK_FAILOVER_ENABLE_LOr_fields,
   7431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7432         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7433         -1,
   7434         -1,
   7435     },
   7436 #endif /* chips */
   7437 
   7438 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   7439     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   7440     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROLr */
   7441         soc_block_list[5],
   7442         soc_genreg,
   7443         1,
   7444         0,
   7445         0xe080109,
   7446         0,
   7447         0,
   7448         11,
   7449         soc_HIGIG_TRUNK_CONTROLr_fields,
   7450         SOC_RESET_VAL_DEC(0x000f0000, 0x00000000)
   7451         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   7452         -1,
   7453         -1,
   7454     },
   7455 #endif /* chips */
   7456 
   7457 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   7458     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   7459     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   7460     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_64r */
   7461         soc_block_list[5],
   7462         soc_genreg,
   7463         1,
   7464         0,
   7465         0xe08001f,
   7466         SOC_REG_FLAG_64_BITS,
   7467         0,
   7468         3,
   7469         soc_HIGIG_TRUNK_CONTROL_64r_fields,
   7470         SOC_RESET_VAL_DEC(0xffffffff, 0x003fffff)
   7471         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   7472         -1,
   7473         -1,
   7474     },
   7475 #endif /* chips */
   7476 
   7477 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   7478     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM53314_A0r */
   7479         soc_block_list[5],
   7480         soc_genreg,
   7481         1,
   7482         0,
   7483         0xf08010e,
   7484         0,
   7485         0,
   7486         11,
   7487         soc_HIGIG_TRUNK_CONTROL_BCM53314_A0r_fields,
   7488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7490         -1,
   7491         -1,
   7492     },
   7493 #endif /* chips */
   7494 
   7495 #if defined(BCM_53400_A0)
   7496     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM53400_A0r */
   7497         soc_block_list[5],
   7498         soc_genreg,
   7499         1,
   7500         0,
   7501         0x42002600,
   7502         0,
   7503         0,
   7504         1,
   7505         soc_HIGIG_TRUNK_CONTROL_BCM53400_A0r_fields,
   7506         SOC_RESET_VAL_DEC(0x3ffffffc, 0x00000000)
   7507         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   7508         -1,
   7509         -1,
   7510     },
   7511 #endif /* chips */
   7512 
   7513 #if defined(BCM_56142_A0)
   7514     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM56142_A0r */
   7515         soc_block_list[5],
   7516         soc_genreg,
   7517         1,
   7518         0,
   7519         0x1108008a,
   7520         0,
   7521         0,
   7522         1,
   7523         soc_HIGIG_TRUNK_CONTROL_BCM56334_A0r_fields,
   7524         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   7525         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7526         -1,
   7527         -1,
   7528     },
   7529 #endif /* chips */
   7530 
   7531 #if defined(BCM_56150_A0)
   7532     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM56150_A0r */
   7533         soc_block_list[5],
   7534         soc_genreg,
   7535         1,
   7536         0,
   7537         0x46002600,
   7538         0,
   7539         0,
   7540         1,
   7541         soc_HIGIG_TRUNK_CONTROL_BCM56150_A0r_fields,
   7542         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   7543         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7544         -1,
   7545         -1,
   7546     },
   7547 #endif /* chips */
   7548 
   7549 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
   7550     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM56160_A0r */
   7551         soc_block_list[5],
   7552         soc_genreg,
   7553         1,
   7554         0,
   7555         0x42002600,
   7556         0,
   7557         0,
   7558         1,
   7559         soc_HIGIG_TRUNK_CONTROL_BCM56160_A0r_fields,
   7560         SOC_RESET_VAL_DEC(0xfffffffc, 0x00000000)
   7561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7562         -1,
   7563         -1,
   7564     },
   7565 #endif /* chips */
   7566 
   7567 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   7568     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM56224_A0r */
   7569         soc_block_list[5],
   7570         soc_genreg,
   7571         1,
   7572         0,
   7573         0xf08010e,
   7574         0,
   7575         0,
   7576         11,
   7577         soc_HIGIG_TRUNK_CONTROL_BCM56224_A0r_fields,
   7578         SOC_RESET_VAL_DEC(0x03f00000, 0x00000000)
   7579         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   7580         -1,
   7581         -1,
   7582     },
   7583 #endif /* chips */
   7584 
   7585 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   7586     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM56334_A0r */
   7587         soc_block_list[5],
   7588         soc_genreg,
   7589         1,
   7590         0,
   7591         0x1108001f,
   7592         0,
   7593         0,
   7594         1,
   7595         soc_HIGIG_TRUNK_CONTROL_BCM56334_A0r_fields,
   7596         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
   7597         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7598         -1,
   7599         -1,
   7600     },
   7601 #endif /* chips */
   7602 
   7603 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   7604     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   7605     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM56624_A0r */
   7606         soc_block_list[5],
   7607         soc_genreg,
   7608         1,
   7609         0,
   7610         0x1108001f,
   7611         0,
   7612         0,
   7613         1,
   7614         soc_HIGIG_TRUNK_CONTROL_BCM56624_A0r_fields,
   7615         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7616         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7617         -1,
   7618         -1,
   7619     },
   7620 #endif /* chips */
   7621 
   7622 #if defined(BCM_56800_A0)
   7623     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM56800_A0r */
   7624         soc_block_list[5],
   7625         soc_genreg,
   7626         1,
   7627         0,
   7628         0xe080613,
   7629         0,
   7630         0,
   7631         1,
   7632         soc_HIGIG_TRUNK_CONTROL_BCM56800_A0r_fields,
   7633         SOC_RESET_VAL_DEC(0x001fffff, 0x00000000)
   7634         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   7635         -1,
   7636         -1,
   7637     },
   7638 #endif /* chips */
   7639 
   7640 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   7641     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_BCM56820_A0r */
   7642         soc_block_list[5],
   7643         soc_genreg,
   7644         1,
   7645         0,
   7646         0xf08063a,
   7647         0,
   7648         0,
   7649         1,
   7650         soc_HIGIG_TRUNK_CONTROL_BCM56820_A0r_fields,
   7651         SOC_RESET_VAL_DEC(0x1fffffff, 0x00000000)
   7652         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   7653         -1,
   7654         -1,
   7655     },
   7656 #endif /* chips */
   7657 
   7658 #if defined(BCM_53570_A0)
   7659     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_HIr */
   7660         soc_block_list[5],
   7661         soc_genreg,
   7662         1,
   7663         0,
   7664         0x42005800,
   7665         SOC_REG_FLAG_64_BITS,
   7666         0,
   7667         2,
   7668         soc_HIGIG_TRUNK_CONTROL_HIr_fields,
   7669         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   7670         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7671         -1,
   7672         -1,
   7673     },
   7674 #endif /* chips */
   7675 
   7676 #if defined(BCM_53570_B0)
   7677     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_HI_BCM53570_B0r */
   7678         soc_block_list[5],
   7679         soc_genreg,
   7680         1,
   7681         0,
   7682         0x42005c00,
   7683         SOC_REG_FLAG_64_BITS,
   7684         0,
   7685         2,
   7686         soc_HIGIG_TRUNK_CONTROL_HIr_fields,
   7687         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   7688         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7689         -1,
   7690         -1,
   7691     },
   7692 #endif /* chips */
   7693 
   7694 #if defined(BCM_53570_A0)
   7695     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_LOr */
   7696         soc_block_list[5],
   7697         soc_genreg,
   7698         1,
   7699         0,
   7700         0x42005700,
   7701         SOC_REG_FLAG_64_BITS,
   7702         0,
   7703         3,
   7704         soc_HIGIG_TRUNK_CONTROL_LOr_fields,
   7705         SOC_RESET_VAL_DEC(0xfffffffc, 0xffffffff)
   7706         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7707         -1,
   7708         -1,
   7709     },
   7710 #endif /* chips */
   7711 
   7712 #if defined(BCM_53570_B0)
   7713     { /* SOC_REG_INT_HIGIG_TRUNK_CONTROL_LO_BCM53570_B0r */
   7714         soc_block_list[5],
   7715         soc_genreg,
   7716         1,
   7717         0,
   7718         0x42005b00,
   7719         SOC_REG_FLAG_64_BITS,
   7720         0,
   7721         3,
   7722         soc_HIGIG_TRUNK_CONTROL_LOr_fields,
   7723         SOC_RESET_VAL_DEC(0xfffffffc, 0xffffffff)
   7724         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7725         -1,
   7726         -1,
   7727     },
   7728 #endif /* chips */
   7729 
   7730 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   7731     defined(BCM_56504_B0)
   7732     { /* SOC_REG_INT_HIGIG_TRUNK_GROUPr */
   7733         soc_block_list[5],
   7734         soc_genreg,
   7735         1,
   7736         0,
   7737         0xe080108,
   7738         0,
   7739         0,
   7740         10,
   7741         soc_HIGIG_TRUNK_GROUPr_fields,
   7742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7743         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
   7744         -1,
   7745         -1,
   7746     },
   7747 #endif /* chips */
   7748 
   7749 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   7750     { /* SOC_REG_INT_HIGIG_TRUNK_GROUP_BCM53314_A0r */
   7751         soc_block_list[5],
   7752         soc_genreg,
   7753         1,
   7754         0,
   7755         0xf08010d,
   7756         0,
   7757         0,
   7758         10,
   7759         soc_HIGIG_TRUNK_GROUP_BCM53314_A0r_fields,
   7760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7762         -1,
   7763         -1,
   7764     },
   7765 #endif /* chips */
   7766 
   7767 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   7768     { /* SOC_REG_INT_HIGIG_TRUNK_GROUP_BCM56224_A0r */
   7769         soc_block_list[5],
   7770         soc_genreg,
   7771         1,
   7772         0,
   7773         0xf08010d,
   7774         0,
   7775         0,
   7776         10,
   7777         soc_HIGIG_TRUNK_GROUP_BCM56224_A0r_fields,
   7778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7779         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   7780         -1,
   7781         -1,
   7782     },
   7783 #endif /* chips */
   7784 
   7785 #if defined(BCM_56514_A0)
   7786     { /* SOC_REG_INT_HIGIG_TRUNK_GROUP_BCM56514_A0r */
   7787         soc_block_list[5],
   7788         soc_genreg,
   7789         1,
   7790         0,
   7791         0xe080108,
   7792         0,
   7793         0,
   7794         12,
   7795         soc_HIGIG_TRUNK_GROUP_BCM56514_A0r_fields,
   7796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7797         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   7798         -1,
   7799         -1,
   7800     },
   7801 #endif /* chips */
   7802 
   7803 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   7804     { /* SOC_REG_INT_HOLCOS0MINXQCNTr */
   7805         soc_block_list[4],
   7806         soc_portreg,
   7807         1,
   7808         0,
   7809         0x17,
   7810         0,
   7811         0,
   7812         1,
   7813         soc_HOLCOS0MINXQCNTr_fields,
   7814         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
   7815         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   7816         -1,
   7817         -1,
   7818     },
   7819 #endif /* chips */
   7820 
   7821 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   7822     { /* SOC_REG_INT_HOLCOS1MINXQCNTr */
   7823         soc_block_list[4],
   7824         soc_portreg,
   7825         1,
   7826         0,
   7827         0x18,
   7828         0,
   7829         0,
   7830         1,
   7831         soc_HOLCOS1MINXQCNTr_fields,
   7832         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
   7833         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   7834         -1,
   7835         -1,
   7836     },
   7837 #endif /* chips */
   7838 
   7839 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   7840     { /* SOC_REG_INT_HOLCOS2MINXQCNTr */
   7841         soc_block_list[4],
   7842         soc_portreg,
   7843         1,
   7844         0,
   7845         0x19,
   7846         0,
   7847         0,
   7848         1,
   7849         soc_HOLCOS2MINXQCNTr_fields,
   7850         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   7851         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   7852         -1,
   7853         -1,
   7854     },
   7855 #endif /* chips */
   7856 
   7857 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   7858     { /* SOC_REG_INT_HOLCOS3MINXQCNTr */
   7859         soc_block_list[4],
   7860         soc_portreg,
   7861         1,
   7862         0,
   7863         0x1a,
   7864         0,
   7865         0,
   7866         1,
   7867         soc_HOLCOS2MINXQCNTr_fields,
   7868         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   7869         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   7870         -1,
   7871         -1,
   7872     },
   7873 #endif /* chips */
   7874 
   7875 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   7876     { /* SOC_REG_INT_HOLCOSCELLMAXLIMITr */
   7877         soc_block_list[4],
   7878         soc_portreg,
   7879         8,
   7880         0,
   7881         0xa5,
   7882         SOC_REG_FLAG_ARRAY,
   7883         0,
   7884         2,
   7885         soc_HOLCOSCELLMAXLIMITr_fields,
   7886         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
   7887         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   7888         -1,
   7889         -1,
   7890     },
   7891 #endif /* chips */
   7892 
   7893 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   7894     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_BCM53314_A0r */
   7895         soc_block_list[4],
   7896         soc_portreg,
   7897         4,
   7898         0,
   7899         0xa5,
   7900         SOC_REG_FLAG_ARRAY,
   7901         0,
   7902         2,
   7903         soc_HOLCOSCELLMAXLIMIT_BCM53314_A0r_fields,
   7904         SOC_RESET_VAL_DEC(0x00954960, 0x00000000)
   7905         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7906         -1,
   7907         -1,
   7908     },
   7909 #endif /* chips */
   7910 
   7911 #if defined(BCM_53400_A0)
   7912     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_BCM53400_A0r */
   7913         soc_block_list[4],
   7914         soc_portreg,
   7915         8,
   7916         0,
   7917         0xed00,
   7918         SOC_REG_FLAG_ARRAY,
   7919         0,
   7920         2,
   7921         soc_HOLCOSCELLMAXLIMIT_BCM53400_A0r_fields,
   7922         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
   7923         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   7924         -1,
   7925         79,
   7926     },
   7927 #endif /* chips */
   7928 
   7929 #if defined(BCM_53540_A0)
   7930     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_BCM53540_A0r */
   7931         soc_block_list[4],
   7932         soc_portreg,
   7933         8,
   7934         0,
   7935         0xf800,
   7936         SOC_REG_FLAG_ARRAY,
   7937         0,
   7938         2,
   7939         soc_HOLCOSCELLMAXLIMIT_BCM53540_A0r_fields,
   7940         SOC_RESET_VAL_DEC(0x007fe7ff, 0x00000000)
   7941         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7942         -1,
   7943         91,
   7944     },
   7945 #endif /* chips */
   7946 
   7947 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   7948     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_BCM53570_A0r */
   7949         soc_block_list[4],
   7950         soc_portreg,
   7951         8,
   7952         0,
   7953         0x10000,
   7954         SOC_REG_FLAG_ARRAY,
   7955         0,
   7956         2,
   7957         soc_HOLCOSCELLMAXLIMIT_BCM53570_A0r_fields,
   7958         SOC_RESET_VAL_DEC(0x00ff87ff, 0x00000000)
   7959         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   7960         -1,
   7961         102,
   7962     },
   7963 #endif /* chips */
   7964 
   7965 #if defined(BCM_56142_A0)
   7966     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_BCM56142_A0r */
   7967         soc_block_list[4],
   7968         soc_portreg,
   7969         8,
   7970         0,
   7971         0xed,
   7972         SOC_REG_FLAG_ARRAY,
   7973         0,
   7974         2,
   7975         soc_HOLCOSCELLMAXLIMIT_BCM56142_A0r_fields,
   7976         SOC_RESET_VAL_DEC(0x0bffefff, 0x00000000)
   7977         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   7978         -1,
   7979         -1,
   7980     },
   7981 #endif /* chips */
   7982 
   7983 #if defined(BCM_56150_A0)
   7984     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_BCM56150_A0r */
   7985         soc_block_list[4],
   7986         soc_portreg,
   7987         8,
   7988         0,
   7989         0xed00,
   7990         SOC_REG_FLAG_ARRAY,
   7991         0,
   7992         2,
   7993         soc_HOLCOSCELLMAXLIMIT_BCM56150_A0r_fields,
   7994         SOC_RESET_VAL_DEC(0x0bffefff, 0x00000000)
   7995         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   7996         -1,
   7997         79,
   7998     },
   7999 #endif /* chips */
   8000 
   8001 #if defined(BCM_56160_A0)
   8002     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_BCM56160_A0r */
   8003         soc_block_list[4],
   8004         soc_portreg,
   8005         8,
   8006         0,
   8007         0xed00,
   8008         SOC_REG_FLAG_ARRAY,
   8009         0,
   8010         2,
   8011         soc_HOLCOSCELLMAXLIMIT_BCM53400_A0r_fields,
   8012         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
   8013         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   8014         -1,
   8015         91,
   8016     },
   8017 #endif /* chips */
   8018 
   8019 #if defined(BCM_53570_A0)
   8020     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_QGROUPr */
   8021         soc_block_list[4],
   8022         soc_portreg,
   8023         8,
   8024         0,
   8025         0xc8e00,
   8026         SOC_REG_FLAG_ARRAY,
   8027         0,
   8028         2,
   8029         soc_HOLCOSCELLMAXLIMIT_QGROUPr_fields,
   8030         SOC_RESET_VAL_DEC(0x03ff87ff, 0x00000000)
   8031         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   8032         -1,
   8033         99,
   8034     },
   8035 #endif /* chips */
   8036 
   8037 #if defined(BCM_53570_B0)
   8038     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_QGROUP_BCM53570_B0r */
   8039         soc_block_list[4],
   8040         soc_portreg,
   8041         8,
   8042         0,
   8043         0xc9100,
   8044         SOC_REG_FLAG_ARRAY,
   8045         0,
   8046         2,
   8047         soc_HOLCOSCELLMAXLIMIT_QGROUPr_fields,
   8048         SOC_RESET_VAL_DEC(0x03ff87ff, 0x00000000)
   8049         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   8050         -1,
   8051         99,
   8052     },
   8053 #endif /* chips */
   8054 
   8055 #if defined(BCM_53570_A0)
   8056     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_QLAYERr */
   8057         soc_block_list[4],
   8058         soc_portreg,
   8059         64,
   8060         0,
   8061         0xc4e00,
   8062         SOC_REG_FLAG_ARRAY,
   8063         0,
   8064         2,
   8065         soc_HOLCOSCELLMAXLIMIT_QGROUPr_fields,
   8066         SOC_RESET_VAL_DEC(0x03ff87ff, 0x00000000)
   8067         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   8068         -1,
   8069         99,
   8070     },
   8071 #endif /* chips */
   8072 
   8073 #if defined(BCM_53570_B0)
   8074     { /* SOC_REG_INT_HOLCOSCELLMAXLIMIT_QLAYER_BCM53570_B0r */
   8075         soc_block_list[4],
   8076         soc_portreg,
   8077         64,
   8078         0,
   8079         0xc5100,
   8080         SOC_REG_FLAG_ARRAY,
   8081         0,
   8082         2,
   8083         soc_HOLCOSCELLMAXLIMIT_QGROUPr_fields,
   8084         SOC_RESET_VAL_DEC(0x03ff87ff, 0x00000000)
   8085         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   8086         -1,
   8087         99,
   8088     },
   8089 #endif /* chips */
   8090 
   8091 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   8092     { /* SOC_REG_INT_HOLCOSMINXQCNTr */
   8093         soc_block_list[4],
   8094         soc_portreg,
   8095         8,
   8096         0,
   8097         0x17,
   8098         SOC_REG_FLAG_ARRAY,
   8099         0,
   8100         1,
   8101         soc_HOLCOSMINXQCNTr_fields,
   8102         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8103         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8104         -1,
   8105         -1,
   8106     },
   8107 #endif /* chips */
   8108 
   8109 #if defined(BCM_53400_A0)
   8110     { /* SOC_REG_INT_HOLCOSMINXQCNT_BCM53400_A0r */
   8111         soc_block_list[4],
   8112         soc_portreg,
   8113         8,
   8114         0,
   8115         0x4800,
   8116         SOC_REG_FLAG_ARRAY,
   8117         0,
   8118         1,
   8119         soc_HOLCOSMINXQCNT_BCM53400_A0r_fields,
   8120         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8121         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8122         -1,
   8123         79,
   8124     },
   8125 #endif /* chips */
   8126 
   8127 #if defined(BCM_53540_A0)
   8128     { /* SOC_REG_INT_HOLCOSMINXQCNT_BCM53540_A0r */
   8129         soc_block_list[4],
   8130         soc_portreg,
   8131         8,
   8132         0,
   8133         0x3800,
   8134         SOC_REG_FLAG_ARRAY,
   8135         0,
   8136         1,
   8137         soc_HOLCOSMINXQCNT_BCM53540_A0r_fields,
   8138         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   8139         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   8140         -1,
   8141         91,
   8142     },
   8143 #endif /* chips */
   8144 
   8145 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8146     { /* SOC_REG_INT_HOLCOSMINXQCNT_BCM53570_A0r */
   8147         soc_block_list[4],
   8148         soc_portreg,
   8149         8,
   8150         0,
   8151         0x4000,
   8152         SOC_REG_FLAG_ARRAY,
   8153         0,
   8154         1,
   8155         soc_HOLCOSMINXQCNT_BCM53400_A0r_fields,
   8156         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8157         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8158         -1,
   8159         102,
   8160     },
   8161 #endif /* chips */
   8162 
   8163 #if defined(BCM_56142_A0)
   8164     { /* SOC_REG_INT_HOLCOSMINXQCNT_BCM56142_A0r */
   8165         soc_block_list[4],
   8166         soc_portreg,
   8167         8,
   8168         0,
   8169         0x48,
   8170         SOC_REG_FLAG_ARRAY,
   8171         0,
   8172         1,
   8173         soc_HOLCOSMINXQCNTr_fields,
   8174         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8175         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8176         -1,
   8177         -1,
   8178     },
   8179 #endif /* chips */
   8180 
   8181 #if defined(BCM_56150_A0)
   8182     { /* SOC_REG_INT_HOLCOSMINXQCNT_BCM56150_A0r */
   8183         soc_block_list[4],
   8184         soc_portreg,
   8185         8,
   8186         0,
   8187         0x4800,
   8188         SOC_REG_FLAG_ARRAY,
   8189         0,
   8190         1,
   8191         soc_HOLCOSMINXQCNT_BCM56150_A0r_fields,
   8192         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8193         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8194         -1,
   8195         79,
   8196     },
   8197 #endif /* chips */
   8198 
   8199 #if defined(BCM_56160_A0)
   8200     { /* SOC_REG_INT_HOLCOSMINXQCNT_BCM56160_A0r */
   8201         soc_block_list[4],
   8202         soc_portreg,
   8203         8,
   8204         0,
   8205         0x4800,
   8206         SOC_REG_FLAG_ARRAY,
   8207         0,
   8208         1,
   8209         soc_HOLCOSMINXQCNT_BCM56160_A0r_fields,
   8210         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8211         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8212         -1,
   8213         91,
   8214     },
   8215 #endif /* chips */
   8216 
   8217 #if defined(BCM_53570_A0)
   8218     { /* SOC_REG_INT_HOLCOSMINXQCNT_QLAYERr */
   8219         soc_block_list[4],
   8220         soc_portreg,
   8221         64,
   8222         0,
   8223         0xa8e00,
   8224         SOC_REG_FLAG_ARRAY,
   8225         0,
   8226         1,
   8227         soc_HOLCOSMINXQCNT_BCM53400_A0r_fields,
   8228         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8229         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8230         -1,
   8231         99,
   8232     },
   8233 #endif /* chips */
   8234 
   8235 #if defined(BCM_53570_B0)
   8236     { /* SOC_REG_INT_HOLCOSMINXQCNT_QLAYER_BCM53570_B0r */
   8237         soc_block_list[4],
   8238         soc_portreg,
   8239         64,
   8240         0,
   8241         0xa9100,
   8242         SOC_REG_FLAG_ARRAY,
   8243         0,
   8244         1,
   8245         soc_HOLCOSMINXQCNT_BCM53400_A0r_fields,
   8246         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8247         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8248         -1,
   8249         99,
   8250     },
   8251 #endif /* chips */
   8252 
   8253 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   8254     { /* SOC_REG_INT_HOLCOSPKTRESETLIMITr */
   8255         soc_block_list[4],
   8256         soc_portreg,
   8257         8,
   8258         0,
   8259         0xf,
   8260         SOC_REG_FLAG_ARRAY,
   8261         0,
   8262         1,
   8263         soc_HOLCOSPKTRESETLIMITr_fields,
   8264         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8265         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8266         -1,
   8267         -1,
   8268     },
   8269 #endif /* chips */
   8270 
   8271 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   8272     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_BCM53314_A0r */
   8273         soc_block_list[4],
   8274         soc_portreg,
   8275         4,
   8276         0,
   8277         0xf,
   8278         SOC_REG_FLAG_ARRAY,
   8279         0,
   8280         1,
   8281         soc_HOLCOSPKTRESETLIMIT_BCM53314_A0r_fields,
   8282         SOC_RESET_VAL_DEC(0x000001ef, 0x00000000)
   8283         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8284         -1,
   8285         -1,
   8286     },
   8287 #endif /* chips */
   8288 
   8289 #if defined(BCM_53400_A0)
   8290     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_BCM53400_A0r */
   8291         soc_block_list[4],
   8292         soc_portreg,
   8293         8,
   8294         0,
   8295         0x2800,
   8296         SOC_REG_FLAG_ARRAY,
   8297         0,
   8298         1,
   8299         soc_HOLCOSPKTRESETLIMIT_BCM53400_A0r_fields,
   8300         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8301         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8302         -1,
   8303         79,
   8304     },
   8305 #endif /* chips */
   8306 
   8307 #if defined(BCM_53540_A0)
   8308     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_BCM53540_A0r */
   8309         soc_block_list[4],
   8310         soc_portreg,
   8311         8,
   8312         0,
   8313         0x3000,
   8314         SOC_REG_FLAG_ARRAY,
   8315         0,
   8316         1,
   8317         soc_HOLCOSPKTRESETLIMIT_BCM53540_A0r_fields,
   8318         SOC_RESET_VAL_DEC(0x00000017, 0x00000000)
   8319         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   8320         -1,
   8321         91,
   8322     },
   8323 #endif /* chips */
   8324 
   8325 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8326     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_BCM53570_A0r */
   8327         soc_block_list[4],
   8328         soc_portreg,
   8329         8,
   8330         0,
   8331         0x3800,
   8332         SOC_REG_FLAG_ARRAY,
   8333         0,
   8334         1,
   8335         soc_HOLCOSPKTRESETLIMIT_BCM53400_A0r_fields,
   8336         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8337         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8338         -1,
   8339         102,
   8340     },
   8341 #endif /* chips */
   8342 
   8343 #if defined(BCM_56142_A0)
   8344     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_BCM56142_A0r */
   8345         soc_block_list[4],
   8346         soc_portreg,
   8347         8,
   8348         0,
   8349         0x28,
   8350         SOC_REG_FLAG_ARRAY,
   8351         0,
   8352         1,
   8353         soc_HOLCOSPKTRESETLIMITr_fields,
   8354         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8355         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8356         -1,
   8357         -1,
   8358     },
   8359 #endif /* chips */
   8360 
   8361 #if defined(BCM_56150_A0)
   8362     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_BCM56150_A0r */
   8363         soc_block_list[4],
   8364         soc_portreg,
   8365         8,
   8366         0,
   8367         0x2800,
   8368         SOC_REG_FLAG_ARRAY,
   8369         0,
   8370         1,
   8371         soc_HOLCOSPKTRESETLIMIT_BCM56150_A0r_fields,
   8372         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8373         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8374         -1,
   8375         79,
   8376     },
   8377 #endif /* chips */
   8378 
   8379 #if defined(BCM_56160_A0)
   8380     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_BCM56160_A0r */
   8381         soc_block_list[4],
   8382         soc_portreg,
   8383         8,
   8384         0,
   8385         0x2800,
   8386         SOC_REG_FLAG_ARRAY,
   8387         0,
   8388         1,
   8389         soc_HOLCOSPKTRESETLIMIT_BCM56160_A0r_fields,
   8390         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8391         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8392         -1,
   8393         91,
   8394     },
   8395 #endif /* chips */
   8396 
   8397 #if defined(BCM_53570_A0)
   8398     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_QGROUPr */
   8399         soc_block_list[4],
   8400         soc_portreg,
   8401         8,
   8402         0,
   8403         0xa4e00,
   8404         SOC_REG_FLAG_ARRAY,
   8405         0,
   8406         1,
   8407         soc_HOLCOSPKTRESETLIMIT_BCM53400_A0r_fields,
   8408         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8409         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8410         -1,
   8411         99,
   8412     },
   8413 #endif /* chips */
   8414 
   8415 #if defined(BCM_53570_B0)
   8416     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_QGROUP_BCM53570_B0r */
   8417         soc_block_list[4],
   8418         soc_portreg,
   8419         8,
   8420         0,
   8421         0xa5100,
   8422         SOC_REG_FLAG_ARRAY,
   8423         0,
   8424         1,
   8425         soc_HOLCOSPKTRESETLIMIT_BCM53400_A0r_fields,
   8426         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8427         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8428         -1,
   8429         99,
   8430     },
   8431 #endif /* chips */
   8432 
   8433 #if defined(BCM_53570_A0)
   8434     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_QLAYERr */
   8435         soc_block_list[4],
   8436         soc_portreg,
   8437         64,
   8438         0,
   8439         0xa0e00,
   8440         SOC_REG_FLAG_ARRAY,
   8441         0,
   8442         1,
   8443         soc_HOLCOSPKTRESETLIMIT_BCM53400_A0r_fields,
   8444         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8445         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8446         -1,
   8447         99,
   8448     },
   8449 #endif /* chips */
   8450 
   8451 #if defined(BCM_53570_B0)
   8452     { /* SOC_REG_INT_HOLCOSPKTRESETLIMIT_QLAYER_BCM53570_B0r */
   8453         soc_block_list[4],
   8454         soc_portreg,
   8455         64,
   8456         0,
   8457         0xa1100,
   8458         SOC_REG_FLAG_ARRAY,
   8459         0,
   8460         1,
   8461         soc_HOLCOSPKTRESETLIMIT_BCM53400_A0r_fields,
   8462         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8463         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8464         -1,
   8465         99,
   8466     },
   8467 #endif /* chips */
   8468 
   8469 #if defined(BCM_56504_A0)
   8470     { /* SOC_REG_INT_HOLCOSPKTSETLIMITr */
   8471         soc_block_list[4],
   8472         soc_portreg,
   8473         8,
   8474         0,
   8475         0x10,
   8476         SOC_REG_FLAG_ARRAY,
   8477         0,
   8478         2,
   8479         soc_HOLCOSPKTSETLIMITr_fields,
   8480         SOC_RESET_VAL_DEC(0x00000900, 0x00000000)
   8481         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8482         -1,
   8483         -1,
   8484     },
   8485 #endif /* chips */
   8486 
   8487 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   8488     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM53314_A0r */
   8489         soc_block_list[4],
   8490         soc_portreg,
   8491         4,
   8492         0,
   8493         0x7,
   8494         SOC_REG_FLAG_ARRAY,
   8495         0,
   8496         1,
   8497         soc_HOLCOSPKTSETLIMIT_BCM53314_A0r_fields,
   8498         SOC_RESET_VAL_DEC(0x000001f3, 0x00000000)
   8499         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8500         -1,
   8501         -1,
   8502     },
   8503 #endif /* chips */
   8504 
   8505 #if defined(BCM_53400_A0)
   8506     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM53400_A0r */
   8507         soc_block_list[4],
   8508         soc_portreg,
   8509         8,
   8510         0,
   8511         0x800,
   8512         SOC_REG_FLAG_ARRAY,
   8513         0,
   8514         1,
   8515         soc_HOLCOSPKTSETLIMIT_BCM53400_A0r_fields,
   8516         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8517         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8518         -1,
   8519         79,
   8520     },
   8521 #endif /* chips */
   8522 
   8523 #if defined(BCM_53540_A0)
   8524     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM53540_A0r */
   8525         soc_block_list[4],
   8526         soc_portreg,
   8527         8,
   8528         0,
   8529         0x2800,
   8530         SOC_REG_FLAG_ARRAY,
   8531         0,
   8532         1,
   8533         soc_HOLCOSPKTSETLIMIT_BCM53540_A0r_fields,
   8534         SOC_RESET_VAL_DEC(0x0000001c, 0x00000000)
   8535         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   8536         -1,
   8537         91,
   8538     },
   8539 #endif /* chips */
   8540 
   8541 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8542     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM53570_A0r */
   8543         soc_block_list[4],
   8544         soc_portreg,
   8545         8,
   8546         0,
   8547         0x3000,
   8548         SOC_REG_FLAG_ARRAY,
   8549         0,
   8550         1,
   8551         soc_HOLCOSPKTSETLIMIT_BCM53400_A0r_fields,
   8552         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8553         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8554         -1,
   8555         102,
   8556     },
   8557 #endif /* chips */
   8558 
   8559 #if defined(BCM_56142_A0)
   8560     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM56142_A0r */
   8561         soc_block_list[4],
   8562         soc_portreg,
   8563         8,
   8564         0,
   8565         0x8,
   8566         SOC_REG_FLAG_ARRAY,
   8567         0,
   8568         1,
   8569         soc_HOLCOSPKTSETLIMIT_BCM56224_A0r_fields,
   8570         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8571         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8572         -1,
   8573         -1,
   8574     },
   8575 #endif /* chips */
   8576 
   8577 #if defined(BCM_56150_A0)
   8578     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM56150_A0r */
   8579         soc_block_list[4],
   8580         soc_portreg,
   8581         8,
   8582         0,
   8583         0x800,
   8584         SOC_REG_FLAG_ARRAY,
   8585         0,
   8586         1,
   8587         soc_HOLCOSPKTSETLIMIT_BCM56150_A0r_fields,
   8588         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8589         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8590         -1,
   8591         79,
   8592     },
   8593 #endif /* chips */
   8594 
   8595 #if defined(BCM_56160_A0)
   8596     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM56160_A0r */
   8597         soc_block_list[4],
   8598         soc_portreg,
   8599         8,
   8600         0,
   8601         0x800,
   8602         SOC_REG_FLAG_ARRAY,
   8603         0,
   8604         1,
   8605         soc_HOLCOSPKTSETLIMIT_BCM56160_A0r_fields,
   8606         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8607         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8608         -1,
   8609         91,
   8610     },
   8611 #endif /* chips */
   8612 
   8613 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   8614     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM56224_A0r */
   8615         soc_block_list[4],
   8616         soc_portreg,
   8617         8,
   8618         0,
   8619         0x7,
   8620         SOC_REG_FLAG_ARRAY,
   8621         0,
   8622         1,
   8623         soc_HOLCOSPKTSETLIMIT_BCM56224_A0r_fields,
   8624         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8625         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   8626         -1,
   8627         -1,
   8628     },
   8629 #endif /* chips */
   8630 
   8631 #if defined(BCM_56314_A0)
   8632     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM56314_A0r */
   8633         soc_block_list[4],
   8634         soc_portreg,
   8635         8,
   8636         0,
   8637         0x10,
   8638         SOC_REG_FLAG_ARRAY,
   8639         0,
   8640         2,
   8641         soc_HOLCOSPKTSETLIMIT_BCM56314_A0r_fields,
   8642         SOC_RESET_VAL_DEC(0x00000860, 0x00000000)
   8643         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8644         -1,
   8645         -1,
   8646     },
   8647 #endif /* chips */
   8648 
   8649 #if defined(BCM_56504_B0)
   8650     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM56504_B0r */
   8651         soc_block_list[4],
   8652         soc_portreg,
   8653         8,
   8654         0,
   8655         0x10,
   8656         SOC_REG_FLAG_ARRAY,
   8657         0,
   8658         2,
   8659         soc_HOLCOSPKTSETLIMIT_BCM56504_B0r_fields,
   8660         SOC_RESET_VAL_DEC(0x000008c0, 0x00000000)
   8661         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8662         -1,
   8663         -1,
   8664     },
   8665 #endif /* chips */
   8666 
   8667 #if defined(BCM_56514_A0)
   8668     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_BCM56514_A0r */
   8669         soc_block_list[4],
   8670         soc_portreg,
   8671         8,
   8672         0,
   8673         0x10,
   8674         SOC_REG_FLAG_ARRAY,
   8675         0,
   8676         2,
   8677         soc_HOLCOSPKTSETLIMIT_BCM56514_A0r_fields,
   8678         SOC_RESET_VAL_DEC(0x000500c0, 0x00000000)
   8679         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
   8680         -1,
   8681         -1,
   8682     },
   8683 #endif /* chips */
   8684 
   8685 #if defined(BCM_53570_A0)
   8686     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_QGROUPr */
   8687         soc_block_list[4],
   8688         soc_portreg,
   8689         8,
   8690         0,
   8691         0x9ce00,
   8692         SOC_REG_FLAG_ARRAY,
   8693         0,
   8694         1,
   8695         soc_HOLCOSPKTSETLIMIT_BCM53400_A0r_fields,
   8696         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8697         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8698         -1,
   8699         99,
   8700     },
   8701 #endif /* chips */
   8702 
   8703 #if defined(BCM_53570_B0)
   8704     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_QGROUP_BCM53570_B0r */
   8705         soc_block_list[4],
   8706         soc_portreg,
   8707         8,
   8708         0,
   8709         0x9d100,
   8710         SOC_REG_FLAG_ARRAY,
   8711         0,
   8712         1,
   8713         soc_HOLCOSPKTSETLIMIT_BCM53400_A0r_fields,
   8714         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8715         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8716         -1,
   8717         99,
   8718     },
   8719 #endif /* chips */
   8720 
   8721 #if defined(BCM_53570_A0)
   8722     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_QLAYERr */
   8723         soc_block_list[4],
   8724         soc_portreg,
   8725         64,
   8726         0,
   8727         0x98e00,
   8728         SOC_REG_FLAG_ARRAY,
   8729         0,
   8730         1,
   8731         soc_HOLCOSPKTSETLIMIT_BCM53400_A0r_fields,
   8732         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8733         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8734         -1,
   8735         99,
   8736     },
   8737 #endif /* chips */
   8738 
   8739 #if defined(BCM_53570_B0)
   8740     { /* SOC_REG_INT_HOLCOSPKTSETLIMIT_QLAYER_BCM53570_B0r */
   8741         soc_block_list[4],
   8742         soc_portreg,
   8743         64,
   8744         0,
   8745         0x99100,
   8746         SOC_REG_FLAG_ARRAY,
   8747         0,
   8748         1,
   8749         soc_HOLCOSPKTSETLIMIT_BCM53400_A0r_fields,
   8750         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
   8751         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8752         -1,
   8753         99,
   8754     },
   8755 #endif /* chips */
   8756 
   8757 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   8758     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   8759     { /* SOC_REG_INT_HOLCOSSTATUSr */
   8760         soc_block_list[4],
   8761         soc_genreg,
   8762         8,
   8763         0,
   8764         0x80008,
   8765         SOC_REG_FLAG_ARRAY |
   8766                           SOC_REG_FLAG_RO,
   8767         0,
   8768         1,
   8769         soc_BKPMETERINGDISCSTATUSr_fields,
   8770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8771         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8772         -1,
   8773         -1,
   8774     },
   8775 #endif /* chips */
   8776 
   8777 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   8778     { /* SOC_REG_INT_HOLCOSSTATUS_BCM53314_A0r */
   8779         soc_block_list[4],
   8780         soc_genreg,
   8781         4,
   8782         0,
   8783         0x80005,
   8784         SOC_REG_FLAG_ARRAY |
   8785                           SOC_REG_FLAG_RO,
   8786         0,
   8787         1,
   8788         soc_BKPMETERINGDISCSTATUS_BCM53314_A0r_fields,
   8789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8790         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   8791         -1,
   8792         -1,
   8793     },
   8794 #endif /* chips */
   8795 
   8796 #if defined(BCM_53400_A0)
   8797     { /* SOC_REG_INT_HOLCOSSTATUS_BCM53400_A0r */
   8798         soc_block_list[4],
   8799         soc_genreg,
   8800         8,
   8801         0,
   8802         0x2024500,
   8803         SOC_REG_FLAG_ARRAY |
   8804                           SOC_REG_FLAG_RO,
   8805         0,
   8806         1,
   8807         soc_BKPMETERINGDISCSTATUS_BCM53400_A0r_fields,
   8808         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   8809         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   8810         -1,
   8811         -1,
   8812     },
   8813 #endif /* chips */
   8814 
   8815 #if defined(BCM_53540_A0)
   8816     { /* SOC_REG_INT_HOLCOSSTATUS_BCM53540_A0r */
   8817         soc_block_list[4],
   8818         soc_genreg,
   8819         8,
   8820         0,
   8821         0x2024800,
   8822         SOC_REG_FLAG_ARRAY |
   8823                           SOC_REG_FLAG_RO,
   8824         0,
   8825         1,
   8826         soc_BKPMETERINGDISCSTATUS_BCM56160_A0r_fields,
   8827         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   8828         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8829         -1,
   8830         -1,
   8831     },
   8832 #endif /* chips */
   8833 
   8834 #if defined(BCM_56142_A0)
   8835     { /* SOC_REG_INT_HOLCOSSTATUS_BCM56142_A0r */
   8836         soc_block_list[4],
   8837         soc_genreg,
   8838         8,
   8839         0,
   8840         0x80005,
   8841         SOC_REG_FLAG_ARRAY |
   8842                           SOC_REG_FLAG_RO,
   8843         0,
   8844         1,
   8845         soc_BKPMETERINGDISCSTATUS_BCM56142_A0r_fields,
   8846         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   8847         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   8848         -1,
   8849         -1,
   8850     },
   8851 #endif /* chips */
   8852 
   8853 #if defined(BCM_56150_A0)
   8854     { /* SOC_REG_INT_HOLCOSSTATUS_BCM56150_A0r */
   8855         soc_block_list[4],
   8856         soc_genreg,
   8857         8,
   8858         0,
   8859         0x2024500,
   8860         SOC_REG_FLAG_ARRAY |
   8861                           SOC_REG_FLAG_RO,
   8862         0,
   8863         1,
   8864         soc_BKPMETERINGDISCSTATUS_BCM56150_A0r_fields,
   8865         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   8866         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   8867         -1,
   8868         -1,
   8869     },
   8870 #endif /* chips */
   8871 
   8872 #if defined(BCM_56160_A0)
   8873     { /* SOC_REG_INT_HOLCOSSTATUS_BCM56160_A0r */
   8874         soc_block_list[4],
   8875         soc_genreg,
   8876         8,
   8877         0,
   8878         0x2024500,
   8879         SOC_REG_FLAG_ARRAY |
   8880                           SOC_REG_FLAG_RO,
   8881         0,
   8882         1,
   8883         soc_BKPMETERINGDISCSTATUS_BCM56160_A0r_fields,
   8884         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   8885         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8886         -1,
   8887         -1,
   8888     },
   8889 #endif /* chips */
   8890 
   8891 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   8892     { /* SOC_REG_INT_HOLCOSSTATUS_BCM56224_A0r */
   8893         soc_block_list[4],
   8894         soc_genreg,
   8895         8,
   8896         0,
   8897         0x80005,
   8898         SOC_REG_FLAG_ARRAY |
   8899                           SOC_REG_FLAG_RO,
   8900         0,
   8901         1,
   8902         soc_BKPMETERINGDISCSTATUS_BCM56224_A0r_fields,
   8903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8904         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   8905         -1,
   8906         -1,
   8907     },
   8908 #endif /* chips */
   8909 
   8910 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8911     { /* SOC_REG_INT_HOLCOSSTATUS_PBMP0r */
   8912         soc_block_list[4],
   8913         soc_genreg,
   8914         64,
   8915         0,
   8916         0x2037800,
   8917         SOC_REG_FLAG_ARRAY |
   8918                           SOC_REG_FLAG_RO,
   8919         0,
   8920         1,
   8921         soc_HOLCOSSTATUS_PBMP0r_fields,
   8922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8923         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8924         -1,
   8925         -1,
   8926     },
   8927 #endif /* chips */
   8928 
   8929 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8930     { /* SOC_REG_INT_HOLCOSSTATUS_PBMP1r */
   8931         soc_block_list[4],
   8932         soc_genreg,
   8933         64,
   8934         0,
   8935         0x203b800,
   8936         SOC_REG_FLAG_ARRAY |
   8937                           SOC_REG_FLAG_RO,
   8938         0,
   8939         1,
   8940         soc_HOLCOSSTATUS_PBMP1r_fields,
   8941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8942         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8943         -1,
   8944         -1,
   8945     },
   8946 #endif /* chips */
   8947 
   8948 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8949     { /* SOC_REG_INT_HOLCOSSTATUS_PBMP2r */
   8950         soc_block_list[4],
   8951         soc_genreg,
   8952         64,
   8953         0,
   8954         0x203f800,
   8955         SOC_REG_FLAG_ARRAY |
   8956                           SOC_REG_FLAG_RO,
   8957         0,
   8958         1,
   8959         soc_HOLCOSSTATUS_PBMP2r_fields,
   8960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8961         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8962         -1,
   8963         -1,
   8964     },
   8965 #endif /* chips */
   8966 
   8967 #if defined(BCM_53570_A0)
   8968     { /* SOC_REG_INT_HOLCOSSTATUS_QGROUPr */
   8969         soc_block_list[4],
   8970         soc_portreg,
   8971         1,
   8972         0,
   8973         0xd0e00,
   8974         SOC_REG_FLAG_RO,
   8975         0,
   8976         1,
   8977         soc_HOLCOSSTATUS_QGROUPr_fields,
   8978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8979         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   8980         -1,
   8981         99,
   8982     },
   8983 #endif /* chips */
   8984 
   8985 #if defined(BCM_53570_B0)
   8986     { /* SOC_REG_INT_HOLCOSSTATUS_QGROUP_BCM53570_B0r */
   8987         soc_block_list[4],
   8988         soc_portreg,
   8989         1,
   8990         0,
   8991         0xd1100,
   8992         SOC_REG_FLAG_RO,
   8993         0,
   8994         1,
   8995         soc_HOLCOSSTATUS_QGROUPr_fields,
   8996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8997         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   8998         -1,
   8999         99,
   9000     },
   9001 #endif /* chips */
   9002 
   9003 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9004     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9005     { /* SOC_REG_INT_HOLDr */
   9006         soc_block_list[5],
   9007         soc_portreg,
   9008         1,
   9009         0,
   9010         0xe000014,
   9011         SOC_REG_FLAG_COUNTER |
   9012                           SOC_REG_FLAG_ED_CNTR,
   9013         0,
   9014         1,
   9015         soc_HOLDr_fields,
   9016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9017         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9018         20,
   9019         -1,
   9020     },
   9021 #endif /* chips */
   9022 
   9023 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9024     { /* SOC_REG_INT_HOLDROP_PKT_CNTr */
   9025         soc_block_list[4],
   9026         soc_portreg,
   9027         32,
   9028         0,
   9029         0xe000040,
   9030         SOC_REG_FLAG_ARRAY,
   9031         0,
   9032         1,
   9033         soc_CFAP_DROP_PKT_CNTr_fields,
   9034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9035         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   9036         -1,
   9037         9,
   9038     },
   9039 #endif /* chips */
   9040 
   9041 #if defined(BCM_56142_A0)
   9042     { /* SOC_REG_INT_HOLD_BCM56142_A0r */
   9043         soc_block_list[5],
   9044         soc_portreg,
   9045         1,
   9046         0,
   9047         0x11000021,
   9048         SOC_REG_FLAG_COUNTER |
   9049                           SOC_REG_FLAG_ED_CNTR,
   9050         0,
   9051         1,
   9052         soc_HOLD_BCM56800_A0r_fields,
   9053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9054         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9055         33,
   9056         -1,
   9057     },
   9058 #endif /* chips */
   9059 
   9060 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9061     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9062     { /* SOC_REG_INT_HOLD_BCM56224_A0r */
   9063         soc_block_list[5],
   9064         soc_portreg,
   9065         1,
   9066         0,
   9067         0xf000014,
   9068         SOC_REG_FLAG_COUNTER |
   9069                           SOC_REG_FLAG_ED_CNTR,
   9070         0,
   9071         1,
   9072         soc_HOLDr_fields,
   9073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9074         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9075         20,
   9076         -1,
   9077     },
   9078 #endif /* chips */
   9079 
   9080 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   9081     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9082     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9083     { /* SOC_REG_INT_HOLD_BCM56624_A0r */
   9084         soc_block_list[5],
   9085         soc_portreg,
   9086         1,
   9087         0,
   9088         0x1100001c,
   9089         SOC_REG_FLAG_COUNTER |
   9090                           SOC_REG_FLAG_ED_CNTR,
   9091         0,
   9092         1,
   9093         soc_HOLD_BCM56800_A0r_fields,
   9094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9095         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9096         28,
   9097         -1,
   9098     },
   9099 #endif /* chips */
   9100 
   9101 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9102     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9103     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9104     { /* SOC_REG_INT_HOLD_BCM56634_A0r */
   9105         soc_block_list[5],
   9106         soc_portreg,
   9107         1,
   9108         0,
   9109         0xe00001c,
   9110         SOC_REG_FLAG_COUNTER |
   9111                           SOC_REG_FLAG_ED_CNTR,
   9112         0,
   9113         1,
   9114         soc_HOLD_BCM56800_A0r_fields,
   9115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9116         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9117         28,
   9118         -1,
   9119     },
   9120 #endif /* chips */
   9121 
   9122 #if defined(BCM_56800_A0)
   9123     { /* SOC_REG_INT_HOLD_BCM56800_A0r */
   9124         soc_block_list[5],
   9125         soc_portreg,
   9126         1,
   9127         0,
   9128         0xe000c1c,
   9129         SOC_REG_FLAG_COUNTER |
   9130                           SOC_REG_FLAG_ED_CNTR,
   9131         0,
   9132         1,
   9133         soc_HOLD_BCM56800_A0r_fields,
   9134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9136         28,
   9137         -1,
   9138     },
   9139 #endif /* chips */
   9140 
   9141 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9142     { /* SOC_REG_INT_HOLD_BCM56820_A0r */
   9143         soc_block_list[5],
   9144         soc_portreg,
   9145         1,
   9146         0,
   9147         0xf000c1c,
   9148         SOC_REG_FLAG_COUNTER |
   9149                           SOC_REG_FLAG_ED_CNTR,
   9150         0,
   9151         1,
   9152         soc_HOLDr_fields,
   9153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9154         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9155         28,
   9156         -1,
   9157     },
   9158 #endif /* chips */
   9159 
   9160 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9161     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9162     { /* SOC_REG_INT_HOLD_COS0r */
   9163         soc_block_list[5],
   9164         soc_genreg,
   9165         1,
   9166         0,
   9167         0xe080015,
   9168         SOC_REG_FLAG_ED_CNTR,
   9169         0,
   9170         1,
   9171         soc_HOLDr_fields,
   9172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9173         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9174         -1,
   9175         -1,
   9176     },
   9177 #endif /* chips */
   9178 
   9179 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9180     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9181     { /* SOC_REG_INT_HOLD_COS1r */
   9182         soc_block_list[5],
   9183         soc_genreg,
   9184         1,
   9185         0,
   9186         0xe080016,
   9187         SOC_REG_FLAG_ED_CNTR,
   9188         0,
   9189         1,
   9190         soc_HOLDr_fields,
   9191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9192         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9193         -1,
   9194         -1,
   9195     },
   9196 #endif /* chips */
   9197 
   9198 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9199     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9200     { /* SOC_REG_INT_HOLD_COS2r */
   9201         soc_block_list[5],
   9202         soc_genreg,
   9203         1,
   9204         0,
   9205         0xe080017,
   9206         SOC_REG_FLAG_ED_CNTR,
   9207         0,
   9208         1,
   9209         soc_HOLDr_fields,
   9210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9211         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9212         -1,
   9213         -1,
   9214     },
   9215 #endif /* chips */
   9216 
   9217 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9218     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9219     { /* SOC_REG_INT_HOLD_COS3r */
   9220         soc_block_list[5],
   9221         soc_genreg,
   9222         1,
   9223         0,
   9224         0xe080018,
   9225         SOC_REG_FLAG_ED_CNTR,
   9226         0,
   9227         1,
   9228         soc_HOLDr_fields,
   9229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9230         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9231         -1,
   9232         -1,
   9233     },
   9234 #endif /* chips */
   9235 
   9236 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9237     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9238     { /* SOC_REG_INT_HOLD_COS4r */
   9239         soc_block_list[5],
   9240         soc_genreg,
   9241         1,
   9242         0,
   9243         0xe080019,
   9244         SOC_REG_FLAG_ED_CNTR,
   9245         0,
   9246         1,
   9247         soc_HOLDr_fields,
   9248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9249         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9250         -1,
   9251         -1,
   9252     },
   9253 #endif /* chips */
   9254 
   9255 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9256     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9257     { /* SOC_REG_INT_HOLD_COS5r */
   9258         soc_block_list[5],
   9259         soc_genreg,
   9260         1,
   9261         0,
   9262         0xe08001a,
   9263         SOC_REG_FLAG_ED_CNTR,
   9264         0,
   9265         1,
   9266         soc_HOLDr_fields,
   9267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9268         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9269         -1,
   9270         -1,
   9271     },
   9272 #endif /* chips */
   9273 
   9274 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9275     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9276     { /* SOC_REG_INT_HOLD_COS6r */
   9277         soc_block_list[5],
   9278         soc_genreg,
   9279         1,
   9280         0,
   9281         0xe08001b,
   9282         SOC_REG_FLAG_ED_CNTR,
   9283         0,
   9284         1,
   9285         soc_HOLDr_fields,
   9286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9287         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9288         -1,
   9289         -1,
   9290     },
   9291 #endif /* chips */
   9292 
   9293 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9294     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9295     { /* SOC_REG_INT_HOLD_COS7r */
   9296         soc_block_list[5],
   9297         soc_genreg,
   9298         1,
   9299         0,
   9300         0xe08001c,
   9301         SOC_REG_FLAG_ED_CNTR,
   9302         0,
   9303         1,
   9304         soc_HOLDr_fields,
   9305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9306         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9307         -1,
   9308         -1,
   9309     },
   9310 #endif /* chips */
   9311 
   9312 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   9313     defined(BCM_56160_A0)
   9314     { /* SOC_REG_INT_HOLD_COS0_BCM53400_A0r */
   9315         soc_block_list[5],
   9316         soc_genreg,
   9317         1,
   9318         0,
   9319         0x42005b00,
   9320         SOC_REG_FLAG_COUNTER |
   9321                           SOC_REG_FLAG_ED_CNTR,
   9322         0,
   9323         1,
   9324         soc_EGR_ECN_COUNTERr_fields,
   9325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9326         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9327         91,
   9328         -1,
   9329     },
   9330 #endif /* chips */
   9331 
   9332 #if defined(BCM_53570_A0)
   9333     { /* SOC_REG_INT_HOLD_COS0_BCM53570_A0r */
   9334         soc_block_list[5],
   9335         soc_genreg,
   9336         1,
   9337         0,
   9338         0x42008d00,
   9339         SOC_REG_FLAG_COUNTER |
   9340                           SOC_REG_FLAG_ED_CNTR,
   9341         0,
   9342         1,
   9343         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
   9344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9346         141,
   9347         -1,
   9348     },
   9349 #endif /* chips */
   9350 
   9351 #if defined(BCM_56142_A0)
   9352     { /* SOC_REG_INT_HOLD_COS0_BCM56142_A0r */
   9353         soc_block_list[5],
   9354         soc_genreg,
   9355         1,
   9356         0,
   9357         0x11080050,
   9358         SOC_REG_FLAG_COUNTER |
   9359                           SOC_REG_FLAG_ED_CNTR,
   9360         0,
   9361         1,
   9362         soc_HOLDr_fields,
   9363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9364         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9365         80,
   9366         -1,
   9367     },
   9368 #endif /* chips */
   9369 
   9370 #if defined(BCM_56150_A0)
   9371     { /* SOC_REG_INT_HOLD_COS0_BCM56150_A0r */
   9372         soc_block_list[5],
   9373         soc_genreg,
   9374         1,
   9375         0,
   9376         0x46005b00,
   9377         SOC_REG_FLAG_COUNTER |
   9378                           SOC_REG_FLAG_ED_CNTR,
   9379         0,
   9380         1,
   9381         soc_TPCE_BCM56450_A0r_fields,
   9382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9383         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9384         91,
   9385         -1,
   9386     },
   9387 #endif /* chips */
   9388 
   9389 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9390     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9391     { /* SOC_REG_INT_HOLD_COS0_BCM56224_A0r */
   9392         soc_block_list[5],
   9393         soc_genreg,
   9394         1,
   9395         0,
   9396         0xf080015,
   9397         SOC_REG_FLAG_ED_CNTR,
   9398         0,
   9399         1,
   9400         soc_HOLDr_fields,
   9401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9402         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9403         -1,
   9404         -1,
   9405     },
   9406 #endif /* chips */
   9407 
   9408 #if defined(BCM_56800_A0)
   9409     { /* SOC_REG_INT_HOLD_COS0_BCM56800_A0r */
   9410         soc_block_list[5],
   9411         soc_genreg,
   9412         1,
   9413         0,
   9414         0xe080c00,
   9415         SOC_REG_FLAG_ED_CNTR,
   9416         0,
   9417         1,
   9418         soc_HOLD_BCM56800_A0r_fields,
   9419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9420         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9421         -1,
   9422         -1,
   9423     },
   9424 #endif /* chips */
   9425 
   9426 #if defined(BCM_56800_A0)
   9427     { /* SOC_REG_INT_HOLD_COS0_Xr */
   9428         soc_block_list[5],
   9429         soc_genreg,
   9430         1,
   9431         0,
   9432         0xe080200,
   9433         SOC_REG_FLAG_ED_CNTR,
   9434         0,
   9435         1,
   9436         soc_HOLDr_fields,
   9437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9438         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9439         -1,
   9440         -1,
   9441     },
   9442 #endif /* chips */
   9443 
   9444 #if defined(BCM_56800_A0)
   9445     { /* SOC_REG_INT_HOLD_COS0_Yr */
   9446         soc_block_list[5],
   9447         soc_genreg,
   9448         1,
   9449         0,
   9450         0xe080400,
   9451         SOC_REG_FLAG_ED_CNTR,
   9452         0,
   9453         1,
   9454         soc_HOLDr_fields,
   9455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9456         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9457         -1,
   9458         -1,
   9459     },
   9460 #endif /* chips */
   9461 
   9462 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   9463     defined(BCM_56160_A0)
   9464     { /* SOC_REG_INT_HOLD_COS1_BCM53400_A0r */
   9465         soc_block_list[5],
   9466         soc_genreg,
   9467         1,
   9468         0,
   9469         0x42005c00,
   9470         SOC_REG_FLAG_COUNTER |
   9471                           SOC_REG_FLAG_ED_CNTR,
   9472         0,
   9473         1,
   9474         soc_EGR_ECN_COUNTERr_fields,
   9475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9476         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9477         92,
   9478         -1,
   9479     },
   9480 #endif /* chips */
   9481 
   9482 #if defined(BCM_53570_A0)
   9483     { /* SOC_REG_INT_HOLD_COS1_BCM53570_A0r */
   9484         soc_block_list[5],
   9485         soc_genreg,
   9486         1,
   9487         0,
   9488         0x42008e00,
   9489         SOC_REG_FLAG_COUNTER |
   9490                           SOC_REG_FLAG_ED_CNTR,
   9491         0,
   9492         1,
   9493         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
   9494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9495         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9496         142,
   9497         -1,
   9498     },
   9499 #endif /* chips */
   9500 
   9501 #if defined(BCM_56142_A0)
   9502     { /* SOC_REG_INT_HOLD_COS1_BCM56142_A0r */
   9503         soc_block_list[5],
   9504         soc_genreg,
   9505         1,
   9506         0,
   9507         0x11080051,
   9508         SOC_REG_FLAG_COUNTER |
   9509                           SOC_REG_FLAG_ED_CNTR,
   9510         0,
   9511         1,
   9512         soc_HOLDr_fields,
   9513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9514         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9515         81,
   9516         -1,
   9517     },
   9518 #endif /* chips */
   9519 
   9520 #if defined(BCM_56150_A0)
   9521     { /* SOC_REG_INT_HOLD_COS1_BCM56150_A0r */
   9522         soc_block_list[5],
   9523         soc_genreg,
   9524         1,
   9525         0,
   9526         0x46005c00,
   9527         SOC_REG_FLAG_COUNTER |
   9528                           SOC_REG_FLAG_ED_CNTR,
   9529         0,
   9530         1,
   9531         soc_TPCE_BCM56450_A0r_fields,
   9532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9533         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9534         92,
   9535         -1,
   9536     },
   9537 #endif /* chips */
   9538 
   9539 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9540     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9541     { /* SOC_REG_INT_HOLD_COS1_BCM56224_A0r */
   9542         soc_block_list[5],
   9543         soc_genreg,
   9544         1,
   9545         0,
   9546         0xf080016,
   9547         SOC_REG_FLAG_ED_CNTR,
   9548         0,
   9549         1,
   9550         soc_HOLDr_fields,
   9551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9552         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9553         -1,
   9554         -1,
   9555     },
   9556 #endif /* chips */
   9557 
   9558 #if defined(BCM_56800_A0)
   9559     { /* SOC_REG_INT_HOLD_COS1_BCM56800_A0r */
   9560         soc_block_list[5],
   9561         soc_genreg,
   9562         1,
   9563         0,
   9564         0xe080c01,
   9565         SOC_REG_FLAG_ED_CNTR,
   9566         0,
   9567         1,
   9568         soc_HOLD_BCM56800_A0r_fields,
   9569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9570         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9571         -1,
   9572         -1,
   9573     },
   9574 #endif /* chips */
   9575 
   9576 #if defined(BCM_56800_A0)
   9577     { /* SOC_REG_INT_HOLD_COS1_Xr */
   9578         soc_block_list[5],
   9579         soc_genreg,
   9580         1,
   9581         0,
   9582         0xe080201,
   9583         SOC_REG_FLAG_ED_CNTR,
   9584         0,
   9585         1,
   9586         soc_HOLDr_fields,
   9587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9588         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9589         -1,
   9590         -1,
   9591     },
   9592 #endif /* chips */
   9593 
   9594 #if defined(BCM_56800_A0)
   9595     { /* SOC_REG_INT_HOLD_COS1_Yr */
   9596         soc_block_list[5],
   9597         soc_genreg,
   9598         1,
   9599         0,
   9600         0xe080401,
   9601         SOC_REG_FLAG_ED_CNTR,
   9602         0,
   9603         1,
   9604         soc_HOLDr_fields,
   9605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9606         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9607         -1,
   9608         -1,
   9609     },
   9610 #endif /* chips */
   9611 
   9612 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   9613     defined(BCM_56160_A0)
   9614     { /* SOC_REG_INT_HOLD_COS2_BCM53400_A0r */
   9615         soc_block_list[5],
   9616         soc_genreg,
   9617         1,
   9618         0,
   9619         0x42005d00,
   9620         SOC_REG_FLAG_COUNTER |
   9621                           SOC_REG_FLAG_ED_CNTR,
   9622         0,
   9623         1,
   9624         soc_EGR_ECN_COUNTERr_fields,
   9625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9626         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9627         93,
   9628         -1,
   9629     },
   9630 #endif /* chips */
   9631 
   9632 #if defined(BCM_53570_A0)
   9633     { /* SOC_REG_INT_HOLD_COS2_BCM53570_A0r */
   9634         soc_block_list[5],
   9635         soc_genreg,
   9636         1,
   9637         0,
   9638         0x42008f00,
   9639         SOC_REG_FLAG_COUNTER |
   9640                           SOC_REG_FLAG_ED_CNTR,
   9641         0,
   9642         1,
   9643         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
   9644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9646         143,
   9647         -1,
   9648     },
   9649 #endif /* chips */
   9650 
   9651 #if defined(BCM_56142_A0)
   9652     { /* SOC_REG_INT_HOLD_COS2_BCM56142_A0r */
   9653         soc_block_list[5],
   9654         soc_genreg,
   9655         1,
   9656         0,
   9657         0x11080052,
   9658         SOC_REG_FLAG_COUNTER |
   9659                           SOC_REG_FLAG_ED_CNTR,
   9660         0,
   9661         1,
   9662         soc_HOLDr_fields,
   9663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9664         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9665         82,
   9666         -1,
   9667     },
   9668 #endif /* chips */
   9669 
   9670 #if defined(BCM_56150_A0)
   9671     { /* SOC_REG_INT_HOLD_COS2_BCM56150_A0r */
   9672         soc_block_list[5],
   9673         soc_genreg,
   9674         1,
   9675         0,
   9676         0x46005d00,
   9677         SOC_REG_FLAG_COUNTER |
   9678                           SOC_REG_FLAG_ED_CNTR,
   9679         0,
   9680         1,
   9681         soc_TPCE_BCM56450_A0r_fields,
   9682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9683         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9684         93,
   9685         -1,
   9686     },
   9687 #endif /* chips */
   9688 
   9689 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9690     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9691     { /* SOC_REG_INT_HOLD_COS2_BCM56224_A0r */
   9692         soc_block_list[5],
   9693         soc_genreg,
   9694         1,
   9695         0,
   9696         0xf080017,
   9697         SOC_REG_FLAG_ED_CNTR,
   9698         0,
   9699         1,
   9700         soc_HOLDr_fields,
   9701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9702         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9703         -1,
   9704         -1,
   9705     },
   9706 #endif /* chips */
   9707 
   9708 #if defined(BCM_56800_A0)
   9709     { /* SOC_REG_INT_HOLD_COS2_BCM56800_A0r */
   9710         soc_block_list[5],
   9711         soc_genreg,
   9712         1,
   9713         0,
   9714         0xe080c02,
   9715         SOC_REG_FLAG_ED_CNTR,
   9716         0,
   9717         1,
   9718         soc_HOLD_BCM56800_A0r_fields,
   9719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9720         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9721         -1,
   9722         -1,
   9723     },
   9724 #endif /* chips */
   9725 
   9726 #if defined(BCM_56800_A0)
   9727     { /* SOC_REG_INT_HOLD_COS2_Xr */
   9728         soc_block_list[5],
   9729         soc_genreg,
   9730         1,
   9731         0,
   9732         0xe080202,
   9733         SOC_REG_FLAG_ED_CNTR,
   9734         0,
   9735         1,
   9736         soc_HOLDr_fields,
   9737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9738         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9739         -1,
   9740         -1,
   9741     },
   9742 #endif /* chips */
   9743 
   9744 #if defined(BCM_56800_A0)
   9745     { /* SOC_REG_INT_HOLD_COS2_Yr */
   9746         soc_block_list[5],
   9747         soc_genreg,
   9748         1,
   9749         0,
   9750         0xe080402,
   9751         SOC_REG_FLAG_ED_CNTR,
   9752         0,
   9753         1,
   9754         soc_HOLDr_fields,
   9755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9756         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9757         -1,
   9758         -1,
   9759     },
   9760 #endif /* chips */
   9761 
   9762 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   9763     defined(BCM_56160_A0)
   9764     { /* SOC_REG_INT_HOLD_COS3_BCM53400_A0r */
   9765         soc_block_list[5],
   9766         soc_genreg,
   9767         1,
   9768         0,
   9769         0x42005e00,
   9770         SOC_REG_FLAG_COUNTER |
   9771                           SOC_REG_FLAG_ED_CNTR,
   9772         0,
   9773         1,
   9774         soc_EGR_ECN_COUNTERr_fields,
   9775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9776         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9777         94,
   9778         -1,
   9779     },
   9780 #endif /* chips */
   9781 
   9782 #if defined(BCM_53570_A0)
   9783     { /* SOC_REG_INT_HOLD_COS3_BCM53570_A0r */
   9784         soc_block_list[5],
   9785         soc_genreg,
   9786         1,
   9787         0,
   9788         0x42009000,
   9789         SOC_REG_FLAG_COUNTER |
   9790                           SOC_REG_FLAG_ED_CNTR,
   9791         0,
   9792         1,
   9793         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
   9794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9796         144,
   9797         -1,
   9798     },
   9799 #endif /* chips */
   9800 
   9801 #if defined(BCM_56142_A0)
   9802     { /* SOC_REG_INT_HOLD_COS3_BCM56142_A0r */
   9803         soc_block_list[5],
   9804         soc_genreg,
   9805         1,
   9806         0,
   9807         0x11080053,
   9808         SOC_REG_FLAG_COUNTER |
   9809                           SOC_REG_FLAG_ED_CNTR,
   9810         0,
   9811         1,
   9812         soc_HOLDr_fields,
   9813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9814         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9815         83,
   9816         -1,
   9817     },
   9818 #endif /* chips */
   9819 
   9820 #if defined(BCM_56150_A0)
   9821     { /* SOC_REG_INT_HOLD_COS3_BCM56150_A0r */
   9822         soc_block_list[5],
   9823         soc_genreg,
   9824         1,
   9825         0,
   9826         0x46005e00,
   9827         SOC_REG_FLAG_COUNTER |
   9828                           SOC_REG_FLAG_ED_CNTR,
   9829         0,
   9830         1,
   9831         soc_TPCE_BCM56450_A0r_fields,
   9832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9833         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9834         94,
   9835         -1,
   9836     },
   9837 #endif /* chips */
   9838 
   9839 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9840     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9841     { /* SOC_REG_INT_HOLD_COS3_BCM56224_A0r */
   9842         soc_block_list[5],
   9843         soc_genreg,
   9844         1,
   9845         0,
   9846         0xf080018,
   9847         SOC_REG_FLAG_ED_CNTR,
   9848         0,
   9849         1,
   9850         soc_HOLDr_fields,
   9851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9852         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9853         -1,
   9854         -1,
   9855     },
   9856 #endif /* chips */
   9857 
   9858 #if defined(BCM_56800_A0)
   9859     { /* SOC_REG_INT_HOLD_COS3_BCM56800_A0r */
   9860         soc_block_list[5],
   9861         soc_genreg,
   9862         1,
   9863         0,
   9864         0xe080c03,
   9865         SOC_REG_FLAG_ED_CNTR,
   9866         0,
   9867         1,
   9868         soc_HOLD_BCM56800_A0r_fields,
   9869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9870         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9871         -1,
   9872         -1,
   9873     },
   9874 #endif /* chips */
   9875 
   9876 #if defined(BCM_56800_A0)
   9877     { /* SOC_REG_INT_HOLD_COS3_Xr */
   9878         soc_block_list[5],
   9879         soc_genreg,
   9880         1,
   9881         0,
   9882         0xe080203,
   9883         SOC_REG_FLAG_ED_CNTR,
   9884         0,
   9885         1,
   9886         soc_HOLDr_fields,
   9887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9888         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9889         -1,
   9890         -1,
   9891     },
   9892 #endif /* chips */
   9893 
   9894 #if defined(BCM_56800_A0)
   9895     { /* SOC_REG_INT_HOLD_COS3_Yr */
   9896         soc_block_list[5],
   9897         soc_genreg,
   9898         1,
   9899         0,
   9900         0xe080403,
   9901         SOC_REG_FLAG_ED_CNTR,
   9902         0,
   9903         1,
   9904         soc_HOLDr_fields,
   9905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9906         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9907         -1,
   9908         -1,
   9909     },
   9910 #endif /* chips */
   9911 
   9912 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   9913     defined(BCM_56160_A0)
   9914     { /* SOC_REG_INT_HOLD_COS4_BCM53400_A0r */
   9915         soc_block_list[5],
   9916         soc_genreg,
   9917         1,
   9918         0,
   9919         0x42005f00,
   9920         SOC_REG_FLAG_COUNTER |
   9921                           SOC_REG_FLAG_ED_CNTR,
   9922         0,
   9923         1,
   9924         soc_EGR_ECN_COUNTERr_fields,
   9925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9926         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9927         95,
   9928         -1,
   9929     },
   9930 #endif /* chips */
   9931 
   9932 #if defined(BCM_53570_A0)
   9933     { /* SOC_REG_INT_HOLD_COS4_BCM53570_A0r */
   9934         soc_block_list[5],
   9935         soc_genreg,
   9936         1,
   9937         0,
   9938         0x42009100,
   9939         SOC_REG_FLAG_COUNTER |
   9940                           SOC_REG_FLAG_ED_CNTR,
   9941         0,
   9942         1,
   9943         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
   9944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9946         145,
   9947         -1,
   9948     },
   9949 #endif /* chips */
   9950 
   9951 #if defined(BCM_56142_A0)
   9952     { /* SOC_REG_INT_HOLD_COS4_BCM56142_A0r */
   9953         soc_block_list[5],
   9954         soc_genreg,
   9955         1,
   9956         0,
   9957         0x11080054,
   9958         SOC_REG_FLAG_COUNTER |
   9959                           SOC_REG_FLAG_ED_CNTR,
   9960         0,
   9961         1,
   9962         soc_HOLDr_fields,
   9963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9964         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9965         84,
   9966         -1,
   9967     },
   9968 #endif /* chips */
   9969 
   9970 #if defined(BCM_56150_A0)
   9971     { /* SOC_REG_INT_HOLD_COS4_BCM56150_A0r */
   9972         soc_block_list[5],
   9973         soc_genreg,
   9974         1,
   9975         0,
   9976         0x46005f00,
   9977         SOC_REG_FLAG_COUNTER |
   9978                           SOC_REG_FLAG_ED_CNTR,
   9979         0,
   9980         1,
   9981         soc_TPCE_BCM56450_A0r_fields,
   9982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9983         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9984         95,
   9985         -1,
   9986     },
   9987 #endif /* chips */
   9988 
   9989 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9990     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9991     { /* SOC_REG_INT_HOLD_COS4_BCM56224_A0r */
   9992         soc_block_list[5],
   9993         soc_genreg,
   9994         1,
   9995         0,
   9996         0xf080019,
   9997         SOC_REG_FLAG_ED_CNTR,
   9998         0,
   9999         1,
  10000         soc_HOLDr_fields,
  10001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10002         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10003         -1,
  10004         -1,
  10005     },
  10006 #endif /* chips */
  10007 
  10008 #if defined(BCM_56800_A0)
  10009     { /* SOC_REG_INT_HOLD_COS4_BCM56800_A0r */
  10010         soc_block_list[5],
  10011         soc_genreg,
  10012         1,
  10013         0,
  10014         0xe080c04,
  10015         SOC_REG_FLAG_ED_CNTR,
  10016         0,
  10017         1,
  10018         soc_HOLD_BCM56800_A0r_fields,
  10019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10020         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10021         -1,
  10022         -1,
  10023     },
  10024 #endif /* chips */
  10025 
  10026 #if defined(BCM_56800_A0)
  10027     { /* SOC_REG_INT_HOLD_COS4_Xr */
  10028         soc_block_list[5],
  10029         soc_genreg,
  10030         1,
  10031         0,
  10032         0xe080204,
  10033         SOC_REG_FLAG_ED_CNTR,
  10034         0,
  10035         1,
  10036         soc_HOLDr_fields,
  10037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10038         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10039         -1,
  10040         -1,
  10041     },
  10042 #endif /* chips */
  10043 
  10044 #if defined(BCM_56800_A0)
  10045     { /* SOC_REG_INT_HOLD_COS4_Yr */
  10046         soc_block_list[5],
  10047         soc_genreg,
  10048         1,
  10049         0,
  10050         0xe080404,
  10051         SOC_REG_FLAG_ED_CNTR,
  10052         0,
  10053         1,
  10054         soc_HOLDr_fields,
  10055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10056         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10057         -1,
  10058         -1,
  10059     },
  10060 #endif /* chips */
  10061 
  10062 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  10063     defined(BCM_56160_A0)
  10064     { /* SOC_REG_INT_HOLD_COS5_BCM53400_A0r */
  10065         soc_block_list[5],
  10066         soc_genreg,
  10067         1,
  10068         0,
  10069         0x42006000,
  10070         SOC_REG_FLAG_COUNTER |
  10071                           SOC_REG_FLAG_ED_CNTR,
  10072         0,
  10073         1,
  10074         soc_EGR_ECN_COUNTERr_fields,
  10075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10076         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10077         96,
  10078         -1,
  10079     },
  10080 #endif /* chips */
  10081 
  10082 #if defined(BCM_53570_A0)
  10083     { /* SOC_REG_INT_HOLD_COS5_BCM53570_A0r */
  10084         soc_block_list[5],
  10085         soc_genreg,
  10086         1,
  10087         0,
  10088         0x42009200,
  10089         SOC_REG_FLAG_COUNTER |
  10090                           SOC_REG_FLAG_ED_CNTR,
  10091         0,
  10092         1,
  10093         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  10094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10096         146,
  10097         -1,
  10098     },
  10099 #endif /* chips */
  10100 
  10101 #if defined(BCM_56142_A0)
  10102     { /* SOC_REG_INT_HOLD_COS5_BCM56142_A0r */
  10103         soc_block_list[5],
  10104         soc_genreg,
  10105         1,
  10106         0,
  10107         0x11080055,
  10108         SOC_REG_FLAG_COUNTER |
  10109                           SOC_REG_FLAG_ED_CNTR,
  10110         0,
  10111         1,
  10112         soc_HOLDr_fields,
  10113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10114         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10115         85,
  10116         -1,
  10117     },
  10118 #endif /* chips */
  10119 
  10120 #if defined(BCM_56150_A0)
  10121     { /* SOC_REG_INT_HOLD_COS5_BCM56150_A0r */
  10122         soc_block_list[5],
  10123         soc_genreg,
  10124         1,
  10125         0,
  10126         0x46006000,
  10127         SOC_REG_FLAG_COUNTER |
  10128                           SOC_REG_FLAG_ED_CNTR,
  10129         0,
  10130         1,
  10131         soc_TPCE_BCM56450_A0r_fields,
  10132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10133         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10134         96,
  10135         -1,
  10136     },
  10137 #endif /* chips */
  10138 
  10139 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  10140     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10141     { /* SOC_REG_INT_HOLD_COS5_BCM56224_A0r */
  10142         soc_block_list[5],
  10143         soc_genreg,
  10144         1,
  10145         0,
  10146         0xf08001a,
  10147         SOC_REG_FLAG_ED_CNTR,
  10148         0,
  10149         1,
  10150         soc_HOLDr_fields,
  10151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10152         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10153         -1,
  10154         -1,
  10155     },
  10156 #endif /* chips */
  10157 
  10158 #if defined(BCM_56800_A0)
  10159     { /* SOC_REG_INT_HOLD_COS5_BCM56800_A0r */
  10160         soc_block_list[5],
  10161         soc_genreg,
  10162         1,
  10163         0,
  10164         0xe080c05,
  10165         SOC_REG_FLAG_ED_CNTR,
  10166         0,
  10167         1,
  10168         soc_HOLD_BCM56800_A0r_fields,
  10169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10170         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10171         -1,
  10172         -1,
  10173     },
  10174 #endif /* chips */
  10175 
  10176 #if defined(BCM_56800_A0)
  10177     { /* SOC_REG_INT_HOLD_COS5_Xr */
  10178         soc_block_list[5],
  10179         soc_genreg,
  10180         1,
  10181         0,
  10182         0xe080205,
  10183         SOC_REG_FLAG_ED_CNTR,
  10184         0,
  10185         1,
  10186         soc_HOLDr_fields,
  10187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10188         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10189         -1,
  10190         -1,
  10191     },
  10192 #endif /* chips */
  10193 
  10194 #if defined(BCM_56800_A0)
  10195     { /* SOC_REG_INT_HOLD_COS5_Yr */
  10196         soc_block_list[5],
  10197         soc_genreg,
  10198         1,
  10199         0,
  10200         0xe080405,
  10201         SOC_REG_FLAG_ED_CNTR,
  10202         0,
  10203         1,
  10204         soc_HOLDr_fields,
  10205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10206         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10207         -1,
  10208         -1,
  10209     },
  10210 #endif /* chips */
  10211 
  10212 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  10213     defined(BCM_56160_A0)
  10214     { /* SOC_REG_INT_HOLD_COS6_BCM53400_A0r */
  10215         soc_block_list[5],
  10216         soc_genreg,
  10217         1,
  10218         0,
  10219         0x42006100,
  10220         SOC_REG_FLAG_COUNTER |
  10221                           SOC_REG_FLAG_ED_CNTR,
  10222         0,
  10223         1,
  10224         soc_EGR_ECN_COUNTERr_fields,
  10225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10226         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10227         97,
  10228         -1,
  10229     },
  10230 #endif /* chips */
  10231 
  10232 #if defined(BCM_53570_A0)
  10233     { /* SOC_REG_INT_HOLD_COS6_BCM53570_A0r */
  10234         soc_block_list[5],
  10235         soc_genreg,
  10236         1,
  10237         0,
  10238         0x42009300,
  10239         SOC_REG_FLAG_COUNTER |
  10240                           SOC_REG_FLAG_ED_CNTR,
  10241         0,
  10242         1,
  10243         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  10244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10246         147,
  10247         -1,
  10248     },
  10249 #endif /* chips */
  10250 
  10251 #if defined(BCM_56142_A0)
  10252     { /* SOC_REG_INT_HOLD_COS6_BCM56142_A0r */
  10253         soc_block_list[5],
  10254         soc_genreg,
  10255         1,
  10256         0,
  10257         0x11080056,
  10258         SOC_REG_FLAG_COUNTER |
  10259                           SOC_REG_FLAG_ED_CNTR,
  10260         0,
  10261         1,
  10262         soc_HOLDr_fields,
  10263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10264         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10265         86,
  10266         -1,
  10267     },
  10268 #endif /* chips */
  10269 
  10270 #if defined(BCM_56150_A0)
  10271     { /* SOC_REG_INT_HOLD_COS6_BCM56150_A0r */
  10272         soc_block_list[5],
  10273         soc_genreg,
  10274         1,
  10275         0,
  10276         0x46006100,
  10277         SOC_REG_FLAG_COUNTER |
  10278                           SOC_REG_FLAG_ED_CNTR,
  10279         0,
  10280         1,
  10281         soc_TPCE_BCM56450_A0r_fields,
  10282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10283         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10284         97,
  10285         -1,
  10286     },
  10287 #endif /* chips */
  10288 
  10289 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  10290     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10291     { /* SOC_REG_INT_HOLD_COS6_BCM56224_A0r */
  10292         soc_block_list[5],
  10293         soc_genreg,
  10294         1,
  10295         0,
  10296         0xf08001b,
  10297         SOC_REG_FLAG_ED_CNTR,
  10298         0,
  10299         1,
  10300         soc_HOLDr_fields,
  10301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10302         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10303         -1,
  10304         -1,
  10305     },
  10306 #endif /* chips */
  10307 
  10308 #if defined(BCM_56800_A0)
  10309     { /* SOC_REG_INT_HOLD_COS6_BCM56800_A0r */
  10310         soc_block_list[5],
  10311         soc_genreg,
  10312         1,
  10313         0,
  10314         0xe080c06,
  10315         SOC_REG_FLAG_ED_CNTR,
  10316         0,
  10317         1,
  10318         soc_HOLD_BCM56800_A0r_fields,
  10319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10321         -1,
  10322         -1,
  10323     },
  10324 #endif /* chips */
  10325 
  10326 #if defined(BCM_56800_A0)
  10327     { /* SOC_REG_INT_HOLD_COS6_Xr */
  10328         soc_block_list[5],
  10329         soc_genreg,
  10330         1,
  10331         0,
  10332         0xe080206,
  10333         SOC_REG_FLAG_ED_CNTR,
  10334         0,
  10335         1,
  10336         soc_HOLDr_fields,
  10337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10338         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10339         -1,
  10340         -1,
  10341     },
  10342 #endif /* chips */
  10343 
  10344 #if defined(BCM_56800_A0)
  10345     { /* SOC_REG_INT_HOLD_COS6_Yr */
  10346         soc_block_list[5],
  10347         soc_genreg,
  10348         1,
  10349         0,
  10350         0xe080406,
  10351         SOC_REG_FLAG_ED_CNTR,
  10352         0,
  10353         1,
  10354         soc_HOLDr_fields,
  10355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10356         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10357         -1,
  10358         -1,
  10359     },
  10360 #endif /* chips */
  10361 
  10362 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  10363     defined(BCM_56160_A0)
  10364     { /* SOC_REG_INT_HOLD_COS7_BCM53400_A0r */
  10365         soc_block_list[5],
  10366         soc_genreg,
  10367         1,
  10368         0,
  10369         0x42006200,
  10370         SOC_REG_FLAG_COUNTER |
  10371                           SOC_REG_FLAG_ED_CNTR,
  10372         0,
  10373         1,
  10374         soc_EGR_ECN_COUNTERr_fields,
  10375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10376         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10377         98,
  10378         -1,
  10379     },
  10380 #endif /* chips */
  10381 
  10382 #if defined(BCM_53570_A0)
  10383     { /* SOC_REG_INT_HOLD_COS7_BCM53570_A0r */
  10384         soc_block_list[5],
  10385         soc_genreg,
  10386         1,
  10387         0,
  10388         0x42009400,
  10389         SOC_REG_FLAG_COUNTER |
  10390                           SOC_REG_FLAG_ED_CNTR,
  10391         0,
  10392         1,
  10393         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  10394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10395         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10396         148,
  10397         -1,
  10398     },
  10399 #endif /* chips */
  10400 
  10401 #if defined(BCM_56142_A0)
  10402     { /* SOC_REG_INT_HOLD_COS7_BCM56142_A0r */
  10403         soc_block_list[5],
  10404         soc_genreg,
  10405         1,
  10406         0,
  10407         0x11080057,
  10408         SOC_REG_FLAG_COUNTER |
  10409                           SOC_REG_FLAG_ED_CNTR,
  10410         0,
  10411         1,
  10412         soc_HOLDr_fields,
  10413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10414         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10415         87,
  10416         -1,
  10417     },
  10418 #endif /* chips */
  10419 
  10420 #if defined(BCM_56150_A0)
  10421     { /* SOC_REG_INT_HOLD_COS7_BCM56150_A0r */
  10422         soc_block_list[5],
  10423         soc_genreg,
  10424         1,
  10425         0,
  10426         0x46006200,
  10427         SOC_REG_FLAG_COUNTER |
  10428                           SOC_REG_FLAG_ED_CNTR,
  10429         0,
  10430         1,
  10431         soc_TPCE_BCM56450_A0r_fields,
  10432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10433         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10434         98,
  10435         -1,
  10436     },
  10437 #endif /* chips */
  10438 
  10439 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  10440     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10441     { /* SOC_REG_INT_HOLD_COS7_BCM56224_A0r */
  10442         soc_block_list[5],
  10443         soc_genreg,
  10444         1,
  10445         0,
  10446         0xf08001c,
  10447         SOC_REG_FLAG_ED_CNTR,
  10448         0,
  10449         1,
  10450         soc_HOLDr_fields,
  10451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10452         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10453         -1,
  10454         -1,
  10455     },
  10456 #endif /* chips */
  10457 
  10458 #if defined(BCM_56800_A0)
  10459     { /* SOC_REG_INT_HOLD_COS7_BCM56800_A0r */
  10460         soc_block_list[5],
  10461         soc_genreg,
  10462         1,
  10463         0,
  10464         0xe080c07,
  10465         SOC_REG_FLAG_ED_CNTR,
  10466         0,
  10467         1,
  10468         soc_HOLD_BCM56800_A0r_fields,
  10469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10470         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10471         -1,
  10472         -1,
  10473     },
  10474 #endif /* chips */
  10475 
  10476 #if defined(BCM_56800_A0)
  10477     { /* SOC_REG_INT_HOLD_COS7_Xr */
  10478         soc_block_list[5],
  10479         soc_genreg,
  10480         1,
  10481         0,
  10482         0xe080207,
  10483         SOC_REG_FLAG_ED_CNTR,
  10484         0,
  10485         1,
  10486         soc_HOLDr_fields,
  10487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10488         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10489         -1,
  10490         -1,
  10491     },
  10492 #endif /* chips */
  10493 
  10494 #if defined(BCM_56800_A0)
  10495     { /* SOC_REG_INT_HOLD_COS7_Yr */
  10496         soc_block_list[5],
  10497         soc_genreg,
  10498         1,
  10499         0,
  10500         0xe080407,
  10501         SOC_REG_FLAG_ED_CNTR,
  10502         0,
  10503         1,
  10504         soc_HOLDr_fields,
  10505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10506         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10507         -1,
  10508         -1,
  10509     },
  10510 #endif /* chips */
  10511 
  10512 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  10513     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  10514     { /* SOC_REG_INT_HOLD_COS_PORT_SELECTr */
  10515         soc_block_list[5],
  10516         soc_genreg,
  10517         1,
  10518         0,
  10519         0xe080118,
  10520         0,
  10521         0,
  10522         1,
  10523         soc_HOLD_COS_PORT_SELECTr_fields,
  10524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10525         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10526         -1,
  10527         -1,
  10528     },
  10529 #endif /* chips */
  10530 
  10531 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  10532     defined(BCM_56160_A0)
  10533     { /* SOC_REG_INT_HOLD_COS_PORT_SELECT_BCM53400_A0r */
  10534         soc_block_list[5],
  10535         soc_genreg,
  10536         1,
  10537         0,
  10538         0x42006800,
  10539         0,
  10540         0,
  10541         1,
  10542         soc_HOLD_COS_PORT_SELECT_BCM53400_A0r_fields,
  10543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10544         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10545         -1,
  10546         -1,
  10547     },
  10548 #endif /* chips */
  10549 
  10550 #if defined(BCM_53570_A0)
  10551     { /* SOC_REG_INT_HOLD_COS_PORT_SELECT_BCM53570_A0r */
  10552         soc_block_list[5],
  10553         soc_genreg,
  10554         1,
  10555         0,
  10556         0x42009900,
  10557         0,
  10558         0,
  10559         1,
  10560         soc_HOLD_COS_PORT_SELECT_BCM53570_A0r_fields,
  10561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10562         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  10563         -1,
  10564         -1,
  10565     },
  10566 #endif /* chips */
  10567 
  10568 #if defined(BCM_56142_A0)
  10569     { /* SOC_REG_INT_HOLD_COS_PORT_SELECT_BCM56142_A0r */
  10570         soc_block_list[5],
  10571         soc_genreg,
  10572         1,
  10573         0,
  10574         0x110800a7,
  10575         0,
  10576         0,
  10577         1,
  10578         soc_HOLD_COS_PORT_SELECTr_fields,
  10579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10580         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10581         -1,
  10582         -1,
  10583     },
  10584 #endif /* chips */
  10585 
  10586 #if defined(BCM_56150_A0)
  10587     { /* SOC_REG_INT_HOLD_COS_PORT_SELECT_BCM56150_A0r */
  10588         soc_block_list[5],
  10589         soc_genreg,
  10590         1,
  10591         0,
  10592         0x46006800,
  10593         0,
  10594         0,
  10595         1,
  10596         soc_HOLD_COS_PORT_SELECT_BCM56150_A0r_fields,
  10597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10598         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10599         -1,
  10600         -1,
  10601     },
  10602 #endif /* chips */
  10603 
  10604 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  10605     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10606     { /* SOC_REG_INT_HOLD_COS_PORT_SELECT_BCM56224_A0r */
  10607         soc_block_list[5],
  10608         soc_genreg,
  10609         1,
  10610         0,
  10611         0xf080128,
  10612         0,
  10613         0,
  10614         1,
  10615         soc_HOLD_COS_PORT_SELECT_BCM56224_A0r_fields,
  10616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10617         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  10618         -1,
  10619         -1,
  10620     },
  10621 #endif /* chips */
  10622 
  10623 #if defined(BCM_56800_A0)
  10624     { /* SOC_REG_INT_HOLD_COS_PORT_SELECT_BCM56800_A0r */
  10625         soc_block_list[5],
  10626         soc_genreg,
  10627         1,
  10628         0,
  10629         0xe080622,
  10630         0,
  10631         0,
  10632         1,
  10633         soc_HOLD_COS_PORT_SELECTr_fields,
  10634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10635         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10636         -1,
  10637         -1,
  10638     },
  10639 #endif /* chips */
  10640 
  10641 #if defined(BCM_56800_A0)
  10642     { /* SOC_REG_INT_HOLD_COS_QMr */
  10643         soc_block_list[5],
  10644         soc_genreg,
  10645         1,
  10646         0,
  10647         0xe080c09,
  10648         SOC_REG_FLAG_ED_CNTR,
  10649         0,
  10650         1,
  10651         soc_HOLD_BCM56800_A0r_fields,
  10652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10654         -1,
  10655         -1,
  10656     },
  10657 #endif /* chips */
  10658 
  10659 #if defined(BCM_56800_A0)
  10660     { /* SOC_REG_INT_HOLD_COS_QM_Xr */
  10661         soc_block_list[5],
  10662         soc_genreg,
  10663         1,
  10664         0,
  10665         0xe080209,
  10666         SOC_REG_FLAG_ED_CNTR,
  10667         0,
  10668         1,
  10669         soc_HOLDr_fields,
  10670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10671         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10672         -1,
  10673         -1,
  10674     },
  10675 #endif /* chips */
  10676 
  10677 #if defined(BCM_56800_A0)
  10678     { /* SOC_REG_INT_HOLD_COS_QM_Yr */
  10679         soc_block_list[5],
  10680         soc_genreg,
  10681         1,
  10682         0,
  10683         0xe080409,
  10684         SOC_REG_FLAG_ED_CNTR,
  10685         0,
  10686         1,
  10687         soc_HOLDr_fields,
  10688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10689         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10690         -1,
  10691         -1,
  10692     },
  10693 #endif /* chips */
  10694 
  10695 #if defined(BCM_56800_A0)
  10696     { /* SOC_REG_INT_HOLD_COS_SCr */
  10697         soc_block_list[5],
  10698         soc_genreg,
  10699         1,
  10700         0,
  10701         0xe080c08,
  10702         SOC_REG_FLAG_ED_CNTR,
  10703         0,
  10704         1,
  10705         soc_HOLD_BCM56800_A0r_fields,
  10706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10707         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10708         -1,
  10709         -1,
  10710     },
  10711 #endif /* chips */
  10712 
  10713 #if defined(BCM_56800_A0)
  10714     { /* SOC_REG_INT_HOLD_COS_SC_Xr */
  10715         soc_block_list[5],
  10716         soc_genreg,
  10717         1,
  10718         0,
  10719         0xe080208,
  10720         SOC_REG_FLAG_ED_CNTR,
  10721         0,
  10722         1,
  10723         soc_HOLDr_fields,
  10724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10725         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10726         -1,
  10727         -1,
  10728     },
  10729 #endif /* chips */
  10730 
  10731 #if defined(BCM_56800_A0)
  10732     { /* SOC_REG_INT_HOLD_COS_SC_Yr */
  10733         soc_block_list[5],
  10734         soc_genreg,
  10735         1,
  10736         0,
  10737         0xe080408,
  10738         SOC_REG_FLAG_ED_CNTR,
  10739         0,
  10740         1,
  10741         soc_HOLDr_fields,
  10742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10743         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10744         -1,
  10745         -1,
  10746     },
  10747 #endif /* chips */
  10748 
  10749 #if defined(BCM_56800_A0)
  10750     { /* SOC_REG_INT_HOLD_Xr */
  10751         soc_block_list[5],
  10752         soc_portreg,
  10753         1,
  10754         0,
  10755         0xe00021c,
  10756         SOC_REG_FLAG_ED_CNTR,
  10757         0,
  10758         1,
  10759         soc_HOLDr_fields,
  10760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10761         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10762         -1,
  10763         -1,
  10764     },
  10765 #endif /* chips */
  10766 
  10767 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  10768     { /* SOC_REG_INT_HOLD_X_BCM56820_A0r */
  10769         soc_block_list[5],
  10770         soc_portreg,
  10771         1,
  10772         0,
  10773         0xf00021c,
  10774         SOC_REG_FLAG_ED_CNTR,
  10775         0,
  10776         1,
  10777         soc_HOLDr_fields,
  10778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10779         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10780         -1,
  10781         -1,
  10782     },
  10783 #endif /* chips */
  10784 
  10785 #if defined(BCM_56800_A0)
  10786     { /* SOC_REG_INT_HOLD_Yr */
  10787         soc_block_list[5],
  10788         soc_portreg,
  10789         1,
  10790         0,
  10791         0xe00041c,
  10792         SOC_REG_FLAG_ED_CNTR,
  10793         0,
  10794         1,
  10795         soc_HOLDr_fields,
  10796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10797         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10798         -1,
  10799         -1,
  10800     },
  10801 #endif /* chips */
  10802 
  10803 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  10804     { /* SOC_REG_INT_HOLD_Y_BCM56820_A0r */
  10805         soc_block_list[5],
  10806         soc_portreg,
  10807         1,
  10808         0,
  10809         0xf00041c,
  10810         SOC_REG_FLAG_ED_CNTR,
  10811         0,
  10812         1,
  10813         soc_HOLDr_fields,
  10814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10815         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  10816         -1,
  10817         -1,
  10818     },
  10819 #endif /* chips */
  10820 
  10821 #if defined(BCM_56150_A0)
  10822     { /* SOC_REG_INT_HOL_DROPr */
  10823         soc_block_list[5],
  10824         soc_portreg,
  10825         1,
  10826         0,
  10827         0x44005100,
  10828         SOC_REG_FLAG_COUNTER |
  10829                           SOC_REG_FLAG_ED_CNTR,
  10830         0,
  10831         1,
  10832         soc_HOL_DROPr_fields,
  10833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10835         81,
  10836         -1,
  10837     },
  10838 #endif /* chips */
  10839 
  10840 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  10841     defined(BCM_56160_A0)
  10842     { /* SOC_REG_INT_HOL_DROP_BCM53400_A0r */
  10843         soc_block_list[5],
  10844         soc_portreg,
  10845         1,
  10846         0,
  10847         0x40005100,
  10848         SOC_REG_FLAG_COUNTER |
  10849                           SOC_REG_FLAG_ED_CNTR,
  10850         0,
  10851         1,
  10852         soc_HOL_DROP_BCM53400_A0r_fields,
  10853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10855         81,
  10856         -1,
  10857     },
  10858 #endif /* chips */
  10859 
  10860 #if defined(BCM_53570_A0)
  10861     { /* SOC_REG_INT_HOL_DROP_BCM53570_A0r */
  10862         soc_block_list[5],
  10863         soc_portreg,
  10864         1,
  10865         0,
  10866         0x40008900,
  10867         SOC_REG_FLAG_COUNTER |
  10868                           SOC_REG_FLAG_ED_CNTR,
  10869         0,
  10870         1,
  10871         soc_EP_NUM_NORM_CELLS_RECVD_BCM56260_A0r_fields,
  10872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10874         137,
  10875         -1,
  10876     },
  10877 #endif /* chips */
  10878 
  10879 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  10880     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  10881     { /* SOC_REG_INT_HOL_STAT_BMAPr */
  10882         soc_block_list[5],
  10883         soc_genreg,
  10884         8,
  10885         0,
  10886         0xe08010d,
  10887         SOC_REG_FLAG_ARRAY,
  10888         0,
  10889         1,
  10890         soc_BKP_DISC_BMAPr_fields,
  10891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10892         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10893         -1,
  10894         -1,
  10895     },
  10896 #endif /* chips */
  10897 
  10898 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  10899     { /* SOC_REG_INT_HOL_STAT_BMAP_BCM53314_A0r */
  10900         soc_block_list[5],
  10901         soc_genreg,
  10902         8,
  10903         0,
  10904         0xf080114,
  10905         SOC_REG_FLAG_ARRAY,
  10906         0,
  10907         1,
  10908         soc_BKP_DISC_BMAP_BCM53314_A0r_fields,
  10909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10910         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10911         -1,
  10912         -1,
  10913     },
  10914 #endif /* chips */
  10915 
  10916 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10917     { /* SOC_REG_INT_HOL_STAT_BMAP_BCM56224_A0r */
  10918         soc_block_list[5],
  10919         soc_genreg,
  10920         8,
  10921         0,
  10922         0xf080114,
  10923         SOC_REG_FLAG_ARRAY,
  10924         0,
  10925         1,
  10926         soc_BKP_DISC_BMAP_BCM56224_A0r_fields,
  10927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10928         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10929         -1,
  10930         -1,
  10931     },
  10932 #endif /* chips */
  10933 
  10934 #if defined(BCM_56800_A0)
  10935     { /* SOC_REG_INT_HOL_STAT_BMAP_BCM56800_A0r */
  10936         soc_block_list[5],
  10937         soc_genreg,
  10938         10,
  10939         0,
  10940         0xe080614,
  10941         SOC_REG_FLAG_ARRAY,
  10942         0,
  10943         1,
  10944         soc_HOL_STAT_BMAPr_fields,
  10945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10946         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10947         -1,
  10948         -1,
  10949     },
  10950 #endif /* chips */
  10951 
  10952 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10953     { /* SOC_REG_INT_HOL_STAT_BMAP_HIr */
  10954         soc_block_list[5],
  10955         soc_genreg,
  10956         8,
  10957         0,
  10958         0xf08011c,
  10959         SOC_REG_FLAG_ARRAY,
  10960         0,
  10961         1,
  10962         soc_BKP_DISC_BMAP_HIr_fields,
  10963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10964         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10965         -1,
  10966         -1,
  10967     },
  10968 #endif /* chips */
  10969 
  10970 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  10971     { /* SOC_REG_INT_HOL_STAT_BMAP_HI_BCM53314_A0r */
  10972         soc_block_list[5],
  10973         soc_genreg,
  10974         8,
  10975         0,
  10976         0xf08011c,
  10977         SOC_REG_FLAG_ARRAY,
  10978         0,
  10979         1,
  10980         soc_BKP_DISC_BMAP_HIr_fields,
  10981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10982         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10983         -1,
  10984         -1,
  10985     },
  10986 #endif /* chips */
  10987 
  10988 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  10989     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10990     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  10991     { /* SOC_REG_INT_HOL_STAT_CPUr */
  10992         soc_block_list[5],
  10993         soc_genreg,
  10994         1,
  10995         0,
  10996         0x11080022,
  10997         SOC_REG_FLAG_64_BITS,
  10998         0,
  10999         3,
  11000         soc_HOL_STAT_CPUr_fields,
  11001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11002         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11003         -1,
  11004         -1,
  11005     },
  11006 #endif /* chips */
  11007 
  11008 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  11009     defined(BCM_56160_A0)
  11010     { /* SOC_REG_INT_HOL_STAT_CPU_BCM53400_A0r */
  11011         soc_block_list[5],
  11012         soc_genreg,
  11013         1,
  11014         0,
  11015         0x42002500,
  11016         SOC_REG_FLAG_64_BITS,
  11017         0,
  11018         2,
  11019         soc_HOL_STAT_CPU_BCM53400_A0r_fields,
  11020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11021         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11022         -1,
  11023         -1,
  11024     },
  11025 #endif /* chips */
  11026 
  11027 #if defined(BCM_53570_A0)
  11028     { /* SOC_REG_INT_HOL_STAT_CPU_BCM53570_A0r */
  11029         soc_block_list[5],
  11030         soc_genreg,
  11031         1,
  11032         0,
  11033         0x42005600,
  11034         SOC_REG_FLAG_64_BITS,
  11035         0,
  11036         2,
  11037         soc_HOL_STAT_CPU_BCM53400_A0r_fields,
  11038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11040         -1,
  11041         -1,
  11042     },
  11043 #endif /* chips */
  11044 
  11045 #if defined(BCM_53570_B0)
  11046     { /* SOC_REG_INT_HOL_STAT_CPU_BCM53570_B0r */
  11047         soc_block_list[5],
  11048         soc_genreg,
  11049         1,
  11050         0,
  11051         0x42005a00,
  11052         SOC_REG_FLAG_64_BITS,
  11053         0,
  11054         2,
  11055         soc_HOL_STAT_CPU_BCM53400_A0r_fields,
  11056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11057         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11058         -1,
  11059         -1,
  11060     },
  11061 #endif /* chips */
  11062 
  11063 #if defined(BCM_56142_A0)
  11064     { /* SOC_REG_INT_HOL_STAT_CPU_BCM56142_A0r */
  11065         soc_block_list[5],
  11066         soc_genreg,
  11067         1,
  11068         0,
  11069         0x11080089,
  11070         SOC_REG_FLAG_64_BITS,
  11071         0,
  11072         2,
  11073         soc_HOL_STAT_CPU_BCM56142_A0r_fields,
  11074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11075         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11076         -1,
  11077         -1,
  11078     },
  11079 #endif /* chips */
  11080 
  11081 #if defined(BCM_56150_A0)
  11082     { /* SOC_REG_INT_HOL_STAT_CPU_BCM56150_A0r */
  11083         soc_block_list[5],
  11084         soc_genreg,
  11085         1,
  11086         0,
  11087         0x46002500,
  11088         SOC_REG_FLAG_64_BITS,
  11089         0,
  11090         2,
  11091         soc_HOL_STAT_CPU_BCM56150_A0r_fields,
  11092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11093         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11094         -1,
  11095         -1,
  11096     },
  11097 #endif /* chips */
  11098 
  11099 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11100     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11101     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11102     { /* SOC_REG_INT_HOL_STAT_CPU_BCM56634_A0r */
  11103         soc_block_list[5],
  11104         soc_genreg,
  11105         1,
  11106         0,
  11107         0xe080022,
  11108         SOC_REG_FLAG_64_BITS,
  11109         0,
  11110         3,
  11111         soc_HOL_STAT_CPUr_fields,
  11112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11113         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11114         -1,
  11115         -1,
  11116     },
  11117 #endif /* chips */
  11118 
  11119 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11120     { /* SOC_REG_INT_HOL_STAT_CPU_BCM56820_A0r */
  11121         soc_block_list[5],
  11122         soc_genreg,
  11123         1,
  11124         0,
  11125         0xf08006d,
  11126         SOC_REG_FLAG_RO,
  11127         0,
  11128         1,
  11129         soc_HOL_STAT_CPU_BCM56820_A0r_fields,
  11130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11132         -1,
  11133         -1,
  11134     },
  11135 #endif /* chips */
  11136 
  11137 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11138     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  11139     { /* SOC_REG_INT_HOL_STAT_PORTr */
  11140         soc_block_list[5],
  11141         soc_portreg,
  11142         1,
  11143         0,
  11144         0x11000067,
  11145         0,
  11146         0,
  11147         1,
  11148         soc_HOL_STAT_PORTr_fields,
  11149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11150         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11151         -1,
  11152         4,
  11153     },
  11154 #endif /* chips */
  11155 
  11156 #if defined(BCM_53400_A0)
  11157     { /* SOC_REG_INT_HOL_STAT_PORT_BCM53400_A0r */
  11158         soc_block_list[5],
  11159         soc_portreg,
  11160         1,
  11161         0,
  11162         0x40002400,
  11163         0,
  11164         0,
  11165         1,
  11166         soc_HOL_STAT_PORT_BCM53400_A0r_fields,
  11167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11169         -1,
  11170         32,
  11171     },
  11172 #endif /* chips */
  11173 
  11174 #if defined(BCM_53570_A0)
  11175     { /* SOC_REG_INT_HOL_STAT_PORT_BCM53570_A0r */
  11176         soc_block_list[5],
  11177         soc_portreg,
  11178         1,
  11179         0,
  11180         0x40005500,
  11181         0,
  11182         0,
  11183         1,
  11184         soc_HOL_STAT_PORT_BCM53400_A0r_fields,
  11185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11187         -1,
  11188         39,
  11189     },
  11190 #endif /* chips */
  11191 
  11192 #if defined(BCM_53570_B0)
  11193     { /* SOC_REG_INT_HOL_STAT_PORT_BCM53570_B0r */
  11194         soc_block_list[5],
  11195         soc_portreg,
  11196         1,
  11197         0,
  11198         0x40005900,
  11199         0,
  11200         0,
  11201         1,
  11202         soc_HOL_STAT_PORT_BCM53400_A0r_fields,
  11203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11205         -1,
  11206         39,
  11207     },
  11208 #endif /* chips */
  11209 
  11210 #if defined(BCM_56142_A0)
  11211     { /* SOC_REG_INT_HOL_STAT_PORT_BCM56142_A0r */
  11212         soc_block_list[5],
  11213         soc_portreg,
  11214         1,
  11215         0,
  11216         0x11000088,
  11217         0,
  11218         0,
  11219         1,
  11220         soc_HOL_STAT_PORT_BCM56142_A0r_fields,
  11221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11222         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11223         -1,
  11224         32,
  11225     },
  11226 #endif /* chips */
  11227 
  11228 #if defined(BCM_56150_A0)
  11229     { /* SOC_REG_INT_HOL_STAT_PORT_BCM56150_A0r */
  11230         soc_block_list[5],
  11231         soc_portreg,
  11232         1,
  11233         0,
  11234         0x44002400,
  11235         0,
  11236         0,
  11237         1,
  11238         soc_HOL_STAT_PORT_BCM56150_A0r_fields,
  11239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11240         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11241         -1,
  11242         32,
  11243     },
  11244 #endif /* chips */
  11245 
  11246 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  11247     { /* SOC_REG_INT_HOL_STAT_PORT_BCM56160_A0r */
  11248         soc_block_list[5],
  11249         soc_portreg,
  11250         1,
  11251         0,
  11252         0x40002400,
  11253         0,
  11254         0,
  11255         1,
  11256         soc_HOL_STAT_PORT_BCM53400_A0r_fields,
  11257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11258         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11259         -1,
  11260         93,
  11261     },
  11262 #endif /* chips */
  11263 
  11264 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  11265     { /* SOC_REG_INT_HOL_STAT_PORT_BCM56334_A0r */
  11266         soc_block_list[5],
  11267         soc_portreg,
  11268         1,
  11269         0,
  11270         0x11000067,
  11271         0,
  11272         0,
  11273         1,
  11274         soc_HOL_STAT_PORTr_fields,
  11275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11276         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11277         -1,
  11278         32,
  11279     },
  11280 #endif /* chips */
  11281 
  11282 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11283     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11284     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11285     { /* SOC_REG_INT_HOL_STAT_PORT_BCM56634_A0r */
  11286         soc_block_list[5],
  11287         soc_portreg,
  11288         1,
  11289         0,
  11290         0xe000067,
  11291         0,
  11292         0,
  11293         1,
  11294         soc_HOL_STAT_PORTr_fields,
  11295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11296         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11297         -1,
  11298         4,
  11299     },
  11300 #endif /* chips */
  11301 
  11302 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11303     { /* SOC_REG_INT_HOL_STAT_PORT_BCM56820_A0r */
  11304         soc_block_list[5],
  11305         soc_portreg,
  11306         1,
  11307         0,
  11308         0xf00006c,
  11309         SOC_REG_FLAG_RO,
  11310         0,
  11311         1,
  11312         soc_HOL_STAT_PORT_BCM56820_A0r_fields,
  11313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11314         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11315         -1,
  11316         10,
  11317     },
  11318 #endif /* chips */
  11319 
  11320 #if defined(BCM_56970_A0)
  11321     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP0_TBLr */
  11322         soc_block_list[125],
  11323         soc_pipereg,
  11324         12,
  11325         0,
  11326         0x15841800,
  11327         SOC_REG_FLAG_ARRAY |
  11328                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11329         0,
  11330         2,
  11331         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11332         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11333         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11334         -1,
  11335         -1,
  11336         3,
  11337     },
  11338 #endif /* chips */
  11339 
  11340 #if defined(BCM_56370_A0)
  11341     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP0_TBL_BCM56370_A0r */
  11342         soc_block_list[125],
  11343         soc_pipereg,
  11344         12,
  11345         0,
  11346         0x15841a00,
  11347         SOC_REG_FLAG_ARRAY |
  11348                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11349         0,
  11350         2,
  11351         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11352         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11353         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11354         -1,
  11355         -1,
  11356         3,
  11357     },
  11358 #endif /* chips */
  11359 
  11360 #if defined(BCM_56770_A0)
  11361     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP0_TBL_BCM56770_A0r */
  11362         soc_block_list[125],
  11363         soc_pipereg,
  11364         12,
  11365         0,
  11366         0x15841900,
  11367         SOC_REG_FLAG_ARRAY |
  11368                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11369         0,
  11370         2,
  11371         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  11372         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11373         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11374         -1,
  11375         -1,
  11376         3,
  11377     },
  11378 #endif /* chips */
  11379 
  11380 #if defined(BCM_56870_A0)
  11381     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP0_TBL_BCM56870_A0r */
  11382         soc_block_list[125],
  11383         soc_pipereg,
  11384         12,
  11385         0,
  11386         0x15841900,
  11387         SOC_REG_FLAG_ARRAY |
  11388                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11389         0,
  11390         2,
  11391         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11392         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11393         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11394         -1,
  11395         -1,
  11396         3,
  11397     },
  11398 #endif /* chips */
  11399 
  11400 #if defined(BCM_56970_A0)
  11401     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP1_TBLr */
  11402         soc_block_list[125],
  11403         soc_pipereg,
  11404         12,
  11405         0,
  11406         0x15842400,
  11407         SOC_REG_FLAG_ARRAY |
  11408                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11409         0,
  11410         2,
  11411         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11412         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11413         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11414         -1,
  11415         -1,
  11416         3,
  11417     },
  11418 #endif /* chips */
  11419 
  11420 #if defined(BCM_56370_A0)
  11421     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP1_TBL_BCM56370_A0r */
  11422         soc_block_list[125],
  11423         soc_pipereg,
  11424         12,
  11425         0,
  11426         0x15842600,
  11427         SOC_REG_FLAG_ARRAY |
  11428                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11429         0,
  11430         2,
  11431         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11432         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11433         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11434         -1,
  11435         -1,
  11436         3,
  11437     },
  11438 #endif /* chips */
  11439 
  11440 #if defined(BCM_56770_A0)
  11441     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP1_TBL_BCM56770_A0r */
  11442         soc_block_list[125],
  11443         soc_pipereg,
  11444         12,
  11445         0,
  11446         0x15842500,
  11447         SOC_REG_FLAG_ARRAY |
  11448                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11449         0,
  11450         2,
  11451         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  11452         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11453         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11454         -1,
  11455         -1,
  11456         3,
  11457     },
  11458 #endif /* chips */
  11459 
  11460 #if defined(BCM_56870_A0)
  11461     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP1_TBL_BCM56870_A0r */
  11462         soc_block_list[125],
  11463         soc_pipereg,
  11464         12,
  11465         0,
  11466         0x15842500,
  11467         SOC_REG_FLAG_ARRAY |
  11468                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11469         0,
  11470         2,
  11471         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11472         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11473         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11474         -1,
  11475         -1,
  11476         3,
  11477     },
  11478 #endif /* chips */
  11479 
  11480 #if defined(BCM_56970_A0)
  11481     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP2_TBLr */
  11482         soc_block_list[125],
  11483         soc_pipereg,
  11484         12,
  11485         0,
  11486         0x15843000,
  11487         SOC_REG_FLAG_ARRAY |
  11488                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11489         0,
  11490         2,
  11491         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11492         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11493         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11494         -1,
  11495         -1,
  11496         3,
  11497     },
  11498 #endif /* chips */
  11499 
  11500 #if defined(BCM_56370_A0)
  11501     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP2_TBL_BCM56370_A0r */
  11502         soc_block_list[125],
  11503         soc_pipereg,
  11504         12,
  11505         0,
  11506         0x15843200,
  11507         SOC_REG_FLAG_ARRAY |
  11508                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11509         0,
  11510         2,
  11511         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11512         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11513         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11514         -1,
  11515         -1,
  11516         3,
  11517     },
  11518 #endif /* chips */
  11519 
  11520 #if defined(BCM_56770_A0)
  11521     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP2_TBL_BCM56770_A0r */
  11522         soc_block_list[125],
  11523         soc_pipereg,
  11524         12,
  11525         0,
  11526         0x15843100,
  11527         SOC_REG_FLAG_ARRAY |
  11528                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11529         0,
  11530         2,
  11531         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  11532         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11533         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11534         -1,
  11535         -1,
  11536         3,
  11537     },
  11538 #endif /* chips */
  11539 
  11540 #if defined(BCM_56870_A0)
  11541     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP2_TBL_BCM56870_A0r */
  11542         soc_block_list[125],
  11543         soc_pipereg,
  11544         12,
  11545         0,
  11546         0x15843100,
  11547         SOC_REG_FLAG_ARRAY |
  11548                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11549         0,
  11550         2,
  11551         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11552         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11553         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11554         -1,
  11555         -1,
  11556         3,
  11557     },
  11558 #endif /* chips */
  11559 
  11560 #if defined(BCM_56970_A0)
  11561     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP3_TBLr */
  11562         soc_block_list[125],
  11563         soc_pipereg,
  11564         12,
  11565         0,
  11566         0x15843c00,
  11567         SOC_REG_FLAG_ARRAY |
  11568                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11569         0,
  11570         2,
  11571         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11572         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11573         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11574         -1,
  11575         -1,
  11576         3,
  11577     },
  11578 #endif /* chips */
  11579 
  11580 #if defined(BCM_56370_A0)
  11581     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP3_TBL_BCM56370_A0r */
  11582         soc_block_list[125],
  11583         soc_pipereg,
  11584         12,
  11585         0,
  11586         0x15843e00,
  11587         SOC_REG_FLAG_ARRAY |
  11588                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11589         0,
  11590         2,
  11591         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11592         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11593         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11594         -1,
  11595         -1,
  11596         3,
  11597     },
  11598 #endif /* chips */
  11599 
  11600 #if defined(BCM_56770_A0)
  11601     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP3_TBL_BCM56770_A0r */
  11602         soc_block_list[125],
  11603         soc_pipereg,
  11604         12,
  11605         0,
  11606         0x15843d00,
  11607         SOC_REG_FLAG_ARRAY |
  11608                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11609         0,
  11610         2,
  11611         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  11612         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11613         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11614         -1,
  11615         -1,
  11616         3,
  11617     },
  11618 #endif /* chips */
  11619 
  11620 #if defined(BCM_56870_A0)
  11621     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP3_TBL_BCM56870_A0r */
  11622         soc_block_list[125],
  11623         soc_pipereg,
  11624         12,
  11625         0,
  11626         0x15843d00,
  11627         SOC_REG_FLAG_ARRAY |
  11628                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11629         0,
  11630         2,
  11631         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11632         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11633         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11634         -1,
  11635         -1,
  11636         3,
  11637     },
  11638 #endif /* chips */
  11639 
  11640 #if defined(BCM_56970_A0)
  11641     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP4_TBLr */
  11642         soc_block_list[125],
  11643         soc_pipereg,
  11644         12,
  11645         0,
  11646         0x15844800,
  11647         SOC_REG_FLAG_ARRAY |
  11648                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11649         0,
  11650         2,
  11651         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11652         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11653         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11654         -1,
  11655         -1,
  11656         3,
  11657     },
  11658 #endif /* chips */
  11659 
  11660 #if defined(BCM_56370_A0)
  11661     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP4_TBL_BCM56370_A0r */
  11662         soc_block_list[125],
  11663         soc_pipereg,
  11664         12,
  11665         0,
  11666         0x15844a00,
  11667         SOC_REG_FLAG_ARRAY |
  11668                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11669         0,
  11670         2,
  11671         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11672         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11673         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11674         -1,
  11675         -1,
  11676         3,
  11677     },
  11678 #endif /* chips */
  11679 
  11680 #if defined(BCM_56770_A0)
  11681     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP4_TBL_BCM56770_A0r */
  11682         soc_block_list[125],
  11683         soc_pipereg,
  11684         12,
  11685         0,
  11686         0x15844900,
  11687         SOC_REG_FLAG_ARRAY |
  11688                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11689         0,
  11690         2,
  11691         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  11692         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11693         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11694         -1,
  11695         -1,
  11696         3,
  11697     },
  11698 #endif /* chips */
  11699 
  11700 #if defined(BCM_56870_A0)
  11701     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP4_TBL_BCM56870_A0r */
  11702         soc_block_list[125],
  11703         soc_pipereg,
  11704         12,
  11705         0,
  11706         0x15844900,
  11707         SOC_REG_FLAG_ARRAY |
  11708                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11709         0,
  11710         2,
  11711         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11712         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11713         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11714         -1,
  11715         -1,
  11716         3,
  11717     },
  11718 #endif /* chips */
  11719 
  11720 #if defined(BCM_56970_A0)
  11721     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP5_TBLr */
  11722         soc_block_list[125],
  11723         soc_pipereg,
  11724         12,
  11725         0,
  11726         0x15845400,
  11727         SOC_REG_FLAG_ARRAY |
  11728                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11729         0,
  11730         2,
  11731         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11732         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11733         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11734         -1,
  11735         -1,
  11736         3,
  11737     },
  11738 #endif /* chips */
  11739 
  11740 #if defined(BCM_56370_A0)
  11741     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP5_TBL_BCM56370_A0r */
  11742         soc_block_list[125],
  11743         soc_pipereg,
  11744         12,
  11745         0,
  11746         0x15845600,
  11747         SOC_REG_FLAG_ARRAY |
  11748                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11749         0,
  11750         2,
  11751         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11752         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11753         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11754         -1,
  11755         -1,
  11756         3,
  11757     },
  11758 #endif /* chips */
  11759 
  11760 #if defined(BCM_56770_A0)
  11761     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP5_TBL_BCM56770_A0r */
  11762         soc_block_list[125],
  11763         soc_pipereg,
  11764         12,
  11765         0,
  11766         0x15845500,
  11767         SOC_REG_FLAG_ARRAY |
  11768                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11769         0,
  11770         2,
  11771         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  11772         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11773         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11774         -1,
  11775         -1,
  11776         3,
  11777     },
  11778 #endif /* chips */
  11779 
  11780 #if defined(BCM_56870_A0)
  11781     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP5_TBL_BCM56870_A0r */
  11782         soc_block_list[125],
  11783         soc_pipereg,
  11784         12,
  11785         0,
  11786         0x15845500,
  11787         SOC_REG_FLAG_ARRAY |
  11788                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11789         0,
  11790         2,
  11791         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  11792         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  11793         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11794         -1,
  11795         -1,
  11796         3,
  11797     },
  11798 #endif /* chips */
  11799 
  11800 #if defined(BCM_56970_A0)
  11801     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP_CFGr */
  11802         soc_block_list[125],
  11803         soc_pipereg,
  11804         6,
  11805         0,
  11806         0x15840c00,
  11807         SOC_REG_FLAG_ARRAY |
  11808                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11809         0,
  11810         3,
  11811         soc_IS_OVR_SUB_GRP_CFGr_fields,
  11812         SOC_RESET_VAL_DEC(0x00000048, 0x00000000)
  11813         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11814         -1,
  11815         -1,
  11816         3,
  11817     },
  11818 #endif /* chips */
  11819 
  11820 #if defined(BCM_56370_A0)
  11821     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP_CFG_BCM56370_A0r */
  11822         soc_block_list[125],
  11823         soc_pipereg,
  11824         6,
  11825         0,
  11826         0x15840e00,
  11827         SOC_REG_FLAG_ARRAY |
  11828                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11829         0,
  11830         3,
  11831         soc_IS_OVR_SUB_GRP_CFGr_fields,
  11832         SOC_RESET_VAL_DEC(0x00000048, 0x00000000)
  11833         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11834         -1,
  11835         -1,
  11836         3,
  11837     },
  11838 #endif /* chips */
  11839 
  11840 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  11841     { /* SOC_REG_INT_HPIPE0_OVR_SUB_GRP_CFG_BCM56870_A0r */
  11842         soc_block_list[125],
  11843         soc_pipereg,
  11844         6,
  11845         0,
  11846         0x15840d00,
  11847         SOC_REG_FLAG_ARRAY |
  11848                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11849         0,
  11850         3,
  11851         soc_IS_OVR_SUB_GRP_CFGr_fields,
  11852         SOC_RESET_VAL_DEC(0x00000048, 0x00000000)
  11853         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11854         -1,
  11855         -1,
  11856         3,
  11857     },
  11858 #endif /* chips */
  11859 
  11860 #if defined(BCM_56970_A0)
  11861     { /* SOC_REG_INT_HPIPE0_PBLK0_CALENDARr */
  11862         soc_block_list[125],
  11863         soc_pipereg,
  11864         7,
  11865         0,
  11866         0x15846000,
  11867         SOC_REG_FLAG_ARRAY |
  11868                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11869         0,
  11870         3,
  11871         soc_IS_PBLK0_CALENDARr_fields,
  11872         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  11873         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11874         -1,
  11875         -1,
  11876         3,
  11877     },
  11878 #endif /* chips */
  11879 
  11880 #if defined(BCM_56370_A0)
  11881     { /* SOC_REG_INT_HPIPE0_PBLK0_CALENDAR_BCM56370_A0r */
  11882         soc_block_list[125],
  11883         soc_pipereg,
  11884         7,
  11885         0,
  11886         0x15846200,
  11887         SOC_REG_FLAG_ARRAY |
  11888                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11889         0,
  11890         3,
  11891         soc_IS_PBLK0_CALENDARr_fields,
  11892         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  11893         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11894         -1,
  11895         -1,
  11896         3,
  11897     },
  11898 #endif /* chips */
  11899 
  11900 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  11901     { /* SOC_REG_INT_HPIPE0_PBLK0_CALENDAR_BCM56870_A0r */
  11902         soc_block_list[125],
  11903         soc_pipereg,
  11904         7,
  11905         0,
  11906         0x15846100,
  11907         SOC_REG_FLAG_ARRAY |
  11908                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11909         0,
  11910         3,
  11911         soc_IS_PBLK0_CALENDARr_fields,
  11912         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  11913         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11914         -1,
  11915         -1,
  11916         3,
  11917     },
  11918 #endif /* chips */
  11919 
  11920 #if defined(BCM_56970_A0)
  11921     { /* SOC_REG_INT_HPIPE0_PBLK1_CALENDARr */
  11922         soc_block_list[125],
  11923         soc_pipereg,
  11924         7,
  11925         0,
  11926         0x15846700,
  11927         SOC_REG_FLAG_ARRAY |
  11928                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11929         0,
  11930         3,
  11931         soc_IS_PBLK0_CALENDARr_fields,
  11932         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  11933         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11934         -1,
  11935         -1,
  11936         3,
  11937     },
  11938 #endif /* chips */
  11939 
  11940 #if defined(BCM_56370_A0)
  11941     { /* SOC_REG_INT_HPIPE0_PBLK1_CALENDAR_BCM56370_A0r */
  11942         soc_block_list[125],
  11943         soc_pipereg,
  11944         7,
  11945         0,
  11946         0x15846900,
  11947         SOC_REG_FLAG_ARRAY |
  11948                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11949         0,
  11950         3,
  11951         soc_IS_PBLK0_CALENDARr_fields,
  11952         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  11953         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11954         -1,
  11955         -1,
  11956         3,
  11957     },
  11958 #endif /* chips */
  11959 
  11960 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  11961     { /* SOC_REG_INT_HPIPE0_PBLK1_CALENDAR_BCM56870_A0r */
  11962         soc_block_list[125],
  11963         soc_pipereg,
  11964         7,
  11965         0,
  11966         0x15846800,
  11967         SOC_REG_FLAG_ARRAY |
  11968                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11969         0,
  11970         3,
  11971         soc_IS_PBLK0_CALENDARr_fields,
  11972         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  11973         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11974         -1,
  11975         -1,
  11976         3,
  11977     },
  11978 #endif /* chips */
  11979 
  11980 #if defined(BCM_56970_A0)
  11981     { /* SOC_REG_INT_HPIPE0_PBLK2_CALENDARr */
  11982         soc_block_list[125],
  11983         soc_pipereg,
  11984         7,
  11985         0,
  11986         0x15846e00,
  11987         SOC_REG_FLAG_ARRAY |
  11988                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11989         0,
  11990         3,
  11991         soc_IS_PBLK0_CALENDARr_fields,
  11992         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  11993         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11994         -1,
  11995         -1,
  11996         3,
  11997     },
  11998 #endif /* chips */
  11999 
  12000 #if defined(BCM_56370_A0)
  12001     { /* SOC_REG_INT_HPIPE0_PBLK2_CALENDAR_BCM56370_A0r */
  12002         soc_block_list[125],
  12003         soc_pipereg,
  12004         7,
  12005         0,
  12006         0x15847000,
  12007         SOC_REG_FLAG_ARRAY |
  12008                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12009         0,
  12010         3,
  12011         soc_IS_PBLK0_CALENDARr_fields,
  12012         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12013         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12014         -1,
  12015         -1,
  12016         3,
  12017     },
  12018 #endif /* chips */
  12019 
  12020 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  12021     { /* SOC_REG_INT_HPIPE0_PBLK2_CALENDAR_BCM56870_A0r */
  12022         soc_block_list[125],
  12023         soc_pipereg,
  12024         7,
  12025         0,
  12026         0x15846f00,
  12027         SOC_REG_FLAG_ARRAY |
  12028                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12029         0,
  12030         3,
  12031         soc_IS_PBLK0_CALENDARr_fields,
  12032         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12033         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12034         -1,
  12035         -1,
  12036         3,
  12037     },
  12038 #endif /* chips */
  12039 
  12040 #if defined(BCM_56970_A0)
  12041     { /* SOC_REG_INT_HPIPE0_PBLK3_CALENDARr */
  12042         soc_block_list[125],
  12043         soc_pipereg,
  12044         7,
  12045         0,
  12046         0x15847500,
  12047         SOC_REG_FLAG_ARRAY |
  12048                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12049         0,
  12050         3,
  12051         soc_IS_PBLK0_CALENDARr_fields,
  12052         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12053         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12054         -1,
  12055         -1,
  12056         3,
  12057     },
  12058 #endif /* chips */
  12059 
  12060 #if defined(BCM_56370_A0)
  12061     { /* SOC_REG_INT_HPIPE0_PBLK3_CALENDAR_BCM56370_A0r */
  12062         soc_block_list[125],
  12063         soc_pipereg,
  12064         7,
  12065         0,
  12066         0x15847700,
  12067         SOC_REG_FLAG_ARRAY |
  12068                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12069         0,
  12070         3,
  12071         soc_IS_PBLK0_CALENDARr_fields,
  12072         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12073         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12074         -1,
  12075         -1,
  12076         3,
  12077     },
  12078 #endif /* chips */
  12079 
  12080 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  12081     { /* SOC_REG_INT_HPIPE0_PBLK3_CALENDAR_BCM56870_A0r */
  12082         soc_block_list[125],
  12083         soc_pipereg,
  12084         7,
  12085         0,
  12086         0x15847600,
  12087         SOC_REG_FLAG_ARRAY |
  12088                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12089         0,
  12090         3,
  12091         soc_IS_PBLK0_CALENDARr_fields,
  12092         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12093         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12094         -1,
  12095         -1,
  12096         3,
  12097     },
  12098 #endif /* chips */
  12099 
  12100 #if defined(BCM_56970_A0)
  12101     { /* SOC_REG_INT_HPIPE0_PBLK4_CALENDARr */
  12102         soc_block_list[125],
  12103         soc_pipereg,
  12104         7,
  12105         0,
  12106         0x15847c00,
  12107         SOC_REG_FLAG_ARRAY |
  12108                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12109         0,
  12110         3,
  12111         soc_IS_PBLK0_CALENDARr_fields,
  12112         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12113         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12114         -1,
  12115         -1,
  12116         3,
  12117     },
  12118 #endif /* chips */
  12119 
  12120 #if defined(BCM_56370_A0)
  12121     { /* SOC_REG_INT_HPIPE0_PBLK4_CALENDAR_BCM56370_A0r */
  12122         soc_block_list[125],
  12123         soc_pipereg,
  12124         7,
  12125         0,
  12126         0x15847e00,
  12127         SOC_REG_FLAG_ARRAY |
  12128                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12129         0,
  12130         3,
  12131         soc_IS_PBLK0_CALENDARr_fields,
  12132         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12133         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12134         -1,
  12135         -1,
  12136         3,
  12137     },
  12138 #endif /* chips */
  12139 
  12140 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  12141     { /* SOC_REG_INT_HPIPE0_PBLK4_CALENDAR_BCM56870_A0r */
  12142         soc_block_list[125],
  12143         soc_pipereg,
  12144         7,
  12145         0,
  12146         0x15847d00,
  12147         SOC_REG_FLAG_ARRAY |
  12148                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12149         0,
  12150         3,
  12151         soc_IS_PBLK0_CALENDARr_fields,
  12152         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12153         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12154         -1,
  12155         -1,
  12156         3,
  12157     },
  12158 #endif /* chips */
  12159 
  12160 #if defined(BCM_56970_A0)
  12161     { /* SOC_REG_INT_HPIPE0_PBLK5_CALENDARr */
  12162         soc_block_list[125],
  12163         soc_pipereg,
  12164         7,
  12165         0,
  12166         0x15848300,
  12167         SOC_REG_FLAG_ARRAY |
  12168                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12169         0,
  12170         3,
  12171         soc_IS_PBLK0_CALENDARr_fields,
  12172         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12173         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12174         -1,
  12175         -1,
  12176         3,
  12177     },
  12178 #endif /* chips */
  12179 
  12180 #if defined(BCM_56370_A0)
  12181     { /* SOC_REG_INT_HPIPE0_PBLK5_CALENDAR_BCM56370_A0r */
  12182         soc_block_list[125],
  12183         soc_pipereg,
  12184         7,
  12185         0,
  12186         0x15848500,
  12187         SOC_REG_FLAG_ARRAY |
  12188                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12189         0,
  12190         3,
  12191         soc_IS_PBLK0_CALENDARr_fields,
  12192         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12193         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12194         -1,
  12195         -1,
  12196         3,
  12197     },
  12198 #endif /* chips */
  12199 
  12200 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  12201     { /* SOC_REG_INT_HPIPE0_PBLK5_CALENDAR_BCM56870_A0r */
  12202         soc_block_list[125],
  12203         soc_pipereg,
  12204         7,
  12205         0,
  12206         0x15848400,
  12207         SOC_REG_FLAG_ARRAY |
  12208                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12209         0,
  12210         3,
  12211         soc_IS_PBLK0_CALENDARr_fields,
  12212         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12213         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12214         -1,
  12215         -1,
  12216         3,
  12217     },
  12218 #endif /* chips */
  12219 
  12220 #if defined(BCM_56970_A0)
  12221     { /* SOC_REG_INT_HPIPE0_PBLK6_CALENDARr */
  12222         soc_block_list[125],
  12223         soc_pipereg,
  12224         7,
  12225         0,
  12226         0x15848a00,
  12227         SOC_REG_FLAG_ARRAY |
  12228                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12229         0,
  12230         3,
  12231         soc_IS_PBLK0_CALENDARr_fields,
  12232         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12233         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12234         -1,
  12235         -1,
  12236         3,
  12237     },
  12238 #endif /* chips */
  12239 
  12240 #if defined(BCM_56370_A0)
  12241     { /* SOC_REG_INT_HPIPE0_PBLK6_CALENDAR_BCM56370_A0r */
  12242         soc_block_list[125],
  12243         soc_pipereg,
  12244         7,
  12245         0,
  12246         0x15848c00,
  12247         SOC_REG_FLAG_ARRAY |
  12248                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12249         0,
  12250         3,
  12251         soc_IS_PBLK0_CALENDARr_fields,
  12252         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12253         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12254         -1,
  12255         -1,
  12256         3,
  12257     },
  12258 #endif /* chips */
  12259 
  12260 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  12261     { /* SOC_REG_INT_HPIPE0_PBLK6_CALENDAR_BCM56870_A0r */
  12262         soc_block_list[125],
  12263         soc_pipereg,
  12264         7,
  12265         0,
  12266         0x15848b00,
  12267         SOC_REG_FLAG_ARRAY |
  12268                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12269         0,
  12270         3,
  12271         soc_IS_PBLK0_CALENDARr_fields,
  12272         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12273         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12274         -1,
  12275         -1,
  12276         3,
  12277     },
  12278 #endif /* chips */
  12279 
  12280 #if defined(BCM_56970_A0)
  12281     { /* SOC_REG_INT_HPIPE0_PBLK7_CALENDARr */
  12282         soc_block_list[125],
  12283         soc_pipereg,
  12284         7,
  12285         0,
  12286         0x15849100,
  12287         SOC_REG_FLAG_ARRAY |
  12288                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12289         0,
  12290         3,
  12291         soc_IS_PBLK0_CALENDARr_fields,
  12292         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12293         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12294         -1,
  12295         -1,
  12296         3,
  12297     },
  12298 #endif /* chips */
  12299 
  12300 #if defined(BCM_56370_A0)
  12301     { /* SOC_REG_INT_HPIPE0_PBLK7_CALENDAR_BCM56370_A0r */
  12302         soc_block_list[125],
  12303         soc_pipereg,
  12304         7,
  12305         0,
  12306         0x15849300,
  12307         SOC_REG_FLAG_ARRAY |
  12308                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12309         0,
  12310         3,
  12311         soc_IS_PBLK0_CALENDARr_fields,
  12312         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12313         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12314         -1,
  12315         -1,
  12316         3,
  12317     },
  12318 #endif /* chips */
  12319 
  12320 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  12321     { /* SOC_REG_INT_HPIPE0_PBLK7_CALENDAR_BCM56870_A0r */
  12322         soc_block_list[125],
  12323         soc_pipereg,
  12324         7,
  12325         0,
  12326         0x15849200,
  12327         SOC_REG_FLAG_ARRAY |
  12328                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12329         0,
  12330         3,
  12331         soc_IS_PBLK0_CALENDARr_fields,
  12332         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12333         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12334         -1,
  12335         -1,
  12336         3,
  12337     },
  12338 #endif /* chips */
  12339 
  12340 #if defined(BCM_56770_A0)
  12341     { /* SOC_REG_INT_HPIPE0_PBLK8_CALENDARr */
  12342         soc_block_list[125],
  12343         soc_pipereg,
  12344         7,
  12345         0,
  12346         0x15849900,
  12347         SOC_REG_FLAG_ARRAY |
  12348                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12349         0,
  12350         3,
  12351         soc_IS_PBLK0_CALENDARr_fields,
  12352         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12353         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12354         -1,
  12355         -1,
  12356         3,
  12357     },
  12358 #endif /* chips */
  12359 
  12360 #if defined(BCM_56770_A0)
  12361     { /* SOC_REG_INT_HPIPE0_PBLK9_CALENDARr */
  12362         soc_block_list[125],
  12363         soc_pipereg,
  12364         7,
  12365         0,
  12366         0x1584a000,
  12367         SOC_REG_FLAG_ARRAY |
  12368                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12369         0,
  12370         3,
  12371         soc_IS_PBLK0_CALENDARr_fields,
  12372         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12373         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12374         -1,
  12375         -1,
  12376         3,
  12377     },
  12378 #endif /* chips */
  12379 
  12380 #if defined(BCM_56970_A0)
  12381     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP0_TBLr */
  12382         soc_block_list[125],
  12383         soc_pipereg,
  12384         12,
  12385         0,
  12386         0x1584a500,
  12387         SOC_REG_FLAG_ARRAY |
  12388                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12389         0,
  12390         2,
  12391         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12392         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12393         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12394         -1,
  12395         -1,
  12396         3,
  12397     },
  12398 #endif /* chips */
  12399 
  12400 #if defined(BCM_56370_A0)
  12401     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP0_TBL_BCM56370_A0r */
  12402         soc_block_list[125],
  12403         soc_pipereg,
  12404         12,
  12405         0,
  12406         0x1584a700,
  12407         SOC_REG_FLAG_ARRAY |
  12408                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12409         0,
  12410         2,
  12411         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12412         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12413         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12414         -1,
  12415         -1,
  12416         3,
  12417     },
  12418 #endif /* chips */
  12419 
  12420 #if defined(BCM_56770_A0)
  12421     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP0_TBL_BCM56770_A0r */
  12422         soc_block_list[125],
  12423         soc_pipereg,
  12424         12,
  12425         0,
  12426         0x1584b400,
  12427         SOC_REG_FLAG_ARRAY |
  12428                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12429         0,
  12430         2,
  12431         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  12432         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12433         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12434         -1,
  12435         -1,
  12436         3,
  12437     },
  12438 #endif /* chips */
  12439 
  12440 #if defined(BCM_56870_A0)
  12441     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP0_TBL_BCM56870_A0r */
  12442         soc_block_list[125],
  12443         soc_pipereg,
  12444         12,
  12445         0,
  12446         0x1584a600,
  12447         SOC_REG_FLAG_ARRAY |
  12448                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12449         0,
  12450         2,
  12451         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12452         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12453         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12454         -1,
  12455         -1,
  12456         3,
  12457     },
  12458 #endif /* chips */
  12459 
  12460 #if defined(BCM_56970_A0)
  12461     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP1_TBLr */
  12462         soc_block_list[125],
  12463         soc_pipereg,
  12464         12,
  12465         0,
  12466         0x1584b100,
  12467         SOC_REG_FLAG_ARRAY |
  12468                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12469         0,
  12470         2,
  12471         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12472         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12473         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12474         -1,
  12475         -1,
  12476         3,
  12477     },
  12478 #endif /* chips */
  12479 
  12480 #if defined(BCM_56370_A0)
  12481     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP1_TBL_BCM56370_A0r */
  12482         soc_block_list[125],
  12483         soc_pipereg,
  12484         12,
  12485         0,
  12486         0x1584b300,
  12487         SOC_REG_FLAG_ARRAY |
  12488                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12489         0,
  12490         2,
  12491         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12492         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12493         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12494         -1,
  12495         -1,
  12496         3,
  12497     },
  12498 #endif /* chips */
  12499 
  12500 #if defined(BCM_56770_A0)
  12501     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP1_TBL_BCM56770_A0r */
  12502         soc_block_list[125],
  12503         soc_pipereg,
  12504         12,
  12505         0,
  12506         0x1584c000,
  12507         SOC_REG_FLAG_ARRAY |
  12508                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12509         0,
  12510         2,
  12511         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  12512         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12513         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12514         -1,
  12515         -1,
  12516         3,
  12517     },
  12518 #endif /* chips */
  12519 
  12520 #if defined(BCM_56870_A0)
  12521     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP1_TBL_BCM56870_A0r */
  12522         soc_block_list[125],
  12523         soc_pipereg,
  12524         12,
  12525         0,
  12526         0x1584b200,
  12527         SOC_REG_FLAG_ARRAY |
  12528                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12529         0,
  12530         2,
  12531         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12532         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12533         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12534         -1,
  12535         -1,
  12536         3,
  12537     },
  12538 #endif /* chips */
  12539 
  12540 #if defined(BCM_56970_A0)
  12541     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP2_TBLr */
  12542         soc_block_list[125],
  12543         soc_pipereg,
  12544         12,
  12545         0,
  12546         0x1584bd00,
  12547         SOC_REG_FLAG_ARRAY |
  12548                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12549         0,
  12550         2,
  12551         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12552         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12553         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12554         -1,
  12555         -1,
  12556         3,
  12557     },
  12558 #endif /* chips */
  12559 
  12560 #if defined(BCM_56370_A0)
  12561     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP2_TBL_BCM56370_A0r */
  12562         soc_block_list[125],
  12563         soc_pipereg,
  12564         12,
  12565         0,
  12566         0x1584bf00,
  12567         SOC_REG_FLAG_ARRAY |
  12568                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12569         0,
  12570         2,
  12571         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12572         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12573         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12574         -1,
  12575         -1,
  12576         3,
  12577     },
  12578 #endif /* chips */
  12579 
  12580 #if defined(BCM_56770_A0)
  12581     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP2_TBL_BCM56770_A0r */
  12582         soc_block_list[125],
  12583         soc_pipereg,
  12584         12,
  12585         0,
  12586         0x1584cc00,
  12587         SOC_REG_FLAG_ARRAY |
  12588                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12589         0,
  12590         2,
  12591         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  12592         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12593         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12594         -1,
  12595         -1,
  12596         3,
  12597     },
  12598 #endif /* chips */
  12599 
  12600 #if defined(BCM_56870_A0)
  12601     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP2_TBL_BCM56870_A0r */
  12602         soc_block_list[125],
  12603         soc_pipereg,
  12604         12,
  12605         0,
  12606         0x1584be00,
  12607         SOC_REG_FLAG_ARRAY |
  12608                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12609         0,
  12610         2,
  12611         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12612         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12613         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12614         -1,
  12615         -1,
  12616         3,
  12617     },
  12618 #endif /* chips */
  12619 
  12620 #if defined(BCM_56970_A0)
  12621     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP3_TBLr */
  12622         soc_block_list[125],
  12623         soc_pipereg,
  12624         12,
  12625         0,
  12626         0x1584c900,
  12627         SOC_REG_FLAG_ARRAY |
  12628                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12629         0,
  12630         2,
  12631         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12632         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12633         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12634         -1,
  12635         -1,
  12636         3,
  12637     },
  12638 #endif /* chips */
  12639 
  12640 #if defined(BCM_56370_A0)
  12641     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP3_TBL_BCM56370_A0r */
  12642         soc_block_list[125],
  12643         soc_pipereg,
  12644         12,
  12645         0,
  12646         0x1584cb00,
  12647         SOC_REG_FLAG_ARRAY |
  12648                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12649         0,
  12650         2,
  12651         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12652         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12653         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12654         -1,
  12655         -1,
  12656         3,
  12657     },
  12658 #endif /* chips */
  12659 
  12660 #if defined(BCM_56770_A0)
  12661     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP3_TBL_BCM56770_A0r */
  12662         soc_block_list[125],
  12663         soc_pipereg,
  12664         12,
  12665         0,
  12666         0x1584d800,
  12667         SOC_REG_FLAG_ARRAY |
  12668                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12669         0,
  12670         2,
  12671         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  12672         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12673         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12674         -1,
  12675         -1,
  12676         3,
  12677     },
  12678 #endif /* chips */
  12679 
  12680 #if defined(BCM_56870_A0)
  12681     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP3_TBL_BCM56870_A0r */
  12682         soc_block_list[125],
  12683         soc_pipereg,
  12684         12,
  12685         0,
  12686         0x1584ca00,
  12687         SOC_REG_FLAG_ARRAY |
  12688                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12689         0,
  12690         2,
  12691         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12692         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12693         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12694         -1,
  12695         -1,
  12696         3,
  12697     },
  12698 #endif /* chips */
  12699 
  12700 #if defined(BCM_56970_A0)
  12701     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP4_TBLr */
  12702         soc_block_list[125],
  12703         soc_pipereg,
  12704         12,
  12705         0,
  12706         0x1584d500,
  12707         SOC_REG_FLAG_ARRAY |
  12708                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12709         0,
  12710         2,
  12711         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12712         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12713         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12714         -1,
  12715         -1,
  12716         3,
  12717     },
  12718 #endif /* chips */
  12719 
  12720 #if defined(BCM_56370_A0)
  12721     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP4_TBL_BCM56370_A0r */
  12722         soc_block_list[125],
  12723         soc_pipereg,
  12724         12,
  12725         0,
  12726         0x1584d700,
  12727         SOC_REG_FLAG_ARRAY |
  12728                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12729         0,
  12730         2,
  12731         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12732         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12733         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12734         -1,
  12735         -1,
  12736         3,
  12737     },
  12738 #endif /* chips */
  12739 
  12740 #if defined(BCM_56770_A0)
  12741     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP4_TBL_BCM56770_A0r */
  12742         soc_block_list[125],
  12743         soc_pipereg,
  12744         12,
  12745         0,
  12746         0x1584e400,
  12747         SOC_REG_FLAG_ARRAY |
  12748                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12749         0,
  12750         2,
  12751         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  12752         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12753         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12754         -1,
  12755         -1,
  12756         3,
  12757     },
  12758 #endif /* chips */
  12759 
  12760 #if defined(BCM_56870_A0)
  12761     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP4_TBL_BCM56870_A0r */
  12762         soc_block_list[125],
  12763         soc_pipereg,
  12764         12,
  12765         0,
  12766         0x1584d600,
  12767         SOC_REG_FLAG_ARRAY |
  12768                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12769         0,
  12770         2,
  12771         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12772         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12773         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12774         -1,
  12775         -1,
  12776         3,
  12777     },
  12778 #endif /* chips */
  12779 
  12780 #if defined(BCM_56970_A0)
  12781     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP5_TBLr */
  12782         soc_block_list[125],
  12783         soc_pipereg,
  12784         12,
  12785         0,
  12786         0x1584e100,
  12787         SOC_REG_FLAG_ARRAY |
  12788                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12789         0,
  12790         2,
  12791         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12792         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12793         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12794         -1,
  12795         -1,
  12796         3,
  12797     },
  12798 #endif /* chips */
  12799 
  12800 #if defined(BCM_56370_A0)
  12801     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP5_TBL_BCM56370_A0r */
  12802         soc_block_list[125],
  12803         soc_pipereg,
  12804         12,
  12805         0,
  12806         0x1584e300,
  12807         SOC_REG_FLAG_ARRAY |
  12808                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12809         0,
  12810         2,
  12811         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12812         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12813         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12814         -1,
  12815         -1,
  12816         3,
  12817     },
  12818 #endif /* chips */
  12819 
  12820 #if defined(BCM_56770_A0)
  12821     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP5_TBL_BCM56770_A0r */
  12822         soc_block_list[125],
  12823         soc_pipereg,
  12824         12,
  12825         0,
  12826         0x1584f000,
  12827         SOC_REG_FLAG_ARRAY |
  12828                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12829         0,
  12830         2,
  12831         soc_HPIPE0_OVR_SUB_GRP0_TBLr_fields,
  12832         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12833         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12834         -1,
  12835         -1,
  12836         3,
  12837     },
  12838 #endif /* chips */
  12839 
  12840 #if defined(BCM_56870_A0)
  12841     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP5_TBL_BCM56870_A0r */
  12842         soc_block_list[125],
  12843         soc_pipereg,
  12844         12,
  12845         0,
  12846         0x1584e200,
  12847         SOC_REG_FLAG_ARRAY |
  12848                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12849         0,
  12850         2,
  12851         soc_IS_OVR_SUB_GRP0_TBLr_fields,
  12852         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  12853         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12854         -1,
  12855         -1,
  12856         3,
  12857     },
  12858 #endif /* chips */
  12859 
  12860 #if defined(BCM_56970_A0)
  12861     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP_CFGr */
  12862         soc_block_list[125],
  12863         soc_pipereg,
  12864         6,
  12865         0,
  12866         0x15849900,
  12867         SOC_REG_FLAG_ARRAY |
  12868                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12869         0,
  12870         3,
  12871         soc_IS_OVR_SUB_GRP_CFGr_fields,
  12872         SOC_RESET_VAL_DEC(0x00000048, 0x00000000)
  12873         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12874         -1,
  12875         -1,
  12876         3,
  12877     },
  12878 #endif /* chips */
  12879 
  12880 #if defined(BCM_56370_A0)
  12881     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP_CFG_BCM56370_A0r */
  12882         soc_block_list[125],
  12883         soc_pipereg,
  12884         6,
  12885         0,
  12886         0x15849b00,
  12887         SOC_REG_FLAG_ARRAY |
  12888                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12889         0,
  12890         3,
  12891         soc_IS_OVR_SUB_GRP_CFGr_fields,
  12892         SOC_RESET_VAL_DEC(0x00000048, 0x00000000)
  12893         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12894         -1,
  12895         -1,
  12896         3,
  12897     },
  12898 #endif /* chips */
  12899 
  12900 #if defined(BCM_56770_A0)
  12901     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP_CFG_BCM56770_A0r */
  12902         soc_block_list[125],
  12903         soc_pipereg,
  12904         6,
  12905         0,
  12906         0x1584a800,
  12907         SOC_REG_FLAG_ARRAY |
  12908                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12909         0,
  12910         3,
  12911         soc_IS_OVR_SUB_GRP_CFGr_fields,
  12912         SOC_RESET_VAL_DEC(0x00000048, 0x00000000)
  12913         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12914         -1,
  12915         -1,
  12916         3,
  12917     },
  12918 #endif /* chips */
  12919 
  12920 #if defined(BCM_56870_A0)
  12921     { /* SOC_REG_INT_HPIPE1_OVR_SUB_GRP_CFG_BCM56870_A0r */
  12922         soc_block_list[125],
  12923         soc_pipereg,
  12924         6,
  12925         0,
  12926         0x15849a00,
  12927         SOC_REG_FLAG_ARRAY |
  12928                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12929         0,
  12930         3,
  12931         soc_IS_OVR_SUB_GRP_CFGr_fields,
  12932         SOC_RESET_VAL_DEC(0x00000048, 0x00000000)
  12933         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12934         -1,
  12935         -1,
  12936         3,
  12937     },
  12938 #endif /* chips */
  12939 
  12940 #if defined(BCM_56970_A0)
  12941     { /* SOC_REG_INT_HPIPE1_PBLK0_CALENDARr */
  12942         soc_block_list[125],
  12943         soc_pipereg,
  12944         7,
  12945         0,
  12946         0x1584ed00,
  12947         SOC_REG_FLAG_ARRAY |
  12948                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12949         0,
  12950         3,
  12951         soc_IS_PBLK0_CALENDARr_fields,
  12952         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12953         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12954         -1,
  12955         -1,
  12956         3,
  12957     },
  12958 #endif /* chips */
  12959 
  12960 #if defined(BCM_56370_A0)
  12961     { /* SOC_REG_INT_HPIPE1_PBLK0_CALENDAR_BCM56370_A0r */
  12962         soc_block_list[125],
  12963         soc_pipereg,
  12964         7,
  12965         0,
  12966         0x1584ef00,
  12967         SOC_REG_FLAG_ARRAY |
  12968                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12969         0,
  12970         3,
  12971         soc_IS_PBLK0_CALENDARr_fields,
  12972         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12973         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12974         -1,
  12975         -1,
  12976         3,
  12977     },
  12978 #endif /* chips */
  12979 
  12980 #if defined(BCM_56870_A0)
  12981     { /* SOC_REG_INT_HPIPE1_PBLK0_CALENDAR_BCM56870_A0r */
  12982         soc_block_list[125],
  12983         soc_pipereg,
  12984         7,
  12985         0,
  12986         0x1584ee00,
  12987         SOC_REG_FLAG_ARRAY |
  12988                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12989         0,
  12990         3,
  12991         soc_IS_PBLK0_CALENDARr_fields,
  12992         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  12993         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  12994         -1,
  12995         -1,
  12996         3,
  12997     },
  12998 #endif /* chips */
  12999 
  13000 #if defined(BCM_56970_A0)
  13001     { /* SOC_REG_INT_HPIPE1_PBLK1_CALENDARr */
  13002         soc_block_list[125],
  13003         soc_pipereg,
  13004         7,
  13005         0,
  13006         0x1584f400,
  13007         SOC_REG_FLAG_ARRAY |
  13008                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13009         0,
  13010         3,
  13011         soc_IS_PBLK0_CALENDARr_fields,
  13012         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13013         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13014         -1,
  13015         -1,
  13016         3,
  13017     },
  13018 #endif /* chips */
  13019 
  13020 #if defined(BCM_56370_A0)
  13021     { /* SOC_REG_INT_HPIPE1_PBLK1_CALENDAR_BCM56370_A0r */
  13022         soc_block_list[125],
  13023         soc_pipereg,
  13024         7,
  13025         0,
  13026         0x1584f600,
  13027         SOC_REG_FLAG_ARRAY |
  13028                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13029         0,
  13030         3,
  13031         soc_IS_PBLK0_CALENDARr_fields,
  13032         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13033         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13034         -1,
  13035         -1,
  13036         3,
  13037     },
  13038 #endif /* chips */
  13039 
  13040 #if defined(BCM_56870_A0)
  13041     { /* SOC_REG_INT_HPIPE1_PBLK1_CALENDAR_BCM56870_A0r */
  13042         soc_block_list[125],
  13043         soc_pipereg,
  13044         7,
  13045         0,
  13046         0x1584f500,
  13047         SOC_REG_FLAG_ARRAY |
  13048                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13049         0,
  13050         3,
  13051         soc_IS_PBLK0_CALENDARr_fields,
  13052         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13053         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13054         -1,
  13055         -1,
  13056         3,
  13057     },
  13058 #endif /* chips */
  13059 
  13060 #if defined(BCM_56970_A0)
  13061     { /* SOC_REG_INT_HPIPE1_PBLK2_CALENDARr */
  13062         soc_block_list[125],
  13063         soc_pipereg,
  13064         7,
  13065         0,
  13066         0x1584fb00,
  13067         SOC_REG_FLAG_ARRAY |
  13068                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13069         0,
  13070         3,
  13071         soc_IS_PBLK0_CALENDARr_fields,
  13072         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13073         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13074         -1,
  13075         -1,
  13076         3,
  13077     },
  13078 #endif /* chips */
  13079 
  13080 #if defined(BCM_56370_A0)
  13081     { /* SOC_REG_INT_HPIPE1_PBLK2_CALENDAR_BCM56370_A0r */
  13082         soc_block_list[125],
  13083         soc_pipereg,
  13084         7,
  13085         0,
  13086         0x1584fd00,
  13087         SOC_REG_FLAG_ARRAY |
  13088                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13089         0,
  13090         3,
  13091         soc_IS_PBLK0_CALENDARr_fields,
  13092         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13093         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13094         -1,
  13095         -1,
  13096         3,
  13097     },
  13098 #endif /* chips */
  13099 
  13100 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  13101     { /* SOC_REG_INT_HPIPE1_PBLK2_CALENDAR_BCM56870_A0r */
  13102         soc_block_list[125],
  13103         soc_pipereg,
  13104         7,
  13105         0,
  13106         0x1584fc00,
  13107         SOC_REG_FLAG_ARRAY |
  13108                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13109         0,
  13110         3,
  13111         soc_IS_PBLK0_CALENDARr_fields,
  13112         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13113         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13114         -1,
  13115         -1,
  13116         3,
  13117     },
  13118 #endif /* chips */
  13119 
  13120 #if defined(BCM_56970_A0)
  13121     { /* SOC_REG_INT_HPIPE1_PBLK3_CALENDARr */
  13122         soc_block_list[125],
  13123         soc_pipereg,
  13124         7,
  13125         0,
  13126         0x15850200,
  13127         SOC_REG_FLAG_ARRAY |
  13128                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13129         0,
  13130         3,
  13131         soc_IS_PBLK0_CALENDARr_fields,
  13132         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13133         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13134         -1,
  13135         -1,
  13136         3,
  13137     },
  13138 #endif /* chips */
  13139 
  13140 #if defined(BCM_56370_A0)
  13141     { /* SOC_REG_INT_HPIPE1_PBLK3_CALENDAR_BCM56370_A0r */
  13142         soc_block_list[125],
  13143         soc_pipereg,
  13144         7,
  13145         0,
  13146         0x15850400,
  13147         SOC_REG_FLAG_ARRAY |
  13148                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13149         0,
  13150         3,
  13151         soc_IS_PBLK0_CALENDARr_fields,
  13152         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13153         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13154         -1,
  13155         -1,
  13156         3,
  13157     },
  13158 #endif /* chips */
  13159 
  13160 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  13161     { /* SOC_REG_INT_HPIPE1_PBLK3_CALENDAR_BCM56870_A0r */
  13162         soc_block_list[125],
  13163         soc_pipereg,
  13164         7,
  13165         0,
  13166         0x15850300,
  13167         SOC_REG_FLAG_ARRAY |
  13168                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13169         0,
  13170         3,
  13171         soc_IS_PBLK0_CALENDARr_fields,
  13172         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13173         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13174         -1,
  13175         -1,
  13176         3,
  13177     },
  13178 #endif /* chips */
  13179 
  13180 #if defined(BCM_56970_A0)
  13181     { /* SOC_REG_INT_HPIPE1_PBLK4_CALENDARr */
  13182         soc_block_list[125],
  13183         soc_pipereg,
  13184         7,
  13185         0,
  13186         0x15850900,
  13187         SOC_REG_FLAG_ARRAY |
  13188                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13189         0,
  13190         3,
  13191         soc_IS_PBLK0_CALENDARr_fields,
  13192         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13193         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13194         -1,
  13195         -1,
  13196         3,
  13197     },
  13198 #endif /* chips */
  13199 
  13200 #if defined(BCM_56370_A0)
  13201     { /* SOC_REG_INT_HPIPE1_PBLK4_CALENDAR_BCM56370_A0r */
  13202         soc_block_list[125],
  13203         soc_pipereg,
  13204         7,
  13205         0,
  13206         0x15850b00,
  13207         SOC_REG_FLAG_ARRAY |
  13208                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13209         0,
  13210         3,
  13211         soc_IS_PBLK0_CALENDARr_fields,
  13212         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13213         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13214         -1,
  13215         -1,
  13216         3,
  13217     },
  13218 #endif /* chips */
  13219 
  13220 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  13221     { /* SOC_REG_INT_HPIPE1_PBLK4_CALENDAR_BCM56870_A0r */
  13222         soc_block_list[125],
  13223         soc_pipereg,
  13224         7,
  13225         0,
  13226         0x15850a00,
  13227         SOC_REG_FLAG_ARRAY |
  13228                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13229         0,
  13230         3,
  13231         soc_IS_PBLK0_CALENDARr_fields,
  13232         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13233         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13234         -1,
  13235         -1,
  13236         3,
  13237     },
  13238 #endif /* chips */
  13239 
  13240 #if defined(BCM_56970_A0)
  13241     { /* SOC_REG_INT_HPIPE1_PBLK5_CALENDARr */
  13242         soc_block_list[125],
  13243         soc_pipereg,
  13244         7,
  13245         0,
  13246         0x15851000,
  13247         SOC_REG_FLAG_ARRAY |
  13248                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13249         0,
  13250         3,
  13251         soc_IS_PBLK0_CALENDARr_fields,
  13252         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13253         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13254         -1,
  13255         -1,
  13256         3,
  13257     },
  13258 #endif /* chips */
  13259 
  13260 #if defined(BCM_56370_A0)
  13261     { /* SOC_REG_INT_HPIPE1_PBLK5_CALENDAR_BCM56370_A0r */
  13262         soc_block_list[125],
  13263         soc_pipereg,
  13264         7,
  13265         0,
  13266         0x15851200,
  13267         SOC_REG_FLAG_ARRAY |
  13268                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13269         0,
  13270         3,
  13271         soc_IS_PBLK0_CALENDARr_fields,
  13272         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13273         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13274         -1,
  13275         -1,
  13276         3,
  13277     },
  13278 #endif /* chips */
  13279 
  13280 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  13281     { /* SOC_REG_INT_HPIPE1_PBLK5_CALENDAR_BCM56870_A0r */
  13282         soc_block_list[125],
  13283         soc_pipereg,
  13284         7,
  13285         0,
  13286         0x15851100,
  13287         SOC_REG_FLAG_ARRAY |
  13288                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13289         0,
  13290         3,
  13291         soc_IS_PBLK0_CALENDARr_fields,
  13292         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13293         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13294         -1,
  13295         -1,
  13296         3,
  13297     },
  13298 #endif /* chips */
  13299 
  13300 #if defined(BCM_56970_A0)
  13301     { /* SOC_REG_INT_HPIPE1_PBLK6_CALENDARr */
  13302         soc_block_list[125],
  13303         soc_pipereg,
  13304         7,
  13305         0,
  13306         0x15851700,
  13307         SOC_REG_FLAG_ARRAY |
  13308                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13309         0,
  13310         3,
  13311         soc_IS_PBLK0_CALENDARr_fields,
  13312         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13313         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13314         -1,
  13315         -1,
  13316         3,
  13317     },
  13318 #endif /* chips */
  13319 
  13320 #if defined(BCM_56370_A0)
  13321     { /* SOC_REG_INT_HPIPE1_PBLK6_CALENDAR_BCM56370_A0r */
  13322         soc_block_list[125],
  13323         soc_pipereg,
  13324         7,
  13325         0,
  13326         0x15851900,
  13327         SOC_REG_FLAG_ARRAY |
  13328                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13329         0,
  13330         3,
  13331         soc_IS_PBLK0_CALENDARr_fields,
  13332         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13333         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13334         -1,
  13335         -1,
  13336         3,
  13337     },
  13338 #endif /* chips */
  13339 
  13340 #if defined(BCM_56770_A0)
  13341     { /* SOC_REG_INT_HPIPE1_PBLK6_CALENDAR_BCM56770_A0r */
  13342         soc_block_list[125],
  13343         soc_pipereg,
  13344         7,
  13345         0,
  13346         0x15852600,
  13347         SOC_REG_FLAG_ARRAY |
  13348                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13349         0,
  13350         3,
  13351         soc_IS_PBLK0_CALENDARr_fields,
  13352         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13353         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13354         -1,
  13355         -1,
  13356         3,
  13357     },
  13358 #endif /* chips */
  13359 
  13360 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  13361     { /* SOC_REG_INT_HPIPE1_PBLK6_CALENDAR_BCM56870_A0r */
  13362         soc_block_list[125],
  13363         soc_pipereg,
  13364         7,
  13365         0,
  13366         0x15851800,
  13367         SOC_REG_FLAG_ARRAY |
  13368                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13369         0,
  13370         3,
  13371         soc_IS_PBLK0_CALENDARr_fields,
  13372         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13373         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13374         -1,
  13375         -1,
  13376         3,
  13377     },
  13378 #endif /* chips */
  13379 
  13380 #if defined(BCM_56970_A0)
  13381     { /* SOC_REG_INT_HPIPE1_PBLK7_CALENDARr */
  13382         soc_block_list[125],
  13383         soc_pipereg,
  13384         7,
  13385         0,
  13386         0x15851e00,
  13387         SOC_REG_FLAG_ARRAY |
  13388                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13389         0,
  13390         3,
  13391         soc_IS_PBLK0_CALENDARr_fields,
  13392         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13393         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13394         -1,
  13395         -1,
  13396         3,
  13397     },
  13398 #endif /* chips */
  13399 
  13400 #if defined(BCM_56370_A0)
  13401     { /* SOC_REG_INT_HPIPE1_PBLK7_CALENDAR_BCM56370_A0r */
  13402         soc_block_list[125],
  13403         soc_pipereg,
  13404         7,
  13405         0,
  13406         0x15852000,
  13407         SOC_REG_FLAG_ARRAY |
  13408                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13409         0,
  13410         3,
  13411         soc_IS_PBLK0_CALENDARr_fields,
  13412         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13413         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13414         -1,
  13415         -1,
  13416         3,
  13417     },
  13418 #endif /* chips */
  13419 
  13420 #if defined(BCM_56770_A0)
  13421     { /* SOC_REG_INT_HPIPE1_PBLK7_CALENDAR_BCM56770_A0r */
  13422         soc_block_list[125],
  13423         soc_pipereg,
  13424         7,
  13425         0,
  13426         0x15852d00,
  13427         SOC_REG_FLAG_ARRAY |
  13428                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13429         0,
  13430         3,
  13431         soc_IS_PBLK0_CALENDARr_fields,
  13432         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13433         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13434         -1,
  13435         -1,
  13436         3,
  13437     },
  13438 #endif /* chips */
  13439 
  13440 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  13441     { /* SOC_REG_INT_HPIPE1_PBLK7_CALENDAR_BCM56870_A0r */
  13442         soc_block_list[125],
  13443         soc_pipereg,
  13444         7,
  13445         0,
  13446         0x15851f00,
  13447         SOC_REG_FLAG_ARRAY |
  13448                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13449         0,
  13450         3,
  13451         soc_IS_PBLK0_CALENDARr_fields,
  13452         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13453         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13454         -1,
  13455         -1,
  13456         3,
  13457     },
  13458 #endif /* chips */
  13459 
  13460 #if defined(BCM_56770_A0)
  13461     { /* SOC_REG_INT_HPIPE1_PBLK8_CALENDARr */
  13462         soc_block_list[125],
  13463         soc_pipereg,
  13464         7,
  13465         0,
  13466         0x15853400,
  13467         SOC_REG_FLAG_ARRAY |
  13468                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13469         0,
  13470         3,
  13471         soc_IS_PBLK0_CALENDARr_fields,
  13472         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13473         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13474         -1,
  13475         -1,
  13476         3,
  13477     },
  13478 #endif /* chips */
  13479 
  13480 #if defined(BCM_56770_A0)
  13481     { /* SOC_REG_INT_HPIPE1_PBLK9_CALENDARr */
  13482         soc_block_list[125],
  13483         soc_pipereg,
  13484         7,
  13485         0,
  13486         0x15853b00,
  13487         SOC_REG_FLAG_ARRAY |
  13488                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13489         0,
  13490         3,
  13491         soc_IS_PBLK0_CALENDARr_fields,
  13492         SOC_RESET_VAL_DEC(0x0000007e, 0x00000000)
  13493         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13494         -1,
  13495         -1,
  13496         3,
  13497     },
  13498 #endif /* chips */
  13499 
  13500 #if defined(BCM_56640_A0)
  13501     { /* SOC_REG_INT_HSP_CONFIGr */
  13502         soc_block_list[4],
  13503         soc_genreg,
  13504         1,
  13505         0,
  13506         0x1a000000,
  13507         0,
  13508         0,
  13509         4,
  13510         soc_HSP_CONFIGr_fields,
  13511         SOC_RESET_VAL_DEC(0x10001000, 0x00000000)
  13512         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13513         -1,
  13514         -1,
  13515     },
  13516 #endif /* chips */
  13517 
  13518 #if defined(BCM_56640_A0)
  13519     { /* SOC_REG_INT_HSP_EMPTY_STATUS_P0r */
  13520         soc_block_list[4],
  13521         soc_genreg,
  13522         1,
  13523         0,
  13524         0x1a008600,
  13525         SOC_REG_FLAG_RO,
  13526         0,
  13527         2,
  13528         soc_HSP_EMPTY_STATUS_P0r_fields,
  13529         SOC_RESET_VAL_DEC(0x000fffff, 0x00000000)
  13530         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  13531         -1,
  13532         -1,
  13533     },
  13534 #endif /* chips */
  13535 
  13536 #if defined(BCM_56640_A0)
  13537     { /* SOC_REG_INT_HSP_EMPTY_STATUS_P1r */
  13538         soc_block_list[4],
  13539         soc_genreg,
  13540         1,
  13541         0,
  13542         0x1a008700,
  13543         SOC_REG_FLAG_RO,
  13544         0,
  13545         2,
  13546         soc_HSP_EMPTY_STATUS_P0r_fields,
  13547         SOC_RESET_VAL_DEC(0x000fffff, 0x00000000)
  13548         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  13549         -1,
  13550         -1,
  13551     },
  13552 #endif /* chips */
  13553 
  13554 #if defined(BCM_56850_A0)
  13555     { /* SOC_REG_INT_HSP_EN_COR_ERR_RPTr */
  13556         soc_block_list[4],
  13557         soc_genreg,
  13558         1,
  13559         0,
  13560         0x96080400,
  13561         0,
  13562         0,
  13563         14,
  13564         soc_HSP_EN_COR_ERR_RPTr_fields,
  13565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13566         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  13567         -1,
  13568         -1,
  13569     },
  13570 #endif /* chips */
  13571 
  13572 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13573     { /* SOC_REG_INT_HSP_EN_COR_ERR_RPT_BCM56560_A0r */
  13574         soc_block_list[4],
  13575         soc_genreg,
  13576         1,
  13577         0,
  13578         0x96080400,
  13579         0,
  13580         0,
  13581         7,
  13582         soc_HSP_EN_COR_ERR_RPT_BCM56560_A0r_fields,
  13583         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  13584         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  13585         -1,
  13586         -1,
  13587     },
  13588 #endif /* chips */
  13589 
  13590 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13591     { /* SOC_REG_INT_HSP_EN_COR_ERR_RPT_BCM56670_A0r */
  13592         soc_block_list[4],
  13593         soc_genreg,
  13594         1,
  13595         0,
  13596         0x96080600,
  13597         0,
  13598         0,
  13599         13,
  13600         soc_HSP_EN_COR_ERR_RPT_BCM56670_A0r_fields,
  13601         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  13602         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  13603         -1,
  13604         -1,
  13605     },
  13606 #endif /* chips */
  13607 
  13608 #if defined(BCM_56860_A0)
  13609     { /* SOC_REG_INT_HSP_EN_COR_ERR_RPT_BCM56860_A0r */
  13610         soc_block_list[4],
  13611         soc_genreg,
  13612         1,
  13613         0,
  13614         0x96080700,
  13615         0,
  13616         0,
  13617         14,
  13618         soc_HSP_EN_COR_ERR_RPTr_fields,
  13619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13620         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  13621         -1,
  13622         -1,
  13623     },
  13624 #endif /* chips */
  13625 
  13626 #if defined(BCM_56850_A0)
  13627     { /* SOC_REG_INT_HSP_MEMORY_TMr */
  13628         soc_block_list[4],
  13629         soc_genreg,
  13630         1,
  13631         0,
  13632         0x96080300,
  13633         0,
  13634         0,
  13635         14,
  13636         soc_HSP_MEMORY_TMr_fields,
  13637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13638         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  13639         -1,
  13640         -1,
  13641     },
  13642 #endif /* chips */
  13643 
  13644 #if defined(BCM_56860_A0)
  13645     { /* SOC_REG_INT_HSP_MEMORY_TM_0r */
  13646         soc_block_list[4],
  13647         soc_genreg,
  13648         1,
  13649         0,
  13650         0x96080300,
  13651         0,
  13652         0,
  13653         6,
  13654         soc_HSP_MEMORY_TM_0r_fields,
  13655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13656         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  13657         -1,
  13658         -1,
  13659     },
  13660 #endif /* chips */
  13661 
  13662 #if defined(BCM_56860_A0)
  13663     { /* SOC_REG_INT_HSP_MEMORY_TM_1r */
  13664         soc_block_list[4],
  13665         soc_genreg,
  13666         1,
  13667         0,
  13668         0x96080400,
  13669         0,
  13670         0,
  13671         3,
  13672         soc_HSP_MEMORY_TM_1r_fields,
  13673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13674         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  13675         -1,
  13676         -1,
  13677     },
  13678 #endif /* chips */
  13679 
  13680 #if defined(BCM_56860_A0)
  13681     { /* SOC_REG_INT_HSP_MEMORY_TM_2r */
  13682         soc_block_list[4],
  13683         soc_genreg,
  13684         1,
  13685         0,
  13686         0x96080500,
  13687         0,
  13688         0,
  13689         6,
  13690         soc_HSP_MEMORY_TM_2r_fields,
  13691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13692         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  13693         -1,
  13694         -1,
  13695     },
  13696 #endif /* chips */
  13697 
  13698 #if defined(BCM_56860_A0)
  13699     { /* SOC_REG_INT_HSP_MEMORY_TM_3r */
  13700         soc_block_list[4],
  13701         soc_genreg,
  13702         1,
  13703         0,
  13704         0x96080600,
  13705         0,
  13706         0,
  13707         3,
  13708         soc_HSP_MEMORY_TM_3r_fields,
  13709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13710         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  13711         -1,
  13712         -1,
  13713     },
  13714 #endif /* chips */
  13715 
  13716 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13717     { /* SOC_REG_INT_HSP_MEMORY_TM_4r */
  13718         soc_block_list[4],
  13719         soc_genreg,
  13720         1,
  13721         0,
  13722         0x96080500,
  13723         0,
  13724         0,
  13725         2,
  13726         soc_HSP_MEMORY_TM_4r_fields,
  13727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13728         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13729         -1,
  13730         -1,
  13731     },
  13732 #endif /* chips */
  13733 
  13734 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13735     { /* SOC_REG_INT_HSP_MEMORY_TM_0_BCM56560_A0r */
  13736         soc_block_list[4],
  13737         soc_genreg,
  13738         1,
  13739         0,
  13740         0x96080200,
  13741         0,
  13742         0,
  13743         6,
  13744         soc_HSP_MEMORY_TM_0_BCM56560_A0r_fields,
  13745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13746         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  13747         -1,
  13748         -1,
  13749     },
  13750 #endif /* chips */
  13751 
  13752 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13753     { /* SOC_REG_INT_HSP_MEMORY_TM_0_BCM56670_A0r */
  13754         soc_block_list[4],
  13755         soc_genreg,
  13756         1,
  13757         0,
  13758         0x96080100,
  13759         0,
  13760         0,
  13761         4,
  13762         soc_HSP_MEMORY_TM_0_BCM56670_A0r_fields,
  13763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13764         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  13765         -1,
  13766         -1,
  13767     },
  13768 #endif /* chips */
  13769 
  13770 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13771     { /* SOC_REG_INT_HSP_MEMORY_TM_1_BCM56560_A0r */
  13772         soc_block_list[4],
  13773         soc_genreg,
  13774         1,
  13775         0,
  13776         0x96080300,
  13777         0,
  13778         0,
  13779         3,
  13780         soc_HSP_MEMORY_TM_1_BCM56560_A0r_fields,
  13781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13782         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  13783         -1,
  13784         -1,
  13785     },
  13786 #endif /* chips */
  13787 
  13788 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13789     { /* SOC_REG_INT_HSP_MEMORY_TM_1_BCM56670_A0r */
  13790         soc_block_list[4],
  13791         soc_genreg,
  13792         1,
  13793         0,
  13794         0x96080200,
  13795         0,
  13796         0,
  13797         2,
  13798         soc_HSP_MEMORY_TM_1_BCM56670_A0r_fields,
  13799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13800         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13801         -1,
  13802         -1,
  13803     },
  13804 #endif /* chips */
  13805 
  13806 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13807     { /* SOC_REG_INT_HSP_MEMORY_TM_2_BCM56670_A0r */
  13808         soc_block_list[4],
  13809         soc_genreg,
  13810         1,
  13811         0,
  13812         0x96080300,
  13813         0,
  13814         0,
  13815         2,
  13816         soc_HSP_MEMORY_TM_2_BCM56670_A0r_fields,
  13817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13818         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  13819         -1,
  13820         -1,
  13821     },
  13822 #endif /* chips */
  13823 
  13824 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13825     { /* SOC_REG_INT_HSP_MEMORY_TM_3_BCM56670_A0r */
  13826         soc_block_list[4],
  13827         soc_genreg,
  13828         1,
  13829         0,
  13830         0x96080400,
  13831         0,
  13832         0,
  13833         2,
  13834         soc_HSP_MEMORY_TM_3_BCM56670_A0r_fields,
  13835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13836         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13837         -1,
  13838         -1,
  13839     },
  13840 #endif /* chips */
  13841 
  13842 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  13843     { /* SOC_REG_INT_HSP_PIPEX_SPECIAL_CONFIGr */
  13844         soc_block_list[4],
  13845         soc_genreg,
  13846         1,
  13847         0,
  13848         0x96080100,
  13849         0,
  13850         0,
  13851         5,
  13852         soc_HSP_PIPEX_SPECIAL_CONFIGr_fields,
  13853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13854         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  13855         -1,
  13856         -1,
  13857     },
  13858 #endif /* chips */
  13859 
  13860 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13861     { /* SOC_REG_INT_HSP_PIPEX_SPECIAL_CONFIG_BCM56560_A0r */
  13862         soc_block_list[4],
  13863         soc_genreg,
  13864         1,
  13865         0,
  13866         0x96080100,
  13867         0,
  13868         0,
  13869         5,
  13870         soc_HSP_PIPEX_SPECIAL_CONFIG_BCM56560_A0r_fields,
  13871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13872         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  13873         -1,
  13874         -1,
  13875     },
  13876 #endif /* chips */
  13877 
  13878 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13879     { /* SOC_REG_INT_HSP_PIPEX_SPECIAL_CONFIG_BCM56670_A0r */
  13880         soc_block_list[4],
  13881         soc_genreg,
  13882         1,
  13883         0,
  13884         0x96080000,
  13885         0,
  13886         0,
  13887         6,
  13888         soc_HSP_PIPEX_SPECIAL_CONFIG_BCM56670_A0r_fields,
  13889         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  13890         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  13891         -1,
  13892         -1,
  13893     },
  13894 #endif /* chips */
  13895 
  13896 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  13897     { /* SOC_REG_INT_HSP_PIPEY_SPECIAL_CONFIGr */
  13898         soc_block_list[4],
  13899         soc_genreg,
  13900         1,
  13901         0,
  13902         0x96080200,
  13903         0,
  13904         0,
  13905         5,
  13906         soc_HSP_PIPEX_SPECIAL_CONFIGr_fields,
  13907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13908         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  13909         -1,
  13910         -1,
  13911     },
  13912 #endif /* chips */
  13913 
  13914 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  13915     { /* SOC_REG_INT_HSP_SCHED_GLOBAL_CONFIGr */
  13916         soc_block_list[4],
  13917         soc_genreg,
  13918         1,
  13919         0,
  13920         0x96080000,
  13921         0,
  13922         0,
  13923         2,
  13924         soc_HSP_SCHED_GLOBAL_CONFIGr_fields,
  13925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13926         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13927         -1,
  13928         -1,
  13929     },
  13930 #endif /* chips */
  13931 
  13932 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13933     { /* SOC_REG_INT_HSP_SCHED_GLOBAL_CONFIG_BCM56560_A0r */
  13934         soc_block_list[4],
  13935         soc_genreg,
  13936         1,
  13937         0,
  13938         0x96080000,
  13939         0,
  13940         0,
  13941         1,
  13942         soc_HSP_SCHED_GLOBAL_CONFIG_BCM56560_A0r_fields,
  13943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13944         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  13945         -1,
  13946         -1,
  13947     },
  13948 #endif /* chips */
  13949 
  13950 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13951     { /* SOC_REG_INT_HSP_SCHED_L0_NODE_4_CONNECTION_CONFIGr */
  13952         soc_block_list[4],
  13953         soc_portreg,
  13954         1,
  13955         0,
  13956         0x98044000,
  13957         0,
  13958         0,
  13959         1,
  13960         soc_HSP_SCHED_L0_NODE_4_CONNECTION_CONFIGr_fields,
  13961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13962         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13963         -1,
  13964         109,
  13965     },
  13966 #endif /* chips */
  13967 
  13968 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  13969     { /* SOC_REG_INT_HSP_SCHED_L0_NODE_CONFIGr */
  13970         soc_block_list[4],
  13971         soc_portreg,
  13972         1,
  13973         0,
  13974         0x98000000,
  13975         0,
  13976         0,
  13977         3,
  13978         soc_HSP_SCHED_L0_NODE_CONFIGr_fields,
  13979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13980         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  13981         -1,
  13982         73,
  13983     },
  13984 #endif /* chips */
  13985 
  13986 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13987     { /* SOC_REG_INT_HSP_SCHED_L0_NODE_CONFIG_BCM56560_A0r */
  13988         soc_block_list[4],
  13989         soc_portreg,
  13990         1,
  13991         0,
  13992         0x98000000,
  13993         0,
  13994         0,
  13995         3,
  13996         soc_HSP_SCHED_L0_NODE_CONFIG_BCM56560_A0r_fields,
  13997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13998         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  13999         -1,
  14000         85,
  14001     },
  14002 #endif /* chips */
  14003 
  14004 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14005     { /* SOC_REG_INT_HSP_SCHED_L0_NODE_CONFIG_BCM56670_A0r */
  14006         soc_block_list[4],
  14007         soc_portreg,
  14008         1,
  14009         0,
  14010         0x98000000,
  14011         0,
  14012         0,
  14013         3,
  14014         soc_HSP_SCHED_L0_NODE_CONFIG_BCM56560_A0r_fields,
  14015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14016         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  14017         -1,
  14018         109,
  14019     },
  14020 #endif /* chips */
  14021 
  14022 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14023     { /* SOC_REG_INT_HSP_SCHED_L0_NODE_CONNECTION_CONFIGr */
  14024         soc_block_list[4],
  14025         soc_portreg,
  14026         5,
  14027         0,
  14028         0x98011000,
  14029         SOC_REG_FLAG_ARRAY,
  14030         0,
  14031         1,
  14032         soc_HSP_SCHED_L0_NODE_CONNECTION_CONFIGr_fields,
  14033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14034         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14035         -1,
  14036         73,
  14037     },
  14038 #endif /* chips */
  14039 
  14040 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14041     { /* SOC_REG_INT_HSP_SCHED_L0_NODE_CONNECTION_CONFIG_BCM56560_A0r */
  14042         soc_block_list[4],
  14043         soc_portreg,
  14044         5,
  14045         0,
  14046         0x98011000,
  14047         SOC_REG_FLAG_ARRAY,
  14048         0,
  14049         1,
  14050         soc_HSP_SCHED_L0_NODE_CONNECTION_CONFIG_BCM56560_A0r_fields,
  14051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14052         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14053         -1,
  14054         85,
  14055     },
  14056 #endif /* chips */
  14057 
  14058 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14059     { /* SOC_REG_INT_HSP_SCHED_L0_NODE_CONNECTION_CONFIG_BCM56670_A0r */
  14060         soc_block_list[4],
  14061         soc_portreg,
  14062         3,
  14063         0,
  14064         0x98011000,
  14065         SOC_REG_FLAG_ARRAY,
  14066         0,
  14067         1,
  14068         soc_HSP_SCHED_L0_NODE_CONNECTION_CONFIG_BCM56560_A0r_fields,
  14069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14070         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14071         -1,
  14072         109,
  14073     },
  14074 #endif /* chips */
  14075 
  14076 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14077     { /* SOC_REG_INT_HSP_SCHED_L0_NODE_WEIGHTr */
  14078         soc_block_list[4],
  14079         soc_portreg,
  14080         5,
  14081         0,
  14082         0x98010000,
  14083         SOC_REG_FLAG_ARRAY,
  14084         0,
  14085         1,
  14086         soc_HSP_SCHED_L0_NODE_WEIGHTr_fields,
  14087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14088         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14089         -1,
  14090         73,
  14091     },
  14092 #endif /* chips */
  14093 
  14094 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14095     { /* SOC_REG_INT_HSP_SCHED_L0_NODE_WEIGHT_BCM56560_A0r */
  14096         soc_block_list[4],
  14097         soc_portreg,
  14098         5,
  14099         0,
  14100         0x98010000,
  14101         SOC_REG_FLAG_ARRAY,
  14102         0,
  14103         1,
  14104         soc_HSP_SCHED_L0_NODE_WEIGHT_BCM56560_A0r_fields,
  14105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14106         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14107         -1,
  14108         85,
  14109     },
  14110 #endif /* chips */
  14111 
  14112 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14113     { /* SOC_REG_INT_HSP_SCHED_L1_NODE_CONFIGr */
  14114         soc_block_list[4],
  14115         soc_portreg,
  14116         1,
  14117         0,
  14118         0x9c000000,
  14119         0,
  14120         0,
  14121         3,
  14122         soc_HSP_SCHED_L1_NODE_CONFIGr_fields,
  14123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14124         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  14125         -1,
  14126         73,
  14127     },
  14128 #endif /* chips */
  14129 
  14130 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14131     { /* SOC_REG_INT_HSP_SCHED_L1_NODE_CONFIG_BCM56560_A0r */
  14132         soc_block_list[4],
  14133         soc_portreg,
  14134         1,
  14135         0,
  14136         0x9c000000,
  14137         0,
  14138         0,
  14139         3,
  14140         soc_Q_SCHED_CPU_L0_NODE_CONFIGr_fields,
  14141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14142         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  14143         -1,
  14144         85,
  14145     },
  14146 #endif /* chips */
  14147 
  14148 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14149     { /* SOC_REG_INT_HSP_SCHED_L1_NODE_CONFIG_BCM56670_A0r */
  14150         soc_block_list[4],
  14151         soc_portreg,
  14152         1,
  14153         0,
  14154         0x9c000000,
  14155         0,
  14156         0,
  14157         3,
  14158         soc_Q_SCHED_CPU_L0_NODE_CONFIGr_fields,
  14159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14160         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  14161         -1,
  14162         109,
  14163     },
  14164 #endif /* chips */
  14165 
  14166 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14167     { /* SOC_REG_INT_HSP_SCHED_L1_NODE_WEIGHTr */
  14168         soc_block_list[4],
  14169         soc_portreg,
  14170         10,
  14171         0,
  14172         0x9c010000,
  14173         SOC_REG_FLAG_ARRAY,
  14174         0,
  14175         1,
  14176         soc_HSP_SCHED_L0_NODE_WEIGHTr_fields,
  14177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14178         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14179         -1,
  14180         73,
  14181     },
  14182 #endif /* chips */
  14183 
  14184 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14185     { /* SOC_REG_INT_HSP_SCHED_L1_NODE_WEIGHT_BCM56560_A0r */
  14186         soc_block_list[4],
  14187         soc_portreg,
  14188         10,
  14189         0,
  14190         0x9c010000,
  14191         SOC_REG_FLAG_ARRAY,
  14192         0,
  14193         1,
  14194         soc_HSP_SCHED_L0_NODE_WEIGHT_BCM56560_A0r_fields,
  14195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14196         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14197         -1,
  14198         85,
  14199     },
  14200 #endif /* chips */
  14201 
  14202 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14203     { /* SOC_REG_INT_HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG0r */
  14204         soc_block_list[4],
  14205         soc_genreg,
  14206         1,
  14207         0,
  14208         0x96080800,
  14209         0,
  14210         0,
  14211         2,
  14212         soc_HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG0r_fields,
  14213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14214         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14215         -1,
  14216         -1,
  14217     },
  14218 #endif /* chips */
  14219 
  14220 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14221     { /* SOC_REG_INT_HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG1r */
  14222         soc_block_list[4],
  14223         soc_genreg,
  14224         1,
  14225         0,
  14226         0x96080900,
  14227         0,
  14228         0,
  14229         2,
  14230         soc_HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG0r_fields,
  14231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14232         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14233         -1,
  14234         -1,
  14235     },
  14236 #endif /* chips */
  14237 
  14238 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14239     { /* SOC_REG_INT_HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG2r */
  14240         soc_block_list[4],
  14241         soc_genreg,
  14242         1,
  14243         0,
  14244         0x96080a00,
  14245         0,
  14246         0,
  14247         2,
  14248         soc_HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG0r_fields,
  14249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14250         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14251         -1,
  14252         -1,
  14253     },
  14254 #endif /* chips */
  14255 
  14256 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14257     { /* SOC_REG_INT_HSP_SCHED_L2_MC_QUEUE_CONFIGr */
  14258         soc_block_list[4],
  14259         soc_portreg,
  14260         1,
  14261         0,
  14262         0xa0000100,
  14263         0,
  14264         0,
  14265         2,
  14266         soc_HSP_SCHED_L2_MC_QUEUE_CONFIGr_fields,
  14267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14268         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14269         -1,
  14270         73,
  14271     },
  14272 #endif /* chips */
  14273 
  14274 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14275     { /* SOC_REG_INT_HSP_SCHED_L2_MC_QUEUE_CONFIG_BCM56560_A0r */
  14276         soc_block_list[4],
  14277         soc_portreg,
  14278         1,
  14279         0,
  14280         0xa0000100,
  14281         0,
  14282         0,
  14283         2,
  14284         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  14285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14286         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14287         -1,
  14288         85,
  14289     },
  14290 #endif /* chips */
  14291 
  14292 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14293     { /* SOC_REG_INT_HSP_SCHED_L2_MC_QUEUE_CONFIG_BCM56670_A0r */
  14294         soc_block_list[4],
  14295         soc_portreg,
  14296         1,
  14297         0,
  14298         0xa0020000,
  14299         0,
  14300         0,
  14301         2,
  14302         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  14303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14304         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14305         -1,
  14306         109,
  14307     },
  14308 #endif /* chips */
  14309 
  14310 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14311     { /* SOC_REG_INT_HSP_SCHED_L2_MC_QUEUE_WEIGHTr */
  14312         soc_block_list[4],
  14313         soc_portreg,
  14314         10,
  14315         0,
  14316         0xa0011000,
  14317         SOC_REG_FLAG_ARRAY,
  14318         0,
  14319         1,
  14320         soc_HSP_SCHED_L0_NODE_WEIGHTr_fields,
  14321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14322         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14323         -1,
  14324         73,
  14325     },
  14326 #endif /* chips */
  14327 
  14328 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14329     { /* SOC_REG_INT_HSP_SCHED_L2_MC_QUEUE_WEIGHT_BCM56560_A0r */
  14330         soc_block_list[4],
  14331         soc_portreg,
  14332         10,
  14333         0,
  14334         0xa0011000,
  14335         SOC_REG_FLAG_ARRAY,
  14336         0,
  14337         1,
  14338         soc_HSP_SCHED_L0_NODE_WEIGHT_BCM56560_A0r_fields,
  14339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14340         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14341         -1,
  14342         85,
  14343     },
  14344 #endif /* chips */
  14345 
  14346 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14347     { /* SOC_REG_INT_HSP_SCHED_L2_UC_QUEUE_CONFIGr */
  14348         soc_block_list[4],
  14349         soc_portreg,
  14350         1,
  14351         0,
  14352         0xa0000000,
  14353         0,
  14354         0,
  14355         2,
  14356         soc_HSP_SCHED_L2_MC_QUEUE_CONFIGr_fields,
  14357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14358         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14359         -1,
  14360         73,
  14361     },
  14362 #endif /* chips */
  14363 
  14364 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14365     { /* SOC_REG_INT_HSP_SCHED_L2_UC_QUEUE_CONFIG_BCM56560_A0r */
  14366         soc_block_list[4],
  14367         soc_portreg,
  14368         1,
  14369         0,
  14370         0xa0000000,
  14371         0,
  14372         0,
  14373         2,
  14374         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  14375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14376         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14377         -1,
  14378         85,
  14379     },
  14380 #endif /* chips */
  14381 
  14382 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14383     { /* SOC_REG_INT_HSP_SCHED_L2_UC_QUEUE_CONFIG_BCM56670_A0r */
  14384         soc_block_list[4],
  14385         soc_portreg,
  14386         1,
  14387         0,
  14388         0xa0000000,
  14389         0,
  14390         0,
  14391         2,
  14392         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  14393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14394         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14395         -1,
  14396         110,
  14397     },
  14398 #endif /* chips */
  14399 
  14400 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14401     { /* SOC_REG_INT_HSP_SCHED_L2_UC_QUEUE_WEIGHTr */
  14402         soc_block_list[4],
  14403         soc_portreg,
  14404         10,
  14405         0,
  14406         0xa0010000,
  14407         SOC_REG_FLAG_ARRAY,
  14408         0,
  14409         1,
  14410         soc_HSP_SCHED_L0_NODE_WEIGHTr_fields,
  14411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14412         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14413         -1,
  14414         73,
  14415     },
  14416 #endif /* chips */
  14417 
  14418 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14419     { /* SOC_REG_INT_HSP_SCHED_L2_UC_QUEUE_WEIGHT_BCM56560_A0r */
  14420         soc_block_list[4],
  14421         soc_portreg,
  14422         10,
  14423         0,
  14424         0xa0010000,
  14425         SOC_REG_FLAG_ARRAY,
  14426         0,
  14427         1,
  14428         soc_HSP_SCHED_L0_NODE_WEIGHT_BCM56560_A0r_fields,
  14429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14430         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14431         -1,
  14432         85,
  14433     },
  14434 #endif /* chips */
  14435 
  14436 #if defined(BCM_56850_A0)
  14437     { /* SOC_REG_INT_HSP_SCHED_PORT_CONFIGr */
  14438         soc_block_list[4],
  14439         soc_portreg,
  14440         1,
  14441         0,
  14442         0x94080500,
  14443         0,
  14444         0,
  14445         2,
  14446         soc_HSP_SCHED_PORT_CONFIGr_fields,
  14447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14448         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14449         -1,
  14450         73,
  14451     },
  14452 #endif /* chips */
  14453 
  14454 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14455     { /* SOC_REG_INT_HSP_SCHED_PORT_CONFIG_BCM56560_A0r */
  14456         soc_block_list[4],
  14457         soc_portreg,
  14458         1,
  14459         0,
  14460         0x94080500,
  14461         0,
  14462         0,
  14463         2,
  14464         soc_HSP_SCHED_PORT_CONFIG_BCM56560_A0r_fields,
  14465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14466         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14467         -1,
  14468         85,
  14469     },
  14470 #endif /* chips */
  14471 
  14472 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14473     { /* SOC_REG_INT_HSP_SCHED_PORT_CONFIG_BCM56670_A0r */
  14474         soc_block_list[4],
  14475         soc_portreg,
  14476         1,
  14477         0,
  14478         0x94080700,
  14479         0,
  14480         0,
  14481         2,
  14482         soc_HSP_SCHED_PORT_CONFIG_BCM56560_A0r_fields,
  14483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14484         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14485         -1,
  14486         109,
  14487     },
  14488 #endif /* chips */
  14489 
  14490 #if defined(BCM_56860_A0)
  14491     { /* SOC_REG_INT_HSP_SCHED_PORT_CONFIG_BCM56860_A0r */
  14492         soc_block_list[4],
  14493         soc_portreg,
  14494         1,
  14495         0,
  14496         0x94080800,
  14497         0,
  14498         0,
  14499         2,
  14500         soc_HSP_SCHED_PORT_CONFIGr_fields,
  14501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14502         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14503         -1,
  14504         73,
  14505     },
  14506 #endif /* chips */
  14507 
  14508 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14509     { /* SOC_REG_INT_HSP_SCHED_PORT_PREEMPT_CONFIGr */
  14510         soc_block_list[4],
  14511         soc_portreg,
  14512         1,
  14513         0,
  14514         0x94080c00,
  14515         0,
  14516         0,
  14517         2,
  14518         soc_HSP_SCHED_PORT_PREEMPT_CONFIGr_fields,
  14519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14520         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  14521         -1,
  14522         110,
  14523     },
  14524 #endif /* chips */
  14525 
  14526 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  14527     { /* SOC_REG_INT_HW_MAC_LEARNINGr */
  14528         soc_block_list[5],
  14529         soc_genreg,
  14530         1,
  14531         0,
  14532         0x6000d00,
  14533         0,
  14534         0,
  14535         1,
  14536         soc_HW_MAC_LEARNINGr_fields,
  14537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14538         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  14539         -1,
  14540         -1,
  14541     },
  14542 #endif /* chips */
  14543
	openbcm Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM
	git clone git://git.finwo.net/mirror/broadcom/openbcm
	Log \| Files \| Refs \| README