openbcm

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allregs_g.i (1454811B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_g.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_53570_A0)
     16     { /* SOC_REG_INT_GATE_CTRL_PERIODr */
     17         soc_block_list[4],
     18         soc_portreg,
     19         1,
     20         0,
     21         0x117000,
     22         0,
     23         0,
     24         1,
     25         soc_GATE_CTRL_PERIODr_fields,
     26         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     27         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
     28         -1,
     29         103,
     30     },
     31 #endif /* chips */
     32 
     33 #if defined(BCM_53570_B0)
     34     { /* SOC_REG_INT_GATE_CTRL_PERIOD_BCM53570_B0r */
     35         soc_block_list[4],
     36         soc_portreg,
     37         1,
     38         0,
     39         0x117300,
     40         0,
     41         0,
     42         1,
     43         soc_GATE_CTRL_PERIODr_fields,
     44         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     45         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
     46         -1,
     47         103,
     48     },
     49 #endif /* chips */
     50 
     51 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
     52     { /* SOC_REG_INT_GBLBKPSTATUSr */
     53         soc_block_list[4],
     54         soc_genreg,
     55         1,
     56         0,
     57         0x217b200,
     58         SOC_REG_FLAG_RO,
     59         0,
     60         2,
     61         soc_GBLBKPSTATUSr_fields,
     62         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     63         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
     64         -1,
     65         -1,
     66     },
     67 #endif /* chips */
     68 
     69 #if defined(BCM_53540_A0)
     70     { /* SOC_REG_INT_GBLBKPSTATUS_BCM53540_A0r */
     71         soc_block_list[4],
     72         soc_genreg,
     73         1,
     74         0,
     75         0x208d000,
     76         SOC_REG_FLAG_RO,
     77         0,
     78         2,
     79         soc_GBLBKPSTATUSr_fields,
     80         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     81         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
     82         -1,
     83         -1,
     84     },
     85 #endif /* chips */
     86 
     87 #if defined(BCM_53570_A0)
     88     { /* SOC_REG_INT_GBLBKPSTATUS_BCM53570_A0r */
     89         soc_block_list[4],
     90         soc_genreg,
     91         1,
     92         0,
     93         0x20fc600,
     94         SOC_REG_FLAG_RO,
     95         0,
     96         2,
     97         soc_GBLBKPSTATUSr_fields,
     98         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     99         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    100         -1,
    101         -1,
    102     },
    103 #endif /* chips */
    104 
    105 #if defined(BCM_53570_B0)
    106     { /* SOC_REG_INT_GBLBKPSTATUS_BCM53570_B0r */
    107         soc_block_list[4],
    108         soc_genreg,
    109         1,
    110         0,
    111         0x20fc900,
    112         SOC_REG_FLAG_RO,
    113         0,
    114         2,
    115         soc_GBLBKPSTATUSr_fields,
    116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    117         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    118         -1,
    119         -1,
    120     },
    121 #endif /* chips */
    122 
    123 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
    124     { /* SOC_REG_INT_GBLLIMITRESETLIMITr */
    125         soc_block_list[4],
    126         soc_genreg,
    127         1,
    128         0,
    129         0x217b100,
    130         0,
    131         0,
    132         1,
    133         soc_GBLLIMITRESETLIMITr_fields,
    134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    135         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    136         -1,
    137         -1,
    138     },
    139 #endif /* chips */
    140 
    141 #if defined(BCM_53540_A0)
    142     { /* SOC_REG_INT_GBLLIMITRESETLIMIT_BCM53540_A0r */
    143         soc_block_list[4],
    144         soc_genreg,
    145         1,
    146         0,
    147         0x208c800,
    148         0,
    149         0,
    150         1,
    151         soc_GBLLIMITRESETLIMITr_fields,
    152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    153         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    154         -1,
    155         -1,
    156     },
    157 #endif /* chips */
    158 
    159 #if defined(BCM_53570_A0)
    160     { /* SOC_REG_INT_GBLLIMITRESETLIMIT_BCM53570_A0r */
    161         soc_block_list[4],
    162         soc_genreg,
    163         1,
    164         0,
    165         0x20fbe00,
    166         0,
    167         0,
    168         1,
    169         soc_GBLLIMITRESETLIMITr_fields,
    170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    171         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    172         -1,
    173         -1,
    174     },
    175 #endif /* chips */
    176 
    177 #if defined(BCM_53570_B0)
    178     { /* SOC_REG_INT_GBLLIMITRESETLIMIT_BCM53570_B0r */
    179         soc_block_list[4],
    180         soc_genreg,
    181         1,
    182         0,
    183         0x20fc100,
    184         0,
    185         0,
    186         1,
    187         soc_GBLLIMITRESETLIMIT_BCM53570_B0r_fields,
    188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    189         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
    190         -1,
    191         -1,
    192     },
    193 #endif /* chips */
    194 
    195 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
    196     { /* SOC_REG_INT_GBLLIMITSETLIMITr */
    197         soc_block_list[4],
    198         soc_genreg,
    199         1,
    200         0,
    201         0x217b000,
    202         0,
    203         0,
    204         1,
    205         soc_GBLLIMITSETLIMITr_fields,
    206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    207         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    208         -1,
    209         -1,
    210     },
    211 #endif /* chips */
    212 
    213 #if defined(BCM_53540_A0)
    214     { /* SOC_REG_INT_GBLLIMITSETLIMIT_BCM53540_A0r */
    215         soc_block_list[4],
    216         soc_genreg,
    217         1,
    218         0,
    219         0x208c000,
    220         0,
    221         0,
    222         1,
    223         soc_GBLLIMITSETLIMITr_fields,
    224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    225         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    226         -1,
    227         -1,
    228     },
    229 #endif /* chips */
    230 
    231 #if defined(BCM_53570_A0)
    232     { /* SOC_REG_INT_GBLLIMITSETLIMIT_BCM53570_A0r */
    233         soc_block_list[4],
    234         soc_genreg,
    235         1,
    236         0,
    237         0x20fb600,
    238         0,
    239         0,
    240         1,
    241         soc_GBLLIMITSETLIMITr_fields,
    242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    243         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
    244         -1,
    245         -1,
    246     },
    247 #endif /* chips */
    248 
    249 #if defined(BCM_53570_B0)
    250     { /* SOC_REG_INT_GBLLIMITSETLIMIT_BCM53570_B0r */
    251         soc_block_list[4],
    252         soc_genreg,
    253         1,
    254         0,
    255         0x20fb900,
    256         0,
    257         0,
    258         1,
    259         soc_GBLLIMITSETLIMIT_BCM53570_B0r_fields,
    260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    261         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
    262         -1,
    263         -1,
    264     },
    265 #endif /* chips */
    266 
    267 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    268     { /* SOC_REG_INT_GCPOLr */
    269         soc_block_list[81],
    270         soc_genreg,
    271         1,
    272         0,
    273         0x80b38,
    274         0,
    275         0,
    276         8,
    277         soc_GCPOLr_fields,
    278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    279         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    280         -1,
    281         -1,
    282     },
    283 #endif /* chips */
    284 
    285 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    286     { /* SOC_REG_INT_GCTRLr */
    287         soc_block_list[81],
    288         soc_genreg,
    289         1,
    290         0,
    291         0x80004,
    292         0,
    293         0,
    294         9,
    295         soc_GCTRLr_fields,
    296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    297         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    298         -1,
    299         -1,
    300     },
    301 #endif /* chips */
    302 
    303 #if defined(BCM_53324_A0)
    304     { /* SOC_REG_INT_GE0_EEE_CONFIGr */
    305         soc_block_list[2],
    306         soc_genreg,
    307         1,
    308         0,
    309         0x80036,
    310         0,
    311         0,
    312         4,
    313         soc_GE0_EEE_CONFIGr_fields,
    314         SOC_RESET_VAL_DEC(0x000014e1, 0x00000000)
    315         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    316         -1,
    317         -1,
    318     },
    319 #endif /* chips */
    320 
    321 #if defined(BCM_53400_A0)
    322     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM53400_A0r */
    323         soc_block_list[9],
    324         soc_genreg,
    325         1,
    326         0,
    327         0x2022400,
    328         0,
    329         0,
    330         3,
    331         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
    332         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    333         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    334         -1,
    335         -1,
    336     },
    337 #endif /* chips */
    338 
    339 #if defined(BCM_53540_A0)
    340     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM53540_A0r */
    341         soc_block_list[2],
    342         soc_genreg,
    343         1,
    344         0,
    345         0x2022400,
    346         0,
    347         0,
    348         3,
    349         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
    350         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    351         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    352         -1,
    353         -1,
    354     },
    355 #endif /* chips */
    356 
    357 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
    358     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM53570_A0r */
    359         soc_block_list[2],
    360         soc_genreg,
    361         1,
    362         0,
    363         0x2022f00,
    364         0,
    365         0,
    366         3,
    367         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
    368         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    369         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    370         -1,
    371         -1,
    372     },
    373 #endif /* chips */
    374 
    375 #if defined(BCM_56150_A0)
    376     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM56150_A0r */
    377         soc_block_list[2],
    378         soc_genreg,
    379         1,
    380         0,
    381         0x2022400,
    382         0,
    383         0,
    384         3,
    385         soc_GE0_EEE_CONFIG_BCM56150_A0r_fields,
    386         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    387         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    388         -1,
    389         -1,
    390     },
    391 #endif /* chips */
    392 
    393 #if defined(BCM_56160_A0)
    394     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM56160_A0r */
    395         soc_block_list[2],
    396         soc_genreg,
    397         1,
    398         0,
    399         0x2022400,
    400         0,
    401         0,
    402         3,
    403         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
    404         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    405         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    406         -1,
    407         -1,
    408     },
    409 #endif /* chips */
    410 
    411 #if defined(BCM_56370_A0)
    412     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM56370_A0r */
    413         soc_block_list[9],
    414         soc_genreg,
    415         1,
    416         0,
    417         0x2022400,
    418         0,
    419         0,
    420         3,
    421         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
    422         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    423         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    424         -1,
    425         -1,
    426         3,
    427     },
    428 #endif /* chips */
    429 
    430 #if defined(BCM_56142_A0) || defined(BCM_56440_A0) || \
    431     defined(BCM_56440_B0)
    432     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM56440_A0r */
    433         soc_block_list[2],
    434         soc_genreg,
    435         1,
    436         0,
    437         0x80033,
    438         0,
    439         0,
    440         4,
    441         soc_GE0_EEE_CONFIG_BCM56440_A0r_fields,
    442         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    444         -1,
    445         -1,
    446     },
    447 #endif /* chips */
    448 
    449 #if defined(BCM_88375_A0)
    450     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM88375_A0r */
    451         soc_block_list[2],
    452         soc_genreg,
    453         1,
    454         0,
    455         0x2022400,
    456         0,
    457         0,
    458         3,
    459         soc_GE0_EEE_CONFIG_BCM88375_A0r_fields,
    460         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    461         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    462         -1,
    463         -1,
    464     },
    465 #endif /* chips */
    466 
    467 #if defined(BCM_88375_B0)
    468     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM88375_B0r */
    469         soc_block_list[2],
    470         soc_genreg,
    471         1,
    472         0,
    473         0x2022400,
    474         0,
    475         0,
    476         3,
    477         soc_GE0_EEE_CONFIG_BCM88375_B0r_fields,
    478         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    479         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    480         -1,
    481         -1,
    482     },
    483 #endif /* chips */
    484 
    485 #if defined(BCM_88470_A0)
    486     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM88470_A0r */
    487         soc_block_list[2],
    488         soc_genreg,
    489         1,
    490         0,
    491         0x2022400,
    492         0,
    493         0,
    494         3,
    495         soc_GE0_EEE_CONFIG_BCM88470_A0r_fields,
    496         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    497         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    498         -1,
    499         -1,
    500     },
    501 #endif /* chips */
    502 
    503 #if defined(BCM_88470_B0)
    504     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM88470_B0r */
    505         soc_block_list[2],
    506         soc_genreg,
    507         1,
    508         0,
    509         0x2022400,
    510         0,
    511         0,
    512         3,
    513         soc_GE0_EEE_CONFIG_BCM88470_B0r_fields,
    514         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    515         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    516         -1,
    517         -1,
    518     },
    519 #endif /* chips */
    520 
    521 #if defined(BCM_88675_A0)
    522     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM88675_A0r */
    523         soc_block_list[2],
    524         soc_genreg,
    525         1,
    526         0,
    527         0x2022400,
    528         0,
    529         0,
    530         3,
    531         soc_GE0_EEE_CONFIG_BCM88675_A0r_fields,
    532         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    533         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    534         -1,
    535         -1,
    536     },
    537 #endif /* chips */
    538 
    539 #if defined(BCM_88675_B0)
    540     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM88675_B0r */
    541         soc_block_list[2],
    542         soc_genreg,
    543         1,
    544         0,
    545         0x2022400,
    546         0,
    547         0,
    548         3,
    549         soc_GE0_EEE_CONFIG_BCM88675_B0r_fields,
    550         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    551         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    552         -1,
    553         -1,
    554     },
    555 #endif /* chips */
    556 
    557 #if defined(BCM_88680_A0)
    558     { /* SOC_REG_INT_GE0_EEE_CONFIG_BCM88680_A0r */
    559         soc_block_list[2],
    560         soc_genreg,
    561         1,
    562         0,
    563         0x2022400,
    564         0,
    565         0,
    566         3,
    567         soc_GE0_EEE_CONFIG_BCM88680_A0r_fields,
    568         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
    569         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    570         -1,
    571         -1,
    572     },
    573 #endif /* chips */
    574 
    575 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
    576     defined(BCM_56504_B0) || defined(BCM_56514_A0)
    577     { /* SOC_REG_INT_GE0_GBODE_CELL_CNTr */
    578         soc_block_list[2],
    579         soc_genreg,
    580         1,
    581         0,
    582         0x80010,
    583         SOC_REG_FLAG_RO,
    584         0,
    585         1,
    586         soc_GE0_GBODE_CELL_CNTr_fields,
    587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    588         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    589         -1,
    590         -1,
    591     },
    592 #endif /* chips */
    593 
    594 #if defined(BCM_53400_A0)
    595     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM53400_A0r */
    596         soc_block_list[9],
    597         soc_genreg,
    598         1,
    599         0,
    600         0x2021100,
    601         SOC_REG_FLAG_RO,
    602         0,
    603         1,
    604         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
    605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    606         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    607         -1,
    608         -1,
    609     },
    610 #endif /* chips */
    611 
    612 #if defined(BCM_53540_A0)
    613     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM53540_A0r */
    614         soc_block_list[2],
    615         soc_genreg,
    616         1,
    617         0,
    618         0x2021100,
    619         SOC_REG_FLAG_RO,
    620         0,
    621         1,
    622         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
    623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    624         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    625         -1,
    626         -1,
    627     },
    628 #endif /* chips */
    629 
    630 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
    631     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM53570_A0r */
    632         soc_block_list[2],
    633         soc_genreg,
    634         1,
    635         0,
    636         0x2021900,
    637         SOC_REG_FLAG_RO,
    638         0,
    639         1,
    640         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
    641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    642         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    643         -1,
    644         -1,
    645     },
    646 #endif /* chips */
    647 
    648 #if defined(BCM_56150_A0)
    649     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM56150_A0r */
    650         soc_block_list[2],
    651         soc_genreg,
    652         1,
    653         0,
    654         0x2021100,
    655         SOC_REG_FLAG_RO,
    656         0,
    657         1,
    658         soc_GE0_GBODE_CELL_CNT_BCM56150_A0r_fields,
    659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    661         -1,
    662         -1,
    663     },
    664 #endif /* chips */
    665 
    666 #if defined(BCM_56160_A0)
    667     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM56160_A0r */
    668         soc_block_list[2],
    669         soc_genreg,
    670         1,
    671         0,
    672         0x2021100,
    673         SOC_REG_FLAG_RO,
    674         0,
    675         1,
    676         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
    677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    678         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    679         -1,
    680         -1,
    681     },
    682 #endif /* chips */
    683 
    684 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
    685     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
    686     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
    687     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
    688     defined(BCM_56440_B0)
    689     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM56224_A0r */
    690         soc_block_list[2],
    691         soc_genreg,
    692         1,
    693         0,
    694         0x80010,
    695         SOC_REG_FLAG_RO,
    696         0,
    697         1,
    698         soc_GE_GBODE_CELL_CNTr_fields,
    699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    701         -1,
    702         -1,
    703     },
    704 #endif /* chips */
    705 
    706 #if defined(BCM_56370_A0)
    707     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM56370_A0r */
    708         soc_block_list[9],
    709         soc_genreg,
    710         1,
    711         0,
    712         0x2021100,
    713         SOC_REG_FLAG_RO,
    714         0,
    715         1,
    716         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
    717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    718         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    719         -1,
    720         -1,
    721         3,
    722     },
    723 #endif /* chips */
    724 
    725 #if defined(BCM_88375_A0)
    726     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM88375_A0r */
    727         soc_block_list[2],
    728         soc_genreg,
    729         1,
    730         0,
    731         0x2021100,
    732         SOC_REG_FLAG_RO,
    733         0,
    734         1,
    735         soc_GE0_GBODE_CELL_CNT_BCM88375_A0r_fields,
    736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    737         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    738         -1,
    739         -1,
    740     },
    741 #endif /* chips */
    742 
    743 #if defined(BCM_88375_B0)
    744     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM88375_B0r */
    745         soc_block_list[2],
    746         soc_genreg,
    747         1,
    748         0,
    749         0x2021100,
    750         SOC_REG_FLAG_RO,
    751         0,
    752         1,
    753         soc_GE0_GBODE_CELL_CNT_BCM88375_B0r_fields,
    754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    755         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    756         -1,
    757         -1,
    758     },
    759 #endif /* chips */
    760 
    761 #if defined(BCM_88470_A0)
    762     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM88470_A0r */
    763         soc_block_list[2],
    764         soc_genreg,
    765         1,
    766         0,
    767         0x2021100,
    768         SOC_REG_FLAG_RO,
    769         0,
    770         1,
    771         soc_GE0_GBODE_CELL_CNT_BCM88470_A0r_fields,
    772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    773         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    774         -1,
    775         -1,
    776     },
    777 #endif /* chips */
    778 
    779 #if defined(BCM_88470_B0)
    780     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM88470_B0r */
    781         soc_block_list[2],
    782         soc_genreg,
    783         1,
    784         0,
    785         0x2021100,
    786         SOC_REG_FLAG_RO,
    787         0,
    788         1,
    789         soc_GE0_GBODE_CELL_CNT_BCM88470_B0r_fields,
    790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    791         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    792         -1,
    793         -1,
    794     },
    795 #endif /* chips */
    796 
    797 #if defined(BCM_88675_A0)
    798     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM88675_A0r */
    799         soc_block_list[2],
    800         soc_genreg,
    801         1,
    802         0,
    803         0x2021100,
    804         SOC_REG_FLAG_RO,
    805         0,
    806         1,
    807         soc_GE0_GBODE_CELL_CNT_BCM88675_A0r_fields,
    808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    809         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    810         -1,
    811         -1,
    812     },
    813 #endif /* chips */
    814 
    815 #if defined(BCM_88675_B0)
    816     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM88675_B0r */
    817         soc_block_list[2],
    818         soc_genreg,
    819         1,
    820         0,
    821         0x2021100,
    822         SOC_REG_FLAG_RO,
    823         0,
    824         1,
    825         soc_GE0_GBODE_CELL_CNT_BCM88675_B0r_fields,
    826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    827         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    828         -1,
    829         -1,
    830     },
    831 #endif /* chips */
    832 
    833 #if defined(BCM_88680_A0)
    834     { /* SOC_REG_INT_GE0_GBODE_CELL_CNT_BCM88680_A0r */
    835         soc_block_list[2],
    836         soc_genreg,
    837         1,
    838         0,
    839         0x2021100,
    840         SOC_REG_FLAG_RO,
    841         0,
    842         1,
    843         soc_GE0_GBODE_CELL_CNT_BCM88680_A0r_fields,
    844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    845         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
    846         -1,
    847         -1,
    848     },
    849 #endif /* chips */
    850 
    851 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
    852     defined(BCM_56504_B0) || defined(BCM_56514_A0)
    853     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNTr */
    854         soc_block_list[2],
    855         soc_genreg,
    856         1,
    857         0,
    858         0x8001c,
    859         SOC_REG_FLAG_RO,
    860         0,
    861         1,
    862         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
    863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    864         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
    865         -1,
    866         -1,
    867     },
    868 #endif /* chips */
    869 
    870 #if defined(BCM_53400_A0)
    871     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r */
    872         soc_block_list[9],
    873         soc_genreg,
    874         1,
    875         0,
    876         0x2021900,
    877         SOC_REG_FLAG_RO,
    878         0,
    879         1,
    880         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
    881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    882         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    883         -1,
    884         -1,
    885     },
    886 #endif /* chips */
    887 
    888 #if defined(BCM_53540_A0)
    889     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM53540_A0r */
    890         soc_block_list[2],
    891         soc_genreg,
    892         1,
    893         0,
    894         0x2021900,
    895         SOC_REG_FLAG_RO,
    896         0,
    897         1,
    898         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
    899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    901         -1,
    902         -1,
    903     },
    904 #endif /* chips */
    905 
    906 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
    907     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM53570_A0r */
    908         soc_block_list[2],
    909         soc_genreg,
    910         1,
    911         0,
    912         0x2022100,
    913         SOC_REG_FLAG_RO,
    914         0,
    915         1,
    916         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
    917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    919         -1,
    920         -1,
    921     },
    922 #endif /* chips */
    923 
    924 #if defined(BCM_56150_A0)
    925     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM56150_A0r */
    926         soc_block_list[2],
    927         soc_genreg,
    928         1,
    929         0,
    930         0x2021900,
    931         SOC_REG_FLAG_RO,
    932         0,
    933         1,
    934         soc_GE0_GBODE_CELL_REQ_CNT_BCM56150_A0r_fields,
    935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    936         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    937         -1,
    938         -1,
    939     },
    940 #endif /* chips */
    941 
    942 #if defined(BCM_56160_A0)
    943     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM56160_A0r */
    944         soc_block_list[2],
    945         soc_genreg,
    946         1,
    947         0,
    948         0x2021900,
    949         SOC_REG_FLAG_RO,
    950         0,
    951         1,
    952         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
    953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    954         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    955         -1,
    956         -1,
    957     },
    958 #endif /* chips */
    959 
    960 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
    961     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
    962     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
    963     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
    964     defined(BCM_56440_B0)
    965     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM56224_A0r */
    966         soc_block_list[2],
    967         soc_genreg,
    968         1,
    969         0,
    970         0x8001c,
    971         SOC_REG_FLAG_RO,
    972         0,
    973         1,
    974         soc_GE_GBODE_CELL_REQ_CNTr_fields,
    975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    976         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    977         -1,
    978         -1,
    979     },
    980 #endif /* chips */
    981 
    982 #if defined(BCM_56370_A0)
    983     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM56370_A0r */
    984         soc_block_list[9],
    985         soc_genreg,
    986         1,
    987         0,
    988         0x2021900,
    989         SOC_REG_FLAG_RO,
    990         0,
    991         1,
    992         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
    993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    994         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    995         -1,
    996         -1,
    997         3,
    998     },
    999 #endif /* chips */
   1000 
   1001 #if defined(BCM_88375_A0)
   1002     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM88375_A0r */
   1003         soc_block_list[2],
   1004         soc_genreg,
   1005         1,
   1006         0,
   1007         0x2021900,
   1008         SOC_REG_FLAG_RO,
   1009         0,
   1010         1,
   1011         soc_GE0_GBODE_CELL_REQ_CNT_BCM88375_A0r_fields,
   1012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1013         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1014         -1,
   1015         -1,
   1016     },
   1017 #endif /* chips */
   1018 
   1019 #if defined(BCM_88375_B0)
   1020     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM88375_B0r */
   1021         soc_block_list[2],
   1022         soc_genreg,
   1023         1,
   1024         0,
   1025         0x2021900,
   1026         SOC_REG_FLAG_RO,
   1027         0,
   1028         1,
   1029         soc_GE0_GBODE_CELL_REQ_CNT_BCM88375_B0r_fields,
   1030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1031         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1032         -1,
   1033         -1,
   1034     },
   1035 #endif /* chips */
   1036 
   1037 #if defined(BCM_88470_A0)
   1038     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM88470_A0r */
   1039         soc_block_list[2],
   1040         soc_genreg,
   1041         1,
   1042         0,
   1043         0x2021900,
   1044         SOC_REG_FLAG_RO,
   1045         0,
   1046         1,
   1047         soc_GE0_GBODE_CELL_REQ_CNT_BCM88470_A0r_fields,
   1048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1049         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1050         -1,
   1051         -1,
   1052     },
   1053 #endif /* chips */
   1054 
   1055 #if defined(BCM_88470_B0)
   1056     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM88470_B0r */
   1057         soc_block_list[2],
   1058         soc_genreg,
   1059         1,
   1060         0,
   1061         0x2021900,
   1062         SOC_REG_FLAG_RO,
   1063         0,
   1064         1,
   1065         soc_GE0_GBODE_CELL_REQ_CNT_BCM88470_B0r_fields,
   1066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1067         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1068         -1,
   1069         -1,
   1070     },
   1071 #endif /* chips */
   1072 
   1073 #if defined(BCM_88675_A0)
   1074     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM88675_A0r */
   1075         soc_block_list[2],
   1076         soc_genreg,
   1077         1,
   1078         0,
   1079         0x2021900,
   1080         SOC_REG_FLAG_RO,
   1081         0,
   1082         1,
   1083         soc_GE0_GBODE_CELL_REQ_CNT_BCM88675_A0r_fields,
   1084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1085         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1086         -1,
   1087         -1,
   1088     },
   1089 #endif /* chips */
   1090 
   1091 #if defined(BCM_88675_B0)
   1092     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM88675_B0r */
   1093         soc_block_list[2],
   1094         soc_genreg,
   1095         1,
   1096         0,
   1097         0x2021900,
   1098         SOC_REG_FLAG_RO,
   1099         0,
   1100         1,
   1101         soc_GE0_GBODE_CELL_REQ_CNT_BCM88675_B0r_fields,
   1102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1103         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1104         -1,
   1105         -1,
   1106     },
   1107 #endif /* chips */
   1108 
   1109 #if defined(BCM_88680_A0)
   1110     { /* SOC_REG_INT_GE0_GBODE_CELL_REQ_CNT_BCM88680_A0r */
   1111         soc_block_list[2],
   1112         soc_genreg,
   1113         1,
   1114         0,
   1115         0x2021900,
   1116         SOC_REG_FLAG_RO,
   1117         0,
   1118         1,
   1119         soc_GE0_GBODE_CELL_REQ_CNT_BCM88680_A0r_fields,
   1120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1121         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1122         -1,
   1123         -1,
   1124     },
   1125 #endif /* chips */
   1126 
   1127 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   1128     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   1129     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   1130     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   1131     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   1132     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
   1133     defined(BCM_56514_A0)
   1134     { /* SOC_REG_INT_GE0_GBOD_OVRFLWr */
   1135         soc_block_list[2],
   1136         soc_genreg,
   1137         1,
   1138         0,
   1139         0x80004,
   1140         SOC_REG_FLAG_RO,
   1141         0,
   1142         1,
   1143         soc_GE0_GBOD_OVRFLWr_fields,
   1144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1145         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1146         -1,
   1147         -1,
   1148     },
   1149 #endif /* chips */
   1150 
   1151 #if defined(BCM_53400_A0)
   1152     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM53400_A0r */
   1153         soc_block_list[9],
   1154         soc_genreg,
   1155         1,
   1156         0,
   1157         0x2020900,
   1158         SOC_REG_FLAG_RO,
   1159         0,
   1160         1,
   1161         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   1162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1163         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1164         -1,
   1165         -1,
   1166     },
   1167 #endif /* chips */
   1168 
   1169 #if defined(BCM_53540_A0)
   1170     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM53540_A0r */
   1171         soc_block_list[2],
   1172         soc_genreg,
   1173         1,
   1174         0,
   1175         0x2020900,
   1176         SOC_REG_FLAG_RO,
   1177         0,
   1178         1,
   1179         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   1180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1181         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1182         -1,
   1183         -1,
   1184     },
   1185 #endif /* chips */
   1186 
   1187 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   1188     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM53570_A0r */
   1189         soc_block_list[2],
   1190         soc_genreg,
   1191         1,
   1192         0,
   1193         0x2021100,
   1194         SOC_REG_FLAG_RO,
   1195         0,
   1196         1,
   1197         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   1198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1199         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1200         -1,
   1201         -1,
   1202     },
   1203 #endif /* chips */
   1204 
   1205 #if defined(BCM_56150_A0)
   1206     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM56150_A0r */
   1207         soc_block_list[2],
   1208         soc_genreg,
   1209         1,
   1210         0,
   1211         0x2020900,
   1212         SOC_REG_FLAG_RO,
   1213         0,
   1214         1,
   1215         soc_PORT_CDC_RXFIFO_OVRFLW_BCM56640_A0r_fields,
   1216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1217         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1218         -1,
   1219         -1,
   1220     },
   1221 #endif /* chips */
   1222 
   1223 #if defined(BCM_56160_A0)
   1224     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM56160_A0r */
   1225         soc_block_list[2],
   1226         soc_genreg,
   1227         1,
   1228         0,
   1229         0x2020900,
   1230         SOC_REG_FLAG_RO,
   1231         0,
   1232         1,
   1233         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   1234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1235         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1236         -1,
   1237         -1,
   1238     },
   1239 #endif /* chips */
   1240 
   1241 #if defined(BCM_56370_A0)
   1242     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM56370_A0r */
   1243         soc_block_list[9],
   1244         soc_genreg,
   1245         1,
   1246         0,
   1247         0x2020900,
   1248         SOC_REG_FLAG_RO,
   1249         0,
   1250         1,
   1251         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   1252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1253         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1254         -1,
   1255         -1,
   1256         3,
   1257     },
   1258 #endif /* chips */
   1259 
   1260 #if defined(BCM_88375_A0)
   1261     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM88375_A0r */
   1262         soc_block_list[2],
   1263         soc_genreg,
   1264         1,
   1265         0,
   1266         0x2020900,
   1267         SOC_REG_FLAG_RO,
   1268         0,
   1269         1,
   1270         soc_GE0_GBOD_OVRFLW_BCM88375_A0r_fields,
   1271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1272         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1273         -1,
   1274         -1,
   1275     },
   1276 #endif /* chips */
   1277 
   1278 #if defined(BCM_88375_B0)
   1279     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM88375_B0r */
   1280         soc_block_list[2],
   1281         soc_genreg,
   1282         1,
   1283         0,
   1284         0x2020900,
   1285         SOC_REG_FLAG_RO,
   1286         0,
   1287         1,
   1288         soc_GE0_GBOD_OVRFLW_BCM88375_B0r_fields,
   1289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1290         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1291         -1,
   1292         -1,
   1293     },
   1294 #endif /* chips */
   1295 
   1296 #if defined(BCM_88470_A0)
   1297     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM88470_A0r */
   1298         soc_block_list[2],
   1299         soc_genreg,
   1300         1,
   1301         0,
   1302         0x2020900,
   1303         SOC_REG_FLAG_RO,
   1304         0,
   1305         1,
   1306         soc_GE0_GBOD_OVRFLW_BCM88470_A0r_fields,
   1307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1308         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1309         -1,
   1310         -1,
   1311     },
   1312 #endif /* chips */
   1313 
   1314 #if defined(BCM_88470_B0)
   1315     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM88470_B0r */
   1316         soc_block_list[2],
   1317         soc_genreg,
   1318         1,
   1319         0,
   1320         0x2020900,
   1321         SOC_REG_FLAG_RO,
   1322         0,
   1323         1,
   1324         soc_GE0_GBOD_OVRFLW_BCM88470_B0r_fields,
   1325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1326         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1327         -1,
   1328         -1,
   1329     },
   1330 #endif /* chips */
   1331 
   1332 #if defined(BCM_88675_A0)
   1333     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM88675_A0r */
   1334         soc_block_list[2],
   1335         soc_genreg,
   1336         1,
   1337         0,
   1338         0x2020900,
   1339         SOC_REG_FLAG_RO,
   1340         0,
   1341         1,
   1342         soc_GE0_GBOD_OVRFLW_BCM88675_A0r_fields,
   1343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1344         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1345         -1,
   1346         -1,
   1347     },
   1348 #endif /* chips */
   1349 
   1350 #if defined(BCM_88675_B0)
   1351     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM88675_B0r */
   1352         soc_block_list[2],
   1353         soc_genreg,
   1354         1,
   1355         0,
   1356         0x2020900,
   1357         SOC_REG_FLAG_RO,
   1358         0,
   1359         1,
   1360         soc_GE0_GBOD_OVRFLW_BCM88675_B0r_fields,
   1361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1362         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1363         -1,
   1364         -1,
   1365     },
   1366 #endif /* chips */
   1367 
   1368 #if defined(BCM_88680_A0)
   1369     { /* SOC_REG_INT_GE0_GBOD_OVRFLW_BCM88680_A0r */
   1370         soc_block_list[2],
   1371         soc_genreg,
   1372         1,
   1373         0,
   1374         0x2020900,
   1375         SOC_REG_FLAG_RO,
   1376         0,
   1377         1,
   1378         soc_GE0_GBOD_OVRFLW_BCM88680_A0r_fields,
   1379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1380         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1381         -1,
   1382         -1,
   1383     },
   1384 #endif /* chips */
   1385 
   1386 #if defined(BCM_53570_A0)
   1387     { /* SOC_REG_INT_GE0_MIN_FRAG_SIZEr */
   1388         soc_block_list[2],
   1389         soc_genreg,
   1390         1,
   1391         0,
   1392         0x2020900,
   1393         0,
   1394         0,
   1395         2,
   1396         soc_GE0_MIN_FRAG_SIZEr_fields,
   1397         SOC_RESET_VAL_DEC(0x00000387, 0x00000000)
   1398         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1399         -1,
   1400         -1,
   1401     },
   1402 #endif /* chips */
   1403 
   1404 #if defined(BCM_53570_B0)
   1405     { /* SOC_REG_INT_GE0_MIN_FRAG_SIZE_BCM53570_B0r */
   1406         soc_block_list[2],
   1407         soc_genreg,
   1408         1,
   1409         0,
   1410         0x2020900,
   1411         0,
   1412         0,
   1413         2,
   1414         soc_GE0_MIN_FRAG_SIZE_BCM53570_B0r_fields,
   1415         SOC_RESET_VAL_DEC(0x00000408, 0x00000000)
   1416         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1417         -1,
   1418         -1,
   1419     },
   1420 #endif /* chips */
   1421 
   1422 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1423     { /* SOC_REG_INT_GE0_S3MII_SPEED_DEBUGr */
   1424         soc_block_list[2],
   1425         soc_genreg,
   1426         1,
   1427         0,
   1428         0x8003b,
   1429         SOC_REG_FLAG_RO,
   1430         0,
   1431         4,
   1432         soc_GE0_S3MII_SPEED_DEBUGr_fields,
   1433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1434         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1435         -1,
   1436         -1,
   1437     },
   1438 #endif /* chips */
   1439 
   1440 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1441     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1442     { /* SOC_REG_INT_GE10_GBODE_CELL_CNTr */
   1443         soc_block_list[2],
   1444         soc_genreg,
   1445         1,
   1446         0,
   1447         0x8001a,
   1448         SOC_REG_FLAG_RO,
   1449         0,
   1450         1,
   1451         soc_GE0_GBODE_CELL_CNTr_fields,
   1452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1453         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1454         -1,
   1455         -1,
   1456     },
   1457 #endif /* chips */
   1458 
   1459 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   1460     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   1461     { /* SOC_REG_INT_GE10_GBODE_CELL_CNT_BCM56224_A0r */
   1462         soc_block_list[2],
   1463         soc_genreg,
   1464         1,
   1465         0,
   1466         0x8001a,
   1467         SOC_REG_FLAG_RO,
   1468         0,
   1469         1,
   1470         soc_GE_GBODE_CELL_CNTr_fields,
   1471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1472         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1473         -1,
   1474         -1,
   1475     },
   1476 #endif /* chips */
   1477 
   1478 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1479     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1480     { /* SOC_REG_INT_GE10_GBODE_CELL_REQ_CNTr */
   1481         soc_block_list[2],
   1482         soc_genreg,
   1483         1,
   1484         0,
   1485         0x80026,
   1486         SOC_REG_FLAG_RO,
   1487         0,
   1488         1,
   1489         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   1490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1491         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1492         -1,
   1493         -1,
   1494     },
   1495 #endif /* chips */
   1496 
   1497 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   1498     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   1499     { /* SOC_REG_INT_GE10_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   1500         soc_block_list[2],
   1501         soc_genreg,
   1502         1,
   1503         0,
   1504         0x80026,
   1505         SOC_REG_FLAG_RO,
   1506         0,
   1507         1,
   1508         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   1509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1510         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1511         -1,
   1512         -1,
   1513     },
   1514 #endif /* chips */
   1515 
   1516 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   1517     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
   1518     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1519     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1520     { /* SOC_REG_INT_GE10_GBOD_OVRFLWr */
   1521         soc_block_list[2],
   1522         soc_genreg,
   1523         1,
   1524         0,
   1525         0x8000e,
   1526         SOC_REG_FLAG_RO,
   1527         0,
   1528         1,
   1529         soc_GE0_GBOD_OVRFLWr_fields,
   1530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1531         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1532         -1,
   1533         -1,
   1534     },
   1535 #endif /* chips */
   1536 
   1537 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1538     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1539     { /* SOC_REG_INT_GE11_GBODE_CELL_CNTr */
   1540         soc_block_list[2],
   1541         soc_genreg,
   1542         1,
   1543         0,
   1544         0x8001b,
   1545         SOC_REG_FLAG_RO,
   1546         0,
   1547         1,
   1548         soc_GE0_GBODE_CELL_CNTr_fields,
   1549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1550         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1551         -1,
   1552         -1,
   1553     },
   1554 #endif /* chips */
   1555 
   1556 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   1557     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   1558     { /* SOC_REG_INT_GE11_GBODE_CELL_CNT_BCM56224_A0r */
   1559         soc_block_list[2],
   1560         soc_genreg,
   1561         1,
   1562         0,
   1563         0x8001b,
   1564         SOC_REG_FLAG_RO,
   1565         0,
   1566         1,
   1567         soc_GE_GBODE_CELL_CNTr_fields,
   1568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1569         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1570         -1,
   1571         -1,
   1572     },
   1573 #endif /* chips */
   1574 
   1575 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1576     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1577     { /* SOC_REG_INT_GE11_GBODE_CELL_REQ_CNTr */
   1578         soc_block_list[2],
   1579         soc_genreg,
   1580         1,
   1581         0,
   1582         0x80027,
   1583         SOC_REG_FLAG_RO,
   1584         0,
   1585         1,
   1586         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   1587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1588         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1589         -1,
   1590         -1,
   1591     },
   1592 #endif /* chips */
   1593 
   1594 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   1595     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   1596     { /* SOC_REG_INT_GE11_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   1597         soc_block_list[2],
   1598         soc_genreg,
   1599         1,
   1600         0,
   1601         0x80027,
   1602         SOC_REG_FLAG_RO,
   1603         0,
   1604         1,
   1605         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   1606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1607         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1608         -1,
   1609         -1,
   1610     },
   1611 #endif /* chips */
   1612 
   1613 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   1614     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
   1615     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1616     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1617     { /* SOC_REG_INT_GE11_GBOD_OVRFLWr */
   1618         soc_block_list[2],
   1619         soc_genreg,
   1620         1,
   1621         0,
   1622         0x8000f,
   1623         SOC_REG_FLAG_RO,
   1624         0,
   1625         1,
   1626         soc_GE0_GBOD_OVRFLWr_fields,
   1627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1628         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1629         -1,
   1630         -1,
   1631     },
   1632 #endif /* chips */
   1633 
   1634 #if defined(BCM_53324_A0)
   1635     { /* SOC_REG_INT_GE1_EEE_CONFIGr */
   1636         soc_block_list[2],
   1637         soc_genreg,
   1638         1,
   1639         0,
   1640         0x80037,
   1641         0,
   1642         0,
   1643         4,
   1644         soc_GE0_EEE_CONFIGr_fields,
   1645         SOC_RESET_VAL_DEC(0x000014e1, 0x00000000)
   1646         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1647         -1,
   1648         -1,
   1649     },
   1650 #endif /* chips */
   1651 
   1652 #if defined(BCM_53400_A0)
   1653     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM53400_A0r */
   1654         soc_block_list[9],
   1655         soc_genreg,
   1656         1,
   1657         0,
   1658         0x2022500,
   1659         0,
   1660         0,
   1661         3,
   1662         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   1663         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1664         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1665         -1,
   1666         -1,
   1667     },
   1668 #endif /* chips */
   1669 
   1670 #if defined(BCM_53540_A0)
   1671     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM53540_A0r */
   1672         soc_block_list[2],
   1673         soc_genreg,
   1674         1,
   1675         0,
   1676         0x2022500,
   1677         0,
   1678         0,
   1679         3,
   1680         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   1681         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1682         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1683         -1,
   1684         -1,
   1685     },
   1686 #endif /* chips */
   1687 
   1688 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   1689     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM53570_A0r */
   1690         soc_block_list[2],
   1691         soc_genreg,
   1692         1,
   1693         0,
   1694         0x2023000,
   1695         0,
   1696         0,
   1697         3,
   1698         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   1699         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1700         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1701         -1,
   1702         -1,
   1703     },
   1704 #endif /* chips */
   1705 
   1706 #if defined(BCM_56150_A0)
   1707     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM56150_A0r */
   1708         soc_block_list[2],
   1709         soc_genreg,
   1710         1,
   1711         0,
   1712         0x2022500,
   1713         0,
   1714         0,
   1715         3,
   1716         soc_GE0_EEE_CONFIG_BCM56150_A0r_fields,
   1717         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1718         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1719         -1,
   1720         -1,
   1721     },
   1722 #endif /* chips */
   1723 
   1724 #if defined(BCM_56160_A0)
   1725     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM56160_A0r */
   1726         soc_block_list[2],
   1727         soc_genreg,
   1728         1,
   1729         0,
   1730         0x2022500,
   1731         0,
   1732         0,
   1733         3,
   1734         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   1735         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1736         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1737         -1,
   1738         -1,
   1739     },
   1740 #endif /* chips */
   1741 
   1742 #if defined(BCM_56370_A0)
   1743     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM56370_A0r */
   1744         soc_block_list[9],
   1745         soc_genreg,
   1746         1,
   1747         0,
   1748         0x2022500,
   1749         0,
   1750         0,
   1751         3,
   1752         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   1753         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1754         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1755         -1,
   1756         -1,
   1757         3,
   1758     },
   1759 #endif /* chips */
   1760 
   1761 #if defined(BCM_56142_A0) || defined(BCM_56440_A0) || \
   1762     defined(BCM_56440_B0)
   1763     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM56440_A0r */
   1764         soc_block_list[2],
   1765         soc_genreg,
   1766         1,
   1767         0,
   1768         0x80034,
   1769         0,
   1770         0,
   1771         4,
   1772         soc_GE0_EEE_CONFIG_BCM56440_A0r_fields,
   1773         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1775         -1,
   1776         -1,
   1777     },
   1778 #endif /* chips */
   1779 
   1780 #if defined(BCM_88375_A0)
   1781     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM88375_A0r */
   1782         soc_block_list[2],
   1783         soc_genreg,
   1784         1,
   1785         0,
   1786         0x2022500,
   1787         0,
   1788         0,
   1789         3,
   1790         soc_GE1_EEE_CONFIG_BCM88375_A0r_fields,
   1791         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1792         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1793         -1,
   1794         -1,
   1795     },
   1796 #endif /* chips */
   1797 
   1798 #if defined(BCM_88375_B0)
   1799     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM88375_B0r */
   1800         soc_block_list[2],
   1801         soc_genreg,
   1802         1,
   1803         0,
   1804         0x2022500,
   1805         0,
   1806         0,
   1807         3,
   1808         soc_GE1_EEE_CONFIG_BCM88375_B0r_fields,
   1809         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1810         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1811         -1,
   1812         -1,
   1813     },
   1814 #endif /* chips */
   1815 
   1816 #if defined(BCM_88470_A0)
   1817     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM88470_A0r */
   1818         soc_block_list[2],
   1819         soc_genreg,
   1820         1,
   1821         0,
   1822         0x2022500,
   1823         0,
   1824         0,
   1825         3,
   1826         soc_GE1_EEE_CONFIG_BCM88470_A0r_fields,
   1827         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1828         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1829         -1,
   1830         -1,
   1831     },
   1832 #endif /* chips */
   1833 
   1834 #if defined(BCM_88470_B0)
   1835     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM88470_B0r */
   1836         soc_block_list[2],
   1837         soc_genreg,
   1838         1,
   1839         0,
   1840         0x2022500,
   1841         0,
   1842         0,
   1843         3,
   1844         soc_GE1_EEE_CONFIG_BCM88470_B0r_fields,
   1845         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1846         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1847         -1,
   1848         -1,
   1849     },
   1850 #endif /* chips */
   1851 
   1852 #if defined(BCM_88675_A0)
   1853     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM88675_A0r */
   1854         soc_block_list[2],
   1855         soc_genreg,
   1856         1,
   1857         0,
   1858         0x2022500,
   1859         0,
   1860         0,
   1861         3,
   1862         soc_GE1_EEE_CONFIGr_fields,
   1863         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1864         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1865         -1,
   1866         -1,
   1867     },
   1868 #endif /* chips */
   1869 
   1870 #if defined(BCM_88675_B0)
   1871     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM88675_B0r */
   1872         soc_block_list[2],
   1873         soc_genreg,
   1874         1,
   1875         0,
   1876         0x2022500,
   1877         0,
   1878         0,
   1879         3,
   1880         soc_GE1_EEE_CONFIG_BCM88675_B0r_fields,
   1881         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1882         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1883         -1,
   1884         -1,
   1885     },
   1886 #endif /* chips */
   1887 
   1888 #if defined(BCM_88680_A0)
   1889     { /* SOC_REG_INT_GE1_EEE_CONFIG_BCM88680_A0r */
   1890         soc_block_list[2],
   1891         soc_genreg,
   1892         1,
   1893         0,
   1894         0x2022500,
   1895         0,
   1896         0,
   1897         3,
   1898         soc_GE1_EEE_CONFIG_BCM88680_A0r_fields,
   1899         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   1900         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   1901         -1,
   1902         -1,
   1903     },
   1904 #endif /* chips */
   1905 
   1906 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1907     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1908     { /* SOC_REG_INT_GE1_GBODE_CELL_CNTr */
   1909         soc_block_list[2],
   1910         soc_genreg,
   1911         1,
   1912         0,
   1913         0x80011,
   1914         SOC_REG_FLAG_RO,
   1915         0,
   1916         1,
   1917         soc_GE0_GBODE_CELL_CNTr_fields,
   1918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1919         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1920         -1,
   1921         -1,
   1922     },
   1923 #endif /* chips */
   1924 
   1925 #if defined(BCM_53400_A0)
   1926     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM53400_A0r */
   1927         soc_block_list[9],
   1928         soc_genreg,
   1929         1,
   1930         0,
   1931         0x2021200,
   1932         SOC_REG_FLAG_RO,
   1933         0,
   1934         1,
   1935         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   1936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1938         -1,
   1939         -1,
   1940     },
   1941 #endif /* chips */
   1942 
   1943 #if defined(BCM_53540_A0)
   1944     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM53540_A0r */
   1945         soc_block_list[2],
   1946         soc_genreg,
   1947         1,
   1948         0,
   1949         0x2021200,
   1950         SOC_REG_FLAG_RO,
   1951         0,
   1952         1,
   1953         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   1954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1956         -1,
   1957         -1,
   1958     },
   1959 #endif /* chips */
   1960 
   1961 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   1962     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM53570_A0r */
   1963         soc_block_list[2],
   1964         soc_genreg,
   1965         1,
   1966         0,
   1967         0x2021a00,
   1968         SOC_REG_FLAG_RO,
   1969         0,
   1970         1,
   1971         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   1972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1973         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1974         -1,
   1975         -1,
   1976     },
   1977 #endif /* chips */
   1978 
   1979 #if defined(BCM_56150_A0)
   1980     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM56150_A0r */
   1981         soc_block_list[2],
   1982         soc_genreg,
   1983         1,
   1984         0,
   1985         0x2021200,
   1986         SOC_REG_FLAG_RO,
   1987         0,
   1988         1,
   1989         soc_GE0_GBODE_CELL_CNT_BCM56150_A0r_fields,
   1990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1992         -1,
   1993         -1,
   1994     },
   1995 #endif /* chips */
   1996 
   1997 #if defined(BCM_56160_A0)
   1998     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM56160_A0r */
   1999         soc_block_list[2],
   2000         soc_genreg,
   2001         1,
   2002         0,
   2003         0x2021200,
   2004         SOC_REG_FLAG_RO,
   2005         0,
   2006         1,
   2007         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   2008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2010         -1,
   2011         -1,
   2012     },
   2013 #endif /* chips */
   2014 
   2015 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   2016     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   2017     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   2018     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   2019     defined(BCM_56440_B0)
   2020     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM56224_A0r */
   2021         soc_block_list[2],
   2022         soc_genreg,
   2023         1,
   2024         0,
   2025         0x80011,
   2026         SOC_REG_FLAG_RO,
   2027         0,
   2028         1,
   2029         soc_GE_GBODE_CELL_CNTr_fields,
   2030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2032         -1,
   2033         -1,
   2034     },
   2035 #endif /* chips */
   2036 
   2037 #if defined(BCM_56370_A0)
   2038     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM56370_A0r */
   2039         soc_block_list[9],
   2040         soc_genreg,
   2041         1,
   2042         0,
   2043         0x2021200,
   2044         SOC_REG_FLAG_RO,
   2045         0,
   2046         1,
   2047         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   2048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2050         -1,
   2051         -1,
   2052         3,
   2053     },
   2054 #endif /* chips */
   2055 
   2056 #if defined(BCM_88375_A0)
   2057     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM88375_A0r */
   2058         soc_block_list[2],
   2059         soc_genreg,
   2060         1,
   2061         0,
   2062         0x2021200,
   2063         SOC_REG_FLAG_RO,
   2064         0,
   2065         1,
   2066         soc_GE1_GBODE_CELL_CNT_BCM88375_A0r_fields,
   2067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2068         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2069         -1,
   2070         -1,
   2071     },
   2072 #endif /* chips */
   2073 
   2074 #if defined(BCM_88375_B0)
   2075     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM88375_B0r */
   2076         soc_block_list[2],
   2077         soc_genreg,
   2078         1,
   2079         0,
   2080         0x2021200,
   2081         SOC_REG_FLAG_RO,
   2082         0,
   2083         1,
   2084         soc_GE1_GBODE_CELL_CNT_BCM88375_B0r_fields,
   2085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2086         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2087         -1,
   2088         -1,
   2089     },
   2090 #endif /* chips */
   2091 
   2092 #if defined(BCM_88470_A0)
   2093     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM88470_A0r */
   2094         soc_block_list[2],
   2095         soc_genreg,
   2096         1,
   2097         0,
   2098         0x2021200,
   2099         SOC_REG_FLAG_RO,
   2100         0,
   2101         1,
   2102         soc_GE1_GBODE_CELL_CNT_BCM88470_A0r_fields,
   2103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2104         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2105         -1,
   2106         -1,
   2107     },
   2108 #endif /* chips */
   2109 
   2110 #if defined(BCM_88470_B0)
   2111     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM88470_B0r */
   2112         soc_block_list[2],
   2113         soc_genreg,
   2114         1,
   2115         0,
   2116         0x2021200,
   2117         SOC_REG_FLAG_RO,
   2118         0,
   2119         1,
   2120         soc_GE1_GBODE_CELL_CNT_BCM88470_B0r_fields,
   2121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2122         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2123         -1,
   2124         -1,
   2125     },
   2126 #endif /* chips */
   2127 
   2128 #if defined(BCM_88675_A0)
   2129     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM88675_A0r */
   2130         soc_block_list[2],
   2131         soc_genreg,
   2132         1,
   2133         0,
   2134         0x2021200,
   2135         SOC_REG_FLAG_RO,
   2136         0,
   2137         1,
   2138         soc_GE1_GBODE_CELL_CNTr_fields,
   2139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2140         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2141         -1,
   2142         -1,
   2143     },
   2144 #endif /* chips */
   2145 
   2146 #if defined(BCM_88675_B0)
   2147     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM88675_B0r */
   2148         soc_block_list[2],
   2149         soc_genreg,
   2150         1,
   2151         0,
   2152         0x2021200,
   2153         SOC_REG_FLAG_RO,
   2154         0,
   2155         1,
   2156         soc_GE1_GBODE_CELL_CNT_BCM88675_B0r_fields,
   2157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2158         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2159         -1,
   2160         -1,
   2161     },
   2162 #endif /* chips */
   2163 
   2164 #if defined(BCM_88680_A0)
   2165     { /* SOC_REG_INT_GE1_GBODE_CELL_CNT_BCM88680_A0r */
   2166         soc_block_list[2],
   2167         soc_genreg,
   2168         1,
   2169         0,
   2170         0x2021200,
   2171         SOC_REG_FLAG_RO,
   2172         0,
   2173         1,
   2174         soc_GE1_GBODE_CELL_CNT_BCM88680_A0r_fields,
   2175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2176         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2177         -1,
   2178         -1,
   2179     },
   2180 #endif /* chips */
   2181 
   2182 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   2183     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   2184     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNTr */
   2185         soc_block_list[2],
   2186         soc_genreg,
   2187         1,
   2188         0,
   2189         0x8001d,
   2190         SOC_REG_FLAG_RO,
   2191         0,
   2192         1,
   2193         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   2194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2195         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2196         -1,
   2197         -1,
   2198     },
   2199 #endif /* chips */
   2200 
   2201 #if defined(BCM_53400_A0)
   2202     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM53400_A0r */
   2203         soc_block_list[9],
   2204         soc_genreg,
   2205         1,
   2206         0,
   2207         0x2021a00,
   2208         SOC_REG_FLAG_RO,
   2209         0,
   2210         1,
   2211         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   2212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2213         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2214         -1,
   2215         -1,
   2216     },
   2217 #endif /* chips */
   2218 
   2219 #if defined(BCM_53540_A0)
   2220     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM53540_A0r */
   2221         soc_block_list[2],
   2222         soc_genreg,
   2223         1,
   2224         0,
   2225         0x2021a00,
   2226         SOC_REG_FLAG_RO,
   2227         0,
   2228         1,
   2229         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   2230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2232         -1,
   2233         -1,
   2234     },
   2235 #endif /* chips */
   2236 
   2237 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   2238     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM53570_A0r */
   2239         soc_block_list[2],
   2240         soc_genreg,
   2241         1,
   2242         0,
   2243         0x2022200,
   2244         SOC_REG_FLAG_RO,
   2245         0,
   2246         1,
   2247         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   2248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2250         -1,
   2251         -1,
   2252     },
   2253 #endif /* chips */
   2254 
   2255 #if defined(BCM_56150_A0)
   2256     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM56150_A0r */
   2257         soc_block_list[2],
   2258         soc_genreg,
   2259         1,
   2260         0,
   2261         0x2021a00,
   2262         SOC_REG_FLAG_RO,
   2263         0,
   2264         1,
   2265         soc_GE0_GBODE_CELL_REQ_CNT_BCM56150_A0r_fields,
   2266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2267         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2268         -1,
   2269         -1,
   2270     },
   2271 #endif /* chips */
   2272 
   2273 #if defined(BCM_56160_A0)
   2274     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM56160_A0r */
   2275         soc_block_list[2],
   2276         soc_genreg,
   2277         1,
   2278         0,
   2279         0x2021a00,
   2280         SOC_REG_FLAG_RO,
   2281         0,
   2282         1,
   2283         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   2284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2285         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2286         -1,
   2287         -1,
   2288     },
   2289 #endif /* chips */
   2290 
   2291 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   2292     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   2293     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   2294     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   2295     defined(BCM_56440_B0)
   2296     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   2297         soc_block_list[2],
   2298         soc_genreg,
   2299         1,
   2300         0,
   2301         0x8001d,
   2302         SOC_REG_FLAG_RO,
   2303         0,
   2304         1,
   2305         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   2306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2308         -1,
   2309         -1,
   2310     },
   2311 #endif /* chips */
   2312 
   2313 #if defined(BCM_56370_A0)
   2314     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM56370_A0r */
   2315         soc_block_list[9],
   2316         soc_genreg,
   2317         1,
   2318         0,
   2319         0x2021a00,
   2320         SOC_REG_FLAG_RO,
   2321         0,
   2322         1,
   2323         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   2324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2326         -1,
   2327         -1,
   2328         3,
   2329     },
   2330 #endif /* chips */
   2331 
   2332 #if defined(BCM_88375_A0)
   2333     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM88375_A0r */
   2334         soc_block_list[2],
   2335         soc_genreg,
   2336         1,
   2337         0,
   2338         0x2021a00,
   2339         SOC_REG_FLAG_RO,
   2340         0,
   2341         1,
   2342         soc_GE1_GBODE_CELL_REQ_CNT_BCM88375_A0r_fields,
   2343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2344         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2345         -1,
   2346         -1,
   2347     },
   2348 #endif /* chips */
   2349 
   2350 #if defined(BCM_88375_B0)
   2351     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM88375_B0r */
   2352         soc_block_list[2],
   2353         soc_genreg,
   2354         1,
   2355         0,
   2356         0x2021a00,
   2357         SOC_REG_FLAG_RO,
   2358         0,
   2359         1,
   2360         soc_GE1_GBODE_CELL_REQ_CNT_BCM88375_B0r_fields,
   2361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2362         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2363         -1,
   2364         -1,
   2365     },
   2366 #endif /* chips */
   2367 
   2368 #if defined(BCM_88470_A0)
   2369     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM88470_A0r */
   2370         soc_block_list[2],
   2371         soc_genreg,
   2372         1,
   2373         0,
   2374         0x2021a00,
   2375         SOC_REG_FLAG_RO,
   2376         0,
   2377         1,
   2378         soc_GE1_GBODE_CELL_REQ_CNT_BCM88470_A0r_fields,
   2379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2380         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2381         -1,
   2382         -1,
   2383     },
   2384 #endif /* chips */
   2385 
   2386 #if defined(BCM_88470_B0)
   2387     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM88470_B0r */
   2388         soc_block_list[2],
   2389         soc_genreg,
   2390         1,
   2391         0,
   2392         0x2021a00,
   2393         SOC_REG_FLAG_RO,
   2394         0,
   2395         1,
   2396         soc_GE1_GBODE_CELL_REQ_CNT_BCM88470_B0r_fields,
   2397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2398         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2399         -1,
   2400         -1,
   2401     },
   2402 #endif /* chips */
   2403 
   2404 #if defined(BCM_88675_A0)
   2405     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM88675_A0r */
   2406         soc_block_list[2],
   2407         soc_genreg,
   2408         1,
   2409         0,
   2410         0x2021a00,
   2411         SOC_REG_FLAG_RO,
   2412         0,
   2413         1,
   2414         soc_GE1_GBODE_CELL_REQ_CNTr_fields,
   2415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2416         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2417         -1,
   2418         -1,
   2419     },
   2420 #endif /* chips */
   2421 
   2422 #if defined(BCM_88675_B0)
   2423     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM88675_B0r */
   2424         soc_block_list[2],
   2425         soc_genreg,
   2426         1,
   2427         0,
   2428         0x2021a00,
   2429         SOC_REG_FLAG_RO,
   2430         0,
   2431         1,
   2432         soc_GE1_GBODE_CELL_REQ_CNT_BCM88675_B0r_fields,
   2433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2434         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2435         -1,
   2436         -1,
   2437     },
   2438 #endif /* chips */
   2439 
   2440 #if defined(BCM_88680_A0)
   2441     { /* SOC_REG_INT_GE1_GBODE_CELL_REQ_CNT_BCM88680_A0r */
   2442         soc_block_list[2],
   2443         soc_genreg,
   2444         1,
   2445         0,
   2446         0x2021a00,
   2447         SOC_REG_FLAG_RO,
   2448         0,
   2449         1,
   2450         soc_GE1_GBODE_CELL_REQ_CNT_BCM88680_A0r_fields,
   2451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2452         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2453         -1,
   2454         -1,
   2455     },
   2456 #endif /* chips */
   2457 
   2458 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   2459     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   2460     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   2461     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   2462     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   2463     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
   2464     defined(BCM_56514_A0)
   2465     { /* SOC_REG_INT_GE1_GBOD_OVRFLWr */
   2466         soc_block_list[2],
   2467         soc_genreg,
   2468         1,
   2469         0,
   2470         0x80005,
   2471         SOC_REG_FLAG_RO,
   2472         0,
   2473         1,
   2474         soc_GE0_GBOD_OVRFLWr_fields,
   2475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2476         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2477         -1,
   2478         -1,
   2479     },
   2480 #endif /* chips */
   2481 
   2482 #if defined(BCM_53400_A0)
   2483     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM53400_A0r */
   2484         soc_block_list[9],
   2485         soc_genreg,
   2486         1,
   2487         0,
   2488         0x2020a00,
   2489         SOC_REG_FLAG_RO,
   2490         0,
   2491         1,
   2492         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   2493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2494         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2495         -1,
   2496         -1,
   2497     },
   2498 #endif /* chips */
   2499 
   2500 #if defined(BCM_53540_A0)
   2501     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM53540_A0r */
   2502         soc_block_list[2],
   2503         soc_genreg,
   2504         1,
   2505         0,
   2506         0x2020a00,
   2507         SOC_REG_FLAG_RO,
   2508         0,
   2509         1,
   2510         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   2511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2512         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2513         -1,
   2514         -1,
   2515     },
   2516 #endif /* chips */
   2517 
   2518 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   2519     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM53570_A0r */
   2520         soc_block_list[2],
   2521         soc_genreg,
   2522         1,
   2523         0,
   2524         0x2021200,
   2525         SOC_REG_FLAG_RO,
   2526         0,
   2527         1,
   2528         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   2529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2530         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2531         -1,
   2532         -1,
   2533     },
   2534 #endif /* chips */
   2535 
   2536 #if defined(BCM_56150_A0)
   2537     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM56150_A0r */
   2538         soc_block_list[2],
   2539         soc_genreg,
   2540         1,
   2541         0,
   2542         0x2020a00,
   2543         SOC_REG_FLAG_RO,
   2544         0,
   2545         1,
   2546         soc_PORT_CDC_RXFIFO_OVRFLW_BCM56640_A0r_fields,
   2547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2548         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2549         -1,
   2550         -1,
   2551     },
   2552 #endif /* chips */
   2553 
   2554 #if defined(BCM_56160_A0)
   2555     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM56160_A0r */
   2556         soc_block_list[2],
   2557         soc_genreg,
   2558         1,
   2559         0,
   2560         0x2020a00,
   2561         SOC_REG_FLAG_RO,
   2562         0,
   2563         1,
   2564         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   2565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2566         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2567         -1,
   2568         -1,
   2569     },
   2570 #endif /* chips */
   2571 
   2572 #if defined(BCM_56370_A0)
   2573     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM56370_A0r */
   2574         soc_block_list[9],
   2575         soc_genreg,
   2576         1,
   2577         0,
   2578         0x2020a00,
   2579         SOC_REG_FLAG_RO,
   2580         0,
   2581         1,
   2582         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   2583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2584         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2585         -1,
   2586         -1,
   2587         3,
   2588     },
   2589 #endif /* chips */
   2590 
   2591 #if defined(BCM_88375_A0)
   2592     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM88375_A0r */
   2593         soc_block_list[2],
   2594         soc_genreg,
   2595         1,
   2596         0,
   2597         0x2020a00,
   2598         SOC_REG_FLAG_RO,
   2599         0,
   2600         1,
   2601         soc_GE1_GBOD_OVRFLW_BCM88375_A0r_fields,
   2602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2603         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2604         -1,
   2605         -1,
   2606     },
   2607 #endif /* chips */
   2608 
   2609 #if defined(BCM_88375_B0)
   2610     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM88375_B0r */
   2611         soc_block_list[2],
   2612         soc_genreg,
   2613         1,
   2614         0,
   2615         0x2020a00,
   2616         SOC_REG_FLAG_RO,
   2617         0,
   2618         1,
   2619         soc_GE1_GBOD_OVRFLW_BCM88375_B0r_fields,
   2620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2621         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2622         -1,
   2623         -1,
   2624     },
   2625 #endif /* chips */
   2626 
   2627 #if defined(BCM_88470_A0)
   2628     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM88470_A0r */
   2629         soc_block_list[2],
   2630         soc_genreg,
   2631         1,
   2632         0,
   2633         0x2020a00,
   2634         SOC_REG_FLAG_RO,
   2635         0,
   2636         1,
   2637         soc_GE1_GBOD_OVRFLW_BCM88470_A0r_fields,
   2638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2639         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2640         -1,
   2641         -1,
   2642     },
   2643 #endif /* chips */
   2644 
   2645 #if defined(BCM_88470_B0)
   2646     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM88470_B0r */
   2647         soc_block_list[2],
   2648         soc_genreg,
   2649         1,
   2650         0,
   2651         0x2020a00,
   2652         SOC_REG_FLAG_RO,
   2653         0,
   2654         1,
   2655         soc_GE1_GBOD_OVRFLW_BCM88470_B0r_fields,
   2656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2657         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2658         -1,
   2659         -1,
   2660     },
   2661 #endif /* chips */
   2662 
   2663 #if defined(BCM_88675_A0)
   2664     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM88675_A0r */
   2665         soc_block_list[2],
   2666         soc_genreg,
   2667         1,
   2668         0,
   2669         0x2020a00,
   2670         SOC_REG_FLAG_RO,
   2671         0,
   2672         1,
   2673         soc_GE1_GBOD_OVRFLWr_fields,
   2674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2675         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2676         -1,
   2677         -1,
   2678     },
   2679 #endif /* chips */
   2680 
   2681 #if defined(BCM_88675_B0)
   2682     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM88675_B0r */
   2683         soc_block_list[2],
   2684         soc_genreg,
   2685         1,
   2686         0,
   2687         0x2020a00,
   2688         SOC_REG_FLAG_RO,
   2689         0,
   2690         1,
   2691         soc_GE1_GBOD_OVRFLW_BCM88675_B0r_fields,
   2692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2693         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2694         -1,
   2695         -1,
   2696     },
   2697 #endif /* chips */
   2698 
   2699 #if defined(BCM_88680_A0)
   2700     { /* SOC_REG_INT_GE1_GBOD_OVRFLW_BCM88680_A0r */
   2701         soc_block_list[2],
   2702         soc_genreg,
   2703         1,
   2704         0,
   2705         0x2020a00,
   2706         SOC_REG_FLAG_RO,
   2707         0,
   2708         1,
   2709         soc_GE1_GBOD_OVRFLW_BCM88680_A0r_fields,
   2710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2711         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2712         -1,
   2713         -1,
   2714     },
   2715 #endif /* chips */
   2716 
   2717 #if defined(BCM_53570_A0)
   2718     { /* SOC_REG_INT_GE1_MIN_FRAG_SIZEr */
   2719         soc_block_list[2],
   2720         soc_genreg,
   2721         1,
   2722         0,
   2723         0x2020a00,
   2724         0,
   2725         0,
   2726         2,
   2727         soc_GE0_MIN_FRAG_SIZEr_fields,
   2728         SOC_RESET_VAL_DEC(0x00000387, 0x00000000)
   2729         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   2730         -1,
   2731         -1,
   2732     },
   2733 #endif /* chips */
   2734 
   2735 #if defined(BCM_53570_B0)
   2736     { /* SOC_REG_INT_GE1_MIN_FRAG_SIZE_BCM53570_B0r */
   2737         soc_block_list[2],
   2738         soc_genreg,
   2739         1,
   2740         0,
   2741         0x2020a00,
   2742         0,
   2743         0,
   2744         2,
   2745         soc_GE0_MIN_FRAG_SIZE_BCM53570_B0r_fields,
   2746         SOC_RESET_VAL_DEC(0x00000408, 0x00000000)
   2747         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   2748         -1,
   2749         -1,
   2750     },
   2751 #endif /* chips */
   2752 
   2753 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2754     { /* SOC_REG_INT_GE1_S3MII_SPEED_DEBUGr */
   2755         soc_block_list[2],
   2756         soc_genreg,
   2757         1,
   2758         0,
   2759         0x8003c,
   2760         SOC_REG_FLAG_RO,
   2761         0,
   2762         4,
   2763         soc_GE0_S3MII_SPEED_DEBUGr_fields,
   2764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2765         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2766         -1,
   2767         -1,
   2768     },
   2769 #endif /* chips */
   2770 
   2771 #if defined(BCM_53324_A0)
   2772     { /* SOC_REG_INT_GE2_EEE_CONFIGr */
   2773         soc_block_list[2],
   2774         soc_genreg,
   2775         1,
   2776         0,
   2777         0x80038,
   2778         0,
   2779         0,
   2780         4,
   2781         soc_GE0_EEE_CONFIGr_fields,
   2782         SOC_RESET_VAL_DEC(0x000014e1, 0x00000000)
   2783         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2784         -1,
   2785         -1,
   2786     },
   2787 #endif /* chips */
   2788 
   2789 #if defined(BCM_53400_A0)
   2790     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM53400_A0r */
   2791         soc_block_list[9],
   2792         soc_genreg,
   2793         1,
   2794         0,
   2795         0x2022600,
   2796         0,
   2797         0,
   2798         3,
   2799         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   2800         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2801         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2802         -1,
   2803         -1,
   2804     },
   2805 #endif /* chips */
   2806 
   2807 #if defined(BCM_53540_A0)
   2808     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM53540_A0r */
   2809         soc_block_list[2],
   2810         soc_genreg,
   2811         1,
   2812         0,
   2813         0x2022600,
   2814         0,
   2815         0,
   2816         3,
   2817         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   2818         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2819         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2820         -1,
   2821         -1,
   2822     },
   2823 #endif /* chips */
   2824 
   2825 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   2826     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM53570_A0r */
   2827         soc_block_list[2],
   2828         soc_genreg,
   2829         1,
   2830         0,
   2831         0x2023100,
   2832         0,
   2833         0,
   2834         3,
   2835         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   2836         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2837         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2838         -1,
   2839         -1,
   2840     },
   2841 #endif /* chips */
   2842 
   2843 #if defined(BCM_56150_A0)
   2844     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM56150_A0r */
   2845         soc_block_list[2],
   2846         soc_genreg,
   2847         1,
   2848         0,
   2849         0x2022600,
   2850         0,
   2851         0,
   2852         3,
   2853         soc_GE0_EEE_CONFIG_BCM56150_A0r_fields,
   2854         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2855         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2856         -1,
   2857         -1,
   2858     },
   2859 #endif /* chips */
   2860 
   2861 #if defined(BCM_56160_A0)
   2862     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM56160_A0r */
   2863         soc_block_list[2],
   2864         soc_genreg,
   2865         1,
   2866         0,
   2867         0x2022600,
   2868         0,
   2869         0,
   2870         3,
   2871         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   2872         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2873         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2874         -1,
   2875         -1,
   2876     },
   2877 #endif /* chips */
   2878 
   2879 #if defined(BCM_56370_A0)
   2880     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM56370_A0r */
   2881         soc_block_list[9],
   2882         soc_genreg,
   2883         1,
   2884         0,
   2885         0x2022600,
   2886         0,
   2887         0,
   2888         3,
   2889         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   2890         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2891         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2892         -1,
   2893         -1,
   2894         3,
   2895     },
   2896 #endif /* chips */
   2897 
   2898 #if defined(BCM_56142_A0) || defined(BCM_56440_A0) || \
   2899     defined(BCM_56440_B0)
   2900     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM56440_A0r */
   2901         soc_block_list[2],
   2902         soc_genreg,
   2903         1,
   2904         0,
   2905         0x80035,
   2906         0,
   2907         0,
   2908         4,
   2909         soc_GE0_EEE_CONFIG_BCM56440_A0r_fields,
   2910         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2912         -1,
   2913         -1,
   2914     },
   2915 #endif /* chips */
   2916 
   2917 #if defined(BCM_88375_A0)
   2918     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM88375_A0r */
   2919         soc_block_list[2],
   2920         soc_genreg,
   2921         1,
   2922         0,
   2923         0x2022600,
   2924         0,
   2925         0,
   2926         3,
   2927         soc_GE2_EEE_CONFIG_BCM88375_A0r_fields,
   2928         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2929         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2930         -1,
   2931         -1,
   2932     },
   2933 #endif /* chips */
   2934 
   2935 #if defined(BCM_88375_B0)
   2936     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM88375_B0r */
   2937         soc_block_list[2],
   2938         soc_genreg,
   2939         1,
   2940         0,
   2941         0x2022600,
   2942         0,
   2943         0,
   2944         3,
   2945         soc_GE2_EEE_CONFIG_BCM88375_B0r_fields,
   2946         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2947         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2948         -1,
   2949         -1,
   2950     },
   2951 #endif /* chips */
   2952 
   2953 #if defined(BCM_88470_A0)
   2954     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM88470_A0r */
   2955         soc_block_list[2],
   2956         soc_genreg,
   2957         1,
   2958         0,
   2959         0x2022600,
   2960         0,
   2961         0,
   2962         3,
   2963         soc_GE2_EEE_CONFIG_BCM88470_A0r_fields,
   2964         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2965         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2966         -1,
   2967         -1,
   2968     },
   2969 #endif /* chips */
   2970 
   2971 #if defined(BCM_88470_B0)
   2972     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM88470_B0r */
   2973         soc_block_list[2],
   2974         soc_genreg,
   2975         1,
   2976         0,
   2977         0x2022600,
   2978         0,
   2979         0,
   2980         3,
   2981         soc_GE2_EEE_CONFIG_BCM88470_B0r_fields,
   2982         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   2983         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   2984         -1,
   2985         -1,
   2986     },
   2987 #endif /* chips */
   2988 
   2989 #if defined(BCM_88675_A0)
   2990     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM88675_A0r */
   2991         soc_block_list[2],
   2992         soc_genreg,
   2993         1,
   2994         0,
   2995         0x2022600,
   2996         0,
   2997         0,
   2998         3,
   2999         soc_GE2_EEE_CONFIGr_fields,
   3000         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   3001         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   3002         -1,
   3003         -1,
   3004     },
   3005 #endif /* chips */
   3006 
   3007 #if defined(BCM_88675_B0)
   3008     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM88675_B0r */
   3009         soc_block_list[2],
   3010         soc_genreg,
   3011         1,
   3012         0,
   3013         0x2022600,
   3014         0,
   3015         0,
   3016         3,
   3017         soc_GE2_EEE_CONFIG_BCM88675_B0r_fields,
   3018         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   3019         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   3020         -1,
   3021         -1,
   3022     },
   3023 #endif /* chips */
   3024 
   3025 #if defined(BCM_88680_A0)
   3026     { /* SOC_REG_INT_GE2_EEE_CONFIG_BCM88680_A0r */
   3027         soc_block_list[2],
   3028         soc_genreg,
   3029         1,
   3030         0,
   3031         0x2022600,
   3032         0,
   3033         0,
   3034         3,
   3035         soc_GE2_EEE_CONFIG_BCM88680_A0r_fields,
   3036         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   3037         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   3038         -1,
   3039         -1,
   3040     },
   3041 #endif /* chips */
   3042 
   3043 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   3044     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   3045     { /* SOC_REG_INT_GE2_GBODE_CELL_CNTr */
   3046         soc_block_list[2],
   3047         soc_genreg,
   3048         1,
   3049         0,
   3050         0x80012,
   3051         SOC_REG_FLAG_RO,
   3052         0,
   3053         1,
   3054         soc_GE0_GBODE_CELL_CNTr_fields,
   3055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3056         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3057         -1,
   3058         -1,
   3059     },
   3060 #endif /* chips */
   3061 
   3062 #if defined(BCM_53400_A0)
   3063     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM53400_A0r */
   3064         soc_block_list[9],
   3065         soc_genreg,
   3066         1,
   3067         0,
   3068         0x2021300,
   3069         SOC_REG_FLAG_RO,
   3070         0,
   3071         1,
   3072         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   3073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3074         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3075         -1,
   3076         -1,
   3077     },
   3078 #endif /* chips */
   3079 
   3080 #if defined(BCM_53540_A0)
   3081     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM53540_A0r */
   3082         soc_block_list[2],
   3083         soc_genreg,
   3084         1,
   3085         0,
   3086         0x2021300,
   3087         SOC_REG_FLAG_RO,
   3088         0,
   3089         1,
   3090         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   3091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3092         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3093         -1,
   3094         -1,
   3095     },
   3096 #endif /* chips */
   3097 
   3098 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   3099     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM53570_A0r */
   3100         soc_block_list[2],
   3101         soc_genreg,
   3102         1,
   3103         0,
   3104         0x2021b00,
   3105         SOC_REG_FLAG_RO,
   3106         0,
   3107         1,
   3108         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   3109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3110         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3111         -1,
   3112         -1,
   3113     },
   3114 #endif /* chips */
   3115 
   3116 #if defined(BCM_56150_A0)
   3117     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM56150_A0r */
   3118         soc_block_list[2],
   3119         soc_genreg,
   3120         1,
   3121         0,
   3122         0x2021300,
   3123         SOC_REG_FLAG_RO,
   3124         0,
   3125         1,
   3126         soc_GE0_GBODE_CELL_CNT_BCM56150_A0r_fields,
   3127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3128         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3129         -1,
   3130         -1,
   3131     },
   3132 #endif /* chips */
   3133 
   3134 #if defined(BCM_56160_A0)
   3135     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM56160_A0r */
   3136         soc_block_list[2],
   3137         soc_genreg,
   3138         1,
   3139         0,
   3140         0x2021300,
   3141         SOC_REG_FLAG_RO,
   3142         0,
   3143         1,
   3144         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   3145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3146         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3147         -1,
   3148         -1,
   3149     },
   3150 #endif /* chips */
   3151 
   3152 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   3153     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   3154     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   3155     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   3156     defined(BCM_56440_B0)
   3157     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM56224_A0r */
   3158         soc_block_list[2],
   3159         soc_genreg,
   3160         1,
   3161         0,
   3162         0x80012,
   3163         SOC_REG_FLAG_RO,
   3164         0,
   3165         1,
   3166         soc_GE_GBODE_CELL_CNTr_fields,
   3167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3169         -1,
   3170         -1,
   3171     },
   3172 #endif /* chips */
   3173 
   3174 #if defined(BCM_56370_A0)
   3175     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM56370_A0r */
   3176         soc_block_list[9],
   3177         soc_genreg,
   3178         1,
   3179         0,
   3180         0x2021300,
   3181         SOC_REG_FLAG_RO,
   3182         0,
   3183         1,
   3184         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   3185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3187         -1,
   3188         -1,
   3189         3,
   3190     },
   3191 #endif /* chips */
   3192 
   3193 #if defined(BCM_88375_A0)
   3194     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM88375_A0r */
   3195         soc_block_list[2],
   3196         soc_genreg,
   3197         1,
   3198         0,
   3199         0x2021300,
   3200         SOC_REG_FLAG_RO,
   3201         0,
   3202         1,
   3203         soc_GE2_GBODE_CELL_CNT_BCM88375_A0r_fields,
   3204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3205         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3206         -1,
   3207         -1,
   3208     },
   3209 #endif /* chips */
   3210 
   3211 #if defined(BCM_88375_B0)
   3212     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM88375_B0r */
   3213         soc_block_list[2],
   3214         soc_genreg,
   3215         1,
   3216         0,
   3217         0x2021300,
   3218         SOC_REG_FLAG_RO,
   3219         0,
   3220         1,
   3221         soc_GE2_GBODE_CELL_CNT_BCM88375_B0r_fields,
   3222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3223         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3224         -1,
   3225         -1,
   3226     },
   3227 #endif /* chips */
   3228 
   3229 #if defined(BCM_88470_A0)
   3230     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM88470_A0r */
   3231         soc_block_list[2],
   3232         soc_genreg,
   3233         1,
   3234         0,
   3235         0x2021300,
   3236         SOC_REG_FLAG_RO,
   3237         0,
   3238         1,
   3239         soc_GE2_GBODE_CELL_CNT_BCM88470_A0r_fields,
   3240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3241         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3242         -1,
   3243         -1,
   3244     },
   3245 #endif /* chips */
   3246 
   3247 #if defined(BCM_88470_B0)
   3248     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM88470_B0r */
   3249         soc_block_list[2],
   3250         soc_genreg,
   3251         1,
   3252         0,
   3253         0x2021300,
   3254         SOC_REG_FLAG_RO,
   3255         0,
   3256         1,
   3257         soc_GE2_GBODE_CELL_CNT_BCM88470_B0r_fields,
   3258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3259         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3260         -1,
   3261         -1,
   3262     },
   3263 #endif /* chips */
   3264 
   3265 #if defined(BCM_88675_A0)
   3266     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM88675_A0r */
   3267         soc_block_list[2],
   3268         soc_genreg,
   3269         1,
   3270         0,
   3271         0x2021300,
   3272         SOC_REG_FLAG_RO,
   3273         0,
   3274         1,
   3275         soc_GE2_GBODE_CELL_CNTr_fields,
   3276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3277         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3278         -1,
   3279         -1,
   3280     },
   3281 #endif /* chips */
   3282 
   3283 #if defined(BCM_88675_B0)
   3284     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM88675_B0r */
   3285         soc_block_list[2],
   3286         soc_genreg,
   3287         1,
   3288         0,
   3289         0x2021300,
   3290         SOC_REG_FLAG_RO,
   3291         0,
   3292         1,
   3293         soc_GE2_GBODE_CELL_CNT_BCM88675_B0r_fields,
   3294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3295         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3296         -1,
   3297         -1,
   3298     },
   3299 #endif /* chips */
   3300 
   3301 #if defined(BCM_88680_A0)
   3302     { /* SOC_REG_INT_GE2_GBODE_CELL_CNT_BCM88680_A0r */
   3303         soc_block_list[2],
   3304         soc_genreg,
   3305         1,
   3306         0,
   3307         0x2021300,
   3308         SOC_REG_FLAG_RO,
   3309         0,
   3310         1,
   3311         soc_GE2_GBODE_CELL_CNT_BCM88680_A0r_fields,
   3312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3313         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3314         -1,
   3315         -1,
   3316     },
   3317 #endif /* chips */
   3318 
   3319 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   3320     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   3321     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNTr */
   3322         soc_block_list[2],
   3323         soc_genreg,
   3324         1,
   3325         0,
   3326         0x8001e,
   3327         SOC_REG_FLAG_RO,
   3328         0,
   3329         1,
   3330         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   3331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3332         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3333         -1,
   3334         -1,
   3335     },
   3336 #endif /* chips */
   3337 
   3338 #if defined(BCM_53400_A0)
   3339     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM53400_A0r */
   3340         soc_block_list[9],
   3341         soc_genreg,
   3342         1,
   3343         0,
   3344         0x2021b00,
   3345         SOC_REG_FLAG_RO,
   3346         0,
   3347         1,
   3348         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   3349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3351         -1,
   3352         -1,
   3353     },
   3354 #endif /* chips */
   3355 
   3356 #if defined(BCM_53540_A0)
   3357     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM53540_A0r */
   3358         soc_block_list[2],
   3359         soc_genreg,
   3360         1,
   3361         0,
   3362         0x2021b00,
   3363         SOC_REG_FLAG_RO,
   3364         0,
   3365         1,
   3366         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   3367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3369         -1,
   3370         -1,
   3371     },
   3372 #endif /* chips */
   3373 
   3374 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   3375     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM53570_A0r */
   3376         soc_block_list[2],
   3377         soc_genreg,
   3378         1,
   3379         0,
   3380         0x2022300,
   3381         SOC_REG_FLAG_RO,
   3382         0,
   3383         1,
   3384         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   3385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3386         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3387         -1,
   3388         -1,
   3389     },
   3390 #endif /* chips */
   3391 
   3392 #if defined(BCM_56150_A0)
   3393     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM56150_A0r */
   3394         soc_block_list[2],
   3395         soc_genreg,
   3396         1,
   3397         0,
   3398         0x2021b00,
   3399         SOC_REG_FLAG_RO,
   3400         0,
   3401         1,
   3402         soc_GE0_GBODE_CELL_REQ_CNT_BCM56150_A0r_fields,
   3403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3404         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3405         -1,
   3406         -1,
   3407     },
   3408 #endif /* chips */
   3409 
   3410 #if defined(BCM_56160_A0)
   3411     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM56160_A0r */
   3412         soc_block_list[2],
   3413         soc_genreg,
   3414         1,
   3415         0,
   3416         0x2021b00,
   3417         SOC_REG_FLAG_RO,
   3418         0,
   3419         1,
   3420         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   3421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3422         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3423         -1,
   3424         -1,
   3425     },
   3426 #endif /* chips */
   3427 
   3428 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   3429     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   3430     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   3431     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   3432     defined(BCM_56440_B0)
   3433     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   3434         soc_block_list[2],
   3435         soc_genreg,
   3436         1,
   3437         0,
   3438         0x8001e,
   3439         SOC_REG_FLAG_RO,
   3440         0,
   3441         1,
   3442         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   3443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3444         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3445         -1,
   3446         -1,
   3447     },
   3448 #endif /* chips */
   3449 
   3450 #if defined(BCM_56370_A0)
   3451     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM56370_A0r */
   3452         soc_block_list[9],
   3453         soc_genreg,
   3454         1,
   3455         0,
   3456         0x2021b00,
   3457         SOC_REG_FLAG_RO,
   3458         0,
   3459         1,
   3460         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   3461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3462         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3463         -1,
   3464         -1,
   3465         3,
   3466     },
   3467 #endif /* chips */
   3468 
   3469 #if defined(BCM_88375_A0)
   3470     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM88375_A0r */
   3471         soc_block_list[2],
   3472         soc_genreg,
   3473         1,
   3474         0,
   3475         0x2021b00,
   3476         SOC_REG_FLAG_RO,
   3477         0,
   3478         1,
   3479         soc_GE2_GBODE_CELL_REQ_CNT_BCM88375_A0r_fields,
   3480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3481         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3482         -1,
   3483         -1,
   3484     },
   3485 #endif /* chips */
   3486 
   3487 #if defined(BCM_88375_B0)
   3488     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM88375_B0r */
   3489         soc_block_list[2],
   3490         soc_genreg,
   3491         1,
   3492         0,
   3493         0x2021b00,
   3494         SOC_REG_FLAG_RO,
   3495         0,
   3496         1,
   3497         soc_GE2_GBODE_CELL_REQ_CNT_BCM88375_B0r_fields,
   3498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3499         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3500         -1,
   3501         -1,
   3502     },
   3503 #endif /* chips */
   3504 
   3505 #if defined(BCM_88470_A0)
   3506     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM88470_A0r */
   3507         soc_block_list[2],
   3508         soc_genreg,
   3509         1,
   3510         0,
   3511         0x2021b00,
   3512         SOC_REG_FLAG_RO,
   3513         0,
   3514         1,
   3515         soc_GE2_GBODE_CELL_REQ_CNT_BCM88470_A0r_fields,
   3516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3517         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3518         -1,
   3519         -1,
   3520     },
   3521 #endif /* chips */
   3522 
   3523 #if defined(BCM_88470_B0)
   3524     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM88470_B0r */
   3525         soc_block_list[2],
   3526         soc_genreg,
   3527         1,
   3528         0,
   3529         0x2021b00,
   3530         SOC_REG_FLAG_RO,
   3531         0,
   3532         1,
   3533         soc_GE2_GBODE_CELL_REQ_CNT_BCM88470_B0r_fields,
   3534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3535         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3536         -1,
   3537         -1,
   3538     },
   3539 #endif /* chips */
   3540 
   3541 #if defined(BCM_88675_A0)
   3542     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM88675_A0r */
   3543         soc_block_list[2],
   3544         soc_genreg,
   3545         1,
   3546         0,
   3547         0x2021b00,
   3548         SOC_REG_FLAG_RO,
   3549         0,
   3550         1,
   3551         soc_GE2_GBODE_CELL_REQ_CNTr_fields,
   3552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3553         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3554         -1,
   3555         -1,
   3556     },
   3557 #endif /* chips */
   3558 
   3559 #if defined(BCM_88675_B0)
   3560     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM88675_B0r */
   3561         soc_block_list[2],
   3562         soc_genreg,
   3563         1,
   3564         0,
   3565         0x2021b00,
   3566         SOC_REG_FLAG_RO,
   3567         0,
   3568         1,
   3569         soc_GE2_GBODE_CELL_REQ_CNT_BCM88675_B0r_fields,
   3570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3571         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3572         -1,
   3573         -1,
   3574     },
   3575 #endif /* chips */
   3576 
   3577 #if defined(BCM_88680_A0)
   3578     { /* SOC_REG_INT_GE2_GBODE_CELL_REQ_CNT_BCM88680_A0r */
   3579         soc_block_list[2],
   3580         soc_genreg,
   3581         1,
   3582         0,
   3583         0x2021b00,
   3584         SOC_REG_FLAG_RO,
   3585         0,
   3586         1,
   3587         soc_GE2_GBODE_CELL_REQ_CNT_BCM88680_A0r_fields,
   3588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3589         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   3590         -1,
   3591         -1,
   3592     },
   3593 #endif /* chips */
   3594 
   3595 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   3596     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   3597     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   3598     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   3599     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   3600     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
   3601     defined(BCM_56514_A0)
   3602     { /* SOC_REG_INT_GE2_GBOD_OVRFLWr */
   3603         soc_block_list[2],
   3604         soc_genreg,
   3605         1,
   3606         0,
   3607         0x80006,
   3608         SOC_REG_FLAG_RO,
   3609         0,
   3610         1,
   3611         soc_GE0_GBOD_OVRFLWr_fields,
   3612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3613         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3614         -1,
   3615         -1,
   3616     },
   3617 #endif /* chips */
   3618 
   3619 #if defined(BCM_53400_A0)
   3620     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM53400_A0r */
   3621         soc_block_list[9],
   3622         soc_genreg,
   3623         1,
   3624         0,
   3625         0x2020b00,
   3626         SOC_REG_FLAG_RO,
   3627         0,
   3628         1,
   3629         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   3630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3631         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3632         -1,
   3633         -1,
   3634     },
   3635 #endif /* chips */
   3636 
   3637 #if defined(BCM_53540_A0)
   3638     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM53540_A0r */
   3639         soc_block_list[2],
   3640         soc_genreg,
   3641         1,
   3642         0,
   3643         0x2020b00,
   3644         SOC_REG_FLAG_RO,
   3645         0,
   3646         1,
   3647         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   3648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3649         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3650         -1,
   3651         -1,
   3652     },
   3653 #endif /* chips */
   3654 
   3655 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   3656     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM53570_A0r */
   3657         soc_block_list[2],
   3658         soc_genreg,
   3659         1,
   3660         0,
   3661         0x2021300,
   3662         SOC_REG_FLAG_RO,
   3663         0,
   3664         1,
   3665         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   3666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3667         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3668         -1,
   3669         -1,
   3670     },
   3671 #endif /* chips */
   3672 
   3673 #if defined(BCM_56150_A0)
   3674     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM56150_A0r */
   3675         soc_block_list[2],
   3676         soc_genreg,
   3677         1,
   3678         0,
   3679         0x2020b00,
   3680         SOC_REG_FLAG_RO,
   3681         0,
   3682         1,
   3683         soc_PORT_CDC_RXFIFO_OVRFLW_BCM56640_A0r_fields,
   3684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3685         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3686         -1,
   3687         -1,
   3688     },
   3689 #endif /* chips */
   3690 
   3691 #if defined(BCM_56160_A0)
   3692     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM56160_A0r */
   3693         soc_block_list[2],
   3694         soc_genreg,
   3695         1,
   3696         0,
   3697         0x2020b00,
   3698         SOC_REG_FLAG_RO,
   3699         0,
   3700         1,
   3701         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   3702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3703         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3704         -1,
   3705         -1,
   3706     },
   3707 #endif /* chips */
   3708 
   3709 #if defined(BCM_56370_A0)
   3710     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM56370_A0r */
   3711         soc_block_list[9],
   3712         soc_genreg,
   3713         1,
   3714         0,
   3715         0x2020b00,
   3716         SOC_REG_FLAG_RO,
   3717         0,
   3718         1,
   3719         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   3720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3721         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3722         -1,
   3723         -1,
   3724         3,
   3725     },
   3726 #endif /* chips */
   3727 
   3728 #if defined(BCM_88375_A0)
   3729     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM88375_A0r */
   3730         soc_block_list[2],
   3731         soc_genreg,
   3732         1,
   3733         0,
   3734         0x2020b00,
   3735         SOC_REG_FLAG_RO,
   3736         0,
   3737         1,
   3738         soc_GE2_GBOD_OVRFLW_BCM88375_A0r_fields,
   3739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3740         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3741         -1,
   3742         -1,
   3743     },
   3744 #endif /* chips */
   3745 
   3746 #if defined(BCM_88375_B0)
   3747     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM88375_B0r */
   3748         soc_block_list[2],
   3749         soc_genreg,
   3750         1,
   3751         0,
   3752         0x2020b00,
   3753         SOC_REG_FLAG_RO,
   3754         0,
   3755         1,
   3756         soc_GE2_GBOD_OVRFLW_BCM88375_B0r_fields,
   3757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3758         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3759         -1,
   3760         -1,
   3761     },
   3762 #endif /* chips */
   3763 
   3764 #if defined(BCM_88470_A0)
   3765     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM88470_A0r */
   3766         soc_block_list[2],
   3767         soc_genreg,
   3768         1,
   3769         0,
   3770         0x2020b00,
   3771         SOC_REG_FLAG_RO,
   3772         0,
   3773         1,
   3774         soc_GE2_GBOD_OVRFLW_BCM88470_A0r_fields,
   3775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3776         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3777         -1,
   3778         -1,
   3779     },
   3780 #endif /* chips */
   3781 
   3782 #if defined(BCM_88470_B0)
   3783     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM88470_B0r */
   3784         soc_block_list[2],
   3785         soc_genreg,
   3786         1,
   3787         0,
   3788         0x2020b00,
   3789         SOC_REG_FLAG_RO,
   3790         0,
   3791         1,
   3792         soc_GE2_GBOD_OVRFLW_BCM88470_B0r_fields,
   3793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3794         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3795         -1,
   3796         -1,
   3797     },
   3798 #endif /* chips */
   3799 
   3800 #if defined(BCM_88675_A0)
   3801     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM88675_A0r */
   3802         soc_block_list[2],
   3803         soc_genreg,
   3804         1,
   3805         0,
   3806         0x2020b00,
   3807         SOC_REG_FLAG_RO,
   3808         0,
   3809         1,
   3810         soc_GE2_GBOD_OVRFLWr_fields,
   3811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3812         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3813         -1,
   3814         -1,
   3815     },
   3816 #endif /* chips */
   3817 
   3818 #if defined(BCM_88675_B0)
   3819     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM88675_B0r */
   3820         soc_block_list[2],
   3821         soc_genreg,
   3822         1,
   3823         0,
   3824         0x2020b00,
   3825         SOC_REG_FLAG_RO,
   3826         0,
   3827         1,
   3828         soc_GE2_GBOD_OVRFLW_BCM88675_B0r_fields,
   3829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3830         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3831         -1,
   3832         -1,
   3833     },
   3834 #endif /* chips */
   3835 
   3836 #if defined(BCM_88680_A0)
   3837     { /* SOC_REG_INT_GE2_GBOD_OVRFLW_BCM88680_A0r */
   3838         soc_block_list[2],
   3839         soc_genreg,
   3840         1,
   3841         0,
   3842         0x2020b00,
   3843         SOC_REG_FLAG_RO,
   3844         0,
   3845         1,
   3846         soc_GE2_GBOD_OVRFLW_BCM88680_A0r_fields,
   3847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3848         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3849         -1,
   3850         -1,
   3851     },
   3852 #endif /* chips */
   3853 
   3854 #if defined(BCM_53570_A0)
   3855     { /* SOC_REG_INT_GE2_MIN_FRAG_SIZEr */
   3856         soc_block_list[2],
   3857         soc_genreg,
   3858         1,
   3859         0,
   3860         0x2020b00,
   3861         0,
   3862         0,
   3863         2,
   3864         soc_GE0_MIN_FRAG_SIZEr_fields,
   3865         SOC_RESET_VAL_DEC(0x00000387, 0x00000000)
   3866         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   3867         -1,
   3868         -1,
   3869     },
   3870 #endif /* chips */
   3871 
   3872 #if defined(BCM_53570_B0)
   3873     { /* SOC_REG_INT_GE2_MIN_FRAG_SIZE_BCM53570_B0r */
   3874         soc_block_list[2],
   3875         soc_genreg,
   3876         1,
   3877         0,
   3878         0x2020b00,
   3879         0,
   3880         0,
   3881         2,
   3882         soc_GE0_MIN_FRAG_SIZE_BCM53570_B0r_fields,
   3883         SOC_RESET_VAL_DEC(0x00000408, 0x00000000)
   3884         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   3885         -1,
   3886         -1,
   3887     },
   3888 #endif /* chips */
   3889 
   3890 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3891     { /* SOC_REG_INT_GE2_S3MII_SPEED_DEBUGr */
   3892         soc_block_list[2],
   3893         soc_genreg,
   3894         1,
   3895         0,
   3896         0x8003d,
   3897         SOC_REG_FLAG_RO,
   3898         0,
   3899         4,
   3900         soc_GE0_S3MII_SPEED_DEBUGr_fields,
   3901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3902         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3903         -1,
   3904         -1,
   3905     },
   3906 #endif /* chips */
   3907 
   3908 #if defined(BCM_53324_A0)
   3909     { /* SOC_REG_INT_GE3_EEE_CONFIGr */
   3910         soc_block_list[2],
   3911         soc_genreg,
   3912         1,
   3913         0,
   3914         0x80039,
   3915         0,
   3916         0,
   3917         4,
   3918         soc_GE0_EEE_CONFIGr_fields,
   3919         SOC_RESET_VAL_DEC(0x000014e1, 0x00000000)
   3920         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3921         -1,
   3922         -1,
   3923     },
   3924 #endif /* chips */
   3925 
   3926 #if defined(BCM_53400_A0)
   3927     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM53400_A0r */
   3928         soc_block_list[9],
   3929         soc_genreg,
   3930         1,
   3931         0,
   3932         0x2022700,
   3933         0,
   3934         0,
   3935         3,
   3936         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   3937         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   3938         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   3939         -1,
   3940         -1,
   3941     },
   3942 #endif /* chips */
   3943 
   3944 #if defined(BCM_53540_A0)
   3945     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM53540_A0r */
   3946         soc_block_list[2],
   3947         soc_genreg,
   3948         1,
   3949         0,
   3950         0x2022700,
   3951         0,
   3952         0,
   3953         3,
   3954         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   3955         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   3956         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   3957         -1,
   3958         -1,
   3959     },
   3960 #endif /* chips */
   3961 
   3962 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   3963     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM53570_A0r */
   3964         soc_block_list[2],
   3965         soc_genreg,
   3966         1,
   3967         0,
   3968         0x2023200,
   3969         0,
   3970         0,
   3971         3,
   3972         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   3973         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   3974         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   3975         -1,
   3976         -1,
   3977     },
   3978 #endif /* chips */
   3979 
   3980 #if defined(BCM_56150_A0)
   3981     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM56150_A0r */
   3982         soc_block_list[2],
   3983         soc_genreg,
   3984         1,
   3985         0,
   3986         0x2022700,
   3987         0,
   3988         0,
   3989         3,
   3990         soc_GE0_EEE_CONFIG_BCM56150_A0r_fields,
   3991         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   3992         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   3993         -1,
   3994         -1,
   3995     },
   3996 #endif /* chips */
   3997 
   3998 #if defined(BCM_56160_A0)
   3999     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM56160_A0r */
   4000         soc_block_list[2],
   4001         soc_genreg,
   4002         1,
   4003         0,
   4004         0x2022700,
   4005         0,
   4006         0,
   4007         3,
   4008         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   4009         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4010         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4011         -1,
   4012         -1,
   4013     },
   4014 #endif /* chips */
   4015 
   4016 #if defined(BCM_56370_A0)
   4017     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM56370_A0r */
   4018         soc_block_list[9],
   4019         soc_genreg,
   4020         1,
   4021         0,
   4022         0x2022700,
   4023         0,
   4024         0,
   4025         3,
   4026         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   4027         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4028         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4029         -1,
   4030         -1,
   4031         3,
   4032     },
   4033 #endif /* chips */
   4034 
   4035 #if defined(BCM_56142_A0) || defined(BCM_56440_A0) || \
   4036     defined(BCM_56440_B0)
   4037     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM56440_A0r */
   4038         soc_block_list[2],
   4039         soc_genreg,
   4040         1,
   4041         0,
   4042         0x80036,
   4043         0,
   4044         0,
   4045         4,
   4046         soc_GE0_EEE_CONFIG_BCM56440_A0r_fields,
   4047         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4048         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4049         -1,
   4050         -1,
   4051     },
   4052 #endif /* chips */
   4053 
   4054 #if defined(BCM_88375_A0)
   4055     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM88375_A0r */
   4056         soc_block_list[2],
   4057         soc_genreg,
   4058         1,
   4059         0,
   4060         0x2022700,
   4061         0,
   4062         0,
   4063         3,
   4064         soc_GE3_EEE_CONFIG_BCM88375_A0r_fields,
   4065         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4066         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4067         -1,
   4068         -1,
   4069     },
   4070 #endif /* chips */
   4071 
   4072 #if defined(BCM_88375_B0)
   4073     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM88375_B0r */
   4074         soc_block_list[2],
   4075         soc_genreg,
   4076         1,
   4077         0,
   4078         0x2022700,
   4079         0,
   4080         0,
   4081         3,
   4082         soc_GE3_EEE_CONFIG_BCM88375_B0r_fields,
   4083         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4084         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4085         -1,
   4086         -1,
   4087     },
   4088 #endif /* chips */
   4089 
   4090 #if defined(BCM_88470_A0)
   4091     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM88470_A0r */
   4092         soc_block_list[2],
   4093         soc_genreg,
   4094         1,
   4095         0,
   4096         0x2022700,
   4097         0,
   4098         0,
   4099         3,
   4100         soc_GE3_EEE_CONFIG_BCM88470_A0r_fields,
   4101         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4102         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4103         -1,
   4104         -1,
   4105     },
   4106 #endif /* chips */
   4107 
   4108 #if defined(BCM_88470_B0)
   4109     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM88470_B0r */
   4110         soc_block_list[2],
   4111         soc_genreg,
   4112         1,
   4113         0,
   4114         0x2022700,
   4115         0,
   4116         0,
   4117         3,
   4118         soc_GE3_EEE_CONFIG_BCM88470_B0r_fields,
   4119         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4120         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4121         -1,
   4122         -1,
   4123     },
   4124 #endif /* chips */
   4125 
   4126 #if defined(BCM_88675_A0)
   4127     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM88675_A0r */
   4128         soc_block_list[2],
   4129         soc_genreg,
   4130         1,
   4131         0,
   4132         0x2022700,
   4133         0,
   4134         0,
   4135         3,
   4136         soc_GE3_EEE_CONFIGr_fields,
   4137         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4138         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4139         -1,
   4140         -1,
   4141     },
   4142 #endif /* chips */
   4143 
   4144 #if defined(BCM_88675_B0)
   4145     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM88675_B0r */
   4146         soc_block_list[2],
   4147         soc_genreg,
   4148         1,
   4149         0,
   4150         0x2022700,
   4151         0,
   4152         0,
   4153         3,
   4154         soc_GE3_EEE_CONFIG_BCM88675_B0r_fields,
   4155         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4156         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4157         -1,
   4158         -1,
   4159     },
   4160 #endif /* chips */
   4161 
   4162 #if defined(BCM_88680_A0)
   4163     { /* SOC_REG_INT_GE3_EEE_CONFIG_BCM88680_A0r */
   4164         soc_block_list[2],
   4165         soc_genreg,
   4166         1,
   4167         0,
   4168         0x2022700,
   4169         0,
   4170         0,
   4171         3,
   4172         soc_GE3_EEE_CONFIG_BCM88680_A0r_fields,
   4173         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   4174         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4175         -1,
   4176         -1,
   4177     },
   4178 #endif /* chips */
   4179 
   4180 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   4181     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   4182     { /* SOC_REG_INT_GE3_GBODE_CELL_CNTr */
   4183         soc_block_list[2],
   4184         soc_genreg,
   4185         1,
   4186         0,
   4187         0x80013,
   4188         SOC_REG_FLAG_RO,
   4189         0,
   4190         1,
   4191         soc_GE0_GBODE_CELL_CNTr_fields,
   4192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4193         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4194         -1,
   4195         -1,
   4196     },
   4197 #endif /* chips */
   4198 
   4199 #if defined(BCM_53400_A0)
   4200     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM53400_A0r */
   4201         soc_block_list[9],
   4202         soc_genreg,
   4203         1,
   4204         0,
   4205         0x2021400,
   4206         SOC_REG_FLAG_RO,
   4207         0,
   4208         1,
   4209         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   4210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4212         -1,
   4213         -1,
   4214     },
   4215 #endif /* chips */
   4216 
   4217 #if defined(BCM_53540_A0)
   4218     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM53540_A0r */
   4219         soc_block_list[2],
   4220         soc_genreg,
   4221         1,
   4222         0,
   4223         0x2021400,
   4224         SOC_REG_FLAG_RO,
   4225         0,
   4226         1,
   4227         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   4228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4229         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4230         -1,
   4231         -1,
   4232     },
   4233 #endif /* chips */
   4234 
   4235 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4236     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM53570_A0r */
   4237         soc_block_list[2],
   4238         soc_genreg,
   4239         1,
   4240         0,
   4241         0x2021c00,
   4242         SOC_REG_FLAG_RO,
   4243         0,
   4244         1,
   4245         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   4246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4247         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4248         -1,
   4249         -1,
   4250     },
   4251 #endif /* chips */
   4252 
   4253 #if defined(BCM_56150_A0)
   4254     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM56150_A0r */
   4255         soc_block_list[2],
   4256         soc_genreg,
   4257         1,
   4258         0,
   4259         0x2021400,
   4260         SOC_REG_FLAG_RO,
   4261         0,
   4262         1,
   4263         soc_GE0_GBODE_CELL_CNT_BCM56150_A0r_fields,
   4264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4265         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4266         -1,
   4267         -1,
   4268     },
   4269 #endif /* chips */
   4270 
   4271 #if defined(BCM_56160_A0)
   4272     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM56160_A0r */
   4273         soc_block_list[2],
   4274         soc_genreg,
   4275         1,
   4276         0,
   4277         0x2021400,
   4278         SOC_REG_FLAG_RO,
   4279         0,
   4280         1,
   4281         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   4282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4284         -1,
   4285         -1,
   4286     },
   4287 #endif /* chips */
   4288 
   4289 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   4290     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   4291     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   4292     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   4293     defined(BCM_56440_B0)
   4294     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM56224_A0r */
   4295         soc_block_list[2],
   4296         soc_genreg,
   4297         1,
   4298         0,
   4299         0x80013,
   4300         SOC_REG_FLAG_RO,
   4301         0,
   4302         1,
   4303         soc_GE_GBODE_CELL_CNTr_fields,
   4304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4305         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4306         -1,
   4307         -1,
   4308     },
   4309 #endif /* chips */
   4310 
   4311 #if defined(BCM_56370_A0)
   4312     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM56370_A0r */
   4313         soc_block_list[9],
   4314         soc_genreg,
   4315         1,
   4316         0,
   4317         0x2021400,
   4318         SOC_REG_FLAG_RO,
   4319         0,
   4320         1,
   4321         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   4322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4323         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4324         -1,
   4325         -1,
   4326         3,
   4327     },
   4328 #endif /* chips */
   4329 
   4330 #if defined(BCM_88375_A0)
   4331     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM88375_A0r */
   4332         soc_block_list[2],
   4333         soc_genreg,
   4334         1,
   4335         0,
   4336         0x2021400,
   4337         SOC_REG_FLAG_RO,
   4338         0,
   4339         1,
   4340         soc_GE3_GBODE_CELL_CNT_BCM88375_A0r_fields,
   4341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4342         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4343         -1,
   4344         -1,
   4345     },
   4346 #endif /* chips */
   4347 
   4348 #if defined(BCM_88375_B0)
   4349     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM88375_B0r */
   4350         soc_block_list[2],
   4351         soc_genreg,
   4352         1,
   4353         0,
   4354         0x2021400,
   4355         SOC_REG_FLAG_RO,
   4356         0,
   4357         1,
   4358         soc_GE3_GBODE_CELL_CNT_BCM88375_B0r_fields,
   4359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4360         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4361         -1,
   4362         -1,
   4363     },
   4364 #endif /* chips */
   4365 
   4366 #if defined(BCM_88470_A0)
   4367     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM88470_A0r */
   4368         soc_block_list[2],
   4369         soc_genreg,
   4370         1,
   4371         0,
   4372         0x2021400,
   4373         SOC_REG_FLAG_RO,
   4374         0,
   4375         1,
   4376         soc_GE3_GBODE_CELL_CNT_BCM88470_A0r_fields,
   4377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4378         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4379         -1,
   4380         -1,
   4381     },
   4382 #endif /* chips */
   4383 
   4384 #if defined(BCM_88470_B0)
   4385     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM88470_B0r */
   4386         soc_block_list[2],
   4387         soc_genreg,
   4388         1,
   4389         0,
   4390         0x2021400,
   4391         SOC_REG_FLAG_RO,
   4392         0,
   4393         1,
   4394         soc_GE3_GBODE_CELL_CNT_BCM88470_B0r_fields,
   4395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4396         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4397         -1,
   4398         -1,
   4399     },
   4400 #endif /* chips */
   4401 
   4402 #if defined(BCM_88675_A0)
   4403     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM88675_A0r */
   4404         soc_block_list[2],
   4405         soc_genreg,
   4406         1,
   4407         0,
   4408         0x2021400,
   4409         SOC_REG_FLAG_RO,
   4410         0,
   4411         1,
   4412         soc_GE3_GBODE_CELL_CNTr_fields,
   4413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4414         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4415         -1,
   4416         -1,
   4417     },
   4418 #endif /* chips */
   4419 
   4420 #if defined(BCM_88675_B0)
   4421     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM88675_B0r */
   4422         soc_block_list[2],
   4423         soc_genreg,
   4424         1,
   4425         0,
   4426         0x2021400,
   4427         SOC_REG_FLAG_RO,
   4428         0,
   4429         1,
   4430         soc_GE3_GBODE_CELL_CNT_BCM88675_B0r_fields,
   4431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4432         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4433         -1,
   4434         -1,
   4435     },
   4436 #endif /* chips */
   4437 
   4438 #if defined(BCM_88680_A0)
   4439     { /* SOC_REG_INT_GE3_GBODE_CELL_CNT_BCM88680_A0r */
   4440         soc_block_list[2],
   4441         soc_genreg,
   4442         1,
   4443         0,
   4444         0x2021400,
   4445         SOC_REG_FLAG_RO,
   4446         0,
   4447         1,
   4448         soc_GE3_GBODE_CELL_CNT_BCM88680_A0r_fields,
   4449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4450         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4451         -1,
   4452         -1,
   4453     },
   4454 #endif /* chips */
   4455 
   4456 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   4457     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   4458     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNTr */
   4459         soc_block_list[2],
   4460         soc_genreg,
   4461         1,
   4462         0,
   4463         0x8001f,
   4464         SOC_REG_FLAG_RO,
   4465         0,
   4466         1,
   4467         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   4468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4469         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4470         -1,
   4471         -1,
   4472     },
   4473 #endif /* chips */
   4474 
   4475 #if defined(BCM_53400_A0)
   4476     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM53400_A0r */
   4477         soc_block_list[9],
   4478         soc_genreg,
   4479         1,
   4480         0,
   4481         0x2021c00,
   4482         SOC_REG_FLAG_RO,
   4483         0,
   4484         1,
   4485         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   4486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4488         -1,
   4489         -1,
   4490     },
   4491 #endif /* chips */
   4492 
   4493 #if defined(BCM_53540_A0)
   4494     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM53540_A0r */
   4495         soc_block_list[2],
   4496         soc_genreg,
   4497         1,
   4498         0,
   4499         0x2021c00,
   4500         SOC_REG_FLAG_RO,
   4501         0,
   4502         1,
   4503         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   4504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4505         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4506         -1,
   4507         -1,
   4508     },
   4509 #endif /* chips */
   4510 
   4511 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4512     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM53570_A0r */
   4513         soc_block_list[2],
   4514         soc_genreg,
   4515         1,
   4516         0,
   4517         0x2022400,
   4518         SOC_REG_FLAG_RO,
   4519         0,
   4520         1,
   4521         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   4522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4524         -1,
   4525         -1,
   4526     },
   4527 #endif /* chips */
   4528 
   4529 #if defined(BCM_56150_A0)
   4530     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM56150_A0r */
   4531         soc_block_list[2],
   4532         soc_genreg,
   4533         1,
   4534         0,
   4535         0x2021c00,
   4536         SOC_REG_FLAG_RO,
   4537         0,
   4538         1,
   4539         soc_GE0_GBODE_CELL_REQ_CNT_BCM56150_A0r_fields,
   4540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4541         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4542         -1,
   4543         -1,
   4544     },
   4545 #endif /* chips */
   4546 
   4547 #if defined(BCM_56160_A0)
   4548     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM56160_A0r */
   4549         soc_block_list[2],
   4550         soc_genreg,
   4551         1,
   4552         0,
   4553         0x2021c00,
   4554         SOC_REG_FLAG_RO,
   4555         0,
   4556         1,
   4557         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   4558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4559         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4560         -1,
   4561         -1,
   4562     },
   4563 #endif /* chips */
   4564 
   4565 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   4566     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   4567     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   4568     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   4569     defined(BCM_56440_B0)
   4570     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   4571         soc_block_list[2],
   4572         soc_genreg,
   4573         1,
   4574         0,
   4575         0x8001f,
   4576         SOC_REG_FLAG_RO,
   4577         0,
   4578         1,
   4579         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   4580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4582         -1,
   4583         -1,
   4584     },
   4585 #endif /* chips */
   4586 
   4587 #if defined(BCM_56370_A0)
   4588     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM56370_A0r */
   4589         soc_block_list[9],
   4590         soc_genreg,
   4591         1,
   4592         0,
   4593         0x2021c00,
   4594         SOC_REG_FLAG_RO,
   4595         0,
   4596         1,
   4597         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   4598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4600         -1,
   4601         -1,
   4602         3,
   4603     },
   4604 #endif /* chips */
   4605 
   4606 #if defined(BCM_88375_A0)
   4607     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM88375_A0r */
   4608         soc_block_list[2],
   4609         soc_genreg,
   4610         1,
   4611         0,
   4612         0x2021c00,
   4613         SOC_REG_FLAG_RO,
   4614         0,
   4615         1,
   4616         soc_GE3_GBODE_CELL_REQ_CNT_BCM88375_A0r_fields,
   4617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4618         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4619         -1,
   4620         -1,
   4621     },
   4622 #endif /* chips */
   4623 
   4624 #if defined(BCM_88375_B0)
   4625     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM88375_B0r */
   4626         soc_block_list[2],
   4627         soc_genreg,
   4628         1,
   4629         0,
   4630         0x2021c00,
   4631         SOC_REG_FLAG_RO,
   4632         0,
   4633         1,
   4634         soc_GE3_GBODE_CELL_REQ_CNT_BCM88375_B0r_fields,
   4635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4636         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4637         -1,
   4638         -1,
   4639     },
   4640 #endif /* chips */
   4641 
   4642 #if defined(BCM_88470_A0)
   4643     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM88470_A0r */
   4644         soc_block_list[2],
   4645         soc_genreg,
   4646         1,
   4647         0,
   4648         0x2021c00,
   4649         SOC_REG_FLAG_RO,
   4650         0,
   4651         1,
   4652         soc_GE3_GBODE_CELL_REQ_CNT_BCM88470_A0r_fields,
   4653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4654         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4655         -1,
   4656         -1,
   4657     },
   4658 #endif /* chips */
   4659 
   4660 #if defined(BCM_88470_B0)
   4661     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM88470_B0r */
   4662         soc_block_list[2],
   4663         soc_genreg,
   4664         1,
   4665         0,
   4666         0x2021c00,
   4667         SOC_REG_FLAG_RO,
   4668         0,
   4669         1,
   4670         soc_GE3_GBODE_CELL_REQ_CNT_BCM88470_B0r_fields,
   4671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4672         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4673         -1,
   4674         -1,
   4675     },
   4676 #endif /* chips */
   4677 
   4678 #if defined(BCM_88675_A0)
   4679     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM88675_A0r */
   4680         soc_block_list[2],
   4681         soc_genreg,
   4682         1,
   4683         0,
   4684         0x2021c00,
   4685         SOC_REG_FLAG_RO,
   4686         0,
   4687         1,
   4688         soc_GE3_GBODE_CELL_REQ_CNTr_fields,
   4689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4690         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4691         -1,
   4692         -1,
   4693     },
   4694 #endif /* chips */
   4695 
   4696 #if defined(BCM_88675_B0)
   4697     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM88675_B0r */
   4698         soc_block_list[2],
   4699         soc_genreg,
   4700         1,
   4701         0,
   4702         0x2021c00,
   4703         SOC_REG_FLAG_RO,
   4704         0,
   4705         1,
   4706         soc_GE3_GBODE_CELL_REQ_CNT_BCM88675_B0r_fields,
   4707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4708         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4709         -1,
   4710         -1,
   4711     },
   4712 #endif /* chips */
   4713 
   4714 #if defined(BCM_88680_A0)
   4715     { /* SOC_REG_INT_GE3_GBODE_CELL_REQ_CNT_BCM88680_A0r */
   4716         soc_block_list[2],
   4717         soc_genreg,
   4718         1,
   4719         0,
   4720         0x2021c00,
   4721         SOC_REG_FLAG_RO,
   4722         0,
   4723         1,
   4724         soc_GE3_GBODE_CELL_REQ_CNT_BCM88680_A0r_fields,
   4725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4726         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4727         -1,
   4728         -1,
   4729     },
   4730 #endif /* chips */
   4731 
   4732 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   4733     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   4734     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   4735     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   4736     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   4737     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
   4738     defined(BCM_56514_A0)
   4739     { /* SOC_REG_INT_GE3_GBOD_OVRFLWr */
   4740         soc_block_list[2],
   4741         soc_genreg,
   4742         1,
   4743         0,
   4744         0x80007,
   4745         SOC_REG_FLAG_RO,
   4746         0,
   4747         1,
   4748         soc_GE0_GBOD_OVRFLWr_fields,
   4749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4750         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4751         -1,
   4752         -1,
   4753     },
   4754 #endif /* chips */
   4755 
   4756 #if defined(BCM_53400_A0)
   4757     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM53400_A0r */
   4758         soc_block_list[9],
   4759         soc_genreg,
   4760         1,
   4761         0,
   4762         0x2020c00,
   4763         SOC_REG_FLAG_RO,
   4764         0,
   4765         1,
   4766         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   4767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4768         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4769         -1,
   4770         -1,
   4771     },
   4772 #endif /* chips */
   4773 
   4774 #if defined(BCM_53540_A0)
   4775     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM53540_A0r */
   4776         soc_block_list[2],
   4777         soc_genreg,
   4778         1,
   4779         0,
   4780         0x2020c00,
   4781         SOC_REG_FLAG_RO,
   4782         0,
   4783         1,
   4784         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   4785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4786         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4787         -1,
   4788         -1,
   4789     },
   4790 #endif /* chips */
   4791 
   4792 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   4793     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM53570_A0r */
   4794         soc_block_list[2],
   4795         soc_genreg,
   4796         1,
   4797         0,
   4798         0x2021400,
   4799         SOC_REG_FLAG_RO,
   4800         0,
   4801         1,
   4802         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   4803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4804         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4805         -1,
   4806         -1,
   4807     },
   4808 #endif /* chips */
   4809 
   4810 #if defined(BCM_56150_A0)
   4811     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM56150_A0r */
   4812         soc_block_list[2],
   4813         soc_genreg,
   4814         1,
   4815         0,
   4816         0x2020c00,
   4817         SOC_REG_FLAG_RO,
   4818         0,
   4819         1,
   4820         soc_PORT_CDC_RXFIFO_OVRFLW_BCM56640_A0r_fields,
   4821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4822         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4823         -1,
   4824         -1,
   4825     },
   4826 #endif /* chips */
   4827 
   4828 #if defined(BCM_56160_A0)
   4829     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM56160_A0r */
   4830         soc_block_list[2],
   4831         soc_genreg,
   4832         1,
   4833         0,
   4834         0x2020c00,
   4835         SOC_REG_FLAG_RO,
   4836         0,
   4837         1,
   4838         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   4839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4840         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4841         -1,
   4842         -1,
   4843     },
   4844 #endif /* chips */
   4845 
   4846 #if defined(BCM_56370_A0)
   4847     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM56370_A0r */
   4848         soc_block_list[9],
   4849         soc_genreg,
   4850         1,
   4851         0,
   4852         0x2020c00,
   4853         SOC_REG_FLAG_RO,
   4854         0,
   4855         1,
   4856         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   4857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4858         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4859         -1,
   4860         -1,
   4861         3,
   4862     },
   4863 #endif /* chips */
   4864 
   4865 #if defined(BCM_88375_A0)
   4866     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM88375_A0r */
   4867         soc_block_list[2],
   4868         soc_genreg,
   4869         1,
   4870         0,
   4871         0x2020c00,
   4872         SOC_REG_FLAG_RO,
   4873         0,
   4874         1,
   4875         soc_GE3_GBOD_OVRFLW_BCM88375_A0r_fields,
   4876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4877         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4878         -1,
   4879         -1,
   4880     },
   4881 #endif /* chips */
   4882 
   4883 #if defined(BCM_88375_B0)
   4884     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM88375_B0r */
   4885         soc_block_list[2],
   4886         soc_genreg,
   4887         1,
   4888         0,
   4889         0x2020c00,
   4890         SOC_REG_FLAG_RO,
   4891         0,
   4892         1,
   4893         soc_GE3_GBOD_OVRFLW_BCM88375_B0r_fields,
   4894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4895         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4896         -1,
   4897         -1,
   4898     },
   4899 #endif /* chips */
   4900 
   4901 #if defined(BCM_88470_A0)
   4902     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM88470_A0r */
   4903         soc_block_list[2],
   4904         soc_genreg,
   4905         1,
   4906         0,
   4907         0x2020c00,
   4908         SOC_REG_FLAG_RO,
   4909         0,
   4910         1,
   4911         soc_GE3_GBOD_OVRFLW_BCM88470_A0r_fields,
   4912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4913         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4914         -1,
   4915         -1,
   4916     },
   4917 #endif /* chips */
   4918 
   4919 #if defined(BCM_88470_B0)
   4920     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM88470_B0r */
   4921         soc_block_list[2],
   4922         soc_genreg,
   4923         1,
   4924         0,
   4925         0x2020c00,
   4926         SOC_REG_FLAG_RO,
   4927         0,
   4928         1,
   4929         soc_GE3_GBOD_OVRFLW_BCM88470_B0r_fields,
   4930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4931         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4932         -1,
   4933         -1,
   4934     },
   4935 #endif /* chips */
   4936 
   4937 #if defined(BCM_88675_A0)
   4938     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM88675_A0r */
   4939         soc_block_list[2],
   4940         soc_genreg,
   4941         1,
   4942         0,
   4943         0x2020c00,
   4944         SOC_REG_FLAG_RO,
   4945         0,
   4946         1,
   4947         soc_GE3_GBOD_OVRFLWr_fields,
   4948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4949         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4950         -1,
   4951         -1,
   4952     },
   4953 #endif /* chips */
   4954 
   4955 #if defined(BCM_88675_B0)
   4956     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM88675_B0r */
   4957         soc_block_list[2],
   4958         soc_genreg,
   4959         1,
   4960         0,
   4961         0x2020c00,
   4962         SOC_REG_FLAG_RO,
   4963         0,
   4964         1,
   4965         soc_GE3_GBOD_OVRFLW_BCM88675_B0r_fields,
   4966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4967         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4968         -1,
   4969         -1,
   4970     },
   4971 #endif /* chips */
   4972 
   4973 #if defined(BCM_88680_A0)
   4974     { /* SOC_REG_INT_GE3_GBOD_OVRFLW_BCM88680_A0r */
   4975         soc_block_list[2],
   4976         soc_genreg,
   4977         1,
   4978         0,
   4979         0x2020c00,
   4980         SOC_REG_FLAG_RO,
   4981         0,
   4982         1,
   4983         soc_GE3_GBOD_OVRFLW_BCM88680_A0r_fields,
   4984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4985         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4986         -1,
   4987         -1,
   4988     },
   4989 #endif /* chips */
   4990 
   4991 #if defined(BCM_53570_A0)
   4992     { /* SOC_REG_INT_GE3_MIN_FRAG_SIZEr */
   4993         soc_block_list[2],
   4994         soc_genreg,
   4995         1,
   4996         0,
   4997         0x2020c00,
   4998         0,
   4999         0,
   5000         2,
   5001         soc_GE0_MIN_FRAG_SIZEr_fields,
   5002         SOC_RESET_VAL_DEC(0x00000387, 0x00000000)
   5003         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   5004         -1,
   5005         -1,
   5006     },
   5007 #endif /* chips */
   5008 
   5009 #if defined(BCM_53570_B0)
   5010     { /* SOC_REG_INT_GE3_MIN_FRAG_SIZE_BCM53570_B0r */
   5011         soc_block_list[2],
   5012         soc_genreg,
   5013         1,
   5014         0,
   5015         0x2020c00,
   5016         0,
   5017         0,
   5018         2,
   5019         soc_GE0_MIN_FRAG_SIZE_BCM53570_B0r_fields,
   5020         SOC_RESET_VAL_DEC(0x00000408, 0x00000000)
   5021         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   5022         -1,
   5023         -1,
   5024     },
   5025 #endif /* chips */
   5026 
   5027 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5028     { /* SOC_REG_INT_GE3_S3MII_SPEED_DEBUGr */
   5029         soc_block_list[2],
   5030         soc_genreg,
   5031         1,
   5032         0,
   5033         0x8003e,
   5034         SOC_REG_FLAG_RO,
   5035         0,
   5036         4,
   5037         soc_GE0_S3MII_SPEED_DEBUGr_fields,
   5038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5040         -1,
   5041         -1,
   5042     },
   5043 #endif /* chips */
   5044 
   5045 #if defined(BCM_53324_A0)
   5046     { /* SOC_REG_INT_GE4_EEE_CONFIGr */
   5047         soc_block_list[2],
   5048         soc_genreg,
   5049         1,
   5050         0,
   5051         0x8003a,
   5052         0,
   5053         0,
   5054         4,
   5055         soc_GE0_EEE_CONFIGr_fields,
   5056         SOC_RESET_VAL_DEC(0x000014e1, 0x00000000)
   5057         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5058         -1,
   5059         -1,
   5060     },
   5061 #endif /* chips */
   5062 
   5063 #if defined(BCM_53400_A0)
   5064     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM53400_A0r */
   5065         soc_block_list[9],
   5066         soc_genreg,
   5067         1,
   5068         0,
   5069         0x2022800,
   5070         0,
   5071         0,
   5072         3,
   5073         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   5074         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5075         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5076         -1,
   5077         -1,
   5078     },
   5079 #endif /* chips */
   5080 
   5081 #if defined(BCM_53540_A0)
   5082     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM53540_A0r */
   5083         soc_block_list[2],
   5084         soc_genreg,
   5085         1,
   5086         0,
   5087         0x2022800,
   5088         0,
   5089         0,
   5090         3,
   5091         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   5092         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5093         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5094         -1,
   5095         -1,
   5096     },
   5097 #endif /* chips */
   5098 
   5099 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5100     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM53570_A0r */
   5101         soc_block_list[2],
   5102         soc_genreg,
   5103         1,
   5104         0,
   5105         0x2023300,
   5106         0,
   5107         0,
   5108         3,
   5109         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   5110         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5111         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5112         -1,
   5113         -1,
   5114     },
   5115 #endif /* chips */
   5116 
   5117 #if defined(BCM_56150_A0)
   5118     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM56150_A0r */
   5119         soc_block_list[2],
   5120         soc_genreg,
   5121         1,
   5122         0,
   5123         0x2022800,
   5124         0,
   5125         0,
   5126         3,
   5127         soc_GE0_EEE_CONFIG_BCM56150_A0r_fields,
   5128         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5129         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5130         -1,
   5131         -1,
   5132     },
   5133 #endif /* chips */
   5134 
   5135 #if defined(BCM_56160_A0)
   5136     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM56160_A0r */
   5137         soc_block_list[2],
   5138         soc_genreg,
   5139         1,
   5140         0,
   5141         0x2022800,
   5142         0,
   5143         0,
   5144         3,
   5145         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   5146         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5147         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5148         -1,
   5149         -1,
   5150     },
   5151 #endif /* chips */
   5152 
   5153 #if defined(BCM_56370_A0)
   5154     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM56370_A0r */
   5155         soc_block_list[9],
   5156         soc_genreg,
   5157         1,
   5158         0,
   5159         0x2022800,
   5160         0,
   5161         0,
   5162         3,
   5163         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   5164         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5165         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5166         -1,
   5167         -1,
   5168         3,
   5169     },
   5170 #endif /* chips */
   5171 
   5172 #if defined(BCM_56142_A0) || defined(BCM_56440_A0) || \
   5173     defined(BCM_56440_B0)
   5174     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM56440_A0r */
   5175         soc_block_list[2],
   5176         soc_genreg,
   5177         1,
   5178         0,
   5179         0x80037,
   5180         0,
   5181         0,
   5182         4,
   5183         soc_GE0_EEE_CONFIG_BCM56440_A0r_fields,
   5184         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5186         -1,
   5187         -1,
   5188     },
   5189 #endif /* chips */
   5190 
   5191 #if defined(BCM_88375_A0)
   5192     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM88375_A0r */
   5193         soc_block_list[2],
   5194         soc_genreg,
   5195         1,
   5196         0,
   5197         0x2022800,
   5198         0,
   5199         0,
   5200         3,
   5201         soc_GE4_EEE_CONFIG_BCM88375_A0r_fields,
   5202         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5203         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5204         -1,
   5205         -1,
   5206     },
   5207 #endif /* chips */
   5208 
   5209 #if defined(BCM_88375_B0)
   5210     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM88375_B0r */
   5211         soc_block_list[2],
   5212         soc_genreg,
   5213         1,
   5214         0,
   5215         0x2022800,
   5216         0,
   5217         0,
   5218         3,
   5219         soc_GE4_EEE_CONFIG_BCM88375_B0r_fields,
   5220         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5221         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5222         -1,
   5223         -1,
   5224     },
   5225 #endif /* chips */
   5226 
   5227 #if defined(BCM_88470_A0)
   5228     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM88470_A0r */
   5229         soc_block_list[2],
   5230         soc_genreg,
   5231         1,
   5232         0,
   5233         0x2022800,
   5234         0,
   5235         0,
   5236         3,
   5237         soc_GE4_EEE_CONFIG_BCM88470_A0r_fields,
   5238         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5239         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5240         -1,
   5241         -1,
   5242     },
   5243 #endif /* chips */
   5244 
   5245 #if defined(BCM_88470_B0)
   5246     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM88470_B0r */
   5247         soc_block_list[2],
   5248         soc_genreg,
   5249         1,
   5250         0,
   5251         0x2022800,
   5252         0,
   5253         0,
   5254         3,
   5255         soc_GE4_EEE_CONFIG_BCM88470_B0r_fields,
   5256         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5257         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5258         -1,
   5259         -1,
   5260     },
   5261 #endif /* chips */
   5262 
   5263 #if defined(BCM_88675_A0)
   5264     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM88675_A0r */
   5265         soc_block_list[2],
   5266         soc_genreg,
   5267         1,
   5268         0,
   5269         0x2022800,
   5270         0,
   5271         0,
   5272         3,
   5273         soc_GE4_EEE_CONFIGr_fields,
   5274         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5275         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5276         -1,
   5277         -1,
   5278     },
   5279 #endif /* chips */
   5280 
   5281 #if defined(BCM_88675_B0)
   5282     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM88675_B0r */
   5283         soc_block_list[2],
   5284         soc_genreg,
   5285         1,
   5286         0,
   5287         0x2022800,
   5288         0,
   5289         0,
   5290         3,
   5291         soc_GE4_EEE_CONFIG_BCM88675_B0r_fields,
   5292         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5293         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5294         -1,
   5295         -1,
   5296     },
   5297 #endif /* chips */
   5298 
   5299 #if defined(BCM_88680_A0)
   5300     { /* SOC_REG_INT_GE4_EEE_CONFIG_BCM88680_A0r */
   5301         soc_block_list[2],
   5302         soc_genreg,
   5303         1,
   5304         0,
   5305         0x2022800,
   5306         0,
   5307         0,
   5308         3,
   5309         soc_GE4_EEE_CONFIG_BCM88680_A0r_fields,
   5310         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   5311         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   5312         -1,
   5313         -1,
   5314     },
   5315 #endif /* chips */
   5316 
   5317 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   5318     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   5319     { /* SOC_REG_INT_GE4_GBODE_CELL_CNTr */
   5320         soc_block_list[2],
   5321         soc_genreg,
   5322         1,
   5323         0,
   5324         0x80014,
   5325         SOC_REG_FLAG_RO,
   5326         0,
   5327         1,
   5328         soc_GE0_GBODE_CELL_CNTr_fields,
   5329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5330         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5331         -1,
   5332         -1,
   5333     },
   5334 #endif /* chips */
   5335 
   5336 #if defined(BCM_53400_A0)
   5337     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM53400_A0r */
   5338         soc_block_list[9],
   5339         soc_genreg,
   5340         1,
   5341         0,
   5342         0x2021500,
   5343         SOC_REG_FLAG_RO,
   5344         0,
   5345         1,
   5346         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   5347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5348         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5349         -1,
   5350         -1,
   5351     },
   5352 #endif /* chips */
   5353 
   5354 #if defined(BCM_53540_A0)
   5355     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM53540_A0r */
   5356         soc_block_list[2],
   5357         soc_genreg,
   5358         1,
   5359         0,
   5360         0x2021500,
   5361         SOC_REG_FLAG_RO,
   5362         0,
   5363         1,
   5364         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   5365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5366         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5367         -1,
   5368         -1,
   5369     },
   5370 #endif /* chips */
   5371 
   5372 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5373     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM53570_A0r */
   5374         soc_block_list[2],
   5375         soc_genreg,
   5376         1,
   5377         0,
   5378         0x2021d00,
   5379         SOC_REG_FLAG_RO,
   5380         0,
   5381         1,
   5382         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   5383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5384         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5385         -1,
   5386         -1,
   5387     },
   5388 #endif /* chips */
   5389 
   5390 #if defined(BCM_56150_A0)
   5391     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM56150_A0r */
   5392         soc_block_list[2],
   5393         soc_genreg,
   5394         1,
   5395         0,
   5396         0x2021500,
   5397         SOC_REG_FLAG_RO,
   5398         0,
   5399         1,
   5400         soc_GE0_GBODE_CELL_CNT_BCM56150_A0r_fields,
   5401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5402         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5403         -1,
   5404         -1,
   5405     },
   5406 #endif /* chips */
   5407 
   5408 #if defined(BCM_56160_A0)
   5409     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM56160_A0r */
   5410         soc_block_list[2],
   5411         soc_genreg,
   5412         1,
   5413         0,
   5414         0x2021500,
   5415         SOC_REG_FLAG_RO,
   5416         0,
   5417         1,
   5418         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   5419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5420         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5421         -1,
   5422         -1,
   5423     },
   5424 #endif /* chips */
   5425 
   5426 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   5427     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   5428     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   5429     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   5430     defined(BCM_56440_B0)
   5431     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM56224_A0r */
   5432         soc_block_list[2],
   5433         soc_genreg,
   5434         1,
   5435         0,
   5436         0x80014,
   5437         SOC_REG_FLAG_RO,
   5438         0,
   5439         1,
   5440         soc_GE_GBODE_CELL_CNTr_fields,
   5441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5442         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5443         -1,
   5444         -1,
   5445     },
   5446 #endif /* chips */
   5447 
   5448 #if defined(BCM_56370_A0)
   5449     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM56370_A0r */
   5450         soc_block_list[9],
   5451         soc_genreg,
   5452         1,
   5453         0,
   5454         0x2021500,
   5455         SOC_REG_FLAG_RO,
   5456         0,
   5457         1,
   5458         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   5459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5460         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5461         -1,
   5462         -1,
   5463         3,
   5464     },
   5465 #endif /* chips */
   5466 
   5467 #if defined(BCM_88375_A0)
   5468     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM88375_A0r */
   5469         soc_block_list[2],
   5470         soc_genreg,
   5471         1,
   5472         0,
   5473         0x2021500,
   5474         SOC_REG_FLAG_RO,
   5475         0,
   5476         1,
   5477         soc_GE4_GBODE_CELL_CNT_BCM88375_A0r_fields,
   5478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5479         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5480         -1,
   5481         -1,
   5482     },
   5483 #endif /* chips */
   5484 
   5485 #if defined(BCM_88375_B0)
   5486     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM88375_B0r */
   5487         soc_block_list[2],
   5488         soc_genreg,
   5489         1,
   5490         0,
   5491         0x2021500,
   5492         SOC_REG_FLAG_RO,
   5493         0,
   5494         1,
   5495         soc_GE4_GBODE_CELL_CNT_BCM88375_B0r_fields,
   5496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5497         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5498         -1,
   5499         -1,
   5500     },
   5501 #endif /* chips */
   5502 
   5503 #if defined(BCM_88470_A0)
   5504     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM88470_A0r */
   5505         soc_block_list[2],
   5506         soc_genreg,
   5507         1,
   5508         0,
   5509         0x2021500,
   5510         SOC_REG_FLAG_RO,
   5511         0,
   5512         1,
   5513         soc_GE4_GBODE_CELL_CNT_BCM88470_A0r_fields,
   5514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5515         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5516         -1,
   5517         -1,
   5518     },
   5519 #endif /* chips */
   5520 
   5521 #if defined(BCM_88470_B0)
   5522     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM88470_B0r */
   5523         soc_block_list[2],
   5524         soc_genreg,
   5525         1,
   5526         0,
   5527         0x2021500,
   5528         SOC_REG_FLAG_RO,
   5529         0,
   5530         1,
   5531         soc_GE4_GBODE_CELL_CNT_BCM88470_B0r_fields,
   5532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5533         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5534         -1,
   5535         -1,
   5536     },
   5537 #endif /* chips */
   5538 
   5539 #if defined(BCM_88675_A0)
   5540     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM88675_A0r */
   5541         soc_block_list[2],
   5542         soc_genreg,
   5543         1,
   5544         0,
   5545         0x2021500,
   5546         SOC_REG_FLAG_RO,
   5547         0,
   5548         1,
   5549         soc_GE4_GBODE_CELL_CNTr_fields,
   5550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5551         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5552         -1,
   5553         -1,
   5554     },
   5555 #endif /* chips */
   5556 
   5557 #if defined(BCM_88675_B0)
   5558     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM88675_B0r */
   5559         soc_block_list[2],
   5560         soc_genreg,
   5561         1,
   5562         0,
   5563         0x2021500,
   5564         SOC_REG_FLAG_RO,
   5565         0,
   5566         1,
   5567         soc_GE4_GBODE_CELL_CNT_BCM88675_B0r_fields,
   5568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5569         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5570         -1,
   5571         -1,
   5572     },
   5573 #endif /* chips */
   5574 
   5575 #if defined(BCM_88680_A0)
   5576     { /* SOC_REG_INT_GE4_GBODE_CELL_CNT_BCM88680_A0r */
   5577         soc_block_list[2],
   5578         soc_genreg,
   5579         1,
   5580         0,
   5581         0x2021500,
   5582         SOC_REG_FLAG_RO,
   5583         0,
   5584         1,
   5585         soc_GE4_GBODE_CELL_CNT_BCM88680_A0r_fields,
   5586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5587         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5588         -1,
   5589         -1,
   5590     },
   5591 #endif /* chips */
   5592 
   5593 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   5594     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   5595     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNTr */
   5596         soc_block_list[2],
   5597         soc_genreg,
   5598         1,
   5599         0,
   5600         0x80020,
   5601         SOC_REG_FLAG_RO,
   5602         0,
   5603         1,
   5604         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   5605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5606         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5607         -1,
   5608         -1,
   5609     },
   5610 #endif /* chips */
   5611 
   5612 #if defined(BCM_53400_A0)
   5613     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM53400_A0r */
   5614         soc_block_list[9],
   5615         soc_genreg,
   5616         1,
   5617         0,
   5618         0x2021d00,
   5619         SOC_REG_FLAG_RO,
   5620         0,
   5621         1,
   5622         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   5623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5624         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5625         -1,
   5626         -1,
   5627     },
   5628 #endif /* chips */
   5629 
   5630 #if defined(BCM_53540_A0)
   5631     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM53540_A0r */
   5632         soc_block_list[2],
   5633         soc_genreg,
   5634         1,
   5635         0,
   5636         0x2021d00,
   5637         SOC_REG_FLAG_RO,
   5638         0,
   5639         1,
   5640         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   5641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5642         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5643         -1,
   5644         -1,
   5645     },
   5646 #endif /* chips */
   5647 
   5648 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5649     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM53570_A0r */
   5650         soc_block_list[2],
   5651         soc_genreg,
   5652         1,
   5653         0,
   5654         0x2022500,
   5655         SOC_REG_FLAG_RO,
   5656         0,
   5657         1,
   5658         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   5659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5661         -1,
   5662         -1,
   5663     },
   5664 #endif /* chips */
   5665 
   5666 #if defined(BCM_56150_A0)
   5667     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM56150_A0r */
   5668         soc_block_list[2],
   5669         soc_genreg,
   5670         1,
   5671         0,
   5672         0x2021d00,
   5673         SOC_REG_FLAG_RO,
   5674         0,
   5675         1,
   5676         soc_GE0_GBODE_CELL_REQ_CNT_BCM56150_A0r_fields,
   5677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5678         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5679         -1,
   5680         -1,
   5681     },
   5682 #endif /* chips */
   5683 
   5684 #if defined(BCM_56160_A0)
   5685     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM56160_A0r */
   5686         soc_block_list[2],
   5687         soc_genreg,
   5688         1,
   5689         0,
   5690         0x2021d00,
   5691         SOC_REG_FLAG_RO,
   5692         0,
   5693         1,
   5694         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   5695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5696         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5697         -1,
   5698         -1,
   5699     },
   5700 #endif /* chips */
   5701 
   5702 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   5703     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   5704     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   5705     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   5706     defined(BCM_56440_B0)
   5707     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   5708         soc_block_list[2],
   5709         soc_genreg,
   5710         1,
   5711         0,
   5712         0x80020,
   5713         SOC_REG_FLAG_RO,
   5714         0,
   5715         1,
   5716         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   5717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5718         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5719         -1,
   5720         -1,
   5721     },
   5722 #endif /* chips */
   5723 
   5724 #if defined(BCM_56370_A0)
   5725     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM56370_A0r */
   5726         soc_block_list[9],
   5727         soc_genreg,
   5728         1,
   5729         0,
   5730         0x2021d00,
   5731         SOC_REG_FLAG_RO,
   5732         0,
   5733         1,
   5734         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   5735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5736         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5737         -1,
   5738         -1,
   5739         3,
   5740     },
   5741 #endif /* chips */
   5742 
   5743 #if defined(BCM_88375_A0)
   5744     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM88375_A0r */
   5745         soc_block_list[2],
   5746         soc_genreg,
   5747         1,
   5748         0,
   5749         0x2021d00,
   5750         SOC_REG_FLAG_RO,
   5751         0,
   5752         1,
   5753         soc_GE4_GBODE_CELL_REQ_CNT_BCM88375_A0r_fields,
   5754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5755         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5756         -1,
   5757         -1,
   5758     },
   5759 #endif /* chips */
   5760 
   5761 #if defined(BCM_88375_B0)
   5762     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM88375_B0r */
   5763         soc_block_list[2],
   5764         soc_genreg,
   5765         1,
   5766         0,
   5767         0x2021d00,
   5768         SOC_REG_FLAG_RO,
   5769         0,
   5770         1,
   5771         soc_GE4_GBODE_CELL_REQ_CNT_BCM88375_B0r_fields,
   5772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5773         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5774         -1,
   5775         -1,
   5776     },
   5777 #endif /* chips */
   5778 
   5779 #if defined(BCM_88470_A0)
   5780     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM88470_A0r */
   5781         soc_block_list[2],
   5782         soc_genreg,
   5783         1,
   5784         0,
   5785         0x2021d00,
   5786         SOC_REG_FLAG_RO,
   5787         0,
   5788         1,
   5789         soc_GE4_GBODE_CELL_REQ_CNT_BCM88470_A0r_fields,
   5790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5791         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5792         -1,
   5793         -1,
   5794     },
   5795 #endif /* chips */
   5796 
   5797 #if defined(BCM_88470_B0)
   5798     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM88470_B0r */
   5799         soc_block_list[2],
   5800         soc_genreg,
   5801         1,
   5802         0,
   5803         0x2021d00,
   5804         SOC_REG_FLAG_RO,
   5805         0,
   5806         1,
   5807         soc_GE4_GBODE_CELL_REQ_CNT_BCM88470_B0r_fields,
   5808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5809         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5810         -1,
   5811         -1,
   5812     },
   5813 #endif /* chips */
   5814 
   5815 #if defined(BCM_88675_A0)
   5816     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM88675_A0r */
   5817         soc_block_list[2],
   5818         soc_genreg,
   5819         1,
   5820         0,
   5821         0x2021d00,
   5822         SOC_REG_FLAG_RO,
   5823         0,
   5824         1,
   5825         soc_GE4_GBODE_CELL_REQ_CNTr_fields,
   5826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5827         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5828         -1,
   5829         -1,
   5830     },
   5831 #endif /* chips */
   5832 
   5833 #if defined(BCM_88675_B0)
   5834     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM88675_B0r */
   5835         soc_block_list[2],
   5836         soc_genreg,
   5837         1,
   5838         0,
   5839         0x2021d00,
   5840         SOC_REG_FLAG_RO,
   5841         0,
   5842         1,
   5843         soc_GE4_GBODE_CELL_REQ_CNT_BCM88675_B0r_fields,
   5844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5845         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5846         -1,
   5847         -1,
   5848     },
   5849 #endif /* chips */
   5850 
   5851 #if defined(BCM_88680_A0)
   5852     { /* SOC_REG_INT_GE4_GBODE_CELL_REQ_CNT_BCM88680_A0r */
   5853         soc_block_list[2],
   5854         soc_genreg,
   5855         1,
   5856         0,
   5857         0x2021d00,
   5858         SOC_REG_FLAG_RO,
   5859         0,
   5860         1,
   5861         soc_GE4_GBODE_CELL_REQ_CNT_BCM88680_A0r_fields,
   5862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5863         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5864         -1,
   5865         -1,
   5866     },
   5867 #endif /* chips */
   5868 
   5869 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   5870     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   5871     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   5872     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   5873     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   5874     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
   5875     defined(BCM_56514_A0)
   5876     { /* SOC_REG_INT_GE4_GBOD_OVRFLWr */
   5877         soc_block_list[2],
   5878         soc_genreg,
   5879         1,
   5880         0,
   5881         0x80008,
   5882         SOC_REG_FLAG_RO,
   5883         0,
   5884         1,
   5885         soc_GE0_GBOD_OVRFLWr_fields,
   5886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5887         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5888         -1,
   5889         -1,
   5890     },
   5891 #endif /* chips */
   5892 
   5893 #if defined(BCM_53400_A0)
   5894     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM53400_A0r */
   5895         soc_block_list[9],
   5896         soc_genreg,
   5897         1,
   5898         0,
   5899         0x2020d00,
   5900         SOC_REG_FLAG_RO,
   5901         0,
   5902         1,
   5903         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   5904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5905         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5906         -1,
   5907         -1,
   5908     },
   5909 #endif /* chips */
   5910 
   5911 #if defined(BCM_53540_A0)
   5912     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM53540_A0r */
   5913         soc_block_list[2],
   5914         soc_genreg,
   5915         1,
   5916         0,
   5917         0x2020d00,
   5918         SOC_REG_FLAG_RO,
   5919         0,
   5920         1,
   5921         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   5922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5923         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5924         -1,
   5925         -1,
   5926     },
   5927 #endif /* chips */
   5928 
   5929 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5930     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM53570_A0r */
   5931         soc_block_list[2],
   5932         soc_genreg,
   5933         1,
   5934         0,
   5935         0x2021500,
   5936         SOC_REG_FLAG_RO,
   5937         0,
   5938         1,
   5939         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   5940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5941         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5942         -1,
   5943         -1,
   5944     },
   5945 #endif /* chips */
   5946 
   5947 #if defined(BCM_56150_A0)
   5948     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM56150_A0r */
   5949         soc_block_list[2],
   5950         soc_genreg,
   5951         1,
   5952         0,
   5953         0x2020d00,
   5954         SOC_REG_FLAG_RO,
   5955         0,
   5956         1,
   5957         soc_PORT_CDC_RXFIFO_OVRFLW_BCM56640_A0r_fields,
   5958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5959         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5960         -1,
   5961         -1,
   5962     },
   5963 #endif /* chips */
   5964 
   5965 #if defined(BCM_56160_A0)
   5966     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM56160_A0r */
   5967         soc_block_list[2],
   5968         soc_genreg,
   5969         1,
   5970         0,
   5971         0x2020d00,
   5972         SOC_REG_FLAG_RO,
   5973         0,
   5974         1,
   5975         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   5976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5977         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5978         -1,
   5979         -1,
   5980     },
   5981 #endif /* chips */
   5982 
   5983 #if defined(BCM_56370_A0)
   5984     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM56370_A0r */
   5985         soc_block_list[9],
   5986         soc_genreg,
   5987         1,
   5988         0,
   5989         0x2020d00,
   5990         SOC_REG_FLAG_RO,
   5991         0,
   5992         1,
   5993         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   5994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5995         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5996         -1,
   5997         -1,
   5998         3,
   5999     },
   6000 #endif /* chips */
   6001 
   6002 #if defined(BCM_88375_A0)
   6003     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM88375_A0r */
   6004         soc_block_list[2],
   6005         soc_genreg,
   6006         1,
   6007         0,
   6008         0x2020d00,
   6009         SOC_REG_FLAG_RO,
   6010         0,
   6011         1,
   6012         soc_GE4_GBOD_OVRFLW_BCM88375_A0r_fields,
   6013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6014         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6015         -1,
   6016         -1,
   6017     },
   6018 #endif /* chips */
   6019 
   6020 #if defined(BCM_88375_B0)
   6021     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM88375_B0r */
   6022         soc_block_list[2],
   6023         soc_genreg,
   6024         1,
   6025         0,
   6026         0x2020d00,
   6027         SOC_REG_FLAG_RO,
   6028         0,
   6029         1,
   6030         soc_GE4_GBOD_OVRFLW_BCM88375_B0r_fields,
   6031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6032         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6033         -1,
   6034         -1,
   6035     },
   6036 #endif /* chips */
   6037 
   6038 #if defined(BCM_88470_A0)
   6039     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM88470_A0r */
   6040         soc_block_list[2],
   6041         soc_genreg,
   6042         1,
   6043         0,
   6044         0x2020d00,
   6045         SOC_REG_FLAG_RO,
   6046         0,
   6047         1,
   6048         soc_GE4_GBOD_OVRFLW_BCM88470_A0r_fields,
   6049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6050         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6051         -1,
   6052         -1,
   6053     },
   6054 #endif /* chips */
   6055 
   6056 #if defined(BCM_88470_B0)
   6057     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM88470_B0r */
   6058         soc_block_list[2],
   6059         soc_genreg,
   6060         1,
   6061         0,
   6062         0x2020d00,
   6063         SOC_REG_FLAG_RO,
   6064         0,
   6065         1,
   6066         soc_GE4_GBOD_OVRFLW_BCM88470_B0r_fields,
   6067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6068         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6069         -1,
   6070         -1,
   6071     },
   6072 #endif /* chips */
   6073 
   6074 #if defined(BCM_88675_A0)
   6075     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM88675_A0r */
   6076         soc_block_list[2],
   6077         soc_genreg,
   6078         1,
   6079         0,
   6080         0x2020d00,
   6081         SOC_REG_FLAG_RO,
   6082         0,
   6083         1,
   6084         soc_GE4_GBOD_OVRFLWr_fields,
   6085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6086         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6087         -1,
   6088         -1,
   6089     },
   6090 #endif /* chips */
   6091 
   6092 #if defined(BCM_88675_B0)
   6093     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM88675_B0r */
   6094         soc_block_list[2],
   6095         soc_genreg,
   6096         1,
   6097         0,
   6098         0x2020d00,
   6099         SOC_REG_FLAG_RO,
   6100         0,
   6101         1,
   6102         soc_GE4_GBOD_OVRFLW_BCM88675_B0r_fields,
   6103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6104         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6105         -1,
   6106         -1,
   6107     },
   6108 #endif /* chips */
   6109 
   6110 #if defined(BCM_88680_A0)
   6111     { /* SOC_REG_INT_GE4_GBOD_OVRFLW_BCM88680_A0r */
   6112         soc_block_list[2],
   6113         soc_genreg,
   6114         1,
   6115         0,
   6116         0x2020d00,
   6117         SOC_REG_FLAG_RO,
   6118         0,
   6119         1,
   6120         soc_GE4_GBOD_OVRFLW_BCM88680_A0r_fields,
   6121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6122         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6123         -1,
   6124         -1,
   6125     },
   6126 #endif /* chips */
   6127 
   6128 #if defined(BCM_53570_A0)
   6129     { /* SOC_REG_INT_GE4_MIN_FRAG_SIZEr */
   6130         soc_block_list[2],
   6131         soc_genreg,
   6132         1,
   6133         0,
   6134         0x2020d00,
   6135         0,
   6136         0,
   6137         2,
   6138         soc_GE0_MIN_FRAG_SIZEr_fields,
   6139         SOC_RESET_VAL_DEC(0x00000387, 0x00000000)
   6140         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6141         -1,
   6142         -1,
   6143     },
   6144 #endif /* chips */
   6145 
   6146 #if defined(BCM_53570_B0)
   6147     { /* SOC_REG_INT_GE4_MIN_FRAG_SIZE_BCM53570_B0r */
   6148         soc_block_list[2],
   6149         soc_genreg,
   6150         1,
   6151         0,
   6152         0x2020d00,
   6153         0,
   6154         0,
   6155         2,
   6156         soc_GE0_MIN_FRAG_SIZE_BCM53570_B0r_fields,
   6157         SOC_RESET_VAL_DEC(0x00000408, 0x00000000)
   6158         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6159         -1,
   6160         -1,
   6161     },
   6162 #endif /* chips */
   6163 
   6164 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6165     { /* SOC_REG_INT_GE4_S3MII_SPEED_DEBUGr */
   6166         soc_block_list[2],
   6167         soc_genreg,
   6168         1,
   6169         0,
   6170         0x8003f,
   6171         SOC_REG_FLAG_RO,
   6172         0,
   6173         4,
   6174         soc_GE0_S3MII_SPEED_DEBUGr_fields,
   6175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6177         -1,
   6178         -1,
   6179     },
   6180 #endif /* chips */
   6181 
   6182 #if defined(BCM_53324_A0)
   6183     { /* SOC_REG_INT_GE5_EEE_CONFIGr */
   6184         soc_block_list[2],
   6185         soc_genreg,
   6186         1,
   6187         0,
   6188         0x8003b,
   6189         0,
   6190         0,
   6191         4,
   6192         soc_GE0_EEE_CONFIGr_fields,
   6193         SOC_RESET_VAL_DEC(0x000014e1, 0x00000000)
   6194         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6195         -1,
   6196         -1,
   6197     },
   6198 #endif /* chips */
   6199 
   6200 #if defined(BCM_53400_A0)
   6201     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM53400_A0r */
   6202         soc_block_list[9],
   6203         soc_genreg,
   6204         1,
   6205         0,
   6206         0x2022900,
   6207         0,
   6208         0,
   6209         3,
   6210         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   6211         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6212         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6213         -1,
   6214         -1,
   6215     },
   6216 #endif /* chips */
   6217 
   6218 #if defined(BCM_53540_A0)
   6219     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM53540_A0r */
   6220         soc_block_list[2],
   6221         soc_genreg,
   6222         1,
   6223         0,
   6224         0x2022900,
   6225         0,
   6226         0,
   6227         3,
   6228         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   6229         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6230         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6231         -1,
   6232         -1,
   6233     },
   6234 #endif /* chips */
   6235 
   6236 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6237     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM53570_A0r */
   6238         soc_block_list[2],
   6239         soc_genreg,
   6240         1,
   6241         0,
   6242         0x2023400,
   6243         0,
   6244         0,
   6245         3,
   6246         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   6247         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6248         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6249         -1,
   6250         -1,
   6251     },
   6252 #endif /* chips */
   6253 
   6254 #if defined(BCM_56150_A0)
   6255     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM56150_A0r */
   6256         soc_block_list[2],
   6257         soc_genreg,
   6258         1,
   6259         0,
   6260         0x2022900,
   6261         0,
   6262         0,
   6263         3,
   6264         soc_GE0_EEE_CONFIG_BCM56150_A0r_fields,
   6265         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6266         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6267         -1,
   6268         -1,
   6269     },
   6270 #endif /* chips */
   6271 
   6272 #if defined(BCM_56160_A0)
   6273     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM56160_A0r */
   6274         soc_block_list[2],
   6275         soc_genreg,
   6276         1,
   6277         0,
   6278         0x2022900,
   6279         0,
   6280         0,
   6281         3,
   6282         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   6283         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6284         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6285         -1,
   6286         -1,
   6287     },
   6288 #endif /* chips */
   6289 
   6290 #if defined(BCM_56370_A0)
   6291     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM56370_A0r */
   6292         soc_block_list[9],
   6293         soc_genreg,
   6294         1,
   6295         0,
   6296         0x2022900,
   6297         0,
   6298         0,
   6299         3,
   6300         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   6301         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6302         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6303         -1,
   6304         -1,
   6305         3,
   6306     },
   6307 #endif /* chips */
   6308 
   6309 #if defined(BCM_56142_A0) || defined(BCM_56440_A0) || \
   6310     defined(BCM_56440_B0)
   6311     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM56440_A0r */
   6312         soc_block_list[2],
   6313         soc_genreg,
   6314         1,
   6315         0,
   6316         0x80038,
   6317         0,
   6318         0,
   6319         4,
   6320         soc_GE0_EEE_CONFIG_BCM56440_A0r_fields,
   6321         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6322         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6323         -1,
   6324         -1,
   6325     },
   6326 #endif /* chips */
   6327 
   6328 #if defined(BCM_88375_A0)
   6329     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM88375_A0r */
   6330         soc_block_list[2],
   6331         soc_genreg,
   6332         1,
   6333         0,
   6334         0x2022900,
   6335         0,
   6336         0,
   6337         3,
   6338         soc_GE5_EEE_CONFIG_BCM88375_A0r_fields,
   6339         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6340         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6341         -1,
   6342         -1,
   6343     },
   6344 #endif /* chips */
   6345 
   6346 #if defined(BCM_88375_B0)
   6347     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM88375_B0r */
   6348         soc_block_list[2],
   6349         soc_genreg,
   6350         1,
   6351         0,
   6352         0x2022900,
   6353         0,
   6354         0,
   6355         3,
   6356         soc_GE5_EEE_CONFIG_BCM88375_B0r_fields,
   6357         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6358         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6359         -1,
   6360         -1,
   6361     },
   6362 #endif /* chips */
   6363 
   6364 #if defined(BCM_88470_A0)
   6365     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM88470_A0r */
   6366         soc_block_list[2],
   6367         soc_genreg,
   6368         1,
   6369         0,
   6370         0x2022900,
   6371         0,
   6372         0,
   6373         3,
   6374         soc_GE5_EEE_CONFIG_BCM88470_A0r_fields,
   6375         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6376         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6377         -1,
   6378         -1,
   6379     },
   6380 #endif /* chips */
   6381 
   6382 #if defined(BCM_88470_B0)
   6383     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM88470_B0r */
   6384         soc_block_list[2],
   6385         soc_genreg,
   6386         1,
   6387         0,
   6388         0x2022900,
   6389         0,
   6390         0,
   6391         3,
   6392         soc_GE5_EEE_CONFIG_BCM88470_B0r_fields,
   6393         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6394         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6395         -1,
   6396         -1,
   6397     },
   6398 #endif /* chips */
   6399 
   6400 #if defined(BCM_88675_A0)
   6401     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM88675_A0r */
   6402         soc_block_list[2],
   6403         soc_genreg,
   6404         1,
   6405         0,
   6406         0x2022900,
   6407         0,
   6408         0,
   6409         3,
   6410         soc_GE5_EEE_CONFIGr_fields,
   6411         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6412         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6413         -1,
   6414         -1,
   6415     },
   6416 #endif /* chips */
   6417 
   6418 #if defined(BCM_88675_B0)
   6419     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM88675_B0r */
   6420         soc_block_list[2],
   6421         soc_genreg,
   6422         1,
   6423         0,
   6424         0x2022900,
   6425         0,
   6426         0,
   6427         3,
   6428         soc_GE5_EEE_CONFIG_BCM88675_B0r_fields,
   6429         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6430         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6431         -1,
   6432         -1,
   6433     },
   6434 #endif /* chips */
   6435 
   6436 #if defined(BCM_88680_A0)
   6437     { /* SOC_REG_INT_GE5_EEE_CONFIG_BCM88680_A0r */
   6438         soc_block_list[2],
   6439         soc_genreg,
   6440         1,
   6441         0,
   6442         0x2022900,
   6443         0,
   6444         0,
   6445         3,
   6446         soc_GE5_EEE_CONFIG_BCM88680_A0r_fields,
   6447         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   6448         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6449         -1,
   6450         -1,
   6451     },
   6452 #endif /* chips */
   6453 
   6454 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   6455     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   6456     { /* SOC_REG_INT_GE5_GBODE_CELL_CNTr */
   6457         soc_block_list[2],
   6458         soc_genreg,
   6459         1,
   6460         0,
   6461         0x80015,
   6462         SOC_REG_FLAG_RO,
   6463         0,
   6464         1,
   6465         soc_GE0_GBODE_CELL_CNTr_fields,
   6466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6467         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6468         -1,
   6469         -1,
   6470     },
   6471 #endif /* chips */
   6472 
   6473 #if defined(BCM_53400_A0)
   6474     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM53400_A0r */
   6475         soc_block_list[9],
   6476         soc_genreg,
   6477         1,
   6478         0,
   6479         0x2021600,
   6480         SOC_REG_FLAG_RO,
   6481         0,
   6482         1,
   6483         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   6484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6486         -1,
   6487         -1,
   6488     },
   6489 #endif /* chips */
   6490 
   6491 #if defined(BCM_53540_A0)
   6492     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM53540_A0r */
   6493         soc_block_list[2],
   6494         soc_genreg,
   6495         1,
   6496         0,
   6497         0x2021600,
   6498         SOC_REG_FLAG_RO,
   6499         0,
   6500         1,
   6501         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   6502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6503         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6504         -1,
   6505         -1,
   6506     },
   6507 #endif /* chips */
   6508 
   6509 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6510     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM53570_A0r */
   6511         soc_block_list[2],
   6512         soc_genreg,
   6513         1,
   6514         0,
   6515         0x2021e00,
   6516         SOC_REG_FLAG_RO,
   6517         0,
   6518         1,
   6519         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   6520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6522         -1,
   6523         -1,
   6524     },
   6525 #endif /* chips */
   6526 
   6527 #if defined(BCM_56150_A0)
   6528     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM56150_A0r */
   6529         soc_block_list[2],
   6530         soc_genreg,
   6531         1,
   6532         0,
   6533         0x2021600,
   6534         SOC_REG_FLAG_RO,
   6535         0,
   6536         1,
   6537         soc_GE0_GBODE_CELL_CNT_BCM56150_A0r_fields,
   6538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6540         -1,
   6541         -1,
   6542     },
   6543 #endif /* chips */
   6544 
   6545 #if defined(BCM_56160_A0)
   6546     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM56160_A0r */
   6547         soc_block_list[2],
   6548         soc_genreg,
   6549         1,
   6550         0,
   6551         0x2021600,
   6552         SOC_REG_FLAG_RO,
   6553         0,
   6554         1,
   6555         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   6556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6558         -1,
   6559         -1,
   6560     },
   6561 #endif /* chips */
   6562 
   6563 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   6564     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   6565     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   6566     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   6567     defined(BCM_56440_B0)
   6568     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM56224_A0r */
   6569         soc_block_list[2],
   6570         soc_genreg,
   6571         1,
   6572         0,
   6573         0x80015,
   6574         SOC_REG_FLAG_RO,
   6575         0,
   6576         1,
   6577         soc_GE_GBODE_CELL_CNTr_fields,
   6578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6580         -1,
   6581         -1,
   6582     },
   6583 #endif /* chips */
   6584 
   6585 #if defined(BCM_56370_A0)
   6586     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM56370_A0r */
   6587         soc_block_list[9],
   6588         soc_genreg,
   6589         1,
   6590         0,
   6591         0x2021600,
   6592         SOC_REG_FLAG_RO,
   6593         0,
   6594         1,
   6595         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   6596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6598         -1,
   6599         -1,
   6600         3,
   6601     },
   6602 #endif /* chips */
   6603 
   6604 #if defined(BCM_88375_A0)
   6605     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM88375_A0r */
   6606         soc_block_list[2],
   6607         soc_genreg,
   6608         1,
   6609         0,
   6610         0x2021600,
   6611         SOC_REG_FLAG_RO,
   6612         0,
   6613         1,
   6614         soc_GE5_GBODE_CELL_CNT_BCM88375_A0r_fields,
   6615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6616         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6617         -1,
   6618         -1,
   6619     },
   6620 #endif /* chips */
   6621 
   6622 #if defined(BCM_88375_B0)
   6623     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM88375_B0r */
   6624         soc_block_list[2],
   6625         soc_genreg,
   6626         1,
   6627         0,
   6628         0x2021600,
   6629         SOC_REG_FLAG_RO,
   6630         0,
   6631         1,
   6632         soc_GE5_GBODE_CELL_CNT_BCM88375_B0r_fields,
   6633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6634         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6635         -1,
   6636         -1,
   6637     },
   6638 #endif /* chips */
   6639 
   6640 #if defined(BCM_88470_A0)
   6641     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM88470_A0r */
   6642         soc_block_list[2],
   6643         soc_genreg,
   6644         1,
   6645         0,
   6646         0x2021600,
   6647         SOC_REG_FLAG_RO,
   6648         0,
   6649         1,
   6650         soc_GE5_GBODE_CELL_CNT_BCM88470_A0r_fields,
   6651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6652         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6653         -1,
   6654         -1,
   6655     },
   6656 #endif /* chips */
   6657 
   6658 #if defined(BCM_88470_B0)
   6659     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM88470_B0r */
   6660         soc_block_list[2],
   6661         soc_genreg,
   6662         1,
   6663         0,
   6664         0x2021600,
   6665         SOC_REG_FLAG_RO,
   6666         0,
   6667         1,
   6668         soc_GE5_GBODE_CELL_CNT_BCM88470_B0r_fields,
   6669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6670         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6671         -1,
   6672         -1,
   6673     },
   6674 #endif /* chips */
   6675 
   6676 #if defined(BCM_88675_A0)
   6677     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM88675_A0r */
   6678         soc_block_list[2],
   6679         soc_genreg,
   6680         1,
   6681         0,
   6682         0x2021600,
   6683         SOC_REG_FLAG_RO,
   6684         0,
   6685         1,
   6686         soc_GE5_GBODE_CELL_CNTr_fields,
   6687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6688         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6689         -1,
   6690         -1,
   6691     },
   6692 #endif /* chips */
   6693 
   6694 #if defined(BCM_88675_B0)
   6695     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM88675_B0r */
   6696         soc_block_list[2],
   6697         soc_genreg,
   6698         1,
   6699         0,
   6700         0x2021600,
   6701         SOC_REG_FLAG_RO,
   6702         0,
   6703         1,
   6704         soc_GE5_GBODE_CELL_CNT_BCM88675_B0r_fields,
   6705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6706         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6707         -1,
   6708         -1,
   6709     },
   6710 #endif /* chips */
   6711 
   6712 #if defined(BCM_88680_A0)
   6713     { /* SOC_REG_INT_GE5_GBODE_CELL_CNT_BCM88680_A0r */
   6714         soc_block_list[2],
   6715         soc_genreg,
   6716         1,
   6717         0,
   6718         0x2021600,
   6719         SOC_REG_FLAG_RO,
   6720         0,
   6721         1,
   6722         soc_GE5_GBODE_CELL_CNT_BCM88680_A0r_fields,
   6723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6724         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6725         -1,
   6726         -1,
   6727     },
   6728 #endif /* chips */
   6729 
   6730 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   6731     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   6732     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNTr */
   6733         soc_block_list[2],
   6734         soc_genreg,
   6735         1,
   6736         0,
   6737         0x80021,
   6738         SOC_REG_FLAG_RO,
   6739         0,
   6740         1,
   6741         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   6742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6743         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6744         -1,
   6745         -1,
   6746     },
   6747 #endif /* chips */
   6748 
   6749 #if defined(BCM_53400_A0)
   6750     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM53400_A0r */
   6751         soc_block_list[9],
   6752         soc_genreg,
   6753         1,
   6754         0,
   6755         0x2021e00,
   6756         SOC_REG_FLAG_RO,
   6757         0,
   6758         1,
   6759         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   6760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6762         -1,
   6763         -1,
   6764     },
   6765 #endif /* chips */
   6766 
   6767 #if defined(BCM_53540_A0)
   6768     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM53540_A0r */
   6769         soc_block_list[2],
   6770         soc_genreg,
   6771         1,
   6772         0,
   6773         0x2021e00,
   6774         SOC_REG_FLAG_RO,
   6775         0,
   6776         1,
   6777         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   6778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6779         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6780         -1,
   6781         -1,
   6782     },
   6783 #endif /* chips */
   6784 
   6785 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6786     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM53570_A0r */
   6787         soc_block_list[2],
   6788         soc_genreg,
   6789         1,
   6790         0,
   6791         0x2022600,
   6792         SOC_REG_FLAG_RO,
   6793         0,
   6794         1,
   6795         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   6796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6797         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6798         -1,
   6799         -1,
   6800     },
   6801 #endif /* chips */
   6802 
   6803 #if defined(BCM_56150_A0)
   6804     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM56150_A0r */
   6805         soc_block_list[2],
   6806         soc_genreg,
   6807         1,
   6808         0,
   6809         0x2021e00,
   6810         SOC_REG_FLAG_RO,
   6811         0,
   6812         1,
   6813         soc_GE0_GBODE_CELL_REQ_CNT_BCM56150_A0r_fields,
   6814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6815         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6816         -1,
   6817         -1,
   6818     },
   6819 #endif /* chips */
   6820 
   6821 #if defined(BCM_56160_A0)
   6822     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM56160_A0r */
   6823         soc_block_list[2],
   6824         soc_genreg,
   6825         1,
   6826         0,
   6827         0x2021e00,
   6828         SOC_REG_FLAG_RO,
   6829         0,
   6830         1,
   6831         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   6832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6833         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6834         -1,
   6835         -1,
   6836     },
   6837 #endif /* chips */
   6838 
   6839 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   6840     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   6841     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   6842     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   6843     defined(BCM_56440_B0)
   6844     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   6845         soc_block_list[2],
   6846         soc_genreg,
   6847         1,
   6848         0,
   6849         0x80021,
   6850         SOC_REG_FLAG_RO,
   6851         0,
   6852         1,
   6853         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   6854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6855         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6856         -1,
   6857         -1,
   6858     },
   6859 #endif /* chips */
   6860 
   6861 #if defined(BCM_56370_A0)
   6862     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM56370_A0r */
   6863         soc_block_list[9],
   6864         soc_genreg,
   6865         1,
   6866         0,
   6867         0x2021e00,
   6868         SOC_REG_FLAG_RO,
   6869         0,
   6870         1,
   6871         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   6872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6874         -1,
   6875         -1,
   6876         3,
   6877     },
   6878 #endif /* chips */
   6879 
   6880 #if defined(BCM_88375_A0)
   6881     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM88375_A0r */
   6882         soc_block_list[2],
   6883         soc_genreg,
   6884         1,
   6885         0,
   6886         0x2021e00,
   6887         SOC_REG_FLAG_RO,
   6888         0,
   6889         1,
   6890         soc_GE5_GBODE_CELL_REQ_CNT_BCM88375_A0r_fields,
   6891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6892         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6893         -1,
   6894         -1,
   6895     },
   6896 #endif /* chips */
   6897 
   6898 #if defined(BCM_88375_B0)
   6899     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM88375_B0r */
   6900         soc_block_list[2],
   6901         soc_genreg,
   6902         1,
   6903         0,
   6904         0x2021e00,
   6905         SOC_REG_FLAG_RO,
   6906         0,
   6907         1,
   6908         soc_GE5_GBODE_CELL_REQ_CNT_BCM88375_B0r_fields,
   6909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6910         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6911         -1,
   6912         -1,
   6913     },
   6914 #endif /* chips */
   6915 
   6916 #if defined(BCM_88470_A0)
   6917     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM88470_A0r */
   6918         soc_block_list[2],
   6919         soc_genreg,
   6920         1,
   6921         0,
   6922         0x2021e00,
   6923         SOC_REG_FLAG_RO,
   6924         0,
   6925         1,
   6926         soc_GE5_GBODE_CELL_REQ_CNT_BCM88470_A0r_fields,
   6927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6928         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6929         -1,
   6930         -1,
   6931     },
   6932 #endif /* chips */
   6933 
   6934 #if defined(BCM_88470_B0)
   6935     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM88470_B0r */
   6936         soc_block_list[2],
   6937         soc_genreg,
   6938         1,
   6939         0,
   6940         0x2021e00,
   6941         SOC_REG_FLAG_RO,
   6942         0,
   6943         1,
   6944         soc_GE5_GBODE_CELL_REQ_CNT_BCM88470_B0r_fields,
   6945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6946         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6947         -1,
   6948         -1,
   6949     },
   6950 #endif /* chips */
   6951 
   6952 #if defined(BCM_88675_A0)
   6953     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM88675_A0r */
   6954         soc_block_list[2],
   6955         soc_genreg,
   6956         1,
   6957         0,
   6958         0x2021e00,
   6959         SOC_REG_FLAG_RO,
   6960         0,
   6961         1,
   6962         soc_GE5_GBODE_CELL_REQ_CNTr_fields,
   6963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6964         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6965         -1,
   6966         -1,
   6967     },
   6968 #endif /* chips */
   6969 
   6970 #if defined(BCM_88675_B0)
   6971     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM88675_B0r */
   6972         soc_block_list[2],
   6973         soc_genreg,
   6974         1,
   6975         0,
   6976         0x2021e00,
   6977         SOC_REG_FLAG_RO,
   6978         0,
   6979         1,
   6980         soc_GE5_GBODE_CELL_REQ_CNT_BCM88675_B0r_fields,
   6981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6982         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6983         -1,
   6984         -1,
   6985     },
   6986 #endif /* chips */
   6987 
   6988 #if defined(BCM_88680_A0)
   6989     { /* SOC_REG_INT_GE5_GBODE_CELL_REQ_CNT_BCM88680_A0r */
   6990         soc_block_list[2],
   6991         soc_genreg,
   6992         1,
   6993         0,
   6994         0x2021e00,
   6995         SOC_REG_FLAG_RO,
   6996         0,
   6997         1,
   6998         soc_GE5_GBODE_CELL_REQ_CNT_BCM88680_A0r_fields,
   6999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7000         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7001         -1,
   7002         -1,
   7003     },
   7004 #endif /* chips */
   7005 
   7006 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   7007     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   7008     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   7009     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   7010     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   7011     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
   7012     defined(BCM_56514_A0)
   7013     { /* SOC_REG_INT_GE5_GBOD_OVRFLWr */
   7014         soc_block_list[2],
   7015         soc_genreg,
   7016         1,
   7017         0,
   7018         0x80009,
   7019         SOC_REG_FLAG_RO,
   7020         0,
   7021         1,
   7022         soc_GE0_GBOD_OVRFLWr_fields,
   7023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7024         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7025         -1,
   7026         -1,
   7027     },
   7028 #endif /* chips */
   7029 
   7030 #if defined(BCM_53400_A0)
   7031     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM53400_A0r */
   7032         soc_block_list[9],
   7033         soc_genreg,
   7034         1,
   7035         0,
   7036         0x2020e00,
   7037         SOC_REG_FLAG_RO,
   7038         0,
   7039         1,
   7040         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   7041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7042         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7043         -1,
   7044         -1,
   7045     },
   7046 #endif /* chips */
   7047 
   7048 #if defined(BCM_53540_A0)
   7049     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM53540_A0r */
   7050         soc_block_list[2],
   7051         soc_genreg,
   7052         1,
   7053         0,
   7054         0x2020e00,
   7055         SOC_REG_FLAG_RO,
   7056         0,
   7057         1,
   7058         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   7059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7060         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7061         -1,
   7062         -1,
   7063     },
   7064 #endif /* chips */
   7065 
   7066 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   7067     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM53570_A0r */
   7068         soc_block_list[2],
   7069         soc_genreg,
   7070         1,
   7071         0,
   7072         0x2021600,
   7073         SOC_REG_FLAG_RO,
   7074         0,
   7075         1,
   7076         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   7077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7078         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7079         -1,
   7080         -1,
   7081     },
   7082 #endif /* chips */
   7083 
   7084 #if defined(BCM_56150_A0)
   7085     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM56150_A0r */
   7086         soc_block_list[2],
   7087         soc_genreg,
   7088         1,
   7089         0,
   7090         0x2020e00,
   7091         SOC_REG_FLAG_RO,
   7092         0,
   7093         1,
   7094         soc_PORT_CDC_RXFIFO_OVRFLW_BCM56640_A0r_fields,
   7095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7096         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7097         -1,
   7098         -1,
   7099     },
   7100 #endif /* chips */
   7101 
   7102 #if defined(BCM_56160_A0)
   7103     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM56160_A0r */
   7104         soc_block_list[2],
   7105         soc_genreg,
   7106         1,
   7107         0,
   7108         0x2020e00,
   7109         SOC_REG_FLAG_RO,
   7110         0,
   7111         1,
   7112         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   7113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7114         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7115         -1,
   7116         -1,
   7117     },
   7118 #endif /* chips */
   7119 
   7120 #if defined(BCM_56370_A0)
   7121     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM56370_A0r */
   7122         soc_block_list[9],
   7123         soc_genreg,
   7124         1,
   7125         0,
   7126         0x2020e00,
   7127         SOC_REG_FLAG_RO,
   7128         0,
   7129         1,
   7130         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   7131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7132         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7133         -1,
   7134         -1,
   7135         3,
   7136     },
   7137 #endif /* chips */
   7138 
   7139 #if defined(BCM_88375_A0)
   7140     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM88375_A0r */
   7141         soc_block_list[2],
   7142         soc_genreg,
   7143         1,
   7144         0,
   7145         0x2020e00,
   7146         SOC_REG_FLAG_RO,
   7147         0,
   7148         1,
   7149         soc_GE5_GBOD_OVRFLW_BCM88375_A0r_fields,
   7150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7151         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7152         -1,
   7153         -1,
   7154     },
   7155 #endif /* chips */
   7156 
   7157 #if defined(BCM_88375_B0)
   7158     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM88375_B0r */
   7159         soc_block_list[2],
   7160         soc_genreg,
   7161         1,
   7162         0,
   7163         0x2020e00,
   7164         SOC_REG_FLAG_RO,
   7165         0,
   7166         1,
   7167         soc_GE5_GBOD_OVRFLW_BCM88375_B0r_fields,
   7168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7169         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7170         -1,
   7171         -1,
   7172     },
   7173 #endif /* chips */
   7174 
   7175 #if defined(BCM_88470_A0)
   7176     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM88470_A0r */
   7177         soc_block_list[2],
   7178         soc_genreg,
   7179         1,
   7180         0,
   7181         0x2020e00,
   7182         SOC_REG_FLAG_RO,
   7183         0,
   7184         1,
   7185         soc_GE5_GBOD_OVRFLW_BCM88470_A0r_fields,
   7186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7187         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7188         -1,
   7189         -1,
   7190     },
   7191 #endif /* chips */
   7192 
   7193 #if defined(BCM_88470_B0)
   7194     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM88470_B0r */
   7195         soc_block_list[2],
   7196         soc_genreg,
   7197         1,
   7198         0,
   7199         0x2020e00,
   7200         SOC_REG_FLAG_RO,
   7201         0,
   7202         1,
   7203         soc_GE5_GBOD_OVRFLW_BCM88470_B0r_fields,
   7204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7205         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7206         -1,
   7207         -1,
   7208     },
   7209 #endif /* chips */
   7210 
   7211 #if defined(BCM_88675_A0)
   7212     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM88675_A0r */
   7213         soc_block_list[2],
   7214         soc_genreg,
   7215         1,
   7216         0,
   7217         0x2020e00,
   7218         SOC_REG_FLAG_RO,
   7219         0,
   7220         1,
   7221         soc_GE5_GBOD_OVRFLWr_fields,
   7222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7223         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7224         -1,
   7225         -1,
   7226     },
   7227 #endif /* chips */
   7228 
   7229 #if defined(BCM_88675_B0)
   7230     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM88675_B0r */
   7231         soc_block_list[2],
   7232         soc_genreg,
   7233         1,
   7234         0,
   7235         0x2020e00,
   7236         SOC_REG_FLAG_RO,
   7237         0,
   7238         1,
   7239         soc_GE5_GBOD_OVRFLW_BCM88675_B0r_fields,
   7240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7241         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7242         -1,
   7243         -1,
   7244     },
   7245 #endif /* chips */
   7246 
   7247 #if defined(BCM_88680_A0)
   7248     { /* SOC_REG_INT_GE5_GBOD_OVRFLW_BCM88680_A0r */
   7249         soc_block_list[2],
   7250         soc_genreg,
   7251         1,
   7252         0,
   7253         0x2020e00,
   7254         SOC_REG_FLAG_RO,
   7255         0,
   7256         1,
   7257         soc_GE5_GBOD_OVRFLW_BCM88680_A0r_fields,
   7258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7259         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7260         -1,
   7261         -1,
   7262     },
   7263 #endif /* chips */
   7264 
   7265 #if defined(BCM_53570_A0)
   7266     { /* SOC_REG_INT_GE5_MIN_FRAG_SIZEr */
   7267         soc_block_list[2],
   7268         soc_genreg,
   7269         1,
   7270         0,
   7271         0x2020e00,
   7272         0,
   7273         0,
   7274         2,
   7275         soc_GE0_MIN_FRAG_SIZEr_fields,
   7276         SOC_RESET_VAL_DEC(0x00000387, 0x00000000)
   7277         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   7278         -1,
   7279         -1,
   7280     },
   7281 #endif /* chips */
   7282 
   7283 #if defined(BCM_53570_B0)
   7284     { /* SOC_REG_INT_GE5_MIN_FRAG_SIZE_BCM53570_B0r */
   7285         soc_block_list[2],
   7286         soc_genreg,
   7287         1,
   7288         0,
   7289         0x2020e00,
   7290         0,
   7291         0,
   7292         2,
   7293         soc_GE0_MIN_FRAG_SIZE_BCM53570_B0r_fields,
   7294         SOC_RESET_VAL_DEC(0x00000408, 0x00000000)
   7295         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   7296         -1,
   7297         -1,
   7298     },
   7299 #endif /* chips */
   7300 
   7301 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7302     { /* SOC_REG_INT_GE5_S3MII_SPEED_DEBUGr */
   7303         soc_block_list[2],
   7304         soc_genreg,
   7305         1,
   7306         0,
   7307         0x80040,
   7308         SOC_REG_FLAG_RO,
   7309         0,
   7310         4,
   7311         soc_GE0_S3MII_SPEED_DEBUGr_fields,
   7312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7313         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7314         -1,
   7315         -1,
   7316     },
   7317 #endif /* chips */
   7318 
   7319 #if defined(BCM_53324_A0)
   7320     { /* SOC_REG_INT_GE6_EEE_CONFIGr */
   7321         soc_block_list[2],
   7322         soc_genreg,
   7323         1,
   7324         0,
   7325         0x8003c,
   7326         0,
   7327         0,
   7328         4,
   7329         soc_GE0_EEE_CONFIGr_fields,
   7330         SOC_RESET_VAL_DEC(0x000014e1, 0x00000000)
   7331         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7332         -1,
   7333         -1,
   7334     },
   7335 #endif /* chips */
   7336 
   7337 #if defined(BCM_53400_A0)
   7338     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM53400_A0r */
   7339         soc_block_list[9],
   7340         soc_genreg,
   7341         1,
   7342         0,
   7343         0x2022a00,
   7344         0,
   7345         0,
   7346         3,
   7347         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   7348         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7349         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7350         -1,
   7351         -1,
   7352     },
   7353 #endif /* chips */
   7354 
   7355 #if defined(BCM_53540_A0)
   7356     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM53540_A0r */
   7357         soc_block_list[2],
   7358         soc_genreg,
   7359         1,
   7360         0,
   7361         0x2022a00,
   7362         0,
   7363         0,
   7364         3,
   7365         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   7366         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7367         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7368         -1,
   7369         -1,
   7370     },
   7371 #endif /* chips */
   7372 
   7373 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   7374     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM53570_A0r */
   7375         soc_block_list[2],
   7376         soc_genreg,
   7377         1,
   7378         0,
   7379         0x2023500,
   7380         0,
   7381         0,
   7382         3,
   7383         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   7384         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7385         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7386         -1,
   7387         -1,
   7388     },
   7389 #endif /* chips */
   7390 
   7391 #if defined(BCM_56150_A0)
   7392     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM56150_A0r */
   7393         soc_block_list[2],
   7394         soc_genreg,
   7395         1,
   7396         0,
   7397         0x2022a00,
   7398         0,
   7399         0,
   7400         3,
   7401         soc_GE0_EEE_CONFIG_BCM56150_A0r_fields,
   7402         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7403         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7404         -1,
   7405         -1,
   7406     },
   7407 #endif /* chips */
   7408 
   7409 #if defined(BCM_56160_A0)
   7410     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM56160_A0r */
   7411         soc_block_list[2],
   7412         soc_genreg,
   7413         1,
   7414         0,
   7415         0x2022a00,
   7416         0,
   7417         0,
   7418         3,
   7419         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   7420         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7421         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7422         -1,
   7423         -1,
   7424     },
   7425 #endif /* chips */
   7426 
   7427 #if defined(BCM_56370_A0)
   7428     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM56370_A0r */
   7429         soc_block_list[9],
   7430         soc_genreg,
   7431         1,
   7432         0,
   7433         0x2022a00,
   7434         0,
   7435         0,
   7436         3,
   7437         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   7438         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7439         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7440         -1,
   7441         -1,
   7442         3,
   7443     },
   7444 #endif /* chips */
   7445 
   7446 #if defined(BCM_56142_A0) || defined(BCM_56440_A0) || \
   7447     defined(BCM_56440_B0)
   7448     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM56440_A0r */
   7449         soc_block_list[2],
   7450         soc_genreg,
   7451         1,
   7452         0,
   7453         0x80039,
   7454         0,
   7455         0,
   7456         4,
   7457         soc_GE0_EEE_CONFIG_BCM56440_A0r_fields,
   7458         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7459         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7460         -1,
   7461         -1,
   7462     },
   7463 #endif /* chips */
   7464 
   7465 #if defined(BCM_88375_A0)
   7466     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM88375_A0r */
   7467         soc_block_list[2],
   7468         soc_genreg,
   7469         1,
   7470         0,
   7471         0x2022a00,
   7472         0,
   7473         0,
   7474         3,
   7475         soc_GE6_EEE_CONFIG_BCM88375_A0r_fields,
   7476         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7477         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7478         -1,
   7479         -1,
   7480     },
   7481 #endif /* chips */
   7482 
   7483 #if defined(BCM_88375_B0)
   7484     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM88375_B0r */
   7485         soc_block_list[2],
   7486         soc_genreg,
   7487         1,
   7488         0,
   7489         0x2022a00,
   7490         0,
   7491         0,
   7492         3,
   7493         soc_GE6_EEE_CONFIG_BCM88375_B0r_fields,
   7494         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7495         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7496         -1,
   7497         -1,
   7498     },
   7499 #endif /* chips */
   7500 
   7501 #if defined(BCM_88470_A0)
   7502     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM88470_A0r */
   7503         soc_block_list[2],
   7504         soc_genreg,
   7505         1,
   7506         0,
   7507         0x2022a00,
   7508         0,
   7509         0,
   7510         3,
   7511         soc_GE6_EEE_CONFIG_BCM88470_A0r_fields,
   7512         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7513         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7514         -1,
   7515         -1,
   7516     },
   7517 #endif /* chips */
   7518 
   7519 #if defined(BCM_88470_B0)
   7520     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM88470_B0r */
   7521         soc_block_list[2],
   7522         soc_genreg,
   7523         1,
   7524         0,
   7525         0x2022a00,
   7526         0,
   7527         0,
   7528         3,
   7529         soc_GE6_EEE_CONFIG_BCM88470_B0r_fields,
   7530         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7531         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7532         -1,
   7533         -1,
   7534     },
   7535 #endif /* chips */
   7536 
   7537 #if defined(BCM_88675_A0)
   7538     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM88675_A0r */
   7539         soc_block_list[2],
   7540         soc_genreg,
   7541         1,
   7542         0,
   7543         0x2022a00,
   7544         0,
   7545         0,
   7546         3,
   7547         soc_GE6_EEE_CONFIGr_fields,
   7548         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7549         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7550         -1,
   7551         -1,
   7552     },
   7553 #endif /* chips */
   7554 
   7555 #if defined(BCM_88675_B0)
   7556     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM88675_B0r */
   7557         soc_block_list[2],
   7558         soc_genreg,
   7559         1,
   7560         0,
   7561         0x2022a00,
   7562         0,
   7563         0,
   7564         3,
   7565         soc_GE6_EEE_CONFIG_BCM88675_B0r_fields,
   7566         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7567         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7568         -1,
   7569         -1,
   7570     },
   7571 #endif /* chips */
   7572 
   7573 #if defined(BCM_88680_A0)
   7574     { /* SOC_REG_INT_GE6_EEE_CONFIG_BCM88680_A0r */
   7575         soc_block_list[2],
   7576         soc_genreg,
   7577         1,
   7578         0,
   7579         0x2022a00,
   7580         0,
   7581         0,
   7582         3,
   7583         soc_GE6_EEE_CONFIG_BCM88680_A0r_fields,
   7584         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   7585         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   7586         -1,
   7587         -1,
   7588     },
   7589 #endif /* chips */
   7590 
   7591 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   7592     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   7593     { /* SOC_REG_INT_GE6_GBODE_CELL_CNTr */
   7594         soc_block_list[2],
   7595         soc_genreg,
   7596         1,
   7597         0,
   7598         0x80016,
   7599         SOC_REG_FLAG_RO,
   7600         0,
   7601         1,
   7602         soc_GE0_GBODE_CELL_CNTr_fields,
   7603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7604         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7605         -1,
   7606         -1,
   7607     },
   7608 #endif /* chips */
   7609 
   7610 #if defined(BCM_53400_A0)
   7611     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM53400_A0r */
   7612         soc_block_list[9],
   7613         soc_genreg,
   7614         1,
   7615         0,
   7616         0x2021700,
   7617         SOC_REG_FLAG_RO,
   7618         0,
   7619         1,
   7620         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   7621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7622         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7623         -1,
   7624         -1,
   7625     },
   7626 #endif /* chips */
   7627 
   7628 #if defined(BCM_53540_A0)
   7629     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM53540_A0r */
   7630         soc_block_list[2],
   7631         soc_genreg,
   7632         1,
   7633         0,
   7634         0x2021700,
   7635         SOC_REG_FLAG_RO,
   7636         0,
   7637         1,
   7638         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   7639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7640         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7641         -1,
   7642         -1,
   7643     },
   7644 #endif /* chips */
   7645 
   7646 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   7647     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM53570_A0r */
   7648         soc_block_list[2],
   7649         soc_genreg,
   7650         1,
   7651         0,
   7652         0x2021f00,
   7653         SOC_REG_FLAG_RO,
   7654         0,
   7655         1,
   7656         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   7657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7658         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7659         -1,
   7660         -1,
   7661     },
   7662 #endif /* chips */
   7663 
   7664 #if defined(BCM_56150_A0)
   7665     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM56150_A0r */
   7666         soc_block_list[2],
   7667         soc_genreg,
   7668         1,
   7669         0,
   7670         0x2021700,
   7671         SOC_REG_FLAG_RO,
   7672         0,
   7673         1,
   7674         soc_GE0_GBODE_CELL_CNT_BCM56150_A0r_fields,
   7675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7676         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7677         -1,
   7678         -1,
   7679     },
   7680 #endif /* chips */
   7681 
   7682 #if defined(BCM_56160_A0)
   7683     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM56160_A0r */
   7684         soc_block_list[2],
   7685         soc_genreg,
   7686         1,
   7687         0,
   7688         0x2021700,
   7689         SOC_REG_FLAG_RO,
   7690         0,
   7691         1,
   7692         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   7693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7694         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7695         -1,
   7696         -1,
   7697     },
   7698 #endif /* chips */
   7699 
   7700 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   7701     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   7702     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   7703     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   7704     defined(BCM_56440_B0)
   7705     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM56224_A0r */
   7706         soc_block_list[2],
   7707         soc_genreg,
   7708         1,
   7709         0,
   7710         0x80016,
   7711         SOC_REG_FLAG_RO,
   7712         0,
   7713         1,
   7714         soc_GE_GBODE_CELL_CNTr_fields,
   7715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7716         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7717         -1,
   7718         -1,
   7719     },
   7720 #endif /* chips */
   7721 
   7722 #if defined(BCM_56370_A0)
   7723     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM56370_A0r */
   7724         soc_block_list[9],
   7725         soc_genreg,
   7726         1,
   7727         0,
   7728         0x2021700,
   7729         SOC_REG_FLAG_RO,
   7730         0,
   7731         1,
   7732         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   7733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7734         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7735         -1,
   7736         -1,
   7737         3,
   7738     },
   7739 #endif /* chips */
   7740 
   7741 #if defined(BCM_88375_A0)
   7742     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM88375_A0r */
   7743         soc_block_list[2],
   7744         soc_genreg,
   7745         1,
   7746         0,
   7747         0x2021700,
   7748         SOC_REG_FLAG_RO,
   7749         0,
   7750         1,
   7751         soc_GE6_GBODE_CELL_CNT_BCM88375_A0r_fields,
   7752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7753         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7754         -1,
   7755         -1,
   7756     },
   7757 #endif /* chips */
   7758 
   7759 #if defined(BCM_88375_B0)
   7760     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM88375_B0r */
   7761         soc_block_list[2],
   7762         soc_genreg,
   7763         1,
   7764         0,
   7765         0x2021700,
   7766         SOC_REG_FLAG_RO,
   7767         0,
   7768         1,
   7769         soc_GE6_GBODE_CELL_CNT_BCM88375_B0r_fields,
   7770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7771         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7772         -1,
   7773         -1,
   7774     },
   7775 #endif /* chips */
   7776 
   7777 #if defined(BCM_88470_A0)
   7778     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM88470_A0r */
   7779         soc_block_list[2],
   7780         soc_genreg,
   7781         1,
   7782         0,
   7783         0x2021700,
   7784         SOC_REG_FLAG_RO,
   7785         0,
   7786         1,
   7787         soc_GE6_GBODE_CELL_CNT_BCM88470_A0r_fields,
   7788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7789         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7790         -1,
   7791         -1,
   7792     },
   7793 #endif /* chips */
   7794 
   7795 #if defined(BCM_88470_B0)
   7796     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM88470_B0r */
   7797         soc_block_list[2],
   7798         soc_genreg,
   7799         1,
   7800         0,
   7801         0x2021700,
   7802         SOC_REG_FLAG_RO,
   7803         0,
   7804         1,
   7805         soc_GE6_GBODE_CELL_CNT_BCM88470_B0r_fields,
   7806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7807         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7808         -1,
   7809         -1,
   7810     },
   7811 #endif /* chips */
   7812 
   7813 #if defined(BCM_88675_A0)
   7814     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM88675_A0r */
   7815         soc_block_list[2],
   7816         soc_genreg,
   7817         1,
   7818         0,
   7819         0x2021700,
   7820         SOC_REG_FLAG_RO,
   7821         0,
   7822         1,
   7823         soc_GE6_GBODE_CELL_CNTr_fields,
   7824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7825         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7826         -1,
   7827         -1,
   7828     },
   7829 #endif /* chips */
   7830 
   7831 #if defined(BCM_88675_B0)
   7832     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM88675_B0r */
   7833         soc_block_list[2],
   7834         soc_genreg,
   7835         1,
   7836         0,
   7837         0x2021700,
   7838         SOC_REG_FLAG_RO,
   7839         0,
   7840         1,
   7841         soc_GE6_GBODE_CELL_CNT_BCM88675_B0r_fields,
   7842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7843         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7844         -1,
   7845         -1,
   7846     },
   7847 #endif /* chips */
   7848 
   7849 #if defined(BCM_88680_A0)
   7850     { /* SOC_REG_INT_GE6_GBODE_CELL_CNT_BCM88680_A0r */
   7851         soc_block_list[2],
   7852         soc_genreg,
   7853         1,
   7854         0,
   7855         0x2021700,
   7856         SOC_REG_FLAG_RO,
   7857         0,
   7858         1,
   7859         soc_GE6_GBODE_CELL_CNT_BCM88680_A0r_fields,
   7860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7861         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7862         -1,
   7863         -1,
   7864     },
   7865 #endif /* chips */
   7866 
   7867 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   7868     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   7869     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNTr */
   7870         soc_block_list[2],
   7871         soc_genreg,
   7872         1,
   7873         0,
   7874         0x80022,
   7875         SOC_REG_FLAG_RO,
   7876         0,
   7877         1,
   7878         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   7879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7880         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7881         -1,
   7882         -1,
   7883     },
   7884 #endif /* chips */
   7885 
   7886 #if defined(BCM_53400_A0)
   7887     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM53400_A0r */
   7888         soc_block_list[9],
   7889         soc_genreg,
   7890         1,
   7891         0,
   7892         0x2021f00,
   7893         SOC_REG_FLAG_RO,
   7894         0,
   7895         1,
   7896         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   7897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7899         -1,
   7900         -1,
   7901     },
   7902 #endif /* chips */
   7903 
   7904 #if defined(BCM_53540_A0)
   7905     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM53540_A0r */
   7906         soc_block_list[2],
   7907         soc_genreg,
   7908         1,
   7909         0,
   7910         0x2021f00,
   7911         SOC_REG_FLAG_RO,
   7912         0,
   7913         1,
   7914         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   7915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7916         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7917         -1,
   7918         -1,
   7919     },
   7920 #endif /* chips */
   7921 
   7922 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   7923     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM53570_A0r */
   7924         soc_block_list[2],
   7925         soc_genreg,
   7926         1,
   7927         0,
   7928         0x2022700,
   7929         SOC_REG_FLAG_RO,
   7930         0,
   7931         1,
   7932         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   7933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7934         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7935         -1,
   7936         -1,
   7937     },
   7938 #endif /* chips */
   7939 
   7940 #if defined(BCM_56150_A0)
   7941     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM56150_A0r */
   7942         soc_block_list[2],
   7943         soc_genreg,
   7944         1,
   7945         0,
   7946         0x2021f00,
   7947         SOC_REG_FLAG_RO,
   7948         0,
   7949         1,
   7950         soc_GE0_GBODE_CELL_REQ_CNT_BCM56150_A0r_fields,
   7951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7952         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7953         -1,
   7954         -1,
   7955     },
   7956 #endif /* chips */
   7957 
   7958 #if defined(BCM_56160_A0)
   7959     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM56160_A0r */
   7960         soc_block_list[2],
   7961         soc_genreg,
   7962         1,
   7963         0,
   7964         0x2021f00,
   7965         SOC_REG_FLAG_RO,
   7966         0,
   7967         1,
   7968         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   7969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7971         -1,
   7972         -1,
   7973     },
   7974 #endif /* chips */
   7975 
   7976 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   7977     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   7978     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   7979     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   7980     defined(BCM_56440_B0)
   7981     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   7982         soc_block_list[2],
   7983         soc_genreg,
   7984         1,
   7985         0,
   7986         0x80022,
   7987         SOC_REG_FLAG_RO,
   7988         0,
   7989         1,
   7990         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   7991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7992         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7993         -1,
   7994         -1,
   7995     },
   7996 #endif /* chips */
   7997 
   7998 #if defined(BCM_56370_A0)
   7999     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM56370_A0r */
   8000         soc_block_list[9],
   8001         soc_genreg,
   8002         1,
   8003         0,
   8004         0x2021f00,
   8005         SOC_REG_FLAG_RO,
   8006         0,
   8007         1,
   8008         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   8009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8010         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8011         -1,
   8012         -1,
   8013         3,
   8014     },
   8015 #endif /* chips */
   8016 
   8017 #if defined(BCM_88375_A0)
   8018     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM88375_A0r */
   8019         soc_block_list[2],
   8020         soc_genreg,
   8021         1,
   8022         0,
   8023         0x2021f00,
   8024         SOC_REG_FLAG_RO,
   8025         0,
   8026         1,
   8027         soc_GE6_GBODE_CELL_REQ_CNT_BCM88375_A0r_fields,
   8028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8029         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8030         -1,
   8031         -1,
   8032     },
   8033 #endif /* chips */
   8034 
   8035 #if defined(BCM_88375_B0)
   8036     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM88375_B0r */
   8037         soc_block_list[2],
   8038         soc_genreg,
   8039         1,
   8040         0,
   8041         0x2021f00,
   8042         SOC_REG_FLAG_RO,
   8043         0,
   8044         1,
   8045         soc_GE6_GBODE_CELL_REQ_CNT_BCM88375_B0r_fields,
   8046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8047         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8048         -1,
   8049         -1,
   8050     },
   8051 #endif /* chips */
   8052 
   8053 #if defined(BCM_88470_A0)
   8054     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM88470_A0r */
   8055         soc_block_list[2],
   8056         soc_genreg,
   8057         1,
   8058         0,
   8059         0x2021f00,
   8060         SOC_REG_FLAG_RO,
   8061         0,
   8062         1,
   8063         soc_GE6_GBODE_CELL_REQ_CNT_BCM88470_A0r_fields,
   8064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8065         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8066         -1,
   8067         -1,
   8068     },
   8069 #endif /* chips */
   8070 
   8071 #if defined(BCM_88470_B0)
   8072     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM88470_B0r */
   8073         soc_block_list[2],
   8074         soc_genreg,
   8075         1,
   8076         0,
   8077         0x2021f00,
   8078         SOC_REG_FLAG_RO,
   8079         0,
   8080         1,
   8081         soc_GE6_GBODE_CELL_REQ_CNT_BCM88470_B0r_fields,
   8082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8083         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8084         -1,
   8085         -1,
   8086     },
   8087 #endif /* chips */
   8088 
   8089 #if defined(BCM_88675_A0)
   8090     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM88675_A0r */
   8091         soc_block_list[2],
   8092         soc_genreg,
   8093         1,
   8094         0,
   8095         0x2021f00,
   8096         SOC_REG_FLAG_RO,
   8097         0,
   8098         1,
   8099         soc_GE6_GBODE_CELL_REQ_CNTr_fields,
   8100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8101         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8102         -1,
   8103         -1,
   8104     },
   8105 #endif /* chips */
   8106 
   8107 #if defined(BCM_88675_B0)
   8108     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM88675_B0r */
   8109         soc_block_list[2],
   8110         soc_genreg,
   8111         1,
   8112         0,
   8113         0x2021f00,
   8114         SOC_REG_FLAG_RO,
   8115         0,
   8116         1,
   8117         soc_GE6_GBODE_CELL_REQ_CNT_BCM88675_B0r_fields,
   8118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8119         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8120         -1,
   8121         -1,
   8122     },
   8123 #endif /* chips */
   8124 
   8125 #if defined(BCM_88680_A0)
   8126     { /* SOC_REG_INT_GE6_GBODE_CELL_REQ_CNT_BCM88680_A0r */
   8127         soc_block_list[2],
   8128         soc_genreg,
   8129         1,
   8130         0,
   8131         0x2021f00,
   8132         SOC_REG_FLAG_RO,
   8133         0,
   8134         1,
   8135         soc_GE6_GBODE_CELL_REQ_CNT_BCM88680_A0r_fields,
   8136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8137         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8138         -1,
   8139         -1,
   8140     },
   8141 #endif /* chips */
   8142 
   8143 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   8144     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   8145     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   8146     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   8147     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   8148     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
   8149     defined(BCM_56514_A0)
   8150     { /* SOC_REG_INT_GE6_GBOD_OVRFLWr */
   8151         soc_block_list[2],
   8152         soc_genreg,
   8153         1,
   8154         0,
   8155         0x8000a,
   8156         SOC_REG_FLAG_RO,
   8157         0,
   8158         1,
   8159         soc_GE0_GBOD_OVRFLWr_fields,
   8160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8161         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8162         -1,
   8163         -1,
   8164     },
   8165 #endif /* chips */
   8166 
   8167 #if defined(BCM_53400_A0)
   8168     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM53400_A0r */
   8169         soc_block_list[9],
   8170         soc_genreg,
   8171         1,
   8172         0,
   8173         0x2020f00,
   8174         SOC_REG_FLAG_RO,
   8175         0,
   8176         1,
   8177         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   8178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8179         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8180         -1,
   8181         -1,
   8182     },
   8183 #endif /* chips */
   8184 
   8185 #if defined(BCM_53540_A0)
   8186     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM53540_A0r */
   8187         soc_block_list[2],
   8188         soc_genreg,
   8189         1,
   8190         0,
   8191         0x2020f00,
   8192         SOC_REG_FLAG_RO,
   8193         0,
   8194         1,
   8195         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   8196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8197         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8198         -1,
   8199         -1,
   8200     },
   8201 #endif /* chips */
   8202 
   8203 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8204     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM53570_A0r */
   8205         soc_block_list[2],
   8206         soc_genreg,
   8207         1,
   8208         0,
   8209         0x2021700,
   8210         SOC_REG_FLAG_RO,
   8211         0,
   8212         1,
   8213         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   8214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8215         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8216         -1,
   8217         -1,
   8218     },
   8219 #endif /* chips */
   8220 
   8221 #if defined(BCM_56150_A0)
   8222     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM56150_A0r */
   8223         soc_block_list[2],
   8224         soc_genreg,
   8225         1,
   8226         0,
   8227         0x2020f00,
   8228         SOC_REG_FLAG_RO,
   8229         0,
   8230         1,
   8231         soc_PORT_CDC_RXFIFO_OVRFLW_BCM56640_A0r_fields,
   8232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8233         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8234         -1,
   8235         -1,
   8236     },
   8237 #endif /* chips */
   8238 
   8239 #if defined(BCM_56160_A0)
   8240     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM56160_A0r */
   8241         soc_block_list[2],
   8242         soc_genreg,
   8243         1,
   8244         0,
   8245         0x2020f00,
   8246         SOC_REG_FLAG_RO,
   8247         0,
   8248         1,
   8249         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   8250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8251         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8252         -1,
   8253         -1,
   8254     },
   8255 #endif /* chips */
   8256 
   8257 #if defined(BCM_56370_A0)
   8258     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM56370_A0r */
   8259         soc_block_list[9],
   8260         soc_genreg,
   8261         1,
   8262         0,
   8263         0x2020f00,
   8264         SOC_REG_FLAG_RO,
   8265         0,
   8266         1,
   8267         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   8268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8269         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8270         -1,
   8271         -1,
   8272         3,
   8273     },
   8274 #endif /* chips */
   8275 
   8276 #if defined(BCM_88375_A0)
   8277     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM88375_A0r */
   8278         soc_block_list[2],
   8279         soc_genreg,
   8280         1,
   8281         0,
   8282         0x2020f00,
   8283         SOC_REG_FLAG_RO,
   8284         0,
   8285         1,
   8286         soc_GE6_GBOD_OVRFLW_BCM88375_A0r_fields,
   8287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8288         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8289         -1,
   8290         -1,
   8291     },
   8292 #endif /* chips */
   8293 
   8294 #if defined(BCM_88375_B0)
   8295     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM88375_B0r */
   8296         soc_block_list[2],
   8297         soc_genreg,
   8298         1,
   8299         0,
   8300         0x2020f00,
   8301         SOC_REG_FLAG_RO,
   8302         0,
   8303         1,
   8304         soc_GE6_GBOD_OVRFLW_BCM88375_B0r_fields,
   8305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8306         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8307         -1,
   8308         -1,
   8309     },
   8310 #endif /* chips */
   8311 
   8312 #if defined(BCM_88470_A0)
   8313     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM88470_A0r */
   8314         soc_block_list[2],
   8315         soc_genreg,
   8316         1,
   8317         0,
   8318         0x2020f00,
   8319         SOC_REG_FLAG_RO,
   8320         0,
   8321         1,
   8322         soc_GE6_GBOD_OVRFLW_BCM88470_A0r_fields,
   8323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8324         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8325         -1,
   8326         -1,
   8327     },
   8328 #endif /* chips */
   8329 
   8330 #if defined(BCM_88470_B0)
   8331     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM88470_B0r */
   8332         soc_block_list[2],
   8333         soc_genreg,
   8334         1,
   8335         0,
   8336         0x2020f00,
   8337         SOC_REG_FLAG_RO,
   8338         0,
   8339         1,
   8340         soc_GE6_GBOD_OVRFLW_BCM88470_B0r_fields,
   8341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8342         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8343         -1,
   8344         -1,
   8345     },
   8346 #endif /* chips */
   8347 
   8348 #if defined(BCM_88675_A0)
   8349     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM88675_A0r */
   8350         soc_block_list[2],
   8351         soc_genreg,
   8352         1,
   8353         0,
   8354         0x2020f00,
   8355         SOC_REG_FLAG_RO,
   8356         0,
   8357         1,
   8358         soc_GE6_GBOD_OVRFLWr_fields,
   8359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8360         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8361         -1,
   8362         -1,
   8363     },
   8364 #endif /* chips */
   8365 
   8366 #if defined(BCM_88675_B0)
   8367     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM88675_B0r */
   8368         soc_block_list[2],
   8369         soc_genreg,
   8370         1,
   8371         0,
   8372         0x2020f00,
   8373         SOC_REG_FLAG_RO,
   8374         0,
   8375         1,
   8376         soc_GE6_GBOD_OVRFLW_BCM88675_B0r_fields,
   8377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8378         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8379         -1,
   8380         -1,
   8381     },
   8382 #endif /* chips */
   8383 
   8384 #if defined(BCM_88680_A0)
   8385     { /* SOC_REG_INT_GE6_GBOD_OVRFLW_BCM88680_A0r */
   8386         soc_block_list[2],
   8387         soc_genreg,
   8388         1,
   8389         0,
   8390         0x2020f00,
   8391         SOC_REG_FLAG_RO,
   8392         0,
   8393         1,
   8394         soc_GE6_GBOD_OVRFLW_BCM88680_A0r_fields,
   8395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8396         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8397         -1,
   8398         -1,
   8399     },
   8400 #endif /* chips */
   8401 
   8402 #if defined(BCM_53570_A0)
   8403     { /* SOC_REG_INT_GE6_MIN_FRAG_SIZEr */
   8404         soc_block_list[2],
   8405         soc_genreg,
   8406         1,
   8407         0,
   8408         0x2020f00,
   8409         0,
   8410         0,
   8411         2,
   8412         soc_GE0_MIN_FRAG_SIZEr_fields,
   8413         SOC_RESET_VAL_DEC(0x00000387, 0x00000000)
   8414         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   8415         -1,
   8416         -1,
   8417     },
   8418 #endif /* chips */
   8419 
   8420 #if defined(BCM_53570_B0)
   8421     { /* SOC_REG_INT_GE6_MIN_FRAG_SIZE_BCM53570_B0r */
   8422         soc_block_list[2],
   8423         soc_genreg,
   8424         1,
   8425         0,
   8426         0x2020f00,
   8427         0,
   8428         0,
   8429         2,
   8430         soc_GE0_MIN_FRAG_SIZE_BCM53570_B0r_fields,
   8431         SOC_RESET_VAL_DEC(0x00000408, 0x00000000)
   8432         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   8433         -1,
   8434         -1,
   8435     },
   8436 #endif /* chips */
   8437 
   8438 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8439     { /* SOC_REG_INT_GE6_S3MII_SPEED_DEBUGr */
   8440         soc_block_list[2],
   8441         soc_genreg,
   8442         1,
   8443         0,
   8444         0x80041,
   8445         SOC_REG_FLAG_RO,
   8446         0,
   8447         4,
   8448         soc_GE0_S3MII_SPEED_DEBUGr_fields,
   8449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8451         -1,
   8452         -1,
   8453     },
   8454 #endif /* chips */
   8455 
   8456 #if defined(BCM_53324_A0)
   8457     { /* SOC_REG_INT_GE7_EEE_CONFIGr */
   8458         soc_block_list[2],
   8459         soc_genreg,
   8460         1,
   8461         0,
   8462         0x8003d,
   8463         0,
   8464         0,
   8465         4,
   8466         soc_GE0_EEE_CONFIGr_fields,
   8467         SOC_RESET_VAL_DEC(0x000014e1, 0x00000000)
   8468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8469         -1,
   8470         -1,
   8471     },
   8472 #endif /* chips */
   8473 
   8474 #if defined(BCM_53400_A0)
   8475     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM53400_A0r */
   8476         soc_block_list[9],
   8477         soc_genreg,
   8478         1,
   8479         0,
   8480         0x2022b00,
   8481         0,
   8482         0,
   8483         3,
   8484         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   8485         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8486         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8487         -1,
   8488         -1,
   8489     },
   8490 #endif /* chips */
   8491 
   8492 #if defined(BCM_53540_A0)
   8493     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM53540_A0r */
   8494         soc_block_list[2],
   8495         soc_genreg,
   8496         1,
   8497         0,
   8498         0x2022b00,
   8499         0,
   8500         0,
   8501         3,
   8502         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   8503         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8504         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8505         -1,
   8506         -1,
   8507     },
   8508 #endif /* chips */
   8509 
   8510 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8511     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM53570_A0r */
   8512         soc_block_list[2],
   8513         soc_genreg,
   8514         1,
   8515         0,
   8516         0x2023600,
   8517         0,
   8518         0,
   8519         3,
   8520         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   8521         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8522         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8523         -1,
   8524         -1,
   8525     },
   8526 #endif /* chips */
   8527 
   8528 #if defined(BCM_56150_A0)
   8529     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM56150_A0r */
   8530         soc_block_list[2],
   8531         soc_genreg,
   8532         1,
   8533         0,
   8534         0x2022b00,
   8535         0,
   8536         0,
   8537         3,
   8538         soc_GE0_EEE_CONFIG_BCM56150_A0r_fields,
   8539         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8540         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8541         -1,
   8542         -1,
   8543     },
   8544 #endif /* chips */
   8545 
   8546 #if defined(BCM_56160_A0)
   8547     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM56160_A0r */
   8548         soc_block_list[2],
   8549         soc_genreg,
   8550         1,
   8551         0,
   8552         0x2022b00,
   8553         0,
   8554         0,
   8555         3,
   8556         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   8557         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8558         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8559         -1,
   8560         -1,
   8561     },
   8562 #endif /* chips */
   8563 
   8564 #if defined(BCM_56370_A0)
   8565     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM56370_A0r */
   8566         soc_block_list[9],
   8567         soc_genreg,
   8568         1,
   8569         0,
   8570         0x2022b00,
   8571         0,
   8572         0,
   8573         3,
   8574         soc_GE0_EEE_CONFIG_BCM53400_A0r_fields,
   8575         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8576         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8577         -1,
   8578         -1,
   8579         3,
   8580     },
   8581 #endif /* chips */
   8582 
   8583 #if defined(BCM_56142_A0) || defined(BCM_56440_A0) || \
   8584     defined(BCM_56440_B0)
   8585     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM56440_A0r */
   8586         soc_block_list[2],
   8587         soc_genreg,
   8588         1,
   8589         0,
   8590         0x8003a,
   8591         0,
   8592         0,
   8593         4,
   8594         soc_GE0_EEE_CONFIG_BCM56440_A0r_fields,
   8595         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8597         -1,
   8598         -1,
   8599     },
   8600 #endif /* chips */
   8601 
   8602 #if defined(BCM_88375_A0)
   8603     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM88375_A0r */
   8604         soc_block_list[2],
   8605         soc_genreg,
   8606         1,
   8607         0,
   8608         0x2022b00,
   8609         0,
   8610         0,
   8611         3,
   8612         soc_GE7_EEE_CONFIG_BCM88375_A0r_fields,
   8613         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8614         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8615         -1,
   8616         -1,
   8617     },
   8618 #endif /* chips */
   8619 
   8620 #if defined(BCM_88375_B0)
   8621     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM88375_B0r */
   8622         soc_block_list[2],
   8623         soc_genreg,
   8624         1,
   8625         0,
   8626         0x2022b00,
   8627         0,
   8628         0,
   8629         3,
   8630         soc_GE7_EEE_CONFIG_BCM88375_B0r_fields,
   8631         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8632         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8633         -1,
   8634         -1,
   8635     },
   8636 #endif /* chips */
   8637 
   8638 #if defined(BCM_88470_A0)
   8639     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM88470_A0r */
   8640         soc_block_list[2],
   8641         soc_genreg,
   8642         1,
   8643         0,
   8644         0x2022b00,
   8645         0,
   8646         0,
   8647         3,
   8648         soc_GE7_EEE_CONFIG_BCM88470_A0r_fields,
   8649         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8650         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8651         -1,
   8652         -1,
   8653     },
   8654 #endif /* chips */
   8655 
   8656 #if defined(BCM_88470_B0)
   8657     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM88470_B0r */
   8658         soc_block_list[2],
   8659         soc_genreg,
   8660         1,
   8661         0,
   8662         0x2022b00,
   8663         0,
   8664         0,
   8665         3,
   8666         soc_GE7_EEE_CONFIG_BCM88470_B0r_fields,
   8667         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8668         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8669         -1,
   8670         -1,
   8671     },
   8672 #endif /* chips */
   8673 
   8674 #if defined(BCM_88675_A0)
   8675     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM88675_A0r */
   8676         soc_block_list[2],
   8677         soc_genreg,
   8678         1,
   8679         0,
   8680         0x2022b00,
   8681         0,
   8682         0,
   8683         3,
   8684         soc_GE7_EEE_CONFIGr_fields,
   8685         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8686         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8687         -1,
   8688         -1,
   8689     },
   8690 #endif /* chips */
   8691 
   8692 #if defined(BCM_88675_B0)
   8693     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM88675_B0r */
   8694         soc_block_list[2],
   8695         soc_genreg,
   8696         1,
   8697         0,
   8698         0x2022b00,
   8699         0,
   8700         0,
   8701         3,
   8702         soc_GE7_EEE_CONFIG_BCM88675_B0r_fields,
   8703         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8704         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8705         -1,
   8706         -1,
   8707     },
   8708 #endif /* chips */
   8709 
   8710 #if defined(BCM_88680_A0)
   8711     { /* SOC_REG_INT_GE7_EEE_CONFIG_BCM88680_A0r */
   8712         soc_block_list[2],
   8713         soc_genreg,
   8714         1,
   8715         0,
   8716         0x2022b00,
   8717         0,
   8718         0,
   8719         3,
   8720         soc_GE7_EEE_CONFIG_BCM88680_A0r_fields,
   8721         SOC_RESET_VAL_DEC(0x000002f9, 0x00000000)
   8722         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   8723         -1,
   8724         -1,
   8725     },
   8726 #endif /* chips */
   8727 
   8728 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   8729     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   8730     { /* SOC_REG_INT_GE7_GBODE_CELL_CNTr */
   8731         soc_block_list[2],
   8732         soc_genreg,
   8733         1,
   8734         0,
   8735         0x80017,
   8736         SOC_REG_FLAG_RO,
   8737         0,
   8738         1,
   8739         soc_GE0_GBODE_CELL_CNTr_fields,
   8740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8741         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8742         -1,
   8743         -1,
   8744     },
   8745 #endif /* chips */
   8746 
   8747 #if defined(BCM_53400_A0)
   8748     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM53400_A0r */
   8749         soc_block_list[9],
   8750         soc_genreg,
   8751         1,
   8752         0,
   8753         0x2021800,
   8754         SOC_REG_FLAG_RO,
   8755         0,
   8756         1,
   8757         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   8758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8760         -1,
   8761         -1,
   8762     },
   8763 #endif /* chips */
   8764 
   8765 #if defined(BCM_53540_A0)
   8766     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM53540_A0r */
   8767         soc_block_list[2],
   8768         soc_genreg,
   8769         1,
   8770         0,
   8771         0x2021800,
   8772         SOC_REG_FLAG_RO,
   8773         0,
   8774         1,
   8775         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   8776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8778         -1,
   8779         -1,
   8780     },
   8781 #endif /* chips */
   8782 
   8783 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8784     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM53570_A0r */
   8785         soc_block_list[2],
   8786         soc_genreg,
   8787         1,
   8788         0,
   8789         0x2022000,
   8790         SOC_REG_FLAG_RO,
   8791         0,
   8792         1,
   8793         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   8794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8796         -1,
   8797         -1,
   8798     },
   8799 #endif /* chips */
   8800 
   8801 #if defined(BCM_56150_A0)
   8802     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM56150_A0r */
   8803         soc_block_list[2],
   8804         soc_genreg,
   8805         1,
   8806         0,
   8807         0x2021800,
   8808         SOC_REG_FLAG_RO,
   8809         0,
   8810         1,
   8811         soc_GE0_GBODE_CELL_CNT_BCM56150_A0r_fields,
   8812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8814         -1,
   8815         -1,
   8816     },
   8817 #endif /* chips */
   8818 
   8819 #if defined(BCM_56160_A0)
   8820     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM56160_A0r */
   8821         soc_block_list[2],
   8822         soc_genreg,
   8823         1,
   8824         0,
   8825         0x2021800,
   8826         SOC_REG_FLAG_RO,
   8827         0,
   8828         1,
   8829         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   8830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8832         -1,
   8833         -1,
   8834     },
   8835 #endif /* chips */
   8836 
   8837 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   8838     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   8839     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   8840     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   8841     defined(BCM_56440_B0)
   8842     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM56224_A0r */
   8843         soc_block_list[2],
   8844         soc_genreg,
   8845         1,
   8846         0,
   8847         0x80017,
   8848         SOC_REG_FLAG_RO,
   8849         0,
   8850         1,
   8851         soc_GE_GBODE_CELL_CNTr_fields,
   8852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8854         -1,
   8855         -1,
   8856     },
   8857 #endif /* chips */
   8858 
   8859 #if defined(BCM_56370_A0)
   8860     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM56370_A0r */
   8861         soc_block_list[9],
   8862         soc_genreg,
   8863         1,
   8864         0,
   8865         0x2021800,
   8866         SOC_REG_FLAG_RO,
   8867         0,
   8868         1,
   8869         soc_GE0_GBODE_CELL_CNT_BCM53400_A0r_fields,
   8870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8872         -1,
   8873         -1,
   8874         3,
   8875     },
   8876 #endif /* chips */
   8877 
   8878 #if defined(BCM_88375_A0)
   8879     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM88375_A0r */
   8880         soc_block_list[2],
   8881         soc_genreg,
   8882         1,
   8883         0,
   8884         0x2021800,
   8885         SOC_REG_FLAG_RO,
   8886         0,
   8887         1,
   8888         soc_GE7_GBODE_CELL_CNT_BCM88375_A0r_fields,
   8889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8890         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8891         -1,
   8892         -1,
   8893     },
   8894 #endif /* chips */
   8895 
   8896 #if defined(BCM_88375_B0)
   8897     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM88375_B0r */
   8898         soc_block_list[2],
   8899         soc_genreg,
   8900         1,
   8901         0,
   8902         0x2021800,
   8903         SOC_REG_FLAG_RO,
   8904         0,
   8905         1,
   8906         soc_GE7_GBODE_CELL_CNT_BCM88375_B0r_fields,
   8907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8908         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8909         -1,
   8910         -1,
   8911     },
   8912 #endif /* chips */
   8913 
   8914 #if defined(BCM_88470_A0)
   8915     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM88470_A0r */
   8916         soc_block_list[2],
   8917         soc_genreg,
   8918         1,
   8919         0,
   8920         0x2021800,
   8921         SOC_REG_FLAG_RO,
   8922         0,
   8923         1,
   8924         soc_GE7_GBODE_CELL_CNT_BCM88470_A0r_fields,
   8925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8926         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8927         -1,
   8928         -1,
   8929     },
   8930 #endif /* chips */
   8931 
   8932 #if defined(BCM_88470_B0)
   8933     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM88470_B0r */
   8934         soc_block_list[2],
   8935         soc_genreg,
   8936         1,
   8937         0,
   8938         0x2021800,
   8939         SOC_REG_FLAG_RO,
   8940         0,
   8941         1,
   8942         soc_GE7_GBODE_CELL_CNT_BCM88470_B0r_fields,
   8943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8944         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8945         -1,
   8946         -1,
   8947     },
   8948 #endif /* chips */
   8949 
   8950 #if defined(BCM_88675_A0)
   8951     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM88675_A0r */
   8952         soc_block_list[2],
   8953         soc_genreg,
   8954         1,
   8955         0,
   8956         0x2021800,
   8957         SOC_REG_FLAG_RO,
   8958         0,
   8959         1,
   8960         soc_GE7_GBODE_CELL_CNTr_fields,
   8961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8962         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8963         -1,
   8964         -1,
   8965     },
   8966 #endif /* chips */
   8967 
   8968 #if defined(BCM_88675_B0)
   8969     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM88675_B0r */
   8970         soc_block_list[2],
   8971         soc_genreg,
   8972         1,
   8973         0,
   8974         0x2021800,
   8975         SOC_REG_FLAG_RO,
   8976         0,
   8977         1,
   8978         soc_GE7_GBODE_CELL_CNT_BCM88675_B0r_fields,
   8979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8980         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8981         -1,
   8982         -1,
   8983     },
   8984 #endif /* chips */
   8985 
   8986 #if defined(BCM_88680_A0)
   8987     { /* SOC_REG_INT_GE7_GBODE_CELL_CNT_BCM88680_A0r */
   8988         soc_block_list[2],
   8989         soc_genreg,
   8990         1,
   8991         0,
   8992         0x2021800,
   8993         SOC_REG_FLAG_RO,
   8994         0,
   8995         1,
   8996         soc_GE7_GBODE_CELL_CNT_BCM88680_A0r_fields,
   8997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8998         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   8999         -1,
   9000         -1,
   9001     },
   9002 #endif /* chips */
   9003 
   9004 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9005     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9006     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNTr */
   9007         soc_block_list[2],
   9008         soc_genreg,
   9009         1,
   9010         0,
   9011         0x80023,
   9012         SOC_REG_FLAG_RO,
   9013         0,
   9014         1,
   9015         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   9016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9017         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9018         -1,
   9019         -1,
   9020     },
   9021 #endif /* chips */
   9022 
   9023 #if defined(BCM_53400_A0)
   9024     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM53400_A0r */
   9025         soc_block_list[9],
   9026         soc_genreg,
   9027         1,
   9028         0,
   9029         0x2022000,
   9030         SOC_REG_FLAG_RO,
   9031         0,
   9032         1,
   9033         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   9034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9035         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9036         -1,
   9037         -1,
   9038     },
   9039 #endif /* chips */
   9040 
   9041 #if defined(BCM_53540_A0)
   9042     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM53540_A0r */
   9043         soc_block_list[2],
   9044         soc_genreg,
   9045         1,
   9046         0,
   9047         0x2022000,
   9048         SOC_REG_FLAG_RO,
   9049         0,
   9050         1,
   9051         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   9052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9053         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9054         -1,
   9055         -1,
   9056     },
   9057 #endif /* chips */
   9058 
   9059 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   9060     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM53570_A0r */
   9061         soc_block_list[2],
   9062         soc_genreg,
   9063         1,
   9064         0,
   9065         0x2022800,
   9066         SOC_REG_FLAG_RO,
   9067         0,
   9068         1,
   9069         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   9070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9072         -1,
   9073         -1,
   9074     },
   9075 #endif /* chips */
   9076 
   9077 #if defined(BCM_56150_A0)
   9078     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM56150_A0r */
   9079         soc_block_list[2],
   9080         soc_genreg,
   9081         1,
   9082         0,
   9083         0x2022000,
   9084         SOC_REG_FLAG_RO,
   9085         0,
   9086         1,
   9087         soc_GE0_GBODE_CELL_REQ_CNT_BCM56150_A0r_fields,
   9088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9089         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9090         -1,
   9091         -1,
   9092     },
   9093 #endif /* chips */
   9094 
   9095 #if defined(BCM_56160_A0)
   9096     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM56160_A0r */
   9097         soc_block_list[2],
   9098         soc_genreg,
   9099         1,
   9100         0,
   9101         0x2022000,
   9102         SOC_REG_FLAG_RO,
   9103         0,
   9104         1,
   9105         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   9106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9107         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9108         -1,
   9109         -1,
   9110     },
   9111 #endif /* chips */
   9112 
   9113 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9114     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   9115     defined(BCM_56224_B0) || defined(BCM_56334_A0) || \
   9116     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
   9117     defined(BCM_56440_B0)
   9118     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   9119         soc_block_list[2],
   9120         soc_genreg,
   9121         1,
   9122         0,
   9123         0x80023,
   9124         SOC_REG_FLAG_RO,
   9125         0,
   9126         1,
   9127         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   9128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9129         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9130         -1,
   9131         -1,
   9132     },
   9133 #endif /* chips */
   9134 
   9135 #if defined(BCM_56370_A0)
   9136     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM56370_A0r */
   9137         soc_block_list[9],
   9138         soc_genreg,
   9139         1,
   9140         0,
   9141         0x2022000,
   9142         SOC_REG_FLAG_RO,
   9143         0,
   9144         1,
   9145         soc_GE0_GBODE_CELL_REQ_CNT_BCM53400_A0r_fields,
   9146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9148         -1,
   9149         -1,
   9150         3,
   9151     },
   9152 #endif /* chips */
   9153 
   9154 #if defined(BCM_88375_A0)
   9155     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM88375_A0r */
   9156         soc_block_list[2],
   9157         soc_genreg,
   9158         1,
   9159         0,
   9160         0x2022000,
   9161         SOC_REG_FLAG_RO,
   9162         0,
   9163         1,
   9164         soc_GE7_GBODE_CELL_REQ_CNT_BCM88375_A0r_fields,
   9165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9166         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9167         -1,
   9168         -1,
   9169     },
   9170 #endif /* chips */
   9171 
   9172 #if defined(BCM_88375_B0)
   9173     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM88375_B0r */
   9174         soc_block_list[2],
   9175         soc_genreg,
   9176         1,
   9177         0,
   9178         0x2022000,
   9179         SOC_REG_FLAG_RO,
   9180         0,
   9181         1,
   9182         soc_GE7_GBODE_CELL_REQ_CNT_BCM88375_B0r_fields,
   9183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9184         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9185         -1,
   9186         -1,
   9187     },
   9188 #endif /* chips */
   9189 
   9190 #if defined(BCM_88470_A0)
   9191     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM88470_A0r */
   9192         soc_block_list[2],
   9193         soc_genreg,
   9194         1,
   9195         0,
   9196         0x2022000,
   9197         SOC_REG_FLAG_RO,
   9198         0,
   9199         1,
   9200         soc_GE7_GBODE_CELL_REQ_CNT_BCM88470_A0r_fields,
   9201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9202         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9203         -1,
   9204         -1,
   9205     },
   9206 #endif /* chips */
   9207 
   9208 #if defined(BCM_88470_B0)
   9209     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM88470_B0r */
   9210         soc_block_list[2],
   9211         soc_genreg,
   9212         1,
   9213         0,
   9214         0x2022000,
   9215         SOC_REG_FLAG_RO,
   9216         0,
   9217         1,
   9218         soc_GE7_GBODE_CELL_REQ_CNT_BCM88470_B0r_fields,
   9219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9220         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9221         -1,
   9222         -1,
   9223     },
   9224 #endif /* chips */
   9225 
   9226 #if defined(BCM_88675_A0)
   9227     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM88675_A0r */
   9228         soc_block_list[2],
   9229         soc_genreg,
   9230         1,
   9231         0,
   9232         0x2022000,
   9233         SOC_REG_FLAG_RO,
   9234         0,
   9235         1,
   9236         soc_GE7_GBODE_CELL_REQ_CNTr_fields,
   9237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9238         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9239         -1,
   9240         -1,
   9241     },
   9242 #endif /* chips */
   9243 
   9244 #if defined(BCM_88675_B0)
   9245     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM88675_B0r */
   9246         soc_block_list[2],
   9247         soc_genreg,
   9248         1,
   9249         0,
   9250         0x2022000,
   9251         SOC_REG_FLAG_RO,
   9252         0,
   9253         1,
   9254         soc_GE7_GBODE_CELL_REQ_CNT_BCM88675_B0r_fields,
   9255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9256         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9257         -1,
   9258         -1,
   9259     },
   9260 #endif /* chips */
   9261 
   9262 #if defined(BCM_88680_A0)
   9263     { /* SOC_REG_INT_GE7_GBODE_CELL_REQ_CNT_BCM88680_A0r */
   9264         soc_block_list[2],
   9265         soc_genreg,
   9266         1,
   9267         0,
   9268         0x2022000,
   9269         SOC_REG_FLAG_RO,
   9270         0,
   9271         1,
   9272         soc_GE7_GBODE_CELL_REQ_CNT_BCM88680_A0r_fields,
   9273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9274         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9275         -1,
   9276         -1,
   9277     },
   9278 #endif /* chips */
   9279 
   9280 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9281     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   9282     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   9283     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   9284     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   9285     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
   9286     defined(BCM_56514_A0)
   9287     { /* SOC_REG_INT_GE7_GBOD_OVRFLWr */
   9288         soc_block_list[2],
   9289         soc_genreg,
   9290         1,
   9291         0,
   9292         0x8000b,
   9293         SOC_REG_FLAG_RO,
   9294         0,
   9295         1,
   9296         soc_GE0_GBOD_OVRFLWr_fields,
   9297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9298         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9299         -1,
   9300         -1,
   9301     },
   9302 #endif /* chips */
   9303 
   9304 #if defined(BCM_53400_A0)
   9305     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM53400_A0r */
   9306         soc_block_list[9],
   9307         soc_genreg,
   9308         1,
   9309         0,
   9310         0x2021000,
   9311         SOC_REG_FLAG_RO,
   9312         0,
   9313         1,
   9314         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   9315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9316         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9317         -1,
   9318         -1,
   9319     },
   9320 #endif /* chips */
   9321 
   9322 #if defined(BCM_53540_A0)
   9323     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM53540_A0r */
   9324         soc_block_list[2],
   9325         soc_genreg,
   9326         1,
   9327         0,
   9328         0x2021000,
   9329         SOC_REG_FLAG_RO,
   9330         0,
   9331         1,
   9332         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   9333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9334         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9335         -1,
   9336         -1,
   9337     },
   9338 #endif /* chips */
   9339 
   9340 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   9341     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM53570_A0r */
   9342         soc_block_list[2],
   9343         soc_genreg,
   9344         1,
   9345         0,
   9346         0x2021800,
   9347         SOC_REG_FLAG_RO,
   9348         0,
   9349         1,
   9350         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   9351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9352         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9353         -1,
   9354         -1,
   9355     },
   9356 #endif /* chips */
   9357 
   9358 #if defined(BCM_56150_A0)
   9359     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM56150_A0r */
   9360         soc_block_list[2],
   9361         soc_genreg,
   9362         1,
   9363         0,
   9364         0x2021000,
   9365         SOC_REG_FLAG_RO,
   9366         0,
   9367         1,
   9368         soc_PORT_CDC_RXFIFO_OVRFLW_BCM56640_A0r_fields,
   9369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9370         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9371         -1,
   9372         -1,
   9373     },
   9374 #endif /* chips */
   9375 
   9376 #if defined(BCM_56160_A0)
   9377     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM56160_A0r */
   9378         soc_block_list[2],
   9379         soc_genreg,
   9380         1,
   9381         0,
   9382         0x2021000,
   9383         SOC_REG_FLAG_RO,
   9384         0,
   9385         1,
   9386         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   9387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9388         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9389         -1,
   9390         -1,
   9391     },
   9392 #endif /* chips */
   9393 
   9394 #if defined(BCM_56370_A0)
   9395     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM56370_A0r */
   9396         soc_block_list[9],
   9397         soc_genreg,
   9398         1,
   9399         0,
   9400         0x2021000,
   9401         SOC_REG_FLAG_RO,
   9402         0,
   9403         1,
   9404         soc_GE0_GBOD_OVRFLW_BCM53400_A0r_fields,
   9405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9406         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9407         -1,
   9408         -1,
   9409         3,
   9410     },
   9411 #endif /* chips */
   9412 
   9413 #if defined(BCM_88375_A0)
   9414     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM88375_A0r */
   9415         soc_block_list[2],
   9416         soc_genreg,
   9417         1,
   9418         0,
   9419         0x2021000,
   9420         SOC_REG_FLAG_RO,
   9421         0,
   9422         1,
   9423         soc_GE7_GBOD_OVRFLW_BCM88375_A0r_fields,
   9424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9425         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9426         -1,
   9427         -1,
   9428     },
   9429 #endif /* chips */
   9430 
   9431 #if defined(BCM_88375_B0)
   9432     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM88375_B0r */
   9433         soc_block_list[2],
   9434         soc_genreg,
   9435         1,
   9436         0,
   9437         0x2021000,
   9438         SOC_REG_FLAG_RO,
   9439         0,
   9440         1,
   9441         soc_GE7_GBOD_OVRFLW_BCM88375_B0r_fields,
   9442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9443         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9444         -1,
   9445         -1,
   9446     },
   9447 #endif /* chips */
   9448 
   9449 #if defined(BCM_88470_A0)
   9450     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM88470_A0r */
   9451         soc_block_list[2],
   9452         soc_genreg,
   9453         1,
   9454         0,
   9455         0x2021000,
   9456         SOC_REG_FLAG_RO,
   9457         0,
   9458         1,
   9459         soc_GE7_GBOD_OVRFLW_BCM88470_A0r_fields,
   9460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9461         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9462         -1,
   9463         -1,
   9464     },
   9465 #endif /* chips */
   9466 
   9467 #if defined(BCM_88470_B0)
   9468     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM88470_B0r */
   9469         soc_block_list[2],
   9470         soc_genreg,
   9471         1,
   9472         0,
   9473         0x2021000,
   9474         SOC_REG_FLAG_RO,
   9475         0,
   9476         1,
   9477         soc_GE7_GBOD_OVRFLW_BCM88470_B0r_fields,
   9478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9479         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9480         -1,
   9481         -1,
   9482     },
   9483 #endif /* chips */
   9484 
   9485 #if defined(BCM_88675_A0)
   9486     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM88675_A0r */
   9487         soc_block_list[2],
   9488         soc_genreg,
   9489         1,
   9490         0,
   9491         0x2021000,
   9492         SOC_REG_FLAG_RO,
   9493         0,
   9494         1,
   9495         soc_GE7_GBOD_OVRFLWr_fields,
   9496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9497         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9498         -1,
   9499         -1,
   9500     },
   9501 #endif /* chips */
   9502 
   9503 #if defined(BCM_88675_B0)
   9504     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM88675_B0r */
   9505         soc_block_list[2],
   9506         soc_genreg,
   9507         1,
   9508         0,
   9509         0x2021000,
   9510         SOC_REG_FLAG_RO,
   9511         0,
   9512         1,
   9513         soc_GE7_GBOD_OVRFLW_BCM88675_B0r_fields,
   9514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9515         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9516         -1,
   9517         -1,
   9518     },
   9519 #endif /* chips */
   9520 
   9521 #if defined(BCM_88680_A0)
   9522     { /* SOC_REG_INT_GE7_GBOD_OVRFLW_BCM88680_A0r */
   9523         soc_block_list[2],
   9524         soc_genreg,
   9525         1,
   9526         0,
   9527         0x2021000,
   9528         SOC_REG_FLAG_RO,
   9529         0,
   9530         1,
   9531         soc_GE7_GBOD_OVRFLW_BCM88680_A0r_fields,
   9532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9533         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9534         -1,
   9535         -1,
   9536     },
   9537 #endif /* chips */
   9538 
   9539 #if defined(BCM_53570_A0)
   9540     { /* SOC_REG_INT_GE7_MIN_FRAG_SIZEr */
   9541         soc_block_list[2],
   9542         soc_genreg,
   9543         1,
   9544         0,
   9545         0x2021000,
   9546         0,
   9547         0,
   9548         2,
   9549         soc_GE0_MIN_FRAG_SIZEr_fields,
   9550         SOC_RESET_VAL_DEC(0x00000387, 0x00000000)
   9551         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   9552         -1,
   9553         -1,
   9554     },
   9555 #endif /* chips */
   9556 
   9557 #if defined(BCM_53570_B0)
   9558     { /* SOC_REG_INT_GE7_MIN_FRAG_SIZE_BCM53570_B0r */
   9559         soc_block_list[2],
   9560         soc_genreg,
   9561         1,
   9562         0,
   9563         0x2021000,
   9564         0,
   9565         0,
   9566         2,
   9567         soc_GE0_MIN_FRAG_SIZE_BCM53570_B0r_fields,
   9568         SOC_RESET_VAL_DEC(0x00000408, 0x00000000)
   9569         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   9570         -1,
   9571         -1,
   9572     },
   9573 #endif /* chips */
   9574 
   9575 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   9576     { /* SOC_REG_INT_GE7_S3MII_SPEED_DEBUGr */
   9577         soc_block_list[2],
   9578         soc_genreg,
   9579         1,
   9580         0,
   9581         0x80042,
   9582         SOC_REG_FLAG_RO,
   9583         0,
   9584         4,
   9585         soc_GE0_S3MII_SPEED_DEBUGr_fields,
   9586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9587         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9588         -1,
   9589         -1,
   9590     },
   9591 #endif /* chips */
   9592 
   9593 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9594     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9595     { /* SOC_REG_INT_GE8_GBODE_CELL_CNTr */
   9596         soc_block_list[2],
   9597         soc_genreg,
   9598         1,
   9599         0,
   9600         0x80018,
   9601         SOC_REG_FLAG_RO,
   9602         0,
   9603         1,
   9604         soc_GE0_GBODE_CELL_CNTr_fields,
   9605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9606         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9607         -1,
   9608         -1,
   9609     },
   9610 #endif /* chips */
   9611 
   9612 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9613     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9614     { /* SOC_REG_INT_GE8_GBODE_CELL_CNT_BCM56224_A0r */
   9615         soc_block_list[2],
   9616         soc_genreg,
   9617         1,
   9618         0,
   9619         0x80018,
   9620         SOC_REG_FLAG_RO,
   9621         0,
   9622         1,
   9623         soc_GE_GBODE_CELL_CNTr_fields,
   9624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9625         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9626         -1,
   9627         -1,
   9628     },
   9629 #endif /* chips */
   9630 
   9631 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9632     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9633     { /* SOC_REG_INT_GE8_GBODE_CELL_REQ_CNTr */
   9634         soc_block_list[2],
   9635         soc_genreg,
   9636         1,
   9637         0,
   9638         0x80024,
   9639         SOC_REG_FLAG_RO,
   9640         0,
   9641         1,
   9642         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   9643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9644         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9645         -1,
   9646         -1,
   9647     },
   9648 #endif /* chips */
   9649 
   9650 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9651     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9652     { /* SOC_REG_INT_GE8_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   9653         soc_block_list[2],
   9654         soc_genreg,
   9655         1,
   9656         0,
   9657         0x80024,
   9658         SOC_REG_FLAG_RO,
   9659         0,
   9660         1,
   9661         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   9662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9663         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9664         -1,
   9665         -1,
   9666     },
   9667 #endif /* chips */
   9668 
   9669 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9670     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
   9671     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9672     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9673     { /* SOC_REG_INT_GE8_GBOD_OVRFLWr */
   9674         soc_block_list[2],
   9675         soc_genreg,
   9676         1,
   9677         0,
   9678         0x8000c,
   9679         SOC_REG_FLAG_RO,
   9680         0,
   9681         1,
   9682         soc_GE0_GBOD_OVRFLWr_fields,
   9683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9684         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9685         -1,
   9686         -1,
   9687     },
   9688 #endif /* chips */
   9689 
   9690 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9691     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9692     { /* SOC_REG_INT_GE9_GBODE_CELL_CNTr */
   9693         soc_block_list[2],
   9694         soc_genreg,
   9695         1,
   9696         0,
   9697         0x80019,
   9698         SOC_REG_FLAG_RO,
   9699         0,
   9700         1,
   9701         soc_GE0_GBODE_CELL_CNTr_fields,
   9702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9703         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9704         -1,
   9705         -1,
   9706     },
   9707 #endif /* chips */
   9708 
   9709 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9710     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9711     { /* SOC_REG_INT_GE9_GBODE_CELL_CNT_BCM56224_A0r */
   9712         soc_block_list[2],
   9713         soc_genreg,
   9714         1,
   9715         0,
   9716         0x80019,
   9717         SOC_REG_FLAG_RO,
   9718         0,
   9719         1,
   9720         soc_GE_GBODE_CELL_CNTr_fields,
   9721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9722         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9723         -1,
   9724         -1,
   9725     },
   9726 #endif /* chips */
   9727 
   9728 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9729     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9730     { /* SOC_REG_INT_GE9_GBODE_CELL_REQ_CNTr */
   9731         soc_block_list[2],
   9732         soc_genreg,
   9733         1,
   9734         0,
   9735         0x80025,
   9736         SOC_REG_FLAG_RO,
   9737         0,
   9738         1,
   9739         soc_GE0_GBODE_CELL_REQ_CNTr_fields,
   9740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9741         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9742         -1,
   9743         -1,
   9744     },
   9745 #endif /* chips */
   9746 
   9747 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9748     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9749     { /* SOC_REG_INT_GE9_GBODE_CELL_REQ_CNT_BCM56224_A0r */
   9750         soc_block_list[2],
   9751         soc_genreg,
   9752         1,
   9753         0,
   9754         0x80025,
   9755         SOC_REG_FLAG_RO,
   9756         0,
   9757         1,
   9758         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   9759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9760         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9761         -1,
   9762         -1,
   9763     },
   9764 #endif /* chips */
   9765 
   9766 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   9767     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
   9768     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9769     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9770     { /* SOC_REG_INT_GE9_GBOD_OVRFLWr */
   9771         soc_block_list[2],
   9772         soc_genreg,
   9773         1,
   9774         0,
   9775         0x8000d,
   9776         SOC_REG_FLAG_RO,
   9777         0,
   9778         1,
   9779         soc_GE0_GBOD_OVRFLWr_fields,
   9780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9781         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9782         -1,
   9783         -1,
   9784     },
   9785 #endif /* chips */
   9786 
   9787 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   9788     defined(BCM_56870_A0)
   9789     { /* SOC_REG_INT_GENEVE_CONTROLr */
   9790         soc_block_list[115],
   9791         soc_genreg,
   9792         1,
   9793         0,
   9794         0x2002a00,
   9795         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9796         SOC_REG_FLAG_CCH,
   9797         1,
   9798         soc_GENEVE_CONTROLr_fields,
   9799         SOC_RESET_VAL_DEC(0x000017c1, 0x00000000)
   9800         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9801         -1,
   9802         -1,
   9803         3,
   9804     },
   9805 #endif /* chips */
   9806 
   9807 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
   9808     { /* SOC_REG_INT_GENEVE_DEFAULT_NETWORK_SVPr */
   9809         soc_block_list[115],
   9810         soc_genreg,
   9811         1,
   9812         0,
   9813         0x2003600,
   9814         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9815         SOC_REG_FLAG_CCH,
   9816         1,
   9817         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
   9818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9819         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9820         -1,
   9821         -1,
   9822         3,
   9823     },
   9824 #endif /* chips */
   9825 
   9826 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   9827     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   9828     { /* SOC_REG_INT_GE_EGR_PKT_DROP_CTLr */
   9829         soc_block_list[2],
   9830         soc_portreg,
   9831         1,
   9832         0,
   9833         0x301,
   9834         0,
   9835         0,
   9836         1,
   9837         soc_GE_EGR_PKT_DROP_CTLr_fields,
   9838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9839         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9840         -1,
   9841         -1,
   9842     },
   9843 #endif /* chips */
   9844 
   9845 #if defined(BCM_56800_A0)
   9846     { /* SOC_REG_INT_GE_EGR_PKT_DROP_CTL_BCM56800_A0r */
   9847         soc_block_list[9],
   9848         soc_portreg,
   9849         1,
   9850         0,
   9851         0x301,
   9852         0,
   9853         0,
   9854         1,
   9855         soc_GE_EGR_PKT_DROP_CTLr_fields,
   9856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9857         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9858         -1,
   9859         -1,
   9860     },
   9861 #endif /* chips */
   9862 
   9863 #if defined(BCM_56800_A0)
   9864     { /* SOC_REG_INT_GE_GBODE_CELL_CNTr */
   9865         soc_block_list[9],
   9866         soc_portreg,
   9867         1,
   9868         0,
   9869         0xa05,
   9870         SOC_REG_FLAG_RO,
   9871         0,
   9872         1,
   9873         soc_GE_GBODE_CELL_CNTr_fields,
   9874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9875         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9876         -1,
   9877         -1,
   9878     },
   9879 #endif /* chips */
   9880 
   9881 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   9882     defined(BCM_56334_B0)
   9883     { /* SOC_REG_INT_GE_GBODE_CELL_CNT_BCM56334_A0r */
   9884         soc_block_list[14],
   9885         soc_portreg,
   9886         1,
   9887         0,
   9888         0x905,
   9889         SOC_REG_FLAG_RO,
   9890         0,
   9891         1,
   9892         soc_GE_GBODE_CELL_CNT_BCM56624_A0r_fields,
   9893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9894         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9895         -1,
   9896         -1,
   9897     },
   9898 #endif /* chips */
   9899 
   9900 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9901     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9902     { /* SOC_REG_INT_GE_GBODE_CELL_CNT_BCM56624_A0r */
   9903         soc_block_list[205],
   9904         soc_portreg,
   9905         1,
   9906         0,
   9907         0x905,
   9908         SOC_REG_FLAG_RO,
   9909         0,
   9910         1,
   9911         soc_GE_GBODE_CELL_CNT_BCM56624_A0r_fields,
   9912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9913         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9914         -1,
   9915         -1,
   9916     },
   9917 #endif /* chips */
   9918 
   9919 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9920     defined(BCM_56634_A0) || defined(BCM_56634_B0)
   9921     { /* SOC_REG_INT_GE_GBODE_CELL_CNT_BCM56634_A0r */
   9922         soc_block_list[207],
   9923         soc_portreg,
   9924         1,
   9925         0,
   9926         0x905,
   9927         SOC_REG_FLAG_RO,
   9928         0,
   9929         1,
   9930         soc_GE_GBODE_CELL_CNT_BCM56624_A0r_fields,
   9931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9932         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9933         -1,
   9934         -1,
   9935     },
   9936 #endif /* chips */
   9937 
   9938 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9939     { /* SOC_REG_INT_GE_GBODE_CELL_CNT_BCM56685_A0r */
   9940         soc_block_list[209],
   9941         soc_portreg,
   9942         1,
   9943         0,
   9944         0x905,
   9945         SOC_REG_FLAG_RO,
   9946         0,
   9947         1,
   9948         soc_GE_GBODE_CELL_CNT_BCM56624_A0r_fields,
   9949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9950         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9951         -1,
   9952         -1,
   9953     },
   9954 #endif /* chips */
   9955 
   9956 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9957     { /* SOC_REG_INT_GE_GBODE_CELL_CNT_BCM56820_A0r */
   9958         soc_block_list[206],
   9959         soc_portreg,
   9960         1,
   9961         0,
   9962         0x905,
   9963         SOC_REG_FLAG_RO,
   9964         0,
   9965         1,
   9966         soc_GE_GBODE_CELL_CNT_BCM56624_A0r_fields,
   9967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9968         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9969         -1,
   9970         -1,
   9971     },
   9972 #endif /* chips */
   9973 
   9974 #if defined(BCM_56800_A0)
   9975     { /* SOC_REG_INT_GE_GBODE_CELL_REQ_CNTr */
   9976         soc_block_list[9],
   9977         soc_portreg,
   9978         1,
   9979         0,
   9980         0xa06,
   9981         SOC_REG_FLAG_RO,
   9982         0,
   9983         1,
   9984         soc_GE_GBODE_CELL_REQ_CNTr_fields,
   9985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9986         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9987         -1,
   9988         -1,
   9989     },
   9990 #endif /* chips */
   9991 
   9992 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   9993     defined(BCM_56334_B0)
   9994     { /* SOC_REG_INT_GE_GBODE_CELL_REQ_CNT_BCM56334_A0r */
   9995         soc_block_list[14],
   9996         soc_portreg,
   9997         1,
   9998         0,
   9999         0x906,
  10000         SOC_REG_FLAG_RO,
  10001         0,
  10002         1,
  10003         soc_GE_GBODE_CELL_REQ_CNT_BCM56624_A0r_fields,
  10004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10006         -1,
  10007         -1,
  10008     },
  10009 #endif /* chips */
  10010 
  10011 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10012     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  10013     { /* SOC_REG_INT_GE_GBODE_CELL_REQ_CNT_BCM56624_A0r */
  10014         soc_block_list[205],
  10015         soc_portreg,
  10016         1,
  10017         0,
  10018         0x906,
  10019         SOC_REG_FLAG_RO,
  10020         0,
  10021         1,
  10022         soc_GE_GBODE_CELL_REQ_CNT_BCM56624_A0r_fields,
  10023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10024         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10025         -1,
  10026         -1,
  10027     },
  10028 #endif /* chips */
  10029 
  10030 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10031     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  10032     { /* SOC_REG_INT_GE_GBODE_CELL_REQ_CNT_BCM56634_A0r */
  10033         soc_block_list[207],
  10034         soc_portreg,
  10035         1,
  10036         0,
  10037         0x906,
  10038         SOC_REG_FLAG_RO,
  10039         0,
  10040         1,
  10041         soc_GE_GBODE_CELL_REQ_CNT_BCM56624_A0r_fields,
  10042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10044         -1,
  10045         -1,
  10046     },
  10047 #endif /* chips */
  10048 
  10049 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10050     { /* SOC_REG_INT_GE_GBODE_CELL_REQ_CNT_BCM56685_A0r */
  10051         soc_block_list[209],
  10052         soc_portreg,
  10053         1,
  10054         0,
  10055         0x906,
  10056         SOC_REG_FLAG_RO,
  10057         0,
  10058         1,
  10059         soc_GE_GBODE_CELL_REQ_CNT_BCM56624_A0r_fields,
  10060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10061         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10062         -1,
  10063         -1,
  10064     },
  10065 #endif /* chips */
  10066 
  10067 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  10068     { /* SOC_REG_INT_GE_GBODE_CELL_REQ_CNT_BCM56820_A0r */
  10069         soc_block_list[206],
  10070         soc_portreg,
  10071         1,
  10072         0,
  10073         0x906,
  10074         SOC_REG_FLAG_RO,
  10075         0,
  10076         1,
  10077         soc_GE_GBODE_CELL_REQ_CNT_BCM56624_A0r_fields,
  10078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10079         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10080         -1,
  10081         -1,
  10082     },
  10083 #endif /* chips */
  10084 
  10085 #if defined(BCM_56800_A0)
  10086     { /* SOC_REG_INT_GE_GBOD_OVRFLWr */
  10087         soc_block_list[9],
  10088         soc_portreg,
  10089         1,
  10090         0,
  10091         0xa04,
  10092         SOC_REG_FLAG_RO,
  10093         0,
  10094         1,
  10095         soc_GE0_GBOD_OVRFLWr_fields,
  10096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10097         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10098         -1,
  10099         -1,
  10100     },
  10101 #endif /* chips */
  10102 
  10103 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  10104     defined(BCM_56334_B0)
  10105     { /* SOC_REG_INT_GE_GBOD_OVRFLW_BCM56334_A0r */
  10106         soc_block_list[14],
  10107         soc_portreg,
  10108         1,
  10109         0,
  10110         0x904,
  10111         SOC_REG_FLAG_RO,
  10112         0,
  10113         1,
  10114         soc_GE0_GBOD_OVRFLWr_fields,
  10115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10116         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10117         -1,
  10118         -1,
  10119     },
  10120 #endif /* chips */
  10121 
  10122 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10123     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  10124     { /* SOC_REG_INT_GE_GBOD_OVRFLW_BCM56624_A0r */
  10125         soc_block_list[205],
  10126         soc_portreg,
  10127         1,
  10128         0,
  10129         0x904,
  10130         SOC_REG_FLAG_RO,
  10131         0,
  10132         1,
  10133         soc_GE0_GBOD_OVRFLWr_fields,
  10134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10135         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10136         -1,
  10137         -1,
  10138     },
  10139 #endif /* chips */
  10140 
  10141 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10142     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  10143     { /* SOC_REG_INT_GE_GBOD_OVRFLW_BCM56634_A0r */
  10144         soc_block_list[207],
  10145         soc_portreg,
  10146         1,
  10147         0,
  10148         0x904,
  10149         SOC_REG_FLAG_RO,
  10150         0,
  10151         1,
  10152         soc_GE0_GBOD_OVRFLWr_fields,
  10153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10154         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10155         -1,
  10156         -1,
  10157     },
  10158 #endif /* chips */
  10159 
  10160 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10161     { /* SOC_REG_INT_GE_GBOD_OVRFLW_BCM56685_A0r */
  10162         soc_block_list[209],
  10163         soc_portreg,
  10164         1,
  10165         0,
  10166         0x904,
  10167         SOC_REG_FLAG_RO,
  10168         0,
  10169         1,
  10170         soc_GE0_GBOD_OVRFLWr_fields,
  10171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10172         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10173         -1,
  10174         -1,
  10175     },
  10176 #endif /* chips */
  10177 
  10178 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  10179     { /* SOC_REG_INT_GE_GBOD_OVRFLW_BCM56820_A0r */
  10180         soc_block_list[206],
  10181         soc_portreg,
  10182         1,
  10183         0,
  10184         0x904,
  10185         SOC_REG_FLAG_RO,
  10186         0,
  10187         1,
  10188         soc_GE0_GBOD_OVRFLWr_fields,
  10189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10190         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10191         -1,
  10192         -1,
  10193     },
  10194 #endif /* chips */
  10195 
  10196 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  10197     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  10198     { /* SOC_REG_INT_GE_PORT_CONFIGr */
  10199         soc_block_list[2],
  10200         soc_portreg,
  10201         1,
  10202         0,
  10203         0x300,
  10204         0,
  10205         0,
  10206         5,
  10207         soc_GE_PORT_CONFIGr_fields,
  10208         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  10209         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  10210         -1,
  10211         -1,
  10212     },
  10213 #endif /* chips */
  10214 
  10215 #if defined(BCM_56800_A0)
  10216     { /* SOC_REG_INT_GE_PORT_CONFIG_BCM56800_A0r */
  10217         soc_block_list[9],
  10218         soc_portreg,
  10219         1,
  10220         0,
  10221         0x300,
  10222         0,
  10223         0,
  10224         5,
  10225         soc_GE_PORT_CONFIGr_fields,
  10226         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  10227         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  10228         -1,
  10229         -1,
  10230     },
  10231 #endif /* chips */
  10232 
  10233 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10234     { /* SOC_REG_INT_GINTEr */
  10235         soc_block_list[81],
  10236         soc_genreg,
  10237         1,
  10238         0,
  10239         0x80010,
  10240         0,
  10241         0,
  10242         8,
  10243         soc_GINTEr_fields,
  10244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10245         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10246         -1,
  10247         -1,
  10248     },
  10249 #endif /* chips */
  10250 
  10251 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10252     { /* SOC_REG_INT_GINTSr */
  10253         soc_block_list[81],
  10254         soc_genreg,
  10255         1,
  10256         0,
  10257         0x80012,
  10258         0,
  10259         0,
  10260         8,
  10261         soc_GINTSr_fields,
  10262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10264         -1,
  10265         -1,
  10266     },
  10267 #endif /* chips */
  10268 
  10269 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10270     { /* SOC_REG_INT_GLB_PKTBUF_CTLr */
  10271         soc_block_list[201],
  10272         soc_genreg,
  10273         1,
  10274         0,
  10275         0x2000e00,
  10276         0,
  10277         0,
  10278         4,
  10279         soc_GLB_PKTBUF_CTLr_fields,
  10280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10281         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10282         -1,
  10283         -1,
  10284     },
  10285 #endif /* chips */
  10286 
  10287 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10288     { /* SOC_REG_INT_GLB_PKTBUF_STSr */
  10289         soc_block_list[201],
  10290         soc_genreg,
  10291         1,
  10292         0,
  10293         0x2000f00,
  10294         SOC_REG_FLAG_RO,
  10295         0,
  10296         11,
  10297         soc_GLB_PKTBUF_STSr_fields,
  10298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10300         -1,
  10301         -1,
  10302     },
  10303 #endif /* chips */
  10304 
  10305 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10306     defined(BCM_56450_B1)
  10307     { /* SOC_REG_INT_GLOBAL_EMIRROR_DROP_COUNT_64r */
  10308         soc_block_list[4],
  10309         soc_genreg,
  10310         1,
  10311         0,
  10312         0xe010000,
  10313         SOC_REG_FLAG_64_BITS,
  10314         0,
  10315         2,
  10316         soc_GLOBAL_EMIRROR_DROP_COUNT_64r_fields,
  10317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10318         SOC_RESET_MASK_DEC(0xffffffff, 0x3fffffff)
  10319         -1,
  10320         -1,
  10321     },
  10322 #endif /* chips */
  10323 
  10324 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10325     defined(BCM_56270_A0)
  10326     { /* SOC_REG_INT_GLOBAL_EMIRROR_DROP_COUNT_64_BCM56260_A0r */
  10327         soc_block_list[4],
  10328         soc_genreg,
  10329         1,
  10330         0,
  10331         0xe010000,
  10332         SOC_REG_FLAG_64_BITS,
  10333         0,
  10334         2,
  10335         soc_GLOBAL_EMIRROR_DROP_COUNT_64_BCM56260_A0r_fields,
  10336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10337         SOC_RESET_MASK_DEC(0xffffffff, 0x3fffffff)
  10338         -1,
  10339         -1,
  10340     },
  10341 #endif /* chips */
  10342 
  10343 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  10344     defined(BCM_56820_A0)
  10345     { /* SOC_REG_INT_GLOBAL_HDRM_COUNTr */
  10346         soc_block_list[4],
  10347         soc_genreg,
  10348         1,
  10349         0,
  10350         0x2080042,
  10351         SOC_REG_FLAG_RO,
  10352         0,
  10353         1,
  10354         soc_GLOBAL_HDRM_COUNTr_fields,
  10355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10356         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10357         -1,
  10358         -1,
  10359     },
  10360 #endif /* chips */
  10361 
  10362 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10363     defined(BCM_56270_A0)
  10364     { /* SOC_REG_INT_GLOBAL_HDRM_COUNT_BCM56260_A0r */
  10365         soc_block_list[4],
  10366         soc_genreg,
  10367         1,
  10368         0,
  10369         0xa007b00,
  10370         SOC_REG_FLAG_RO,
  10371         0,
  10372         1,
  10373         soc_GLOBAL_HDRM_COUNT_BCM56260_A0r_fields,
  10374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10375         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10376         -1,
  10377         -1,
  10378     },
  10379 #endif /* chips */
  10380 
  10381 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  10382     { /* SOC_REG_INT_GLOBAL_HDRM_COUNT_BCM56334_A0r */
  10383         soc_block_list[4],
  10384         soc_genreg,
  10385         1,
  10386         0,
  10387         0x208007b,
  10388         SOC_REG_FLAG_RO,
  10389         0,
  10390         1,
  10391         soc_GLOBAL_HDRM_COUNTr_fields,
  10392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10393         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10394         -1,
  10395         -1,
  10396     },
  10397 #endif /* chips */
  10398 
  10399 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10400     { /* SOC_REG_INT_GLOBAL_HDRM_COUNT_BCM56440_A0r */
  10401         soc_block_list[4],
  10402         soc_genreg,
  10403         1,
  10404         0,
  10405         0x208007b,
  10406         SOC_REG_FLAG_RO,
  10407         0,
  10408         1,
  10409         soc_GLOBAL_HDRM_COUNT_BCM56440_A0r_fields,
  10410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10411         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  10412         -1,
  10413         -1,
  10414     },
  10415 #endif /* chips */
  10416 
  10417 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10418     defined(BCM_56450_B1)
  10419     { /* SOC_REG_INT_GLOBAL_HDRM_COUNT_BCM56450_A0r */
  10420         soc_block_list[4],
  10421         soc_genreg,
  10422         1,
  10423         0,
  10424         0xa007b00,
  10425         SOC_REG_FLAG_RO,
  10426         0,
  10427         1,
  10428         soc_GLOBAL_HDRM_COUNT_BCM56450_A0r_fields,
  10429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10430         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  10431         -1,
  10432         -1,
  10433     },
  10434 #endif /* chips */
  10435 
  10436 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10437     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10438     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10439     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  10440     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10441     { /* SOC_REG_INT_GLOBAL_HDRM_COUNT_BCM56624_A0r */
  10442         soc_block_list[4],
  10443         soc_genreg,
  10444         1,
  10445         0,
  10446         0x208007b,
  10447         SOC_REG_FLAG_RO,
  10448         0,
  10449         1,
  10450         soc_GLOBAL_HDRM_COUNT_BCM56624_A0r_fields,
  10451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10452         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10453         -1,
  10454         -1,
  10455     },
  10456 #endif /* chips */
  10457 
  10458 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \
  10459     defined(BCM_56850_A0) || defined(BCM_56860_A0)
  10460     { /* SOC_REG_INT_GLOBAL_HDRM_COUNT_BCM56640_A0r */
  10461         soc_block_list[4],
  10462         soc_genreg,
  10463         1,
  10464         0,
  10465         0xa007b00,
  10466         SOC_REG_FLAG_RO,
  10467         0,
  10468         1,
  10469         soc_GLOBAL_HDRM_COUNT_BCM56640_A0r_fields,
  10470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10471         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10472         -1,
  10473         -1,
  10474     },
  10475 #endif /* chips */
  10476 
  10477 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  10478     { /* SOC_REG_INT_GLOBAL_HDRM_COUNT_BCM56840_A0r */
  10479         soc_block_list[4],
  10480         soc_genreg,
  10481         1,
  10482         0,
  10483         0x208007b,
  10484         SOC_REG_FLAG_RO,
  10485         0,
  10486         1,
  10487         soc_GLOBAL_HDRM_COUNT_BCM56840_A0r_fields,
  10488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10489         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10490         -1,
  10491         -1,
  10492     },
  10493 #endif /* chips */
  10494 
  10495 #if defined(BCM_88732_A0)
  10496     { /* SOC_REG_INT_GLOBAL_HDRM_COUNT_BCM88732_A0r */
  10497         soc_block_list[4],
  10498         soc_genreg,
  10499         1,
  10500         0,
  10501         0x2080042,
  10502         SOC_REG_FLAG_RO,
  10503         0,
  10504         1,
  10505         soc_GLOBAL_HDRM_COUNT_BCM88732_A0r_fields,
  10506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10507         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  10508         -1,
  10509         -1,
  10510     },
  10511 #endif /* chips */
  10512 
  10513 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  10514     defined(BCM_56820_A0)
  10515     { /* SOC_REG_INT_GLOBAL_HDRM_LIMITr */
  10516         soc_block_list[4],
  10517         soc_genreg,
  10518         1,
  10519         0,
  10520         0x2080001,
  10521         0,
  10522         0,
  10523         1,
  10524         soc_GLOBAL_HDRM_LIMITr_fields,
  10525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10526         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10527         -1,
  10528         -1,
  10529     },
  10530 #endif /* chips */
  10531 
  10532 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10533     defined(BCM_56270_A0)
  10534     { /* SOC_REG_INT_GLOBAL_HDRM_LIMIT_BCM56260_A0r */
  10535         soc_block_list[4],
  10536         soc_genreg,
  10537         1,
  10538         0,
  10539         0xa000600,
  10540         0,
  10541         0,
  10542         1,
  10543         soc_GLOBAL_HDRM_LIMIT_BCM56260_A0r_fields,
  10544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10545         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10546         -1,
  10547         -1,
  10548     },
  10549 #endif /* chips */
  10550 
  10551 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  10552     { /* SOC_REG_INT_GLOBAL_HDRM_LIMIT_BCM56334_A0r */
  10553         soc_block_list[4],
  10554         soc_genreg,
  10555         1,
  10556         0,
  10557         0x2080002,
  10558         0,
  10559         0,
  10560         1,
  10561         soc_GLOBAL_HDRM_LIMITr_fields,
  10562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10563         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10564         -1,
  10565         -1,
  10566     },
  10567 #endif /* chips */
  10568 
  10569 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10570     { /* SOC_REG_INT_GLOBAL_HDRM_LIMIT_BCM56440_A0r */
  10571         soc_block_list[4],
  10572         soc_genreg,
  10573         1,
  10574         0,
  10575         0x2080002,
  10576         0,
  10577         0,
  10578         1,
  10579         soc_GLOBAL_HDRM_LIMIT_BCM56440_A0r_fields,
  10580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10581         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  10582         -1,
  10583         -1,
  10584     },
  10585 #endif /* chips */
  10586 
  10587 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10588     defined(BCM_56450_B1)
  10589     { /* SOC_REG_INT_GLOBAL_HDRM_LIMIT_BCM56450_A0r */
  10590         soc_block_list[4],
  10591         soc_genreg,
  10592         1,
  10593         0,
  10594         0xa000600,
  10595         0,
  10596         0,
  10597         1,
  10598         soc_GLOBAL_HDRM_LIMIT_BCM56450_A0r_fields,
  10599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10600         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  10601         -1,
  10602         -1,
  10603     },
  10604 #endif /* chips */
  10605 
  10606 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10607     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10608     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10609     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  10610     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10611     { /* SOC_REG_INT_GLOBAL_HDRM_LIMIT_BCM56624_A0r */
  10612         soc_block_list[4],
  10613         soc_genreg,
  10614         1,
  10615         0,
  10616         0x2080002,
  10617         0,
  10618         0,
  10619         1,
  10620         soc_GLOBAL_HDRM_LIMIT_BCM56624_A0r_fields,
  10621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10622         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10623         -1,
  10624         -1,
  10625     },
  10626 #endif /* chips */
  10627 
  10628 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  10629     { /* SOC_REG_INT_GLOBAL_HDRM_LIMIT_BCM56640_A0r */
  10630         soc_block_list[4],
  10631         soc_genreg,
  10632         1,
  10633         0,
  10634         0xa000600,
  10635         0,
  10636         0,
  10637         1,
  10638         soc_GLOBAL_HDRM_LIMIT_BCM56640_A0r_fields,
  10639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10640         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10641         -1,
  10642         -1,
  10643     },
  10644 #endif /* chips */
  10645 
  10646 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  10647     { /* SOC_REG_INT_GLOBAL_HDRM_LIMIT_BCM56840_A0r */
  10648         soc_block_list[4],
  10649         soc_genreg,
  10650         1,
  10651         0,
  10652         0x2080002,
  10653         0,
  10654         0,
  10655         1,
  10656         soc_GLOBAL_HDRM_LIMIT_BCM56840_A0r_fields,
  10657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10658         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10659         -1,
  10660         -1,
  10661     },
  10662 #endif /* chips */
  10663 
  10664 #if defined(BCM_88732_A0)
  10665     { /* SOC_REG_INT_GLOBAL_HDRM_LIMIT_BCM88732_A0r */
  10666         soc_block_list[4],
  10667         soc_genreg,
  10668         1,
  10669         0,
  10670         0x2080001,
  10671         0,
  10672         0,
  10673         1,
  10674         soc_GLOBAL_HDRM_LIMIT_BCM88732_A0r_fields,
  10675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10676         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  10677         -1,
  10678         -1,
  10679     },
  10680 #endif /* chips */
  10681 
  10682 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  10683     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10684     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  10685     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWERr */
  10686         soc_block_list[5],
  10687         soc_genreg,
  10688         1,
  10689         0,
  10690         0x2080031,
  10691         0,
  10692         0,
  10693         1,
  10694         soc_GLOBAL_MPLS_RANGE_1_LOWERr_fields,
  10695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10696         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10697         -1,
  10698         -1,
  10699     },
  10700 #endif /* chips */
  10701 
  10702 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10703     defined(BCM_56270_A0)
  10704     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56260_A0r */
  10705         soc_block_list[5],
  10706         soc_genreg,
  10707         1,
  10708         0,
  10709         0xa000f00,
  10710         0,
  10711         0,
  10712         1,
  10713         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  10714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10715         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10716         -1,
  10717         -1,
  10718     },
  10719 #endif /* chips */
  10720 
  10721 #if defined(BCM_56370_A0)
  10722     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56370_A0r */
  10723         soc_block_list[5],
  10724         soc_genreg,
  10725         1,
  10726         0,
  10727         0x56002000,
  10728         0,
  10729         0,
  10730         1,
  10731         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  10732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10733         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10734         -1,
  10735         -1,
  10736         0,
  10737     },
  10738 #endif /* chips */
  10739 
  10740 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10741     defined(BCM_56450_B1)
  10742     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56450_A0r */
  10743         soc_block_list[5],
  10744         soc_genreg,
  10745         1,
  10746         0,
  10747         0xa000f00,
  10748         0,
  10749         0,
  10750         1,
  10751         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  10752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10753         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10754         -1,
  10755         -1,
  10756     },
  10757 #endif /* chips */
  10758 
  10759 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  10760     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10761     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56560_A0r */
  10762         soc_block_list[5],
  10763         soc_genreg,
  10764         1,
  10765         0,
  10766         0xa003200,
  10767         0,
  10768         0,
  10769         1,
  10770         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  10771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10772         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10773         -1,
  10774         -1,
  10775     },
  10776 #endif /* chips */
  10777 
  10778 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  10779     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r */
  10780         soc_block_list[5],
  10781         soc_genreg,
  10782         1,
  10783         0,
  10784         0xa000e00,
  10785         0,
  10786         0,
  10787         1,
  10788         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  10789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10790         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10791         -1,
  10792         -1,
  10793     },
  10794 #endif /* chips */
  10795 
  10796 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  10797     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  10798     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56840_A0r */
  10799         soc_block_list[5],
  10800         soc_genreg,
  10801         1,
  10802         0,
  10803         0x2080632,
  10804         0,
  10805         0,
  10806         1,
  10807         soc_GLOBAL_MPLS_RANGE_1_LOWERr_fields,
  10808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10809         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10810         -1,
  10811         -1,
  10812     },
  10813 #endif /* chips */
  10814 
  10815 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  10816     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56850_A0r */
  10817         soc_block_list[5],
  10818         soc_genreg,
  10819         1,
  10820         0,
  10821         0xa003200,
  10822         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10823         0,
  10824         1,
  10825         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  10826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10827         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10828         -1,
  10829         -1,
  10830     },
  10831 #endif /* chips */
  10832 
  10833 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  10834     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56870_A0r */
  10835         soc_block_list[5],
  10836         soc_genreg,
  10837         1,
  10838         0,
  10839         0x56002000,
  10840         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10841         0,
  10842         1,
  10843         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  10844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10845         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10846         -1,
  10847         -1,
  10848         0,
  10849     },
  10850 #endif /* chips */
  10851 
  10852 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10853     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r */
  10854         soc_block_list[5],
  10855         soc_genreg,
  10856         1,
  10857         0,
  10858         0x2e000400,
  10859         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10860         0,
  10861         1,
  10862         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  10863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10864         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10865         -1,
  10866         -1,
  10867         0,
  10868     },
  10869 #endif /* chips */
  10870 
  10871 #if defined(BCM_56970_A0)
  10872     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56970_A0r */
  10873         soc_block_list[5],
  10874         soc_genreg,
  10875         1,
  10876         0,
  10877         0x52000400,
  10878         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10879         0,
  10880         1,
  10881         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  10882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10883         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10884         -1,
  10885         -1,
  10886         0,
  10887     },
  10888 #endif /* chips */
  10889 
  10890 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10891     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_LOWER_BCM56980_A0r */
  10892         soc_block_list[5],
  10893         soc_genreg,
  10894         1,
  10895         0,
  10896         0x6000f00,
  10897         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10898         0,
  10899         1,
  10900         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  10901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10902         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10903         -1,
  10904         -1,
  10905         3,
  10906     },
  10907 #endif /* chips */
  10908 
  10909 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  10910     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10911     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10912     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10913     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  10914     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10915     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPERr */
  10916         soc_block_list[5],
  10917         soc_genreg,
  10918         1,
  10919         0,
  10920         0x2080032,
  10921         0,
  10922         0,
  10923         1,
  10924         soc_GLOBAL_MPLS_RANGE_1_LOWERr_fields,
  10925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10926         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10927         -1,
  10928         -1,
  10929     },
  10930 #endif /* chips */
  10931 
  10932 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10933     defined(BCM_56270_A0)
  10934     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56260_A0r */
  10935         soc_block_list[5],
  10936         soc_genreg,
  10937         1,
  10938         0,
  10939         0xa001000,
  10940         0,
  10941         0,
  10942         1,
  10943         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  10944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10945         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10946         -1,
  10947         -1,
  10948     },
  10949 #endif /* chips */
  10950 
  10951 #if defined(BCM_56370_A0)
  10952     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56370_A0r */
  10953         soc_block_list[5],
  10954         soc_genreg,
  10955         1,
  10956         0,
  10957         0x56002100,
  10958         0,
  10959         0,
  10960         1,
  10961         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  10962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10963         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10964         -1,
  10965         -1,
  10966         0,
  10967     },
  10968 #endif /* chips */
  10969 
  10970 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10971     defined(BCM_56450_B1)
  10972     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56450_A0r */
  10973         soc_block_list[5],
  10974         soc_genreg,
  10975         1,
  10976         0,
  10977         0xa001000,
  10978         0,
  10979         0,
  10980         1,
  10981         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  10982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10983         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  10984         -1,
  10985         -1,
  10986     },
  10987 #endif /* chips */
  10988 
  10989 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  10990     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10991     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56560_A0r */
  10992         soc_block_list[5],
  10993         soc_genreg,
  10994         1,
  10995         0,
  10996         0xa003300,
  10997         0,
  10998         0,
  10999         1,
  11000         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11002         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11003         -1,
  11004         -1,
  11005     },
  11006 #endif /* chips */
  11007 
  11008 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  11009     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56640_A0r */
  11010         soc_block_list[5],
  11011         soc_genreg,
  11012         1,
  11013         0,
  11014         0xa000f00,
  11015         0,
  11016         0,
  11017         1,
  11018         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  11019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11020         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11021         -1,
  11022         -1,
  11023     },
  11024 #endif /* chips */
  11025 
  11026 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  11027     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11028     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56840_A0r */
  11029         soc_block_list[5],
  11030         soc_genreg,
  11031         1,
  11032         0,
  11033         0x2080633,
  11034         0,
  11035         0,
  11036         1,
  11037         soc_GLOBAL_MPLS_RANGE_1_LOWERr_fields,
  11038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11039         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11040         -1,
  11041         -1,
  11042     },
  11043 #endif /* chips */
  11044 
  11045 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  11046     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56850_A0r */
  11047         soc_block_list[5],
  11048         soc_genreg,
  11049         1,
  11050         0,
  11051         0xa003300,
  11052         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11053         0,
  11054         1,
  11055         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  11056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11057         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11058         -1,
  11059         -1,
  11060     },
  11061 #endif /* chips */
  11062 
  11063 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  11064     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56870_A0r */
  11065         soc_block_list[5],
  11066         soc_genreg,
  11067         1,
  11068         0,
  11069         0x56002100,
  11070         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11071         0,
  11072         1,
  11073         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11075         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11076         -1,
  11077         -1,
  11078         0,
  11079     },
  11080 #endif /* chips */
  11081 
  11082 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11083     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56960_A0r */
  11084         soc_block_list[5],
  11085         soc_genreg,
  11086         1,
  11087         0,
  11088         0x2e000500,
  11089         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11090         0,
  11091         1,
  11092         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11094         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11095         -1,
  11096         -1,
  11097         0,
  11098     },
  11099 #endif /* chips */
  11100 
  11101 #if defined(BCM_56970_A0)
  11102     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56970_A0r */
  11103         soc_block_list[5],
  11104         soc_genreg,
  11105         1,
  11106         0,
  11107         0x52000500,
  11108         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11109         0,
  11110         1,
  11111         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11113         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11114         -1,
  11115         -1,
  11116         0,
  11117     },
  11118 #endif /* chips */
  11119 
  11120 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11121     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_1_UPPER_BCM56980_A0r */
  11122         soc_block_list[5],
  11123         soc_genreg,
  11124         1,
  11125         0,
  11126         0x6001000,
  11127         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11128         0,
  11129         1,
  11130         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11132         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11133         -1,
  11134         -1,
  11135         3,
  11136     },
  11137 #endif /* chips */
  11138 
  11139 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  11140     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11141     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11142     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11143     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11144     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11145     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWERr */
  11146         soc_block_list[5],
  11147         soc_genreg,
  11148         1,
  11149         0,
  11150         0x2080033,
  11151         0,
  11152         0,
  11153         1,
  11154         soc_GLOBAL_MPLS_RANGE_1_LOWERr_fields,
  11155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11156         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11157         -1,
  11158         -1,
  11159     },
  11160 #endif /* chips */
  11161 
  11162 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  11163     defined(BCM_56270_A0)
  11164     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56260_A0r */
  11165         soc_block_list[5],
  11166         soc_genreg,
  11167         1,
  11168         0,
  11169         0xa001100,
  11170         0,
  11171         0,
  11172         1,
  11173         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11175         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11176         -1,
  11177         -1,
  11178     },
  11179 #endif /* chips */
  11180 
  11181 #if defined(BCM_56370_A0)
  11182     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56370_A0r */
  11183         soc_block_list[5],
  11184         soc_genreg,
  11185         1,
  11186         0,
  11187         0x56002200,
  11188         0,
  11189         0,
  11190         1,
  11191         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11193         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11194         -1,
  11195         -1,
  11196         0,
  11197     },
  11198 #endif /* chips */
  11199 
  11200 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11201     defined(BCM_56450_B1)
  11202     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56450_A0r */
  11203         soc_block_list[5],
  11204         soc_genreg,
  11205         1,
  11206         0,
  11207         0xa001100,
  11208         0,
  11209         0,
  11210         1,
  11211         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  11212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11213         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11214         -1,
  11215         -1,
  11216     },
  11217 #endif /* chips */
  11218 
  11219 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  11220     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  11221     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56560_A0r */
  11222         soc_block_list[5],
  11223         soc_genreg,
  11224         1,
  11225         0,
  11226         0xa003400,
  11227         0,
  11228         0,
  11229         1,
  11230         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11232         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11233         -1,
  11234         -1,
  11235     },
  11236 #endif /* chips */
  11237 
  11238 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  11239     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56640_A0r */
  11240         soc_block_list[5],
  11241         soc_genreg,
  11242         1,
  11243         0,
  11244         0xa001000,
  11245         0,
  11246         0,
  11247         1,
  11248         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  11249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11250         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11251         -1,
  11252         -1,
  11253     },
  11254 #endif /* chips */
  11255 
  11256 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  11257     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11258     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56840_A0r */
  11259         soc_block_list[5],
  11260         soc_genreg,
  11261         1,
  11262         0,
  11263         0x2080634,
  11264         0,
  11265         0,
  11266         1,
  11267         soc_GLOBAL_MPLS_RANGE_1_LOWERr_fields,
  11268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11269         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11270         -1,
  11271         -1,
  11272     },
  11273 #endif /* chips */
  11274 
  11275 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  11276     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56850_A0r */
  11277         soc_block_list[5],
  11278         soc_genreg,
  11279         1,
  11280         0,
  11281         0xa003400,
  11282         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11283         0,
  11284         1,
  11285         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  11286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11287         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11288         -1,
  11289         -1,
  11290     },
  11291 #endif /* chips */
  11292 
  11293 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  11294     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56870_A0r */
  11295         soc_block_list[5],
  11296         soc_genreg,
  11297         1,
  11298         0,
  11299         0x56002200,
  11300         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11301         0,
  11302         1,
  11303         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11305         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11306         -1,
  11307         -1,
  11308         0,
  11309     },
  11310 #endif /* chips */
  11311 
  11312 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11313     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56960_A0r */
  11314         soc_block_list[5],
  11315         soc_genreg,
  11316         1,
  11317         0,
  11318         0x2e000600,
  11319         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11320         0,
  11321         1,
  11322         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11324         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11325         -1,
  11326         -1,
  11327         0,
  11328     },
  11329 #endif /* chips */
  11330 
  11331 #if defined(BCM_56970_A0)
  11332     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56970_A0r */
  11333         soc_block_list[5],
  11334         soc_genreg,
  11335         1,
  11336         0,
  11337         0x52000600,
  11338         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11339         0,
  11340         1,
  11341         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11343         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11344         -1,
  11345         -1,
  11346         0,
  11347     },
  11348 #endif /* chips */
  11349 
  11350 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11351     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_LOWER_BCM56980_A0r */
  11352         soc_block_list[5],
  11353         soc_genreg,
  11354         1,
  11355         0,
  11356         0x6001100,
  11357         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11358         0,
  11359         1,
  11360         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11362         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11363         -1,
  11364         -1,
  11365         3,
  11366     },
  11367 #endif /* chips */
  11368 
  11369 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  11370     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11371     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11372     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11373     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11374     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11375     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPERr */
  11376         soc_block_list[5],
  11377         soc_genreg,
  11378         1,
  11379         0,
  11380         0x2080034,
  11381         0,
  11382         0,
  11383         1,
  11384         soc_GLOBAL_MPLS_RANGE_1_LOWERr_fields,
  11385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11386         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11387         -1,
  11388         -1,
  11389     },
  11390 #endif /* chips */
  11391 
  11392 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  11393     defined(BCM_56270_A0)
  11394     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56260_A0r */
  11395         soc_block_list[5],
  11396         soc_genreg,
  11397         1,
  11398         0,
  11399         0xa001200,
  11400         0,
  11401         0,
  11402         1,
  11403         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11405         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11406         -1,
  11407         -1,
  11408     },
  11409 #endif /* chips */
  11410 
  11411 #if defined(BCM_56370_A0)
  11412     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56370_A0r */
  11413         soc_block_list[5],
  11414         soc_genreg,
  11415         1,
  11416         0,
  11417         0x56002300,
  11418         0,
  11419         0,
  11420         1,
  11421         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11423         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11424         -1,
  11425         -1,
  11426         0,
  11427     },
  11428 #endif /* chips */
  11429 
  11430 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11431     defined(BCM_56450_B1)
  11432     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56450_A0r */
  11433         soc_block_list[5],
  11434         soc_genreg,
  11435         1,
  11436         0,
  11437         0xa001200,
  11438         0,
  11439         0,
  11440         1,
  11441         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  11442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11443         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11444         -1,
  11445         -1,
  11446     },
  11447 #endif /* chips */
  11448 
  11449 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  11450     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  11451     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56560_A0r */
  11452         soc_block_list[5],
  11453         soc_genreg,
  11454         1,
  11455         0,
  11456         0xa003500,
  11457         0,
  11458         0,
  11459         1,
  11460         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11462         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11463         -1,
  11464         -1,
  11465     },
  11466 #endif /* chips */
  11467 
  11468 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11469     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11470     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11471     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56634_A0r */
  11472         soc_block_list[5],
  11473         soc_genreg,
  11474         1,
  11475         0,
  11476         0x2080035,
  11477         0,
  11478         0,
  11479         1,
  11480         soc_GLOBAL_MPLS_RANGE_1_LOWERr_fields,
  11481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11482         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11483         -1,
  11484         -1,
  11485     },
  11486 #endif /* chips */
  11487 
  11488 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  11489     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56640_A0r */
  11490         soc_block_list[5],
  11491         soc_genreg,
  11492         1,
  11493         0,
  11494         0xa001100,
  11495         0,
  11496         0,
  11497         1,
  11498         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  11499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11500         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11501         -1,
  11502         -1,
  11503     },
  11504 #endif /* chips */
  11505 
  11506 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  11507     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11508     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56840_A0r */
  11509         soc_block_list[5],
  11510         soc_genreg,
  11511         1,
  11512         0,
  11513         0x2080635,
  11514         0,
  11515         0,
  11516         1,
  11517         soc_GLOBAL_MPLS_RANGE_1_LOWERr_fields,
  11518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11519         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11520         -1,
  11521         -1,
  11522     },
  11523 #endif /* chips */
  11524 
  11525 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  11526     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56850_A0r */
  11527         soc_block_list[5],
  11528         soc_genreg,
  11529         1,
  11530         0,
  11531         0xa003500,
  11532         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11533         0,
  11534         1,
  11535         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56640_A0r_fields,
  11536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11537         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11538         -1,
  11539         -1,
  11540     },
  11541 #endif /* chips */
  11542 
  11543 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  11544     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56870_A0r */
  11545         soc_block_list[5],
  11546         soc_genreg,
  11547         1,
  11548         0,
  11549         0x56002300,
  11550         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11551         0,
  11552         1,
  11553         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11555         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11556         -1,
  11557         -1,
  11558         0,
  11559     },
  11560 #endif /* chips */
  11561 
  11562 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11563     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56960_A0r */
  11564         soc_block_list[5],
  11565         soc_genreg,
  11566         1,
  11567         0,
  11568         0x2e000700,
  11569         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11570         0,
  11571         1,
  11572         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11574         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11575         -1,
  11576         -1,
  11577         0,
  11578     },
  11579 #endif /* chips */
  11580 
  11581 #if defined(BCM_56970_A0)
  11582     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56970_A0r */
  11583         soc_block_list[5],
  11584         soc_genreg,
  11585         1,
  11586         0,
  11587         0x52000700,
  11588         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11589         0,
  11590         1,
  11591         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11593         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11594         -1,
  11595         -1,
  11596         0,
  11597     },
  11598 #endif /* chips */
  11599 
  11600 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11601     { /* SOC_REG_INT_GLOBAL_MPLS_RANGE_2_UPPER_BCM56980_A0r */
  11602         soc_block_list[5],
  11603         soc_genreg,
  11604         1,
  11605         0,
  11606         0x6001200,
  11607         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11608         0,
  11609         1,
  11610         soc_GLOBAL_MPLS_RANGE_1_LOWER_BCM56960_A0r_fields,
  11611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11612         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11613         -1,
  11614         -1,
  11615         3,
  11616     },
  11617 #endif /* chips */
  11618 
  11619 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11620     { /* SOC_REG_INT_GLOBAL_SHARED_FILL_STATE_CONFIGr */
  11621         soc_block_list[4],
  11622         soc_genreg,
  11623         1,
  11624         0,
  11625         0x308000a,
  11626         0,
  11627         0,
  11628         1,
  11629         soc_GLOBAL_SHARED_FILL_STATE_CONFIGr_fields,
  11630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11631         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  11632         -1,
  11633         -1,
  11634     },
  11635 #endif /* chips */
  11636 
  11637 #if defined(BCM_88732_A0)
  11638     { /* SOC_REG_INT_GLOBAL_SHARED_FILL_STATE_CONFIG_BCM88732_A0r */
  11639         soc_block_list[4],
  11640         soc_genreg,
  11641         1,
  11642         0,
  11643         0x308000b,
  11644         0,
  11645         0,
  11646         1,
  11647         soc_GLOBAL_SHARED_FILL_STATE_CONFIGr_fields,
  11648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11649         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  11650         -1,
  11651         -1,
  11652     },
  11653 #endif /* chips */
  11654 
  11655 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11656     { /* SOC_REG_INT_GLOBAL_SP_WRED_AVG_QSIZEr */
  11657         soc_block_list[4],
  11658         soc_genreg,
  11659         4,
  11660         0,
  11661         0x1708000c,
  11662         SOC_REG_FLAG_ARRAY,
  11663         0,
  11664         3,
  11665         soc_GLOBAL_SP_WRED_AVG_QSIZEr_fields,
  11666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11667         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11668         -1,
  11669         -1,
  11670     },
  11671 #endif /* chips */
  11672 
  11673 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11674     { /* SOC_REG_INT_GLOBAL_SP_WRED_CONFIGr */
  11675         soc_block_list[4],
  11676         soc_genreg,
  11677         4,
  11678         0,
  11679         0x17080008,
  11680         SOC_REG_FLAG_ARRAY,
  11681         0,
  11682         7,
  11683         soc_GLOBAL_SP_WRED_CONFIGr_fields,
  11684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11685         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  11686         -1,
  11687         -1,
  11688     },
  11689 #endif /* chips */
  11690 
  11691 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  11692     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11693     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11694     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11695     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11696     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11697     { /* SOC_REG_INT_GLOBAL_WREDAVGQSIZE_CELLr */
  11698         soc_block_list[4],
  11699         soc_genreg,
  11700         1,
  11701         0,
  11702         0x17080008,
  11703         0,
  11704         0,
  11705         2,
  11706         soc_GLOBAL_WREDAVGQSIZE_CELLr_fields,
  11707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11708         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  11709         -1,
  11710         -1,
  11711     },
  11712 #endif /* chips */
  11713 
  11714 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11715     { /* SOC_REG_INT_GLOBAL_WREDAVGQSIZE_CELL_BCM56820_A0r */
  11716         soc_block_list[4],
  11717         soc_genreg,
  11718         1,
  11719         0,
  11720         0x12080008,
  11721         0,
  11722         0,
  11723         2,
  11724         soc_GLOBAL_WREDAVGQSIZE_CELLr_fields,
  11725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11726         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  11727         -1,
  11728         -1,
  11729     },
  11730 #endif /* chips */
  11731 
  11732 #if defined(BCM_88732_A0)
  11733     { /* SOC_REG_INT_GLOBAL_WREDAVGQSIZE_CELL_BCM88732_A0r */
  11734         soc_block_list[4],
  11735         soc_genreg,
  11736         1,
  11737         0,
  11738         0x1208000c,
  11739         0,
  11740         0,
  11741         1,
  11742         soc_GLOBAL_WREDAVGQSIZE_CELL_BCM88732_A0r_fields,
  11743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11744         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11745         -1,
  11746         -1,
  11747     },
  11748 #endif /* chips */
  11749 
  11750 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  11751     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11752     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11753     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11754     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11755     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11756     { /* SOC_REG_INT_GLOBAL_WREDAVGQSIZE_PACKETr */
  11757         soc_block_list[4],
  11758         soc_genreg,
  11759         1,
  11760         0,
  11761         0x1708000e,
  11762         0,
  11763         0,
  11764         2,
  11765         soc_GLOBAL_WREDAVGQSIZE_PACKETr_fields,
  11766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11767         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  11768         -1,
  11769         -1,
  11770     },
  11771 #endif /* chips */
  11772 
  11773 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  11774     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11775     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11776     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11777     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11778     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11779     { /* SOC_REG_INT_GLOBAL_WREDCONFIG_CELLr */
  11780         soc_block_list[4],
  11781         soc_genreg,
  11782         1,
  11783         0,
  11784         0x17080007,
  11785         0,
  11786         0,
  11787         8,
  11788         soc_GLOBAL_WREDCONFIG_CELLr_fields,
  11789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11790         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11791         -1,
  11792         -1,
  11793     },
  11794 #endif /* chips */
  11795 
  11796 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11797     { /* SOC_REG_INT_GLOBAL_WREDCONFIG_CELL_BCM56820_A0r */
  11798         soc_block_list[4],
  11799         soc_genreg,
  11800         1,
  11801         0,
  11802         0x12080007,
  11803         0,
  11804         0,
  11805         8,
  11806         soc_GLOBAL_WREDCONFIG_CELLr_fields,
  11807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11808         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11809         -1,
  11810         -1,
  11811     },
  11812 #endif /* chips */
  11813 
  11814 #if defined(BCM_88732_A0)
  11815     { /* SOC_REG_INT_GLOBAL_WREDCONFIG_CELL_BCM88732_A0r */
  11816         soc_block_list[4],
  11817         soc_genreg,
  11818         1,
  11819         0,
  11820         0x1208000b,
  11821         0,
  11822         0,
  11823         8,
  11824         soc_GLOBAL_WREDCONFIG_CELL_BCM88732_A0r_fields,
  11825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11826         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  11827         -1,
  11828         -1,
  11829     },
  11830 #endif /* chips */
  11831 
  11832 #if defined(BCM_88732_A0)
  11833     { /* SOC_REG_INT_GLOBAL_WREDCONFIG_ECCPr */
  11834         soc_block_list[4],
  11835         soc_genreg,
  11836         1,
  11837         0,
  11838         0x12080420,
  11839         0,
  11840         0,
  11841         1,
  11842         soc_BUCKET_ECCr_fields,
  11843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11844         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  11845         -1,
  11846         -1,
  11847     },
  11848 #endif /* chips */
  11849 
  11850 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  11851     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11852     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11853     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11854     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11855     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11856     { /* SOC_REG_INT_GLOBAL_WREDCONFIG_PACKETr */
  11857         soc_block_list[4],
  11858         soc_genreg,
  11859         1,
  11860         0,
  11861         0x1708000d,
  11862         0,
  11863         0,
  11864         8,
  11865         soc_GLOBAL_WREDCONFIG_CELLr_fields,
  11866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11867         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11868         -1,
  11869         -1,
  11870     },
  11871 #endif /* chips */
  11872 
  11873 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11874     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11875     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11876     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11877     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11878     { /* SOC_REG_INT_GLOBAL_WREDPARAM_CELLr */
  11879         soc_block_list[4],
  11880         soc_genreg,
  11881         1,
  11882         0,
  11883         0x17080003,
  11884         0,
  11885         0,
  11886         3,
  11887         soc_GLOBAL_WREDPARAM_CELLr_fields,
  11888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11889         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  11890         -1,
  11891         -1,
  11892     },
  11893 #endif /* chips */
  11894 
  11895 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  11896     { /* SOC_REG_INT_GLOBAL_WREDPARAM_CELL_BCM56334_A0r */
  11897         soc_block_list[4],
  11898         soc_genreg,
  11899         1,
  11900         0,
  11901         0x17080003,
  11902         0,
  11903         0,
  11904         3,
  11905         soc_GLOBAL_WREDPARAM_PACKETr_fields,
  11906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11907         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  11908         -1,
  11909         -1,
  11910     },
  11911 #endif /* chips */
  11912 
  11913 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11914     { /* SOC_REG_INT_GLOBAL_WREDPARAM_CELL_BCM56820_A0r */
  11915         soc_block_list[4],
  11916         soc_genreg,
  11917         1,
  11918         0,
  11919         0x12080003,
  11920         0,
  11921         0,
  11922         3,
  11923         soc_GLOBAL_WREDPARAM_PACKETr_fields,
  11924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11925         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  11926         -1,
  11927         -1,
  11928     },
  11929 #endif /* chips */
  11930 
  11931 #if defined(BCM_88732_A0)
  11932     { /* SOC_REG_INT_GLOBAL_WREDPARAM_END_CELLr */
  11933         soc_block_list[4],
  11934         soc_genreg,
  11935         1,
  11936         0,
  11937         0x12080004,
  11938         0,
  11939         0,
  11940         1,
  11941         soc_GLOBAL_WREDPARAM_END_CELLr_fields,
  11942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11943         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  11944         -1,
  11945         -1,
  11946     },
  11947 #endif /* chips */
  11948 
  11949 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11950     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11951     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11952     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11953     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11954     { /* SOC_REG_INT_GLOBAL_WREDPARAM_NONTCP_CELLr */
  11955         soc_block_list[4],
  11956         soc_genreg,
  11957         1,
  11958         0,
  11959         0x17080006,
  11960         0,
  11961         0,
  11962         3,
  11963         soc_GLOBAL_WREDPARAM_NONTCP_CELLr_fields,
  11964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11965         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  11966         -1,
  11967         -1,
  11968     },
  11969 #endif /* chips */
  11970 
  11971 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  11972     { /* SOC_REG_INT_GLOBAL_WREDPARAM_NONTCP_CELL_BCM56334_A0r */
  11973         soc_block_list[4],
  11974         soc_genreg,
  11975         1,
  11976         0,
  11977         0x17080006,
  11978         0,
  11979         0,
  11980         3,
  11981         soc_GLOBAL_WREDPARAM_NONTCP_PACKETr_fields,
  11982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11983         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  11984         -1,
  11985         -1,
  11986     },
  11987 #endif /* chips */
  11988 
  11989 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11990     { /* SOC_REG_INT_GLOBAL_WREDPARAM_NONTCP_CELL_BCM56820_A0r */
  11991         soc_block_list[4],
  11992         soc_genreg,
  11993         1,
  11994         0,
  11995         0x12080006,
  11996         0,
  11997         0,
  11998         3,
  11999         soc_GLOBAL_WREDPARAM_NONTCP_PACKETr_fields,
  12000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12001         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  12002         -1,
  12003         -1,
  12004     },
  12005 #endif /* chips */
  12006 
  12007 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12008     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  12009     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12010     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  12011     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12012     { /* SOC_REG_INT_GLOBAL_WREDPARAM_NONTCP_PACKETr */
  12013         soc_block_list[4],
  12014         soc_genreg,
  12015         1,
  12016         0,
  12017         0x1708000c,
  12018         0,
  12019         0,
  12020         3,
  12021         soc_GLOBAL_WREDPARAM_NONTCP_PACKETr_fields,
  12022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12023         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  12024         -1,
  12025         -1,
  12026     },
  12027 #endif /* chips */
  12028 
  12029 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  12030     { /* SOC_REG_INT_GLOBAL_WREDPARAM_NONTCP_PACKET_BCM56334_A0r */
  12031         soc_block_list[4],
  12032         soc_genreg,
  12033         1,
  12034         0,
  12035         0x1708000c,
  12036         0,
  12037         0,
  12038         3,
  12039         soc_GLOBAL_WREDPARAM_NONTCP_PACKET_BCM56334_A0r_fields,
  12040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12041         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  12042         -1,
  12043         -1,
  12044     },
  12045 #endif /* chips */
  12046 
  12047 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12048     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  12049     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12050     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  12051     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12052     { /* SOC_REG_INT_GLOBAL_WREDPARAM_PACKETr */
  12053         soc_block_list[4],
  12054         soc_genreg,
  12055         1,
  12056         0,
  12057         0x17080009,
  12058         0,
  12059         0,
  12060         3,
  12061         soc_GLOBAL_WREDPARAM_PACKETr_fields,
  12062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12063         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  12064         -1,
  12065         -1,
  12066     },
  12067 #endif /* chips */
  12068 
  12069 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  12070     { /* SOC_REG_INT_GLOBAL_WREDPARAM_PACKET_BCM56334_A0r */
  12071         soc_block_list[4],
  12072         soc_genreg,
  12073         1,
  12074         0,
  12075         0x17080009,
  12076         0,
  12077         0,
  12078         3,
  12079         soc_GLOBAL_WREDPARAM_PACKET_BCM56334_A0r_fields,
  12080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12081         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  12082         -1,
  12083         -1,
  12084     },
  12085 #endif /* chips */
  12086 
  12087 #if defined(BCM_88732_A0)
  12088     { /* SOC_REG_INT_GLOBAL_WREDPARAM_PRI0_END_CELLr */
  12089         soc_block_list[4],
  12090         soc_genreg,
  12091         1,
  12092         0,
  12093         0x1208000a,
  12094         0,
  12095         0,
  12096         1,
  12097         soc_GLOBAL_WREDPARAM_PRI0_END_CELLr_fields,
  12098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12099         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  12100         -1,
  12101         -1,
  12102     },
  12103 #endif /* chips */
  12104 
  12105 #if defined(BCM_88732_A0)
  12106     { /* SOC_REG_INT_GLOBAL_WREDPARAM_PRI0_START_CELLr */
  12107         soc_block_list[4],
  12108         soc_genreg,
  12109         1,
  12110         0,
  12111         0x12080009,
  12112         0,
  12113         0,
  12114         1,
  12115         soc_GLOBAL_WREDPARAM_PRI0_START_CELLr_fields,
  12116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12117         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  12118         -1,
  12119         -1,
  12120     },
  12121 #endif /* chips */
  12122 
  12123 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12124     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  12125     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12126     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  12127     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12128     { /* SOC_REG_INT_GLOBAL_WREDPARAM_RED_CELLr */
  12129         soc_block_list[4],
  12130         soc_genreg,
  12131         1,
  12132         0,
  12133         0x17080005,
  12134         0,
  12135         0,
  12136         3,
  12137         soc_GLOBAL_WREDPARAM_RED_CELLr_fields,
  12138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12139         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  12140         -1,
  12141         -1,
  12142     },
  12143 #endif /* chips */
  12144 
  12145 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  12146     { /* SOC_REG_INT_GLOBAL_WREDPARAM_RED_CELL_BCM56334_A0r */
  12147         soc_block_list[4],
  12148         soc_genreg,
  12149         1,
  12150         0,
  12151         0x17080005,
  12152         0,
  12153         0,
  12154         3,
  12155         soc_GLOBAL_WREDPARAM_RED_PACKETr_fields,
  12156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12157         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  12158         -1,
  12159         -1,
  12160     },
  12161 #endif /* chips */
  12162 
  12163 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  12164     { /* SOC_REG_INT_GLOBAL_WREDPARAM_RED_CELL_BCM56820_A0r */
  12165         soc_block_list[4],
  12166         soc_genreg,
  12167         1,
  12168         0,
  12169         0x12080005,
  12170         0,
  12171         0,
  12172         3,
  12173         soc_GLOBAL_WREDPARAM_RED_PACKETr_fields,
  12174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12175         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  12176         -1,
  12177         -1,
  12178     },
  12179 #endif /* chips */
  12180 
  12181 #if defined(BCM_88732_A0)
  12182     { /* SOC_REG_INT_GLOBAL_WREDPARAM_RED_END_CELLr */
  12183         soc_block_list[4],
  12184         soc_genreg,
  12185         1,
  12186         0,
  12187         0x12080008,
  12188         0,
  12189         0,
  12190         1,
  12191         soc_GLOBAL_WREDPARAM_RED_END_CELLr_fields,
  12192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12193         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  12194         -1,
  12195         -1,
  12196     },
  12197 #endif /* chips */
  12198 
  12199 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12200     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  12201     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12202     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  12203     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12204     { /* SOC_REG_INT_GLOBAL_WREDPARAM_RED_PACKETr */
  12205         soc_block_list[4],
  12206         soc_genreg,
  12207         1,
  12208         0,
  12209         0x1708000b,
  12210         0,
  12211         0,
  12212         3,
  12213         soc_GLOBAL_WREDPARAM_RED_PACKETr_fields,
  12214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12215         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  12216         -1,
  12217         -1,
  12218     },
  12219 #endif /* chips */
  12220 
  12221 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  12222     { /* SOC_REG_INT_GLOBAL_WREDPARAM_RED_PACKET_BCM56334_A0r */
  12223         soc_block_list[4],
  12224         soc_genreg,
  12225         1,
  12226         0,
  12227         0x1708000b,
  12228         0,
  12229         0,
  12230         3,
  12231         soc_GLOBAL_WREDPARAM_RED_PACKET_BCM56334_A0r_fields,
  12232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12233         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  12234         -1,
  12235         -1,
  12236     },
  12237 #endif /* chips */
  12238 
  12239 #if defined(BCM_88732_A0)
  12240     { /* SOC_REG_INT_GLOBAL_WREDPARAM_RED_START_CELLr */
  12241         soc_block_list[4],
  12242         soc_genreg,
  12243         1,
  12244         0,
  12245         0x12080007,
  12246         0,
  12247         0,
  12248         1,
  12249         soc_GLOBAL_WREDPARAM_RED_START_CELLr_fields,
  12250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12251         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  12252         -1,
  12253         -1,
  12254     },
  12255 #endif /* chips */
  12256 
  12257 #if defined(BCM_88732_A0)
  12258     { /* SOC_REG_INT_GLOBAL_WREDPARAM_START_CELLr */
  12259         soc_block_list[4],
  12260         soc_genreg,
  12261         1,
  12262         0,
  12263         0x12080003,
  12264         0,
  12265         0,
  12266         1,
  12267         soc_GLOBAL_WREDPARAM_START_CELLr_fields,
  12268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12269         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  12270         -1,
  12271         -1,
  12272     },
  12273 #endif /* chips */
  12274 
  12275 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12276     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  12277     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12278     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  12279     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12280     { /* SOC_REG_INT_GLOBAL_WREDPARAM_YELLOW_CELLr */
  12281         soc_block_list[4],
  12282         soc_genreg,
  12283         1,
  12284         0,
  12285         0x17080004,
  12286         0,
  12287         0,
  12288         3,
  12289         soc_GLOBAL_WREDPARAM_YELLOW_CELLr_fields,
  12290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12291         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  12292         -1,
  12293         -1,
  12294     },
  12295 #endif /* chips */
  12296 
  12297 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  12298     { /* SOC_REG_INT_GLOBAL_WREDPARAM_YELLOW_CELL_BCM56334_A0r */
  12299         soc_block_list[4],
  12300         soc_genreg,
  12301         1,
  12302         0,
  12303         0x17080004,
  12304         0,
  12305         0,
  12306         3,
  12307         soc_GLOBAL_WREDPARAM_YELLOW_PACKETr_fields,
  12308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12309         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  12310         -1,
  12311         -1,
  12312     },
  12313 #endif /* chips */
  12314 
  12315 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  12316     { /* SOC_REG_INT_GLOBAL_WREDPARAM_YELLOW_CELL_BCM56820_A0r */
  12317         soc_block_list[4],
  12318         soc_genreg,
  12319         1,
  12320         0,
  12321         0x12080004,
  12322         0,
  12323         0,
  12324         3,
  12325         soc_GLOBAL_WREDPARAM_YELLOW_PACKETr_fields,
  12326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12327         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  12328         -1,
  12329         -1,
  12330     },
  12331 #endif /* chips */
  12332 
  12333 #if defined(BCM_88732_A0)
  12334     { /* SOC_REG_INT_GLOBAL_WREDPARAM_YELLOW_END_CELLr */
  12335         soc_block_list[4],
  12336         soc_genreg,
  12337         1,
  12338         0,
  12339         0x12080006,
  12340         0,
  12341         0,
  12342         1,
  12343         soc_GLOBAL_WREDPARAM_YELLOW_END_CELLr_fields,
  12344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12345         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  12346         -1,
  12347         -1,
  12348     },
  12349 #endif /* chips */
  12350 
  12351 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12352     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  12353     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12354     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  12355     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12356     { /* SOC_REG_INT_GLOBAL_WREDPARAM_YELLOW_PACKETr */
  12357         soc_block_list[4],
  12358         soc_genreg,
  12359         1,
  12360         0,
  12361         0x1708000a,
  12362         0,
  12363         0,
  12364         3,
  12365         soc_GLOBAL_WREDPARAM_YELLOW_PACKETr_fields,
  12366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12367         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  12368         -1,
  12369         -1,
  12370     },
  12371 #endif /* chips */
  12372 
  12373 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  12374     { /* SOC_REG_INT_GLOBAL_WREDPARAM_YELLOW_PACKET_BCM56334_A0r */
  12375         soc_block_list[4],
  12376         soc_genreg,
  12377         1,
  12378         0,
  12379         0x1708000a,
  12380         0,
  12381         0,
  12382         3,
  12383         soc_GLOBAL_WREDPARAM_YELLOW_PACKET_BCM56334_A0r_fields,
  12384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12385         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  12386         -1,
  12387         -1,
  12388     },
  12389 #endif /* chips */
  12390 
  12391 #if defined(BCM_88732_A0)
  12392     { /* SOC_REG_INT_GLOBAL_WREDPARAM_YELLOW_START_CELLr */
  12393         soc_block_list[4],
  12394         soc_genreg,
  12395         1,
  12396         0,
  12397         0x12080005,
  12398         0,
  12399         0,
  12400         1,
  12401         soc_GLOBAL_WREDPARAM_YELLOW_START_CELLr_fields,
  12402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12403         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  12404         -1,
  12405         -1,
  12406     },
  12407 #endif /* chips */
  12408 
  12409 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12410     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_BUFFEREr */
  12411         soc_block_list[4],
  12412         soc_genreg,
  12413         1,
  12414         0,
  12415         0x17080005,
  12416         0,
  12417         0,
  12418         1,
  12419         soc_GLOBAL_WRED_AVG_QSIZE_BUFFEREr_fields,
  12420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12421         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  12422         -1,
  12423         -1,
  12424     },
  12425 #endif /* chips */
  12426 
  12427 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12428     defined(BCM_56450_B1)
  12429     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0r */
  12430         soc_block_list[4],
  12431         soc_genreg,
  12432         1,
  12433         0,
  12434         0x5e000500,
  12435         0,
  12436         0,
  12437         1,
  12438         soc_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0r_fields,
  12439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12440         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  12441         -1,
  12442         -1,
  12443     },
  12444 #endif /* chips */
  12445 
  12446 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12447     defined(BCM_56450_B1)
  12448     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL1r */
  12449         soc_block_list[4],
  12450         soc_genreg,
  12451         1,
  12452         0,
  12453         0x5e000800,
  12454         0,
  12455         0,
  12456         1,
  12457         soc_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0r_fields,
  12458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12459         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  12460         -1,
  12461         -1,
  12462     },
  12463 #endif /* chips */
  12464 
  12465 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12466     defined(BCM_56270_A0)
  12467     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0_BCM56260_A0r */
  12468         soc_block_list[4],
  12469         soc_genreg,
  12470         1,
  12471         0,
  12472         0x5e000500,
  12473         0,
  12474         0,
  12475         1,
  12476         soc_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0_BCM56260_A0r_fields,
  12477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12478         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12479         -1,
  12480         -1,
  12481     },
  12482 #endif /* chips */
  12483 
  12484 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12485     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL1_BCM56260_A0r */
  12486         soc_block_list[4],
  12487         soc_genreg,
  12488         1,
  12489         0,
  12490         0x5e000800,
  12491         0,
  12492         0,
  12493         1,
  12494         soc_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0_BCM56260_A0r_fields,
  12495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12496         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12497         -1,
  12498         -1,
  12499     },
  12500 #endif /* chips */
  12501 
  12502 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12503     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_BUFFERIr */
  12504         soc_block_list[4],
  12505         soc_genreg,
  12506         1,
  12507         0,
  12508         0x17080002,
  12509         0,
  12510         0,
  12511         1,
  12512         soc_GLOBAL_WRED_AVG_QSIZE_BUFFERIr_fields,
  12513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12514         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  12515         -1,
  12516         -1,
  12517     },
  12518 #endif /* chips */
  12519 
  12520 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12521     defined(BCM_56270_A0)
  12522     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_BUFFERI_BCM56260_A0r */
  12523         soc_block_list[4],
  12524         soc_genreg,
  12525         1,
  12526         0,
  12527         0x5e000200,
  12528         0,
  12529         0,
  12530         1,
  12531         soc_GLOBAL_WRED_AVG_QSIZE_BUFFERI_BCM56260_A0r_fields,
  12532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12533         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  12534         -1,
  12535         -1,
  12536     },
  12537 #endif /* chips */
  12538 
  12539 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12540     defined(BCM_56450_B1)
  12541     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_BUFFERI_BCM56450_A0r */
  12542         soc_block_list[4],
  12543         soc_genreg,
  12544         1,
  12545         0,
  12546         0x5e000200,
  12547         0,
  12548         0,
  12549         1,
  12550         soc_GLOBAL_WRED_AVG_QSIZE_BUFFERI_BCM56450_A0r_fields,
  12551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12552         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  12553         -1,
  12554         -1,
  12555     },
  12556 #endif /* chips */
  12557 
  12558 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12559     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFEREr */
  12560         soc_block_list[4],
  12561         soc_genreg,
  12562         1,
  12563         0,
  12564         0x17080004,
  12565         0,
  12566         0,
  12567         1,
  12568         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFEREr_fields,
  12569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12570         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12571         -1,
  12572         -1,
  12573     },
  12574 #endif /* chips */
  12575 
  12576 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12577     defined(BCM_56450_B1)
  12578     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0r */
  12579         soc_block_list[4],
  12580         soc_genreg,
  12581         1,
  12582         0,
  12583         0x5e000400,
  12584         0,
  12585         0,
  12586         1,
  12587         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0r_fields,
  12588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12589         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12590         -1,
  12591         -1,
  12592     },
  12593 #endif /* chips */
  12594 
  12595 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12596     defined(BCM_56450_B1)
  12597     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL1r */
  12598         soc_block_list[4],
  12599         soc_genreg,
  12600         1,
  12601         0,
  12602         0x5e000700,
  12603         0,
  12604         0,
  12605         1,
  12606         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0r_fields,
  12607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12608         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12609         -1,
  12610         -1,
  12611     },
  12612 #endif /* chips */
  12613 
  12614 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12615     defined(BCM_56270_A0)
  12616     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0_BCM56260_A0r */
  12617         soc_block_list[4],
  12618         soc_genreg,
  12619         1,
  12620         0,
  12621         0x5e000400,
  12622         0,
  12623         0,
  12624         1,
  12625         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0_BCM56260_A0r_fields,
  12626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12627         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12628         -1,
  12629         -1,
  12630     },
  12631 #endif /* chips */
  12632 
  12633 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12634     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL1_BCM56260_A0r */
  12635         soc_block_list[4],
  12636         soc_genreg,
  12637         1,
  12638         0,
  12639         0x5e000700,
  12640         0,
  12641         0,
  12642         1,
  12643         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0_BCM56260_A0r_fields,
  12644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12645         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12646         -1,
  12647         -1,
  12648     },
  12649 #endif /* chips */
  12650 
  12651 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12652     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERIr */
  12653         soc_block_list[4],
  12654         soc_genreg,
  12655         1,
  12656         0,
  12657         0x17080001,
  12658         0,
  12659         0,
  12660         1,
  12661         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFEREr_fields,
  12662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12663         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12664         -1,
  12665         -1,
  12666     },
  12667 #endif /* chips */
  12668 
  12669 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12670     defined(BCM_56270_A0)
  12671     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERI_BCM56260_A0r */
  12672         soc_block_list[4],
  12673         soc_genreg,
  12674         1,
  12675         0,
  12676         0x5e000100,
  12677         0,
  12678         0,
  12679         1,
  12680         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0_BCM56260_A0r_fields,
  12681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12682         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12683         -1,
  12684         -1,
  12685     },
  12686 #endif /* chips */
  12687 
  12688 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12689     defined(BCM_56450_B1)
  12690     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERI_BCM56450_A0r */
  12691         soc_block_list[4],
  12692         soc_genreg,
  12693         1,
  12694         0,
  12695         0x5e000100,
  12696         0,
  12697         0,
  12698         1,
  12699         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0r_fields,
  12700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12701         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12702         -1,
  12703         -1,
  12704     },
  12705 #endif /* chips */
  12706 
  12707 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12708     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_QENTRYr */
  12709         soc_block_list[4],
  12710         soc_genreg,
  12711         1,
  12712         0,
  12713         0x17080007,
  12714         0,
  12715         0,
  12716         1,
  12717         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFEREr_fields,
  12718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12719         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12720         -1,
  12721         -1,
  12722     },
  12723 #endif /* chips */
  12724 
  12725 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12726     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_QENTRY_BCM56260_A0r */
  12727         soc_block_list[4],
  12728         soc_genreg,
  12729         1,
  12730         0,
  12731         0x5e000a00,
  12732         0,
  12733         0,
  12734         1,
  12735         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0_BCM56260_A0r_fields,
  12736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12737         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12738         -1,
  12739         -1,
  12740     },
  12741 #endif /* chips */
  12742 
  12743 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12744     defined(BCM_56450_B1)
  12745     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_FRACTION_QENTRY_BCM56450_A0r */
  12746         soc_block_list[4],
  12747         soc_genreg,
  12748         1,
  12749         0,
  12750         0x5e000a00,
  12751         0,
  12752         0,
  12753         1,
  12754         soc_GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0r_fields,
  12755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12756         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12757         -1,
  12758         -1,
  12759     },
  12760 #endif /* chips */
  12761 
  12762 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12763     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_QENTRYr */
  12764         soc_block_list[4],
  12765         soc_genreg,
  12766         1,
  12767         0,
  12768         0x17080008,
  12769         0,
  12770         0,
  12771         1,
  12772         soc_GLOBAL_WRED_AVG_QSIZE_BUFFEREr_fields,
  12773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12774         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  12775         -1,
  12776         -1,
  12777     },
  12778 #endif /* chips */
  12779 
  12780 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12781     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_QENTRY_BCM56260_A0r */
  12782         soc_block_list[4],
  12783         soc_genreg,
  12784         1,
  12785         0,
  12786         0x5e000b00,
  12787         0,
  12788         0,
  12789         1,
  12790         soc_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0_BCM56260_A0r_fields,
  12791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12792         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  12793         -1,
  12794         -1,
  12795     },
  12796 #endif /* chips */
  12797 
  12798 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12799     defined(BCM_56450_B1)
  12800     { /* SOC_REG_INT_GLOBAL_WRED_AVG_QSIZE_QENTRY_BCM56450_A0r */
  12801         soc_block_list[4],
  12802         soc_genreg,
  12803         1,
  12804         0,
  12805         0x5e000b00,
  12806         0,
  12807         0,
  12808         1,
  12809         soc_GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0r_fields,
  12810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12811         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  12812         -1,
  12813         -1,
  12814     },
  12815 #endif /* chips */
  12816 
  12817 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12818     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_BUFFEREr */
  12819         soc_block_list[4],
  12820         soc_genreg,
  12821         1,
  12822         0,
  12823         0x17080003,
  12824         0,
  12825         0,
  12826         5,
  12827         soc_GLOBAL_WRED_CONFIG_BUFFEREr_fields,
  12828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12829         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12830         -1,
  12831         -1,
  12832     },
  12833 #endif /* chips */
  12834 
  12835 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12836     defined(BCM_56450_B1)
  12837     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_BUFFERE_POOL0r */
  12838         soc_block_list[4],
  12839         soc_genreg,
  12840         1,
  12841         0,
  12842         0x5e000300,
  12843         0,
  12844         0,
  12845         5,
  12846         soc_GLOBAL_WRED_CONFIG_BUFFERE_POOL0r_fields,
  12847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12848         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12849         -1,
  12850         -1,
  12851     },
  12852 #endif /* chips */
  12853 
  12854 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12855     defined(BCM_56450_B1)
  12856     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_BUFFERE_POOL1r */
  12857         soc_block_list[4],
  12858         soc_genreg,
  12859         1,
  12860         0,
  12861         0x5e000600,
  12862         0,
  12863         0,
  12864         5,
  12865         soc_GLOBAL_WRED_CONFIG_BUFFERE_POOL0r_fields,
  12866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12867         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12868         -1,
  12869         -1,
  12870     },
  12871 #endif /* chips */
  12872 
  12873 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12874     defined(BCM_56270_A0)
  12875     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_BUFFERE_POOL0_BCM56260_A0r */
  12876         soc_block_list[4],
  12877         soc_genreg,
  12878         1,
  12879         0,
  12880         0x5e000300,
  12881         0,
  12882         0,
  12883         5,
  12884         soc_GLOBAL_WRED_CONFIG_BUFFERE_POOL0_BCM56260_A0r_fields,
  12885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12886         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12887         -1,
  12888         -1,
  12889     },
  12890 #endif /* chips */
  12891 
  12892 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12893     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_BUFFERE_POOL1_BCM56260_A0r */
  12894         soc_block_list[4],
  12895         soc_genreg,
  12896         1,
  12897         0,
  12898         0x5e000600,
  12899         0,
  12900         0,
  12901         5,
  12902         soc_GLOBAL_WRED_CONFIG_BUFFERE_POOL0_BCM56260_A0r_fields,
  12903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12904         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12905         -1,
  12906         -1,
  12907     },
  12908 #endif /* chips */
  12909 
  12910 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12911     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_BUFFERIr */
  12912         soc_block_list[4],
  12913         soc_genreg,
  12914         1,
  12915         0,
  12916         0x17080000,
  12917         0,
  12918         0,
  12919         5,
  12920         soc_GLOBAL_WRED_CONFIG_BUFFEREr_fields,
  12921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12922         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12923         -1,
  12924         -1,
  12925     },
  12926 #endif /* chips */
  12927 
  12928 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12929     defined(BCM_56270_A0)
  12930     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_BUFFERI_BCM56260_A0r */
  12931         soc_block_list[4],
  12932         soc_genreg,
  12933         1,
  12934         0,
  12935         0x5e000000,
  12936         0,
  12937         0,
  12938         5,
  12939         soc_GLOBAL_WRED_CONFIG_BUFFERE_POOL0_BCM56260_A0r_fields,
  12940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12941         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12942         -1,
  12943         -1,
  12944     },
  12945 #endif /* chips */
  12946 
  12947 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12948     defined(BCM_56450_B1)
  12949     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_BUFFERI_BCM56450_A0r */
  12950         soc_block_list[4],
  12951         soc_genreg,
  12952         1,
  12953         0,
  12954         0x5e000000,
  12955         0,
  12956         0,
  12957         5,
  12958         soc_GLOBAL_WRED_CONFIG_BUFFERE_POOL0r_fields,
  12959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12960         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12961         -1,
  12962         -1,
  12963     },
  12964 #endif /* chips */
  12965 
  12966 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12967     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_QENTRYr */
  12968         soc_block_list[4],
  12969         soc_genreg,
  12970         1,
  12971         0,
  12972         0x17080006,
  12973         0,
  12974         0,
  12975         5,
  12976         soc_GLOBAL_WRED_CONFIG_BUFFEREr_fields,
  12977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12978         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12979         -1,
  12980         -1,
  12981     },
  12982 #endif /* chips */
  12983 
  12984 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12985     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_QENTRY_BCM56260_A0r */
  12986         soc_block_list[4],
  12987         soc_genreg,
  12988         1,
  12989         0,
  12990         0x5e000900,
  12991         0,
  12992         0,
  12993         5,
  12994         soc_GLOBAL_WRED_CONFIG_BUFFERE_POOL0_BCM56260_A0r_fields,
  12995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12996         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  12997         -1,
  12998         -1,
  12999     },
  13000 #endif /* chips */
  13001 
  13002 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13003     defined(BCM_56450_B1)
  13004     { /* SOC_REG_INT_GLOBAL_WRED_CONFIG_QENTRY_BCM56450_A0r */
  13005         soc_block_list[4],
  13006         soc_genreg,
  13007         1,
  13008         0,
  13009         0x5e000900,
  13010         0,
  13011         0,
  13012         5,
  13013         soc_GLOBAL_WRED_CONFIG_BUFFERE_POOL0r_fields,
  13014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13015         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  13016         -1,
  13017         -1,
  13018     },
  13019 #endif /* chips */
  13020 
  13021 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13022     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_BUFFEREr */
  13023         soc_block_list[4],
  13024         soc_genreg,
  13025         1,
  13026         0,
  13027         0x1708000c,
  13028         0,
  13029         0,
  13030         3,
  13031         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFEREr_fields,
  13032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13033         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13034         -1,
  13035         -1,
  13036     },
  13037 #endif /* chips */
  13038 
  13039 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13040     defined(BCM_56450_B1)
  13041     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0r */
  13042         soc_block_list[4],
  13043         soc_genreg,
  13044         1,
  13045         0,
  13046         0x5e000f00,
  13047         0,
  13048         0,
  13049         3,
  13050         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0r_fields,
  13051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13052         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13053         -1,
  13054         -1,
  13055     },
  13056 #endif /* chips */
  13057 
  13058 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13059     defined(BCM_56450_B1)
  13060     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL1r */
  13061         soc_block_list[4],
  13062         soc_genreg,
  13063         1,
  13064         0,
  13065         0x5e001100,
  13066         0,
  13067         0,
  13068         3,
  13069         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0r_fields,
  13070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13071         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13072         -1,
  13073         -1,
  13074     },
  13075 #endif /* chips */
  13076 
  13077 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13078     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0_BCM56260_A0r */
  13079         soc_block_list[4],
  13080         soc_genreg,
  13081         1,
  13082         0,
  13083         0x5e000f00,
  13084         0,
  13085         0,
  13086         3,
  13087         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13089         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13090         -1,
  13091         -1,
  13092     },
  13093 #endif /* chips */
  13094 
  13095 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13096     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL1_BCM56260_A0r */
  13097         soc_block_list[4],
  13098         soc_genreg,
  13099         1,
  13100         0,
  13101         0x5e001100,
  13102         0,
  13103         0,
  13104         3,
  13105         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13107         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13108         -1,
  13109         -1,
  13110     },
  13111 #endif /* chips */
  13112 
  13113 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13114     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERIr */
  13115         soc_block_list[4],
  13116         soc_genreg,
  13117         1,
  13118         0,
  13119         0x1708000a,
  13120         0,
  13121         0,
  13122         3,
  13123         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFEREr_fields,
  13124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13125         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13126         -1,
  13127         -1,
  13128     },
  13129 #endif /* chips */
  13130 
  13131 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13132     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERI_BCM56260_A0r */
  13133         soc_block_list[4],
  13134         soc_genreg,
  13135         1,
  13136         0,
  13137         0x5e000d00,
  13138         0,
  13139         0,
  13140         3,
  13141         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13143         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13144         -1,
  13145         -1,
  13146     },
  13147 #endif /* chips */
  13148 
  13149 #if defined(BCM_56270_A0)
  13150     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERI_BCM56270_A0r */
  13151         soc_block_list[4],
  13152         soc_genreg,
  13153         1,
  13154         0,
  13155         0x5e000700,
  13156         0,
  13157         0,
  13158         3,
  13159         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13161         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13162         -1,
  13163         -1,
  13164     },
  13165 #endif /* chips */
  13166 
  13167 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13168     defined(BCM_56450_B1)
  13169     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERI_BCM56450_A0r */
  13170         soc_block_list[4],
  13171         soc_genreg,
  13172         1,
  13173         0,
  13174         0x5e000d00,
  13175         0,
  13176         0,
  13177         3,
  13178         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0r_fields,
  13179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13180         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13181         -1,
  13182         -1,
  13183     },
  13184 #endif /* chips */
  13185 
  13186 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13187     defined(BCM_56450_B1)
  13188     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_QENTRYr */
  13189         soc_block_list[4],
  13190         soc_genreg,
  13191         1,
  13192         0,
  13193         0x5e001300,
  13194         0,
  13195         0,
  13196         3,
  13197         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0r_fields,
  13198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13199         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13200         -1,
  13201         -1,
  13202     },
  13203 #endif /* chips */
  13204 
  13205 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13206     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_QENTRY_BCM56260_A0r */
  13207         soc_block_list[4],
  13208         soc_genreg,
  13209         1,
  13210         0,
  13211         0x5e001300,
  13212         0,
  13213         0,
  13214         3,
  13215         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13217         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13218         -1,
  13219         -1,
  13220     },
  13221 #endif /* chips */
  13222 
  13223 #if defined(BCM_56270_A0)
  13224     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_NONTCP_QENTRY_BCM56270_A0r */
  13225         soc_block_list[4],
  13226         soc_genreg,
  13227         1,
  13228         0,
  13229         0x5e000900,
  13230         0,
  13231         0,
  13232         3,
  13233         soc_GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13235         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13236         -1,
  13237         -1,
  13238     },
  13239 #endif /* chips */
  13240 
  13241 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13242     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_BUFFEREr */
  13243         soc_block_list[4],
  13244         soc_genreg,
  13245         1,
  13246         0,
  13247         0x1708000b,
  13248         0,
  13249         0,
  13250         3,
  13251         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFEREr_fields,
  13252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13253         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13254         -1,
  13255         -1,
  13256     },
  13257 #endif /* chips */
  13258 
  13259 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13260     defined(BCM_56450_B1)
  13261     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0r */
  13262         soc_block_list[4],
  13263         soc_genreg,
  13264         1,
  13265         0,
  13266         0x5e000e00,
  13267         0,
  13268         0,
  13269         3,
  13270         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0r_fields,
  13271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13272         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13273         -1,
  13274         -1,
  13275     },
  13276 #endif /* chips */
  13277 
  13278 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13279     defined(BCM_56450_B1)
  13280     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL1r */
  13281         soc_block_list[4],
  13282         soc_genreg,
  13283         1,
  13284         0,
  13285         0x5e001000,
  13286         0,
  13287         0,
  13288         3,
  13289         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0r_fields,
  13290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13291         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13292         -1,
  13293         -1,
  13294     },
  13295 #endif /* chips */
  13296 
  13297 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13298     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0_BCM56260_A0r */
  13299         soc_block_list[4],
  13300         soc_genreg,
  13301         1,
  13302         0,
  13303         0x5e000e00,
  13304         0,
  13305         0,
  13306         3,
  13307         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13309         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13310         -1,
  13311         -1,
  13312     },
  13313 #endif /* chips */
  13314 
  13315 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13316     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL1_BCM56260_A0r */
  13317         soc_block_list[4],
  13318         soc_genreg,
  13319         1,
  13320         0,
  13321         0x5e001000,
  13322         0,
  13323         0,
  13324         3,
  13325         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13327         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13328         -1,
  13329         -1,
  13330     },
  13331 #endif /* chips */
  13332 
  13333 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13334     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_BUFFERIr */
  13335         soc_block_list[4],
  13336         soc_genreg,
  13337         1,
  13338         0,
  13339         0x17080009,
  13340         0,
  13341         0,
  13342         3,
  13343         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFEREr_fields,
  13344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13345         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13346         -1,
  13347         -1,
  13348     },
  13349 #endif /* chips */
  13350 
  13351 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13352     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_BUFFERI_BCM56260_A0r */
  13353         soc_block_list[4],
  13354         soc_genreg,
  13355         1,
  13356         0,
  13357         0x5e000c00,
  13358         0,
  13359         0,
  13360         3,
  13361         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13363         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13364         -1,
  13365         -1,
  13366     },
  13367 #endif /* chips */
  13368 
  13369 #if defined(BCM_56270_A0)
  13370     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_BUFFERI_BCM56270_A0r */
  13371         soc_block_list[4],
  13372         soc_genreg,
  13373         1,
  13374         0,
  13375         0x5e000600,
  13376         0,
  13377         0,
  13378         3,
  13379         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13381         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13382         -1,
  13383         -1,
  13384     },
  13385 #endif /* chips */
  13386 
  13387 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13388     defined(BCM_56450_B1)
  13389     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_BUFFERI_BCM56450_A0r */
  13390         soc_block_list[4],
  13391         soc_genreg,
  13392         1,
  13393         0,
  13394         0x5e000c00,
  13395         0,
  13396         0,
  13397         3,
  13398         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0r_fields,
  13399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13400         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13401         -1,
  13402         -1,
  13403     },
  13404 #endif /* chips */
  13405 
  13406 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13407     defined(BCM_56450_B1)
  13408     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_QENTRYr */
  13409         soc_block_list[4],
  13410         soc_genreg,
  13411         1,
  13412         0,
  13413         0x5e001200,
  13414         0,
  13415         0,
  13416         3,
  13417         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0r_fields,
  13418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13419         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13420         -1,
  13421         -1,
  13422     },
  13423 #endif /* chips */
  13424 
  13425 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13426     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_QENTRY_BCM56260_A0r */
  13427         soc_block_list[4],
  13428         soc_genreg,
  13429         1,
  13430         0,
  13431         0x5e001200,
  13432         0,
  13433         0,
  13434         3,
  13435         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13437         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13438         -1,
  13439         -1,
  13440     },
  13441 #endif /* chips */
  13442 
  13443 #if defined(BCM_56270_A0)
  13444     { /* SOC_REG_INT_GLOBAL_WRED_DROP_THD_TCP_QENTRY_BCM56270_A0r */
  13445         soc_block_list[4],
  13446         soc_genreg,
  13447         1,
  13448         0,
  13449         0x5e000800,
  13450         0,
  13451         0,
  13452         3,
  13453         soc_GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0_BCM56260_A0r_fields,
  13454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13455         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13456         -1,
  13457         -1,
  13458     },
  13459 #endif /* chips */
  13460 
  13461 #if defined(BCM_88732_A0)
  13462     { /* SOC_REG_INT_GLOBAL_WRED_THD_0_ECCPr */
  13463         soc_block_list[4],
  13464         soc_genreg,
  13465         1,
  13466         0,
  13467         0x12080421,
  13468         0,
  13469         0,
  13470         1,
  13471         soc_BUCKET_ECCr_fields,
  13472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13473         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13474         -1,
  13475         -1,
  13476     },
  13477 #endif /* chips */
  13478 
  13479 #if defined(BCM_88732_A0)
  13480     { /* SOC_REG_INT_GLOBAL_WRED_THD_1_ECCPr */
  13481         soc_block_list[4],
  13482         soc_genreg,
  13483         1,
  13484         0,
  13485         0x12080422,
  13486         0,
  13487         0,
  13488         1,
  13489         soc_BUCKET_ECCr_fields,
  13490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13491         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13492         -1,
  13493         -1,
  13494     },
  13495 #endif /* chips */
  13496 
  13497 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13498     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13499     defined(BCM_56450_B1)
  13500     { /* SOC_REG_INT_GMAC0_BISTSTATUSr */
  13501         soc_block_list[61],
  13502         soc_iprocreg,
  13503         1,
  13504         0,
  13505         0x1802200c,
  13506         SOC_REG_FLAG_RO,
  13507         0,
  13508         10,
  13509         soc_GMAC0_BISTSTATUSr_fields,
  13510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13511         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  13512         -1,
  13513         -1,
  13514     },
  13515 #endif /* chips */
  13516 
  13517 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13518     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13519     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13520     defined(BCM_56260_B0)
  13521     { /* SOC_REG_INT_GMAC0_BISTSTATUS_BCM53400_A0r */
  13522         soc_block_list[61],
  13523         soc_iprocreg,
  13524         1,
  13525         0,
  13526         0x1804200c,
  13527         SOC_REG_FLAG_RO,
  13528         0,
  13529         10,
  13530         soc_GMAC0_BISTSTATUS_BCM53400_A0r_fields,
  13531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13532         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  13533         -1,
  13534         -1,
  13535     },
  13536 #endif /* chips */
  13537 
  13538 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  13539     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
  13540     defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13541     { /* SOC_REG_INT_GMAC0_CKSUM_CONTROLr */
  13542         soc_block_list[61],
  13543         soc_iprocreg,
  13544         1,
  13545         0,
  13546         0x180422e0,
  13547         0,
  13548         0,
  13549         5,
  13550         soc_GMAC0_CKSUM_CONTROLr_fields,
  13551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13552         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  13553         -1,
  13554         -1,
  13555     },
  13556 #endif /* chips */
  13557 
  13558 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13559     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13560     defined(BCM_56450_B1)
  13561     { /* SOC_REG_INT_GMAC0_CLOCKCONTROLSTATUSr */
  13562         soc_block_list[61],
  13563         soc_iprocreg,
  13564         1,
  13565         0,
  13566         0x180221e0,
  13567         0,
  13568         0,
  13569         12,
  13570         soc_GMAC0_CLOCKCONTROLSTATUSr_fields,
  13571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13572         SOC_RESET_MASK_DEC(0x010f013f, 0x00000000)
  13573         -1,
  13574         -1,
  13575     },
  13576 #endif /* chips */
  13577 
  13578 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13579     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13580     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13581     defined(BCM_56260_B0)
  13582     { /* SOC_REG_INT_GMAC0_CLOCKCONTROLSTATUS_BCM53400_A0r */
  13583         soc_block_list[61],
  13584         soc_iprocreg,
  13585         1,
  13586         0,
  13587         0x180421e0,
  13588         0,
  13589         0,
  13590         12,
  13591         soc_GMAC0_CLOCKCONTROLSTATUS_BCM53400_A0r_fields,
  13592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13593         SOC_RESET_MASK_DEC(0x010f013f, 0x00000000)
  13594         -1,
  13595         -1,
  13596     },
  13597 #endif /* chips */
  13598 
  13599 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13600     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13601     defined(BCM_56450_B1)
  13602     { /* SOC_REG_INT_GMAC0_DEVCONTROLr */
  13603         soc_block_list[61],
  13604         soc_iprocreg,
  13605         1,
  13606         0,
  13607         0x18022000,
  13608         0,
  13609         0,
  13610         12,
  13611         soc_GMAC0_DEVCONTROLr_fields,
  13612         SOC_RESET_VAL_DEC(0x00300003, 0x00000000)
  13613         SOC_RESET_MASK_DEC(0x003f01ff, 0x00000000)
  13614         -1,
  13615         -1,
  13616     },
  13617 #endif /* chips */
  13618 
  13619 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13620     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13621     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13622     defined(BCM_56260_B0)
  13623     { /* SOC_REG_INT_GMAC0_DEVCONTROL_BCM53400_A0r */
  13624         soc_block_list[61],
  13625         soc_iprocreg,
  13626         1,
  13627         0,
  13628         0x18042000,
  13629         0,
  13630         0,
  13631         12,
  13632         soc_GMAC0_DEVCONTROL_BCM53400_A0r_fields,
  13633         SOC_RESET_VAL_DEC(0x00300003, 0x00000000)
  13634         SOC_RESET_MASK_DEC(0x003f01ff, 0x00000000)
  13635         -1,
  13636         -1,
  13637     },
  13638 #endif /* chips */
  13639 
  13640 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13641     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13642     defined(BCM_56450_B1)
  13643     { /* SOC_REG_INT_GMAC0_DEVSTATUSr */
  13644         soc_block_list[61],
  13645         soc_iprocreg,
  13646         1,
  13647         0,
  13648         0x18022004,
  13649         SOC_REG_FLAG_RO,
  13650         0,
  13651         10,
  13652         soc_GMAC0_DEVSTATUSr_fields,
  13653         SOC_RESET_VAL_DEC(0x00131100, 0x00000000)
  13654         SOC_RESET_MASK_DEC(0x00ff1f7f, 0x00000000)
  13655         -1,
  13656         -1,
  13657     },
  13658 #endif /* chips */
  13659 
  13660 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13661     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13662     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13663     defined(BCM_56260_B0)
  13664     { /* SOC_REG_INT_GMAC0_DEVSTATUS_BCM53400_A0r */
  13665         soc_block_list[61],
  13666         soc_iprocreg,
  13667         1,
  13668         0,
  13669         0x18042004,
  13670         SOC_REG_FLAG_RO,
  13671         0,
  13672         10,
  13673         soc_GMAC0_DEVSTATUS_BCM53400_A0r_fields,
  13674         SOC_RESET_VAL_DEC(0x00131100, 0x00000000)
  13675         SOC_RESET_MASK_DEC(0x00ff1f7f, 0x00000000)
  13676         -1,
  13677         -1,
  13678     },
  13679 #endif /* chips */
  13680 
  13681 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13682     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13683     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13684     defined(BCM_56260_B0)
  13685     { /* SOC_REG_INT_GMAC0_EEECONTROLr */
  13686         soc_block_list[61],
  13687         soc_iprocreg,
  13688         1,
  13689         0,
  13690         0x180421ec,
  13691         0,
  13692         0,
  13693         3,
  13694         soc_GMAC0_EEECONTROLr_fields,
  13695         SOC_RESET_VAL_DEC(0x000003e8, 0x00000000)
  13696         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  13697         -1,
  13698         -1,
  13699     },
  13700 #endif /* chips */
  13701 
  13702 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13703     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13704     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13705     defined(BCM_56260_B0)
  13706     { /* SOC_REG_INT_GMAC0_EEERXDURATIONCOUNTr */
  13707         soc_block_list[61],
  13708         soc_iprocreg,
  13709         1,
  13710         0,
  13711         0x180421fc,
  13712         0,
  13713         0,
  13714         1,
  13715         soc_GMAC0_EEERXDURATIONCOUNTr_fields,
  13716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13718         -1,
  13719         -1,
  13720     },
  13721 #endif /* chips */
  13722 
  13723 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13724     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13725     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13726     defined(BCM_56260_B0)
  13727     { /* SOC_REG_INT_GMAC0_EEERXEVENTCOUNTr */
  13728         soc_block_list[61],
  13729         soc_iprocreg,
  13730         1,
  13731         0,
  13732         0x180421f8,
  13733         0,
  13734         0,
  13735         1,
  13736         soc_GMAC0_EEERXEVENTCOUNTr_fields,
  13737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13739         -1,
  13740         -1,
  13741     },
  13742 #endif /* chips */
  13743 
  13744 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13745     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13746     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13747     defined(BCM_56260_B0)
  13748     { /* SOC_REG_INT_GMAC0_EEETXDURATIONCOUNTr */
  13749         soc_block_list[61],
  13750         soc_iprocreg,
  13751         1,
  13752         0,
  13753         0x180421f4,
  13754         0,
  13755         0,
  13756         1,
  13757         soc_GMAC0_EEETXDURATIONCOUNTr_fields,
  13758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13760         -1,
  13761         -1,
  13762     },
  13763 #endif /* chips */
  13764 
  13765 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13766     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13767     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13768     defined(BCM_56260_B0)
  13769     { /* SOC_REG_INT_GMAC0_EEETXEVENTCOUNTr */
  13770         soc_block_list[61],
  13771         soc_iprocreg,
  13772         1,
  13773         0,
  13774         0x180421f0,
  13775         0,
  13776         0,
  13777         1,
  13778         soc_GMAC0_EEETXEVENTCOUNTr_fields,
  13779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13781         -1,
  13782         -1,
  13783     },
  13784 #endif /* chips */
  13785 
  13786 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13787     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13788     defined(BCM_56450_B1)
  13789     { /* SOC_REG_INT_GMAC0_FIFOACCESSADDRr */
  13790         soc_block_list[61],
  13791         soc_iprocreg,
  13792         1,
  13793         0,
  13794         0x18022120,
  13795         0,
  13796         0,
  13797         2,
  13798         soc_GMAC0_FIFOACCESSADDRr_fields,
  13799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13800         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  13801         -1,
  13802         -1,
  13803     },
  13804 #endif /* chips */
  13805 
  13806 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13807     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13808     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13809     defined(BCM_56260_B0)
  13810     { /* SOC_REG_INT_GMAC0_FIFOACCESSADDR_BCM53400_A0r */
  13811         soc_block_list[61],
  13812         soc_iprocreg,
  13813         1,
  13814         0,
  13815         0x18042120,
  13816         0,
  13817         0,
  13818         2,
  13819         soc_GMAC0_FIFOACCESSADDR_BCM53400_A0r_fields,
  13820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13821         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  13822         -1,
  13823         -1,
  13824     },
  13825 #endif /* chips */
  13826 
  13827 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13828     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13829     defined(BCM_56450_B1)
  13830     { /* SOC_REG_INT_GMAC0_FIFOACCESSBYTEr */
  13831         soc_block_list[61],
  13832         soc_iprocreg,
  13833         1,
  13834         0,
  13835         0x18022124,
  13836         0,
  13837         0,
  13838         1,
  13839         soc_GMAC0_FIFOACCESSBYTEr_fields,
  13840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13841         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13842         -1,
  13843         -1,
  13844     },
  13845 #endif /* chips */
  13846 
  13847 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13848     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13849     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13850     defined(BCM_56260_B0)
  13851     { /* SOC_REG_INT_GMAC0_FIFOACCESSBYTE_BCM53400_A0r */
  13852         soc_block_list[61],
  13853         soc_iprocreg,
  13854         1,
  13855         0,
  13856         0x18042124,
  13857         0,
  13858         0,
  13859         1,
  13860         soc_GMAC0_FIFOACCESSBYTE_BCM53400_A0r_fields,
  13861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13862         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13863         -1,
  13864         -1,
  13865     },
  13866 #endif /* chips */
  13867 
  13868 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13869     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13870     defined(BCM_56450_B1)
  13871     { /* SOC_REG_INT_GMAC0_FIFOACCESSDATAr */
  13872         soc_block_list[61],
  13873         soc_iprocreg,
  13874         1,
  13875         0,
  13876         0x18022128,
  13877         0,
  13878         0,
  13879         1,
  13880         soc_GMAC0_FIFOACCESSDATAr_fields,
  13881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13882         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13883         -1,
  13884         -1,
  13885     },
  13886 #endif /* chips */
  13887 
  13888 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13889     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13890     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13891     defined(BCM_56260_B0)
  13892     { /* SOC_REG_INT_GMAC0_FIFOACCESSDATA_BCM53400_A0r */
  13893         soc_block_list[61],
  13894         soc_iprocreg,
  13895         1,
  13896         0,
  13897         0x18042128,
  13898         0,
  13899         0,
  13900         1,
  13901         soc_GMAC0_FIFOACCESSDATA_BCM53400_A0r_fields,
  13902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13903         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13904         -1,
  13905         -1,
  13906     },
  13907 #endif /* chips */
  13908 
  13909 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13910     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13911     defined(BCM_56450_B1)
  13912     { /* SOC_REG_INT_GMAC0_FLOWCNTL_THr */
  13913         soc_block_list[61],
  13914         soc_iprocreg,
  13915         1,
  13916         0,
  13917         0x18022104,
  13918         0,
  13919         0,
  13920         2,
  13921         soc_GMAC0_FLOWCNTL_THr_fields,
  13922         SOC_RESET_VAL_DEC(0x04cc0599, 0x00000000)
  13923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13924         -1,
  13925         -1,
  13926     },
  13927 #endif /* chips */
  13928 
  13929 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13930     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13931     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13932     defined(BCM_56260_B0)
  13933     { /* SOC_REG_INT_GMAC0_FLOWCNTL_TH_BCM53400_A0r */
  13934         soc_block_list[61],
  13935         soc_iprocreg,
  13936         1,
  13937         0,
  13938         0x18042104,
  13939         0,
  13940         0,
  13941         2,
  13942         soc_GMAC0_FLOWCNTL_TH_BCM53400_A0r_fields,
  13943         SOC_RESET_VAL_DEC(0x04cc0599, 0x00000000)
  13944         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13945         -1,
  13946         -1,
  13947     },
  13948 #endif /* chips */
  13949 
  13950 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13951     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13952     defined(BCM_56450_B1)
  13953     { /* SOC_REG_INT_GMAC0_GMACIDLE_CNT_THr */
  13954         soc_block_list[61],
  13955         soc_iprocreg,
  13956         1,
  13957         0,
  13958         0x1802210c,
  13959         0,
  13960         0,
  13961         2,
  13962         soc_GMAC0_GMACIDLE_CNT_THr_fields,
  13963         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  13964         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  13965         -1,
  13966         -1,
  13967     },
  13968 #endif /* chips */
  13969 
  13970 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13971     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13972     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13973     defined(BCM_56260_B0)
  13974     { /* SOC_REG_INT_GMAC0_GMACIDLE_CNT_TH_BCM53400_A0r */
  13975         soc_block_list[61],
  13976         soc_iprocreg,
  13977         1,
  13978         0,
  13979         0x1804210c,
  13980         0,
  13981         0,
  13982         2,
  13983         soc_GMAC0_GMACIDLE_CNT_TH_BCM53400_A0r_fields,
  13984         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  13985         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  13986         -1,
  13987         -1,
  13988     },
  13989 #endif /* chips */
  13990 
  13991 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13992     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13993     defined(BCM_56450_B1)
  13994     { /* SOC_REG_INT_GMAC0_GPIOOUTPUTENr */
  13995         soc_block_list[61],
  13996         soc_iprocreg,
  13997         1,
  13998         0,
  13999         0x18022198,
  14000         0,
  14001         0,
  14002         1,
  14003         soc_GMAC0_GPIOOUTPUTENr_fields,
  14004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14005         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  14006         -1,
  14007         -1,
  14008     },
  14009 #endif /* chips */
  14010 
  14011 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14012     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14013     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14014     defined(BCM_56260_B0)
  14015     { /* SOC_REG_INT_GMAC0_GPIOOUTPUTEN_BCM53400_A0r */
  14016         soc_block_list[61],
  14017         soc_iprocreg,
  14018         1,
  14019         0,
  14020         0x18042198,
  14021         0,
  14022         0,
  14023         1,
  14024         soc_GMAC0_GPIOOUTPUTEN_BCM53400_A0r_fields,
  14025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14026         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  14027         -1,
  14028         -1,
  14029     },
  14030 #endif /* chips */
  14031 
  14032 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14033     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14034     defined(BCM_56450_B1)
  14035     { /* SOC_REG_INT_GMAC0_GPIOSELECTr */
  14036         soc_block_list[61],
  14037         soc_iprocreg,
  14038         1,
  14039         0,
  14040         0x18022194,
  14041         0,
  14042         0,
  14043         1,
  14044         soc_GMAC0_GPIOSELECTr_fields,
  14045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14046         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  14047         -1,
  14048         -1,
  14049     },
  14050 #endif /* chips */
  14051 
  14052 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14053     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14054     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14055     defined(BCM_56260_B0)
  14056     { /* SOC_REG_INT_GMAC0_GPIOSELECT_BCM53400_A0r */
  14057         soc_block_list[61],
  14058         soc_iprocreg,
  14059         1,
  14060         0,
  14061         0x18042194,
  14062         0,
  14063         0,
  14064         1,
  14065         soc_GMAC0_GPIOSELECT_BCM53400_A0r_fields,
  14066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14067         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  14068         -1,
  14069         -1,
  14070     },
  14071 #endif /* chips */
  14072 
  14073 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14074     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14075     defined(BCM_56450_B1)
  14076     { /* SOC_REG_INT_GMAC0_GPTIMERr */
  14077         soc_block_list[61],
  14078         soc_iprocreg,
  14079         1,
  14080         0,
  14081         0x18022028,
  14082         0,
  14083         0,
  14084         1,
  14085         soc_GMAC0_GPTIMERr_fields,
  14086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14087         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14088         -1,
  14089         -1,
  14090     },
  14091 #endif /* chips */
  14092 
  14093 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14094     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14095     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14096     defined(BCM_56260_B0)
  14097     { /* SOC_REG_INT_GMAC0_GPTIMER_BCM53400_A0r */
  14098         soc_block_list[61],
  14099         soc_iprocreg,
  14100         1,
  14101         0,
  14102         0x18042028,
  14103         0,
  14104         0,
  14105         1,
  14106         soc_GMAC0_GPTIMER_BCM53400_A0r_fields,
  14107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14108         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14109         -1,
  14110         -1,
  14111     },
  14112 #endif /* chips */
  14113 
  14114 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14115     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14116     defined(BCM_56450_B1)
  14117     { /* SOC_REG_INT_GMAC0_INTMASKr */
  14118         soc_block_list[61],
  14119         soc_iprocreg,
  14120         1,
  14121         0,
  14122         0x18022024,
  14123         0,
  14124         0,
  14125         24,
  14126         soc_GMAC0_INTMASKr_fields,
  14127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14128         SOC_RESET_MASK_DEC(0xff01fdff, 0x00000000)
  14129         -1,
  14130         -1,
  14131     },
  14132 #endif /* chips */
  14133 
  14134 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14135     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14136     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14137     defined(BCM_56260_B0)
  14138     { /* SOC_REG_INT_GMAC0_INTMASK_BCM53400_A0r */
  14139         soc_block_list[61],
  14140         soc_iprocreg,
  14141         1,
  14142         0,
  14143         0x18042024,
  14144         0,
  14145         0,
  14146         24,
  14147         soc_GMAC0_INTMASK_BCM53400_A0r_fields,
  14148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14149         SOC_RESET_MASK_DEC(0xff01fdff, 0x00000000)
  14150         -1,
  14151         -1,
  14152     },
  14153 #endif /* chips */
  14154 
  14155 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14156     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14157     defined(BCM_56450_B1)
  14158     { /* SOC_REG_INT_GMAC0_INTRCVLAZYr */
  14159         soc_block_list[61],
  14160         soc_iprocreg,
  14161         1,
  14162         0,
  14163         0x18022100,
  14164         0,
  14165         0,
  14166         2,
  14167         soc_GMAC0_INTRCVLAZYr_fields,
  14168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14169         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14170         -1,
  14171         -1,
  14172     },
  14173 #endif /* chips */
  14174 
  14175 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14176     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14177     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14178     defined(BCM_56260_B0)
  14179     { /* SOC_REG_INT_GMAC0_INTRCVLAZY_BCM53400_A0r */
  14180         soc_block_list[61],
  14181         soc_iprocreg,
  14182         1,
  14183         0,
  14184         0x18042100,
  14185         0,
  14186         0,
  14187         2,
  14188         soc_GMAC0_INTRCVLAZY_BCM53400_A0r_fields,
  14189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14190         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14191         -1,
  14192         -1,
  14193     },
  14194 #endif /* chips */
  14195 
  14196 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14197     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14198     defined(BCM_56450_B1)
  14199     { /* SOC_REG_INT_GMAC0_INTSTATUSr */
  14200         soc_block_list[61],
  14201         soc_iprocreg,
  14202         1,
  14203         0,
  14204         0x18022020,
  14205         0,
  14206         0,
  14207         24,
  14208         soc_GMAC0_INTSTATUSr_fields,
  14209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14210         SOC_RESET_MASK_DEC(0xff01fdff, 0x00000000)
  14211         -1,
  14212         -1,
  14213     },
  14214 #endif /* chips */
  14215 
  14216 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14217     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14218     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14219     defined(BCM_56260_B0)
  14220     { /* SOC_REG_INT_GMAC0_INTSTATUS_BCM53400_A0r */
  14221         soc_block_list[61],
  14222         soc_iprocreg,
  14223         1,
  14224         0,
  14225         0x18042020,
  14226         0,
  14227         0,
  14228         24,
  14229         soc_GMAC0_INTSTATUS_BCM53400_A0r_fields,
  14230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14231         SOC_RESET_MASK_DEC(0xff01fdff, 0x00000000)
  14232         -1,
  14233         -1,
  14234     },
  14235 #endif /* chips */
  14236 
  14237 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14238     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14239     defined(BCM_56450_B1)
  14240     { /* SOC_REG_INT_GMAC0_MEMORYECCSTATUSr */
  14241         soc_block_list[61],
  14242         soc_iprocreg,
  14243         1,
  14244         0,
  14245         0x180221a4,
  14246         0,
  14247         0,
  14248         2,
  14249         soc_GMAC0_MEMORYECCSTATUSr_fields,
  14250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14251         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14252         -1,
  14253         -1,
  14254     },
  14255 #endif /* chips */
  14256 
  14257 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14258     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14259     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14260     defined(BCM_56260_B0)
  14261     { /* SOC_REG_INT_GMAC0_MEMORYECCSTATUS_BCM53400_A0r */
  14262         soc_block_list[61],
  14263         soc_iprocreg,
  14264         1,
  14265         0,
  14266         0x180421a4,
  14267         0,
  14268         0,
  14269         2,
  14270         soc_GMAC0_MEMORYECCSTATUS_BCM53400_A0r_fields,
  14271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14272         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14273         -1,
  14274         -1,
  14275     },
  14276 #endif /* chips */
  14277 
  14278 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14279     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14280     defined(BCM_56450_B1)
  14281     { /* SOC_REG_INT_GMAC0_PHYACCESSr */
  14282         soc_block_list[61],
  14283         soc_iprocreg,
  14284         1,
  14285         0,
  14286         0x18022180,
  14287         0,
  14288         0,
  14289         5,
  14290         soc_GMAC0_PHYACCESSr_fields,
  14291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14292         SOC_RESET_MASK_DEC(0x7f1fffff, 0x00000000)
  14293         -1,
  14294         -1,
  14295     },
  14296 #endif /* chips */
  14297 
  14298 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14299     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14300     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14301     defined(BCM_56260_B0)
  14302     { /* SOC_REG_INT_GMAC0_PHYACCESS_BCM53400_A0r */
  14303         soc_block_list[61],
  14304         soc_iprocreg,
  14305         1,
  14306         0,
  14307         0x18042180,
  14308         0,
  14309         0,
  14310         5,
  14311         soc_GMAC0_PHYACCESS_BCM53400_A0r_fields,
  14312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14313         SOC_RESET_MASK_DEC(0x7f1fffff, 0x00000000)
  14314         -1,
  14315         -1,
  14316     },
  14317 #endif /* chips */
  14318 
  14319 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14320     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14321     defined(BCM_56450_B1)
  14322     { /* SOC_REG_INT_GMAC0_PHYCONTROLr */
  14323         soc_block_list[61],
  14324         soc_iprocreg,
  14325         1,
  14326         0,
  14327         0x18022188,
  14328         0,
  14329         0,
  14330         3,
  14331         soc_GMAC0_PHYCONTROLr_fields,
  14332         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  14333         SOC_RESET_MASK_DEC(0x00ff001f, 0x00000000)
  14334         -1,
  14335         -1,
  14336     },
  14337 #endif /* chips */
  14338 
  14339 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14340     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14341     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14342     defined(BCM_56260_B0)
  14343     { /* SOC_REG_INT_GMAC0_PHYCONTROL_BCM53400_A0r */
  14344         soc_block_list[61],
  14345         soc_iprocreg,
  14346         1,
  14347         0,
  14348         0x18042188,
  14349         0,
  14350         0,
  14351         3,
  14352         soc_GMAC0_PHYCONTROL_BCM53400_A0r_fields,
  14353         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  14354         SOC_RESET_MASK_DEC(0x00ff001f, 0x00000000)
  14355         -1,
  14356         -1,
  14357     },
  14358 #endif /* chips */
  14359 
  14360 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14361     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14362     defined(BCM_56450_B1)
  14363     { /* SOC_REG_INT_GMAC0_POWERCONTROLr */
  14364         soc_block_list[61],
  14365         soc_iprocreg,
  14366         1,
  14367         0,
  14368         0x180221e8,
  14369         0,
  14370         0,
  14371         1,
  14372         soc_GMAC0_POWERCONTROLr_fields,
  14373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14374         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  14375         -1,
  14376         -1,
  14377     },
  14378 #endif /* chips */
  14379 
  14380 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14381     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14382     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14383     defined(BCM_56260_B0)
  14384     { /* SOC_REG_INT_GMAC0_POWERCONTROL_BCM53400_A0r */
  14385         soc_block_list[61],
  14386         soc_iprocreg,
  14387         1,
  14388         0,
  14389         0x180421e8,
  14390         0,
  14391         0,
  14392         1,
  14393         soc_GMAC0_POWERCONTROL_BCM53400_A0r_fields,
  14394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14395         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  14396         -1,
  14397         -1,
  14398     },
  14399 #endif /* chips */
  14400 
  14401 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14402     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14403     defined(BCM_56450_B1)
  14404     { /* SOC_REG_INT_GMAC0_RCVADDR_HIGHr */
  14405         soc_block_list[61],
  14406         soc_iprocreg,
  14407         1,
  14408         0,
  14409         0x1802222c,
  14410         0,
  14411         0,
  14412         1,
  14413         soc_GMAC0_RCVADDR_HIGHr_fields,
  14414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14416         -1,
  14417         -1,
  14418     },
  14419 #endif /* chips */
  14420 
  14421 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14422     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14423     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14424     defined(BCM_56260_B0)
  14425     { /* SOC_REG_INT_GMAC0_RCVADDR_HIGH_BCM53400_A0r */
  14426         soc_block_list[61],
  14427         soc_iprocreg,
  14428         1,
  14429         0,
  14430         0x1804222c,
  14431         0,
  14432         0,
  14433         1,
  14434         soc_GMAC0_RCVADDR_HIGH_BCM53400_A0r_fields,
  14435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14436         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14437         -1,
  14438         -1,
  14439     },
  14440 #endif /* chips */
  14441 
  14442 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14443     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14444     defined(BCM_56450_B1)
  14445     { /* SOC_REG_INT_GMAC0_RCVADDR_LOWr */
  14446         soc_block_list[61],
  14447         soc_iprocreg,
  14448         1,
  14449         0,
  14450         0x18022228,
  14451         0,
  14452         0,
  14453         2,
  14454         soc_GMAC0_RCVADDR_LOWr_fields,
  14455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14456         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14457         -1,
  14458         -1,
  14459     },
  14460 #endif /* chips */
  14461 
  14462 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14463     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14464     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14465     defined(BCM_56260_B0)
  14466     { /* SOC_REG_INT_GMAC0_RCVADDR_LOW_BCM53400_A0r */
  14467         soc_block_list[61],
  14468         soc_iprocreg,
  14469         1,
  14470         0,
  14471         0x18042228,
  14472         0,
  14473         0,
  14474         2,
  14475         soc_GMAC0_RCVADDR_LOW_BCM53400_A0r_fields,
  14476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14478         -1,
  14479         -1,
  14480     },
  14481 #endif /* chips */
  14482 
  14483 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14484     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14485     defined(BCM_56450_B1)
  14486     { /* SOC_REG_INT_GMAC0_RCVCONTROLr */
  14487         soc_block_list[61],
  14488         soc_iprocreg,
  14489         1,
  14490         0,
  14491         0x18022220,
  14492         0,
  14493         0,
  14494         11,
  14495         soc_GMAC0_RCVCONTROLr_fields,
  14496         SOC_RESET_VAL_DEC(0x00040008, 0x00000000)
  14497         SOC_RESET_MASK_DEC(0x03ff3eff, 0x00000000)
  14498         -1,
  14499         -1,
  14500     },
  14501 #endif /* chips */
  14502 
  14503 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14504     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14505     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14506     defined(BCM_56260_B0)
  14507     { /* SOC_REG_INT_GMAC0_RCVCONTROL_BCM53400_A0r */
  14508         soc_block_list[61],
  14509         soc_iprocreg,
  14510         1,
  14511         0,
  14512         0x18042220,
  14513         0,
  14514         0,
  14515         11,
  14516         soc_GMAC0_RCVCONTROL_BCM53400_A0r_fields,
  14517         SOC_RESET_VAL_DEC(0x00040008, 0x00000000)
  14518         SOC_RESET_MASK_DEC(0x03ff3eff, 0x00000000)
  14519         -1,
  14520         -1,
  14521     },
  14522 #endif /* chips */
  14523 
  14524 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14525     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14526     defined(BCM_56450_B1)
  14527     { /* SOC_REG_INT_GMAC0_RCVPTRr */
  14528         soc_block_list[61],
  14529         soc_iprocreg,
  14530         1,
  14531         0,
  14532         0x18022224,
  14533         0,
  14534         0,
  14535         1,
  14536         soc_GMAC0_RCVPTRr_fields,
  14537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14538         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  14539         -1,
  14540         -1,
  14541     },
  14542 #endif /* chips */
  14543 
  14544 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14545     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14546     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14547     defined(BCM_56260_B0)
  14548     { /* SOC_REG_INT_GMAC0_RCVPTR_BCM53400_A0r */
  14549         soc_block_list[61],
  14550         soc_iprocreg,
  14551         1,
  14552         0,
  14553         0x18042224,
  14554         0,
  14555         0,
  14556         1,
  14557         soc_GMAC0_RCVPTR_BCM53400_A0r_fields,
  14558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14559         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  14560         -1,
  14561         -1,
  14562     },
  14563 #endif /* chips */
  14564 
  14565 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14566     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14567     defined(BCM_56450_B1)
  14568     { /* SOC_REG_INT_GMAC0_RCVSTATUS0r */
  14569         soc_block_list[61],
  14570         soc_iprocreg,
  14571         1,
  14572         0,
  14573         0x18022230,
  14574         SOC_REG_FLAG_RO,
  14575         0,
  14576         2,
  14577         soc_GMAC0_RCVSTATUS0r_fields,
  14578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14579         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  14580         -1,
  14581         -1,
  14582     },
  14583 #endif /* chips */
  14584 
  14585 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14586     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14587     defined(BCM_56450_B1)
  14588     { /* SOC_REG_INT_GMAC0_RCVSTATUS1r */
  14589         soc_block_list[61],
  14590         soc_iprocreg,
  14591         1,
  14592         0,
  14593         0x18022234,
  14594         SOC_REG_FLAG_RO,
  14595         0,
  14596         2,
  14597         soc_GMAC0_RCVSTATUS1r_fields,
  14598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14599         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  14600         -1,
  14601         -1,
  14602     },
  14603 #endif /* chips */
  14604 
  14605 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14606     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14607     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14608     defined(BCM_56260_B0)
  14609     { /* SOC_REG_INT_GMAC0_RCVSTATUS0_BCM53400_A0r */
  14610         soc_block_list[61],
  14611         soc_iprocreg,
  14612         1,
  14613         0,
  14614         0x18042230,
  14615         SOC_REG_FLAG_RO,
  14616         0,
  14617         2,
  14618         soc_GMAC0_RCVSTATUS0_BCM53400_A0r_fields,
  14619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14620         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  14621         -1,
  14622         -1,
  14623     },
  14624 #endif /* chips */
  14625 
  14626 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14627     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14628     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14629     defined(BCM_56260_B0)
  14630     { /* SOC_REG_INT_GMAC0_RCVSTATUS1_BCM53400_A0r */
  14631         soc_block_list[61],
  14632         soc_iprocreg,
  14633         1,
  14634         0,
  14635         0x18042234,
  14636         SOC_REG_FLAG_RO,
  14637         0,
  14638         2,
  14639         soc_GMAC0_RCVSTATUS1_BCM53400_A0r_fields,
  14640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14641         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  14642         -1,
  14643         -1,
  14644     },
  14645 #endif /* chips */
  14646 
  14647 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  14648     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
  14649     defined(BCM_56260_A0) || defined(BCM_56260_B0)
  14650     { /* SOC_REG_INT_GMAC0_RXPRSR_L3r */
  14651         soc_block_list[61],
  14652         soc_iprocreg,
  14653         1,
  14654         0,
  14655         0x180422e8,
  14656         0,
  14657         0,
  14658         2,
  14659         soc_GMAC0_RXPRSR_L3r_fields,
  14660         SOC_RESET_VAL_DEC(0x86dd0800, 0x00000000)
  14661         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14662         -1,
  14663         -1,
  14664     },
  14665 #endif /* chips */
  14666 
  14667 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  14668     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
  14669     defined(BCM_56260_A0) || defined(BCM_56260_B0)
  14670     { /* SOC_REG_INT_GMAC0_RXPRSR_MAXLENr */
  14671         soc_block_list[61],
  14672         soc_iprocreg,
  14673         1,
  14674         0,
  14675         0x180422ec,
  14676         0,
  14677         0,
  14678         1,
  14679         soc_GMAC0_RXPRSR_MAXLENr_fields,
  14680         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  14681         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  14682         -1,
  14683         -1,
  14684     },
  14685 #endif /* chips */
  14686 
  14687 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  14688     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
  14689     defined(BCM_56260_A0) || defined(BCM_56260_B0)
  14690     { /* SOC_REG_INT_GMAC0_RXPRSR_VLANr */
  14691         soc_block_list[61],
  14692         soc_iprocreg,
  14693         1,
  14694         0,
  14695         0x180422e4,
  14696         0,
  14697         0,
  14698         2,
  14699         soc_GMAC0_RXPRSR_VLANr_fields,
  14700         SOC_RESET_VAL_DEC(0x81008100, 0x00000000)
  14701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14702         -1,
  14703         -1,
  14704     },
  14705 #endif /* chips */
  14706 
  14707 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14708     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14709     defined(BCM_56450_B1)
  14710     { /* SOC_REG_INT_GMAC0_RXQCONTROLr */
  14711         soc_block_list[61],
  14712         soc_iprocreg,
  14713         1,
  14714         0,
  14715         0x18022190,
  14716         0,
  14717         0,
  14718         3,
  14719         soc_GMAC0_RXQCONTROLr_fields,
  14720         SOC_RESET_VAL_DEC(0x06000001, 0x00000000)
  14721         SOC_RESET_MASK_DEC(0x7f000fff, 0x00000000)
  14722         -1,
  14723         -1,
  14724     },
  14725 #endif /* chips */
  14726 
  14727 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14728     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14729     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14730     defined(BCM_56260_B0)
  14731     { /* SOC_REG_INT_GMAC0_RXQCONTROL_BCM53400_A0r */
  14732         soc_block_list[61],
  14733         soc_iprocreg,
  14734         1,
  14735         0,
  14736         0x18042190,
  14737         0,
  14738         0,
  14739         3,
  14740         soc_GMAC0_RXQCONTROL_BCM53400_A0r_fields,
  14741         SOC_RESET_VAL_DEC(0x06000001, 0x00000000)
  14742         SOC_RESET_MASK_DEC(0x7f000fff, 0x00000000)
  14743         -1,
  14744         -1,
  14745     },
  14746 #endif /* chips */
  14747 
  14748 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14749     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14750     defined(BCM_56450_B1)
  14751     { /* SOC_REG_INT_GMAC0_RXSACHANGESr */
  14752         soc_block_list[61],
  14753         soc_iprocreg,
  14754         1,
  14755         0,
  14756         0x18022424,
  14757         0,
  14758         0,
  14759         1,
  14760         soc_GMAC0_RXSACHANGESr_fields,
  14761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14762         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14763         -1,
  14764         -1,
  14765     },
  14766 #endif /* chips */
  14767 
  14768 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14769     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14770     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14771     defined(BCM_56260_B0)
  14772     { /* SOC_REG_INT_GMAC0_RXSACHANGES_BCM53400_A0r */
  14773         soc_block_list[61],
  14774         soc_iprocreg,
  14775         1,
  14776         0,
  14777         0x18042424,
  14778         0,
  14779         0,
  14780         1,
  14781         soc_GMAC0_RXSACHANGES_BCM53400_A0r_fields,
  14782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14783         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14784         -1,
  14785         -1,
  14786     },
  14787 #endif /* chips */
  14788 
  14789 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14790     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14791     defined(BCM_56450_B1)
  14792     { /* SOC_REG_INT_GMAC0_RXUNICASTPKTSr */
  14793         soc_block_list[61],
  14794         soc_iprocreg,
  14795         1,
  14796         0,
  14797         0x18022428,
  14798         0,
  14799         0,
  14800         1,
  14801         soc_GMAC0_RXUNICASTPKTSr_fields,
  14802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14803         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14804         -1,
  14805         -1,
  14806     },
  14807 #endif /* chips */
  14808 
  14809 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14810     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14811     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14812     defined(BCM_56260_B0)
  14813     { /* SOC_REG_INT_GMAC0_RXUNICASTPKTS_BCM53400_A0r */
  14814         soc_block_list[61],
  14815         soc_iprocreg,
  14816         1,
  14817         0,
  14818         0x18042428,
  14819         0,
  14820         0,
  14821         1,
  14822         soc_GMAC0_RXUNICASTPKTS_BCM53400_A0r_fields,
  14823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14824         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14825         -1,
  14826         -1,
  14827     },
  14828 #endif /* chips */
  14829 
  14830 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14831     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14832     defined(BCM_56450_B1)
  14833     { /* SOC_REG_INT_GMAC0_RX_64r */
  14834         soc_block_list[61],
  14835         soc_iprocreg,
  14836         1,
  14837         0,
  14838         0x180223d0,
  14839         0,
  14840         0,
  14841         1,
  14842         soc_GMAC0_RX_64r_fields,
  14843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14844         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14845         -1,
  14846         -1,
  14847     },
  14848 #endif /* chips */
  14849 
  14850 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14851     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14852     defined(BCM_56450_B1)
  14853     { /* SOC_REG_INT_GMAC0_RX_1024_1522r */
  14854         soc_block_list[61],
  14855         soc_iprocreg,
  14856         1,
  14857         0,
  14858         0x180223e4,
  14859         0,
  14860         0,
  14861         1,
  14862         soc_GMAC0_RX_1024_1522r_fields,
  14863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14864         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14865         -1,
  14866         -1,
  14867     },
  14868 #endif /* chips */
  14869 
  14870 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14871     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14872     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14873     defined(BCM_56260_B0)
  14874     { /* SOC_REG_INT_GMAC0_RX_1024_1522_BCM53400_A0r */
  14875         soc_block_list[61],
  14876         soc_iprocreg,
  14877         1,
  14878         0,
  14879         0x180423e4,
  14880         0,
  14881         0,
  14882         1,
  14883         soc_GMAC0_RX_1024_1522_BCM53400_A0r_fields,
  14884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14885         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14886         -1,
  14887         -1,
  14888     },
  14889 #endif /* chips */
  14890 
  14891 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14892     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14893     defined(BCM_56450_B1)
  14894     { /* SOC_REG_INT_GMAC0_RX_128_255r */
  14895         soc_block_list[61],
  14896         soc_iprocreg,
  14897         1,
  14898         0,
  14899         0x180223d8,
  14900         0,
  14901         0,
  14902         1,
  14903         soc_GMAC0_RX_128_255r_fields,
  14904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14905         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14906         -1,
  14907         -1,
  14908     },
  14909 #endif /* chips */
  14910 
  14911 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14912     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14913     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14914     defined(BCM_56260_B0)
  14915     { /* SOC_REG_INT_GMAC0_RX_128_255_BCM53400_A0r */
  14916         soc_block_list[61],
  14917         soc_iprocreg,
  14918         1,
  14919         0,
  14920         0x180423d8,
  14921         0,
  14922         0,
  14923         1,
  14924         soc_GMAC0_RX_128_255_BCM53400_A0r_fields,
  14925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14926         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14927         -1,
  14928         -1,
  14929     },
  14930 #endif /* chips */
  14931 
  14932 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14933     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14934     defined(BCM_56450_B1)
  14935     { /* SOC_REG_INT_GMAC0_RX_1523_2047r */
  14936         soc_block_list[61],
  14937         soc_iprocreg,
  14938         1,
  14939         0,
  14940         0x180223e8,
  14941         0,
  14942         0,
  14943         1,
  14944         soc_GMAC0_RX_1523_2047r_fields,
  14945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14946         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14947         -1,
  14948         -1,
  14949     },
  14950 #endif /* chips */
  14951 
  14952 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14953     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14954     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14955     defined(BCM_56260_B0)
  14956     { /* SOC_REG_INT_GMAC0_RX_1523_2047_BCM53400_A0r */
  14957         soc_block_list[61],
  14958         soc_iprocreg,
  14959         1,
  14960         0,
  14961         0x180423e8,
  14962         0,
  14963         0,
  14964         1,
  14965         soc_GMAC0_RX_1523_2047_BCM53400_A0r_fields,
  14966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14967         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14968         -1,
  14969         -1,
  14970     },
  14971 #endif /* chips */
  14972 
  14973 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14974     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14975     defined(BCM_56450_B1)
  14976     { /* SOC_REG_INT_GMAC0_RX_2048_4095r */
  14977         soc_block_list[61],
  14978         soc_iprocreg,
  14979         1,
  14980         0,
  14981         0x180223ec,
  14982         0,
  14983         0,
  14984         1,
  14985         soc_GMAC0_RX_2048_4095r_fields,
  14986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14987         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14988         -1,
  14989         -1,
  14990     },
  14991 #endif /* chips */
  14992 
  14993 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14994     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14995     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14996     defined(BCM_56260_B0)
  14997     { /* SOC_REG_INT_GMAC0_RX_2048_4095_BCM53400_A0r */
  14998         soc_block_list[61],
  14999         soc_iprocreg,
  15000         1,
  15001         0,
  15002         0x180423ec,
  15003         0,
  15004         0,
  15005         1,
  15006         soc_GMAC0_RX_2048_4095_BCM53400_A0r_fields,
  15007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15008         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15009         -1,
  15010         -1,
  15011     },
  15012 #endif /* chips */
  15013 
  15014 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15015     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15016     defined(BCM_56450_B1)
  15017     { /* SOC_REG_INT_GMAC0_RX_256_511r */
  15018         soc_block_list[61],
  15019         soc_iprocreg,
  15020         1,
  15021         0,
  15022         0x180223dc,
  15023         0,
  15024         0,
  15025         1,
  15026         soc_GMAC0_RX_256_511r_fields,
  15027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15028         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15029         -1,
  15030         -1,
  15031     },
  15032 #endif /* chips */
  15033 
  15034 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15035     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15036     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15037     defined(BCM_56260_B0)
  15038     { /* SOC_REG_INT_GMAC0_RX_256_511_BCM53400_A0r */
  15039         soc_block_list[61],
  15040         soc_iprocreg,
  15041         1,
  15042         0,
  15043         0x180423dc,
  15044         0,
  15045         0,
  15046         1,
  15047         soc_GMAC0_RX_256_511_BCM53400_A0r_fields,
  15048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15049         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15050         -1,
  15051         -1,
  15052     },
  15053 #endif /* chips */
  15054 
  15055 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15056     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15057     defined(BCM_56450_B1)
  15058     { /* SOC_REG_INT_GMAC0_RX_4096_8191r */
  15059         soc_block_list[61],
  15060         soc_iprocreg,
  15061         1,
  15062         0,
  15063         0x180223f0,
  15064         0,
  15065         0,
  15066         1,
  15067         soc_GMAC0_RX_4096_8191r_fields,
  15068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15069         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15070         -1,
  15071         -1,
  15072     },
  15073 #endif /* chips */
  15074 
  15075 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15076     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15077     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15078     defined(BCM_56260_B0)
  15079     { /* SOC_REG_INT_GMAC0_RX_4096_8191_BCM53400_A0r */
  15080         soc_block_list[61],
  15081         soc_iprocreg,
  15082         1,
  15083         0,
  15084         0x180423f0,
  15085         0,
  15086         0,
  15087         1,
  15088         soc_GMAC0_RX_4096_8191_BCM53400_A0r_fields,
  15089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15090         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15091         -1,
  15092         -1,
  15093     },
  15094 #endif /* chips */
  15095 
  15096 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15097     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15098     defined(BCM_56450_B1)
  15099     { /* SOC_REG_INT_GMAC0_RX_512_1023r */
  15100         soc_block_list[61],
  15101         soc_iprocreg,
  15102         1,
  15103         0,
  15104         0x180223e0,
  15105         0,
  15106         0,
  15107         1,
  15108         soc_GMAC0_RX_512_1023r_fields,
  15109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15110         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15111         -1,
  15112         -1,
  15113     },
  15114 #endif /* chips */
  15115 
  15116 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15117     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15118     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15119     defined(BCM_56260_B0)
  15120     { /* SOC_REG_INT_GMAC0_RX_512_1023_BCM53400_A0r */
  15121         soc_block_list[61],
  15122         soc_iprocreg,
  15123         1,
  15124         0,
  15125         0x180423e0,
  15126         0,
  15127         0,
  15128         1,
  15129         soc_GMAC0_RX_512_1023_BCM53400_A0r_fields,
  15130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15132         -1,
  15133         -1,
  15134     },
  15135 #endif /* chips */
  15136 
  15137 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15138     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15139     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15140     defined(BCM_56260_B0)
  15141     { /* SOC_REG_INT_GMAC0_RX_64_BCM53400_A0r */
  15142         soc_block_list[61],
  15143         soc_iprocreg,
  15144         1,
  15145         0,
  15146         0x180423d0,
  15147         0,
  15148         0,
  15149         1,
  15150         soc_GMAC0_RX_64_BCM53400_A0r_fields,
  15151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15152         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15153         -1,
  15154         -1,
  15155     },
  15156 #endif /* chips */
  15157 
  15158 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15159     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15160     defined(BCM_56450_B1)
  15161     { /* SOC_REG_INT_GMAC0_RX_65_127r */
  15162         soc_block_list[61],
  15163         soc_iprocreg,
  15164         1,
  15165         0,
  15166         0x180223d4,
  15167         0,
  15168         0,
  15169         1,
  15170         soc_GMAC0_RX_65_127r_fields,
  15171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15173         -1,
  15174         -1,
  15175     },
  15176 #endif /* chips */
  15177 
  15178 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15179     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15180     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15181     defined(BCM_56260_B0)
  15182     { /* SOC_REG_INT_GMAC0_RX_65_127_BCM53400_A0r */
  15183         soc_block_list[61],
  15184         soc_iprocreg,
  15185         1,
  15186         0,
  15187         0x180423d4,
  15188         0,
  15189         0,
  15190         1,
  15191         soc_GMAC0_RX_65_127_BCM53400_A0r_fields,
  15192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15193         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15194         -1,
  15195         -1,
  15196     },
  15197 #endif /* chips */
  15198 
  15199 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15200     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15201     defined(BCM_56450_B1)
  15202     { /* SOC_REG_INT_GMAC0_RX_8192_MAXr */
  15203         soc_block_list[61],
  15204         soc_iprocreg,
  15205         1,
  15206         0,
  15207         0x180223f4,
  15208         0,
  15209         0,
  15210         1,
  15211         soc_GMAC0_RX_8192_MAXr_fields,
  15212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15213         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15214         -1,
  15215         -1,
  15216     },
  15217 #endif /* chips */
  15218 
  15219 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15220     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15221     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15222     defined(BCM_56260_B0)
  15223     { /* SOC_REG_INT_GMAC0_RX_8192_MAX_BCM53400_A0r */
  15224         soc_block_list[61],
  15225         soc_iprocreg,
  15226         1,
  15227         0,
  15228         0x180423f4,
  15229         0,
  15230         0,
  15231         1,
  15232         soc_GMAC0_RX_8192_MAX_BCM53400_A0r_fields,
  15233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15234         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15235         -1,
  15236         -1,
  15237     },
  15238 #endif /* chips */
  15239 
  15240 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15241     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15242     defined(BCM_56450_B1)
  15243     { /* SOC_REG_INT_GMAC0_RX_ALIGNr */
  15244         soc_block_list[61],
  15245         soc_iprocreg,
  15246         1,
  15247         0,
  15248         0x18022414,
  15249         0,
  15250         0,
  15251         1,
  15252         soc_GMAC0_RX_ALIGNr_fields,
  15253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15254         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15255         -1,
  15256         -1,
  15257     },
  15258 #endif /* chips */
  15259 
  15260 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15261     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15262     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15263     defined(BCM_56260_B0)
  15264     { /* SOC_REG_INT_GMAC0_RX_ALIGN_BCM53400_A0r */
  15265         soc_block_list[61],
  15266         soc_iprocreg,
  15267         1,
  15268         0,
  15269         0x18042414,
  15270         0,
  15271         0,
  15272         1,
  15273         soc_GMAC0_RX_ALIGN_BCM53400_A0r_fields,
  15274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15276         -1,
  15277         -1,
  15278     },
  15279 #endif /* chips */
  15280 
  15281 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15282     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15283     defined(BCM_56450_B1)
  15284     { /* SOC_REG_INT_GMAC0_RX_ALL_OCTETS_HIr */
  15285         soc_block_list[61],
  15286         soc_iprocreg,
  15287         1,
  15288         0,
  15289         0x180223c0,
  15290         0,
  15291         0,
  15292         1,
  15293         soc_GMAC0_RX_ALL_OCTETS_HIr_fields,
  15294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15295         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15296         -1,
  15297         -1,
  15298     },
  15299 #endif /* chips */
  15300 
  15301 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15302     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15303     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15304     defined(BCM_56260_B0)
  15305     { /* SOC_REG_INT_GMAC0_RX_ALL_OCTETS_HI_BCM53400_A0r */
  15306         soc_block_list[61],
  15307         soc_iprocreg,
  15308         1,
  15309         0,
  15310         0x180423c0,
  15311         0,
  15312         0,
  15313         1,
  15314         soc_GMAC0_RX_ALL_OCTETS_HI_BCM53400_A0r_fields,
  15315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15316         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15317         -1,
  15318         -1,
  15319     },
  15320 #endif /* chips */
  15321 
  15322 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15323     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15324     defined(BCM_56450_B1)
  15325     { /* SOC_REG_INT_GMAC0_RX_ALL_OCTETS_LOr */
  15326         soc_block_list[61],
  15327         soc_iprocreg,
  15328         1,
  15329         0,
  15330         0x180223bc,
  15331         0,
  15332         0,
  15333         1,
  15334         soc_GMAC0_RX_ALL_OCTETS_LOr_fields,
  15335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15336         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15337         -1,
  15338         -1,
  15339     },
  15340 #endif /* chips */
  15341 
  15342 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15343     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15344     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15345     defined(BCM_56260_B0)
  15346     { /* SOC_REG_INT_GMAC0_RX_ALL_OCTETS_LO_BCM53400_A0r */
  15347         soc_block_list[61],
  15348         soc_iprocreg,
  15349         1,
  15350         0,
  15351         0x180423bc,
  15352         0,
  15353         0,
  15354         1,
  15355         soc_GMAC0_RX_ALL_OCTETS_LO_BCM53400_A0r_fields,
  15356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15357         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15358         -1,
  15359         -1,
  15360     },
  15361 #endif /* chips */
  15362 
  15363 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15364     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15365     defined(BCM_56450_B1)
  15366     { /* SOC_REG_INT_GMAC0_RX_ALL_PKTSr */
  15367         soc_block_list[61],
  15368         soc_iprocreg,
  15369         1,
  15370         0,
  15371         0x180223c4,
  15372         0,
  15373         0,
  15374         1,
  15375         soc_GMAC0_RX_ALL_PKTSr_fields,
  15376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15377         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15378         -1,
  15379         -1,
  15380     },
  15381 #endif /* chips */
  15382 
  15383 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15384     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15385     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15386     defined(BCM_56260_B0)
  15387     { /* SOC_REG_INT_GMAC0_RX_ALL_PKTS_BCM53400_A0r */
  15388         soc_block_list[61],
  15389         soc_iprocreg,
  15390         1,
  15391         0,
  15392         0x180423c4,
  15393         0,
  15394         0,
  15395         1,
  15396         soc_GMAC0_RX_ALL_PKTS_BCM53400_A0r_fields,
  15397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15398         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15399         -1,
  15400         -1,
  15401     },
  15402 #endif /* chips */
  15403 
  15404 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15405     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15406     defined(BCM_56450_B1)
  15407     { /* SOC_REG_INT_GMAC0_RX_BRDCASTr */
  15408         soc_block_list[61],
  15409         soc_iprocreg,
  15410         1,
  15411         0,
  15412         0x180223c8,
  15413         0,
  15414         0,
  15415         1,
  15416         soc_GMAC0_RX_BRDCASTr_fields,
  15417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15418         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15419         -1,
  15420         -1,
  15421     },
  15422 #endif /* chips */
  15423 
  15424 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15425     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15426     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15427     defined(BCM_56260_B0)
  15428     { /* SOC_REG_INT_GMAC0_RX_BRDCAST_BCM53400_A0r */
  15429         soc_block_list[61],
  15430         soc_iprocreg,
  15431         1,
  15432         0,
  15433         0x180423c8,
  15434         0,
  15435         0,
  15436         1,
  15437         soc_GMAC0_RX_BRDCAST_BCM53400_A0r_fields,
  15438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15439         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15440         -1,
  15441         -1,
  15442     },
  15443 #endif /* chips */
  15444 
  15445 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15446     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15447     defined(BCM_56450_B1)
  15448     { /* SOC_REG_INT_GMAC0_RX_CNTRLr */
  15449         soc_block_list[61],
  15450         soc_iprocreg,
  15451         1,
  15452         0,
  15453         0x18022420,
  15454         0,
  15455         0,
  15456         1,
  15457         soc_GMAC0_RX_CNTRLr_fields,
  15458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15459         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15460         -1,
  15461         -1,
  15462     },
  15463 #endif /* chips */
  15464 
  15465 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15466     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15467     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15468     defined(BCM_56260_B0)
  15469     { /* SOC_REG_INT_GMAC0_RX_CNTRL_BCM53400_A0r */
  15470         soc_block_list[61],
  15471         soc_iprocreg,
  15472         1,
  15473         0,
  15474         0x18042420,
  15475         0,
  15476         0,
  15477         1,
  15478         soc_GMAC0_RX_CNTRL_BCM53400_A0r_fields,
  15479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15480         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15481         -1,
  15482         -1,
  15483     },
  15484 #endif /* chips */
  15485 
  15486 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15487     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15488     defined(BCM_56450_B1)
  15489     { /* SOC_REG_INT_GMAC0_RX_CRCr */
  15490         soc_block_list[61],
  15491         soc_iprocreg,
  15492         1,
  15493         0,
  15494         0x18022410,
  15495         0,
  15496         0,
  15497         1,
  15498         soc_GMAC0_RX_CRCr_fields,
  15499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15501         -1,
  15502         -1,
  15503     },
  15504 #endif /* chips */
  15505 
  15506 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15507     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15508     defined(BCM_56450_B1)
  15509     { /* SOC_REG_INT_GMAC0_RX_CRC_ALIGNr */
  15510         soc_block_list[61],
  15511         soc_iprocreg,
  15512         1,
  15513         0,
  15514         0x18022408,
  15515         0,
  15516         0,
  15517         1,
  15518         soc_GMAC0_RX_CRC_ALIGNr_fields,
  15519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15520         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15521         -1,
  15522         -1,
  15523     },
  15524 #endif /* chips */
  15525 
  15526 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15527     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15528     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15529     defined(BCM_56260_B0)
  15530     { /* SOC_REG_INT_GMAC0_RX_CRC_ALIGN_BCM53400_A0r */
  15531         soc_block_list[61],
  15532         soc_iprocreg,
  15533         1,
  15534         0,
  15535         0x18042408,
  15536         0,
  15537         0,
  15538         1,
  15539         soc_GMAC0_RX_CRC_ALIGN_BCM53400_A0r_fields,
  15540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15542         -1,
  15543         -1,
  15544     },
  15545 #endif /* chips */
  15546 
  15547 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15548     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15549     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15550     defined(BCM_56260_B0)
  15551     { /* SOC_REG_INT_GMAC0_RX_CRC_BCM53400_A0r */
  15552         soc_block_list[61],
  15553         soc_iprocreg,
  15554         1,
  15555         0,
  15556         0x18042410,
  15557         0,
  15558         0,
  15559         1,
  15560         soc_GMAC0_RX_CRC_BCM53400_A0r_fields,
  15561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15562         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15563         -1,
  15564         -1,
  15565     },
  15566 #endif /* chips */
  15567 
  15568 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15569     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15570     defined(BCM_56450_B1)
  15571     { /* SOC_REG_INT_GMAC0_RX_DROPr */
  15572         soc_block_list[61],
  15573         soc_iprocreg,
  15574         1,
  15575         0,
  15576         0x18022404,
  15577         0,
  15578         0,
  15579         1,
  15580         soc_GMAC0_RX_DROPr_fields,
  15581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15582         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15583         -1,
  15584         -1,
  15585     },
  15586 #endif /* chips */
  15587 
  15588 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15589     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15590     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15591     defined(BCM_56260_B0)
  15592     { /* SOC_REG_INT_GMAC0_RX_DROP_BCM53400_A0r */
  15593         soc_block_list[61],
  15594         soc_iprocreg,
  15595         1,
  15596         0,
  15597         0x18042404,
  15598         0,
  15599         0,
  15600         1,
  15601         soc_GMAC0_RX_DROP_BCM53400_A0r_fields,
  15602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15603         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15604         -1,
  15605         -1,
  15606     },
  15607 #endif /* chips */
  15608 
  15609 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15610     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15611     defined(BCM_56450_B1)
  15612     { /* SOC_REG_INT_GMAC0_RX_FRAGr */
  15613         soc_block_list[61],
  15614         soc_iprocreg,
  15615         1,
  15616         0,
  15617         0x18022400,
  15618         0,
  15619         0,
  15620         1,
  15621         soc_GMAC0_RX_FRAGr_fields,
  15622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15623         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15624         -1,
  15625         -1,
  15626     },
  15627 #endif /* chips */
  15628 
  15629 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15630     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15631     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15632     defined(BCM_56260_B0)
  15633     { /* SOC_REG_INT_GMAC0_RX_FRAG_BCM53400_A0r */
  15634         soc_block_list[61],
  15635         soc_iprocreg,
  15636         1,
  15637         0,
  15638         0x18042400,
  15639         0,
  15640         0,
  15641         1,
  15642         soc_GMAC0_RX_FRAG_BCM53400_A0r_fields,
  15643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15644         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15645         -1,
  15646         -1,
  15647     },
  15648 #endif /* chips */
  15649 
  15650 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15651     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15652     defined(BCM_56450_B1)
  15653     { /* SOC_REG_INT_GMAC0_RX_GD_OCTETS_HIr */
  15654         soc_block_list[61],
  15655         soc_iprocreg,
  15656         1,
  15657         0,
  15658         0x180223b4,
  15659         0,
  15660         0,
  15661         1,
  15662         soc_GMAC0_RX_GD_OCTETS_HIr_fields,
  15663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15664         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15665         -1,
  15666         -1,
  15667     },
  15668 #endif /* chips */
  15669 
  15670 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15671     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15672     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15673     defined(BCM_56260_B0)
  15674     { /* SOC_REG_INT_GMAC0_RX_GD_OCTETS_HI_BCM53400_A0r */
  15675         soc_block_list[61],
  15676         soc_iprocreg,
  15677         1,
  15678         0,
  15679         0x180423b4,
  15680         0,
  15681         0,
  15682         1,
  15683         soc_GMAC0_RX_GD_OCTETS_HI_BCM53400_A0r_fields,
  15684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15685         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15686         -1,
  15687         -1,
  15688     },
  15689 #endif /* chips */
  15690 
  15691 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15692     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15693     defined(BCM_56450_B1)
  15694     { /* SOC_REG_INT_GMAC0_RX_GD_OCTETS_LOr */
  15695         soc_block_list[61],
  15696         soc_iprocreg,
  15697         1,
  15698         0,
  15699         0x180223b0,
  15700         0,
  15701         0,
  15702         1,
  15703         soc_GMAC0_RX_GD_OCTETS_LOr_fields,
  15704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15705         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15706         -1,
  15707         -1,
  15708     },
  15709 #endif /* chips */
  15710 
  15711 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15712     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15713     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15714     defined(BCM_56260_B0)
  15715     { /* SOC_REG_INT_GMAC0_RX_GD_OCTETS_LO_BCM53400_A0r */
  15716         soc_block_list[61],
  15717         soc_iprocreg,
  15718         1,
  15719         0,
  15720         0x180423b0,
  15721         0,
  15722         0,
  15723         1,
  15724         soc_GMAC0_RX_GD_OCTETS_LO_BCM53400_A0r_fields,
  15725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15726         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15727         -1,
  15728         -1,
  15729     },
  15730 #endif /* chips */
  15731 
  15732 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15733     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15734     defined(BCM_56450_B1)
  15735     { /* SOC_REG_INT_GMAC0_RX_GD_PKTSr */
  15736         soc_block_list[61],
  15737         soc_iprocreg,
  15738         1,
  15739         0,
  15740         0x180223b8,
  15741         0,
  15742         0,
  15743         1,
  15744         soc_GMAC0_RX_GD_PKTSr_fields,
  15745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15746         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15747         -1,
  15748         -1,
  15749     },
  15750 #endif /* chips */
  15751 
  15752 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15753     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15754     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15755     defined(BCM_56260_B0)
  15756     { /* SOC_REG_INT_GMAC0_RX_GD_PKTS_BCM53400_A0r */
  15757         soc_block_list[61],
  15758         soc_iprocreg,
  15759         1,
  15760         0,
  15761         0x180423b8,
  15762         0,
  15763         0,
  15764         1,
  15765         soc_GMAC0_RX_GD_PKTS_BCM53400_A0r_fields,
  15766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15767         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15768         -1,
  15769         -1,
  15770     },
  15771 #endif /* chips */
  15772 
  15773 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15774     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15775     defined(BCM_56450_B1)
  15776     { /* SOC_REG_INT_GMAC0_RX_JABr */
  15777         soc_block_list[61],
  15778         soc_iprocreg,
  15779         1,
  15780         0,
  15781         0x180223f8,
  15782         0,
  15783         0,
  15784         1,
  15785         soc_GMAC0_RX_JABr_fields,
  15786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15787         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15788         -1,
  15789         -1,
  15790     },
  15791 #endif /* chips */
  15792 
  15793 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15794     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15795     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15796     defined(BCM_56260_B0)
  15797     { /* SOC_REG_INT_GMAC0_RX_JAB_BCM53400_A0r */
  15798         soc_block_list[61],
  15799         soc_iprocreg,
  15800         1,
  15801         0,
  15802         0x180423f8,
  15803         0,
  15804         0,
  15805         1,
  15806         soc_GMAC0_RX_JAB_BCM53400_A0r_fields,
  15807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15808         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15809         -1,
  15810         -1,
  15811     },
  15812 #endif /* chips */
  15813 
  15814 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15815     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15816     defined(BCM_56450_B1)
  15817     { /* SOC_REG_INT_GMAC0_RX_MULTr */
  15818         soc_block_list[61],
  15819         soc_iprocreg,
  15820         1,
  15821         0,
  15822         0x180223cc,
  15823         0,
  15824         0,
  15825         1,
  15826         soc_GMAC0_RX_MULTr_fields,
  15827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15828         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15829         -1,
  15830         -1,
  15831     },
  15832 #endif /* chips */
  15833 
  15834 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15835     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15836     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15837     defined(BCM_56260_B0)
  15838     { /* SOC_REG_INT_GMAC0_RX_MULT_BCM53400_A0r */
  15839         soc_block_list[61],
  15840         soc_iprocreg,
  15841         1,
  15842         0,
  15843         0x180423cc,
  15844         0,
  15845         0,
  15846         1,
  15847         soc_GMAC0_RX_MULT_BCM53400_A0r_fields,
  15848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15849         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15850         -1,
  15851         -1,
  15852     },
  15853 #endif /* chips */
  15854 
  15855 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15856     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15857     defined(BCM_56450_B1)
  15858     { /* SOC_REG_INT_GMAC0_RX_OVRr */
  15859         soc_block_list[61],
  15860         soc_iprocreg,
  15861         1,
  15862         0,
  15863         0x180223fc,
  15864         0,
  15865         0,
  15866         1,
  15867         soc_GMAC0_RX_OVRr_fields,
  15868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15870         -1,
  15871         -1,
  15872     },
  15873 #endif /* chips */
  15874 
  15875 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15876     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15877     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15878     defined(BCM_56260_B0)
  15879     { /* SOC_REG_INT_GMAC0_RX_OVR_BCM53400_A0r */
  15880         soc_block_list[61],
  15881         soc_iprocreg,
  15882         1,
  15883         0,
  15884         0x180423fc,
  15885         0,
  15886         0,
  15887         1,
  15888         soc_GMAC0_RX_OVR_BCM53400_A0r_fields,
  15889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15890         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15891         -1,
  15892         -1,
  15893     },
  15894 #endif /* chips */
  15895 
  15896 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15897     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15898     defined(BCM_56450_B1)
  15899     { /* SOC_REG_INT_GMAC0_RX_PAUSr */
  15900         soc_block_list[61],
  15901         soc_iprocreg,
  15902         1,
  15903         0,
  15904         0x1802241c,
  15905         0,
  15906         0,
  15907         1,
  15908         soc_GMAC0_RX_PAUSr_fields,
  15909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15910         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15911         -1,
  15912         -1,
  15913     },
  15914 #endif /* chips */
  15915 
  15916 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15917     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15918     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15919     defined(BCM_56260_B0)
  15920     { /* SOC_REG_INT_GMAC0_RX_PAUS_BCM53400_A0r */
  15921         soc_block_list[61],
  15922         soc_iprocreg,
  15923         1,
  15924         0,
  15925         0x1804241c,
  15926         0,
  15927         0,
  15928         1,
  15929         soc_GMAC0_RX_PAUS_BCM53400_A0r_fields,
  15930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15932         -1,
  15933         -1,
  15934     },
  15935 #endif /* chips */
  15936 
  15937 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15938     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15939     defined(BCM_56450_B1)
  15940     { /* SOC_REG_INT_GMAC0_RX_SYMr */
  15941         soc_block_list[61],
  15942         soc_iprocreg,
  15943         1,
  15944         0,
  15945         0x18022418,
  15946         0,
  15947         0,
  15948         1,
  15949         soc_GMAC0_RX_SYMr_fields,
  15950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15952         -1,
  15953         -1,
  15954     },
  15955 #endif /* chips */
  15956 
  15957 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15958     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15959     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15960     defined(BCM_56260_B0)
  15961     { /* SOC_REG_INT_GMAC0_RX_SYM_BCM53400_A0r */
  15962         soc_block_list[61],
  15963         soc_iprocreg,
  15964         1,
  15965         0,
  15966         0x18042418,
  15967         0,
  15968         0,
  15969         1,
  15970         soc_GMAC0_RX_SYM_BCM53400_A0r_fields,
  15971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15972         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15973         -1,
  15974         -1,
  15975     },
  15976 #endif /* chips */
  15977 
  15978 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15979     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15980     defined(BCM_56450_B1)
  15981     { /* SOC_REG_INT_GMAC0_RX_UNDr */
  15982         soc_block_list[61],
  15983         soc_iprocreg,
  15984         1,
  15985         0,
  15986         0x1802240c,
  15987         0,
  15988         0,
  15989         1,
  15990         soc_GMAC0_RX_UNDr_fields,
  15991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15993         -1,
  15994         -1,
  15995     },
  15996 #endif /* chips */
  15997 
  15998 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15999     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16000     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16001     defined(BCM_56260_B0)
  16002     { /* SOC_REG_INT_GMAC0_RX_UND_BCM53400_A0r */
  16003         soc_block_list[61],
  16004         soc_iprocreg,
  16005         1,
  16006         0,
  16007         0x1804240c,
  16008         0,
  16009         0,
  16010         1,
  16011         soc_GMAC0_RX_UND_BCM53400_A0r_fields,
  16012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16013         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16014         -1,
  16015         -1,
  16016     },
  16017 #endif /* chips */
  16018 
  16019 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16020     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16021     defined(BCM_56450_B1)
  16022     { /* SOC_REG_INT_GMAC0_SERDESCONTROLr */
  16023         soc_block_list[61],
  16024         soc_iprocreg,
  16025         1,
  16026         0,
  16027         0x180221a8,
  16028         0,
  16029         0,
  16030         19,
  16031         soc_GMAC0_SERDESCONTROLr_fields,
  16032         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  16033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16034         -1,
  16035         -1,
  16036     },
  16037 #endif /* chips */
  16038 
  16039 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16040     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16041     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16042     defined(BCM_56260_B0)
  16043     { /* SOC_REG_INT_GMAC0_SERDESCONTROL_BCM53400_A0r */
  16044         soc_block_list[61],
  16045         soc_iprocreg,
  16046         1,
  16047         0,
  16048         0x180421a8,
  16049         0,
  16050         0,
  16051         18,
  16052         soc_GMAC0_SERDESCONTROL_BCM53400_A0r_fields,
  16053         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  16054         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  16055         -1,
  16056         -1,
  16057     },
  16058 #endif /* chips */
  16059 
  16060 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16061     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16062     defined(BCM_56450_B1)
  16063     { /* SOC_REG_INT_GMAC0_SERDESSTATUS0r */
  16064         soc_block_list[61],
  16065         soc_iprocreg,
  16066         1,
  16067         0,
  16068         0x180221ac,
  16069         SOC_REG_FLAG_RO,
  16070         0,
  16071         9,
  16072         soc_GMAC0_SERDESSTATUS0r_fields,
  16073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16074         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16075         -1,
  16076         -1,
  16077     },
  16078 #endif /* chips */
  16079 
  16080 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16081     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16082     defined(BCM_56450_B1)
  16083     { /* SOC_REG_INT_GMAC0_SERDESSTATUS1r */
  16084         soc_block_list[61],
  16085         soc_iprocreg,
  16086         1,
  16087         0,
  16088         0x180221b0,
  16089         SOC_REG_FLAG_RO,
  16090         0,
  16091         6,
  16092         soc_GMAC0_SERDESSTATUS1r_fields,
  16093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16094         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16095         -1,
  16096         -1,
  16097     },
  16098 #endif /* chips */
  16099 
  16100 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16101     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16102     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16103     defined(BCM_56260_B0)
  16104     { /* SOC_REG_INT_GMAC0_SERDESSTATUS0_BCM53400_A0r */
  16105         soc_block_list[61],
  16106         soc_iprocreg,
  16107         1,
  16108         0,
  16109         0x180421ac,
  16110         SOC_REG_FLAG_RO,
  16111         0,
  16112         9,
  16113         soc_GMAC0_SERDESSTATUS0_BCM53400_A0r_fields,
  16114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16116         -1,
  16117         -1,
  16118     },
  16119 #endif /* chips */
  16120 
  16121 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16122     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16123     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16124     defined(BCM_56260_B0)
  16125     { /* SOC_REG_INT_GMAC0_SERDESSTATUS1_BCM53400_A0r */
  16126         soc_block_list[61],
  16127         soc_iprocreg,
  16128         1,
  16129         0,
  16130         0x180421b0,
  16131         SOC_REG_FLAG_RO,
  16132         0,
  16133         6,
  16134         soc_GMAC0_SERDESSTATUS1_BCM53400_A0r_fields,
  16135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16137         -1,
  16138         -1,
  16139     },
  16140 #endif /* chips */
  16141 
  16142 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16143     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16144     defined(BCM_56450_B1)
  16145     { /* SOC_REG_INT_GMAC0_TXARB_WRR_THr */
  16146         soc_block_list[61],
  16147         soc_iprocreg,
  16148         1,
  16149         0,
  16150         0x18022108,
  16151         0,
  16152         0,
  16153         4,
  16154         soc_GMAC0_TXARB_WRR_THr_fields,
  16155         SOC_RESET_VAL_DEC(0x0a0a0a0a, 0x00000000)
  16156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16157         -1,
  16158         -1,
  16159     },
  16160 #endif /* chips */
  16161 
  16162 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16163     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16164     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16165     defined(BCM_56260_B0)
  16166     { /* SOC_REG_INT_GMAC0_TXARB_WRR_TH_BCM53400_A0r */
  16167         soc_block_list[61],
  16168         soc_iprocreg,
  16169         1,
  16170         0,
  16171         0x18042108,
  16172         0,
  16173         0,
  16174         4,
  16175         soc_GMAC0_TXARB_WRR_TH_BCM53400_A0r_fields,
  16176         SOC_RESET_VAL_DEC(0x0a0a0a0a, 0x00000000)
  16177         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16178         -1,
  16179         -1,
  16180     },
  16181 #endif /* chips */
  16182 
  16183 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16184     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16185     defined(BCM_56450_B1)
  16186     { /* SOC_REG_INT_GMAC0_TXQCONTROLr */
  16187         soc_block_list[61],
  16188         soc_iprocreg,
  16189         1,
  16190         0,
  16191         0x1802218c,
  16192         0,
  16193         0,
  16194         1,
  16195         soc_GMAC0_TXQCONTROLr_fields,
  16196         SOC_RESET_VAL_DEC(0x00000271, 0x00000000)
  16197         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  16198         -1,
  16199         -1,
  16200     },
  16201 #endif /* chips */
  16202 
  16203 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16204     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16205     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16206     defined(BCM_56260_B0)
  16207     { /* SOC_REG_INT_GMAC0_TXQCONTROL_BCM53400_A0r */
  16208         soc_block_list[61],
  16209         soc_iprocreg,
  16210         1,
  16211         0,
  16212         0x1804218c,
  16213         0,
  16214         0,
  16215         1,
  16216         soc_GMAC0_TXQCONTROL_BCM53400_A0r_fields,
  16217         SOC_RESET_VAL_DEC(0x00000271, 0x00000000)
  16218         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  16219         -1,
  16220         -1,
  16221     },
  16222 #endif /* chips */
  16223 
  16224 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16225     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16226     defined(BCM_56450_B1)
  16227     { /* SOC_REG_INT_GMAC0_TXQOSQ0OCTET_HIr */
  16228         soc_block_list[61],
  16229         soc_iprocreg,
  16230         1,
  16231         0,
  16232         0x18022384,
  16233         0,
  16234         0,
  16235         1,
  16236         soc_GMAC0_TXQOSQ0OCTET_HIr_fields,
  16237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16238         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16239         -1,
  16240         -1,
  16241     },
  16242 #endif /* chips */
  16243 
  16244 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16245     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16246     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16247     defined(BCM_56260_B0)
  16248     { /* SOC_REG_INT_GMAC0_TXQOSQ0OCTET_HI_BCM53400_A0r */
  16249         soc_block_list[61],
  16250         soc_iprocreg,
  16251         1,
  16252         0,
  16253         0x18042384,
  16254         0,
  16255         0,
  16256         1,
  16257         soc_GMAC0_TXQOSQ0OCTET_HI_BCM53400_A0r_fields,
  16258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16259         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16260         -1,
  16261         -1,
  16262     },
  16263 #endif /* chips */
  16264 
  16265 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16266     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16267     defined(BCM_56450_B1)
  16268     { /* SOC_REG_INT_GMAC0_TXQOSQ0OCTET_LOr */
  16269         soc_block_list[61],
  16270         soc_iprocreg,
  16271         1,
  16272         0,
  16273         0x18022380,
  16274         0,
  16275         0,
  16276         1,
  16277         soc_GMAC0_TXQOSQ0OCTET_LOr_fields,
  16278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16279         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16280         -1,
  16281         -1,
  16282     },
  16283 #endif /* chips */
  16284 
  16285 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16286     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16287     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16288     defined(BCM_56260_B0)
  16289     { /* SOC_REG_INT_GMAC0_TXQOSQ0OCTET_LO_BCM53400_A0r */
  16290         soc_block_list[61],
  16291         soc_iprocreg,
  16292         1,
  16293         0,
  16294         0x18042380,
  16295         0,
  16296         0,
  16297         1,
  16298         soc_GMAC0_TXQOSQ0OCTET_LO_BCM53400_A0r_fields,
  16299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16300         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16301         -1,
  16302         -1,
  16303     },
  16304 #endif /* chips */
  16305 
  16306 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16307     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16308     defined(BCM_56450_B1)
  16309     { /* SOC_REG_INT_GMAC0_TXQOSQ0PKTr */
  16310         soc_block_list[61],
  16311         soc_iprocreg,
  16312         1,
  16313         0,
  16314         0x1802237c,
  16315         0,
  16316         0,
  16317         1,
  16318         soc_GMAC0_TXQOSQ0PKTr_fields,
  16319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16320         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16321         -1,
  16322         -1,
  16323     },
  16324 #endif /* chips */
  16325 
  16326 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16327     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16328     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16329     defined(BCM_56260_B0)
  16330     { /* SOC_REG_INT_GMAC0_TXQOSQ0PKT_BCM53400_A0r */
  16331         soc_block_list[61],
  16332         soc_iprocreg,
  16333         1,
  16334         0,
  16335         0x1804237c,
  16336         0,
  16337         0,
  16338         1,
  16339         soc_GMAC0_TXQOSQ0PKT_BCM53400_A0r_fields,
  16340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16341         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16342         -1,
  16343         -1,
  16344     },
  16345 #endif /* chips */
  16346 
  16347 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16348     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16349     defined(BCM_56450_B1)
  16350     { /* SOC_REG_INT_GMAC0_TXQOSQ1OCTET_HIr */
  16351         soc_block_list[61],
  16352         soc_iprocreg,
  16353         1,
  16354         0,
  16355         0x18022390,
  16356         0,
  16357         0,
  16358         1,
  16359         soc_GMAC0_TXQOSQ1OCTET_HIr_fields,
  16360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16361         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16362         -1,
  16363         -1,
  16364     },
  16365 #endif /* chips */
  16366 
  16367 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16368     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16369     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16370     defined(BCM_56260_B0)
  16371     { /* SOC_REG_INT_GMAC0_TXQOSQ1OCTET_HI_BCM53400_A0r */
  16372         soc_block_list[61],
  16373         soc_iprocreg,
  16374         1,
  16375         0,
  16376         0x18042390,
  16377         0,
  16378         0,
  16379         1,
  16380         soc_GMAC0_TXQOSQ1OCTET_HI_BCM53400_A0r_fields,
  16381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16383         -1,
  16384         -1,
  16385     },
  16386 #endif /* chips */
  16387 
  16388 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16389     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16390     defined(BCM_56450_B1)
  16391     { /* SOC_REG_INT_GMAC0_TXQOSQ1OCTET_LOr */
  16392         soc_block_list[61],
  16393         soc_iprocreg,
  16394         1,
  16395         0,
  16396         0x1802238c,
  16397         0,
  16398         0,
  16399         1,
  16400         soc_GMAC0_TXQOSQ1OCTET_LOr_fields,
  16401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16402         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16403         -1,
  16404         -1,
  16405     },
  16406 #endif /* chips */
  16407 
  16408 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16409     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16410     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16411     defined(BCM_56260_B0)
  16412     { /* SOC_REG_INT_GMAC0_TXQOSQ1OCTET_LO_BCM53400_A0r */
  16413         soc_block_list[61],
  16414         soc_iprocreg,
  16415         1,
  16416         0,
  16417         0x1804238c,
  16418         0,
  16419         0,
  16420         1,
  16421         soc_GMAC0_TXQOSQ1OCTET_LO_BCM53400_A0r_fields,
  16422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16423         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16424         -1,
  16425         -1,
  16426     },
  16427 #endif /* chips */
  16428 
  16429 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16430     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16431     defined(BCM_56450_B1)
  16432     { /* SOC_REG_INT_GMAC0_TXQOSQ1PKTr */
  16433         soc_block_list[61],
  16434         soc_iprocreg,
  16435         1,
  16436         0,
  16437         0x18022388,
  16438         0,
  16439         0,
  16440         1,
  16441         soc_GMAC0_TXQOSQ1PKTr_fields,
  16442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16444         -1,
  16445         -1,
  16446     },
  16447 #endif /* chips */
  16448 
  16449 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16450     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16451     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16452     defined(BCM_56260_B0)
  16453     { /* SOC_REG_INT_GMAC0_TXQOSQ1PKT_BCM53400_A0r */
  16454         soc_block_list[61],
  16455         soc_iprocreg,
  16456         1,
  16457         0,
  16458         0x18042388,
  16459         0,
  16460         0,
  16461         1,
  16462         soc_GMAC0_TXQOSQ1PKT_BCM53400_A0r_fields,
  16463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16464         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16465         -1,
  16466         -1,
  16467     },
  16468 #endif /* chips */
  16469 
  16470 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16471     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16472     defined(BCM_56450_B1)
  16473     { /* SOC_REG_INT_GMAC0_TXQOSQ2OCTET_HIr */
  16474         soc_block_list[61],
  16475         soc_iprocreg,
  16476         1,
  16477         0,
  16478         0x1802239c,
  16479         0,
  16480         0,
  16481         1,
  16482         soc_GMAC0_TXQOSQ2OCTET_HIr_fields,
  16483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16484         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16485         -1,
  16486         -1,
  16487     },
  16488 #endif /* chips */
  16489 
  16490 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16491     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16492     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16493     defined(BCM_56260_B0)
  16494     { /* SOC_REG_INT_GMAC0_TXQOSQ2OCTET_HI_BCM53400_A0r */
  16495         soc_block_list[61],
  16496         soc_iprocreg,
  16497         1,
  16498         0,
  16499         0x1804239c,
  16500         0,
  16501         0,
  16502         1,
  16503         soc_GMAC0_TXQOSQ2OCTET_HI_BCM53400_A0r_fields,
  16504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16505         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16506         -1,
  16507         -1,
  16508     },
  16509 #endif /* chips */
  16510 
  16511 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16512     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16513     defined(BCM_56450_B1)
  16514     { /* SOC_REG_INT_GMAC0_TXQOSQ2OCTET_LOr */
  16515         soc_block_list[61],
  16516         soc_iprocreg,
  16517         1,
  16518         0,
  16519         0x18022398,
  16520         0,
  16521         0,
  16522         1,
  16523         soc_GMAC0_TXQOSQ2OCTET_LOr_fields,
  16524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16526         -1,
  16527         -1,
  16528     },
  16529 #endif /* chips */
  16530 
  16531 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16532     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16533     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16534     defined(BCM_56260_B0)
  16535     { /* SOC_REG_INT_GMAC0_TXQOSQ2OCTET_LO_BCM53400_A0r */
  16536         soc_block_list[61],
  16537         soc_iprocreg,
  16538         1,
  16539         0,
  16540         0x18042398,
  16541         0,
  16542         0,
  16543         1,
  16544         soc_GMAC0_TXQOSQ2OCTET_LO_BCM53400_A0r_fields,
  16545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16546         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16547         -1,
  16548         -1,
  16549     },
  16550 #endif /* chips */
  16551 
  16552 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16553     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16554     defined(BCM_56450_B1)
  16555     { /* SOC_REG_INT_GMAC0_TXQOSQ2PKTr */
  16556         soc_block_list[61],
  16557         soc_iprocreg,
  16558         1,
  16559         0,
  16560         0x18022394,
  16561         0,
  16562         0,
  16563         1,
  16564         soc_GMAC0_TXQOSQ2PKTr_fields,
  16565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16566         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16567         -1,
  16568         -1,
  16569     },
  16570 #endif /* chips */
  16571 
  16572 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16573     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16574     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16575     defined(BCM_56260_B0)
  16576     { /* SOC_REG_INT_GMAC0_TXQOSQ2PKT_BCM53400_A0r */
  16577         soc_block_list[61],
  16578         soc_iprocreg,
  16579         1,
  16580         0,
  16581         0x18042394,
  16582         0,
  16583         0,
  16584         1,
  16585         soc_GMAC0_TXQOSQ2PKT_BCM53400_A0r_fields,
  16586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16587         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16588         -1,
  16589         -1,
  16590     },
  16591 #endif /* chips */
  16592 
  16593 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16594     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16595     defined(BCM_56450_B1)
  16596     { /* SOC_REG_INT_GMAC0_TXQOSQ3OCTET_HIr */
  16597         soc_block_list[61],
  16598         soc_iprocreg,
  16599         1,
  16600         0,
  16601         0x180223a8,
  16602         0,
  16603         0,
  16604         1,
  16605         soc_GMAC0_TXQOSQ3OCTET_HIr_fields,
  16606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16608         -1,
  16609         -1,
  16610     },
  16611 #endif /* chips */
  16612 
  16613 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16614     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16615     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16616     defined(BCM_56260_B0)
  16617     { /* SOC_REG_INT_GMAC0_TXQOSQ3OCTET_HI_BCM53400_A0r */
  16618         soc_block_list[61],
  16619         soc_iprocreg,
  16620         1,
  16621         0,
  16622         0x180423a8,
  16623         0,
  16624         0,
  16625         1,
  16626         soc_GMAC0_TXQOSQ3OCTET_HI_BCM53400_A0r_fields,
  16627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16628         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16629         -1,
  16630         -1,
  16631     },
  16632 #endif /* chips */
  16633 
  16634 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16635     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16636     defined(BCM_56450_B1)
  16637     { /* SOC_REG_INT_GMAC0_TXQOSQ3OCTET_LOr */
  16638         soc_block_list[61],
  16639         soc_iprocreg,
  16640         1,
  16641         0,
  16642         0x180223a4,
  16643         0,
  16644         0,
  16645         1,
  16646         soc_GMAC0_TXQOSQ3OCTET_LOr_fields,
  16647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16649         -1,
  16650         -1,
  16651     },
  16652 #endif /* chips */
  16653 
  16654 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16655     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16656     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16657     defined(BCM_56260_B0)
  16658     { /* SOC_REG_INT_GMAC0_TXQOSQ3OCTET_LO_BCM53400_A0r */
  16659         soc_block_list[61],
  16660         soc_iprocreg,
  16661         1,
  16662         0,
  16663         0x180423a4,
  16664         0,
  16665         0,
  16666         1,
  16667         soc_GMAC0_TXQOSQ3OCTET_LO_BCM53400_A0r_fields,
  16668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16670         -1,
  16671         -1,
  16672     },
  16673 #endif /* chips */
  16674 
  16675 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16676     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16677     defined(BCM_56450_B1)
  16678     { /* SOC_REG_INT_GMAC0_TXQOSQ3PKTr */
  16679         soc_block_list[61],
  16680         soc_iprocreg,
  16681         1,
  16682         0,
  16683         0x180223a0,
  16684         0,
  16685         0,
  16686         1,
  16687         soc_GMAC0_TXQOSQ3PKTr_fields,
  16688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16690         -1,
  16691         -1,
  16692     },
  16693 #endif /* chips */
  16694 
  16695 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16696     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16697     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16698     defined(BCM_56260_B0)
  16699     { /* SOC_REG_INT_GMAC0_TXQOSQ3PKT_BCM53400_A0r */
  16700         soc_block_list[61],
  16701         soc_iprocreg,
  16702         1,
  16703         0,
  16704         0x180423a0,
  16705         0,
  16706         0,
  16707         1,
  16708         soc_GMAC0_TXQOSQ3PKT_BCM53400_A0r_fields,
  16709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16710         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16711         -1,
  16712         -1,
  16713     },
  16714 #endif /* chips */
  16715 
  16716 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16717     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16718     defined(BCM_56450_B1)
  16719     { /* SOC_REG_INT_GMAC0_TXQRXQMEMORYCONTROLr */
  16720         soc_block_list[61],
  16721         soc_iprocreg,
  16722         1,
  16723         0,
  16724         0x180221a0,
  16725         0,
  16726         0,
  16727         6,
  16728         soc_GMAC0_TXQRXQMEMORYCONTROLr_fields,
  16729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16730         SOC_RESET_MASK_DEC(0x00ff00ff, 0x00000000)
  16731         -1,
  16732         -1,
  16733     },
  16734 #endif /* chips */
  16735 
  16736 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16737     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16738     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16739     defined(BCM_56260_B0)
  16740     { /* SOC_REG_INT_GMAC0_TXQRXQMEMORYCONTROL_BCM53400_A0r */
  16741         soc_block_list[61],
  16742         soc_iprocreg,
  16743         1,
  16744         0,
  16745         0x180421a0,
  16746         0,
  16747         0,
  16748         6,
  16749         soc_GMAC0_TXQRXQMEMORYCONTROL_BCM53400_A0r_fields,
  16750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16751         SOC_RESET_MASK_DEC(0x00ff00ff, 0x00000000)
  16752         -1,
  16753         -1,
  16754     },
  16755 #endif /* chips */
  16756 
  16757 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16758     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16759     defined(BCM_56450_B1)
  16760     { /* SOC_REG_INT_GMAC0_TXUNICASTPKTr */
  16761         soc_block_list[61],
  16762         soc_iprocreg,
  16763         1,
  16764         0,
  16765         0x18022378,
  16766         0,
  16767         0,
  16768         1,
  16769         soc_GMAC0_TXUNICASTPKTr_fields,
  16770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16772         -1,
  16773         -1,
  16774     },
  16775 #endif /* chips */
  16776 
  16777 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16778     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16779     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16780     defined(BCM_56260_B0)
  16781     { /* SOC_REG_INT_GMAC0_TXUNICASTPKT_BCM53400_A0r */
  16782         soc_block_list[61],
  16783         soc_iprocreg,
  16784         1,
  16785         0,
  16786         0x18042378,
  16787         0,
  16788         0,
  16789         1,
  16790         soc_GMAC0_TXUNICASTPKT_BCM53400_A0r_fields,
  16791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16792         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16793         -1,
  16794         -1,
  16795     },
  16796 #endif /* chips */
  16797 
  16798 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16799     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16800     defined(BCM_56450_B1)
  16801     { /* SOC_REG_INT_GMAC0_TX_64r */
  16802         soc_block_list[61],
  16803         soc_iprocreg,
  16804         1,
  16805         0,
  16806         0x18022320,
  16807         0,
  16808         0,
  16809         1,
  16810         soc_GMAC0_TX_64r_fields,
  16811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16812         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16813         -1,
  16814         -1,
  16815     },
  16816 #endif /* chips */
  16817 
  16818 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16819     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16820     defined(BCM_56450_B1)
  16821     { /* SOC_REG_INT_GMAC0_TX_1024_1522r */
  16822         soc_block_list[61],
  16823         soc_iprocreg,
  16824         1,
  16825         0,
  16826         0x18022334,
  16827         0,
  16828         0,
  16829         1,
  16830         soc_GMAC0_TX_1024_1522r_fields,
  16831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16832         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16833         -1,
  16834         -1,
  16835     },
  16836 #endif /* chips */
  16837 
  16838 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16839     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16840     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16841     defined(BCM_56260_B0)
  16842     { /* SOC_REG_INT_GMAC0_TX_1024_1522_BCM53400_A0r */
  16843         soc_block_list[61],
  16844         soc_iprocreg,
  16845         1,
  16846         0,
  16847         0x18042334,
  16848         0,
  16849         0,
  16850         1,
  16851         soc_GMAC0_TX_1024_1522_BCM53400_A0r_fields,
  16852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16854         -1,
  16855         -1,
  16856     },
  16857 #endif /* chips */
  16858 
  16859 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16860     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16861     defined(BCM_56450_B1)
  16862     { /* SOC_REG_INT_GMAC0_TX_128_255r */
  16863         soc_block_list[61],
  16864         soc_iprocreg,
  16865         1,
  16866         0,
  16867         0x18022328,
  16868         0,
  16869         0,
  16870         1,
  16871         soc_GMAC0_TX_128_255r_fields,
  16872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16873         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16874         -1,
  16875         -1,
  16876     },
  16877 #endif /* chips */
  16878 
  16879 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16880     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16881     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16882     defined(BCM_56260_B0)
  16883     { /* SOC_REG_INT_GMAC0_TX_128_255_BCM53400_A0r */
  16884         soc_block_list[61],
  16885         soc_iprocreg,
  16886         1,
  16887         0,
  16888         0x18042328,
  16889         0,
  16890         0,
  16891         1,
  16892         soc_GMAC0_TX_128_255_BCM53400_A0r_fields,
  16893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16894         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16895         -1,
  16896         -1,
  16897     },
  16898 #endif /* chips */
  16899 
  16900 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16901     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16902     defined(BCM_56450_B1)
  16903     { /* SOC_REG_INT_GMAC0_TX_1523_2047r */
  16904         soc_block_list[61],
  16905         soc_iprocreg,
  16906         1,
  16907         0,
  16908         0x18022338,
  16909         0,
  16910         0,
  16911         1,
  16912         soc_GMAC0_TX_1523_2047r_fields,
  16913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16915         -1,
  16916         -1,
  16917     },
  16918 #endif /* chips */
  16919 
  16920 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16921     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16922     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16923     defined(BCM_56260_B0)
  16924     { /* SOC_REG_INT_GMAC0_TX_1523_2047_BCM53400_A0r */
  16925         soc_block_list[61],
  16926         soc_iprocreg,
  16927         1,
  16928         0,
  16929         0x18042338,
  16930         0,
  16931         0,
  16932         1,
  16933         soc_GMAC0_TX_1523_2047_BCM53400_A0r_fields,
  16934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16935         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16936         -1,
  16937         -1,
  16938     },
  16939 #endif /* chips */
  16940 
  16941 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16942     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16943     defined(BCM_56450_B1)
  16944     { /* SOC_REG_INT_GMAC0_TX_1_COLr */
  16945         soc_block_list[61],
  16946         soc_iprocreg,
  16947         1,
  16948         0,
  16949         0x1802235c,
  16950         0,
  16951         0,
  16952         1,
  16953         soc_GMAC0_TX_1_COLr_fields,
  16954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16956         -1,
  16957         -1,
  16958     },
  16959 #endif /* chips */
  16960 
  16961 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16962     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16963     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16964     defined(BCM_56260_B0)
  16965     { /* SOC_REG_INT_GMAC0_TX_1_COL_BCM53400_A0r */
  16966         soc_block_list[61],
  16967         soc_iprocreg,
  16968         1,
  16969         0,
  16970         0x1804235c,
  16971         0,
  16972         0,
  16973         1,
  16974         soc_GMAC0_TX_1_COL_BCM53400_A0r_fields,
  16975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16976         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16977         -1,
  16978         -1,
  16979     },
  16980 #endif /* chips */
  16981 
  16982 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16983     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16984     defined(BCM_56450_B1)
  16985     { /* SOC_REG_INT_GMAC0_TX_2048_4095r */
  16986         soc_block_list[61],
  16987         soc_iprocreg,
  16988         1,
  16989         0,
  16990         0x1802233c,
  16991         0,
  16992         0,
  16993         1,
  16994         soc_GMAC0_TX_2048_4095r_fields,
  16995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16997         -1,
  16998         -1,
  16999     },
  17000 #endif /* chips */
  17001 
  17002 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17003     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17004     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17005     defined(BCM_56260_B0)
  17006     { /* SOC_REG_INT_GMAC0_TX_2048_4095_BCM53400_A0r */
  17007         soc_block_list[61],
  17008         soc_iprocreg,
  17009         1,
  17010         0,
  17011         0x1804233c,
  17012         0,
  17013         0,
  17014         1,
  17015         soc_GMAC0_TX_2048_4095_BCM53400_A0r_fields,
  17016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17018         -1,
  17019         -1,
  17020     },
  17021 #endif /* chips */
  17022 
  17023 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17024     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17025     defined(BCM_56450_B1)
  17026     { /* SOC_REG_INT_GMAC0_TX_256_511r */
  17027         soc_block_list[61],
  17028         soc_iprocreg,
  17029         1,
  17030         0,
  17031         0x1802232c,
  17032         0,
  17033         0,
  17034         1,
  17035         soc_GMAC0_TX_256_511r_fields,
  17036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17038         -1,
  17039         -1,
  17040     },
  17041 #endif /* chips */
  17042 
  17043 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17044     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17045     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17046     defined(BCM_56260_B0)
  17047     { /* SOC_REG_INT_GMAC0_TX_256_511_BCM53400_A0r */
  17048         soc_block_list[61],
  17049         soc_iprocreg,
  17050         1,
  17051         0,
  17052         0x1804232c,
  17053         0,
  17054         0,
  17055         1,
  17056         soc_GMAC0_TX_256_511_BCM53400_A0r_fields,
  17057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17058         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17059         -1,
  17060         -1,
  17061     },
  17062 #endif /* chips */
  17063 
  17064 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17065     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17066     defined(BCM_56450_B1)
  17067     { /* SOC_REG_INT_GMAC0_TX_4096_8191r */
  17068         soc_block_list[61],
  17069         soc_iprocreg,
  17070         1,
  17071         0,
  17072         0x18022340,
  17073         0,
  17074         0,
  17075         1,
  17076         soc_GMAC0_TX_4096_8191r_fields,
  17077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17078         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17079         -1,
  17080         -1,
  17081     },
  17082 #endif /* chips */
  17083 
  17084 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17085     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17086     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17087     defined(BCM_56260_B0)
  17088     { /* SOC_REG_INT_GMAC0_TX_4096_8191_BCM53400_A0r */
  17089         soc_block_list[61],
  17090         soc_iprocreg,
  17091         1,
  17092         0,
  17093         0x18042340,
  17094         0,
  17095         0,
  17096         1,
  17097         soc_GMAC0_TX_4096_8191_BCM53400_A0r_fields,
  17098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17099         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17100         -1,
  17101         -1,
  17102     },
  17103 #endif /* chips */
  17104 
  17105 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17106     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17107     defined(BCM_56450_B1)
  17108     { /* SOC_REG_INT_GMAC0_TX_512_1023r */
  17109         soc_block_list[61],
  17110         soc_iprocreg,
  17111         1,
  17112         0,
  17113         0x18022330,
  17114         0,
  17115         0,
  17116         1,
  17117         soc_GMAC0_TX_512_1023r_fields,
  17118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17120         -1,
  17121         -1,
  17122     },
  17123 #endif /* chips */
  17124 
  17125 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17126     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17127     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17128     defined(BCM_56260_B0)
  17129     { /* SOC_REG_INT_GMAC0_TX_512_1023_BCM53400_A0r */
  17130         soc_block_list[61],
  17131         soc_iprocreg,
  17132         1,
  17133         0,
  17134         0x18042330,
  17135         0,
  17136         0,
  17137         1,
  17138         soc_GMAC0_TX_512_1023_BCM53400_A0r_fields,
  17139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17140         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17141         -1,
  17142         -1,
  17143     },
  17144 #endif /* chips */
  17145 
  17146 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17147     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17148     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17149     defined(BCM_56260_B0)
  17150     { /* SOC_REG_INT_GMAC0_TX_64_BCM53400_A0r */
  17151         soc_block_list[61],
  17152         soc_iprocreg,
  17153         1,
  17154         0,
  17155         0x18042320,
  17156         0,
  17157         0,
  17158         1,
  17159         soc_GMAC0_TX_64_BCM53400_A0r_fields,
  17160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17161         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17162         -1,
  17163         -1,
  17164     },
  17165 #endif /* chips */
  17166 
  17167 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17168     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17169     defined(BCM_56450_B1)
  17170     { /* SOC_REG_INT_GMAC0_TX_65_127r */
  17171         soc_block_list[61],
  17172         soc_iprocreg,
  17173         1,
  17174         0,
  17175         0x18022324,
  17176         0,
  17177         0,
  17178         1,
  17179         soc_GMAC0_TX_65_127r_fields,
  17180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17181         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17182         -1,
  17183         -1,
  17184     },
  17185 #endif /* chips */
  17186 
  17187 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17188     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17189     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17190     defined(BCM_56260_B0)
  17191     { /* SOC_REG_INT_GMAC0_TX_65_127_BCM53400_A0r */
  17192         soc_block_list[61],
  17193         soc_iprocreg,
  17194         1,
  17195         0,
  17196         0x18042324,
  17197         0,
  17198         0,
  17199         1,
  17200         soc_GMAC0_TX_65_127_BCM53400_A0r_fields,
  17201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17202         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17203         -1,
  17204         -1,
  17205     },
  17206 #endif /* chips */
  17207 
  17208 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17209     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17210     defined(BCM_56450_B1)
  17211     { /* SOC_REG_INT_GMAC0_TX_8192_MAXr */
  17212         soc_block_list[61],
  17213         soc_iprocreg,
  17214         1,
  17215         0,
  17216         0x18022344,
  17217         0,
  17218         0,
  17219         1,
  17220         soc_GMAC0_TX_8192_MAXr_fields,
  17221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17222         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17223         -1,
  17224         -1,
  17225     },
  17226 #endif /* chips */
  17227 
  17228 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17229     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17230     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17231     defined(BCM_56260_B0)
  17232     { /* SOC_REG_INT_GMAC0_TX_8192_MAX_BCM53400_A0r */
  17233         soc_block_list[61],
  17234         soc_iprocreg,
  17235         1,
  17236         0,
  17237         0x18042344,
  17238         0,
  17239         0,
  17240         1,
  17241         soc_GMAC0_TX_8192_MAX_BCM53400_A0r_fields,
  17242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17243         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17244         -1,
  17245         -1,
  17246     },
  17247 #endif /* chips */
  17248 
  17249 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17250     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17251     defined(BCM_56450_B1)
  17252     { /* SOC_REG_INT_GMAC0_TX_ALL_OCTETS_HIr */
  17253         soc_block_list[61],
  17254         soc_iprocreg,
  17255         1,
  17256         0,
  17257         0x18022310,
  17258         0,
  17259         0,
  17260         1,
  17261         soc_GMAC0_TX_ALL_OCTETS_HIr_fields,
  17262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17264         -1,
  17265         -1,
  17266     },
  17267 #endif /* chips */
  17268 
  17269 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17270     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17271     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17272     defined(BCM_56260_B0)
  17273     { /* SOC_REG_INT_GMAC0_TX_ALL_OCTETS_HI_BCM53400_A0r */
  17274         soc_block_list[61],
  17275         soc_iprocreg,
  17276         1,
  17277         0,
  17278         0x18042310,
  17279         0,
  17280         0,
  17281         1,
  17282         soc_GMAC0_TX_ALL_OCTETS_HI_BCM53400_A0r_fields,
  17283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17284         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17285         -1,
  17286         -1,
  17287     },
  17288 #endif /* chips */
  17289 
  17290 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17291     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17292     defined(BCM_56450_B1)
  17293     { /* SOC_REG_INT_GMAC0_TX_ALL_OCTETS_LOr */
  17294         soc_block_list[61],
  17295         soc_iprocreg,
  17296         1,
  17297         0,
  17298         0x1802230c,
  17299         0,
  17300         0,
  17301         1,
  17302         soc_GMAC0_TX_ALL_OCTETS_LOr_fields,
  17303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17304         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17305         -1,
  17306         -1,
  17307     },
  17308 #endif /* chips */
  17309 
  17310 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17311     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17312     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17313     defined(BCM_56260_B0)
  17314     { /* SOC_REG_INT_GMAC0_TX_ALL_OCTETS_LO_BCM53400_A0r */
  17315         soc_block_list[61],
  17316         soc_iprocreg,
  17317         1,
  17318         0,
  17319         0x1804230c,
  17320         0,
  17321         0,
  17322         1,
  17323         soc_GMAC0_TX_ALL_OCTETS_LO_BCM53400_A0r_fields,
  17324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17325         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17326         -1,
  17327         -1,
  17328     },
  17329 #endif /* chips */
  17330 
  17331 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17332     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17333     defined(BCM_56450_B1)
  17334     { /* SOC_REG_INT_GMAC0_TX_ALL_PKTSr */
  17335         soc_block_list[61],
  17336         soc_iprocreg,
  17337         1,
  17338         0,
  17339         0x18022314,
  17340         0,
  17341         0,
  17342         1,
  17343         soc_GMAC0_TX_ALL_PKTSr_fields,
  17344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17346         -1,
  17347         -1,
  17348     },
  17349 #endif /* chips */
  17350 
  17351 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17352     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17353     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17354     defined(BCM_56260_B0)
  17355     { /* SOC_REG_INT_GMAC0_TX_ALL_PKTS_BCM53400_A0r */
  17356         soc_block_list[61],
  17357         soc_iprocreg,
  17358         1,
  17359         0,
  17360         0x18042314,
  17361         0,
  17362         0,
  17363         1,
  17364         soc_GMAC0_TX_ALL_PKTS_BCM53400_A0r_fields,
  17365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17366         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17367         -1,
  17368         -1,
  17369     },
  17370 #endif /* chips */
  17371 
  17372 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17373     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17374     defined(BCM_56450_B1)
  17375     { /* SOC_REG_INT_GMAC0_TX_BRDCASTr */
  17376         soc_block_list[61],
  17377         soc_iprocreg,
  17378         1,
  17379         0,
  17380         0x18022318,
  17381         0,
  17382         0,
  17383         1,
  17384         soc_GMAC0_TX_BRDCASTr_fields,
  17385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17386         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17387         -1,
  17388         -1,
  17389     },
  17390 #endif /* chips */
  17391 
  17392 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17393     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17394     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17395     defined(BCM_56260_B0)
  17396     { /* SOC_REG_INT_GMAC0_TX_BRDCAST_BCM53400_A0r */
  17397         soc_block_list[61],
  17398         soc_iprocreg,
  17399         1,
  17400         0,
  17401         0x18042318,
  17402         0,
  17403         0,
  17404         1,
  17405         soc_GMAC0_TX_BRDCAST_BCM53400_A0r_fields,
  17406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17407         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17408         -1,
  17409         -1,
  17410     },
  17411 #endif /* chips */
  17412 
  17413 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17414     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17415     defined(BCM_56450_B1)
  17416     { /* SOC_REG_INT_GMAC0_TX_COLr */
  17417         soc_block_list[61],
  17418         soc_iprocreg,
  17419         1,
  17420         0,
  17421         0x18022358,
  17422         0,
  17423         0,
  17424         1,
  17425         soc_GMAC0_TX_COLr_fields,
  17426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17428         -1,
  17429         -1,
  17430     },
  17431 #endif /* chips */
  17432 
  17433 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17434     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17435     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17436     defined(BCM_56260_B0)
  17437     { /* SOC_REG_INT_GMAC0_TX_COL_BCM53400_A0r */
  17438         soc_block_list[61],
  17439         soc_iprocreg,
  17440         1,
  17441         0,
  17442         0x18042358,
  17443         0,
  17444         0,
  17445         1,
  17446         soc_GMAC0_TX_COL_BCM53400_A0r_fields,
  17447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17448         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17449         -1,
  17450         -1,
  17451     },
  17452 #endif /* chips */
  17453 
  17454 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17455     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17456     defined(BCM_56450_B1)
  17457     { /* SOC_REG_INT_GMAC0_TX_CRSr */
  17458         soc_block_list[61],
  17459         soc_iprocreg,
  17460         1,
  17461         0,
  17462         0x18022370,
  17463         0,
  17464         0,
  17465         1,
  17466         soc_GMAC0_TX_CRSr_fields,
  17467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17469         -1,
  17470         -1,
  17471     },
  17472 #endif /* chips */
  17473 
  17474 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17475     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17476     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17477     defined(BCM_56260_B0)
  17478     { /* SOC_REG_INT_GMAC0_TX_CRS_BCM53400_A0r */
  17479         soc_block_list[61],
  17480         soc_iprocreg,
  17481         1,
  17482         0,
  17483         0x18042370,
  17484         0,
  17485         0,
  17486         1,
  17487         soc_GMAC0_TX_CRS_BCM53400_A0r_fields,
  17488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17490         -1,
  17491         -1,
  17492     },
  17493 #endif /* chips */
  17494 
  17495 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17496     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17497     defined(BCM_56450_B1)
  17498     { /* SOC_REG_INT_GMAC0_TX_DEFr */
  17499         soc_block_list[61],
  17500         soc_iprocreg,
  17501         1,
  17502         0,
  17503         0x1802236c,
  17504         0,
  17505         0,
  17506         1,
  17507         soc_GMAC0_TX_DEFr_fields,
  17508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17509         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17510         -1,
  17511         -1,
  17512     },
  17513 #endif /* chips */
  17514 
  17515 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17516     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17517     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17518     defined(BCM_56260_B0)
  17519     { /* SOC_REG_INT_GMAC0_TX_DEF_BCM53400_A0r */
  17520         soc_block_list[61],
  17521         soc_iprocreg,
  17522         1,
  17523         0,
  17524         0x1804236c,
  17525         0,
  17526         0,
  17527         1,
  17528         soc_GMAC0_TX_DEF_BCM53400_A0r_fields,
  17529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17530         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17531         -1,
  17532         -1,
  17533     },
  17534 #endif /* chips */
  17535 
  17536 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17537     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17538     defined(BCM_56450_B1)
  17539     { /* SOC_REG_INT_GMAC0_TX_EX_COLr */
  17540         soc_block_list[61],
  17541         soc_iprocreg,
  17542         1,
  17543         0,
  17544         0x18022364,
  17545         0,
  17546         0,
  17547         1,
  17548         soc_GMAC0_TX_EX_COLr_fields,
  17549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17550         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17551         -1,
  17552         -1,
  17553     },
  17554 #endif /* chips */
  17555 
  17556 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17557     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17558     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17559     defined(BCM_56260_B0)
  17560     { /* SOC_REG_INT_GMAC0_TX_EX_COL_BCM53400_A0r */
  17561         soc_block_list[61],
  17562         soc_iprocreg,
  17563         1,
  17564         0,
  17565         0x18042364,
  17566         0,
  17567         0,
  17568         1,
  17569         soc_GMAC0_TX_EX_COL_BCM53400_A0r_fields,
  17570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17572         -1,
  17573         -1,
  17574     },
  17575 #endif /* chips */
  17576 
  17577 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17578     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17579     defined(BCM_56450_B1)
  17580     { /* SOC_REG_INT_GMAC0_TX_FRAGr */
  17581         soc_block_list[61],
  17582         soc_iprocreg,
  17583         1,
  17584         0,
  17585         0x18022350,
  17586         0,
  17587         0,
  17588         1,
  17589         soc_GMAC0_TX_FRAGr_fields,
  17590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17591         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17592         -1,
  17593         -1,
  17594     },
  17595 #endif /* chips */
  17596 
  17597 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17598     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17599     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17600     defined(BCM_56260_B0)
  17601     { /* SOC_REG_INT_GMAC0_TX_FRAG_BCM53400_A0r */
  17602         soc_block_list[61],
  17603         soc_iprocreg,
  17604         1,
  17605         0,
  17606         0x18042350,
  17607         0,
  17608         0,
  17609         1,
  17610         soc_GMAC0_TX_FRAG_BCM53400_A0r_fields,
  17611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17612         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17613         -1,
  17614         -1,
  17615     },
  17616 #endif /* chips */
  17617 
  17618 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17619     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17620     defined(BCM_56450_B1)
  17621     { /* SOC_REG_INT_GMAC0_TX_GD_OCTETS_HIr */
  17622         soc_block_list[61],
  17623         soc_iprocreg,
  17624         1,
  17625         0,
  17626         0x18022304,
  17627         0,
  17628         0,
  17629         1,
  17630         soc_GMAC0_TX_GD_OCTETS_HIr_fields,
  17631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17633         -1,
  17634         -1,
  17635     },
  17636 #endif /* chips */
  17637 
  17638 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17639     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17640     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17641     defined(BCM_56260_B0)
  17642     { /* SOC_REG_INT_GMAC0_TX_GD_OCTETS_HI_BCM53400_A0r */
  17643         soc_block_list[61],
  17644         soc_iprocreg,
  17645         1,
  17646         0,
  17647         0x18042304,
  17648         0,
  17649         0,
  17650         1,
  17651         soc_GMAC0_TX_GD_OCTETS_HI_BCM53400_A0r_fields,
  17652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17653         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17654         -1,
  17655         -1,
  17656     },
  17657 #endif /* chips */
  17658 
  17659 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17660     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17661     defined(BCM_56450_B1)
  17662     { /* SOC_REG_INT_GMAC0_TX_GD_OCTETS_LOr */
  17663         soc_block_list[61],
  17664         soc_iprocreg,
  17665         1,
  17666         0,
  17667         0x18022300,
  17668         0,
  17669         0,
  17670         1,
  17671         soc_GMAC0_TX_GD_OCTETS_LOr_fields,
  17672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17673         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17674         -1,
  17675         -1,
  17676     },
  17677 #endif /* chips */
  17678 
  17679 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17680     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17681     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17682     defined(BCM_56260_B0)
  17683     { /* SOC_REG_INT_GMAC0_TX_GD_OCTETS_LO_BCM53400_A0r */
  17684         soc_block_list[61],
  17685         soc_iprocreg,
  17686         1,
  17687         0,
  17688         0x18042300,
  17689         0,
  17690         0,
  17691         1,
  17692         soc_GMAC0_TX_GD_OCTETS_LO_BCM53400_A0r_fields,
  17693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17694         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17695         -1,
  17696         -1,
  17697     },
  17698 #endif /* chips */
  17699 
  17700 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17701     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17702     defined(BCM_56450_B1)
  17703     { /* SOC_REG_INT_GMAC0_TX_GD_PKTSr */
  17704         soc_block_list[61],
  17705         soc_iprocreg,
  17706         1,
  17707         0,
  17708         0x18022308,
  17709         0,
  17710         0,
  17711         1,
  17712         soc_GMAC0_TX_GD_PKTSr_fields,
  17713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17714         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17715         -1,
  17716         -1,
  17717     },
  17718 #endif /* chips */
  17719 
  17720 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17721     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17722     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17723     defined(BCM_56260_B0)
  17724     { /* SOC_REG_INT_GMAC0_TX_GD_PKTS_BCM53400_A0r */
  17725         soc_block_list[61],
  17726         soc_iprocreg,
  17727         1,
  17728         0,
  17729         0x18042308,
  17730         0,
  17731         0,
  17732         1,
  17733         soc_GMAC0_TX_GD_PKTS_BCM53400_A0r_fields,
  17734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17736         -1,
  17737         -1,
  17738     },
  17739 #endif /* chips */
  17740 
  17741 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17742     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17743     defined(BCM_56450_B1)
  17744     { /* SOC_REG_INT_GMAC0_TX_JABr */
  17745         soc_block_list[61],
  17746         soc_iprocreg,
  17747         1,
  17748         0,
  17749         0x18022348,
  17750         0,
  17751         0,
  17752         1,
  17753         soc_GMAC0_TX_JABr_fields,
  17754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17756         -1,
  17757         -1,
  17758     },
  17759 #endif /* chips */
  17760 
  17761 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17762     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17763     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17764     defined(BCM_56260_B0)
  17765     { /* SOC_REG_INT_GMAC0_TX_JAB_BCM53400_A0r */
  17766         soc_block_list[61],
  17767         soc_iprocreg,
  17768         1,
  17769         0,
  17770         0x18042348,
  17771         0,
  17772         0,
  17773         1,
  17774         soc_GMAC0_TX_JAB_BCM53400_A0r_fields,
  17775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17777         -1,
  17778         -1,
  17779     },
  17780 #endif /* chips */
  17781 
  17782 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17783     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17784     defined(BCM_56450_B1)
  17785     { /* SOC_REG_INT_GMAC0_TX_LATEr */
  17786         soc_block_list[61],
  17787         soc_iprocreg,
  17788         1,
  17789         0,
  17790         0x18022368,
  17791         0,
  17792         0,
  17793         1,
  17794         soc_GMAC0_TX_LATEr_fields,
  17795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17797         -1,
  17798         -1,
  17799     },
  17800 #endif /* chips */
  17801 
  17802 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17803     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17804     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17805     defined(BCM_56260_B0)
  17806     { /* SOC_REG_INT_GMAC0_TX_LATE_BCM53400_A0r */
  17807         soc_block_list[61],
  17808         soc_iprocreg,
  17809         1,
  17810         0,
  17811         0x18042368,
  17812         0,
  17813         0,
  17814         1,
  17815         soc_GMAC0_TX_LATE_BCM53400_A0r_fields,
  17816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17817         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17818         -1,
  17819         -1,
  17820     },
  17821 #endif /* chips */
  17822 
  17823 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17824     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17825     defined(BCM_56450_B1)
  17826     { /* SOC_REG_INT_GMAC0_TX_MULTr */
  17827         soc_block_list[61],
  17828         soc_iprocreg,
  17829         1,
  17830         0,
  17831         0x1802231c,
  17832         0,
  17833         0,
  17834         1,
  17835         soc_GMAC0_TX_MULTr_fields,
  17836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17837         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17838         -1,
  17839         -1,
  17840     },
  17841 #endif /* chips */
  17842 
  17843 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17844     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17845     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17846     defined(BCM_56260_B0)
  17847     { /* SOC_REG_INT_GMAC0_TX_MULT_BCM53400_A0r */
  17848         soc_block_list[61],
  17849         soc_iprocreg,
  17850         1,
  17851         0,
  17852         0x1804231c,
  17853         0,
  17854         0,
  17855         1,
  17856         soc_GMAC0_TX_MULT_BCM53400_A0r_fields,
  17857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17859         -1,
  17860         -1,
  17861     },
  17862 #endif /* chips */
  17863 
  17864 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17865     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17866     defined(BCM_56450_B1)
  17867     { /* SOC_REG_INT_GMAC0_TX_M_COLr */
  17868         soc_block_list[61],
  17869         soc_iprocreg,
  17870         1,
  17871         0,
  17872         0x18022360,
  17873         0,
  17874         0,
  17875         1,
  17876         soc_GMAC0_TX_M_COLr_fields,
  17877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17878         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17879         -1,
  17880         -1,
  17881     },
  17882 #endif /* chips */
  17883 
  17884 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17885     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17886     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17887     defined(BCM_56260_B0)
  17888     { /* SOC_REG_INT_GMAC0_TX_M_COL_BCM53400_A0r */
  17889         soc_block_list[61],
  17890         soc_iprocreg,
  17891         1,
  17892         0,
  17893         0x18042360,
  17894         0,
  17895         0,
  17896         1,
  17897         soc_GMAC0_TX_M_COL_BCM53400_A0r_fields,
  17898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17899         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17900         -1,
  17901         -1,
  17902     },
  17903 #endif /* chips */
  17904 
  17905 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17906     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17907     defined(BCM_56450_B1)
  17908     { /* SOC_REG_INT_GMAC0_TX_OVERr */
  17909         soc_block_list[61],
  17910         soc_iprocreg,
  17911         1,
  17912         0,
  17913         0x1802234c,
  17914         0,
  17915         0,
  17916         1,
  17917         soc_GMAC0_TX_OVERr_fields,
  17918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17919         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17920         -1,
  17921         -1,
  17922     },
  17923 #endif /* chips */
  17924 
  17925 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17926     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17927     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17928     defined(BCM_56260_B0)
  17929     { /* SOC_REG_INT_GMAC0_TX_OVER_BCM53400_A0r */
  17930         soc_block_list[61],
  17931         soc_iprocreg,
  17932         1,
  17933         0,
  17934         0x1804234c,
  17935         0,
  17936         0,
  17937         1,
  17938         soc_GMAC0_TX_OVER_BCM53400_A0r_fields,
  17939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17941         -1,
  17942         -1,
  17943     },
  17944 #endif /* chips */
  17945 
  17946 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17947     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17948     defined(BCM_56450_B1)
  17949     { /* SOC_REG_INT_GMAC0_TX_PAUSr */
  17950         soc_block_list[61],
  17951         soc_iprocreg,
  17952         1,
  17953         0,
  17954         0x18022374,
  17955         0,
  17956         0,
  17957         1,
  17958         soc_GMAC0_TX_PAUSr_fields,
  17959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17960         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17961         -1,
  17962         -1,
  17963     },
  17964 #endif /* chips */
  17965 
  17966 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17967     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17968     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17969     defined(BCM_56260_B0)
  17970     { /* SOC_REG_INT_GMAC0_TX_PAUS_BCM53400_A0r */
  17971         soc_block_list[61],
  17972         soc_iprocreg,
  17973         1,
  17974         0,
  17975         0x18042374,
  17976         0,
  17977         0,
  17978         1,
  17979         soc_GMAC0_TX_PAUS_BCM53400_A0r_fields,
  17980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17982         -1,
  17983         -1,
  17984     },
  17985 #endif /* chips */
  17986 
  17987 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17988     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17989     defined(BCM_56450_B1)
  17990     { /* SOC_REG_INT_GMAC0_TX_UNDERRUNr */
  17991         soc_block_list[61],
  17992         soc_iprocreg,
  17993         1,
  17994         0,
  17995         0x18022354,
  17996         0,
  17997         0,
  17998         1,
  17999         soc_GMAC0_TX_UNDERRUNr_fields,
  18000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18002         -1,
  18003         -1,
  18004     },
  18005 #endif /* chips */
  18006 
  18007 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18008     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18009     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18010     defined(BCM_56260_B0)
  18011     { /* SOC_REG_INT_GMAC0_TX_UNDERRUN_BCM53400_A0r */
  18012         soc_block_list[61],
  18013         soc_iprocreg,
  18014         1,
  18015         0,
  18016         0x18042354,
  18017         0,
  18018         0,
  18019         1,
  18020         soc_GMAC0_TX_UNDERRUN_BCM53400_A0r_fields,
  18021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18023         -1,
  18024         -1,
  18025     },
  18026 #endif /* chips */
  18027 
  18028 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  18029     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18030     defined(BCM_56450_B1)
  18031     { /* SOC_REG_INT_GMAC0_XMTADDR_HIGH_0r */
  18032         soc_block_list[61],
  18033         soc_iprocreg,
  18034         1,
  18035         0,
  18036         0x1802220c,
  18037         0,
  18038         0,
  18039         1,
  18040         soc_GMAC0_XMTADDR_HIGH_0r_fields,
  18041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18042         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18043         -1,
  18044         -1,
  18045     },
  18046 #endif /* chips */
  18047 
  18048 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18049     { /* SOC_REG_INT_GMAC0_XMTADDR_HIGH_1r */
  18050         soc_block_list[61],
  18051         soc_iprocreg,
  18052         1,
  18053         0,
  18054         0x1802224c,
  18055         0,
  18056         0,
  18057         1,
  18058         soc_GMAC0_XMTADDR_HIGH_0r_fields,
  18059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18060         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18061         -1,
  18062         -1,
  18063     },
  18064 #endif /* chips */
  18065 
  18066 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18067     { /* SOC_REG_INT_GMAC0_XMTADDR_HIGH_2r */
  18068         soc_block_list[61],
  18069         soc_iprocreg,
  18070         1,
  18071         0,
  18072         0x1802228c,
  18073         0,
  18074         0,
  18075         1,
  18076         soc_GMAC0_XMTADDR_HIGH_0r_fields,
  18077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18078         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18079         -1,
  18080         -1,
  18081     },
  18082 #endif /* chips */
  18083 
  18084 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18085     { /* SOC_REG_INT_GMAC0_XMTADDR_HIGH_3r */
  18086         soc_block_list[61],
  18087         soc_iprocreg,
  18088         1,
  18089         0,
  18090         0x180222cc,
  18091         0,
  18092         0,
  18093         1,
  18094         soc_GMAC0_XMTADDR_HIGH_0r_fields,
  18095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18096         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18097         -1,
  18098         -1,
  18099     },
  18100 #endif /* chips */
  18101 
  18102 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18103     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18104     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18105     defined(BCM_56260_B0)
  18106     { /* SOC_REG_INT_GMAC0_XMTADDR_HIGH_0_BCM53400_A0r */
  18107         soc_block_list[61],
  18108         soc_iprocreg,
  18109         1,
  18110         0,
  18111         0x1804220c,
  18112         0,
  18113         0,
  18114         1,
  18115         soc_GMAC0_XMTADDR_HIGH_0_BCM53400_A0r_fields,
  18116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18117         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18118         -1,
  18119         -1,
  18120     },
  18121 #endif /* chips */
  18122 
  18123 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  18124     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18125     defined(BCM_56450_B1)
  18126     { /* SOC_REG_INT_GMAC0_XMTADDR_LOW_0r */
  18127         soc_block_list[61],
  18128         soc_iprocreg,
  18129         1,
  18130         0,
  18131         0x18022208,
  18132         0,
  18133         0,
  18134         2,
  18135         soc_GMAC0_XMTADDR_LOW_0r_fields,
  18136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18138         -1,
  18139         -1,
  18140     },
  18141 #endif /* chips */
  18142 
  18143 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18144     { /* SOC_REG_INT_GMAC0_XMTADDR_LOW_1r */
  18145         soc_block_list[61],
  18146         soc_iprocreg,
  18147         1,
  18148         0,
  18149         0x18022248,
  18150         0,
  18151         0,
  18152         2,
  18153         soc_GMAC0_XMTADDR_LOW_0r_fields,
  18154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18156         -1,
  18157         -1,
  18158     },
  18159 #endif /* chips */
  18160 
  18161 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18162     { /* SOC_REG_INT_GMAC0_XMTADDR_LOW_2r */
  18163         soc_block_list[61],
  18164         soc_iprocreg,
  18165         1,
  18166         0,
  18167         0x18022288,
  18168         0,
  18169         0,
  18170         2,
  18171         soc_GMAC0_XMTADDR_LOW_0r_fields,
  18172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18174         -1,
  18175         -1,
  18176     },
  18177 #endif /* chips */
  18178 
  18179 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18180     { /* SOC_REG_INT_GMAC0_XMTADDR_LOW_3r */
  18181         soc_block_list[61],
  18182         soc_iprocreg,
  18183         1,
  18184         0,
  18185         0x180222c8,
  18186         0,
  18187         0,
  18188         2,
  18189         soc_GMAC0_XMTADDR_LOW_0r_fields,
  18190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18192         -1,
  18193         -1,
  18194     },
  18195 #endif /* chips */
  18196 
  18197 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18198     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18199     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18200     defined(BCM_56260_B0)
  18201     { /* SOC_REG_INT_GMAC0_XMTADDR_LOW_0_BCM53400_A0r */
  18202         soc_block_list[61],
  18203         soc_iprocreg,
  18204         1,
  18205         0,
  18206         0x18042208,
  18207         0,
  18208         0,
  18209         2,
  18210         soc_GMAC0_XMTADDR_LOW_0_BCM53400_A0r_fields,
  18211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18212         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18213         -1,
  18214         -1,
  18215     },
  18216 #endif /* chips */
  18217 
  18218 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  18219     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18220     defined(BCM_56450_B1)
  18221     { /* SOC_REG_INT_GMAC0_XMTCONTROL_0r */
  18222         soc_block_list[61],
  18223         soc_iprocreg,
  18224         1,
  18225         0,
  18226         0x18022200,
  18227         0,
  18228         0,
  18229         11,
  18230         soc_GMAC0_XMTCONTROL_0r_fields,
  18231         SOC_RESET_VAL_DEC(0x00040000, 0x00000000)
  18232         SOC_RESET_MASK_DEC(0x03ff28e7, 0x00000000)
  18233         -1,
  18234         -1,
  18235     },
  18236 #endif /* chips */
  18237 
  18238 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18239     { /* SOC_REG_INT_GMAC0_XMTCONTROL_1r */
  18240         soc_block_list[61],
  18241         soc_iprocreg,
  18242         1,
  18243         0,
  18244         0x18022240,
  18245         0,
  18246         0,
  18247         10,
  18248         soc_GMAC0_XMTCONTROL_1r_fields,
  18249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18250         SOC_RESET_MASK_DEC(0x03ff28e3, 0x00000000)
  18251         -1,
  18252         -1,
  18253     },
  18254 #endif /* chips */
  18255 
  18256 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18257     { /* SOC_REG_INT_GMAC0_XMTCONTROL_2r */
  18258         soc_block_list[61],
  18259         soc_iprocreg,
  18260         1,
  18261         0,
  18262         0x18022280,
  18263         0,
  18264         0,
  18265         10,
  18266         soc_GMAC0_XMTCONTROL_1r_fields,
  18267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18268         SOC_RESET_MASK_DEC(0x03ff28e3, 0x00000000)
  18269         -1,
  18270         -1,
  18271     },
  18272 #endif /* chips */
  18273 
  18274 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18275     { /* SOC_REG_INT_GMAC0_XMTCONTROL_3r */
  18276         soc_block_list[61],
  18277         soc_iprocreg,
  18278         1,
  18279         0,
  18280         0x180222c0,
  18281         0,
  18282         0,
  18283         10,
  18284         soc_GMAC0_XMTCONTROL_1r_fields,
  18285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18286         SOC_RESET_MASK_DEC(0x03ff28e3, 0x00000000)
  18287         -1,
  18288         -1,
  18289     },
  18290 #endif /* chips */
  18291 
  18292 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18293     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18294     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18295     defined(BCM_56260_B0)
  18296     { /* SOC_REG_INT_GMAC0_XMTCONTROL_0_BCM53400_A0r */
  18297         soc_block_list[61],
  18298         soc_iprocreg,
  18299         1,
  18300         0,
  18301         0x18042200,
  18302         0,
  18303         0,
  18304         11,
  18305         soc_GMAC0_XMTCONTROL_0_BCM53400_A0r_fields,
  18306         SOC_RESET_VAL_DEC(0x00040000, 0x00000000)
  18307         SOC_RESET_MASK_DEC(0x03ff28e7, 0x00000000)
  18308         -1,
  18309         -1,
  18310     },
  18311 #endif /* chips */
  18312 
  18313 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  18314     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18315     defined(BCM_56450_B1)
  18316     { /* SOC_REG_INT_GMAC0_XMTPTR_0r */
  18317         soc_block_list[61],
  18318         soc_iprocreg,
  18319         1,
  18320         0,
  18321         0x18022204,
  18322         0,
  18323         0,
  18324         1,
  18325         soc_GMAC0_XMTPTR_0r_fields,
  18326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18327         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  18328         -1,
  18329         -1,
  18330     },
  18331 #endif /* chips */
  18332 
  18333 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18334     { /* SOC_REG_INT_GMAC0_XMTPTR_1r */
  18335         soc_block_list[61],
  18336         soc_iprocreg,
  18337         1,
  18338         0,
  18339         0x18022244,
  18340         0,
  18341         0,
  18342         1,
  18343         soc_GMAC0_XMTPTR_0r_fields,
  18344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18345         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  18346         -1,
  18347         -1,
  18348     },
  18349 #endif /* chips */
  18350 
  18351 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18352     { /* SOC_REG_INT_GMAC0_XMTPTR_2r */
  18353         soc_block_list[61],
  18354         soc_iprocreg,
  18355         1,
  18356         0,
  18357         0x18022284,
  18358         0,
  18359         0,
  18360         1,
  18361         soc_GMAC0_XMTPTR_0r_fields,
  18362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18363         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  18364         -1,
  18365         -1,
  18366     },
  18367 #endif /* chips */
  18368 
  18369 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18370     { /* SOC_REG_INT_GMAC0_XMTPTR_3r */
  18371         soc_block_list[61],
  18372         soc_iprocreg,
  18373         1,
  18374         0,
  18375         0x180222c4,
  18376         0,
  18377         0,
  18378         1,
  18379         soc_GMAC0_XMTPTR_0r_fields,
  18380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18381         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  18382         -1,
  18383         -1,
  18384     },
  18385 #endif /* chips */
  18386 
  18387 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18388     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18389     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18390     defined(BCM_56260_B0)
  18391     { /* SOC_REG_INT_GMAC0_XMTPTR_0_BCM53400_A0r */
  18392         soc_block_list[61],
  18393         soc_iprocreg,
  18394         1,
  18395         0,
  18396         0x18042204,
  18397         0,
  18398         0,
  18399         1,
  18400         soc_GMAC0_XMTPTR_0_BCM53400_A0r_fields,
  18401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18402         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  18403         -1,
  18404         -1,
  18405     },
  18406 #endif /* chips */
  18407 
  18408 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  18409     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18410     defined(BCM_56450_B1)
  18411     { /* SOC_REG_INT_GMAC0_XMTSTATUS0_0r */
  18412         soc_block_list[61],
  18413         soc_iprocreg,
  18414         1,
  18415         0,
  18416         0x18022210,
  18417         SOC_REG_FLAG_RO,
  18418         0,
  18419         2,
  18420         soc_GMAC0_XMTSTATUS0_0r_fields,
  18421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18422         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18423         -1,
  18424         -1,
  18425     },
  18426 #endif /* chips */
  18427 
  18428 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18429     { /* SOC_REG_INT_GMAC0_XMTSTATUS0_1r */
  18430         soc_block_list[61],
  18431         soc_iprocreg,
  18432         1,
  18433         0,
  18434         0x18022250,
  18435         SOC_REG_FLAG_RO,
  18436         0,
  18437         2,
  18438         soc_GMAC0_XMTSTATUS0_0r_fields,
  18439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18440         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18441         -1,
  18442         -1,
  18443     },
  18444 #endif /* chips */
  18445 
  18446 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18447     { /* SOC_REG_INT_GMAC0_XMTSTATUS0_2r */
  18448         soc_block_list[61],
  18449         soc_iprocreg,
  18450         1,
  18451         0,
  18452         0x18022290,
  18453         SOC_REG_FLAG_RO,
  18454         0,
  18455         2,
  18456         soc_GMAC0_XMTSTATUS0_0r_fields,
  18457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18458         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18459         -1,
  18460         -1,
  18461     },
  18462 #endif /* chips */
  18463 
  18464 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18465     { /* SOC_REG_INT_GMAC0_XMTSTATUS0_3r */
  18466         soc_block_list[61],
  18467         soc_iprocreg,
  18468         1,
  18469         0,
  18470         0x180222d0,
  18471         SOC_REG_FLAG_RO,
  18472         0,
  18473         2,
  18474         soc_GMAC0_XMTSTATUS0_0r_fields,
  18475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18476         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18477         -1,
  18478         -1,
  18479     },
  18480 #endif /* chips */
  18481 
  18482 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18483     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18484     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18485     defined(BCM_56260_B0)
  18486     { /* SOC_REG_INT_GMAC0_XMTSTATUS0_0_BCM53400_A0r */
  18487         soc_block_list[61],
  18488         soc_iprocreg,
  18489         1,
  18490         0,
  18491         0x18042210,
  18492         SOC_REG_FLAG_RO,
  18493         0,
  18494         2,
  18495         soc_GMAC0_XMTSTATUS0_0_BCM53400_A0r_fields,
  18496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18497         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18498         -1,
  18499         -1,
  18500     },
  18501 #endif /* chips */
  18502 
  18503 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  18504     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18505     defined(BCM_56450_B1)
  18506     { /* SOC_REG_INT_GMAC0_XMTSTATUS1_0r */
  18507         soc_block_list[61],
  18508         soc_iprocreg,
  18509         1,
  18510         0,
  18511         0x18022214,
  18512         SOC_REG_FLAG_RO,
  18513         0,
  18514         2,
  18515         soc_GMAC0_XMTSTATUS1_0r_fields,
  18516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18517         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18518         -1,
  18519         -1,
  18520     },
  18521 #endif /* chips */
  18522 
  18523 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18524     { /* SOC_REG_INT_GMAC0_XMTSTATUS1_1r */
  18525         soc_block_list[61],
  18526         soc_iprocreg,
  18527         1,
  18528         0,
  18529         0x18022254,
  18530         SOC_REG_FLAG_RO,
  18531         0,
  18532         2,
  18533         soc_GMAC0_XMTSTATUS1_0r_fields,
  18534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18535         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18536         -1,
  18537         -1,
  18538     },
  18539 #endif /* chips */
  18540 
  18541 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18542     { /* SOC_REG_INT_GMAC0_XMTSTATUS1_2r */
  18543         soc_block_list[61],
  18544         soc_iprocreg,
  18545         1,
  18546         0,
  18547         0x18022294,
  18548         SOC_REG_FLAG_RO,
  18549         0,
  18550         2,
  18551         soc_GMAC0_XMTSTATUS1_0r_fields,
  18552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18553         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18554         -1,
  18555         -1,
  18556     },
  18557 #endif /* chips */
  18558 
  18559 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18560     { /* SOC_REG_INT_GMAC0_XMTSTATUS1_3r */
  18561         soc_block_list[61],
  18562         soc_iprocreg,
  18563         1,
  18564         0,
  18565         0x180222d4,
  18566         SOC_REG_FLAG_RO,
  18567         0,
  18568         2,
  18569         soc_GMAC0_XMTSTATUS1_0r_fields,
  18570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18571         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18572         -1,
  18573         -1,
  18574     },
  18575 #endif /* chips */
  18576 
  18577 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18578     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18579     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18580     defined(BCM_56260_B0)
  18581     { /* SOC_REG_INT_GMAC0_XMTSTATUS1_0_BCM53400_A0r */
  18582         soc_block_list[61],
  18583         soc_iprocreg,
  18584         1,
  18585         0,
  18586         0x18042214,
  18587         SOC_REG_FLAG_RO,
  18588         0,
  18589         2,
  18590         soc_GMAC0_XMTSTATUS1_0_BCM53400_A0r_fields,
  18591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18592         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  18593         -1,
  18594         -1,
  18595     },
  18596 #endif /* chips */
  18597 
  18598 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  18599     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18600     { /* SOC_REG_INT_GMAC1_BISTSTATUSr */
  18601         soc_block_list[61],
  18602         soc_iprocreg,
  18603         1,
  18604         0,
  18605         0x1802300c,
  18606         SOC_REG_FLAG_RO,
  18607         0,
  18608         10,
  18609         soc_GMAC0_BISTSTATUSr_fields,
  18610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18611         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  18612         -1,
  18613         -1,
  18614     },
  18615 #endif /* chips */
  18616 
  18617 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18618     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18619     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18620     defined(BCM_56260_B0)
  18621     { /* SOC_REG_INT_GMAC1_BISTSTATUS_BCM53400_A0r */
  18622         soc_block_list[61],
  18623         soc_iprocreg,
  18624         1,
  18625         0,
  18626         0x1804a00c,
  18627         SOC_REG_FLAG_RO,
  18628         0,
  18629         10,
  18630         soc_GMAC0_BISTSTATUS_BCM53400_A0r_fields,
  18631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18632         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  18633         -1,
  18634         -1,
  18635     },
  18636 #endif /* chips */
  18637 
  18638 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  18639     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
  18640     defined(BCM_56260_A0) || defined(BCM_56260_B0)
  18641     { /* SOC_REG_INT_GMAC1_CKSUM_CONTROLr */
  18642         soc_block_list[61],
  18643         soc_iprocreg,
  18644         1,
  18645         0,
  18646         0x1804a2e0,
  18647         0,
  18648         0,
  18649         5,
  18650         soc_GMAC0_CKSUM_CONTROLr_fields,
  18651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18652         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  18653         -1,
  18654         -1,
  18655     },
  18656 #endif /* chips */
  18657 
  18658 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  18659     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18660     { /* SOC_REG_INT_GMAC1_CLOCKCONTROLSTATUSr */
  18661         soc_block_list[61],
  18662         soc_iprocreg,
  18663         1,
  18664         0,
  18665         0x180231e0,
  18666         0,
  18667         0,
  18668         12,
  18669         soc_GMAC0_CLOCKCONTROLSTATUSr_fields,
  18670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18671         SOC_RESET_MASK_DEC(0x010f013f, 0x00000000)
  18672         -1,
  18673         -1,
  18674     },
  18675 #endif /* chips */
  18676 
  18677 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18678     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18679     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18680     defined(BCM_56260_B0)
  18681     { /* SOC_REG_INT_GMAC1_CLOCKCONTROLSTATUS_BCM53400_A0r */
  18682         soc_block_list[61],
  18683         soc_iprocreg,
  18684         1,
  18685         0,
  18686         0x1804a1e0,
  18687         0,
  18688         0,
  18689         12,
  18690         soc_GMAC0_CLOCKCONTROLSTATUS_BCM53400_A0r_fields,
  18691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18692         SOC_RESET_MASK_DEC(0x010f013f, 0x00000000)
  18693         -1,
  18694         -1,
  18695     },
  18696 #endif /* chips */
  18697 
  18698 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  18699     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18700     { /* SOC_REG_INT_GMAC1_DEVCONTROLr */
  18701         soc_block_list[61],
  18702         soc_iprocreg,
  18703         1,
  18704         0,
  18705         0x18023000,
  18706         0,
  18707         0,
  18708         12,
  18709         soc_GMAC0_DEVCONTROLr_fields,
  18710         SOC_RESET_VAL_DEC(0x00300003, 0x00000000)
  18711         SOC_RESET_MASK_DEC(0x003f01ff, 0x00000000)
  18712         -1,
  18713         -1,
  18714     },
  18715 #endif /* chips */
  18716 
  18717 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18718     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18719     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18720     defined(BCM_56260_B0)
  18721     { /* SOC_REG_INT_GMAC1_DEVCONTROL_BCM53400_A0r */
  18722         soc_block_list[61],
  18723         soc_iprocreg,
  18724         1,
  18725         0,
  18726         0x1804a000,
  18727         0,
  18728         0,
  18729         12,
  18730         soc_GMAC0_DEVCONTROL_BCM53400_A0r_fields,
  18731         SOC_RESET_VAL_DEC(0x00300003, 0x00000000)
  18732         SOC_RESET_MASK_DEC(0x003f01ff, 0x00000000)
  18733         -1,
  18734         -1,
  18735     },
  18736 #endif /* chips */
  18737 
  18738 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  18739     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18740     { /* SOC_REG_INT_GMAC1_DEVSTATUSr */
  18741         soc_block_list[61],
  18742         soc_iprocreg,
  18743         1,
  18744         0,
  18745         0x18023004,
  18746         SOC_REG_FLAG_RO,
  18747         0,
  18748         10,
  18749         soc_GMAC0_DEVSTATUSr_fields,
  18750         SOC_RESET_VAL_DEC(0x00131100, 0x00000000)
  18751         SOC_RESET_MASK_DEC(0x00ff1f7f, 0x00000000)
  18752         -1,
  18753         -1,
  18754     },
  18755 #endif /* chips */
  18756 
  18757 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18758     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18759     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18760     defined(BCM_56260_B0)
  18761     { /* SOC_REG_INT_GMAC1_DEVSTATUS_BCM53400_A0r */
  18762         soc_block_list[61],
  18763         soc_iprocreg,
  18764         1,
  18765         0,
  18766         0x1804a004,
  18767         SOC_REG_FLAG_RO,
  18768         0,
  18769         10,
  18770         soc_GMAC0_DEVSTATUS_BCM53400_A0r_fields,
  18771         SOC_RESET_VAL_DEC(0x00131100, 0x00000000)
  18772         SOC_RESET_MASK_DEC(0x00ff1f7f, 0x00000000)
  18773         -1,
  18774         -1,
  18775     },
  18776 #endif /* chips */
  18777 
  18778 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18779     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18780     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18781     defined(BCM_56260_B0)
  18782     { /* SOC_REG_INT_GMAC1_EEECONTROLr */
  18783         soc_block_list[61],
  18784         soc_iprocreg,
  18785         1,
  18786         0,
  18787         0x1804a1ec,
  18788         0,
  18789         0,
  18790         3,
  18791         soc_GMAC0_EEECONTROLr_fields,
  18792         SOC_RESET_VAL_DEC(0x000003e8, 0x00000000)
  18793         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  18794         -1,
  18795         -1,
  18796     },
  18797 #endif /* chips */
  18798 
  18799 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18800     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18801     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18802     defined(BCM_56260_B0)
  18803     { /* SOC_REG_INT_GMAC1_EEERXDURATIONCOUNTr */
  18804         soc_block_list[61],
  18805         soc_iprocreg,
  18806         1,
  18807         0,
  18808         0x1804a1fc,
  18809         0,
  18810         0,
  18811         1,
  18812         soc_GMAC0_EEERXDURATIONCOUNTr_fields,
  18813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18814         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18815         -1,
  18816         -1,
  18817     },
  18818 #endif /* chips */
  18819 
  18820 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18821     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18822     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18823     defined(BCM_56260_B0)
  18824     { /* SOC_REG_INT_GMAC1_EEERXEVENTCOUNTr */
  18825         soc_block_list[61],
  18826         soc_iprocreg,
  18827         1,
  18828         0,
  18829         0x1804a1f8,
  18830         0,
  18831         0,
  18832         1,
  18833         soc_GMAC0_EEERXEVENTCOUNTr_fields,
  18834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18836         -1,
  18837         -1,
  18838     },
  18839 #endif /* chips */
  18840 
  18841 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18842     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18843     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18844     defined(BCM_56260_B0)
  18845     { /* SOC_REG_INT_GMAC1_EEETXDURATIONCOUNTr */
  18846         soc_block_list[61],
  18847         soc_iprocreg,
  18848         1,
  18849         0,
  18850         0x1804a1f4,
  18851         0,
  18852         0,
  18853         1,
  18854         soc_GMAC0_EEETXDURATIONCOUNTr_fields,
  18855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18856         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18857         -1,
  18858         -1,
  18859     },
  18860 #endif /* chips */
  18861 
  18862 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18863     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18864     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18865     defined(BCM_56260_B0)
  18866     { /* SOC_REG_INT_GMAC1_EEETXEVENTCOUNTr */
  18867         soc_block_list[61],
  18868         soc_iprocreg,
  18869         1,
  18870         0,
  18871         0x1804a1f0,
  18872         0,
  18873         0,
  18874         1,
  18875         soc_GMAC0_EEETXEVENTCOUNTr_fields,
  18876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18878         -1,
  18879         -1,
  18880     },
  18881 #endif /* chips */
  18882 
  18883 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  18884     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18885     { /* SOC_REG_INT_GMAC1_FIFOACCESSADDRr */
  18886         soc_block_list[61],
  18887         soc_iprocreg,
  18888         1,
  18889         0,
  18890         0x18023120,
  18891         0,
  18892         0,
  18893         2,
  18894         soc_GMAC0_FIFOACCESSADDRr_fields,
  18895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18896         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  18897         -1,
  18898         -1,
  18899     },
  18900 #endif /* chips */
  18901 
  18902 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18903     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18904     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18905     defined(BCM_56260_B0)
  18906     { /* SOC_REG_INT_GMAC1_FIFOACCESSADDR_BCM53400_A0r */
  18907         soc_block_list[61],
  18908         soc_iprocreg,
  18909         1,
  18910         0,
  18911         0x1804a120,
  18912         0,
  18913         0,
  18914         2,
  18915         soc_GMAC0_FIFOACCESSADDR_BCM53400_A0r_fields,
  18916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18917         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  18918         -1,
  18919         -1,
  18920     },
  18921 #endif /* chips */
  18922 
  18923 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  18924     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18925     { /* SOC_REG_INT_GMAC1_FIFOACCESSBYTEr */
  18926         soc_block_list[61],
  18927         soc_iprocreg,
  18928         1,
  18929         0,
  18930         0x18023124,
  18931         0,
  18932         0,
  18933         1,
  18934         soc_GMAC0_FIFOACCESSBYTEr_fields,
  18935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18936         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  18937         -1,
  18938         -1,
  18939     },
  18940 #endif /* chips */
  18941 
  18942 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18943     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18944     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18945     defined(BCM_56260_B0)
  18946     { /* SOC_REG_INT_GMAC1_FIFOACCESSBYTE_BCM53400_A0r */
  18947         soc_block_list[61],
  18948         soc_iprocreg,
  18949         1,
  18950         0,
  18951         0x1804a124,
  18952         0,
  18953         0,
  18954         1,
  18955         soc_GMAC0_FIFOACCESSBYTE_BCM53400_A0r_fields,
  18956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18957         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  18958         -1,
  18959         -1,
  18960     },
  18961 #endif /* chips */
  18962 
  18963 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  18964     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  18965     { /* SOC_REG_INT_GMAC1_FIFOACCESSDATAr */
  18966         soc_block_list[61],
  18967         soc_iprocreg,
  18968         1,
  18969         0,
  18970         0x18023128,
  18971         0,
  18972         0,
  18973         1,
  18974         soc_GMAC0_FIFOACCESSDATAr_fields,
  18975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18976         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18977         -1,
  18978         -1,
  18979     },
  18980 #endif /* chips */
  18981 
  18982 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18983     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18984     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18985     defined(BCM_56260_B0)
  18986     { /* SOC_REG_INT_GMAC1_FIFOACCESSDATA_BCM53400_A0r */
  18987         soc_block_list[61],
  18988         soc_iprocreg,
  18989         1,
  18990         0,
  18991         0x1804a128,
  18992         0,
  18993         0,
  18994         1,
  18995         soc_GMAC0_FIFOACCESSDATA_BCM53400_A0r_fields,
  18996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18998         -1,
  18999         -1,
  19000     },
  19001 #endif /* chips */
  19002 
  19003 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19004     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19005     { /* SOC_REG_INT_GMAC1_FLOWCNTL_THr */
  19006         soc_block_list[61],
  19007         soc_iprocreg,
  19008         1,
  19009         0,
  19010         0x18023104,
  19011         0,
  19012         0,
  19013         2,
  19014         soc_GMAC0_FLOWCNTL_THr_fields,
  19015         SOC_RESET_VAL_DEC(0x04cc0599, 0x00000000)
  19016         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19017         -1,
  19018         -1,
  19019     },
  19020 #endif /* chips */
  19021 
  19022 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19023     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19024     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19025     defined(BCM_56260_B0)
  19026     { /* SOC_REG_INT_GMAC1_FLOWCNTL_TH_BCM53400_A0r */
  19027         soc_block_list[61],
  19028         soc_iprocreg,
  19029         1,
  19030         0,
  19031         0x1804a104,
  19032         0,
  19033         0,
  19034         2,
  19035         soc_GMAC0_FLOWCNTL_TH_BCM53400_A0r_fields,
  19036         SOC_RESET_VAL_DEC(0x04cc0599, 0x00000000)
  19037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19038         -1,
  19039         -1,
  19040     },
  19041 #endif /* chips */
  19042 
  19043 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19044     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19045     { /* SOC_REG_INT_GMAC1_GMACIDLE_CNT_THr */
  19046         soc_block_list[61],
  19047         soc_iprocreg,
  19048         1,
  19049         0,
  19050         0x1802310c,
  19051         0,
  19052         0,
  19053         2,
  19054         soc_GMAC0_GMACIDLE_CNT_THr_fields,
  19055         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  19056         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19057         -1,
  19058         -1,
  19059     },
  19060 #endif /* chips */
  19061 
  19062 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19063     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19064     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19065     defined(BCM_56260_B0)
  19066     { /* SOC_REG_INT_GMAC1_GMACIDLE_CNT_TH_BCM53400_A0r */
  19067         soc_block_list[61],
  19068         soc_iprocreg,
  19069         1,
  19070         0,
  19071         0x1804a10c,
  19072         0,
  19073         0,
  19074         2,
  19075         soc_GMAC0_GMACIDLE_CNT_TH_BCM53400_A0r_fields,
  19076         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  19077         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19078         -1,
  19079         -1,
  19080     },
  19081 #endif /* chips */
  19082 
  19083 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19084     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19085     { /* SOC_REG_INT_GMAC1_GPIOOUTPUTENr */
  19086         soc_block_list[61],
  19087         soc_iprocreg,
  19088         1,
  19089         0,
  19090         0x18023198,
  19091         0,
  19092         0,
  19093         1,
  19094         soc_GMAC0_GPIOOUTPUTENr_fields,
  19095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19096         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19097         -1,
  19098         -1,
  19099     },
  19100 #endif /* chips */
  19101 
  19102 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19103     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19104     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19105     defined(BCM_56260_B0)
  19106     { /* SOC_REG_INT_GMAC1_GPIOOUTPUTEN_BCM53400_A0r */
  19107         soc_block_list[61],
  19108         soc_iprocreg,
  19109         1,
  19110         0,
  19111         0x1804a198,
  19112         0,
  19113         0,
  19114         1,
  19115         soc_GMAC0_GPIOOUTPUTEN_BCM53400_A0r_fields,
  19116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19117         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19118         -1,
  19119         -1,
  19120     },
  19121 #endif /* chips */
  19122 
  19123 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19124     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19125     { /* SOC_REG_INT_GMAC1_GPIOSELECTr */
  19126         soc_block_list[61],
  19127         soc_iprocreg,
  19128         1,
  19129         0,
  19130         0x18023194,
  19131         0,
  19132         0,
  19133         1,
  19134         soc_GMAC0_GPIOSELECTr_fields,
  19135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19136         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  19137         -1,
  19138         -1,
  19139     },
  19140 #endif /* chips */
  19141 
  19142 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19143     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19144     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19145     defined(BCM_56260_B0)
  19146     { /* SOC_REG_INT_GMAC1_GPIOSELECT_BCM53400_A0r */
  19147         soc_block_list[61],
  19148         soc_iprocreg,
  19149         1,
  19150         0,
  19151         0x1804a194,
  19152         0,
  19153         0,
  19154         1,
  19155         soc_GMAC0_GPIOSELECT_BCM53400_A0r_fields,
  19156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19157         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  19158         -1,
  19159         -1,
  19160     },
  19161 #endif /* chips */
  19162 
  19163 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19164     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19165     { /* SOC_REG_INT_GMAC1_GPTIMERr */
  19166         soc_block_list[61],
  19167         soc_iprocreg,
  19168         1,
  19169         0,
  19170         0x18023028,
  19171         0,
  19172         0,
  19173         1,
  19174         soc_GMAC0_GPTIMERr_fields,
  19175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19177         -1,
  19178         -1,
  19179     },
  19180 #endif /* chips */
  19181 
  19182 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19183     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19184     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19185     defined(BCM_56260_B0)
  19186     { /* SOC_REG_INT_GMAC1_GPTIMER_BCM53400_A0r */
  19187         soc_block_list[61],
  19188         soc_iprocreg,
  19189         1,
  19190         0,
  19191         0x1804a028,
  19192         0,
  19193         0,
  19194         1,
  19195         soc_GMAC0_GPTIMER_BCM53400_A0r_fields,
  19196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19198         -1,
  19199         -1,
  19200     },
  19201 #endif /* chips */
  19202 
  19203 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19204     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19205     { /* SOC_REG_INT_GMAC1_INTMASKr */
  19206         soc_block_list[61],
  19207         soc_iprocreg,
  19208         1,
  19209         0,
  19210         0x18023024,
  19211         0,
  19212         0,
  19213         24,
  19214         soc_GMAC0_INTMASKr_fields,
  19215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19216         SOC_RESET_MASK_DEC(0xff01fdff, 0x00000000)
  19217         -1,
  19218         -1,
  19219     },
  19220 #endif /* chips */
  19221 
  19222 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19223     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19224     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19225     defined(BCM_56260_B0)
  19226     { /* SOC_REG_INT_GMAC1_INTMASK_BCM53400_A0r */
  19227         soc_block_list[61],
  19228         soc_iprocreg,
  19229         1,
  19230         0,
  19231         0x1804a024,
  19232         0,
  19233         0,
  19234         24,
  19235         soc_GMAC0_INTMASK_BCM53400_A0r_fields,
  19236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19237         SOC_RESET_MASK_DEC(0xff01fdff, 0x00000000)
  19238         -1,
  19239         -1,
  19240     },
  19241 #endif /* chips */
  19242 
  19243 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19244     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19245     { /* SOC_REG_INT_GMAC1_INTRCVLAZYr */
  19246         soc_block_list[61],
  19247         soc_iprocreg,
  19248         1,
  19249         0,
  19250         0x18023100,
  19251         0,
  19252         0,
  19253         2,
  19254         soc_GMAC0_INTRCVLAZYr_fields,
  19255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19256         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19257         -1,
  19258         -1,
  19259     },
  19260 #endif /* chips */
  19261 
  19262 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19263     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19264     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19265     defined(BCM_56260_B0)
  19266     { /* SOC_REG_INT_GMAC1_INTRCVLAZY_BCM53400_A0r */
  19267         soc_block_list[61],
  19268         soc_iprocreg,
  19269         1,
  19270         0,
  19271         0x1804a100,
  19272         0,
  19273         0,
  19274         2,
  19275         soc_GMAC0_INTRCVLAZY_BCM53400_A0r_fields,
  19276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19277         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19278         -1,
  19279         -1,
  19280     },
  19281 #endif /* chips */
  19282 
  19283 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19284     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19285     { /* SOC_REG_INT_GMAC1_INTSTATUSr */
  19286         soc_block_list[61],
  19287         soc_iprocreg,
  19288         1,
  19289         0,
  19290         0x18023020,
  19291         0,
  19292         0,
  19293         24,
  19294         soc_GMAC0_INTSTATUSr_fields,
  19295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19296         SOC_RESET_MASK_DEC(0xff01fdff, 0x00000000)
  19297         -1,
  19298         -1,
  19299     },
  19300 #endif /* chips */
  19301 
  19302 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19303     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19304     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19305     defined(BCM_56260_B0)
  19306     { /* SOC_REG_INT_GMAC1_INTSTATUS_BCM53400_A0r */
  19307         soc_block_list[61],
  19308         soc_iprocreg,
  19309         1,
  19310         0,
  19311         0x1804a020,
  19312         0,
  19313         0,
  19314         24,
  19315         soc_GMAC0_INTSTATUS_BCM53400_A0r_fields,
  19316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19317         SOC_RESET_MASK_DEC(0xff01fdff, 0x00000000)
  19318         -1,
  19319         -1,
  19320     },
  19321 #endif /* chips */
  19322 
  19323 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19324     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19325     { /* SOC_REG_INT_GMAC1_MEMORYECCSTATUSr */
  19326         soc_block_list[61],
  19327         soc_iprocreg,
  19328         1,
  19329         0,
  19330         0x180231a4,
  19331         0,
  19332         0,
  19333         2,
  19334         soc_GMAC0_MEMORYECCSTATUSr_fields,
  19335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19336         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19337         -1,
  19338         -1,
  19339     },
  19340 #endif /* chips */
  19341 
  19342 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19343     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19344     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19345     defined(BCM_56260_B0)
  19346     { /* SOC_REG_INT_GMAC1_MEMORYECCSTATUS_BCM53400_A0r */
  19347         soc_block_list[61],
  19348         soc_iprocreg,
  19349         1,
  19350         0,
  19351         0x1804a1a4,
  19352         0,
  19353         0,
  19354         2,
  19355         soc_GMAC0_MEMORYECCSTATUS_BCM53400_A0r_fields,
  19356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19357         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19358         -1,
  19359         -1,
  19360     },
  19361 #endif /* chips */
  19362 
  19363 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19364     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19365     { /* SOC_REG_INT_GMAC1_PHYACCESSr */
  19366         soc_block_list[61],
  19367         soc_iprocreg,
  19368         1,
  19369         0,
  19370         0x18023180,
  19371         0,
  19372         0,
  19373         5,
  19374         soc_GMAC0_PHYACCESSr_fields,
  19375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19376         SOC_RESET_MASK_DEC(0x7f1fffff, 0x00000000)
  19377         -1,
  19378         -1,
  19379     },
  19380 #endif /* chips */
  19381 
  19382 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19383     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19384     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19385     defined(BCM_56260_B0)
  19386     { /* SOC_REG_INT_GMAC1_PHYACCESS_BCM53400_A0r */
  19387         soc_block_list[61],
  19388         soc_iprocreg,
  19389         1,
  19390         0,
  19391         0x1804a180,
  19392         0,
  19393         0,
  19394         5,
  19395         soc_GMAC0_PHYACCESS_BCM53400_A0r_fields,
  19396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19397         SOC_RESET_MASK_DEC(0x7f1fffff, 0x00000000)
  19398         -1,
  19399         -1,
  19400     },
  19401 #endif /* chips */
  19402 
  19403 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19404     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19405     { /* SOC_REG_INT_GMAC1_PHYCONTROLr */
  19406         soc_block_list[61],
  19407         soc_iprocreg,
  19408         1,
  19409         0,
  19410         0x18023188,
  19411         0,
  19412         0,
  19413         3,
  19414         soc_GMAC0_PHYCONTROLr_fields,
  19415         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  19416         SOC_RESET_MASK_DEC(0x00ff001f, 0x00000000)
  19417         -1,
  19418         -1,
  19419     },
  19420 #endif /* chips */
  19421 
  19422 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19423     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19424     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19425     defined(BCM_56260_B0)
  19426     { /* SOC_REG_INT_GMAC1_PHYCONTROL_BCM53400_A0r */
  19427         soc_block_list[61],
  19428         soc_iprocreg,
  19429         1,
  19430         0,
  19431         0x1804a188,
  19432         0,
  19433         0,
  19434         3,
  19435         soc_GMAC0_PHYCONTROL_BCM53400_A0r_fields,
  19436         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  19437         SOC_RESET_MASK_DEC(0x00ff001f, 0x00000000)
  19438         -1,
  19439         -1,
  19440     },
  19441 #endif /* chips */
  19442 
  19443 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19444     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19445     { /* SOC_REG_INT_GMAC1_POWERCONTROLr */
  19446         soc_block_list[61],
  19447         soc_iprocreg,
  19448         1,
  19449         0,
  19450         0x180231e8,
  19451         0,
  19452         0,
  19453         1,
  19454         soc_GMAC0_POWERCONTROLr_fields,
  19455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19456         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  19457         -1,
  19458         -1,
  19459     },
  19460 #endif /* chips */
  19461 
  19462 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19463     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19464     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19465     defined(BCM_56260_B0)
  19466     { /* SOC_REG_INT_GMAC1_POWERCONTROL_BCM53400_A0r */
  19467         soc_block_list[61],
  19468         soc_iprocreg,
  19469         1,
  19470         0,
  19471         0x1804a1e8,
  19472         0,
  19473         0,
  19474         1,
  19475         soc_GMAC0_POWERCONTROL_BCM53400_A0r_fields,
  19476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19477         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  19478         -1,
  19479         -1,
  19480     },
  19481 #endif /* chips */
  19482 
  19483 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19484     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19485     { /* SOC_REG_INT_GMAC1_RCVADDR_HIGHr */
  19486         soc_block_list[61],
  19487         soc_iprocreg,
  19488         1,
  19489         0,
  19490         0x1802322c,
  19491         0,
  19492         0,
  19493         1,
  19494         soc_GMAC0_RCVADDR_HIGHr_fields,
  19495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19496         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19497         -1,
  19498         -1,
  19499     },
  19500 #endif /* chips */
  19501 
  19502 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19503     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19504     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19505     defined(BCM_56260_B0)
  19506     { /* SOC_REG_INT_GMAC1_RCVADDR_HIGH_BCM53400_A0r */
  19507         soc_block_list[61],
  19508         soc_iprocreg,
  19509         1,
  19510         0,
  19511         0x1804a22c,
  19512         0,
  19513         0,
  19514         1,
  19515         soc_GMAC0_RCVADDR_HIGH_BCM53400_A0r_fields,
  19516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19517         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19518         -1,
  19519         -1,
  19520     },
  19521 #endif /* chips */
  19522 
  19523 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19524     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19525     { /* SOC_REG_INT_GMAC1_RCVADDR_LOWr */
  19526         soc_block_list[61],
  19527         soc_iprocreg,
  19528         1,
  19529         0,
  19530         0x18023228,
  19531         0,
  19532         0,
  19533         2,
  19534         soc_GMAC0_RCVADDR_LOWr_fields,
  19535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19536         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19537         -1,
  19538         -1,
  19539     },
  19540 #endif /* chips */
  19541 
  19542 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19543     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19544     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19545     defined(BCM_56260_B0)
  19546     { /* SOC_REG_INT_GMAC1_RCVADDR_LOW_BCM53400_A0r */
  19547         soc_block_list[61],
  19548         soc_iprocreg,
  19549         1,
  19550         0,
  19551         0x1804a228,
  19552         0,
  19553         0,
  19554         2,
  19555         soc_GMAC0_RCVADDR_LOW_BCM53400_A0r_fields,
  19556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19557         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19558         -1,
  19559         -1,
  19560     },
  19561 #endif /* chips */
  19562 
  19563 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19564     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19565     { /* SOC_REG_INT_GMAC1_RCVCONTROLr */
  19566         soc_block_list[61],
  19567         soc_iprocreg,
  19568         1,
  19569         0,
  19570         0x18023220,
  19571         0,
  19572         0,
  19573         11,
  19574         soc_GMAC0_RCVCONTROLr_fields,
  19575         SOC_RESET_VAL_DEC(0x00040008, 0x00000000)
  19576         SOC_RESET_MASK_DEC(0x03ff3eff, 0x00000000)
  19577         -1,
  19578         -1,
  19579     },
  19580 #endif /* chips */
  19581 
  19582 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19583     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19584     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19585     defined(BCM_56260_B0)
  19586     { /* SOC_REG_INT_GMAC1_RCVCONTROL_BCM53400_A0r */
  19587         soc_block_list[61],
  19588         soc_iprocreg,
  19589         1,
  19590         0,
  19591         0x1804a220,
  19592         0,
  19593         0,
  19594         11,
  19595         soc_GMAC0_RCVCONTROL_BCM53400_A0r_fields,
  19596         SOC_RESET_VAL_DEC(0x00040008, 0x00000000)
  19597         SOC_RESET_MASK_DEC(0x03ff3eff, 0x00000000)
  19598         -1,
  19599         -1,
  19600     },
  19601 #endif /* chips */
  19602 
  19603 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19604     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19605     { /* SOC_REG_INT_GMAC1_RCVPTRr */
  19606         soc_block_list[61],
  19607         soc_iprocreg,
  19608         1,
  19609         0,
  19610         0x18023224,
  19611         0,
  19612         0,
  19613         1,
  19614         soc_GMAC0_RCVPTRr_fields,
  19615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19616         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  19617         -1,
  19618         -1,
  19619     },
  19620 #endif /* chips */
  19621 
  19622 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19623     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19624     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19625     defined(BCM_56260_B0)
  19626     { /* SOC_REG_INT_GMAC1_RCVPTR_BCM53400_A0r */
  19627         soc_block_list[61],
  19628         soc_iprocreg,
  19629         1,
  19630         0,
  19631         0x1804a224,
  19632         0,
  19633         0,
  19634         1,
  19635         soc_GMAC0_RCVPTR_BCM53400_A0r_fields,
  19636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19637         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  19638         -1,
  19639         -1,
  19640     },
  19641 #endif /* chips */
  19642 
  19643 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19644     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19645     { /* SOC_REG_INT_GMAC1_RCVSTATUS0r */
  19646         soc_block_list[61],
  19647         soc_iprocreg,
  19648         1,
  19649         0,
  19650         0x18023230,
  19651         SOC_REG_FLAG_RO,
  19652         0,
  19653         2,
  19654         soc_GMAC0_RCVSTATUS0r_fields,
  19655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19656         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  19657         -1,
  19658         -1,
  19659     },
  19660 #endif /* chips */
  19661 
  19662 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19663     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19664     { /* SOC_REG_INT_GMAC1_RCVSTATUS1r */
  19665         soc_block_list[61],
  19666         soc_iprocreg,
  19667         1,
  19668         0,
  19669         0x18023234,
  19670         SOC_REG_FLAG_RO,
  19671         0,
  19672         2,
  19673         soc_GMAC0_RCVSTATUS1r_fields,
  19674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19675         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  19676         -1,
  19677         -1,
  19678     },
  19679 #endif /* chips */
  19680 
  19681 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19682     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19683     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19684     defined(BCM_56260_B0)
  19685     { /* SOC_REG_INT_GMAC1_RCVSTATUS0_BCM53400_A0r */
  19686         soc_block_list[61],
  19687         soc_iprocreg,
  19688         1,
  19689         0,
  19690         0x1804a230,
  19691         SOC_REG_FLAG_RO,
  19692         0,
  19693         2,
  19694         soc_GMAC0_RCVSTATUS0_BCM53400_A0r_fields,
  19695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19696         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  19697         -1,
  19698         -1,
  19699     },
  19700 #endif /* chips */
  19701 
  19702 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19703     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19704     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19705     defined(BCM_56260_B0)
  19706     { /* SOC_REG_INT_GMAC1_RCVSTATUS1_BCM53400_A0r */
  19707         soc_block_list[61],
  19708         soc_iprocreg,
  19709         1,
  19710         0,
  19711         0x1804a234,
  19712         SOC_REG_FLAG_RO,
  19713         0,
  19714         2,
  19715         soc_GMAC0_RCVSTATUS1_BCM53400_A0r_fields,
  19716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19717         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  19718         -1,
  19719         -1,
  19720     },
  19721 #endif /* chips */
  19722 
  19723 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  19724     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
  19725     defined(BCM_56260_A0) || defined(BCM_56260_B0)
  19726     { /* SOC_REG_INT_GMAC1_RXPRSR_L3r */
  19727         soc_block_list[61],
  19728         soc_iprocreg,
  19729         1,
  19730         0,
  19731         0x1804a2e8,
  19732         0,
  19733         0,
  19734         2,
  19735         soc_GMAC0_RXPRSR_L3r_fields,
  19736         SOC_RESET_VAL_DEC(0x86dd0800, 0x00000000)
  19737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19738         -1,
  19739         -1,
  19740     },
  19741 #endif /* chips */
  19742 
  19743 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  19744     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
  19745     defined(BCM_56260_A0) || defined(BCM_56260_B0)
  19746     { /* SOC_REG_INT_GMAC1_RXPRSR_MAXLENr */
  19747         soc_block_list[61],
  19748         soc_iprocreg,
  19749         1,
  19750         0,
  19751         0x1804a2ec,
  19752         0,
  19753         0,
  19754         1,
  19755         soc_GMAC0_RXPRSR_MAXLENr_fields,
  19756         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  19757         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19758         -1,
  19759         -1,
  19760     },
  19761 #endif /* chips */
  19762 
  19763 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  19764     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
  19765     defined(BCM_56260_A0) || defined(BCM_56260_B0)
  19766     { /* SOC_REG_INT_GMAC1_RXPRSR_VLANr */
  19767         soc_block_list[61],
  19768         soc_iprocreg,
  19769         1,
  19770         0,
  19771         0x1804a2e4,
  19772         0,
  19773         0,
  19774         2,
  19775         soc_GMAC0_RXPRSR_VLANr_fields,
  19776         SOC_RESET_VAL_DEC(0x81008100, 0x00000000)
  19777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19778         -1,
  19779         -1,
  19780     },
  19781 #endif /* chips */
  19782 
  19783 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19784     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19785     { /* SOC_REG_INT_GMAC1_RXQCONTROLr */
  19786         soc_block_list[61],
  19787         soc_iprocreg,
  19788         1,
  19789         0,
  19790         0x18023190,
  19791         0,
  19792         0,
  19793         3,
  19794         soc_GMAC0_RXQCONTROLr_fields,
  19795         SOC_RESET_VAL_DEC(0x06000001, 0x00000000)
  19796         SOC_RESET_MASK_DEC(0x7f000fff, 0x00000000)
  19797         -1,
  19798         -1,
  19799     },
  19800 #endif /* chips */
  19801 
  19802 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19803     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19804     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19805     defined(BCM_56260_B0)
  19806     { /* SOC_REG_INT_GMAC1_RXQCONTROL_BCM53400_A0r */
  19807         soc_block_list[61],
  19808         soc_iprocreg,
  19809         1,
  19810         0,
  19811         0x1804a190,
  19812         0,
  19813         0,
  19814         3,
  19815         soc_GMAC0_RXQCONTROL_BCM53400_A0r_fields,
  19816         SOC_RESET_VAL_DEC(0x06000001, 0x00000000)
  19817         SOC_RESET_MASK_DEC(0x7f000fff, 0x00000000)
  19818         -1,
  19819         -1,
  19820     },
  19821 #endif /* chips */
  19822 
  19823 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19824     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19825     { /* SOC_REG_INT_GMAC1_RXSACHANGESr */
  19826         soc_block_list[61],
  19827         soc_iprocreg,
  19828         1,
  19829         0,
  19830         0x18023424,
  19831         0,
  19832         0,
  19833         1,
  19834         soc_GMAC0_RXSACHANGESr_fields,
  19835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19837         -1,
  19838         -1,
  19839     },
  19840 #endif /* chips */
  19841 
  19842 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19843     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19844     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19845     defined(BCM_56260_B0)
  19846     { /* SOC_REG_INT_GMAC1_RXSACHANGES_BCM53400_A0r */
  19847         soc_block_list[61],
  19848         soc_iprocreg,
  19849         1,
  19850         0,
  19851         0x1804a424,
  19852         0,
  19853         0,
  19854         1,
  19855         soc_GMAC0_RXSACHANGES_BCM53400_A0r_fields,
  19856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19858         -1,
  19859         -1,
  19860     },
  19861 #endif /* chips */
  19862 
  19863 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19864     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19865     { /* SOC_REG_INT_GMAC1_RXUNICASTPKTSr */
  19866         soc_block_list[61],
  19867         soc_iprocreg,
  19868         1,
  19869         0,
  19870         0x18023428,
  19871         0,
  19872         0,
  19873         1,
  19874         soc_GMAC0_RXUNICASTPKTSr_fields,
  19875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19877         -1,
  19878         -1,
  19879     },
  19880 #endif /* chips */
  19881 
  19882 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19883     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19884     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19885     defined(BCM_56260_B0)
  19886     { /* SOC_REG_INT_GMAC1_RXUNICASTPKTS_BCM53400_A0r */
  19887         soc_block_list[61],
  19888         soc_iprocreg,
  19889         1,
  19890         0,
  19891         0x1804a428,
  19892         0,
  19893         0,
  19894         1,
  19895         soc_GMAC0_RXUNICASTPKTS_BCM53400_A0r_fields,
  19896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19898         -1,
  19899         -1,
  19900     },
  19901 #endif /* chips */
  19902 
  19903 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19904     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19905     { /* SOC_REG_INT_GMAC1_RX_64r */
  19906         soc_block_list[61],
  19907         soc_iprocreg,
  19908         1,
  19909         0,
  19910         0x180233d0,
  19911         0,
  19912         0,
  19913         1,
  19914         soc_GMAC0_RX_64r_fields,
  19915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19916         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19917         -1,
  19918         -1,
  19919     },
  19920 #endif /* chips */
  19921 
  19922 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19923     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19924     { /* SOC_REG_INT_GMAC1_RX_1024_1522r */
  19925         soc_block_list[61],
  19926         soc_iprocreg,
  19927         1,
  19928         0,
  19929         0x180233e4,
  19930         0,
  19931         0,
  19932         1,
  19933         soc_GMAC0_RX_1024_1522r_fields,
  19934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19935         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19936         -1,
  19937         -1,
  19938     },
  19939 #endif /* chips */
  19940 
  19941 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19942     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19943     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19944     defined(BCM_56260_B0)
  19945     { /* SOC_REG_INT_GMAC1_RX_1024_1522_BCM53400_A0r */
  19946         soc_block_list[61],
  19947         soc_iprocreg,
  19948         1,
  19949         0,
  19950         0x1804a3e4,
  19951         0,
  19952         0,
  19953         1,
  19954         soc_GMAC0_RX_1024_1522_BCM53400_A0r_fields,
  19955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19957         -1,
  19958         -1,
  19959     },
  19960 #endif /* chips */
  19961 
  19962 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19963     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  19964     { /* SOC_REG_INT_GMAC1_RX_128_255r */
  19965         soc_block_list[61],
  19966         soc_iprocreg,
  19967         1,
  19968         0,
  19969         0x180233d8,
  19970         0,
  19971         0,
  19972         1,
  19973         soc_GMAC0_RX_128_255r_fields,
  19974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19975         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19976         -1,
  19977         -1,
  19978     },
  19979 #endif /* chips */
  19980 
  19981 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19982     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19983     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19984     defined(BCM_56260_B0)
  19985     { /* SOC_REG_INT_GMAC1_RX_128_255_BCM53400_A0r */
  19986         soc_block_list[61],
  19987         soc_iprocreg,
  19988         1,
  19989         0,
  19990         0x1804a3d8,
  19991         0,
  19992         0,
  19993         1,
  19994         soc_GMAC0_RX_128_255_BCM53400_A0r_fields,
  19995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19997         -1,
  19998         -1,
  19999     },
  20000 #endif /* chips */
  20001 
  20002 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20003     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20004     { /* SOC_REG_INT_GMAC1_RX_1523_2047r */
  20005         soc_block_list[61],
  20006         soc_iprocreg,
  20007         1,
  20008         0,
  20009         0x180233e8,
  20010         0,
  20011         0,
  20012         1,
  20013         soc_GMAC0_RX_1523_2047r_fields,
  20014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20016         -1,
  20017         -1,
  20018     },
  20019 #endif /* chips */
  20020 
  20021 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20022     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20023     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20024     defined(BCM_56260_B0)
  20025     { /* SOC_REG_INT_GMAC1_RX_1523_2047_BCM53400_A0r */
  20026         soc_block_list[61],
  20027         soc_iprocreg,
  20028         1,
  20029         0,
  20030         0x1804a3e8,
  20031         0,
  20032         0,
  20033         1,
  20034         soc_GMAC0_RX_1523_2047_BCM53400_A0r_fields,
  20035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20037         -1,
  20038         -1,
  20039     },
  20040 #endif /* chips */
  20041 
  20042 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20043     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20044     { /* SOC_REG_INT_GMAC1_RX_2048_4095r */
  20045         soc_block_list[61],
  20046         soc_iprocreg,
  20047         1,
  20048         0,
  20049         0x180233ec,
  20050         0,
  20051         0,
  20052         1,
  20053         soc_GMAC0_RX_2048_4095r_fields,
  20054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20055         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20056         -1,
  20057         -1,
  20058     },
  20059 #endif /* chips */
  20060 
  20061 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20062     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20063     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20064     defined(BCM_56260_B0)
  20065     { /* SOC_REG_INT_GMAC1_RX_2048_4095_BCM53400_A0r */
  20066         soc_block_list[61],
  20067         soc_iprocreg,
  20068         1,
  20069         0,
  20070         0x1804a3ec,
  20071         0,
  20072         0,
  20073         1,
  20074         soc_GMAC0_RX_2048_4095_BCM53400_A0r_fields,
  20075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20076         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20077         -1,
  20078         -1,
  20079     },
  20080 #endif /* chips */
  20081 
  20082 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20083     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20084     { /* SOC_REG_INT_GMAC1_RX_256_511r */
  20085         soc_block_list[61],
  20086         soc_iprocreg,
  20087         1,
  20088         0,
  20089         0x180233dc,
  20090         0,
  20091         0,
  20092         1,
  20093         soc_GMAC0_RX_256_511r_fields,
  20094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20096         -1,
  20097         -1,
  20098     },
  20099 #endif /* chips */
  20100 
  20101 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20102     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20103     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20104     defined(BCM_56260_B0)
  20105     { /* SOC_REG_INT_GMAC1_RX_256_511_BCM53400_A0r */
  20106         soc_block_list[61],
  20107         soc_iprocreg,
  20108         1,
  20109         0,
  20110         0x1804a3dc,
  20111         0,
  20112         0,
  20113         1,
  20114         soc_GMAC0_RX_256_511_BCM53400_A0r_fields,
  20115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20116         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20117         -1,
  20118         -1,
  20119     },
  20120 #endif /* chips */
  20121 
  20122 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20123     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20124     { /* SOC_REG_INT_GMAC1_RX_4096_8191r */
  20125         soc_block_list[61],
  20126         soc_iprocreg,
  20127         1,
  20128         0,
  20129         0x180233f0,
  20130         0,
  20131         0,
  20132         1,
  20133         soc_GMAC0_RX_4096_8191r_fields,
  20134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20136         -1,
  20137         -1,
  20138     },
  20139 #endif /* chips */
  20140 
  20141 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20142     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20143     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20144     defined(BCM_56260_B0)
  20145     { /* SOC_REG_INT_GMAC1_RX_4096_8191_BCM53400_A0r */
  20146         soc_block_list[61],
  20147         soc_iprocreg,
  20148         1,
  20149         0,
  20150         0x1804a3f0,
  20151         0,
  20152         0,
  20153         1,
  20154         soc_GMAC0_RX_4096_8191_BCM53400_A0r_fields,
  20155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20157         -1,
  20158         -1,
  20159     },
  20160 #endif /* chips */
  20161 
  20162 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20163     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20164     { /* SOC_REG_INT_GMAC1_RX_512_1023r */
  20165         soc_block_list[61],
  20166         soc_iprocreg,
  20167         1,
  20168         0,
  20169         0x180233e0,
  20170         0,
  20171         0,
  20172         1,
  20173         soc_GMAC0_RX_512_1023r_fields,
  20174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20175         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20176         -1,
  20177         -1,
  20178     },
  20179 #endif /* chips */
  20180 
  20181 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20182     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20183     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20184     defined(BCM_56260_B0)
  20185     { /* SOC_REG_INT_GMAC1_RX_512_1023_BCM53400_A0r */
  20186         soc_block_list[61],
  20187         soc_iprocreg,
  20188         1,
  20189         0,
  20190         0x1804a3e0,
  20191         0,
  20192         0,
  20193         1,
  20194         soc_GMAC0_RX_512_1023_BCM53400_A0r_fields,
  20195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20197         -1,
  20198         -1,
  20199     },
  20200 #endif /* chips */
  20201 
  20202 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20203     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20204     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20205     defined(BCM_56260_B0)
  20206     { /* SOC_REG_INT_GMAC1_RX_64_BCM53400_A0r */
  20207         soc_block_list[61],
  20208         soc_iprocreg,
  20209         1,
  20210         0,
  20211         0x1804a3d0,
  20212         0,
  20213         0,
  20214         1,
  20215         soc_GMAC0_RX_64_BCM53400_A0r_fields,
  20216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20217         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20218         -1,
  20219         -1,
  20220     },
  20221 #endif /* chips */
  20222 
  20223 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20224     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20225     { /* SOC_REG_INT_GMAC1_RX_65_127r */
  20226         soc_block_list[61],
  20227         soc_iprocreg,
  20228         1,
  20229         0,
  20230         0x180233d4,
  20231         0,
  20232         0,
  20233         1,
  20234         soc_GMAC0_RX_65_127r_fields,
  20235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20236         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20237         -1,
  20238         -1,
  20239     },
  20240 #endif /* chips */
  20241 
  20242 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20243     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20244     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20245     defined(BCM_56260_B0)
  20246     { /* SOC_REG_INT_GMAC1_RX_65_127_BCM53400_A0r */
  20247         soc_block_list[61],
  20248         soc_iprocreg,
  20249         1,
  20250         0,
  20251         0x1804a3d4,
  20252         0,
  20253         0,
  20254         1,
  20255         soc_GMAC0_RX_65_127_BCM53400_A0r_fields,
  20256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20258         -1,
  20259         -1,
  20260     },
  20261 #endif /* chips */
  20262 
  20263 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20264     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20265     { /* SOC_REG_INT_GMAC1_RX_8192_MAXr */
  20266         soc_block_list[61],
  20267         soc_iprocreg,
  20268         1,
  20269         0,
  20270         0x180233f4,
  20271         0,
  20272         0,
  20273         1,
  20274         soc_GMAC0_RX_8192_MAXr_fields,
  20275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20276         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20277         -1,
  20278         -1,
  20279     },
  20280 #endif /* chips */
  20281 
  20282 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20283     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20284     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20285     defined(BCM_56260_B0)
  20286     { /* SOC_REG_INT_GMAC1_RX_8192_MAX_BCM53400_A0r */
  20287         soc_block_list[61],
  20288         soc_iprocreg,
  20289         1,
  20290         0,
  20291         0x1804a3f4,
  20292         0,
  20293         0,
  20294         1,
  20295         soc_GMAC0_RX_8192_MAX_BCM53400_A0r_fields,
  20296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20298         -1,
  20299         -1,
  20300     },
  20301 #endif /* chips */
  20302 
  20303 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20304     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20305     { /* SOC_REG_INT_GMAC1_RX_ALIGNr */
  20306         soc_block_list[61],
  20307         soc_iprocreg,
  20308         1,
  20309         0,
  20310         0x18023414,
  20311         0,
  20312         0,
  20313         1,
  20314         soc_GMAC0_RX_ALIGNr_fields,
  20315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20316         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20317         -1,
  20318         -1,
  20319     },
  20320 #endif /* chips */
  20321 
  20322 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20323     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20324     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20325     defined(BCM_56260_B0)
  20326     { /* SOC_REG_INT_GMAC1_RX_ALIGN_BCM53400_A0r */
  20327         soc_block_list[61],
  20328         soc_iprocreg,
  20329         1,
  20330         0,
  20331         0x1804a414,
  20332         0,
  20333         0,
  20334         1,
  20335         soc_GMAC0_RX_ALIGN_BCM53400_A0r_fields,
  20336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20338         -1,
  20339         -1,
  20340     },
  20341 #endif /* chips */
  20342 
  20343 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20344     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20345     { /* SOC_REG_INT_GMAC1_RX_ALL_OCTETS_HIr */
  20346         soc_block_list[61],
  20347         soc_iprocreg,
  20348         1,
  20349         0,
  20350         0x180233c0,
  20351         0,
  20352         0,
  20353         1,
  20354         soc_GMAC0_RX_ALL_OCTETS_HIr_fields,
  20355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20357         -1,
  20358         -1,
  20359     },
  20360 #endif /* chips */
  20361 
  20362 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20363     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20364     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20365     defined(BCM_56260_B0)
  20366     { /* SOC_REG_INT_GMAC1_RX_ALL_OCTETS_HI_BCM53400_A0r */
  20367         soc_block_list[61],
  20368         soc_iprocreg,
  20369         1,
  20370         0,
  20371         0x1804a3c0,
  20372         0,
  20373         0,
  20374         1,
  20375         soc_GMAC0_RX_ALL_OCTETS_HI_BCM53400_A0r_fields,
  20376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20377         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20378         -1,
  20379         -1,
  20380     },
  20381 #endif /* chips */
  20382 
  20383 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20384     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20385     { /* SOC_REG_INT_GMAC1_RX_ALL_OCTETS_LOr */
  20386         soc_block_list[61],
  20387         soc_iprocreg,
  20388         1,
  20389         0,
  20390         0x180233bc,
  20391         0,
  20392         0,
  20393         1,
  20394         soc_GMAC0_RX_ALL_OCTETS_LOr_fields,
  20395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20396         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20397         -1,
  20398         -1,
  20399     },
  20400 #endif /* chips */
  20401 
  20402 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20403     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20404     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20405     defined(BCM_56260_B0)
  20406     { /* SOC_REG_INT_GMAC1_RX_ALL_OCTETS_LO_BCM53400_A0r */
  20407         soc_block_list[61],
  20408         soc_iprocreg,
  20409         1,
  20410         0,
  20411         0x1804a3bc,
  20412         0,
  20413         0,
  20414         1,
  20415         soc_GMAC0_RX_ALL_OCTETS_LO_BCM53400_A0r_fields,
  20416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20418         -1,
  20419         -1,
  20420     },
  20421 #endif /* chips */
  20422 
  20423 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20424     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20425     { /* SOC_REG_INT_GMAC1_RX_ALL_PKTSr */
  20426         soc_block_list[61],
  20427         soc_iprocreg,
  20428         1,
  20429         0,
  20430         0x180233c4,
  20431         0,
  20432         0,
  20433         1,
  20434         soc_GMAC0_RX_ALL_PKTSr_fields,
  20435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20436         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20437         -1,
  20438         -1,
  20439     },
  20440 #endif /* chips */
  20441 
  20442 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20443     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20444     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20445     defined(BCM_56260_B0)
  20446     { /* SOC_REG_INT_GMAC1_RX_ALL_PKTS_BCM53400_A0r */
  20447         soc_block_list[61],
  20448         soc_iprocreg,
  20449         1,
  20450         0,
  20451         0x1804a3c4,
  20452         0,
  20453         0,
  20454         1,
  20455         soc_GMAC0_RX_ALL_PKTS_BCM53400_A0r_fields,
  20456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20457         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20458         -1,
  20459         -1,
  20460     },
  20461 #endif /* chips */
  20462 
  20463 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20464     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20465     { /* SOC_REG_INT_GMAC1_RX_BRDCASTr */
  20466         soc_block_list[61],
  20467         soc_iprocreg,
  20468         1,
  20469         0,
  20470         0x180233c8,
  20471         0,
  20472         0,
  20473         1,
  20474         soc_GMAC0_RX_BRDCASTr_fields,
  20475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20477         -1,
  20478         -1,
  20479     },
  20480 #endif /* chips */
  20481 
  20482 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20483     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20484     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20485     defined(BCM_56260_B0)
  20486     { /* SOC_REG_INT_GMAC1_RX_BRDCAST_BCM53400_A0r */
  20487         soc_block_list[61],
  20488         soc_iprocreg,
  20489         1,
  20490         0,
  20491         0x1804a3c8,
  20492         0,
  20493         0,
  20494         1,
  20495         soc_GMAC0_RX_BRDCAST_BCM53400_A0r_fields,
  20496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20498         -1,
  20499         -1,
  20500     },
  20501 #endif /* chips */
  20502 
  20503 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20504     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20505     { /* SOC_REG_INT_GMAC1_RX_CNTRLr */
  20506         soc_block_list[61],
  20507         soc_iprocreg,
  20508         1,
  20509         0,
  20510         0x18023420,
  20511         0,
  20512         0,
  20513         1,
  20514         soc_GMAC0_RX_CNTRLr_fields,
  20515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20516         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20517         -1,
  20518         -1,
  20519     },
  20520 #endif /* chips */
  20521 
  20522 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20523     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20524     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20525     defined(BCM_56260_B0)
  20526     { /* SOC_REG_INT_GMAC1_RX_CNTRL_BCM53400_A0r */
  20527         soc_block_list[61],
  20528         soc_iprocreg,
  20529         1,
  20530         0,
  20531         0x1804a420,
  20532         0,
  20533         0,
  20534         1,
  20535         soc_GMAC0_RX_CNTRL_BCM53400_A0r_fields,
  20536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20538         -1,
  20539         -1,
  20540     },
  20541 #endif /* chips */
  20542 
  20543 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20544     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20545     { /* SOC_REG_INT_GMAC1_RX_CRCr */
  20546         soc_block_list[61],
  20547         soc_iprocreg,
  20548         1,
  20549         0,
  20550         0x18023410,
  20551         0,
  20552         0,
  20553         1,
  20554         soc_GMAC0_RX_CRCr_fields,
  20555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20557         -1,
  20558         -1,
  20559     },
  20560 #endif /* chips */
  20561 
  20562 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20563     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20564     { /* SOC_REG_INT_GMAC1_RX_CRC_ALIGNr */
  20565         soc_block_list[61],
  20566         soc_iprocreg,
  20567         1,
  20568         0,
  20569         0x18023408,
  20570         0,
  20571         0,
  20572         1,
  20573         soc_GMAC0_RX_CRC_ALIGNr_fields,
  20574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20575         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20576         -1,
  20577         -1,
  20578     },
  20579 #endif /* chips */
  20580 
  20581 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20582     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20583     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20584     defined(BCM_56260_B0)
  20585     { /* SOC_REG_INT_GMAC1_RX_CRC_ALIGN_BCM53400_A0r */
  20586         soc_block_list[61],
  20587         soc_iprocreg,
  20588         1,
  20589         0,
  20590         0x1804a408,
  20591         0,
  20592         0,
  20593         1,
  20594         soc_GMAC0_RX_CRC_ALIGN_BCM53400_A0r_fields,
  20595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20597         -1,
  20598         -1,
  20599     },
  20600 #endif /* chips */
  20601 
  20602 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20603     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20604     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20605     defined(BCM_56260_B0)
  20606     { /* SOC_REG_INT_GMAC1_RX_CRC_BCM53400_A0r */
  20607         soc_block_list[61],
  20608         soc_iprocreg,
  20609         1,
  20610         0,
  20611         0x1804a410,
  20612         0,
  20613         0,
  20614         1,
  20615         soc_GMAC0_RX_CRC_BCM53400_A0r_fields,
  20616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20618         -1,
  20619         -1,
  20620     },
  20621 #endif /* chips */
  20622 
  20623 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20624     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20625     { /* SOC_REG_INT_GMAC1_RX_DROPr */
  20626         soc_block_list[61],
  20627         soc_iprocreg,
  20628         1,
  20629         0,
  20630         0x18023404,
  20631         0,
  20632         0,
  20633         1,
  20634         soc_GMAC0_RX_DROPr_fields,
  20635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20637         -1,
  20638         -1,
  20639     },
  20640 #endif /* chips */
  20641 
  20642 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20643     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20644     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20645     defined(BCM_56260_B0)
  20646     { /* SOC_REG_INT_GMAC1_RX_DROP_BCM53400_A0r */
  20647         soc_block_list[61],
  20648         soc_iprocreg,
  20649         1,
  20650         0,
  20651         0x1804a404,
  20652         0,
  20653         0,
  20654         1,
  20655         soc_GMAC0_RX_DROP_BCM53400_A0r_fields,
  20656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20657         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20658         -1,
  20659         -1,
  20660     },
  20661 #endif /* chips */
  20662 
  20663 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20664     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20665     { /* SOC_REG_INT_GMAC1_RX_FRAGr */
  20666         soc_block_list[61],
  20667         soc_iprocreg,
  20668         1,
  20669         0,
  20670         0x18023400,
  20671         0,
  20672         0,
  20673         1,
  20674         soc_GMAC0_RX_FRAGr_fields,
  20675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20676         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20677         -1,
  20678         -1,
  20679     },
  20680 #endif /* chips */
  20681 
  20682 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20683     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20684     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20685     defined(BCM_56260_B0)
  20686     { /* SOC_REG_INT_GMAC1_RX_FRAG_BCM53400_A0r */
  20687         soc_block_list[61],
  20688         soc_iprocreg,
  20689         1,
  20690         0,
  20691         0x1804a400,
  20692         0,
  20693         0,
  20694         1,
  20695         soc_GMAC0_RX_FRAG_BCM53400_A0r_fields,
  20696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20698         -1,
  20699         -1,
  20700     },
  20701 #endif /* chips */
  20702 
  20703 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20704     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20705     { /* SOC_REG_INT_GMAC1_RX_GD_OCTETS_HIr */
  20706         soc_block_list[61],
  20707         soc_iprocreg,
  20708         1,
  20709         0,
  20710         0x180233b4,
  20711         0,
  20712         0,
  20713         1,
  20714         soc_GMAC0_RX_GD_OCTETS_HIr_fields,
  20715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20716         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20717         -1,
  20718         -1,
  20719     },
  20720 #endif /* chips */
  20721 
  20722 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20723     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20724     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20725     defined(BCM_56260_B0)
  20726     { /* SOC_REG_INT_GMAC1_RX_GD_OCTETS_HI_BCM53400_A0r */
  20727         soc_block_list[61],
  20728         soc_iprocreg,
  20729         1,
  20730         0,
  20731         0x1804a3b4,
  20732         0,
  20733         0,
  20734         1,
  20735         soc_GMAC0_RX_GD_OCTETS_HI_BCM53400_A0r_fields,
  20736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20738         -1,
  20739         -1,
  20740     },
  20741 #endif /* chips */
  20742 
  20743 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20744     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20745     { /* SOC_REG_INT_GMAC1_RX_GD_OCTETS_LOr */
  20746         soc_block_list[61],
  20747         soc_iprocreg,
  20748         1,
  20749         0,
  20750         0x180233b0,
  20751         0,
  20752         0,
  20753         1,
  20754         soc_GMAC0_RX_GD_OCTETS_LOr_fields,
  20755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20757         -1,
  20758         -1,
  20759     },
  20760 #endif /* chips */
  20761 
  20762 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20763     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20764     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20765     defined(BCM_56260_B0)
  20766     { /* SOC_REG_INT_GMAC1_RX_GD_OCTETS_LO_BCM53400_A0r */
  20767         soc_block_list[61],
  20768         soc_iprocreg,
  20769         1,
  20770         0,
  20771         0x1804a3b0,
  20772         0,
  20773         0,
  20774         1,
  20775         soc_GMAC0_RX_GD_OCTETS_LO_BCM53400_A0r_fields,
  20776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20778         -1,
  20779         -1,
  20780     },
  20781 #endif /* chips */
  20782 
  20783 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20784     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20785     { /* SOC_REG_INT_GMAC1_RX_GD_PKTSr */
  20786         soc_block_list[61],
  20787         soc_iprocreg,
  20788         1,
  20789         0,
  20790         0x180233b8,
  20791         0,
  20792         0,
  20793         1,
  20794         soc_GMAC0_RX_GD_PKTSr_fields,
  20795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20797         -1,
  20798         -1,
  20799     },
  20800 #endif /* chips */
  20801 
  20802 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20803     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20804     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20805     defined(BCM_56260_B0)
  20806     { /* SOC_REG_INT_GMAC1_RX_GD_PKTS_BCM53400_A0r */
  20807         soc_block_list[61],
  20808         soc_iprocreg,
  20809         1,
  20810         0,
  20811         0x1804a3b8,
  20812         0,
  20813         0,
  20814         1,
  20815         soc_GMAC0_RX_GD_PKTS_BCM53400_A0r_fields,
  20816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20817         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20818         -1,
  20819         -1,
  20820     },
  20821 #endif /* chips */
  20822 
  20823 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20824     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20825     { /* SOC_REG_INT_GMAC1_RX_JABr */
  20826         soc_block_list[61],
  20827         soc_iprocreg,
  20828         1,
  20829         0,
  20830         0x180233f8,
  20831         0,
  20832         0,
  20833         1,
  20834         soc_GMAC0_RX_JABr_fields,
  20835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20837         -1,
  20838         -1,
  20839     },
  20840 #endif /* chips */
  20841 
  20842 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20843     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20844     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20845     defined(BCM_56260_B0)
  20846     { /* SOC_REG_INT_GMAC1_RX_JAB_BCM53400_A0r */
  20847         soc_block_list[61],
  20848         soc_iprocreg,
  20849         1,
  20850         0,
  20851         0x1804a3f8,
  20852         0,
  20853         0,
  20854         1,
  20855         soc_GMAC0_RX_JAB_BCM53400_A0r_fields,
  20856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20858         -1,
  20859         -1,
  20860     },
  20861 #endif /* chips */
  20862 
  20863 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20864     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20865     { /* SOC_REG_INT_GMAC1_RX_MULTr */
  20866         soc_block_list[61],
  20867         soc_iprocreg,
  20868         1,
  20869         0,
  20870         0x180233cc,
  20871         0,
  20872         0,
  20873         1,
  20874         soc_GMAC0_RX_MULTr_fields,
  20875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20877         -1,
  20878         -1,
  20879     },
  20880 #endif /* chips */
  20881 
  20882 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20883     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20884     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20885     defined(BCM_56260_B0)
  20886     { /* SOC_REG_INT_GMAC1_RX_MULT_BCM53400_A0r */
  20887         soc_block_list[61],
  20888         soc_iprocreg,
  20889         1,
  20890         0,
  20891         0x1804a3cc,
  20892         0,
  20893         0,
  20894         1,
  20895         soc_GMAC0_RX_MULT_BCM53400_A0r_fields,
  20896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20898         -1,
  20899         -1,
  20900     },
  20901 #endif /* chips */
  20902 
  20903 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20904     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20905     { /* SOC_REG_INT_GMAC1_RX_OVRr */
  20906         soc_block_list[61],
  20907         soc_iprocreg,
  20908         1,
  20909         0,
  20910         0x180233fc,
  20911         0,
  20912         0,
  20913         1,
  20914         soc_GMAC0_RX_OVRr_fields,
  20915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20916         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20917         -1,
  20918         -1,
  20919     },
  20920 #endif /* chips */
  20921 
  20922 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20923     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20924     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20925     defined(BCM_56260_B0)
  20926     { /* SOC_REG_INT_GMAC1_RX_OVR_BCM53400_A0r */
  20927         soc_block_list[61],
  20928         soc_iprocreg,
  20929         1,
  20930         0,
  20931         0x1804a3fc,
  20932         0,
  20933         0,
  20934         1,
  20935         soc_GMAC0_RX_OVR_BCM53400_A0r_fields,
  20936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20937         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20938         -1,
  20939         -1,
  20940     },
  20941 #endif /* chips */
  20942 
  20943 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20944     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20945     { /* SOC_REG_INT_GMAC1_RX_PAUSr */
  20946         soc_block_list[61],
  20947         soc_iprocreg,
  20948         1,
  20949         0,
  20950         0x1802341c,
  20951         0,
  20952         0,
  20953         1,
  20954         soc_GMAC0_RX_PAUSr_fields,
  20955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20957         -1,
  20958         -1,
  20959     },
  20960 #endif /* chips */
  20961 
  20962 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20963     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20964     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20965     defined(BCM_56260_B0)
  20966     { /* SOC_REG_INT_GMAC1_RX_PAUS_BCM53400_A0r */
  20967         soc_block_list[61],
  20968         soc_iprocreg,
  20969         1,
  20970         0,
  20971         0x1804a41c,
  20972         0,
  20973         0,
  20974         1,
  20975         soc_GMAC0_RX_PAUS_BCM53400_A0r_fields,
  20976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20978         -1,
  20979         -1,
  20980     },
  20981 #endif /* chips */
  20982 
  20983 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20984     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  20985     { /* SOC_REG_INT_GMAC1_RX_SYMr */
  20986         soc_block_list[61],
  20987         soc_iprocreg,
  20988         1,
  20989         0,
  20990         0x18023418,
  20991         0,
  20992         0,
  20993         1,
  20994         soc_GMAC0_RX_SYMr_fields,
  20995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20997         -1,
  20998         -1,
  20999     },
  21000 #endif /* chips */
  21001 
  21002 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21003     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21004     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21005     defined(BCM_56260_B0)
  21006     { /* SOC_REG_INT_GMAC1_RX_SYM_BCM53400_A0r */
  21007         soc_block_list[61],
  21008         soc_iprocreg,
  21009         1,
  21010         0,
  21011         0x1804a418,
  21012         0,
  21013         0,
  21014         1,
  21015         soc_GMAC0_RX_SYM_BCM53400_A0r_fields,
  21016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21018         -1,
  21019         -1,
  21020     },
  21021 #endif /* chips */
  21022 
  21023 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21024     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21025     { /* SOC_REG_INT_GMAC1_RX_UNDr */
  21026         soc_block_list[61],
  21027         soc_iprocreg,
  21028         1,
  21029         0,
  21030         0x1802340c,
  21031         0,
  21032         0,
  21033         1,
  21034         soc_GMAC0_RX_UNDr_fields,
  21035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21037         -1,
  21038         -1,
  21039     },
  21040 #endif /* chips */
  21041 
  21042 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21043     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21044     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21045     defined(BCM_56260_B0)
  21046     { /* SOC_REG_INT_GMAC1_RX_UND_BCM53400_A0r */
  21047         soc_block_list[61],
  21048         soc_iprocreg,
  21049         1,
  21050         0,
  21051         0x1804a40c,
  21052         0,
  21053         0,
  21054         1,
  21055         soc_GMAC0_RX_UND_BCM53400_A0r_fields,
  21056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21057         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21058         -1,
  21059         -1,
  21060     },
  21061 #endif /* chips */
  21062 
  21063 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21064     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21065     { /* SOC_REG_INT_GMAC1_SERDESCONTROLr */
  21066         soc_block_list[61],
  21067         soc_iprocreg,
  21068         1,
  21069         0,
  21070         0x180231a8,
  21071         0,
  21072         0,
  21073         19,
  21074         soc_GMAC0_SERDESCONTROLr_fields,
  21075         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  21076         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21077         -1,
  21078         -1,
  21079     },
  21080 #endif /* chips */
  21081 
  21082 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21083     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21084     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21085     defined(BCM_56260_B0)
  21086     { /* SOC_REG_INT_GMAC1_SERDESCONTROL_BCM53400_A0r */
  21087         soc_block_list[61],
  21088         soc_iprocreg,
  21089         1,
  21090         0,
  21091         0x1804a1a8,
  21092         0,
  21093         0,
  21094         18,
  21095         soc_GMAC0_SERDESCONTROL_BCM53400_A0r_fields,
  21096         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  21097         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  21098         -1,
  21099         -1,
  21100     },
  21101 #endif /* chips */
  21102 
  21103 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21104     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21105     { /* SOC_REG_INT_GMAC1_SERDESSTATUS0r */
  21106         soc_block_list[61],
  21107         soc_iprocreg,
  21108         1,
  21109         0,
  21110         0x180231ac,
  21111         SOC_REG_FLAG_RO,
  21112         0,
  21113         9,
  21114         soc_GMAC0_SERDESSTATUS0r_fields,
  21115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21116         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21117         -1,
  21118         -1,
  21119     },
  21120 #endif /* chips */
  21121 
  21122 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21123     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21124     { /* SOC_REG_INT_GMAC1_SERDESSTATUS1r */
  21125         soc_block_list[61],
  21126         soc_iprocreg,
  21127         1,
  21128         0,
  21129         0x180231b0,
  21130         SOC_REG_FLAG_RO,
  21131         0,
  21132         6,
  21133         soc_GMAC0_SERDESSTATUS1r_fields,
  21134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21136         -1,
  21137         -1,
  21138     },
  21139 #endif /* chips */
  21140 
  21141 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21142     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21143     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21144     defined(BCM_56260_B0)
  21145     { /* SOC_REG_INT_GMAC1_SERDESSTATUS0_BCM53400_A0r */
  21146         soc_block_list[61],
  21147         soc_iprocreg,
  21148         1,
  21149         0,
  21150         0x1804a1ac,
  21151         SOC_REG_FLAG_RO,
  21152         0,
  21153         9,
  21154         soc_GMAC0_SERDESSTATUS0_BCM53400_A0r_fields,
  21155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21157         -1,
  21158         -1,
  21159     },
  21160 #endif /* chips */
  21161 
  21162 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21163     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21164     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21165     defined(BCM_56260_B0)
  21166     { /* SOC_REG_INT_GMAC1_SERDESSTATUS1_BCM53400_A0r */
  21167         soc_block_list[61],
  21168         soc_iprocreg,
  21169         1,
  21170         0,
  21171         0x1804a1b0,
  21172         SOC_REG_FLAG_RO,
  21173         0,
  21174         6,
  21175         soc_GMAC0_SERDESSTATUS1_BCM53400_A0r_fields,
  21176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21177         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21178         -1,
  21179         -1,
  21180     },
  21181 #endif /* chips */
  21182 
  21183 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21184     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21185     { /* SOC_REG_INT_GMAC1_TXARB_WRR_THr */
  21186         soc_block_list[61],
  21187         soc_iprocreg,
  21188         1,
  21189         0,
  21190         0x18023108,
  21191         0,
  21192         0,
  21193         4,
  21194         soc_GMAC0_TXARB_WRR_THr_fields,
  21195         SOC_RESET_VAL_DEC(0x0a0a0a0a, 0x00000000)
  21196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21197         -1,
  21198         -1,
  21199     },
  21200 #endif /* chips */
  21201 
  21202 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21203     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21204     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21205     defined(BCM_56260_B0)
  21206     { /* SOC_REG_INT_GMAC1_TXARB_WRR_TH_BCM53400_A0r */
  21207         soc_block_list[61],
  21208         soc_iprocreg,
  21209         1,
  21210         0,
  21211         0x1804a108,
  21212         0,
  21213         0,
  21214         4,
  21215         soc_GMAC0_TXARB_WRR_TH_BCM53400_A0r_fields,
  21216         SOC_RESET_VAL_DEC(0x0a0a0a0a, 0x00000000)
  21217         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21218         -1,
  21219         -1,
  21220     },
  21221 #endif /* chips */
  21222 
  21223 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21224     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21225     { /* SOC_REG_INT_GMAC1_TXQCONTROLr */
  21226         soc_block_list[61],
  21227         soc_iprocreg,
  21228         1,
  21229         0,
  21230         0x1802318c,
  21231         0,
  21232         0,
  21233         1,
  21234         soc_GMAC0_TXQCONTROLr_fields,
  21235         SOC_RESET_VAL_DEC(0x00000271, 0x00000000)
  21236         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  21237         -1,
  21238         -1,
  21239     },
  21240 #endif /* chips */
  21241 
  21242 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21243     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21244     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21245     defined(BCM_56260_B0)
  21246     { /* SOC_REG_INT_GMAC1_TXQCONTROL_BCM53400_A0r */
  21247         soc_block_list[61],
  21248         soc_iprocreg,
  21249         1,
  21250         0,
  21251         0x1804a18c,
  21252         0,
  21253         0,
  21254         1,
  21255         soc_GMAC0_TXQCONTROL_BCM53400_A0r_fields,
  21256         SOC_RESET_VAL_DEC(0x00000271, 0x00000000)
  21257         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  21258         -1,
  21259         -1,
  21260     },
  21261 #endif /* chips */
  21262 
  21263 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21264     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21265     { /* SOC_REG_INT_GMAC1_TXQOSQ0OCTET_HIr */
  21266         soc_block_list[61],
  21267         soc_iprocreg,
  21268         1,
  21269         0,
  21270         0x18023384,
  21271         0,
  21272         0,
  21273         1,
  21274         soc_GMAC0_TXQOSQ0OCTET_HIr_fields,
  21275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21276         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21277         -1,
  21278         -1,
  21279     },
  21280 #endif /* chips */
  21281 
  21282 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21283     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21284     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21285     defined(BCM_56260_B0)
  21286     { /* SOC_REG_INT_GMAC1_TXQOSQ0OCTET_HI_BCM53400_A0r */
  21287         soc_block_list[61],
  21288         soc_iprocreg,
  21289         1,
  21290         0,
  21291         0x1804a384,
  21292         0,
  21293         0,
  21294         1,
  21295         soc_GMAC0_TXQOSQ0OCTET_HI_BCM53400_A0r_fields,
  21296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21298         -1,
  21299         -1,
  21300     },
  21301 #endif /* chips */
  21302 
  21303 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21304     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21305     { /* SOC_REG_INT_GMAC1_TXQOSQ0OCTET_LOr */
  21306         soc_block_list[61],
  21307         soc_iprocreg,
  21308         1,
  21309         0,
  21310         0x18023380,
  21311         0,
  21312         0,
  21313         1,
  21314         soc_GMAC0_TXQOSQ0OCTET_LOr_fields,
  21315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21316         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21317         -1,
  21318         -1,
  21319     },
  21320 #endif /* chips */
  21321 
  21322 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21323     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21324     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21325     defined(BCM_56260_B0)
  21326     { /* SOC_REG_INT_GMAC1_TXQOSQ0OCTET_LO_BCM53400_A0r */
  21327         soc_block_list[61],
  21328         soc_iprocreg,
  21329         1,
  21330         0,
  21331         0x1804a380,
  21332         0,
  21333         0,
  21334         1,
  21335         soc_GMAC0_TXQOSQ0OCTET_LO_BCM53400_A0r_fields,
  21336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21338         -1,
  21339         -1,
  21340     },
  21341 #endif /* chips */
  21342 
  21343 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21344     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21345     { /* SOC_REG_INT_GMAC1_TXQOSQ0PKTr */
  21346         soc_block_list[61],
  21347         soc_iprocreg,
  21348         1,
  21349         0,
  21350         0x1802337c,
  21351         0,
  21352         0,
  21353         1,
  21354         soc_GMAC0_TXQOSQ0PKTr_fields,
  21355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21357         -1,
  21358         -1,
  21359     },
  21360 #endif /* chips */
  21361 
  21362 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21363     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21364     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21365     defined(BCM_56260_B0)
  21366     { /* SOC_REG_INT_GMAC1_TXQOSQ0PKT_BCM53400_A0r */
  21367         soc_block_list[61],
  21368         soc_iprocreg,
  21369         1,
  21370         0,
  21371         0x1804a37c,
  21372         0,
  21373         0,
  21374         1,
  21375         soc_GMAC0_TXQOSQ0PKT_BCM53400_A0r_fields,
  21376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21377         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21378         -1,
  21379         -1,
  21380     },
  21381 #endif /* chips */
  21382 
  21383 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21384     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21385     { /* SOC_REG_INT_GMAC1_TXQOSQ1OCTET_HIr */
  21386         soc_block_list[61],
  21387         soc_iprocreg,
  21388         1,
  21389         0,
  21390         0x18023390,
  21391         0,
  21392         0,
  21393         1,
  21394         soc_GMAC0_TXQOSQ1OCTET_HIr_fields,
  21395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21396         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21397         -1,
  21398         -1,
  21399     },
  21400 #endif /* chips */
  21401 
  21402 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21403     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21404     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21405     defined(BCM_56260_B0)
  21406     { /* SOC_REG_INT_GMAC1_TXQOSQ1OCTET_HI_BCM53400_A0r */
  21407         soc_block_list[61],
  21408         soc_iprocreg,
  21409         1,
  21410         0,
  21411         0x1804a390,
  21412         0,
  21413         0,
  21414         1,
  21415         soc_GMAC0_TXQOSQ1OCTET_HI_BCM53400_A0r_fields,
  21416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21418         -1,
  21419         -1,
  21420     },
  21421 #endif /* chips */
  21422 
  21423 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21424     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21425     { /* SOC_REG_INT_GMAC1_TXQOSQ1OCTET_LOr */
  21426         soc_block_list[61],
  21427         soc_iprocreg,
  21428         1,
  21429         0,
  21430         0x1802338c,
  21431         0,
  21432         0,
  21433         1,
  21434         soc_GMAC0_TXQOSQ1OCTET_LOr_fields,
  21435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21436         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21437         -1,
  21438         -1,
  21439     },
  21440 #endif /* chips */
  21441 
  21442 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21443     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21444     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21445     defined(BCM_56260_B0)
  21446     { /* SOC_REG_INT_GMAC1_TXQOSQ1OCTET_LO_BCM53400_A0r */
  21447         soc_block_list[61],
  21448         soc_iprocreg,
  21449         1,
  21450         0,
  21451         0x1804a38c,
  21452         0,
  21453         0,
  21454         1,
  21455         soc_GMAC0_TXQOSQ1OCTET_LO_BCM53400_A0r_fields,
  21456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21457         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21458         -1,
  21459         -1,
  21460     },
  21461 #endif /* chips */
  21462 
  21463 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21464     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21465     { /* SOC_REG_INT_GMAC1_TXQOSQ1PKTr */
  21466         soc_block_list[61],
  21467         soc_iprocreg,
  21468         1,
  21469         0,
  21470         0x18023388,
  21471         0,
  21472         0,
  21473         1,
  21474         soc_GMAC0_TXQOSQ1PKTr_fields,
  21475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21477         -1,
  21478         -1,
  21479     },
  21480 #endif /* chips */
  21481 
  21482 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21483     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21484     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21485     defined(BCM_56260_B0)
  21486     { /* SOC_REG_INT_GMAC1_TXQOSQ1PKT_BCM53400_A0r */
  21487         soc_block_list[61],
  21488         soc_iprocreg,
  21489         1,
  21490         0,
  21491         0x1804a388,
  21492         0,
  21493         0,
  21494         1,
  21495         soc_GMAC0_TXQOSQ1PKT_BCM53400_A0r_fields,
  21496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21498         -1,
  21499         -1,
  21500     },
  21501 #endif /* chips */
  21502 
  21503 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21504     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21505     { /* SOC_REG_INT_GMAC1_TXQOSQ2OCTET_HIr */
  21506         soc_block_list[61],
  21507         soc_iprocreg,
  21508         1,
  21509         0,
  21510         0x1802339c,
  21511         0,
  21512         0,
  21513         1,
  21514         soc_GMAC0_TXQOSQ2OCTET_HIr_fields,
  21515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21516         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21517         -1,
  21518         -1,
  21519     },
  21520 #endif /* chips */
  21521 
  21522 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21523     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21524     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21525     defined(BCM_56260_B0)
  21526     { /* SOC_REG_INT_GMAC1_TXQOSQ2OCTET_HI_BCM53400_A0r */
  21527         soc_block_list[61],
  21528         soc_iprocreg,
  21529         1,
  21530         0,
  21531         0x1804a39c,
  21532         0,
  21533         0,
  21534         1,
  21535         soc_GMAC0_TXQOSQ2OCTET_HI_BCM53400_A0r_fields,
  21536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21538         -1,
  21539         -1,
  21540     },
  21541 #endif /* chips */
  21542 
  21543 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21544     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21545     { /* SOC_REG_INT_GMAC1_TXQOSQ2OCTET_LOr */
  21546         soc_block_list[61],
  21547         soc_iprocreg,
  21548         1,
  21549         0,
  21550         0x18023398,
  21551         0,
  21552         0,
  21553         1,
  21554         soc_GMAC0_TXQOSQ2OCTET_LOr_fields,
  21555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21557         -1,
  21558         -1,
  21559     },
  21560 #endif /* chips */
  21561 
  21562 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21563     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21564     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21565     defined(BCM_56260_B0)
  21566     { /* SOC_REG_INT_GMAC1_TXQOSQ2OCTET_LO_BCM53400_A0r */
  21567         soc_block_list[61],
  21568         soc_iprocreg,
  21569         1,
  21570         0,
  21571         0x1804a398,
  21572         0,
  21573         0,
  21574         1,
  21575         soc_GMAC0_TXQOSQ2OCTET_LO_BCM53400_A0r_fields,
  21576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21578         -1,
  21579         -1,
  21580     },
  21581 #endif /* chips */
  21582 
  21583 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21584     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21585     { /* SOC_REG_INT_GMAC1_TXQOSQ2PKTr */
  21586         soc_block_list[61],
  21587         soc_iprocreg,
  21588         1,
  21589         0,
  21590         0x18023394,
  21591         0,
  21592         0,
  21593         1,
  21594         soc_GMAC0_TXQOSQ2PKTr_fields,
  21595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21597         -1,
  21598         -1,
  21599     },
  21600 #endif /* chips */
  21601 
  21602 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21603     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21604     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21605     defined(BCM_56260_B0)
  21606     { /* SOC_REG_INT_GMAC1_TXQOSQ2PKT_BCM53400_A0r */
  21607         soc_block_list[61],
  21608         soc_iprocreg,
  21609         1,
  21610         0,
  21611         0x1804a394,
  21612         0,
  21613         0,
  21614         1,
  21615         soc_GMAC0_TXQOSQ2PKT_BCM53400_A0r_fields,
  21616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21618         -1,
  21619         -1,
  21620     },
  21621 #endif /* chips */
  21622 
  21623 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21624     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21625     { /* SOC_REG_INT_GMAC1_TXQOSQ3OCTET_HIr */
  21626         soc_block_list[61],
  21627         soc_iprocreg,
  21628         1,
  21629         0,
  21630         0x180233a8,
  21631         0,
  21632         0,
  21633         1,
  21634         soc_GMAC0_TXQOSQ3OCTET_HIr_fields,
  21635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21637         -1,
  21638         -1,
  21639     },
  21640 #endif /* chips */
  21641 
  21642 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21643     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21644     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21645     defined(BCM_56260_B0)
  21646     { /* SOC_REG_INT_GMAC1_TXQOSQ3OCTET_HI_BCM53400_A0r */
  21647         soc_block_list[61],
  21648         soc_iprocreg,
  21649         1,
  21650         0,
  21651         0x1804a3a8,
  21652         0,
  21653         0,
  21654         1,
  21655         soc_GMAC0_TXQOSQ3OCTET_HI_BCM53400_A0r_fields,
  21656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21657         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21658         -1,
  21659         -1,
  21660     },
  21661 #endif /* chips */
  21662 
  21663 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21664     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21665     { /* SOC_REG_INT_GMAC1_TXQOSQ3OCTET_LOr */
  21666         soc_block_list[61],
  21667         soc_iprocreg,
  21668         1,
  21669         0,
  21670         0x180233a4,
  21671         0,
  21672         0,
  21673         1,
  21674         soc_GMAC0_TXQOSQ3OCTET_LOr_fields,
  21675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21676         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21677         -1,
  21678         -1,
  21679     },
  21680 #endif /* chips */
  21681 
  21682 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21683     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21684     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21685     defined(BCM_56260_B0)
  21686     { /* SOC_REG_INT_GMAC1_TXQOSQ3OCTET_LO_BCM53400_A0r */
  21687         soc_block_list[61],
  21688         soc_iprocreg,
  21689         1,
  21690         0,
  21691         0x1804a3a4,
  21692         0,
  21693         0,
  21694         1,
  21695         soc_GMAC0_TXQOSQ3OCTET_LO_BCM53400_A0r_fields,
  21696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21698         -1,
  21699         -1,
  21700     },
  21701 #endif /* chips */
  21702 
  21703 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21704     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21705     { /* SOC_REG_INT_GMAC1_TXQOSQ3PKTr */
  21706         soc_block_list[61],
  21707         soc_iprocreg,
  21708         1,
  21709         0,
  21710         0x180233a0,
  21711         0,
  21712         0,
  21713         1,
  21714         soc_GMAC0_TXQOSQ3PKTr_fields,
  21715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21716         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21717         -1,
  21718         -1,
  21719     },
  21720 #endif /* chips */
  21721 
  21722 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21723     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21724     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21725     defined(BCM_56260_B0)
  21726     { /* SOC_REG_INT_GMAC1_TXQOSQ3PKT_BCM53400_A0r */
  21727         soc_block_list[61],
  21728         soc_iprocreg,
  21729         1,
  21730         0,
  21731         0x1804a3a0,
  21732         0,
  21733         0,
  21734         1,
  21735         soc_GMAC0_TXQOSQ3PKT_BCM53400_A0r_fields,
  21736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21738         -1,
  21739         -1,
  21740     },
  21741 #endif /* chips */
  21742 
  21743 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21744     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21745     { /* SOC_REG_INT_GMAC1_TXQRXQMEMORYCONTROLr */
  21746         soc_block_list[61],
  21747         soc_iprocreg,
  21748         1,
  21749         0,
  21750         0x180231a0,
  21751         0,
  21752         0,
  21753         6,
  21754         soc_GMAC0_TXQRXQMEMORYCONTROLr_fields,
  21755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21756         SOC_RESET_MASK_DEC(0x00ff00ff, 0x00000000)
  21757         -1,
  21758         -1,
  21759     },
  21760 #endif /* chips */
  21761 
  21762 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21763     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21764     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21765     defined(BCM_56260_B0)
  21766     { /* SOC_REG_INT_GMAC1_TXQRXQMEMORYCONTROL_BCM53400_A0r */
  21767         soc_block_list[61],
  21768         soc_iprocreg,
  21769         1,
  21770         0,
  21771         0x1804a1a0,
  21772         0,
  21773         0,
  21774         6,
  21775         soc_GMAC0_TXQRXQMEMORYCONTROL_BCM53400_A0r_fields,
  21776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21777         SOC_RESET_MASK_DEC(0x00ff00ff, 0x00000000)
  21778         -1,
  21779         -1,
  21780     },
  21781 #endif /* chips */
  21782 
  21783 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21784     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21785     { /* SOC_REG_INT_GMAC1_TXUNICASTPKTr */
  21786         soc_block_list[61],
  21787         soc_iprocreg,
  21788         1,
  21789         0,
  21790         0x18023378,
  21791         0,
  21792         0,
  21793         1,
  21794         soc_GMAC0_TXUNICASTPKTr_fields,
  21795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21797         -1,
  21798         -1,
  21799     },
  21800 #endif /* chips */
  21801 
  21802 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21803     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21804     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21805     defined(BCM_56260_B0)
  21806     { /* SOC_REG_INT_GMAC1_TXUNICASTPKT_BCM53400_A0r */
  21807         soc_block_list[61],
  21808         soc_iprocreg,
  21809         1,
  21810         0,
  21811         0x1804a378,
  21812         0,
  21813         0,
  21814         1,
  21815         soc_GMAC0_TXUNICASTPKT_BCM53400_A0r_fields,
  21816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21817         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21818         -1,
  21819         -1,
  21820     },
  21821 #endif /* chips */
  21822 
  21823 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21824     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21825     { /* SOC_REG_INT_GMAC1_TX_64r */
  21826         soc_block_list[61],
  21827         soc_iprocreg,
  21828         1,
  21829         0,
  21830         0x18023320,
  21831         0,
  21832         0,
  21833         1,
  21834         soc_GMAC0_TX_64r_fields,
  21835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21837         -1,
  21838         -1,
  21839     },
  21840 #endif /* chips */
  21841 
  21842 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21843     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21844     { /* SOC_REG_INT_GMAC1_TX_1024_1522r */
  21845         soc_block_list[61],
  21846         soc_iprocreg,
  21847         1,
  21848         0,
  21849         0x18023334,
  21850         0,
  21851         0,
  21852         1,
  21853         soc_GMAC0_TX_1024_1522r_fields,
  21854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21855         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21856         -1,
  21857         -1,
  21858     },
  21859 #endif /* chips */
  21860 
  21861 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21862     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21863     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21864     defined(BCM_56260_B0)
  21865     { /* SOC_REG_INT_GMAC1_TX_1024_1522_BCM53400_A0r */
  21866         soc_block_list[61],
  21867         soc_iprocreg,
  21868         1,
  21869         0,
  21870         0x1804a334,
  21871         0,
  21872         0,
  21873         1,
  21874         soc_GMAC0_TX_1024_1522_BCM53400_A0r_fields,
  21875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21877         -1,
  21878         -1,
  21879     },
  21880 #endif /* chips */
  21881 
  21882 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21883     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21884     { /* SOC_REG_INT_GMAC1_TX_128_255r */
  21885         soc_block_list[61],
  21886         soc_iprocreg,
  21887         1,
  21888         0,
  21889         0x18023328,
  21890         0,
  21891         0,
  21892         1,
  21893         soc_GMAC0_TX_128_255r_fields,
  21894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21895         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21896         -1,
  21897         -1,
  21898     },
  21899 #endif /* chips */
  21900 
  21901 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21902     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21903     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21904     defined(BCM_56260_B0)
  21905     { /* SOC_REG_INT_GMAC1_TX_128_255_BCM53400_A0r */
  21906         soc_block_list[61],
  21907         soc_iprocreg,
  21908         1,
  21909         0,
  21910         0x1804a328,
  21911         0,
  21912         0,
  21913         1,
  21914         soc_GMAC0_TX_128_255_BCM53400_A0r_fields,
  21915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21916         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21917         -1,
  21918         -1,
  21919     },
  21920 #endif /* chips */
  21921 
  21922 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21923     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21924     { /* SOC_REG_INT_GMAC1_TX_1523_2047r */
  21925         soc_block_list[61],
  21926         soc_iprocreg,
  21927         1,
  21928         0,
  21929         0x18023338,
  21930         0,
  21931         0,
  21932         1,
  21933         soc_GMAC0_TX_1523_2047r_fields,
  21934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21935         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21936         -1,
  21937         -1,
  21938     },
  21939 #endif /* chips */
  21940 
  21941 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21942     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21943     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21944     defined(BCM_56260_B0)
  21945     { /* SOC_REG_INT_GMAC1_TX_1523_2047_BCM53400_A0r */
  21946         soc_block_list[61],
  21947         soc_iprocreg,
  21948         1,
  21949         0,
  21950         0x1804a338,
  21951         0,
  21952         0,
  21953         1,
  21954         soc_GMAC0_TX_1523_2047_BCM53400_A0r_fields,
  21955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21957         -1,
  21958         -1,
  21959     },
  21960 #endif /* chips */
  21961 
  21962 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  21963     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  21964     { /* SOC_REG_INT_GMAC1_TX_1_COLr */
  21965         soc_block_list[61],
  21966         soc_iprocreg,
  21967         1,
  21968         0,
  21969         0x1802335c,
  21970         0,
  21971         0,
  21972         1,
  21973         soc_GMAC0_TX_1_COLr_fields,
  21974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21975         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21976         -1,
  21977         -1,
  21978     },
  21979 #endif /* chips */
  21980 
  21981 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21982     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21983     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21984     defined(BCM_56260_B0)
  21985     { /* SOC_REG_INT_GMAC1_TX_1_COL_BCM53400_A0r */
  21986         soc_block_list[61],
  21987         soc_iprocreg,
  21988         1,
  21989         0,
  21990         0x1804a35c,
  21991         0,
  21992         0,
  21993         1,
  21994         soc_GMAC0_TX_1_COL_BCM53400_A0r_fields,
  21995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21997         -1,
  21998         -1,
  21999     },
  22000 #endif /* chips */
  22001 
  22002 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22003     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22004     { /* SOC_REG_INT_GMAC1_TX_2048_4095r */
  22005         soc_block_list[61],
  22006         soc_iprocreg,
  22007         1,
  22008         0,
  22009         0x1802333c,
  22010         0,
  22011         0,
  22012         1,
  22013         soc_GMAC0_TX_2048_4095r_fields,
  22014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22016         -1,
  22017         -1,
  22018     },
  22019 #endif /* chips */
  22020 
  22021 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22022     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22023     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22024     defined(BCM_56260_B0)
  22025     { /* SOC_REG_INT_GMAC1_TX_2048_4095_BCM53400_A0r */
  22026         soc_block_list[61],
  22027         soc_iprocreg,
  22028         1,
  22029         0,
  22030         0x1804a33c,
  22031         0,
  22032         0,
  22033         1,
  22034         soc_GMAC0_TX_2048_4095_BCM53400_A0r_fields,
  22035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22037         -1,
  22038         -1,
  22039     },
  22040 #endif /* chips */
  22041 
  22042 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22043     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22044     { /* SOC_REG_INT_GMAC1_TX_256_511r */
  22045         soc_block_list[61],
  22046         soc_iprocreg,
  22047         1,
  22048         0,
  22049         0x1802332c,
  22050         0,
  22051         0,
  22052         1,
  22053         soc_GMAC0_TX_256_511r_fields,
  22054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22055         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22056         -1,
  22057         -1,
  22058     },
  22059 #endif /* chips */
  22060 
  22061 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22062     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22063     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22064     defined(BCM_56260_B0)
  22065     { /* SOC_REG_INT_GMAC1_TX_256_511_BCM53400_A0r */
  22066         soc_block_list[61],
  22067         soc_iprocreg,
  22068         1,
  22069         0,
  22070         0x1804a32c,
  22071         0,
  22072         0,
  22073         1,
  22074         soc_GMAC0_TX_256_511_BCM53400_A0r_fields,
  22075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22076         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22077         -1,
  22078         -1,
  22079     },
  22080 #endif /* chips */
  22081 
  22082 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22083     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22084     { /* SOC_REG_INT_GMAC1_TX_4096_8191r */
  22085         soc_block_list[61],
  22086         soc_iprocreg,
  22087         1,
  22088         0,
  22089         0x18023340,
  22090         0,
  22091         0,
  22092         1,
  22093         soc_GMAC0_TX_4096_8191r_fields,
  22094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22096         -1,
  22097         -1,
  22098     },
  22099 #endif /* chips */
  22100 
  22101 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22102     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22103     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22104     defined(BCM_56260_B0)
  22105     { /* SOC_REG_INT_GMAC1_TX_4096_8191_BCM53400_A0r */
  22106         soc_block_list[61],
  22107         soc_iprocreg,
  22108         1,
  22109         0,
  22110         0x1804a340,
  22111         0,
  22112         0,
  22113         1,
  22114         soc_GMAC0_TX_4096_8191_BCM53400_A0r_fields,
  22115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22116         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22117         -1,
  22118         -1,
  22119     },
  22120 #endif /* chips */
  22121 
  22122 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22123     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22124     { /* SOC_REG_INT_GMAC1_TX_512_1023r */
  22125         soc_block_list[61],
  22126         soc_iprocreg,
  22127         1,
  22128         0,
  22129         0x18023330,
  22130         0,
  22131         0,
  22132         1,
  22133         soc_GMAC0_TX_512_1023r_fields,
  22134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22136         -1,
  22137         -1,
  22138     },
  22139 #endif /* chips */
  22140 
  22141 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22142     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22143     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22144     defined(BCM_56260_B0)
  22145     { /* SOC_REG_INT_GMAC1_TX_512_1023_BCM53400_A0r */
  22146         soc_block_list[61],
  22147         soc_iprocreg,
  22148         1,
  22149         0,
  22150         0x1804a330,
  22151         0,
  22152         0,
  22153         1,
  22154         soc_GMAC0_TX_512_1023_BCM53400_A0r_fields,
  22155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22157         -1,
  22158         -1,
  22159     },
  22160 #endif /* chips */
  22161 
  22162 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22163     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22164     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22165     defined(BCM_56260_B0)
  22166     { /* SOC_REG_INT_GMAC1_TX_64_BCM53400_A0r */
  22167         soc_block_list[61],
  22168         soc_iprocreg,
  22169         1,
  22170         0,
  22171         0x1804a320,
  22172         0,
  22173         0,
  22174         1,
  22175         soc_GMAC0_TX_64_BCM53400_A0r_fields,
  22176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22177         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22178         -1,
  22179         -1,
  22180     },
  22181 #endif /* chips */
  22182 
  22183 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22184     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22185     { /* SOC_REG_INT_GMAC1_TX_65_127r */
  22186         soc_block_list[61],
  22187         soc_iprocreg,
  22188         1,
  22189         0,
  22190         0x18023324,
  22191         0,
  22192         0,
  22193         1,
  22194         soc_GMAC0_TX_65_127r_fields,
  22195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22197         -1,
  22198         -1,
  22199     },
  22200 #endif /* chips */
  22201 
  22202 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22203     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22204     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22205     defined(BCM_56260_B0)
  22206     { /* SOC_REG_INT_GMAC1_TX_65_127_BCM53400_A0r */
  22207         soc_block_list[61],
  22208         soc_iprocreg,
  22209         1,
  22210         0,
  22211         0x1804a324,
  22212         0,
  22213         0,
  22214         1,
  22215         soc_GMAC0_TX_65_127_BCM53400_A0r_fields,
  22216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22217         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22218         -1,
  22219         -1,
  22220     },
  22221 #endif /* chips */
  22222 
  22223 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22224     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22225     { /* SOC_REG_INT_GMAC1_TX_8192_MAXr */
  22226         soc_block_list[61],
  22227         soc_iprocreg,
  22228         1,
  22229         0,
  22230         0x18023344,
  22231         0,
  22232         0,
  22233         1,
  22234         soc_GMAC0_TX_8192_MAXr_fields,
  22235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22236         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22237         -1,
  22238         -1,
  22239     },
  22240 #endif /* chips */
  22241 
  22242 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22243     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22244     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22245     defined(BCM_56260_B0)
  22246     { /* SOC_REG_INT_GMAC1_TX_8192_MAX_BCM53400_A0r */
  22247         soc_block_list[61],
  22248         soc_iprocreg,
  22249         1,
  22250         0,
  22251         0x1804a344,
  22252         0,
  22253         0,
  22254         1,
  22255         soc_GMAC0_TX_8192_MAX_BCM53400_A0r_fields,
  22256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22258         -1,
  22259         -1,
  22260     },
  22261 #endif /* chips */
  22262 
  22263 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22264     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22265     { /* SOC_REG_INT_GMAC1_TX_ALL_OCTETS_HIr */
  22266         soc_block_list[61],
  22267         soc_iprocreg,
  22268         1,
  22269         0,
  22270         0x18023310,
  22271         0,
  22272         0,
  22273         1,
  22274         soc_GMAC0_TX_ALL_OCTETS_HIr_fields,
  22275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22276         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22277         -1,
  22278         -1,
  22279     },
  22280 #endif /* chips */
  22281 
  22282 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22283     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22284     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22285     defined(BCM_56260_B0)
  22286     { /* SOC_REG_INT_GMAC1_TX_ALL_OCTETS_HI_BCM53400_A0r */
  22287         soc_block_list[61],
  22288         soc_iprocreg,
  22289         1,
  22290         0,
  22291         0x1804a310,
  22292         0,
  22293         0,
  22294         1,
  22295         soc_GMAC0_TX_ALL_OCTETS_HI_BCM53400_A0r_fields,
  22296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22298         -1,
  22299         -1,
  22300     },
  22301 #endif /* chips */
  22302 
  22303 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22304     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22305     { /* SOC_REG_INT_GMAC1_TX_ALL_OCTETS_LOr */
  22306         soc_block_list[61],
  22307         soc_iprocreg,
  22308         1,
  22309         0,
  22310         0x1802330c,
  22311         0,
  22312         0,
  22313         1,
  22314         soc_GMAC0_TX_ALL_OCTETS_LOr_fields,
  22315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22316         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22317         -1,
  22318         -1,
  22319     },
  22320 #endif /* chips */
  22321 
  22322 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22323     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22324     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22325     defined(BCM_56260_B0)
  22326     { /* SOC_REG_INT_GMAC1_TX_ALL_OCTETS_LO_BCM53400_A0r */
  22327         soc_block_list[61],
  22328         soc_iprocreg,
  22329         1,
  22330         0,
  22331         0x1804a30c,
  22332         0,
  22333         0,
  22334         1,
  22335         soc_GMAC0_TX_ALL_OCTETS_LO_BCM53400_A0r_fields,
  22336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22338         -1,
  22339         -1,
  22340     },
  22341 #endif /* chips */
  22342 
  22343 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22344     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22345     { /* SOC_REG_INT_GMAC1_TX_ALL_PKTSr */
  22346         soc_block_list[61],
  22347         soc_iprocreg,
  22348         1,
  22349         0,
  22350         0x18023314,
  22351         0,
  22352         0,
  22353         1,
  22354         soc_GMAC0_TX_ALL_PKTSr_fields,
  22355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22357         -1,
  22358         -1,
  22359     },
  22360 #endif /* chips */
  22361 
  22362 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22363     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22364     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22365     defined(BCM_56260_B0)
  22366     { /* SOC_REG_INT_GMAC1_TX_ALL_PKTS_BCM53400_A0r */
  22367         soc_block_list[61],
  22368         soc_iprocreg,
  22369         1,
  22370         0,
  22371         0x1804a314,
  22372         0,
  22373         0,
  22374         1,
  22375         soc_GMAC0_TX_ALL_PKTS_BCM53400_A0r_fields,
  22376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22377         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22378         -1,
  22379         -1,
  22380     },
  22381 #endif /* chips */
  22382 
  22383 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22384     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22385     { /* SOC_REG_INT_GMAC1_TX_BRDCASTr */
  22386         soc_block_list[61],
  22387         soc_iprocreg,
  22388         1,
  22389         0,
  22390         0x18023318,
  22391         0,
  22392         0,
  22393         1,
  22394         soc_GMAC0_TX_BRDCASTr_fields,
  22395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22396         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22397         -1,
  22398         -1,
  22399     },
  22400 #endif /* chips */
  22401 
  22402 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22403     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22404     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22405     defined(BCM_56260_B0)
  22406     { /* SOC_REG_INT_GMAC1_TX_BRDCAST_BCM53400_A0r */
  22407         soc_block_list[61],
  22408         soc_iprocreg,
  22409         1,
  22410         0,
  22411         0x1804a318,
  22412         0,
  22413         0,
  22414         1,
  22415         soc_GMAC0_TX_BRDCAST_BCM53400_A0r_fields,
  22416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22418         -1,
  22419         -1,
  22420     },
  22421 #endif /* chips */
  22422 
  22423 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22424     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22425     { /* SOC_REG_INT_GMAC1_TX_COLr */
  22426         soc_block_list[61],
  22427         soc_iprocreg,
  22428         1,
  22429         0,
  22430         0x18023358,
  22431         0,
  22432         0,
  22433         1,
  22434         soc_GMAC0_TX_COLr_fields,
  22435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22436         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22437         -1,
  22438         -1,
  22439     },
  22440 #endif /* chips */
  22441 
  22442 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22443     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22444     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22445     defined(BCM_56260_B0)
  22446     { /* SOC_REG_INT_GMAC1_TX_COL_BCM53400_A0r */
  22447         soc_block_list[61],
  22448         soc_iprocreg,
  22449         1,
  22450         0,
  22451         0x1804a358,
  22452         0,
  22453         0,
  22454         1,
  22455         soc_GMAC0_TX_COL_BCM53400_A0r_fields,
  22456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22457         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22458         -1,
  22459         -1,
  22460     },
  22461 #endif /* chips */
  22462 
  22463 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22464     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22465     { /* SOC_REG_INT_GMAC1_TX_CRSr */
  22466         soc_block_list[61],
  22467         soc_iprocreg,
  22468         1,
  22469         0,
  22470         0x18023370,
  22471         0,
  22472         0,
  22473         1,
  22474         soc_GMAC0_TX_CRSr_fields,
  22475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22477         -1,
  22478         -1,
  22479     },
  22480 #endif /* chips */
  22481 
  22482 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22483     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22484     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22485     defined(BCM_56260_B0)
  22486     { /* SOC_REG_INT_GMAC1_TX_CRS_BCM53400_A0r */
  22487         soc_block_list[61],
  22488         soc_iprocreg,
  22489         1,
  22490         0,
  22491         0x1804a370,
  22492         0,
  22493         0,
  22494         1,
  22495         soc_GMAC0_TX_CRS_BCM53400_A0r_fields,
  22496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22498         -1,
  22499         -1,
  22500     },
  22501 #endif /* chips */
  22502 
  22503 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22504     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22505     { /* SOC_REG_INT_GMAC1_TX_DEFr */
  22506         soc_block_list[61],
  22507         soc_iprocreg,
  22508         1,
  22509         0,
  22510         0x1802336c,
  22511         0,
  22512         0,
  22513         1,
  22514         soc_GMAC0_TX_DEFr_fields,
  22515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22516         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22517         -1,
  22518         -1,
  22519     },
  22520 #endif /* chips */
  22521 
  22522 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22523     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22524     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22525     defined(BCM_56260_B0)
  22526     { /* SOC_REG_INT_GMAC1_TX_DEF_BCM53400_A0r */
  22527         soc_block_list[61],
  22528         soc_iprocreg,
  22529         1,
  22530         0,
  22531         0x1804a36c,
  22532         0,
  22533         0,
  22534         1,
  22535         soc_GMAC0_TX_DEF_BCM53400_A0r_fields,
  22536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22538         -1,
  22539         -1,
  22540     },
  22541 #endif /* chips */
  22542 
  22543 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22544     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22545     { /* SOC_REG_INT_GMAC1_TX_EX_COLr */
  22546         soc_block_list[61],
  22547         soc_iprocreg,
  22548         1,
  22549         0,
  22550         0x18023364,
  22551         0,
  22552         0,
  22553         1,
  22554         soc_GMAC0_TX_EX_COLr_fields,
  22555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22557         -1,
  22558         -1,
  22559     },
  22560 #endif /* chips */
  22561 
  22562 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22563     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22564     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22565     defined(BCM_56260_B0)
  22566     { /* SOC_REG_INT_GMAC1_TX_EX_COL_BCM53400_A0r */
  22567         soc_block_list[61],
  22568         soc_iprocreg,
  22569         1,
  22570         0,
  22571         0x1804a364,
  22572         0,
  22573         0,
  22574         1,
  22575         soc_GMAC0_TX_EX_COL_BCM53400_A0r_fields,
  22576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22578         -1,
  22579         -1,
  22580     },
  22581 #endif /* chips */
  22582 
  22583 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22584     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22585     { /* SOC_REG_INT_GMAC1_TX_FRAGr */
  22586         soc_block_list[61],
  22587         soc_iprocreg,
  22588         1,
  22589         0,
  22590         0x18023350,
  22591         0,
  22592         0,
  22593         1,
  22594         soc_GMAC0_TX_FRAGr_fields,
  22595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22597         -1,
  22598         -1,
  22599     },
  22600 #endif /* chips */
  22601 
  22602 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22603     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22604     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22605     defined(BCM_56260_B0)
  22606     { /* SOC_REG_INT_GMAC1_TX_FRAG_BCM53400_A0r */
  22607         soc_block_list[61],
  22608         soc_iprocreg,
  22609         1,
  22610         0,
  22611         0x1804a350,
  22612         0,
  22613         0,
  22614         1,
  22615         soc_GMAC0_TX_FRAG_BCM53400_A0r_fields,
  22616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22618         -1,
  22619         -1,
  22620     },
  22621 #endif /* chips */
  22622 
  22623 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22624     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22625     { /* SOC_REG_INT_GMAC1_TX_GD_OCTETS_HIr */
  22626         soc_block_list[61],
  22627         soc_iprocreg,
  22628         1,
  22629         0,
  22630         0x18023304,
  22631         0,
  22632         0,
  22633         1,
  22634         soc_GMAC0_TX_GD_OCTETS_HIr_fields,
  22635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22637         -1,
  22638         -1,
  22639     },
  22640 #endif /* chips */
  22641 
  22642 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22643     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22644     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22645     defined(BCM_56260_B0)
  22646     { /* SOC_REG_INT_GMAC1_TX_GD_OCTETS_HI_BCM53400_A0r */
  22647         soc_block_list[61],
  22648         soc_iprocreg,
  22649         1,
  22650         0,
  22651         0x1804a304,
  22652         0,
  22653         0,
  22654         1,
  22655         soc_GMAC0_TX_GD_OCTETS_HI_BCM53400_A0r_fields,
  22656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22657         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22658         -1,
  22659         -1,
  22660     },
  22661 #endif /* chips */
  22662 
  22663 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22664     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22665     { /* SOC_REG_INT_GMAC1_TX_GD_OCTETS_LOr */
  22666         soc_block_list[61],
  22667         soc_iprocreg,
  22668         1,
  22669         0,
  22670         0x18023300,
  22671         0,
  22672         0,
  22673         1,
  22674         soc_GMAC0_TX_GD_OCTETS_LOr_fields,
  22675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22676         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22677         -1,
  22678         -1,
  22679     },
  22680 #endif /* chips */
  22681 
  22682 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22683     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22684     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22685     defined(BCM_56260_B0)
  22686     { /* SOC_REG_INT_GMAC1_TX_GD_OCTETS_LO_BCM53400_A0r */
  22687         soc_block_list[61],
  22688         soc_iprocreg,
  22689         1,
  22690         0,
  22691         0x1804a300,
  22692         0,
  22693         0,
  22694         1,
  22695         soc_GMAC0_TX_GD_OCTETS_LO_BCM53400_A0r_fields,
  22696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22698         -1,
  22699         -1,
  22700     },
  22701 #endif /* chips */
  22702 
  22703 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22704     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22705     { /* SOC_REG_INT_GMAC1_TX_GD_PKTSr */
  22706         soc_block_list[61],
  22707         soc_iprocreg,
  22708         1,
  22709         0,
  22710         0x18023308,
  22711         0,
  22712         0,
  22713         1,
  22714         soc_GMAC0_TX_GD_PKTSr_fields,
  22715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22716         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22717         -1,
  22718         -1,
  22719     },
  22720 #endif /* chips */
  22721 
  22722 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22723     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22724     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22725     defined(BCM_56260_B0)
  22726     { /* SOC_REG_INT_GMAC1_TX_GD_PKTS_BCM53400_A0r */
  22727         soc_block_list[61],
  22728         soc_iprocreg,
  22729         1,
  22730         0,
  22731         0x1804a308,
  22732         0,
  22733         0,
  22734         1,
  22735         soc_GMAC0_TX_GD_PKTS_BCM53400_A0r_fields,
  22736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22738         -1,
  22739         -1,
  22740     },
  22741 #endif /* chips */
  22742 
  22743 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22744     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22745     { /* SOC_REG_INT_GMAC1_TX_JABr */
  22746         soc_block_list[61],
  22747         soc_iprocreg,
  22748         1,
  22749         0,
  22750         0x18023348,
  22751         0,
  22752         0,
  22753         1,
  22754         soc_GMAC0_TX_JABr_fields,
  22755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22757         -1,
  22758         -1,
  22759     },
  22760 #endif /* chips */
  22761 
  22762 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22763     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22764     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22765     defined(BCM_56260_B0)
  22766     { /* SOC_REG_INT_GMAC1_TX_JAB_BCM53400_A0r */
  22767         soc_block_list[61],
  22768         soc_iprocreg,
  22769         1,
  22770         0,
  22771         0x1804a348,
  22772         0,
  22773         0,
  22774         1,
  22775         soc_GMAC0_TX_JAB_BCM53400_A0r_fields,
  22776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22778         -1,
  22779         -1,
  22780     },
  22781 #endif /* chips */
  22782 
  22783 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22784     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22785     { /* SOC_REG_INT_GMAC1_TX_LATEr */
  22786         soc_block_list[61],
  22787         soc_iprocreg,
  22788         1,
  22789         0,
  22790         0x18023368,
  22791         0,
  22792         0,
  22793         1,
  22794         soc_GMAC0_TX_LATEr_fields,
  22795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22797         -1,
  22798         -1,
  22799     },
  22800 #endif /* chips */
  22801 
  22802 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22803     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22804     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22805     defined(BCM_56260_B0)
  22806     { /* SOC_REG_INT_GMAC1_TX_LATE_BCM53400_A0r */
  22807         soc_block_list[61],
  22808         soc_iprocreg,
  22809         1,
  22810         0,
  22811         0x1804a368,
  22812         0,
  22813         0,
  22814         1,
  22815         soc_GMAC0_TX_LATE_BCM53400_A0r_fields,
  22816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22817         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22818         -1,
  22819         -1,
  22820     },
  22821 #endif /* chips */
  22822 
  22823 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22824     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22825     { /* SOC_REG_INT_GMAC1_TX_MULTr */
  22826         soc_block_list[61],
  22827         soc_iprocreg,
  22828         1,
  22829         0,
  22830         0x1802331c,
  22831         0,
  22832         0,
  22833         1,
  22834         soc_GMAC0_TX_MULTr_fields,
  22835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22837         -1,
  22838         -1,
  22839     },
  22840 #endif /* chips */
  22841 
  22842 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22843     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22844     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22845     defined(BCM_56260_B0)
  22846     { /* SOC_REG_INT_GMAC1_TX_MULT_BCM53400_A0r */
  22847         soc_block_list[61],
  22848         soc_iprocreg,
  22849         1,
  22850         0,
  22851         0x1804a31c,
  22852         0,
  22853         0,
  22854         1,
  22855         soc_GMAC0_TX_MULT_BCM53400_A0r_fields,
  22856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22858         -1,
  22859         -1,
  22860     },
  22861 #endif /* chips */
  22862 
  22863 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22864     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22865     { /* SOC_REG_INT_GMAC1_TX_M_COLr */
  22866         soc_block_list[61],
  22867         soc_iprocreg,
  22868         1,
  22869         0,
  22870         0x18023360,
  22871         0,
  22872         0,
  22873         1,
  22874         soc_GMAC0_TX_M_COLr_fields,
  22875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22877         -1,
  22878         -1,
  22879     },
  22880 #endif /* chips */
  22881 
  22882 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22883     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22884     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22885     defined(BCM_56260_B0)
  22886     { /* SOC_REG_INT_GMAC1_TX_M_COL_BCM53400_A0r */
  22887         soc_block_list[61],
  22888         soc_iprocreg,
  22889         1,
  22890         0,
  22891         0x1804a360,
  22892         0,
  22893         0,
  22894         1,
  22895         soc_GMAC0_TX_M_COL_BCM53400_A0r_fields,
  22896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22898         -1,
  22899         -1,
  22900     },
  22901 #endif /* chips */
  22902 
  22903 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22904     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22905     { /* SOC_REG_INT_GMAC1_TX_OVERr */
  22906         soc_block_list[61],
  22907         soc_iprocreg,
  22908         1,
  22909         0,
  22910         0x1802334c,
  22911         0,
  22912         0,
  22913         1,
  22914         soc_GMAC0_TX_OVERr_fields,
  22915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22916         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22917         -1,
  22918         -1,
  22919     },
  22920 #endif /* chips */
  22921 
  22922 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22923     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22924     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22925     defined(BCM_56260_B0)
  22926     { /* SOC_REG_INT_GMAC1_TX_OVER_BCM53400_A0r */
  22927         soc_block_list[61],
  22928         soc_iprocreg,
  22929         1,
  22930         0,
  22931         0x1804a34c,
  22932         0,
  22933         0,
  22934         1,
  22935         soc_GMAC0_TX_OVER_BCM53400_A0r_fields,
  22936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22937         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22938         -1,
  22939         -1,
  22940     },
  22941 #endif /* chips */
  22942 
  22943 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22944     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22945     { /* SOC_REG_INT_GMAC1_TX_PAUSr */
  22946         soc_block_list[61],
  22947         soc_iprocreg,
  22948         1,
  22949         0,
  22950         0x18023374,
  22951         0,
  22952         0,
  22953         1,
  22954         soc_GMAC0_TX_PAUSr_fields,
  22955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22957         -1,
  22958         -1,
  22959     },
  22960 #endif /* chips */
  22961 
  22962 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22963     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22964     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22965     defined(BCM_56260_B0)
  22966     { /* SOC_REG_INT_GMAC1_TX_PAUS_BCM53400_A0r */
  22967         soc_block_list[61],
  22968         soc_iprocreg,
  22969         1,
  22970         0,
  22971         0x1804a374,
  22972         0,
  22973         0,
  22974         1,
  22975         soc_GMAC0_TX_PAUS_BCM53400_A0r_fields,
  22976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22978         -1,
  22979         -1,
  22980     },
  22981 #endif /* chips */
  22982 
  22983 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  22984     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  22985     { /* SOC_REG_INT_GMAC1_TX_UNDERRUNr */
  22986         soc_block_list[61],
  22987         soc_iprocreg,
  22988         1,
  22989         0,
  22990         0x18023354,
  22991         0,
  22992         0,
  22993         1,
  22994         soc_GMAC0_TX_UNDERRUNr_fields,
  22995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22997         -1,
  22998         -1,
  22999     },
  23000 #endif /* chips */
  23001 
  23002 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23003     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23004     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23005     defined(BCM_56260_B0)
  23006     { /* SOC_REG_INT_GMAC1_TX_UNDERRUN_BCM53400_A0r */
  23007         soc_block_list[61],
  23008         soc_iprocreg,
  23009         1,
  23010         0,
  23011         0x1804a354,
  23012         0,
  23013         0,
  23014         1,
  23015         soc_GMAC0_TX_UNDERRUN_BCM53400_A0r_fields,
  23016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23018         -1,
  23019         -1,
  23020     },
  23021 #endif /* chips */
  23022 
  23023 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23024     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23025     { /* SOC_REG_INT_GMAC1_XMTADDR_HIGH_0r */
  23026         soc_block_list[61],
  23027         soc_iprocreg,
  23028         1,
  23029         0,
  23030         0x1802320c,
  23031         0,
  23032         0,
  23033         1,
  23034         soc_GMAC0_XMTADDR_HIGH_0r_fields,
  23035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23037         -1,
  23038         -1,
  23039     },
  23040 #endif /* chips */
  23041 
  23042 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23043     { /* SOC_REG_INT_GMAC1_XMTADDR_HIGH_1r */
  23044         soc_block_list[61],
  23045         soc_iprocreg,
  23046         1,
  23047         0,
  23048         0x1802324c,
  23049         0,
  23050         0,
  23051         1,
  23052         soc_GMAC0_XMTADDR_HIGH_0r_fields,
  23053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23054         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23055         -1,
  23056         -1,
  23057     },
  23058 #endif /* chips */
  23059 
  23060 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23061     { /* SOC_REG_INT_GMAC1_XMTADDR_HIGH_2r */
  23062         soc_block_list[61],
  23063         soc_iprocreg,
  23064         1,
  23065         0,
  23066         0x1802328c,
  23067         0,
  23068         0,
  23069         1,
  23070         soc_GMAC0_XMTADDR_HIGH_0r_fields,
  23071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23072         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23073         -1,
  23074         -1,
  23075     },
  23076 #endif /* chips */
  23077 
  23078 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23079     { /* SOC_REG_INT_GMAC1_XMTADDR_HIGH_3r */
  23080         soc_block_list[61],
  23081         soc_iprocreg,
  23082         1,
  23083         0,
  23084         0x180232cc,
  23085         0,
  23086         0,
  23087         1,
  23088         soc_GMAC0_XMTADDR_HIGH_0r_fields,
  23089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23090         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23091         -1,
  23092         -1,
  23093     },
  23094 #endif /* chips */
  23095 
  23096 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23097     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23098     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23099     defined(BCM_56260_B0)
  23100     { /* SOC_REG_INT_GMAC1_XMTADDR_HIGH_0_BCM53400_A0r */
  23101         soc_block_list[61],
  23102         soc_iprocreg,
  23103         1,
  23104         0,
  23105         0x1804a20c,
  23106         0,
  23107         0,
  23108         1,
  23109         soc_GMAC0_XMTADDR_HIGH_0_BCM53400_A0r_fields,
  23110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23111         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23112         -1,
  23113         -1,
  23114     },
  23115 #endif /* chips */
  23116 
  23117 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23118     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23119     { /* SOC_REG_INT_GMAC1_XMTADDR_LOW_0r */
  23120         soc_block_list[61],
  23121         soc_iprocreg,
  23122         1,
  23123         0,
  23124         0x18023208,
  23125         0,
  23126         0,
  23127         2,
  23128         soc_GMAC0_XMTADDR_LOW_0r_fields,
  23129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23130         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23131         -1,
  23132         -1,
  23133     },
  23134 #endif /* chips */
  23135 
  23136 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23137     { /* SOC_REG_INT_GMAC1_XMTADDR_LOW_1r */
  23138         soc_block_list[61],
  23139         soc_iprocreg,
  23140         1,
  23141         0,
  23142         0x18023248,
  23143         0,
  23144         0,
  23145         2,
  23146         soc_GMAC0_XMTADDR_LOW_0r_fields,
  23147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23149         -1,
  23150         -1,
  23151     },
  23152 #endif /* chips */
  23153 
  23154 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23155     { /* SOC_REG_INT_GMAC1_XMTADDR_LOW_2r */
  23156         soc_block_list[61],
  23157         soc_iprocreg,
  23158         1,
  23159         0,
  23160         0x18023288,
  23161         0,
  23162         0,
  23163         2,
  23164         soc_GMAC0_XMTADDR_LOW_0r_fields,
  23165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23166         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23167         -1,
  23168         -1,
  23169     },
  23170 #endif /* chips */
  23171 
  23172 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23173     { /* SOC_REG_INT_GMAC1_XMTADDR_LOW_3r */
  23174         soc_block_list[61],
  23175         soc_iprocreg,
  23176         1,
  23177         0,
  23178         0x180232c8,
  23179         0,
  23180         0,
  23181         2,
  23182         soc_GMAC0_XMTADDR_LOW_0r_fields,
  23183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23184         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23185         -1,
  23186         -1,
  23187     },
  23188 #endif /* chips */
  23189 
  23190 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23191     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23192     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23193     defined(BCM_56260_B0)
  23194     { /* SOC_REG_INT_GMAC1_XMTADDR_LOW_0_BCM53400_A0r */
  23195         soc_block_list[61],
  23196         soc_iprocreg,
  23197         1,
  23198         0,
  23199         0x1804a208,
  23200         0,
  23201         0,
  23202         2,
  23203         soc_GMAC0_XMTADDR_LOW_0_BCM53400_A0r_fields,
  23204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23205         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23206         -1,
  23207         -1,
  23208     },
  23209 #endif /* chips */
  23210 
  23211 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23212     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23213     { /* SOC_REG_INT_GMAC1_XMTCONTROL_0r */
  23214         soc_block_list[61],
  23215         soc_iprocreg,
  23216         1,
  23217         0,
  23218         0x18023200,
  23219         0,
  23220         0,
  23221         11,
  23222         soc_GMAC0_XMTCONTROL_0r_fields,
  23223         SOC_RESET_VAL_DEC(0x00040000, 0x00000000)
  23224         SOC_RESET_MASK_DEC(0x03ff28e7, 0x00000000)
  23225         -1,
  23226         -1,
  23227     },
  23228 #endif /* chips */
  23229 
  23230 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23231     { /* SOC_REG_INT_GMAC1_XMTCONTROL_1r */
  23232         soc_block_list[61],
  23233         soc_iprocreg,
  23234         1,
  23235         0,
  23236         0x18023240,
  23237         0,
  23238         0,
  23239         10,
  23240         soc_GMAC0_XMTCONTROL_1r_fields,
  23241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23242         SOC_RESET_MASK_DEC(0x03ff28e3, 0x00000000)
  23243         -1,
  23244         -1,
  23245     },
  23246 #endif /* chips */
  23247 
  23248 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23249     { /* SOC_REG_INT_GMAC1_XMTCONTROL_2r */
  23250         soc_block_list[61],
  23251         soc_iprocreg,
  23252         1,
  23253         0,
  23254         0x18023280,
  23255         0,
  23256         0,
  23257         10,
  23258         soc_GMAC0_XMTCONTROL_1r_fields,
  23259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23260         SOC_RESET_MASK_DEC(0x03ff28e3, 0x00000000)
  23261         -1,
  23262         -1,
  23263     },
  23264 #endif /* chips */
  23265 
  23266 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23267     { /* SOC_REG_INT_GMAC1_XMTCONTROL_3r */
  23268         soc_block_list[61],
  23269         soc_iprocreg,
  23270         1,
  23271         0,
  23272         0x180232c0,
  23273         0,
  23274         0,
  23275         10,
  23276         soc_GMAC0_XMTCONTROL_1r_fields,
  23277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23278         SOC_RESET_MASK_DEC(0x03ff28e3, 0x00000000)
  23279         -1,
  23280         -1,
  23281     },
  23282 #endif /* chips */
  23283 
  23284 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23285     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23286     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23287     defined(BCM_56260_B0)
  23288     { /* SOC_REG_INT_GMAC1_XMTCONTROL_0_BCM53400_A0r */
  23289         soc_block_list[61],
  23290         soc_iprocreg,
  23291         1,
  23292         0,
  23293         0x1804a200,
  23294         0,
  23295         0,
  23296         11,
  23297         soc_GMAC0_XMTCONTROL_0_BCM53400_A0r_fields,
  23298         SOC_RESET_VAL_DEC(0x00040000, 0x00000000)
  23299         SOC_RESET_MASK_DEC(0x03ff28e7, 0x00000000)
  23300         -1,
  23301         -1,
  23302     },
  23303 #endif /* chips */
  23304 
  23305 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23306     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23307     { /* SOC_REG_INT_GMAC1_XMTPTR_0r */
  23308         soc_block_list[61],
  23309         soc_iprocreg,
  23310         1,
  23311         0,
  23312         0x18023204,
  23313         0,
  23314         0,
  23315         1,
  23316         soc_GMAC0_XMTPTR_0r_fields,
  23317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23318         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  23319         -1,
  23320         -1,
  23321     },
  23322 #endif /* chips */
  23323 
  23324 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23325     { /* SOC_REG_INT_GMAC1_XMTPTR_1r */
  23326         soc_block_list[61],
  23327         soc_iprocreg,
  23328         1,
  23329         0,
  23330         0x18023244,
  23331         0,
  23332         0,
  23333         1,
  23334         soc_GMAC0_XMTPTR_0r_fields,
  23335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23336         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  23337         -1,
  23338         -1,
  23339     },
  23340 #endif /* chips */
  23341 
  23342 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23343     { /* SOC_REG_INT_GMAC1_XMTPTR_2r */
  23344         soc_block_list[61],
  23345         soc_iprocreg,
  23346         1,
  23347         0,
  23348         0x18023284,
  23349         0,
  23350         0,
  23351         1,
  23352         soc_GMAC0_XMTPTR_0r_fields,
  23353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23354         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  23355         -1,
  23356         -1,
  23357     },
  23358 #endif /* chips */
  23359 
  23360 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23361     { /* SOC_REG_INT_GMAC1_XMTPTR_3r */
  23362         soc_block_list[61],
  23363         soc_iprocreg,
  23364         1,
  23365         0,
  23366         0x180232c4,
  23367         0,
  23368         0,
  23369         1,
  23370         soc_GMAC0_XMTPTR_0r_fields,
  23371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23372         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  23373         -1,
  23374         -1,
  23375     },
  23376 #endif /* chips */
  23377 
  23378 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23379     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23380     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23381     defined(BCM_56260_B0)
  23382     { /* SOC_REG_INT_GMAC1_XMTPTR_0_BCM53400_A0r */
  23383         soc_block_list[61],
  23384         soc_iprocreg,
  23385         1,
  23386         0,
  23387         0x1804a204,
  23388         0,
  23389         0,
  23390         1,
  23391         soc_GMAC0_XMTPTR_0_BCM53400_A0r_fields,
  23392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23393         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  23394         -1,
  23395         -1,
  23396     },
  23397 #endif /* chips */
  23398 
  23399 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23400     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23401     { /* SOC_REG_INT_GMAC1_XMTSTATUS0_0r */
  23402         soc_block_list[61],
  23403         soc_iprocreg,
  23404         1,
  23405         0,
  23406         0x18023210,
  23407         SOC_REG_FLAG_RO,
  23408         0,
  23409         2,
  23410         soc_GMAC0_XMTSTATUS0_0r_fields,
  23411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23412         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23413         -1,
  23414         -1,
  23415     },
  23416 #endif /* chips */
  23417 
  23418 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23419     { /* SOC_REG_INT_GMAC1_XMTSTATUS0_1r */
  23420         soc_block_list[61],
  23421         soc_iprocreg,
  23422         1,
  23423         0,
  23424         0x18023250,
  23425         SOC_REG_FLAG_RO,
  23426         0,
  23427         2,
  23428         soc_GMAC0_XMTSTATUS0_0r_fields,
  23429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23430         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23431         -1,
  23432         -1,
  23433     },
  23434 #endif /* chips */
  23435 
  23436 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23437     { /* SOC_REG_INT_GMAC1_XMTSTATUS0_2r */
  23438         soc_block_list[61],
  23439         soc_iprocreg,
  23440         1,
  23441         0,
  23442         0x18023290,
  23443         SOC_REG_FLAG_RO,
  23444         0,
  23445         2,
  23446         soc_GMAC0_XMTSTATUS0_0r_fields,
  23447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23448         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23449         -1,
  23450         -1,
  23451     },
  23452 #endif /* chips */
  23453 
  23454 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23455     { /* SOC_REG_INT_GMAC1_XMTSTATUS0_3r */
  23456         soc_block_list[61],
  23457         soc_iprocreg,
  23458         1,
  23459         0,
  23460         0x180232d0,
  23461         SOC_REG_FLAG_RO,
  23462         0,
  23463         2,
  23464         soc_GMAC0_XMTSTATUS0_0r_fields,
  23465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23466         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23467         -1,
  23468         -1,
  23469     },
  23470 #endif /* chips */
  23471 
  23472 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23473     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23474     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23475     defined(BCM_56260_B0)
  23476     { /* SOC_REG_INT_GMAC1_XMTSTATUS0_0_BCM53400_A0r */
  23477         soc_block_list[61],
  23478         soc_iprocreg,
  23479         1,
  23480         0,
  23481         0x1804a210,
  23482         SOC_REG_FLAG_RO,
  23483         0,
  23484         2,
  23485         soc_GMAC0_XMTSTATUS0_0_BCM53400_A0r_fields,
  23486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23487         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23488         -1,
  23489         -1,
  23490     },
  23491 #endif /* chips */
  23492 
  23493 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23494     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23495     { /* SOC_REG_INT_GMAC1_XMTSTATUS1_0r */
  23496         soc_block_list[61],
  23497         soc_iprocreg,
  23498         1,
  23499         0,
  23500         0x18023214,
  23501         SOC_REG_FLAG_RO,
  23502         0,
  23503         2,
  23504         soc_GMAC0_XMTSTATUS1_0r_fields,
  23505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23506         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23507         -1,
  23508         -1,
  23509     },
  23510 #endif /* chips */
  23511 
  23512 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23513     { /* SOC_REG_INT_GMAC1_XMTSTATUS1_1r */
  23514         soc_block_list[61],
  23515         soc_iprocreg,
  23516         1,
  23517         0,
  23518         0x18023254,
  23519         SOC_REG_FLAG_RO,
  23520         0,
  23521         2,
  23522         soc_GMAC0_XMTSTATUS1_0r_fields,
  23523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23524         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23525         -1,
  23526         -1,
  23527     },
  23528 #endif /* chips */
  23529 
  23530 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23531     { /* SOC_REG_INT_GMAC1_XMTSTATUS1_2r */
  23532         soc_block_list[61],
  23533         soc_iprocreg,
  23534         1,
  23535         0,
  23536         0x18023294,
  23537         SOC_REG_FLAG_RO,
  23538         0,
  23539         2,
  23540         soc_GMAC0_XMTSTATUS1_0r_fields,
  23541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23542         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23543         -1,
  23544         -1,
  23545     },
  23546 #endif /* chips */
  23547 
  23548 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23549     { /* SOC_REG_INT_GMAC1_XMTSTATUS1_3r */
  23550         soc_block_list[61],
  23551         soc_iprocreg,
  23552         1,
  23553         0,
  23554         0x180232d4,
  23555         SOC_REG_FLAG_RO,
  23556         0,
  23557         2,
  23558         soc_GMAC0_XMTSTATUS1_0r_fields,
  23559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23560         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23561         -1,
  23562         -1,
  23563     },
  23564 #endif /* chips */
  23565 
  23566 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23567     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23568     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23569     defined(BCM_56260_B0)
  23570     { /* SOC_REG_INT_GMAC1_XMTSTATUS1_0_BCM53400_A0r */
  23571         soc_block_list[61],
  23572         soc_iprocreg,
  23573         1,
  23574         0,
  23575         0x1804a214,
  23576         SOC_REG_FLAG_RO,
  23577         0,
  23578         2,
  23579         soc_GMAC0_XMTSTATUS1_0_BCM53400_A0r_fields,
  23580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23581         SOC_RESET_MASK_DEC(0xf0001fff, 0x00000000)
  23582         -1,
  23583         -1,
  23584     },
  23585 #endif /* chips */
  23586 
  23587 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  23588     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  23589     { /* SOC_REG_INT_GMACC0r */
  23590         soc_block_list[2],
  23591         soc_portreg,
  23592         1,
  23593         0,
  23594         0x100,
  23595         0,
  23596         0,
  23597         4,
  23598         soc_GMACC0r_fields,
  23599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23600         SOC_RESET_MASK_DEC(0x800003ff, 0x00000000)
  23601         -1,
  23602         -1,
  23603     },
  23604 #endif /* chips */
  23605 
  23606 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  23607     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  23608     { /* SOC_REG_INT_GMACC1r */
  23609         soc_block_list[2],
  23610         soc_portreg,
  23611         1,
  23612         0,
  23613         0x101,
  23614         0,
  23615         0,
  23616         18,
  23617         soc_GMACC1r_fields,
  23618         SOC_RESET_VAL_DEC(0x000a1001, 0x00000000)
  23619         SOC_RESET_MASK_DEC(0x50cf1fff, 0x00000000)
  23620         -1,
  23621         -1,
  23622     },
  23623 #endif /* chips */
  23624 
  23625 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  23626     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  23627     { /* SOC_REG_INT_GMACC2r */
  23628         soc_block_list[2],
  23629         soc_portreg,
  23630         1,
  23631         0,
  23632         0x102,
  23633         0,
  23634         0,
  23635         1,
  23636         soc_GMACC2r_fields,
  23637         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  23638         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  23639         -1,
  23640         -1,
  23641     },
  23642 #endif /* chips */
  23643 
  23644 #if defined(BCM_56800_A0)
  23645     { /* SOC_REG_INT_GMACC0_BCM56800_A0r */
  23646         soc_block_list[9],
  23647         soc_portreg,
  23648         1,
  23649         0,
  23650         0x100,
  23651         0,
  23652         0,
  23653         4,
  23654         soc_GMACC0r_fields,
  23655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23656         SOC_RESET_MASK_DEC(0x800003ff, 0x00000000)
  23657         -1,
  23658         -1,
  23659     },
  23660 #endif /* chips */
  23661 
  23662 #if defined(BCM_56800_A0)
  23663     { /* SOC_REG_INT_GMACC1_BCM56800_A0r */
  23664         soc_block_list[9],
  23665         soc_portreg,
  23666         1,
  23667         0,
  23668         0x101,
  23669         0,
  23670         0,
  23671         18,
  23672         soc_GMACC1r_fields,
  23673         SOC_RESET_VAL_DEC(0x000a1001, 0x00000000)
  23674         SOC_RESET_MASK_DEC(0x50cf1fff, 0x00000000)
  23675         -1,
  23676         -1,
  23677     },
  23678 #endif /* chips */
  23679 
  23680 #if defined(BCM_56800_A0)
  23681     { /* SOC_REG_INT_GMACC2_BCM56800_A0r */
  23682         soc_block_list[9],
  23683         soc_portreg,
  23684         1,
  23685         0,
  23686         0x102,
  23687         0,
  23688         0,
  23689         1,
  23690         soc_GMACC2r_fields,
  23691         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  23692         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  23693         -1,
  23694         -1,
  23695     },
  23696 #endif /* chips */
  23697 
  23698 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  23699     { /* SOC_REG_INT_GMHIGHBANKr */
  23700         soc_block_list[4],
  23701         soc_genreg,
  23702         1,
  23703         0,
  23704         0x7080046,
  23705         0,
  23706         0,
  23707         2,
  23708         soc_GMHIGHBANKr_fields,
  23709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23710         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  23711         -1,
  23712         -1,
  23713     },
  23714 #endif /* chips */
  23715 
  23716 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  23717     { /* SOC_REG_INT_GMHIGHBANK_BCM56640_A0r */
  23718         soc_block_list[4],
  23719         soc_genreg,
  23720         1,
  23721         0,
  23722         0x1e004600,
  23723         0,
  23724         0,
  23725         2,
  23726         soc_GMHIGHBANK_BCM56640_A0r_fields,
  23727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23728         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  23729         -1,
  23730         -1,
  23731     },
  23732 #endif /* chips */
  23733 
  23734 #if defined(BCM_88675_A0)
  23735     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMERr */
  23736         soc_block_list[2],
  23737         soc_portreg,
  23738         1,
  23739         0,
  23740         0x11b00,
  23741         0,
  23742         0,
  23743         1,
  23744         soc_GMII_EEE_DELAY_ENTRY_TIMERr_fields,
  23745         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23746         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23747         -1,
  23748         -1,
  23749     },
  23750 #endif /* chips */
  23751 
  23752 #if defined(BCM_53400_A0)
  23753     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r */
  23754         soc_block_list[9],
  23755         soc_portreg,
  23756         1,
  23757         0,
  23758         0x11b00,
  23759         0,
  23760         0,
  23761         1,
  23762         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r_fields,
  23763         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23764         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23765         -1,
  23766         -1,
  23767     },
  23768 #endif /* chips */
  23769 
  23770 #if defined(BCM_53540_A0)
  23771     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM53540_A0r */
  23772         soc_block_list[2],
  23773         soc_portreg,
  23774         1,
  23775         0,
  23776         0x11b00,
  23777         0,
  23778         0,
  23779         1,
  23780         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r_fields,
  23781         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23782         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23783         -1,
  23784         -1,
  23785     },
  23786 #endif /* chips */
  23787 
  23788 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  23789     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM53570_A0r */
  23790         soc_block_list[2],
  23791         soc_portreg,
  23792         1,
  23793         0,
  23794         0x11b00,
  23795         0,
  23796         0,
  23797         1,
  23798         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r_fields,
  23799         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23801         -1,
  23802         -1,
  23803     },
  23804 #endif /* chips */
  23805 
  23806 #if defined(BCM_56150_A0)
  23807     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM56150_A0r */
  23808         soc_block_list[2],
  23809         soc_portreg,
  23810         1,
  23811         0,
  23812         0x11b00,
  23813         0,
  23814         0,
  23815         1,
  23816         soc_UNIMAC0_GMII_EEE_DELAY_ENTRY_TIMERr_fields,
  23817         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23819         -1,
  23820         -1,
  23821     },
  23822 #endif /* chips */
  23823 
  23824 #if defined(BCM_56160_A0)
  23825     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM56160_A0r */
  23826         soc_block_list[2],
  23827         soc_portreg,
  23828         1,
  23829         0,
  23830         0x11b00,
  23831         0,
  23832         0,
  23833         1,
  23834         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r_fields,
  23835         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23837         -1,
  23838         -1,
  23839     },
  23840 #endif /* chips */
  23841 
  23842 #if defined(BCM_56370_A0)
  23843     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM56370_A0r */
  23844         soc_block_list[9],
  23845         soc_portreg,
  23846         1,
  23847         0,
  23848         0x11b00,
  23849         0,
  23850         0,
  23851         1,
  23852         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r_fields,
  23853         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23854         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23855         -1,
  23856         -1,
  23857         3,
  23858     },
  23859 #endif /* chips */
  23860 
  23861 #if defined(BCM_88375_A0)
  23862     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM88375_A0r */
  23863         soc_block_list[2],
  23864         soc_portreg,
  23865         1,
  23866         0,
  23867         0x11b00,
  23868         0,
  23869         0,
  23870         1,
  23871         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM88375_A0r_fields,
  23872         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23873         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23874         -1,
  23875         -1,
  23876     },
  23877 #endif /* chips */
  23878 
  23879 #if defined(BCM_88375_B0)
  23880     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM88375_B0r */
  23881         soc_block_list[2],
  23882         soc_portreg,
  23883         1,
  23884         0,
  23885         0x11b00,
  23886         0,
  23887         0,
  23888         1,
  23889         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM88375_B0r_fields,
  23890         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23891         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23892         -1,
  23893         -1,
  23894     },
  23895 #endif /* chips */
  23896 
  23897 #if defined(BCM_88470_A0)
  23898     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM88470_A0r */
  23899         soc_block_list[2],
  23900         soc_portreg,
  23901         1,
  23902         0,
  23903         0x11b00,
  23904         0,
  23905         0,
  23906         1,
  23907         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM88470_A0r_fields,
  23908         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23909         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23910         -1,
  23911         -1,
  23912     },
  23913 #endif /* chips */
  23914 
  23915 #if defined(BCM_88470_B0)
  23916     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM88470_B0r */
  23917         soc_block_list[2],
  23918         soc_portreg,
  23919         1,
  23920         0,
  23921         0x11b00,
  23922         0,
  23923         0,
  23924         1,
  23925         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM88470_B0r_fields,
  23926         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23927         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23928         -1,
  23929         -1,
  23930     },
  23931 #endif /* chips */
  23932 
  23933 #if defined(BCM_88675_B0)
  23934     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM88675_B0r */
  23935         soc_block_list[2],
  23936         soc_portreg,
  23937         1,
  23938         0,
  23939         0x11b00,
  23940         0,
  23941         0,
  23942         1,
  23943         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM88675_B0r_fields,
  23944         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23946         -1,
  23947         -1,
  23948     },
  23949 #endif /* chips */
  23950 
  23951 #if defined(BCM_88680_A0)
  23952     { /* SOC_REG_INT_GMII_EEE_DELAY_ENTRY_TIMER_BCM88680_A0r */
  23953         soc_block_list[2],
  23954         soc_portreg,
  23955         1,
  23956         0,
  23957         0x11b00,
  23958         0,
  23959         0,
  23960         1,
  23961         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM88680_A0r_fields,
  23962         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23964         -1,
  23965         -1,
  23966     },
  23967 #endif /* chips */
  23968 
  23969 #if defined(BCM_88675_A0)
  23970     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMERr */
  23971         soc_block_list[2],
  23972         soc_portreg,
  23973         1,
  23974         0,
  23975         0x12100,
  23976         0,
  23977         0,
  23978         1,
  23979         soc_GMII_EEE_WAKE_TIMERr_fields,
  23980         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  23981         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23982         -1,
  23983         -1,
  23984     },
  23985 #endif /* chips */
  23986 
  23987 #if defined(BCM_53400_A0)
  23988     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM53400_A0r */
  23989         soc_block_list[9],
  23990         soc_portreg,
  23991         1,
  23992         0,
  23993         0x12100,
  23994         0,
  23995         0,
  23996         1,
  23997         soc_GMII_EEE_WAKE_TIMER_BCM53400_A0r_fields,
  23998         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  23999         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24000         -1,
  24001         -1,
  24002     },
  24003 #endif /* chips */
  24004 
  24005 #if defined(BCM_53540_A0)
  24006     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM53540_A0r */
  24007         soc_block_list[2],
  24008         soc_portreg,
  24009         1,
  24010         0,
  24011         0x12100,
  24012         0,
  24013         0,
  24014         1,
  24015         soc_GMII_EEE_WAKE_TIMER_BCM53400_A0r_fields,
  24016         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24017         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24018         -1,
  24019         -1,
  24020     },
  24021 #endif /* chips */
  24022 
  24023 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  24024     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM53570_A0r */
  24025         soc_block_list[2],
  24026         soc_portreg,
  24027         1,
  24028         0,
  24029         0x12100,
  24030         0,
  24031         0,
  24032         1,
  24033         soc_GMII_EEE_WAKE_TIMER_BCM53400_A0r_fields,
  24034         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24035         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24036         -1,
  24037         -1,
  24038     },
  24039 #endif /* chips */
  24040 
  24041 #if defined(BCM_56150_A0)
  24042     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM56150_A0r */
  24043         soc_block_list[2],
  24044         soc_portreg,
  24045         1,
  24046         0,
  24047         0x12100,
  24048         0,
  24049         0,
  24050         1,
  24051         soc_UNIMAC0_GMII_EEE_WAKE_TIMERr_fields,
  24052         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24053         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24054         -1,
  24055         -1,
  24056     },
  24057 #endif /* chips */
  24058 
  24059 #if defined(BCM_56160_A0)
  24060     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM56160_A0r */
  24061         soc_block_list[2],
  24062         soc_portreg,
  24063         1,
  24064         0,
  24065         0x12100,
  24066         0,
  24067         0,
  24068         1,
  24069         soc_GMII_EEE_WAKE_TIMER_BCM53400_A0r_fields,
  24070         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24071         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24072         -1,
  24073         -1,
  24074     },
  24075 #endif /* chips */
  24076 
  24077 #if defined(BCM_56370_A0)
  24078     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM56370_A0r */
  24079         soc_block_list[9],
  24080         soc_portreg,
  24081         1,
  24082         0,
  24083         0x12100,
  24084         0,
  24085         0,
  24086         1,
  24087         soc_GMII_EEE_WAKE_TIMER_BCM53400_A0r_fields,
  24088         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24089         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24090         -1,
  24091         -1,
  24092         3,
  24093     },
  24094 #endif /* chips */
  24095 
  24096 #if defined(BCM_88375_A0)
  24097     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM88375_A0r */
  24098         soc_block_list[2],
  24099         soc_portreg,
  24100         1,
  24101         0,
  24102         0x12100,
  24103         0,
  24104         0,
  24105         1,
  24106         soc_GMII_EEE_WAKE_TIMER_BCM88375_A0r_fields,
  24107         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24108         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24109         -1,
  24110         -1,
  24111     },
  24112 #endif /* chips */
  24113 
  24114 #if defined(BCM_88375_B0)
  24115     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM88375_B0r */
  24116         soc_block_list[2],
  24117         soc_portreg,
  24118         1,
  24119         0,
  24120         0x12100,
  24121         0,
  24122         0,
  24123         1,
  24124         soc_GMII_EEE_WAKE_TIMER_BCM88375_B0r_fields,
  24125         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24126         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24127         -1,
  24128         -1,
  24129     },
  24130 #endif /* chips */
  24131 
  24132 #if defined(BCM_88470_A0)
  24133     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM88470_A0r */
  24134         soc_block_list[2],
  24135         soc_portreg,
  24136         1,
  24137         0,
  24138         0x12100,
  24139         0,
  24140         0,
  24141         1,
  24142         soc_GMII_EEE_WAKE_TIMER_BCM88470_A0r_fields,
  24143         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24144         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24145         -1,
  24146         -1,
  24147     },
  24148 #endif /* chips */
  24149 
  24150 #if defined(BCM_88470_B0)
  24151     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM88470_B0r */
  24152         soc_block_list[2],
  24153         soc_portreg,
  24154         1,
  24155         0,
  24156         0x12100,
  24157         0,
  24158         0,
  24159         1,
  24160         soc_GMII_EEE_WAKE_TIMER_BCM88470_B0r_fields,
  24161         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24162         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24163         -1,
  24164         -1,
  24165     },
  24166 #endif /* chips */
  24167 
  24168 #if defined(BCM_88675_B0)
  24169     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM88675_B0r */
  24170         soc_block_list[2],
  24171         soc_portreg,
  24172         1,
  24173         0,
  24174         0x12100,
  24175         0,
  24176         0,
  24177         1,
  24178         soc_GMII_EEE_WAKE_TIMER_BCM88675_B0r_fields,
  24179         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24180         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24181         -1,
  24182         -1,
  24183     },
  24184 #endif /* chips */
  24185 
  24186 #if defined(BCM_88680_A0)
  24187     { /* SOC_REG_INT_GMII_EEE_WAKE_TIMER_BCM88680_A0r */
  24188         soc_block_list[2],
  24189         soc_portreg,
  24190         1,
  24191         0,
  24192         0x12100,
  24193         0,
  24194         0,
  24195         1,
  24196         soc_GMII_EEE_WAKE_TIMER_BCM88680_A0r_fields,
  24197         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24198         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24199         -1,
  24200         -1,
  24201     },
  24202 #endif /* chips */
  24203 
  24204 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  24205     { /* SOC_REG_INT_GMLOWBANKr */
  24206         soc_block_list[4],
  24207         soc_genreg,
  24208         1,
  24209         0,
  24210         0x7080045,
  24211         0,
  24212         0,
  24213         2,
  24214         soc_GMHIGHBANKr_fields,
  24215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24216         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24217         -1,
  24218         -1,
  24219     },
  24220 #endif /* chips */
  24221 
  24222 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  24223     { /* SOC_REG_INT_GMLOWBANK_BCM56640_A0r */
  24224         soc_block_list[4],
  24225         soc_genreg,
  24226         1,
  24227         0,
  24228         0x1e004500,
  24229         0,
  24230         0,
  24231         2,
  24232         soc_GMHIGHBANK_BCM56640_A0r_fields,
  24233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24234         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  24235         -1,
  24236         -1,
  24237     },
  24238 #endif /* chips */
  24239 
  24240 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  24241     { /* SOC_REG_INT_GMMEMWARMUPr */
  24242         soc_block_list[4],
  24243         soc_genreg,
  24244         1,
  24245         0,
  24246         0x7080044,
  24247         0,
  24248         0,
  24249         1,
  24250         soc_GMMEMWARMUPr_fields,
  24251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24252         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  24253         -1,
  24254         -1,
  24255     },
  24256 #endif /* chips */
  24257 
  24258 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  24259     { /* SOC_REG_INT_GMMEMWARMUP_BCM56640_A0r */
  24260         soc_block_list[4],
  24261         soc_genreg,
  24262         1,
  24263         0,
  24264         0x1e004400,
  24265         0,
  24266         0,
  24267         1,
  24268         soc_GMMEMWARMUP_BCM56640_A0r_fields,
  24269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24270         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  24271         -1,
  24272         -1,
  24273     },
  24274 #endif /* chips */
  24275 
  24276 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  24277     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  24278     { /* SOC_REG_INT_GPCSCr */
  24279         soc_block_list[2],
  24280         soc_portreg,
  24281         1,
  24282         0,
  24283         0x103,
  24284         0,
  24285         0,
  24286         2,
  24287         soc_GPCSCr_fields,
  24288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24289         SOC_RESET_MASK_DEC(0x00000006, 0x00000000)
  24290         -1,
  24291         -1,
  24292     },
  24293 #endif /* chips */
  24294 
  24295 #if defined(BCM_56800_A0)
  24296     { /* SOC_REG_INT_GPCSC_BCM56800_A0r */
  24297         soc_block_list[9],
  24298         soc_portreg,
  24299         1,
  24300         0,
  24301         0x103,
  24302         0,
  24303         0,
  24304         2,
  24305         soc_GPCSCr_fields,
  24306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24307         SOC_RESET_MASK_DEC(0x00000006, 0x00000000)
  24308         -1,
  24309         -1,
  24310     },
  24311 #endif /* chips */
  24312 
  24313 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  24314     defined(BCM_56870_A0)
  24315     { /* SOC_REG_INT_GPE_CONTROLr */
  24316         soc_block_list[115],
  24317         soc_genreg,
  24318         1,
  24319         0,
  24320         0x2002b00,
  24321         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24322         SOC_REG_FLAG_CCH,
  24323         1,
  24324         soc_GPE_CONTROLr_fields,
  24325         SOC_RESET_VAL_DEC(0x000012b6, 0x00000000)
  24326         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24327         -1,
  24328         -1,
  24329         3,
  24330     },
  24331 #endif /* chips */
  24332 
  24333 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  24334     defined(BCM_56870_A0)
  24335     { /* SOC_REG_INT_GPE_DEFAULT_NETWORK_SVPr */
  24336         soc_block_list[115],
  24337         soc_genreg,
  24338         1,
  24339         0,
  24340         0x2003500,
  24341         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24342         SOC_REG_FLAG_CCH,
  24343         1,
  24344         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
  24345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24346         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24347         -1,
  24348         -1,
  24349         3,
  24350     },
  24351 #endif /* chips */
  24352 
  24353 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  24354     { /* SOC_REG_INT_GPE_GENEVE_IPV6_CONTROLr */
  24355         soc_block_list[115],
  24356         soc_genreg,
  24357         1,
  24358         0,
  24359         0x2002e00,
  24360         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24361         SOC_REG_FLAG_CCH,
  24362         1,
  24363         soc_GPE_GENEVE_IPV6_CONTROLr_fields,
  24364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24365         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24366         -1,
  24367         -1,
  24368         3,
  24369     },
  24370 #endif /* chips */
  24371 
  24372 #if defined(BCM_56370_A0)
  24373     { /* SOC_REG_INT_GPE_GENEVE_IPV6_CONTROL_BCM56370_A0r */
  24374         soc_block_list[115],
  24375         soc_genreg,
  24376         1,
  24377         0,
  24378         0x2002d00,
  24379         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24380         SOC_REG_FLAG_CCH,
  24381         1,
  24382         soc_GPE_GENEVE_IPV6_CONTROLr_fields,
  24383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24384         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24385         -1,
  24386         -1,
  24387         3,
  24388     },
  24389 #endif /* chips */
  24390 
  24391 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  24392     defined(BCM_56870_A0)
  24393     { /* SOC_REG_INT_GPE_NEXT_PROTOCOLr */
  24394         soc_block_list[115],
  24395         soc_genreg,
  24396         1,
  24397         0,
  24398         0x2000200,
  24399         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  24400         SOC_REG_FLAG_CCH,
  24401         1,
  24402         soc_GPE_NEXT_PROTOCOLr_fields,
  24403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24404         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24405         -1,
  24406         -1,
  24407         3,
  24408     },
  24409 #endif /* chips */
  24410 
  24411 #if defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
  24412     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
  24413     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  24414     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  24415     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
  24416     defined(BCM_56514_A0)
  24417     { /* SOC_REG_INT_GPORT_CNTMAXSIZEr */
  24418         soc_block_list[2],
  24419         soc_genreg,
  24420         1,
  24421         0,
  24422         0x80003,
  24423         0,
  24424         0,
  24425         1,
  24426         soc_GPORT_CNTMAXSIZEr_fields,
  24427         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24428         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24429         -1,
  24430         -1,
  24431     },
  24432 #endif /* chips */
  24433 
  24434 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  24435     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM53314_A0r */
  24436         soc_block_list[2],
  24437         soc_genreg,
  24438         1,
  24439         0,
  24440         0x80003,
  24441         0,
  24442         0,
  24443         1,
  24444         soc_GPORT_CNTMAXSIZE_BCM53314_A0r_fields,
  24445         SOC_RESET_VAL_DEC(0x00002800, 0x00000000)
  24446         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24447         -1,
  24448         -1,
  24449     },
  24450 #endif /* chips */
  24451 
  24452 #if defined(BCM_53400_A0)
  24453     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM53400_A0r */
  24454         soc_block_list[9],
  24455         soc_genreg,
  24456         1,
  24457         0,
  24458         0x2020800,
  24459         0,
  24460         0,
  24461         1,
  24462         soc_CLPORT_CNTMAXSIZEr_fields,
  24463         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24464         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24465         -1,
  24466         -1,
  24467     },
  24468 #endif /* chips */
  24469 
  24470 #if defined(BCM_53540_A0)
  24471     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM53540_A0r */
  24472         soc_block_list[2],
  24473         soc_genreg,
  24474         1,
  24475         0,
  24476         0x2020800,
  24477         0,
  24478         0,
  24479         1,
  24480         soc_CLPORT_CNTMAXSIZEr_fields,
  24481         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24482         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24483         -1,
  24484         -1,
  24485     },
  24486 #endif /* chips */
  24487 
  24488 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  24489     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM53570_A0r */
  24490         soc_block_list[2],
  24491         soc_genreg,
  24492         1,
  24493         0,
  24494         0x2020800,
  24495         0,
  24496         0,
  24497         1,
  24498         soc_CLPORT_CNTMAXSIZEr_fields,
  24499         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24500         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24501         -1,
  24502         -1,
  24503     },
  24504 #endif /* chips */
  24505 
  24506 #if defined(BCM_56150_A0)
  24507     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56150_A0r */
  24508         soc_block_list[2],
  24509         soc_genreg,
  24510         1,
  24511         0,
  24512         0x2020800,
  24513         0,
  24514         0,
  24515         1,
  24516         soc_PORT_CNTMAXSIZE_BCM56640_A0r_fields,
  24517         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24518         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24519         -1,
  24520         -1,
  24521     },
  24522 #endif /* chips */
  24523 
  24524 #if defined(BCM_56160_A0)
  24525     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56160_A0r */
  24526         soc_block_list[2],
  24527         soc_genreg,
  24528         1,
  24529         0,
  24530         0x2020800,
  24531         0,
  24532         0,
  24533         1,
  24534         soc_CLPORT_CNTMAXSIZEr_fields,
  24535         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24536         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24537         -1,
  24538         -1,
  24539     },
  24540 #endif /* chips */
  24541 
  24542 #if defined(BCM_56370_A0)
  24543     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56370_A0r */
  24544         soc_block_list[9],
  24545         soc_genreg,
  24546         1,
  24547         0,
  24548         0x2020800,
  24549         0,
  24550         0,
  24551         1,
  24552         soc_CLPORT_CNTMAXSIZEr_fields,
  24553         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24554         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24555         -1,
  24556         -1,
  24557         3,
  24558     },
  24559 #endif /* chips */
  24560 
  24561 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  24562     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  24563     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56624_A0r */
  24564         soc_block_list[205],
  24565         soc_genreg,
  24566         1,
  24567         0,
  24568         0x80903,
  24569         0,
  24570         0,
  24571         1,
  24572         soc_GPORT_CNTMAXSIZEr_fields,
  24573         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24574         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24575         -1,
  24576         -1,
  24577     },
  24578 #endif /* chips */
  24579 
  24580 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  24581     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  24582     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56634_A0r */
  24583         soc_block_list[207],
  24584         soc_genreg,
  24585         1,
  24586         0,
  24587         0x80903,
  24588         0,
  24589         0,
  24590         1,
  24591         soc_GPORT_CNTMAXSIZEr_fields,
  24592         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24593         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24594         -1,
  24595         -1,
  24596     },
  24597 #endif /* chips */
  24598 
  24599 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  24600     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56685_A0r */
  24601         soc_block_list[209],
  24602         soc_genreg,
  24603         1,
  24604         0,
  24605         0x80903,
  24606         0,
  24607         0,
  24608         1,
  24609         soc_GPORT_CNTMAXSIZEr_fields,
  24610         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24611         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24612         -1,
  24613         -1,
  24614     },
  24615 #endif /* chips */
  24616 
  24617 #if defined(BCM_56800_A0)
  24618     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56800_A0r */
  24619         soc_block_list[9],
  24620         soc_portreg,
  24621         1,
  24622         0,
  24623         0xa03,
  24624         0,
  24625         0,
  24626         1,
  24627         soc_GPORT_CNTMAXSIZEr_fields,
  24628         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24629         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24630         -1,
  24631         -1,
  24632     },
  24633 #endif /* chips */
  24634 
  24635 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  24636     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56820_A0r */
  24637         soc_block_list[206],
  24638         soc_portreg,
  24639         1,
  24640         0,
  24641         0x903,
  24642         0,
  24643         0,
  24644         1,
  24645         soc_GPORT_CNTMAXSIZEr_fields,
  24646         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24647         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24648         -1,
  24649         -1,
  24650     },
  24651 #endif /* chips */
  24652 
  24653 #if defined(BCM_56840_A0)
  24654     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56840_A0r */
  24655         soc_block_list[16],
  24656         soc_portreg,
  24657         1,
  24658         0,
  24659         0x227,
  24660         0,
  24661         0,
  24662         1,
  24663         soc_GPORT_CNTMAXSIZEr_fields,
  24664         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24665         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24666         -1,
  24667         -1,
  24668     },
  24669 #endif /* chips */
  24670 
  24671 #if defined(BCM_56840_B0)
  24672     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM56840_B0r */
  24673         soc_block_list[16],
  24674         soc_portreg,
  24675         1,
  24676         0,
  24677         0x227,
  24678         0,
  24679         0,
  24680         1,
  24681         soc_GPORT_CNTMAXSIZEr_fields,
  24682         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24683         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24684         -1,
  24685         -1,
  24686     },
  24687 #endif /* chips */
  24688 
  24689 #if defined(BCM_88375_A0)
  24690     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM88375_A0r */
  24691         soc_block_list[2],
  24692         soc_genreg,
  24693         1,
  24694         0,
  24695         0x2020800,
  24696         0,
  24697         0,
  24698         1,
  24699         soc_GPORT_CNTMAXSIZE_BCM88375_A0r_fields,
  24700         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24701         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24702         -1,
  24703         -1,
  24704     },
  24705 #endif /* chips */
  24706 
  24707 #if defined(BCM_88375_B0)
  24708     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM88375_B0r */
  24709         soc_block_list[2],
  24710         soc_genreg,
  24711         1,
  24712         0,
  24713         0x2020800,
  24714         0,
  24715         0,
  24716         1,
  24717         soc_GPORT_CNTMAXSIZE_BCM88375_B0r_fields,
  24718         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24719         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24720         -1,
  24721         -1,
  24722     },
  24723 #endif /* chips */
  24724 
  24725 #if defined(BCM_88470_A0)
  24726     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM88470_A0r */
  24727         soc_block_list[2],
  24728         soc_genreg,
  24729         1,
  24730         0,
  24731         0x2020800,
  24732         0,
  24733         0,
  24734         1,
  24735         soc_GPORT_CNTMAXSIZE_BCM88470_A0r_fields,
  24736         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24737         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24738         -1,
  24739         -1,
  24740     },
  24741 #endif /* chips */
  24742 
  24743 #if defined(BCM_88470_B0)
  24744     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM88470_B0r */
  24745         soc_block_list[2],
  24746         soc_genreg,
  24747         1,
  24748         0,
  24749         0x2020800,
  24750         0,
  24751         0,
  24752         1,
  24753         soc_GPORT_CNTMAXSIZE_BCM88470_B0r_fields,
  24754         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24755         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24756         -1,
  24757         -1,
  24758     },
  24759 #endif /* chips */
  24760 
  24761 #if defined(BCM_88675_A0)
  24762     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM88675_A0r */
  24763         soc_block_list[2],
  24764         soc_genreg,
  24765         1,
  24766         0,
  24767         0x2020800,
  24768         0,
  24769         0,
  24770         1,
  24771         soc_GPORT_CNTMAXSIZE_BCM88675_A0r_fields,
  24772         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24773         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24774         -1,
  24775         -1,
  24776     },
  24777 #endif /* chips */
  24778 
  24779 #if defined(BCM_88675_B0)
  24780     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM88675_B0r */
  24781         soc_block_list[2],
  24782         soc_genreg,
  24783         1,
  24784         0,
  24785         0x2020800,
  24786         0,
  24787         0,
  24788         1,
  24789         soc_GPORT_CNTMAXSIZE_BCM88675_B0r_fields,
  24790         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24791         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24792         -1,
  24793         -1,
  24794     },
  24795 #endif /* chips */
  24796 
  24797 #if defined(BCM_88680_A0)
  24798     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM88680_A0r */
  24799         soc_block_list[2],
  24800         soc_genreg,
  24801         1,
  24802         0,
  24803         0x2020800,
  24804         0,
  24805         0,
  24806         1,
  24807         soc_GPORT_CNTMAXSIZE_BCM88680_A0r_fields,
  24808         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24809         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24810         -1,
  24811         -1,
  24812     },
  24813 #endif /* chips */
  24814 
  24815 #if defined(BCM_88732_A0)
  24816     { /* SOC_REG_INT_GPORT_CNTMAXSIZE_BCM88732_A0r */
  24817         soc_block_list[16],
  24818         soc_portreg,
  24819         1,
  24820         0,
  24821         0x227,
  24822         0,
  24823         0,
  24824         1,
  24825         soc_GPORT_CNTMAXSIZEr_fields,
  24826         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24827         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24828         -1,
  24829         -1,
  24830     },
  24831 #endif /* chips */
  24832 
  24833 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \
  24834     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  24835     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  24836     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
  24837     defined(BCM_56514_A0)
  24838     { /* SOC_REG_INT_GPORT_CONFIGr */
  24839         soc_block_list[2],
  24840         soc_genreg,
  24841         1,
  24842         0,
  24843         0x80000,
  24844         0,
  24845         0,
  24846         2,
  24847         soc_GPORT_CONFIGr_fields,
  24848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24849         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24850         -1,
  24851         -1,
  24852     },
  24853 #endif /* chips */
  24854 
  24855 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  24856     { /* SOC_REG_INT_GPORT_CONFIG_BCM53314_A0r */
  24857         soc_block_list[2],
  24858         soc_genreg,
  24859         1,
  24860         0,
  24861         0x80000,
  24862         0,
  24863         0,
  24864         11,
  24865         soc_GPORT_CONFIG_BCM53314_A0r_fields,
  24866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24867         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24868         -1,
  24869         -1,
  24870     },
  24871 #endif /* chips */
  24872 
  24873 #if defined(BCM_53400_A0)
  24874     { /* SOC_REG_INT_GPORT_CONFIG_BCM53400_A0r */
  24875         soc_block_list[9],
  24876         soc_genreg,
  24877         1,
  24878         0,
  24879         0x2020000,
  24880         0,
  24881         0,
  24882         2,
  24883         soc_GPORT_CONFIG_BCM53400_A0r_fields,
  24884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24885         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24886         -1,
  24887         -1,
  24888     },
  24889 #endif /* chips */
  24890 
  24891 #if defined(BCM_53540_A0)
  24892     { /* SOC_REG_INT_GPORT_CONFIG_BCM53540_A0r */
  24893         soc_block_list[2],
  24894         soc_genreg,
  24895         1,
  24896         0,
  24897         0x2020000,
  24898         0,
  24899         0,
  24900         2,
  24901         soc_GPORT_CONFIG_BCM53400_A0r_fields,
  24902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24903         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24904         -1,
  24905         -1,
  24906     },
  24907 #endif /* chips */
  24908 
  24909 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  24910     { /* SOC_REG_INT_GPORT_CONFIG_BCM53570_A0r */
  24911         soc_block_list[2],
  24912         soc_genreg,
  24913         1,
  24914         0,
  24915         0x2020000,
  24916         0,
  24917         0,
  24918         2,
  24919         soc_GPORT_CONFIG_BCM53400_A0r_fields,
  24920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24921         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24922         -1,
  24923         -1,
  24924     },
  24925 #endif /* chips */
  24926 
  24927 #if defined(BCM_56150_A0)
  24928     { /* SOC_REG_INT_GPORT_CONFIG_BCM56150_A0r */
  24929         soc_block_list[2],
  24930         soc_genreg,
  24931         1,
  24932         0,
  24933         0x2020000,
  24934         0,
  24935         0,
  24936         2,
  24937         soc_GPORT_CONFIG_BCM56150_A0r_fields,
  24938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24939         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24940         -1,
  24941         -1,
  24942     },
  24943 #endif /* chips */
  24944 
  24945 #if defined(BCM_56160_A0)
  24946     { /* SOC_REG_INT_GPORT_CONFIG_BCM56160_A0r */
  24947         soc_block_list[2],
  24948         soc_genreg,
  24949         1,
  24950         0,
  24951         0x2020000,
  24952         0,
  24953         0,
  24954         2,
  24955         soc_GPORT_CONFIG_BCM53400_A0r_fields,
  24956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24957         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24958         -1,
  24959         -1,
  24960     },
  24961 #endif /* chips */
  24962 
  24963 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  24964     { /* SOC_REG_INT_GPORT_CONFIG_BCM56224_A0r */
  24965         soc_block_list[2],
  24966         soc_genreg,
  24967         1,
  24968         0,
  24969         0x80000,
  24970         0,
  24971         0,
  24972         10,
  24973         soc_GPORT_CONFIG_BCM56224_A0r_fields,
  24974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24975         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24976         -1,
  24977         -1,
  24978     },
  24979 #endif /* chips */
  24980 
  24981 #if defined(BCM_56370_A0)
  24982     { /* SOC_REG_INT_GPORT_CONFIG_BCM56370_A0r */
  24983         soc_block_list[9],
  24984         soc_genreg,
  24985         1,
  24986         0,
  24987         0x2020000,
  24988         0,
  24989         0,
  24990         2,
  24991         soc_GPORT_CONFIG_BCM53400_A0r_fields,
  24992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24993         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24994         -1,
  24995         -1,
  24996         3,
  24997     },
  24998 #endif /* chips */
  24999 
  25000 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  25001     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  25002     { /* SOC_REG_INT_GPORT_CONFIG_BCM56624_A0r */
  25003         soc_block_list[205],
  25004         soc_genreg,
  25005         1,
  25006         0,
  25007         0x80900,
  25008         0,
  25009         0,
  25010         1,
  25011         soc_GPORT_CONFIG_BCM56624_A0r_fields,
  25012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25013         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25014         -1,
  25015         -1,
  25016     },
  25017 #endif /* chips */
  25018 
  25019 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25020     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25021     { /* SOC_REG_INT_GPORT_CONFIG_BCM56634_A0r */
  25022         soc_block_list[207],
  25023         soc_genreg,
  25024         1,
  25025         0,
  25026         0x80900,
  25027         0,
  25028         0,
  25029         1,
  25030         soc_GPORT_CONFIG_BCM56624_A0r_fields,
  25031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25032         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25033         -1,
  25034         -1,
  25035     },
  25036 #endif /* chips */
  25037 
  25038 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  25039     { /* SOC_REG_INT_GPORT_CONFIG_BCM56685_A0r */
  25040         soc_block_list[209],
  25041         soc_genreg,
  25042         1,
  25043         0,
  25044         0x80900,
  25045         0,
  25046         0,
  25047         1,
  25048         soc_GPORT_CONFIG_BCM56624_A0r_fields,
  25049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25050         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25051         -1,
  25052         -1,
  25053     },
  25054 #endif /* chips */
  25055 
  25056 #if defined(BCM_56800_A0)
  25057     { /* SOC_REG_INT_GPORT_CONFIG_BCM56800_A0r */
  25058         soc_block_list[9],
  25059         soc_portreg,
  25060         1,
  25061         0,
  25062         0xa00,
  25063         0,
  25064         0,
  25065         3,
  25066         soc_GPORT_CONFIG_BCM56800_A0r_fields,
  25067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25068         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25069         -1,
  25070         -1,
  25071     },
  25072 #endif /* chips */
  25073 
  25074 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  25075     { /* SOC_REG_INT_GPORT_CONFIG_BCM56820_A0r */
  25076         soc_block_list[206],
  25077         soc_portreg,
  25078         1,
  25079         0,
  25080         0x900,
  25081         0,
  25082         0,
  25083         1,
  25084         soc_GPORT_CONFIG_BCM56624_A0r_fields,
  25085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25086         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25087         -1,
  25088         -1,
  25089     },
  25090 #endif /* chips */
  25091 
  25092 #if defined(BCM_56840_A0)
  25093     { /* SOC_REG_INT_GPORT_CONFIG_BCM56840_A0r */
  25094         soc_block_list[16],
  25095         soc_portreg,
  25096         1,
  25097         0,
  25098         0x226,
  25099         0,
  25100         0,
  25101         1,
  25102         soc_GPORT_CONFIG_BCM56840_A0r_fields,
  25103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25105         -1,
  25106         -1,
  25107     },
  25108 #endif /* chips */
  25109 
  25110 #if defined(BCM_56840_B0)
  25111     { /* SOC_REG_INT_GPORT_CONFIG_BCM56840_B0r */
  25112         soc_block_list[16],
  25113         soc_portreg,
  25114         1,
  25115         0,
  25116         0x226,
  25117         0,
  25118         0,
  25119         1,
  25120         soc_GPORT_CONFIG_BCM56840_A0r_fields,
  25121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25122         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25123         -1,
  25124         -1,
  25125     },
  25126 #endif /* chips */
  25127 
  25128 #if defined(BCM_88375_A0)
  25129     { /* SOC_REG_INT_GPORT_CONFIG_BCM88375_A0r */
  25130         soc_block_list[2],
  25131         soc_genreg,
  25132         1,
  25133         0,
  25134         0x2020000,
  25135         0,
  25136         0,
  25137         2,
  25138         soc_GPORT_CONFIG_BCM88375_A0r_fields,
  25139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25140         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25141         -1,
  25142         -1,
  25143     },
  25144 #endif /* chips */
  25145 
  25146 #if defined(BCM_88375_B0)
  25147     { /* SOC_REG_INT_GPORT_CONFIG_BCM88375_B0r */
  25148         soc_block_list[2],
  25149         soc_genreg,
  25150         1,
  25151         0,
  25152         0x2020000,
  25153         0,
  25154         0,
  25155         2,
  25156         soc_GPORT_CONFIG_BCM88375_B0r_fields,
  25157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25158         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25159         -1,
  25160         -1,
  25161     },
  25162 #endif /* chips */
  25163 
  25164 #if defined(BCM_88470_A0)
  25165     { /* SOC_REG_INT_GPORT_CONFIG_BCM88470_A0r */
  25166         soc_block_list[2],
  25167         soc_genreg,
  25168         1,
  25169         0,
  25170         0x2020000,
  25171         0,
  25172         0,
  25173         2,
  25174         soc_GPORT_CONFIG_BCM88470_A0r_fields,
  25175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25176         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25177         -1,
  25178         -1,
  25179     },
  25180 #endif /* chips */
  25181 
  25182 #if defined(BCM_88470_B0)
  25183     { /* SOC_REG_INT_GPORT_CONFIG_BCM88470_B0r */
  25184         soc_block_list[2],
  25185         soc_genreg,
  25186         1,
  25187         0,
  25188         0x2020000,
  25189         0,
  25190         0,
  25191         2,
  25192         soc_GPORT_CONFIG_BCM88470_B0r_fields,
  25193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25194         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25195         -1,
  25196         -1,
  25197     },
  25198 #endif /* chips */
  25199 
  25200 #if defined(BCM_88675_A0)
  25201     { /* SOC_REG_INT_GPORT_CONFIG_BCM88675_A0r */
  25202         soc_block_list[2],
  25203         soc_genreg,
  25204         1,
  25205         0,
  25206         0x2020000,
  25207         0,
  25208         0,
  25209         2,
  25210         soc_GPORT_CONFIG_BCM88675_A0r_fields,
  25211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25212         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25213         -1,
  25214         -1,
  25215     },
  25216 #endif /* chips */
  25217 
  25218 #if defined(BCM_88675_B0)
  25219     { /* SOC_REG_INT_GPORT_CONFIG_BCM88675_B0r */
  25220         soc_block_list[2],
  25221         soc_genreg,
  25222         1,
  25223         0,
  25224         0x2020000,
  25225         0,
  25226         0,
  25227         2,
  25228         soc_GPORT_CONFIG_BCM88675_B0r_fields,
  25229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25230         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25231         -1,
  25232         -1,
  25233     },
  25234 #endif /* chips */
  25235 
  25236 #if defined(BCM_88680_A0)
  25237     { /* SOC_REG_INT_GPORT_CONFIG_BCM88680_A0r */
  25238         soc_block_list[2],
  25239         soc_genreg,
  25240         1,
  25241         0,
  25242         0x2020000,
  25243         0,
  25244         0,
  25245         2,
  25246         soc_GPORT_CONFIG_BCM88680_A0r_fields,
  25247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25248         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25249         -1,
  25250         -1,
  25251     },
  25252 #endif /* chips */
  25253 
  25254 #if defined(BCM_88732_A0)
  25255     { /* SOC_REG_INT_GPORT_CONFIG_BCM88732_A0r */
  25256         soc_block_list[16],
  25257         soc_portreg,
  25258         1,
  25259         0,
  25260         0x226,
  25261         0,
  25262         0,
  25263         1,
  25264         soc_GPORT_CONFIG_BCM56840_A0r_fields,
  25265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25266         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25267         -1,
  25268         -1,
  25269     },
  25270 #endif /* chips */
  25271 
  25272 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  25273     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  25274     { /* SOC_REG_INT_GPORT_DROP_ON_WRONG_SOP_S0_CNTr */
  25275         soc_block_list[2],
  25276         soc_genreg,
  25277         1,
  25278         0,
  25279         0x8002c,
  25280         SOC_REG_FLAG_RO,
  25281         0,
  25282         1,
  25283         soc_GPORT_DROP_ON_WRONG_SOP_S0_CNTr_fields,
  25284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25285         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25286         -1,
  25287         -1,
  25288     },
  25289 #endif /* chips */
  25290 
  25291 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  25292     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  25293     { /* SOC_REG_INT_GPORT_DROP_ON_WRONG_SOP_S1_CNTr */
  25294         soc_block_list[2],
  25295         soc_genreg,
  25296         1,
  25297         0,
  25298         0x8002b,
  25299         SOC_REG_FLAG_RO,
  25300         0,
  25301         1,
  25302         soc_GPORT_DROP_ON_WRONG_SOP_S1_CNTr_fields,
  25303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25304         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25305         -1,
  25306         -1,
  25307     },
  25308 #endif /* chips */
  25309 
  25310 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  25311     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  25312     { /* SOC_REG_INT_GPORT_DROP_ON_WRONG_SOP_S3_CNTr */
  25313         soc_block_list[2],
  25314         soc_genreg,
  25315         1,
  25316         0,
  25317         0x80030,
  25318         SOC_REG_FLAG_RO,
  25319         0,
  25320         1,
  25321         soc_GPORT_DROP_ON_WRONG_SOP_S3_CNTr_fields,
  25322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25323         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25324         -1,
  25325         -1,
  25326     },
  25327 #endif /* chips */
  25328 
  25329 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  25330     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  25331     { /* SOC_REG_INT_GPORT_DROP_ON_WRONG_SOP_S4_CNTr */
  25332         soc_block_list[2],
  25333         soc_genreg,
  25334         1,
  25335         0,
  25336         0x8002f,
  25337         SOC_REG_FLAG_RO,
  25338         0,
  25339         1,
  25340         soc_GPORT_DROP_ON_WRONG_SOP_S4_CNTr_fields,
  25341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25342         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25343         -1,
  25344         -1,
  25345     },
  25346 #endif /* chips */
  25347 
  25348 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  25349     { /* SOC_REG_INT_GPORT_ECC_CONTROLr */
  25350         soc_block_list[2],
  25351         soc_genreg,
  25352         1,
  25353         0,
  25354         0x2022900,
  25355         0,
  25356         0,
  25357         1,
  25358         soc_GPORT_ECC_CONTROLr_fields,
  25359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25360         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25361         -1,
  25362         -1,
  25363     },
  25364 #endif /* chips */
  25365 
  25366 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25367     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25368     { /* SOC_REG_INT_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr */
  25369         soc_block_list[2],
  25370         soc_genreg,
  25371         1,
  25372         0,
  25373         0x80e09,
  25374         0,
  25375         0,
  25376         4,
  25377         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  25378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25379         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  25380         -1,
  25381         -1,
  25382     },
  25383 #endif /* chips */
  25384 
  25385 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25386     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25387     { /* SOC_REG_INT_GPORT_EHG_RX_DATA_PARITY_STATUS_NACKr */
  25388         soc_block_list[2],
  25389         soc_genreg,
  25390         1,
  25391         0,
  25392         0x80e0e,
  25393         0,
  25394         0,
  25395         4,
  25396         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  25397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25398         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  25399         -1,
  25400         -1,
  25401     },
  25402 #endif /* chips */
  25403 
  25404 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25405     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25406     { /* SOC_REG_INT_GPORT_EHG_RX_MASK_PARITY_STATUS_INTRr */
  25407         soc_block_list[2],
  25408         soc_genreg,
  25409         1,
  25410         0,
  25411         0x80e0a,
  25412         0,
  25413         0,
  25414         4,
  25415         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  25416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25417         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  25418         -1,
  25419         -1,
  25420     },
  25421 #endif /* chips */
  25422 
  25423 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25424     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25425     { /* SOC_REG_INT_GPORT_EHG_RX_MASK_PARITY_STATUS_NACKr */
  25426         soc_block_list[2],
  25427         soc_genreg,
  25428         1,
  25429         0,
  25430         0x80e0f,
  25431         0,
  25432         0,
  25433         4,
  25434         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  25435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25436         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  25437         -1,
  25438         -1,
  25439     },
  25440 #endif /* chips */
  25441 
  25442 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25443     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25444     { /* SOC_REG_INT_GPORT_EHG_TX_DATA_PARITY_STATUS_INTRr */
  25445         soc_block_list[2],
  25446         soc_genreg,
  25447         1,
  25448         0,
  25449         0x80e08,
  25450         0,
  25451         0,
  25452         4,
  25453         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  25454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25455         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  25456         -1,
  25457         -1,
  25458     },
  25459 #endif /* chips */
  25460 
  25461 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25462     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25463     { /* SOC_REG_INT_GPORT_EHG_TX_DATA_PARITY_STATUS_NACKr */
  25464         soc_block_list[2],
  25465         soc_genreg,
  25466         1,
  25467         0,
  25468         0x80e0d,
  25469         0,
  25470         0,
  25471         4,
  25472         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  25473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25474         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  25475         -1,
  25476         -1,
  25477     },
  25478 #endif /* chips */
  25479 
  25480 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25481     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25482     { /* SOC_REG_INT_GPORT_EXTRA_SERDES_CTLr */
  25483         soc_block_list[2],
  25484         soc_genreg,
  25485         1,
  25486         0,
  25487         0x80e02,
  25488         0,
  25489         0,
  25490         1,
  25491         soc_GPORT_EXTRA_SERDES_CTLr_fields,
  25492         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25493         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25494         -1,
  25495         -1,
  25496     },
  25497 #endif /* chips */
  25498 
  25499 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25500     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25501     { /* SOC_REG_INT_GPORT_FORCE_DOUBLE_BIT_ERRORr */
  25502         soc_block_list[2],
  25503         soc_genreg,
  25504         1,
  25505         0,
  25506         0x80e04,
  25507         0,
  25508         0,
  25509         5,
  25510         soc_GPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  25511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25512         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25513         -1,
  25514         -1,
  25515     },
  25516 #endif /* chips */
  25517 
  25518 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25519     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25520     { /* SOC_REG_INT_GPORT_FORCE_SINGLE_BIT_ERRORr */
  25521         soc_block_list[2],
  25522         soc_genreg,
  25523         1,
  25524         0,
  25525         0x80e05,
  25526         0,
  25527         0,
  25528         5,
  25529         soc_GPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  25530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25531         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25532         -1,
  25533         -1,
  25534     },
  25535 #endif /* chips */
  25536 
  25537 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25538     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25539     { /* SOC_REG_INT_GPORT_GBODE_TXFIFO_PARITY_STATUS_INTRr */
  25540         soc_block_list[2],
  25541         soc_genreg,
  25542         1,
  25543         0,
  25544         0x80e0c,
  25545         0,
  25546         0,
  25547         4,
  25548         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  25549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25550         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  25551         -1,
  25552         -1,
  25553     },
  25554 #endif /* chips */
  25555 
  25556 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25557     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25558     { /* SOC_REG_INT_GPORT_GBOD_RXFIFO_PARITY_STATUS_INTRr */
  25559         soc_block_list[2],
  25560         soc_genreg,
  25561         1,
  25562         0,
  25563         0x80e0b,
  25564         0,
  25565         0,
  25566         4,
  25567         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  25568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25569         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  25570         -1,
  25571         -1,
  25572     },
  25573 #endif /* chips */
  25574 
  25575 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25576     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25577     { /* SOC_REG_INT_GPORT_INTR_ENABLEr */
  25578         soc_block_list[2],
  25579         soc_genreg,
  25580         1,
  25581         0,
  25582         0x80e07,
  25583         0,
  25584         0,
  25585         5,
  25586         soc_GPORT_INTR_ENABLEr_fields,
  25587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25588         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  25589         -1,
  25590         -1,
  25591     },
  25592 #endif /* chips */
  25593 
  25594 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  25595     { /* SOC_REG_INT_GPORT_INTR_ENABLE_BCM53570_A0r */
  25596         soc_block_list[2],
  25597         soc_genreg,
  25598         1,
  25599         0,
  25600         0x2023800,
  25601         0,
  25602         0,
  25603         2,
  25604         soc_GPORT_INTR_ENABLE_BCM53570_A0r_fields,
  25605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25606         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25607         -1,
  25608         -1,
  25609     },
  25610 #endif /* chips */
  25611 
  25612 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25613     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  25614     { /* SOC_REG_INT_GPORT_INTR_STATUSr */
  25615         soc_block_list[2],
  25616         soc_genreg,
  25617         1,
  25618         0,
  25619         0x80e06,
  25620         SOC_REG_FLAG_RO,
  25621         0,
  25622         5,
  25623         soc_GPORT_INTR_STATUSr_fields,
  25624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25625         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  25626         -1,
  25627         -1,
  25628     },
  25629 #endif /* chips */
  25630 
  25631 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  25632     { /* SOC_REG_INT_GPORT_INTR_STATUS_BCM53570_A0r */
  25633         soc_block_list[2],
  25634         soc_genreg,
  25635         1,
  25636         0,
  25637         0x2023700,
  25638         SOC_REG_FLAG_RO,
  25639         0,
  25640         2,
  25641         soc_GPORT_INTR_STATUS_BCM53570_A0r_fields,
  25642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25643         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25644         -1,
  25645         -1,
  25646     },
  25647 #endif /* chips */
  25648 
  25649 #if defined(BCM_88675_A0)
  25650     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMICr */
  25651         soc_block_list[2],
  25652         soc_genreg,
  25653         1,
  25654         0,
  25655         0x2020500,
  25656         0,
  25657         0,
  25658         1,
  25659         soc_GPORT_LINK_STATUS_TO_CMICr_fields,
  25660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25661         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25662         -1,
  25663         -1,
  25664     },
  25665 #endif /* chips */
  25666 
  25667 #if defined(BCM_53400_A0)
  25668     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM53400_A0r */
  25669         soc_block_list[9],
  25670         soc_genreg,
  25671         1,
  25672         0,
  25673         0x2020500,
  25674         0,
  25675         0,
  25676         1,
  25677         soc_GPORT_LINK_STATUS_TO_CMIC_BCM53400_A0r_fields,
  25678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25679         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25680         -1,
  25681         -1,
  25682     },
  25683 #endif /* chips */
  25684 
  25685 #if defined(BCM_53540_A0)
  25686     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM53540_A0r */
  25687         soc_block_list[2],
  25688         soc_genreg,
  25689         1,
  25690         0,
  25691         0x2020500,
  25692         0,
  25693         0,
  25694         1,
  25695         soc_GPORT_LINK_STATUS_TO_CMIC_BCM53400_A0r_fields,
  25696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25697         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25698         -1,
  25699         -1,
  25700     },
  25701 #endif /* chips */
  25702 
  25703 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  25704     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM53570_A0r */
  25705         soc_block_list[2],
  25706         soc_genreg,
  25707         1,
  25708         0,
  25709         0x2020500,
  25710         0,
  25711         0,
  25712         1,
  25713         soc_GPORT_LINK_STATUS_TO_CMIC_BCM53400_A0r_fields,
  25714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25715         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25716         -1,
  25717         -1,
  25718     },
  25719 #endif /* chips */
  25720 
  25721 #if defined(BCM_56150_A0)
  25722     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM56150_A0r */
  25723         soc_block_list[2],
  25724         soc_genreg,
  25725         1,
  25726         0,
  25727         0x2020500,
  25728         0,
  25729         0,
  25730         1,
  25731         soc_GPORT_LINK_STATUS_TO_CMIC_BCM56150_A0r_fields,
  25732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25733         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25734         -1,
  25735         -1,
  25736     },
  25737 #endif /* chips */
  25738 
  25739 #if defined(BCM_56160_A0)
  25740     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM56160_A0r */
  25741         soc_block_list[2],
  25742         soc_genreg,
  25743         1,
  25744         0,
  25745         0x2020500,
  25746         0,
  25747         0,
  25748         1,
  25749         soc_GPORT_LINK_STATUS_TO_CMIC_BCM53400_A0r_fields,
  25750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25751         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25752         -1,
  25753         -1,
  25754     },
  25755 #endif /* chips */
  25756 
  25757 #if defined(BCM_56370_A0)
  25758     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM56370_A0r */
  25759         soc_block_list[9],
  25760         soc_genreg,
  25761         1,
  25762         0,
  25763         0x2020500,
  25764         0,
  25765         0,
  25766         1,
  25767         soc_GPORT_LINK_STATUS_TO_CMIC_BCM53400_A0r_fields,
  25768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25769         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25770         -1,
  25771         -1,
  25772         3,
  25773     },
  25774 #endif /* chips */
  25775 
  25776 #if defined(BCM_88375_A0)
  25777     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM88375_A0r */
  25778         soc_block_list[2],
  25779         soc_genreg,
  25780         1,
  25781         0,
  25782         0x2020500,
  25783         0,
  25784         0,
  25785         1,
  25786         soc_GPORT_LINK_STATUS_TO_CMIC_BCM88375_A0r_fields,
  25787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25788         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25789         -1,
  25790         -1,
  25791     },
  25792 #endif /* chips */
  25793 
  25794 #if defined(BCM_88375_B0)
  25795     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM88375_B0r */
  25796         soc_block_list[2],
  25797         soc_genreg,
  25798         1,
  25799         0,
  25800         0x2020500,
  25801         0,
  25802         0,
  25803         1,
  25804         soc_GPORT_LINK_STATUS_TO_CMIC_BCM88375_B0r_fields,
  25805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25806         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25807         -1,
  25808         -1,
  25809     },
  25810 #endif /* chips */
  25811 
  25812 #if defined(BCM_88470_A0)
  25813     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM88470_A0r */
  25814         soc_block_list[2],
  25815         soc_genreg,
  25816         1,
  25817         0,
  25818         0x2020500,
  25819         0,
  25820         0,
  25821         1,
  25822         soc_GPORT_LINK_STATUS_TO_CMIC_BCM88470_A0r_fields,
  25823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25824         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25825         -1,
  25826         -1,
  25827     },
  25828 #endif /* chips */
  25829 
  25830 #if defined(BCM_88470_B0)
  25831     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM88470_B0r */
  25832         soc_block_list[2],
  25833         soc_genreg,
  25834         1,
  25835         0,
  25836         0x2020500,
  25837         0,
  25838         0,
  25839         1,
  25840         soc_GPORT_LINK_STATUS_TO_CMIC_BCM88470_B0r_fields,
  25841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25842         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25843         -1,
  25844         -1,
  25845     },
  25846 #endif /* chips */
  25847 
  25848 #if defined(BCM_88675_B0)
  25849     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM88675_B0r */
  25850         soc_block_list[2],
  25851         soc_genreg,
  25852         1,
  25853         0,
  25854         0x2020500,
  25855         0,
  25856         0,
  25857         1,
  25858         soc_GPORT_LINK_STATUS_TO_CMIC_BCM88675_B0r_fields,
  25859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25860         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25861         -1,
  25862         -1,
  25863     },
  25864 #endif /* chips */
  25865 
  25866 #if defined(BCM_88680_A0)
  25867     { /* SOC_REG_INT_GPORT_LINK_STATUS_TO_CMIC_BCM88680_A0r */
  25868         soc_block_list[2],
  25869         soc_genreg,
  25870         1,
  25871         0,
  25872         0x2020500,
  25873         0,
  25874         0,
  25875         1,
  25876         soc_GPORT_LINK_STATUS_TO_CMIC_BCM88680_A0r_fields,
  25877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25878         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25879         -1,
  25880         -1,
  25881     },
  25882 #endif /* chips */
  25883 
  25884 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  25885     { /* SOC_REG_INT_GPORT_MAC_CRS_SELr */
  25886         soc_block_list[2],
  25887         soc_genreg,
  25888         1,
  25889         0,
  25890         0x80031,
  25891         0,
  25892         0,
  25893         1,
  25894         soc_GPORT_MAC_CRS_SELr_fields,
  25895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25896         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25897         -1,
  25898         -1,
  25899     },
  25900 #endif /* chips */
  25901 
  25902 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  25903     defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  25904     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
  25905     defined(BCM_56440_B0)
  25906     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM53314_A0r */
  25907         soc_block_list[2],
  25908         soc_genreg,
  25909         1,
  25910         0,
  25911         0x80031,
  25912         0,
  25913         0,
  25914         1,
  25915         soc_GPORT_MAC_CRS_SEL_BCM53314_A0r_fields,
  25916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25918         -1,
  25919         -1,
  25920     },
  25921 #endif /* chips */
  25922 
  25923 #if defined(BCM_53400_A0)
  25924     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM53400_A0r */
  25925         soc_block_list[9],
  25926         soc_genreg,
  25927         1,
  25928         0,
  25929         0x2022200,
  25930         0,
  25931         0,
  25932         1,
  25933         soc_GPORT_MAC_CRS_SEL_BCM53400_A0r_fields,
  25934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25936         -1,
  25937         -1,
  25938     },
  25939 #endif /* chips */
  25940 
  25941 #if defined(BCM_53540_A0)
  25942     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM53540_A0r */
  25943         soc_block_list[2],
  25944         soc_genreg,
  25945         1,
  25946         0,
  25947         0x2022200,
  25948         0,
  25949         0,
  25950         1,
  25951         soc_GPORT_MAC_CRS_SEL_BCM53400_A0r_fields,
  25952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25953         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25954         -1,
  25955         -1,
  25956     },
  25957 #endif /* chips */
  25958 
  25959 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  25960     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM53570_A0r */
  25961         soc_block_list[2],
  25962         soc_genreg,
  25963         1,
  25964         0,
  25965         0x2022d00,
  25966         0,
  25967         0,
  25968         1,
  25969         soc_GPORT_MAC_CRS_SEL_BCM53400_A0r_fields,
  25970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25971         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25972         -1,
  25973         -1,
  25974     },
  25975 #endif /* chips */
  25976 
  25977 #if defined(BCM_56150_A0)
  25978     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM56150_A0r */
  25979         soc_block_list[2],
  25980         soc_genreg,
  25981         1,
  25982         0,
  25983         0x2022200,
  25984         0,
  25985         0,
  25986         1,
  25987         soc_GPORT_MAC_CRS_SEL_BCM56150_A0r_fields,
  25988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25990         -1,
  25991         -1,
  25992     },
  25993 #endif /* chips */
  25994 
  25995 #if defined(BCM_56160_A0)
  25996     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM56160_A0r */
  25997         soc_block_list[2],
  25998         soc_genreg,
  25999         1,
  26000         0,
  26001         0x2022200,
  26002         0,
  26003         0,
  26004         1,
  26005         soc_GPORT_MAC_CRS_SEL_BCM53400_A0r_fields,
  26006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26007         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26008         -1,
  26009         -1,
  26010     },
  26011 #endif /* chips */
  26012 
  26013 #if defined(BCM_56370_A0)
  26014     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM56370_A0r */
  26015         soc_block_list[9],
  26016         soc_genreg,
  26017         1,
  26018         0,
  26019         0x2022200,
  26020         0,
  26021         0,
  26022         1,
  26023         soc_GPORT_MAC_CRS_SEL_BCM53400_A0r_fields,
  26024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26026         -1,
  26027         -1,
  26028         3,
  26029     },
  26030 #endif /* chips */
  26031 
  26032 #if defined(BCM_88375_A0)
  26033     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM88375_A0r */
  26034         soc_block_list[2],
  26035         soc_genreg,
  26036         1,
  26037         0,
  26038         0x2022200,
  26039         0,
  26040         0,
  26041         1,
  26042         soc_GPORT_MAC_CRS_SEL_BCM88375_A0r_fields,
  26043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26044         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26045         -1,
  26046         -1,
  26047     },
  26048 #endif /* chips */
  26049 
  26050 #if defined(BCM_88375_B0)
  26051     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM88375_B0r */
  26052         soc_block_list[2],
  26053         soc_genreg,
  26054         1,
  26055         0,
  26056         0x2022200,
  26057         0,
  26058         0,
  26059         1,
  26060         soc_GPORT_MAC_CRS_SEL_BCM88375_B0r_fields,
  26061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26062         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26063         -1,
  26064         -1,
  26065     },
  26066 #endif /* chips */
  26067 
  26068 #if defined(BCM_88470_A0)
  26069     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM88470_A0r */
  26070         soc_block_list[2],
  26071         soc_genreg,
  26072         1,
  26073         0,
  26074         0x2022200,
  26075         0,
  26076         0,
  26077         1,
  26078         soc_GPORT_MAC_CRS_SEL_BCM88470_A0r_fields,
  26079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26080         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26081         -1,
  26082         -1,
  26083     },
  26084 #endif /* chips */
  26085 
  26086 #if defined(BCM_88470_B0)
  26087     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM88470_B0r */
  26088         soc_block_list[2],
  26089         soc_genreg,
  26090         1,
  26091         0,
  26092         0x2022200,
  26093         0,
  26094         0,
  26095         1,
  26096         soc_GPORT_MAC_CRS_SEL_BCM88470_B0r_fields,
  26097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26098         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26099         -1,
  26100         -1,
  26101     },
  26102 #endif /* chips */
  26103 
  26104 #if defined(BCM_88675_A0)
  26105     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM88675_A0r */
  26106         soc_block_list[2],
  26107         soc_genreg,
  26108         1,
  26109         0,
  26110         0x2022200,
  26111         0,
  26112         0,
  26113         1,
  26114         soc_GPORT_MAC_CRS_SEL_BCM88675_A0r_fields,
  26115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26116         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26117         -1,
  26118         -1,
  26119     },
  26120 #endif /* chips */
  26121 
  26122 #if defined(BCM_88675_B0)
  26123     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM88675_B0r */
  26124         soc_block_list[2],
  26125         soc_genreg,
  26126         1,
  26127         0,
  26128         0x2022200,
  26129         0,
  26130         0,
  26131         1,
  26132         soc_GPORT_MAC_CRS_SEL_BCM88675_B0r_fields,
  26133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26134         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26135         -1,
  26136         -1,
  26137     },
  26138 #endif /* chips */
  26139 
  26140 #if defined(BCM_88680_A0)
  26141     { /* SOC_REG_INT_GPORT_MAC_CRS_SEL_BCM88680_A0r */
  26142         soc_block_list[2],
  26143         soc_genreg,
  26144         1,
  26145         0,
  26146         0x2022200,
  26147         0,
  26148         0,
  26149         1,
  26150         soc_GPORT_MAC_CRS_SEL_BCM88680_A0r_fields,
  26151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26152         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26153         -1,
  26154         -1,
  26155     },
  26156 #endif /* chips */
  26157 
  26158 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26159     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  26160     { /* SOC_REG_INT_GPORT_MODE_REGr */
  26161         soc_block_list[2],
  26162         soc_genreg,
  26163         1,
  26164         0,
  26165         0x80e00,
  26166         0,
  26167         0,
  26168         1,
  26169         soc_GPORT_MODE_REGr_fields,
  26170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26171         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26172         -1,
  26173         -1,
  26174     },
  26175 #endif /* chips */
  26176 
  26177 #if defined(BCM_53400_A0)
  26178     { /* SOC_REG_INT_GPORT_MODE_REG_BCM53400_A0r */
  26179         soc_block_list[9],
  26180         soc_genreg,
  26181         1,
  26182         0,
  26183         0x2020100,
  26184         0,
  26185         0,
  26186         6,
  26187         soc_GPORT_MODE_REG_BCM53400_A0r_fields,
  26188         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26189         SOC_RESET_MASK_DEC(0x0000003b, 0x00000000)
  26190         -1,
  26191         -1,
  26192     },
  26193 #endif /* chips */
  26194 
  26195 #if defined(BCM_53540_A0)
  26196     { /* SOC_REG_INT_GPORT_MODE_REG_BCM53540_A0r */
  26197         soc_block_list[2],
  26198         soc_genreg,
  26199         1,
  26200         0,
  26201         0x2020100,
  26202         0,
  26203         0,
  26204         6,
  26205         soc_GPORT_MODE_REG_BCM53400_A0r_fields,
  26206         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26207         SOC_RESET_MASK_DEC(0x0000003b, 0x00000000)
  26208         -1,
  26209         -1,
  26210     },
  26211 #endif /* chips */
  26212 
  26213 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26214     { /* SOC_REG_INT_GPORT_MODE_REG_BCM53570_A0r */
  26215         soc_block_list[2],
  26216         soc_genreg,
  26217         1,
  26218         0,
  26219         0x2020100,
  26220         0,
  26221         0,
  26222         6,
  26223         soc_GPORT_MODE_REG_BCM53400_A0r_fields,
  26224         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26225         SOC_RESET_MASK_DEC(0x0000003b, 0x00000000)
  26226         -1,
  26227         -1,
  26228     },
  26229 #endif /* chips */
  26230 
  26231 #if defined(BCM_56150_A0)
  26232     { /* SOC_REG_INT_GPORT_MODE_REG_BCM56150_A0r */
  26233         soc_block_list[2],
  26234         soc_genreg,
  26235         1,
  26236         0,
  26237         0x2020100,
  26238         0,
  26239         0,
  26240         3,
  26241         soc_GPORT_MODE_REG_BCM56150_A0r_fields,
  26242         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26243         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  26244         -1,
  26245         -1,
  26246     },
  26247 #endif /* chips */
  26248 
  26249 #if defined(BCM_56160_A0)
  26250     { /* SOC_REG_INT_GPORT_MODE_REG_BCM56160_A0r */
  26251         soc_block_list[2],
  26252         soc_genreg,
  26253         1,
  26254         0,
  26255         0x2020100,
  26256         0,
  26257         0,
  26258         6,
  26259         soc_GPORT_MODE_REG_BCM53400_A0r_fields,
  26260         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26261         SOC_RESET_MASK_DEC(0x0000003b, 0x00000000)
  26262         -1,
  26263         -1,
  26264     },
  26265 #endif /* chips */
  26266 
  26267 #if defined(BCM_56370_A0)
  26268     { /* SOC_REG_INT_GPORT_MODE_REG_BCM56370_A0r */
  26269         soc_block_list[9],
  26270         soc_genreg,
  26271         1,
  26272         0,
  26273         0x2020100,
  26274         0,
  26275         0,
  26276         6,
  26277         soc_GPORT_MODE_REG_BCM53400_A0r_fields,
  26278         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26279         SOC_RESET_MASK_DEC(0x0000003b, 0x00000000)
  26280         -1,
  26281         -1,
  26282         3,
  26283     },
  26284 #endif /* chips */
  26285 
  26286 #if defined(BCM_88375_A0)
  26287     { /* SOC_REG_INT_GPORT_MODE_REG_BCM88375_A0r */
  26288         soc_block_list[2],
  26289         soc_genreg,
  26290         1,
  26291         0,
  26292         0x2020100,
  26293         0,
  26294         0,
  26295         6,
  26296         soc_GPORT_MODE_REG_BCM88375_A0r_fields,
  26297         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26298         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26299         -1,
  26300         -1,
  26301     },
  26302 #endif /* chips */
  26303 
  26304 #if defined(BCM_88375_B0)
  26305     { /* SOC_REG_INT_GPORT_MODE_REG_BCM88375_B0r */
  26306         soc_block_list[2],
  26307         soc_genreg,
  26308         1,
  26309         0,
  26310         0x2020100,
  26311         0,
  26312         0,
  26313         6,
  26314         soc_GPORT_MODE_REG_BCM88375_B0r_fields,
  26315         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26316         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26317         -1,
  26318         -1,
  26319     },
  26320 #endif /* chips */
  26321 
  26322 #if defined(BCM_88470_A0)
  26323     { /* SOC_REG_INT_GPORT_MODE_REG_BCM88470_A0r */
  26324         soc_block_list[2],
  26325         soc_genreg,
  26326         1,
  26327         0,
  26328         0x2020100,
  26329         0,
  26330         0,
  26331         6,
  26332         soc_GPORT_MODE_REG_BCM88470_A0r_fields,
  26333         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26334         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26335         -1,
  26336         -1,
  26337     },
  26338 #endif /* chips */
  26339 
  26340 #if defined(BCM_88470_B0)
  26341     { /* SOC_REG_INT_GPORT_MODE_REG_BCM88470_B0r */
  26342         soc_block_list[2],
  26343         soc_genreg,
  26344         1,
  26345         0,
  26346         0x2020100,
  26347         0,
  26348         0,
  26349         6,
  26350         soc_GPORT_MODE_REG_BCM88470_B0r_fields,
  26351         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26352         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26353         -1,
  26354         -1,
  26355     },
  26356 #endif /* chips */
  26357 
  26358 #if defined(BCM_88675_A0)
  26359     { /* SOC_REG_INT_GPORT_MODE_REG_BCM88675_A0r */
  26360         soc_block_list[2],
  26361         soc_genreg,
  26362         1,
  26363         0,
  26364         0x2020100,
  26365         0,
  26366         0,
  26367         6,
  26368         soc_GPORT_MODE_REG_BCM88675_A0r_fields,
  26369         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26370         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26371         -1,
  26372         -1,
  26373     },
  26374 #endif /* chips */
  26375 
  26376 #if defined(BCM_88675_B0)
  26377     { /* SOC_REG_INT_GPORT_MODE_REG_BCM88675_B0r */
  26378         soc_block_list[2],
  26379         soc_genreg,
  26380         1,
  26381         0,
  26382         0x2020100,
  26383         0,
  26384         0,
  26385         6,
  26386         soc_GPORT_MODE_REG_BCM88675_B0r_fields,
  26387         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26388         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26389         -1,
  26390         -1,
  26391     },
  26392 #endif /* chips */
  26393 
  26394 #if defined(BCM_88680_A0)
  26395     { /* SOC_REG_INT_GPORT_MODE_REG_BCM88680_A0r */
  26396         soc_block_list[2],
  26397         soc_genreg,
  26398         1,
  26399         0,
  26400         0x2020100,
  26401         0,
  26402         0,
  26403         6,
  26404         soc_GPORT_MODE_REG_BCM88680_A0r_fields,
  26405         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  26406         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26407         -1,
  26408         -1,
  26409     },
  26410 #endif /* chips */
  26411 
  26412 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26413     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  26414     { /* SOC_REG_INT_GPORT_PARITY_CONTROLr */
  26415         soc_block_list[2],
  26416         soc_genreg,
  26417         1,
  26418         0,
  26419         0x80e03,
  26420         0,
  26421         0,
  26422         5,
  26423         soc_GPORT_INTR_ENABLEr_fields,
  26424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26425         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  26426         -1,
  26427         -1,
  26428     },
  26429 #endif /* chips */
  26430 
  26431 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  26432     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  26433     { /* SOC_REG_INT_GPORT_RSV_MASKr */
  26434         soc_block_list[2],
  26435         soc_genreg,
  26436         1,
  26437         0,
  26438         0x80001,
  26439         0,
  26440         0,
  26441         1,
  26442         soc_GPORT_RSV_MASKr_fields,
  26443         SOC_RESET_VAL_DEC(0x04380000, 0x00000000)
  26444         SOC_RESET_MASK_DEC(0x7fff0000, 0x00000000)
  26445         -1,
  26446         -1,
  26447     },
  26448 #endif /* chips */
  26449 
  26450 #if defined(BCM_53400_A0)
  26451     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM53400_A0r */
  26452         soc_block_list[9],
  26453         soc_genreg,
  26454         1,
  26455         0,
  26456         0x2020600,
  26457         0,
  26458         0,
  26459         1,
  26460         soc_GPORT_RSV_MASK_BCM53400_A0r_fields,
  26461         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26462         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26463         -1,
  26464         -1,
  26465     },
  26466 #endif /* chips */
  26467 
  26468 #if defined(BCM_53540_A0)
  26469     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM53540_A0r */
  26470         soc_block_list[2],
  26471         soc_genreg,
  26472         1,
  26473         0,
  26474         0x2020600,
  26475         0,
  26476         0,
  26477         1,
  26478         soc_GPORT_RSV_MASK_BCM53400_A0r_fields,
  26479         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26480         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26481         -1,
  26482         -1,
  26483     },
  26484 #endif /* chips */
  26485 
  26486 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26487     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM53570_A0r */
  26488         soc_block_list[2],
  26489         soc_genreg,
  26490         1,
  26491         0,
  26492         0x2020600,
  26493         0,
  26494         0,
  26495         1,
  26496         soc_GPORT_RSV_MASK_BCM53570_A0r_fields,
  26497         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26498         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  26499         -1,
  26500         -1,
  26501     },
  26502 #endif /* chips */
  26503 
  26504 #if defined(BCM_56150_A0)
  26505     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56150_A0r */
  26506         soc_block_list[2],
  26507         soc_genreg,
  26508         1,
  26509         0,
  26510         0x2020600,
  26511         0,
  26512         0,
  26513         1,
  26514         soc_GPORT_RSV_MASK_BCM56150_A0r_fields,
  26515         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26516         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26517         -1,
  26518         -1,
  26519     },
  26520 #endif /* chips */
  26521 
  26522 #if defined(BCM_56160_A0)
  26523     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56160_A0r */
  26524         soc_block_list[2],
  26525         soc_genreg,
  26526         1,
  26527         0,
  26528         0x2020600,
  26529         0,
  26530         0,
  26531         1,
  26532         soc_GPORT_RSV_MASK_BCM53400_A0r_fields,
  26533         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26534         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26535         -1,
  26536         -1,
  26537     },
  26538 #endif /* chips */
  26539 
  26540 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  26541     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  26542     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56224_A0r */
  26543         soc_block_list[2],
  26544         soc_genreg,
  26545         1,
  26546         0,
  26547         0x80001,
  26548         0,
  26549         0,
  26550         1,
  26551         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  26552         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  26553         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26554         -1,
  26555         -1,
  26556     },
  26557 #endif /* chips */
  26558 
  26559 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  26560     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
  26561     defined(BCM_56440_B0)
  26562     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56334_A0r */
  26563         soc_block_list[2],
  26564         soc_genreg,
  26565         1,
  26566         0,
  26567         0x80001,
  26568         0,
  26569         0,
  26570         1,
  26571         soc_GPORT_RSV_MASK_BCM56334_A0r_fields,
  26572         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26573         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26574         -1,
  26575         -1,
  26576     },
  26577 #endif /* chips */
  26578 
  26579 #if defined(BCM_56370_A0)
  26580     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56370_A0r */
  26581         soc_block_list[9],
  26582         soc_genreg,
  26583         1,
  26584         0,
  26585         0x2020600,
  26586         0,
  26587         0,
  26588         1,
  26589         soc_GPORT_RSV_MASK_BCM53400_A0r_fields,
  26590         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26591         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26592         -1,
  26593         -1,
  26594         3,
  26595     },
  26596 #endif /* chips */
  26597 
  26598 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  26599     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  26600     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56624_A0r */
  26601         soc_block_list[205],
  26602         soc_genreg,
  26603         1,
  26604         0,
  26605         0x80901,
  26606         0,
  26607         0,
  26608         1,
  26609         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  26610         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  26611         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26612         -1,
  26613         -1,
  26614     },
  26615 #endif /* chips */
  26616 
  26617 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26618     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  26619     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56634_A0r */
  26620         soc_block_list[207],
  26621         soc_genreg,
  26622         1,
  26623         0,
  26624         0x80901,
  26625         0,
  26626         0,
  26627         1,
  26628         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  26629         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  26630         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26631         -1,
  26632         -1,
  26633     },
  26634 #endif /* chips */
  26635 
  26636 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  26637     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56685_A0r */
  26638         soc_block_list[209],
  26639         soc_genreg,
  26640         1,
  26641         0,
  26642         0x80901,
  26643         0,
  26644         0,
  26645         1,
  26646         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  26647         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  26648         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26649         -1,
  26650         -1,
  26651     },
  26652 #endif /* chips */
  26653 
  26654 #if defined(BCM_56800_A0)
  26655     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56800_A0r */
  26656         soc_block_list[9],
  26657         soc_portreg,
  26658         1,
  26659         0,
  26660         0xa01,
  26661         0,
  26662         0,
  26663         1,
  26664         soc_GPORT_RSV_MASKr_fields,
  26665         SOC_RESET_VAL_DEC(0x04380000, 0x00000000)
  26666         SOC_RESET_MASK_DEC(0x7fff0000, 0x00000000)
  26667         -1,
  26668         -1,
  26669     },
  26670 #endif /* chips */
  26671 
  26672 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  26673     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM56820_A0r */
  26674         soc_block_list[206],
  26675         soc_portreg,
  26676         1,
  26677         0,
  26678         0x901,
  26679         0,
  26680         0,
  26681         1,
  26682         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  26683         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  26684         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26685         -1,
  26686         -1,
  26687     },
  26688 #endif /* chips */
  26689 
  26690 #if defined(BCM_88375_A0)
  26691     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM88375_A0r */
  26692         soc_block_list[2],
  26693         soc_genreg,
  26694         1,
  26695         0,
  26696         0x2020600,
  26697         0,
  26698         0,
  26699         1,
  26700         soc_GPORT_RSV_MASK_BCM88375_A0r_fields,
  26701         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26702         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26703         -1,
  26704         -1,
  26705     },
  26706 #endif /* chips */
  26707 
  26708 #if defined(BCM_88375_B0)
  26709     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM88375_B0r */
  26710         soc_block_list[2],
  26711         soc_genreg,
  26712         1,
  26713         0,
  26714         0x2020600,
  26715         0,
  26716         0,
  26717         1,
  26718         soc_GPORT_RSV_MASK_BCM88375_B0r_fields,
  26719         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26720         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26721         -1,
  26722         -1,
  26723     },
  26724 #endif /* chips */
  26725 
  26726 #if defined(BCM_88470_A0)
  26727     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM88470_A0r */
  26728         soc_block_list[2],
  26729         soc_genreg,
  26730         1,
  26731         0,
  26732         0x2020600,
  26733         0,
  26734         0,
  26735         1,
  26736         soc_GPORT_RSV_MASK_BCM88470_A0r_fields,
  26737         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26738         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26739         -1,
  26740         -1,
  26741     },
  26742 #endif /* chips */
  26743 
  26744 #if defined(BCM_88470_B0)
  26745     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM88470_B0r */
  26746         soc_block_list[2],
  26747         soc_genreg,
  26748         1,
  26749         0,
  26750         0x2020600,
  26751         0,
  26752         0,
  26753         1,
  26754         soc_GPORT_RSV_MASK_BCM88470_B0r_fields,
  26755         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26756         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26757         -1,
  26758         -1,
  26759     },
  26760 #endif /* chips */
  26761 
  26762 #if defined(BCM_88675_A0)
  26763     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM88675_A0r */
  26764         soc_block_list[2],
  26765         soc_genreg,
  26766         1,
  26767         0,
  26768         0x2020600,
  26769         0,
  26770         0,
  26771         1,
  26772         soc_GPORT_RSV_MASK_BCM88675_A0r_fields,
  26773         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26774         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26775         -1,
  26776         -1,
  26777     },
  26778 #endif /* chips */
  26779 
  26780 #if defined(BCM_88675_B0)
  26781     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM88675_B0r */
  26782         soc_block_list[2],
  26783         soc_genreg,
  26784         1,
  26785         0,
  26786         0x2020600,
  26787         0,
  26788         0,
  26789         1,
  26790         soc_GPORT_RSV_MASK_BCM88675_B0r_fields,
  26791         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26792         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26793         -1,
  26794         -1,
  26795     },
  26796 #endif /* chips */
  26797 
  26798 #if defined(BCM_88680_A0)
  26799     { /* SOC_REG_INT_GPORT_RSV_MASK_BCM88680_A0r */
  26800         soc_block_list[2],
  26801         soc_genreg,
  26802         1,
  26803         0,
  26804         0x2020600,
  26805         0,
  26806         0,
  26807         1,
  26808         soc_GPORT_RSV_MASK_BCM88680_A0r_fields,
  26809         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  26810         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  26811         -1,
  26812         -1,
  26813     },
  26814 #endif /* chips */
  26815 
  26816 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  26817     { /* SOC_REG_INT_GPORT_RX_EEE_LPI_DURATION_COUNTERr */
  26818         soc_block_list[2],
  26819         soc_portreg,
  26820         1,
  26821         0,
  26822         0xbf,
  26823         SOC_REG_FLAG_COUNTER,
  26824         0,
  26825         1,
  26826         soc_GR1023r_fields,
  26827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26828         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26829         230,
  26830         -1,
  26831     },
  26832 #endif /* chips */
  26833 
  26834 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  26835     { /* SOC_REG_INT_GPORT_RX_EEE_LPI_EVENT_COUNTERr */
  26836         soc_block_list[2],
  26837         soc_portreg,
  26838         1,
  26839         0,
  26840         0xbe,
  26841         SOC_REG_FLAG_COUNTER,
  26842         0,
  26843         1,
  26844         soc_GR1023r_fields,
  26845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26846         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26847         229,
  26848         -1,
  26849     },
  26850 #endif /* chips */
  26851 
  26852 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26853     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  26854     { /* SOC_REG_INT_GPORT_SERDES_CTLr */
  26855         soc_block_list[2],
  26856         soc_genreg,
  26857         1,
  26858         0,
  26859         0x80e01,
  26860         0,
  26861         0,
  26862         1,
  26863         soc_XGPORT_SERDES_CTLr_fields,
  26864         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  26865         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  26866         -1,
  26867         -1,
  26868     },
  26869 #endif /* chips */
  26870 
  26871 #if defined(BCM_53570_A0)
  26872     { /* SOC_REG_INT_GPORT_SGMII0_CTRL_REGr */
  26873         soc_block_list[71],
  26874         soc_genreg,
  26875         1,
  26876         0,
  26877         0x2020600,
  26878         0,
  26879         0,
  26880         6,
  26881         soc_GPORT_SGMII0_CTRL_REGr_fields,
  26882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26883         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26884         -1,
  26885         -1,
  26886     },
  26887 #endif /* chips */
  26888 
  26889 #if defined(BCM_53540_A0)
  26890     { /* SOC_REG_INT_GPORT_SGMII0_CTRL_REG_BCM53540_A0r */
  26891         soc_block_list[71],
  26892         soc_genreg,
  26893         1,
  26894         0,
  26895         0x2020600,
  26896         0,
  26897         0,
  26898         6,
  26899         soc_IPROC_WRAP_SGMII_CTRL_REGr_fields,
  26900         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  26901         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26902         -1,
  26903         -1,
  26904     },
  26905 #endif /* chips */
  26906 
  26907 #if defined(BCM_53570_B0)
  26908     { /* SOC_REG_INT_GPORT_SGMII0_CTRL_REG_BCM53570_B0r */
  26909         soc_block_list[71],
  26910         soc_genreg,
  26911         1,
  26912         0,
  26913         0x2020600,
  26914         0,
  26915         0,
  26916         6,
  26917         soc_IPROC_WRAP_SGMII_CTRL_REGr_fields,
  26918         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  26919         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26920         -1,
  26921         -1,
  26922     },
  26923 #endif /* chips */
  26924 
  26925 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26926     { /* SOC_REG_INT_GPORT_SGMII0_STATUS0_REGr */
  26927         soc_block_list[71],
  26928         soc_genreg,
  26929         1,
  26930         0,
  26931         0x2020700,
  26932         SOC_REG_FLAG_RO,
  26933         0,
  26934         7,
  26935         soc_GPORT_SGMII0_STATUS0_REGr_fields,
  26936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26938         -1,
  26939         -1,
  26940     },
  26941 #endif /* chips */
  26942 
  26943 #if defined(BCM_53540_A0)
  26944     { /* SOC_REG_INT_GPORT_SGMII0_STATUS0_REG_BCM53540_A0r */
  26945         soc_block_list[71],
  26946         soc_genreg,
  26947         1,
  26948         0,
  26949         0x2020700,
  26950         SOC_REG_FLAG_RO,
  26951         0,
  26952         7,
  26953         soc_GPORT_SGMII0_STATUS0_REGr_fields,
  26954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26956         -1,
  26957         -1,
  26958     },
  26959 #endif /* chips */
  26960 
  26961 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26962     { /* SOC_REG_INT_GPORT_SGMII0_STATUS1_REGr */
  26963         soc_block_list[71],
  26964         soc_genreg,
  26965         1,
  26966         0,
  26967         0x2020800,
  26968         SOC_REG_FLAG_RO,
  26969         0,
  26970         6,
  26971         soc_GPORT_SGMII0_STATUS1_REGr_fields,
  26972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26973         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26974         -1,
  26975         -1,
  26976     },
  26977 #endif /* chips */
  26978 
  26979 #if defined(BCM_53540_A0)
  26980     { /* SOC_REG_INT_GPORT_SGMII0_STATUS1_REG_BCM53540_A0r */
  26981         soc_block_list[71],
  26982         soc_genreg,
  26983         1,
  26984         0,
  26985         0x2020800,
  26986         SOC_REG_FLAG_RO,
  26987         0,
  26988         6,
  26989         soc_GPORT_SGMII0_STATUS1_REGr_fields,
  26990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26992         -1,
  26993         -1,
  26994     },
  26995 #endif /* chips */
  26996 
  26997 #if defined(BCM_53570_A0)
  26998     { /* SOC_REG_INT_GPORT_SGMII1_CTRL_REGr */
  26999         soc_block_list[71],
  27000         soc_genreg,
  27001         1,
  27002         0,
  27003         0x2020900,
  27004         0,
  27005         0,
  27006         6,
  27007         soc_GPORT_SGMII0_CTRL_REGr_fields,
  27008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27009         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27010         -1,
  27011         -1,
  27012     },
  27013 #endif /* chips */
  27014 
  27015 #if defined(BCM_53540_A0)
  27016     { /* SOC_REG_INT_GPORT_SGMII1_CTRL_REG_BCM53540_A0r */
  27017         soc_block_list[71],
  27018         soc_genreg,
  27019         1,
  27020         0,
  27021         0x2020900,
  27022         0,
  27023         0,
  27024         6,
  27025         soc_IPROC_WRAP_SGMII_CTRL_REGr_fields,
  27026         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  27027         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27028         -1,
  27029         -1,
  27030     },
  27031 #endif /* chips */
  27032 
  27033 #if defined(BCM_53570_B0)
  27034     { /* SOC_REG_INT_GPORT_SGMII1_CTRL_REG_BCM53570_B0r */
  27035         soc_block_list[71],
  27036         soc_genreg,
  27037         1,
  27038         0,
  27039         0x2020900,
  27040         0,
  27041         0,
  27042         6,
  27043         soc_IPROC_WRAP_SGMII_CTRL_REGr_fields,
  27044         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  27045         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27046         -1,
  27047         -1,
  27048     },
  27049 #endif /* chips */
  27050 
  27051 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27052     { /* SOC_REG_INT_GPORT_SGMII1_STATUS0_REGr */
  27053         soc_block_list[71],
  27054         soc_genreg,
  27055         1,
  27056         0,
  27057         0x2020a00,
  27058         SOC_REG_FLAG_RO,
  27059         0,
  27060         7,
  27061         soc_GPORT_SGMII0_STATUS0_REGr_fields,
  27062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27064         -1,
  27065         -1,
  27066     },
  27067 #endif /* chips */
  27068 
  27069 #if defined(BCM_53540_A0)
  27070     { /* SOC_REG_INT_GPORT_SGMII1_STATUS0_REG_BCM53540_A0r */
  27071         soc_block_list[71],
  27072         soc_genreg,
  27073         1,
  27074         0,
  27075         0x2020a00,
  27076         SOC_REG_FLAG_RO,
  27077         0,
  27078         7,
  27079         soc_GPORT_SGMII0_STATUS0_REGr_fields,
  27080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27081         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27082         -1,
  27083         -1,
  27084     },
  27085 #endif /* chips */
  27086 
  27087 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27088     { /* SOC_REG_INT_GPORT_SGMII1_STATUS1_REGr */
  27089         soc_block_list[71],
  27090         soc_genreg,
  27091         1,
  27092         0,
  27093         0x2020b00,
  27094         SOC_REG_FLAG_RO,
  27095         0,
  27096         6,
  27097         soc_GPORT_SGMII0_STATUS1_REGr_fields,
  27098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27100         -1,
  27101         -1,
  27102     },
  27103 #endif /* chips */
  27104 
  27105 #if defined(BCM_53540_A0)
  27106     { /* SOC_REG_INT_GPORT_SGMII1_STATUS1_REG_BCM53540_A0r */
  27107         soc_block_list[71],
  27108         soc_genreg,
  27109         1,
  27110         0,
  27111         0x2020b00,
  27112         SOC_REG_FLAG_RO,
  27113         0,
  27114         6,
  27115         soc_GPORT_SGMII0_STATUS1_REGr_fields,
  27116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27118         -1,
  27119         -1,
  27120     },
  27121 #endif /* chips */
  27122 
  27123 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  27124     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  27125     { /* SOC_REG_INT_GPORT_SGNDET_EARLYCRSr */
  27126         soc_block_list[205],
  27127         soc_portreg,
  27128         1,
  27129         0,
  27130         0x908,
  27131         0,
  27132         0,
  27133         2,
  27134         soc_GPORT_SGNDET_EARLYCRSr_fields,
  27135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27136         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  27137         -1,
  27138         -1,
  27139     },
  27140 #endif /* chips */
  27141 
  27142 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  27143     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  27144     { /* SOC_REG_INT_GPORT_SGNDET_EARLYCRS_BCM56634_A0r */
  27145         soc_block_list[207],
  27146         soc_portreg,
  27147         1,
  27148         0,
  27149         0x908,
  27150         0,
  27151         0,
  27152         2,
  27153         soc_GPORT_SGNDET_EARLYCRSr_fields,
  27154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27155         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  27156         -1,
  27157         -1,
  27158     },
  27159 #endif /* chips */
  27160 
  27161 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  27162     { /* SOC_REG_INT_GPORT_SGNDET_EARLYCRS_BCM56685_A0r */
  27163         soc_block_list[209],
  27164         soc_portreg,
  27165         1,
  27166         0,
  27167         0x908,
  27168         0,
  27169         0,
  27170         2,
  27171         soc_GPORT_SGNDET_EARLYCRSr_fields,
  27172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27173         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  27174         -1,
  27175         -1,
  27176     },
  27177 #endif /* chips */
  27178 
  27179 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  27180     { /* SOC_REG_INT_GPORT_SGNDET_EARLYCRS_BCM56820_A0r */
  27181         soc_block_list[9],
  27182         soc_portreg,
  27183         1,
  27184         0,
  27185         0xc09,
  27186         0,
  27187         0,
  27188         2,
  27189         soc_GPORT_SGNDET_EARLYCRSr_fields,
  27190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27191         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  27192         -1,
  27193         -1,
  27194     },
  27195 #endif /* chips */
  27196 
  27197 #if defined(BCM_56840_A0)
  27198     { /* SOC_REG_INT_GPORT_SGNDET_EARLYCRS_BCM56840_A0r */
  27199         soc_block_list[16],
  27200         soc_portreg,
  27201         1,
  27202         0,
  27203         0x228,
  27204         0,
  27205         0,
  27206         2,
  27207         soc_GPORT_SGNDET_EARLYCRSr_fields,
  27208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27209         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  27210         -1,
  27211         -1,
  27212     },
  27213 #endif /* chips */
  27214 
  27215 #if defined(BCM_56840_B0)
  27216     { /* SOC_REG_INT_GPORT_SGNDET_EARLYCRS_BCM56840_B0r */
  27217         soc_block_list[16],
  27218         soc_portreg,
  27219         1,
  27220         0,
  27221         0x228,
  27222         0,
  27223         0,
  27224         2,
  27225         soc_GPORT_SGNDET_EARLYCRSr_fields,
  27226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27227         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  27228         -1,
  27229         -1,
  27230     },
  27231 #endif /* chips */
  27232 
  27233 #if defined(BCM_88732_A0)
  27234     { /* SOC_REG_INT_GPORT_SGNDET_EARLYCRS_BCM88732_A0r */
  27235         soc_block_list[16],
  27236         soc_portreg,
  27237         1,
  27238         0,
  27239         0x228,
  27240         0,
  27241         0,
  27242         2,
  27243         soc_GPORT_SGNDET_EARLYCRSr_fields,
  27244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27245         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  27246         -1,
  27247         -1,
  27248     },
  27249 #endif /* chips */
  27250 
  27251 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  27252     { /* SOC_REG_INT_GPORT_SGN_DET_SELr */
  27253         soc_block_list[2],
  27254         soc_genreg,
  27255         1,
  27256         0,
  27257         0x80032,
  27258         0,
  27259         0,
  27260         1,
  27261         soc_GPORT_SGN_DET_SELr_fields,
  27262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27264         -1,
  27265         -1,
  27266     },
  27267 #endif /* chips */
  27268 
  27269 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  27270     defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  27271     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
  27272     defined(BCM_56440_B0)
  27273     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM53314_A0r */
  27274         soc_block_list[2],
  27275         soc_genreg,
  27276         1,
  27277         0,
  27278         0x80032,
  27279         0,
  27280         0,
  27281         1,
  27282         soc_GPORT_SGN_DET_SEL_BCM53314_A0r_fields,
  27283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27284         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27285         -1,
  27286         -1,
  27287     },
  27288 #endif /* chips */
  27289 
  27290 #if defined(BCM_53400_A0)
  27291     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM53400_A0r */
  27292         soc_block_list[9],
  27293         soc_genreg,
  27294         1,
  27295         0,
  27296         0x2022300,
  27297         0,
  27298         0,
  27299         1,
  27300         soc_GPORT_SGN_DET_SEL_BCM53400_A0r_fields,
  27301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27303         -1,
  27304         -1,
  27305     },
  27306 #endif /* chips */
  27307 
  27308 #if defined(BCM_53540_A0)
  27309     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM53540_A0r */
  27310         soc_block_list[2],
  27311         soc_genreg,
  27312         1,
  27313         0,
  27314         0x2022300,
  27315         0,
  27316         0,
  27317         1,
  27318         soc_GPORT_SGN_DET_SEL_BCM53400_A0r_fields,
  27319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27321         -1,
  27322         -1,
  27323     },
  27324 #endif /* chips */
  27325 
  27326 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27327     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM53570_A0r */
  27328         soc_block_list[2],
  27329         soc_genreg,
  27330         1,
  27331         0,
  27332         0x2022e00,
  27333         0,
  27334         0,
  27335         1,
  27336         soc_GPORT_SGN_DET_SEL_BCM53400_A0r_fields,
  27337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27339         -1,
  27340         -1,
  27341     },
  27342 #endif /* chips */
  27343 
  27344 #if defined(BCM_56150_A0)
  27345     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM56150_A0r */
  27346         soc_block_list[2],
  27347         soc_genreg,
  27348         1,
  27349         0,
  27350         0x2022300,
  27351         0,
  27352         0,
  27353         1,
  27354         soc_GPORT_SGN_DET_SEL_BCM56150_A0r_fields,
  27355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27357         -1,
  27358         -1,
  27359     },
  27360 #endif /* chips */
  27361 
  27362 #if defined(BCM_56160_A0)
  27363     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM56160_A0r */
  27364         soc_block_list[2],
  27365         soc_genreg,
  27366         1,
  27367         0,
  27368         0x2022300,
  27369         0,
  27370         0,
  27371         1,
  27372         soc_GPORT_SGN_DET_SEL_BCM53400_A0r_fields,
  27373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27375         -1,
  27376         -1,
  27377     },
  27378 #endif /* chips */
  27379 
  27380 #if defined(BCM_56370_A0)
  27381     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM56370_A0r */
  27382         soc_block_list[9],
  27383         soc_genreg,
  27384         1,
  27385         0,
  27386         0x2022300,
  27387         0,
  27388         0,
  27389         1,
  27390         soc_GPORT_SGN_DET_SEL_BCM53400_A0r_fields,
  27391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27393         -1,
  27394         -1,
  27395         3,
  27396     },
  27397 #endif /* chips */
  27398 
  27399 #if defined(BCM_88375_A0)
  27400     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM88375_A0r */
  27401         soc_block_list[2],
  27402         soc_genreg,
  27403         1,
  27404         0,
  27405         0x2022300,
  27406         0,
  27407         0,
  27408         1,
  27409         soc_GPORT_SGN_DET_SEL_BCM88375_A0r_fields,
  27410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27411         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27412         -1,
  27413         -1,
  27414     },
  27415 #endif /* chips */
  27416 
  27417 #if defined(BCM_88375_B0)
  27418     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM88375_B0r */
  27419         soc_block_list[2],
  27420         soc_genreg,
  27421         1,
  27422         0,
  27423         0x2022300,
  27424         0,
  27425         0,
  27426         1,
  27427         soc_GPORT_SGN_DET_SEL_BCM88375_B0r_fields,
  27428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27429         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27430         -1,
  27431         -1,
  27432     },
  27433 #endif /* chips */
  27434 
  27435 #if defined(BCM_88470_A0)
  27436     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM88470_A0r */
  27437         soc_block_list[2],
  27438         soc_genreg,
  27439         1,
  27440         0,
  27441         0x2022300,
  27442         0,
  27443         0,
  27444         1,
  27445         soc_GPORT_SGN_DET_SEL_BCM88470_A0r_fields,
  27446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27447         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27448         -1,
  27449         -1,
  27450     },
  27451 #endif /* chips */
  27452 
  27453 #if defined(BCM_88470_B0)
  27454     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM88470_B0r */
  27455         soc_block_list[2],
  27456         soc_genreg,
  27457         1,
  27458         0,
  27459         0x2022300,
  27460         0,
  27461         0,
  27462         1,
  27463         soc_GPORT_SGN_DET_SEL_BCM88470_B0r_fields,
  27464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27465         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27466         -1,
  27467         -1,
  27468     },
  27469 #endif /* chips */
  27470 
  27471 #if defined(BCM_88675_A0)
  27472     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM88675_A0r */
  27473         soc_block_list[2],
  27474         soc_genreg,
  27475         1,
  27476         0,
  27477         0x2022300,
  27478         0,
  27479         0,
  27480         1,
  27481         soc_GPORT_SGN_DET_SEL_BCM88675_A0r_fields,
  27482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27483         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27484         -1,
  27485         -1,
  27486     },
  27487 #endif /* chips */
  27488 
  27489 #if defined(BCM_88675_B0)
  27490     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM88675_B0r */
  27491         soc_block_list[2],
  27492         soc_genreg,
  27493         1,
  27494         0,
  27495         0x2022300,
  27496         0,
  27497         0,
  27498         1,
  27499         soc_GPORT_SGN_DET_SEL_BCM88675_B0r_fields,
  27500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27501         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27502         -1,
  27503         -1,
  27504     },
  27505 #endif /* chips */
  27506 
  27507 #if defined(BCM_88680_A0)
  27508     { /* SOC_REG_INT_GPORT_SGN_DET_SEL_BCM88680_A0r */
  27509         soc_block_list[2],
  27510         soc_genreg,
  27511         1,
  27512         0,
  27513         0x2022300,
  27514         0,
  27515         0,
  27516         1,
  27517         soc_GPORT_SGN_DET_SEL_BCM88680_A0r_fields,
  27518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27519         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27520         -1,
  27521         -1,
  27522     },
  27523 #endif /* chips */
  27524 
  27525 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  27526     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  27527     { /* SOC_REG_INT_GPORT_SOP_S0r */
  27528         soc_block_list[2],
  27529         soc_genreg,
  27530         1,
  27531         0,
  27532         0x8002a,
  27533         0,
  27534         0,
  27535         1,
  27536         soc_GPORT_SOP_S0r_fields,
  27537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27539         -1,
  27540         -1,
  27541     },
  27542 #endif /* chips */
  27543 
  27544 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  27545     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  27546     { /* SOC_REG_INT_GPORT_SOP_S1r */
  27547         soc_block_list[2],
  27548         soc_genreg,
  27549         1,
  27550         0,
  27551         0x80029,
  27552         0,
  27553         0,
  27554         1,
  27555         soc_GPORT_SOP_S1r_fields,
  27556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27558         -1,
  27559         -1,
  27560     },
  27561 #endif /* chips */
  27562 
  27563 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  27564     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  27565     { /* SOC_REG_INT_GPORT_SOP_S3r */
  27566         soc_block_list[2],
  27567         soc_genreg,
  27568         1,
  27569         0,
  27570         0x8002e,
  27571         0,
  27572         0,
  27573         1,
  27574         soc_GPORT_SOP_S3r_fields,
  27575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27577         -1,
  27578         -1,
  27579     },
  27580 #endif /* chips */
  27581 
  27582 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  27583     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  27584     { /* SOC_REG_INT_GPORT_SOP_S4r */
  27585         soc_block_list[2],
  27586         soc_genreg,
  27587         1,
  27588         0,
  27589         0x8002d,
  27590         0,
  27591         0,
  27592         1,
  27593         soc_GPORT_SOP_S4r_fields,
  27594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27595         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27596         -1,
  27597         -1,
  27598     },
  27599 #endif /* chips */
  27600 
  27601 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  27602     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  27603     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASKr */
  27604         soc_block_list[2],
  27605         soc_genreg,
  27606         1,
  27607         0,
  27608         0x80002,
  27609         0,
  27610         0,
  27611         1,
  27612         soc_GPORT_RSV_MASKr_fields,
  27613         SOC_RESET_VAL_DEC(0x04380000, 0x00000000)
  27614         SOC_RESET_MASK_DEC(0x7fff0000, 0x00000000)
  27615         -1,
  27616         -1,
  27617     },
  27618 #endif /* chips */
  27619 
  27620 #if defined(BCM_53400_A0)
  27621     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM53400_A0r */
  27622         soc_block_list[9],
  27623         soc_genreg,
  27624         1,
  27625         0,
  27626         0x2020700,
  27627         0,
  27628         0,
  27629         1,
  27630         soc_GPORT_RSV_MASK_BCM53400_A0r_fields,
  27631         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27632         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27633         -1,
  27634         -1,
  27635     },
  27636 #endif /* chips */
  27637 
  27638 #if defined(BCM_53540_A0)
  27639     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM53540_A0r */
  27640         soc_block_list[2],
  27641         soc_genreg,
  27642         1,
  27643         0,
  27644         0x2020700,
  27645         0,
  27646         0,
  27647         1,
  27648         soc_GPORT_RSV_MASK_BCM53400_A0r_fields,
  27649         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27650         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27651         -1,
  27652         -1,
  27653     },
  27654 #endif /* chips */
  27655 
  27656 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27657     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM53570_A0r */
  27658         soc_block_list[2],
  27659         soc_genreg,
  27660         1,
  27661         0,
  27662         0x2020700,
  27663         0,
  27664         0,
  27665         1,
  27666         soc_GPORT_RSV_MASK_BCM53570_A0r_fields,
  27667         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27668         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  27669         -1,
  27670         -1,
  27671     },
  27672 #endif /* chips */
  27673 
  27674 #if defined(BCM_56150_A0)
  27675     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56150_A0r */
  27676         soc_block_list[2],
  27677         soc_genreg,
  27678         1,
  27679         0,
  27680         0x2020700,
  27681         0,
  27682         0,
  27683         1,
  27684         soc_GPORT_RSV_MASK_BCM56150_A0r_fields,
  27685         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27686         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27687         -1,
  27688         -1,
  27689     },
  27690 #endif /* chips */
  27691 
  27692 #if defined(BCM_56160_A0)
  27693     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56160_A0r */
  27694         soc_block_list[2],
  27695         soc_genreg,
  27696         1,
  27697         0,
  27698         0x2020700,
  27699         0,
  27700         0,
  27701         1,
  27702         soc_GPORT_RSV_MASK_BCM53400_A0r_fields,
  27703         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27704         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27705         -1,
  27706         -1,
  27707     },
  27708 #endif /* chips */
  27709 
  27710 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  27711     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  27712     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56224_A0r */
  27713         soc_block_list[2],
  27714         soc_genreg,
  27715         1,
  27716         0,
  27717         0x80002,
  27718         0,
  27719         0,
  27720         1,
  27721         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  27722         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  27723         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27724         -1,
  27725         -1,
  27726     },
  27727 #endif /* chips */
  27728 
  27729 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  27730     defined(BCM_56334_B0) || defined(BCM_56440_A0) || \
  27731     defined(BCM_56440_B0)
  27732     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56334_A0r */
  27733         soc_block_list[2],
  27734         soc_genreg,
  27735         1,
  27736         0,
  27737         0x80002,
  27738         0,
  27739         0,
  27740         1,
  27741         soc_GPORT_RSV_MASK_BCM56334_A0r_fields,
  27742         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27743         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27744         -1,
  27745         -1,
  27746     },
  27747 #endif /* chips */
  27748 
  27749 #if defined(BCM_56370_A0)
  27750     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56370_A0r */
  27751         soc_block_list[9],
  27752         soc_genreg,
  27753         1,
  27754         0,
  27755         0x2020700,
  27756         0,
  27757         0,
  27758         1,
  27759         soc_GPORT_RSV_MASK_BCM53400_A0r_fields,
  27760         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27761         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27762         -1,
  27763         -1,
  27764         3,
  27765     },
  27766 #endif /* chips */
  27767 
  27768 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  27769     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  27770     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56624_A0r */
  27771         soc_block_list[205],
  27772         soc_genreg,
  27773         1,
  27774         0,
  27775         0x80902,
  27776         0,
  27777         0,
  27778         1,
  27779         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  27780         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  27781         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27782         -1,
  27783         -1,
  27784     },
  27785 #endif /* chips */
  27786 
  27787 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  27788     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  27789     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56634_A0r */
  27790         soc_block_list[207],
  27791         soc_genreg,
  27792         1,
  27793         0,
  27794         0x80902,
  27795         0,
  27796         0,
  27797         1,
  27798         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  27799         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  27800         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27801         -1,
  27802         -1,
  27803     },
  27804 #endif /* chips */
  27805 
  27806 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  27807     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56685_A0r */
  27808         soc_block_list[209],
  27809         soc_genreg,
  27810         1,
  27811         0,
  27812         0x80902,
  27813         0,
  27814         0,
  27815         1,
  27816         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  27817         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  27818         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27819         -1,
  27820         -1,
  27821     },
  27822 #endif /* chips */
  27823 
  27824 #if defined(BCM_56800_A0)
  27825     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56800_A0r */
  27826         soc_block_list[9],
  27827         soc_portreg,
  27828         1,
  27829         0,
  27830         0xa02,
  27831         0,
  27832         0,
  27833         1,
  27834         soc_GPORT_RSV_MASKr_fields,
  27835         SOC_RESET_VAL_DEC(0x04380000, 0x00000000)
  27836         SOC_RESET_MASK_DEC(0x7fff0000, 0x00000000)
  27837         -1,
  27838         -1,
  27839     },
  27840 #endif /* chips */
  27841 
  27842 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  27843     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM56820_A0r */
  27844         soc_block_list[206],
  27845         soc_portreg,
  27846         1,
  27847         0,
  27848         0x902,
  27849         0,
  27850         0,
  27851         1,
  27852         soc_GPORT_RSV_MASK_BCM56624_A0r_fields,
  27853         SOC_RESET_VAL_DEC(0x00000438, 0x00000000)
  27854         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27855         -1,
  27856         -1,
  27857     },
  27858 #endif /* chips */
  27859 
  27860 #if defined(BCM_88375_A0)
  27861     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM88375_A0r */
  27862         soc_block_list[2],
  27863         soc_genreg,
  27864         1,
  27865         0,
  27866         0x2020700,
  27867         0,
  27868         0,
  27869         1,
  27870         soc_GPORT_STAT_UPDATE_MASK_BCM88375_A0r_fields,
  27871         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27872         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27873         -1,
  27874         -1,
  27875     },
  27876 #endif /* chips */
  27877 
  27878 #if defined(BCM_88375_B0)
  27879     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM88375_B0r */
  27880         soc_block_list[2],
  27881         soc_genreg,
  27882         1,
  27883         0,
  27884         0x2020700,
  27885         0,
  27886         0,
  27887         1,
  27888         soc_GPORT_STAT_UPDATE_MASK_BCM88375_B0r_fields,
  27889         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27890         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27891         -1,
  27892         -1,
  27893     },
  27894 #endif /* chips */
  27895 
  27896 #if defined(BCM_88470_A0)
  27897     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM88470_A0r */
  27898         soc_block_list[2],
  27899         soc_genreg,
  27900         1,
  27901         0,
  27902         0x2020700,
  27903         0,
  27904         0,
  27905         1,
  27906         soc_GPORT_STAT_UPDATE_MASK_BCM88470_A0r_fields,
  27907         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27908         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27909         -1,
  27910         -1,
  27911     },
  27912 #endif /* chips */
  27913 
  27914 #if defined(BCM_88470_B0)
  27915     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM88470_B0r */
  27916         soc_block_list[2],
  27917         soc_genreg,
  27918         1,
  27919         0,
  27920         0x2020700,
  27921         0,
  27922         0,
  27923         1,
  27924         soc_GPORT_STAT_UPDATE_MASK_BCM88470_B0r_fields,
  27925         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27926         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27927         -1,
  27928         -1,
  27929     },
  27930 #endif /* chips */
  27931 
  27932 #if defined(BCM_88675_A0)
  27933     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM88675_A0r */
  27934         soc_block_list[2],
  27935         soc_genreg,
  27936         1,
  27937         0,
  27938         0x2020700,
  27939         0,
  27940         0,
  27941         1,
  27942         soc_GPORT_STAT_UPDATE_MASKr_fields,
  27943         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27944         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27945         -1,
  27946         -1,
  27947     },
  27948 #endif /* chips */
  27949 
  27950 #if defined(BCM_88675_B0)
  27951     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM88675_B0r */
  27952         soc_block_list[2],
  27953         soc_genreg,
  27954         1,
  27955         0,
  27956         0x2020700,
  27957         0,
  27958         0,
  27959         1,
  27960         soc_GPORT_STAT_UPDATE_MASK_BCM88675_B0r_fields,
  27961         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27962         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27963         -1,
  27964         -1,
  27965     },
  27966 #endif /* chips */
  27967 
  27968 #if defined(BCM_88680_A0)
  27969     { /* SOC_REG_INT_GPORT_STAT_UPDATE_MASK_BCM88680_A0r */
  27970         soc_block_list[2],
  27971         soc_genreg,
  27972         1,
  27973         0,
  27974         0x2020700,
  27975         0,
  27976         0,
  27977         1,
  27978         soc_GPORT_STAT_UPDATE_MASK_BCM88680_A0r_fields,
  27979         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
  27980         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27981         -1,
  27982         -1,
  27983     },
  27984 #endif /* chips */
  27985 
  27986 #if defined(BCM_88675_A0)
  27987     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROLr */
  27988         soc_block_list[2],
  27989         soc_genreg,
  27990         1,
  27991         0,
  27992         0x2020400,
  27993         0,
  27994         0,
  27995         2,
  27996         soc_GPORT_SW_FLOW_CONTROLr_fields,
  27997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27998         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  27999         -1,
  28000         -1,
  28001     },
  28002 #endif /* chips */
  28003 
  28004 #if defined(BCM_53400_A0)
  28005     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM53400_A0r */
  28006         soc_block_list[9],
  28007         soc_genreg,
  28008         1,
  28009         0,
  28010         0x2020400,
  28011         0,
  28012         0,
  28013         2,
  28014         soc_GPORT_SW_FLOW_CONTROL_BCM53400_A0r_fields,
  28015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28016         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28017         -1,
  28018         -1,
  28019     },
  28020 #endif /* chips */
  28021 
  28022 #if defined(BCM_53540_A0)
  28023     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM53540_A0r */
  28024         soc_block_list[2],
  28025         soc_genreg,
  28026         1,
  28027         0,
  28028         0x2020400,
  28029         0,
  28030         0,
  28031         2,
  28032         soc_GPORT_SW_FLOW_CONTROL_BCM53400_A0r_fields,
  28033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28034         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28035         -1,
  28036         -1,
  28037     },
  28038 #endif /* chips */
  28039 
  28040 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  28041     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM53570_A0r */
  28042         soc_block_list[2],
  28043         soc_genreg,
  28044         1,
  28045         0,
  28046         0x2020400,
  28047         0,
  28048         0,
  28049         2,
  28050         soc_GPORT_SW_FLOW_CONTROL_BCM53400_A0r_fields,
  28051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28052         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28053         -1,
  28054         -1,
  28055     },
  28056 #endif /* chips */
  28057 
  28058 #if defined(BCM_56150_A0)
  28059     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM56150_A0r */
  28060         soc_block_list[2],
  28061         soc_genreg,
  28062         1,
  28063         0,
  28064         0x2020400,
  28065         0,
  28066         0,
  28067         2,
  28068         soc_GPORT_SW_FLOW_CONTROL_BCM56150_A0r_fields,
  28069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28070         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28071         -1,
  28072         -1,
  28073     },
  28074 #endif /* chips */
  28075 
  28076 #if defined(BCM_56160_A0)
  28077     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM56160_A0r */
  28078         soc_block_list[2],
  28079         soc_genreg,
  28080         1,
  28081         0,
  28082         0x2020400,
  28083         0,
  28084         0,
  28085         2,
  28086         soc_GPORT_SW_FLOW_CONTROL_BCM53400_A0r_fields,
  28087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28088         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28089         -1,
  28090         -1,
  28091     },
  28092 #endif /* chips */
  28093 
  28094 #if defined(BCM_56370_A0)
  28095     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM56370_A0r */
  28096         soc_block_list[9],
  28097         soc_genreg,
  28098         1,
  28099         0,
  28100         0x2020400,
  28101         0,
  28102         0,
  28103         2,
  28104         soc_GPORT_SW_FLOW_CONTROL_BCM53400_A0r_fields,
  28105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28106         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28107         -1,
  28108         -1,
  28109         3,
  28110     },
  28111 #endif /* chips */
  28112 
  28113 #if defined(BCM_88375_A0)
  28114     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM88375_A0r */
  28115         soc_block_list[2],
  28116         soc_genreg,
  28117         1,
  28118         0,
  28119         0x2020400,
  28120         0,
  28121         0,
  28122         2,
  28123         soc_GPORT_SW_FLOW_CONTROL_BCM88375_A0r_fields,
  28124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28125         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28126         -1,
  28127         -1,
  28128     },
  28129 #endif /* chips */
  28130 
  28131 #if defined(BCM_88375_B0)
  28132     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM88375_B0r */
  28133         soc_block_list[2],
  28134         soc_genreg,
  28135         1,
  28136         0,
  28137         0x2020400,
  28138         0,
  28139         0,
  28140         2,
  28141         soc_GPORT_SW_FLOW_CONTROL_BCM88375_B0r_fields,
  28142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28143         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28144         -1,
  28145         -1,
  28146     },
  28147 #endif /* chips */
  28148 
  28149 #if defined(BCM_88470_A0)
  28150     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM88470_A0r */
  28151         soc_block_list[2],
  28152         soc_genreg,
  28153         1,
  28154         0,
  28155         0x2020400,
  28156         0,
  28157         0,
  28158         2,
  28159         soc_GPORT_SW_FLOW_CONTROL_BCM88470_A0r_fields,
  28160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28161         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28162         -1,
  28163         -1,
  28164     },
  28165 #endif /* chips */
  28166 
  28167 #if defined(BCM_88470_B0)
  28168     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM88470_B0r */
  28169         soc_block_list[2],
  28170         soc_genreg,
  28171         1,
  28172         0,
  28173         0x2020400,
  28174         0,
  28175         0,
  28176         2,
  28177         soc_GPORT_SW_FLOW_CONTROL_BCM88470_B0r_fields,
  28178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28179         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28180         -1,
  28181         -1,
  28182     },
  28183 #endif /* chips */
  28184 
  28185 #if defined(BCM_88675_B0)
  28186     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM88675_B0r */
  28187         soc_block_list[2],
  28188         soc_genreg,
  28189         1,
  28190         0,
  28191         0x2020400,
  28192         0,
  28193         0,
  28194         2,
  28195         soc_GPORT_SW_FLOW_CONTROL_BCM88675_B0r_fields,
  28196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28197         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28198         -1,
  28199         -1,
  28200     },
  28201 #endif /* chips */
  28202 
  28203 #if defined(BCM_88680_A0)
  28204     { /* SOC_REG_INT_GPORT_SW_FLOW_CONTROL_BCM88680_A0r */
  28205         soc_block_list[2],
  28206         soc_genreg,
  28207         1,
  28208         0,
  28209         0x2020400,
  28210         0,
  28211         0,
  28212         2,
  28213         soc_GPORT_SW_FLOW_CONTROL_BCM88680_A0r_fields,
  28214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28215         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28216         -1,
  28217         -1,
  28218     },
  28219 #endif /* chips */
  28220 
  28221 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  28222     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
  28223     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
  28224     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  28225     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  28226     defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
  28227     defined(BCM_56514_A0)
  28228     { /* SOC_REG_INT_GPORT_TPIDr */
  28229         soc_block_list[2],
  28230         soc_genreg,
  28231         1,
  28232         0,
  28233         0x80028,
  28234         0,
  28235         0,
  28236         1,
  28237         soc_GPORT_TPIDr_fields,
  28238         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28239         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28240         -1,
  28241         -1,
  28242     },
  28243 #endif /* chips */
  28244 
  28245 #if defined(BCM_53400_A0)
  28246     { /* SOC_REG_INT_GPORT_TPID_BCM53400_A0r */
  28247         soc_block_list[9],
  28248         soc_genreg,
  28249         1,
  28250         0,
  28251         0x2022100,
  28252         0,
  28253         0,
  28254         1,
  28255         soc_EGR_OUTER_TPID_0_BCM53400_A0r_fields,
  28256         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28257         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28258         -1,
  28259         -1,
  28260     },
  28261 #endif /* chips */
  28262 
  28263 #if defined(BCM_53540_A0)
  28264     { /* SOC_REG_INT_GPORT_TPID_BCM53540_A0r */
  28265         soc_block_list[2],
  28266         soc_genreg,
  28267         1,
  28268         0,
  28269         0x2022100,
  28270         0,
  28271         0,
  28272         1,
  28273         soc_EGR_OUTER_TPID_0_BCM53400_A0r_fields,
  28274         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28275         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28276         -1,
  28277         -1,
  28278     },
  28279 #endif /* chips */
  28280 
  28281 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  28282     { /* SOC_REG_INT_GPORT_TPID_BCM53570_A0r */
  28283         soc_block_list[2],
  28284         soc_genreg,
  28285         1,
  28286         0,
  28287         0x2022c00,
  28288         0,
  28289         0,
  28290         1,
  28291         soc_EGR_OUTER_TPID_0_BCM53400_A0r_fields,
  28292         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28293         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28294         -1,
  28295         -1,
  28296     },
  28297 #endif /* chips */
  28298 
  28299 #if defined(BCM_56150_A0)
  28300     { /* SOC_REG_INT_GPORT_TPID_BCM56150_A0r */
  28301         soc_block_list[2],
  28302         soc_genreg,
  28303         1,
  28304         0,
  28305         0x2022100,
  28306         0,
  28307         0,
  28308         1,
  28309         soc_EGR_OUTER_TPID_0r_fields,
  28310         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28311         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28312         -1,
  28313         -1,
  28314     },
  28315 #endif /* chips */
  28316 
  28317 #if defined(BCM_56160_A0)
  28318     { /* SOC_REG_INT_GPORT_TPID_BCM56160_A0r */
  28319         soc_block_list[2],
  28320         soc_genreg,
  28321         1,
  28322         0,
  28323         0x2022100,
  28324         0,
  28325         0,
  28326         1,
  28327         soc_EGR_OUTER_TPID_0_BCM53400_A0r_fields,
  28328         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28329         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28330         -1,
  28331         -1,
  28332     },
  28333 #endif /* chips */
  28334 
  28335 #if defined(BCM_56370_A0)
  28336     { /* SOC_REG_INT_GPORT_TPID_BCM56370_A0r */
  28337         soc_block_list[9],
  28338         soc_genreg,
  28339         1,
  28340         0,
  28341         0x2022100,
  28342         0,
  28343         0,
  28344         1,
  28345         soc_EGR_OUTER_TPID_0_BCM53400_A0r_fields,
  28346         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28347         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28348         -1,
  28349         -1,
  28350         3,
  28351     },
  28352 #endif /* chips */
  28353 
  28354 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  28355     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  28356     { /* SOC_REG_INT_GPORT_TPID_BCM56624_A0r */
  28357         soc_block_list[205],
  28358         soc_genreg,
  28359         1,
  28360         0,
  28361         0x80907,
  28362         0,
  28363         0,
  28364         1,
  28365         soc_GPORT_TPIDr_fields,
  28366         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28367         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28368         -1,
  28369         -1,
  28370     },
  28371 #endif /* chips */
  28372 
  28373 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  28374     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  28375     { /* SOC_REG_INT_GPORT_TPID_BCM56634_A0r */
  28376         soc_block_list[207],
  28377         soc_genreg,
  28378         1,
  28379         0,
  28380         0x80907,
  28381         0,
  28382         0,
  28383         1,
  28384         soc_GPORT_TPIDr_fields,
  28385         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28386         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28387         -1,
  28388         -1,
  28389     },
  28390 #endif /* chips */
  28391 
  28392 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  28393     { /* SOC_REG_INT_GPORT_TPID_BCM56685_A0r */
  28394         soc_block_list[209],
  28395         soc_genreg,
  28396         1,
  28397         0,
  28398         0x80907,
  28399         0,
  28400         0,
  28401         1,
  28402         soc_GPORT_TPIDr_fields,
  28403         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28404         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28405         -1,
  28406         -1,
  28407     },
  28408 #endif /* chips */
  28409 
  28410 #if defined(BCM_56800_A0)
  28411     { /* SOC_REG_INT_GPORT_TPID_BCM56800_A0r */
  28412         soc_block_list[9],
  28413         soc_portreg,
  28414         1,
  28415         0,
  28416         0xa07,
  28417         0,
  28418         0,
  28419         1,
  28420         soc_GPORT_TPIDr_fields,
  28421         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28422         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28423         -1,
  28424         -1,
  28425     },
  28426 #endif /* chips */
  28427 
  28428 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  28429     { /* SOC_REG_INT_GPORT_TPID_BCM56820_A0r */
  28430         soc_block_list[206],
  28431         soc_portreg,
  28432         1,
  28433         0,
  28434         0x907,
  28435         0,
  28436         0,
  28437         1,
  28438         soc_GPORT_TPIDr_fields,
  28439         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28440         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28441         -1,
  28442         -1,
  28443     },
  28444 #endif /* chips */
  28445 
  28446 #if defined(BCM_88375_A0)
  28447     { /* SOC_REG_INT_GPORT_TPID_BCM88375_A0r */
  28448         soc_block_list[2],
  28449         soc_genreg,
  28450         1,
  28451         0,
  28452         0x2022100,
  28453         0,
  28454         0,
  28455         1,
  28456         soc_GPORT_TPID_BCM88375_A0r_fields,
  28457         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28458         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28459         -1,
  28460         -1,
  28461     },
  28462 #endif /* chips */
  28463 
  28464 #if defined(BCM_88375_B0)
  28465     { /* SOC_REG_INT_GPORT_TPID_BCM88375_B0r */
  28466         soc_block_list[2],
  28467         soc_genreg,
  28468         1,
  28469         0,
  28470         0x2022100,
  28471         0,
  28472         0,
  28473         1,
  28474         soc_GPORT_TPID_BCM88375_B0r_fields,
  28475         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28476         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28477         -1,
  28478         -1,
  28479     },
  28480 #endif /* chips */
  28481 
  28482 #if defined(BCM_88470_A0)
  28483     { /* SOC_REG_INT_GPORT_TPID_BCM88470_A0r */
  28484         soc_block_list[2],
  28485         soc_genreg,
  28486         1,
  28487         0,
  28488         0x2022100,
  28489         0,
  28490         0,
  28491         1,
  28492         soc_GPORT_TPID_BCM88470_A0r_fields,
  28493         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28494         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28495         -1,
  28496         -1,
  28497     },
  28498 #endif /* chips */
  28499 
  28500 #if defined(BCM_88470_B0)
  28501     { /* SOC_REG_INT_GPORT_TPID_BCM88470_B0r */
  28502         soc_block_list[2],
  28503         soc_genreg,
  28504         1,
  28505         0,
  28506         0x2022100,
  28507         0,
  28508         0,
  28509         1,
  28510         soc_GPORT_TPID_BCM88470_B0r_fields,
  28511         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28512         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28513         -1,
  28514         -1,
  28515     },
  28516 #endif /* chips */
  28517 
  28518 #if defined(BCM_88675_A0)
  28519     { /* SOC_REG_INT_GPORT_TPID_BCM88675_A0r */
  28520         soc_block_list[2],
  28521         soc_genreg,
  28522         1,
  28523         0,
  28524         0x2022100,
  28525         0,
  28526         0,
  28527         1,
  28528         soc_GPORT_TPID_BCM88675_A0r_fields,
  28529         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28530         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28531         -1,
  28532         -1,
  28533     },
  28534 #endif /* chips */
  28535 
  28536 #if defined(BCM_88675_B0)
  28537     { /* SOC_REG_INT_GPORT_TPID_BCM88675_B0r */
  28538         soc_block_list[2],
  28539         soc_genreg,
  28540         1,
  28541         0,
  28542         0x2022100,
  28543         0,
  28544         0,
  28545         1,
  28546         soc_GPORT_TPID_BCM88675_B0r_fields,
  28547         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28548         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28549         -1,
  28550         -1,
  28551     },
  28552 #endif /* chips */
  28553 
  28554 #if defined(BCM_88680_A0)
  28555     { /* SOC_REG_INT_GPORT_TPID_BCM88680_A0r */
  28556         soc_block_list[2],
  28557         soc_genreg,
  28558         1,
  28559         0,
  28560         0x2022100,
  28561         0,
  28562         0,
  28563         1,
  28564         soc_GPORT_TPID_BCM88680_A0r_fields,
  28565         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
  28566         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28567         -1,
  28568         -1,
  28569     },
  28570 #endif /* chips */
  28571 
  28572 #if defined(BCM_88675_A0)
  28573     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REGr */
  28574         soc_block_list[2],
  28575         soc_genreg,
  28576         1,
  28577         0,
  28578         0x2020300,
  28579         0,
  28580         0,
  28581         1,
  28582         soc_GPORT_TS_TIMER_31_0_REGr_fields,
  28583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28584         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28585         -1,
  28586         -1,
  28587     },
  28588 #endif /* chips */
  28589 
  28590 #if defined(BCM_53400_A0)
  28591     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r */
  28592         soc_block_list[9],
  28593         soc_genreg,
  28594         1,
  28595         0,
  28596         0x2020300,
  28597         0,
  28598         0,
  28599         1,
  28600         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  28601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28602         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28603         -1,
  28604         -1,
  28605     },
  28606 #endif /* chips */
  28607 
  28608 #if defined(BCM_53540_A0)
  28609     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM53540_A0r */
  28610         soc_block_list[2],
  28611         soc_genreg,
  28612         1,
  28613         0,
  28614         0x2020300,
  28615         0,
  28616         0,
  28617         1,
  28618         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  28619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28620         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28621         -1,
  28622         -1,
  28623     },
  28624 #endif /* chips */
  28625 
  28626 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  28627     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM53570_A0r */
  28628         soc_block_list[2],
  28629         soc_genreg,
  28630         1,
  28631         0,
  28632         0x2020300,
  28633         0,
  28634         0,
  28635         1,
  28636         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  28637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28638         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28639         -1,
  28640         -1,
  28641     },
  28642 #endif /* chips */
  28643 
  28644 #if defined(BCM_56150_A0)
  28645     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM56150_A0r */
  28646         soc_block_list[2],
  28647         soc_genreg,
  28648         1,
  28649         0,
  28650         0x2020300,
  28651         0,
  28652         0,
  28653         1,
  28654         soc_GPORT_TS_TIMER_31_0_REG_BCM56150_A0r_fields,
  28655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28656         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28657         -1,
  28658         -1,
  28659     },
  28660 #endif /* chips */
  28661 
  28662 #if defined(BCM_56160_A0)
  28663     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM56160_A0r */
  28664         soc_block_list[2],
  28665         soc_genreg,
  28666         1,
  28667         0,
  28668         0x2020300,
  28669         0,
  28670         0,
  28671         1,
  28672         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  28673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28674         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28675         -1,
  28676         -1,
  28677     },
  28678 #endif /* chips */
  28679 
  28680 #if defined(BCM_56370_A0)
  28681     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM56370_A0r */
  28682         soc_block_list[9],
  28683         soc_genreg,
  28684         1,
  28685         0,
  28686         0x2020300,
  28687         0,
  28688         0,
  28689         1,
  28690         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  28691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28692         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28693         -1,
  28694         -1,
  28695         3,
  28696     },
  28697 #endif /* chips */
  28698 
  28699 #if defined(BCM_88375_A0)
  28700     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM88375_A0r */
  28701         soc_block_list[2],
  28702         soc_genreg,
  28703         1,
  28704         0,
  28705         0x2020300,
  28706         0,
  28707         0,
  28708         1,
  28709         soc_GPORT_TS_TIMER_31_0_REG_BCM88375_A0r_fields,
  28710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28711         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28712         -1,
  28713         -1,
  28714     },
  28715 #endif /* chips */
  28716 
  28717 #if defined(BCM_88375_B0)
  28718     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM88375_B0r */
  28719         soc_block_list[2],
  28720         soc_genreg,
  28721         1,
  28722         0,
  28723         0x2020300,
  28724         0,
  28725         0,
  28726         1,
  28727         soc_GPORT_TS_TIMER_31_0_REG_BCM88375_B0r_fields,
  28728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28729         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28730         -1,
  28731         -1,
  28732     },
  28733 #endif /* chips */
  28734 
  28735 #if defined(BCM_88470_A0)
  28736     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM88470_A0r */
  28737         soc_block_list[2],
  28738         soc_genreg,
  28739         1,
  28740         0,
  28741         0x2020300,
  28742         0,
  28743         0,
  28744         1,
  28745         soc_GPORT_TS_TIMER_31_0_REG_BCM88470_A0r_fields,
  28746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28747         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28748         -1,
  28749         -1,
  28750     },
  28751 #endif /* chips */
  28752 
  28753 #if defined(BCM_88470_B0)
  28754     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM88470_B0r */
  28755         soc_block_list[2],
  28756         soc_genreg,
  28757         1,
  28758         0,
  28759         0x2020300,
  28760         0,
  28761         0,
  28762         1,
  28763         soc_GPORT_TS_TIMER_31_0_REG_BCM88470_B0r_fields,
  28764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28765         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28766         -1,
  28767         -1,
  28768     },
  28769 #endif /* chips */
  28770 
  28771 #if defined(BCM_88675_B0)
  28772     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM88675_B0r */
  28773         soc_block_list[2],
  28774         soc_genreg,
  28775         1,
  28776         0,
  28777         0x2020300,
  28778         0,
  28779         0,
  28780         1,
  28781         soc_GPORT_TS_TIMER_31_0_REG_BCM88675_B0r_fields,
  28782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28783         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28784         -1,
  28785         -1,
  28786     },
  28787 #endif /* chips */
  28788 
  28789 #if defined(BCM_88680_A0)
  28790     { /* SOC_REG_INT_GPORT_TS_TIMER_31_0_REG_BCM88680_A0r */
  28791         soc_block_list[2],
  28792         soc_genreg,
  28793         1,
  28794         0,
  28795         0x2020300,
  28796         0,
  28797         0,
  28798         1,
  28799         soc_GPORT_TS_TIMER_31_0_REG_BCM88680_A0r_fields,
  28800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28801         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28802         -1,
  28803         -1,
  28804     },
  28805 #endif /* chips */
  28806 
  28807 #if defined(BCM_88675_A0)
  28808     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REGr */
  28809         soc_block_list[2],
  28810         soc_genreg,
  28811         1,
  28812         0,
  28813         0x2020200,
  28814         0,
  28815         0,
  28816         1,
  28817         soc_GPORT_TS_TIMER_47_32_REGr_fields,
  28818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28819         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28820         -1,
  28821         -1,
  28822     },
  28823 #endif /* chips */
  28824 
  28825 #if defined(BCM_53400_A0)
  28826     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r */
  28827         soc_block_list[9],
  28828         soc_genreg,
  28829         1,
  28830         0,
  28831         0x2020200,
  28832         0,
  28833         0,
  28834         1,
  28835         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  28836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28838         -1,
  28839         -1,
  28840     },
  28841 #endif /* chips */
  28842 
  28843 #if defined(BCM_53540_A0)
  28844     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM53540_A0r */
  28845         soc_block_list[2],
  28846         soc_genreg,
  28847         1,
  28848         0,
  28849         0x2020200,
  28850         0,
  28851         0,
  28852         1,
  28853         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  28854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28855         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28856         -1,
  28857         -1,
  28858     },
  28859 #endif /* chips */
  28860 
  28861 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  28862     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM53570_A0r */
  28863         soc_block_list[2],
  28864         soc_genreg,
  28865         1,
  28866         0,
  28867         0x2020200,
  28868         0,
  28869         0,
  28870         1,
  28871         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  28872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28874         -1,
  28875         -1,
  28876     },
  28877 #endif /* chips */
  28878 
  28879 #if defined(BCM_56150_A0)
  28880     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM56150_A0r */
  28881         soc_block_list[2],
  28882         soc_genreg,
  28883         1,
  28884         0,
  28885         0x2020200,
  28886         0,
  28887         0,
  28888         1,
  28889         soc_GPORT_TS_TIMER_47_32_REG_BCM56150_A0r_fields,
  28890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28892         -1,
  28893         -1,
  28894     },
  28895 #endif /* chips */
  28896 
  28897 #if defined(BCM_56160_A0)
  28898     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM56160_A0r */
  28899         soc_block_list[2],
  28900         soc_genreg,
  28901         1,
  28902         0,
  28903         0x2020200,
  28904         0,
  28905         0,
  28906         1,
  28907         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  28908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28909         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28910         -1,
  28911         -1,
  28912     },
  28913 #endif /* chips */
  28914 
  28915 #if defined(BCM_56370_A0)
  28916     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM56370_A0r */
  28917         soc_block_list[9],
  28918         soc_genreg,
  28919         1,
  28920         0,
  28921         0x2020200,
  28922         0,
  28923         0,
  28924         1,
  28925         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  28926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28927         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28928         -1,
  28929         -1,
  28930         3,
  28931     },
  28932 #endif /* chips */
  28933 
  28934 #if defined(BCM_88375_A0)
  28935     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM88375_A0r */
  28936         soc_block_list[2],
  28937         soc_genreg,
  28938         1,
  28939         0,
  28940         0x2020200,
  28941         0,
  28942         0,
  28943         1,
  28944         soc_GPORT_TS_TIMER_47_32_REG_BCM88375_A0r_fields,
  28945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28946         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28947         -1,
  28948         -1,
  28949     },
  28950 #endif /* chips */
  28951 
  28952 #if defined(BCM_88375_B0)
  28953     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM88375_B0r */
  28954         soc_block_list[2],
  28955         soc_genreg,
  28956         1,
  28957         0,
  28958         0x2020200,
  28959         0,
  28960         0,
  28961         1,
  28962         soc_GPORT_TS_TIMER_47_32_REG_BCM88375_B0r_fields,
  28963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28964         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28965         -1,
  28966         -1,
  28967     },
  28968 #endif /* chips */
  28969 
  28970 #if defined(BCM_88470_A0)
  28971     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM88470_A0r */
  28972         soc_block_list[2],
  28973         soc_genreg,
  28974         1,
  28975         0,
  28976         0x2020200,
  28977         0,
  28978         0,
  28979         1,
  28980         soc_GPORT_TS_TIMER_47_32_REG_BCM88470_A0r_fields,
  28981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28982         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28983         -1,
  28984         -1,
  28985     },
  28986 #endif /* chips */
  28987 
  28988 #if defined(BCM_88470_B0)
  28989     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM88470_B0r */
  28990         soc_block_list[2],
  28991         soc_genreg,
  28992         1,
  28993         0,
  28994         0x2020200,
  28995         0,
  28996         0,
  28997         1,
  28998         soc_GPORT_TS_TIMER_47_32_REG_BCM88470_B0r_fields,
  28999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29000         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29001         -1,
  29002         -1,
  29003     },
  29004 #endif /* chips */
  29005 
  29006 #if defined(BCM_88675_B0)
  29007     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM88675_B0r */
  29008         soc_block_list[2],
  29009         soc_genreg,
  29010         1,
  29011         0,
  29012         0x2020200,
  29013         0,
  29014         0,
  29015         1,
  29016         soc_GPORT_TS_TIMER_47_32_REG_BCM88675_B0r_fields,
  29017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29018         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29019         -1,
  29020         -1,
  29021     },
  29022 #endif /* chips */
  29023 
  29024 #if defined(BCM_88680_A0)
  29025     { /* SOC_REG_INT_GPORT_TS_TIMER_47_32_REG_BCM88680_A0r */
  29026         soc_block_list[2],
  29027         soc_genreg,
  29028         1,
  29029         0,
  29030         0x2020200,
  29031         0,
  29032         0,
  29033         1,
  29034         soc_GPORT_TS_TIMER_47_32_REG_BCM88680_A0r_fields,
  29035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29036         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29037         -1,
  29038         -1,
  29039     },
  29040 #endif /* chips */
  29041 
  29042 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  29043     { /* SOC_REG_INT_GPORT_TXFIFO_ECC_DBE_STATUSr */
  29044         soc_block_list[2],
  29045         soc_genreg,
  29046         1,
  29047         0,
  29048         0x2022b00,
  29049         0,
  29050         0,
  29051         4,
  29052         soc_EGR_INITBUF_ECC_STATUS_DBE_BCM53400_A0r_fields,
  29053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29054         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29055         -1,
  29056         -1,
  29057     },
  29058 #endif /* chips */
  29059 
  29060 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  29061     { /* SOC_REG_INT_GPORT_TXFIFO_ECC_SBE_STATUSr */
  29062         soc_block_list[2],
  29063         soc_genreg,
  29064         1,
  29065         0,
  29066         0x2022a00,
  29067         0,
  29068         0,
  29069         4,
  29070         soc_EGR_INITBUF_ECC_STATUS_DBE_BCM53400_A0r_fields,
  29071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29072         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29073         -1,
  29074         -1,
  29075     },
  29076 #endif /* chips */
  29077 
  29078 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  29079     { /* SOC_REG_INT_GPORT_TX_EEE_LPI_DURATION_COUNTERr */
  29080         soc_block_list[2],
  29081         soc_portreg,
  29082         1,
  29083         0,
  29084         0xc1,
  29085         SOC_REG_FLAG_COUNTER,
  29086         0,
  29087         1,
  29088         soc_GR1023r_fields,
  29089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29091         232,
  29092         -1,
  29093     },
  29094 #endif /* chips */
  29095 
  29096 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  29097     { /* SOC_REG_INT_GPORT_TX_EEE_LPI_EVENT_COUNTERr */
  29098         soc_block_list[2],
  29099         soc_portreg,
  29100         1,
  29101         0,
  29102         0xc0,
  29103         SOC_REG_FLAG_COUNTER,
  29104         0,
  29105         1,
  29106         soc_GR1023r_fields,
  29107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29109         231,
  29110         -1,
  29111     },
  29112 #endif /* chips */
  29113 
  29114 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  29115     { /* SOC_REG_INT_GPORT_UMAC_CONTROLr */
  29116         soc_block_list[2],
  29117         soc_genreg,
  29118         1,
  29119         0,
  29120         0x80049,
  29121         0,
  29122         0,
  29123         9,
  29124         soc_GPORT_UMAC_CONTROLr_fields,
  29125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29126         SOC_RESET_MASK_DEC(0xffffff00, 0x00000000)
  29127         -1,
  29128         -1,
  29129     },
  29130 #endif /* chips */
  29131 
  29132 #if defined(BCM_56160_A0)
  29133     { /* SOC_REG_INT_GPORT_WC_UCMEM_CTRLr */
  29134         soc_block_list[71],
  29135         soc_genreg,
  29136         1,
  29137         0,
  29138         0x2020500,
  29139         0,
  29140         0,
  29141         2,
  29142         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  29143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29144         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  29145         -1,
  29146         -1,
  29147     },
  29148 #endif /* chips */
  29149 
  29150 #if defined(BCM_53540_A0)
  29151     { /* SOC_REG_INT_GPORT_WC_UCMEM_CTRL_BCM53540_A0r */
  29152         soc_block_list[71],
  29153         soc_genreg,
  29154         1,
  29155         0,
  29156         0x2020500,
  29157         0,
  29158         0,
  29159         2,
  29160         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  29161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29162         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  29163         -1,
  29164         -1,
  29165     },
  29166 #endif /* chips */
  29167 
  29168 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  29169     { /* SOC_REG_INT_GPORT_WC_UCMEM_CTRL_BCM53570_A0r */
  29170         soc_block_list[71],
  29171         soc_genreg,
  29172         1,
  29173         0,
  29174         0x2020500,
  29175         0,
  29176         0,
  29177         2,
  29178         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  29179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29180         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  29181         -1,
  29182         -1,
  29183     },
  29184 #endif /* chips */
  29185 
  29186 #if defined(BCM_56160_A0)
  29187     { /* SOC_REG_INT_GPORT_XGXS0_CTRL_REGr */
  29188         soc_block_list[71],
  29189         soc_genreg,
  29190         1,
  29191         0,
  29192         0x2020000,
  29193         0,
  29194         0,
  29195         9,
  29196         soc_GPORT_XGXS0_CTRL_REGr_fields,
  29197         SOC_RESET_VAL_DEC(0x000000a0, 0x00000000)
  29198         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  29199         -1,
  29200         -1,
  29201     },
  29202 #endif /* chips */
  29203 
  29204 #if defined(BCM_53540_A0)
  29205     { /* SOC_REG_INT_GPORT_XGXS0_CTRL_REG_BCM53540_A0r */
  29206         soc_block_list[71],
  29207         soc_genreg,
  29208         1,
  29209         0,
  29210         0x2020000,
  29211         0,
  29212         0,
  29213         9,
  29214         soc_GPORT_XGXS0_CTRL_REGr_fields,
  29215         SOC_RESET_VAL_DEC(0x000000a0, 0x00000000)
  29216         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  29217         -1,
  29218         -1,
  29219     },
  29220 #endif /* chips */
  29221 
  29222 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  29223     { /* SOC_REG_INT_GPORT_XGXS0_CTRL_REG_BCM53570_A0r */
  29224         soc_block_list[71],
  29225         soc_genreg,
  29226         1,
  29227         0,
  29228         0x2020000,
  29229         0,
  29230         0,
  29231         9,
  29232         soc_GPORT_XGXS0_CTRL_REGr_fields,
  29233         SOC_RESET_VAL_DEC(0x000000a0, 0x00000000)
  29234         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  29235         -1,
  29236         -1,
  29237     },
  29238 #endif /* chips */
  29239 
  29240 #if defined(BCM_56160_A0)
  29241     { /* SOC_REG_INT_GPORT_XGXS0_LN0_STATUS0_REGr */
  29242         soc_block_list[71],
  29243         soc_genreg,
  29244         1,
  29245         0,
  29246         0x2020100,
  29247         SOC_REG_FLAG_RO,
  29248         0,
  29249         2,
  29250         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29252         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29253         -1,
  29254         -1,
  29255     },
  29256 #endif /* chips */
  29257 
  29258 #if defined(BCM_53540_A0)
  29259     { /* SOC_REG_INT_GPORT_XGXS0_LN0_STATUS0_REG_BCM53540_A0r */
  29260         soc_block_list[71],
  29261         soc_genreg,
  29262         1,
  29263         0,
  29264         0x2020100,
  29265         SOC_REG_FLAG_RO,
  29266         0,
  29267         2,
  29268         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29270         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29271         -1,
  29272         -1,
  29273     },
  29274 #endif /* chips */
  29275 
  29276 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  29277     { /* SOC_REG_INT_GPORT_XGXS0_LN0_STATUS0_REG_BCM53570_A0r */
  29278         soc_block_list[71],
  29279         soc_genreg,
  29280         1,
  29281         0,
  29282         0x2020100,
  29283         SOC_REG_FLAG_RO,
  29284         0,
  29285         2,
  29286         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29288         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29289         -1,
  29290         -1,
  29291     },
  29292 #endif /* chips */
  29293 
  29294 #if defined(BCM_56160_A0)
  29295     { /* SOC_REG_INT_GPORT_XGXS0_LN1_STATUS0_REGr */
  29296         soc_block_list[71],
  29297         soc_genreg,
  29298         1,
  29299         0,
  29300         0x2020200,
  29301         SOC_REG_FLAG_RO,
  29302         0,
  29303         2,
  29304         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29307         -1,
  29308         -1,
  29309     },
  29310 #endif /* chips */
  29311 
  29312 #if defined(BCM_53540_A0)
  29313     { /* SOC_REG_INT_GPORT_XGXS0_LN1_STATUS0_REG_BCM53540_A0r */
  29314         soc_block_list[71],
  29315         soc_genreg,
  29316         1,
  29317         0,
  29318         0x2020200,
  29319         SOC_REG_FLAG_RO,
  29320         0,
  29321         2,
  29322         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29324         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29325         -1,
  29326         -1,
  29327     },
  29328 #endif /* chips */
  29329 
  29330 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  29331     { /* SOC_REG_INT_GPORT_XGXS0_LN1_STATUS0_REG_BCM53570_A0r */
  29332         soc_block_list[71],
  29333         soc_genreg,
  29334         1,
  29335         0,
  29336         0x2020200,
  29337         SOC_REG_FLAG_RO,
  29338         0,
  29339         2,
  29340         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29342         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29343         -1,
  29344         -1,
  29345     },
  29346 #endif /* chips */
  29347 
  29348 #if defined(BCM_56160_A0)
  29349     { /* SOC_REG_INT_GPORT_XGXS0_LN2_STATUS0_REGr */
  29350         soc_block_list[71],
  29351         soc_genreg,
  29352         1,
  29353         0,
  29354         0x2020300,
  29355         SOC_REG_FLAG_RO,
  29356         0,
  29357         2,
  29358         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29360         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29361         -1,
  29362         -1,
  29363     },
  29364 #endif /* chips */
  29365 
  29366 #if defined(BCM_53540_A0)
  29367     { /* SOC_REG_INT_GPORT_XGXS0_LN2_STATUS0_REG_BCM53540_A0r */
  29368         soc_block_list[71],
  29369         soc_genreg,
  29370         1,
  29371         0,
  29372         0x2020300,
  29373         SOC_REG_FLAG_RO,
  29374         0,
  29375         2,
  29376         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29378         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29379         -1,
  29380         -1,
  29381     },
  29382 #endif /* chips */
  29383 
  29384 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  29385     { /* SOC_REG_INT_GPORT_XGXS0_LN2_STATUS0_REG_BCM53570_A0r */
  29386         soc_block_list[71],
  29387         soc_genreg,
  29388         1,
  29389         0,
  29390         0x2020300,
  29391         SOC_REG_FLAG_RO,
  29392         0,
  29393         2,
  29394         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29397         -1,
  29398         -1,
  29399     },
  29400 #endif /* chips */
  29401 
  29402 #if defined(BCM_56160_A0)
  29403     { /* SOC_REG_INT_GPORT_XGXS0_LN3_STATUS0_REGr */
  29404         soc_block_list[71],
  29405         soc_genreg,
  29406         1,
  29407         0,
  29408         0x2020400,
  29409         SOC_REG_FLAG_RO,
  29410         0,
  29411         2,
  29412         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29414         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29415         -1,
  29416         -1,
  29417     },
  29418 #endif /* chips */
  29419 
  29420 #if defined(BCM_53540_A0)
  29421     { /* SOC_REG_INT_GPORT_XGXS0_LN3_STATUS0_REG_BCM53540_A0r */
  29422         soc_block_list[71],
  29423         soc_genreg,
  29424         1,
  29425         0,
  29426         0x2020400,
  29427         SOC_REG_FLAG_RO,
  29428         0,
  29429         2,
  29430         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29433         -1,
  29434         -1,
  29435     },
  29436 #endif /* chips */
  29437 
  29438 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  29439     { /* SOC_REG_INT_GPORT_XGXS0_LN3_STATUS0_REG_BCM53570_A0r */
  29440         soc_block_list[71],
  29441         soc_genreg,
  29442         1,
  29443         0,
  29444         0x2020400,
  29445         SOC_REG_FLAG_RO,
  29446         0,
  29447         2,
  29448         soc_GPORT_XGXS0_LN0_STATUS0_REGr_fields,
  29449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29450         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29451         -1,
  29452         -1,
  29453     },
  29454 #endif /* chips */
  29455 
  29456 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  29457     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  29458     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29459     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  29460     { /* SOC_REG_INT_GR64r */
  29461         soc_block_list[2],
  29462         soc_portreg,
  29463         1,
  29464         0,
  29465         0,
  29466         SOC_REG_FLAG_COUNTER,
  29467         0,
  29468         1,
  29469         soc_GR1023r_fields,
  29470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29472         34,
  29473         -1,
  29474     },
  29475 #endif /* chips */
  29476 
  29477 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  29478     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  29479     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29480     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  29481     { /* SOC_REG_INT_GR127r */
  29482         soc_block_list[2],
  29483         soc_portreg,
  29484         1,
  29485         0,
  29486         0x1,
  29487         SOC_REG_FLAG_COUNTER,
  29488         0,
  29489         1,
  29490         soc_GR1023r_fields,
  29491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29492         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29493         35,
  29494         -1,
  29495     },
  29496 #endif /* chips */
  29497 
  29498 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  29499     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  29500     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29501     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  29502     { /* SOC_REG_INT_GR255r */
  29503         soc_block_list[2],
  29504         soc_portreg,
  29505         1,
  29506         0,
  29507         0x2,
  29508         SOC_REG_FLAG_COUNTER,
  29509         0,
  29510         1,
  29511         soc_GR1023r_fields,
  29512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29514         36,
  29515         -1,
  29516     },
  29517 #endif /* chips */
  29518 
  29519 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  29520     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  29521     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29522     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  29523     { /* SOC_REG_INT_GR511r */
  29524         soc_block_list[2],
  29525         soc_portreg,
  29526         1,
  29527         0,
  29528         0x3,
  29529         SOC_REG_FLAG_COUNTER,
  29530         0,
  29531         1,
  29532         soc_GR1023r_fields,
  29533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29534         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29535         37,
  29536         -1,
  29537     },
  29538 #endif /* chips */
  29539 
  29540 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  29541     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  29542     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29543     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  29544     { /* SOC_REG_INT_GR1023r */
  29545         soc_block_list[2],
  29546         soc_portreg,
  29547         1,
  29548         0,
  29549         0x4,
  29550         SOC_REG_FLAG_COUNTER,
  29551         0,
  29552         1,
  29553         soc_GR1023r_fields,
  29554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29556         38,
  29557         -1,
  29558     },
  29559 #endif /* chips */
  29560 
  29561 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29562     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  29563     { /* SOC_REG_INT_GR1518r */
  29564         soc_block_list[2],
  29565         soc_portreg,
  29566         1,
  29567         0,
  29568         0x5,
  29569         SOC_REG_FLAG_COUNTER,
  29570         0,
  29571         1,
  29572         soc_GR1023r_fields,
  29573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29574         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29575         39,
  29576         -1,
  29577     },
  29578 #endif /* chips */
  29579 
  29580 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  29581     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  29582     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29583     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  29584     { /* SOC_REG_INT_GR2047r */
  29585         soc_block_list[2],
  29586         soc_portreg,
  29587         1,
  29588         0,
  29589         0x7,
  29590         SOC_REG_FLAG_COUNTER,
  29591         0,
  29592         1,
  29593         soc_GR1023r_fields,
  29594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29595         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29596         41,
  29597         -1,
  29598     },
  29599 #endif /* chips */
  29600 
  29601 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  29602     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  29603     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29604     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  29605     { /* SOC_REG_INT_GR4095r */
  29606         soc_block_list[2],
  29607         soc_portreg,
  29608         1,
  29609         0,
  29610         0x8,
  29611         SOC_REG_FLAG_COUNTER,
  29612         0,
  29613         1,
  29614         soc_GR1023r_fields,
  29615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29616         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29617         42,
  29618         -1,
  29619     },
  29620 #endif /* chips */
  29621 
  29622 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  29623     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  29624     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  29625     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  29626     { /* SOC_REG_INT_GR9216r */
  29627         soc_block_list[2],
  29628         soc_portreg,
  29629         1,
  29630         0,
  29631         0x9,
  29632         SOC_REG_FLAG_COUNTER,
  29633         0,
  29634         1,
  29635         soc_GR1023r_fields,
  29636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29637         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29638         43,
  29639         -1,
  29640     },
  29641 #endif /* chips */
  29642 
  29643 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  29644     { /* SOC_REG_INT_GR16383r */
  29645         soc_block_list[2],
  29646         soc_portreg,
  29647         1,
  29648         0,
  29649         0x9b,
  29650         SOC_REG_FLAG_COUNTER,
  29651         0,
  29652         1,
  29653         soc_GR1023r_fields,
  29654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29655         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29656         194,
  29657         -1,
  29658     },
  29659 #endif /* chips */
  29660 
  29661 #if defined(BCM_53570_A0)
  29662     { /* SOC_REG_INT_GR1023Pr */
  29663         soc_block_list[2],
  29664         soc_portreg,
  29665         1,
  29666         0,
  29667         0x7400,
  29668         SOC_REG_FLAG_COUNTER,
  29669         0,
  29670         1,
  29671         soc_GR1023_BCM53400_A0r_fields,
  29672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29673         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29674         270,
  29675         -1,
  29676     },
  29677 #endif /* chips */
  29678 
  29679 #if defined(BCM_53570_B0)
  29680     { /* SOC_REG_INT_GR1023P_BCM53570_B0r */
  29681         soc_block_list[2],
  29682         soc_portreg,
  29683         1,
  29684         0,
  29685         0x7400,
  29686         SOC_REG_FLAG_COUNTER,
  29687         0,
  29688         1,
  29689         soc_GR1023_BCM53400_A0r_fields,
  29690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29692         274,
  29693         -1,
  29694     },
  29695 #endif /* chips */
  29696 
  29697 #if defined(BCM_53400_A0)
  29698     { /* SOC_REG_INT_GR1023_BCM53400_A0r */
  29699         soc_block_list[9],
  29700         soc_portreg,
  29701         1,
  29702         0,
  29703         0x1500,
  29704         SOC_REG_FLAG_COUNTER,
  29705         0,
  29706         1,
  29707         soc_GR1023_BCM53400_A0r_fields,
  29708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29710         120,
  29711         -1,
  29712     },
  29713 #endif /* chips */
  29714 
  29715 #if defined(BCM_53540_A0)
  29716     { /* SOC_REG_INT_GR1023_BCM53540_A0r */
  29717         soc_block_list[2],
  29718         soc_portreg,
  29719         1,
  29720         0,
  29721         0x1500,
  29722         SOC_REG_FLAG_COUNTER,
  29723         0,
  29724         1,
  29725         soc_GR1023_BCM53400_A0r_fields,
  29726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29727         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29728         120,
  29729         -1,
  29730     },
  29731 #endif /* chips */
  29732 
  29733 #if defined(BCM_53570_A0)
  29734     { /* SOC_REG_INT_GR1023_BCM53570_A0r */
  29735         soc_block_list[2],
  29736         soc_portreg,
  29737         1,
  29738         0,
  29739         0x1500,
  29740         SOC_REG_FLAG_COUNTER,
  29741         0,
  29742         1,
  29743         soc_GR1023_BCM53400_A0r_fields,
  29744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29745         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29746         175,
  29747         -1,
  29748     },
  29749 #endif /* chips */
  29750 
  29751 #if defined(BCM_53570_B0)
  29752     { /* SOC_REG_INT_GR1023_BCM53570_B0r */
  29753         soc_block_list[2],
  29754         soc_portreg,
  29755         1,
  29756         0,
  29757         0x1500,
  29758         SOC_REG_FLAG_COUNTER,
  29759         0,
  29760         1,
  29761         soc_GR1023_BCM53400_A0r_fields,
  29762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29764         179,
  29765         -1,
  29766     },
  29767 #endif /* chips */
  29768 
  29769 #if defined(BCM_56142_A0)
  29770     { /* SOC_REG_INT_GR1023_BCM56142_A0r */
  29771         soc_block_list[210],
  29772         soc_portreg,
  29773         1,
  29774         0,
  29775         0x95,
  29776         SOC_REG_FLAG_COUNTER,
  29777         0,
  29778         1,
  29779         soc_GR1023r_fields,
  29780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29782         196,
  29783         -1,
  29784     },
  29785 #endif /* chips */
  29786 
  29787 #if defined(BCM_56150_A0)
  29788     { /* SOC_REG_INT_GR1023_BCM56150_A0r */
  29789         soc_block_list[2],
  29790         soc_portreg,
  29791         1,
  29792         0,
  29793         0x1500,
  29794         SOC_REG_FLAG_COUNTER,
  29795         0,
  29796         1,
  29797         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  29798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29800         116,
  29801         -1,
  29802     },
  29803 #endif /* chips */
  29804 
  29805 #if defined(BCM_56160_A0)
  29806     { /* SOC_REG_INT_GR1023_BCM56160_A0r */
  29807         soc_block_list[2],
  29808         soc_portreg,
  29809         1,
  29810         0,
  29811         0x1500,
  29812         SOC_REG_FLAG_COUNTER,
  29813         0,
  29814         1,
  29815         soc_GR1023_BCM53400_A0r_fields,
  29816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29818         120,
  29819         -1,
  29820     },
  29821 #endif /* chips */
  29822 
  29823 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  29824     { /* SOC_REG_INT_GR1023_BCM56334_A0r */
  29825         soc_block_list[210],
  29826         soc_portreg,
  29827         1,
  29828         0,
  29829         0x95,
  29830         SOC_REG_FLAG_COUNTER,
  29831         0,
  29832         1,
  29833         soc_GR1023r_fields,
  29834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29835         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29836         191,
  29837         -1,
  29838     },
  29839 #endif /* chips */
  29840 
  29841 #if defined(BCM_56370_A0)
  29842     { /* SOC_REG_INT_GR1023_BCM56370_A0r */
  29843         soc_block_list[9],
  29844         soc_portreg,
  29845         1,
  29846         0,
  29847         0x1500,
  29848         SOC_REG_FLAG_COUNTER,
  29849         0,
  29850         1,
  29851         soc_GR1023_BCM53400_A0r_fields,
  29852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29854         81,
  29855         -1,
  29856         3,
  29857     },
  29858 #endif /* chips */
  29859 
  29860 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  29861     { /* SOC_REG_INT_GR1023_BCM56440_A0r */
  29862         soc_block_list[2],
  29863         soc_portreg,
  29864         1,
  29865         0,
  29866         0x95,
  29867         SOC_REG_FLAG_COUNTER,
  29868         0,
  29869         1,
  29870         soc_GR1023r_fields,
  29871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29873         188,
  29874         -1,
  29875     },
  29876 #endif /* chips */
  29877 
  29878 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  29879     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  29880     { /* SOC_REG_INT_GR1023_BCM56624_A0r */
  29881         soc_block_list[205],
  29882         soc_portreg,
  29883         1,
  29884         0,
  29885         0x84,
  29886         SOC_REG_FLAG_COUNTER,
  29887         0,
  29888         1,
  29889         soc_GR1023r_fields,
  29890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29892         174,
  29893         -1,
  29894     },
  29895 #endif /* chips */
  29896 
  29897 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  29898     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  29899     { /* SOC_REG_INT_GR1023_BCM56634_A0r */
  29900         soc_block_list[207],
  29901         soc_portreg,
  29902         1,
  29903         0,
  29904         0x84,
  29905         SOC_REG_FLAG_COUNTER,
  29906         0,
  29907         1,
  29908         soc_GR1023r_fields,
  29909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29910         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29911         174,
  29912         -1,
  29913     },
  29914 #endif /* chips */
  29915 
  29916 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  29917     { /* SOC_REG_INT_GR1023_BCM56685_A0r */
  29918         soc_block_list[209],
  29919         soc_portreg,
  29920         1,
  29921         0,
  29922         0x84,
  29923         SOC_REG_FLAG_COUNTER,
  29924         0,
  29925         1,
  29926         soc_GR1023r_fields,
  29927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29928         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29929         174,
  29930         -1,
  29931     },
  29932 #endif /* chips */
  29933 
  29934 #if defined(BCM_56800_A0)
  29935     { /* SOC_REG_INT_GR1023_BCM56800_A0r */
  29936         soc_block_list[9],
  29937         soc_portreg,
  29938         1,
  29939         0,
  29940         0x4b,
  29941         SOC_REG_FLAG_COUNTER,
  29942         0,
  29943         1,
  29944         soc_GR1023r_fields,
  29945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29946         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29947         117,
  29948         -1,
  29949     },
  29950 #endif /* chips */
  29951 
  29952 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  29953     { /* SOC_REG_INT_GR1023_BCM56820_A0r */
  29954         soc_block_list[206],
  29955         soc_portreg,
  29956         1,
  29957         0,
  29958         0x84,
  29959         SOC_REG_FLAG_COUNTER,
  29960         0,
  29961         1,
  29962         soc_GR1023r_fields,
  29963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29964         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29965         184,
  29966         -1,
  29967     },
  29968 #endif /* chips */
  29969 
  29970 #if defined(BCM_88375_A0)
  29971     { /* SOC_REG_INT_GR1023_BCM88375_A0r */
  29972         soc_block_list[2],
  29973         soc_portreg,
  29974         1,
  29975         0,
  29976         0x1500,
  29977         SOC_REG_FLAG_COUNTER,
  29978         0,
  29979         1,
  29980         soc_GR1023_BCM88375_A0r_fields,
  29981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29982         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29983         21,
  29984         -1,
  29985     },
  29986 #endif /* chips */
  29987 
  29988 #if defined(BCM_88375_B0)
  29989     { /* SOC_REG_INT_GR1023_BCM88375_B0r */
  29990         soc_block_list[2],
  29991         soc_portreg,
  29992         1,
  29993         0,
  29994         0x1500,
  29995         SOC_REG_FLAG_COUNTER,
  29996         0,
  29997         1,
  29998         soc_GR1023_BCM88375_B0r_fields,
  29999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30000         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30001         21,
  30002         -1,
  30003     },
  30004 #endif /* chips */
  30005 
  30006 #if defined(BCM_88470_A0)
  30007     { /* SOC_REG_INT_GR1023_BCM88470_A0r */
  30008         soc_block_list[2],
  30009         soc_portreg,
  30010         1,
  30011         0,
  30012         0x1500,
  30013         SOC_REG_FLAG_COUNTER,
  30014         0,
  30015         1,
  30016         soc_GR1023_BCM88470_A0r_fields,
  30017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30018         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30019         21,
  30020         -1,
  30021     },
  30022 #endif /* chips */
  30023 
  30024 #if defined(BCM_88470_B0)
  30025     { /* SOC_REG_INT_GR1023_BCM88470_B0r */
  30026         soc_block_list[2],
  30027         soc_portreg,
  30028         1,
  30029         0,
  30030         0x1500,
  30031         SOC_REG_FLAG_COUNTER,
  30032         0,
  30033         1,
  30034         soc_GR1023_BCM88470_B0r_fields,
  30035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30037         21,
  30038         -1,
  30039     },
  30040 #endif /* chips */
  30041 
  30042 #if defined(BCM_88675_A0)
  30043     { /* SOC_REG_INT_GR1023_BCM88675_A0r */
  30044         soc_block_list[2],
  30045         soc_portreg,
  30046         1,
  30047         0,
  30048         0x1500,
  30049         SOC_REG_FLAG_COUNTER,
  30050         0,
  30051         1,
  30052         soc_GR1023_BCM88675_A0r_fields,
  30053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30054         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30055         21,
  30056         -1,
  30057     },
  30058 #endif /* chips */
  30059 
  30060 #if defined(BCM_88675_B0)
  30061     { /* SOC_REG_INT_GR1023_BCM88675_B0r */
  30062         soc_block_list[2],
  30063         soc_portreg,
  30064         1,
  30065         0,
  30066         0x1500,
  30067         SOC_REG_FLAG_COUNTER,
  30068         0,
  30069         1,
  30070         soc_GR1023_BCM88675_B0r_fields,
  30071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30072         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30073         21,
  30074         -1,
  30075     },
  30076 #endif /* chips */
  30077 
  30078 #if defined(BCM_88680_A0)
  30079     { /* SOC_REG_INT_GR1023_BCM88680_A0r */
  30080         soc_block_list[2],
  30081         soc_portreg,
  30082         1,
  30083         0,
  30084         0x1500,
  30085         SOC_REG_FLAG_COUNTER,
  30086         0,
  30087         1,
  30088         soc_GR1023_BCM88680_A0r_fields,
  30089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30090         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30091         21,
  30092         -1,
  30093     },
  30094 #endif /* chips */
  30095 
  30096 #if defined(BCM_53570_A0)
  30097     { /* SOC_REG_INT_GR127Pr */
  30098         soc_block_list[2],
  30099         soc_portreg,
  30100         1,
  30101         0,
  30102         0x7100,
  30103         SOC_REG_FLAG_COUNTER,
  30104         0,
  30105         1,
  30106         soc_GR1023_BCM53400_A0r_fields,
  30107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30109         267,
  30110         -1,
  30111     },
  30112 #endif /* chips */
  30113 
  30114 #if defined(BCM_53570_B0)
  30115     { /* SOC_REG_INT_GR127P_BCM53570_B0r */
  30116         soc_block_list[2],
  30117         soc_portreg,
  30118         1,
  30119         0,
  30120         0x7100,
  30121         SOC_REG_FLAG_COUNTER,
  30122         0,
  30123         1,
  30124         soc_GR1023_BCM53400_A0r_fields,
  30125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30126         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30127         271,
  30128         -1,
  30129     },
  30130 #endif /* chips */
  30131 
  30132 #if defined(BCM_53400_A0)
  30133     { /* SOC_REG_INT_GR127_BCM53400_A0r */
  30134         soc_block_list[9],
  30135         soc_portreg,
  30136         1,
  30137         0,
  30138         0x1200,
  30139         SOC_REG_FLAG_COUNTER,
  30140         0,
  30141         1,
  30142         soc_GR1023_BCM53400_A0r_fields,
  30143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30144         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30145         117,
  30146         -1,
  30147     },
  30148 #endif /* chips */
  30149 
  30150 #if defined(BCM_53540_A0)
  30151     { /* SOC_REG_INT_GR127_BCM53540_A0r */
  30152         soc_block_list[2],
  30153         soc_portreg,
  30154         1,
  30155         0,
  30156         0x1200,
  30157         SOC_REG_FLAG_COUNTER,
  30158         0,
  30159         1,
  30160         soc_GR1023_BCM53400_A0r_fields,
  30161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30163         117,
  30164         -1,
  30165     },
  30166 #endif /* chips */
  30167 
  30168 #if defined(BCM_53570_A0)
  30169     { /* SOC_REG_INT_GR127_BCM53570_A0r */
  30170         soc_block_list[2],
  30171         soc_portreg,
  30172         1,
  30173         0,
  30174         0x1200,
  30175         SOC_REG_FLAG_COUNTER,
  30176         0,
  30177         1,
  30178         soc_GR1023_BCM53400_A0r_fields,
  30179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30180         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30181         172,
  30182         -1,
  30183     },
  30184 #endif /* chips */
  30185 
  30186 #if defined(BCM_53570_B0)
  30187     { /* SOC_REG_INT_GR127_BCM53570_B0r */
  30188         soc_block_list[2],
  30189         soc_portreg,
  30190         1,
  30191         0,
  30192         0x1200,
  30193         SOC_REG_FLAG_COUNTER,
  30194         0,
  30195         1,
  30196         soc_GR1023_BCM53400_A0r_fields,
  30197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30198         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30199         176,
  30200         -1,
  30201     },
  30202 #endif /* chips */
  30203 
  30204 #if defined(BCM_56142_A0)
  30205     { /* SOC_REG_INT_GR127_BCM56142_A0r */
  30206         soc_block_list[210],
  30207         soc_portreg,
  30208         1,
  30209         0,
  30210         0x92,
  30211         SOC_REG_FLAG_COUNTER,
  30212         0,
  30213         1,
  30214         soc_GR1023r_fields,
  30215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30216         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30217         193,
  30218         -1,
  30219     },
  30220 #endif /* chips */
  30221 
  30222 #if defined(BCM_56150_A0)
  30223     { /* SOC_REG_INT_GR127_BCM56150_A0r */
  30224         soc_block_list[2],
  30225         soc_portreg,
  30226         1,
  30227         0,
  30228         0x1200,
  30229         SOC_REG_FLAG_COUNTER,
  30230         0,
  30231         1,
  30232         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  30233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30234         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30235         113,
  30236         -1,
  30237     },
  30238 #endif /* chips */
  30239 
  30240 #if defined(BCM_56160_A0)
  30241     { /* SOC_REG_INT_GR127_BCM56160_A0r */
  30242         soc_block_list[2],
  30243         soc_portreg,
  30244         1,
  30245         0,
  30246         0x1200,
  30247         SOC_REG_FLAG_COUNTER,
  30248         0,
  30249         1,
  30250         soc_GR1023_BCM53400_A0r_fields,
  30251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30252         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30253         117,
  30254         -1,
  30255     },
  30256 #endif /* chips */
  30257 
  30258 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  30259     { /* SOC_REG_INT_GR127_BCM56334_A0r */
  30260         soc_block_list[210],
  30261         soc_portreg,
  30262         1,
  30263         0,
  30264         0x92,
  30265         SOC_REG_FLAG_COUNTER,
  30266         0,
  30267         1,
  30268         soc_GR1023r_fields,
  30269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30270         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30271         188,
  30272         -1,
  30273     },
  30274 #endif /* chips */
  30275 
  30276 #if defined(BCM_56370_A0)
  30277     { /* SOC_REG_INT_GR127_BCM56370_A0r */
  30278         soc_block_list[9],
  30279         soc_portreg,
  30280         1,
  30281         0,
  30282         0x1200,
  30283         SOC_REG_FLAG_COUNTER,
  30284         0,
  30285         1,
  30286         soc_GR1023_BCM53400_A0r_fields,
  30287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30288         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30289         78,
  30290         -1,
  30291         3,
  30292     },
  30293 #endif /* chips */
  30294 
  30295 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  30296     { /* SOC_REG_INT_GR127_BCM56440_A0r */
  30297         soc_block_list[2],
  30298         soc_portreg,
  30299         1,
  30300         0,
  30301         0x92,
  30302         SOC_REG_FLAG_COUNTER,
  30303         0,
  30304         1,
  30305         soc_GR1023r_fields,
  30306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30308         185,
  30309         -1,
  30310     },
  30311 #endif /* chips */
  30312 
  30313 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  30314     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  30315     { /* SOC_REG_INT_GR127_BCM56624_A0r */
  30316         soc_block_list[205],
  30317         soc_portreg,
  30318         1,
  30319         0,
  30320         0x81,
  30321         SOC_REG_FLAG_COUNTER,
  30322         0,
  30323         1,
  30324         soc_GR1023r_fields,
  30325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30326         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30327         171,
  30328         -1,
  30329     },
  30330 #endif /* chips */
  30331 
  30332 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30333     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  30334     { /* SOC_REG_INT_GR127_BCM56634_A0r */
  30335         soc_block_list[207],
  30336         soc_portreg,
  30337         1,
  30338         0,
  30339         0x81,
  30340         SOC_REG_FLAG_COUNTER,
  30341         0,
  30342         1,
  30343         soc_GR1023r_fields,
  30344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30346         171,
  30347         -1,
  30348     },
  30349 #endif /* chips */
  30350 
  30351 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30352     { /* SOC_REG_INT_GR127_BCM56685_A0r */
  30353         soc_block_list[209],
  30354         soc_portreg,
  30355         1,
  30356         0,
  30357         0x81,
  30358         SOC_REG_FLAG_COUNTER,
  30359         0,
  30360         1,
  30361         soc_GR1023r_fields,
  30362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30364         171,
  30365         -1,
  30366     },
  30367 #endif /* chips */
  30368 
  30369 #if defined(BCM_56800_A0)
  30370     { /* SOC_REG_INT_GR127_BCM56800_A0r */
  30371         soc_block_list[9],
  30372         soc_portreg,
  30373         1,
  30374         0,
  30375         0x48,
  30376         SOC_REG_FLAG_COUNTER,
  30377         0,
  30378         1,
  30379         soc_GR1023r_fields,
  30380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30381         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30382         114,
  30383         -1,
  30384     },
  30385 #endif /* chips */
  30386 
  30387 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  30388     { /* SOC_REG_INT_GR127_BCM56820_A0r */
  30389         soc_block_list[206],
  30390         soc_portreg,
  30391         1,
  30392         0,
  30393         0x81,
  30394         SOC_REG_FLAG_COUNTER,
  30395         0,
  30396         1,
  30397         soc_GR1023r_fields,
  30398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30399         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30400         181,
  30401         -1,
  30402     },
  30403 #endif /* chips */
  30404 
  30405 #if defined(BCM_88375_A0)
  30406     { /* SOC_REG_INT_GR127_BCM88375_A0r */
  30407         soc_block_list[2],
  30408         soc_portreg,
  30409         1,
  30410         0,
  30411         0x1200,
  30412         SOC_REG_FLAG_COUNTER,
  30413         0,
  30414         1,
  30415         soc_GR127_BCM88375_A0r_fields,
  30416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30418         18,
  30419         -1,
  30420     },
  30421 #endif /* chips */
  30422 
  30423 #if defined(BCM_88375_B0)
  30424     { /* SOC_REG_INT_GR127_BCM88375_B0r */
  30425         soc_block_list[2],
  30426         soc_portreg,
  30427         1,
  30428         0,
  30429         0x1200,
  30430         SOC_REG_FLAG_COUNTER,
  30431         0,
  30432         1,
  30433         soc_GR127_BCM88375_B0r_fields,
  30434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30436         18,
  30437         -1,
  30438     },
  30439 #endif /* chips */
  30440 
  30441 #if defined(BCM_88470_A0)
  30442     { /* SOC_REG_INT_GR127_BCM88470_A0r */
  30443         soc_block_list[2],
  30444         soc_portreg,
  30445         1,
  30446         0,
  30447         0x1200,
  30448         SOC_REG_FLAG_COUNTER,
  30449         0,
  30450         1,
  30451         soc_GR127_BCM88470_A0r_fields,
  30452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30454         18,
  30455         -1,
  30456     },
  30457 #endif /* chips */
  30458 
  30459 #if defined(BCM_88470_B0)
  30460     { /* SOC_REG_INT_GR127_BCM88470_B0r */
  30461         soc_block_list[2],
  30462         soc_portreg,
  30463         1,
  30464         0,
  30465         0x1200,
  30466         SOC_REG_FLAG_COUNTER,
  30467         0,
  30468         1,
  30469         soc_GR127_BCM88470_B0r_fields,
  30470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30471         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30472         18,
  30473         -1,
  30474     },
  30475 #endif /* chips */
  30476 
  30477 #if defined(BCM_88675_A0)
  30478     { /* SOC_REG_INT_GR127_BCM88675_A0r */
  30479         soc_block_list[2],
  30480         soc_portreg,
  30481         1,
  30482         0,
  30483         0x1200,
  30484         SOC_REG_FLAG_COUNTER,
  30485         0,
  30486         1,
  30487         soc_GR127r_fields,
  30488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30490         18,
  30491         -1,
  30492     },
  30493 #endif /* chips */
  30494 
  30495 #if defined(BCM_88675_B0)
  30496     { /* SOC_REG_INT_GR127_BCM88675_B0r */
  30497         soc_block_list[2],
  30498         soc_portreg,
  30499         1,
  30500         0,
  30501         0x1200,
  30502         SOC_REG_FLAG_COUNTER,
  30503         0,
  30504         1,
  30505         soc_GR127_BCM88675_B0r_fields,
  30506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30508         18,
  30509         -1,
  30510     },
  30511 #endif /* chips */
  30512 
  30513 #if defined(BCM_88680_A0)
  30514     { /* SOC_REG_INT_GR127_BCM88680_A0r */
  30515         soc_block_list[2],
  30516         soc_portreg,
  30517         1,
  30518         0,
  30519         0x1200,
  30520         SOC_REG_FLAG_COUNTER,
  30521         0,
  30522         1,
  30523         soc_GR127_BCM88680_A0r_fields,
  30524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30526         18,
  30527         -1,
  30528     },
  30529 #endif /* chips */
  30530 
  30531 #if defined(BCM_53570_A0)
  30532     { /* SOC_REG_INT_GR1518Pr */
  30533         soc_block_list[2],
  30534         soc_portreg,
  30535         1,
  30536         0,
  30537         0x7500,
  30538         SOC_REG_FLAG_COUNTER,
  30539         0,
  30540         1,
  30541         soc_GR1023_BCM53400_A0r_fields,
  30542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30544         271,
  30545         -1,
  30546     },
  30547 #endif /* chips */
  30548 
  30549 #if defined(BCM_53570_B0)
  30550     { /* SOC_REG_INT_GR1518P_BCM53570_B0r */
  30551         soc_block_list[2],
  30552         soc_portreg,
  30553         1,
  30554         0,
  30555         0x7500,
  30556         SOC_REG_FLAG_COUNTER,
  30557         0,
  30558         1,
  30559         soc_GR1023_BCM53400_A0r_fields,
  30560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30562         275,
  30563         -1,
  30564     },
  30565 #endif /* chips */
  30566 
  30567 #if defined(BCM_53400_A0)
  30568     { /* SOC_REG_INT_GR1518_BCM53400_A0r */
  30569         soc_block_list[9],
  30570         soc_portreg,
  30571         1,
  30572         0,
  30573         0x1600,
  30574         SOC_REG_FLAG_COUNTER,
  30575         0,
  30576         1,
  30577         soc_GR1023_BCM53400_A0r_fields,
  30578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30580         121,
  30581         -1,
  30582     },
  30583 #endif /* chips */
  30584 
  30585 #if defined(BCM_53540_A0)
  30586     { /* SOC_REG_INT_GR1518_BCM53540_A0r */
  30587         soc_block_list[2],
  30588         soc_portreg,
  30589         1,
  30590         0,
  30591         0x1600,
  30592         SOC_REG_FLAG_COUNTER,
  30593         0,
  30594         1,
  30595         soc_GR1023_BCM53400_A0r_fields,
  30596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30598         121,
  30599         -1,
  30600     },
  30601 #endif /* chips */
  30602 
  30603 #if defined(BCM_53570_A0)
  30604     { /* SOC_REG_INT_GR1518_BCM53570_A0r */
  30605         soc_block_list[2],
  30606         soc_portreg,
  30607         1,
  30608         0,
  30609         0x1600,
  30610         SOC_REG_FLAG_COUNTER,
  30611         0,
  30612         1,
  30613         soc_GR1023_BCM53400_A0r_fields,
  30614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30616         176,
  30617         -1,
  30618     },
  30619 #endif /* chips */
  30620 
  30621 #if defined(BCM_53570_B0)
  30622     { /* SOC_REG_INT_GR1518_BCM53570_B0r */
  30623         soc_block_list[2],
  30624         soc_portreg,
  30625         1,
  30626         0,
  30627         0x1600,
  30628         SOC_REG_FLAG_COUNTER,
  30629         0,
  30630         1,
  30631         soc_GR1023_BCM53400_A0r_fields,
  30632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30634         180,
  30635         -1,
  30636     },
  30637 #endif /* chips */
  30638 
  30639 #if defined(BCM_56142_A0)
  30640     { /* SOC_REG_INT_GR1518_BCM56142_A0r */
  30641         soc_block_list[210],
  30642         soc_portreg,
  30643         1,
  30644         0,
  30645         0x96,
  30646         SOC_REG_FLAG_COUNTER,
  30647         0,
  30648         1,
  30649         soc_GR1023r_fields,
  30650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30652         197,
  30653         -1,
  30654     },
  30655 #endif /* chips */
  30656 
  30657 #if defined(BCM_56150_A0)
  30658     { /* SOC_REG_INT_GR1518_BCM56150_A0r */
  30659         soc_block_list[2],
  30660         soc_portreg,
  30661         1,
  30662         0,
  30663         0x1600,
  30664         SOC_REG_FLAG_COUNTER,
  30665         0,
  30666         1,
  30667         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  30668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30670         117,
  30671         -1,
  30672     },
  30673 #endif /* chips */
  30674 
  30675 #if defined(BCM_56160_A0)
  30676     { /* SOC_REG_INT_GR1518_BCM56160_A0r */
  30677         soc_block_list[2],
  30678         soc_portreg,
  30679         1,
  30680         0,
  30681         0x1600,
  30682         SOC_REG_FLAG_COUNTER,
  30683         0,
  30684         1,
  30685         soc_GR1023_BCM53400_A0r_fields,
  30686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30687         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30688         121,
  30689         -1,
  30690     },
  30691 #endif /* chips */
  30692 
  30693 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  30694     { /* SOC_REG_INT_GR1518_BCM56334_A0r */
  30695         soc_block_list[210],
  30696         soc_portreg,
  30697         1,
  30698         0,
  30699         0x96,
  30700         SOC_REG_FLAG_COUNTER,
  30701         0,
  30702         1,
  30703         soc_GR1023r_fields,
  30704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30706         192,
  30707         -1,
  30708     },
  30709 #endif /* chips */
  30710 
  30711 #if defined(BCM_56370_A0)
  30712     { /* SOC_REG_INT_GR1518_BCM56370_A0r */
  30713         soc_block_list[9],
  30714         soc_portreg,
  30715         1,
  30716         0,
  30717         0x1600,
  30718         SOC_REG_FLAG_COUNTER,
  30719         0,
  30720         1,
  30721         soc_GR1023_BCM53400_A0r_fields,
  30722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30724         82,
  30725         -1,
  30726         3,
  30727     },
  30728 #endif /* chips */
  30729 
  30730 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  30731     { /* SOC_REG_INT_GR1518_BCM56440_A0r */
  30732         soc_block_list[2],
  30733         soc_portreg,
  30734         1,
  30735         0,
  30736         0x96,
  30737         SOC_REG_FLAG_COUNTER,
  30738         0,
  30739         1,
  30740         soc_GR1023r_fields,
  30741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30742         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30743         189,
  30744         -1,
  30745     },
  30746 #endif /* chips */
  30747 
  30748 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  30749     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  30750     { /* SOC_REG_INT_GR1518_BCM56624_A0r */
  30751         soc_block_list[205],
  30752         soc_portreg,
  30753         1,
  30754         0,
  30755         0x85,
  30756         SOC_REG_FLAG_COUNTER,
  30757         0,
  30758         1,
  30759         soc_GR1023r_fields,
  30760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30762         175,
  30763         -1,
  30764     },
  30765 #endif /* chips */
  30766 
  30767 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  30768     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  30769     { /* SOC_REG_INT_GR1518_BCM56634_A0r */
  30770         soc_block_list[207],
  30771         soc_portreg,
  30772         1,
  30773         0,
  30774         0x85,
  30775         SOC_REG_FLAG_COUNTER,
  30776         0,
  30777         1,
  30778         soc_GR1023r_fields,
  30779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30781         175,
  30782         -1,
  30783     },
  30784 #endif /* chips */
  30785 
  30786 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  30787     { /* SOC_REG_INT_GR1518_BCM56685_A0r */
  30788         soc_block_list[209],
  30789         soc_portreg,
  30790         1,
  30791         0,
  30792         0x85,
  30793         SOC_REG_FLAG_COUNTER,
  30794         0,
  30795         1,
  30796         soc_GR1023r_fields,
  30797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30798         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30799         175,
  30800         -1,
  30801     },
  30802 #endif /* chips */
  30803 
  30804 #if defined(BCM_56800_A0)
  30805     { /* SOC_REG_INT_GR1518_BCM56800_A0r */
  30806         soc_block_list[9],
  30807         soc_portreg,
  30808         1,
  30809         0,
  30810         0x4c,
  30811         SOC_REG_FLAG_COUNTER,
  30812         0,
  30813         1,
  30814         soc_GR1023r_fields,
  30815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30816         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30817         118,
  30818         -1,
  30819     },
  30820 #endif /* chips */
  30821 
  30822 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  30823     { /* SOC_REG_INT_GR1518_BCM56820_A0r */
  30824         soc_block_list[206],
  30825         soc_portreg,
  30826         1,
  30827         0,
  30828         0x85,
  30829         SOC_REG_FLAG_COUNTER,
  30830         0,
  30831         1,
  30832         soc_GR1023r_fields,
  30833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30835         185,
  30836         -1,
  30837     },
  30838 #endif /* chips */
  30839 
  30840 #if defined(BCM_88375_A0)
  30841     { /* SOC_REG_INT_GR1518_BCM88375_A0r */
  30842         soc_block_list[2],
  30843         soc_portreg,
  30844         1,
  30845         0,
  30846         0x1600,
  30847         SOC_REG_FLAG_COUNTER,
  30848         0,
  30849         1,
  30850         soc_GR1518_BCM88375_A0r_fields,
  30851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30852         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30853         22,
  30854         -1,
  30855     },
  30856 #endif /* chips */
  30857 
  30858 #if defined(BCM_88375_B0)
  30859     { /* SOC_REG_INT_GR1518_BCM88375_B0r */
  30860         soc_block_list[2],
  30861         soc_portreg,
  30862         1,
  30863         0,
  30864         0x1600,
  30865         SOC_REG_FLAG_COUNTER,
  30866         0,
  30867         1,
  30868         soc_GR1518_BCM88375_B0r_fields,
  30869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30871         22,
  30872         -1,
  30873     },
  30874 #endif /* chips */
  30875 
  30876 #if defined(BCM_88470_A0)
  30877     { /* SOC_REG_INT_GR1518_BCM88470_A0r */
  30878         soc_block_list[2],
  30879         soc_portreg,
  30880         1,
  30881         0,
  30882         0x1600,
  30883         SOC_REG_FLAG_COUNTER,
  30884         0,
  30885         1,
  30886         soc_GR1518_BCM88470_A0r_fields,
  30887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30889         22,
  30890         -1,
  30891     },
  30892 #endif /* chips */
  30893 
  30894 #if defined(BCM_88470_B0)
  30895     { /* SOC_REG_INT_GR1518_BCM88470_B0r */
  30896         soc_block_list[2],
  30897         soc_portreg,
  30898         1,
  30899         0,
  30900         0x1600,
  30901         SOC_REG_FLAG_COUNTER,
  30902         0,
  30903         1,
  30904         soc_GR1518_BCM88470_B0r_fields,
  30905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30907         22,
  30908         -1,
  30909     },
  30910 #endif /* chips */
  30911 
  30912 #if defined(BCM_88675_A0)
  30913     { /* SOC_REG_INT_GR1518_BCM88675_A0r */
  30914         soc_block_list[2],
  30915         soc_portreg,
  30916         1,
  30917         0,
  30918         0x1600,
  30919         SOC_REG_FLAG_COUNTER,
  30920         0,
  30921         1,
  30922         soc_GR1518r_fields,
  30923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30925         22,
  30926         -1,
  30927     },
  30928 #endif /* chips */
  30929 
  30930 #if defined(BCM_88675_B0)
  30931     { /* SOC_REG_INT_GR1518_BCM88675_B0r */
  30932         soc_block_list[2],
  30933         soc_portreg,
  30934         1,
  30935         0,
  30936         0x1600,
  30937         SOC_REG_FLAG_COUNTER,
  30938         0,
  30939         1,
  30940         soc_GR1518_BCM88675_B0r_fields,
  30941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30943         22,
  30944         -1,
  30945     },
  30946 #endif /* chips */
  30947 
  30948 #if defined(BCM_88680_A0)
  30949     { /* SOC_REG_INT_GR1518_BCM88680_A0r */
  30950         soc_block_list[2],
  30951         soc_portreg,
  30952         1,
  30953         0,
  30954         0x1600,
  30955         SOC_REG_FLAG_COUNTER,
  30956         0,
  30957         1,
  30958         soc_GR1518_BCM88680_A0r_fields,
  30959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30960         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30961         22,
  30962         -1,
  30963     },
  30964 #endif /* chips */
  30965 
  30966 #if defined(BCM_53570_A0)
  30967     { /* SOC_REG_INT_GR2047Pr */
  30968         soc_block_list[2],
  30969         soc_portreg,
  30970         1,
  30971         0,
  30972         0x7700,
  30973         SOC_REG_FLAG_COUNTER,
  30974         0,
  30975         1,
  30976         soc_GR1023_BCM53400_A0r_fields,
  30977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30978         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30979         273,
  30980         -1,
  30981     },
  30982 #endif /* chips */
  30983 
  30984 #if defined(BCM_53570_B0)
  30985     { /* SOC_REG_INT_GR2047P_BCM53570_B0r */
  30986         soc_block_list[2],
  30987         soc_portreg,
  30988         1,
  30989         0,
  30990         0x7700,
  30991         SOC_REG_FLAG_COUNTER,
  30992         0,
  30993         1,
  30994         soc_GR1023_BCM53400_A0r_fields,
  30995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30996         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30997         277,
  30998         -1,
  30999     },
  31000 #endif /* chips */
  31001 
  31002 #if defined(BCM_53400_A0)
  31003     { /* SOC_REG_INT_GR2047_BCM53400_A0r */
  31004         soc_block_list[9],
  31005         soc_portreg,
  31006         1,
  31007         0,
  31008         0x1800,
  31009         SOC_REG_FLAG_COUNTER,
  31010         0,
  31011         1,
  31012         soc_GR1023_BCM53400_A0r_fields,
  31013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31014         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31015         123,
  31016         -1,
  31017     },
  31018 #endif /* chips */
  31019 
  31020 #if defined(BCM_53540_A0)
  31021     { /* SOC_REG_INT_GR2047_BCM53540_A0r */
  31022         soc_block_list[2],
  31023         soc_portreg,
  31024         1,
  31025         0,
  31026         0x1800,
  31027         SOC_REG_FLAG_COUNTER,
  31028         0,
  31029         1,
  31030         soc_GR1023_BCM53400_A0r_fields,
  31031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31032         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31033         123,
  31034         -1,
  31035     },
  31036 #endif /* chips */
  31037 
  31038 #if defined(BCM_53570_A0)
  31039     { /* SOC_REG_INT_GR2047_BCM53570_A0r */
  31040         soc_block_list[2],
  31041         soc_portreg,
  31042         1,
  31043         0,
  31044         0x1800,
  31045         SOC_REG_FLAG_COUNTER,
  31046         0,
  31047         1,
  31048         soc_GR1023_BCM53400_A0r_fields,
  31049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31050         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31051         178,
  31052         -1,
  31053     },
  31054 #endif /* chips */
  31055 
  31056 #if defined(BCM_53570_B0)
  31057     { /* SOC_REG_INT_GR2047_BCM53570_B0r */
  31058         soc_block_list[2],
  31059         soc_portreg,
  31060         1,
  31061         0,
  31062         0x1800,
  31063         SOC_REG_FLAG_COUNTER,
  31064         0,
  31065         1,
  31066         soc_GR1023_BCM53400_A0r_fields,
  31067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31068         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31069         182,
  31070         -1,
  31071     },
  31072 #endif /* chips */
  31073 
  31074 #if defined(BCM_56142_A0)
  31075     { /* SOC_REG_INT_GR2047_BCM56142_A0r */
  31076         soc_block_list[210],
  31077         soc_portreg,
  31078         1,
  31079         0,
  31080         0x98,
  31081         SOC_REG_FLAG_COUNTER,
  31082         0,
  31083         1,
  31084         soc_GR1023r_fields,
  31085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31086         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31087         199,
  31088         -1,
  31089     },
  31090 #endif /* chips */
  31091 
  31092 #if defined(BCM_56150_A0)
  31093     { /* SOC_REG_INT_GR2047_BCM56150_A0r */
  31094         soc_block_list[2],
  31095         soc_portreg,
  31096         1,
  31097         0,
  31098         0x1800,
  31099         SOC_REG_FLAG_COUNTER,
  31100         0,
  31101         1,
  31102         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  31103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31105         119,
  31106         -1,
  31107     },
  31108 #endif /* chips */
  31109 
  31110 #if defined(BCM_56160_A0)
  31111     { /* SOC_REG_INT_GR2047_BCM56160_A0r */
  31112         soc_block_list[2],
  31113         soc_portreg,
  31114         1,
  31115         0,
  31116         0x1800,
  31117         SOC_REG_FLAG_COUNTER,
  31118         0,
  31119         1,
  31120         soc_GR1023_BCM53400_A0r_fields,
  31121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31122         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31123         123,
  31124         -1,
  31125     },
  31126 #endif /* chips */
  31127 
  31128 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  31129     { /* SOC_REG_INT_GR2047_BCM56334_A0r */
  31130         soc_block_list[210],
  31131         soc_portreg,
  31132         1,
  31133         0,
  31134         0x98,
  31135         SOC_REG_FLAG_COUNTER,
  31136         0,
  31137         1,
  31138         soc_GR1023r_fields,
  31139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31141         194,
  31142         -1,
  31143     },
  31144 #endif /* chips */
  31145 
  31146 #if defined(BCM_56370_A0)
  31147     { /* SOC_REG_INT_GR2047_BCM56370_A0r */
  31148         soc_block_list[9],
  31149         soc_portreg,
  31150         1,
  31151         0,
  31152         0x1800,
  31153         SOC_REG_FLAG_COUNTER,
  31154         0,
  31155         1,
  31156         soc_GR1023_BCM53400_A0r_fields,
  31157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31159         84,
  31160         -1,
  31161         3,
  31162     },
  31163 #endif /* chips */
  31164 
  31165 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  31166     { /* SOC_REG_INT_GR2047_BCM56440_A0r */
  31167         soc_block_list[2],
  31168         soc_portreg,
  31169         1,
  31170         0,
  31171         0x98,
  31172         SOC_REG_FLAG_COUNTER,
  31173         0,
  31174         1,
  31175         soc_GR1023r_fields,
  31176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31178         191,
  31179         -1,
  31180     },
  31181 #endif /* chips */
  31182 
  31183 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  31184     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  31185     { /* SOC_REG_INT_GR2047_BCM56624_A0r */
  31186         soc_block_list[205],
  31187         soc_portreg,
  31188         1,
  31189         0,
  31190         0x87,
  31191         SOC_REG_FLAG_COUNTER,
  31192         0,
  31193         1,
  31194         soc_GR1023r_fields,
  31195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31196         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31197         177,
  31198         -1,
  31199     },
  31200 #endif /* chips */
  31201 
  31202 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  31203     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  31204     { /* SOC_REG_INT_GR2047_BCM56634_A0r */
  31205         soc_block_list[207],
  31206         soc_portreg,
  31207         1,
  31208         0,
  31209         0x87,
  31210         SOC_REG_FLAG_COUNTER,
  31211         0,
  31212         1,
  31213         soc_GR1023r_fields,
  31214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31215         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31216         177,
  31217         -1,
  31218     },
  31219 #endif /* chips */
  31220 
  31221 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  31222     { /* SOC_REG_INT_GR2047_BCM56685_A0r */
  31223         soc_block_list[209],
  31224         soc_portreg,
  31225         1,
  31226         0,
  31227         0x87,
  31228         SOC_REG_FLAG_COUNTER,
  31229         0,
  31230         1,
  31231         soc_GR1023r_fields,
  31232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31233         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31234         177,
  31235         -1,
  31236     },
  31237 #endif /* chips */
  31238 
  31239 #if defined(BCM_56800_A0)
  31240     { /* SOC_REG_INT_GR2047_BCM56800_A0r */
  31241         soc_block_list[9],
  31242         soc_portreg,
  31243         1,
  31244         0,
  31245         0x4e,
  31246         SOC_REG_FLAG_COUNTER,
  31247         0,
  31248         1,
  31249         soc_GR1023r_fields,
  31250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31252         120,
  31253         -1,
  31254     },
  31255 #endif /* chips */
  31256 
  31257 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  31258     { /* SOC_REG_INT_GR2047_BCM56820_A0r */
  31259         soc_block_list[206],
  31260         soc_portreg,
  31261         1,
  31262         0,
  31263         0x87,
  31264         SOC_REG_FLAG_COUNTER,
  31265         0,
  31266         1,
  31267         soc_GR1023r_fields,
  31268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31269         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31270         187,
  31271         -1,
  31272     },
  31273 #endif /* chips */
  31274 
  31275 #if defined(BCM_88375_A0)
  31276     { /* SOC_REG_INT_GR2047_BCM88375_A0r */
  31277         soc_block_list[2],
  31278         soc_portreg,
  31279         1,
  31280         0,
  31281         0x1800,
  31282         SOC_REG_FLAG_COUNTER,
  31283         0,
  31284         1,
  31285         soc_GR2047_BCM88375_A0r_fields,
  31286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31288         24,
  31289         -1,
  31290     },
  31291 #endif /* chips */
  31292 
  31293 #if defined(BCM_88375_B0)
  31294     { /* SOC_REG_INT_GR2047_BCM88375_B0r */
  31295         soc_block_list[2],
  31296         soc_portreg,
  31297         1,
  31298         0,
  31299         0x1800,
  31300         SOC_REG_FLAG_COUNTER,
  31301         0,
  31302         1,
  31303         soc_GR2047_BCM88375_B0r_fields,
  31304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31306         24,
  31307         -1,
  31308     },
  31309 #endif /* chips */
  31310 
  31311 #if defined(BCM_88470_A0)
  31312     { /* SOC_REG_INT_GR2047_BCM88470_A0r */
  31313         soc_block_list[2],
  31314         soc_portreg,
  31315         1,
  31316         0,
  31317         0x1800,
  31318         SOC_REG_FLAG_COUNTER,
  31319         0,
  31320         1,
  31321         soc_GR2047_BCM88470_A0r_fields,
  31322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31323         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31324         24,
  31325         -1,
  31326     },
  31327 #endif /* chips */
  31328 
  31329 #if defined(BCM_88470_B0)
  31330     { /* SOC_REG_INT_GR2047_BCM88470_B0r */
  31331         soc_block_list[2],
  31332         soc_portreg,
  31333         1,
  31334         0,
  31335         0x1800,
  31336         SOC_REG_FLAG_COUNTER,
  31337         0,
  31338         1,
  31339         soc_GR2047_BCM88470_B0r_fields,
  31340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31341         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31342         24,
  31343         -1,
  31344     },
  31345 #endif /* chips */
  31346 
  31347 #if defined(BCM_88675_A0)
  31348     { /* SOC_REG_INT_GR2047_BCM88675_A0r */
  31349         soc_block_list[2],
  31350         soc_portreg,
  31351         1,
  31352         0,
  31353         0x1800,
  31354         SOC_REG_FLAG_COUNTER,
  31355         0,
  31356         1,
  31357         soc_GR2047r_fields,
  31358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31359         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31360         24,
  31361         -1,
  31362     },
  31363 #endif /* chips */
  31364 
  31365 #if defined(BCM_88675_B0)
  31366     { /* SOC_REG_INT_GR2047_BCM88675_B0r */
  31367         soc_block_list[2],
  31368         soc_portreg,
  31369         1,
  31370         0,
  31371         0x1800,
  31372         SOC_REG_FLAG_COUNTER,
  31373         0,
  31374         1,
  31375         soc_GR2047_BCM88675_B0r_fields,
  31376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31377         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31378         24,
  31379         -1,
  31380     },
  31381 #endif /* chips */
  31382 
  31383 #if defined(BCM_88680_A0)
  31384     { /* SOC_REG_INT_GR2047_BCM88680_A0r */
  31385         soc_block_list[2],
  31386         soc_portreg,
  31387         1,
  31388         0,
  31389         0x1800,
  31390         SOC_REG_FLAG_COUNTER,
  31391         0,
  31392         1,
  31393         soc_GR2047_BCM88680_A0r_fields,
  31394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31395         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31396         24,
  31397         -1,
  31398     },
  31399 #endif /* chips */
  31400 
  31401 #if defined(BCM_53570_A0)
  31402     { /* SOC_REG_INT_GR255Pr */
  31403         soc_block_list[2],
  31404         soc_portreg,
  31405         1,
  31406         0,
  31407         0x7200,
  31408         SOC_REG_FLAG_COUNTER,
  31409         0,
  31410         1,
  31411         soc_GR1023_BCM53400_A0r_fields,
  31412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31413         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31414         268,
  31415         -1,
  31416     },
  31417 #endif /* chips */
  31418 
  31419 #if defined(BCM_53570_B0)
  31420     { /* SOC_REG_INT_GR255P_BCM53570_B0r */
  31421         soc_block_list[2],
  31422         soc_portreg,
  31423         1,
  31424         0,
  31425         0x7200,
  31426         SOC_REG_FLAG_COUNTER,
  31427         0,
  31428         1,
  31429         soc_GR1023_BCM53400_A0r_fields,
  31430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31431         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31432         272,
  31433         -1,
  31434     },
  31435 #endif /* chips */
  31436 
  31437 #if defined(BCM_53400_A0)
  31438     { /* SOC_REG_INT_GR255_BCM53400_A0r */
  31439         soc_block_list[9],
  31440         soc_portreg,
  31441         1,
  31442         0,
  31443         0x1300,
  31444         SOC_REG_FLAG_COUNTER,
  31445         0,
  31446         1,
  31447         soc_GR1023_BCM53400_A0r_fields,
  31448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31449         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31450         118,
  31451         -1,
  31452     },
  31453 #endif /* chips */
  31454 
  31455 #if defined(BCM_53540_A0)
  31456     { /* SOC_REG_INT_GR255_BCM53540_A0r */
  31457         soc_block_list[2],
  31458         soc_portreg,
  31459         1,
  31460         0,
  31461         0x1300,
  31462         SOC_REG_FLAG_COUNTER,
  31463         0,
  31464         1,
  31465         soc_GR1023_BCM53400_A0r_fields,
  31466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31467         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31468         118,
  31469         -1,
  31470     },
  31471 #endif /* chips */
  31472 
  31473 #if defined(BCM_53570_A0)
  31474     { /* SOC_REG_INT_GR255_BCM53570_A0r */
  31475         soc_block_list[2],
  31476         soc_portreg,
  31477         1,
  31478         0,
  31479         0x1300,
  31480         SOC_REG_FLAG_COUNTER,
  31481         0,
  31482         1,
  31483         soc_GR1023_BCM53400_A0r_fields,
  31484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31486         173,
  31487         -1,
  31488     },
  31489 #endif /* chips */
  31490 
  31491 #if defined(BCM_53570_B0)
  31492     { /* SOC_REG_INT_GR255_BCM53570_B0r */
  31493         soc_block_list[2],
  31494         soc_portreg,
  31495         1,
  31496         0,
  31497         0x1300,
  31498         SOC_REG_FLAG_COUNTER,
  31499         0,
  31500         1,
  31501         soc_GR1023_BCM53400_A0r_fields,
  31502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31503         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31504         177,
  31505         -1,
  31506     },
  31507 #endif /* chips */
  31508 
  31509 #if defined(BCM_56142_A0)
  31510     { /* SOC_REG_INT_GR255_BCM56142_A0r */
  31511         soc_block_list[210],
  31512         soc_portreg,
  31513         1,
  31514         0,
  31515         0x93,
  31516         SOC_REG_FLAG_COUNTER,
  31517         0,
  31518         1,
  31519         soc_GR1023r_fields,
  31520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31522         194,
  31523         -1,
  31524     },
  31525 #endif /* chips */
  31526 
  31527 #if defined(BCM_56150_A0)
  31528     { /* SOC_REG_INT_GR255_BCM56150_A0r */
  31529         soc_block_list[2],
  31530         soc_portreg,
  31531         1,
  31532         0,
  31533         0x1300,
  31534         SOC_REG_FLAG_COUNTER,
  31535         0,
  31536         1,
  31537         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  31538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31540         114,
  31541         -1,
  31542     },
  31543 #endif /* chips */
  31544 
  31545 #if defined(BCM_56160_A0)
  31546     { /* SOC_REG_INT_GR255_BCM56160_A0r */
  31547         soc_block_list[2],
  31548         soc_portreg,
  31549         1,
  31550         0,
  31551         0x1300,
  31552         SOC_REG_FLAG_COUNTER,
  31553         0,
  31554         1,
  31555         soc_GR1023_BCM53400_A0r_fields,
  31556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31558         118,
  31559         -1,
  31560     },
  31561 #endif /* chips */
  31562 
  31563 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  31564     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  31565     { /* SOC_REG_INT_GR255_BCM56224_A0r */
  31566         soc_block_list[2],
  31567         soc_portreg,
  31568         1,
  31569         0,
  31570         0x13,
  31571         SOC_REG_FLAG_COUNTER,
  31572         0,
  31573         1,
  31574         soc_GR1023r_fields,
  31575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31577         53,
  31578         -1,
  31579     },
  31580 #endif /* chips */
  31581 
  31582 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  31583     { /* SOC_REG_INT_GR255_BCM56334_A0r */
  31584         soc_block_list[210],
  31585         soc_portreg,
  31586         1,
  31587         0,
  31588         0x93,
  31589         SOC_REG_FLAG_COUNTER,
  31590         0,
  31591         1,
  31592         soc_GR1023r_fields,
  31593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31594         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31595         189,
  31596         -1,
  31597     },
  31598 #endif /* chips */
  31599 
  31600 #if defined(BCM_56370_A0)
  31601     { /* SOC_REG_INT_GR255_BCM56370_A0r */
  31602         soc_block_list[9],
  31603         soc_portreg,
  31604         1,
  31605         0,
  31606         0x1300,
  31607         SOC_REG_FLAG_COUNTER,
  31608         0,
  31609         1,
  31610         soc_GR1023_BCM53400_A0r_fields,
  31611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31613         79,
  31614         -1,
  31615         3,
  31616     },
  31617 #endif /* chips */
  31618 
  31619 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  31620     { /* SOC_REG_INT_GR255_BCM56440_A0r */
  31621         soc_block_list[2],
  31622         soc_portreg,
  31623         1,
  31624         0,
  31625         0x93,
  31626         SOC_REG_FLAG_COUNTER,
  31627         0,
  31628         1,
  31629         soc_GR1023r_fields,
  31630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31632         186,
  31633         -1,
  31634     },
  31635 #endif /* chips */
  31636 
  31637 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  31638     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  31639     { /* SOC_REG_INT_GR255_BCM56624_A0r */
  31640         soc_block_list[205],
  31641         soc_portreg,
  31642         1,
  31643         0,
  31644         0x82,
  31645         SOC_REG_FLAG_COUNTER,
  31646         0,
  31647         1,
  31648         soc_GR1023r_fields,
  31649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31650         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31651         172,
  31652         -1,
  31653     },
  31654 #endif /* chips */
  31655 
  31656 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  31657     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  31658     { /* SOC_REG_INT_GR255_BCM56634_A0r */
  31659         soc_block_list[207],
  31660         soc_portreg,
  31661         1,
  31662         0,
  31663         0x82,
  31664         SOC_REG_FLAG_COUNTER,
  31665         0,
  31666         1,
  31667         soc_GR1023r_fields,
  31668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31670         172,
  31671         -1,
  31672     },
  31673 #endif /* chips */
  31674 
  31675 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  31676     { /* SOC_REG_INT_GR255_BCM56685_A0r */
  31677         soc_block_list[209],
  31678         soc_portreg,
  31679         1,
  31680         0,
  31681         0x82,
  31682         SOC_REG_FLAG_COUNTER,
  31683         0,
  31684         1,
  31685         soc_GR1023r_fields,
  31686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31687         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31688         172,
  31689         -1,
  31690     },
  31691 #endif /* chips */
  31692 
  31693 #if defined(BCM_56800_A0)
  31694     { /* SOC_REG_INT_GR255_BCM56800_A0r */
  31695         soc_block_list[9],
  31696         soc_portreg,
  31697         1,
  31698         0,
  31699         0x49,
  31700         SOC_REG_FLAG_COUNTER,
  31701         0,
  31702         1,
  31703         soc_GR1023r_fields,
  31704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31706         115,
  31707         -1,
  31708     },
  31709 #endif /* chips */
  31710 
  31711 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  31712     { /* SOC_REG_INT_GR255_BCM56820_A0r */
  31713         soc_block_list[206],
  31714         soc_portreg,
  31715         1,
  31716         0,
  31717         0x82,
  31718         SOC_REG_FLAG_COUNTER,
  31719         0,
  31720         1,
  31721         soc_GR1023r_fields,
  31722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31724         182,
  31725         -1,
  31726     },
  31727 #endif /* chips */
  31728 
  31729 #if defined(BCM_88375_A0)
  31730     { /* SOC_REG_INT_GR255_BCM88375_A0r */
  31731         soc_block_list[2],
  31732         soc_portreg,
  31733         1,
  31734         0,
  31735         0x1300,
  31736         SOC_REG_FLAG_COUNTER,
  31737         0,
  31738         1,
  31739         soc_GR255_BCM88375_A0r_fields,
  31740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31742         19,
  31743         -1,
  31744     },
  31745 #endif /* chips */
  31746 
  31747 #if defined(BCM_88375_B0)
  31748     { /* SOC_REG_INT_GR255_BCM88375_B0r */
  31749         soc_block_list[2],
  31750         soc_portreg,
  31751         1,
  31752         0,
  31753         0x1300,
  31754         SOC_REG_FLAG_COUNTER,
  31755         0,
  31756         1,
  31757         soc_GR255_BCM88375_B0r_fields,
  31758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31760         19,
  31761         -1,
  31762     },
  31763 #endif /* chips */
  31764 
  31765 #if defined(BCM_88470_A0)
  31766     { /* SOC_REG_INT_GR255_BCM88470_A0r */
  31767         soc_block_list[2],
  31768         soc_portreg,
  31769         1,
  31770         0,
  31771         0x1300,
  31772         SOC_REG_FLAG_COUNTER,
  31773         0,
  31774         1,
  31775         soc_GR255_BCM88470_A0r_fields,
  31776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31778         19,
  31779         -1,
  31780     },
  31781 #endif /* chips */
  31782 
  31783 #if defined(BCM_88470_B0)
  31784     { /* SOC_REG_INT_GR255_BCM88470_B0r */
  31785         soc_block_list[2],
  31786         soc_portreg,
  31787         1,
  31788         0,
  31789         0x1300,
  31790         SOC_REG_FLAG_COUNTER,
  31791         0,
  31792         1,
  31793         soc_GR255_BCM88470_B0r_fields,
  31794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31796         19,
  31797         -1,
  31798     },
  31799 #endif /* chips */
  31800 
  31801 #if defined(BCM_88675_A0)
  31802     { /* SOC_REG_INT_GR255_BCM88675_A0r */
  31803         soc_block_list[2],
  31804         soc_portreg,
  31805         1,
  31806         0,
  31807         0x1300,
  31808         SOC_REG_FLAG_COUNTER,
  31809         0,
  31810         1,
  31811         soc_GR255r_fields,
  31812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31813         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31814         19,
  31815         -1,
  31816     },
  31817 #endif /* chips */
  31818 
  31819 #if defined(BCM_88675_B0)
  31820     { /* SOC_REG_INT_GR255_BCM88675_B0r */
  31821         soc_block_list[2],
  31822         soc_portreg,
  31823         1,
  31824         0,
  31825         0x1300,
  31826         SOC_REG_FLAG_COUNTER,
  31827         0,
  31828         1,
  31829         soc_GR255_BCM88675_B0r_fields,
  31830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31832         19,
  31833         -1,
  31834     },
  31835 #endif /* chips */
  31836 
  31837 #if defined(BCM_88680_A0)
  31838     { /* SOC_REG_INT_GR255_BCM88680_A0r */
  31839         soc_block_list[2],
  31840         soc_portreg,
  31841         1,
  31842         0,
  31843         0x1300,
  31844         SOC_REG_FLAG_COUNTER,
  31845         0,
  31846         1,
  31847         soc_GR255_BCM88680_A0r_fields,
  31848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31849         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31850         19,
  31851         -1,
  31852     },
  31853 #endif /* chips */
  31854 
  31855 #if defined(BCM_53570_A0)
  31856     { /* SOC_REG_INT_GR4095Pr */
  31857         soc_block_list[2],
  31858         soc_portreg,
  31859         1,
  31860         0,
  31861         0x7800,
  31862         SOC_REG_FLAG_COUNTER,
  31863         0,
  31864         1,
  31865         soc_GR1023_BCM53400_A0r_fields,
  31866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31867         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31868         274,
  31869         -1,
  31870     },
  31871 #endif /* chips */
  31872 
  31873 #if defined(BCM_53570_B0)
  31874     { /* SOC_REG_INT_GR4095P_BCM53570_B0r */
  31875         soc_block_list[2],
  31876         soc_portreg,
  31877         1,
  31878         0,
  31879         0x7800,
  31880         SOC_REG_FLAG_COUNTER,
  31881         0,
  31882         1,
  31883         soc_GR1023_BCM53400_A0r_fields,
  31884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31886         278,
  31887         -1,
  31888     },
  31889 #endif /* chips */
  31890 
  31891 #if defined(BCM_53400_A0)
  31892     { /* SOC_REG_INT_GR4095_BCM53400_A0r */
  31893         soc_block_list[9],
  31894         soc_portreg,
  31895         1,
  31896         0,
  31897         0x1900,
  31898         SOC_REG_FLAG_COUNTER,
  31899         0,
  31900         1,
  31901         soc_GR1023_BCM53400_A0r_fields,
  31902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31904         124,
  31905         -1,
  31906     },
  31907 #endif /* chips */
  31908 
  31909 #if defined(BCM_53540_A0)
  31910     { /* SOC_REG_INT_GR4095_BCM53540_A0r */
  31911         soc_block_list[2],
  31912         soc_portreg,
  31913         1,
  31914         0,
  31915         0x1900,
  31916         SOC_REG_FLAG_COUNTER,
  31917         0,
  31918         1,
  31919         soc_GR1023_BCM53400_A0r_fields,
  31920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31922         124,
  31923         -1,
  31924     },
  31925 #endif /* chips */
  31926 
  31927 #if defined(BCM_53570_A0)
  31928     { /* SOC_REG_INT_GR4095_BCM53570_A0r */
  31929         soc_block_list[2],
  31930         soc_portreg,
  31931         1,
  31932         0,
  31933         0x1900,
  31934         SOC_REG_FLAG_COUNTER,
  31935         0,
  31936         1,
  31937         soc_GR1023_BCM53400_A0r_fields,
  31938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31940         179,
  31941         -1,
  31942     },
  31943 #endif /* chips */
  31944 
  31945 #if defined(BCM_53570_B0)
  31946     { /* SOC_REG_INT_GR4095_BCM53570_B0r */
  31947         soc_block_list[2],
  31948         soc_portreg,
  31949         1,
  31950         0,
  31951         0x1900,
  31952         SOC_REG_FLAG_COUNTER,
  31953         0,
  31954         1,
  31955         soc_GR1023_BCM53400_A0r_fields,
  31956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31958         183,
  31959         -1,
  31960     },
  31961 #endif /* chips */
  31962 
  31963 #if defined(BCM_56142_A0)
  31964     { /* SOC_REG_INT_GR4095_BCM56142_A0r */
  31965         soc_block_list[210],
  31966         soc_portreg,
  31967         1,
  31968         0,
  31969         0x99,
  31970         SOC_REG_FLAG_COUNTER,
  31971         0,
  31972         1,
  31973         soc_GR1023r_fields,
  31974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31976         200,
  31977         -1,
  31978     },
  31979 #endif /* chips */
  31980 
  31981 #if defined(BCM_56150_A0)
  31982     { /* SOC_REG_INT_GR4095_BCM56150_A0r */
  31983         soc_block_list[2],
  31984         soc_portreg,
  31985         1,
  31986         0,
  31987         0x1900,
  31988         SOC_REG_FLAG_COUNTER,
  31989         0,
  31990         1,
  31991         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  31992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31994         120,
  31995         -1,
  31996     },
  31997 #endif /* chips */
  31998 
  31999 #if defined(BCM_56160_A0)
  32000     { /* SOC_REG_INT_GR4095_BCM56160_A0r */
  32001         soc_block_list[2],
  32002         soc_portreg,
  32003         1,
  32004         0,
  32005         0x1900,
  32006         SOC_REG_FLAG_COUNTER,
  32007         0,
  32008         1,
  32009         soc_GR1023_BCM53400_A0r_fields,
  32010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32012         124,
  32013         -1,
  32014     },
  32015 #endif /* chips */
  32016 
  32017 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  32018     { /* SOC_REG_INT_GR4095_BCM56334_A0r */
  32019         soc_block_list[210],
  32020         soc_portreg,
  32021         1,
  32022         0,
  32023         0x99,
  32024         SOC_REG_FLAG_COUNTER,
  32025         0,
  32026         1,
  32027         soc_GR1023r_fields,
  32028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32030         195,
  32031         -1,
  32032     },
  32033 #endif /* chips */
  32034 
  32035 #if defined(BCM_56370_A0)
  32036     { /* SOC_REG_INT_GR4095_BCM56370_A0r */
  32037         soc_block_list[9],
  32038         soc_portreg,
  32039         1,
  32040         0,
  32041         0x1900,
  32042         SOC_REG_FLAG_COUNTER,
  32043         0,
  32044         1,
  32045         soc_GR1023_BCM53400_A0r_fields,
  32046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32048         85,
  32049         -1,
  32050         3,
  32051     },
  32052 #endif /* chips */
  32053 
  32054 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  32055     { /* SOC_REG_INT_GR4095_BCM56440_A0r */
  32056         soc_block_list[2],
  32057         soc_portreg,
  32058         1,
  32059         0,
  32060         0x99,
  32061         SOC_REG_FLAG_COUNTER,
  32062         0,
  32063         1,
  32064         soc_GR1023r_fields,
  32065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32066         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32067         192,
  32068         -1,
  32069     },
  32070 #endif /* chips */
  32071 
  32072 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  32073     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  32074     { /* SOC_REG_INT_GR4095_BCM56624_A0r */
  32075         soc_block_list[205],
  32076         soc_portreg,
  32077         1,
  32078         0,
  32079         0x88,
  32080         SOC_REG_FLAG_COUNTER,
  32081         0,
  32082         1,
  32083         soc_GR1023r_fields,
  32084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32086         178,
  32087         -1,
  32088     },
  32089 #endif /* chips */
  32090 
  32091 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  32092     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  32093     { /* SOC_REG_INT_GR4095_BCM56634_A0r */
  32094         soc_block_list[207],
  32095         soc_portreg,
  32096         1,
  32097         0,
  32098         0x88,
  32099         SOC_REG_FLAG_COUNTER,
  32100         0,
  32101         1,
  32102         soc_GR1023r_fields,
  32103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32105         178,
  32106         -1,
  32107     },
  32108 #endif /* chips */
  32109 
  32110 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  32111     { /* SOC_REG_INT_GR4095_BCM56685_A0r */
  32112         soc_block_list[209],
  32113         soc_portreg,
  32114         1,
  32115         0,
  32116         0x88,
  32117         SOC_REG_FLAG_COUNTER,
  32118         0,
  32119         1,
  32120         soc_GR1023r_fields,
  32121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32122         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32123         178,
  32124         -1,
  32125     },
  32126 #endif /* chips */
  32127 
  32128 #if defined(BCM_56800_A0)
  32129     { /* SOC_REG_INT_GR4095_BCM56800_A0r */
  32130         soc_block_list[9],
  32131         soc_portreg,
  32132         1,
  32133         0,
  32134         0x4f,
  32135         SOC_REG_FLAG_COUNTER,
  32136         0,
  32137         1,
  32138         soc_GR1023r_fields,
  32139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32141         121,
  32142         -1,
  32143     },
  32144 #endif /* chips */
  32145 
  32146 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  32147     { /* SOC_REG_INT_GR4095_BCM56820_A0r */
  32148         soc_block_list[206],
  32149         soc_portreg,
  32150         1,
  32151         0,
  32152         0x88,
  32153         SOC_REG_FLAG_COUNTER,
  32154         0,
  32155         1,
  32156         soc_GR1023r_fields,
  32157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32159         188,
  32160         -1,
  32161     },
  32162 #endif /* chips */
  32163 
  32164 #if defined(BCM_88375_A0)
  32165     { /* SOC_REG_INT_GR4095_BCM88375_A0r */
  32166         soc_block_list[2],
  32167         soc_portreg,
  32168         1,
  32169         0,
  32170         0x1900,
  32171         SOC_REG_FLAG_COUNTER,
  32172         0,
  32173         1,
  32174         soc_GR4095_BCM88375_A0r_fields,
  32175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32177         25,
  32178         -1,
  32179     },
  32180 #endif /* chips */
  32181 
  32182 #if defined(BCM_88375_B0)
  32183     { /* SOC_REG_INT_GR4095_BCM88375_B0r */
  32184         soc_block_list[2],
  32185         soc_portreg,
  32186         1,
  32187         0,
  32188         0x1900,
  32189         SOC_REG_FLAG_COUNTER,
  32190         0,
  32191         1,
  32192         soc_GR4095_BCM88375_B0r_fields,
  32193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32194         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32195         25,
  32196         -1,
  32197     },
  32198 #endif /* chips */
  32199 
  32200 #if defined(BCM_88470_A0)
  32201     { /* SOC_REG_INT_GR4095_BCM88470_A0r */
  32202         soc_block_list[2],
  32203         soc_portreg,
  32204         1,
  32205         0,
  32206         0x1900,
  32207         SOC_REG_FLAG_COUNTER,
  32208         0,
  32209         1,
  32210         soc_GR4095_BCM88470_A0r_fields,
  32211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32212         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32213         25,
  32214         -1,
  32215     },
  32216 #endif /* chips */
  32217 
  32218 #if defined(BCM_88470_B0)
  32219     { /* SOC_REG_INT_GR4095_BCM88470_B0r */
  32220         soc_block_list[2],
  32221         soc_portreg,
  32222         1,
  32223         0,
  32224         0x1900,
  32225         SOC_REG_FLAG_COUNTER,
  32226         0,
  32227         1,
  32228         soc_GR4095_BCM88470_B0r_fields,
  32229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32230         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32231         25,
  32232         -1,
  32233     },
  32234 #endif /* chips */
  32235 
  32236 #if defined(BCM_88675_A0)
  32237     { /* SOC_REG_INT_GR4095_BCM88675_A0r */
  32238         soc_block_list[2],
  32239         soc_portreg,
  32240         1,
  32241         0,
  32242         0x1900,
  32243         SOC_REG_FLAG_COUNTER,
  32244         0,
  32245         1,
  32246         soc_GR4095r_fields,
  32247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32248         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32249         25,
  32250         -1,
  32251     },
  32252 #endif /* chips */
  32253 
  32254 #if defined(BCM_88675_B0)
  32255     { /* SOC_REG_INT_GR4095_BCM88675_B0r */
  32256         soc_block_list[2],
  32257         soc_portreg,
  32258         1,
  32259         0,
  32260         0x1900,
  32261         SOC_REG_FLAG_COUNTER,
  32262         0,
  32263         1,
  32264         soc_GR4095_BCM88675_B0r_fields,
  32265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32266         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32267         25,
  32268         -1,
  32269     },
  32270 #endif /* chips */
  32271 
  32272 #if defined(BCM_88680_A0)
  32273     { /* SOC_REG_INT_GR4095_BCM88680_A0r */
  32274         soc_block_list[2],
  32275         soc_portreg,
  32276         1,
  32277         0,
  32278         0x1900,
  32279         SOC_REG_FLAG_COUNTER,
  32280         0,
  32281         1,
  32282         soc_GR4095_BCM88680_A0r_fields,
  32283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32284         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32285         25,
  32286         -1,
  32287     },
  32288 #endif /* chips */
  32289 
  32290 #if defined(BCM_53570_A0)
  32291     { /* SOC_REG_INT_GR511Pr */
  32292         soc_block_list[2],
  32293         soc_portreg,
  32294         1,
  32295         0,
  32296         0x7300,
  32297         SOC_REG_FLAG_COUNTER,
  32298         0,
  32299         1,
  32300         soc_GR1023_BCM53400_A0r_fields,
  32301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32303         269,
  32304         -1,
  32305     },
  32306 #endif /* chips */
  32307 
  32308 #if defined(BCM_53570_B0)
  32309     { /* SOC_REG_INT_GR511P_BCM53570_B0r */
  32310         soc_block_list[2],
  32311         soc_portreg,
  32312         1,
  32313         0,
  32314         0x7300,
  32315         SOC_REG_FLAG_COUNTER,
  32316         0,
  32317         1,
  32318         soc_GR1023_BCM53400_A0r_fields,
  32319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32321         273,
  32322         -1,
  32323     },
  32324 #endif /* chips */
  32325 
  32326 #if defined(BCM_53400_A0)
  32327     { /* SOC_REG_INT_GR511_BCM53400_A0r */
  32328         soc_block_list[9],
  32329         soc_portreg,
  32330         1,
  32331         0,
  32332         0x1400,
  32333         SOC_REG_FLAG_COUNTER,
  32334         0,
  32335         1,
  32336         soc_GR1023_BCM53400_A0r_fields,
  32337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32339         119,
  32340         -1,
  32341     },
  32342 #endif /* chips */
  32343 
  32344 #if defined(BCM_53540_A0)
  32345     { /* SOC_REG_INT_GR511_BCM53540_A0r */
  32346         soc_block_list[2],
  32347         soc_portreg,
  32348         1,
  32349         0,
  32350         0x1400,
  32351         SOC_REG_FLAG_COUNTER,
  32352         0,
  32353         1,
  32354         soc_GR1023_BCM53400_A0r_fields,
  32355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32357         119,
  32358         -1,
  32359     },
  32360 #endif /* chips */
  32361 
  32362 #if defined(BCM_53570_A0)
  32363     { /* SOC_REG_INT_GR511_BCM53570_A0r */
  32364         soc_block_list[2],
  32365         soc_portreg,
  32366         1,
  32367         0,
  32368         0x1400,
  32369         SOC_REG_FLAG_COUNTER,
  32370         0,
  32371         1,
  32372         soc_GR1023_BCM53400_A0r_fields,
  32373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32375         174,
  32376         -1,
  32377     },
  32378 #endif /* chips */
  32379 
  32380 #if defined(BCM_53570_B0)
  32381     { /* SOC_REG_INT_GR511_BCM53570_B0r */
  32382         soc_block_list[2],
  32383         soc_portreg,
  32384         1,
  32385         0,
  32386         0x1400,
  32387         SOC_REG_FLAG_COUNTER,
  32388         0,
  32389         1,
  32390         soc_GR1023_BCM53400_A0r_fields,
  32391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32393         178,
  32394         -1,
  32395     },
  32396 #endif /* chips */
  32397 
  32398 #if defined(BCM_56142_A0)
  32399     { /* SOC_REG_INT_GR511_BCM56142_A0r */
  32400         soc_block_list[210],
  32401         soc_portreg,
  32402         1,
  32403         0,
  32404         0x94,
  32405         SOC_REG_FLAG_COUNTER,
  32406         0,
  32407         1,
  32408         soc_GR1023r_fields,
  32409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32410         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32411         195,
  32412         -1,
  32413     },
  32414 #endif /* chips */
  32415 
  32416 #if defined(BCM_56150_A0)
  32417     { /* SOC_REG_INT_GR511_BCM56150_A0r */
  32418         soc_block_list[2],
  32419         soc_portreg,
  32420         1,
  32421         0,
  32422         0x1400,
  32423         SOC_REG_FLAG_COUNTER,
  32424         0,
  32425         1,
  32426         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  32427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32429         115,
  32430         -1,
  32431     },
  32432 #endif /* chips */
  32433 
  32434 #if defined(BCM_56160_A0)
  32435     { /* SOC_REG_INT_GR511_BCM56160_A0r */
  32436         soc_block_list[2],
  32437         soc_portreg,
  32438         1,
  32439         0,
  32440         0x1400,
  32441         SOC_REG_FLAG_COUNTER,
  32442         0,
  32443         1,
  32444         soc_GR1023_BCM53400_A0r_fields,
  32445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32446         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32447         119,
  32448         -1,
  32449     },
  32450 #endif /* chips */
  32451 
  32452 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  32453     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  32454     { /* SOC_REG_INT_GR511_BCM56224_A0r */
  32455         soc_block_list[2],
  32456         soc_portreg,
  32457         1,
  32458         0,
  32459         0x14,
  32460         SOC_REG_FLAG_COUNTER,
  32461         0,
  32462         1,
  32463         soc_GR1023r_fields,
  32464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32465         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32466         54,
  32467         -1,
  32468     },
  32469 #endif /* chips */
  32470 
  32471 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  32472     { /* SOC_REG_INT_GR511_BCM56334_A0r */
  32473         soc_block_list[210],
  32474         soc_portreg,
  32475         1,
  32476         0,
  32477         0x94,
  32478         SOC_REG_FLAG_COUNTER,
  32479         0,
  32480         1,
  32481         soc_GR1023r_fields,
  32482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32484         190,
  32485         -1,
  32486     },
  32487 #endif /* chips */
  32488 
  32489 #if defined(BCM_56370_A0)
  32490     { /* SOC_REG_INT_GR511_BCM56370_A0r */
  32491         soc_block_list[9],
  32492         soc_portreg,
  32493         1,
  32494         0,
  32495         0x1400,
  32496         SOC_REG_FLAG_COUNTER,
  32497         0,
  32498         1,
  32499         soc_GR1023_BCM53400_A0r_fields,
  32500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32502         80,
  32503         -1,
  32504         3,
  32505     },
  32506 #endif /* chips */
  32507 
  32508 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  32509     { /* SOC_REG_INT_GR511_BCM56440_A0r */
  32510         soc_block_list[2],
  32511         soc_portreg,
  32512         1,
  32513         0,
  32514         0x94,
  32515         SOC_REG_FLAG_COUNTER,
  32516         0,
  32517         1,
  32518         soc_GR1023r_fields,
  32519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32520         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32521         187,
  32522         -1,
  32523     },
  32524 #endif /* chips */
  32525 
  32526 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  32527     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  32528     { /* SOC_REG_INT_GR511_BCM56624_A0r */
  32529         soc_block_list[205],
  32530         soc_portreg,
  32531         1,
  32532         0,
  32533         0x83,
  32534         SOC_REG_FLAG_COUNTER,
  32535         0,
  32536         1,
  32537         soc_GR1023r_fields,
  32538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32540         173,
  32541         -1,
  32542     },
  32543 #endif /* chips */
  32544 
  32545 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  32546     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  32547     { /* SOC_REG_INT_GR511_BCM56634_A0r */
  32548         soc_block_list[207],
  32549         soc_portreg,
  32550         1,
  32551         0,
  32552         0x83,
  32553         SOC_REG_FLAG_COUNTER,
  32554         0,
  32555         1,
  32556         soc_GR1023r_fields,
  32557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32559         173,
  32560         -1,
  32561     },
  32562 #endif /* chips */
  32563 
  32564 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  32565     { /* SOC_REG_INT_GR511_BCM56685_A0r */
  32566         soc_block_list[209],
  32567         soc_portreg,
  32568         1,
  32569         0,
  32570         0x83,
  32571         SOC_REG_FLAG_COUNTER,
  32572         0,
  32573         1,
  32574         soc_GR1023r_fields,
  32575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32577         173,
  32578         -1,
  32579     },
  32580 #endif /* chips */
  32581 
  32582 #if defined(BCM_56800_A0)
  32583     { /* SOC_REG_INT_GR511_BCM56800_A0r */
  32584         soc_block_list[9],
  32585         soc_portreg,
  32586         1,
  32587         0,
  32588         0x4a,
  32589         SOC_REG_FLAG_COUNTER,
  32590         0,
  32591         1,
  32592         soc_GR1023r_fields,
  32593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32594         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32595         116,
  32596         -1,
  32597     },
  32598 #endif /* chips */
  32599 
  32600 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  32601     { /* SOC_REG_INT_GR511_BCM56820_A0r */
  32602         soc_block_list[206],
  32603         soc_portreg,
  32604         1,
  32605         0,
  32606         0x83,
  32607         SOC_REG_FLAG_COUNTER,
  32608         0,
  32609         1,
  32610         soc_GR1023r_fields,
  32611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32613         183,
  32614         -1,
  32615     },
  32616 #endif /* chips */
  32617 
  32618 #if defined(BCM_88375_A0)
  32619     { /* SOC_REG_INT_GR511_BCM88375_A0r */
  32620         soc_block_list[2],
  32621         soc_portreg,
  32622         1,
  32623         0,
  32624         0x1400,
  32625         SOC_REG_FLAG_COUNTER,
  32626         0,
  32627         1,
  32628         soc_GR511_BCM88375_A0r_fields,
  32629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32631         20,
  32632         -1,
  32633     },
  32634 #endif /* chips */
  32635 
  32636 #if defined(BCM_88375_B0)
  32637     { /* SOC_REG_INT_GR511_BCM88375_B0r */
  32638         soc_block_list[2],
  32639         soc_portreg,
  32640         1,
  32641         0,
  32642         0x1400,
  32643         SOC_REG_FLAG_COUNTER,
  32644         0,
  32645         1,
  32646         soc_GR511_BCM88375_B0r_fields,
  32647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32649         20,
  32650         -1,
  32651     },
  32652 #endif /* chips */
  32653 
  32654 #if defined(BCM_88470_A0)
  32655     { /* SOC_REG_INT_GR511_BCM88470_A0r */
  32656         soc_block_list[2],
  32657         soc_portreg,
  32658         1,
  32659         0,
  32660         0x1400,
  32661         SOC_REG_FLAG_COUNTER,
  32662         0,
  32663         1,
  32664         soc_GR511_BCM88470_A0r_fields,
  32665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32667         20,
  32668         -1,
  32669     },
  32670 #endif /* chips */
  32671 
  32672 #if defined(BCM_88470_B0)
  32673     { /* SOC_REG_INT_GR511_BCM88470_B0r */
  32674         soc_block_list[2],
  32675         soc_portreg,
  32676         1,
  32677         0,
  32678         0x1400,
  32679         SOC_REG_FLAG_COUNTER,
  32680         0,
  32681         1,
  32682         soc_GR511_BCM88470_B0r_fields,
  32683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32685         20,
  32686         -1,
  32687     },
  32688 #endif /* chips */
  32689 
  32690 #if defined(BCM_88675_A0)
  32691     { /* SOC_REG_INT_GR511_BCM88675_A0r */
  32692         soc_block_list[2],
  32693         soc_portreg,
  32694         1,
  32695         0,
  32696         0x1400,
  32697         SOC_REG_FLAG_COUNTER,
  32698         0,
  32699         1,
  32700         soc_GR511r_fields,
  32701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32703         20,
  32704         -1,
  32705     },
  32706 #endif /* chips */
  32707 
  32708 #if defined(BCM_88675_B0)
  32709     { /* SOC_REG_INT_GR511_BCM88675_B0r */
  32710         soc_block_list[2],
  32711         soc_portreg,
  32712         1,
  32713         0,
  32714         0x1400,
  32715         SOC_REG_FLAG_COUNTER,
  32716         0,
  32717         1,
  32718         soc_GR511_BCM88675_B0r_fields,
  32719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32721         20,
  32722         -1,
  32723     },
  32724 #endif /* chips */
  32725 
  32726 #if defined(BCM_88680_A0)
  32727     { /* SOC_REG_INT_GR511_BCM88680_A0r */
  32728         soc_block_list[2],
  32729         soc_portreg,
  32730         1,
  32731         0,
  32732         0x1400,
  32733         SOC_REG_FLAG_COUNTER,
  32734         0,
  32735         1,
  32736         soc_GR511_BCM88680_A0r_fields,
  32737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32739         20,
  32740         -1,
  32741     },
  32742 #endif /* chips */
  32743 
  32744 #if defined(BCM_53570_A0)
  32745     { /* SOC_REG_INT_GR64Pr */
  32746         soc_block_list[2],
  32747         soc_portreg,
  32748         1,
  32749         0,
  32750         0x7000,
  32751         SOC_REG_FLAG_COUNTER,
  32752         0,
  32753         1,
  32754         soc_GR1023_BCM53400_A0r_fields,
  32755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32756         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32757         266,
  32758         -1,
  32759     },
  32760 #endif /* chips */
  32761 
  32762 #if defined(BCM_53570_B0)
  32763     { /* SOC_REG_INT_GR64P_BCM53570_B0r */
  32764         soc_block_list[2],
  32765         soc_portreg,
  32766         1,
  32767         0,
  32768         0x7000,
  32769         SOC_REG_FLAG_COUNTER,
  32770         0,
  32771         1,
  32772         soc_GR1023_BCM53400_A0r_fields,
  32773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32774         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32775         270,
  32776         -1,
  32777     },
  32778 #endif /* chips */
  32779 
  32780 #if defined(BCM_53400_A0)
  32781     { /* SOC_REG_INT_GR64_BCM53400_A0r */
  32782         soc_block_list[9],
  32783         soc_portreg,
  32784         1,
  32785         0,
  32786         0x1100,
  32787         SOC_REG_FLAG_COUNTER,
  32788         0,
  32789         1,
  32790         soc_GR1023_BCM53400_A0r_fields,
  32791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32792         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32793         116,
  32794         -1,
  32795     },
  32796 #endif /* chips */
  32797 
  32798 #if defined(BCM_53540_A0)
  32799     { /* SOC_REG_INT_GR64_BCM53540_A0r */
  32800         soc_block_list[2],
  32801         soc_portreg,
  32802         1,
  32803         0,
  32804         0x1100,
  32805         SOC_REG_FLAG_COUNTER,
  32806         0,
  32807         1,
  32808         soc_GR1023_BCM53400_A0r_fields,
  32809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32810         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32811         116,
  32812         -1,
  32813     },
  32814 #endif /* chips */
  32815 
  32816 #if defined(BCM_53570_A0)
  32817     { /* SOC_REG_INT_GR64_BCM53570_A0r */
  32818         soc_block_list[2],
  32819         soc_portreg,
  32820         1,
  32821         0,
  32822         0x1100,
  32823         SOC_REG_FLAG_COUNTER,
  32824         0,
  32825         1,
  32826         soc_GR1023_BCM53400_A0r_fields,
  32827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32828         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32829         171,
  32830         -1,
  32831     },
  32832 #endif /* chips */
  32833 
  32834 #if defined(BCM_53570_B0)
  32835     { /* SOC_REG_INT_GR64_BCM53570_B0r */
  32836         soc_block_list[2],
  32837         soc_portreg,
  32838         1,
  32839         0,
  32840         0x1100,
  32841         SOC_REG_FLAG_COUNTER,
  32842         0,
  32843         1,
  32844         soc_GR1023_BCM53400_A0r_fields,
  32845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32846         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32847         175,
  32848         -1,
  32849     },
  32850 #endif /* chips */
  32851 
  32852 #if defined(BCM_56142_A0)
  32853     { /* SOC_REG_INT_GR64_BCM56142_A0r */
  32854         soc_block_list[210],
  32855         soc_portreg,
  32856         1,
  32857         0,
  32858         0x91,
  32859         SOC_REG_FLAG_COUNTER,
  32860         0,
  32861         1,
  32862         soc_GR1023r_fields,
  32863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32864         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32865         192,
  32866         -1,
  32867     },
  32868 #endif /* chips */
  32869 
  32870 #if defined(BCM_56150_A0)
  32871     { /* SOC_REG_INT_GR64_BCM56150_A0r */
  32872         soc_block_list[2],
  32873         soc_portreg,
  32874         1,
  32875         0,
  32876         0x1100,
  32877         SOC_REG_FLAG_COUNTER,
  32878         0,
  32879         1,
  32880         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  32881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32882         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32883         112,
  32884         -1,
  32885     },
  32886 #endif /* chips */
  32887 
  32888 #if defined(BCM_56160_A0)
  32889     { /* SOC_REG_INT_GR64_BCM56160_A0r */
  32890         soc_block_list[2],
  32891         soc_portreg,
  32892         1,
  32893         0,
  32894         0x1100,
  32895         SOC_REG_FLAG_COUNTER,
  32896         0,
  32897         1,
  32898         soc_GR1023_BCM53400_A0r_fields,
  32899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32901         116,
  32902         -1,
  32903     },
  32904 #endif /* chips */
  32905 
  32906 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  32907     { /* SOC_REG_INT_GR64_BCM56334_A0r */
  32908         soc_block_list[210],
  32909         soc_portreg,
  32910         1,
  32911         0,
  32912         0x91,
  32913         SOC_REG_FLAG_COUNTER,
  32914         0,
  32915         1,
  32916         soc_GR1023r_fields,
  32917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32919         187,
  32920         -1,
  32921     },
  32922 #endif /* chips */
  32923 
  32924 #if defined(BCM_56370_A0)
  32925     { /* SOC_REG_INT_GR64_BCM56370_A0r */
  32926         soc_block_list[9],
  32927         soc_portreg,
  32928         1,
  32929         0,
  32930         0x1100,
  32931         SOC_REG_FLAG_COUNTER,
  32932         0,
  32933         1,
  32934         soc_GR1023_BCM53400_A0r_fields,
  32935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32936         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32937         77,
  32938         -1,
  32939         3,
  32940     },
  32941 #endif /* chips */
  32942 
  32943 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  32944     { /* SOC_REG_INT_GR64_BCM56440_A0r */
  32945         soc_block_list[2],
  32946         soc_portreg,
  32947         1,
  32948         0,
  32949         0x91,
  32950         SOC_REG_FLAG_COUNTER,
  32951         0,
  32952         1,
  32953         soc_GR1023r_fields,
  32954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32956         184,
  32957         -1,
  32958     },
  32959 #endif /* chips */
  32960 
  32961 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  32962     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  32963     { /* SOC_REG_INT_GR64_BCM56624_A0r */
  32964         soc_block_list[205],
  32965         soc_portreg,
  32966         1,
  32967         0,
  32968         0x80,
  32969         SOC_REG_FLAG_COUNTER,
  32970         0,
  32971         1,
  32972         soc_GR1023r_fields,
  32973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32974         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32975         170,
  32976         -1,
  32977     },
  32978 #endif /* chips */
  32979 
  32980 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  32981     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  32982     { /* SOC_REG_INT_GR64_BCM56634_A0r */
  32983         soc_block_list[207],
  32984         soc_portreg,
  32985         1,
  32986         0,
  32987         0x80,
  32988         SOC_REG_FLAG_COUNTER,
  32989         0,
  32990         1,
  32991         soc_GR1023r_fields,
  32992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32994         170,
  32995         -1,
  32996     },
  32997 #endif /* chips */
  32998 
  32999 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  33000     { /* SOC_REG_INT_GR64_BCM56685_A0r */
  33001         soc_block_list[209],
  33002         soc_portreg,
  33003         1,
  33004         0,
  33005         0x80,
  33006         SOC_REG_FLAG_COUNTER,
  33007         0,
  33008         1,
  33009         soc_GR1023r_fields,
  33010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33012         170,
  33013         -1,
  33014     },
  33015 #endif /* chips */
  33016 
  33017 #if defined(BCM_56800_A0)
  33018     { /* SOC_REG_INT_GR64_BCM56800_A0r */
  33019         soc_block_list[9],
  33020         soc_portreg,
  33021         1,
  33022         0,
  33023         0x47,
  33024         SOC_REG_FLAG_COUNTER,
  33025         0,
  33026         1,
  33027         soc_GR1023r_fields,
  33028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33030         113,
  33031         -1,
  33032     },
  33033 #endif /* chips */
  33034 
  33035 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  33036     { /* SOC_REG_INT_GR64_BCM56820_A0r */
  33037         soc_block_list[206],
  33038         soc_portreg,
  33039         1,
  33040         0,
  33041         0x80,
  33042         SOC_REG_FLAG_COUNTER,
  33043         0,
  33044         1,
  33045         soc_GR1023r_fields,
  33046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33048         180,
  33049         -1,
  33050     },
  33051 #endif /* chips */
  33052 
  33053 #if defined(BCM_88375_A0)
  33054     { /* SOC_REG_INT_GR64_BCM88375_A0r */
  33055         soc_block_list[2],
  33056         soc_portreg,
  33057         1,
  33058         0,
  33059         0x1100,
  33060         SOC_REG_FLAG_COUNTER,
  33061         0,
  33062         1,
  33063         soc_GR64_BCM88375_A0r_fields,
  33064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33065         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33066         17,
  33067         -1,
  33068     },
  33069 #endif /* chips */
  33070 
  33071 #if defined(BCM_88375_B0)
  33072     { /* SOC_REG_INT_GR64_BCM88375_B0r */
  33073         soc_block_list[2],
  33074         soc_portreg,
  33075         1,
  33076         0,
  33077         0x1100,
  33078         SOC_REG_FLAG_COUNTER,
  33079         0,
  33080         1,
  33081         soc_GR64_BCM88375_B0r_fields,
  33082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33083         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33084         17,
  33085         -1,
  33086     },
  33087 #endif /* chips */
  33088 
  33089 #if defined(BCM_88470_A0)
  33090     { /* SOC_REG_INT_GR64_BCM88470_A0r */
  33091         soc_block_list[2],
  33092         soc_portreg,
  33093         1,
  33094         0,
  33095         0x1100,
  33096         SOC_REG_FLAG_COUNTER,
  33097         0,
  33098         1,
  33099         soc_GR64_BCM88470_A0r_fields,
  33100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33102         17,
  33103         -1,
  33104     },
  33105 #endif /* chips */
  33106 
  33107 #if defined(BCM_88470_B0)
  33108     { /* SOC_REG_INT_GR64_BCM88470_B0r */
  33109         soc_block_list[2],
  33110         soc_portreg,
  33111         1,
  33112         0,
  33113         0x1100,
  33114         SOC_REG_FLAG_COUNTER,
  33115         0,
  33116         1,
  33117         soc_GR64_BCM88470_B0r_fields,
  33118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33120         17,
  33121         -1,
  33122     },
  33123 #endif /* chips */
  33124 
  33125 #if defined(BCM_88675_A0)
  33126     { /* SOC_REG_INT_GR64_BCM88675_A0r */
  33127         soc_block_list[2],
  33128         soc_portreg,
  33129         1,
  33130         0,
  33131         0x1100,
  33132         SOC_REG_FLAG_COUNTER,
  33133         0,
  33134         1,
  33135         soc_GR64r_fields,
  33136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33138         17,
  33139         -1,
  33140     },
  33141 #endif /* chips */
  33142 
  33143 #if defined(BCM_88675_B0)
  33144     { /* SOC_REG_INT_GR64_BCM88675_B0r */
  33145         soc_block_list[2],
  33146         soc_portreg,
  33147         1,
  33148         0,
  33149         0x1100,
  33150         SOC_REG_FLAG_COUNTER,
  33151         0,
  33152         1,
  33153         soc_GR64_BCM88675_B0r_fields,
  33154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33156         17,
  33157         -1,
  33158     },
  33159 #endif /* chips */
  33160 
  33161 #if defined(BCM_88680_A0)
  33162     { /* SOC_REG_INT_GR64_BCM88680_A0r */
  33163         soc_block_list[2],
  33164         soc_portreg,
  33165         1,
  33166         0,
  33167         0x1100,
  33168         SOC_REG_FLAG_COUNTER,
  33169         0,
  33170         1,
  33171         soc_GR64_BCM88680_A0r_fields,
  33172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33174         17,
  33175         -1,
  33176     },
  33177 #endif /* chips */
  33178 
  33179 #if defined(BCM_53570_A0)
  33180     { /* SOC_REG_INT_GR9216Pr */
  33181         soc_block_list[2],
  33182         soc_portreg,
  33183         1,
  33184         0,
  33185         0x7900,
  33186         SOC_REG_FLAG_COUNTER,
  33187         0,
  33188         1,
  33189         soc_GR1023_BCM53400_A0r_fields,
  33190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33192         275,
  33193         -1,
  33194     },
  33195 #endif /* chips */
  33196 
  33197 #if defined(BCM_53570_B0)
  33198     { /* SOC_REG_INT_GR9216P_BCM53570_B0r */
  33199         soc_block_list[2],
  33200         soc_portreg,
  33201         1,
  33202         0,
  33203         0x7900,
  33204         SOC_REG_FLAG_COUNTER,
  33205         0,
  33206         1,
  33207         soc_GR1023_BCM53400_A0r_fields,
  33208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33209         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33210         279,
  33211         -1,
  33212     },
  33213 #endif /* chips */
  33214 
  33215 #if defined(BCM_53400_A0)
  33216     { /* SOC_REG_INT_GR9216_BCM53400_A0r */
  33217         soc_block_list[9],
  33218         soc_portreg,
  33219         1,
  33220         0,
  33221         0x1a00,
  33222         SOC_REG_FLAG_COUNTER,
  33223         0,
  33224         1,
  33225         soc_GR1023_BCM53400_A0r_fields,
  33226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33227         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33228         125,
  33229         -1,
  33230     },
  33231 #endif /* chips */
  33232 
  33233 #if defined(BCM_53540_A0)
  33234     { /* SOC_REG_INT_GR9216_BCM53540_A0r */
  33235         soc_block_list[2],
  33236         soc_portreg,
  33237         1,
  33238         0,
  33239         0x1a00,
  33240         SOC_REG_FLAG_COUNTER,
  33241         0,
  33242         1,
  33243         soc_GR1023_BCM53400_A0r_fields,
  33244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33245         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33246         125,
  33247         -1,
  33248     },
  33249 #endif /* chips */
  33250 
  33251 #if defined(BCM_53570_A0)
  33252     { /* SOC_REG_INT_GR9216_BCM53570_A0r */
  33253         soc_block_list[2],
  33254         soc_portreg,
  33255         1,
  33256         0,
  33257         0x1a00,
  33258         SOC_REG_FLAG_COUNTER,
  33259         0,
  33260         1,
  33261         soc_GR1023_BCM53400_A0r_fields,
  33262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33264         180,
  33265         -1,
  33266     },
  33267 #endif /* chips */
  33268 
  33269 #if defined(BCM_53570_B0)
  33270     { /* SOC_REG_INT_GR9216_BCM53570_B0r */
  33271         soc_block_list[2],
  33272         soc_portreg,
  33273         1,
  33274         0,
  33275         0x1a00,
  33276         SOC_REG_FLAG_COUNTER,
  33277         0,
  33278         1,
  33279         soc_GR1023_BCM53400_A0r_fields,
  33280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33281         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33282         184,
  33283         -1,
  33284     },
  33285 #endif /* chips */
  33286 
  33287 #if defined(BCM_56142_A0)
  33288     { /* SOC_REG_INT_GR9216_BCM56142_A0r */
  33289         soc_block_list[210],
  33290         soc_portreg,
  33291         1,
  33292         0,
  33293         0x9a,
  33294         SOC_REG_FLAG_COUNTER,
  33295         0,
  33296         1,
  33297         soc_GR1023r_fields,
  33298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33300         201,
  33301         -1,
  33302     },
  33303 #endif /* chips */
  33304 
  33305 #if defined(BCM_56150_A0)
  33306     { /* SOC_REG_INT_GR9216_BCM56150_A0r */
  33307         soc_block_list[2],
  33308         soc_portreg,
  33309         1,
  33310         0,
  33311         0x1a00,
  33312         SOC_REG_FLAG_COUNTER,
  33313         0,
  33314         1,
  33315         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  33316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33317         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33318         121,
  33319         -1,
  33320     },
  33321 #endif /* chips */
  33322 
  33323 #if defined(BCM_56160_A0)
  33324     { /* SOC_REG_INT_GR9216_BCM56160_A0r */
  33325         soc_block_list[2],
  33326         soc_portreg,
  33327         1,
  33328         0,
  33329         0x1a00,
  33330         SOC_REG_FLAG_COUNTER,
  33331         0,
  33332         1,
  33333         soc_GR1023_BCM53400_A0r_fields,
  33334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33335         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33336         125,
  33337         -1,
  33338     },
  33339 #endif /* chips */
  33340 
  33341 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  33342     { /* SOC_REG_INT_GR9216_BCM56334_A0r */
  33343         soc_block_list[210],
  33344         soc_portreg,
  33345         1,
  33346         0,
  33347         0x9a,
  33348         SOC_REG_FLAG_COUNTER,
  33349         0,
  33350         1,
  33351         soc_GR1023r_fields,
  33352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33353         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33354         196,
  33355         -1,
  33356     },
  33357 #endif /* chips */
  33358 
  33359 #if defined(BCM_56370_A0)
  33360     { /* SOC_REG_INT_GR9216_BCM56370_A0r */
  33361         soc_block_list[9],
  33362         soc_portreg,
  33363         1,
  33364         0,
  33365         0x1a00,
  33366         SOC_REG_FLAG_COUNTER,
  33367         0,
  33368         1,
  33369         soc_GR1023_BCM53400_A0r_fields,
  33370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33372         86,
  33373         -1,
  33374         3,
  33375     },
  33376 #endif /* chips */
  33377 
  33378 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  33379     { /* SOC_REG_INT_GR9216_BCM56440_A0r */
  33380         soc_block_list[2],
  33381         soc_portreg,
  33382         1,
  33383         0,
  33384         0x9a,
  33385         SOC_REG_FLAG_COUNTER,
  33386         0,
  33387         1,
  33388         soc_GR1023r_fields,
  33389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33390         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33391         193,
  33392         -1,
  33393     },
  33394 #endif /* chips */
  33395 
  33396 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  33397     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  33398     { /* SOC_REG_INT_GR9216_BCM56624_A0r */
  33399         soc_block_list[205],
  33400         soc_portreg,
  33401         1,
  33402         0,
  33403         0x89,
  33404         SOC_REG_FLAG_COUNTER,
  33405         0,
  33406         1,
  33407         soc_GR1023r_fields,
  33408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33409         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33410         179,
  33411         -1,
  33412     },
  33413 #endif /* chips */
  33414 
  33415 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  33416     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  33417     { /* SOC_REG_INT_GR9216_BCM56634_A0r */
  33418         soc_block_list[207],
  33419         soc_portreg,
  33420         1,
  33421         0,
  33422         0x89,
  33423         SOC_REG_FLAG_COUNTER,
  33424         0,
  33425         1,
  33426         soc_GR1023r_fields,
  33427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33429         179,
  33430         -1,
  33431     },
  33432 #endif /* chips */
  33433 
  33434 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  33435     { /* SOC_REG_INT_GR9216_BCM56685_A0r */
  33436         soc_block_list[209],
  33437         soc_portreg,
  33438         1,
  33439         0,
  33440         0x89,
  33441         SOC_REG_FLAG_COUNTER,
  33442         0,
  33443         1,
  33444         soc_GR1023r_fields,
  33445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33446         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33447         179,
  33448         -1,
  33449     },
  33450 #endif /* chips */
  33451 
  33452 #if defined(BCM_56800_A0)
  33453     { /* SOC_REG_INT_GR9216_BCM56800_A0r */
  33454         soc_block_list[9],
  33455         soc_portreg,
  33456         1,
  33457         0,
  33458         0x50,
  33459         SOC_REG_FLAG_COUNTER,
  33460         0,
  33461         1,
  33462         soc_GR1023r_fields,
  33463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33464         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33465         122,
  33466         -1,
  33467     },
  33468 #endif /* chips */
  33469 
  33470 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  33471     { /* SOC_REG_INT_GR9216_BCM56820_A0r */
  33472         soc_block_list[206],
  33473         soc_portreg,
  33474         1,
  33475         0,
  33476         0x89,
  33477         SOC_REG_FLAG_COUNTER,
  33478         0,
  33479         1,
  33480         soc_GR1023r_fields,
  33481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33482         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33483         189,
  33484         -1,
  33485     },
  33486 #endif /* chips */
  33487 
  33488 #if defined(BCM_88375_A0)
  33489     { /* SOC_REG_INT_GR9216_BCM88375_A0r */
  33490         soc_block_list[2],
  33491         soc_portreg,
  33492         1,
  33493         0,
  33494         0x1a00,
  33495         SOC_REG_FLAG_COUNTER,
  33496         0,
  33497         1,
  33498         soc_GR9216_BCM88375_A0r_fields,
  33499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33501         26,
  33502         -1,
  33503     },
  33504 #endif /* chips */
  33505 
  33506 #if defined(BCM_88375_B0)
  33507     { /* SOC_REG_INT_GR9216_BCM88375_B0r */
  33508         soc_block_list[2],
  33509         soc_portreg,
  33510         1,
  33511         0,
  33512         0x1a00,
  33513         SOC_REG_FLAG_COUNTER,
  33514         0,
  33515         1,
  33516         soc_GR9216_BCM88375_B0r_fields,
  33517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33518         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33519         26,
  33520         -1,
  33521     },
  33522 #endif /* chips */
  33523 
  33524 #if defined(BCM_88470_A0)
  33525     { /* SOC_REG_INT_GR9216_BCM88470_A0r */
  33526         soc_block_list[2],
  33527         soc_portreg,
  33528         1,
  33529         0,
  33530         0x1a00,
  33531         SOC_REG_FLAG_COUNTER,
  33532         0,
  33533         1,
  33534         soc_GR9216_BCM88470_A0r_fields,
  33535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33536         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33537         26,
  33538         -1,
  33539     },
  33540 #endif /* chips */
  33541 
  33542 #if defined(BCM_88470_B0)
  33543     { /* SOC_REG_INT_GR9216_BCM88470_B0r */
  33544         soc_block_list[2],
  33545         soc_portreg,
  33546         1,
  33547         0,
  33548         0x1a00,
  33549         SOC_REG_FLAG_COUNTER,
  33550         0,
  33551         1,
  33552         soc_GR9216_BCM88470_B0r_fields,
  33553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33554         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33555         26,
  33556         -1,
  33557     },
  33558 #endif /* chips */
  33559 
  33560 #if defined(BCM_88675_A0)
  33561     { /* SOC_REG_INT_GR9216_BCM88675_A0r */
  33562         soc_block_list[2],
  33563         soc_portreg,
  33564         1,
  33565         0,
  33566         0x1a00,
  33567         SOC_REG_FLAG_COUNTER,
  33568         0,
  33569         1,
  33570         soc_GR9216r_fields,
  33571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33572         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33573         26,
  33574         -1,
  33575     },
  33576 #endif /* chips */
  33577 
  33578 #if defined(BCM_88675_B0)
  33579     { /* SOC_REG_INT_GR9216_BCM88675_B0r */
  33580         soc_block_list[2],
  33581         soc_portreg,
  33582         1,
  33583         0,
  33584         0x1a00,
  33585         SOC_REG_FLAG_COUNTER,
  33586         0,
  33587         1,
  33588         soc_GR9216_BCM88675_B0r_fields,
  33589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33590         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33591         26,
  33592         -1,
  33593     },
  33594 #endif /* chips */
  33595 
  33596 #if defined(BCM_88680_A0)
  33597     { /* SOC_REG_INT_GR9216_BCM88680_A0r */
  33598         soc_block_list[2],
  33599         soc_portreg,
  33600         1,
  33601         0,
  33602         0x1a00,
  33603         SOC_REG_FLAG_COUNTER,
  33604         0,
  33605         1,
  33606         soc_GR9216_BCM88680_A0r_fields,
  33607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33608         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33609         26,
  33610         -1,
  33611     },
  33612 #endif /* chips */
  33613 
  33614 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  33615     defined(BCM_56504_B0)
  33616     { /* SOC_REG_INT_GRALNr */
  33617         soc_block_list[2],
  33618         soc_portreg,
  33619         1,
  33620         0,
  33621         0x12,
  33622         SOC_REG_FLAG_COUNTER |
  33623                           SOC_REG_FLAG_ED_CNTR,
  33624         0,
  33625         1,
  33626         soc_GR1023r_fields,
  33627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33628         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33629         52,
  33630         -1,
  33631     },
  33632 #endif /* chips */
  33633 
  33634 #if defined(BCM_53570_A0)
  33635     { /* SOC_REG_INT_GRALNPr */
  33636         soc_block_list[2],
  33637         soc_portreg,
  33638         1,
  33639         0,
  33640         0x6300,
  33641         SOC_REG_FLAG_COUNTER,
  33642         0,
  33643         1,
  33644         soc_GR1023_BCM53400_A0r_fields,
  33645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33646         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33647         253,
  33648         -1,
  33649     },
  33650 #endif /* chips */
  33651 
  33652 #if defined(BCM_53570_B0)
  33653     { /* SOC_REG_INT_GRALNP_BCM53570_B0r */
  33654         soc_block_list[2],
  33655         soc_portreg,
  33656         1,
  33657         0,
  33658         0x6300,
  33659         SOC_REG_FLAG_COUNTER,
  33660         0,
  33661         1,
  33662         soc_GR1023_BCM53400_A0r_fields,
  33663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33665         257,
  33666         -1,
  33667     },
  33668 #endif /* chips */
  33669 
  33670 #if defined(BCM_53400_A0)
  33671     { /* SOC_REG_INT_GRALN_BCM53400_A0r */
  33672         soc_block_list[9],
  33673         soc_portreg,
  33674         1,
  33675         0,
  33676         0x400,
  33677         SOC_REG_FLAG_COUNTER,
  33678         0,
  33679         1,
  33680         soc_GR1023_BCM53400_A0r_fields,
  33681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33682         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33683         103,
  33684         -1,
  33685     },
  33686 #endif /* chips */
  33687 
  33688 #if defined(BCM_53540_A0)
  33689     { /* SOC_REG_INT_GRALN_BCM53540_A0r */
  33690         soc_block_list[2],
  33691         soc_portreg,
  33692         1,
  33693         0,
  33694         0x400,
  33695         SOC_REG_FLAG_COUNTER,
  33696         0,
  33697         1,
  33698         soc_GR1023_BCM53400_A0r_fields,
  33699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33701         103,
  33702         -1,
  33703     },
  33704 #endif /* chips */
  33705 
  33706 #if defined(BCM_53570_A0)
  33707     { /* SOC_REG_INT_GRALN_BCM53570_A0r */
  33708         soc_block_list[2],
  33709         soc_portreg,
  33710         1,
  33711         0,
  33712         0x400,
  33713         SOC_REG_FLAG_COUNTER,
  33714         0,
  33715         1,
  33716         soc_GR1023_BCM53400_A0r_fields,
  33717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33718         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33719         158,
  33720         -1,
  33721     },
  33722 #endif /* chips */
  33723 
  33724 #if defined(BCM_53570_B0)
  33725     { /* SOC_REG_INT_GRALN_BCM53570_B0r */
  33726         soc_block_list[2],
  33727         soc_portreg,
  33728         1,
  33729         0,
  33730         0x400,
  33731         SOC_REG_FLAG_COUNTER,
  33732         0,
  33733         1,
  33734         soc_GR1023_BCM53400_A0r_fields,
  33735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33736         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33737         162,
  33738         -1,
  33739     },
  33740 #endif /* chips */
  33741 
  33742 #if defined(BCM_56142_A0)
  33743     { /* SOC_REG_INT_GRALN_BCM56142_A0r */
  33744         soc_block_list[210],
  33745         soc_portreg,
  33746         1,
  33747         0,
  33748         0x84,
  33749         SOC_REG_FLAG_COUNTER,
  33750         0,
  33751         1,
  33752         soc_GR1023r_fields,
  33753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33754         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33755         179,
  33756         -1,
  33757     },
  33758 #endif /* chips */
  33759 
  33760 #if defined(BCM_56150_A0)
  33761     { /* SOC_REG_INT_GRALN_BCM56150_A0r */
  33762         soc_block_list[2],
  33763         soc_portreg,
  33764         1,
  33765         0,
  33766         0x400,
  33767         SOC_REG_FLAG_COUNTER,
  33768         0,
  33769         1,
  33770         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  33771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33773         99,
  33774         -1,
  33775     },
  33776 #endif /* chips */
  33777 
  33778 #if defined(BCM_56160_A0)
  33779     { /* SOC_REG_INT_GRALN_BCM56160_A0r */
  33780         soc_block_list[2],
  33781         soc_portreg,
  33782         1,
  33783         0,
  33784         0x400,
  33785         SOC_REG_FLAG_COUNTER,
  33786         0,
  33787         1,
  33788         soc_GR1023_BCM53400_A0r_fields,
  33789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33791         103,
  33792         -1,
  33793     },
  33794 #endif /* chips */
  33795 
  33796 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  33797     { /* SOC_REG_INT_GRALN_BCM56334_A0r */
  33798         soc_block_list[210],
  33799         soc_portreg,
  33800         1,
  33801         0,
  33802         0x84,
  33803         SOC_REG_FLAG_COUNTER,
  33804         0,
  33805         1,
  33806         soc_GR1023r_fields,
  33807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33808         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33809         174,
  33810         -1,
  33811     },
  33812 #endif /* chips */
  33813 
  33814 #if defined(BCM_56370_A0)
  33815     { /* SOC_REG_INT_GRALN_BCM56370_A0r */
  33816         soc_block_list[9],
  33817         soc_portreg,
  33818         1,
  33819         0,
  33820         0x400,
  33821         SOC_REG_FLAG_COUNTER,
  33822         0,
  33823         1,
  33824         soc_GR1023_BCM53400_A0r_fields,
  33825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33826         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33827         64,
  33828         -1,
  33829         3,
  33830     },
  33831 #endif /* chips */
  33832 
  33833 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  33834     { /* SOC_REG_INT_GRALN_BCM56440_A0r */
  33835         soc_block_list[2],
  33836         soc_portreg,
  33837         1,
  33838         0,
  33839         0x84,
  33840         SOC_REG_FLAG_COUNTER,
  33841         0,
  33842         1,
  33843         soc_GR1023r_fields,
  33844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33845         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33846         171,
  33847         -1,
  33848     },
  33849 #endif /* chips */
  33850 
  33851 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  33852     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  33853     defined(BCM_56514_A0)
  33854     { /* SOC_REG_INT_GRALN_BCM56514_A0r */
  33855         soc_block_list[2],
  33856         soc_portreg,
  33857         1,
  33858         0,
  33859         0x12,
  33860         SOC_REG_FLAG_COUNTER,
  33861         0,
  33862         1,
  33863         soc_GR1023r_fields,
  33864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33865         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33866         52,
  33867         -1,
  33868     },
  33869 #endif /* chips */
  33870 
  33871 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  33872     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  33873     { /* SOC_REG_INT_GRALN_BCM56624_A0r */
  33874         soc_block_list[205],
  33875         soc_portreg,
  33876         1,
  33877         0,
  33878         0x92,
  33879         SOC_REG_FLAG_COUNTER,
  33880         0,
  33881         1,
  33882         soc_GR1023r_fields,
  33883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33884         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33885         188,
  33886         -1,
  33887     },
  33888 #endif /* chips */
  33889 
  33890 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  33891     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  33892     { /* SOC_REG_INT_GRALN_BCM56634_A0r */
  33893         soc_block_list[207],
  33894         soc_portreg,
  33895         1,
  33896         0,
  33897         0x92,
  33898         SOC_REG_FLAG_COUNTER,
  33899         0,
  33900         1,
  33901         soc_GR1023r_fields,
  33902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33904         188,
  33905         -1,
  33906     },
  33907 #endif /* chips */
  33908 
  33909 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  33910     { /* SOC_REG_INT_GRALN_BCM56685_A0r */
  33911         soc_block_list[209],
  33912         soc_portreg,
  33913         1,
  33914         0,
  33915         0x92,
  33916         SOC_REG_FLAG_COUNTER,
  33917         0,
  33918         1,
  33919         soc_GR1023r_fields,
  33920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33922         188,
  33923         -1,
  33924     },
  33925 #endif /* chips */
  33926 
  33927 #if defined(BCM_56800_A0)
  33928     { /* SOC_REG_INT_GRALN_BCM56800_A0r */
  33929         soc_block_list[9],
  33930         soc_portreg,
  33931         1,
  33932         0,
  33933         0x59,
  33934         SOC_REG_FLAG_COUNTER,
  33935         0,
  33936         1,
  33937         soc_GR1023r_fields,
  33938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33940         131,
  33941         -1,
  33942     },
  33943 #endif /* chips */
  33944 
  33945 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  33946     { /* SOC_REG_INT_GRALN_BCM56820_A0r */
  33947         soc_block_list[206],
  33948         soc_portreg,
  33949         1,
  33950         0,
  33951         0x92,
  33952         SOC_REG_FLAG_COUNTER,
  33953         0,
  33954         1,
  33955         soc_GR1023r_fields,
  33956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33958         198,
  33959         -1,
  33960     },
  33961 #endif /* chips */
  33962 
  33963 #if defined(BCM_88375_A0)
  33964     { /* SOC_REG_INT_GRALN_BCM88375_A0r */
  33965         soc_block_list[2],
  33966         soc_portreg,
  33967         1,
  33968         0,
  33969         0x400,
  33970         SOC_REG_FLAG_COUNTER,
  33971         0,
  33972         1,
  33973         soc_GRALN_BCM88375_A0r_fields,
  33974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33975         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33976         4,
  33977         -1,
  33978     },
  33979 #endif /* chips */
  33980 
  33981 #if defined(BCM_88375_B0)
  33982     { /* SOC_REG_INT_GRALN_BCM88375_B0r */
  33983         soc_block_list[2],
  33984         soc_portreg,
  33985         1,
  33986         0,
  33987         0x400,
  33988         SOC_REG_FLAG_COUNTER,
  33989         0,
  33990         1,
  33991         soc_GRALN_BCM88375_B0r_fields,
  33992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33993         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33994         4,
  33995         -1,
  33996     },
  33997 #endif /* chips */
  33998 
  33999 #if defined(BCM_88470_A0)
  34000     { /* SOC_REG_INT_GRALN_BCM88470_A0r */
  34001         soc_block_list[2],
  34002         soc_portreg,
  34003         1,
  34004         0,
  34005         0x400,
  34006         SOC_REG_FLAG_COUNTER,
  34007         0,
  34008         1,
  34009         soc_GRALN_BCM88470_A0r_fields,
  34010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34011         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34012         4,
  34013         -1,
  34014     },
  34015 #endif /* chips */
  34016 
  34017 #if defined(BCM_88470_B0)
  34018     { /* SOC_REG_INT_GRALN_BCM88470_B0r */
  34019         soc_block_list[2],
  34020         soc_portreg,
  34021         1,
  34022         0,
  34023         0x400,
  34024         SOC_REG_FLAG_COUNTER,
  34025         0,
  34026         1,
  34027         soc_GRALN_BCM88470_B0r_fields,
  34028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34029         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34030         4,
  34031         -1,
  34032     },
  34033 #endif /* chips */
  34034 
  34035 #if defined(BCM_88675_A0)
  34036     { /* SOC_REG_INT_GRALN_BCM88675_A0r */
  34037         soc_block_list[2],
  34038         soc_portreg,
  34039         1,
  34040         0,
  34041         0x400,
  34042         SOC_REG_FLAG_COUNTER,
  34043         0,
  34044         1,
  34045         soc_GRALNr_fields,
  34046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34047         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34048         4,
  34049         -1,
  34050     },
  34051 #endif /* chips */
  34052 
  34053 #if defined(BCM_88675_B0)
  34054     { /* SOC_REG_INT_GRALN_BCM88675_B0r */
  34055         soc_block_list[2],
  34056         soc_portreg,
  34057         1,
  34058         0,
  34059         0x400,
  34060         SOC_REG_FLAG_COUNTER,
  34061         0,
  34062         1,
  34063         soc_GRALN_BCM88675_B0r_fields,
  34064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34065         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34066         4,
  34067         -1,
  34068     },
  34069 #endif /* chips */
  34070 
  34071 #if defined(BCM_88680_A0)
  34072     { /* SOC_REG_INT_GRALN_BCM88680_A0r */
  34073         soc_block_list[2],
  34074         soc_portreg,
  34075         1,
  34076         0,
  34077         0x400,
  34078         SOC_REG_FLAG_COUNTER,
  34079         0,
  34080         1,
  34081         soc_GRALN_BCM88680_A0r_fields,
  34082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34083         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34084         4,
  34085         -1,
  34086     },
  34087 #endif /* chips */
  34088 
  34089 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  34090     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  34091     { /* SOC_REG_INT_GRBCAr */
  34092         soc_block_list[2],
  34093         soc_portreg,
  34094         1,
  34095         0,
  34096         0xd,
  34097         SOC_REG_FLAG_COUNTER,
  34098         0,
  34099         1,
  34100         soc_GR1023r_fields,
  34101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34102         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34103         47,
  34104         -1,
  34105     },
  34106 #endif /* chips */
  34107 
  34108 #if defined(BCM_53570_A0)
  34109     { /* SOC_REG_INT_GRBCAPr */
  34110         soc_block_list[2],
  34111         soc_portreg,
  34112         1,
  34113         0,
  34114         0x6f00,
  34115         SOC_REG_FLAG_COUNTER,
  34116         0,
  34117         1,
  34118         soc_GR1023_BCM53400_A0r_fields,
  34119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34120         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34121         265,
  34122         -1,
  34123     },
  34124 #endif /* chips */
  34125 
  34126 #if defined(BCM_53570_B0)
  34127     { /* SOC_REG_INT_GRBCAP_BCM53570_B0r */
  34128         soc_block_list[2],
  34129         soc_portreg,
  34130         1,
  34131         0,
  34132         0x6f00,
  34133         SOC_REG_FLAG_COUNTER,
  34134         0,
  34135         1,
  34136         soc_GR1023_BCM53400_A0r_fields,
  34137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34138         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34139         269,
  34140         -1,
  34141     },
  34142 #endif /* chips */
  34143 
  34144 #if defined(BCM_53400_A0)
  34145     { /* SOC_REG_INT_GRBCA_BCM53400_A0r */
  34146         soc_block_list[9],
  34147         soc_portreg,
  34148         1,
  34149         0,
  34150         0x1000,
  34151         SOC_REG_FLAG_COUNTER,
  34152         0,
  34153         1,
  34154         soc_GR1023_BCM53400_A0r_fields,
  34155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34156         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34157         115,
  34158         -1,
  34159     },
  34160 #endif /* chips */
  34161 
  34162 #if defined(BCM_53540_A0)
  34163     { /* SOC_REG_INT_GRBCA_BCM53540_A0r */
  34164         soc_block_list[2],
  34165         soc_portreg,
  34166         1,
  34167         0,
  34168         0x1000,
  34169         SOC_REG_FLAG_COUNTER,
  34170         0,
  34171         1,
  34172         soc_GR1023_BCM53400_A0r_fields,
  34173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34174         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34175         115,
  34176         -1,
  34177     },
  34178 #endif /* chips */
  34179 
  34180 #if defined(BCM_53570_A0)
  34181     { /* SOC_REG_INT_GRBCA_BCM53570_A0r */
  34182         soc_block_list[2],
  34183         soc_portreg,
  34184         1,
  34185         0,
  34186         0x1000,
  34187         SOC_REG_FLAG_COUNTER,
  34188         0,
  34189         1,
  34190         soc_GR1023_BCM53400_A0r_fields,
  34191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34192         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34193         170,
  34194         -1,
  34195     },
  34196 #endif /* chips */
  34197 
  34198 #if defined(BCM_53570_B0)
  34199     { /* SOC_REG_INT_GRBCA_BCM53570_B0r */
  34200         soc_block_list[2],
  34201         soc_portreg,
  34202         1,
  34203         0,
  34204         0x1000,
  34205         SOC_REG_FLAG_COUNTER,
  34206         0,
  34207         1,
  34208         soc_GR1023_BCM53400_A0r_fields,
  34209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34210         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34211         174,
  34212         -1,
  34213     },
  34214 #endif /* chips */
  34215 
  34216 #if defined(BCM_56142_A0)
  34217     { /* SOC_REG_INT_GRBCA_BCM56142_A0r */
  34218         soc_block_list[210],
  34219         soc_portreg,
  34220         1,
  34221         0,
  34222         0x90,
  34223         SOC_REG_FLAG_COUNTER,
  34224         0,
  34225         1,
  34226         soc_GR1023r_fields,
  34227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34228         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34229         191,
  34230         -1,
  34231     },
  34232 #endif /* chips */
  34233 
  34234 #if defined(BCM_56150_A0)
  34235     { /* SOC_REG_INT_GRBCA_BCM56150_A0r */
  34236         soc_block_list[2],
  34237         soc_portreg,
  34238         1,
  34239         0,
  34240         0x1000,
  34241         SOC_REG_FLAG_COUNTER,
  34242         0,
  34243         1,
  34244         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  34245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34246         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34247         111,
  34248         -1,
  34249     },
  34250 #endif /* chips */
  34251 
  34252 #if defined(BCM_56160_A0)
  34253     { /* SOC_REG_INT_GRBCA_BCM56160_A0r */
  34254         soc_block_list[2],
  34255         soc_portreg,
  34256         1,
  34257         0,
  34258         0x1000,
  34259         SOC_REG_FLAG_COUNTER,
  34260         0,
  34261         1,
  34262         soc_GR1023_BCM53400_A0r_fields,
  34263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34264         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34265         115,
  34266         -1,
  34267     },
  34268 #endif /* chips */
  34269 
  34270 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  34271     { /* SOC_REG_INT_GRBCA_BCM56334_A0r */
  34272         soc_block_list[210],
  34273         soc_portreg,
  34274         1,
  34275         0,
  34276         0x90,
  34277         SOC_REG_FLAG_COUNTER,
  34278         0,
  34279         1,
  34280         soc_GR1023r_fields,
  34281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34282         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34283         186,
  34284         -1,
  34285     },
  34286 #endif /* chips */
  34287 
  34288 #if defined(BCM_56370_A0)
  34289     { /* SOC_REG_INT_GRBCA_BCM56370_A0r */
  34290         soc_block_list[9],
  34291         soc_portreg,
  34292         1,
  34293         0,
  34294         0x1000,
  34295         SOC_REG_FLAG_COUNTER,
  34296         0,
  34297         1,
  34298         soc_GR1023_BCM53400_A0r_fields,
  34299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34300         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34301         76,
  34302         -1,
  34303         3,
  34304     },
  34305 #endif /* chips */
  34306 
  34307 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  34308     { /* SOC_REG_INT_GRBCA_BCM56440_A0r */
  34309         soc_block_list[2],
  34310         soc_portreg,
  34311         1,
  34312         0,
  34313         0x90,
  34314         SOC_REG_FLAG_COUNTER,
  34315         0,
  34316         1,
  34317         soc_GR1023r_fields,
  34318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34319         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34320         183,
  34321         -1,
  34322     },
  34323 #endif /* chips */
  34324 
  34325 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  34326     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  34327     { /* SOC_REG_INT_GRBCA_BCM56624_A0r */
  34328         soc_block_list[205],
  34329         soc_portreg,
  34330         1,
  34331         0,
  34332         0x8d,
  34333         SOC_REG_FLAG_COUNTER,
  34334         0,
  34335         1,
  34336         soc_GR1023r_fields,
  34337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34339         183,
  34340         -1,
  34341     },
  34342 #endif /* chips */
  34343 
  34344 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  34345     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  34346     { /* SOC_REG_INT_GRBCA_BCM56634_A0r */
  34347         soc_block_list[207],
  34348         soc_portreg,
  34349         1,
  34350         0,
  34351         0x8d,
  34352         SOC_REG_FLAG_COUNTER,
  34353         0,
  34354         1,
  34355         soc_GR1023r_fields,
  34356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34358         183,
  34359         -1,
  34360     },
  34361 #endif /* chips */
  34362 
  34363 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  34364     { /* SOC_REG_INT_GRBCA_BCM56685_A0r */
  34365         soc_block_list[209],
  34366         soc_portreg,
  34367         1,
  34368         0,
  34369         0x8d,
  34370         SOC_REG_FLAG_COUNTER,
  34371         0,
  34372         1,
  34373         soc_GR1023r_fields,
  34374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34375         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34376         183,
  34377         -1,
  34378     },
  34379 #endif /* chips */
  34380 
  34381 #if defined(BCM_56800_A0)
  34382     { /* SOC_REG_INT_GRBCA_BCM56800_A0r */
  34383         soc_block_list[9],
  34384         soc_portreg,
  34385         1,
  34386         0,
  34387         0x54,
  34388         SOC_REG_FLAG_COUNTER,
  34389         0,
  34390         1,
  34391         soc_GR1023r_fields,
  34392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34393         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34394         126,
  34395         -1,
  34396     },
  34397 #endif /* chips */
  34398 
  34399 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  34400     { /* SOC_REG_INT_GRBCA_BCM56820_A0r */
  34401         soc_block_list[206],
  34402         soc_portreg,
  34403         1,
  34404         0,
  34405         0x8d,
  34406         SOC_REG_FLAG_COUNTER,
  34407         0,
  34408         1,
  34409         soc_GR1023r_fields,
  34410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34411         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34412         193,
  34413         -1,
  34414     },
  34415 #endif /* chips */
  34416 
  34417 #if defined(BCM_88375_A0)
  34418     { /* SOC_REG_INT_GRBCA_BCM88375_A0r */
  34419         soc_block_list[2],
  34420         soc_portreg,
  34421         1,
  34422         0,
  34423         0x1000,
  34424         SOC_REG_FLAG_COUNTER,
  34425         0,
  34426         1,
  34427         soc_GRBCA_BCM88375_A0r_fields,
  34428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34429         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34430         16,
  34431         -1,
  34432     },
  34433 #endif /* chips */
  34434 
  34435 #if defined(BCM_88375_B0)
  34436     { /* SOC_REG_INT_GRBCA_BCM88375_B0r */
  34437         soc_block_list[2],
  34438         soc_portreg,
  34439         1,
  34440         0,
  34441         0x1000,
  34442         SOC_REG_FLAG_COUNTER,
  34443         0,
  34444         1,
  34445         soc_GRBCA_BCM88375_B0r_fields,
  34446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34447         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34448         16,
  34449         -1,
  34450     },
  34451 #endif /* chips */
  34452 
  34453 #if defined(BCM_88470_A0)
  34454     { /* SOC_REG_INT_GRBCA_BCM88470_A0r */
  34455         soc_block_list[2],
  34456         soc_portreg,
  34457         1,
  34458         0,
  34459         0x1000,
  34460         SOC_REG_FLAG_COUNTER,
  34461         0,
  34462         1,
  34463         soc_GRBCA_BCM88470_A0r_fields,
  34464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34465         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34466         16,
  34467         -1,
  34468     },
  34469 #endif /* chips */
  34470 
  34471 #if defined(BCM_88470_B0)
  34472     { /* SOC_REG_INT_GRBCA_BCM88470_B0r */
  34473         soc_block_list[2],
  34474         soc_portreg,
  34475         1,
  34476         0,
  34477         0x1000,
  34478         SOC_REG_FLAG_COUNTER,
  34479         0,
  34480         1,
  34481         soc_GRBCA_BCM88470_B0r_fields,
  34482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34483         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34484         16,
  34485         -1,
  34486     },
  34487 #endif /* chips */
  34488 
  34489 #if defined(BCM_88675_A0)
  34490     { /* SOC_REG_INT_GRBCA_BCM88675_A0r */
  34491         soc_block_list[2],
  34492         soc_portreg,
  34493         1,
  34494         0,
  34495         0x1000,
  34496         SOC_REG_FLAG_COUNTER,
  34497         0,
  34498         1,
  34499         soc_GRBCAr_fields,
  34500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34501         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34502         16,
  34503         -1,
  34504     },
  34505 #endif /* chips */
  34506 
  34507 #if defined(BCM_88675_B0)
  34508     { /* SOC_REG_INT_GRBCA_BCM88675_B0r */
  34509         soc_block_list[2],
  34510         soc_portreg,
  34511         1,
  34512         0,
  34513         0x1000,
  34514         SOC_REG_FLAG_COUNTER,
  34515         0,
  34516         1,
  34517         soc_GRBCA_BCM88675_B0r_fields,
  34518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34519         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34520         16,
  34521         -1,
  34522     },
  34523 #endif /* chips */
  34524 
  34525 #if defined(BCM_88680_A0)
  34526     { /* SOC_REG_INT_GRBCA_BCM88680_A0r */
  34527         soc_block_list[2],
  34528         soc_portreg,
  34529         1,
  34530         0,
  34531         0x1000,
  34532         SOC_REG_FLAG_COUNTER,
  34533         0,
  34534         1,
  34535         soc_GRBCA_BCM88680_A0r_fields,
  34536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34538         16,
  34539         -1,
  34540     },
  34541 #endif /* chips */
  34542 
  34543 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  34544     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  34545     { /* SOC_REG_INT_GRBYTr */
  34546         soc_block_list[2],
  34547         soc_portreg,
  34548         1,
  34549         0,
  34550         0xb,
  34551         SOC_REG_FLAG_COUNTER,
  34552         0,
  34553         1,
  34554         soc_GR1023r_fields,
  34555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34556         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34557         45,
  34558         -1,
  34559     },
  34560 #endif /* chips */
  34561 
  34562 #if defined(BCM_53570_A0)
  34563     { /* SOC_REG_INT_GRBYTPr */
  34564         soc_block_list[2],
  34565         soc_portreg,
  34566         1,
  34567         0,
  34568         0x7b00,
  34569         SOC_REG_FLAG_COUNTER,
  34570         0,
  34571         1,
  34572         soc_GR1023_BCM53400_A0r_fields,
  34573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34574         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34575         277,
  34576         -1,
  34577     },
  34578 #endif /* chips */
  34579 
  34580 #if defined(BCM_53570_B0)
  34581     { /* SOC_REG_INT_GRBYTP_BCM53570_B0r */
  34582         soc_block_list[2],
  34583         soc_portreg,
  34584         1,
  34585         0,
  34586         0x7b00,
  34587         SOC_REG_FLAG_COUNTER,
  34588         0,
  34589         1,
  34590         soc_GR1023_BCM53400_A0r_fields,
  34591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34592         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34593         281,
  34594         -1,
  34595     },
  34596 #endif /* chips */
  34597 
  34598 #if defined(BCM_53400_A0)
  34599     { /* SOC_REG_INT_GRBYT_BCM53400_A0r */
  34600         soc_block_list[9],
  34601         soc_portreg,
  34602         1,
  34603         0,
  34604         0x1c00,
  34605         SOC_REG_FLAG_COUNTER,
  34606         0,
  34607         1,
  34608         soc_GR1023_BCM53400_A0r_fields,
  34609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34610         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34611         127,
  34612         -1,
  34613     },
  34614 #endif /* chips */
  34615 
  34616 #if defined(BCM_53540_A0)
  34617     { /* SOC_REG_INT_GRBYT_BCM53540_A0r */
  34618         soc_block_list[2],
  34619         soc_portreg,
  34620         1,
  34621         0,
  34622         0x1c00,
  34623         SOC_REG_FLAG_COUNTER,
  34624         0,
  34625         1,
  34626         soc_GR1023_BCM53400_A0r_fields,
  34627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34628         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34629         127,
  34630         -1,
  34631     },
  34632 #endif /* chips */
  34633 
  34634 #if defined(BCM_53570_A0)
  34635     { /* SOC_REG_INT_GRBYT_BCM53570_A0r */
  34636         soc_block_list[2],
  34637         soc_portreg,
  34638         1,
  34639         0,
  34640         0x1c00,
  34641         SOC_REG_FLAG_COUNTER,
  34642         0,
  34643         1,
  34644         soc_GR1023_BCM53400_A0r_fields,
  34645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34646         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34647         182,
  34648         -1,
  34649     },
  34650 #endif /* chips */
  34651 
  34652 #if defined(BCM_53570_B0)
  34653     { /* SOC_REG_INT_GRBYT_BCM53570_B0r */
  34654         soc_block_list[2],
  34655         soc_portreg,
  34656         1,
  34657         0,
  34658         0x1c00,
  34659         SOC_REG_FLAG_COUNTER,
  34660         0,
  34661         1,
  34662         soc_GR1023_BCM53400_A0r_fields,
  34663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34665         186,
  34666         -1,
  34667     },
  34668 #endif /* chips */
  34669 
  34670 #if defined(BCM_56142_A0)
  34671     { /* SOC_REG_INT_GRBYT_BCM56142_A0r */
  34672         soc_block_list[210],
  34673         soc_portreg,
  34674         1,
  34675         0,
  34676         0x9c,
  34677         SOC_REG_FLAG_COUNTER,
  34678         0,
  34679         1,
  34680         soc_GR1023r_fields,
  34681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34682         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34683         203,
  34684         -1,
  34685     },
  34686 #endif /* chips */
  34687 
  34688 #if defined(BCM_56150_A0)
  34689     { /* SOC_REG_INT_GRBYT_BCM56150_A0r */
  34690         soc_block_list[2],
  34691         soc_portreg,
  34692         1,
  34693         0,
  34694         0x1c00,
  34695         SOC_REG_FLAG_COUNTER,
  34696         0,
  34697         1,
  34698         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  34699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34701         123,
  34702         -1,
  34703     },
  34704 #endif /* chips */
  34705 
  34706 #if defined(BCM_56160_A0)
  34707     { /* SOC_REG_INT_GRBYT_BCM56160_A0r */
  34708         soc_block_list[2],
  34709         soc_portreg,
  34710         1,
  34711         0,
  34712         0x1c00,
  34713         SOC_REG_FLAG_COUNTER,
  34714         0,
  34715         1,
  34716         soc_GR1023_BCM53400_A0r_fields,
  34717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34718         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34719         127,
  34720         -1,
  34721     },
  34722 #endif /* chips */
  34723 
  34724 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  34725     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  34726     { /* SOC_REG_INT_GRBYT_BCM56224_A0r */
  34727         soc_block_list[2],
  34728         soc_portreg,
  34729         1,
  34730         0,
  34731         0x1c,
  34732         SOC_REG_FLAG_COUNTER,
  34733         0,
  34734         1,
  34735         soc_GR1023r_fields,
  34736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34737         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34738         62,
  34739         -1,
  34740     },
  34741 #endif /* chips */
  34742 
  34743 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  34744     { /* SOC_REG_INT_GRBYT_BCM56334_A0r */
  34745         soc_block_list[210],
  34746         soc_portreg,
  34747         1,
  34748         0,
  34749         0x9c,
  34750         SOC_REG_FLAG_COUNTER,
  34751         0,
  34752         1,
  34753         soc_GR1023r_fields,
  34754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34755         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34756         198,
  34757         -1,
  34758     },
  34759 #endif /* chips */
  34760 
  34761 #if defined(BCM_56370_A0)
  34762     { /* SOC_REG_INT_GRBYT_BCM56370_A0r */
  34763         soc_block_list[9],
  34764         soc_portreg,
  34765         1,
  34766         0,
  34767         0x1c00,
  34768         SOC_REG_FLAG_COUNTER,
  34769         0,
  34770         1,
  34771         soc_GR1023_BCM53400_A0r_fields,
  34772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34774         88,
  34775         -1,
  34776         3,
  34777     },
  34778 #endif /* chips */
  34779 
  34780 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  34781     { /* SOC_REG_INT_GRBYT_BCM56440_A0r */
  34782         soc_block_list[2],
  34783         soc_portreg,
  34784         1,
  34785         0,
  34786         0x9d,
  34787         SOC_REG_FLAG_COUNTER,
  34788         0,
  34789         1,
  34790         soc_GR1023r_fields,
  34791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34792         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34793         196,
  34794         -1,
  34795     },
  34796 #endif /* chips */
  34797 
  34798 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  34799     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  34800     { /* SOC_REG_INT_GRBYT_BCM56624_A0r */
  34801         soc_block_list[205],
  34802         soc_portreg,
  34803         1,
  34804         0,
  34805         0x8b,
  34806         SOC_REG_FLAG_COUNTER,
  34807         0,
  34808         1,
  34809         soc_GR1023r_fields,
  34810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34811         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34812         181,
  34813         -1,
  34814     },
  34815 #endif /* chips */
  34816 
  34817 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  34818     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  34819     { /* SOC_REG_INT_GRBYT_BCM56634_A0r */
  34820         soc_block_list[207],
  34821         soc_portreg,
  34822         1,
  34823         0,
  34824         0x8b,
  34825         SOC_REG_FLAG_COUNTER,
  34826         0,
  34827         1,
  34828         soc_GR1023r_fields,
  34829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34830         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34831         181,
  34832         -1,
  34833     },
  34834 #endif /* chips */
  34835 
  34836 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  34837     { /* SOC_REG_INT_GRBYT_BCM56685_A0r */
  34838         soc_block_list[209],
  34839         soc_portreg,
  34840         1,
  34841         0,
  34842         0x8b,
  34843         SOC_REG_FLAG_COUNTER,
  34844         0,
  34845         1,
  34846         soc_GR1023r_fields,
  34847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34848         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34849         181,
  34850         -1,
  34851     },
  34852 #endif /* chips */
  34853 
  34854 #if defined(BCM_56800_A0)
  34855     { /* SOC_REG_INT_GRBYT_BCM56800_A0r */
  34856         soc_block_list[9],
  34857         soc_portreg,
  34858         1,
  34859         0,
  34860         0x52,
  34861         SOC_REG_FLAG_COUNTER,
  34862         0,
  34863         1,
  34864         soc_GR1023r_fields,
  34865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34866         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34867         124,
  34868         -1,
  34869     },
  34870 #endif /* chips */
  34871 
  34872 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  34873     { /* SOC_REG_INT_GRBYT_BCM56820_A0r */
  34874         soc_block_list[206],
  34875         soc_portreg,
  34876         1,
  34877         0,
  34878         0x8b,
  34879         SOC_REG_FLAG_COUNTER,
  34880         0,
  34881         1,
  34882         soc_GR1023r_fields,
  34883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34884         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34885         191,
  34886         -1,
  34887     },
  34888 #endif /* chips */
  34889 
  34890 #if defined(BCM_88375_A0)
  34891     { /* SOC_REG_INT_GRBYT_BCM88375_A0r */
  34892         soc_block_list[2],
  34893         soc_portreg,
  34894         1,
  34895         0,
  34896         0x1c00,
  34897         SOC_REG_FLAG_COUNTER,
  34898         0,
  34899         1,
  34900         soc_GRBYT_BCM88375_A0r_fields,
  34901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34902         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34903         28,
  34904         -1,
  34905     },
  34906 #endif /* chips */
  34907 
  34908 #if defined(BCM_88375_B0)
  34909     { /* SOC_REG_INT_GRBYT_BCM88375_B0r */
  34910         soc_block_list[2],
  34911         soc_portreg,
  34912         1,
  34913         0,
  34914         0x1c00,
  34915         SOC_REG_FLAG_COUNTER,
  34916         0,
  34917         1,
  34918         soc_GRBYT_BCM88375_B0r_fields,
  34919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34920         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34921         28,
  34922         -1,
  34923     },
  34924 #endif /* chips */
  34925 
  34926 #if defined(BCM_88470_A0)
  34927     { /* SOC_REG_INT_GRBYT_BCM88470_A0r */
  34928         soc_block_list[2],
  34929         soc_portreg,
  34930         1,
  34931         0,
  34932         0x1c00,
  34933         SOC_REG_FLAG_COUNTER,
  34934         0,
  34935         1,
  34936         soc_GRBYT_BCM88470_A0r_fields,
  34937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34938         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34939         28,
  34940         -1,
  34941     },
  34942 #endif /* chips */
  34943 
  34944 #if defined(BCM_88470_B0)
  34945     { /* SOC_REG_INT_GRBYT_BCM88470_B0r */
  34946         soc_block_list[2],
  34947         soc_portreg,
  34948         1,
  34949         0,
  34950         0x1c00,
  34951         SOC_REG_FLAG_COUNTER,
  34952         0,
  34953         1,
  34954         soc_GRBYT_BCM88470_B0r_fields,
  34955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34957         28,
  34958         -1,
  34959     },
  34960 #endif /* chips */
  34961 
  34962 #if defined(BCM_88675_A0)
  34963     { /* SOC_REG_INT_GRBYT_BCM88675_A0r */
  34964         soc_block_list[2],
  34965         soc_portreg,
  34966         1,
  34967         0,
  34968         0x1c00,
  34969         SOC_REG_FLAG_COUNTER,
  34970         0,
  34971         1,
  34972         soc_GRBYTr_fields,
  34973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34974         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34975         28,
  34976         -1,
  34977     },
  34978 #endif /* chips */
  34979 
  34980 #if defined(BCM_88675_B0)
  34981     { /* SOC_REG_INT_GRBYT_BCM88675_B0r */
  34982         soc_block_list[2],
  34983         soc_portreg,
  34984         1,
  34985         0,
  34986         0x1c00,
  34987         SOC_REG_FLAG_COUNTER,
  34988         0,
  34989         1,
  34990         soc_GRBYT_BCM88675_B0r_fields,
  34991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34993         28,
  34994         -1,
  34995     },
  34996 #endif /* chips */
  34997 
  34998 #if defined(BCM_88680_A0)
  34999     { /* SOC_REG_INT_GRBYT_BCM88680_A0r */
  35000         soc_block_list[2],
  35001         soc_portreg,
  35002         1,
  35003         0,
  35004         0x1c00,
  35005         SOC_REG_FLAG_COUNTER,
  35006         0,
  35007         1,
  35008         soc_GRBYT_BCM88680_A0r_fields,
  35009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35010         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35011         28,
  35012         -1,
  35013     },
  35014 #endif /* chips */
  35015 
  35016 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  35017     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  35018     { /* SOC_REG_INT_GRCDEr */
  35019         soc_block_list[2],
  35020         soc_portreg,
  35021         1,
  35022         0,
  35023         0x14,
  35024         SOC_REG_FLAG_COUNTER |
  35025                           SOC_REG_FLAG_ED_CNTR,
  35026         0,
  35027         1,
  35028         soc_GR1023r_fields,
  35029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35030         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35031         54,
  35032         -1,
  35033     },
  35034 #endif /* chips */
  35035 
  35036 #if defined(BCM_53570_A0)
  35037     { /* SOC_REG_INT_GRCDEPr */
  35038         soc_block_list[2],
  35039         soc_portreg,
  35040         1,
  35041         0,
  35042         0x6500,
  35043         SOC_REG_FLAG_COUNTER |
  35044                           SOC_REG_FLAG_ED_CNTR,
  35045         0,
  35046         1,
  35047         soc_GR1023_BCM53400_A0r_fields,
  35048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35050         255,
  35051         -1,
  35052     },
  35053 #endif /* chips */
  35054 
  35055 #if defined(BCM_53570_B0)
  35056     { /* SOC_REG_INT_GRCDEP_BCM53570_B0r */
  35057         soc_block_list[2],
  35058         soc_portreg,
  35059         1,
  35060         0,
  35061         0x6500,
  35062         SOC_REG_FLAG_COUNTER |
  35063                           SOC_REG_FLAG_ED_CNTR,
  35064         0,
  35065         1,
  35066         soc_GR1023_BCM53400_A0r_fields,
  35067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35068         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35069         259,
  35070         -1,
  35071     },
  35072 #endif /* chips */
  35073 
  35074 #if defined(BCM_53400_A0)
  35075     { /* SOC_REG_INT_GRCDE_BCM53400_A0r */
  35076         soc_block_list[9],
  35077         soc_portreg,
  35078         1,
  35079         0,
  35080         0x600,
  35081         SOC_REG_FLAG_COUNTER |
  35082                           SOC_REG_FLAG_ED_CNTR,
  35083         0,
  35084         1,
  35085         soc_GR1023_BCM53400_A0r_fields,
  35086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35088         105,
  35089         -1,
  35090     },
  35091 #endif /* chips */
  35092 
  35093 #if defined(BCM_53540_A0)
  35094     { /* SOC_REG_INT_GRCDE_BCM53540_A0r */
  35095         soc_block_list[2],
  35096         soc_portreg,
  35097         1,
  35098         0,
  35099         0x600,
  35100         SOC_REG_FLAG_COUNTER |
  35101                           SOC_REG_FLAG_ED_CNTR,
  35102         0,
  35103         1,
  35104         soc_GR1023_BCM53400_A0r_fields,
  35105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35106         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35107         105,
  35108         -1,
  35109     },
  35110 #endif /* chips */
  35111 
  35112 #if defined(BCM_53570_A0)
  35113     { /* SOC_REG_INT_GRCDE_BCM53570_A0r */
  35114         soc_block_list[2],
  35115         soc_portreg,
  35116         1,
  35117         0,
  35118         0x600,
  35119         SOC_REG_FLAG_COUNTER |
  35120                           SOC_REG_FLAG_ED_CNTR,
  35121         0,
  35122         1,
  35123         soc_GR1023_BCM53400_A0r_fields,
  35124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35125         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35126         160,
  35127         -1,
  35128     },
  35129 #endif /* chips */
  35130 
  35131 #if defined(BCM_53570_B0)
  35132     { /* SOC_REG_INT_GRCDE_BCM53570_B0r */
  35133         soc_block_list[2],
  35134         soc_portreg,
  35135         1,
  35136         0,
  35137         0x600,
  35138         SOC_REG_FLAG_COUNTER |
  35139                           SOC_REG_FLAG_ED_CNTR,
  35140         0,
  35141         1,
  35142         soc_GR1023_BCM53400_A0r_fields,
  35143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35144         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35145         164,
  35146         -1,
  35147     },
  35148 #endif /* chips */
  35149 
  35150 #if defined(BCM_56142_A0)
  35151     { /* SOC_REG_INT_GRCDE_BCM56142_A0r */
  35152         soc_block_list[210],
  35153         soc_portreg,
  35154         1,
  35155         0,
  35156         0x86,
  35157         SOC_REG_FLAG_COUNTER |
  35158                           SOC_REG_FLAG_ED_CNTR,
  35159         0,
  35160         1,
  35161         soc_GR1023r_fields,
  35162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35163         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35164         181,
  35165         -1,
  35166     },
  35167 #endif /* chips */
  35168 
  35169 #if defined(BCM_56150_A0)
  35170     { /* SOC_REG_INT_GRCDE_BCM56150_A0r */
  35171         soc_block_list[2],
  35172         soc_portreg,
  35173         1,
  35174         0,
  35175         0x600,
  35176         SOC_REG_FLAG_COUNTER |
  35177                           SOC_REG_FLAG_ED_CNTR,
  35178         0,
  35179         1,
  35180         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  35181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35182         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35183         101,
  35184         -1,
  35185     },
  35186 #endif /* chips */
  35187 
  35188 #if defined(BCM_56160_A0)
  35189     { /* SOC_REG_INT_GRCDE_BCM56160_A0r */
  35190         soc_block_list[2],
  35191         soc_portreg,
  35192         1,
  35193         0,
  35194         0x600,
  35195         SOC_REG_FLAG_COUNTER |
  35196                           SOC_REG_FLAG_ED_CNTR,
  35197         0,
  35198         1,
  35199         soc_GR1023_BCM53400_A0r_fields,
  35200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35201         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35202         105,
  35203         -1,
  35204     },
  35205 #endif /* chips */
  35206 
  35207 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  35208     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  35209     { /* SOC_REG_INT_GRCDE_BCM56224_A0r */
  35210         soc_block_list[2],
  35211         soc_portreg,
  35212         1,
  35213         0,
  35214         0x6,
  35215         SOC_REG_FLAG_COUNTER |
  35216                           SOC_REG_FLAG_ED_CNTR,
  35217         0,
  35218         1,
  35219         soc_GR1023r_fields,
  35220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35221         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35222         40,
  35223         -1,
  35224     },
  35225 #endif /* chips */
  35226 
  35227 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  35228     { /* SOC_REG_INT_GRCDE_BCM56334_A0r */
  35229         soc_block_list[210],
  35230         soc_portreg,
  35231         1,
  35232         0,
  35233         0x86,
  35234         SOC_REG_FLAG_COUNTER |
  35235                           SOC_REG_FLAG_ED_CNTR,
  35236         0,
  35237         1,
  35238         soc_GR1023r_fields,
  35239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35240         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35241         176,
  35242         -1,
  35243     },
  35244 #endif /* chips */
  35245 
  35246 #if defined(BCM_56370_A0)
  35247     { /* SOC_REG_INT_GRCDE_BCM56370_A0r */
  35248         soc_block_list[9],
  35249         soc_portreg,
  35250         1,
  35251         0,
  35252         0x600,
  35253         SOC_REG_FLAG_COUNTER |
  35254                           SOC_REG_FLAG_ED_CNTR,
  35255         0,
  35256         1,
  35257         soc_GR1023_BCM53400_A0r_fields,
  35258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35259         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35260         66,
  35261         -1,
  35262         3,
  35263     },
  35264 #endif /* chips */
  35265 
  35266 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  35267     { /* SOC_REG_INT_GRCDE_BCM56440_A0r */
  35268         soc_block_list[2],
  35269         soc_portreg,
  35270         1,
  35271         0,
  35272         0x86,
  35273         SOC_REG_FLAG_COUNTER |
  35274                           SOC_REG_FLAG_ED_CNTR,
  35275         0,
  35276         1,
  35277         soc_GR1023r_fields,
  35278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35279         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35280         173,
  35281         -1,
  35282     },
  35283 #endif /* chips */
  35284 
  35285 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  35286     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  35287     { /* SOC_REG_INT_GRCDE_BCM56624_A0r */
  35288         soc_block_list[205],
  35289         soc_portreg,
  35290         1,
  35291         0,
  35292         0x94,
  35293         SOC_REG_FLAG_COUNTER |
  35294                           SOC_REG_FLAG_ED_CNTR,
  35295         0,
  35296         1,
  35297         soc_GR1023r_fields,
  35298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35300         190,
  35301         -1,
  35302     },
  35303 #endif /* chips */
  35304 
  35305 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  35306     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  35307     { /* SOC_REG_INT_GRCDE_BCM56634_A0r */
  35308         soc_block_list[207],
  35309         soc_portreg,
  35310         1,
  35311         0,
  35312         0x94,
  35313         SOC_REG_FLAG_COUNTER |
  35314                           SOC_REG_FLAG_ED_CNTR,
  35315         0,
  35316         1,
  35317         soc_GR1023r_fields,
  35318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35319         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35320         190,
  35321         -1,
  35322     },
  35323 #endif /* chips */
  35324 
  35325 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  35326     { /* SOC_REG_INT_GRCDE_BCM56685_A0r */
  35327         soc_block_list[209],
  35328         soc_portreg,
  35329         1,
  35330         0,
  35331         0x94,
  35332         SOC_REG_FLAG_COUNTER |
  35333                           SOC_REG_FLAG_ED_CNTR,
  35334         0,
  35335         1,
  35336         soc_GR1023r_fields,
  35337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35339         190,
  35340         -1,
  35341     },
  35342 #endif /* chips */
  35343 
  35344 #if defined(BCM_56800_A0)
  35345     { /* SOC_REG_INT_GRCDE_BCM56800_A0r */
  35346         soc_block_list[9],
  35347         soc_portreg,
  35348         1,
  35349         0,
  35350         0x5b,
  35351         SOC_REG_FLAG_COUNTER |
  35352                           SOC_REG_FLAG_ED_CNTR,
  35353         0,
  35354         1,
  35355         soc_GR1023r_fields,
  35356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35358         133,
  35359         -1,
  35360     },
  35361 #endif /* chips */
  35362 
  35363 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  35364     { /* SOC_REG_INT_GRCDE_BCM56820_A0r */
  35365         soc_block_list[206],
  35366         soc_portreg,
  35367         1,
  35368         0,
  35369         0x94,
  35370         SOC_REG_FLAG_COUNTER |
  35371                           SOC_REG_FLAG_ED_CNTR,
  35372         0,
  35373         1,
  35374         soc_GR1023r_fields,
  35375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35376         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35377         200,
  35378         -1,
  35379     },
  35380 #endif /* chips */
  35381 
  35382 #if defined(BCM_88375_A0)
  35383     { /* SOC_REG_INT_GRCDE_BCM88375_A0r */
  35384         soc_block_list[2],
  35385         soc_portreg,
  35386         1,
  35387         0,
  35388         0x600,
  35389         SOC_REG_FLAG_COUNTER,
  35390         0,
  35391         1,
  35392         soc_GRCDE_BCM88375_A0r_fields,
  35393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35394         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35395         6,
  35396         -1,
  35397     },
  35398 #endif /* chips */
  35399 
  35400 #if defined(BCM_88375_B0)
  35401     { /* SOC_REG_INT_GRCDE_BCM88375_B0r */
  35402         soc_block_list[2],
  35403         soc_portreg,
  35404         1,
  35405         0,
  35406         0x600,
  35407         SOC_REG_FLAG_COUNTER,
  35408         0,
  35409         1,
  35410         soc_GRCDE_BCM88375_B0r_fields,
  35411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35413         6,
  35414         -1,
  35415     },
  35416 #endif /* chips */
  35417 
  35418 #if defined(BCM_88470_A0)
  35419     { /* SOC_REG_INT_GRCDE_BCM88470_A0r */
  35420         soc_block_list[2],
  35421         soc_portreg,
  35422         1,
  35423         0,
  35424         0x600,
  35425         SOC_REG_FLAG_COUNTER,
  35426         0,
  35427         1,
  35428         soc_GRCDE_BCM88470_A0r_fields,
  35429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35430         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35431         6,
  35432         -1,
  35433     },
  35434 #endif /* chips */
  35435 
  35436 #if defined(BCM_88470_B0)
  35437     { /* SOC_REG_INT_GRCDE_BCM88470_B0r */
  35438         soc_block_list[2],
  35439         soc_portreg,
  35440         1,
  35441         0,
  35442         0x600,
  35443         SOC_REG_FLAG_COUNTER,
  35444         0,
  35445         1,
  35446         soc_GRCDE_BCM88470_B0r_fields,
  35447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35448         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35449         6,
  35450         -1,
  35451     },
  35452 #endif /* chips */
  35453 
  35454 #if defined(BCM_88675_A0)
  35455     { /* SOC_REG_INT_GRCDE_BCM88675_A0r */
  35456         soc_block_list[2],
  35457         soc_portreg,
  35458         1,
  35459         0,
  35460         0x600,
  35461         SOC_REG_FLAG_COUNTER,
  35462         0,
  35463         1,
  35464         soc_GRCDEr_fields,
  35465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35466         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35467         6,
  35468         -1,
  35469     },
  35470 #endif /* chips */
  35471 
  35472 #if defined(BCM_88675_B0)
  35473     { /* SOC_REG_INT_GRCDE_BCM88675_B0r */
  35474         soc_block_list[2],
  35475         soc_portreg,
  35476         1,
  35477         0,
  35478         0x600,
  35479         SOC_REG_FLAG_COUNTER,
  35480         0,
  35481         1,
  35482         soc_GRCDE_BCM88675_B0r_fields,
  35483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35484         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35485         6,
  35486         -1,
  35487     },
  35488 #endif /* chips */
  35489 
  35490 #if defined(BCM_88680_A0)
  35491     { /* SOC_REG_INT_GRCDE_BCM88680_A0r */
  35492         soc_block_list[2],
  35493         soc_portreg,
  35494         1,
  35495         0,
  35496         0x600,
  35497         SOC_REG_FLAG_COUNTER,
  35498         0,
  35499         1,
  35500         soc_GRCDE_BCM88680_A0r_fields,
  35501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35502         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35503         6,
  35504         -1,
  35505     },
  35506 #endif /* chips */
  35507 
  35508 #if defined(BCM_53570_A0)
  35509     { /* SOC_REG_INT_GRDMFPr */
  35510         soc_block_list[2],
  35511         soc_portreg,
  35512         1,
  35513         0,
  35514         0x8600,
  35515         SOC_REG_FLAG_COUNTER,
  35516         0,
  35517         1,
  35518         soc_GR1023_BCM53400_A0r_fields,
  35519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35520         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35521         288,
  35522         -1,
  35523     },
  35524 #endif /* chips */
  35525 
  35526 #if defined(BCM_53570_B0)
  35527     { /* SOC_REG_INT_GRDMFP_BCM53570_B0r */
  35528         soc_block_list[2],
  35529         soc_portreg,
  35530         1,
  35531         0,
  35532         0x8600,
  35533         SOC_REG_FLAG_COUNTER,
  35534         0,
  35535         1,
  35536         soc_GR1023_BCM53400_A0r_fields,
  35537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35539         292,
  35540         -1,
  35541     },
  35542 #endif /* chips */
  35543 
  35544 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  35545     defined(BCM_56504_B0)
  35546     { /* SOC_REG_INT_GRFCRr */
  35547         soc_block_list[2],
  35548         soc_portreg,
  35549         1,
  35550         0,
  35551         0x15,
  35552         SOC_REG_FLAG_COUNTER |
  35553                           SOC_REG_FLAG_ED_CNTR,
  35554         0,
  35555         1,
  35556         soc_GR1023r_fields,
  35557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35559         55,
  35560         -1,
  35561     },
  35562 #endif /* chips */
  35563 
  35564 #if defined(BCM_53570_A0)
  35565     { /* SOC_REG_INT_GRFCRPr */
  35566         soc_block_list[2],
  35567         soc_portreg,
  35568         1,
  35569         0,
  35570         0x6600,
  35571         SOC_REG_FLAG_COUNTER,
  35572         0,
  35573         1,
  35574         soc_GR1023_BCM53400_A0r_fields,
  35575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35577         256,
  35578         -1,
  35579     },
  35580 #endif /* chips */
  35581 
  35582 #if defined(BCM_53570_B0)
  35583     { /* SOC_REG_INT_GRFCRP_BCM53570_B0r */
  35584         soc_block_list[2],
  35585         soc_portreg,
  35586         1,
  35587         0,
  35588         0x6600,
  35589         SOC_REG_FLAG_COUNTER,
  35590         0,
  35591         1,
  35592         soc_GR1023_BCM53400_A0r_fields,
  35593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35594         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35595         260,
  35596         -1,
  35597     },
  35598 #endif /* chips */
  35599 
  35600 #if defined(BCM_53400_A0)
  35601     { /* SOC_REG_INT_GRFCR_BCM53400_A0r */
  35602         soc_block_list[9],
  35603         soc_portreg,
  35604         1,
  35605         0,
  35606         0x700,
  35607         SOC_REG_FLAG_COUNTER,
  35608         0,
  35609         1,
  35610         soc_GR1023_BCM53400_A0r_fields,
  35611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35613         106,
  35614         -1,
  35615     },
  35616 #endif /* chips */
  35617 
  35618 #if defined(BCM_53540_A0)
  35619     { /* SOC_REG_INT_GRFCR_BCM53540_A0r */
  35620         soc_block_list[2],
  35621         soc_portreg,
  35622         1,
  35623         0,
  35624         0x700,
  35625         SOC_REG_FLAG_COUNTER,
  35626         0,
  35627         1,
  35628         soc_GR1023_BCM53400_A0r_fields,
  35629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35631         106,
  35632         -1,
  35633     },
  35634 #endif /* chips */
  35635 
  35636 #if defined(BCM_53570_A0)
  35637     { /* SOC_REG_INT_GRFCR_BCM53570_A0r */
  35638         soc_block_list[2],
  35639         soc_portreg,
  35640         1,
  35641         0,
  35642         0x700,
  35643         SOC_REG_FLAG_COUNTER,
  35644         0,
  35645         1,
  35646         soc_GR1023_BCM53400_A0r_fields,
  35647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35649         161,
  35650         -1,
  35651     },
  35652 #endif /* chips */
  35653 
  35654 #if defined(BCM_53570_B0)
  35655     { /* SOC_REG_INT_GRFCR_BCM53570_B0r */
  35656         soc_block_list[2],
  35657         soc_portreg,
  35658         1,
  35659         0,
  35660         0x700,
  35661         SOC_REG_FLAG_COUNTER,
  35662         0,
  35663         1,
  35664         soc_GR1023_BCM53400_A0r_fields,
  35665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35666         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35667         165,
  35668         -1,
  35669     },
  35670 #endif /* chips */
  35671 
  35672 #if defined(BCM_56142_A0)
  35673     { /* SOC_REG_INT_GRFCR_BCM56142_A0r */
  35674         soc_block_list[210],
  35675         soc_portreg,
  35676         1,
  35677         0,
  35678         0x87,
  35679         SOC_REG_FLAG_COUNTER,
  35680         0,
  35681         1,
  35682         soc_GR1023r_fields,
  35683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35684         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35685         182,
  35686         -1,
  35687     },
  35688 #endif /* chips */
  35689 
  35690 #if defined(BCM_56150_A0)
  35691     { /* SOC_REG_INT_GRFCR_BCM56150_A0r */
  35692         soc_block_list[2],
  35693         soc_portreg,
  35694         1,
  35695         0,
  35696         0x700,
  35697         SOC_REG_FLAG_COUNTER,
  35698         0,
  35699         1,
  35700         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  35701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35703         102,
  35704         -1,
  35705     },
  35706 #endif /* chips */
  35707 
  35708 #if defined(BCM_56160_A0)
  35709     { /* SOC_REG_INT_GRFCR_BCM56160_A0r */
  35710         soc_block_list[2],
  35711         soc_portreg,
  35712         1,
  35713         0,
  35714         0x700,
  35715         SOC_REG_FLAG_COUNTER,
  35716         0,
  35717         1,
  35718         soc_GR1023_BCM53400_A0r_fields,
  35719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35720         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35721         106,
  35722         -1,
  35723     },
  35724 #endif /* chips */
  35725 
  35726 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  35727     { /* SOC_REG_INT_GRFCR_BCM56334_A0r */
  35728         soc_block_list[210],
  35729         soc_portreg,
  35730         1,
  35731         0,
  35732         0x87,
  35733         SOC_REG_FLAG_COUNTER,
  35734         0,
  35735         1,
  35736         soc_GR1023r_fields,
  35737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35738         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35739         177,
  35740         -1,
  35741     },
  35742 #endif /* chips */
  35743 
  35744 #if defined(BCM_56370_A0)
  35745     { /* SOC_REG_INT_GRFCR_BCM56370_A0r */
  35746         soc_block_list[9],
  35747         soc_portreg,
  35748         1,
  35749         0,
  35750         0x700,
  35751         SOC_REG_FLAG_COUNTER,
  35752         0,
  35753         1,
  35754         soc_GR1023_BCM53400_A0r_fields,
  35755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35756         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35757         67,
  35758         -1,
  35759         3,
  35760     },
  35761 #endif /* chips */
  35762 
  35763 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  35764     { /* SOC_REG_INT_GRFCR_BCM56440_A0r */
  35765         soc_block_list[2],
  35766         soc_portreg,
  35767         1,
  35768         0,
  35769         0x87,
  35770         SOC_REG_FLAG_COUNTER,
  35771         0,
  35772         1,
  35773         soc_GR1023r_fields,
  35774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35775         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35776         174,
  35777         -1,
  35778     },
  35779 #endif /* chips */
  35780 
  35781 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  35782     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  35783     defined(BCM_56514_A0)
  35784     { /* SOC_REG_INT_GRFCR_BCM56514_A0r */
  35785         soc_block_list[2],
  35786         soc_portreg,
  35787         1,
  35788         0,
  35789         0x15,
  35790         SOC_REG_FLAG_COUNTER,
  35791         0,
  35792         1,
  35793         soc_GR1023r_fields,
  35794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35796         55,
  35797         -1,
  35798     },
  35799 #endif /* chips */
  35800 
  35801 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  35802     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  35803     { /* SOC_REG_INT_GRFCR_BCM56624_A0r */
  35804         soc_block_list[205],
  35805         soc_portreg,
  35806         1,
  35807         0,
  35808         0x95,
  35809         SOC_REG_FLAG_COUNTER,
  35810         0,
  35811         1,
  35812         soc_GR1023r_fields,
  35813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35814         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35815         191,
  35816         -1,
  35817     },
  35818 #endif /* chips */
  35819 
  35820 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  35821     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  35822     { /* SOC_REG_INT_GRFCR_BCM56634_A0r */
  35823         soc_block_list[207],
  35824         soc_portreg,
  35825         1,
  35826         0,
  35827         0x95,
  35828         SOC_REG_FLAG_COUNTER,
  35829         0,
  35830         1,
  35831         soc_GR1023r_fields,
  35832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35833         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35834         191,
  35835         -1,
  35836     },
  35837 #endif /* chips */
  35838 
  35839 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  35840     { /* SOC_REG_INT_GRFCR_BCM56685_A0r */
  35841         soc_block_list[209],
  35842         soc_portreg,
  35843         1,
  35844         0,
  35845         0x95,
  35846         SOC_REG_FLAG_COUNTER,
  35847         0,
  35848         1,
  35849         soc_GR1023r_fields,
  35850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35851         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35852         191,
  35853         -1,
  35854     },
  35855 #endif /* chips */
  35856 
  35857 #if defined(BCM_56800_A0)
  35858     { /* SOC_REG_INT_GRFCR_BCM56800_A0r */
  35859         soc_block_list[9],
  35860         soc_portreg,
  35861         1,
  35862         0,
  35863         0x5c,
  35864         SOC_REG_FLAG_COUNTER,
  35865         0,
  35866         1,
  35867         soc_GR1023r_fields,
  35868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35870         134,
  35871         -1,
  35872     },
  35873 #endif /* chips */
  35874 
  35875 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  35876     { /* SOC_REG_INT_GRFCR_BCM56820_A0r */
  35877         soc_block_list[206],
  35878         soc_portreg,
  35879         1,
  35880         0,
  35881         0x95,
  35882         SOC_REG_FLAG_COUNTER,
  35883         0,
  35884         1,
  35885         soc_GR1023r_fields,
  35886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35887         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35888         201,
  35889         -1,
  35890     },
  35891 #endif /* chips */
  35892 
  35893 #if defined(BCM_88375_A0)
  35894     { /* SOC_REG_INT_GRFCR_BCM88375_A0r */
  35895         soc_block_list[2],
  35896         soc_portreg,
  35897         1,
  35898         0,
  35899         0x700,
  35900         SOC_REG_FLAG_COUNTER,
  35901         0,
  35902         1,
  35903         soc_GRFCR_BCM88375_A0r_fields,
  35904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35905         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35906         7,
  35907         -1,
  35908     },
  35909 #endif /* chips */
  35910 
  35911 #if defined(BCM_88375_B0)
  35912     { /* SOC_REG_INT_GRFCR_BCM88375_B0r */
  35913         soc_block_list[2],
  35914         soc_portreg,
  35915         1,
  35916         0,
  35917         0x700,
  35918         SOC_REG_FLAG_COUNTER,
  35919         0,
  35920         1,
  35921         soc_GRFCR_BCM88375_B0r_fields,
  35922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35924         7,
  35925         -1,
  35926     },
  35927 #endif /* chips */
  35928 
  35929 #if defined(BCM_88470_A0)
  35930     { /* SOC_REG_INT_GRFCR_BCM88470_A0r */
  35931         soc_block_list[2],
  35932         soc_portreg,
  35933         1,
  35934         0,
  35935         0x700,
  35936         SOC_REG_FLAG_COUNTER,
  35937         0,
  35938         1,
  35939         soc_GRFCR_BCM88470_A0r_fields,
  35940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35941         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35942         7,
  35943         -1,
  35944     },
  35945 #endif /* chips */
  35946 
  35947 #if defined(BCM_88470_B0)
  35948     { /* SOC_REG_INT_GRFCR_BCM88470_B0r */
  35949         soc_block_list[2],
  35950         soc_portreg,
  35951         1,
  35952         0,
  35953         0x700,
  35954         SOC_REG_FLAG_COUNTER,
  35955         0,
  35956         1,
  35957         soc_GRFCR_BCM88470_B0r_fields,
  35958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35959         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35960         7,
  35961         -1,
  35962     },
  35963 #endif /* chips */
  35964 
  35965 #if defined(BCM_88675_A0)
  35966     { /* SOC_REG_INT_GRFCR_BCM88675_A0r */
  35967         soc_block_list[2],
  35968         soc_portreg,
  35969         1,
  35970         0,
  35971         0x700,
  35972         SOC_REG_FLAG_COUNTER,
  35973         0,
  35974         1,
  35975         soc_GRFCRr_fields,
  35976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35978         7,
  35979         -1,
  35980     },
  35981 #endif /* chips */
  35982 
  35983 #if defined(BCM_88675_B0)
  35984     { /* SOC_REG_INT_GRFCR_BCM88675_B0r */
  35985         soc_block_list[2],
  35986         soc_portreg,
  35987         1,
  35988         0,
  35989         0x700,
  35990         SOC_REG_FLAG_COUNTER,
  35991         0,
  35992         1,
  35993         soc_GRFCR_BCM88675_B0r_fields,
  35994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35995         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35996         7,
  35997         -1,
  35998     },
  35999 #endif /* chips */
  36000 
  36001 #if defined(BCM_88680_A0)
  36002     { /* SOC_REG_INT_GRFCR_BCM88680_A0r */
  36003         soc_block_list[2],
  36004         soc_portreg,
  36005         1,
  36006         0,
  36007         0x700,
  36008         SOC_REG_FLAG_COUNTER,
  36009         0,
  36010         1,
  36011         soc_GRFCR_BCM88680_A0r_fields,
  36012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36013         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36014         7,
  36015         -1,
  36016     },
  36017 #endif /* chips */
  36018 
  36019 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  36020     defined(BCM_56504_B0)
  36021     { /* SOC_REG_INT_GRFCSr */
  36022         soc_block_list[2],
  36023         soc_portreg,
  36024         1,
  36025         0,
  36026         0xe,
  36027         SOC_REG_FLAG_COUNTER |
  36028                           SOC_REG_FLAG_ED_CNTR,
  36029         0,
  36030         1,
  36031         soc_GR1023r_fields,
  36032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36034         48,
  36035         -1,
  36036     },
  36037 #endif /* chips */
  36038 
  36039 #if defined(BCM_53570_A0)
  36040     { /* SOC_REG_INT_GRFCSPr */
  36041         soc_block_list[2],
  36042         soc_portreg,
  36043         1,
  36044         0,
  36045         0x6200,
  36046         SOC_REG_FLAG_COUNTER,
  36047         0,
  36048         1,
  36049         soc_GR1023_BCM53400_A0r_fields,
  36050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36052         252,
  36053         -1,
  36054     },
  36055 #endif /* chips */
  36056 
  36057 #if defined(BCM_53570_B0)
  36058     { /* SOC_REG_INT_GRFCSP_BCM53570_B0r */
  36059         soc_block_list[2],
  36060         soc_portreg,
  36061         1,
  36062         0,
  36063         0x6200,
  36064         SOC_REG_FLAG_COUNTER,
  36065         0,
  36066         1,
  36067         soc_GR1023_BCM53400_A0r_fields,
  36068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36070         256,
  36071         -1,
  36072     },
  36073 #endif /* chips */
  36074 
  36075 #if defined(BCM_53400_A0)
  36076     { /* SOC_REG_INT_GRFCS_BCM53400_A0r */
  36077         soc_block_list[9],
  36078         soc_portreg,
  36079         1,
  36080         0,
  36081         0,
  36082         SOC_REG_FLAG_COUNTER,
  36083         0,
  36084         1,
  36085         soc_GR1023_BCM53400_A0r_fields,
  36086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36088         99,
  36089         -1,
  36090     },
  36091 #endif /* chips */
  36092 
  36093 #if defined(BCM_53540_A0)
  36094     { /* SOC_REG_INT_GRFCS_BCM53540_A0r */
  36095         soc_block_list[2],
  36096         soc_portreg,
  36097         1,
  36098         0,
  36099         0,
  36100         SOC_REG_FLAG_COUNTER,
  36101         0,
  36102         1,
  36103         soc_GR1023_BCM53400_A0r_fields,
  36104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36105         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36106         99,
  36107         -1,
  36108     },
  36109 #endif /* chips */
  36110 
  36111 #if defined(BCM_53570_A0)
  36112     { /* SOC_REG_INT_GRFCS_BCM53570_A0r */
  36113         soc_block_list[2],
  36114         soc_portreg,
  36115         1,
  36116         0,
  36117         0,
  36118         SOC_REG_FLAG_COUNTER,
  36119         0,
  36120         1,
  36121         soc_GR1023_BCM53400_A0r_fields,
  36122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36124         154,
  36125         -1,
  36126     },
  36127 #endif /* chips */
  36128 
  36129 #if defined(BCM_53570_B0)
  36130     { /* SOC_REG_INT_GRFCS_BCM53570_B0r */
  36131         soc_block_list[2],
  36132         soc_portreg,
  36133         1,
  36134         0,
  36135         0,
  36136         SOC_REG_FLAG_COUNTER,
  36137         0,
  36138         1,
  36139         soc_GR1023_BCM53400_A0r_fields,
  36140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36142         158,
  36143         -1,
  36144     },
  36145 #endif /* chips */
  36146 
  36147 #if defined(BCM_56142_A0)
  36148     { /* SOC_REG_INT_GRFCS_BCM56142_A0r */
  36149         soc_block_list[210],
  36150         soc_portreg,
  36151         1,
  36152         0,
  36153         0x80,
  36154         SOC_REG_FLAG_COUNTER,
  36155         0,
  36156         1,
  36157         soc_GR1023r_fields,
  36158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36160         175,
  36161         -1,
  36162     },
  36163 #endif /* chips */
  36164 
  36165 #if defined(BCM_56150_A0)
  36166     { /* SOC_REG_INT_GRFCS_BCM56150_A0r */
  36167         soc_block_list[2],
  36168         soc_portreg,
  36169         1,
  36170         0,
  36171         0,
  36172         SOC_REG_FLAG_COUNTER,
  36173         0,
  36174         1,
  36175         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  36176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36178         95,
  36179         -1,
  36180     },
  36181 #endif /* chips */
  36182 
  36183 #if defined(BCM_56160_A0)
  36184     { /* SOC_REG_INT_GRFCS_BCM56160_A0r */
  36185         soc_block_list[2],
  36186         soc_portreg,
  36187         1,
  36188         0,
  36189         0,
  36190         SOC_REG_FLAG_COUNTER,
  36191         0,
  36192         1,
  36193         soc_GR1023_BCM53400_A0r_fields,
  36194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36195         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36196         99,
  36197         -1,
  36198     },
  36199 #endif /* chips */
  36200 
  36201 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  36202     { /* SOC_REG_INT_GRFCS_BCM56334_A0r */
  36203         soc_block_list[210],
  36204         soc_portreg,
  36205         1,
  36206         0,
  36207         0x80,
  36208         SOC_REG_FLAG_COUNTER,
  36209         0,
  36210         1,
  36211         soc_GR1023r_fields,
  36212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36213         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36214         170,
  36215         -1,
  36216     },
  36217 #endif /* chips */
  36218 
  36219 #if defined(BCM_56370_A0)
  36220     { /* SOC_REG_INT_GRFCS_BCM56370_A0r */
  36221         soc_block_list[9],
  36222         soc_portreg,
  36223         1,
  36224         0,
  36225         0,
  36226         SOC_REG_FLAG_COUNTER,
  36227         0,
  36228         1,
  36229         soc_GR1023_BCM53400_A0r_fields,
  36230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36232         60,
  36233         -1,
  36234         3,
  36235     },
  36236 #endif /* chips */
  36237 
  36238 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  36239     { /* SOC_REG_INT_GRFCS_BCM56440_A0r */
  36240         soc_block_list[2],
  36241         soc_portreg,
  36242         1,
  36243         0,
  36244         0x80,
  36245         SOC_REG_FLAG_COUNTER,
  36246         0,
  36247         1,
  36248         soc_GR1023r_fields,
  36249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36250         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36251         167,
  36252         -1,
  36253     },
  36254 #endif /* chips */
  36255 
  36256 #if defined(BCM_56514_A0)
  36257     { /* SOC_REG_INT_GRFCS_BCM56514_A0r */
  36258         soc_block_list[2],
  36259         soc_portreg,
  36260         1,
  36261         0,
  36262         0xe,
  36263         SOC_REG_FLAG_COUNTER,
  36264         0,
  36265         1,
  36266         soc_GR1023r_fields,
  36267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36268         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36269         48,
  36270         -1,
  36271     },
  36272 #endif /* chips */
  36273 
  36274 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  36275     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  36276     { /* SOC_REG_INT_GRFCS_BCM56624_A0r */
  36277         soc_block_list[205],
  36278         soc_portreg,
  36279         1,
  36280         0,
  36281         0x8e,
  36282         SOC_REG_FLAG_COUNTER,
  36283         0,
  36284         1,
  36285         soc_GR1023r_fields,
  36286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36288         184,
  36289         -1,
  36290     },
  36291 #endif /* chips */
  36292 
  36293 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  36294     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  36295     { /* SOC_REG_INT_GRFCS_BCM56634_A0r */
  36296         soc_block_list[207],
  36297         soc_portreg,
  36298         1,
  36299         0,
  36300         0x8e,
  36301         SOC_REG_FLAG_COUNTER,
  36302         0,
  36303         1,
  36304         soc_GR1023r_fields,
  36305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36307         184,
  36308         -1,
  36309     },
  36310 #endif /* chips */
  36311 
  36312 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  36313     { /* SOC_REG_INT_GRFCS_BCM56685_A0r */
  36314         soc_block_list[209],
  36315         soc_portreg,
  36316         1,
  36317         0,
  36318         0x8e,
  36319         SOC_REG_FLAG_COUNTER,
  36320         0,
  36321         1,
  36322         soc_GR1023r_fields,
  36323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36324         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36325         184,
  36326         -1,
  36327     },
  36328 #endif /* chips */
  36329 
  36330 #if defined(BCM_56800_A0)
  36331     { /* SOC_REG_INT_GRFCS_BCM56800_A0r */
  36332         soc_block_list[9],
  36333         soc_portreg,
  36334         1,
  36335         0,
  36336         0x55,
  36337         SOC_REG_FLAG_COUNTER,
  36338         0,
  36339         1,
  36340         soc_GR1023r_fields,
  36341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36342         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36343         127,
  36344         -1,
  36345     },
  36346 #endif /* chips */
  36347 
  36348 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  36349     { /* SOC_REG_INT_GRFCS_BCM56820_A0r */
  36350         soc_block_list[206],
  36351         soc_portreg,
  36352         1,
  36353         0,
  36354         0x8e,
  36355         SOC_REG_FLAG_COUNTER,
  36356         0,
  36357         1,
  36358         soc_GR1023r_fields,
  36359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36360         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36361         194,
  36362         -1,
  36363     },
  36364 #endif /* chips */
  36365 
  36366 #if defined(BCM_88375_A0)
  36367     { /* SOC_REG_INT_GRFCS_BCM88375_A0r */
  36368         soc_block_list[2],
  36369         soc_portreg,
  36370         1,
  36371         0,
  36372         0,
  36373         SOC_REG_FLAG_COUNTER,
  36374         0,
  36375         1,
  36376         soc_GRFCS_BCM88375_A0r_fields,
  36377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36378         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36379         0,
  36380         -1,
  36381     },
  36382 #endif /* chips */
  36383 
  36384 #if defined(BCM_88375_B0)
  36385     { /* SOC_REG_INT_GRFCS_BCM88375_B0r */
  36386         soc_block_list[2],
  36387         soc_portreg,
  36388         1,
  36389         0,
  36390         0,
  36391         SOC_REG_FLAG_COUNTER,
  36392         0,
  36393         1,
  36394         soc_GRFCS_BCM88375_B0r_fields,
  36395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36396         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36397         0,
  36398         -1,
  36399     },
  36400 #endif /* chips */
  36401 
  36402 #if defined(BCM_88470_A0)
  36403     { /* SOC_REG_INT_GRFCS_BCM88470_A0r */
  36404         soc_block_list[2],
  36405         soc_portreg,
  36406         1,
  36407         0,
  36408         0,
  36409         SOC_REG_FLAG_COUNTER,
  36410         0,
  36411         1,
  36412         soc_GRFCS_BCM88470_A0r_fields,
  36413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36414         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36415         0,
  36416         -1,
  36417     },
  36418 #endif /* chips */
  36419 
  36420 #if defined(BCM_88470_B0)
  36421     { /* SOC_REG_INT_GRFCS_BCM88470_B0r */
  36422         soc_block_list[2],
  36423         soc_portreg,
  36424         1,
  36425         0,
  36426         0,
  36427         SOC_REG_FLAG_COUNTER,
  36428         0,
  36429         1,
  36430         soc_GRFCS_BCM88470_B0r_fields,
  36431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36433         0,
  36434         -1,
  36435     },
  36436 #endif /* chips */
  36437 
  36438 #if defined(BCM_88675_A0)
  36439     { /* SOC_REG_INT_GRFCS_BCM88675_A0r */
  36440         soc_block_list[2],
  36441         soc_portreg,
  36442         1,
  36443         0,
  36444         0,
  36445         SOC_REG_FLAG_COUNTER,
  36446         0,
  36447         1,
  36448         soc_GRFCSr_fields,
  36449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36451         0,
  36452         -1,
  36453     },
  36454 #endif /* chips */
  36455 
  36456 #if defined(BCM_88675_B0)
  36457     { /* SOC_REG_INT_GRFCS_BCM88675_B0r */
  36458         soc_block_list[2],
  36459         soc_portreg,
  36460         1,
  36461         0,
  36462         0,
  36463         SOC_REG_FLAG_COUNTER,
  36464         0,
  36465         1,
  36466         soc_GRFCS_BCM88675_B0r_fields,
  36467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36469         0,
  36470         -1,
  36471     },
  36472 #endif /* chips */
  36473 
  36474 #if defined(BCM_88680_A0)
  36475     { /* SOC_REG_INT_GRFCS_BCM88680_A0r */
  36476         soc_block_list[2],
  36477         soc_portreg,
  36478         1,
  36479         0,
  36480         0,
  36481         SOC_REG_FLAG_COUNTER,
  36482         0,
  36483         1,
  36484         soc_GRFCS_BCM88680_A0r_fields,
  36485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36487         0,
  36488         -1,
  36489     },
  36490 #endif /* chips */
  36491 
  36492 #if defined(BCM_53570_A0)
  36493     { /* SOC_REG_INT_GRFFSEPr */
  36494         soc_block_list[2],
  36495         soc_portreg,
  36496         1,
  36497         0,
  36498         0x8200,
  36499         SOC_REG_FLAG_COUNTER,
  36500         0,
  36501         1,
  36502         soc_GR1023_BCM53400_A0r_fields,
  36503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36505         284,
  36506         -1,
  36507     },
  36508 #endif /* chips */
  36509 
  36510 #if defined(BCM_53570_B0)
  36511     { /* SOC_REG_INT_GRFFSEP_BCM53570_B0r */
  36512         soc_block_list[2],
  36513         soc_portreg,
  36514         1,
  36515         0,
  36516         0x8200,
  36517         SOC_REG_FLAG_COUNTER,
  36518         0,
  36519         1,
  36520         soc_GR1023_BCM53400_A0r_fields,
  36521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36522         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36523         288,
  36524         -1,
  36525     },
  36526 #endif /* chips */
  36527 
  36528 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  36529     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  36530     { /* SOC_REG_INT_GRFLRr */
  36531         soc_block_list[2],
  36532         soc_portreg,
  36533         1,
  36534         0,
  36535         0x13,
  36536         SOC_REG_FLAG_COUNTER |
  36537                           SOC_REG_FLAG_ED_CNTR,
  36538         0,
  36539         1,
  36540         soc_GR1023r_fields,
  36541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36542         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36543         53,
  36544         -1,
  36545     },
  36546 #endif /* chips */
  36547 
  36548 #if defined(BCM_53570_A0)
  36549     { /* SOC_REG_INT_GRFLRPr */
  36550         soc_block_list[2],
  36551         soc_portreg,
  36552         1,
  36553         0,
  36554         0x6400,
  36555         SOC_REG_FLAG_COUNTER |
  36556                           SOC_REG_FLAG_ED_CNTR,
  36557         0,
  36558         1,
  36559         soc_GR1023_BCM53400_A0r_fields,
  36560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36562         254,
  36563         -1,
  36564     },
  36565 #endif /* chips */
  36566 
  36567 #if defined(BCM_53570_B0)
  36568     { /* SOC_REG_INT_GRFLRP_BCM53570_B0r */
  36569         soc_block_list[2],
  36570         soc_portreg,
  36571         1,
  36572         0,
  36573         0x6400,
  36574         SOC_REG_FLAG_COUNTER |
  36575                           SOC_REG_FLAG_ED_CNTR,
  36576         0,
  36577         1,
  36578         soc_GR1023_BCM53400_A0r_fields,
  36579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36580         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36581         258,
  36582         -1,
  36583     },
  36584 #endif /* chips */
  36585 
  36586 #if defined(BCM_53400_A0)
  36587     { /* SOC_REG_INT_GRFLR_BCM53400_A0r */
  36588         soc_block_list[9],
  36589         soc_portreg,
  36590         1,
  36591         0,
  36592         0x500,
  36593         SOC_REG_FLAG_COUNTER |
  36594                           SOC_REG_FLAG_ED_CNTR,
  36595         0,
  36596         1,
  36597         soc_GR1023_BCM53400_A0r_fields,
  36598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36600         104,
  36601         -1,
  36602     },
  36603 #endif /* chips */
  36604 
  36605 #if defined(BCM_53540_A0)
  36606     { /* SOC_REG_INT_GRFLR_BCM53540_A0r */
  36607         soc_block_list[2],
  36608         soc_portreg,
  36609         1,
  36610         0,
  36611         0x500,
  36612         SOC_REG_FLAG_COUNTER |
  36613                           SOC_REG_FLAG_ED_CNTR,
  36614         0,
  36615         1,
  36616         soc_GR1023_BCM53400_A0r_fields,
  36617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36618         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36619         104,
  36620         -1,
  36621     },
  36622 #endif /* chips */
  36623 
  36624 #if defined(BCM_53570_A0)
  36625     { /* SOC_REG_INT_GRFLR_BCM53570_A0r */
  36626         soc_block_list[2],
  36627         soc_portreg,
  36628         1,
  36629         0,
  36630         0x500,
  36631         SOC_REG_FLAG_COUNTER |
  36632                           SOC_REG_FLAG_ED_CNTR,
  36633         0,
  36634         1,
  36635         soc_GR1023_BCM53400_A0r_fields,
  36636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36637         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36638         159,
  36639         -1,
  36640     },
  36641 #endif /* chips */
  36642 
  36643 #if defined(BCM_53570_B0)
  36644     { /* SOC_REG_INT_GRFLR_BCM53570_B0r */
  36645         soc_block_list[2],
  36646         soc_portreg,
  36647         1,
  36648         0,
  36649         0x500,
  36650         SOC_REG_FLAG_COUNTER |
  36651                           SOC_REG_FLAG_ED_CNTR,
  36652         0,
  36653         1,
  36654         soc_GR1023_BCM53400_A0r_fields,
  36655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36656         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36657         163,
  36658         -1,
  36659     },
  36660 #endif /* chips */
  36661 
  36662 #if defined(BCM_56142_A0)
  36663     { /* SOC_REG_INT_GRFLR_BCM56142_A0r */
  36664         soc_block_list[210],
  36665         soc_portreg,
  36666         1,
  36667         0,
  36668         0x85,
  36669         SOC_REG_FLAG_COUNTER |
  36670                           SOC_REG_FLAG_ED_CNTR,
  36671         0,
  36672         1,
  36673         soc_GR1023r_fields,
  36674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36676         180,
  36677         -1,
  36678     },
  36679 #endif /* chips */
  36680 
  36681 #if defined(BCM_56150_A0)
  36682     { /* SOC_REG_INT_GRFLR_BCM56150_A0r */
  36683         soc_block_list[2],
  36684         soc_portreg,
  36685         1,
  36686         0,
  36687         0x500,
  36688         SOC_REG_FLAG_COUNTER |
  36689                           SOC_REG_FLAG_ED_CNTR,
  36690         0,
  36691         1,
  36692         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  36693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36694         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36695         100,
  36696         -1,
  36697     },
  36698 #endif /* chips */
  36699 
  36700 #if defined(BCM_56160_A0)
  36701     { /* SOC_REG_INT_GRFLR_BCM56160_A0r */
  36702         soc_block_list[2],
  36703         soc_portreg,
  36704         1,
  36705         0,
  36706         0x500,
  36707         SOC_REG_FLAG_COUNTER |
  36708                           SOC_REG_FLAG_ED_CNTR,
  36709         0,
  36710         1,
  36711         soc_GR1023_BCM53400_A0r_fields,
  36712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36713         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36714         104,
  36715         -1,
  36716     },
  36717 #endif /* chips */
  36718 
  36719 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  36720     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  36721     { /* SOC_REG_INT_GRFLR_BCM56224_A0r */
  36722         soc_block_list[2],
  36723         soc_portreg,
  36724         1,
  36725         0,
  36726         0x5,
  36727         SOC_REG_FLAG_COUNTER |
  36728                           SOC_REG_FLAG_ED_CNTR,
  36729         0,
  36730         1,
  36731         soc_GR1023r_fields,
  36732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36734         39,
  36735         -1,
  36736     },
  36737 #endif /* chips */
  36738 
  36739 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  36740     { /* SOC_REG_INT_GRFLR_BCM56334_A0r */
  36741         soc_block_list[210],
  36742         soc_portreg,
  36743         1,
  36744         0,
  36745         0x85,
  36746         SOC_REG_FLAG_COUNTER |
  36747                           SOC_REG_FLAG_ED_CNTR,
  36748         0,
  36749         1,
  36750         soc_GR1023r_fields,
  36751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36752         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36753         175,
  36754         -1,
  36755     },
  36756 #endif /* chips */
  36757 
  36758 #if defined(BCM_56370_A0)
  36759     { /* SOC_REG_INT_GRFLR_BCM56370_A0r */
  36760         soc_block_list[9],
  36761         soc_portreg,
  36762         1,
  36763         0,
  36764         0x500,
  36765         SOC_REG_FLAG_COUNTER |
  36766                           SOC_REG_FLAG_ED_CNTR,
  36767         0,
  36768         1,
  36769         soc_GR1023_BCM53400_A0r_fields,
  36770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36772         65,
  36773         -1,
  36774         3,
  36775     },
  36776 #endif /* chips */
  36777 
  36778 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  36779     { /* SOC_REG_INT_GRFLR_BCM56440_A0r */
  36780         soc_block_list[2],
  36781         soc_portreg,
  36782         1,
  36783         0,
  36784         0x85,
  36785         SOC_REG_FLAG_COUNTER |
  36786                           SOC_REG_FLAG_ED_CNTR,
  36787         0,
  36788         1,
  36789         soc_GR1023r_fields,
  36790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36792         172,
  36793         -1,
  36794     },
  36795 #endif /* chips */
  36796 
  36797 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  36798     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  36799     { /* SOC_REG_INT_GRFLR_BCM56624_A0r */
  36800         soc_block_list[205],
  36801         soc_portreg,
  36802         1,
  36803         0,
  36804         0x93,
  36805         SOC_REG_FLAG_COUNTER |
  36806                           SOC_REG_FLAG_ED_CNTR,
  36807         0,
  36808         1,
  36809         soc_GR1023r_fields,
  36810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36811         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36812         189,
  36813         -1,
  36814     },
  36815 #endif /* chips */
  36816 
  36817 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  36818     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  36819     { /* SOC_REG_INT_GRFLR_BCM56634_A0r */
  36820         soc_block_list[207],
  36821         soc_portreg,
  36822         1,
  36823         0,
  36824         0x93,
  36825         SOC_REG_FLAG_COUNTER |
  36826                           SOC_REG_FLAG_ED_CNTR,
  36827         0,
  36828         1,
  36829         soc_GR1023r_fields,
  36830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36832         189,
  36833         -1,
  36834     },
  36835 #endif /* chips */
  36836 
  36837 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  36838     { /* SOC_REG_INT_GRFLR_BCM56685_A0r */
  36839         soc_block_list[209],
  36840         soc_portreg,
  36841         1,
  36842         0,
  36843         0x93,
  36844         SOC_REG_FLAG_COUNTER |
  36845                           SOC_REG_FLAG_ED_CNTR,
  36846         0,
  36847         1,
  36848         soc_GR1023r_fields,
  36849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36851         189,
  36852         -1,
  36853     },
  36854 #endif /* chips */
  36855 
  36856 #if defined(BCM_56800_A0)
  36857     { /* SOC_REG_INT_GRFLR_BCM56800_A0r */
  36858         soc_block_list[9],
  36859         soc_portreg,
  36860         1,
  36861         0,
  36862         0x5a,
  36863         SOC_REG_FLAG_COUNTER |
  36864                           SOC_REG_FLAG_ED_CNTR,
  36865         0,
  36866         1,
  36867         soc_GR1023r_fields,
  36868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36870         132,
  36871         -1,
  36872     },
  36873 #endif /* chips */
  36874 
  36875 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  36876     { /* SOC_REG_INT_GRFLR_BCM56820_A0r */
  36877         soc_block_list[206],
  36878         soc_portreg,
  36879         1,
  36880         0,
  36881         0x93,
  36882         SOC_REG_FLAG_COUNTER |
  36883                           SOC_REG_FLAG_ED_CNTR,
  36884         0,
  36885         1,
  36886         soc_GR1023r_fields,
  36887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36888         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36889         199,
  36890         -1,
  36891     },
  36892 #endif /* chips */
  36893 
  36894 #if defined(BCM_88375_A0)
  36895     { /* SOC_REG_INT_GRFLR_BCM88375_A0r */
  36896         soc_block_list[2],
  36897         soc_portreg,
  36898         1,
  36899         0,
  36900         0x500,
  36901         SOC_REG_FLAG_COUNTER,
  36902         0,
  36903         1,
  36904         soc_GRFLR_BCM88375_A0r_fields,
  36905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36907         5,
  36908         -1,
  36909     },
  36910 #endif /* chips */
  36911 
  36912 #if defined(BCM_88375_B0)
  36913     { /* SOC_REG_INT_GRFLR_BCM88375_B0r */
  36914         soc_block_list[2],
  36915         soc_portreg,
  36916         1,
  36917         0,
  36918         0x500,
  36919         SOC_REG_FLAG_COUNTER,
  36920         0,
  36921         1,
  36922         soc_GRFLR_BCM88375_B0r_fields,
  36923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36925         5,
  36926         -1,
  36927     },
  36928 #endif /* chips */
  36929 
  36930 #if defined(BCM_88470_A0)
  36931     { /* SOC_REG_INT_GRFLR_BCM88470_A0r */
  36932         soc_block_list[2],
  36933         soc_portreg,
  36934         1,
  36935         0,
  36936         0x500,
  36937         SOC_REG_FLAG_COUNTER,
  36938         0,
  36939         1,
  36940         soc_GRFLR_BCM88470_A0r_fields,
  36941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36943         5,
  36944         -1,
  36945     },
  36946 #endif /* chips */
  36947 
  36948 #if defined(BCM_88470_B0)
  36949     { /* SOC_REG_INT_GRFLR_BCM88470_B0r */
  36950         soc_block_list[2],
  36951         soc_portreg,
  36952         1,
  36953         0,
  36954         0x500,
  36955         SOC_REG_FLAG_COUNTER,
  36956         0,
  36957         1,
  36958         soc_GRFLR_BCM88470_B0r_fields,
  36959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36960         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36961         5,
  36962         -1,
  36963     },
  36964 #endif /* chips */
  36965 
  36966 #if defined(BCM_88675_A0)
  36967     { /* SOC_REG_INT_GRFLR_BCM88675_A0r */
  36968         soc_block_list[2],
  36969         soc_portreg,
  36970         1,
  36971         0,
  36972         0x500,
  36973         SOC_REG_FLAG_COUNTER,
  36974         0,
  36975         1,
  36976         soc_GRFLRr_fields,
  36977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36978         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36979         5,
  36980         -1,
  36981     },
  36982 #endif /* chips */
  36983 
  36984 #if defined(BCM_88675_B0)
  36985     { /* SOC_REG_INT_GRFLR_BCM88675_B0r */
  36986         soc_block_list[2],
  36987         soc_portreg,
  36988         1,
  36989         0,
  36990         0x500,
  36991         SOC_REG_FLAG_COUNTER,
  36992         0,
  36993         1,
  36994         soc_GRFLR_BCM88675_B0r_fields,
  36995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36997         5,
  36998         -1,
  36999     },
  37000 #endif /* chips */
  37001 
  37002 #if defined(BCM_88680_A0)
  37003     { /* SOC_REG_INT_GRFLR_BCM88680_A0r */
  37004         soc_block_list[2],
  37005         soc_portreg,
  37006         1,
  37007         0,
  37008         0x500,
  37009         SOC_REG_FLAG_COUNTER,
  37010         0,
  37011         1,
  37012         soc_GRFLR_BCM88680_A0r_fields,
  37013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37014         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37015         5,
  37016         -1,
  37017     },
  37018 #endif /* chips */
  37019 
  37020 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  37021     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  37022     { /* SOC_REG_INT_GRFRGr */
  37023         soc_block_list[2],
  37024         soc_portreg,
  37025         1,
  37026         0,
  37027         0x1b,
  37028         SOC_REG_FLAG_COUNTER |
  37029                           SOC_REG_FLAG_ED_CNTR,
  37030         0,
  37031         1,
  37032         soc_GR1023r_fields,
  37033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37034         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37035         61,
  37036         -1,
  37037     },
  37038 #endif /* chips */
  37039 
  37040 #if defined(BCM_53570_A0)
  37041     { /* SOC_REG_INT_GRFRGPr */
  37042         soc_block_list[2],
  37043         soc_portreg,
  37044         1,
  37045         0,
  37046         0x6c00,
  37047         SOC_REG_FLAG_COUNTER |
  37048                           SOC_REG_FLAG_ED_CNTR,
  37049         0,
  37050         1,
  37051         soc_GR1023_BCM53400_A0r_fields,
  37052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37053         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37054         262,
  37055         -1,
  37056     },
  37057 #endif /* chips */
  37058 
  37059 #if defined(BCM_53570_B0)
  37060     { /* SOC_REG_INT_GRFRGP_BCM53570_B0r */
  37061         soc_block_list[2],
  37062         soc_portreg,
  37063         1,
  37064         0,
  37065         0x6c00,
  37066         SOC_REG_FLAG_COUNTER |
  37067                           SOC_REG_FLAG_ED_CNTR,
  37068         0,
  37069         1,
  37070         soc_GR1023_BCM53400_A0r_fields,
  37071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37072         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37073         266,
  37074         -1,
  37075     },
  37076 #endif /* chips */
  37077 
  37078 #if defined(BCM_53400_A0)
  37079     { /* SOC_REG_INT_GRFRG_BCM53400_A0r */
  37080         soc_block_list[9],
  37081         soc_portreg,
  37082         1,
  37083         0,
  37084         0xd00,
  37085         SOC_REG_FLAG_COUNTER |
  37086                           SOC_REG_FLAG_ED_CNTR,
  37087         0,
  37088         1,
  37089         soc_GR1023_BCM53400_A0r_fields,
  37090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37092         112,
  37093         -1,
  37094     },
  37095 #endif /* chips */
  37096 
  37097 #if defined(BCM_53540_A0)
  37098     { /* SOC_REG_INT_GRFRG_BCM53540_A0r */
  37099         soc_block_list[2],
  37100         soc_portreg,
  37101         1,
  37102         0,
  37103         0xd00,
  37104         SOC_REG_FLAG_COUNTER |
  37105                           SOC_REG_FLAG_ED_CNTR,
  37106         0,
  37107         1,
  37108         soc_GR1023_BCM53400_A0r_fields,
  37109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37110         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37111         112,
  37112         -1,
  37113     },
  37114 #endif /* chips */
  37115 
  37116 #if defined(BCM_53570_A0)
  37117     { /* SOC_REG_INT_GRFRG_BCM53570_A0r */
  37118         soc_block_list[2],
  37119         soc_portreg,
  37120         1,
  37121         0,
  37122         0xd00,
  37123         SOC_REG_FLAG_COUNTER |
  37124                           SOC_REG_FLAG_ED_CNTR,
  37125         0,
  37126         1,
  37127         soc_GR1023_BCM53400_A0r_fields,
  37128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37129         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37130         167,
  37131         -1,
  37132     },
  37133 #endif /* chips */
  37134 
  37135 #if defined(BCM_53570_B0)
  37136     { /* SOC_REG_INT_GRFRG_BCM53570_B0r */
  37137         soc_block_list[2],
  37138         soc_portreg,
  37139         1,
  37140         0,
  37141         0xd00,
  37142         SOC_REG_FLAG_COUNTER |
  37143                           SOC_REG_FLAG_ED_CNTR,
  37144         0,
  37145         1,
  37146         soc_GR1023_BCM53400_A0r_fields,
  37147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37148         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37149         171,
  37150         -1,
  37151     },
  37152 #endif /* chips */
  37153 
  37154 #if defined(BCM_56142_A0)
  37155     { /* SOC_REG_INT_GRFRG_BCM56142_A0r */
  37156         soc_block_list[210],
  37157         soc_portreg,
  37158         1,
  37159         0,
  37160         0x8d,
  37161         SOC_REG_FLAG_COUNTER |
  37162                           SOC_REG_FLAG_ED_CNTR,
  37163         0,
  37164         1,
  37165         soc_GR1023r_fields,
  37166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37167         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37168         188,
  37169         -1,
  37170     },
  37171 #endif /* chips */
  37172 
  37173 #if defined(BCM_56150_A0)
  37174     { /* SOC_REG_INT_GRFRG_BCM56150_A0r */
  37175         soc_block_list[2],
  37176         soc_portreg,
  37177         1,
  37178         0,
  37179         0xd00,
  37180         SOC_REG_FLAG_COUNTER |
  37181                           SOC_REG_FLAG_ED_CNTR,
  37182         0,
  37183         1,
  37184         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  37185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37187         108,
  37188         -1,
  37189     },
  37190 #endif /* chips */
  37191 
  37192 #if defined(BCM_56160_A0)
  37193     { /* SOC_REG_INT_GRFRG_BCM56160_A0r */
  37194         soc_block_list[2],
  37195         soc_portreg,
  37196         1,
  37197         0,
  37198         0xd00,
  37199         SOC_REG_FLAG_COUNTER |
  37200                           SOC_REG_FLAG_ED_CNTR,
  37201         0,
  37202         1,
  37203         soc_GR1023_BCM53400_A0r_fields,
  37204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37206         112,
  37207         -1,
  37208     },
  37209 #endif /* chips */
  37210 
  37211 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  37212     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  37213     { /* SOC_REG_INT_GRFRG_BCM56224_A0r */
  37214         soc_block_list[2],
  37215         soc_portreg,
  37216         1,
  37217         0,
  37218         0xd,
  37219         SOC_REG_FLAG_COUNTER |
  37220                           SOC_REG_FLAG_ED_CNTR,
  37221         0,
  37222         1,
  37223         soc_GR1023r_fields,
  37224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37225         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37226         47,
  37227         -1,
  37228     },
  37229 #endif /* chips */
  37230 
  37231 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  37232     { /* SOC_REG_INT_GRFRG_BCM56334_A0r */
  37233         soc_block_list[210],
  37234         soc_portreg,
  37235         1,
  37236         0,
  37237         0x8d,
  37238         SOC_REG_FLAG_COUNTER |
  37239                           SOC_REG_FLAG_ED_CNTR,
  37240         0,
  37241         1,
  37242         soc_GR1023r_fields,
  37243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37244         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37245         183,
  37246         -1,
  37247     },
  37248 #endif /* chips */
  37249 
  37250 #if defined(BCM_56370_A0)
  37251     { /* SOC_REG_INT_GRFRG_BCM56370_A0r */
  37252         soc_block_list[9],
  37253         soc_portreg,
  37254         1,
  37255         0,
  37256         0xd00,
  37257         SOC_REG_FLAG_COUNTER |
  37258                           SOC_REG_FLAG_ED_CNTR,
  37259         0,
  37260         1,
  37261         soc_GR1023_BCM53400_A0r_fields,
  37262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37264         73,
  37265         -1,
  37266         3,
  37267     },
  37268 #endif /* chips */
  37269 
  37270 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  37271     { /* SOC_REG_INT_GRFRG_BCM56440_A0r */
  37272         soc_block_list[2],
  37273         soc_portreg,
  37274         1,
  37275         0,
  37276         0x8d,
  37277         SOC_REG_FLAG_COUNTER |
  37278                           SOC_REG_FLAG_ED_CNTR,
  37279         0,
  37280         1,
  37281         soc_GR1023r_fields,
  37282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37284         180,
  37285         -1,
  37286     },
  37287 #endif /* chips */
  37288 
  37289 #if defined(BCM_56514_A0)
  37290     { /* SOC_REG_INT_GRFRG_BCM56514_A0r */
  37291         soc_block_list[2],
  37292         soc_portreg,
  37293         1,
  37294         0,
  37295         0x1d,
  37296         SOC_REG_FLAG_COUNTER |
  37297                           SOC_REG_FLAG_ED_CNTR,
  37298         0,
  37299         1,
  37300         soc_GR1023r_fields,
  37301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37303         63,
  37304         -1,
  37305     },
  37306 #endif /* chips */
  37307 
  37308 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  37309     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  37310     { /* SOC_REG_INT_GRFRG_BCM56624_A0r */
  37311         soc_block_list[205],
  37312         soc_portreg,
  37313         1,
  37314         0,
  37315         0x9d,
  37316         SOC_REG_FLAG_COUNTER |
  37317                           SOC_REG_FLAG_ED_CNTR,
  37318         0,
  37319         1,
  37320         soc_GR1023r_fields,
  37321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37322         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37323         199,
  37324         -1,
  37325     },
  37326 #endif /* chips */
  37327 
  37328 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  37329     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  37330     { /* SOC_REG_INT_GRFRG_BCM56634_A0r */
  37331         soc_block_list[207],
  37332         soc_portreg,
  37333         1,
  37334         0,
  37335         0x9d,
  37336         SOC_REG_FLAG_COUNTER |
  37337                           SOC_REG_FLAG_ED_CNTR,
  37338         0,
  37339         1,
  37340         soc_GR1023r_fields,
  37341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37342         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37343         199,
  37344         -1,
  37345     },
  37346 #endif /* chips */
  37347 
  37348 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  37349     { /* SOC_REG_INT_GRFRG_BCM56685_A0r */
  37350         soc_block_list[209],
  37351         soc_portreg,
  37352         1,
  37353         0,
  37354         0x9d,
  37355         SOC_REG_FLAG_COUNTER |
  37356                           SOC_REG_FLAG_ED_CNTR,
  37357         0,
  37358         1,
  37359         soc_GR1023r_fields,
  37360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37361         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37362         199,
  37363         -1,
  37364     },
  37365 #endif /* chips */
  37366 
  37367 #if defined(BCM_56800_A0)
  37368     { /* SOC_REG_INT_GRFRG_BCM56800_A0r */
  37369         soc_block_list[9],
  37370         soc_portreg,
  37371         1,
  37372         0,
  37373         0x62,
  37374         SOC_REG_FLAG_COUNTER |
  37375                           SOC_REG_FLAG_ED_CNTR,
  37376         0,
  37377         1,
  37378         soc_GR1023r_fields,
  37379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37380         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37381         140,
  37382         -1,
  37383     },
  37384 #endif /* chips */
  37385 
  37386 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  37387     { /* SOC_REG_INT_GRFRG_BCM56820_A0r */
  37388         soc_block_list[206],
  37389         soc_portreg,
  37390         1,
  37391         0,
  37392         0x9e,
  37393         SOC_REG_FLAG_COUNTER |
  37394                           SOC_REG_FLAG_ED_CNTR,
  37395         0,
  37396         1,
  37397         soc_GR1023r_fields,
  37398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37399         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37400         210,
  37401         -1,
  37402     },
  37403 #endif /* chips */
  37404 
  37405 #if defined(BCM_88375_A0)
  37406     { /* SOC_REG_INT_GRFRG_BCM88375_A0r */
  37407         soc_block_list[2],
  37408         soc_portreg,
  37409         1,
  37410         0,
  37411         0xd00,
  37412         SOC_REG_FLAG_COUNTER,
  37413         0,
  37414         1,
  37415         soc_GRFRG_BCM88375_A0r_fields,
  37416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37418         13,
  37419         -1,
  37420     },
  37421 #endif /* chips */
  37422 
  37423 #if defined(BCM_88375_B0)
  37424     { /* SOC_REG_INT_GRFRG_BCM88375_B0r */
  37425         soc_block_list[2],
  37426         soc_portreg,
  37427         1,
  37428         0,
  37429         0xd00,
  37430         SOC_REG_FLAG_COUNTER,
  37431         0,
  37432         1,
  37433         soc_GRFRG_BCM88375_B0r_fields,
  37434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37436         13,
  37437         -1,
  37438     },
  37439 #endif /* chips */
  37440 
  37441 #if defined(BCM_88470_A0)
  37442     { /* SOC_REG_INT_GRFRG_BCM88470_A0r */
  37443         soc_block_list[2],
  37444         soc_portreg,
  37445         1,
  37446         0,
  37447         0xd00,
  37448         SOC_REG_FLAG_COUNTER,
  37449         0,
  37450         1,
  37451         soc_GRFRG_BCM88470_A0r_fields,
  37452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37454         13,
  37455         -1,
  37456     },
  37457 #endif /* chips */
  37458 
  37459 #if defined(BCM_88470_B0)
  37460     { /* SOC_REG_INT_GRFRG_BCM88470_B0r */
  37461         soc_block_list[2],
  37462         soc_portreg,
  37463         1,
  37464         0,
  37465         0xd00,
  37466         SOC_REG_FLAG_COUNTER,
  37467         0,
  37468         1,
  37469         soc_GRFRG_BCM88470_B0r_fields,
  37470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37471         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37472         13,
  37473         -1,
  37474     },
  37475 #endif /* chips */
  37476 
  37477 #if defined(BCM_88675_A0)
  37478     { /* SOC_REG_INT_GRFRG_BCM88675_A0r */
  37479         soc_block_list[2],
  37480         soc_portreg,
  37481         1,
  37482         0,
  37483         0xd00,
  37484         SOC_REG_FLAG_COUNTER,
  37485         0,
  37486         1,
  37487         soc_GRFRGr_fields,
  37488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37490         13,
  37491         -1,
  37492     },
  37493 #endif /* chips */
  37494 
  37495 #if defined(BCM_88675_B0)
  37496     { /* SOC_REG_INT_GRFRG_BCM88675_B0r */
  37497         soc_block_list[2],
  37498         soc_portreg,
  37499         1,
  37500         0,
  37501         0xd00,
  37502         SOC_REG_FLAG_COUNTER,
  37503         0,
  37504         1,
  37505         soc_GRFRG_BCM88675_B0r_fields,
  37506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37508         13,
  37509         -1,
  37510     },
  37511 #endif /* chips */
  37512 
  37513 #if defined(BCM_88680_A0)
  37514     { /* SOC_REG_INT_GRFRG_BCM88680_A0r */
  37515         soc_block_list[2],
  37516         soc_portreg,
  37517         1,
  37518         0,
  37519         0xd00,
  37520         SOC_REG_FLAG_COUNTER,
  37521         0,
  37522         1,
  37523         soc_GRFRG_BCM88680_A0r_fields,
  37524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37526         13,
  37527         -1,
  37528     },
  37529 #endif /* chips */
  37530 
  37531 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  37532     defined(BCM_56504_B0)
  37533     { /* SOC_REG_INT_GRJBRr */
  37534         soc_block_list[2],
  37535         soc_portreg,
  37536         1,
  37537         0,
  37538         0x17,
  37539         SOC_REG_FLAG_COUNTER |
  37540                           SOC_REG_FLAG_ED_CNTR,
  37541         0,
  37542         1,
  37543         soc_GR1023r_fields,
  37544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37545         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37546         57,
  37547         -1,
  37548     },
  37549 #endif /* chips */
  37550 
  37551 #if defined(BCM_53570_A0)
  37552     { /* SOC_REG_INT_GRJBRPr */
  37553         soc_block_list[2],
  37554         soc_portreg,
  37555         1,
  37556         0,
  37557         0x6800,
  37558         SOC_REG_FLAG_COUNTER,
  37559         0,
  37560         1,
  37561         soc_GR1023_BCM53400_A0r_fields,
  37562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37564         258,
  37565         -1,
  37566     },
  37567 #endif /* chips */
  37568 
  37569 #if defined(BCM_53570_B0)
  37570     { /* SOC_REG_INT_GRJBRP_BCM53570_B0r */
  37571         soc_block_list[2],
  37572         soc_portreg,
  37573         1,
  37574         0,
  37575         0x6800,
  37576         SOC_REG_FLAG_COUNTER,
  37577         0,
  37578         1,
  37579         soc_GR1023_BCM53400_A0r_fields,
  37580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37582         262,
  37583         -1,
  37584     },
  37585 #endif /* chips */
  37586 
  37587 #if defined(BCM_53400_A0)
  37588     { /* SOC_REG_INT_GRJBR_BCM53400_A0r */
  37589         soc_block_list[9],
  37590         soc_portreg,
  37591         1,
  37592         0,
  37593         0x900,
  37594         SOC_REG_FLAG_COUNTER,
  37595         0,
  37596         1,
  37597         soc_GR1023_BCM53400_A0r_fields,
  37598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37600         108,
  37601         -1,
  37602     },
  37603 #endif /* chips */
  37604 
  37605 #if defined(BCM_53540_A0)
  37606     { /* SOC_REG_INT_GRJBR_BCM53540_A0r */
  37607         soc_block_list[2],
  37608         soc_portreg,
  37609         1,
  37610         0,
  37611         0x900,
  37612         SOC_REG_FLAG_COUNTER,
  37613         0,
  37614         1,
  37615         soc_GR1023_BCM53400_A0r_fields,
  37616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37617         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37618         108,
  37619         -1,
  37620     },
  37621 #endif /* chips */
  37622 
  37623 #if defined(BCM_53570_A0)
  37624     { /* SOC_REG_INT_GRJBR_BCM53570_A0r */
  37625         soc_block_list[2],
  37626         soc_portreg,
  37627         1,
  37628         0,
  37629         0x900,
  37630         SOC_REG_FLAG_COUNTER,
  37631         0,
  37632         1,
  37633         soc_GR1023_BCM53400_A0r_fields,
  37634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37635         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37636         163,
  37637         -1,
  37638     },
  37639 #endif /* chips */
  37640 
  37641 #if defined(BCM_53570_B0)
  37642     { /* SOC_REG_INT_GRJBR_BCM53570_B0r */
  37643         soc_block_list[2],
  37644         soc_portreg,
  37645         1,
  37646         0,
  37647         0x900,
  37648         SOC_REG_FLAG_COUNTER,
  37649         0,
  37650         1,
  37651         soc_GR1023_BCM53400_A0r_fields,
  37652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37654         167,
  37655         -1,
  37656     },
  37657 #endif /* chips */
  37658 
  37659 #if defined(BCM_56142_A0)
  37660     { /* SOC_REG_INT_GRJBR_BCM56142_A0r */
  37661         soc_block_list[210],
  37662         soc_portreg,
  37663         1,
  37664         0,
  37665         0x89,
  37666         SOC_REG_FLAG_COUNTER,
  37667         0,
  37668         1,
  37669         soc_GR1023r_fields,
  37670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37671         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37672         184,
  37673         -1,
  37674     },
  37675 #endif /* chips */
  37676 
  37677 #if defined(BCM_56150_A0)
  37678     { /* SOC_REG_INT_GRJBR_BCM56150_A0r */
  37679         soc_block_list[2],
  37680         soc_portreg,
  37681         1,
  37682         0,
  37683         0x900,
  37684         SOC_REG_FLAG_COUNTER,
  37685         0,
  37686         1,
  37687         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  37688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37690         104,
  37691         -1,
  37692     },
  37693 #endif /* chips */
  37694 
  37695 #if defined(BCM_56160_A0)
  37696     { /* SOC_REG_INT_GRJBR_BCM56160_A0r */
  37697         soc_block_list[2],
  37698         soc_portreg,
  37699         1,
  37700         0,
  37701         0x900,
  37702         SOC_REG_FLAG_COUNTER,
  37703         0,
  37704         1,
  37705         soc_GR1023_BCM53400_A0r_fields,
  37706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37707         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37708         108,
  37709         -1,
  37710     },
  37711 #endif /* chips */
  37712 
  37713 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  37714     { /* SOC_REG_INT_GRJBR_BCM56334_A0r */
  37715         soc_block_list[210],
  37716         soc_portreg,
  37717         1,
  37718         0,
  37719         0x89,
  37720         SOC_REG_FLAG_COUNTER,
  37721         0,
  37722         1,
  37723         soc_GR1023r_fields,
  37724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37725         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37726         179,
  37727         -1,
  37728     },
  37729 #endif /* chips */
  37730 
  37731 #if defined(BCM_56370_A0)
  37732     { /* SOC_REG_INT_GRJBR_BCM56370_A0r */
  37733         soc_block_list[9],
  37734         soc_portreg,
  37735         1,
  37736         0,
  37737         0x900,
  37738         SOC_REG_FLAG_COUNTER,
  37739         0,
  37740         1,
  37741         soc_GR1023_BCM53400_A0r_fields,
  37742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37744         69,
  37745         -1,
  37746         3,
  37747     },
  37748 #endif /* chips */
  37749 
  37750 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  37751     { /* SOC_REG_INT_GRJBR_BCM56440_A0r */
  37752         soc_block_list[2],
  37753         soc_portreg,
  37754         1,
  37755         0,
  37756         0x89,
  37757         SOC_REG_FLAG_COUNTER,
  37758         0,
  37759         1,
  37760         soc_GR1023r_fields,
  37761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37763         176,
  37764         -1,
  37765     },
  37766 #endif /* chips */
  37767 
  37768 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  37769     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  37770     defined(BCM_56514_A0)
  37771     { /* SOC_REG_INT_GRJBR_BCM56514_A0r */
  37772         soc_block_list[2],
  37773         soc_portreg,
  37774         1,
  37775         0,
  37776         0x17,
  37777         SOC_REG_FLAG_COUNTER,
  37778         0,
  37779         1,
  37780         soc_GR1023r_fields,
  37781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37782         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37783         57,
  37784         -1,
  37785     },
  37786 #endif /* chips */
  37787 
  37788 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  37789     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  37790     { /* SOC_REG_INT_GRJBR_BCM56624_A0r */
  37791         soc_block_list[205],
  37792         soc_portreg,
  37793         1,
  37794         0,
  37795         0x97,
  37796         SOC_REG_FLAG_COUNTER,
  37797         0,
  37798         1,
  37799         soc_GR1023r_fields,
  37800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37801         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37802         193,
  37803         -1,
  37804     },
  37805 #endif /* chips */
  37806 
  37807 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  37808     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  37809     { /* SOC_REG_INT_GRJBR_BCM56634_A0r */
  37810         soc_block_list[207],
  37811         soc_portreg,
  37812         1,
  37813         0,
  37814         0x97,
  37815         SOC_REG_FLAG_COUNTER,
  37816         0,
  37817         1,
  37818         soc_GR1023r_fields,
  37819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37820         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37821         193,
  37822         -1,
  37823     },
  37824 #endif /* chips */
  37825 
  37826 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  37827     { /* SOC_REG_INT_GRJBR_BCM56685_A0r */
  37828         soc_block_list[209],
  37829         soc_portreg,
  37830         1,
  37831         0,
  37832         0x97,
  37833         SOC_REG_FLAG_COUNTER,
  37834         0,
  37835         1,
  37836         soc_GR1023r_fields,
  37837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37838         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37839         193,
  37840         -1,
  37841     },
  37842 #endif /* chips */
  37843 
  37844 #if defined(BCM_56800_A0)
  37845     { /* SOC_REG_INT_GRJBR_BCM56800_A0r */
  37846         soc_block_list[9],
  37847         soc_portreg,
  37848         1,
  37849         0,
  37850         0x5e,
  37851         SOC_REG_FLAG_COUNTER,
  37852         0,
  37853         1,
  37854         soc_GR1023r_fields,
  37855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37856         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37857         136,
  37858         -1,
  37859     },
  37860 #endif /* chips */
  37861 
  37862 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  37863     { /* SOC_REG_INT_GRJBR_BCM56820_A0r */
  37864         soc_block_list[206],
  37865         soc_portreg,
  37866         1,
  37867         0,
  37868         0x97,
  37869         SOC_REG_FLAG_COUNTER,
  37870         0,
  37871         1,
  37872         soc_GR1023r_fields,
  37873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37874         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37875         203,
  37876         -1,
  37877     },
  37878 #endif /* chips */
  37879 
  37880 #if defined(BCM_88375_A0)
  37881     { /* SOC_REG_INT_GRJBR_BCM88375_A0r */
  37882         soc_block_list[2],
  37883         soc_portreg,
  37884         1,
  37885         0,
  37886         0x900,
  37887         SOC_REG_FLAG_COUNTER,
  37888         0,
  37889         1,
  37890         soc_GRJBR_BCM88375_A0r_fields,
  37891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37893         9,
  37894         -1,
  37895     },
  37896 #endif /* chips */
  37897 
  37898 #if defined(BCM_88375_B0)
  37899     { /* SOC_REG_INT_GRJBR_BCM88375_B0r */
  37900         soc_block_list[2],
  37901         soc_portreg,
  37902         1,
  37903         0,
  37904         0x900,
  37905         SOC_REG_FLAG_COUNTER,
  37906         0,
  37907         1,
  37908         soc_GRJBR_BCM88375_B0r_fields,
  37909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37910         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37911         9,
  37912         -1,
  37913     },
  37914 #endif /* chips */
  37915 
  37916 #if defined(BCM_88470_A0)
  37917     { /* SOC_REG_INT_GRJBR_BCM88470_A0r */
  37918         soc_block_list[2],
  37919         soc_portreg,
  37920         1,
  37921         0,
  37922         0x900,
  37923         SOC_REG_FLAG_COUNTER,
  37924         0,
  37925         1,
  37926         soc_GRJBR_BCM88470_A0r_fields,
  37927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37928         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37929         9,
  37930         -1,
  37931     },
  37932 #endif /* chips */
  37933 
  37934 #if defined(BCM_88470_B0)
  37935     { /* SOC_REG_INT_GRJBR_BCM88470_B0r */
  37936         soc_block_list[2],
  37937         soc_portreg,
  37938         1,
  37939         0,
  37940         0x900,
  37941         SOC_REG_FLAG_COUNTER,
  37942         0,
  37943         1,
  37944         soc_GRJBR_BCM88470_B0r_fields,
  37945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37946         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37947         9,
  37948         -1,
  37949     },
  37950 #endif /* chips */
  37951 
  37952 #if defined(BCM_88675_A0)
  37953     { /* SOC_REG_INT_GRJBR_BCM88675_A0r */
  37954         soc_block_list[2],
  37955         soc_portreg,
  37956         1,
  37957         0,
  37958         0x900,
  37959         SOC_REG_FLAG_COUNTER,
  37960         0,
  37961         1,
  37962         soc_GRJBRr_fields,
  37963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37964         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37965         9,
  37966         -1,
  37967     },
  37968 #endif /* chips */
  37969 
  37970 #if defined(BCM_88675_B0)
  37971     { /* SOC_REG_INT_GRJBR_BCM88675_B0r */
  37972         soc_block_list[2],
  37973         soc_portreg,
  37974         1,
  37975         0,
  37976         0x900,
  37977         SOC_REG_FLAG_COUNTER,
  37978         0,
  37979         1,
  37980         soc_GRJBR_BCM88675_B0r_fields,
  37981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37982         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37983         9,
  37984         -1,
  37985     },
  37986 #endif /* chips */
  37987 
  37988 #if defined(BCM_88680_A0)
  37989     { /* SOC_REG_INT_GRJBR_BCM88680_A0r */
  37990         soc_block_list[2],
  37991         soc_portreg,
  37992         1,
  37993         0,
  37994         0x900,
  37995         SOC_REG_FLAG_COUNTER,
  37996         0,
  37997         1,
  37998         soc_GRJBR_BCM88680_A0r_fields,
  37999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38000         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38001         9,
  38002         -1,
  38003     },
  38004 #endif /* chips */
  38005 
  38006 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  38007     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  38008     { /* SOC_REG_INT_GRMCAr */
  38009         soc_block_list[2],
  38010         soc_portreg,
  38011         1,
  38012         0,
  38013         0xc,
  38014         SOC_REG_FLAG_COUNTER,
  38015         0,
  38016         1,
  38017         soc_GR1023r_fields,
  38018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38019         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38020         46,
  38021         -1,
  38022     },
  38023 #endif /* chips */
  38024 
  38025 #if defined(BCM_53570_A0)
  38026     { /* SOC_REG_INT_GRMCAPr */
  38027         soc_block_list[2],
  38028         soc_portreg,
  38029         1,
  38030         0,
  38031         0x6e00,
  38032         SOC_REG_FLAG_COUNTER,
  38033         0,
  38034         1,
  38035         soc_GR1023_BCM53400_A0r_fields,
  38036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38037         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38038         264,
  38039         -1,
  38040     },
  38041 #endif /* chips */
  38042 
  38043 #if defined(BCM_53570_B0)
  38044     { /* SOC_REG_INT_GRMCAP_BCM53570_B0r */
  38045         soc_block_list[2],
  38046         soc_portreg,
  38047         1,
  38048         0,
  38049         0x6e00,
  38050         SOC_REG_FLAG_COUNTER,
  38051         0,
  38052         1,
  38053         soc_GR1023_BCM53400_A0r_fields,
  38054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38055         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38056         268,
  38057         -1,
  38058     },
  38059 #endif /* chips */
  38060 
  38061 #if defined(BCM_53400_A0)
  38062     { /* SOC_REG_INT_GRMCA_BCM53400_A0r */
  38063         soc_block_list[9],
  38064         soc_portreg,
  38065         1,
  38066         0,
  38067         0xf00,
  38068         SOC_REG_FLAG_COUNTER,
  38069         0,
  38070         1,
  38071         soc_GR1023_BCM53400_A0r_fields,
  38072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38073         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38074         114,
  38075         -1,
  38076     },
  38077 #endif /* chips */
  38078 
  38079 #if defined(BCM_53540_A0)
  38080     { /* SOC_REG_INT_GRMCA_BCM53540_A0r */
  38081         soc_block_list[2],
  38082         soc_portreg,
  38083         1,
  38084         0,
  38085         0xf00,
  38086         SOC_REG_FLAG_COUNTER,
  38087         0,
  38088         1,
  38089         soc_GR1023_BCM53400_A0r_fields,
  38090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38092         114,
  38093         -1,
  38094     },
  38095 #endif /* chips */
  38096 
  38097 #if defined(BCM_53570_A0)
  38098     { /* SOC_REG_INT_GRMCA_BCM53570_A0r */
  38099         soc_block_list[2],
  38100         soc_portreg,
  38101         1,
  38102         0,
  38103         0xf00,
  38104         SOC_REG_FLAG_COUNTER,
  38105         0,
  38106         1,
  38107         soc_GR1023_BCM53400_A0r_fields,
  38108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38110         169,
  38111         -1,
  38112     },
  38113 #endif /* chips */
  38114 
  38115 #if defined(BCM_53570_B0)
  38116     { /* SOC_REG_INT_GRMCA_BCM53570_B0r */
  38117         soc_block_list[2],
  38118         soc_portreg,
  38119         1,
  38120         0,
  38121         0xf00,
  38122         SOC_REG_FLAG_COUNTER,
  38123         0,
  38124         1,
  38125         soc_GR1023_BCM53400_A0r_fields,
  38126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38127         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38128         173,
  38129         -1,
  38130     },
  38131 #endif /* chips */
  38132 
  38133 #if defined(BCM_56142_A0)
  38134     { /* SOC_REG_INT_GRMCA_BCM56142_A0r */
  38135         soc_block_list[210],
  38136         soc_portreg,
  38137         1,
  38138         0,
  38139         0x8f,
  38140         SOC_REG_FLAG_COUNTER,
  38141         0,
  38142         1,
  38143         soc_GR1023r_fields,
  38144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38145         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38146         190,
  38147         -1,
  38148     },
  38149 #endif /* chips */
  38150 
  38151 #if defined(BCM_56150_A0)
  38152     { /* SOC_REG_INT_GRMCA_BCM56150_A0r */
  38153         soc_block_list[2],
  38154         soc_portreg,
  38155         1,
  38156         0,
  38157         0xf00,
  38158         SOC_REG_FLAG_COUNTER,
  38159         0,
  38160         1,
  38161         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  38162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38163         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38164         110,
  38165         -1,
  38166     },
  38167 #endif /* chips */
  38168 
  38169 #if defined(BCM_56160_A0)
  38170     { /* SOC_REG_INT_GRMCA_BCM56160_A0r */
  38171         soc_block_list[2],
  38172         soc_portreg,
  38173         1,
  38174         0,
  38175         0xf00,
  38176         SOC_REG_FLAG_COUNTER,
  38177         0,
  38178         1,
  38179         soc_GR1023_BCM53400_A0r_fields,
  38180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38182         114,
  38183         -1,
  38184     },
  38185 #endif /* chips */
  38186 
  38187 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  38188     { /* SOC_REG_INT_GRMCA_BCM56334_A0r */
  38189         soc_block_list[210],
  38190         soc_portreg,
  38191         1,
  38192         0,
  38193         0x8f,
  38194         SOC_REG_FLAG_COUNTER,
  38195         0,
  38196         1,
  38197         soc_GR1023r_fields,
  38198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38200         185,
  38201         -1,
  38202     },
  38203 #endif /* chips */
  38204 
  38205 #if defined(BCM_56370_A0)
  38206     { /* SOC_REG_INT_GRMCA_BCM56370_A0r */
  38207         soc_block_list[9],
  38208         soc_portreg,
  38209         1,
  38210         0,
  38211         0xf00,
  38212         SOC_REG_FLAG_COUNTER,
  38213         0,
  38214         1,
  38215         soc_GR1023_BCM53400_A0r_fields,
  38216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38217         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38218         75,
  38219         -1,
  38220         3,
  38221     },
  38222 #endif /* chips */
  38223 
  38224 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  38225     { /* SOC_REG_INT_GRMCA_BCM56440_A0r */
  38226         soc_block_list[2],
  38227         soc_portreg,
  38228         1,
  38229         0,
  38230         0x8f,
  38231         SOC_REG_FLAG_COUNTER,
  38232         0,
  38233         1,
  38234         soc_GR1023r_fields,
  38235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38236         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38237         182,
  38238         -1,
  38239     },
  38240 #endif /* chips */
  38241 
  38242 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  38243     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  38244     { /* SOC_REG_INT_GRMCA_BCM56624_A0r */
  38245         soc_block_list[205],
  38246         soc_portreg,
  38247         1,
  38248         0,
  38249         0x8c,
  38250         SOC_REG_FLAG_COUNTER,
  38251         0,
  38252         1,
  38253         soc_GR1023r_fields,
  38254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38255         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38256         182,
  38257         -1,
  38258     },
  38259 #endif /* chips */
  38260 
  38261 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  38262     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  38263     { /* SOC_REG_INT_GRMCA_BCM56634_A0r */
  38264         soc_block_list[207],
  38265         soc_portreg,
  38266         1,
  38267         0,
  38268         0x8c,
  38269         SOC_REG_FLAG_COUNTER,
  38270         0,
  38271         1,
  38272         soc_GR1023r_fields,
  38273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38274         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38275         182,
  38276         -1,
  38277     },
  38278 #endif /* chips */
  38279 
  38280 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  38281     { /* SOC_REG_INT_GRMCA_BCM56685_A0r */
  38282         soc_block_list[209],
  38283         soc_portreg,
  38284         1,
  38285         0,
  38286         0x8c,
  38287         SOC_REG_FLAG_COUNTER,
  38288         0,
  38289         1,
  38290         soc_GR1023r_fields,
  38291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38293         182,
  38294         -1,
  38295     },
  38296 #endif /* chips */
  38297 
  38298 #if defined(BCM_56800_A0)
  38299     { /* SOC_REG_INT_GRMCA_BCM56800_A0r */
  38300         soc_block_list[9],
  38301         soc_portreg,
  38302         1,
  38303         0,
  38304         0x53,
  38305         SOC_REG_FLAG_COUNTER,
  38306         0,
  38307         1,
  38308         soc_GR1023r_fields,
  38309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38310         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38311         125,
  38312         -1,
  38313     },
  38314 #endif /* chips */
  38315 
  38316 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  38317     { /* SOC_REG_INT_GRMCA_BCM56820_A0r */
  38318         soc_block_list[206],
  38319         soc_portreg,
  38320         1,
  38321         0,
  38322         0x8c,
  38323         SOC_REG_FLAG_COUNTER,
  38324         0,
  38325         1,
  38326         soc_GR1023r_fields,
  38327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38328         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38329         192,
  38330         -1,
  38331     },
  38332 #endif /* chips */
  38333 
  38334 #if defined(BCM_88375_A0)
  38335     { /* SOC_REG_INT_GRMCA_BCM88375_A0r */
  38336         soc_block_list[2],
  38337         soc_portreg,
  38338         1,
  38339         0,
  38340         0xf00,
  38341         SOC_REG_FLAG_COUNTER,
  38342         0,
  38343         1,
  38344         soc_GRMCA_BCM88375_A0r_fields,
  38345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38346         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38347         15,
  38348         -1,
  38349     },
  38350 #endif /* chips */
  38351 
  38352 #if defined(BCM_88375_B0)
  38353     { /* SOC_REG_INT_GRMCA_BCM88375_B0r */
  38354         soc_block_list[2],
  38355         soc_portreg,
  38356         1,
  38357         0,
  38358         0xf00,
  38359         SOC_REG_FLAG_COUNTER,
  38360         0,
  38361         1,
  38362         soc_GRMCA_BCM88375_B0r_fields,
  38363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38364         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38365         15,
  38366         -1,
  38367     },
  38368 #endif /* chips */
  38369 
  38370 #if defined(BCM_88470_A0)
  38371     { /* SOC_REG_INT_GRMCA_BCM88470_A0r */
  38372         soc_block_list[2],
  38373         soc_portreg,
  38374         1,
  38375         0,
  38376         0xf00,
  38377         SOC_REG_FLAG_COUNTER,
  38378         0,
  38379         1,
  38380         soc_GRMCA_BCM88470_A0r_fields,
  38381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38383         15,
  38384         -1,
  38385     },
  38386 #endif /* chips */
  38387 
  38388 #if defined(BCM_88470_B0)
  38389     { /* SOC_REG_INT_GRMCA_BCM88470_B0r */
  38390         soc_block_list[2],
  38391         soc_portreg,
  38392         1,
  38393         0,
  38394         0xf00,
  38395         SOC_REG_FLAG_COUNTER,
  38396         0,
  38397         1,
  38398         soc_GRMCA_BCM88470_B0r_fields,
  38399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38400         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38401         15,
  38402         -1,
  38403     },
  38404 #endif /* chips */
  38405 
  38406 #if defined(BCM_88675_A0)
  38407     { /* SOC_REG_INT_GRMCA_BCM88675_A0r */
  38408         soc_block_list[2],
  38409         soc_portreg,
  38410         1,
  38411         0,
  38412         0xf00,
  38413         SOC_REG_FLAG_COUNTER,
  38414         0,
  38415         1,
  38416         soc_GRMCAr_fields,
  38417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38418         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38419         15,
  38420         -1,
  38421     },
  38422 #endif /* chips */
  38423 
  38424 #if defined(BCM_88675_B0)
  38425     { /* SOC_REG_INT_GRMCA_BCM88675_B0r */
  38426         soc_block_list[2],
  38427         soc_portreg,
  38428         1,
  38429         0,
  38430         0xf00,
  38431         SOC_REG_FLAG_COUNTER,
  38432         0,
  38433         1,
  38434         soc_GRMCA_BCM88675_B0r_fields,
  38435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38436         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38437         15,
  38438         -1,
  38439     },
  38440 #endif /* chips */
  38441 
  38442 #if defined(BCM_88680_A0)
  38443     { /* SOC_REG_INT_GRMCA_BCM88680_A0r */
  38444         soc_block_list[2],
  38445         soc_portreg,
  38446         1,
  38447         0,
  38448         0xf00,
  38449         SOC_REG_FLAG_COUNTER,
  38450         0,
  38451         1,
  38452         soc_GRMCA_BCM88680_A0r_fields,
  38453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38454         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38455         15,
  38456         -1,
  38457     },
  38458 #endif /* chips */
  38459 
  38460 #if defined(BCM_53570_A0)
  38461     { /* SOC_REG_INT_GRMFAEPr */
  38462         soc_block_list[2],
  38463         soc_portreg,
  38464         1,
  38465         0,
  38466         0x8400,
  38467         SOC_REG_FLAG_COUNTER,
  38468         0,
  38469         1,
  38470         soc_GR1023_BCM53400_A0r_fields,
  38471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38472         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38473         286,
  38474         -1,
  38475     },
  38476 #endif /* chips */
  38477 
  38478 #if defined(BCM_53570_B0)
  38479     { /* SOC_REG_INT_GRMFAEP_BCM53570_B0r */
  38480         soc_block_list[2],
  38481         soc_portreg,
  38482         1,
  38483         0,
  38484         0x8400,
  38485         SOC_REG_FLAG_COUNTER,
  38486         0,
  38487         1,
  38488         soc_GR1023_BCM53400_A0r_fields,
  38489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38490         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38491         290,
  38492         -1,
  38493     },
  38494 #endif /* chips */
  38495 
  38496 #if defined(BCM_53570_A0)
  38497     { /* SOC_REG_INT_GRMFAOPr */
  38498         soc_block_list[2],
  38499         soc_portreg,
  38500         1,
  38501         0,
  38502         0x7e00,
  38503         SOC_REG_FLAG_COUNTER,
  38504         0,
  38505         1,
  38506         soc_GR1023_BCM53400_A0r_fields,
  38507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38508         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38509         280,
  38510         -1,
  38511     },
  38512 #endif /* chips */
  38513 
  38514 #if defined(BCM_53570_B0)
  38515     { /* SOC_REG_INT_GRMFAOP_BCM53570_B0r */
  38516         soc_block_list[2],
  38517         soc_portreg,
  38518         1,
  38519         0,
  38520         0x7e00,
  38521         SOC_REG_FLAG_COUNTER,
  38522         0,
  38523         1,
  38524         soc_GR1023_BCM53400_A0r_fields,
  38525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38526         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38527         284,
  38528         -1,
  38529     },
  38530 #endif /* chips */
  38531 
  38532 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  38533     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  38534     { /* SOC_REG_INT_GRMGVr */
  38535         soc_block_list[2],
  38536         soc_portreg,
  38537         1,
  38538         0,
  38539         0x6,
  38540         SOC_REG_FLAG_COUNTER,
  38541         0,
  38542         1,
  38543         soc_GR1023r_fields,
  38544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38545         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38546         40,
  38547         -1,
  38548     },
  38549 #endif /* chips */
  38550 
  38551 #if defined(BCM_53570_A0)
  38552     { /* SOC_REG_INT_GRMGVPr */
  38553         soc_block_list[2],
  38554         soc_portreg,
  38555         1,
  38556         0,
  38557         0x7600,
  38558         SOC_REG_FLAG_COUNTER,
  38559         0,
  38560         1,
  38561         soc_GR1023_BCM53400_A0r_fields,
  38562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38564         272,
  38565         -1,
  38566     },
  38567 #endif /* chips */
  38568 
  38569 #if defined(BCM_53570_B0)
  38570     { /* SOC_REG_INT_GRMGVP_BCM53570_B0r */
  38571         soc_block_list[2],
  38572         soc_portreg,
  38573         1,
  38574         0,
  38575         0x7600,
  38576         SOC_REG_FLAG_COUNTER,
  38577         0,
  38578         1,
  38579         soc_GR1023_BCM53400_A0r_fields,
  38580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38582         276,
  38583         -1,
  38584     },
  38585 #endif /* chips */
  38586 
  38587 #if defined(BCM_53400_A0)
  38588     { /* SOC_REG_INT_GRMGV_BCM53400_A0r */
  38589         soc_block_list[9],
  38590         soc_portreg,
  38591         1,
  38592         0,
  38593         0x1700,
  38594         SOC_REG_FLAG_COUNTER,
  38595         0,
  38596         1,
  38597         soc_GR1023_BCM53400_A0r_fields,
  38598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38600         122,
  38601         -1,
  38602     },
  38603 #endif /* chips */
  38604 
  38605 #if defined(BCM_53540_A0)
  38606     { /* SOC_REG_INT_GRMGV_BCM53540_A0r */
  38607         soc_block_list[2],
  38608         soc_portreg,
  38609         1,
  38610         0,
  38611         0x1700,
  38612         SOC_REG_FLAG_COUNTER,
  38613         0,
  38614         1,
  38615         soc_GR1023_BCM53400_A0r_fields,
  38616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38617         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38618         122,
  38619         -1,
  38620     },
  38621 #endif /* chips */
  38622 
  38623 #if defined(BCM_53570_A0)
  38624     { /* SOC_REG_INT_GRMGV_BCM53570_A0r */
  38625         soc_block_list[2],
  38626         soc_portreg,
  38627         1,
  38628         0,
  38629         0x1700,
  38630         SOC_REG_FLAG_COUNTER,
  38631         0,
  38632         1,
  38633         soc_GR1023_BCM53400_A0r_fields,
  38634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38635         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38636         177,
  38637         -1,
  38638     },
  38639 #endif /* chips */
  38640 
  38641 #if defined(BCM_53570_B0)
  38642     { /* SOC_REG_INT_GRMGV_BCM53570_B0r */
  38643         soc_block_list[2],
  38644         soc_portreg,
  38645         1,
  38646         0,
  38647         0x1700,
  38648         SOC_REG_FLAG_COUNTER,
  38649         0,
  38650         1,
  38651         soc_GR1023_BCM53400_A0r_fields,
  38652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38654         181,
  38655         -1,
  38656     },
  38657 #endif /* chips */
  38658 
  38659 #if defined(BCM_56142_A0)
  38660     { /* SOC_REG_INT_GRMGV_BCM56142_A0r */
  38661         soc_block_list[210],
  38662         soc_portreg,
  38663         1,
  38664         0,
  38665         0x97,
  38666         SOC_REG_FLAG_COUNTER,
  38667         0,
  38668         1,
  38669         soc_GR1023r_fields,
  38670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38671         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38672         198,
  38673         -1,
  38674     },
  38675 #endif /* chips */
  38676 
  38677 #if defined(BCM_56150_A0)
  38678     { /* SOC_REG_INT_GRMGV_BCM56150_A0r */
  38679         soc_block_list[2],
  38680         soc_portreg,
  38681         1,
  38682         0,
  38683         0x1700,
  38684         SOC_REG_FLAG_COUNTER,
  38685         0,
  38686         1,
  38687         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  38688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38690         118,
  38691         -1,
  38692     },
  38693 #endif /* chips */
  38694 
  38695 #if defined(BCM_56160_A0)
  38696     { /* SOC_REG_INT_GRMGV_BCM56160_A0r */
  38697         soc_block_list[2],
  38698         soc_portreg,
  38699         1,
  38700         0,
  38701         0x1700,
  38702         SOC_REG_FLAG_COUNTER,
  38703         0,
  38704         1,
  38705         soc_GR1023_BCM53400_A0r_fields,
  38706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38707         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38708         122,
  38709         -1,
  38710     },
  38711 #endif /* chips */
  38712 
  38713 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  38714     { /* SOC_REG_INT_GRMGV_BCM56334_A0r */
  38715         soc_block_list[210],
  38716         soc_portreg,
  38717         1,
  38718         0,
  38719         0x97,
  38720         SOC_REG_FLAG_COUNTER,
  38721         0,
  38722         1,
  38723         soc_GR1023r_fields,
  38724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38725         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38726         193,
  38727         -1,
  38728     },
  38729 #endif /* chips */
  38730 
  38731 #if defined(BCM_56370_A0)
  38732     { /* SOC_REG_INT_GRMGV_BCM56370_A0r */
  38733         soc_block_list[9],
  38734         soc_portreg,
  38735         1,
  38736         0,
  38737         0x1700,
  38738         SOC_REG_FLAG_COUNTER,
  38739         0,
  38740         1,
  38741         soc_GR1023_BCM53400_A0r_fields,
  38742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38744         83,
  38745         -1,
  38746         3,
  38747     },
  38748 #endif /* chips */
  38749 
  38750 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  38751     { /* SOC_REG_INT_GRMGV_BCM56440_A0r */
  38752         soc_block_list[2],
  38753         soc_portreg,
  38754         1,
  38755         0,
  38756         0x97,
  38757         SOC_REG_FLAG_COUNTER,
  38758         0,
  38759         1,
  38760         soc_GR1023r_fields,
  38761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38763         190,
  38764         -1,
  38765     },
  38766 #endif /* chips */
  38767 
  38768 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  38769     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  38770     { /* SOC_REG_INT_GRMGV_BCM56624_A0r */
  38771         soc_block_list[205],
  38772         soc_portreg,
  38773         1,
  38774         0,
  38775         0x86,
  38776         SOC_REG_FLAG_COUNTER,
  38777         0,
  38778         1,
  38779         soc_GR1023r_fields,
  38780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38782         176,
  38783         -1,
  38784     },
  38785 #endif /* chips */
  38786 
  38787 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  38788     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  38789     { /* SOC_REG_INT_GRMGV_BCM56634_A0r */
  38790         soc_block_list[207],
  38791         soc_portreg,
  38792         1,
  38793         0,
  38794         0x86,
  38795         SOC_REG_FLAG_COUNTER,
  38796         0,
  38797         1,
  38798         soc_GR1023r_fields,
  38799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38801         176,
  38802         -1,
  38803     },
  38804 #endif /* chips */
  38805 
  38806 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  38807     { /* SOC_REG_INT_GRMGV_BCM56685_A0r */
  38808         soc_block_list[209],
  38809         soc_portreg,
  38810         1,
  38811         0,
  38812         0x86,
  38813         SOC_REG_FLAG_COUNTER,
  38814         0,
  38815         1,
  38816         soc_GR1023r_fields,
  38817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38819         176,
  38820         -1,
  38821     },
  38822 #endif /* chips */
  38823 
  38824 #if defined(BCM_56800_A0)
  38825     { /* SOC_REG_INT_GRMGV_BCM56800_A0r */
  38826         soc_block_list[9],
  38827         soc_portreg,
  38828         1,
  38829         0,
  38830         0x4d,
  38831         SOC_REG_FLAG_COUNTER,
  38832         0,
  38833         1,
  38834         soc_GR1023r_fields,
  38835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38836         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38837         119,
  38838         -1,
  38839     },
  38840 #endif /* chips */
  38841 
  38842 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  38843     { /* SOC_REG_INT_GRMGV_BCM56820_A0r */
  38844         soc_block_list[206],
  38845         soc_portreg,
  38846         1,
  38847         0,
  38848         0x86,
  38849         SOC_REG_FLAG_COUNTER,
  38850         0,
  38851         1,
  38852         soc_GR1023r_fields,
  38853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38855         186,
  38856         -1,
  38857     },
  38858 #endif /* chips */
  38859 
  38860 #if defined(BCM_88375_A0)
  38861     { /* SOC_REG_INT_GRMGV_BCM88375_A0r */
  38862         soc_block_list[2],
  38863         soc_portreg,
  38864         1,
  38865         0,
  38866         0x1700,
  38867         SOC_REG_FLAG_COUNTER,
  38868         0,
  38869         1,
  38870         soc_GRMGV_BCM88375_A0r_fields,
  38871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38872         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38873         23,
  38874         -1,
  38875     },
  38876 #endif /* chips */
  38877 
  38878 #if defined(BCM_88375_B0)
  38879     { /* SOC_REG_INT_GRMGV_BCM88375_B0r */
  38880         soc_block_list[2],
  38881         soc_portreg,
  38882         1,
  38883         0,
  38884         0x1700,
  38885         SOC_REG_FLAG_COUNTER,
  38886         0,
  38887         1,
  38888         soc_GRMGV_BCM88375_B0r_fields,
  38889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38890         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38891         23,
  38892         -1,
  38893     },
  38894 #endif /* chips */
  38895 
  38896 #if defined(BCM_88470_A0)
  38897     { /* SOC_REG_INT_GRMGV_BCM88470_A0r */
  38898         soc_block_list[2],
  38899         soc_portreg,
  38900         1,
  38901         0,
  38902         0x1700,
  38903         SOC_REG_FLAG_COUNTER,
  38904         0,
  38905         1,
  38906         soc_GRMGV_BCM88470_A0r_fields,
  38907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38908         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38909         23,
  38910         -1,
  38911     },
  38912 #endif /* chips */
  38913 
  38914 #if defined(BCM_88470_B0)
  38915     { /* SOC_REG_INT_GRMGV_BCM88470_B0r */
  38916         soc_block_list[2],
  38917         soc_portreg,
  38918         1,
  38919         0,
  38920         0x1700,
  38921         SOC_REG_FLAG_COUNTER,
  38922         0,
  38923         1,
  38924         soc_GRMGV_BCM88470_B0r_fields,
  38925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38926         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38927         23,
  38928         -1,
  38929     },
  38930 #endif /* chips */
  38931 
  38932 #if defined(BCM_88675_A0)
  38933     { /* SOC_REG_INT_GRMGV_BCM88675_A0r */
  38934         soc_block_list[2],
  38935         soc_portreg,
  38936         1,
  38937         0,
  38938         0x1700,
  38939         SOC_REG_FLAG_COUNTER,
  38940         0,
  38941         1,
  38942         soc_GRMGVr_fields,
  38943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38944         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38945         23,
  38946         -1,
  38947     },
  38948 #endif /* chips */
  38949 
  38950 #if defined(BCM_88675_B0)
  38951     { /* SOC_REG_INT_GRMGV_BCM88675_B0r */
  38952         soc_block_list[2],
  38953         soc_portreg,
  38954         1,
  38955         0,
  38956         0x1700,
  38957         SOC_REG_FLAG_COUNTER,
  38958         0,
  38959         1,
  38960         soc_GRMGV_BCM88675_B0r_fields,
  38961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38962         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38963         23,
  38964         -1,
  38965     },
  38966 #endif /* chips */
  38967 
  38968 #if defined(BCM_88680_A0)
  38969     { /* SOC_REG_INT_GRMGV_BCM88680_A0r */
  38970         soc_block_list[2],
  38971         soc_portreg,
  38972         1,
  38973         0,
  38974         0x1700,
  38975         SOC_REG_FLAG_COUNTER,
  38976         0,
  38977         1,
  38978         soc_GRMGV_BCM88680_A0r_fields,
  38979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38980         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38981         23,
  38982         -1,
  38983     },
  38984 #endif /* chips */
  38985 
  38986 #if defined(BCM_53570_A0)
  38987     { /* SOC_REG_INT_GRMSEPr */
  38988         soc_block_list[2],
  38989         soc_portreg,
  38990         1,
  38991         0,
  38992         0x8500,
  38993         SOC_REG_FLAG_COUNTER,
  38994         0,
  38995         1,
  38996         soc_GR1023_BCM53400_A0r_fields,
  38997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38998         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38999         287,
  39000         -1,
  39001     },
  39002 #endif /* chips */
  39003 
  39004 #if defined(BCM_53570_B0)
  39005     { /* SOC_REG_INT_GRMSEP_BCM53570_B0r */
  39006         soc_block_list[2],
  39007         soc_portreg,
  39008         1,
  39009         0,
  39010         0x8500,
  39011         SOC_REG_FLAG_COUNTER,
  39012         0,
  39013         1,
  39014         soc_GR1023_BCM53400_A0r_fields,
  39015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39016         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39017         291,
  39018         -1,
  39019     },
  39020 #endif /* chips */
  39021 
  39022 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  39023     defined(BCM_56504_B0)
  39024     { /* SOC_REG_INT_GRMTUEr */
  39025         soc_block_list[2],
  39026         soc_portreg,
  39027         1,
  39028         0,
  39029         0x18,
  39030         SOC_REG_FLAG_COUNTER |
  39031                           SOC_REG_FLAG_ED_CNTR,
  39032         0,
  39033         1,
  39034         soc_GR1023r_fields,
  39035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39036         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39037         58,
  39038         -1,
  39039     },
  39040 #endif /* chips */
  39041 
  39042 #if defined(BCM_53570_A0)
  39043     { /* SOC_REG_INT_GRMTUEPr */
  39044         soc_block_list[2],
  39045         soc_portreg,
  39046         1,
  39047         0,
  39048         0x6900,
  39049         SOC_REG_FLAG_COUNTER,
  39050         0,
  39051         1,
  39052         soc_GR1023_BCM53400_A0r_fields,
  39053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39054         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39055         259,
  39056         -1,
  39057     },
  39058 #endif /* chips */
  39059 
  39060 #if defined(BCM_53570_B0)
  39061     { /* SOC_REG_INT_GRMTUEP_BCM53570_B0r */
  39062         soc_block_list[2],
  39063         soc_portreg,
  39064         1,
  39065         0,
  39066         0x6900,
  39067         SOC_REG_FLAG_COUNTER,
  39068         0,
  39069         1,
  39070         soc_GR1023_BCM53400_A0r_fields,
  39071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39072         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39073         263,
  39074         -1,
  39075     },
  39076 #endif /* chips */
  39077 
  39078 #if defined(BCM_53400_A0)
  39079     { /* SOC_REG_INT_GRMTUE_BCM53400_A0r */
  39080         soc_block_list[9],
  39081         soc_portreg,
  39082         1,
  39083         0,
  39084         0xa00,
  39085         SOC_REG_FLAG_COUNTER,
  39086         0,
  39087         1,
  39088         soc_GR1023_BCM53400_A0r_fields,
  39089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39091         109,
  39092         -1,
  39093     },
  39094 #endif /* chips */
  39095 
  39096 #if defined(BCM_53540_A0)
  39097     { /* SOC_REG_INT_GRMTUE_BCM53540_A0r */
  39098         soc_block_list[2],
  39099         soc_portreg,
  39100         1,
  39101         0,
  39102         0xa00,
  39103         SOC_REG_FLAG_COUNTER,
  39104         0,
  39105         1,
  39106         soc_GR1023_BCM53400_A0r_fields,
  39107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39109         109,
  39110         -1,
  39111     },
  39112 #endif /* chips */
  39113 
  39114 #if defined(BCM_53570_A0)
  39115     { /* SOC_REG_INT_GRMTUE_BCM53570_A0r */
  39116         soc_block_list[2],
  39117         soc_portreg,
  39118         1,
  39119         0,
  39120         0xa00,
  39121         SOC_REG_FLAG_COUNTER,
  39122         0,
  39123         1,
  39124         soc_GR1023_BCM53400_A0r_fields,
  39125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39126         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39127         164,
  39128         -1,
  39129     },
  39130 #endif /* chips */
  39131 
  39132 #if defined(BCM_53570_B0)
  39133     { /* SOC_REG_INT_GRMTUE_BCM53570_B0r */
  39134         soc_block_list[2],
  39135         soc_portreg,
  39136         1,
  39137         0,
  39138         0xa00,
  39139         SOC_REG_FLAG_COUNTER,
  39140         0,
  39141         1,
  39142         soc_GR1023_BCM53400_A0r_fields,
  39143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39144         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39145         168,
  39146         -1,
  39147     },
  39148 #endif /* chips */
  39149 
  39150 #if defined(BCM_56142_A0)
  39151     { /* SOC_REG_INT_GRMTUE_BCM56142_A0r */
  39152         soc_block_list[210],
  39153         soc_portreg,
  39154         1,
  39155         0,
  39156         0x8a,
  39157         SOC_REG_FLAG_COUNTER,
  39158         0,
  39159         1,
  39160         soc_GR1023r_fields,
  39161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39163         185,
  39164         -1,
  39165     },
  39166 #endif /* chips */
  39167 
  39168 #if defined(BCM_56150_A0)
  39169     { /* SOC_REG_INT_GRMTUE_BCM56150_A0r */
  39170         soc_block_list[2],
  39171         soc_portreg,
  39172         1,
  39173         0,
  39174         0xa00,
  39175         SOC_REG_FLAG_COUNTER,
  39176         0,
  39177         1,
  39178         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  39179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39180         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39181         105,
  39182         -1,
  39183     },
  39184 #endif /* chips */
  39185 
  39186 #if defined(BCM_56160_A0)
  39187     { /* SOC_REG_INT_GRMTUE_BCM56160_A0r */
  39188         soc_block_list[2],
  39189         soc_portreg,
  39190         1,
  39191         0,
  39192         0xa00,
  39193         SOC_REG_FLAG_COUNTER,
  39194         0,
  39195         1,
  39196         soc_GR1023_BCM53400_A0r_fields,
  39197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39198         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39199         109,
  39200         -1,
  39201     },
  39202 #endif /* chips */
  39203 
  39204 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  39205     { /* SOC_REG_INT_GRMTUE_BCM56334_A0r */
  39206         soc_block_list[210],
  39207         soc_portreg,
  39208         1,
  39209         0,
  39210         0x8a,
  39211         SOC_REG_FLAG_COUNTER,
  39212         0,
  39213         1,
  39214         soc_GR1023r_fields,
  39215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39216         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39217         180,
  39218         -1,
  39219     },
  39220 #endif /* chips */
  39221 
  39222 #if defined(BCM_56370_A0)
  39223     { /* SOC_REG_INT_GRMTUE_BCM56370_A0r */
  39224         soc_block_list[9],
  39225         soc_portreg,
  39226         1,
  39227         0,
  39228         0xa00,
  39229         SOC_REG_FLAG_COUNTER,
  39230         0,
  39231         1,
  39232         soc_GR1023_BCM53400_A0r_fields,
  39233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39234         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39235         70,
  39236         -1,
  39237         3,
  39238     },
  39239 #endif /* chips */
  39240 
  39241 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  39242     { /* SOC_REG_INT_GRMTUE_BCM56440_A0r */
  39243         soc_block_list[2],
  39244         soc_portreg,
  39245         1,
  39246         0,
  39247         0x8a,
  39248         SOC_REG_FLAG_COUNTER,
  39249         0,
  39250         1,
  39251         soc_GR1023r_fields,
  39252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39253         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39254         177,
  39255         -1,
  39256     },
  39257 #endif /* chips */
  39258 
  39259 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  39260     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  39261     defined(BCM_56514_A0)
  39262     { /* SOC_REG_INT_GRMTUE_BCM56514_A0r */
  39263         soc_block_list[2],
  39264         soc_portreg,
  39265         1,
  39266         0,
  39267         0x18,
  39268         SOC_REG_FLAG_COUNTER,
  39269         0,
  39270         1,
  39271         soc_GR1023r_fields,
  39272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39273         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39274         58,
  39275         -1,
  39276     },
  39277 #endif /* chips */
  39278 
  39279 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  39280     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  39281     { /* SOC_REG_INT_GRMTUE_BCM56624_A0r */
  39282         soc_block_list[205],
  39283         soc_portreg,
  39284         1,
  39285         0,
  39286         0x98,
  39287         SOC_REG_FLAG_COUNTER,
  39288         0,
  39289         1,
  39290         soc_GR1023r_fields,
  39291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39293         194,
  39294         -1,
  39295     },
  39296 #endif /* chips */
  39297 
  39298 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  39299     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  39300     { /* SOC_REG_INT_GRMTUE_BCM56634_A0r */
  39301         soc_block_list[207],
  39302         soc_portreg,
  39303         1,
  39304         0,
  39305         0x98,
  39306         SOC_REG_FLAG_COUNTER,
  39307         0,
  39308         1,
  39309         soc_GR1023r_fields,
  39310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39312         194,
  39313         -1,
  39314     },
  39315 #endif /* chips */
  39316 
  39317 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  39318     { /* SOC_REG_INT_GRMTUE_BCM56685_A0r */
  39319         soc_block_list[209],
  39320         soc_portreg,
  39321         1,
  39322         0,
  39323         0x98,
  39324         SOC_REG_FLAG_COUNTER,
  39325         0,
  39326         1,
  39327         soc_GR1023r_fields,
  39328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39329         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39330         194,
  39331         -1,
  39332     },
  39333 #endif /* chips */
  39334 
  39335 #if defined(BCM_56800_A0)
  39336     { /* SOC_REG_INT_GRMTUE_BCM56800_A0r */
  39337         soc_block_list[9],
  39338         soc_portreg,
  39339         1,
  39340         0,
  39341         0x5f,
  39342         SOC_REG_FLAG_COUNTER,
  39343         0,
  39344         1,
  39345         soc_GR1023r_fields,
  39346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39347         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39348         137,
  39349         -1,
  39350     },
  39351 #endif /* chips */
  39352 
  39353 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  39354     { /* SOC_REG_INT_GRMTUE_BCM56820_A0r */
  39355         soc_block_list[206],
  39356         soc_portreg,
  39357         1,
  39358         0,
  39359         0x98,
  39360         SOC_REG_FLAG_COUNTER,
  39361         0,
  39362         1,
  39363         soc_GR1023r_fields,
  39364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39365         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39366         204,
  39367         -1,
  39368     },
  39369 #endif /* chips */
  39370 
  39371 #if defined(BCM_88375_A0)
  39372     { /* SOC_REG_INT_GRMTUE_BCM88375_A0r */
  39373         soc_block_list[2],
  39374         soc_portreg,
  39375         1,
  39376         0,
  39377         0xa00,
  39378         SOC_REG_FLAG_COUNTER,
  39379         0,
  39380         1,
  39381         soc_GRMTUE_BCM88375_A0r_fields,
  39382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39383         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39384         10,
  39385         -1,
  39386     },
  39387 #endif /* chips */
  39388 
  39389 #if defined(BCM_88375_B0)
  39390     { /* SOC_REG_INT_GRMTUE_BCM88375_B0r */
  39391         soc_block_list[2],
  39392         soc_portreg,
  39393         1,
  39394         0,
  39395         0xa00,
  39396         SOC_REG_FLAG_COUNTER,
  39397         0,
  39398         1,
  39399         soc_GRMTUE_BCM88375_B0r_fields,
  39400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39401         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39402         10,
  39403         -1,
  39404     },
  39405 #endif /* chips */
  39406 
  39407 #if defined(BCM_88470_A0)
  39408     { /* SOC_REG_INT_GRMTUE_BCM88470_A0r */
  39409         soc_block_list[2],
  39410         soc_portreg,
  39411         1,
  39412         0,
  39413         0xa00,
  39414         SOC_REG_FLAG_COUNTER,
  39415         0,
  39416         1,
  39417         soc_GRMTUE_BCM88470_A0r_fields,
  39418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39420         10,
  39421         -1,
  39422     },
  39423 #endif /* chips */
  39424 
  39425 #if defined(BCM_88470_B0)
  39426     { /* SOC_REG_INT_GRMTUE_BCM88470_B0r */
  39427         soc_block_list[2],
  39428         soc_portreg,
  39429         1,
  39430         0,
  39431         0xa00,
  39432         SOC_REG_FLAG_COUNTER,
  39433         0,
  39434         1,
  39435         soc_GRMTUE_BCM88470_B0r_fields,
  39436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39437         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39438         10,
  39439         -1,
  39440     },
  39441 #endif /* chips */
  39442 
  39443 #if defined(BCM_88675_A0)
  39444     { /* SOC_REG_INT_GRMTUE_BCM88675_A0r */
  39445         soc_block_list[2],
  39446         soc_portreg,
  39447         1,
  39448         0,
  39449         0xa00,
  39450         SOC_REG_FLAG_COUNTER,
  39451         0,
  39452         1,
  39453         soc_GRMTUEr_fields,
  39454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39455         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39456         10,
  39457         -1,
  39458     },
  39459 #endif /* chips */
  39460 
  39461 #if defined(BCM_88675_B0)
  39462     { /* SOC_REG_INT_GRMTUE_BCM88675_B0r */
  39463         soc_block_list[2],
  39464         soc_portreg,
  39465         1,
  39466         0,
  39467         0xa00,
  39468         SOC_REG_FLAG_COUNTER,
  39469         0,
  39470         1,
  39471         soc_GRMTUE_BCM88675_B0r_fields,
  39472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39473         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39474         10,
  39475         -1,
  39476     },
  39477 #endif /* chips */
  39478 
  39479 #if defined(BCM_88680_A0)
  39480     { /* SOC_REG_INT_GRMTUE_BCM88680_A0r */
  39481         soc_block_list[2],
  39482         soc_portreg,
  39483         1,
  39484         0,
  39485         0xa00,
  39486         SOC_REG_FLAG_COUNTER,
  39487         0,
  39488         1,
  39489         soc_GRMTUE_BCM88680_A0r_fields,
  39490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39491         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39492         10,
  39493         -1,
  39494     },
  39495 #endif /* chips */
  39496 
  39497 #if defined(BCM_53570_A0)
  39498     { /* SOC_REG_INT_GRNFFPr */
  39499         soc_block_list[2],
  39500         soc_portreg,
  39501         1,
  39502         0,
  39503         0x7f00,
  39504         SOC_REG_FLAG_COUNTER,
  39505         0,
  39506         1,
  39507         soc_GR1023_BCM53400_A0r_fields,
  39508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39509         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39510         281,
  39511         -1,
  39512     },
  39513 #endif /* chips */
  39514 
  39515 #if defined(BCM_53570_B0)
  39516     { /* SOC_REG_INT_GRNFFP_BCM53570_B0r */
  39517         soc_block_list[2],
  39518         soc_portreg,
  39519         1,
  39520         0,
  39521         0x7f00,
  39522         SOC_REG_FLAG_COUNTER,
  39523         0,
  39524         1,
  39525         soc_GR1023_BCM53400_A0r_fields,
  39526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39527         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39528         285,
  39529         -1,
  39530     },
  39531 #endif /* chips */
  39532 
  39533 #if defined(BCM_53570_A0)
  39534     { /* SOC_REG_INT_GRNFSEPr */
  39535         soc_block_list[2],
  39536         soc_portreg,
  39537         1,
  39538         0,
  39539         0x8300,
  39540         SOC_REG_FLAG_COUNTER,
  39541         0,
  39542         1,
  39543         soc_GR1023_BCM53400_A0r_fields,
  39544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39545         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39546         285,
  39547         -1,
  39548     },
  39549 #endif /* chips */
  39550 
  39551 #if defined(BCM_53570_B0)
  39552     { /* SOC_REG_INT_GRNFSEP_BCM53570_B0r */
  39553         soc_block_list[2],
  39554         soc_portreg,
  39555         1,
  39556         0,
  39557         0x8300,
  39558         SOC_REG_FLAG_COUNTER,
  39559         0,
  39560         1,
  39561         soc_GR1023_BCM53400_A0r_fields,
  39562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39564         289,
  39565         -1,
  39566     },
  39567 #endif /* chips */
  39568 
  39569 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  39570     defined(BCM_56504_B0)
  39571     { /* SOC_REG_INT_GROVRr */
  39572         soc_block_list[2],
  39573         soc_portreg,
  39574         1,
  39575         0,
  39576         0x16,
  39577         SOC_REG_FLAG_COUNTER |
  39578                           SOC_REG_FLAG_ED_CNTR,
  39579         0,
  39580         1,
  39581         soc_GR1023r_fields,
  39582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39584         56,
  39585         -1,
  39586     },
  39587 #endif /* chips */
  39588 
  39589 #if defined(BCM_53570_A0)
  39590     { /* SOC_REG_INT_GROVRPr */
  39591         soc_block_list[2],
  39592         soc_portreg,
  39593         1,
  39594         0,
  39595         0x6700,
  39596         SOC_REG_FLAG_COUNTER,
  39597         0,
  39598         1,
  39599         soc_GR1023_BCM53400_A0r_fields,
  39600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39602         257,
  39603         -1,
  39604     },
  39605 #endif /* chips */
  39606 
  39607 #if defined(BCM_53570_B0)
  39608     { /* SOC_REG_INT_GROVRP_BCM53570_B0r */
  39609         soc_block_list[2],
  39610         soc_portreg,
  39611         1,
  39612         0,
  39613         0x6700,
  39614         SOC_REG_FLAG_COUNTER,
  39615         0,
  39616         1,
  39617         soc_GR1023_BCM53400_A0r_fields,
  39618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39619         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39620         261,
  39621         -1,
  39622     },
  39623 #endif /* chips */
  39624 
  39625 #if defined(BCM_53400_A0)
  39626     { /* SOC_REG_INT_GROVR_BCM53400_A0r */
  39627         soc_block_list[9],
  39628         soc_portreg,
  39629         1,
  39630         0,
  39631         0x800,
  39632         SOC_REG_FLAG_COUNTER,
  39633         0,
  39634         1,
  39635         soc_GR1023_BCM53400_A0r_fields,
  39636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39637         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39638         107,
  39639         -1,
  39640     },
  39641 #endif /* chips */
  39642 
  39643 #if defined(BCM_53540_A0)
  39644     { /* SOC_REG_INT_GROVR_BCM53540_A0r */
  39645         soc_block_list[2],
  39646         soc_portreg,
  39647         1,
  39648         0,
  39649         0x800,
  39650         SOC_REG_FLAG_COUNTER,
  39651         0,
  39652         1,
  39653         soc_GR1023_BCM53400_A0r_fields,
  39654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39655         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39656         107,
  39657         -1,
  39658     },
  39659 #endif /* chips */
  39660 
  39661 #if defined(BCM_53570_A0)
  39662     { /* SOC_REG_INT_GROVR_BCM53570_A0r */
  39663         soc_block_list[2],
  39664         soc_portreg,
  39665         1,
  39666         0,
  39667         0x800,
  39668         SOC_REG_FLAG_COUNTER,
  39669         0,
  39670         1,
  39671         soc_GR1023_BCM53400_A0r_fields,
  39672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39673         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39674         162,
  39675         -1,
  39676     },
  39677 #endif /* chips */
  39678 
  39679 #if defined(BCM_53570_B0)
  39680     { /* SOC_REG_INT_GROVR_BCM53570_B0r */
  39681         soc_block_list[2],
  39682         soc_portreg,
  39683         1,
  39684         0,
  39685         0x800,
  39686         SOC_REG_FLAG_COUNTER,
  39687         0,
  39688         1,
  39689         soc_GR1023_BCM53400_A0r_fields,
  39690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39692         166,
  39693         -1,
  39694     },
  39695 #endif /* chips */
  39696 
  39697 #if defined(BCM_56142_A0)
  39698     { /* SOC_REG_INT_GROVR_BCM56142_A0r */
  39699         soc_block_list[210],
  39700         soc_portreg,
  39701         1,
  39702         0,
  39703         0x88,
  39704         SOC_REG_FLAG_COUNTER,
  39705         0,
  39706         1,
  39707         soc_GR1023r_fields,
  39708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39710         183,
  39711         -1,
  39712     },
  39713 #endif /* chips */
  39714 
  39715 #if defined(BCM_56150_A0)
  39716     { /* SOC_REG_INT_GROVR_BCM56150_A0r */
  39717         soc_block_list[2],
  39718         soc_portreg,
  39719         1,
  39720         0,
  39721         0x800,
  39722         SOC_REG_FLAG_COUNTER,
  39723         0,
  39724         1,
  39725         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  39726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39727         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39728         103,
  39729         -1,
  39730     },
  39731 #endif /* chips */
  39732 
  39733 #if defined(BCM_56160_A0)
  39734     { /* SOC_REG_INT_GROVR_BCM56160_A0r */
  39735         soc_block_list[2],
  39736         soc_portreg,
  39737         1,
  39738         0,
  39739         0x800,
  39740         SOC_REG_FLAG_COUNTER,
  39741         0,
  39742         1,
  39743         soc_GR1023_BCM53400_A0r_fields,
  39744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39745         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39746         107,
  39747         -1,
  39748     },
  39749 #endif /* chips */
  39750 
  39751 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  39752     { /* SOC_REG_INT_GROVR_BCM56334_A0r */
  39753         soc_block_list[210],
  39754         soc_portreg,
  39755         1,
  39756         0,
  39757         0x88,
  39758         SOC_REG_FLAG_COUNTER,
  39759         0,
  39760         1,
  39761         soc_GR1023r_fields,
  39762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39764         178,
  39765         -1,
  39766     },
  39767 #endif /* chips */
  39768 
  39769 #if defined(BCM_56370_A0)
  39770     { /* SOC_REG_INT_GROVR_BCM56370_A0r */
  39771         soc_block_list[9],
  39772         soc_portreg,
  39773         1,
  39774         0,
  39775         0x800,
  39776         SOC_REG_FLAG_COUNTER,
  39777         0,
  39778         1,
  39779         soc_GR1023_BCM53400_A0r_fields,
  39780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39782         68,
  39783         -1,
  39784         3,
  39785     },
  39786 #endif /* chips */
  39787 
  39788 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  39789     { /* SOC_REG_INT_GROVR_BCM56440_A0r */
  39790         soc_block_list[2],
  39791         soc_portreg,
  39792         1,
  39793         0,
  39794         0x88,
  39795         SOC_REG_FLAG_COUNTER,
  39796         0,
  39797         1,
  39798         soc_GR1023r_fields,
  39799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39801         175,
  39802         -1,
  39803     },
  39804 #endif /* chips */
  39805 
  39806 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  39807     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  39808     defined(BCM_56514_A0)
  39809     { /* SOC_REG_INT_GROVR_BCM56514_A0r */
  39810         soc_block_list[2],
  39811         soc_portreg,
  39812         1,
  39813         0,
  39814         0x16,
  39815         SOC_REG_FLAG_COUNTER,
  39816         0,
  39817         1,
  39818         soc_GR1023r_fields,
  39819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39820         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39821         56,
  39822         -1,
  39823     },
  39824 #endif /* chips */
  39825 
  39826 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  39827     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  39828     { /* SOC_REG_INT_GROVR_BCM56624_A0r */
  39829         soc_block_list[205],
  39830         soc_portreg,
  39831         1,
  39832         0,
  39833         0x96,
  39834         SOC_REG_FLAG_COUNTER,
  39835         0,
  39836         1,
  39837         soc_GR1023r_fields,
  39838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39840         192,
  39841         -1,
  39842     },
  39843 #endif /* chips */
  39844 
  39845 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  39846     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  39847     { /* SOC_REG_INT_GROVR_BCM56634_A0r */
  39848         soc_block_list[207],
  39849         soc_portreg,
  39850         1,
  39851         0,
  39852         0x96,
  39853         SOC_REG_FLAG_COUNTER,
  39854         0,
  39855         1,
  39856         soc_GR1023r_fields,
  39857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39858         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39859         192,
  39860         -1,
  39861     },
  39862 #endif /* chips */
  39863 
  39864 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  39865     { /* SOC_REG_INT_GROVR_BCM56685_A0r */
  39866         soc_block_list[209],
  39867         soc_portreg,
  39868         1,
  39869         0,
  39870         0x96,
  39871         SOC_REG_FLAG_COUNTER,
  39872         0,
  39873         1,
  39874         soc_GR1023r_fields,
  39875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39877         192,
  39878         -1,
  39879     },
  39880 #endif /* chips */
  39881 
  39882 #if defined(BCM_56800_A0)
  39883     { /* SOC_REG_INT_GROVR_BCM56800_A0r */
  39884         soc_block_list[9],
  39885         soc_portreg,
  39886         1,
  39887         0,
  39888         0x5d,
  39889         SOC_REG_FLAG_COUNTER,
  39890         0,
  39891         1,
  39892         soc_GR1023r_fields,
  39893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39894         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39895         135,
  39896         -1,
  39897     },
  39898 #endif /* chips */
  39899 
  39900 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  39901     { /* SOC_REG_INT_GROVR_BCM56820_A0r */
  39902         soc_block_list[206],
  39903         soc_portreg,
  39904         1,
  39905         0,
  39906         0x96,
  39907         SOC_REG_FLAG_COUNTER,
  39908         0,
  39909         1,
  39910         soc_GR1023r_fields,
  39911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39912         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39913         202,
  39914         -1,
  39915     },
  39916 #endif /* chips */
  39917 
  39918 #if defined(BCM_88375_A0)
  39919     { /* SOC_REG_INT_GROVR_BCM88375_A0r */
  39920         soc_block_list[2],
  39921         soc_portreg,
  39922         1,
  39923         0,
  39924         0x800,
  39925         SOC_REG_FLAG_COUNTER,
  39926         0,
  39927         1,
  39928         soc_GROVR_BCM88375_A0r_fields,
  39929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39930         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39931         8,
  39932         -1,
  39933     },
  39934 #endif /* chips */
  39935 
  39936 #if defined(BCM_88375_B0)
  39937     { /* SOC_REG_INT_GROVR_BCM88375_B0r */
  39938         soc_block_list[2],
  39939         soc_portreg,
  39940         1,
  39941         0,
  39942         0x800,
  39943         SOC_REG_FLAG_COUNTER,
  39944         0,
  39945         1,
  39946         soc_GROVR_BCM88375_B0r_fields,
  39947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39948         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39949         8,
  39950         -1,
  39951     },
  39952 #endif /* chips */
  39953 
  39954 #if defined(BCM_88470_A0)
  39955     { /* SOC_REG_INT_GROVR_BCM88470_A0r */
  39956         soc_block_list[2],
  39957         soc_portreg,
  39958         1,
  39959         0,
  39960         0x800,
  39961         SOC_REG_FLAG_COUNTER,
  39962         0,
  39963         1,
  39964         soc_GROVR_BCM88470_A0r_fields,
  39965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39966         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39967         8,
  39968         -1,
  39969     },
  39970 #endif /* chips */
  39971 
  39972 #if defined(BCM_88470_B0)
  39973     { /* SOC_REG_INT_GROVR_BCM88470_B0r */
  39974         soc_block_list[2],
  39975         soc_portreg,
  39976         1,
  39977         0,
  39978         0x800,
  39979         SOC_REG_FLAG_COUNTER,
  39980         0,
  39981         1,
  39982         soc_GROVR_BCM88470_B0r_fields,
  39983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39984         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39985         8,
  39986         -1,
  39987     },
  39988 #endif /* chips */
  39989 
  39990 #if defined(BCM_88675_A0)
  39991     { /* SOC_REG_INT_GROVR_BCM88675_A0r */
  39992         soc_block_list[2],
  39993         soc_portreg,
  39994         1,
  39995         0,
  39996         0x800,
  39997         SOC_REG_FLAG_COUNTER,
  39998         0,
  39999         1,
  40000         soc_GROVRr_fields,
  40001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40002         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40003         8,
  40004         -1,
  40005     },
  40006 #endif /* chips */
  40007 
  40008 #if defined(BCM_88675_B0)
  40009     { /* SOC_REG_INT_GROVR_BCM88675_B0r */
  40010         soc_block_list[2],
  40011         soc_portreg,
  40012         1,
  40013         0,
  40014         0x800,
  40015         SOC_REG_FLAG_COUNTER,
  40016         0,
  40017         1,
  40018         soc_GROVR_BCM88675_B0r_fields,
  40019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40020         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40021         8,
  40022         -1,
  40023     },
  40024 #endif /* chips */
  40025 
  40026 #if defined(BCM_88680_A0)
  40027     { /* SOC_REG_INT_GROVR_BCM88680_A0r */
  40028         soc_block_list[2],
  40029         soc_portreg,
  40030         1,
  40031         0,
  40032         0x800,
  40033         SOC_REG_FLAG_COUNTER,
  40034         0,
  40035         1,
  40036         soc_GROVR_BCM88680_A0r_fields,
  40037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40038         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40039         8,
  40040         -1,
  40041     },
  40042 #endif /* chips */
  40043 
  40044 #if defined(BCM_56370_A0)
  40045     { /* SOC_REG_INT_GRPFCr */
  40046         soc_block_list[9],
  40047         soc_portreg,
  40048         1,
  40049         0,
  40050         0x1f00,
  40051         SOC_REG_FLAG_COUNTER,
  40052         0,
  40053         1,
  40054         soc_GR1023_BCM53400_A0r_fields,
  40055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40056         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40057         91,
  40058         -1,
  40059         3,
  40060     },
  40061 #endif /* chips */
  40062 
  40063 #if defined(BCM_56160_A0)
  40064     { /* SOC_REG_INT_GRPFC0r */
  40065         soc_block_list[2],
  40066         soc_portreg,
  40067         1,
  40068         0,
  40069         0x2800,
  40070         SOC_REG_FLAG_COUNTER,
  40071         0,
  40072         1,
  40073         soc_GR1023_BCM53400_A0r_fields,
  40074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40075         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40076         139,
  40077         -1,
  40078     },
  40079 #endif /* chips */
  40080 
  40081 #if defined(BCM_56160_A0)
  40082     { /* SOC_REG_INT_GRPFC1r */
  40083         soc_block_list[2],
  40084         soc_portreg,
  40085         1,
  40086         0,
  40087         0x2900,
  40088         SOC_REG_FLAG_COUNTER,
  40089         0,
  40090         1,
  40091         soc_GR1023_BCM53400_A0r_fields,
  40092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40093         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40094         140,
  40095         -1,
  40096     },
  40097 #endif /* chips */
  40098 
  40099 #if defined(BCM_56160_A0)
  40100     { /* SOC_REG_INT_GRPFC2r */
  40101         soc_block_list[2],
  40102         soc_portreg,
  40103         1,
  40104         0,
  40105         0x2a00,
  40106         SOC_REG_FLAG_COUNTER,
  40107         0,
  40108         1,
  40109         soc_GR1023_BCM53400_A0r_fields,
  40110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40112         141,
  40113         -1,
  40114     },
  40115 #endif /* chips */
  40116 
  40117 #if defined(BCM_56160_A0)
  40118     { /* SOC_REG_INT_GRPFC3r */
  40119         soc_block_list[2],
  40120         soc_portreg,
  40121         1,
  40122         0,
  40123         0x2b00,
  40124         SOC_REG_FLAG_COUNTER,
  40125         0,
  40126         1,
  40127         soc_GR1023_BCM53400_A0r_fields,
  40128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40129         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40130         142,
  40131         -1,
  40132     },
  40133 #endif /* chips */
  40134 
  40135 #if defined(BCM_56160_A0)
  40136     { /* SOC_REG_INT_GRPFC4r */
  40137         soc_block_list[2],
  40138         soc_portreg,
  40139         1,
  40140         0,
  40141         0x2c00,
  40142         SOC_REG_FLAG_COUNTER,
  40143         0,
  40144         1,
  40145         soc_GR1023_BCM53400_A0r_fields,
  40146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40148         143,
  40149         -1,
  40150     },
  40151 #endif /* chips */
  40152 
  40153 #if defined(BCM_56160_A0)
  40154     { /* SOC_REG_INT_GRPFC5r */
  40155         soc_block_list[2],
  40156         soc_portreg,
  40157         1,
  40158         0,
  40159         0x2d00,
  40160         SOC_REG_FLAG_COUNTER,
  40161         0,
  40162         1,
  40163         soc_GR1023_BCM53400_A0r_fields,
  40164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40165         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40166         144,
  40167         -1,
  40168     },
  40169 #endif /* chips */
  40170 
  40171 #if defined(BCM_56160_A0)
  40172     { /* SOC_REG_INT_GRPFC6r */
  40173         soc_block_list[2],
  40174         soc_portreg,
  40175         1,
  40176         0,
  40177         0x2e00,
  40178         SOC_REG_FLAG_COUNTER,
  40179         0,
  40180         1,
  40181         soc_GR1023_BCM53400_A0r_fields,
  40182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40183         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40184         145,
  40185         -1,
  40186     },
  40187 #endif /* chips */
  40188 
  40189 #if defined(BCM_56160_A0)
  40190     { /* SOC_REG_INT_GRPFC7r */
  40191         soc_block_list[2],
  40192         soc_portreg,
  40193         1,
  40194         0,
  40195         0x2f00,
  40196         SOC_REG_FLAG_COUNTER,
  40197         0,
  40198         1,
  40199         soc_GR1023_BCM53400_A0r_fields,
  40200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40201         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40202         146,
  40203         -1,
  40204     },
  40205 #endif /* chips */
  40206 
  40207 #if defined(BCM_53540_A0)
  40208     { /* SOC_REG_INT_GRPFC0_BCM53540_A0r */
  40209         soc_block_list[2],
  40210         soc_portreg,
  40211         1,
  40212         0,
  40213         0x2800,
  40214         SOC_REG_FLAG_COUNTER,
  40215         0,
  40216         1,
  40217         soc_GR1023_BCM53400_A0r_fields,
  40218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40219         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40220         139,
  40221         -1,
  40222     },
  40223 #endif /* chips */
  40224 
  40225 #if defined(BCM_53570_A0)
  40226     { /* SOC_REG_INT_GRPFC0_BCM53570_A0r */
  40227         soc_block_list[2],
  40228         soc_portreg,
  40229         1,
  40230         0,
  40231         0x2800,
  40232         SOC_REG_FLAG_COUNTER,
  40233         0,
  40234         1,
  40235         soc_GR1023_BCM53400_A0r_fields,
  40236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40237         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40238         194,
  40239         -1,
  40240     },
  40241 #endif /* chips */
  40242 
  40243 #if defined(BCM_53570_B0)
  40244     { /* SOC_REG_INT_GRPFC0_BCM53570_B0r */
  40245         soc_block_list[2],
  40246         soc_portreg,
  40247         1,
  40248         0,
  40249         0x2800,
  40250         SOC_REG_FLAG_COUNTER,
  40251         0,
  40252         1,
  40253         soc_GR1023_BCM53400_A0r_fields,
  40254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40255         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40256         198,
  40257         -1,
  40258     },
  40259 #endif /* chips */
  40260 
  40261 #if defined(BCM_53540_A0)
  40262     { /* SOC_REG_INT_GRPFC1_BCM53540_A0r */
  40263         soc_block_list[2],
  40264         soc_portreg,
  40265         1,
  40266         0,
  40267         0x2900,
  40268         SOC_REG_FLAG_COUNTER,
  40269         0,
  40270         1,
  40271         soc_GR1023_BCM53400_A0r_fields,
  40272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40273         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40274         140,
  40275         -1,
  40276     },
  40277 #endif /* chips */
  40278 
  40279 #if defined(BCM_53570_A0)
  40280     { /* SOC_REG_INT_GRPFC1_BCM53570_A0r */
  40281         soc_block_list[2],
  40282         soc_portreg,
  40283         1,
  40284         0,
  40285         0x2900,
  40286         SOC_REG_FLAG_COUNTER,
  40287         0,
  40288         1,
  40289         soc_GR1023_BCM53400_A0r_fields,
  40290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40291         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40292         195,
  40293         -1,
  40294     },
  40295 #endif /* chips */
  40296 
  40297 #if defined(BCM_53570_B0)
  40298     { /* SOC_REG_INT_GRPFC1_BCM53570_B0r */
  40299         soc_block_list[2],
  40300         soc_portreg,
  40301         1,
  40302         0,
  40303         0x2900,
  40304         SOC_REG_FLAG_COUNTER,
  40305         0,
  40306         1,
  40307         soc_GR1023_BCM53400_A0r_fields,
  40308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40309         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40310         199,
  40311         -1,
  40312     },
  40313 #endif /* chips */
  40314 
  40315 #if defined(BCM_53540_A0)
  40316     { /* SOC_REG_INT_GRPFC2_BCM53540_A0r */
  40317         soc_block_list[2],
  40318         soc_portreg,
  40319         1,
  40320         0,
  40321         0x2a00,
  40322         SOC_REG_FLAG_COUNTER,
  40323         0,
  40324         1,
  40325         soc_GR1023_BCM53400_A0r_fields,
  40326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40328         141,
  40329         -1,
  40330     },
  40331 #endif /* chips */
  40332 
  40333 #if defined(BCM_53570_A0)
  40334     { /* SOC_REG_INT_GRPFC2_BCM53570_A0r */
  40335         soc_block_list[2],
  40336         soc_portreg,
  40337         1,
  40338         0,
  40339         0x2a00,
  40340         SOC_REG_FLAG_COUNTER,
  40341         0,
  40342         1,
  40343         soc_GR1023_BCM53400_A0r_fields,
  40344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40346         196,
  40347         -1,
  40348     },
  40349 #endif /* chips */
  40350 
  40351 #if defined(BCM_53570_B0)
  40352     { /* SOC_REG_INT_GRPFC2_BCM53570_B0r */
  40353         soc_block_list[2],
  40354         soc_portreg,
  40355         1,
  40356         0,
  40357         0x2a00,
  40358         SOC_REG_FLAG_COUNTER,
  40359         0,
  40360         1,
  40361         soc_GR1023_BCM53400_A0r_fields,
  40362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40364         200,
  40365         -1,
  40366     },
  40367 #endif /* chips */
  40368 
  40369 #if defined(BCM_53540_A0)
  40370     { /* SOC_REG_INT_GRPFC3_BCM53540_A0r */
  40371         soc_block_list[2],
  40372         soc_portreg,
  40373         1,
  40374         0,
  40375         0x2b00,
  40376         SOC_REG_FLAG_COUNTER,
  40377         0,
  40378         1,
  40379         soc_GR1023_BCM53400_A0r_fields,
  40380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40381         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40382         142,
  40383         -1,
  40384     },
  40385 #endif /* chips */
  40386 
  40387 #if defined(BCM_53570_A0)
  40388     { /* SOC_REG_INT_GRPFC3_BCM53570_A0r */
  40389         soc_block_list[2],
  40390         soc_portreg,
  40391         1,
  40392         0,
  40393         0x2b00,
  40394         SOC_REG_FLAG_COUNTER,
  40395         0,
  40396         1,
  40397         soc_GR1023_BCM53400_A0r_fields,
  40398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40399         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40400         197,
  40401         -1,
  40402     },
  40403 #endif /* chips */
  40404 
  40405 #if defined(BCM_53570_B0)
  40406     { /* SOC_REG_INT_GRPFC3_BCM53570_B0r */
  40407         soc_block_list[2],
  40408         soc_portreg,
  40409         1,
  40410         0,
  40411         0x2b00,
  40412         SOC_REG_FLAG_COUNTER,
  40413         0,
  40414         1,
  40415         soc_GR1023_BCM53400_A0r_fields,
  40416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40417         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40418         201,
  40419         -1,
  40420     },
  40421 #endif /* chips */
  40422 
  40423 #if defined(BCM_53540_A0)
  40424     { /* SOC_REG_INT_GRPFC4_BCM53540_A0r */
  40425         soc_block_list[2],
  40426         soc_portreg,
  40427         1,
  40428         0,
  40429         0x2c00,
  40430         SOC_REG_FLAG_COUNTER,
  40431         0,
  40432         1,
  40433         soc_GR1023_BCM53400_A0r_fields,
  40434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40435         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40436         143,
  40437         -1,
  40438     },
  40439 #endif /* chips */
  40440 
  40441 #if defined(BCM_53570_A0)
  40442     { /* SOC_REG_INT_GRPFC4_BCM53570_A0r */
  40443         soc_block_list[2],
  40444         soc_portreg,
  40445         1,
  40446         0,
  40447         0x2c00,
  40448         SOC_REG_FLAG_COUNTER,
  40449         0,
  40450         1,
  40451         soc_GR1023_BCM53400_A0r_fields,
  40452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40453         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40454         198,
  40455         -1,
  40456     },
  40457 #endif /* chips */
  40458 
  40459 #if defined(BCM_53570_B0)
  40460     { /* SOC_REG_INT_GRPFC4_BCM53570_B0r */
  40461         soc_block_list[2],
  40462         soc_portreg,
  40463         1,
  40464         0,
  40465         0x2c00,
  40466         SOC_REG_FLAG_COUNTER,
  40467         0,
  40468         1,
  40469         soc_GR1023_BCM53400_A0r_fields,
  40470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40472         202,
  40473         -1,
  40474     },
  40475 #endif /* chips */
  40476 
  40477 #if defined(BCM_53540_A0)
  40478     { /* SOC_REG_INT_GRPFC5_BCM53540_A0r */
  40479         soc_block_list[2],
  40480         soc_portreg,
  40481         1,
  40482         0,
  40483         0x2d00,
  40484         SOC_REG_FLAG_COUNTER,
  40485         0,
  40486         1,
  40487         soc_GR1023_BCM53400_A0r_fields,
  40488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40490         144,
  40491         -1,
  40492     },
  40493 #endif /* chips */
  40494 
  40495 #if defined(BCM_53570_A0)
  40496     { /* SOC_REG_INT_GRPFC5_BCM53570_A0r */
  40497         soc_block_list[2],
  40498         soc_portreg,
  40499         1,
  40500         0,
  40501         0x2d00,
  40502         SOC_REG_FLAG_COUNTER,
  40503         0,
  40504         1,
  40505         soc_GR1023_BCM53400_A0r_fields,
  40506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40508         199,
  40509         -1,
  40510     },
  40511 #endif /* chips */
  40512 
  40513 #if defined(BCM_53570_B0)
  40514     { /* SOC_REG_INT_GRPFC5_BCM53570_B0r */
  40515         soc_block_list[2],
  40516         soc_portreg,
  40517         1,
  40518         0,
  40519         0x2d00,
  40520         SOC_REG_FLAG_COUNTER,
  40521         0,
  40522         1,
  40523         soc_GR1023_BCM53400_A0r_fields,
  40524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40525         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40526         203,
  40527         -1,
  40528     },
  40529 #endif /* chips */
  40530 
  40531 #if defined(BCM_53540_A0)
  40532     { /* SOC_REG_INT_GRPFC6_BCM53540_A0r */
  40533         soc_block_list[2],
  40534         soc_portreg,
  40535         1,
  40536         0,
  40537         0x2e00,
  40538         SOC_REG_FLAG_COUNTER,
  40539         0,
  40540         1,
  40541         soc_GR1023_BCM53400_A0r_fields,
  40542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40544         145,
  40545         -1,
  40546     },
  40547 #endif /* chips */
  40548 
  40549 #if defined(BCM_53570_A0)
  40550     { /* SOC_REG_INT_GRPFC6_BCM53570_A0r */
  40551         soc_block_list[2],
  40552         soc_portreg,
  40553         1,
  40554         0,
  40555         0x2e00,
  40556         SOC_REG_FLAG_COUNTER,
  40557         0,
  40558         1,
  40559         soc_GR1023_BCM53400_A0r_fields,
  40560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40562         200,
  40563         -1,
  40564     },
  40565 #endif /* chips */
  40566 
  40567 #if defined(BCM_53570_B0)
  40568     { /* SOC_REG_INT_GRPFC6_BCM53570_B0r */
  40569         soc_block_list[2],
  40570         soc_portreg,
  40571         1,
  40572         0,
  40573         0x2e00,
  40574         SOC_REG_FLAG_COUNTER,
  40575         0,
  40576         1,
  40577         soc_GR1023_BCM53400_A0r_fields,
  40578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40580         204,
  40581         -1,
  40582     },
  40583 #endif /* chips */
  40584 
  40585 #if defined(BCM_53540_A0)
  40586     { /* SOC_REG_INT_GRPFC7_BCM53540_A0r */
  40587         soc_block_list[2],
  40588         soc_portreg,
  40589         1,
  40590         0,
  40591         0x2f00,
  40592         SOC_REG_FLAG_COUNTER,
  40593         0,
  40594         1,
  40595         soc_GR1023_BCM53400_A0r_fields,
  40596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40598         146,
  40599         -1,
  40600     },
  40601 #endif /* chips */
  40602 
  40603 #if defined(BCM_53570_A0)
  40604     { /* SOC_REG_INT_GRPFC7_BCM53570_A0r */
  40605         soc_block_list[2],
  40606         soc_portreg,
  40607         1,
  40608         0,
  40609         0x2f00,
  40610         SOC_REG_FLAG_COUNTER,
  40611         0,
  40612         1,
  40613         soc_GR1023_BCM53400_A0r_fields,
  40614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40616         201,
  40617         -1,
  40618     },
  40619 #endif /* chips */
  40620 
  40621 #if defined(BCM_53570_B0)
  40622     { /* SOC_REG_INT_GRPFC7_BCM53570_B0r */
  40623         soc_block_list[2],
  40624         soc_portreg,
  40625         1,
  40626         0,
  40627         0x2f00,
  40628         SOC_REG_FLAG_COUNTER,
  40629         0,
  40630         1,
  40631         soc_GR1023_BCM53400_A0r_fields,
  40632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40634         205,
  40635         -1,
  40636     },
  40637 #endif /* chips */
  40638 
  40639 #if defined(BCM_56160_A0)
  40640     { /* SOC_REG_INT_GRPFCOFF0r */
  40641         soc_block_list[2],
  40642         soc_portreg,
  40643         1,
  40644         0,
  40645         0x2000,
  40646         SOC_REG_FLAG_COUNTER,
  40647         0,
  40648         1,
  40649         soc_GR1023_BCM53400_A0r_fields,
  40650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40652         131,
  40653         -1,
  40654     },
  40655 #endif /* chips */
  40656 
  40657 #if defined(BCM_56160_A0)
  40658     { /* SOC_REG_INT_GRPFCOFF1r */
  40659         soc_block_list[2],
  40660         soc_portreg,
  40661         1,
  40662         0,
  40663         0x2100,
  40664         SOC_REG_FLAG_COUNTER,
  40665         0,
  40666         1,
  40667         soc_GR1023_BCM53400_A0r_fields,
  40668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40670         132,
  40671         -1,
  40672     },
  40673 #endif /* chips */
  40674 
  40675 #if defined(BCM_56160_A0)
  40676     { /* SOC_REG_INT_GRPFCOFF2r */
  40677         soc_block_list[2],
  40678         soc_portreg,
  40679         1,
  40680         0,
  40681         0x2200,
  40682         SOC_REG_FLAG_COUNTER,
  40683         0,
  40684         1,
  40685         soc_GR1023_BCM53400_A0r_fields,
  40686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40687         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40688         133,
  40689         -1,
  40690     },
  40691 #endif /* chips */
  40692 
  40693 #if defined(BCM_56160_A0)
  40694     { /* SOC_REG_INT_GRPFCOFF3r */
  40695         soc_block_list[2],
  40696         soc_portreg,
  40697         1,
  40698         0,
  40699         0x2300,
  40700         SOC_REG_FLAG_COUNTER,
  40701         0,
  40702         1,
  40703         soc_GR1023_BCM53400_A0r_fields,
  40704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40706         134,
  40707         -1,
  40708     },
  40709 #endif /* chips */
  40710 
  40711 #if defined(BCM_56160_A0)
  40712     { /* SOC_REG_INT_GRPFCOFF4r */
  40713         soc_block_list[2],
  40714         soc_portreg,
  40715         1,
  40716         0,
  40717         0x2400,
  40718         SOC_REG_FLAG_COUNTER,
  40719         0,
  40720         1,
  40721         soc_GR1023_BCM53400_A0r_fields,
  40722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40724         135,
  40725         -1,
  40726     },
  40727 #endif /* chips */
  40728 
  40729 #if defined(BCM_56160_A0)
  40730     { /* SOC_REG_INT_GRPFCOFF5r */
  40731         soc_block_list[2],
  40732         soc_portreg,
  40733         1,
  40734         0,
  40735         0x2500,
  40736         SOC_REG_FLAG_COUNTER,
  40737         0,
  40738         1,
  40739         soc_GR1023_BCM53400_A0r_fields,
  40740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40742         136,
  40743         -1,
  40744     },
  40745 #endif /* chips */
  40746 
  40747 #if defined(BCM_56160_A0)
  40748     { /* SOC_REG_INT_GRPFCOFF6r */
  40749         soc_block_list[2],
  40750         soc_portreg,
  40751         1,
  40752         0,
  40753         0x2600,
  40754         SOC_REG_FLAG_COUNTER,
  40755         0,
  40756         1,
  40757         soc_GR1023_BCM53400_A0r_fields,
  40758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40760         137,
  40761         -1,
  40762     },
  40763 #endif /* chips */
  40764 
  40765 #if defined(BCM_56160_A0)
  40766     { /* SOC_REG_INT_GRPFCOFF7r */
  40767         soc_block_list[2],
  40768         soc_portreg,
  40769         1,
  40770         0,
  40771         0x2700,
  40772         SOC_REG_FLAG_COUNTER,
  40773         0,
  40774         1,
  40775         soc_GR1023_BCM53400_A0r_fields,
  40776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40778         138,
  40779         -1,
  40780     },
  40781 #endif /* chips */
  40782 
  40783 #if defined(BCM_53540_A0)
  40784     { /* SOC_REG_INT_GRPFCOFF0_BCM53540_A0r */
  40785         soc_block_list[2],
  40786         soc_portreg,
  40787         1,
  40788         0,
  40789         0x2000,
  40790         SOC_REG_FLAG_COUNTER,
  40791         0,
  40792         1,
  40793         soc_GR1023_BCM53400_A0r_fields,
  40794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40796         131,
  40797         -1,
  40798     },
  40799 #endif /* chips */
  40800 
  40801 #if defined(BCM_53570_A0)
  40802     { /* SOC_REG_INT_GRPFCOFF0_BCM53570_A0r */
  40803         soc_block_list[2],
  40804         soc_portreg,
  40805         1,
  40806         0,
  40807         0x2000,
  40808         SOC_REG_FLAG_COUNTER,
  40809         0,
  40810         1,
  40811         soc_GR1023_BCM53400_A0r_fields,
  40812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40814         186,
  40815         -1,
  40816     },
  40817 #endif /* chips */
  40818 
  40819 #if defined(BCM_53570_B0)
  40820     { /* SOC_REG_INT_GRPFCOFF0_BCM53570_B0r */
  40821         soc_block_list[2],
  40822         soc_portreg,
  40823         1,
  40824         0,
  40825         0x2000,
  40826         SOC_REG_FLAG_COUNTER,
  40827         0,
  40828         1,
  40829         soc_GR1023_BCM53400_A0r_fields,
  40830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40832         190,
  40833         -1,
  40834     },
  40835 #endif /* chips */
  40836 
  40837 #if defined(BCM_53540_A0)
  40838     { /* SOC_REG_INT_GRPFCOFF1_BCM53540_A0r */
  40839         soc_block_list[2],
  40840         soc_portreg,
  40841         1,
  40842         0,
  40843         0x2100,
  40844         SOC_REG_FLAG_COUNTER,
  40845         0,
  40846         1,
  40847         soc_GR1023_BCM53400_A0r_fields,
  40848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40850         132,
  40851         -1,
  40852     },
  40853 #endif /* chips */
  40854 
  40855 #if defined(BCM_53570_A0)
  40856     { /* SOC_REG_INT_GRPFCOFF1_BCM53570_A0r */
  40857         soc_block_list[2],
  40858         soc_portreg,
  40859         1,
  40860         0,
  40861         0x2100,
  40862         SOC_REG_FLAG_COUNTER,
  40863         0,
  40864         1,
  40865         soc_GR1023_BCM53400_A0r_fields,
  40866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40867         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40868         187,
  40869         -1,
  40870     },
  40871 #endif /* chips */
  40872 
  40873 #if defined(BCM_53570_B0)
  40874     { /* SOC_REG_INT_GRPFCOFF1_BCM53570_B0r */
  40875         soc_block_list[2],
  40876         soc_portreg,
  40877         1,
  40878         0,
  40879         0x2100,
  40880         SOC_REG_FLAG_COUNTER,
  40881         0,
  40882         1,
  40883         soc_GR1023_BCM53400_A0r_fields,
  40884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40886         191,
  40887         -1,
  40888     },
  40889 #endif /* chips */
  40890 
  40891 #if defined(BCM_53540_A0)
  40892     { /* SOC_REG_INT_GRPFCOFF2_BCM53540_A0r */
  40893         soc_block_list[2],
  40894         soc_portreg,
  40895         1,
  40896         0,
  40897         0x2200,
  40898         SOC_REG_FLAG_COUNTER,
  40899         0,
  40900         1,
  40901         soc_GR1023_BCM53400_A0r_fields,
  40902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40904         133,
  40905         -1,
  40906     },
  40907 #endif /* chips */
  40908 
  40909 #if defined(BCM_53570_A0)
  40910     { /* SOC_REG_INT_GRPFCOFF2_BCM53570_A0r */
  40911         soc_block_list[2],
  40912         soc_portreg,
  40913         1,
  40914         0,
  40915         0x2200,
  40916         SOC_REG_FLAG_COUNTER,
  40917         0,
  40918         1,
  40919         soc_GR1023_BCM53400_A0r_fields,
  40920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40922         188,
  40923         -1,
  40924     },
  40925 #endif /* chips */
  40926 
  40927 #if defined(BCM_53570_B0)
  40928     { /* SOC_REG_INT_GRPFCOFF2_BCM53570_B0r */
  40929         soc_block_list[2],
  40930         soc_portreg,
  40931         1,
  40932         0,
  40933         0x2200,
  40934         SOC_REG_FLAG_COUNTER,
  40935         0,
  40936         1,
  40937         soc_GR1023_BCM53400_A0r_fields,
  40938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40940         192,
  40941         -1,
  40942     },
  40943 #endif /* chips */
  40944 
  40945 #if defined(BCM_53540_A0)
  40946     { /* SOC_REG_INT_GRPFCOFF3_BCM53540_A0r */
  40947         soc_block_list[2],
  40948         soc_portreg,
  40949         1,
  40950         0,
  40951         0x2300,
  40952         SOC_REG_FLAG_COUNTER,
  40953         0,
  40954         1,
  40955         soc_GR1023_BCM53400_A0r_fields,
  40956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40958         134,
  40959         -1,
  40960     },
  40961 #endif /* chips */
  40962 
  40963 #if defined(BCM_53570_A0)
  40964     { /* SOC_REG_INT_GRPFCOFF3_BCM53570_A0r */
  40965         soc_block_list[2],
  40966         soc_portreg,
  40967         1,
  40968         0,
  40969         0x2300,
  40970         SOC_REG_FLAG_COUNTER,
  40971         0,
  40972         1,
  40973         soc_GR1023_BCM53400_A0r_fields,
  40974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40976         189,
  40977         -1,
  40978     },
  40979 #endif /* chips */
  40980 
  40981 #if defined(BCM_53570_B0)
  40982     { /* SOC_REG_INT_GRPFCOFF3_BCM53570_B0r */
  40983         soc_block_list[2],
  40984         soc_portreg,
  40985         1,
  40986         0,
  40987         0x2300,
  40988         SOC_REG_FLAG_COUNTER,
  40989         0,
  40990         1,
  40991         soc_GR1023_BCM53400_A0r_fields,
  40992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40994         193,
  40995         -1,
  40996     },
  40997 #endif /* chips */
  40998 
  40999 #if defined(BCM_53540_A0)
  41000     { /* SOC_REG_INT_GRPFCOFF4_BCM53540_A0r */
  41001         soc_block_list[2],
  41002         soc_portreg,
  41003         1,
  41004         0,
  41005         0x2400,
  41006         SOC_REG_FLAG_COUNTER,
  41007         0,
  41008         1,
  41009         soc_GR1023_BCM53400_A0r_fields,
  41010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41012         135,
  41013         -1,
  41014     },
  41015 #endif /* chips */
  41016 
  41017 #if defined(BCM_53570_A0)
  41018     { /* SOC_REG_INT_GRPFCOFF4_BCM53570_A0r */
  41019         soc_block_list[2],
  41020         soc_portreg,
  41021         1,
  41022         0,
  41023         0x2400,
  41024         SOC_REG_FLAG_COUNTER,
  41025         0,
  41026         1,
  41027         soc_GR1023_BCM53400_A0r_fields,
  41028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41030         190,
  41031         -1,
  41032     },
  41033 #endif /* chips */
  41034 
  41035 #if defined(BCM_53570_B0)
  41036     { /* SOC_REG_INT_GRPFCOFF4_BCM53570_B0r */
  41037         soc_block_list[2],
  41038         soc_portreg,
  41039         1,
  41040         0,
  41041         0x2400,
  41042         SOC_REG_FLAG_COUNTER,
  41043         0,
  41044         1,
  41045         soc_GR1023_BCM53400_A0r_fields,
  41046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41048         194,
  41049         -1,
  41050     },
  41051 #endif /* chips */
  41052 
  41053 #if defined(BCM_53540_A0)
  41054     { /* SOC_REG_INT_GRPFCOFF5_BCM53540_A0r */
  41055         soc_block_list[2],
  41056         soc_portreg,
  41057         1,
  41058         0,
  41059         0x2500,
  41060         SOC_REG_FLAG_COUNTER,
  41061         0,
  41062         1,
  41063         soc_GR1023_BCM53400_A0r_fields,
  41064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41065         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41066         136,
  41067         -1,
  41068     },
  41069 #endif /* chips */
  41070 
  41071 #if defined(BCM_53570_A0)
  41072     { /* SOC_REG_INT_GRPFCOFF5_BCM53570_A0r */
  41073         soc_block_list[2],
  41074         soc_portreg,
  41075         1,
  41076         0,
  41077         0x2500,
  41078         SOC_REG_FLAG_COUNTER,
  41079         0,
  41080         1,
  41081         soc_GR1023_BCM53400_A0r_fields,
  41082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41084         191,
  41085         -1,
  41086     },
  41087 #endif /* chips */
  41088 
  41089 #if defined(BCM_53570_B0)
  41090     { /* SOC_REG_INT_GRPFCOFF5_BCM53570_B0r */
  41091         soc_block_list[2],
  41092         soc_portreg,
  41093         1,
  41094         0,
  41095         0x2500,
  41096         SOC_REG_FLAG_COUNTER,
  41097         0,
  41098         1,
  41099         soc_GR1023_BCM53400_A0r_fields,
  41100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41101         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41102         195,
  41103         -1,
  41104     },
  41105 #endif /* chips */
  41106 
  41107 #if defined(BCM_53540_A0)
  41108     { /* SOC_REG_INT_GRPFCOFF6_BCM53540_A0r */
  41109         soc_block_list[2],
  41110         soc_portreg,
  41111         1,
  41112         0,
  41113         0x2600,
  41114         SOC_REG_FLAG_COUNTER,
  41115         0,
  41116         1,
  41117         soc_GR1023_BCM53400_A0r_fields,
  41118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41119         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41120         137,
  41121         -1,
  41122     },
  41123 #endif /* chips */
  41124 
  41125 #if defined(BCM_53570_A0)
  41126     { /* SOC_REG_INT_GRPFCOFF6_BCM53570_A0r */
  41127         soc_block_list[2],
  41128         soc_portreg,
  41129         1,
  41130         0,
  41131         0x2600,
  41132         SOC_REG_FLAG_COUNTER,
  41133         0,
  41134         1,
  41135         soc_GR1023_BCM53400_A0r_fields,
  41136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41137         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41138         192,
  41139         -1,
  41140     },
  41141 #endif /* chips */
  41142 
  41143 #if defined(BCM_53570_B0)
  41144     { /* SOC_REG_INT_GRPFCOFF6_BCM53570_B0r */
  41145         soc_block_list[2],
  41146         soc_portreg,
  41147         1,
  41148         0,
  41149         0x2600,
  41150         SOC_REG_FLAG_COUNTER,
  41151         0,
  41152         1,
  41153         soc_GR1023_BCM53400_A0r_fields,
  41154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41155         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41156         196,
  41157         -1,
  41158     },
  41159 #endif /* chips */
  41160 
  41161 #if defined(BCM_53540_A0)
  41162     { /* SOC_REG_INT_GRPFCOFF7_BCM53540_A0r */
  41163         soc_block_list[2],
  41164         soc_portreg,
  41165         1,
  41166         0,
  41167         0x2700,
  41168         SOC_REG_FLAG_COUNTER,
  41169         0,
  41170         1,
  41171         soc_GR1023_BCM53400_A0r_fields,
  41172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41174         138,
  41175         -1,
  41176     },
  41177 #endif /* chips */
  41178 
  41179 #if defined(BCM_53570_A0)
  41180     { /* SOC_REG_INT_GRPFCOFF7_BCM53570_A0r */
  41181         soc_block_list[2],
  41182         soc_portreg,
  41183         1,
  41184         0,
  41185         0x2700,
  41186         SOC_REG_FLAG_COUNTER,
  41187         0,
  41188         1,
  41189         soc_GR1023_BCM53400_A0r_fields,
  41190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41192         193,
  41193         -1,
  41194     },
  41195 #endif /* chips */
  41196 
  41197 #if defined(BCM_53570_B0)
  41198     { /* SOC_REG_INT_GRPFCOFF7_BCM53570_B0r */
  41199         soc_block_list[2],
  41200         soc_portreg,
  41201         1,
  41202         0,
  41203         0x2700,
  41204         SOC_REG_FLAG_COUNTER,
  41205         0,
  41206         1,
  41207         soc_GR1023_BCM53400_A0r_fields,
  41208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41209         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41210         197,
  41211         -1,
  41212     },
  41213 #endif /* chips */
  41214 
  41215 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  41216     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  41217     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  41218     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  41219     { /* SOC_REG_INT_GRPKTr */
  41220         soc_block_list[2],
  41221         soc_portreg,
  41222         1,
  41223         0,
  41224         0xa,
  41225         SOC_REG_FLAG_COUNTER,
  41226         0,
  41227         1,
  41228         soc_GR1023r_fields,
  41229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41230         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41231         44,
  41232         -1,
  41233     },
  41234 #endif /* chips */
  41235 
  41236 #if defined(BCM_53570_A0)
  41237     { /* SOC_REG_INT_GRPKTPr */
  41238         soc_block_list[2],
  41239         soc_portreg,
  41240         1,
  41241         0,
  41242         0x7a00,
  41243         SOC_REG_FLAG_COUNTER,
  41244         0,
  41245         1,
  41246         soc_GR1023_BCM53400_A0r_fields,
  41247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41248         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41249         276,
  41250         -1,
  41251     },
  41252 #endif /* chips */
  41253 
  41254 #if defined(BCM_53570_B0)
  41255     { /* SOC_REG_INT_GRPKTP_BCM53570_B0r */
  41256         soc_block_list[2],
  41257         soc_portreg,
  41258         1,
  41259         0,
  41260         0x7a00,
  41261         SOC_REG_FLAG_COUNTER,
  41262         0,
  41263         1,
  41264         soc_GR1023_BCM53400_A0r_fields,
  41265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41266         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41267         280,
  41268         -1,
  41269     },
  41270 #endif /* chips */
  41271 
  41272 #if defined(BCM_53400_A0)
  41273     { /* SOC_REG_INT_GRPKT_BCM53400_A0r */
  41274         soc_block_list[9],
  41275         soc_portreg,
  41276         1,
  41277         0,
  41278         0x1b00,
  41279         SOC_REG_FLAG_COUNTER,
  41280         0,
  41281         1,
  41282         soc_GR1023_BCM53400_A0r_fields,
  41283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41284         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41285         126,
  41286         -1,
  41287     },
  41288 #endif /* chips */
  41289 
  41290 #if defined(BCM_53540_A0)
  41291     { /* SOC_REG_INT_GRPKT_BCM53540_A0r */
  41292         soc_block_list[2],
  41293         soc_portreg,
  41294         1,
  41295         0,
  41296         0x1b00,
  41297         SOC_REG_FLAG_COUNTER,
  41298         0,
  41299         1,
  41300         soc_GR1023_BCM53400_A0r_fields,
  41301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41303         126,
  41304         -1,
  41305     },
  41306 #endif /* chips */
  41307 
  41308 #if defined(BCM_53570_A0)
  41309     { /* SOC_REG_INT_GRPKT_BCM53570_A0r */
  41310         soc_block_list[2],
  41311         soc_portreg,
  41312         1,
  41313         0,
  41314         0x1b00,
  41315         SOC_REG_FLAG_COUNTER,
  41316         0,
  41317         1,
  41318         soc_GR1023_BCM53400_A0r_fields,
  41319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41321         181,
  41322         -1,
  41323     },
  41324 #endif /* chips */
  41325 
  41326 #if defined(BCM_53570_B0)
  41327     { /* SOC_REG_INT_GRPKT_BCM53570_B0r */
  41328         soc_block_list[2],
  41329         soc_portreg,
  41330         1,
  41331         0,
  41332         0x1b00,
  41333         SOC_REG_FLAG_COUNTER,
  41334         0,
  41335         1,
  41336         soc_GR1023_BCM53400_A0r_fields,
  41337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41339         185,
  41340         -1,
  41341     },
  41342 #endif /* chips */
  41343 
  41344 #if defined(BCM_56142_A0)
  41345     { /* SOC_REG_INT_GRPKT_BCM56142_A0r */
  41346         soc_block_list[210],
  41347         soc_portreg,
  41348         1,
  41349         0,
  41350         0x9b,
  41351         SOC_REG_FLAG_COUNTER,
  41352         0,
  41353         1,
  41354         soc_GR1023r_fields,
  41355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41357         202,
  41358         -1,
  41359     },
  41360 #endif /* chips */
  41361 
  41362 #if defined(BCM_56150_A0)
  41363     { /* SOC_REG_INT_GRPKT_BCM56150_A0r */
  41364         soc_block_list[2],
  41365         soc_portreg,
  41366         1,
  41367         0,
  41368         0x1b00,
  41369         SOC_REG_FLAG_COUNTER,
  41370         0,
  41371         1,
  41372         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  41373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41375         122,
  41376         -1,
  41377     },
  41378 #endif /* chips */
  41379 
  41380 #if defined(BCM_56160_A0)
  41381     { /* SOC_REG_INT_GRPKT_BCM56160_A0r */
  41382         soc_block_list[2],
  41383         soc_portreg,
  41384         1,
  41385         0,
  41386         0x1b00,
  41387         SOC_REG_FLAG_COUNTER,
  41388         0,
  41389         1,
  41390         soc_GR1023_BCM53400_A0r_fields,
  41391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41393         126,
  41394         -1,
  41395     },
  41396 #endif /* chips */
  41397 
  41398 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  41399     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  41400     { /* SOC_REG_INT_GRPKT_BCM56224_A0r */
  41401         soc_block_list[2],
  41402         soc_portreg,
  41403         1,
  41404         0,
  41405         0x1b,
  41406         SOC_REG_FLAG_COUNTER,
  41407         0,
  41408         1,
  41409         soc_GR1023r_fields,
  41410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41411         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41412         61,
  41413         -1,
  41414     },
  41415 #endif /* chips */
  41416 
  41417 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  41418     { /* SOC_REG_INT_GRPKT_BCM56334_A0r */
  41419         soc_block_list[210],
  41420         soc_portreg,
  41421         1,
  41422         0,
  41423         0x9b,
  41424         SOC_REG_FLAG_COUNTER,
  41425         0,
  41426         1,
  41427         soc_GR1023r_fields,
  41428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41429         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41430         197,
  41431         -1,
  41432     },
  41433 #endif /* chips */
  41434 
  41435 #if defined(BCM_56370_A0)
  41436     { /* SOC_REG_INT_GRPKT_BCM56370_A0r */
  41437         soc_block_list[9],
  41438         soc_portreg,
  41439         1,
  41440         0,
  41441         0x1b00,
  41442         SOC_REG_FLAG_COUNTER,
  41443         0,
  41444         1,
  41445         soc_GR1023_BCM53400_A0r_fields,
  41446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41448         87,
  41449         -1,
  41450         3,
  41451     },
  41452 #endif /* chips */
  41453 
  41454 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41455     { /* SOC_REG_INT_GRPKT_BCM56440_A0r */
  41456         soc_block_list[2],
  41457         soc_portreg,
  41458         1,
  41459         0,
  41460         0x9c,
  41461         SOC_REG_FLAG_COUNTER,
  41462         0,
  41463         1,
  41464         soc_GR1023r_fields,
  41465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41466         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41467         195,
  41468         -1,
  41469     },
  41470 #endif /* chips */
  41471 
  41472 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  41473     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  41474     { /* SOC_REG_INT_GRPKT_BCM56624_A0r */
  41475         soc_block_list[205],
  41476         soc_portreg,
  41477         1,
  41478         0,
  41479         0x8a,
  41480         SOC_REG_FLAG_COUNTER,
  41481         0,
  41482         1,
  41483         soc_GR1023r_fields,
  41484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41486         180,
  41487         -1,
  41488     },
  41489 #endif /* chips */
  41490 
  41491 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  41492     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  41493     { /* SOC_REG_INT_GRPKT_BCM56634_A0r */
  41494         soc_block_list[207],
  41495         soc_portreg,
  41496         1,
  41497         0,
  41498         0x8a,
  41499         SOC_REG_FLAG_COUNTER,
  41500         0,
  41501         1,
  41502         soc_GR1023r_fields,
  41503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41505         180,
  41506         -1,
  41507     },
  41508 #endif /* chips */
  41509 
  41510 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  41511     { /* SOC_REG_INT_GRPKT_BCM56685_A0r */
  41512         soc_block_list[209],
  41513         soc_portreg,
  41514         1,
  41515         0,
  41516         0x8a,
  41517         SOC_REG_FLAG_COUNTER,
  41518         0,
  41519         1,
  41520         soc_GR1023r_fields,
  41521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41522         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41523         180,
  41524         -1,
  41525     },
  41526 #endif /* chips */
  41527 
  41528 #if defined(BCM_56800_A0)
  41529     { /* SOC_REG_INT_GRPKT_BCM56800_A0r */
  41530         soc_block_list[9],
  41531         soc_portreg,
  41532         1,
  41533         0,
  41534         0x51,
  41535         SOC_REG_FLAG_COUNTER,
  41536         0,
  41537         1,
  41538         soc_GR1023r_fields,
  41539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41540         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41541         123,
  41542         -1,
  41543     },
  41544 #endif /* chips */
  41545 
  41546 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  41547     { /* SOC_REG_INT_GRPKT_BCM56820_A0r */
  41548         soc_block_list[206],
  41549         soc_portreg,
  41550         1,
  41551         0,
  41552         0x8a,
  41553         SOC_REG_FLAG_COUNTER,
  41554         0,
  41555         1,
  41556         soc_GR1023r_fields,
  41557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41559         190,
  41560         -1,
  41561     },
  41562 #endif /* chips */
  41563 
  41564 #if defined(BCM_88375_A0)
  41565     { /* SOC_REG_INT_GRPKT_BCM88375_A0r */
  41566         soc_block_list[2],
  41567         soc_portreg,
  41568         1,
  41569         0,
  41570         0x1b00,
  41571         SOC_REG_FLAG_COUNTER,
  41572         0,
  41573         1,
  41574         soc_GRPKT_BCM88375_A0r_fields,
  41575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41576         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41577         27,
  41578         -1,
  41579     },
  41580 #endif /* chips */
  41581 
  41582 #if defined(BCM_88375_B0)
  41583     { /* SOC_REG_INT_GRPKT_BCM88375_B0r */
  41584         soc_block_list[2],
  41585         soc_portreg,
  41586         1,
  41587         0,
  41588         0x1b00,
  41589         SOC_REG_FLAG_COUNTER,
  41590         0,
  41591         1,
  41592         soc_GRPKT_BCM88375_B0r_fields,
  41593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41594         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41595         27,
  41596         -1,
  41597     },
  41598 #endif /* chips */
  41599 
  41600 #if defined(BCM_88470_A0)
  41601     { /* SOC_REG_INT_GRPKT_BCM88470_A0r */
  41602         soc_block_list[2],
  41603         soc_portreg,
  41604         1,
  41605         0,
  41606         0x1b00,
  41607         SOC_REG_FLAG_COUNTER,
  41608         0,
  41609         1,
  41610         soc_GRPKT_BCM88470_A0r_fields,
  41611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41612         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41613         27,
  41614         -1,
  41615     },
  41616 #endif /* chips */
  41617 
  41618 #if defined(BCM_88470_B0)
  41619     { /* SOC_REG_INT_GRPKT_BCM88470_B0r */
  41620         soc_block_list[2],
  41621         soc_portreg,
  41622         1,
  41623         0,
  41624         0x1b00,
  41625         SOC_REG_FLAG_COUNTER,
  41626         0,
  41627         1,
  41628         soc_GRPKT_BCM88470_B0r_fields,
  41629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41631         27,
  41632         -1,
  41633     },
  41634 #endif /* chips */
  41635 
  41636 #if defined(BCM_88675_A0)
  41637     { /* SOC_REG_INT_GRPKT_BCM88675_A0r */
  41638         soc_block_list[2],
  41639         soc_portreg,
  41640         1,
  41641         0,
  41642         0x1b00,
  41643         SOC_REG_FLAG_COUNTER,
  41644         0,
  41645         1,
  41646         soc_GRPKTr_fields,
  41647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41649         27,
  41650         -1,
  41651     },
  41652 #endif /* chips */
  41653 
  41654 #if defined(BCM_88675_B0)
  41655     { /* SOC_REG_INT_GRPKT_BCM88675_B0r */
  41656         soc_block_list[2],
  41657         soc_portreg,
  41658         1,
  41659         0,
  41660         0x1b00,
  41661         SOC_REG_FLAG_COUNTER,
  41662         0,
  41663         1,
  41664         soc_GRPKT_BCM88675_B0r_fields,
  41665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41667         27,
  41668         -1,
  41669     },
  41670 #endif /* chips */
  41671 
  41672 #if defined(BCM_88680_A0)
  41673     { /* SOC_REG_INT_GRPKT_BCM88680_A0r */
  41674         soc_block_list[2],
  41675         soc_portreg,
  41676         1,
  41677         0,
  41678         0x1b00,
  41679         SOC_REG_FLAG_COUNTER,
  41680         0,
  41681         1,
  41682         soc_GRPKT_BCM88680_A0r_fields,
  41683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41685         27,
  41686         -1,
  41687     },
  41688 #endif /* chips */
  41689 
  41690 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  41691     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  41692     defined(BCM_56514_A0)
  41693     { /* SOC_REG_INT_GRPOKr */
  41694         soc_block_list[2],
  41695         soc_portreg,
  41696         1,
  41697         0,
  41698         0x1a,
  41699         SOC_REG_FLAG_COUNTER,
  41700         0,
  41701         1,
  41702         soc_GR1023r_fields,
  41703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41704         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41705         60,
  41706         -1,
  41707     },
  41708 #endif /* chips */
  41709 
  41710 #if defined(BCM_53570_A0)
  41711     { /* SOC_REG_INT_GRPOKPr */
  41712         soc_block_list[2],
  41713         soc_portreg,
  41714         1,
  41715         0,
  41716         0x7d00,
  41717         SOC_REG_FLAG_COUNTER,
  41718         0,
  41719         1,
  41720         soc_GR1023_BCM53400_A0r_fields,
  41721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41722         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41723         279,
  41724         -1,
  41725     },
  41726 #endif /* chips */
  41727 
  41728 #if defined(BCM_53570_B0)
  41729     { /* SOC_REG_INT_GRPOKP_BCM53570_B0r */
  41730         soc_block_list[2],
  41731         soc_portreg,
  41732         1,
  41733         0,
  41734         0x7d00,
  41735         SOC_REG_FLAG_COUNTER,
  41736         0,
  41737         1,
  41738         soc_GR1023_BCM53400_A0r_fields,
  41739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41740         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41741         283,
  41742         -1,
  41743     },
  41744 #endif /* chips */
  41745 
  41746 #if defined(BCM_53400_A0)
  41747     { /* SOC_REG_INT_GRPOK_BCM53400_A0r */
  41748         soc_block_list[9],
  41749         soc_portreg,
  41750         1,
  41751         0,
  41752         0x1e00,
  41753         SOC_REG_FLAG_COUNTER,
  41754         0,
  41755         1,
  41756         soc_GR1023_BCM53400_A0r_fields,
  41757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41758         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41759         129,
  41760         -1,
  41761     },
  41762 #endif /* chips */
  41763 
  41764 #if defined(BCM_53540_A0)
  41765     { /* SOC_REG_INT_GRPOK_BCM53540_A0r */
  41766         soc_block_list[2],
  41767         soc_portreg,
  41768         1,
  41769         0,
  41770         0x1e00,
  41771         SOC_REG_FLAG_COUNTER,
  41772         0,
  41773         1,
  41774         soc_GR1023_BCM53400_A0r_fields,
  41775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41776         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41777         129,
  41778         -1,
  41779     },
  41780 #endif /* chips */
  41781 
  41782 #if defined(BCM_53570_A0)
  41783     { /* SOC_REG_INT_GRPOK_BCM53570_A0r */
  41784         soc_block_list[2],
  41785         soc_portreg,
  41786         1,
  41787         0,
  41788         0x1e00,
  41789         SOC_REG_FLAG_COUNTER,
  41790         0,
  41791         1,
  41792         soc_GR1023_BCM53400_A0r_fields,
  41793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41794         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41795         184,
  41796         -1,
  41797     },
  41798 #endif /* chips */
  41799 
  41800 #if defined(BCM_53570_B0)
  41801     { /* SOC_REG_INT_GRPOK_BCM53570_B0r */
  41802         soc_block_list[2],
  41803         soc_portreg,
  41804         1,
  41805         0,
  41806         0x1e00,
  41807         SOC_REG_FLAG_COUNTER,
  41808         0,
  41809         1,
  41810         soc_GR1023_BCM53400_A0r_fields,
  41811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41812         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41813         188,
  41814         -1,
  41815     },
  41816 #endif /* chips */
  41817 
  41818 #if defined(BCM_56142_A0)
  41819     { /* SOC_REG_INT_GRPOK_BCM56142_A0r */
  41820         soc_block_list[210],
  41821         soc_portreg,
  41822         1,
  41823         0,
  41824         0x9e,
  41825         SOC_REG_FLAG_COUNTER,
  41826         0,
  41827         1,
  41828         soc_GR1023r_fields,
  41829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41830         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41831         205,
  41832         -1,
  41833     },
  41834 #endif /* chips */
  41835 
  41836 #if defined(BCM_56150_A0)
  41837     { /* SOC_REG_INT_GRPOK_BCM56150_A0r */
  41838         soc_block_list[2],
  41839         soc_portreg,
  41840         1,
  41841         0,
  41842         0x1e00,
  41843         SOC_REG_FLAG_COUNTER,
  41844         0,
  41845         1,
  41846         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  41847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41848         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41849         125,
  41850         -1,
  41851     },
  41852 #endif /* chips */
  41853 
  41854 #if defined(BCM_56160_A0)
  41855     { /* SOC_REG_INT_GRPOK_BCM56160_A0r */
  41856         soc_block_list[2],
  41857         soc_portreg,
  41858         1,
  41859         0,
  41860         0x1e00,
  41861         SOC_REG_FLAG_COUNTER,
  41862         0,
  41863         1,
  41864         soc_GR1023_BCM53400_A0r_fields,
  41865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41866         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41867         129,
  41868         -1,
  41869     },
  41870 #endif /* chips */
  41871 
  41872 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  41873     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  41874     { /* SOC_REG_INT_GRPOK_BCM56224_A0r */
  41875         soc_block_list[2],
  41876         soc_portreg,
  41877         1,
  41878         0,
  41879         0x1e,
  41880         SOC_REG_FLAG_COUNTER,
  41881         0,
  41882         1,
  41883         soc_GR1023r_fields,
  41884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41886         64,
  41887         -1,
  41888     },
  41889 #endif /* chips */
  41890 
  41891 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  41892     { /* SOC_REG_INT_GRPOK_BCM56334_A0r */
  41893         soc_block_list[210],
  41894         soc_portreg,
  41895         1,
  41896         0,
  41897         0x9e,
  41898         SOC_REG_FLAG_COUNTER,
  41899         0,
  41900         1,
  41901         soc_GR1023r_fields,
  41902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41904         200,
  41905         -1,
  41906     },
  41907 #endif /* chips */
  41908 
  41909 #if defined(BCM_56370_A0)
  41910     { /* SOC_REG_INT_GRPOK_BCM56370_A0r */
  41911         soc_block_list[9],
  41912         soc_portreg,
  41913         1,
  41914         0,
  41915         0x1e00,
  41916         SOC_REG_FLAG_COUNTER,
  41917         0,
  41918         1,
  41919         soc_GR1023_BCM53400_A0r_fields,
  41920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41922         90,
  41923         -1,
  41924         3,
  41925     },
  41926 #endif /* chips */
  41927 
  41928 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  41929     { /* SOC_REG_INT_GRPOK_BCM56440_A0r */
  41930         soc_block_list[2],
  41931         soc_portreg,
  41932         1,
  41933         0,
  41934         0x9f,
  41935         SOC_REG_FLAG_COUNTER,
  41936         0,
  41937         1,
  41938         soc_GR1023r_fields,
  41939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41940         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41941         198,
  41942         -1,
  41943     },
  41944 #endif /* chips */
  41945 
  41946 #if defined(BCM_56624_A0) || defined(BCM_56680_A0)
  41947     { /* SOC_REG_INT_GRPOK_BCM56624_A0r */
  41948         soc_block_list[205],
  41949         soc_portreg,
  41950         1,
  41951         0,
  41952         0x9a,
  41953         SOC_REG_FLAG_COUNTER,
  41954         0,
  41955         1,
  41956         soc_GR1023r_fields,
  41957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41959         196,
  41960         -1,
  41961     },
  41962 #endif /* chips */
  41963 
  41964 #if defined(BCM_56624_B0) || defined(BCM_56680_B0)
  41965     { /* SOC_REG_INT_GRPOK_BCM56624_B0r */
  41966         soc_block_list[205],
  41967         soc_portreg,
  41968         1,
  41969         0,
  41970         0x9a,
  41971         SOC_REG_FLAG_COUNTER |
  41972                           SOC_REG_FLAG_ED_CNTR,
  41973         0,
  41974         1,
  41975         soc_GR1023r_fields,
  41976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41977         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41978         196,
  41979         -1,
  41980     },
  41981 #endif /* chips */
  41982 
  41983 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  41984     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  41985     { /* SOC_REG_INT_GRPOK_BCM56634_A0r */
  41986         soc_block_list[207],
  41987         soc_portreg,
  41988         1,
  41989         0,
  41990         0x9a,
  41991         SOC_REG_FLAG_COUNTER |
  41992                           SOC_REG_FLAG_ED_CNTR,
  41993         0,
  41994         1,
  41995         soc_GR1023r_fields,
  41996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41997         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41998         196,
  41999         -1,
  42000     },
  42001 #endif /* chips */
  42002 
  42003 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  42004     { /* SOC_REG_INT_GRPOK_BCM56685_A0r */
  42005         soc_block_list[209],
  42006         soc_portreg,
  42007         1,
  42008         0,
  42009         0x9a,
  42010         SOC_REG_FLAG_COUNTER |
  42011                           SOC_REG_FLAG_ED_CNTR,
  42012         0,
  42013         1,
  42014         soc_GR1023r_fields,
  42015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42016         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42017         196,
  42018         -1,
  42019     },
  42020 #endif /* chips */
  42021 
  42022 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  42023     { /* SOC_REG_INT_GRPOK_BCM56820_A0r */
  42024         soc_block_list[206],
  42025         soc_portreg,
  42026         1,
  42027         0,
  42028         0x9a,
  42029         SOC_REG_FLAG_COUNTER,
  42030         0,
  42031         1,
  42032         soc_GR1023r_fields,
  42033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42034         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42035         206,
  42036         -1,
  42037     },
  42038 #endif /* chips */
  42039 
  42040 #if defined(BCM_88375_A0)
  42041     { /* SOC_REG_INT_GRPOK_BCM88375_A0r */
  42042         soc_block_list[2],
  42043         soc_portreg,
  42044         1,
  42045         0,
  42046         0x1e00,
  42047         SOC_REG_FLAG_COUNTER,
  42048         0,
  42049         1,
  42050         soc_GRPOK_BCM88375_A0r_fields,
  42051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42052         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42053         30,
  42054         -1,
  42055     },
  42056 #endif /* chips */
  42057 
  42058 #if defined(BCM_88375_B0)
  42059     { /* SOC_REG_INT_GRPOK_BCM88375_B0r */
  42060         soc_block_list[2],
  42061         soc_portreg,
  42062         1,
  42063         0,
  42064         0x1e00,
  42065         SOC_REG_FLAG_COUNTER,
  42066         0,
  42067         1,
  42068         soc_GRPOK_BCM88375_B0r_fields,
  42069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42070         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42071         30,
  42072         -1,
  42073     },
  42074 #endif /* chips */
  42075 
  42076 #if defined(BCM_88470_A0)
  42077     { /* SOC_REG_INT_GRPOK_BCM88470_A0r */
  42078         soc_block_list[2],
  42079         soc_portreg,
  42080         1,
  42081         0,
  42082         0x1e00,
  42083         SOC_REG_FLAG_COUNTER,
  42084         0,
  42085         1,
  42086         soc_GRPOK_BCM88470_A0r_fields,
  42087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42088         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42089         30,
  42090         -1,
  42091     },
  42092 #endif /* chips */
  42093 
  42094 #if defined(BCM_88470_B0)
  42095     { /* SOC_REG_INT_GRPOK_BCM88470_B0r */
  42096         soc_block_list[2],
  42097         soc_portreg,
  42098         1,
  42099         0,
  42100         0x1e00,
  42101         SOC_REG_FLAG_COUNTER,
  42102         0,
  42103         1,
  42104         soc_GRPOK_BCM88470_B0r_fields,
  42105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42106         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42107         30,
  42108         -1,
  42109     },
  42110 #endif /* chips */
  42111 
  42112 #if defined(BCM_88675_A0)
  42113     { /* SOC_REG_INT_GRPOK_BCM88675_A0r */
  42114         soc_block_list[2],
  42115         soc_portreg,
  42116         1,
  42117         0,
  42118         0x1e00,
  42119         SOC_REG_FLAG_COUNTER,
  42120         0,
  42121         1,
  42122         soc_GRPOKr_fields,
  42123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42124         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42125         30,
  42126         -1,
  42127     },
  42128 #endif /* chips */
  42129 
  42130 #if defined(BCM_88675_B0)
  42131     { /* SOC_REG_INT_GRPOK_BCM88675_B0r */
  42132         soc_block_list[2],
  42133         soc_portreg,
  42134         1,
  42135         0,
  42136         0x1e00,
  42137         SOC_REG_FLAG_COUNTER,
  42138         0,
  42139         1,
  42140         soc_GRPOK_BCM88675_B0r_fields,
  42141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42142         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42143         30,
  42144         -1,
  42145     },
  42146 #endif /* chips */
  42147 
  42148 #if defined(BCM_88680_A0)
  42149     { /* SOC_REG_INT_GRPOK_BCM88680_A0r */
  42150         soc_block_list[2],
  42151         soc_portreg,
  42152         1,
  42153         0,
  42154         0x1e00,
  42155         SOC_REG_FLAG_COUNTER,
  42156         0,
  42157         1,
  42158         soc_GRPOK_BCM88680_A0r_fields,
  42159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42160         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42161         30,
  42162         -1,
  42163     },
  42164 #endif /* chips */
  42165 
  42166 #if defined(BCM_88675_A0)
  42167     { /* SOC_REG_INT_GRRBYTr */
  42168         soc_block_list[2],
  42169         soc_portreg,
  42170         1,
  42171         0,
  42172         0xe00,
  42173         SOC_REG_FLAG_COUNTER,
  42174         0,
  42175         1,
  42176         soc_GRRBYTr_fields,
  42177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42178         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42179         14,
  42180         -1,
  42181     },
  42182 #endif /* chips */
  42183 
  42184 #if defined(BCM_53570_A0)
  42185     { /* SOC_REG_INT_GRRBYTPr */
  42186         soc_block_list[2],
  42187         soc_portreg,
  42188         1,
  42189         0,
  42190         0x6d00,
  42191         SOC_REG_FLAG_COUNTER |
  42192                           SOC_REG_FLAG_ED_CNTR,
  42193         0,
  42194         1,
  42195         soc_GR1023_BCM53400_A0r_fields,
  42196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42197         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42198         263,
  42199         -1,
  42200     },
  42201 #endif /* chips */
  42202 
  42203 #if defined(BCM_53570_B0)
  42204     { /* SOC_REG_INT_GRRBYTP_BCM53570_B0r */
  42205         soc_block_list[2],
  42206         soc_portreg,
  42207         1,
  42208         0,
  42209         0x6d00,
  42210         SOC_REG_FLAG_COUNTER |
  42211                           SOC_REG_FLAG_ED_CNTR,
  42212         0,
  42213         1,
  42214         soc_GR1023_BCM53400_A0r_fields,
  42215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42216         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42217         267,
  42218         -1,
  42219     },
  42220 #endif /* chips */
  42221 
  42222 #if defined(BCM_53400_A0)
  42223     { /* SOC_REG_INT_GRRBYT_BCM53400_A0r */
  42224         soc_block_list[9],
  42225         soc_portreg,
  42226         1,
  42227         0,
  42228         0xe00,
  42229         SOC_REG_FLAG_COUNTER |
  42230                           SOC_REG_FLAG_ED_CNTR,
  42231         0,
  42232         1,
  42233         soc_GR1023_BCM53400_A0r_fields,
  42234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42235         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42236         113,
  42237         -1,
  42238     },
  42239 #endif /* chips */
  42240 
  42241 #if defined(BCM_53540_A0)
  42242     { /* SOC_REG_INT_GRRBYT_BCM53540_A0r */
  42243         soc_block_list[2],
  42244         soc_portreg,
  42245         1,
  42246         0,
  42247         0xe00,
  42248         SOC_REG_FLAG_COUNTER |
  42249                           SOC_REG_FLAG_ED_CNTR,
  42250         0,
  42251         1,
  42252         soc_GR1023_BCM53400_A0r_fields,
  42253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42254         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42255         113,
  42256         -1,
  42257     },
  42258 #endif /* chips */
  42259 
  42260 #if defined(BCM_53570_A0)
  42261     { /* SOC_REG_INT_GRRBYT_BCM53570_A0r */
  42262         soc_block_list[2],
  42263         soc_portreg,
  42264         1,
  42265         0,
  42266         0xe00,
  42267         SOC_REG_FLAG_COUNTER |
  42268                           SOC_REG_FLAG_ED_CNTR,
  42269         0,
  42270         1,
  42271         soc_GR1023_BCM53400_A0r_fields,
  42272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42273         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42274         168,
  42275         -1,
  42276     },
  42277 #endif /* chips */
  42278 
  42279 #if defined(BCM_53570_B0)
  42280     { /* SOC_REG_INT_GRRBYT_BCM53570_B0r */
  42281         soc_block_list[2],
  42282         soc_portreg,
  42283         1,
  42284         0,
  42285         0xe00,
  42286         SOC_REG_FLAG_COUNTER |
  42287                           SOC_REG_FLAG_ED_CNTR,
  42288         0,
  42289         1,
  42290         soc_GR1023_BCM53400_A0r_fields,
  42291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42293         172,
  42294         -1,
  42295     },
  42296 #endif /* chips */
  42297 
  42298 #if defined(BCM_56150_A0)
  42299     { /* SOC_REG_INT_GRRBYT_BCM56150_A0r */
  42300         soc_block_list[2],
  42301         soc_portreg,
  42302         1,
  42303         0,
  42304         0xe00,
  42305         SOC_REG_FLAG_COUNTER |
  42306                           SOC_REG_FLAG_ED_CNTR,
  42307         0,
  42308         1,
  42309         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  42310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42312         109,
  42313         -1,
  42314     },
  42315 #endif /* chips */
  42316 
  42317 #if defined(BCM_56160_A0)
  42318     { /* SOC_REG_INT_GRRBYT_BCM56160_A0r */
  42319         soc_block_list[2],
  42320         soc_portreg,
  42321         1,
  42322         0,
  42323         0xe00,
  42324         SOC_REG_FLAG_COUNTER |
  42325                           SOC_REG_FLAG_ED_CNTR,
  42326         0,
  42327         1,
  42328         soc_GR1023_BCM53400_A0r_fields,
  42329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42331         113,
  42332         -1,
  42333     },
  42334 #endif /* chips */
  42335 
  42336 #if defined(BCM_56370_A0)
  42337     { /* SOC_REG_INT_GRRBYT_BCM56370_A0r */
  42338         soc_block_list[9],
  42339         soc_portreg,
  42340         1,
  42341         0,
  42342         0xe00,
  42343         SOC_REG_FLAG_COUNTER |
  42344                           SOC_REG_FLAG_ED_CNTR,
  42345         0,
  42346         1,
  42347         soc_GR1023_BCM53400_A0r_fields,
  42348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42349         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42350         74,
  42351         -1,
  42352         3,
  42353     },
  42354 #endif /* chips */
  42355 
  42356 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42357     { /* SOC_REG_INT_GRRBYT_BCM56440_A0r */
  42358         soc_block_list[2],
  42359         soc_portreg,
  42360         1,
  42361         0,
  42362         0x8e,
  42363         SOC_REG_FLAG_COUNTER |
  42364                           SOC_REG_FLAG_ED_CNTR,
  42365         0,
  42366         1,
  42367         soc_GR1023r_fields,
  42368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42370         181,
  42371         -1,
  42372     },
  42373 #endif /* chips */
  42374 
  42375 #if defined(BCM_88375_A0)
  42376     { /* SOC_REG_INT_GRRBYT_BCM88375_A0r */
  42377         soc_block_list[2],
  42378         soc_portreg,
  42379         1,
  42380         0,
  42381         0xe00,
  42382         SOC_REG_FLAG_COUNTER,
  42383         0,
  42384         1,
  42385         soc_GRRBYT_BCM88375_A0r_fields,
  42386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42388         14,
  42389         -1,
  42390     },
  42391 #endif /* chips */
  42392 
  42393 #if defined(BCM_88375_B0)
  42394     { /* SOC_REG_INT_GRRBYT_BCM88375_B0r */
  42395         soc_block_list[2],
  42396         soc_portreg,
  42397         1,
  42398         0,
  42399         0xe00,
  42400         SOC_REG_FLAG_COUNTER,
  42401         0,
  42402         1,
  42403         soc_GRRBYT_BCM88375_B0r_fields,
  42404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42405         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42406         14,
  42407         -1,
  42408     },
  42409 #endif /* chips */
  42410 
  42411 #if defined(BCM_88470_A0)
  42412     { /* SOC_REG_INT_GRRBYT_BCM88470_A0r */
  42413         soc_block_list[2],
  42414         soc_portreg,
  42415         1,
  42416         0,
  42417         0xe00,
  42418         SOC_REG_FLAG_COUNTER,
  42419         0,
  42420         1,
  42421         soc_GRRBYT_BCM88470_A0r_fields,
  42422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42423         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42424         14,
  42425         -1,
  42426     },
  42427 #endif /* chips */
  42428 
  42429 #if defined(BCM_88470_B0)
  42430     { /* SOC_REG_INT_GRRBYT_BCM88470_B0r */
  42431         soc_block_list[2],
  42432         soc_portreg,
  42433         1,
  42434         0,
  42435         0xe00,
  42436         SOC_REG_FLAG_COUNTER,
  42437         0,
  42438         1,
  42439         soc_GRRBYT_BCM88470_B0r_fields,
  42440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42441         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42442         14,
  42443         -1,
  42444     },
  42445 #endif /* chips */
  42446 
  42447 #if defined(BCM_88675_B0)
  42448     { /* SOC_REG_INT_GRRBYT_BCM88675_B0r */
  42449         soc_block_list[2],
  42450         soc_portreg,
  42451         1,
  42452         0,
  42453         0xe00,
  42454         SOC_REG_FLAG_COUNTER,
  42455         0,
  42456         1,
  42457         soc_GRRBYT_BCM88675_B0r_fields,
  42458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42459         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42460         14,
  42461         -1,
  42462     },
  42463 #endif /* chips */
  42464 
  42465 #if defined(BCM_88680_A0)
  42466     { /* SOC_REG_INT_GRRBYT_BCM88680_A0r */
  42467         soc_block_list[2],
  42468         soc_portreg,
  42469         1,
  42470         0,
  42471         0xe00,
  42472         SOC_REG_FLAG_COUNTER,
  42473         0,
  42474         1,
  42475         soc_GRRBYT_BCM88680_A0r_fields,
  42476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42478         14,
  42479         -1,
  42480     },
  42481 #endif /* chips */
  42482 
  42483 #if defined(BCM_53570_A0)
  42484     { /* SOC_REG_INT_GRRMFPr */
  42485         soc_block_list[2],
  42486         soc_portreg,
  42487         1,
  42488         0,
  42489         0x8100,
  42490         SOC_REG_FLAG_COUNTER,
  42491         0,
  42492         1,
  42493         soc_GR1023_BCM53400_A0r_fields,
  42494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42495         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42496         283,
  42497         -1,
  42498     },
  42499 #endif /* chips */
  42500 
  42501 #if defined(BCM_53570_B0)
  42502     { /* SOC_REG_INT_GRRMFP_BCM53570_B0r */
  42503         soc_block_list[2],
  42504         soc_portreg,
  42505         1,
  42506         0,
  42507         0x8100,
  42508         SOC_REG_FLAG_COUNTER,
  42509         0,
  42510         1,
  42511         soc_GR1023_BCM53400_A0r_fields,
  42512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42514         287,
  42515         -1,
  42516     },
  42517 #endif /* chips */
  42518 
  42519 #if defined(BCM_88675_A0)
  42520     { /* SOC_REG_INT_GRRPKTr */
  42521         soc_block_list[2],
  42522         soc_portreg,
  42523         1,
  42524         0,
  42525         0xb00,
  42526         SOC_REG_FLAG_COUNTER,
  42527         0,
  42528         1,
  42529         soc_GRRPKTr_fields,
  42530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42531         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42532         11,
  42533         -1,
  42534     },
  42535 #endif /* chips */
  42536 
  42537 #if defined(BCM_53570_A0)
  42538     { /* SOC_REG_INT_GRRPKTPr */
  42539         soc_block_list[2],
  42540         soc_portreg,
  42541         1,
  42542         0,
  42543         0x6a00,
  42544         SOC_REG_FLAG_COUNTER |
  42545                           SOC_REG_FLAG_ED_CNTR,
  42546         0,
  42547         1,
  42548         soc_GR1023_BCM53400_A0r_fields,
  42549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42550         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42551         260,
  42552         -1,
  42553     },
  42554 #endif /* chips */
  42555 
  42556 #if defined(BCM_53570_B0)
  42557     { /* SOC_REG_INT_GRRPKTP_BCM53570_B0r */
  42558         soc_block_list[2],
  42559         soc_portreg,
  42560         1,
  42561         0,
  42562         0x6a00,
  42563         SOC_REG_FLAG_COUNTER |
  42564                           SOC_REG_FLAG_ED_CNTR,
  42565         0,
  42566         1,
  42567         soc_GR1023_BCM53400_A0r_fields,
  42568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42569         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42570         264,
  42571         -1,
  42572     },
  42573 #endif /* chips */
  42574 
  42575 #if defined(BCM_53400_A0)
  42576     { /* SOC_REG_INT_GRRPKT_BCM53400_A0r */
  42577         soc_block_list[9],
  42578         soc_portreg,
  42579         1,
  42580         0,
  42581         0xb00,
  42582         SOC_REG_FLAG_COUNTER |
  42583                           SOC_REG_FLAG_ED_CNTR,
  42584         0,
  42585         1,
  42586         soc_GR1023_BCM53400_A0r_fields,
  42587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42588         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42589         110,
  42590         -1,
  42591     },
  42592 #endif /* chips */
  42593 
  42594 #if defined(BCM_53540_A0)
  42595     { /* SOC_REG_INT_GRRPKT_BCM53540_A0r */
  42596         soc_block_list[2],
  42597         soc_portreg,
  42598         1,
  42599         0,
  42600         0xb00,
  42601         SOC_REG_FLAG_COUNTER |
  42602                           SOC_REG_FLAG_ED_CNTR,
  42603         0,
  42604         1,
  42605         soc_GR1023_BCM53400_A0r_fields,
  42606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42607         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42608         110,
  42609         -1,
  42610     },
  42611 #endif /* chips */
  42612 
  42613 #if defined(BCM_53570_A0)
  42614     { /* SOC_REG_INT_GRRPKT_BCM53570_A0r */
  42615         soc_block_list[2],
  42616         soc_portreg,
  42617         1,
  42618         0,
  42619         0xb00,
  42620         SOC_REG_FLAG_COUNTER |
  42621                           SOC_REG_FLAG_ED_CNTR,
  42622         0,
  42623         1,
  42624         soc_GR1023_BCM53400_A0r_fields,
  42625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42626         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42627         165,
  42628         -1,
  42629     },
  42630 #endif /* chips */
  42631 
  42632 #if defined(BCM_53570_B0)
  42633     { /* SOC_REG_INT_GRRPKT_BCM53570_B0r */
  42634         soc_block_list[2],
  42635         soc_portreg,
  42636         1,
  42637         0,
  42638         0xb00,
  42639         SOC_REG_FLAG_COUNTER |
  42640                           SOC_REG_FLAG_ED_CNTR,
  42641         0,
  42642         1,
  42643         soc_GR1023_BCM53400_A0r_fields,
  42644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42646         169,
  42647         -1,
  42648     },
  42649 #endif /* chips */
  42650 
  42651 #if defined(BCM_56150_A0)
  42652     { /* SOC_REG_INT_GRRPKT_BCM56150_A0r */
  42653         soc_block_list[2],
  42654         soc_portreg,
  42655         1,
  42656         0,
  42657         0xb00,
  42658         SOC_REG_FLAG_COUNTER |
  42659                           SOC_REG_FLAG_ED_CNTR,
  42660         0,
  42661         1,
  42662         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  42663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42665         106,
  42666         -1,
  42667     },
  42668 #endif /* chips */
  42669 
  42670 #if defined(BCM_56160_A0)
  42671     { /* SOC_REG_INT_GRRPKT_BCM56160_A0r */
  42672         soc_block_list[2],
  42673         soc_portreg,
  42674         1,
  42675         0,
  42676         0xb00,
  42677         SOC_REG_FLAG_COUNTER |
  42678                           SOC_REG_FLAG_ED_CNTR,
  42679         0,
  42680         1,
  42681         soc_GR1023_BCM53400_A0r_fields,
  42682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42683         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42684         110,
  42685         -1,
  42686     },
  42687 #endif /* chips */
  42688 
  42689 #if defined(BCM_56370_A0)
  42690     { /* SOC_REG_INT_GRRPKT_BCM56370_A0r */
  42691         soc_block_list[9],
  42692         soc_portreg,
  42693         1,
  42694         0,
  42695         0xb00,
  42696         SOC_REG_FLAG_COUNTER |
  42697                           SOC_REG_FLAG_ED_CNTR,
  42698         0,
  42699         1,
  42700         soc_GR1023_BCM53400_A0r_fields,
  42701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42703         71,
  42704         -1,
  42705         3,
  42706     },
  42707 #endif /* chips */
  42708 
  42709 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  42710     { /* SOC_REG_INT_GRRPKT_BCM56440_A0r */
  42711         soc_block_list[2],
  42712         soc_portreg,
  42713         1,
  42714         0,
  42715         0x8b,
  42716         SOC_REG_FLAG_COUNTER |
  42717                           SOC_REG_FLAG_ED_CNTR,
  42718         0,
  42719         1,
  42720         soc_GR1023r_fields,
  42721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42722         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42723         178,
  42724         -1,
  42725     },
  42726 #endif /* chips */
  42727 
  42728 #if defined(BCM_88375_A0)
  42729     { /* SOC_REG_INT_GRRPKT_BCM88375_A0r */
  42730         soc_block_list[2],
  42731         soc_portreg,
  42732         1,
  42733         0,
  42734         0xb00,
  42735         SOC_REG_FLAG_COUNTER,
  42736         0,
  42737         1,
  42738         soc_GRRPKT_BCM88375_A0r_fields,
  42739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42741         11,
  42742         -1,
  42743     },
  42744 #endif /* chips */
  42745 
  42746 #if defined(BCM_88375_B0)
  42747     { /* SOC_REG_INT_GRRPKT_BCM88375_B0r */
  42748         soc_block_list[2],
  42749         soc_portreg,
  42750         1,
  42751         0,
  42752         0xb00,
  42753         SOC_REG_FLAG_COUNTER,
  42754         0,
  42755         1,
  42756         soc_GRRPKT_BCM88375_B0r_fields,
  42757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42759         11,
  42760         -1,
  42761     },
  42762 #endif /* chips */
  42763 
  42764 #if defined(BCM_88470_A0)
  42765     { /* SOC_REG_INT_GRRPKT_BCM88470_A0r */
  42766         soc_block_list[2],
  42767         soc_portreg,
  42768         1,
  42769         0,
  42770         0xb00,
  42771         SOC_REG_FLAG_COUNTER,
  42772         0,
  42773         1,
  42774         soc_GRRPKT_BCM88470_A0r_fields,
  42775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42777         11,
  42778         -1,
  42779     },
  42780 #endif /* chips */
  42781 
  42782 #if defined(BCM_88470_B0)
  42783     { /* SOC_REG_INT_GRRPKT_BCM88470_B0r */
  42784         soc_block_list[2],
  42785         soc_portreg,
  42786         1,
  42787         0,
  42788         0xb00,
  42789         SOC_REG_FLAG_COUNTER,
  42790         0,
  42791         1,
  42792         soc_GRRPKT_BCM88470_B0r_fields,
  42793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42794         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42795         11,
  42796         -1,
  42797     },
  42798 #endif /* chips */
  42799 
  42800 #if defined(BCM_88675_B0)
  42801     { /* SOC_REG_INT_GRRPKT_BCM88675_B0r */
  42802         soc_block_list[2],
  42803         soc_portreg,
  42804         1,
  42805         0,
  42806         0xb00,
  42807         SOC_REG_FLAG_COUNTER,
  42808         0,
  42809         1,
  42810         soc_GRRPKT_BCM88675_B0r_fields,
  42811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42812         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42813         11,
  42814         -1,
  42815     },
  42816 #endif /* chips */
  42817 
  42818 #if defined(BCM_88680_A0)
  42819     { /* SOC_REG_INT_GRRPKT_BCM88680_A0r */
  42820         soc_block_list[2],
  42821         soc_portreg,
  42822         1,
  42823         0,
  42824         0xb00,
  42825         SOC_REG_FLAG_COUNTER,
  42826         0,
  42827         1,
  42828         soc_GRRPKT_BCM88680_A0r_fields,
  42829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42830         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42831         11,
  42832         -1,
  42833     },
  42834 #endif /* chips */
  42835 
  42836 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  42837     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  42838     defined(BCM_56514_A0)
  42839     { /* SOC_REG_INT_GRUCr */
  42840         soc_block_list[2],
  42841         soc_portreg,
  42842         1,
  42843         0,
  42844         0x19,
  42845         SOC_REG_FLAG_COUNTER,
  42846         0,
  42847         1,
  42848         soc_GR1023r_fields,
  42849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42851         59,
  42852         -1,
  42853     },
  42854 #endif /* chips */
  42855 
  42856 #if defined(BCM_53570_A0)
  42857     { /* SOC_REG_INT_GRUCPr */
  42858         soc_block_list[2],
  42859         soc_portreg,
  42860         1,
  42861         0,
  42862         0x7c00,
  42863         SOC_REG_FLAG_COUNTER,
  42864         0,
  42865         1,
  42866         soc_GR1023_BCM53400_A0r_fields,
  42867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42868         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42869         278,
  42870         -1,
  42871     },
  42872 #endif /* chips */
  42873 
  42874 #if defined(BCM_53570_B0)
  42875     { /* SOC_REG_INT_GRUCP_BCM53570_B0r */
  42876         soc_block_list[2],
  42877         soc_portreg,
  42878         1,
  42879         0,
  42880         0x7c00,
  42881         SOC_REG_FLAG_COUNTER,
  42882         0,
  42883         1,
  42884         soc_GR1023_BCM53400_A0r_fields,
  42885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42886         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42887         282,
  42888         -1,
  42889     },
  42890 #endif /* chips */
  42891 
  42892 #if defined(BCM_53400_A0)
  42893     { /* SOC_REG_INT_GRUC_BCM53400_A0r */
  42894         soc_block_list[9],
  42895         soc_portreg,
  42896         1,
  42897         0,
  42898         0x1d00,
  42899         SOC_REG_FLAG_COUNTER,
  42900         0,
  42901         1,
  42902         soc_GR1023_BCM53400_A0r_fields,
  42903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42904         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42905         128,
  42906         -1,
  42907     },
  42908 #endif /* chips */
  42909 
  42910 #if defined(BCM_53540_A0)
  42911     { /* SOC_REG_INT_GRUC_BCM53540_A0r */
  42912         soc_block_list[2],
  42913         soc_portreg,
  42914         1,
  42915         0,
  42916         0x1d00,
  42917         SOC_REG_FLAG_COUNTER,
  42918         0,
  42919         1,
  42920         soc_GR1023_BCM53400_A0r_fields,
  42921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42922         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42923         128,
  42924         -1,
  42925     },
  42926 #endif /* chips */
  42927 
  42928 #if defined(BCM_53570_A0)
  42929     { /* SOC_REG_INT_GRUC_BCM53570_A0r */
  42930         soc_block_list[2],
  42931         soc_portreg,
  42932         1,
  42933         0,
  42934         0x1d00,
  42935         SOC_REG_FLAG_COUNTER,
  42936         0,
  42937         1,
  42938         soc_GR1023_BCM53400_A0r_fields,
  42939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42940         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42941         183,
  42942         -1,
  42943     },
  42944 #endif /* chips */
  42945 
  42946 #if defined(BCM_53570_B0)
  42947     { /* SOC_REG_INT_GRUC_BCM53570_B0r */
  42948         soc_block_list[2],
  42949         soc_portreg,
  42950         1,
  42951         0,
  42952         0x1d00,
  42953         SOC_REG_FLAG_COUNTER,
  42954         0,
  42955         1,
  42956         soc_GR1023_BCM53400_A0r_fields,
  42957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42959         187,
  42960         -1,
  42961     },
  42962 #endif /* chips */
  42963 
  42964 #if defined(BCM_56142_A0)
  42965     { /* SOC_REG_INT_GRUC_BCM56142_A0r */
  42966         soc_block_list[210],
  42967         soc_portreg,
  42968         1,
  42969         0,
  42970         0x9d,
  42971         SOC_REG_FLAG_COUNTER,
  42972         0,
  42973         1,
  42974         soc_GR1023r_fields,
  42975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42976         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42977         204,
  42978         -1,
  42979     },
  42980 #endif /* chips */
  42981 
  42982 #if defined(BCM_56150_A0)
  42983     { /* SOC_REG_INT_GRUC_BCM56150_A0r */
  42984         soc_block_list[2],
  42985         soc_portreg,
  42986         1,
  42987         0,
  42988         0x1d00,
  42989         SOC_REG_FLAG_COUNTER,
  42990         0,
  42991         1,
  42992         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  42993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42994         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42995         124,
  42996         -1,
  42997     },
  42998 #endif /* chips */
  42999 
  43000 #if defined(BCM_56160_A0)
  43001     { /* SOC_REG_INT_GRUC_BCM56160_A0r */
  43002         soc_block_list[2],
  43003         soc_portreg,
  43004         1,
  43005         0,
  43006         0x1d00,
  43007         SOC_REG_FLAG_COUNTER,
  43008         0,
  43009         1,
  43010         soc_GR1023_BCM53400_A0r_fields,
  43011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43012         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43013         128,
  43014         -1,
  43015     },
  43016 #endif /* chips */
  43017 
  43018 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  43019     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  43020     { /* SOC_REG_INT_GRUC_BCM56224_A0r */
  43021         soc_block_list[2],
  43022         soc_portreg,
  43023         1,
  43024         0,
  43025         0x1d,
  43026         SOC_REG_FLAG_COUNTER,
  43027         0,
  43028         1,
  43029         soc_GR1023r_fields,
  43030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43032         63,
  43033         -1,
  43034     },
  43035 #endif /* chips */
  43036 
  43037 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  43038     { /* SOC_REG_INT_GRUC_BCM56334_A0r */
  43039         soc_block_list[210],
  43040         soc_portreg,
  43041         1,
  43042         0,
  43043         0x9d,
  43044         SOC_REG_FLAG_COUNTER,
  43045         0,
  43046         1,
  43047         soc_GR1023r_fields,
  43048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43050         199,
  43051         -1,
  43052     },
  43053 #endif /* chips */
  43054 
  43055 #if defined(BCM_56370_A0)
  43056     { /* SOC_REG_INT_GRUC_BCM56370_A0r */
  43057         soc_block_list[9],
  43058         soc_portreg,
  43059         1,
  43060         0,
  43061         0x1d00,
  43062         SOC_REG_FLAG_COUNTER,
  43063         0,
  43064         1,
  43065         soc_GR1023_BCM53400_A0r_fields,
  43066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43067         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43068         89,
  43069         -1,
  43070         3,
  43071     },
  43072 #endif /* chips */
  43073 
  43074 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  43075     { /* SOC_REG_INT_GRUC_BCM56440_A0r */
  43076         soc_block_list[2],
  43077         soc_portreg,
  43078         1,
  43079         0,
  43080         0x9e,
  43081         SOC_REG_FLAG_COUNTER,
  43082         0,
  43083         1,
  43084         soc_GR1023r_fields,
  43085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43086         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43087         197,
  43088         -1,
  43089     },
  43090 #endif /* chips */
  43091 
  43092 #if defined(BCM_56624_A0) || defined(BCM_56680_A0)
  43093     { /* SOC_REG_INT_GRUC_BCM56624_A0r */
  43094         soc_block_list[205],
  43095         soc_portreg,
  43096         1,
  43097         0,
  43098         0x99,
  43099         SOC_REG_FLAG_COUNTER,
  43100         0,
  43101         1,
  43102         soc_GR1023r_fields,
  43103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43105         195,
  43106         -1,
  43107     },
  43108 #endif /* chips */
  43109 
  43110 #if defined(BCM_56624_B0) || defined(BCM_56680_B0)
  43111     { /* SOC_REG_INT_GRUC_BCM56624_B0r */
  43112         soc_block_list[205],
  43113         soc_portreg,
  43114         1,
  43115         0,
  43116         0x99,
  43117         SOC_REG_FLAG_COUNTER |
  43118                           SOC_REG_FLAG_ED_CNTR,
  43119         0,
  43120         1,
  43121         soc_GR1023r_fields,
  43122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43124         195,
  43125         -1,
  43126     },
  43127 #endif /* chips */
  43128 
  43129 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  43130     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  43131     { /* SOC_REG_INT_GRUC_BCM56634_A0r */
  43132         soc_block_list[207],
  43133         soc_portreg,
  43134         1,
  43135         0,
  43136         0x99,
  43137         SOC_REG_FLAG_COUNTER |
  43138                           SOC_REG_FLAG_ED_CNTR,
  43139         0,
  43140         1,
  43141         soc_GR1023r_fields,
  43142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43143         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43144         195,
  43145         -1,
  43146     },
  43147 #endif /* chips */
  43148 
  43149 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  43150     { /* SOC_REG_INT_GRUC_BCM56685_A0r */
  43151         soc_block_list[209],
  43152         soc_portreg,
  43153         1,
  43154         0,
  43155         0x99,
  43156         SOC_REG_FLAG_COUNTER |
  43157                           SOC_REG_FLAG_ED_CNTR,
  43158         0,
  43159         1,
  43160         soc_GR1023r_fields,
  43161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43163         195,
  43164         -1,
  43165     },
  43166 #endif /* chips */
  43167 
  43168 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  43169     { /* SOC_REG_INT_GRUC_BCM56820_A0r */
  43170         soc_block_list[206],
  43171         soc_portreg,
  43172         1,
  43173         0,
  43174         0x99,
  43175         SOC_REG_FLAG_COUNTER,
  43176         0,
  43177         1,
  43178         soc_GR1023r_fields,
  43179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43180         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43181         205,
  43182         -1,
  43183     },
  43184 #endif /* chips */
  43185 
  43186 #if defined(BCM_88375_A0)
  43187     { /* SOC_REG_INT_GRUC_BCM88375_A0r */
  43188         soc_block_list[2],
  43189         soc_portreg,
  43190         1,
  43191         0,
  43192         0x1d00,
  43193         SOC_REG_FLAG_COUNTER,
  43194         0,
  43195         1,
  43196         soc_GRUC_BCM88375_A0r_fields,
  43197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43198         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43199         29,
  43200         -1,
  43201     },
  43202 #endif /* chips */
  43203 
  43204 #if defined(BCM_88375_B0)
  43205     { /* SOC_REG_INT_GRUC_BCM88375_B0r */
  43206         soc_block_list[2],
  43207         soc_portreg,
  43208         1,
  43209         0,
  43210         0x1d00,
  43211         SOC_REG_FLAG_COUNTER,
  43212         0,
  43213         1,
  43214         soc_GRUC_BCM88375_B0r_fields,
  43215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43216         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43217         29,
  43218         -1,
  43219     },
  43220 #endif /* chips */
  43221 
  43222 #if defined(BCM_88470_A0)
  43223     { /* SOC_REG_INT_GRUC_BCM88470_A0r */
  43224         soc_block_list[2],
  43225         soc_portreg,
  43226         1,
  43227         0,
  43228         0x1d00,
  43229         SOC_REG_FLAG_COUNTER,
  43230         0,
  43231         1,
  43232         soc_GRUC_BCM88470_A0r_fields,
  43233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43234         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43235         29,
  43236         -1,
  43237     },
  43238 #endif /* chips */
  43239 
  43240 #if defined(BCM_88470_B0)
  43241     { /* SOC_REG_INT_GRUC_BCM88470_B0r */
  43242         soc_block_list[2],
  43243         soc_portreg,
  43244         1,
  43245         0,
  43246         0x1d00,
  43247         SOC_REG_FLAG_COUNTER,
  43248         0,
  43249         1,
  43250         soc_GRUC_BCM88470_B0r_fields,
  43251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43253         29,
  43254         -1,
  43255     },
  43256 #endif /* chips */
  43257 
  43258 #if defined(BCM_88675_A0)
  43259     { /* SOC_REG_INT_GRUC_BCM88675_A0r */
  43260         soc_block_list[2],
  43261         soc_portreg,
  43262         1,
  43263         0,
  43264         0x1d00,
  43265         SOC_REG_FLAG_COUNTER,
  43266         0,
  43267         1,
  43268         soc_GRUCr_fields,
  43269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43270         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43271         29,
  43272         -1,
  43273     },
  43274 #endif /* chips */
  43275 
  43276 #if defined(BCM_88675_B0)
  43277     { /* SOC_REG_INT_GRUC_BCM88675_B0r */
  43278         soc_block_list[2],
  43279         soc_portreg,
  43280         1,
  43281         0,
  43282         0x1d00,
  43283         SOC_REG_FLAG_COUNTER,
  43284         0,
  43285         1,
  43286         soc_GRUC_BCM88675_B0r_fields,
  43287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43288         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43289         29,
  43290         -1,
  43291     },
  43292 #endif /* chips */
  43293 
  43294 #if defined(BCM_88680_A0)
  43295     { /* SOC_REG_INT_GRUC_BCM88680_A0r */
  43296         soc_block_list[2],
  43297         soc_portreg,
  43298         1,
  43299         0,
  43300         0x1d00,
  43301         SOC_REG_FLAG_COUNTER,
  43302         0,
  43303         1,
  43304         soc_GRUC_BCM88680_A0r_fields,
  43305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43306         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43307         29,
  43308         -1,
  43309     },
  43310 #endif /* chips */
  43311 
  43312 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  43313     defined(BCM_56504_B0)
  43314     { /* SOC_REG_INT_GRUNDr */
  43315         soc_block_list[2],
  43316         soc_portreg,
  43317         1,
  43318         0,
  43319         0x1a,
  43320         SOC_REG_FLAG_COUNTER |
  43321                           SOC_REG_FLAG_ED_CNTR,
  43322         0,
  43323         1,
  43324         soc_GR1023r_fields,
  43325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43326         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43327         60,
  43328         -1,
  43329     },
  43330 #endif /* chips */
  43331 
  43332 #if defined(BCM_53570_A0)
  43333     { /* SOC_REG_INT_GRUNDPr */
  43334         soc_block_list[2],
  43335         soc_portreg,
  43336         1,
  43337         0,
  43338         0x6b00,
  43339         SOC_REG_FLAG_COUNTER |
  43340                           SOC_REG_FLAG_ED_CNTR,
  43341         0,
  43342         1,
  43343         soc_GR1023_BCM53400_A0r_fields,
  43344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43346         261,
  43347         -1,
  43348     },
  43349 #endif /* chips */
  43350 
  43351 #if defined(BCM_53570_B0)
  43352     { /* SOC_REG_INT_GRUNDP_BCM53570_B0r */
  43353         soc_block_list[2],
  43354         soc_portreg,
  43355         1,
  43356         0,
  43357         0x6b00,
  43358         SOC_REG_FLAG_COUNTER |
  43359                           SOC_REG_FLAG_ED_CNTR,
  43360         0,
  43361         1,
  43362         soc_GR1023_BCM53400_A0r_fields,
  43363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43364         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43365         265,
  43366         -1,
  43367     },
  43368 #endif /* chips */
  43369 
  43370 #if defined(BCM_53400_A0)
  43371     { /* SOC_REG_INT_GRUND_BCM53400_A0r */
  43372         soc_block_list[9],
  43373         soc_portreg,
  43374         1,
  43375         0,
  43376         0xc00,
  43377         SOC_REG_FLAG_COUNTER |
  43378                           SOC_REG_FLAG_ED_CNTR,
  43379         0,
  43380         1,
  43381         soc_GR1023_BCM53400_A0r_fields,
  43382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43384         111,
  43385         -1,
  43386     },
  43387 #endif /* chips */
  43388 
  43389 #if defined(BCM_53540_A0)
  43390     { /* SOC_REG_INT_GRUND_BCM53540_A0r */
  43391         soc_block_list[2],
  43392         soc_portreg,
  43393         1,
  43394         0,
  43395         0xc00,
  43396         SOC_REG_FLAG_COUNTER |
  43397                           SOC_REG_FLAG_ED_CNTR,
  43398         0,
  43399         1,
  43400         soc_GR1023_BCM53400_A0r_fields,
  43401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43402         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43403         111,
  43404         -1,
  43405     },
  43406 #endif /* chips */
  43407 
  43408 #if defined(BCM_53570_A0)
  43409     { /* SOC_REG_INT_GRUND_BCM53570_A0r */
  43410         soc_block_list[2],
  43411         soc_portreg,
  43412         1,
  43413         0,
  43414         0xc00,
  43415         SOC_REG_FLAG_COUNTER |
  43416                           SOC_REG_FLAG_ED_CNTR,
  43417         0,
  43418         1,
  43419         soc_GR1023_BCM53400_A0r_fields,
  43420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43421         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43422         166,
  43423         -1,
  43424     },
  43425 #endif /* chips */
  43426 
  43427 #if defined(BCM_53570_B0)
  43428     { /* SOC_REG_INT_GRUND_BCM53570_B0r */
  43429         soc_block_list[2],
  43430         soc_portreg,
  43431         1,
  43432         0,
  43433         0xc00,
  43434         SOC_REG_FLAG_COUNTER |
  43435                           SOC_REG_FLAG_ED_CNTR,
  43436         0,
  43437         1,
  43438         soc_GR1023_BCM53400_A0r_fields,
  43439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43440         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43441         170,
  43442         -1,
  43443     },
  43444 #endif /* chips */
  43445 
  43446 #if defined(BCM_56142_A0)
  43447     { /* SOC_REG_INT_GRUND_BCM56142_A0r */
  43448         soc_block_list[210],
  43449         soc_portreg,
  43450         1,
  43451         0,
  43452         0x8c,
  43453         SOC_REG_FLAG_COUNTER |
  43454                           SOC_REG_FLAG_ED_CNTR,
  43455         0,
  43456         1,
  43457         soc_GR1023r_fields,
  43458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43459         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43460         187,
  43461         -1,
  43462     },
  43463 #endif /* chips */
  43464 
  43465 #if defined(BCM_56150_A0)
  43466     { /* SOC_REG_INT_GRUND_BCM56150_A0r */
  43467         soc_block_list[2],
  43468         soc_portreg,
  43469         1,
  43470         0,
  43471         0xc00,
  43472         SOC_REG_FLAG_COUNTER |
  43473                           SOC_REG_FLAG_ED_CNTR,
  43474         0,
  43475         1,
  43476         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  43477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43479         107,
  43480         -1,
  43481     },
  43482 #endif /* chips */
  43483 
  43484 #if defined(BCM_56160_A0)
  43485     { /* SOC_REG_INT_GRUND_BCM56160_A0r */
  43486         soc_block_list[2],
  43487         soc_portreg,
  43488         1,
  43489         0,
  43490         0xc00,
  43491         SOC_REG_FLAG_COUNTER |
  43492                           SOC_REG_FLAG_ED_CNTR,
  43493         0,
  43494         1,
  43495         soc_GR1023_BCM53400_A0r_fields,
  43496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43497         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43498         111,
  43499         -1,
  43500     },
  43501 #endif /* chips */
  43502 
  43503 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  43504     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  43505     { /* SOC_REG_INT_GRUND_BCM56224_A0r */
  43506         soc_block_list[2],
  43507         soc_portreg,
  43508         1,
  43509         0,
  43510         0xc,
  43511         SOC_REG_FLAG_COUNTER |
  43512                           SOC_REG_FLAG_ED_CNTR,
  43513         0,
  43514         1,
  43515         soc_GR1023r_fields,
  43516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43517         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43518         46,
  43519         -1,
  43520     },
  43521 #endif /* chips */
  43522 
  43523 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  43524     { /* SOC_REG_INT_GRUND_BCM56334_A0r */
  43525         soc_block_list[210],
  43526         soc_portreg,
  43527         1,
  43528         0,
  43529         0x8c,
  43530         SOC_REG_FLAG_COUNTER |
  43531                           SOC_REG_FLAG_ED_CNTR,
  43532         0,
  43533         1,
  43534         soc_GR1023r_fields,
  43535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43536         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43537         182,
  43538         -1,
  43539     },
  43540 #endif /* chips */
  43541 
  43542 #if defined(BCM_56370_A0)
  43543     { /* SOC_REG_INT_GRUND_BCM56370_A0r */
  43544         soc_block_list[9],
  43545         soc_portreg,
  43546         1,
  43547         0,
  43548         0xc00,
  43549         SOC_REG_FLAG_COUNTER |
  43550                           SOC_REG_FLAG_ED_CNTR,
  43551         0,
  43552         1,
  43553         soc_GR1023_BCM53400_A0r_fields,
  43554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43556         72,
  43557         -1,
  43558         3,
  43559     },
  43560 #endif /* chips */
  43561 
  43562 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  43563     { /* SOC_REG_INT_GRUND_BCM56440_A0r */
  43564         soc_block_list[2],
  43565         soc_portreg,
  43566         1,
  43567         0,
  43568         0x8c,
  43569         SOC_REG_FLAG_COUNTER |
  43570                           SOC_REG_FLAG_ED_CNTR,
  43571         0,
  43572         1,
  43573         soc_GR1023r_fields,
  43574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43576         179,
  43577         -1,
  43578     },
  43579 #endif /* chips */
  43580 
  43581 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  43582     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  43583     { /* SOC_REG_INT_GRUND_BCM56624_A0r */
  43584         soc_block_list[205],
  43585         soc_portreg,
  43586         1,
  43587         0,
  43588         0x9c,
  43589         SOC_REG_FLAG_COUNTER |
  43590                           SOC_REG_FLAG_ED_CNTR,
  43591         0,
  43592         1,
  43593         soc_GR1023r_fields,
  43594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43595         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43596         198,
  43597         -1,
  43598     },
  43599 #endif /* chips */
  43600 
  43601 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  43602     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  43603     { /* SOC_REG_INT_GRUND_BCM56634_A0r */
  43604         soc_block_list[207],
  43605         soc_portreg,
  43606         1,
  43607         0,
  43608         0x9c,
  43609         SOC_REG_FLAG_COUNTER |
  43610                           SOC_REG_FLAG_ED_CNTR,
  43611         0,
  43612         1,
  43613         soc_GR1023r_fields,
  43614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43616         198,
  43617         -1,
  43618     },
  43619 #endif /* chips */
  43620 
  43621 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  43622     { /* SOC_REG_INT_GRUND_BCM56685_A0r */
  43623         soc_block_list[209],
  43624         soc_portreg,
  43625         1,
  43626         0,
  43627         0x9c,
  43628         SOC_REG_FLAG_COUNTER |
  43629                           SOC_REG_FLAG_ED_CNTR,
  43630         0,
  43631         1,
  43632         soc_GR1023r_fields,
  43633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43634         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43635         198,
  43636         -1,
  43637     },
  43638 #endif /* chips */
  43639 
  43640 #if defined(BCM_56800_A0)
  43641     { /* SOC_REG_INT_GRUND_BCM56800_A0r */
  43642         soc_block_list[9],
  43643         soc_portreg,
  43644         1,
  43645         0,
  43646         0x61,
  43647         SOC_REG_FLAG_COUNTER |
  43648                           SOC_REG_FLAG_ED_CNTR,
  43649         0,
  43650         1,
  43651         soc_GR1023r_fields,
  43652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43654         139,
  43655         -1,
  43656     },
  43657 #endif /* chips */
  43658 
  43659 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  43660     { /* SOC_REG_INT_GRUND_BCM56820_A0r */
  43661         soc_block_list[206],
  43662         soc_portreg,
  43663         1,
  43664         0,
  43665         0x9d,
  43666         SOC_REG_FLAG_COUNTER |
  43667                           SOC_REG_FLAG_ED_CNTR,
  43668         0,
  43669         1,
  43670         soc_GR1023r_fields,
  43671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43672         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43673         209,
  43674         -1,
  43675     },
  43676 #endif /* chips */
  43677 
  43678 #if defined(BCM_88375_A0)
  43679     { /* SOC_REG_INT_GRUND_BCM88375_A0r */
  43680         soc_block_list[2],
  43681         soc_portreg,
  43682         1,
  43683         0,
  43684         0xc00,
  43685         SOC_REG_FLAG_COUNTER,
  43686         0,
  43687         1,
  43688         soc_GRUND_BCM88375_A0r_fields,
  43689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43690         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43691         12,
  43692         -1,
  43693     },
  43694 #endif /* chips */
  43695 
  43696 #if defined(BCM_88375_B0)
  43697     { /* SOC_REG_INT_GRUND_BCM88375_B0r */
  43698         soc_block_list[2],
  43699         soc_portreg,
  43700         1,
  43701         0,
  43702         0xc00,
  43703         SOC_REG_FLAG_COUNTER,
  43704         0,
  43705         1,
  43706         soc_GRUND_BCM88375_B0r_fields,
  43707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43708         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43709         12,
  43710         -1,
  43711     },
  43712 #endif /* chips */
  43713 
  43714 #if defined(BCM_88470_A0)
  43715     { /* SOC_REG_INT_GRUND_BCM88470_A0r */
  43716         soc_block_list[2],
  43717         soc_portreg,
  43718         1,
  43719         0,
  43720         0xc00,
  43721         SOC_REG_FLAG_COUNTER,
  43722         0,
  43723         1,
  43724         soc_GRUND_BCM88470_A0r_fields,
  43725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43726         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43727         12,
  43728         -1,
  43729     },
  43730 #endif /* chips */
  43731 
  43732 #if defined(BCM_88470_B0)
  43733     { /* SOC_REG_INT_GRUND_BCM88470_B0r */
  43734         soc_block_list[2],
  43735         soc_portreg,
  43736         1,
  43737         0,
  43738         0xc00,
  43739         SOC_REG_FLAG_COUNTER,
  43740         0,
  43741         1,
  43742         soc_GRUND_BCM88470_B0r_fields,
  43743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43744         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43745         12,
  43746         -1,
  43747     },
  43748 #endif /* chips */
  43749 
  43750 #if defined(BCM_88675_A0)
  43751     { /* SOC_REG_INT_GRUND_BCM88675_A0r */
  43752         soc_block_list[2],
  43753         soc_portreg,
  43754         1,
  43755         0,
  43756         0xc00,
  43757         SOC_REG_FLAG_COUNTER,
  43758         0,
  43759         1,
  43760         soc_GRUNDr_fields,
  43761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43762         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43763         12,
  43764         -1,
  43765     },
  43766 #endif /* chips */
  43767 
  43768 #if defined(BCM_88675_B0)
  43769     { /* SOC_REG_INT_GRUND_BCM88675_B0r */
  43770         soc_block_list[2],
  43771         soc_portreg,
  43772         1,
  43773         0,
  43774         0xc00,
  43775         SOC_REG_FLAG_COUNTER,
  43776         0,
  43777         1,
  43778         soc_GRUND_BCM88675_B0r_fields,
  43779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43781         12,
  43782         -1,
  43783     },
  43784 #endif /* chips */
  43785 
  43786 #if defined(BCM_88680_A0)
  43787     { /* SOC_REG_INT_GRUND_BCM88680_A0r */
  43788         soc_block_list[2],
  43789         soc_portreg,
  43790         1,
  43791         0,
  43792         0xc00,
  43793         SOC_REG_FLAG_COUNTER,
  43794         0,
  43795         1,
  43796         soc_GRUND_BCM88680_A0r_fields,
  43797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43798         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43799         12,
  43800         -1,
  43801     },
  43802 #endif /* chips */
  43803 
  43804 #if defined(BCM_53570_A0)
  43805     { /* SOC_REG_INT_GRVMFPr */
  43806         soc_block_list[2],
  43807         soc_portreg,
  43808         1,
  43809         0,
  43810         0x8000,
  43811         SOC_REG_FLAG_COUNTER,
  43812         0,
  43813         1,
  43814         soc_GR1023_BCM53400_A0r_fields,
  43815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43816         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43817         282,
  43818         -1,
  43819     },
  43820 #endif /* chips */
  43821 
  43822 #if defined(BCM_53570_B0)
  43823     { /* SOC_REG_INT_GRVMFP_BCM53570_B0r */
  43824         soc_block_list[2],
  43825         soc_portreg,
  43826         1,
  43827         0,
  43828         0x8000,
  43829         SOC_REG_FLAG_COUNTER,
  43830         0,
  43831         1,
  43832         soc_GR1023_BCM53400_A0r_fields,
  43833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43835         286,
  43836         -1,
  43837     },
  43838 #endif /* chips */
  43839 
  43840 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  43841     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  43842     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  43843     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  43844     { /* SOC_REG_INT_GRXCFr */
  43845         soc_block_list[2],
  43846         soc_portreg,
  43847         1,
  43848         0,
  43849         0xf,
  43850         SOC_REG_FLAG_COUNTER,
  43851         0,
  43852         1,
  43853         soc_GR1023r_fields,
  43854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43855         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43856         49,
  43857         -1,
  43858     },
  43859 #endif /* chips */
  43860 
  43861 #if defined(BCM_53400_A0)
  43862     { /* SOC_REG_INT_GRXCF_BCM53400_A0r */
  43863         soc_block_list[9],
  43864         soc_portreg,
  43865         1,
  43866         0,
  43867         0x100,
  43868         SOC_REG_FLAG_COUNTER,
  43869         0,
  43870         1,
  43871         soc_GR1023_BCM53400_A0r_fields,
  43872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43874         100,
  43875         -1,
  43876     },
  43877 #endif /* chips */
  43878 
  43879 #if defined(BCM_53540_A0)
  43880     { /* SOC_REG_INT_GRXCF_BCM53540_A0r */
  43881         soc_block_list[2],
  43882         soc_portreg,
  43883         1,
  43884         0,
  43885         0x100,
  43886         SOC_REG_FLAG_COUNTER,
  43887         0,
  43888         1,
  43889         soc_GR1023_BCM53400_A0r_fields,
  43890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43892         100,
  43893         -1,
  43894     },
  43895 #endif /* chips */
  43896 
  43897 #if defined(BCM_53570_A0)
  43898     { /* SOC_REG_INT_GRXCF_BCM53570_A0r */
  43899         soc_block_list[2],
  43900         soc_portreg,
  43901         1,
  43902         0,
  43903         0x100,
  43904         SOC_REG_FLAG_COUNTER,
  43905         0,
  43906         1,
  43907         soc_GR1023_BCM53400_A0r_fields,
  43908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43909         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43910         155,
  43911         -1,
  43912     },
  43913 #endif /* chips */
  43914 
  43915 #if defined(BCM_53570_B0)
  43916     { /* SOC_REG_INT_GRXCF_BCM53570_B0r */
  43917         soc_block_list[2],
  43918         soc_portreg,
  43919         1,
  43920         0,
  43921         0x100,
  43922         SOC_REG_FLAG_COUNTER,
  43923         0,
  43924         1,
  43925         soc_GR1023_BCM53400_A0r_fields,
  43926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43927         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43928         159,
  43929         -1,
  43930     },
  43931 #endif /* chips */
  43932 
  43933 #if defined(BCM_56142_A0)
  43934     { /* SOC_REG_INT_GRXCF_BCM56142_A0r */
  43935         soc_block_list[210],
  43936         soc_portreg,
  43937         1,
  43938         0,
  43939         0x81,
  43940         SOC_REG_FLAG_COUNTER,
  43941         0,
  43942         1,
  43943         soc_GR1023r_fields,
  43944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43945         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43946         176,
  43947         -1,
  43948     },
  43949 #endif /* chips */
  43950 
  43951 #if defined(BCM_56150_A0)
  43952     { /* SOC_REG_INT_GRXCF_BCM56150_A0r */
  43953         soc_block_list[2],
  43954         soc_portreg,
  43955         1,
  43956         0,
  43957         0x100,
  43958         SOC_REG_FLAG_COUNTER,
  43959         0,
  43960         1,
  43961         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  43962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43963         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43964         96,
  43965         -1,
  43966     },
  43967 #endif /* chips */
  43968 
  43969 #if defined(BCM_56160_A0)
  43970     { /* SOC_REG_INT_GRXCF_BCM56160_A0r */
  43971         soc_block_list[2],
  43972         soc_portreg,
  43973         1,
  43974         0,
  43975         0x100,
  43976         SOC_REG_FLAG_COUNTER,
  43977         0,
  43978         1,
  43979         soc_GR1023_BCM53400_A0r_fields,
  43980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43981         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43982         100,
  43983         -1,
  43984     },
  43985 #endif /* chips */
  43986 
  43987 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  43988     { /* SOC_REG_INT_GRXCF_BCM56334_A0r */
  43989         soc_block_list[210],
  43990         soc_portreg,
  43991         1,
  43992         0,
  43993         0x81,
  43994         SOC_REG_FLAG_COUNTER,
  43995         0,
  43996         1,
  43997         soc_GR1023r_fields,
  43998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43999         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44000         171,
  44001         -1,
  44002     },
  44003 #endif /* chips */
  44004 
  44005 #if defined(BCM_56370_A0)
  44006     { /* SOC_REG_INT_GRXCF_BCM56370_A0r */
  44007         soc_block_list[9],
  44008         soc_portreg,
  44009         1,
  44010         0,
  44011         0x100,
  44012         SOC_REG_FLAG_COUNTER,
  44013         0,
  44014         1,
  44015         soc_GR1023_BCM53400_A0r_fields,
  44016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44017         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44018         61,
  44019         -1,
  44020         3,
  44021     },
  44022 #endif /* chips */
  44023 
  44024 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  44025     { /* SOC_REG_INT_GRXCF_BCM56440_A0r */
  44026         soc_block_list[2],
  44027         soc_portreg,
  44028         1,
  44029         0,
  44030         0x81,
  44031         SOC_REG_FLAG_COUNTER,
  44032         0,
  44033         1,
  44034         soc_GR1023r_fields,
  44035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44036         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44037         168,
  44038         -1,
  44039     },
  44040 #endif /* chips */
  44041 
  44042 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  44043     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  44044     { /* SOC_REG_INT_GRXCF_BCM56624_A0r */
  44045         soc_block_list[205],
  44046         soc_portreg,
  44047         1,
  44048         0,
  44049         0x8f,
  44050         SOC_REG_FLAG_COUNTER,
  44051         0,
  44052         1,
  44053         soc_GR1023r_fields,
  44054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44055         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44056         185,
  44057         -1,
  44058     },
  44059 #endif /* chips */
  44060 
  44061 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  44062     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  44063     { /* SOC_REG_INT_GRXCF_BCM56634_A0r */
  44064         soc_block_list[207],
  44065         soc_portreg,
  44066         1,
  44067         0,
  44068         0x8f,
  44069         SOC_REG_FLAG_COUNTER,
  44070         0,
  44071         1,
  44072         soc_GR1023r_fields,
  44073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44074         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44075         185,
  44076         -1,
  44077     },
  44078 #endif /* chips */
  44079 
  44080 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  44081     { /* SOC_REG_INT_GRXCF_BCM56685_A0r */
  44082         soc_block_list[209],
  44083         soc_portreg,
  44084         1,
  44085         0,
  44086         0x8f,
  44087         SOC_REG_FLAG_COUNTER,
  44088         0,
  44089         1,
  44090         soc_GR1023r_fields,
  44091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44092         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44093         185,
  44094         -1,
  44095     },
  44096 #endif /* chips */
  44097 
  44098 #if defined(BCM_56800_A0)
  44099     { /* SOC_REG_INT_GRXCF_BCM56800_A0r */
  44100         soc_block_list[9],
  44101         soc_portreg,
  44102         1,
  44103         0,
  44104         0x56,
  44105         SOC_REG_FLAG_COUNTER,
  44106         0,
  44107         1,
  44108         soc_GR1023r_fields,
  44109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44110         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44111         128,
  44112         -1,
  44113     },
  44114 #endif /* chips */
  44115 
  44116 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  44117     { /* SOC_REG_INT_GRXCF_BCM56820_A0r */
  44118         soc_block_list[206],
  44119         soc_portreg,
  44120         1,
  44121         0,
  44122         0x8f,
  44123         SOC_REG_FLAG_COUNTER,
  44124         0,
  44125         1,
  44126         soc_GR1023r_fields,
  44127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44128         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44129         195,
  44130         -1,
  44131     },
  44132 #endif /* chips */
  44133 
  44134 #if defined(BCM_88375_A0)
  44135     { /* SOC_REG_INT_GRXCF_BCM88375_A0r */
  44136         soc_block_list[2],
  44137         soc_portreg,
  44138         1,
  44139         0,
  44140         0x100,
  44141         SOC_REG_FLAG_COUNTER,
  44142         0,
  44143         1,
  44144         soc_GRXCF_BCM88375_A0r_fields,
  44145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44146         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44147         1,
  44148         -1,
  44149     },
  44150 #endif /* chips */
  44151 
  44152 #if defined(BCM_88375_B0)
  44153     { /* SOC_REG_INT_GRXCF_BCM88375_B0r */
  44154         soc_block_list[2],
  44155         soc_portreg,
  44156         1,
  44157         0,
  44158         0x100,
  44159         SOC_REG_FLAG_COUNTER,
  44160         0,
  44161         1,
  44162         soc_GRXCF_BCM88375_B0r_fields,
  44163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44164         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44165         1,
  44166         -1,
  44167     },
  44168 #endif /* chips */
  44169 
  44170 #if defined(BCM_88470_A0)
  44171     { /* SOC_REG_INT_GRXCF_BCM88470_A0r */
  44172         soc_block_list[2],
  44173         soc_portreg,
  44174         1,
  44175         0,
  44176         0x100,
  44177         SOC_REG_FLAG_COUNTER,
  44178         0,
  44179         1,
  44180         soc_GRXCF_BCM88470_A0r_fields,
  44181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44182         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44183         1,
  44184         -1,
  44185     },
  44186 #endif /* chips */
  44187 
  44188 #if defined(BCM_88470_B0)
  44189     { /* SOC_REG_INT_GRXCF_BCM88470_B0r */
  44190         soc_block_list[2],
  44191         soc_portreg,
  44192         1,
  44193         0,
  44194         0x100,
  44195         SOC_REG_FLAG_COUNTER,
  44196         0,
  44197         1,
  44198         soc_GRXCF_BCM88470_B0r_fields,
  44199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44200         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44201         1,
  44202         -1,
  44203     },
  44204 #endif /* chips */
  44205 
  44206 #if defined(BCM_88675_A0)
  44207     { /* SOC_REG_INT_GRXCF_BCM88675_A0r */
  44208         soc_block_list[2],
  44209         soc_portreg,
  44210         1,
  44211         0,
  44212         0x100,
  44213         SOC_REG_FLAG_COUNTER,
  44214         0,
  44215         1,
  44216         soc_GRXCFr_fields,
  44217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44219         1,
  44220         -1,
  44221     },
  44222 #endif /* chips */
  44223 
  44224 #if defined(BCM_88675_B0)
  44225     { /* SOC_REG_INT_GRXCF_BCM88675_B0r */
  44226         soc_block_list[2],
  44227         soc_portreg,
  44228         1,
  44229         0,
  44230         0x100,
  44231         SOC_REG_FLAG_COUNTER,
  44232         0,
  44233         1,
  44234         soc_GRXCF_BCM88675_B0r_fields,
  44235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44236         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44237         1,
  44238         -1,
  44239     },
  44240 #endif /* chips */
  44241 
  44242 #if defined(BCM_88680_A0)
  44243     { /* SOC_REG_INT_GRXCF_BCM88680_A0r */
  44244         soc_block_list[2],
  44245         soc_portreg,
  44246         1,
  44247         0,
  44248         0x100,
  44249         SOC_REG_FLAG_COUNTER,
  44250         0,
  44251         1,
  44252         soc_GRXCF_BCM88680_A0r_fields,
  44253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44254         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44255         1,
  44256         -1,
  44257     },
  44258 #endif /* chips */
  44259 
  44260 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  44261     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  44262     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  44263     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  44264     { /* SOC_REG_INT_GRXPFr */
  44265         soc_block_list[2],
  44266         soc_portreg,
  44267         1,
  44268         0,
  44269         0x10,
  44270         SOC_REG_FLAG_COUNTER,
  44271         0,
  44272         1,
  44273         soc_GR1023r_fields,
  44274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44275         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44276         50,
  44277         -1,
  44278     },
  44279 #endif /* chips */
  44280 
  44281 #if defined(BCM_53400_A0)
  44282     { /* SOC_REG_INT_GRXPF_BCM53400_A0r */
  44283         soc_block_list[9],
  44284         soc_portreg,
  44285         1,
  44286         0,
  44287         0x200,
  44288         SOC_REG_FLAG_COUNTER,
  44289         0,
  44290         1,
  44291         soc_GR1023_BCM53400_A0r_fields,
  44292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44293         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44294         101,
  44295         -1,
  44296     },
  44297 #endif /* chips */
  44298 
  44299 #if defined(BCM_53540_A0)
  44300     { /* SOC_REG_INT_GRXPF_BCM53540_A0r */
  44301         soc_block_list[2],
  44302         soc_portreg,
  44303         1,
  44304         0,
  44305         0x200,
  44306         SOC_REG_FLAG_COUNTER,
  44307         0,
  44308         1,
  44309         soc_GR1023_BCM53400_A0r_fields,
  44310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44312         101,
  44313         -1,
  44314     },
  44315 #endif /* chips */
  44316 
  44317 #if defined(BCM_53570_A0)
  44318     { /* SOC_REG_INT_GRXPF_BCM53570_A0r */
  44319         soc_block_list[2],
  44320         soc_portreg,
  44321         1,
  44322         0,
  44323         0x200,
  44324         SOC_REG_FLAG_COUNTER,
  44325         0,
  44326         1,
  44327         soc_GR1023_BCM53400_A0r_fields,
  44328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44329         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44330         156,
  44331         -1,
  44332     },
  44333 #endif /* chips */
  44334 
  44335 #if defined(BCM_53570_B0)
  44336     { /* SOC_REG_INT_GRXPF_BCM53570_B0r */
  44337         soc_block_list[2],
  44338         soc_portreg,
  44339         1,
  44340         0,
  44341         0x200,
  44342         SOC_REG_FLAG_COUNTER,
  44343         0,
  44344         1,
  44345         soc_GR1023_BCM53400_A0r_fields,
  44346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44347         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44348         160,
  44349         -1,
  44350     },
  44351 #endif /* chips */
  44352 
  44353 #if defined(BCM_56142_A0)
  44354     { /* SOC_REG_INT_GRXPF_BCM56142_A0r */
  44355         soc_block_list[210],
  44356         soc_portreg,
  44357         1,
  44358         0,
  44359         0x82,
  44360         SOC_REG_FLAG_COUNTER,
  44361         0,
  44362         1,
  44363         soc_GR1023r_fields,
  44364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44365         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44366         177,
  44367         -1,
  44368     },
  44369 #endif /* chips */
  44370 
  44371 #if defined(BCM_56150_A0)
  44372     { /* SOC_REG_INT_GRXPF_BCM56150_A0r */
  44373         soc_block_list[2],
  44374         soc_portreg,
  44375         1,
  44376         0,
  44377         0x200,
  44378         SOC_REG_FLAG_COUNTER,
  44379         0,
  44380         1,
  44381         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  44382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44384         97,
  44385         -1,
  44386     },
  44387 #endif /* chips */
  44388 
  44389 #if defined(BCM_56160_A0)
  44390     { /* SOC_REG_INT_GRXPF_BCM56160_A0r */
  44391         soc_block_list[2],
  44392         soc_portreg,
  44393         1,
  44394         0,
  44395         0x200,
  44396         SOC_REG_FLAG_COUNTER,
  44397         0,
  44398         1,
  44399         soc_GR1023_BCM53400_A0r_fields,
  44400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44402         101,
  44403         -1,
  44404     },
  44405 #endif /* chips */
  44406 
  44407 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  44408     { /* SOC_REG_INT_GRXPF_BCM56334_A0r */
  44409         soc_block_list[210],
  44410         soc_portreg,
  44411         1,
  44412         0,
  44413         0x82,
  44414         SOC_REG_FLAG_COUNTER,
  44415         0,
  44416         1,
  44417         soc_GR1023r_fields,
  44418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44419         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44420         172,
  44421         -1,
  44422     },
  44423 #endif /* chips */
  44424 
  44425 #if defined(BCM_56370_A0)
  44426     { /* SOC_REG_INT_GRXPF_BCM56370_A0r */
  44427         soc_block_list[9],
  44428         soc_portreg,
  44429         1,
  44430         0,
  44431         0x200,
  44432         SOC_REG_FLAG_COUNTER,
  44433         0,
  44434         1,
  44435         soc_GR1023_BCM53400_A0r_fields,
  44436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44438         62,
  44439         -1,
  44440         3,
  44441     },
  44442 #endif /* chips */
  44443 
  44444 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  44445     { /* SOC_REG_INT_GRXPF_BCM56440_A0r */
  44446         soc_block_list[2],
  44447         soc_portreg,
  44448         1,
  44449         0,
  44450         0x82,
  44451         SOC_REG_FLAG_COUNTER,
  44452         0,
  44453         1,
  44454         soc_GR1023r_fields,
  44455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44456         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44457         169,
  44458         -1,
  44459     },
  44460 #endif /* chips */
  44461 
  44462 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  44463     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  44464     { /* SOC_REG_INT_GRXPF_BCM56624_A0r */
  44465         soc_block_list[205],
  44466         soc_portreg,
  44467         1,
  44468         0,
  44469         0x90,
  44470         SOC_REG_FLAG_COUNTER,
  44471         0,
  44472         1,
  44473         soc_GR1023r_fields,
  44474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44475         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44476         186,
  44477         -1,
  44478     },
  44479 #endif /* chips */
  44480 
  44481 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  44482     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  44483     { /* SOC_REG_INT_GRXPF_BCM56634_A0r */
  44484         soc_block_list[207],
  44485         soc_portreg,
  44486         1,
  44487         0,
  44488         0x90,
  44489         SOC_REG_FLAG_COUNTER,
  44490         0,
  44491         1,
  44492         soc_GR1023r_fields,
  44493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44494         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44495         186,
  44496         -1,
  44497     },
  44498 #endif /* chips */
  44499 
  44500 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  44501     { /* SOC_REG_INT_GRXPF_BCM56685_A0r */
  44502         soc_block_list[209],
  44503         soc_portreg,
  44504         1,
  44505         0,
  44506         0x90,
  44507         SOC_REG_FLAG_COUNTER,
  44508         0,
  44509         1,
  44510         soc_GR1023r_fields,
  44511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44512         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44513         186,
  44514         -1,
  44515     },
  44516 #endif /* chips */
  44517 
  44518 #if defined(BCM_56800_A0)
  44519     { /* SOC_REG_INT_GRXPF_BCM56800_A0r */
  44520         soc_block_list[9],
  44521         soc_portreg,
  44522         1,
  44523         0,
  44524         0x57,
  44525         SOC_REG_FLAG_COUNTER,
  44526         0,
  44527         1,
  44528         soc_GR1023r_fields,
  44529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44530         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44531         129,
  44532         -1,
  44533     },
  44534 #endif /* chips */
  44535 
  44536 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  44537     { /* SOC_REG_INT_GRXPF_BCM56820_A0r */
  44538         soc_block_list[206],
  44539         soc_portreg,
  44540         1,
  44541         0,
  44542         0x90,
  44543         SOC_REG_FLAG_COUNTER,
  44544         0,
  44545         1,
  44546         soc_GR1023r_fields,
  44547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44548         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44549         196,
  44550         -1,
  44551     },
  44552 #endif /* chips */
  44553 
  44554 #if defined(BCM_88375_A0)
  44555     { /* SOC_REG_INT_GRXPF_BCM88375_A0r */
  44556         soc_block_list[2],
  44557         soc_portreg,
  44558         1,
  44559         0,
  44560         0x200,
  44561         SOC_REG_FLAG_COUNTER,
  44562         0,
  44563         1,
  44564         soc_GRXPF_BCM88375_A0r_fields,
  44565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44566         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44567         2,
  44568         -1,
  44569     },
  44570 #endif /* chips */
  44571 
  44572 #if defined(BCM_88375_B0)
  44573     { /* SOC_REG_INT_GRXPF_BCM88375_B0r */
  44574         soc_block_list[2],
  44575         soc_portreg,
  44576         1,
  44577         0,
  44578         0x200,
  44579         SOC_REG_FLAG_COUNTER,
  44580         0,
  44581         1,
  44582         soc_GRXPF_BCM88375_B0r_fields,
  44583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44584         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44585         2,
  44586         -1,
  44587     },
  44588 #endif /* chips */
  44589 
  44590 #if defined(BCM_88470_A0)
  44591     { /* SOC_REG_INT_GRXPF_BCM88470_A0r */
  44592         soc_block_list[2],
  44593         soc_portreg,
  44594         1,
  44595         0,
  44596         0x200,
  44597         SOC_REG_FLAG_COUNTER,
  44598         0,
  44599         1,
  44600         soc_GRXPF_BCM88470_A0r_fields,
  44601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44602         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44603         2,
  44604         -1,
  44605     },
  44606 #endif /* chips */
  44607 
  44608 #if defined(BCM_88470_B0)
  44609     { /* SOC_REG_INT_GRXPF_BCM88470_B0r */
  44610         soc_block_list[2],
  44611         soc_portreg,
  44612         1,
  44613         0,
  44614         0x200,
  44615         SOC_REG_FLAG_COUNTER,
  44616         0,
  44617         1,
  44618         soc_GRXPF_BCM88470_B0r_fields,
  44619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44620         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44621         2,
  44622         -1,
  44623     },
  44624 #endif /* chips */
  44625 
  44626 #if defined(BCM_88675_A0)
  44627     { /* SOC_REG_INT_GRXPF_BCM88675_A0r */
  44628         soc_block_list[2],
  44629         soc_portreg,
  44630         1,
  44631         0,
  44632         0x200,
  44633         SOC_REG_FLAG_COUNTER,
  44634         0,
  44635         1,
  44636         soc_GRXPFr_fields,
  44637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44638         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44639         2,
  44640         -1,
  44641     },
  44642 #endif /* chips */
  44643 
  44644 #if defined(BCM_88675_B0)
  44645     { /* SOC_REG_INT_GRXPF_BCM88675_B0r */
  44646         soc_block_list[2],
  44647         soc_portreg,
  44648         1,
  44649         0,
  44650         0x200,
  44651         SOC_REG_FLAG_COUNTER,
  44652         0,
  44653         1,
  44654         soc_GRXPF_BCM88675_B0r_fields,
  44655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44656         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44657         2,
  44658         -1,
  44659     },
  44660 #endif /* chips */
  44661 
  44662 #if defined(BCM_88680_A0)
  44663     { /* SOC_REG_INT_GRXPF_BCM88680_A0r */
  44664         soc_block_list[2],
  44665         soc_portreg,
  44666         1,
  44667         0,
  44668         0x200,
  44669         SOC_REG_FLAG_COUNTER,
  44670         0,
  44671         1,
  44672         soc_GRXPF_BCM88680_A0r_fields,
  44673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44674         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44675         2,
  44676         -1,
  44677     },
  44678 #endif /* chips */
  44679 
  44680 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  44681     { /* SOC_REG_INT_GRXPPr */
  44682         soc_block_list[206],
  44683         soc_portreg,
  44684         1,
  44685         0,
  44686         0x9b,
  44687         SOC_REG_FLAG_COUNTER |
  44688                           SOC_REG_FLAG_ED_CNTR,
  44689         0,
  44690         1,
  44691         soc_GR1023r_fields,
  44692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44693         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44694         207,
  44695         -1,
  44696     },
  44697 #endif /* chips */
  44698 
  44699 #if defined(BCM_53540_A0)
  44700     { /* SOC_REG_INT_GRXPP_BCM53540_A0r */
  44701         soc_block_list[2],
  44702         soc_portreg,
  44703         1,
  44704         0,
  44705         0x1f00,
  44706         SOC_REG_FLAG_COUNTER,
  44707         0,
  44708         1,
  44709         soc_GR1023_BCM53400_A0r_fields,
  44710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44711         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44712         130,
  44713         -1,
  44714     },
  44715 #endif /* chips */
  44716 
  44717 #if defined(BCM_53570_A0)
  44718     { /* SOC_REG_INT_GRXPP_BCM53570_A0r */
  44719         soc_block_list[2],
  44720         soc_portreg,
  44721         1,
  44722         0,
  44723         0x1f00,
  44724         SOC_REG_FLAG_COUNTER,
  44725         0,
  44726         1,
  44727         soc_GR1023_BCM53400_A0r_fields,
  44728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44729         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44730         185,
  44731         -1,
  44732     },
  44733 #endif /* chips */
  44734 
  44735 #if defined(BCM_53570_B0)
  44736     { /* SOC_REG_INT_GRXPP_BCM53570_B0r */
  44737         soc_block_list[2],
  44738         soc_portreg,
  44739         1,
  44740         0,
  44741         0x1f00,
  44742         SOC_REG_FLAG_COUNTER,
  44743         0,
  44744         1,
  44745         soc_GR1023_BCM53400_A0r_fields,
  44746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44747         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44748         189,
  44749         -1,
  44750     },
  44751 #endif /* chips */
  44752 
  44753 #if defined(BCM_56160_A0)
  44754     { /* SOC_REG_INT_GRXPP_BCM56160_A0r */
  44755         soc_block_list[2],
  44756         soc_portreg,
  44757         1,
  44758         0,
  44759         0x1f00,
  44760         SOC_REG_FLAG_COUNTER,
  44761         0,
  44762         1,
  44763         soc_GR1023_BCM53400_A0r_fields,
  44764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44765         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44766         130,
  44767         -1,
  44768     },
  44769 #endif /* chips */
  44770 
  44771 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  44772     defined(BCM_56504_B0)
  44773     { /* SOC_REG_INT_GRXUOr */
  44774         soc_block_list[2],
  44775         soc_portreg,
  44776         1,
  44777         0,
  44778         0x11,
  44779         SOC_REG_FLAG_COUNTER |
  44780                           SOC_REG_FLAG_ED_CNTR,
  44781         0,
  44782         1,
  44783         soc_GR1023r_fields,
  44784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44785         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44786         51,
  44787         -1,
  44788     },
  44789 #endif /* chips */
  44790 
  44791 #if defined(BCM_53400_A0)
  44792     { /* SOC_REG_INT_GRXUO_BCM53400_A0r */
  44793         soc_block_list[9],
  44794         soc_portreg,
  44795         1,
  44796         0,
  44797         0x300,
  44798         SOC_REG_FLAG_COUNTER,
  44799         0,
  44800         1,
  44801         soc_GR1023_BCM53400_A0r_fields,
  44802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44803         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44804         102,
  44805         -1,
  44806     },
  44807 #endif /* chips */
  44808 
  44809 #if defined(BCM_53540_A0)
  44810     { /* SOC_REG_INT_GRXUO_BCM53540_A0r */
  44811         soc_block_list[2],
  44812         soc_portreg,
  44813         1,
  44814         0,
  44815         0x300,
  44816         SOC_REG_FLAG_COUNTER,
  44817         0,
  44818         1,
  44819         soc_GR1023_BCM53400_A0r_fields,
  44820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44821         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44822         102,
  44823         -1,
  44824     },
  44825 #endif /* chips */
  44826 
  44827 #if defined(BCM_53570_A0)
  44828     { /* SOC_REG_INT_GRXUO_BCM53570_A0r */
  44829         soc_block_list[2],
  44830         soc_portreg,
  44831         1,
  44832         0,
  44833         0x300,
  44834         SOC_REG_FLAG_COUNTER,
  44835         0,
  44836         1,
  44837         soc_GR1023_BCM53400_A0r_fields,
  44838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44840         157,
  44841         -1,
  44842     },
  44843 #endif /* chips */
  44844 
  44845 #if defined(BCM_53570_B0)
  44846     { /* SOC_REG_INT_GRXUO_BCM53570_B0r */
  44847         soc_block_list[2],
  44848         soc_portreg,
  44849         1,
  44850         0,
  44851         0x300,
  44852         SOC_REG_FLAG_COUNTER,
  44853         0,
  44854         1,
  44855         soc_GR1023_BCM53400_A0r_fields,
  44856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44857         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44858         161,
  44859         -1,
  44860     },
  44861 #endif /* chips */
  44862 
  44863 #if defined(BCM_56142_A0)
  44864     { /* SOC_REG_INT_GRXUO_BCM56142_A0r */
  44865         soc_block_list[210],
  44866         soc_portreg,
  44867         1,
  44868         0,
  44869         0x83,
  44870         SOC_REG_FLAG_COUNTER,
  44871         0,
  44872         1,
  44873         soc_GR1023r_fields,
  44874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44875         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44876         178,
  44877         -1,
  44878     },
  44879 #endif /* chips */
  44880 
  44881 #if defined(BCM_56150_A0)
  44882     { /* SOC_REG_INT_GRXUO_BCM56150_A0r */
  44883         soc_block_list[2],
  44884         soc_portreg,
  44885         1,
  44886         0,
  44887         0x300,
  44888         SOC_REG_FLAG_COUNTER,
  44889         0,
  44890         1,
  44891         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  44892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44893         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44894         98,
  44895         -1,
  44896     },
  44897 #endif /* chips */
  44898 
  44899 #if defined(BCM_56160_A0)
  44900     { /* SOC_REG_INT_GRXUO_BCM56160_A0r */
  44901         soc_block_list[2],
  44902         soc_portreg,
  44903         1,
  44904         0,
  44905         0x300,
  44906         SOC_REG_FLAG_COUNTER,
  44907         0,
  44908         1,
  44909         soc_GR1023_BCM53400_A0r_fields,
  44910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44912         102,
  44913         -1,
  44914     },
  44915 #endif /* chips */
  44916 
  44917 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  44918     { /* SOC_REG_INT_GRXUO_BCM56334_A0r */
  44919         soc_block_list[210],
  44920         soc_portreg,
  44921         1,
  44922         0,
  44923         0x83,
  44924         SOC_REG_FLAG_COUNTER,
  44925         0,
  44926         1,
  44927         soc_GR1023r_fields,
  44928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44929         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44930         173,
  44931         -1,
  44932     },
  44933 #endif /* chips */
  44934 
  44935 #if defined(BCM_56370_A0)
  44936     { /* SOC_REG_INT_GRXUO_BCM56370_A0r */
  44937         soc_block_list[9],
  44938         soc_portreg,
  44939         1,
  44940         0,
  44941         0x300,
  44942         SOC_REG_FLAG_COUNTER,
  44943         0,
  44944         1,
  44945         soc_GR1023_BCM53400_A0r_fields,
  44946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44947         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44948         63,
  44949         -1,
  44950         3,
  44951     },
  44952 #endif /* chips */
  44953 
  44954 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  44955     { /* SOC_REG_INT_GRXUO_BCM56440_A0r */
  44956         soc_block_list[2],
  44957         soc_portreg,
  44958         1,
  44959         0,
  44960         0x83,
  44961         SOC_REG_FLAG_COUNTER,
  44962         0,
  44963         1,
  44964         soc_GR1023r_fields,
  44965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44966         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44967         170,
  44968         -1,
  44969     },
  44970 #endif /* chips */
  44971 
  44972 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  44973     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  44974     defined(BCM_56514_A0)
  44975     { /* SOC_REG_INT_GRXUO_BCM56514_A0r */
  44976         soc_block_list[2],
  44977         soc_portreg,
  44978         1,
  44979         0,
  44980         0x11,
  44981         SOC_REG_FLAG_COUNTER,
  44982         0,
  44983         1,
  44984         soc_GR1023r_fields,
  44985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44986         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44987         51,
  44988         -1,
  44989     },
  44990 #endif /* chips */
  44991 
  44992 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  44993     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  44994     { /* SOC_REG_INT_GRXUO_BCM56624_A0r */
  44995         soc_block_list[205],
  44996         soc_portreg,
  44997         1,
  44998         0,
  44999         0x91,
  45000         SOC_REG_FLAG_COUNTER,
  45001         0,
  45002         1,
  45003         soc_GR1023r_fields,
  45004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45006         187,
  45007         -1,
  45008     },
  45009 #endif /* chips */
  45010 
  45011 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  45012     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  45013     { /* SOC_REG_INT_GRXUO_BCM56634_A0r */
  45014         soc_block_list[207],
  45015         soc_portreg,
  45016         1,
  45017         0,
  45018         0x91,
  45019         SOC_REG_FLAG_COUNTER,
  45020         0,
  45021         1,
  45022         soc_GR1023r_fields,
  45023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45024         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45025         187,
  45026         -1,
  45027     },
  45028 #endif /* chips */
  45029 
  45030 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  45031     { /* SOC_REG_INT_GRXUO_BCM56685_A0r */
  45032         soc_block_list[209],
  45033         soc_portreg,
  45034         1,
  45035         0,
  45036         0x91,
  45037         SOC_REG_FLAG_COUNTER,
  45038         0,
  45039         1,
  45040         soc_GR1023r_fields,
  45041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45042         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45043         187,
  45044         -1,
  45045     },
  45046 #endif /* chips */
  45047 
  45048 #if defined(BCM_56800_A0)
  45049     { /* SOC_REG_INT_GRXUO_BCM56800_A0r */
  45050         soc_block_list[9],
  45051         soc_portreg,
  45052         1,
  45053         0,
  45054         0x58,
  45055         SOC_REG_FLAG_COUNTER,
  45056         0,
  45057         1,
  45058         soc_GR1023r_fields,
  45059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45060         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45061         130,
  45062         -1,
  45063     },
  45064 #endif /* chips */
  45065 
  45066 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  45067     { /* SOC_REG_INT_GRXUO_BCM56820_A0r */
  45068         soc_block_list[206],
  45069         soc_portreg,
  45070         1,
  45071         0,
  45072         0x91,
  45073         SOC_REG_FLAG_COUNTER,
  45074         0,
  45075         1,
  45076         soc_GR1023r_fields,
  45077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45078         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45079         197,
  45080         -1,
  45081     },
  45082 #endif /* chips */
  45083 
  45084 #if defined(BCM_88375_A0)
  45085     { /* SOC_REG_INT_GRXUO_BCM88375_A0r */
  45086         soc_block_list[2],
  45087         soc_portreg,
  45088         1,
  45089         0,
  45090         0x300,
  45091         SOC_REG_FLAG_COUNTER,
  45092         0,
  45093         1,
  45094         soc_GRXUO_BCM88375_A0r_fields,
  45095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45096         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45097         3,
  45098         -1,
  45099     },
  45100 #endif /* chips */
  45101 
  45102 #if defined(BCM_88375_B0)
  45103     { /* SOC_REG_INT_GRXUO_BCM88375_B0r */
  45104         soc_block_list[2],
  45105         soc_portreg,
  45106         1,
  45107         0,
  45108         0x300,
  45109         SOC_REG_FLAG_COUNTER,
  45110         0,
  45111         1,
  45112         soc_GRXUO_BCM88375_B0r_fields,
  45113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45114         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45115         3,
  45116         -1,
  45117     },
  45118 #endif /* chips */
  45119 
  45120 #if defined(BCM_88470_A0)
  45121     { /* SOC_REG_INT_GRXUO_BCM88470_A0r */
  45122         soc_block_list[2],
  45123         soc_portreg,
  45124         1,
  45125         0,
  45126         0x300,
  45127         SOC_REG_FLAG_COUNTER,
  45128         0,
  45129         1,
  45130         soc_GRXUO_BCM88470_A0r_fields,
  45131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45132         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45133         3,
  45134         -1,
  45135     },
  45136 #endif /* chips */
  45137 
  45138 #if defined(BCM_88470_B0)
  45139     { /* SOC_REG_INT_GRXUO_BCM88470_B0r */
  45140         soc_block_list[2],
  45141         soc_portreg,
  45142         1,
  45143         0,
  45144         0x300,
  45145         SOC_REG_FLAG_COUNTER,
  45146         0,
  45147         1,
  45148         soc_GRXUO_BCM88470_B0r_fields,
  45149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45150         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45151         3,
  45152         -1,
  45153     },
  45154 #endif /* chips */
  45155 
  45156 #if defined(BCM_88675_A0)
  45157     { /* SOC_REG_INT_GRXUO_BCM88675_A0r */
  45158         soc_block_list[2],
  45159         soc_portreg,
  45160         1,
  45161         0,
  45162         0x300,
  45163         SOC_REG_FLAG_COUNTER,
  45164         0,
  45165         1,
  45166         soc_GRXUOr_fields,
  45167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45168         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45169         3,
  45170         -1,
  45171     },
  45172 #endif /* chips */
  45173 
  45174 #if defined(BCM_88675_B0)
  45175     { /* SOC_REG_INT_GRXUO_BCM88675_B0r */
  45176         soc_block_list[2],
  45177         soc_portreg,
  45178         1,
  45179         0,
  45180         0x300,
  45181         SOC_REG_FLAG_COUNTER,
  45182         0,
  45183         1,
  45184         soc_GRXUO_BCM88675_B0r_fields,
  45185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45186         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45187         3,
  45188         -1,
  45189     },
  45190 #endif /* chips */
  45191 
  45192 #if defined(BCM_88680_A0)
  45193     { /* SOC_REG_INT_GRXUO_BCM88680_A0r */
  45194         soc_block_list[2],
  45195         soc_portreg,
  45196         1,
  45197         0,
  45198         0x300,
  45199         SOC_REG_FLAG_COUNTER,
  45200         0,
  45201         1,
  45202         soc_GRXUO_BCM88680_A0r_fields,
  45203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45204         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45205         3,
  45206         -1,
  45207     },
  45208 #endif /* chips */
  45209 
  45210 #if defined(BCM_88675_A0)
  45211     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTERr */
  45212         soc_block_list[2],
  45213         soc_portreg,
  45214         1,
  45215         0,
  45216         0x3d00,
  45217         SOC_REG_FLAG_COUNTER,
  45218         0,
  45219         1,
  45220         soc_GRX_EEE_LPI_DURATION_COUNTERr_fields,
  45221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45222         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45223         61,
  45224         -1,
  45225     },
  45226 #endif /* chips */
  45227 
  45228 #if defined(BCM_53400_A0)
  45229     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM53400_A0r */
  45230         soc_block_list[9],
  45231         soc_portreg,
  45232         1,
  45233         0,
  45234         0x3d00,
  45235         SOC_REG_FLAG_COUNTER,
  45236         0,
  45237         1,
  45238         soc_GR1023_BCM53400_A0r_fields,
  45239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45240         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45241         160,
  45242         -1,
  45243     },
  45244 #endif /* chips */
  45245 
  45246 #if defined(BCM_53540_A0)
  45247     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM53540_A0r */
  45248         soc_block_list[2],
  45249         soc_portreg,
  45250         1,
  45251         0,
  45252         0x5700,
  45253         SOC_REG_FLAG_COUNTER,
  45254         0,
  45255         1,
  45256         soc_GR1023_BCM53400_A0r_fields,
  45257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45258         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45259         186,
  45260         -1,
  45261     },
  45262 #endif /* chips */
  45263 
  45264 #if defined(BCM_53570_A0)
  45265     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM53570_A0r */
  45266         soc_block_list[2],
  45267         soc_portreg,
  45268         1,
  45269         0,
  45270         0x5f00,
  45271         SOC_REG_FLAG_COUNTER,
  45272         0,
  45273         1,
  45274         soc_GR1023_BCM53400_A0r_fields,
  45275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45276         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45277         249,
  45278         -1,
  45279     },
  45280 #endif /* chips */
  45281 
  45282 #if defined(BCM_53570_B0)
  45283     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM53570_B0r */
  45284         soc_block_list[2],
  45285         soc_portreg,
  45286         1,
  45287         0,
  45288         0x5f00,
  45289         SOC_REG_FLAG_COUNTER,
  45290         0,
  45291         1,
  45292         soc_GR1023_BCM53400_A0r_fields,
  45293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45294         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45295         253,
  45296         -1,
  45297     },
  45298 #endif /* chips */
  45299 
  45300 #if defined(BCM_56150_A0)
  45301     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM56150_A0r */
  45302         soc_block_list[2],
  45303         soc_portreg,
  45304         1,
  45305         0,
  45306         0x3d00,
  45307         SOC_REG_FLAG_COUNTER,
  45308         0,
  45309         1,
  45310         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  45311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45312         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45313         156,
  45314         -1,
  45315     },
  45316 #endif /* chips */
  45317 
  45318 #if defined(BCM_56160_A0)
  45319     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM56160_A0r */
  45320         soc_block_list[2],
  45321         soc_portreg,
  45322         1,
  45323         0,
  45324         0x5700,
  45325         SOC_REG_FLAG_COUNTER,
  45326         0,
  45327         1,
  45328         soc_GR1023_BCM53400_A0r_fields,
  45329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45331         186,
  45332         -1,
  45333     },
  45334 #endif /* chips */
  45335 
  45336 #if defined(BCM_56370_A0)
  45337     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM56370_A0r */
  45338         soc_block_list[9],
  45339         soc_portreg,
  45340         1,
  45341         0,
  45342         0x3f00,
  45343         SOC_REG_FLAG_COUNTER,
  45344         0,
  45345         1,
  45346         soc_GR1023_BCM53400_A0r_fields,
  45347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45348         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45349         123,
  45350         -1,
  45351         3,
  45352     },
  45353 #endif /* chips */
  45354 
  45355 #if defined(BCM_88375_A0)
  45356     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM88375_A0r */
  45357         soc_block_list[2],
  45358         soc_portreg,
  45359         1,
  45360         0,
  45361         0x3d00,
  45362         SOC_REG_FLAG_COUNTER,
  45363         0,
  45364         1,
  45365         soc_GRX_EEE_LPI_DURATION_COUNTER_BCM88375_A0r_fields,
  45366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45367         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45368         61,
  45369         -1,
  45370     },
  45371 #endif /* chips */
  45372 
  45373 #if defined(BCM_88375_B0)
  45374     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM88375_B0r */
  45375         soc_block_list[2],
  45376         soc_portreg,
  45377         1,
  45378         0,
  45379         0x3d00,
  45380         SOC_REG_FLAG_COUNTER,
  45381         0,
  45382         1,
  45383         soc_GRX_EEE_LPI_DURATION_COUNTER_BCM88375_B0r_fields,
  45384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45385         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45386         61,
  45387         -1,
  45388     },
  45389 #endif /* chips */
  45390 
  45391 #if defined(BCM_88470_A0)
  45392     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM88470_A0r */
  45393         soc_block_list[2],
  45394         soc_portreg,
  45395         1,
  45396         0,
  45397         0x3d00,
  45398         SOC_REG_FLAG_COUNTER,
  45399         0,
  45400         1,
  45401         soc_GRX_EEE_LPI_DURATION_COUNTER_BCM88470_A0r_fields,
  45402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45403         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45404         61,
  45405         -1,
  45406     },
  45407 #endif /* chips */
  45408 
  45409 #if defined(BCM_88470_B0)
  45410     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM88470_B0r */
  45411         soc_block_list[2],
  45412         soc_portreg,
  45413         1,
  45414         0,
  45415         0x3d00,
  45416         SOC_REG_FLAG_COUNTER,
  45417         0,
  45418         1,
  45419         soc_GRX_EEE_LPI_DURATION_COUNTER_BCM88470_B0r_fields,
  45420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45421         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45422         61,
  45423         -1,
  45424     },
  45425 #endif /* chips */
  45426 
  45427 #if defined(BCM_88675_B0)
  45428     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM88675_B0r */
  45429         soc_block_list[2],
  45430         soc_portreg,
  45431         1,
  45432         0,
  45433         0x3d00,
  45434         SOC_REG_FLAG_COUNTER,
  45435         0,
  45436         1,
  45437         soc_GRX_EEE_LPI_DURATION_COUNTER_BCM88675_B0r_fields,
  45438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45439         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45440         61,
  45441         -1,
  45442     },
  45443 #endif /* chips */
  45444 
  45445 #if defined(BCM_88680_A0)
  45446     { /* SOC_REG_INT_GRX_EEE_LPI_DURATION_COUNTER_BCM88680_A0r */
  45447         soc_block_list[2],
  45448         soc_portreg,
  45449         1,
  45450         0,
  45451         0x3d00,
  45452         SOC_REG_FLAG_COUNTER,
  45453         0,
  45454         1,
  45455         soc_GRX_EEE_LPI_DURATION_COUNTER_BCM88680_A0r_fields,
  45456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45457         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45458         61,
  45459         -1,
  45460     },
  45461 #endif /* chips */
  45462 
  45463 #if defined(BCM_88675_A0)
  45464     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTERr */
  45465         soc_block_list[2],
  45466         soc_portreg,
  45467         1,
  45468         0,
  45469         0x3c00,
  45470         SOC_REG_FLAG_COUNTER,
  45471         0,
  45472         1,
  45473         soc_GRX_EEE_LPI_EVENT_COUNTERr_fields,
  45474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45475         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45476         60,
  45477         -1,
  45478     },
  45479 #endif /* chips */
  45480 
  45481 #if defined(BCM_53400_A0)
  45482     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM53400_A0r */
  45483         soc_block_list[9],
  45484         soc_portreg,
  45485         1,
  45486         0,
  45487         0x3c00,
  45488         SOC_REG_FLAG_COUNTER,
  45489         0,
  45490         1,
  45491         soc_GR1023_BCM53400_A0r_fields,
  45492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45493         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45494         159,
  45495         -1,
  45496     },
  45497 #endif /* chips */
  45498 
  45499 #if defined(BCM_53540_A0)
  45500     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM53540_A0r */
  45501         soc_block_list[2],
  45502         soc_portreg,
  45503         1,
  45504         0,
  45505         0x5600,
  45506         SOC_REG_FLAG_COUNTER,
  45507         0,
  45508         1,
  45509         soc_GR1023_BCM53400_A0r_fields,
  45510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45511         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45512         185,
  45513         -1,
  45514     },
  45515 #endif /* chips */
  45516 
  45517 #if defined(BCM_53570_A0)
  45518     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM53570_A0r */
  45519         soc_block_list[2],
  45520         soc_portreg,
  45521         1,
  45522         0,
  45523         0x5e00,
  45524         SOC_REG_FLAG_COUNTER,
  45525         0,
  45526         1,
  45527         soc_GR1023_BCM53400_A0r_fields,
  45528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45529         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45530         248,
  45531         -1,
  45532     },
  45533 #endif /* chips */
  45534 
  45535 #if defined(BCM_53570_B0)
  45536     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM53570_B0r */
  45537         soc_block_list[2],
  45538         soc_portreg,
  45539         1,
  45540         0,
  45541         0x5e00,
  45542         SOC_REG_FLAG_COUNTER,
  45543         0,
  45544         1,
  45545         soc_GR1023_BCM53400_A0r_fields,
  45546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45547         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45548         252,
  45549         -1,
  45550     },
  45551 #endif /* chips */
  45552 
  45553 #if defined(BCM_56150_A0)
  45554     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM56150_A0r */
  45555         soc_block_list[2],
  45556         soc_portreg,
  45557         1,
  45558         0,
  45559         0x3c00,
  45560         SOC_REG_FLAG_COUNTER,
  45561         0,
  45562         1,
  45563         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  45564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45565         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45566         155,
  45567         -1,
  45568     },
  45569 #endif /* chips */
  45570 
  45571 #if defined(BCM_56160_A0)
  45572     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM56160_A0r */
  45573         soc_block_list[2],
  45574         soc_portreg,
  45575         1,
  45576         0,
  45577         0x5600,
  45578         SOC_REG_FLAG_COUNTER,
  45579         0,
  45580         1,
  45581         soc_GR1023_BCM53400_A0r_fields,
  45582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45584         185,
  45585         -1,
  45586     },
  45587 #endif /* chips */
  45588 
  45589 #if defined(BCM_56370_A0)
  45590     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM56370_A0r */
  45591         soc_block_list[9],
  45592         soc_portreg,
  45593         1,
  45594         0,
  45595         0x3e00,
  45596         SOC_REG_FLAG_COUNTER,
  45597         0,
  45598         1,
  45599         soc_GR1023_BCM53400_A0r_fields,
  45600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45602         122,
  45603         -1,
  45604         3,
  45605     },
  45606 #endif /* chips */
  45607 
  45608 #if defined(BCM_88375_A0)
  45609     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM88375_A0r */
  45610         soc_block_list[2],
  45611         soc_portreg,
  45612         1,
  45613         0,
  45614         0x3c00,
  45615         SOC_REG_FLAG_COUNTER,
  45616         0,
  45617         1,
  45618         soc_GRX_EEE_LPI_EVENT_COUNTER_BCM88375_A0r_fields,
  45619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45620         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45621         60,
  45622         -1,
  45623     },
  45624 #endif /* chips */
  45625 
  45626 #if defined(BCM_88375_B0)
  45627     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM88375_B0r */
  45628         soc_block_list[2],
  45629         soc_portreg,
  45630         1,
  45631         0,
  45632         0x3c00,
  45633         SOC_REG_FLAG_COUNTER,
  45634         0,
  45635         1,
  45636         soc_GRX_EEE_LPI_EVENT_COUNTER_BCM88375_B0r_fields,
  45637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45638         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45639         60,
  45640         -1,
  45641     },
  45642 #endif /* chips */
  45643 
  45644 #if defined(BCM_88470_A0)
  45645     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM88470_A0r */
  45646         soc_block_list[2],
  45647         soc_portreg,
  45648         1,
  45649         0,
  45650         0x3c00,
  45651         SOC_REG_FLAG_COUNTER,
  45652         0,
  45653         1,
  45654         soc_GRX_EEE_LPI_EVENT_COUNTER_BCM88470_A0r_fields,
  45655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45656         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45657         60,
  45658         -1,
  45659     },
  45660 #endif /* chips */
  45661 
  45662 #if defined(BCM_88470_B0)
  45663     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM88470_B0r */
  45664         soc_block_list[2],
  45665         soc_portreg,
  45666         1,
  45667         0,
  45668         0x3c00,
  45669         SOC_REG_FLAG_COUNTER,
  45670         0,
  45671         1,
  45672         soc_GRX_EEE_LPI_EVENT_COUNTER_BCM88470_B0r_fields,
  45673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45674         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45675         60,
  45676         -1,
  45677     },
  45678 #endif /* chips */
  45679 
  45680 #if defined(BCM_88675_B0)
  45681     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM88675_B0r */
  45682         soc_block_list[2],
  45683         soc_portreg,
  45684         1,
  45685         0,
  45686         0x3c00,
  45687         SOC_REG_FLAG_COUNTER,
  45688         0,
  45689         1,
  45690         soc_GRX_EEE_LPI_EVENT_COUNTER_BCM88675_B0r_fields,
  45691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45692         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45693         60,
  45694         -1,
  45695     },
  45696 #endif /* chips */
  45697 
  45698 #if defined(BCM_88680_A0)
  45699     { /* SOC_REG_INT_GRX_EEE_LPI_EVENT_COUNTER_BCM88680_A0r */
  45700         soc_block_list[2],
  45701         soc_portreg,
  45702         1,
  45703         0,
  45704         0x3c00,
  45705         SOC_REG_FLAG_COUNTER,
  45706         0,
  45707         1,
  45708         soc_GRX_EEE_LPI_EVENT_COUNTER_BCM88680_A0r_fields,
  45709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45710         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45711         60,
  45712         -1,
  45713     },
  45714 #endif /* chips */
  45715 
  45716 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45717     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  45718     { /* SOC_REG_INT_GSA0r */
  45719         soc_block_list[2],
  45720         soc_portreg,
  45721         1,
  45722         0,
  45723         0x104,
  45724         0,
  45725         0,
  45726         1,
  45727         soc_GSA0r_fields,
  45728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45729         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45730         -1,
  45731         -1,
  45732     },
  45733 #endif /* chips */
  45734 
  45735 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45736     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  45737     { /* SOC_REG_INT_GSA1r */
  45738         soc_block_list[2],
  45739         soc_portreg,
  45740         1,
  45741         0,
  45742         0x105,
  45743         0,
  45744         0,
  45745         1,
  45746         soc_GSA1r_fields,
  45747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45748         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45749         -1,
  45750         -1,
  45751     },
  45752 #endif /* chips */
  45753 
  45754 #if defined(BCM_56800_A0)
  45755     { /* SOC_REG_INT_GSA0_BCM56800_A0r */
  45756         soc_block_list[9],
  45757         soc_portreg,
  45758         1,
  45759         0,
  45760         0x104,
  45761         0,
  45762         0,
  45763         1,
  45764         soc_GSA0r_fields,
  45765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45766         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45767         -1,
  45768         -1,
  45769     },
  45770 #endif /* chips */
  45771 
  45772 #if defined(BCM_56800_A0)
  45773     { /* SOC_REG_INT_GSA1_BCM56800_A0r */
  45774         soc_block_list[9],
  45775         soc_portreg,
  45776         1,
  45777         0,
  45778         0x105,
  45779         0,
  45780         0,
  45781         1,
  45782         soc_GSA1r_fields,
  45783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45784         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45785         -1,
  45786         -1,
  45787     },
  45788 #endif /* chips */
  45789 
  45790 #if defined(BCM_88732_A0)
  45791     { /* SOC_REG_INT_GSBU_OVERSUB_FC_CONFIG1r */
  45792         soc_block_list[4],
  45793         soc_genreg,
  45794         1,
  45795         0,
  45796         0xb080061,
  45797         0,
  45798         0,
  45799         6,
  45800         soc_GSBU_OVERSUB_FC_CONFIG1r_fields,
  45801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45802         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  45803         -1,
  45804         -1,
  45805     },
  45806 #endif /* chips */
  45807 
  45808 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45809     defined(BCM_56504_B0)
  45810     { /* SOC_REG_INT_GT64r */
  45811         soc_block_list[2],
  45812         soc_portreg,
  45813         1,
  45814         0,
  45815         0x1d,
  45816         SOC_REG_FLAG_COUNTER,
  45817         0,
  45818         1,
  45819         soc_GR1023r_fields,
  45820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45821         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45822         63,
  45823         -1,
  45824     },
  45825 #endif /* chips */
  45826 
  45827 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45828     defined(BCM_56504_B0)
  45829     { /* SOC_REG_INT_GT127r */
  45830         soc_block_list[2],
  45831         soc_portreg,
  45832         1,
  45833         0,
  45834         0x1e,
  45835         SOC_REG_FLAG_COUNTER,
  45836         0,
  45837         1,
  45838         soc_GR1023r_fields,
  45839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45840         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45841         64,
  45842         -1,
  45843     },
  45844 #endif /* chips */
  45845 
  45846 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45847     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  45848     { /* SOC_REG_INT_GT255r */
  45849         soc_block_list[2],
  45850         soc_portreg,
  45851         1,
  45852         0,
  45853         0x1f,
  45854         SOC_REG_FLAG_COUNTER,
  45855         0,
  45856         1,
  45857         soc_GR1023r_fields,
  45858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45859         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45860         65,
  45861         -1,
  45862     },
  45863 #endif /* chips */
  45864 
  45865 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45866     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  45867     { /* SOC_REG_INT_GT511r */
  45868         soc_block_list[2],
  45869         soc_portreg,
  45870         1,
  45871         0,
  45872         0x20,
  45873         SOC_REG_FLAG_COUNTER,
  45874         0,
  45875         1,
  45876         soc_GR1023r_fields,
  45877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45878         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45879         66,
  45880         -1,
  45881     },
  45882 #endif /* chips */
  45883 
  45884 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45885     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  45886     { /* SOC_REG_INT_GT1023r */
  45887         soc_block_list[2],
  45888         soc_portreg,
  45889         1,
  45890         0,
  45891         0x21,
  45892         SOC_REG_FLAG_COUNTER,
  45893         0,
  45894         1,
  45895         soc_GR1023r_fields,
  45896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45898         67,
  45899         -1,
  45900     },
  45901 #endif /* chips */
  45902 
  45903 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45904     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  45905     { /* SOC_REG_INT_GT1518r */
  45906         soc_block_list[2],
  45907         soc_portreg,
  45908         1,
  45909         0,
  45910         0x22,
  45911         SOC_REG_FLAG_COUNTER,
  45912         0,
  45913         1,
  45914         soc_GR1023r_fields,
  45915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45916         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45917         68,
  45918         -1,
  45919     },
  45920 #endif /* chips */
  45921 
  45922 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45923     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  45924     { /* SOC_REG_INT_GT2047r */
  45925         soc_block_list[2],
  45926         soc_portreg,
  45927         1,
  45928         0,
  45929         0x24,
  45930         SOC_REG_FLAG_COUNTER,
  45931         0,
  45932         1,
  45933         soc_GR1023r_fields,
  45934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45936         70,
  45937         -1,
  45938     },
  45939 #endif /* chips */
  45940 
  45941 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45942     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  45943     { /* SOC_REG_INT_GT4095r */
  45944         soc_block_list[2],
  45945         soc_portreg,
  45946         1,
  45947         0,
  45948         0x25,
  45949         SOC_REG_FLAG_COUNTER,
  45950         0,
  45951         1,
  45952         soc_GR1023r_fields,
  45953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45954         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45955         71,
  45956         -1,
  45957     },
  45958 #endif /* chips */
  45959 
  45960 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  45961     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  45962     { /* SOC_REG_INT_GT9216r */
  45963         soc_block_list[2],
  45964         soc_portreg,
  45965         1,
  45966         0,
  45967         0x26,
  45968         SOC_REG_FLAG_COUNTER,
  45969         0,
  45970         1,
  45971         soc_GR1023r_fields,
  45972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45973         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45974         72,
  45975         -1,
  45976     },
  45977 #endif /* chips */
  45978 
  45979 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45980     { /* SOC_REG_INT_GT16383r */
  45981         soc_block_list[2],
  45982         soc_portreg,
  45983         1,
  45984         0,
  45985         0xb9,
  45986         SOC_REG_FLAG_COUNTER,
  45987         0,
  45988         1,
  45989         soc_GR1023r_fields,
  45990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45992         224,
  45993         -1,
  45994     },
  45995 #endif /* chips */
  45996 
  45997 #if defined(BCM_53570_A0)
  45998     { /* SOC_REG_INT_GT1023Pr */
  45999         soc_block_list[2],
  46000         soc_portreg,
  46001         1,
  46002         0,
  46003         0x9800,
  46004         SOC_REG_FLAG_COUNTER,
  46005         0,
  46006         1,
  46007         soc_GR1023_BCM53400_A0r_fields,
  46008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46010         306,
  46011         -1,
  46012     },
  46013 #endif /* chips */
  46014 
  46015 #if defined(BCM_53570_B0)
  46016     { /* SOC_REG_INT_GT1023P_BCM53570_B0r */
  46017         soc_block_list[2],
  46018         soc_portreg,
  46019         1,
  46020         0,
  46021         0x9800,
  46022         SOC_REG_FLAG_COUNTER,
  46023         0,
  46024         1,
  46025         soc_GR1023_BCM53400_A0r_fields,
  46026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46027         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46028         310,
  46029         -1,
  46030     },
  46031 #endif /* chips */
  46032 
  46033 #if defined(BCM_53400_A0)
  46034     { /* SOC_REG_INT_GT1023_BCM53400_A0r */
  46035         soc_block_list[9],
  46036         soc_portreg,
  46037         1,
  46038         0,
  46039         0x3200,
  46040         SOC_REG_FLAG_COUNTER,
  46041         0,
  46042         1,
  46043         soc_GR1023_BCM53400_A0r_fields,
  46044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46046         149,
  46047         -1,
  46048     },
  46049 #endif /* chips */
  46050 
  46051 #if defined(BCM_53540_A0)
  46052     { /* SOC_REG_INT_GT1023_BCM53540_A0r */
  46053         soc_block_list[2],
  46054         soc_portreg,
  46055         1,
  46056         0,
  46057         0x4300,
  46058         SOC_REG_FLAG_COUNTER,
  46059         0,
  46060         1,
  46061         soc_GR1023_BCM53400_A0r_fields,
  46062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46064         166,
  46065         -1,
  46066     },
  46067 #endif /* chips */
  46068 
  46069 #if defined(BCM_53570_A0)
  46070     { /* SOC_REG_INT_GT1023_BCM53570_A0r */
  46071         soc_block_list[2],
  46072         soc_portreg,
  46073         1,
  46074         0,
  46075         0x4300,
  46076         SOC_REG_FLAG_COUNTER,
  46077         0,
  46078         1,
  46079         soc_GR1023_BCM53400_A0r_fields,
  46080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46081         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46082         221,
  46083         -1,
  46084     },
  46085 #endif /* chips */
  46086 
  46087 #if defined(BCM_53570_B0)
  46088     { /* SOC_REG_INT_GT1023_BCM53570_B0r */
  46089         soc_block_list[2],
  46090         soc_portreg,
  46091         1,
  46092         0,
  46093         0x4300,
  46094         SOC_REG_FLAG_COUNTER,
  46095         0,
  46096         1,
  46097         soc_GR1023_BCM53400_A0r_fields,
  46098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46100         225,
  46101         -1,
  46102     },
  46103 #endif /* chips */
  46104 
  46105 #if defined(BCM_56142_A0)
  46106     { /* SOC_REG_INT_GT1023_BCM56142_A0r */
  46107         soc_block_list[210],
  46108         soc_portreg,
  46109         1,
  46110         0,
  46111         0xb2,
  46112         SOC_REG_FLAG_COUNTER,
  46113         0,
  46114         1,
  46115         soc_GR1023r_fields,
  46116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46118         225,
  46119         -1,
  46120     },
  46121 #endif /* chips */
  46122 
  46123 #if defined(BCM_56150_A0)
  46124     { /* SOC_REG_INT_GT1023_BCM56150_A0r */
  46125         soc_block_list[2],
  46126         soc_portreg,
  46127         1,
  46128         0,
  46129         0x3200,
  46130         SOC_REG_FLAG_COUNTER,
  46131         0,
  46132         1,
  46133         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  46134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46136         145,
  46137         -1,
  46138     },
  46139 #endif /* chips */
  46140 
  46141 #if defined(BCM_56160_A0)
  46142     { /* SOC_REG_INT_GT1023_BCM56160_A0r */
  46143         soc_block_list[2],
  46144         soc_portreg,
  46145         1,
  46146         0,
  46147         0x4300,
  46148         SOC_REG_FLAG_COUNTER,
  46149         0,
  46150         1,
  46151         soc_GR1023_BCM53400_A0r_fields,
  46152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46153         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46154         166,
  46155         -1,
  46156     },
  46157 #endif /* chips */
  46158 
  46159 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  46160     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  46161     { /* SOC_REG_INT_GT1023_BCM56224_A0r */
  46162         soc_block_list[2],
  46163         soc_portreg,
  46164         1,
  46165         0,
  46166         0x32,
  46167         SOC_REG_FLAG_COUNTER,
  46168         0,
  46169         1,
  46170         soc_GR1023r_fields,
  46171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46172         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46173         84,
  46174         -1,
  46175     },
  46176 #endif /* chips */
  46177 
  46178 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  46179     { /* SOC_REG_INT_GT1023_BCM56334_A0r */
  46180         soc_block_list[210],
  46181         soc_portreg,
  46182         1,
  46183         0,
  46184         0xb2,
  46185         SOC_REG_FLAG_COUNTER,
  46186         0,
  46187         1,
  46188         soc_GR1023r_fields,
  46189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46190         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46191         220,
  46192         -1,
  46193     },
  46194 #endif /* chips */
  46195 
  46196 #if defined(BCM_56370_A0)
  46197     { /* SOC_REG_INT_GT1023_BCM56370_A0r */
  46198         soc_block_list[9],
  46199         soc_portreg,
  46200         1,
  46201         0,
  46202         0x3300,
  46203         SOC_REG_FLAG_COUNTER,
  46204         0,
  46205         1,
  46206         soc_GR1023_BCM53400_A0r_fields,
  46207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46208         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46209         111,
  46210         -1,
  46211         3,
  46212     },
  46213 #endif /* chips */
  46214 
  46215 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46216     { /* SOC_REG_INT_GT1023_BCM56440_A0r */
  46217         soc_block_list[2],
  46218         soc_portreg,
  46219         1,
  46220         0,
  46221         0xb3,
  46222         SOC_REG_FLAG_COUNTER,
  46223         0,
  46224         1,
  46225         soc_GR1023r_fields,
  46226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46227         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46228         218,
  46229         -1,
  46230     },
  46231 #endif /* chips */
  46232 
  46233 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  46234     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  46235     { /* SOC_REG_INT_GT1023_BCM56624_A0r */
  46236         soc_block_list[205],
  46237         soc_portreg,
  46238         1,
  46239         0,
  46240         0xa3,
  46241         SOC_REG_FLAG_COUNTER,
  46242         0,
  46243         1,
  46244         soc_GR1023r_fields,
  46245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46246         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46247         205,
  46248         -1,
  46249     },
  46250 #endif /* chips */
  46251 
  46252 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  46253     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  46254     { /* SOC_REG_INT_GT1023_BCM56634_A0r */
  46255         soc_block_list[207],
  46256         soc_portreg,
  46257         1,
  46258         0,
  46259         0xa3,
  46260         SOC_REG_FLAG_COUNTER,
  46261         0,
  46262         1,
  46263         soc_GR1023r_fields,
  46264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46265         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46266         205,
  46267         -1,
  46268     },
  46269 #endif /* chips */
  46270 
  46271 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  46272     { /* SOC_REG_INT_GT1023_BCM56685_A0r */
  46273         soc_block_list[209],
  46274         soc_portreg,
  46275         1,
  46276         0,
  46277         0xa3,
  46278         SOC_REG_FLAG_COUNTER,
  46279         0,
  46280         1,
  46281         soc_GR1023r_fields,
  46282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46284         205,
  46285         -1,
  46286     },
  46287 #endif /* chips */
  46288 
  46289 #if defined(BCM_56800_A0)
  46290     { /* SOC_REG_INT_GT1023_BCM56800_A0r */
  46291         soc_block_list[9],
  46292         soc_portreg,
  46293         1,
  46294         0,
  46295         0x68,
  46296         SOC_REG_FLAG_COUNTER,
  46297         0,
  46298         1,
  46299         soc_GR1023r_fields,
  46300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46302         146,
  46303         -1,
  46304     },
  46305 #endif /* chips */
  46306 
  46307 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  46308     { /* SOC_REG_INT_GT1023_BCM56820_A0r */
  46309         soc_block_list[206],
  46310         soc_portreg,
  46311         1,
  46312         0,
  46313         0xa4,
  46314         SOC_REG_FLAG_COUNTER,
  46315         0,
  46316         1,
  46317         soc_GR1023r_fields,
  46318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46319         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46320         216,
  46321         -1,
  46322     },
  46323 #endif /* chips */
  46324 
  46325 #if defined(BCM_88375_A0)
  46326     { /* SOC_REG_INT_GT1023_BCM88375_A0r */
  46327         soc_block_list[2],
  46328         soc_portreg,
  46329         1,
  46330         0,
  46331         0x3200,
  46332         SOC_REG_FLAG_COUNTER,
  46333         0,
  46334         1,
  46335         soc_GT1023_BCM88375_A0r_fields,
  46336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46338         50,
  46339         -1,
  46340     },
  46341 #endif /* chips */
  46342 
  46343 #if defined(BCM_88375_B0)
  46344     { /* SOC_REG_INT_GT1023_BCM88375_B0r */
  46345         soc_block_list[2],
  46346         soc_portreg,
  46347         1,
  46348         0,
  46349         0x3200,
  46350         SOC_REG_FLAG_COUNTER,
  46351         0,
  46352         1,
  46353         soc_GT1023_BCM88375_B0r_fields,
  46354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46355         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46356         50,
  46357         -1,
  46358     },
  46359 #endif /* chips */
  46360 
  46361 #if defined(BCM_88470_A0)
  46362     { /* SOC_REG_INT_GT1023_BCM88470_A0r */
  46363         soc_block_list[2],
  46364         soc_portreg,
  46365         1,
  46366         0,
  46367         0x3200,
  46368         SOC_REG_FLAG_COUNTER,
  46369         0,
  46370         1,
  46371         soc_GT1023_BCM88470_A0r_fields,
  46372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46373         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46374         50,
  46375         -1,
  46376     },
  46377 #endif /* chips */
  46378 
  46379 #if defined(BCM_88470_B0)
  46380     { /* SOC_REG_INT_GT1023_BCM88470_B0r */
  46381         soc_block_list[2],
  46382         soc_portreg,
  46383         1,
  46384         0,
  46385         0x3200,
  46386         SOC_REG_FLAG_COUNTER,
  46387         0,
  46388         1,
  46389         soc_GT1023_BCM88470_B0r_fields,
  46390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46392         50,
  46393         -1,
  46394     },
  46395 #endif /* chips */
  46396 
  46397 #if defined(BCM_88675_A0)
  46398     { /* SOC_REG_INT_GT1023_BCM88675_A0r */
  46399         soc_block_list[2],
  46400         soc_portreg,
  46401         1,
  46402         0,
  46403         0x3200,
  46404         SOC_REG_FLAG_COUNTER,
  46405         0,
  46406         1,
  46407         soc_GT1023r_fields,
  46408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46409         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46410         50,
  46411         -1,
  46412     },
  46413 #endif /* chips */
  46414 
  46415 #if defined(BCM_88675_B0)
  46416     { /* SOC_REG_INT_GT1023_BCM88675_B0r */
  46417         soc_block_list[2],
  46418         soc_portreg,
  46419         1,
  46420         0,
  46421         0x3200,
  46422         SOC_REG_FLAG_COUNTER,
  46423         0,
  46424         1,
  46425         soc_GT1023_BCM88675_B0r_fields,
  46426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46428         50,
  46429         -1,
  46430     },
  46431 #endif /* chips */
  46432 
  46433 #if defined(BCM_88680_A0)
  46434     { /* SOC_REG_INT_GT1023_BCM88680_A0r */
  46435         soc_block_list[2],
  46436         soc_portreg,
  46437         1,
  46438         0,
  46439         0x3200,
  46440         SOC_REG_FLAG_COUNTER,
  46441         0,
  46442         1,
  46443         soc_GT1023_BCM88680_A0r_fields,
  46444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46446         50,
  46447         -1,
  46448     },
  46449 #endif /* chips */
  46450 
  46451 #if defined(BCM_53570_A0)
  46452     { /* SOC_REG_INT_GT127Pr */
  46453         soc_block_list[2],
  46454         soc_portreg,
  46455         1,
  46456         0,
  46457         0x9500,
  46458         SOC_REG_FLAG_COUNTER,
  46459         0,
  46460         1,
  46461         soc_GR1023_BCM53400_A0r_fields,
  46462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46464         303,
  46465         -1,
  46466     },
  46467 #endif /* chips */
  46468 
  46469 #if defined(BCM_53570_B0)
  46470     { /* SOC_REG_INT_GT127P_BCM53570_B0r */
  46471         soc_block_list[2],
  46472         soc_portreg,
  46473         1,
  46474         0,
  46475         0x9500,
  46476         SOC_REG_FLAG_COUNTER,
  46477         0,
  46478         1,
  46479         soc_GR1023_BCM53400_A0r_fields,
  46480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46482         307,
  46483         -1,
  46484     },
  46485 #endif /* chips */
  46486 
  46487 #if defined(BCM_53400_A0)
  46488     { /* SOC_REG_INT_GT127_BCM53400_A0r */
  46489         soc_block_list[9],
  46490         soc_portreg,
  46491         1,
  46492         0,
  46493         0x2f00,
  46494         SOC_REG_FLAG_COUNTER,
  46495         0,
  46496         1,
  46497         soc_GR1023_BCM53400_A0r_fields,
  46498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46499         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46500         146,
  46501         -1,
  46502     },
  46503 #endif /* chips */
  46504 
  46505 #if defined(BCM_53540_A0)
  46506     { /* SOC_REG_INT_GT127_BCM53540_A0r */
  46507         soc_block_list[2],
  46508         soc_portreg,
  46509         1,
  46510         0,
  46511         0x4000,
  46512         SOC_REG_FLAG_COUNTER,
  46513         0,
  46514         1,
  46515         soc_GR1023_BCM53400_A0r_fields,
  46516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46517         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46518         163,
  46519         -1,
  46520     },
  46521 #endif /* chips */
  46522 
  46523 #if defined(BCM_53570_A0)
  46524     { /* SOC_REG_INT_GT127_BCM53570_A0r */
  46525         soc_block_list[2],
  46526         soc_portreg,
  46527         1,
  46528         0,
  46529         0x4000,
  46530         SOC_REG_FLAG_COUNTER,
  46531         0,
  46532         1,
  46533         soc_GR1023_BCM53400_A0r_fields,
  46534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46535         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46536         218,
  46537         -1,
  46538     },
  46539 #endif /* chips */
  46540 
  46541 #if defined(BCM_53570_B0)
  46542     { /* SOC_REG_INT_GT127_BCM53570_B0r */
  46543         soc_block_list[2],
  46544         soc_portreg,
  46545         1,
  46546         0,
  46547         0x4000,
  46548         SOC_REG_FLAG_COUNTER,
  46549         0,
  46550         1,
  46551         soc_GR1023_BCM53400_A0r_fields,
  46552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46554         222,
  46555         -1,
  46556     },
  46557 #endif /* chips */
  46558 
  46559 #if defined(BCM_56142_A0)
  46560     { /* SOC_REG_INT_GT127_BCM56142_A0r */
  46561         soc_block_list[210],
  46562         soc_portreg,
  46563         1,
  46564         0,
  46565         0xaf,
  46566         SOC_REG_FLAG_COUNTER,
  46567         0,
  46568         1,
  46569         soc_GR1023r_fields,
  46570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46572         222,
  46573         -1,
  46574     },
  46575 #endif /* chips */
  46576 
  46577 #if defined(BCM_56150_A0)
  46578     { /* SOC_REG_INT_GT127_BCM56150_A0r */
  46579         soc_block_list[2],
  46580         soc_portreg,
  46581         1,
  46582         0,
  46583         0x2f00,
  46584         SOC_REG_FLAG_COUNTER,
  46585         0,
  46586         1,
  46587         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  46588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46589         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46590         142,
  46591         -1,
  46592     },
  46593 #endif /* chips */
  46594 
  46595 #if defined(BCM_56160_A0)
  46596     { /* SOC_REG_INT_GT127_BCM56160_A0r */
  46597         soc_block_list[2],
  46598         soc_portreg,
  46599         1,
  46600         0,
  46601         0x4000,
  46602         SOC_REG_FLAG_COUNTER,
  46603         0,
  46604         1,
  46605         soc_GR1023_BCM53400_A0r_fields,
  46606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46607         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46608         163,
  46609         -1,
  46610     },
  46611 #endif /* chips */
  46612 
  46613 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  46614     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  46615     { /* SOC_REG_INT_GT127_BCM56224_A0r */
  46616         soc_block_list[2],
  46617         soc_portreg,
  46618         1,
  46619         0,
  46620         0x2f,
  46621         SOC_REG_FLAG_COUNTER,
  46622         0,
  46623         1,
  46624         soc_GR1023r_fields,
  46625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46626         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46627         81,
  46628         -1,
  46629     },
  46630 #endif /* chips */
  46631 
  46632 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  46633     { /* SOC_REG_INT_GT127_BCM56334_A0r */
  46634         soc_block_list[210],
  46635         soc_portreg,
  46636         1,
  46637         0,
  46638         0xaf,
  46639         SOC_REG_FLAG_COUNTER,
  46640         0,
  46641         1,
  46642         soc_GR1023r_fields,
  46643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46644         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46645         217,
  46646         -1,
  46647     },
  46648 #endif /* chips */
  46649 
  46650 #if defined(BCM_56370_A0)
  46651     { /* SOC_REG_INT_GT127_BCM56370_A0r */
  46652         soc_block_list[9],
  46653         soc_portreg,
  46654         1,
  46655         0,
  46656         0x3000,
  46657         SOC_REG_FLAG_COUNTER,
  46658         0,
  46659         1,
  46660         soc_GR1023_BCM53400_A0r_fields,
  46661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46662         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46663         108,
  46664         -1,
  46665         3,
  46666     },
  46667 #endif /* chips */
  46668 
  46669 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46670     { /* SOC_REG_INT_GT127_BCM56440_A0r */
  46671         soc_block_list[2],
  46672         soc_portreg,
  46673         1,
  46674         0,
  46675         0xb0,
  46676         SOC_REG_FLAG_COUNTER,
  46677         0,
  46678         1,
  46679         soc_GR1023r_fields,
  46680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46682         215,
  46683         -1,
  46684     },
  46685 #endif /* chips */
  46686 
  46687 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  46688     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  46689     { /* SOC_REG_INT_GT127_BCM56624_A0r */
  46690         soc_block_list[205],
  46691         soc_portreg,
  46692         1,
  46693         0,
  46694         0xa0,
  46695         SOC_REG_FLAG_COUNTER,
  46696         0,
  46697         1,
  46698         soc_GR1023r_fields,
  46699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46701         202,
  46702         -1,
  46703     },
  46704 #endif /* chips */
  46705 
  46706 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  46707     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  46708     { /* SOC_REG_INT_GT127_BCM56634_A0r */
  46709         soc_block_list[207],
  46710         soc_portreg,
  46711         1,
  46712         0,
  46713         0xa0,
  46714         SOC_REG_FLAG_COUNTER,
  46715         0,
  46716         1,
  46717         soc_GR1023r_fields,
  46718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46719         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46720         202,
  46721         -1,
  46722     },
  46723 #endif /* chips */
  46724 
  46725 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  46726     { /* SOC_REG_INT_GT127_BCM56685_A0r */
  46727         soc_block_list[209],
  46728         soc_portreg,
  46729         1,
  46730         0,
  46731         0xa0,
  46732         SOC_REG_FLAG_COUNTER,
  46733         0,
  46734         1,
  46735         soc_GR1023r_fields,
  46736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46737         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46738         202,
  46739         -1,
  46740     },
  46741 #endif /* chips */
  46742 
  46743 #if defined(BCM_56800_A0)
  46744     { /* SOC_REG_INT_GT127_BCM56800_A0r */
  46745         soc_block_list[9],
  46746         soc_portreg,
  46747         1,
  46748         0,
  46749         0x65,
  46750         SOC_REG_FLAG_COUNTER,
  46751         0,
  46752         1,
  46753         soc_GR1023r_fields,
  46754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46755         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46756         143,
  46757         -1,
  46758     },
  46759 #endif /* chips */
  46760 
  46761 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  46762     { /* SOC_REG_INT_GT127_BCM56820_A0r */
  46763         soc_block_list[206],
  46764         soc_portreg,
  46765         1,
  46766         0,
  46767         0xa1,
  46768         SOC_REG_FLAG_COUNTER,
  46769         0,
  46770         1,
  46771         soc_GR1023r_fields,
  46772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46774         213,
  46775         -1,
  46776     },
  46777 #endif /* chips */
  46778 
  46779 #if defined(BCM_88375_A0)
  46780     { /* SOC_REG_INT_GT127_BCM88375_A0r */
  46781         soc_block_list[2],
  46782         soc_portreg,
  46783         1,
  46784         0,
  46785         0x2f00,
  46786         SOC_REG_FLAG_COUNTER,
  46787         0,
  46788         1,
  46789         soc_GT127_BCM88375_A0r_fields,
  46790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46791         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46792         47,
  46793         -1,
  46794     },
  46795 #endif /* chips */
  46796 
  46797 #if defined(BCM_88375_B0)
  46798     { /* SOC_REG_INT_GT127_BCM88375_B0r */
  46799         soc_block_list[2],
  46800         soc_portreg,
  46801         1,
  46802         0,
  46803         0x2f00,
  46804         SOC_REG_FLAG_COUNTER,
  46805         0,
  46806         1,
  46807         soc_GT127_BCM88375_B0r_fields,
  46808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46809         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46810         47,
  46811         -1,
  46812     },
  46813 #endif /* chips */
  46814 
  46815 #if defined(BCM_88470_A0)
  46816     { /* SOC_REG_INT_GT127_BCM88470_A0r */
  46817         soc_block_list[2],
  46818         soc_portreg,
  46819         1,
  46820         0,
  46821         0x2f00,
  46822         SOC_REG_FLAG_COUNTER,
  46823         0,
  46824         1,
  46825         soc_GT127_BCM88470_A0r_fields,
  46826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46827         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46828         47,
  46829         -1,
  46830     },
  46831 #endif /* chips */
  46832 
  46833 #if defined(BCM_88470_B0)
  46834     { /* SOC_REG_INT_GT127_BCM88470_B0r */
  46835         soc_block_list[2],
  46836         soc_portreg,
  46837         1,
  46838         0,
  46839         0x2f00,
  46840         SOC_REG_FLAG_COUNTER,
  46841         0,
  46842         1,
  46843         soc_GT127_BCM88470_B0r_fields,
  46844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46846         47,
  46847         -1,
  46848     },
  46849 #endif /* chips */
  46850 
  46851 #if defined(BCM_88675_A0)
  46852     { /* SOC_REG_INT_GT127_BCM88675_A0r */
  46853         soc_block_list[2],
  46854         soc_portreg,
  46855         1,
  46856         0,
  46857         0x2f00,
  46858         SOC_REG_FLAG_COUNTER,
  46859         0,
  46860         1,
  46861         soc_GT127r_fields,
  46862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46863         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46864         47,
  46865         -1,
  46866     },
  46867 #endif /* chips */
  46868 
  46869 #if defined(BCM_88675_B0)
  46870     { /* SOC_REG_INT_GT127_BCM88675_B0r */
  46871         soc_block_list[2],
  46872         soc_portreg,
  46873         1,
  46874         0,
  46875         0x2f00,
  46876         SOC_REG_FLAG_COUNTER,
  46877         0,
  46878         1,
  46879         soc_GT127_BCM88675_B0r_fields,
  46880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46881         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46882         47,
  46883         -1,
  46884     },
  46885 #endif /* chips */
  46886 
  46887 #if defined(BCM_88680_A0)
  46888     { /* SOC_REG_INT_GT127_BCM88680_A0r */
  46889         soc_block_list[2],
  46890         soc_portreg,
  46891         1,
  46892         0,
  46893         0x2f00,
  46894         SOC_REG_FLAG_COUNTER,
  46895         0,
  46896         1,
  46897         soc_GT127_BCM88680_A0r_fields,
  46898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46899         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  46900         47,
  46901         -1,
  46902     },
  46903 #endif /* chips */
  46904 
  46905 #if defined(BCM_53570_A0)
  46906     { /* SOC_REG_INT_GT1518Pr */
  46907         soc_block_list[2],
  46908         soc_portreg,
  46909         1,
  46910         0,
  46911         0x9900,
  46912         SOC_REG_FLAG_COUNTER,
  46913         0,
  46914         1,
  46915         soc_GR1023_BCM53400_A0r_fields,
  46916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46918         307,
  46919         -1,
  46920     },
  46921 #endif /* chips */
  46922 
  46923 #if defined(BCM_53570_B0)
  46924     { /* SOC_REG_INT_GT1518P_BCM53570_B0r */
  46925         soc_block_list[2],
  46926         soc_portreg,
  46927         1,
  46928         0,
  46929         0x9900,
  46930         SOC_REG_FLAG_COUNTER,
  46931         0,
  46932         1,
  46933         soc_GR1023_BCM53400_A0r_fields,
  46934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46936         311,
  46937         -1,
  46938     },
  46939 #endif /* chips */
  46940 
  46941 #if defined(BCM_53400_A0)
  46942     { /* SOC_REG_INT_GT1518_BCM53400_A0r */
  46943         soc_block_list[9],
  46944         soc_portreg,
  46945         1,
  46946         0,
  46947         0x3300,
  46948         SOC_REG_FLAG_COUNTER,
  46949         0,
  46950         1,
  46951         soc_GR1023_BCM53400_A0r_fields,
  46952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46953         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46954         150,
  46955         -1,
  46956     },
  46957 #endif /* chips */
  46958 
  46959 #if defined(BCM_53540_A0)
  46960     { /* SOC_REG_INT_GT1518_BCM53540_A0r */
  46961         soc_block_list[2],
  46962         soc_portreg,
  46963         1,
  46964         0,
  46965         0x4400,
  46966         SOC_REG_FLAG_COUNTER,
  46967         0,
  46968         1,
  46969         soc_GR1023_BCM53400_A0r_fields,
  46970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46971         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46972         167,
  46973         -1,
  46974     },
  46975 #endif /* chips */
  46976 
  46977 #if defined(BCM_53570_A0)
  46978     { /* SOC_REG_INT_GT1518_BCM53570_A0r */
  46979         soc_block_list[2],
  46980         soc_portreg,
  46981         1,
  46982         0,
  46983         0x4400,
  46984         SOC_REG_FLAG_COUNTER,
  46985         0,
  46986         1,
  46987         soc_GR1023_BCM53400_A0r_fields,
  46988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46990         222,
  46991         -1,
  46992     },
  46993 #endif /* chips */
  46994 
  46995 #if defined(BCM_53570_B0)
  46996     { /* SOC_REG_INT_GT1518_BCM53570_B0r */
  46997         soc_block_list[2],
  46998         soc_portreg,
  46999         1,
  47000         0,
  47001         0x4400,
  47002         SOC_REG_FLAG_COUNTER,
  47003         0,
  47004         1,
  47005         soc_GR1023_BCM53400_A0r_fields,
  47006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47007         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47008         226,
  47009         -1,
  47010     },
  47011 #endif /* chips */
  47012 
  47013 #if defined(BCM_56142_A0)
  47014     { /* SOC_REG_INT_GT1518_BCM56142_A0r */
  47015         soc_block_list[210],
  47016         soc_portreg,
  47017         1,
  47018         0,
  47019         0xb3,
  47020         SOC_REG_FLAG_COUNTER,
  47021         0,
  47022         1,
  47023         soc_GR1023r_fields,
  47024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47026         226,
  47027         -1,
  47028     },
  47029 #endif /* chips */
  47030 
  47031 #if defined(BCM_56150_A0)
  47032     { /* SOC_REG_INT_GT1518_BCM56150_A0r */
  47033         soc_block_list[2],
  47034         soc_portreg,
  47035         1,
  47036         0,
  47037         0x3300,
  47038         SOC_REG_FLAG_COUNTER,
  47039         0,
  47040         1,
  47041         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  47042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47044         146,
  47045         -1,
  47046     },
  47047 #endif /* chips */
  47048 
  47049 #if defined(BCM_56160_A0)
  47050     { /* SOC_REG_INT_GT1518_BCM56160_A0r */
  47051         soc_block_list[2],
  47052         soc_portreg,
  47053         1,
  47054         0,
  47055         0x4400,
  47056         SOC_REG_FLAG_COUNTER,
  47057         0,
  47058         1,
  47059         soc_GR1023_BCM53400_A0r_fields,
  47060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47061         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47062         167,
  47063         -1,
  47064     },
  47065 #endif /* chips */
  47066 
  47067 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  47068     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  47069     { /* SOC_REG_INT_GT1518_BCM56224_A0r */
  47070         soc_block_list[2],
  47071         soc_portreg,
  47072         1,
  47073         0,
  47074         0x33,
  47075         SOC_REG_FLAG_COUNTER,
  47076         0,
  47077         1,
  47078         soc_GR1023r_fields,
  47079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47080         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47081         85,
  47082         -1,
  47083     },
  47084 #endif /* chips */
  47085 
  47086 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  47087     { /* SOC_REG_INT_GT1518_BCM56334_A0r */
  47088         soc_block_list[210],
  47089         soc_portreg,
  47090         1,
  47091         0,
  47092         0xb3,
  47093         SOC_REG_FLAG_COUNTER,
  47094         0,
  47095         1,
  47096         soc_GR1023r_fields,
  47097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47098         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47099         221,
  47100         -1,
  47101     },
  47102 #endif /* chips */
  47103 
  47104 #if defined(BCM_56370_A0)
  47105     { /* SOC_REG_INT_GT1518_BCM56370_A0r */
  47106         soc_block_list[9],
  47107         soc_portreg,
  47108         1,
  47109         0,
  47110         0x3400,
  47111         SOC_REG_FLAG_COUNTER,
  47112         0,
  47113         1,
  47114         soc_GR1023_BCM53400_A0r_fields,
  47115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47116         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47117         112,
  47118         -1,
  47119         3,
  47120     },
  47121 #endif /* chips */
  47122 
  47123 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47124     { /* SOC_REG_INT_GT1518_BCM56440_A0r */
  47125         soc_block_list[2],
  47126         soc_portreg,
  47127         1,
  47128         0,
  47129         0xb4,
  47130         SOC_REG_FLAG_COUNTER,
  47131         0,
  47132         1,
  47133         soc_GR1023r_fields,
  47134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47136         219,
  47137         -1,
  47138     },
  47139 #endif /* chips */
  47140 
  47141 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  47142     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  47143     { /* SOC_REG_INT_GT1518_BCM56624_A0r */
  47144         soc_block_list[205],
  47145         soc_portreg,
  47146         1,
  47147         0,
  47148         0xa4,
  47149         SOC_REG_FLAG_COUNTER,
  47150         0,
  47151         1,
  47152         soc_GR1023r_fields,
  47153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47154         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47155         206,
  47156         -1,
  47157     },
  47158 #endif /* chips */
  47159 
  47160 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  47161     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  47162     { /* SOC_REG_INT_GT1518_BCM56634_A0r */
  47163         soc_block_list[207],
  47164         soc_portreg,
  47165         1,
  47166         0,
  47167         0xa4,
  47168         SOC_REG_FLAG_COUNTER,
  47169         0,
  47170         1,
  47171         soc_GR1023r_fields,
  47172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47174         206,
  47175         -1,
  47176     },
  47177 #endif /* chips */
  47178 
  47179 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  47180     { /* SOC_REG_INT_GT1518_BCM56685_A0r */
  47181         soc_block_list[209],
  47182         soc_portreg,
  47183         1,
  47184         0,
  47185         0xa4,
  47186         SOC_REG_FLAG_COUNTER,
  47187         0,
  47188         1,
  47189         soc_GR1023r_fields,
  47190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47192         206,
  47193         -1,
  47194     },
  47195 #endif /* chips */
  47196 
  47197 #if defined(BCM_56800_A0)
  47198     { /* SOC_REG_INT_GT1518_BCM56800_A0r */
  47199         soc_block_list[9],
  47200         soc_portreg,
  47201         1,
  47202         0,
  47203         0x69,
  47204         SOC_REG_FLAG_COUNTER,
  47205         0,
  47206         1,
  47207         soc_GR1023r_fields,
  47208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47209         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47210         147,
  47211         -1,
  47212     },
  47213 #endif /* chips */
  47214 
  47215 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  47216     { /* SOC_REG_INT_GT1518_BCM56820_A0r */
  47217         soc_block_list[206],
  47218         soc_portreg,
  47219         1,
  47220         0,
  47221         0xa5,
  47222         SOC_REG_FLAG_COUNTER,
  47223         0,
  47224         1,
  47225         soc_GR1023r_fields,
  47226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47227         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47228         217,
  47229         -1,
  47230     },
  47231 #endif /* chips */
  47232 
  47233 #if defined(BCM_88375_A0)
  47234     { /* SOC_REG_INT_GT1518_BCM88375_A0r */
  47235         soc_block_list[2],
  47236         soc_portreg,
  47237         1,
  47238         0,
  47239         0x3300,
  47240         SOC_REG_FLAG_COUNTER,
  47241         0,
  47242         1,
  47243         soc_GT1518_BCM88375_A0r_fields,
  47244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47246         51,
  47247         -1,
  47248     },
  47249 #endif /* chips */
  47250 
  47251 #if defined(BCM_88375_B0)
  47252     { /* SOC_REG_INT_GT1518_BCM88375_B0r */
  47253         soc_block_list[2],
  47254         soc_portreg,
  47255         1,
  47256         0,
  47257         0x3300,
  47258         SOC_REG_FLAG_COUNTER,
  47259         0,
  47260         1,
  47261         soc_GT1518_BCM88375_B0r_fields,
  47262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47264         51,
  47265         -1,
  47266     },
  47267 #endif /* chips */
  47268 
  47269 #if defined(BCM_88470_A0)
  47270     { /* SOC_REG_INT_GT1518_BCM88470_A0r */
  47271         soc_block_list[2],
  47272         soc_portreg,
  47273         1,
  47274         0,
  47275         0x3300,
  47276         SOC_REG_FLAG_COUNTER,
  47277         0,
  47278         1,
  47279         soc_GT1518_BCM88470_A0r_fields,
  47280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47282         51,
  47283         -1,
  47284     },
  47285 #endif /* chips */
  47286 
  47287 #if defined(BCM_88470_B0)
  47288     { /* SOC_REG_INT_GT1518_BCM88470_B0r */
  47289         soc_block_list[2],
  47290         soc_portreg,
  47291         1,
  47292         0,
  47293         0x3300,
  47294         SOC_REG_FLAG_COUNTER,
  47295         0,
  47296         1,
  47297         soc_GT1518_BCM88470_B0r_fields,
  47298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47300         51,
  47301         -1,
  47302     },
  47303 #endif /* chips */
  47304 
  47305 #if defined(BCM_88675_A0)
  47306     { /* SOC_REG_INT_GT1518_BCM88675_A0r */
  47307         soc_block_list[2],
  47308         soc_portreg,
  47309         1,
  47310         0,
  47311         0x3300,
  47312         SOC_REG_FLAG_COUNTER,
  47313         0,
  47314         1,
  47315         soc_GT1518r_fields,
  47316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47318         51,
  47319         -1,
  47320     },
  47321 #endif /* chips */
  47322 
  47323 #if defined(BCM_88675_B0)
  47324     { /* SOC_REG_INT_GT1518_BCM88675_B0r */
  47325         soc_block_list[2],
  47326         soc_portreg,
  47327         1,
  47328         0,
  47329         0x3300,
  47330         SOC_REG_FLAG_COUNTER,
  47331         0,
  47332         1,
  47333         soc_GT1518_BCM88675_B0r_fields,
  47334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47336         51,
  47337         -1,
  47338     },
  47339 #endif /* chips */
  47340 
  47341 #if defined(BCM_88680_A0)
  47342     { /* SOC_REG_INT_GT1518_BCM88680_A0r */
  47343         soc_block_list[2],
  47344         soc_portreg,
  47345         1,
  47346         0,
  47347         0x3300,
  47348         SOC_REG_FLAG_COUNTER,
  47349         0,
  47350         1,
  47351         soc_GT1518_BCM88680_A0r_fields,
  47352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47354         51,
  47355         -1,
  47356     },
  47357 #endif /* chips */
  47358 
  47359 #if defined(BCM_53570_A0)
  47360     { /* SOC_REG_INT_GT2047Pr */
  47361         soc_block_list[2],
  47362         soc_portreg,
  47363         1,
  47364         0,
  47365         0x9b00,
  47366         SOC_REG_FLAG_COUNTER,
  47367         0,
  47368         1,
  47369         soc_GR1023_BCM53400_A0r_fields,
  47370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47372         309,
  47373         -1,
  47374     },
  47375 #endif /* chips */
  47376 
  47377 #if defined(BCM_53570_B0)
  47378     { /* SOC_REG_INT_GT2047P_BCM53570_B0r */
  47379         soc_block_list[2],
  47380         soc_portreg,
  47381         1,
  47382         0,
  47383         0x9b00,
  47384         SOC_REG_FLAG_COUNTER,
  47385         0,
  47386         1,
  47387         soc_GR1023_BCM53400_A0r_fields,
  47388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47389         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47390         313,
  47391         -1,
  47392     },
  47393 #endif /* chips */
  47394 
  47395 #if defined(BCM_53400_A0)
  47396     { /* SOC_REG_INT_GT2047_BCM53400_A0r */
  47397         soc_block_list[9],
  47398         soc_portreg,
  47399         1,
  47400         0,
  47401         0x3500,
  47402         SOC_REG_FLAG_COUNTER,
  47403         0,
  47404         1,
  47405         soc_GR1023_BCM53400_A0r_fields,
  47406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47408         152,
  47409         -1,
  47410     },
  47411 #endif /* chips */
  47412 
  47413 #if defined(BCM_53540_A0)
  47414     { /* SOC_REG_INT_GT2047_BCM53540_A0r */
  47415         soc_block_list[2],
  47416         soc_portreg,
  47417         1,
  47418         0,
  47419         0x4600,
  47420         SOC_REG_FLAG_COUNTER,
  47421         0,
  47422         1,
  47423         soc_GR1023_BCM53400_A0r_fields,
  47424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47426         169,
  47427         -1,
  47428     },
  47429 #endif /* chips */
  47430 
  47431 #if defined(BCM_53570_A0)
  47432     { /* SOC_REG_INT_GT2047_BCM53570_A0r */
  47433         soc_block_list[2],
  47434         soc_portreg,
  47435         1,
  47436         0,
  47437         0x4600,
  47438         SOC_REG_FLAG_COUNTER,
  47439         0,
  47440         1,
  47441         soc_GR1023_BCM53400_A0r_fields,
  47442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47443         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47444         224,
  47445         -1,
  47446     },
  47447 #endif /* chips */
  47448 
  47449 #if defined(BCM_53570_B0)
  47450     { /* SOC_REG_INT_GT2047_BCM53570_B0r */
  47451         soc_block_list[2],
  47452         soc_portreg,
  47453         1,
  47454         0,
  47455         0x4600,
  47456         SOC_REG_FLAG_COUNTER,
  47457         0,
  47458         1,
  47459         soc_GR1023_BCM53400_A0r_fields,
  47460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47461         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47462         228,
  47463         -1,
  47464     },
  47465 #endif /* chips */
  47466 
  47467 #if defined(BCM_56142_A0)
  47468     { /* SOC_REG_INT_GT2047_BCM56142_A0r */
  47469         soc_block_list[210],
  47470         soc_portreg,
  47471         1,
  47472         0,
  47473         0xb5,
  47474         SOC_REG_FLAG_COUNTER,
  47475         0,
  47476         1,
  47477         soc_GR1023r_fields,
  47478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47479         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47480         228,
  47481         -1,
  47482     },
  47483 #endif /* chips */
  47484 
  47485 #if defined(BCM_56150_A0)
  47486     { /* SOC_REG_INT_GT2047_BCM56150_A0r */
  47487         soc_block_list[2],
  47488         soc_portreg,
  47489         1,
  47490         0,
  47491         0x3500,
  47492         SOC_REG_FLAG_COUNTER,
  47493         0,
  47494         1,
  47495         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  47496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47497         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47498         148,
  47499         -1,
  47500     },
  47501 #endif /* chips */
  47502 
  47503 #if defined(BCM_56160_A0)
  47504     { /* SOC_REG_INT_GT2047_BCM56160_A0r */
  47505         soc_block_list[2],
  47506         soc_portreg,
  47507         1,
  47508         0,
  47509         0x4600,
  47510         SOC_REG_FLAG_COUNTER,
  47511         0,
  47512         1,
  47513         soc_GR1023_BCM53400_A0r_fields,
  47514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47515         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47516         169,
  47517         -1,
  47518     },
  47519 #endif /* chips */
  47520 
  47521 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  47522     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  47523     { /* SOC_REG_INT_GT2047_BCM56224_A0r */
  47524         soc_block_list[2],
  47525         soc_portreg,
  47526         1,
  47527         0,
  47528         0x35,
  47529         SOC_REG_FLAG_COUNTER,
  47530         0,
  47531         1,
  47532         soc_GR1023r_fields,
  47533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47534         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47535         87,
  47536         -1,
  47537     },
  47538 #endif /* chips */
  47539 
  47540 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  47541     { /* SOC_REG_INT_GT2047_BCM56334_A0r */
  47542         soc_block_list[210],
  47543         soc_portreg,
  47544         1,
  47545         0,
  47546         0xb5,
  47547         SOC_REG_FLAG_COUNTER,
  47548         0,
  47549         1,
  47550         soc_GR1023r_fields,
  47551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47552         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47553         223,
  47554         -1,
  47555     },
  47556 #endif /* chips */
  47557 
  47558 #if defined(BCM_56370_A0)
  47559     { /* SOC_REG_INT_GT2047_BCM56370_A0r */
  47560         soc_block_list[9],
  47561         soc_portreg,
  47562         1,
  47563         0,
  47564         0x3600,
  47565         SOC_REG_FLAG_COUNTER,
  47566         0,
  47567         1,
  47568         soc_GR1023_BCM53400_A0r_fields,
  47569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47570         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47571         114,
  47572         -1,
  47573         3,
  47574     },
  47575 #endif /* chips */
  47576 
  47577 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47578     { /* SOC_REG_INT_GT2047_BCM56440_A0r */
  47579         soc_block_list[2],
  47580         soc_portreg,
  47581         1,
  47582         0,
  47583         0xb6,
  47584         SOC_REG_FLAG_COUNTER,
  47585         0,
  47586         1,
  47587         soc_GR1023r_fields,
  47588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47589         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47590         221,
  47591         -1,
  47592     },
  47593 #endif /* chips */
  47594 
  47595 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  47596     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  47597     { /* SOC_REG_INT_GT2047_BCM56624_A0r */
  47598         soc_block_list[205],
  47599         soc_portreg,
  47600         1,
  47601         0,
  47602         0xa6,
  47603         SOC_REG_FLAG_COUNTER,
  47604         0,
  47605         1,
  47606         soc_GR1023r_fields,
  47607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47608         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47609         208,
  47610         -1,
  47611     },
  47612 #endif /* chips */
  47613 
  47614 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  47615     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  47616     { /* SOC_REG_INT_GT2047_BCM56634_A0r */
  47617         soc_block_list[207],
  47618         soc_portreg,
  47619         1,
  47620         0,
  47621         0xa6,
  47622         SOC_REG_FLAG_COUNTER,
  47623         0,
  47624         1,
  47625         soc_GR1023r_fields,
  47626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47628         208,
  47629         -1,
  47630     },
  47631 #endif /* chips */
  47632 
  47633 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  47634     { /* SOC_REG_INT_GT2047_BCM56685_A0r */
  47635         soc_block_list[209],
  47636         soc_portreg,
  47637         1,
  47638         0,
  47639         0xa6,
  47640         SOC_REG_FLAG_COUNTER,
  47641         0,
  47642         1,
  47643         soc_GR1023r_fields,
  47644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47646         208,
  47647         -1,
  47648     },
  47649 #endif /* chips */
  47650 
  47651 #if defined(BCM_56800_A0)
  47652     { /* SOC_REG_INT_GT2047_BCM56800_A0r */
  47653         soc_block_list[9],
  47654         soc_portreg,
  47655         1,
  47656         0,
  47657         0x6b,
  47658         SOC_REG_FLAG_COUNTER,
  47659         0,
  47660         1,
  47661         soc_GR1023r_fields,
  47662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47663         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47664         149,
  47665         -1,
  47666     },
  47667 #endif /* chips */
  47668 
  47669 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  47670     { /* SOC_REG_INT_GT2047_BCM56820_A0r */
  47671         soc_block_list[206],
  47672         soc_portreg,
  47673         1,
  47674         0,
  47675         0xa7,
  47676         SOC_REG_FLAG_COUNTER,
  47677         0,
  47678         1,
  47679         soc_GR1023r_fields,
  47680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47682         219,
  47683         -1,
  47684     },
  47685 #endif /* chips */
  47686 
  47687 #if defined(BCM_88375_A0)
  47688     { /* SOC_REG_INT_GT2047_BCM88375_A0r */
  47689         soc_block_list[2],
  47690         soc_portreg,
  47691         1,
  47692         0,
  47693         0x3500,
  47694         SOC_REG_FLAG_COUNTER,
  47695         0,
  47696         1,
  47697         soc_GT2047_BCM88375_A0r_fields,
  47698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47700         53,
  47701         -1,
  47702     },
  47703 #endif /* chips */
  47704 
  47705 #if defined(BCM_88375_B0)
  47706     { /* SOC_REG_INT_GT2047_BCM88375_B0r */
  47707         soc_block_list[2],
  47708         soc_portreg,
  47709         1,
  47710         0,
  47711         0x3500,
  47712         SOC_REG_FLAG_COUNTER,
  47713         0,
  47714         1,
  47715         soc_GT2047_BCM88375_B0r_fields,
  47716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47718         53,
  47719         -1,
  47720     },
  47721 #endif /* chips */
  47722 
  47723 #if defined(BCM_88470_A0)
  47724     { /* SOC_REG_INT_GT2047_BCM88470_A0r */
  47725         soc_block_list[2],
  47726         soc_portreg,
  47727         1,
  47728         0,
  47729         0x3500,
  47730         SOC_REG_FLAG_COUNTER,
  47731         0,
  47732         1,
  47733         soc_GT2047_BCM88470_A0r_fields,
  47734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47736         53,
  47737         -1,
  47738     },
  47739 #endif /* chips */
  47740 
  47741 #if defined(BCM_88470_B0)
  47742     { /* SOC_REG_INT_GT2047_BCM88470_B0r */
  47743         soc_block_list[2],
  47744         soc_portreg,
  47745         1,
  47746         0,
  47747         0x3500,
  47748         SOC_REG_FLAG_COUNTER,
  47749         0,
  47750         1,
  47751         soc_GT2047_BCM88470_B0r_fields,
  47752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47754         53,
  47755         -1,
  47756     },
  47757 #endif /* chips */
  47758 
  47759 #if defined(BCM_88675_A0)
  47760     { /* SOC_REG_INT_GT2047_BCM88675_A0r */
  47761         soc_block_list[2],
  47762         soc_portreg,
  47763         1,
  47764         0,
  47765         0x3500,
  47766         SOC_REG_FLAG_COUNTER,
  47767         0,
  47768         1,
  47769         soc_GT2047r_fields,
  47770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47772         53,
  47773         -1,
  47774     },
  47775 #endif /* chips */
  47776 
  47777 #if defined(BCM_88675_B0)
  47778     { /* SOC_REG_INT_GT2047_BCM88675_B0r */
  47779         soc_block_list[2],
  47780         soc_portreg,
  47781         1,
  47782         0,
  47783         0x3500,
  47784         SOC_REG_FLAG_COUNTER,
  47785         0,
  47786         1,
  47787         soc_GT2047_BCM88675_B0r_fields,
  47788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47789         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47790         53,
  47791         -1,
  47792     },
  47793 #endif /* chips */
  47794 
  47795 #if defined(BCM_88680_A0)
  47796     { /* SOC_REG_INT_GT2047_BCM88680_A0r */
  47797         soc_block_list[2],
  47798         soc_portreg,
  47799         1,
  47800         0,
  47801         0x3500,
  47802         SOC_REG_FLAG_COUNTER,
  47803         0,
  47804         1,
  47805         soc_GT2047_BCM88680_A0r_fields,
  47806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47807         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47808         53,
  47809         -1,
  47810     },
  47811 #endif /* chips */
  47812 
  47813 #if defined(BCM_53570_A0)
  47814     { /* SOC_REG_INT_GT255Pr */
  47815         soc_block_list[2],
  47816         soc_portreg,
  47817         1,
  47818         0,
  47819         0x9600,
  47820         SOC_REG_FLAG_COUNTER,
  47821         0,
  47822         1,
  47823         soc_GR1023_BCM53400_A0r_fields,
  47824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47825         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47826         304,
  47827         -1,
  47828     },
  47829 #endif /* chips */
  47830 
  47831 #if defined(BCM_53570_B0)
  47832     { /* SOC_REG_INT_GT255P_BCM53570_B0r */
  47833         soc_block_list[2],
  47834         soc_portreg,
  47835         1,
  47836         0,
  47837         0x9600,
  47838         SOC_REG_FLAG_COUNTER,
  47839         0,
  47840         1,
  47841         soc_GR1023_BCM53400_A0r_fields,
  47842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47843         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47844         308,
  47845         -1,
  47846     },
  47847 #endif /* chips */
  47848 
  47849 #if defined(BCM_53400_A0)
  47850     { /* SOC_REG_INT_GT255_BCM53400_A0r */
  47851         soc_block_list[9],
  47852         soc_portreg,
  47853         1,
  47854         0,
  47855         0x3000,
  47856         SOC_REG_FLAG_COUNTER,
  47857         0,
  47858         1,
  47859         soc_GR1023_BCM53400_A0r_fields,
  47860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47861         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47862         147,
  47863         -1,
  47864     },
  47865 #endif /* chips */
  47866 
  47867 #if defined(BCM_53540_A0)
  47868     { /* SOC_REG_INT_GT255_BCM53540_A0r */
  47869         soc_block_list[2],
  47870         soc_portreg,
  47871         1,
  47872         0,
  47873         0x4100,
  47874         SOC_REG_FLAG_COUNTER,
  47875         0,
  47876         1,
  47877         soc_GR1023_BCM53400_A0r_fields,
  47878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47879         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47880         164,
  47881         -1,
  47882     },
  47883 #endif /* chips */
  47884 
  47885 #if defined(BCM_53570_A0)
  47886     { /* SOC_REG_INT_GT255_BCM53570_A0r */
  47887         soc_block_list[2],
  47888         soc_portreg,
  47889         1,
  47890         0,
  47891         0x4100,
  47892         SOC_REG_FLAG_COUNTER,
  47893         0,
  47894         1,
  47895         soc_GR1023_BCM53400_A0r_fields,
  47896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47898         219,
  47899         -1,
  47900     },
  47901 #endif /* chips */
  47902 
  47903 #if defined(BCM_53570_B0)
  47904     { /* SOC_REG_INT_GT255_BCM53570_B0r */
  47905         soc_block_list[2],
  47906         soc_portreg,
  47907         1,
  47908         0,
  47909         0x4100,
  47910         SOC_REG_FLAG_COUNTER,
  47911         0,
  47912         1,
  47913         soc_GR1023_BCM53400_A0r_fields,
  47914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47916         223,
  47917         -1,
  47918     },
  47919 #endif /* chips */
  47920 
  47921 #if defined(BCM_56142_A0)
  47922     { /* SOC_REG_INT_GT255_BCM56142_A0r */
  47923         soc_block_list[210],
  47924         soc_portreg,
  47925         1,
  47926         0,
  47927         0xb0,
  47928         SOC_REG_FLAG_COUNTER,
  47929         0,
  47930         1,
  47931         soc_GR1023r_fields,
  47932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47934         223,
  47935         -1,
  47936     },
  47937 #endif /* chips */
  47938 
  47939 #if defined(BCM_56150_A0)
  47940     { /* SOC_REG_INT_GT255_BCM56150_A0r */
  47941         soc_block_list[2],
  47942         soc_portreg,
  47943         1,
  47944         0,
  47945         0x3000,
  47946         SOC_REG_FLAG_COUNTER,
  47947         0,
  47948         1,
  47949         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  47950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47952         143,
  47953         -1,
  47954     },
  47955 #endif /* chips */
  47956 
  47957 #if defined(BCM_56160_A0)
  47958     { /* SOC_REG_INT_GT255_BCM56160_A0r */
  47959         soc_block_list[2],
  47960         soc_portreg,
  47961         1,
  47962         0,
  47963         0x4100,
  47964         SOC_REG_FLAG_COUNTER,
  47965         0,
  47966         1,
  47967         soc_GR1023_BCM53400_A0r_fields,
  47968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47970         164,
  47971         -1,
  47972     },
  47973 #endif /* chips */
  47974 
  47975 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  47976     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  47977     { /* SOC_REG_INT_GT255_BCM56224_A0r */
  47978         soc_block_list[2],
  47979         soc_portreg,
  47980         1,
  47981         0,
  47982         0x30,
  47983         SOC_REG_FLAG_COUNTER,
  47984         0,
  47985         1,
  47986         soc_GR1023r_fields,
  47987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47988         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47989         82,
  47990         -1,
  47991     },
  47992 #endif /* chips */
  47993 
  47994 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  47995     { /* SOC_REG_INT_GT255_BCM56334_A0r */
  47996         soc_block_list[210],
  47997         soc_portreg,
  47998         1,
  47999         0,
  48000         0xb0,
  48001         SOC_REG_FLAG_COUNTER,
  48002         0,
  48003         1,
  48004         soc_GR1023r_fields,
  48005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48006         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48007         218,
  48008         -1,
  48009     },
  48010 #endif /* chips */
  48011 
  48012 #if defined(BCM_56370_A0)
  48013     { /* SOC_REG_INT_GT255_BCM56370_A0r */
  48014         soc_block_list[9],
  48015         soc_portreg,
  48016         1,
  48017         0,
  48018         0x3100,
  48019         SOC_REG_FLAG_COUNTER,
  48020         0,
  48021         1,
  48022         soc_GR1023_BCM53400_A0r_fields,
  48023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48024         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48025         109,
  48026         -1,
  48027         3,
  48028     },
  48029 #endif /* chips */
  48030 
  48031 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48032     { /* SOC_REG_INT_GT255_BCM56440_A0r */
  48033         soc_block_list[2],
  48034         soc_portreg,
  48035         1,
  48036         0,
  48037         0xb1,
  48038         SOC_REG_FLAG_COUNTER,
  48039         0,
  48040         1,
  48041         soc_GR1023r_fields,
  48042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48044         216,
  48045         -1,
  48046     },
  48047 #endif /* chips */
  48048 
  48049 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  48050     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  48051     { /* SOC_REG_INT_GT255_BCM56624_A0r */
  48052         soc_block_list[205],
  48053         soc_portreg,
  48054         1,
  48055         0,
  48056         0xa1,
  48057         SOC_REG_FLAG_COUNTER,
  48058         0,
  48059         1,
  48060         soc_GR1023r_fields,
  48061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48062         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48063         203,
  48064         -1,
  48065     },
  48066 #endif /* chips */
  48067 
  48068 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  48069     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  48070     { /* SOC_REG_INT_GT255_BCM56634_A0r */
  48071         soc_block_list[207],
  48072         soc_portreg,
  48073         1,
  48074         0,
  48075         0xa1,
  48076         SOC_REG_FLAG_COUNTER,
  48077         0,
  48078         1,
  48079         soc_GR1023r_fields,
  48080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48081         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48082         203,
  48083         -1,
  48084     },
  48085 #endif /* chips */
  48086 
  48087 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  48088     { /* SOC_REG_INT_GT255_BCM56685_A0r */
  48089         soc_block_list[209],
  48090         soc_portreg,
  48091         1,
  48092         0,
  48093         0xa1,
  48094         SOC_REG_FLAG_COUNTER,
  48095         0,
  48096         1,
  48097         soc_GR1023r_fields,
  48098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48100         203,
  48101         -1,
  48102     },
  48103 #endif /* chips */
  48104 
  48105 #if defined(BCM_56800_A0)
  48106     { /* SOC_REG_INT_GT255_BCM56800_A0r */
  48107         soc_block_list[9],
  48108         soc_portreg,
  48109         1,
  48110         0,
  48111         0x66,
  48112         SOC_REG_FLAG_COUNTER,
  48113         0,
  48114         1,
  48115         soc_GR1023r_fields,
  48116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48118         144,
  48119         -1,
  48120     },
  48121 #endif /* chips */
  48122 
  48123 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  48124     { /* SOC_REG_INT_GT255_BCM56820_A0r */
  48125         soc_block_list[206],
  48126         soc_portreg,
  48127         1,
  48128         0,
  48129         0xa2,
  48130         SOC_REG_FLAG_COUNTER,
  48131         0,
  48132         1,
  48133         soc_GR1023r_fields,
  48134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48136         214,
  48137         -1,
  48138     },
  48139 #endif /* chips */
  48140 
  48141 #if defined(BCM_88375_A0)
  48142     { /* SOC_REG_INT_GT255_BCM88375_A0r */
  48143         soc_block_list[2],
  48144         soc_portreg,
  48145         1,
  48146         0,
  48147         0x3000,
  48148         SOC_REG_FLAG_COUNTER,
  48149         0,
  48150         1,
  48151         soc_GT255_BCM88375_A0r_fields,
  48152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48153         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48154         48,
  48155         -1,
  48156     },
  48157 #endif /* chips */
  48158 
  48159 #if defined(BCM_88375_B0)
  48160     { /* SOC_REG_INT_GT255_BCM88375_B0r */
  48161         soc_block_list[2],
  48162         soc_portreg,
  48163         1,
  48164         0,
  48165         0x3000,
  48166         SOC_REG_FLAG_COUNTER,
  48167         0,
  48168         1,
  48169         soc_GT255_BCM88375_B0r_fields,
  48170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48171         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48172         48,
  48173         -1,
  48174     },
  48175 #endif /* chips */
  48176 
  48177 #if defined(BCM_88470_A0)
  48178     { /* SOC_REG_INT_GT255_BCM88470_A0r */
  48179         soc_block_list[2],
  48180         soc_portreg,
  48181         1,
  48182         0,
  48183         0x3000,
  48184         SOC_REG_FLAG_COUNTER,
  48185         0,
  48186         1,
  48187         soc_GT255_BCM88470_A0r_fields,
  48188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48189         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48190         48,
  48191         -1,
  48192     },
  48193 #endif /* chips */
  48194 
  48195 #if defined(BCM_88470_B0)
  48196     { /* SOC_REG_INT_GT255_BCM88470_B0r */
  48197         soc_block_list[2],
  48198         soc_portreg,
  48199         1,
  48200         0,
  48201         0x3000,
  48202         SOC_REG_FLAG_COUNTER,
  48203         0,
  48204         1,
  48205         soc_GT255_BCM88470_B0r_fields,
  48206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48207         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48208         48,
  48209         -1,
  48210     },
  48211 #endif /* chips */
  48212 
  48213 #if defined(BCM_88675_A0)
  48214     { /* SOC_REG_INT_GT255_BCM88675_A0r */
  48215         soc_block_list[2],
  48216         soc_portreg,
  48217         1,
  48218         0,
  48219         0x3000,
  48220         SOC_REG_FLAG_COUNTER,
  48221         0,
  48222         1,
  48223         soc_GT255r_fields,
  48224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48225         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48226         48,
  48227         -1,
  48228     },
  48229 #endif /* chips */
  48230 
  48231 #if defined(BCM_88675_B0)
  48232     { /* SOC_REG_INT_GT255_BCM88675_B0r */
  48233         soc_block_list[2],
  48234         soc_portreg,
  48235         1,
  48236         0,
  48237         0x3000,
  48238         SOC_REG_FLAG_COUNTER,
  48239         0,
  48240         1,
  48241         soc_GT255_BCM88675_B0r_fields,
  48242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48243         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48244         48,
  48245         -1,
  48246     },
  48247 #endif /* chips */
  48248 
  48249 #if defined(BCM_88680_A0)
  48250     { /* SOC_REG_INT_GT255_BCM88680_A0r */
  48251         soc_block_list[2],
  48252         soc_portreg,
  48253         1,
  48254         0,
  48255         0x3000,
  48256         SOC_REG_FLAG_COUNTER,
  48257         0,
  48258         1,
  48259         soc_GT255_BCM88680_A0r_fields,
  48260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48261         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48262         48,
  48263         -1,
  48264     },
  48265 #endif /* chips */
  48266 
  48267 #if defined(BCM_53570_A0)
  48268     { /* SOC_REG_INT_GT4095Pr */
  48269         soc_block_list[2],
  48270         soc_portreg,
  48271         1,
  48272         0,
  48273         0x9c00,
  48274         SOC_REG_FLAG_COUNTER,
  48275         0,
  48276         1,
  48277         soc_GR1023_BCM53400_A0r_fields,
  48278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48279         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48280         310,
  48281         -1,
  48282     },
  48283 #endif /* chips */
  48284 
  48285 #if defined(BCM_53570_B0)
  48286     { /* SOC_REG_INT_GT4095P_BCM53570_B0r */
  48287         soc_block_list[2],
  48288         soc_portreg,
  48289         1,
  48290         0,
  48291         0x9c00,
  48292         SOC_REG_FLAG_COUNTER,
  48293         0,
  48294         1,
  48295         soc_GR1023_BCM53400_A0r_fields,
  48296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48297         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48298         314,
  48299         -1,
  48300     },
  48301 #endif /* chips */
  48302 
  48303 #if defined(BCM_53400_A0)
  48304     { /* SOC_REG_INT_GT4095_BCM53400_A0r */
  48305         soc_block_list[9],
  48306         soc_portreg,
  48307         1,
  48308         0,
  48309         0x3600,
  48310         SOC_REG_FLAG_COUNTER,
  48311         0,
  48312         1,
  48313         soc_GR1023_BCM53400_A0r_fields,
  48314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48315         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48316         153,
  48317         -1,
  48318     },
  48319 #endif /* chips */
  48320 
  48321 #if defined(BCM_53540_A0)
  48322     { /* SOC_REG_INT_GT4095_BCM53540_A0r */
  48323         soc_block_list[2],
  48324         soc_portreg,
  48325         1,
  48326         0,
  48327         0x4700,
  48328         SOC_REG_FLAG_COUNTER,
  48329         0,
  48330         1,
  48331         soc_GR1023_BCM53400_A0r_fields,
  48332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48334         170,
  48335         -1,
  48336     },
  48337 #endif /* chips */
  48338 
  48339 #if defined(BCM_53570_A0)
  48340     { /* SOC_REG_INT_GT4095_BCM53570_A0r */
  48341         soc_block_list[2],
  48342         soc_portreg,
  48343         1,
  48344         0,
  48345         0x4700,
  48346         SOC_REG_FLAG_COUNTER,
  48347         0,
  48348         1,
  48349         soc_GR1023_BCM53400_A0r_fields,
  48350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48351         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48352         225,
  48353         -1,
  48354     },
  48355 #endif /* chips */
  48356 
  48357 #if defined(BCM_53570_B0)
  48358     { /* SOC_REG_INT_GT4095_BCM53570_B0r */
  48359         soc_block_list[2],
  48360         soc_portreg,
  48361         1,
  48362         0,
  48363         0x4700,
  48364         SOC_REG_FLAG_COUNTER,
  48365         0,
  48366         1,
  48367         soc_GR1023_BCM53400_A0r_fields,
  48368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48370         229,
  48371         -1,
  48372     },
  48373 #endif /* chips */
  48374 
  48375 #if defined(BCM_56142_A0)
  48376     { /* SOC_REG_INT_GT4095_BCM56142_A0r */
  48377         soc_block_list[210],
  48378         soc_portreg,
  48379         1,
  48380         0,
  48381         0xb6,
  48382         SOC_REG_FLAG_COUNTER,
  48383         0,
  48384         1,
  48385         soc_GR1023r_fields,
  48386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48387         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48388         229,
  48389         -1,
  48390     },
  48391 #endif /* chips */
  48392 
  48393 #if defined(BCM_56150_A0)
  48394     { /* SOC_REG_INT_GT4095_BCM56150_A0r */
  48395         soc_block_list[2],
  48396         soc_portreg,
  48397         1,
  48398         0,
  48399         0x3600,
  48400         SOC_REG_FLAG_COUNTER,
  48401         0,
  48402         1,
  48403         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  48404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48405         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48406         149,
  48407         -1,
  48408     },
  48409 #endif /* chips */
  48410 
  48411 #if defined(BCM_56160_A0)
  48412     { /* SOC_REG_INT_GT4095_BCM56160_A0r */
  48413         soc_block_list[2],
  48414         soc_portreg,
  48415         1,
  48416         0,
  48417         0x4700,
  48418         SOC_REG_FLAG_COUNTER,
  48419         0,
  48420         1,
  48421         soc_GR1023_BCM53400_A0r_fields,
  48422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48423         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48424         170,
  48425         -1,
  48426     },
  48427 #endif /* chips */
  48428 
  48429 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  48430     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  48431     { /* SOC_REG_INT_GT4095_BCM56224_A0r */
  48432         soc_block_list[2],
  48433         soc_portreg,
  48434         1,
  48435         0,
  48436         0x36,
  48437         SOC_REG_FLAG_COUNTER,
  48438         0,
  48439         1,
  48440         soc_GR1023r_fields,
  48441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48442         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48443         88,
  48444         -1,
  48445     },
  48446 #endif /* chips */
  48447 
  48448 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  48449     { /* SOC_REG_INT_GT4095_BCM56334_A0r */
  48450         soc_block_list[210],
  48451         soc_portreg,
  48452         1,
  48453         0,
  48454         0xb6,
  48455         SOC_REG_FLAG_COUNTER,
  48456         0,
  48457         1,
  48458         soc_GR1023r_fields,
  48459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48460         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48461         224,
  48462         -1,
  48463     },
  48464 #endif /* chips */
  48465 
  48466 #if defined(BCM_56370_A0)
  48467     { /* SOC_REG_INT_GT4095_BCM56370_A0r */
  48468         soc_block_list[9],
  48469         soc_portreg,
  48470         1,
  48471         0,
  48472         0x3700,
  48473         SOC_REG_FLAG_COUNTER,
  48474         0,
  48475         1,
  48476         soc_GR1023_BCM53400_A0r_fields,
  48477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48479         115,
  48480         -1,
  48481         3,
  48482     },
  48483 #endif /* chips */
  48484 
  48485 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48486     { /* SOC_REG_INT_GT4095_BCM56440_A0r */
  48487         soc_block_list[2],
  48488         soc_portreg,
  48489         1,
  48490         0,
  48491         0xb7,
  48492         SOC_REG_FLAG_COUNTER,
  48493         0,
  48494         1,
  48495         soc_GR1023r_fields,
  48496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48497         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48498         222,
  48499         -1,
  48500     },
  48501 #endif /* chips */
  48502 
  48503 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  48504     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  48505     { /* SOC_REG_INT_GT4095_BCM56624_A0r */
  48506         soc_block_list[205],
  48507         soc_portreg,
  48508         1,
  48509         0,
  48510         0xa7,
  48511         SOC_REG_FLAG_COUNTER,
  48512         0,
  48513         1,
  48514         soc_GR1023r_fields,
  48515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48516         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48517         209,
  48518         -1,
  48519     },
  48520 #endif /* chips */
  48521 
  48522 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  48523     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  48524     { /* SOC_REG_INT_GT4095_BCM56634_A0r */
  48525         soc_block_list[207],
  48526         soc_portreg,
  48527         1,
  48528         0,
  48529         0xa7,
  48530         SOC_REG_FLAG_COUNTER,
  48531         0,
  48532         1,
  48533         soc_GR1023r_fields,
  48534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48535         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48536         209,
  48537         -1,
  48538     },
  48539 #endif /* chips */
  48540 
  48541 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  48542     { /* SOC_REG_INT_GT4095_BCM56685_A0r */
  48543         soc_block_list[209],
  48544         soc_portreg,
  48545         1,
  48546         0,
  48547         0xa7,
  48548         SOC_REG_FLAG_COUNTER,
  48549         0,
  48550         1,
  48551         soc_GR1023r_fields,
  48552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48554         209,
  48555         -1,
  48556     },
  48557 #endif /* chips */
  48558 
  48559 #if defined(BCM_56800_A0)
  48560     { /* SOC_REG_INT_GT4095_BCM56800_A0r */
  48561         soc_block_list[9],
  48562         soc_portreg,
  48563         1,
  48564         0,
  48565         0x6c,
  48566         SOC_REG_FLAG_COUNTER,
  48567         0,
  48568         1,
  48569         soc_GR1023r_fields,
  48570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48572         150,
  48573         -1,
  48574     },
  48575 #endif /* chips */
  48576 
  48577 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  48578     { /* SOC_REG_INT_GT4095_BCM56820_A0r */
  48579         soc_block_list[206],
  48580         soc_portreg,
  48581         1,
  48582         0,
  48583         0xa8,
  48584         SOC_REG_FLAG_COUNTER,
  48585         0,
  48586         1,
  48587         soc_GR1023r_fields,
  48588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48589         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48590         220,
  48591         -1,
  48592     },
  48593 #endif /* chips */
  48594 
  48595 #if defined(BCM_88375_A0)
  48596     { /* SOC_REG_INT_GT4095_BCM88375_A0r */
  48597         soc_block_list[2],
  48598         soc_portreg,
  48599         1,
  48600         0,
  48601         0x3600,
  48602         SOC_REG_FLAG_COUNTER,
  48603         0,
  48604         1,
  48605         soc_GT4095_BCM88375_A0r_fields,
  48606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48608         54,
  48609         -1,
  48610     },
  48611 #endif /* chips */
  48612 
  48613 #if defined(BCM_88375_B0)
  48614     { /* SOC_REG_INT_GT4095_BCM88375_B0r */
  48615         soc_block_list[2],
  48616         soc_portreg,
  48617         1,
  48618         0,
  48619         0x3600,
  48620         SOC_REG_FLAG_COUNTER,
  48621         0,
  48622         1,
  48623         soc_GT4095_BCM88375_B0r_fields,
  48624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48625         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48626         54,
  48627         -1,
  48628     },
  48629 #endif /* chips */
  48630 
  48631 #if defined(BCM_88470_A0)
  48632     { /* SOC_REG_INT_GT4095_BCM88470_A0r */
  48633         soc_block_list[2],
  48634         soc_portreg,
  48635         1,
  48636         0,
  48637         0x3600,
  48638         SOC_REG_FLAG_COUNTER,
  48639         0,
  48640         1,
  48641         soc_GT4095_BCM88470_A0r_fields,
  48642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48643         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48644         54,
  48645         -1,
  48646     },
  48647 #endif /* chips */
  48648 
  48649 #if defined(BCM_88470_B0)
  48650     { /* SOC_REG_INT_GT4095_BCM88470_B0r */
  48651         soc_block_list[2],
  48652         soc_portreg,
  48653         1,
  48654         0,
  48655         0x3600,
  48656         SOC_REG_FLAG_COUNTER,
  48657         0,
  48658         1,
  48659         soc_GT4095_BCM88470_B0r_fields,
  48660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48661         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48662         54,
  48663         -1,
  48664     },
  48665 #endif /* chips */
  48666 
  48667 #if defined(BCM_88675_A0)
  48668     { /* SOC_REG_INT_GT4095_BCM88675_A0r */
  48669         soc_block_list[2],
  48670         soc_portreg,
  48671         1,
  48672         0,
  48673         0x3600,
  48674         SOC_REG_FLAG_COUNTER,
  48675         0,
  48676         1,
  48677         soc_GT4095r_fields,
  48678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48680         54,
  48681         -1,
  48682     },
  48683 #endif /* chips */
  48684 
  48685 #if defined(BCM_88675_B0)
  48686     { /* SOC_REG_INT_GT4095_BCM88675_B0r */
  48687         soc_block_list[2],
  48688         soc_portreg,
  48689         1,
  48690         0,
  48691         0x3600,
  48692         SOC_REG_FLAG_COUNTER,
  48693         0,
  48694         1,
  48695         soc_GT4095_BCM88675_B0r_fields,
  48696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48698         54,
  48699         -1,
  48700     },
  48701 #endif /* chips */
  48702 
  48703 #if defined(BCM_88680_A0)
  48704     { /* SOC_REG_INT_GT4095_BCM88680_A0r */
  48705         soc_block_list[2],
  48706         soc_portreg,
  48707         1,
  48708         0,
  48709         0x3600,
  48710         SOC_REG_FLAG_COUNTER,
  48711         0,
  48712         1,
  48713         soc_GT4095_BCM88680_A0r_fields,
  48714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48716         54,
  48717         -1,
  48718     },
  48719 #endif /* chips */
  48720 
  48721 #if defined(BCM_53570_A0)
  48722     { /* SOC_REG_INT_GT511Pr */
  48723         soc_block_list[2],
  48724         soc_portreg,
  48725         1,
  48726         0,
  48727         0x9700,
  48728         SOC_REG_FLAG_COUNTER,
  48729         0,
  48730         1,
  48731         soc_GR1023_BCM53400_A0r_fields,
  48732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48734         305,
  48735         -1,
  48736     },
  48737 #endif /* chips */
  48738 
  48739 #if defined(BCM_53570_B0)
  48740     { /* SOC_REG_INT_GT511P_BCM53570_B0r */
  48741         soc_block_list[2],
  48742         soc_portreg,
  48743         1,
  48744         0,
  48745         0x9700,
  48746         SOC_REG_FLAG_COUNTER,
  48747         0,
  48748         1,
  48749         soc_GR1023_BCM53400_A0r_fields,
  48750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48751         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48752         309,
  48753         -1,
  48754     },
  48755 #endif /* chips */
  48756 
  48757 #if defined(BCM_53400_A0)
  48758     { /* SOC_REG_INT_GT511_BCM53400_A0r */
  48759         soc_block_list[9],
  48760         soc_portreg,
  48761         1,
  48762         0,
  48763         0x3100,
  48764         SOC_REG_FLAG_COUNTER,
  48765         0,
  48766         1,
  48767         soc_GR1023_BCM53400_A0r_fields,
  48768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48769         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48770         148,
  48771         -1,
  48772     },
  48773 #endif /* chips */
  48774 
  48775 #if defined(BCM_53540_A0)
  48776     { /* SOC_REG_INT_GT511_BCM53540_A0r */
  48777         soc_block_list[2],
  48778         soc_portreg,
  48779         1,
  48780         0,
  48781         0x4200,
  48782         SOC_REG_FLAG_COUNTER,
  48783         0,
  48784         1,
  48785         soc_GR1023_BCM53400_A0r_fields,
  48786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48787         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48788         165,
  48789         -1,
  48790     },
  48791 #endif /* chips */
  48792 
  48793 #if defined(BCM_53570_A0)
  48794     { /* SOC_REG_INT_GT511_BCM53570_A0r */
  48795         soc_block_list[2],
  48796         soc_portreg,
  48797         1,
  48798         0,
  48799         0x4200,
  48800         SOC_REG_FLAG_COUNTER,
  48801         0,
  48802         1,
  48803         soc_GR1023_BCM53400_A0r_fields,
  48804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48805         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48806         220,
  48807         -1,
  48808     },
  48809 #endif /* chips */
  48810 
  48811 #if defined(BCM_53570_B0)
  48812     { /* SOC_REG_INT_GT511_BCM53570_B0r */
  48813         soc_block_list[2],
  48814         soc_portreg,
  48815         1,
  48816         0,
  48817         0x4200,
  48818         SOC_REG_FLAG_COUNTER,
  48819         0,
  48820         1,
  48821         soc_GR1023_BCM53400_A0r_fields,
  48822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48823         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48824         224,
  48825         -1,
  48826     },
  48827 #endif /* chips */
  48828 
  48829 #if defined(BCM_56142_A0)
  48830     { /* SOC_REG_INT_GT511_BCM56142_A0r */
  48831         soc_block_list[210],
  48832         soc_portreg,
  48833         1,
  48834         0,
  48835         0xb1,
  48836         SOC_REG_FLAG_COUNTER,
  48837         0,
  48838         1,
  48839         soc_GR1023r_fields,
  48840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48841         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48842         224,
  48843         -1,
  48844     },
  48845 #endif /* chips */
  48846 
  48847 #if defined(BCM_56150_A0)
  48848     { /* SOC_REG_INT_GT511_BCM56150_A0r */
  48849         soc_block_list[2],
  48850         soc_portreg,
  48851         1,
  48852         0,
  48853         0x3100,
  48854         SOC_REG_FLAG_COUNTER,
  48855         0,
  48856         1,
  48857         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  48858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48859         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48860         144,
  48861         -1,
  48862     },
  48863 #endif /* chips */
  48864 
  48865 #if defined(BCM_56160_A0)
  48866     { /* SOC_REG_INT_GT511_BCM56160_A0r */
  48867         soc_block_list[2],
  48868         soc_portreg,
  48869         1,
  48870         0,
  48871         0x4200,
  48872         SOC_REG_FLAG_COUNTER,
  48873         0,
  48874         1,
  48875         soc_GR1023_BCM53400_A0r_fields,
  48876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48877         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48878         165,
  48879         -1,
  48880     },
  48881 #endif /* chips */
  48882 
  48883 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  48884     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  48885     { /* SOC_REG_INT_GT511_BCM56224_A0r */
  48886         soc_block_list[2],
  48887         soc_portreg,
  48888         1,
  48889         0,
  48890         0x31,
  48891         SOC_REG_FLAG_COUNTER,
  48892         0,
  48893         1,
  48894         soc_GR1023r_fields,
  48895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48896         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48897         83,
  48898         -1,
  48899     },
  48900 #endif /* chips */
  48901 
  48902 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  48903     { /* SOC_REG_INT_GT511_BCM56334_A0r */
  48904         soc_block_list[210],
  48905         soc_portreg,
  48906         1,
  48907         0,
  48908         0xb1,
  48909         SOC_REG_FLAG_COUNTER,
  48910         0,
  48911         1,
  48912         soc_GR1023r_fields,
  48913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48914         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48915         219,
  48916         -1,
  48917     },
  48918 #endif /* chips */
  48919 
  48920 #if defined(BCM_56370_A0)
  48921     { /* SOC_REG_INT_GT511_BCM56370_A0r */
  48922         soc_block_list[9],
  48923         soc_portreg,
  48924         1,
  48925         0,
  48926         0x3200,
  48927         SOC_REG_FLAG_COUNTER,
  48928         0,
  48929         1,
  48930         soc_GR1023_BCM53400_A0r_fields,
  48931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48932         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48933         110,
  48934         -1,
  48935         3,
  48936     },
  48937 #endif /* chips */
  48938 
  48939 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48940     { /* SOC_REG_INT_GT511_BCM56440_A0r */
  48941         soc_block_list[2],
  48942         soc_portreg,
  48943         1,
  48944         0,
  48945         0xb2,
  48946         SOC_REG_FLAG_COUNTER,
  48947         0,
  48948         1,
  48949         soc_GR1023r_fields,
  48950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48952         217,
  48953         -1,
  48954     },
  48955 #endif /* chips */
  48956 
  48957 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  48958     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  48959     { /* SOC_REG_INT_GT511_BCM56624_A0r */
  48960         soc_block_list[205],
  48961         soc_portreg,
  48962         1,
  48963         0,
  48964         0xa2,
  48965         SOC_REG_FLAG_COUNTER,
  48966         0,
  48967         1,
  48968         soc_GR1023r_fields,
  48969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48971         204,
  48972         -1,
  48973     },
  48974 #endif /* chips */
  48975 
  48976 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  48977     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  48978     { /* SOC_REG_INT_GT511_BCM56634_A0r */
  48979         soc_block_list[207],
  48980         soc_portreg,
  48981         1,
  48982         0,
  48983         0xa2,
  48984         SOC_REG_FLAG_COUNTER,
  48985         0,
  48986         1,
  48987         soc_GR1023r_fields,
  48988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48990         204,
  48991         -1,
  48992     },
  48993 #endif /* chips */
  48994 
  48995 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  48996     { /* SOC_REG_INT_GT511_BCM56685_A0r */
  48997         soc_block_list[209],
  48998         soc_portreg,
  48999         1,
  49000         0,
  49001         0xa2,
  49002         SOC_REG_FLAG_COUNTER,
  49003         0,
  49004         1,
  49005         soc_GR1023r_fields,
  49006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49007         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49008         204,
  49009         -1,
  49010     },
  49011 #endif /* chips */
  49012 
  49013 #if defined(BCM_56800_A0)
  49014     { /* SOC_REG_INT_GT511_BCM56800_A0r */
  49015         soc_block_list[9],
  49016         soc_portreg,
  49017         1,
  49018         0,
  49019         0x67,
  49020         SOC_REG_FLAG_COUNTER,
  49021         0,
  49022         1,
  49023         soc_GR1023r_fields,
  49024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49026         145,
  49027         -1,
  49028     },
  49029 #endif /* chips */
  49030 
  49031 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  49032     { /* SOC_REG_INT_GT511_BCM56820_A0r */
  49033         soc_block_list[206],
  49034         soc_portreg,
  49035         1,
  49036         0,
  49037         0xa3,
  49038         SOC_REG_FLAG_COUNTER,
  49039         0,
  49040         1,
  49041         soc_GR1023r_fields,
  49042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49044         215,
  49045         -1,
  49046     },
  49047 #endif /* chips */
  49048 
  49049 #if defined(BCM_88375_A0)
  49050     { /* SOC_REG_INT_GT511_BCM88375_A0r */
  49051         soc_block_list[2],
  49052         soc_portreg,
  49053         1,
  49054         0,
  49055         0x3100,
  49056         SOC_REG_FLAG_COUNTER,
  49057         0,
  49058         1,
  49059         soc_GT511_BCM88375_A0r_fields,
  49060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49061         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49062         49,
  49063         -1,
  49064     },
  49065 #endif /* chips */
  49066 
  49067 #if defined(BCM_88375_B0)
  49068     { /* SOC_REG_INT_GT511_BCM88375_B0r */
  49069         soc_block_list[2],
  49070         soc_portreg,
  49071         1,
  49072         0,
  49073         0x3100,
  49074         SOC_REG_FLAG_COUNTER,
  49075         0,
  49076         1,
  49077         soc_GT511_BCM88375_B0r_fields,
  49078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49080         49,
  49081         -1,
  49082     },
  49083 #endif /* chips */
  49084 
  49085 #if defined(BCM_88470_A0)
  49086     { /* SOC_REG_INT_GT511_BCM88470_A0r */
  49087         soc_block_list[2],
  49088         soc_portreg,
  49089         1,
  49090         0,
  49091         0x3100,
  49092         SOC_REG_FLAG_COUNTER,
  49093         0,
  49094         1,
  49095         soc_GT511_BCM88470_A0r_fields,
  49096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49098         49,
  49099         -1,
  49100     },
  49101 #endif /* chips */
  49102 
  49103 #if defined(BCM_88470_B0)
  49104     { /* SOC_REG_INT_GT511_BCM88470_B0r */
  49105         soc_block_list[2],
  49106         soc_portreg,
  49107         1,
  49108         0,
  49109         0x3100,
  49110         SOC_REG_FLAG_COUNTER,
  49111         0,
  49112         1,
  49113         soc_GT511_BCM88470_B0r_fields,
  49114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49116         49,
  49117         -1,
  49118     },
  49119 #endif /* chips */
  49120 
  49121 #if defined(BCM_88675_A0)
  49122     { /* SOC_REG_INT_GT511_BCM88675_A0r */
  49123         soc_block_list[2],
  49124         soc_portreg,
  49125         1,
  49126         0,
  49127         0x3100,
  49128         SOC_REG_FLAG_COUNTER,
  49129         0,
  49130         1,
  49131         soc_GT511r_fields,
  49132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49133         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49134         49,
  49135         -1,
  49136     },
  49137 #endif /* chips */
  49138 
  49139 #if defined(BCM_88675_B0)
  49140     { /* SOC_REG_INT_GT511_BCM88675_B0r */
  49141         soc_block_list[2],
  49142         soc_portreg,
  49143         1,
  49144         0,
  49145         0x3100,
  49146         SOC_REG_FLAG_COUNTER,
  49147         0,
  49148         1,
  49149         soc_GT511_BCM88675_B0r_fields,
  49150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49151         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49152         49,
  49153         -1,
  49154     },
  49155 #endif /* chips */
  49156 
  49157 #if defined(BCM_88680_A0)
  49158     { /* SOC_REG_INT_GT511_BCM88680_A0r */
  49159         soc_block_list[2],
  49160         soc_portreg,
  49161         1,
  49162         0,
  49163         0x3100,
  49164         SOC_REG_FLAG_COUNTER,
  49165         0,
  49166         1,
  49167         soc_GT511_BCM88680_A0r_fields,
  49168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49169         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49170         49,
  49171         -1,
  49172     },
  49173 #endif /* chips */
  49174 
  49175 #if defined(BCM_53570_A0)
  49176     { /* SOC_REG_INT_GT64Pr */
  49177         soc_block_list[2],
  49178         soc_portreg,
  49179         1,
  49180         0,
  49181         0x9400,
  49182         SOC_REG_FLAG_COUNTER,
  49183         0,
  49184         1,
  49185         soc_GR1023_BCM53400_A0r_fields,
  49186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49188         302,
  49189         -1,
  49190     },
  49191 #endif /* chips */
  49192 
  49193 #if defined(BCM_53570_B0)
  49194     { /* SOC_REG_INT_GT64P_BCM53570_B0r */
  49195         soc_block_list[2],
  49196         soc_portreg,
  49197         1,
  49198         0,
  49199         0x9400,
  49200         SOC_REG_FLAG_COUNTER,
  49201         0,
  49202         1,
  49203         soc_GR1023_BCM53400_A0r_fields,
  49204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49206         306,
  49207         -1,
  49208     },
  49209 #endif /* chips */
  49210 
  49211 #if defined(BCM_53400_A0)
  49212     { /* SOC_REG_INT_GT64_BCM53400_A0r */
  49213         soc_block_list[9],
  49214         soc_portreg,
  49215         1,
  49216         0,
  49217         0x2e00,
  49218         SOC_REG_FLAG_COUNTER,
  49219         0,
  49220         1,
  49221         soc_GR1023_BCM53400_A0r_fields,
  49222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49224         145,
  49225         -1,
  49226     },
  49227 #endif /* chips */
  49228 
  49229 #if defined(BCM_53540_A0)
  49230     { /* SOC_REG_INT_GT64_BCM53540_A0r */
  49231         soc_block_list[2],
  49232         soc_portreg,
  49233         1,
  49234         0,
  49235         0x3f00,
  49236         SOC_REG_FLAG_COUNTER,
  49237         0,
  49238         1,
  49239         soc_GR1023_BCM53400_A0r_fields,
  49240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49241         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49242         162,
  49243         -1,
  49244     },
  49245 #endif /* chips */
  49246 
  49247 #if defined(BCM_53570_A0)
  49248     { /* SOC_REG_INT_GT64_BCM53570_A0r */
  49249         soc_block_list[2],
  49250         soc_portreg,
  49251         1,
  49252         0,
  49253         0x3f00,
  49254         SOC_REG_FLAG_COUNTER,
  49255         0,
  49256         1,
  49257         soc_GR1023_BCM53400_A0r_fields,
  49258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49259         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49260         217,
  49261         -1,
  49262     },
  49263 #endif /* chips */
  49264 
  49265 #if defined(BCM_53570_B0)
  49266     { /* SOC_REG_INT_GT64_BCM53570_B0r */
  49267         soc_block_list[2],
  49268         soc_portreg,
  49269         1,
  49270         0,
  49271         0x3f00,
  49272         SOC_REG_FLAG_COUNTER,
  49273         0,
  49274         1,
  49275         soc_GR1023_BCM53400_A0r_fields,
  49276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49277         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49278         221,
  49279         -1,
  49280     },
  49281 #endif /* chips */
  49282 
  49283 #if defined(BCM_56142_A0)
  49284     { /* SOC_REG_INT_GT64_BCM56142_A0r */
  49285         soc_block_list[210],
  49286         soc_portreg,
  49287         1,
  49288         0,
  49289         0xae,
  49290         SOC_REG_FLAG_COUNTER,
  49291         0,
  49292         1,
  49293         soc_GR1023r_fields,
  49294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49296         221,
  49297         -1,
  49298     },
  49299 #endif /* chips */
  49300 
  49301 #if defined(BCM_56150_A0)
  49302     { /* SOC_REG_INT_GT64_BCM56150_A0r */
  49303         soc_block_list[2],
  49304         soc_portreg,
  49305         1,
  49306         0,
  49307         0x2e00,
  49308         SOC_REG_FLAG_COUNTER,
  49309         0,
  49310         1,
  49311         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  49312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49313         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49314         141,
  49315         -1,
  49316     },
  49317 #endif /* chips */
  49318 
  49319 #if defined(BCM_56160_A0)
  49320     { /* SOC_REG_INT_GT64_BCM56160_A0r */
  49321         soc_block_list[2],
  49322         soc_portreg,
  49323         1,
  49324         0,
  49325         0x3f00,
  49326         SOC_REG_FLAG_COUNTER,
  49327         0,
  49328         1,
  49329         soc_GR1023_BCM53400_A0r_fields,
  49330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49332         162,
  49333         -1,
  49334     },
  49335 #endif /* chips */
  49336 
  49337 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  49338     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  49339     { /* SOC_REG_INT_GT64_BCM56224_A0r */
  49340         soc_block_list[2],
  49341         soc_portreg,
  49342         1,
  49343         0,
  49344         0x2e,
  49345         SOC_REG_FLAG_COUNTER,
  49346         0,
  49347         1,
  49348         soc_GR1023r_fields,
  49349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49351         80,
  49352         -1,
  49353     },
  49354 #endif /* chips */
  49355 
  49356 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  49357     { /* SOC_REG_INT_GT64_BCM56334_A0r */
  49358         soc_block_list[210],
  49359         soc_portreg,
  49360         1,
  49361         0,
  49362         0xae,
  49363         SOC_REG_FLAG_COUNTER,
  49364         0,
  49365         1,
  49366         soc_GR1023r_fields,
  49367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49369         216,
  49370         -1,
  49371     },
  49372 #endif /* chips */
  49373 
  49374 #if defined(BCM_56370_A0)
  49375     { /* SOC_REG_INT_GT64_BCM56370_A0r */
  49376         soc_block_list[9],
  49377         soc_portreg,
  49378         1,
  49379         0,
  49380         0x2f00,
  49381         SOC_REG_FLAG_COUNTER,
  49382         0,
  49383         1,
  49384         soc_GR1023_BCM53400_A0r_fields,
  49385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49386         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49387         107,
  49388         -1,
  49389         3,
  49390     },
  49391 #endif /* chips */
  49392 
  49393 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  49394     { /* SOC_REG_INT_GT64_BCM56440_A0r */
  49395         soc_block_list[2],
  49396         soc_portreg,
  49397         1,
  49398         0,
  49399         0xaf,
  49400         SOC_REG_FLAG_COUNTER,
  49401         0,
  49402         1,
  49403         soc_GR1023r_fields,
  49404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49405         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49406         214,
  49407         -1,
  49408     },
  49409 #endif /* chips */
  49410 
  49411 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  49412     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  49413     { /* SOC_REG_INT_GT64_BCM56624_A0r */
  49414         soc_block_list[205],
  49415         soc_portreg,
  49416         1,
  49417         0,
  49418         0x9f,
  49419         SOC_REG_FLAG_COUNTER,
  49420         0,
  49421         1,
  49422         soc_GR1023r_fields,
  49423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49424         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49425         201,
  49426         -1,
  49427     },
  49428 #endif /* chips */
  49429 
  49430 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  49431     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  49432     { /* SOC_REG_INT_GT64_BCM56634_A0r */
  49433         soc_block_list[207],
  49434         soc_portreg,
  49435         1,
  49436         0,
  49437         0x9f,
  49438         SOC_REG_FLAG_COUNTER,
  49439         0,
  49440         1,
  49441         soc_GR1023r_fields,
  49442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49443         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49444         201,
  49445         -1,
  49446     },
  49447 #endif /* chips */
  49448 
  49449 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  49450     { /* SOC_REG_INT_GT64_BCM56685_A0r */
  49451         soc_block_list[209],
  49452         soc_portreg,
  49453         1,
  49454         0,
  49455         0x9f,
  49456         SOC_REG_FLAG_COUNTER,
  49457         0,
  49458         1,
  49459         soc_GR1023r_fields,
  49460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49461         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49462         201,
  49463         -1,
  49464     },
  49465 #endif /* chips */
  49466 
  49467 #if defined(BCM_56800_A0)
  49468     { /* SOC_REG_INT_GT64_BCM56800_A0r */
  49469         soc_block_list[9],
  49470         soc_portreg,
  49471         1,
  49472         0,
  49473         0x64,
  49474         SOC_REG_FLAG_COUNTER,
  49475         0,
  49476         1,
  49477         soc_GR1023r_fields,
  49478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49479         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49480         142,
  49481         -1,
  49482     },
  49483 #endif /* chips */
  49484 
  49485 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  49486     { /* SOC_REG_INT_GT64_BCM56820_A0r */
  49487         soc_block_list[206],
  49488         soc_portreg,
  49489         1,
  49490         0,
  49491         0xa0,
  49492         SOC_REG_FLAG_COUNTER,
  49493         0,
  49494         1,
  49495         soc_GR1023r_fields,
  49496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49497         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49498         212,
  49499         -1,
  49500     },
  49501 #endif /* chips */
  49502 
  49503 #if defined(BCM_88375_A0)
  49504     { /* SOC_REG_INT_GT64_BCM88375_A0r */
  49505         soc_block_list[2],
  49506         soc_portreg,
  49507         1,
  49508         0,
  49509         0x2e00,
  49510         SOC_REG_FLAG_COUNTER,
  49511         0,
  49512         1,
  49513         soc_GT64_BCM88375_A0r_fields,
  49514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49516         46,
  49517         -1,
  49518     },
  49519 #endif /* chips */
  49520 
  49521 #if defined(BCM_88375_B0)
  49522     { /* SOC_REG_INT_GT64_BCM88375_B0r */
  49523         soc_block_list[2],
  49524         soc_portreg,
  49525         1,
  49526         0,
  49527         0x2e00,
  49528         SOC_REG_FLAG_COUNTER,
  49529         0,
  49530         1,
  49531         soc_GT64_BCM88375_B0r_fields,
  49532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49534         46,
  49535         -1,
  49536     },
  49537 #endif /* chips */
  49538 
  49539 #if defined(BCM_88470_A0)
  49540     { /* SOC_REG_INT_GT64_BCM88470_A0r */
  49541         soc_block_list[2],
  49542         soc_portreg,
  49543         1,
  49544         0,
  49545         0x2e00,
  49546         SOC_REG_FLAG_COUNTER,
  49547         0,
  49548         1,
  49549         soc_GT64_BCM88470_A0r_fields,
  49550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49552         46,
  49553         -1,
  49554     },
  49555 #endif /* chips */
  49556 
  49557 #if defined(BCM_88470_B0)
  49558     { /* SOC_REG_INT_GT64_BCM88470_B0r */
  49559         soc_block_list[2],
  49560         soc_portreg,
  49561         1,
  49562         0,
  49563         0x2e00,
  49564         SOC_REG_FLAG_COUNTER,
  49565         0,
  49566         1,
  49567         soc_GT64_BCM88470_B0r_fields,
  49568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49570         46,
  49571         -1,
  49572     },
  49573 #endif /* chips */
  49574 
  49575 #if defined(BCM_88675_A0)
  49576     { /* SOC_REG_INT_GT64_BCM88675_A0r */
  49577         soc_block_list[2],
  49578         soc_portreg,
  49579         1,
  49580         0,
  49581         0x2e00,
  49582         SOC_REG_FLAG_COUNTER,
  49583         0,
  49584         1,
  49585         soc_GT64r_fields,
  49586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49587         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49588         46,
  49589         -1,
  49590     },
  49591 #endif /* chips */
  49592 
  49593 #if defined(BCM_88675_B0)
  49594     { /* SOC_REG_INT_GT64_BCM88675_B0r */
  49595         soc_block_list[2],
  49596         soc_portreg,
  49597         1,
  49598         0,
  49599         0x2e00,
  49600         SOC_REG_FLAG_COUNTER,
  49601         0,
  49602         1,
  49603         soc_GT64_BCM88675_B0r_fields,
  49604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49605         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49606         46,
  49607         -1,
  49608     },
  49609 #endif /* chips */
  49610 
  49611 #if defined(BCM_88680_A0)
  49612     { /* SOC_REG_INT_GT64_BCM88680_A0r */
  49613         soc_block_list[2],
  49614         soc_portreg,
  49615         1,
  49616         0,
  49617         0x2e00,
  49618         SOC_REG_FLAG_COUNTER,
  49619         0,
  49620         1,
  49621         soc_GT64_BCM88680_A0r_fields,
  49622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49623         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49624         46,
  49625         -1,
  49626     },
  49627 #endif /* chips */
  49628 
  49629 #if defined(BCM_53570_A0)
  49630     { /* SOC_REG_INT_GT9216Pr */
  49631         soc_block_list[2],
  49632         soc_portreg,
  49633         1,
  49634         0,
  49635         0x9d00,
  49636         SOC_REG_FLAG_COUNTER,
  49637         0,
  49638         1,
  49639         soc_GR1023_BCM53400_A0r_fields,
  49640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49641         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49642         311,
  49643         -1,
  49644     },
  49645 #endif /* chips */
  49646 
  49647 #if defined(BCM_53570_B0)
  49648     { /* SOC_REG_INT_GT9216P_BCM53570_B0r */
  49649         soc_block_list[2],
  49650         soc_portreg,
  49651         1,
  49652         0,
  49653         0x9d00,
  49654         SOC_REG_FLAG_COUNTER,
  49655         0,
  49656         1,
  49657         soc_GR1023_BCM53400_A0r_fields,
  49658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49659         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49660         315,
  49661         -1,
  49662     },
  49663 #endif /* chips */
  49664 
  49665 #if defined(BCM_53400_A0)
  49666     { /* SOC_REG_INT_GT9216_BCM53400_A0r */
  49667         soc_block_list[9],
  49668         soc_portreg,
  49669         1,
  49670         0,
  49671         0x3700,
  49672         SOC_REG_FLAG_COUNTER,
  49673         0,
  49674         1,
  49675         soc_GR1023_BCM53400_A0r_fields,
  49676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49677         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49678         154,
  49679         -1,
  49680     },
  49681 #endif /* chips */
  49682 
  49683 #if defined(BCM_53540_A0)
  49684     { /* SOC_REG_INT_GT9216_BCM53540_A0r */
  49685         soc_block_list[2],
  49686         soc_portreg,
  49687         1,
  49688         0,
  49689         0x4800,
  49690         SOC_REG_FLAG_COUNTER,
  49691         0,
  49692         1,
  49693         soc_GR1023_BCM53400_A0r_fields,
  49694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49695         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49696         171,
  49697         -1,
  49698     },
  49699 #endif /* chips */
  49700 
  49701 #if defined(BCM_53570_A0)
  49702     { /* SOC_REG_INT_GT9216_BCM53570_A0r */
  49703         soc_block_list[2],
  49704         soc_portreg,
  49705         1,
  49706         0,
  49707         0x4800,
  49708         SOC_REG_FLAG_COUNTER,
  49709         0,
  49710         1,
  49711         soc_GR1023_BCM53400_A0r_fields,
  49712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49713         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49714         226,
  49715         -1,
  49716     },
  49717 #endif /* chips */
  49718 
  49719 #if defined(BCM_53570_B0)
  49720     { /* SOC_REG_INT_GT9216_BCM53570_B0r */
  49721         soc_block_list[2],
  49722         soc_portreg,
  49723         1,
  49724         0,
  49725         0x4800,
  49726         SOC_REG_FLAG_COUNTER,
  49727         0,
  49728         1,
  49729         soc_GR1023_BCM53400_A0r_fields,
  49730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49731         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49732         230,
  49733         -1,
  49734     },
  49735 #endif /* chips */
  49736 
  49737 #if defined(BCM_56142_A0)
  49738     { /* SOC_REG_INT_GT9216_BCM56142_A0r */
  49739         soc_block_list[210],
  49740         soc_portreg,
  49741         1,
  49742         0,
  49743         0xb7,
  49744         SOC_REG_FLAG_COUNTER,
  49745         0,
  49746         1,
  49747         soc_GR1023r_fields,
  49748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49749         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49750         230,
  49751         -1,
  49752     },
  49753 #endif /* chips */
  49754 
  49755 #if defined(BCM_56150_A0)
  49756     { /* SOC_REG_INT_GT9216_BCM56150_A0r */
  49757         soc_block_list[2],
  49758         soc_portreg,
  49759         1,
  49760         0,
  49761         0x3700,
  49762         SOC_REG_FLAG_COUNTER,
  49763         0,
  49764         1,
  49765         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  49766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49767         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49768         150,
  49769         -1,
  49770     },
  49771 #endif /* chips */
  49772 
  49773 #if defined(BCM_56160_A0)
  49774     { /* SOC_REG_INT_GT9216_BCM56160_A0r */
  49775         soc_block_list[2],
  49776         soc_portreg,
  49777         1,
  49778         0,
  49779         0x4800,
  49780         SOC_REG_FLAG_COUNTER,
  49781         0,
  49782         1,
  49783         soc_GR1023_BCM53400_A0r_fields,
  49784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49785         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49786         171,
  49787         -1,
  49788     },
  49789 #endif /* chips */
  49790 
  49791 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  49792     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  49793     { /* SOC_REG_INT_GT9216_BCM56224_A0r */
  49794         soc_block_list[2],
  49795         soc_portreg,
  49796         1,
  49797         0,
  49798         0x37,
  49799         SOC_REG_FLAG_COUNTER,
  49800         0,
  49801         1,
  49802         soc_GR1023r_fields,
  49803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49804         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49805         89,
  49806         -1,
  49807     },
  49808 #endif /* chips */
  49809 
  49810 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  49811     { /* SOC_REG_INT_GT9216_BCM56334_A0r */
  49812         soc_block_list[210],
  49813         soc_portreg,
  49814         1,
  49815         0,
  49816         0xb7,
  49817         SOC_REG_FLAG_COUNTER,
  49818         0,
  49819         1,
  49820         soc_GR1023r_fields,
  49821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49822         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49823         225,
  49824         -1,
  49825     },
  49826 #endif /* chips */
  49827 
  49828 #if defined(BCM_56370_A0)
  49829     { /* SOC_REG_INT_GT9216_BCM56370_A0r */
  49830         soc_block_list[9],
  49831         soc_portreg,
  49832         1,
  49833         0,
  49834         0x3800,
  49835         SOC_REG_FLAG_COUNTER,
  49836         0,
  49837         1,
  49838         soc_GR1023_BCM53400_A0r_fields,
  49839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49840         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49841         116,
  49842         -1,
  49843         3,
  49844     },
  49845 #endif /* chips */
  49846 
  49847 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  49848     { /* SOC_REG_INT_GT9216_BCM56440_A0r */
  49849         soc_block_list[2],
  49850         soc_portreg,
  49851         1,
  49852         0,
  49853         0xb8,
  49854         SOC_REG_FLAG_COUNTER,
  49855         0,
  49856         1,
  49857         soc_GR1023r_fields,
  49858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49859         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49860         223,
  49861         -1,
  49862     },
  49863 #endif /* chips */
  49864 
  49865 #if defined(BCM_56514_A0)
  49866     { /* SOC_REG_INT_GT9216_BCM56514_A0r */
  49867         soc_block_list[2],
  49868         soc_portreg,
  49869         1,
  49870         0,
  49871         0x28,
  49872         SOC_REG_FLAG_COUNTER,
  49873         0,
  49874         1,
  49875         soc_GR1023r_fields,
  49876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49877         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49878         74,
  49879         -1,
  49880     },
  49881 #endif /* chips */
  49882 
  49883 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  49884     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  49885     { /* SOC_REG_INT_GT9216_BCM56624_A0r */
  49886         soc_block_list[205],
  49887         soc_portreg,
  49888         1,
  49889         0,
  49890         0xa8,
  49891         SOC_REG_FLAG_COUNTER,
  49892         0,
  49893         1,
  49894         soc_GR1023r_fields,
  49895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49896         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49897         210,
  49898         -1,
  49899     },
  49900 #endif /* chips */
  49901 
  49902 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  49903     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  49904     { /* SOC_REG_INT_GT9216_BCM56634_A0r */
  49905         soc_block_list[207],
  49906         soc_portreg,
  49907         1,
  49908         0,
  49909         0xa8,
  49910         SOC_REG_FLAG_COUNTER,
  49911         0,
  49912         1,
  49913         soc_GR1023r_fields,
  49914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49916         210,
  49917         -1,
  49918     },
  49919 #endif /* chips */
  49920 
  49921 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  49922     { /* SOC_REG_INT_GT9216_BCM56685_A0r */
  49923         soc_block_list[209],
  49924         soc_portreg,
  49925         1,
  49926         0,
  49927         0xa8,
  49928         SOC_REG_FLAG_COUNTER,
  49929         0,
  49930         1,
  49931         soc_GR1023r_fields,
  49932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49934         210,
  49935         -1,
  49936     },
  49937 #endif /* chips */
  49938 
  49939 #if defined(BCM_56800_A0)
  49940     { /* SOC_REG_INT_GT9216_BCM56800_A0r */
  49941         soc_block_list[9],
  49942         soc_portreg,
  49943         1,
  49944         0,
  49945         0x6d,
  49946         SOC_REG_FLAG_COUNTER,
  49947         0,
  49948         1,
  49949         soc_GR1023r_fields,
  49950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49952         151,
  49953         -1,
  49954     },
  49955 #endif /* chips */
  49956 
  49957 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  49958     { /* SOC_REG_INT_GT9216_BCM56820_A0r */
  49959         soc_block_list[206],
  49960         soc_portreg,
  49961         1,
  49962         0,
  49963         0xa9,
  49964         SOC_REG_FLAG_COUNTER,
  49965         0,
  49966         1,
  49967         soc_GR1023r_fields,
  49968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49970         221,
  49971         -1,
  49972     },
  49973 #endif /* chips */
  49974 
  49975 #if defined(BCM_88375_A0)
  49976     { /* SOC_REG_INT_GT9216_BCM88375_A0r */
  49977         soc_block_list[2],
  49978         soc_portreg,
  49979         1,
  49980         0,
  49981         0x3700,
  49982         SOC_REG_FLAG_COUNTER,
  49983         0,
  49984         1,
  49985         soc_GT9216_BCM88375_A0r_fields,
  49986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49987         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  49988         55,
  49989         -1,
  49990     },
  49991 #endif /* chips */
  49992 
  49993 #if defined(BCM_88375_B0)
  49994     { /* SOC_REG_INT_GT9216_BCM88375_B0r */
  49995         soc_block_list[2],
  49996         soc_portreg,
  49997         1,
  49998         0,
  49999         0x3700,
  50000         SOC_REG_FLAG_COUNTER,
  50001         0,
  50002         1,
  50003         soc_GT9216_BCM88375_B0r_fields,
  50004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50005         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50006         55,
  50007         -1,
  50008     },
  50009 #endif /* chips */
  50010 
  50011 #if defined(BCM_88470_A0)
  50012     { /* SOC_REG_INT_GT9216_BCM88470_A0r */
  50013         soc_block_list[2],
  50014         soc_portreg,
  50015         1,
  50016         0,
  50017         0x3700,
  50018         SOC_REG_FLAG_COUNTER,
  50019         0,
  50020         1,
  50021         soc_GT9216_BCM88470_A0r_fields,
  50022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50023         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50024         55,
  50025         -1,
  50026     },
  50027 #endif /* chips */
  50028 
  50029 #if defined(BCM_88470_B0)
  50030     { /* SOC_REG_INT_GT9216_BCM88470_B0r */
  50031         soc_block_list[2],
  50032         soc_portreg,
  50033         1,
  50034         0,
  50035         0x3700,
  50036         SOC_REG_FLAG_COUNTER,
  50037         0,
  50038         1,
  50039         soc_GT9216_BCM88470_B0r_fields,
  50040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50041         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50042         55,
  50043         -1,
  50044     },
  50045 #endif /* chips */
  50046 
  50047 #if defined(BCM_88675_A0)
  50048     { /* SOC_REG_INT_GT9216_BCM88675_A0r */
  50049         soc_block_list[2],
  50050         soc_portreg,
  50051         1,
  50052         0,
  50053         0x3700,
  50054         SOC_REG_FLAG_COUNTER,
  50055         0,
  50056         1,
  50057         soc_GT9216r_fields,
  50058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50060         55,
  50061         -1,
  50062     },
  50063 #endif /* chips */
  50064 
  50065 #if defined(BCM_88675_B0)
  50066     { /* SOC_REG_INT_GT9216_BCM88675_B0r */
  50067         soc_block_list[2],
  50068         soc_portreg,
  50069         1,
  50070         0,
  50071         0x3700,
  50072         SOC_REG_FLAG_COUNTER,
  50073         0,
  50074         1,
  50075         soc_GT9216_BCM88675_B0r_fields,
  50076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50078         55,
  50079         -1,
  50080     },
  50081 #endif /* chips */
  50082 
  50083 #if defined(BCM_88680_A0)
  50084     { /* SOC_REG_INT_GT9216_BCM88680_A0r */
  50085         soc_block_list[2],
  50086         soc_portreg,
  50087         1,
  50088         0,
  50089         0x3700,
  50090         SOC_REG_FLAG_COUNTER,
  50091         0,
  50092         1,
  50093         soc_GT9216_BCM88680_A0r_fields,
  50094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50096         55,
  50097         -1,
  50098     },
  50099 #endif /* chips */
  50100 
  50101 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  50102     defined(BCM_56504_B0)
  50103     { /* SOC_REG_INT_GTBCAr */
  50104         soc_block_list[2],
  50105         soc_portreg,
  50106         1,
  50107         0,
  50108         0x29,
  50109         SOC_REG_FLAG_COUNTER,
  50110         0,
  50111         1,
  50112         soc_GR1023r_fields,
  50113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50114         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50115         75,
  50116         -1,
  50117     },
  50118 #endif /* chips */
  50119 
  50120 #if defined(BCM_53570_A0)
  50121     { /* SOC_REG_INT_GTBCAPr */
  50122         soc_block_list[2],
  50123         soc_portreg,
  50124         1,
  50125         0,
  50126         0x9300,
  50127         SOC_REG_FLAG_COUNTER,
  50128         0,
  50129         1,
  50130         soc_GR1023_BCM53400_A0r_fields,
  50131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50132         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50133         301,
  50134         -1,
  50135     },
  50136 #endif /* chips */
  50137 
  50138 #if defined(BCM_53570_B0)
  50139     { /* SOC_REG_INT_GTBCAP_BCM53570_B0r */
  50140         soc_block_list[2],
  50141         soc_portreg,
  50142         1,
  50143         0,
  50144         0x9300,
  50145         SOC_REG_FLAG_COUNTER,
  50146         0,
  50147         1,
  50148         soc_GR1023_BCM53400_A0r_fields,
  50149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50150         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50151         305,
  50152         -1,
  50153     },
  50154 #endif /* chips */
  50155 
  50156 #if defined(BCM_53400_A0)
  50157     { /* SOC_REG_INT_GTBCA_BCM53400_A0r */
  50158         soc_block_list[9],
  50159         soc_portreg,
  50160         1,
  50161         0,
  50162         0x2d00,
  50163         SOC_REG_FLAG_COUNTER,
  50164         0,
  50165         1,
  50166         soc_GR1023_BCM53400_A0r_fields,
  50167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50169         144,
  50170         -1,
  50171     },
  50172 #endif /* chips */
  50173 
  50174 #if defined(BCM_53540_A0)
  50175     { /* SOC_REG_INT_GTBCA_BCM53540_A0r */
  50176         soc_block_list[2],
  50177         soc_portreg,
  50178         1,
  50179         0,
  50180         0x3e00,
  50181         SOC_REG_FLAG_COUNTER,
  50182         0,
  50183         1,
  50184         soc_GR1023_BCM53400_A0r_fields,
  50185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50187         161,
  50188         -1,
  50189     },
  50190 #endif /* chips */
  50191 
  50192 #if defined(BCM_53570_A0)
  50193     { /* SOC_REG_INT_GTBCA_BCM53570_A0r */
  50194         soc_block_list[2],
  50195         soc_portreg,
  50196         1,
  50197         0,
  50198         0x3e00,
  50199         SOC_REG_FLAG_COUNTER,
  50200         0,
  50201         1,
  50202         soc_GR1023_BCM53400_A0r_fields,
  50203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50205         216,
  50206         -1,
  50207     },
  50208 #endif /* chips */
  50209 
  50210 #if defined(BCM_53570_B0)
  50211     { /* SOC_REG_INT_GTBCA_BCM53570_B0r */
  50212         soc_block_list[2],
  50213         soc_portreg,
  50214         1,
  50215         0,
  50216         0x3e00,
  50217         SOC_REG_FLAG_COUNTER,
  50218         0,
  50219         1,
  50220         soc_GR1023_BCM53400_A0r_fields,
  50221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50222         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50223         220,
  50224         -1,
  50225     },
  50226 #endif /* chips */
  50227 
  50228 #if defined(BCM_56142_A0)
  50229     { /* SOC_REG_INT_GTBCA_BCM56142_A0r */
  50230         soc_block_list[210],
  50231         soc_portreg,
  50232         1,
  50233         0,
  50234         0xad,
  50235         SOC_REG_FLAG_COUNTER,
  50236         0,
  50237         1,
  50238         soc_GR1023r_fields,
  50239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50240         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50241         220,
  50242         -1,
  50243     },
  50244 #endif /* chips */
  50245 
  50246 #if defined(BCM_56150_A0)
  50247     { /* SOC_REG_INT_GTBCA_BCM56150_A0r */
  50248         soc_block_list[2],
  50249         soc_portreg,
  50250         1,
  50251         0,
  50252         0x2d00,
  50253         SOC_REG_FLAG_COUNTER,
  50254         0,
  50255         1,
  50256         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  50257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50258         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50259         140,
  50260         -1,
  50261     },
  50262 #endif /* chips */
  50263 
  50264 #if defined(BCM_56160_A0)
  50265     { /* SOC_REG_INT_GTBCA_BCM56160_A0r */
  50266         soc_block_list[2],
  50267         soc_portreg,
  50268         1,
  50269         0,
  50270         0x3e00,
  50271         SOC_REG_FLAG_COUNTER,
  50272         0,
  50273         1,
  50274         soc_GR1023_BCM53400_A0r_fields,
  50275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50276         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50277         161,
  50278         -1,
  50279     },
  50280 #endif /* chips */
  50281 
  50282 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  50283     { /* SOC_REG_INT_GTBCA_BCM56334_A0r */
  50284         soc_block_list[210],
  50285         soc_portreg,
  50286         1,
  50287         0,
  50288         0xad,
  50289         SOC_REG_FLAG_COUNTER,
  50290         0,
  50291         1,
  50292         soc_GR1023r_fields,
  50293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50294         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50295         215,
  50296         -1,
  50297     },
  50298 #endif /* chips */
  50299 
  50300 #if defined(BCM_56370_A0)
  50301     { /* SOC_REG_INT_GTBCA_BCM56370_A0r */
  50302         soc_block_list[9],
  50303         soc_portreg,
  50304         1,
  50305         0,
  50306         0x2e00,
  50307         SOC_REG_FLAG_COUNTER,
  50308         0,
  50309         1,
  50310         soc_GR1023_BCM53400_A0r_fields,
  50311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50312         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50313         106,
  50314         -1,
  50315         3,
  50316     },
  50317 #endif /* chips */
  50318 
  50319 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  50320     { /* SOC_REG_INT_GTBCA_BCM56440_A0r */
  50321         soc_block_list[2],
  50322         soc_portreg,
  50323         1,
  50324         0,
  50325         0xae,
  50326         SOC_REG_FLAG_COUNTER,
  50327         0,
  50328         1,
  50329         soc_GR1023r_fields,
  50330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50332         213,
  50333         -1,
  50334     },
  50335 #endif /* chips */
  50336 
  50337 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  50338     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  50339     defined(BCM_56514_A0)
  50340     { /* SOC_REG_INT_GTBCA_BCM56514_A0r */
  50341         soc_block_list[2],
  50342         soc_portreg,
  50343         1,
  50344         0,
  50345         0x2b,
  50346         SOC_REG_FLAG_COUNTER,
  50347         0,
  50348         1,
  50349         soc_GR1023r_fields,
  50350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50351         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50352         77,
  50353         -1,
  50354     },
  50355 #endif /* chips */
  50356 
  50357 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  50358     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  50359     { /* SOC_REG_INT_GTBCA_BCM56624_A0r */
  50360         soc_block_list[205],
  50361         soc_portreg,
  50362         1,
  50363         0,
  50364         0xab,
  50365         SOC_REG_FLAG_COUNTER,
  50366         0,
  50367         1,
  50368         soc_GR1023r_fields,
  50369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50370         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50371         213,
  50372         -1,
  50373     },
  50374 #endif /* chips */
  50375 
  50376 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  50377     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  50378     { /* SOC_REG_INT_GTBCA_BCM56634_A0r */
  50379         soc_block_list[207],
  50380         soc_portreg,
  50381         1,
  50382         0,
  50383         0xab,
  50384         SOC_REG_FLAG_COUNTER,
  50385         0,
  50386         1,
  50387         soc_GR1023r_fields,
  50388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50389         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50390         213,
  50391         -1,
  50392     },
  50393 #endif /* chips */
  50394 
  50395 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  50396     { /* SOC_REG_INT_GTBCA_BCM56685_A0r */
  50397         soc_block_list[209],
  50398         soc_portreg,
  50399         1,
  50400         0,
  50401         0xab,
  50402         SOC_REG_FLAG_COUNTER,
  50403         0,
  50404         1,
  50405         soc_GR1023r_fields,
  50406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50408         213,
  50409         -1,
  50410     },
  50411 #endif /* chips */
  50412 
  50413 #if defined(BCM_56800_A0)
  50414     { /* SOC_REG_INT_GTBCA_BCM56800_A0r */
  50415         soc_block_list[9],
  50416         soc_portreg,
  50417         1,
  50418         0,
  50419         0x70,
  50420         SOC_REG_FLAG_COUNTER,
  50421         0,
  50422         1,
  50423         soc_GR1023r_fields,
  50424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50426         154,
  50427         -1,
  50428     },
  50429 #endif /* chips */
  50430 
  50431 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  50432     { /* SOC_REG_INT_GTBCA_BCM56820_A0r */
  50433         soc_block_list[206],
  50434         soc_portreg,
  50435         1,
  50436         0,
  50437         0xac,
  50438         SOC_REG_FLAG_COUNTER,
  50439         0,
  50440         1,
  50441         soc_GR1023r_fields,
  50442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50443         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50444         224,
  50445         -1,
  50446     },
  50447 #endif /* chips */
  50448 
  50449 #if defined(BCM_88375_A0)
  50450     { /* SOC_REG_INT_GTBCA_BCM88375_A0r */
  50451         soc_block_list[2],
  50452         soc_portreg,
  50453         1,
  50454         0,
  50455         0x2d00,
  50456         SOC_REG_FLAG_COUNTER,
  50457         0,
  50458         1,
  50459         soc_GTBCA_BCM88375_A0r_fields,
  50460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50462         45,
  50463         -1,
  50464     },
  50465 #endif /* chips */
  50466 
  50467 #if defined(BCM_88375_B0)
  50468     { /* SOC_REG_INT_GTBCA_BCM88375_B0r */
  50469         soc_block_list[2],
  50470         soc_portreg,
  50471         1,
  50472         0,
  50473         0x2d00,
  50474         SOC_REG_FLAG_COUNTER,
  50475         0,
  50476         1,
  50477         soc_GTBCA_BCM88375_B0r_fields,
  50478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50480         45,
  50481         -1,
  50482     },
  50483 #endif /* chips */
  50484 
  50485 #if defined(BCM_88470_A0)
  50486     { /* SOC_REG_INT_GTBCA_BCM88470_A0r */
  50487         soc_block_list[2],
  50488         soc_portreg,
  50489         1,
  50490         0,
  50491         0x2d00,
  50492         SOC_REG_FLAG_COUNTER,
  50493         0,
  50494         1,
  50495         soc_GTBCA_BCM88470_A0r_fields,
  50496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50498         45,
  50499         -1,
  50500     },
  50501 #endif /* chips */
  50502 
  50503 #if defined(BCM_88470_B0)
  50504     { /* SOC_REG_INT_GTBCA_BCM88470_B0r */
  50505         soc_block_list[2],
  50506         soc_portreg,
  50507         1,
  50508         0,
  50509         0x2d00,
  50510         SOC_REG_FLAG_COUNTER,
  50511         0,
  50512         1,
  50513         soc_GTBCA_BCM88470_B0r_fields,
  50514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50516         45,
  50517         -1,
  50518     },
  50519 #endif /* chips */
  50520 
  50521 #if defined(BCM_88675_A0)
  50522     { /* SOC_REG_INT_GTBCA_BCM88675_A0r */
  50523         soc_block_list[2],
  50524         soc_portreg,
  50525         1,
  50526         0,
  50527         0x2d00,
  50528         SOC_REG_FLAG_COUNTER,
  50529         0,
  50530         1,
  50531         soc_GTBCAr_fields,
  50532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50534         45,
  50535         -1,
  50536     },
  50537 #endif /* chips */
  50538 
  50539 #if defined(BCM_88675_B0)
  50540     { /* SOC_REG_INT_GTBCA_BCM88675_B0r */
  50541         soc_block_list[2],
  50542         soc_portreg,
  50543         1,
  50544         0,
  50545         0x2d00,
  50546         SOC_REG_FLAG_COUNTER,
  50547         0,
  50548         1,
  50549         soc_GTBCA_BCM88675_B0r_fields,
  50550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50552         45,
  50553         -1,
  50554     },
  50555 #endif /* chips */
  50556 
  50557 #if defined(BCM_88680_A0)
  50558     { /* SOC_REG_INT_GTBCA_BCM88680_A0r */
  50559         soc_block_list[2],
  50560         soc_portreg,
  50561         1,
  50562         0,
  50563         0x2d00,
  50564         SOC_REG_FLAG_COUNTER,
  50565         0,
  50566         1,
  50567         soc_GTBCA_BCM88680_A0r_fields,
  50568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50570         45,
  50571         -1,
  50572     },
  50573 #endif /* chips */
  50574 
  50575 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  50576     defined(BCM_56504_B0)
  50577     { /* SOC_REG_INT_GTBYTr */
  50578         soc_block_list[2],
  50579         soc_portreg,
  50580         1,
  50581         0,
  50582         0x37,
  50583         SOC_REG_FLAG_COUNTER,
  50584         0,
  50585         1,
  50586         soc_GR1023r_fields,
  50587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50588         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50589         89,
  50590         -1,
  50591     },
  50592 #endif /* chips */
  50593 
  50594 #if defined(BCM_53570_A0)
  50595     { /* SOC_REG_INT_GTBYTPr */
  50596         soc_block_list[2],
  50597         soc_portreg,
  50598         1,
  50599         0,
  50600         0x9f00,
  50601         SOC_REG_FLAG_COUNTER,
  50602         0,
  50603         1,
  50604         soc_GR1023_BCM53400_A0r_fields,
  50605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50606         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50607         313,
  50608         -1,
  50609     },
  50610 #endif /* chips */
  50611 
  50612 #if defined(BCM_53570_B0)
  50613     { /* SOC_REG_INT_GTBYTP_BCM53570_B0r */
  50614         soc_block_list[2],
  50615         soc_portreg,
  50616         1,
  50617         0,
  50618         0x9f00,
  50619         SOC_REG_FLAG_COUNTER,
  50620         0,
  50621         1,
  50622         soc_GR1023_BCM53400_A0r_fields,
  50623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50624         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50625         317,
  50626         -1,
  50627     },
  50628 #endif /* chips */
  50629 
  50630 #if defined(BCM_53400_A0)
  50631     { /* SOC_REG_INT_GTBYT_BCM53400_A0r */
  50632         soc_block_list[9],
  50633         soc_portreg,
  50634         1,
  50635         0,
  50636         0x3900,
  50637         SOC_REG_FLAG_COUNTER,
  50638         0,
  50639         1,
  50640         soc_GR1023_BCM53400_A0r_fields,
  50641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50642         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50643         156,
  50644         -1,
  50645     },
  50646 #endif /* chips */
  50647 
  50648 #if defined(BCM_53540_A0)
  50649     { /* SOC_REG_INT_GTBYT_BCM53540_A0r */
  50650         soc_block_list[2],
  50651         soc_portreg,
  50652         1,
  50653         0,
  50654         0x4a00,
  50655         SOC_REG_FLAG_COUNTER,
  50656         0,
  50657         1,
  50658         soc_GR1023_BCM53400_A0r_fields,
  50659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50661         173,
  50662         -1,
  50663     },
  50664 #endif /* chips */
  50665 
  50666 #if defined(BCM_53570_A0)
  50667     { /* SOC_REG_INT_GTBYT_BCM53570_A0r */
  50668         soc_block_list[2],
  50669         soc_portreg,
  50670         1,
  50671         0,
  50672         0x4a00,
  50673         SOC_REG_FLAG_COUNTER,
  50674         0,
  50675         1,
  50676         soc_GR1023_BCM53400_A0r_fields,
  50677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50678         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50679         228,
  50680         -1,
  50681     },
  50682 #endif /* chips */
  50683 
  50684 #if defined(BCM_53570_B0)
  50685     { /* SOC_REG_INT_GTBYT_BCM53570_B0r */
  50686         soc_block_list[2],
  50687         soc_portreg,
  50688         1,
  50689         0,
  50690         0x4a00,
  50691         SOC_REG_FLAG_COUNTER,
  50692         0,
  50693         1,
  50694         soc_GR1023_BCM53400_A0r_fields,
  50695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50696         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50697         232,
  50698         -1,
  50699     },
  50700 #endif /* chips */
  50701 
  50702 #if defined(BCM_56142_A0)
  50703     { /* SOC_REG_INT_GTBYT_BCM56142_A0r */
  50704         soc_block_list[210],
  50705         soc_portreg,
  50706         1,
  50707         0,
  50708         0xb9,
  50709         SOC_REG_FLAG_COUNTER,
  50710         0,
  50711         1,
  50712         soc_GR1023r_fields,
  50713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50714         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50715         232,
  50716         -1,
  50717     },
  50718 #endif /* chips */
  50719 
  50720 #if defined(BCM_56150_A0)
  50721     { /* SOC_REG_INT_GTBYT_BCM56150_A0r */
  50722         soc_block_list[2],
  50723         soc_portreg,
  50724         1,
  50725         0,
  50726         0x3900,
  50727         SOC_REG_FLAG_COUNTER,
  50728         0,
  50729         1,
  50730         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  50731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50732         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50733         152,
  50734         -1,
  50735     },
  50736 #endif /* chips */
  50737 
  50738 #if defined(BCM_56160_A0)
  50739     { /* SOC_REG_INT_GTBYT_BCM56160_A0r */
  50740         soc_block_list[2],
  50741         soc_portreg,
  50742         1,
  50743         0,
  50744         0x4a00,
  50745         SOC_REG_FLAG_COUNTER,
  50746         0,
  50747         1,
  50748         soc_GR1023_BCM53400_A0r_fields,
  50749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50750         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50751         173,
  50752         -1,
  50753     },
  50754 #endif /* chips */
  50755 
  50756 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  50757     { /* SOC_REG_INT_GTBYT_BCM56334_A0r */
  50758         soc_block_list[210],
  50759         soc_portreg,
  50760         1,
  50761         0,
  50762         0xb9,
  50763         SOC_REG_FLAG_COUNTER,
  50764         0,
  50765         1,
  50766         soc_GR1023r_fields,
  50767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50768         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50769         227,
  50770         -1,
  50771     },
  50772 #endif /* chips */
  50773 
  50774 #if defined(BCM_56370_A0)
  50775     { /* SOC_REG_INT_GTBYT_BCM56370_A0r */
  50776         soc_block_list[9],
  50777         soc_portreg,
  50778         1,
  50779         0,
  50780         0x3a00,
  50781         SOC_REG_FLAG_COUNTER,
  50782         0,
  50783         1,
  50784         soc_GR1023_BCM53400_A0r_fields,
  50785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50786         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50787         118,
  50788         -1,
  50789         3,
  50790     },
  50791 #endif /* chips */
  50792 
  50793 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  50794     { /* SOC_REG_INT_GTBYT_BCM56440_A0r */
  50795         soc_block_list[2],
  50796         soc_portreg,
  50797         1,
  50798         0,
  50799         0xbb,
  50800         SOC_REG_FLAG_COUNTER,
  50801         0,
  50802         1,
  50803         soc_GR1023r_fields,
  50804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50805         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50806         226,
  50807         -1,
  50808     },
  50809 #endif /* chips */
  50810 
  50811 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  50812     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  50813     defined(BCM_56514_A0)
  50814     { /* SOC_REG_INT_GTBYT_BCM56514_A0r */
  50815         soc_block_list[2],
  50816         soc_portreg,
  50817         1,
  50818         0,
  50819         0x39,
  50820         SOC_REG_FLAG_COUNTER,
  50821         0,
  50822         1,
  50823         soc_GR1023r_fields,
  50824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50825         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50826         91,
  50827         -1,
  50828     },
  50829 #endif /* chips */
  50830 
  50831 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  50832     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  50833     { /* SOC_REG_INT_GTBYT_BCM56624_A0r */
  50834         soc_block_list[205],
  50835         soc_portreg,
  50836         1,
  50837         0,
  50838         0xb9,
  50839         SOC_REG_FLAG_COUNTER,
  50840         0,
  50841         1,
  50842         soc_GR1023r_fields,
  50843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50844         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50845         227,
  50846         -1,
  50847     },
  50848 #endif /* chips */
  50849 
  50850 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  50851     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  50852     { /* SOC_REG_INT_GTBYT_BCM56634_A0r */
  50853         soc_block_list[207],
  50854         soc_portreg,
  50855         1,
  50856         0,
  50857         0xb9,
  50858         SOC_REG_FLAG_COUNTER,
  50859         0,
  50860         1,
  50861         soc_GR1023r_fields,
  50862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50863         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50864         227,
  50865         -1,
  50866     },
  50867 #endif /* chips */
  50868 
  50869 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  50870     { /* SOC_REG_INT_GTBYT_BCM56685_A0r */
  50871         soc_block_list[209],
  50872         soc_portreg,
  50873         1,
  50874         0,
  50875         0xb9,
  50876         SOC_REG_FLAG_COUNTER,
  50877         0,
  50878         1,
  50879         soc_GR1023r_fields,
  50880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50882         227,
  50883         -1,
  50884     },
  50885 #endif /* chips */
  50886 
  50887 #if defined(BCM_56800_A0)
  50888     { /* SOC_REG_INT_GTBYT_BCM56800_A0r */
  50889         soc_block_list[9],
  50890         soc_portreg,
  50891         1,
  50892         0,
  50893         0x7e,
  50894         SOC_REG_FLAG_COUNTER,
  50895         0,
  50896         1,
  50897         soc_GR1023r_fields,
  50898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50899         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50900         168,
  50901         -1,
  50902     },
  50903 #endif /* chips */
  50904 
  50905 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  50906     { /* SOC_REG_INT_GTBYT_BCM56820_A0r */
  50907         soc_block_list[206],
  50908         soc_portreg,
  50909         1,
  50910         0,
  50911         0xba,
  50912         SOC_REG_FLAG_COUNTER,
  50913         0,
  50914         1,
  50915         soc_GR1023r_fields,
  50916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50918         238,
  50919         -1,
  50920     },
  50921 #endif /* chips */
  50922 
  50923 #if defined(BCM_88375_A0)
  50924     { /* SOC_REG_INT_GTBYT_BCM88375_A0r */
  50925         soc_block_list[2],
  50926         soc_portreg,
  50927         1,
  50928         0,
  50929         0x3900,
  50930         SOC_REG_FLAG_COUNTER,
  50931         0,
  50932         1,
  50933         soc_GTBYT_BCM88375_A0r_fields,
  50934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50935         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50936         57,
  50937         -1,
  50938     },
  50939 #endif /* chips */
  50940 
  50941 #if defined(BCM_88375_B0)
  50942     { /* SOC_REG_INT_GTBYT_BCM88375_B0r */
  50943         soc_block_list[2],
  50944         soc_portreg,
  50945         1,
  50946         0,
  50947         0x3900,
  50948         SOC_REG_FLAG_COUNTER,
  50949         0,
  50950         1,
  50951         soc_GTBYT_BCM88375_B0r_fields,
  50952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50953         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50954         57,
  50955         -1,
  50956     },
  50957 #endif /* chips */
  50958 
  50959 #if defined(BCM_88470_A0)
  50960     { /* SOC_REG_INT_GTBYT_BCM88470_A0r */
  50961         soc_block_list[2],
  50962         soc_portreg,
  50963         1,
  50964         0,
  50965         0x3900,
  50966         SOC_REG_FLAG_COUNTER,
  50967         0,
  50968         1,
  50969         soc_GTBYT_BCM88470_A0r_fields,
  50970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50971         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50972         57,
  50973         -1,
  50974     },
  50975 #endif /* chips */
  50976 
  50977 #if defined(BCM_88470_B0)
  50978     { /* SOC_REG_INT_GTBYT_BCM88470_B0r */
  50979         soc_block_list[2],
  50980         soc_portreg,
  50981         1,
  50982         0,
  50983         0x3900,
  50984         SOC_REG_FLAG_COUNTER,
  50985         0,
  50986         1,
  50987         soc_GTBYT_BCM88470_B0r_fields,
  50988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50989         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50990         57,
  50991         -1,
  50992     },
  50993 #endif /* chips */
  50994 
  50995 #if defined(BCM_88675_A0)
  50996     { /* SOC_REG_INT_GTBYT_BCM88675_A0r */
  50997         soc_block_list[2],
  50998         soc_portreg,
  50999         1,
  51000         0,
  51001         0x3900,
  51002         SOC_REG_FLAG_COUNTER,
  51003         0,
  51004         1,
  51005         soc_GTBYTr_fields,
  51006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51007         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51008         57,
  51009         -1,
  51010     },
  51011 #endif /* chips */
  51012 
  51013 #if defined(BCM_88675_B0)
  51014     { /* SOC_REG_INT_GTBYT_BCM88675_B0r */
  51015         soc_block_list[2],
  51016         soc_portreg,
  51017         1,
  51018         0,
  51019         0x3900,
  51020         SOC_REG_FLAG_COUNTER,
  51021         0,
  51022         1,
  51023         soc_GTBYT_BCM88675_B0r_fields,
  51024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51025         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51026         57,
  51027         -1,
  51028     },
  51029 #endif /* chips */
  51030 
  51031 #if defined(BCM_88680_A0)
  51032     { /* SOC_REG_INT_GTBYT_BCM88680_A0r */
  51033         soc_block_list[2],
  51034         soc_portreg,
  51035         1,
  51036         0,
  51037         0x3900,
  51038         SOC_REG_FLAG_COUNTER,
  51039         0,
  51040         1,
  51041         soc_GTBYT_BCM88680_A0r_fields,
  51042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51043         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51044         57,
  51045         -1,
  51046     },
  51047 #endif /* chips */
  51048 
  51049 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  51050     defined(BCM_56504_B0)
  51051     { /* SOC_REG_INT_GTDFRr */
  51052         soc_block_list[2],
  51053         soc_portreg,
  51054         1,
  51055         0,
  51056         0x2f,
  51057         SOC_REG_FLAG_COUNTER |
  51058                           SOC_REG_FLAG_ED_CNTR,
  51059         0,
  51060         1,
  51061         soc_GR1023r_fields,
  51062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51064         81,
  51065         -1,
  51066     },
  51067 #endif /* chips */
  51068 
  51069 #if defined(BCM_53570_A0)
  51070     { /* SOC_REG_INT_GTDFRPr */
  51071         soc_block_list[2],
  51072         soc_portreg,
  51073         1,
  51074         0,
  51075         0x8a00,
  51076         SOC_REG_FLAG_COUNTER |
  51077                           SOC_REG_FLAG_ED_CNTR,
  51078         0,
  51079         1,
  51080         soc_GR1023_BCM53400_A0r_fields,
  51081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51082         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51083         292,
  51084         -1,
  51085     },
  51086 #endif /* chips */
  51087 
  51088 #if defined(BCM_53570_B0)
  51089     { /* SOC_REG_INT_GTDFRP_BCM53570_B0r */
  51090         soc_block_list[2],
  51091         soc_portreg,
  51092         1,
  51093         0,
  51094         0x8a00,
  51095         SOC_REG_FLAG_COUNTER |
  51096                           SOC_REG_FLAG_ED_CNTR,
  51097         0,
  51098         1,
  51099         soc_GR1023_BCM53400_A0r_fields,
  51100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51101         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51102         296,
  51103         -1,
  51104     },
  51105 #endif /* chips */
  51106 
  51107 #if defined(BCM_53400_A0)
  51108     { /* SOC_REG_INT_GTDFR_BCM53400_A0r */
  51109         soc_block_list[9],
  51110         soc_portreg,
  51111         1,
  51112         0,
  51113         0x2400,
  51114         SOC_REG_FLAG_COUNTER |
  51115                           SOC_REG_FLAG_ED_CNTR,
  51116         0,
  51117         1,
  51118         soc_GR1023_BCM53400_A0r_fields,
  51119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51120         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51121         135,
  51122         -1,
  51123     },
  51124 #endif /* chips */
  51125 
  51126 #if defined(BCM_53540_A0)
  51127     { /* SOC_REG_INT_GTDFR_BCM53540_A0r */
  51128         soc_block_list[2],
  51129         soc_portreg,
  51130         1,
  51131         0,
  51132         0x3500,
  51133         SOC_REG_FLAG_COUNTER |
  51134                           SOC_REG_FLAG_ED_CNTR,
  51135         0,
  51136         1,
  51137         soc_GR1023_BCM53400_A0r_fields,
  51138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51139         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51140         152,
  51141         -1,
  51142     },
  51143 #endif /* chips */
  51144 
  51145 #if defined(BCM_53570_A0)
  51146     { /* SOC_REG_INT_GTDFR_BCM53570_A0r */
  51147         soc_block_list[2],
  51148         soc_portreg,
  51149         1,
  51150         0,
  51151         0x3500,
  51152         SOC_REG_FLAG_COUNTER |
  51153                           SOC_REG_FLAG_ED_CNTR,
  51154         0,
  51155         1,
  51156         soc_GR1023_BCM53400_A0r_fields,
  51157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51159         207,
  51160         -1,
  51161     },
  51162 #endif /* chips */
  51163 
  51164 #if defined(BCM_53570_B0)
  51165     { /* SOC_REG_INT_GTDFR_BCM53570_B0r */
  51166         soc_block_list[2],
  51167         soc_portreg,
  51168         1,
  51169         0,
  51170         0x3500,
  51171         SOC_REG_FLAG_COUNTER |
  51172                           SOC_REG_FLAG_ED_CNTR,
  51173         0,
  51174         1,
  51175         soc_GR1023_BCM53400_A0r_fields,
  51176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51178         211,
  51179         -1,
  51180     },
  51181 #endif /* chips */
  51182 
  51183 #if defined(BCM_56142_A0)
  51184     { /* SOC_REG_INT_GTDFR_BCM56142_A0r */
  51185         soc_block_list[210],
  51186         soc_portreg,
  51187         1,
  51188         0,
  51189         0xa4,
  51190         SOC_REG_FLAG_COUNTER |
  51191                           SOC_REG_FLAG_ED_CNTR,
  51192         0,
  51193         1,
  51194         soc_GR1023r_fields,
  51195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51196         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51197         211,
  51198         -1,
  51199     },
  51200 #endif /* chips */
  51201 
  51202 #if defined(BCM_56150_A0)
  51203     { /* SOC_REG_INT_GTDFR_BCM56150_A0r */
  51204         soc_block_list[2],
  51205         soc_portreg,
  51206         1,
  51207         0,
  51208         0x2400,
  51209         SOC_REG_FLAG_COUNTER |
  51210                           SOC_REG_FLAG_ED_CNTR,
  51211         0,
  51212         1,
  51213         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  51214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51215         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51216         131,
  51217         -1,
  51218     },
  51219 #endif /* chips */
  51220 
  51221 #if defined(BCM_56160_A0)
  51222     { /* SOC_REG_INT_GTDFR_BCM56160_A0r */
  51223         soc_block_list[2],
  51224         soc_portreg,
  51225         1,
  51226         0,
  51227         0x3500,
  51228         SOC_REG_FLAG_COUNTER |
  51229                           SOC_REG_FLAG_ED_CNTR,
  51230         0,
  51231         1,
  51232         soc_GR1023_BCM53400_A0r_fields,
  51233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51234         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51235         152,
  51236         -1,
  51237     },
  51238 #endif /* chips */
  51239 
  51240 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  51241     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  51242     { /* SOC_REG_INT_GTDFR_BCM56224_A0r */
  51243         soc_block_list[2],
  51244         soc_portreg,
  51245         1,
  51246         0,
  51247         0x24,
  51248         SOC_REG_FLAG_COUNTER |
  51249                           SOC_REG_FLAG_ED_CNTR,
  51250         0,
  51251         1,
  51252         soc_GR1023r_fields,
  51253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51254         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51255         70,
  51256         -1,
  51257     },
  51258 #endif /* chips */
  51259 
  51260 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  51261     { /* SOC_REG_INT_GTDFR_BCM56334_A0r */
  51262         soc_block_list[210],
  51263         soc_portreg,
  51264         1,
  51265         0,
  51266         0xa4,
  51267         SOC_REG_FLAG_COUNTER |
  51268                           SOC_REG_FLAG_ED_CNTR,
  51269         0,
  51270         1,
  51271         soc_GR1023r_fields,
  51272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51273         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51274         206,
  51275         -1,
  51276     },
  51277 #endif /* chips */
  51278 
  51279 #if defined(BCM_56370_A0)
  51280     { /* SOC_REG_INT_GTDFR_BCM56370_A0r */
  51281         soc_block_list[9],
  51282         soc_portreg,
  51283         1,
  51284         0,
  51285         0x2500,
  51286         SOC_REG_FLAG_COUNTER |
  51287                           SOC_REG_FLAG_ED_CNTR,
  51288         0,
  51289         1,
  51290         soc_GR1023_BCM53400_A0r_fields,
  51291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51293         97,
  51294         -1,
  51295         3,
  51296     },
  51297 #endif /* chips */
  51298 
  51299 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  51300     { /* SOC_REG_INT_GTDFR_BCM56440_A0r */
  51301         soc_block_list[2],
  51302         soc_portreg,
  51303         1,
  51304         0,
  51305         0xa5,
  51306         SOC_REG_FLAG_COUNTER |
  51307                           SOC_REG_FLAG_ED_CNTR,
  51308         0,
  51309         1,
  51310         soc_GR1023r_fields,
  51311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51312         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51313         204,
  51314         -1,
  51315     },
  51316 #endif /* chips */
  51317 
  51318 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  51319     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  51320     { /* SOC_REG_INT_GTDFR_BCM56624_A0r */
  51321         soc_block_list[205],
  51322         soc_portreg,
  51323         1,
  51324         0,
  51325         0xb1,
  51326         SOC_REG_FLAG_COUNTER |
  51327                           SOC_REG_FLAG_ED_CNTR,
  51328         0,
  51329         1,
  51330         soc_GR1023r_fields,
  51331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51332         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51333         219,
  51334         -1,
  51335     },
  51336 #endif /* chips */
  51337 
  51338 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  51339     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  51340     { /* SOC_REG_INT_GTDFR_BCM56634_A0r */
  51341         soc_block_list[207],
  51342         soc_portreg,
  51343         1,
  51344         0,
  51345         0xb1,
  51346         SOC_REG_FLAG_COUNTER |
  51347                           SOC_REG_FLAG_ED_CNTR,
  51348         0,
  51349         1,
  51350         soc_GR1023r_fields,
  51351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51352         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51353         219,
  51354         -1,
  51355     },
  51356 #endif /* chips */
  51357 
  51358 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  51359     { /* SOC_REG_INT_GTDFR_BCM56685_A0r */
  51360         soc_block_list[209],
  51361         soc_portreg,
  51362         1,
  51363         0,
  51364         0xb1,
  51365         SOC_REG_FLAG_COUNTER |
  51366                           SOC_REG_FLAG_ED_CNTR,
  51367         0,
  51368         1,
  51369         soc_GR1023r_fields,
  51370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51372         219,
  51373         -1,
  51374     },
  51375 #endif /* chips */
  51376 
  51377 #if defined(BCM_56800_A0)
  51378     { /* SOC_REG_INT_GTDFR_BCM56800_A0r */
  51379         soc_block_list[9],
  51380         soc_portreg,
  51381         1,
  51382         0,
  51383         0x76,
  51384         SOC_REG_FLAG_COUNTER |
  51385                           SOC_REG_FLAG_ED_CNTR,
  51386         0,
  51387         1,
  51388         soc_GR1023r_fields,
  51389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51390         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51391         160,
  51392         -1,
  51393     },
  51394 #endif /* chips */
  51395 
  51396 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  51397     { /* SOC_REG_INT_GTDFR_BCM56820_A0r */
  51398         soc_block_list[206],
  51399         soc_portreg,
  51400         1,
  51401         0,
  51402         0xb2,
  51403         SOC_REG_FLAG_COUNTER |
  51404                           SOC_REG_FLAG_ED_CNTR,
  51405         0,
  51406         1,
  51407         soc_GR1023r_fields,
  51408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51409         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51410         230,
  51411         -1,
  51412     },
  51413 #endif /* chips */
  51414 
  51415 #if defined(BCM_88375_A0)
  51416     { /* SOC_REG_INT_GTDFR_BCM88375_A0r */
  51417         soc_block_list[2],
  51418         soc_portreg,
  51419         1,
  51420         0,
  51421         0x2400,
  51422         SOC_REG_FLAG_COUNTER,
  51423         0,
  51424         1,
  51425         soc_GTDFR_BCM88375_A0r_fields,
  51426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51428         36,
  51429         -1,
  51430     },
  51431 #endif /* chips */
  51432 
  51433 #if defined(BCM_88375_B0)
  51434     { /* SOC_REG_INT_GTDFR_BCM88375_B0r */
  51435         soc_block_list[2],
  51436         soc_portreg,
  51437         1,
  51438         0,
  51439         0x2400,
  51440         SOC_REG_FLAG_COUNTER,
  51441         0,
  51442         1,
  51443         soc_GTDFR_BCM88375_B0r_fields,
  51444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51446         36,
  51447         -1,
  51448     },
  51449 #endif /* chips */
  51450 
  51451 #if defined(BCM_88470_A0)
  51452     { /* SOC_REG_INT_GTDFR_BCM88470_A0r */
  51453         soc_block_list[2],
  51454         soc_portreg,
  51455         1,
  51456         0,
  51457         0x2400,
  51458         SOC_REG_FLAG_COUNTER,
  51459         0,
  51460         1,
  51461         soc_GTDFR_BCM88470_A0r_fields,
  51462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51463         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51464         36,
  51465         -1,
  51466     },
  51467 #endif /* chips */
  51468 
  51469 #if defined(BCM_88470_B0)
  51470     { /* SOC_REG_INT_GTDFR_BCM88470_B0r */
  51471         soc_block_list[2],
  51472         soc_portreg,
  51473         1,
  51474         0,
  51475         0x2400,
  51476         SOC_REG_FLAG_COUNTER,
  51477         0,
  51478         1,
  51479         soc_GTDFR_BCM88470_B0r_fields,
  51480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51481         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51482         36,
  51483         -1,
  51484     },
  51485 #endif /* chips */
  51486 
  51487 #if defined(BCM_88675_A0)
  51488     { /* SOC_REG_INT_GTDFR_BCM88675_A0r */
  51489         soc_block_list[2],
  51490         soc_portreg,
  51491         1,
  51492         0,
  51493         0x2400,
  51494         SOC_REG_FLAG_COUNTER,
  51495         0,
  51496         1,
  51497         soc_GTDFRr_fields,
  51498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51499         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51500         36,
  51501         -1,
  51502     },
  51503 #endif /* chips */
  51504 
  51505 #if defined(BCM_88675_B0)
  51506     { /* SOC_REG_INT_GTDFR_BCM88675_B0r */
  51507         soc_block_list[2],
  51508         soc_portreg,
  51509         1,
  51510         0,
  51511         0x2400,
  51512         SOC_REG_FLAG_COUNTER,
  51513         0,
  51514         1,
  51515         soc_GTDFR_BCM88675_B0r_fields,
  51516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51517         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51518         36,
  51519         -1,
  51520     },
  51521 #endif /* chips */
  51522 
  51523 #if defined(BCM_88680_A0)
  51524     { /* SOC_REG_INT_GTDFR_BCM88680_A0r */
  51525         soc_block_list[2],
  51526         soc_portreg,
  51527         1,
  51528         0,
  51529         0x2400,
  51530         SOC_REG_FLAG_COUNTER,
  51531         0,
  51532         1,
  51533         soc_GTDFR_BCM88680_A0r_fields,
  51534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51535         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51536         36,
  51537         -1,
  51538     },
  51539 #endif /* chips */
  51540 
  51541 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  51542     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  51543     { /* SOC_REG_INT_GTEDFr */
  51544         soc_block_list[2],
  51545         soc_portreg,
  51546         1,
  51547         0,
  51548         0x30,
  51549         SOC_REG_FLAG_COUNTER |
  51550                           SOC_REG_FLAG_ED_CNTR,
  51551         0,
  51552         1,
  51553         soc_GR1023r_fields,
  51554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51556         82,
  51557         -1,
  51558     },
  51559 #endif /* chips */
  51560 
  51561 #if defined(BCM_53570_A0)
  51562     { /* SOC_REG_INT_GTEDFPr */
  51563         soc_block_list[2],
  51564         soc_portreg,
  51565         1,
  51566         0,
  51567         0x8b00,
  51568         SOC_REG_FLAG_COUNTER |
  51569                           SOC_REG_FLAG_ED_CNTR,
  51570         0,
  51571         1,
  51572         soc_GR1023_BCM53400_A0r_fields,
  51573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51574         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51575         293,
  51576         -1,
  51577     },
  51578 #endif /* chips */
  51579 
  51580 #if defined(BCM_53570_B0)
  51581     { /* SOC_REG_INT_GTEDFP_BCM53570_B0r */
  51582         soc_block_list[2],
  51583         soc_portreg,
  51584         1,
  51585         0,
  51586         0x8b00,
  51587         SOC_REG_FLAG_COUNTER |
  51588                           SOC_REG_FLAG_ED_CNTR,
  51589         0,
  51590         1,
  51591         soc_GR1023_BCM53400_A0r_fields,
  51592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51594         297,
  51595         -1,
  51596     },
  51597 #endif /* chips */
  51598 
  51599 #if defined(BCM_53400_A0)
  51600     { /* SOC_REG_INT_GTEDF_BCM53400_A0r */
  51601         soc_block_list[9],
  51602         soc_portreg,
  51603         1,
  51604         0,
  51605         0x2500,
  51606         SOC_REG_FLAG_COUNTER |
  51607                           SOC_REG_FLAG_ED_CNTR,
  51608         0,
  51609         1,
  51610         soc_GR1023_BCM53400_A0r_fields,
  51611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51613         136,
  51614         -1,
  51615     },
  51616 #endif /* chips */
  51617 
  51618 #if defined(BCM_53540_A0)
  51619     { /* SOC_REG_INT_GTEDF_BCM53540_A0r */
  51620         soc_block_list[2],
  51621         soc_portreg,
  51622         1,
  51623         0,
  51624         0x3600,
  51625         SOC_REG_FLAG_COUNTER |
  51626                           SOC_REG_FLAG_ED_CNTR,
  51627         0,
  51628         1,
  51629         soc_GR1023_BCM53400_A0r_fields,
  51630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51632         153,
  51633         -1,
  51634     },
  51635 #endif /* chips */
  51636 
  51637 #if defined(BCM_53570_A0)
  51638     { /* SOC_REG_INT_GTEDF_BCM53570_A0r */
  51639         soc_block_list[2],
  51640         soc_portreg,
  51641         1,
  51642         0,
  51643         0x3600,
  51644         SOC_REG_FLAG_COUNTER |
  51645                           SOC_REG_FLAG_ED_CNTR,
  51646         0,
  51647         1,
  51648         soc_GR1023_BCM53400_A0r_fields,
  51649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51650         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51651         208,
  51652         -1,
  51653     },
  51654 #endif /* chips */
  51655 
  51656 #if defined(BCM_53570_B0)
  51657     { /* SOC_REG_INT_GTEDF_BCM53570_B0r */
  51658         soc_block_list[2],
  51659         soc_portreg,
  51660         1,
  51661         0,
  51662         0x3600,
  51663         SOC_REG_FLAG_COUNTER |
  51664                           SOC_REG_FLAG_ED_CNTR,
  51665         0,
  51666         1,
  51667         soc_GR1023_BCM53400_A0r_fields,
  51668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51670         212,
  51671         -1,
  51672     },
  51673 #endif /* chips */
  51674 
  51675 #if defined(BCM_56142_A0)
  51676     { /* SOC_REG_INT_GTEDF_BCM56142_A0r */
  51677         soc_block_list[210],
  51678         soc_portreg,
  51679         1,
  51680         0,
  51681         0xa5,
  51682         SOC_REG_FLAG_COUNTER |
  51683                           SOC_REG_FLAG_ED_CNTR,
  51684         0,
  51685         1,
  51686         soc_GR1023r_fields,
  51687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51688         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51689         212,
  51690         -1,
  51691     },
  51692 #endif /* chips */
  51693 
  51694 #if defined(BCM_56150_A0)
  51695     { /* SOC_REG_INT_GTEDF_BCM56150_A0r */
  51696         soc_block_list[2],
  51697         soc_portreg,
  51698         1,
  51699         0,
  51700         0x2500,
  51701         SOC_REG_FLAG_COUNTER |
  51702                           SOC_REG_FLAG_ED_CNTR,
  51703         0,
  51704         1,
  51705         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  51706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51707         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51708         132,
  51709         -1,
  51710     },
  51711 #endif /* chips */
  51712 
  51713 #if defined(BCM_56160_A0)
  51714     { /* SOC_REG_INT_GTEDF_BCM56160_A0r */
  51715         soc_block_list[2],
  51716         soc_portreg,
  51717         1,
  51718         0,
  51719         0x3600,
  51720         SOC_REG_FLAG_COUNTER |
  51721                           SOC_REG_FLAG_ED_CNTR,
  51722         0,
  51723         1,
  51724         soc_GR1023_BCM53400_A0r_fields,
  51725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51726         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51727         153,
  51728         -1,
  51729     },
  51730 #endif /* chips */
  51731 
  51732 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  51733     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  51734     { /* SOC_REG_INT_GTEDF_BCM56224_A0r */
  51735         soc_block_list[2],
  51736         soc_portreg,
  51737         1,
  51738         0,
  51739         0x25,
  51740         SOC_REG_FLAG_COUNTER |
  51741                           SOC_REG_FLAG_ED_CNTR,
  51742         0,
  51743         1,
  51744         soc_GR1023r_fields,
  51745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51746         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51747         71,
  51748         -1,
  51749     },
  51750 #endif /* chips */
  51751 
  51752 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  51753     { /* SOC_REG_INT_GTEDF_BCM56334_A0r */
  51754         soc_block_list[210],
  51755         soc_portreg,
  51756         1,
  51757         0,
  51758         0xa5,
  51759         SOC_REG_FLAG_COUNTER |
  51760                           SOC_REG_FLAG_ED_CNTR,
  51761         0,
  51762         1,
  51763         soc_GR1023r_fields,
  51764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51765         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51766         207,
  51767         -1,
  51768     },
  51769 #endif /* chips */
  51770 
  51771 #if defined(BCM_56370_A0)
  51772     { /* SOC_REG_INT_GTEDF_BCM56370_A0r */
  51773         soc_block_list[9],
  51774         soc_portreg,
  51775         1,
  51776         0,
  51777         0x2600,
  51778         SOC_REG_FLAG_COUNTER |
  51779                           SOC_REG_FLAG_ED_CNTR,
  51780         0,
  51781         1,
  51782         soc_GR1023_BCM53400_A0r_fields,
  51783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51784         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51785         98,
  51786         -1,
  51787         3,
  51788     },
  51789 #endif /* chips */
  51790 
  51791 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  51792     { /* SOC_REG_INT_GTEDF_BCM56440_A0r */
  51793         soc_block_list[2],
  51794         soc_portreg,
  51795         1,
  51796         0,
  51797         0xa6,
  51798         SOC_REG_FLAG_COUNTER |
  51799                           SOC_REG_FLAG_ED_CNTR,
  51800         0,
  51801         1,
  51802         soc_GR1023r_fields,
  51803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51804         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51805         205,
  51806         -1,
  51807     },
  51808 #endif /* chips */
  51809 
  51810 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  51811     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  51812     { /* SOC_REG_INT_GTEDF_BCM56624_A0r */
  51813         soc_block_list[205],
  51814         soc_portreg,
  51815         1,
  51816         0,
  51817         0xb2,
  51818         SOC_REG_FLAG_COUNTER |
  51819                           SOC_REG_FLAG_ED_CNTR,
  51820         0,
  51821         1,
  51822         soc_GR1023r_fields,
  51823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51824         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51825         220,
  51826         -1,
  51827     },
  51828 #endif /* chips */
  51829 
  51830 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  51831     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  51832     { /* SOC_REG_INT_GTEDF_BCM56634_A0r */
  51833         soc_block_list[207],
  51834         soc_portreg,
  51835         1,
  51836         0,
  51837         0xb2,
  51838         SOC_REG_FLAG_COUNTER |
  51839                           SOC_REG_FLAG_ED_CNTR,
  51840         0,
  51841         1,
  51842         soc_GR1023r_fields,
  51843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51844         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51845         220,
  51846         -1,
  51847     },
  51848 #endif /* chips */
  51849 
  51850 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  51851     { /* SOC_REG_INT_GTEDF_BCM56685_A0r */
  51852         soc_block_list[209],
  51853         soc_portreg,
  51854         1,
  51855         0,
  51856         0xb2,
  51857         SOC_REG_FLAG_COUNTER |
  51858                           SOC_REG_FLAG_ED_CNTR,
  51859         0,
  51860         1,
  51861         soc_GR1023r_fields,
  51862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51863         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51864         220,
  51865         -1,
  51866     },
  51867 #endif /* chips */
  51868 
  51869 #if defined(BCM_56800_A0)
  51870     { /* SOC_REG_INT_GTEDF_BCM56800_A0r */
  51871         soc_block_list[9],
  51872         soc_portreg,
  51873         1,
  51874         0,
  51875         0x77,
  51876         SOC_REG_FLAG_COUNTER |
  51877                           SOC_REG_FLAG_ED_CNTR,
  51878         0,
  51879         1,
  51880         soc_GR1023r_fields,
  51881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51882         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51883         161,
  51884         -1,
  51885     },
  51886 #endif /* chips */
  51887 
  51888 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  51889     { /* SOC_REG_INT_GTEDF_BCM56820_A0r */
  51890         soc_block_list[206],
  51891         soc_portreg,
  51892         1,
  51893         0,
  51894         0xb3,
  51895         SOC_REG_FLAG_COUNTER |
  51896                           SOC_REG_FLAG_ED_CNTR,
  51897         0,
  51898         1,
  51899         soc_GR1023r_fields,
  51900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51901         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51902         231,
  51903         -1,
  51904     },
  51905 #endif /* chips */
  51906 
  51907 #if defined(BCM_88375_A0)
  51908     { /* SOC_REG_INT_GTEDF_BCM88375_A0r */
  51909         soc_block_list[2],
  51910         soc_portreg,
  51911         1,
  51912         0,
  51913         0x2500,
  51914         SOC_REG_FLAG_COUNTER,
  51915         0,
  51916         1,
  51917         soc_GTEDF_BCM88375_A0r_fields,
  51918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51919         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51920         37,
  51921         -1,
  51922     },
  51923 #endif /* chips */
  51924 
  51925 #if defined(BCM_88375_B0)
  51926     { /* SOC_REG_INT_GTEDF_BCM88375_B0r */
  51927         soc_block_list[2],
  51928         soc_portreg,
  51929         1,
  51930         0,
  51931         0x2500,
  51932         SOC_REG_FLAG_COUNTER,
  51933         0,
  51934         1,
  51935         soc_GTEDF_BCM88375_B0r_fields,
  51936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51937         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51938         37,
  51939         -1,
  51940     },
  51941 #endif /* chips */
  51942 
  51943 #if defined(BCM_88470_A0)
  51944     { /* SOC_REG_INT_GTEDF_BCM88470_A0r */
  51945         soc_block_list[2],
  51946         soc_portreg,
  51947         1,
  51948         0,
  51949         0x2500,
  51950         SOC_REG_FLAG_COUNTER,
  51951         0,
  51952         1,
  51953         soc_GTEDF_BCM88470_A0r_fields,
  51954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51956         37,
  51957         -1,
  51958     },
  51959 #endif /* chips */
  51960 
  51961 #if defined(BCM_88470_B0)
  51962     { /* SOC_REG_INT_GTEDF_BCM88470_B0r */
  51963         soc_block_list[2],
  51964         soc_portreg,
  51965         1,
  51966         0,
  51967         0x2500,
  51968         SOC_REG_FLAG_COUNTER,
  51969         0,
  51970         1,
  51971         soc_GTEDF_BCM88470_B0r_fields,
  51972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51973         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51974         37,
  51975         -1,
  51976     },
  51977 #endif /* chips */
  51978 
  51979 #if defined(BCM_88675_A0)
  51980     { /* SOC_REG_INT_GTEDF_BCM88675_A0r */
  51981         soc_block_list[2],
  51982         soc_portreg,
  51983         1,
  51984         0,
  51985         0x2500,
  51986         SOC_REG_FLAG_COUNTER,
  51987         0,
  51988         1,
  51989         soc_GTEDFr_fields,
  51990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51991         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51992         37,
  51993         -1,
  51994     },
  51995 #endif /* chips */
  51996 
  51997 #if defined(BCM_88675_B0)
  51998     { /* SOC_REG_INT_GTEDF_BCM88675_B0r */
  51999         soc_block_list[2],
  52000         soc_portreg,
  52001         1,
  52002         0,
  52003         0x2500,
  52004         SOC_REG_FLAG_COUNTER,
  52005         0,
  52006         1,
  52007         soc_GTEDF_BCM88675_B0r_fields,
  52008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52009         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52010         37,
  52011         -1,
  52012     },
  52013 #endif /* chips */
  52014 
  52015 #if defined(BCM_88680_A0)
  52016     { /* SOC_REG_INT_GTEDF_BCM88680_A0r */
  52017         soc_block_list[2],
  52018         soc_portreg,
  52019         1,
  52020         0,
  52021         0x2500,
  52022         SOC_REG_FLAG_COUNTER,
  52023         0,
  52024         1,
  52025         soc_GTEDF_BCM88680_A0r_fields,
  52026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52028         37,
  52029         -1,
  52030     },
  52031 #endif /* chips */
  52032 
  52033 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  52034     defined(BCM_56504_B0)
  52035     { /* SOC_REG_INT_GTFCSr */
  52036         soc_block_list[2],
  52037         soc_portreg,
  52038         1,
  52039         0,
  52040         0x2c,
  52041         SOC_REG_FLAG_COUNTER |
  52042                           SOC_REG_FLAG_ED_CNTR,
  52043         0,
  52044         1,
  52045         soc_GR1023r_fields,
  52046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52048         78,
  52049         -1,
  52050     },
  52051 #endif /* chips */
  52052 
  52053 #if defined(BCM_53570_A0)
  52054     { /* SOC_REG_INT_GTFCSPr */
  52055         soc_block_list[2],
  52056         soc_portreg,
  52057         1,
  52058         0,
  52059         0x8800,
  52060         SOC_REG_FLAG_COUNTER |
  52061                           SOC_REG_FLAG_ED_CNTR,
  52062         0,
  52063         1,
  52064         soc_GR1023_BCM53400_A0r_fields,
  52065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52066         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52067         290,
  52068         -1,
  52069     },
  52070 #endif /* chips */
  52071 
  52072 #if defined(BCM_53570_B0)
  52073     { /* SOC_REG_INT_GTFCSP_BCM53570_B0r */
  52074         soc_block_list[2],
  52075         soc_portreg,
  52076         1,
  52077         0,
  52078         0x8800,
  52079         SOC_REG_FLAG_COUNTER |
  52080                           SOC_REG_FLAG_ED_CNTR,
  52081         0,
  52082         1,
  52083         soc_GR1023_BCM53400_A0r_fields,
  52084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52086         294,
  52087         -1,
  52088     },
  52089 #endif /* chips */
  52090 
  52091 #if defined(BCM_53400_A0)
  52092     { /* SOC_REG_INT_GTFCS_BCM53400_A0r */
  52093         soc_block_list[9],
  52094         soc_portreg,
  52095         1,
  52096         0,
  52097         0x2100,
  52098         SOC_REG_FLAG_COUNTER |
  52099                           SOC_REG_FLAG_ED_CNTR,
  52100         0,
  52101         1,
  52102         soc_GR1023_BCM53400_A0r_fields,
  52103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52105         132,
  52106         -1,
  52107     },
  52108 #endif /* chips */
  52109 
  52110 #if defined(BCM_53540_A0)
  52111     { /* SOC_REG_INT_GTFCS_BCM53540_A0r */
  52112         soc_block_list[2],
  52113         soc_portreg,
  52114         1,
  52115         0,
  52116         0x3200,
  52117         SOC_REG_FLAG_COUNTER |
  52118                           SOC_REG_FLAG_ED_CNTR,
  52119         0,
  52120         1,
  52121         soc_GR1023_BCM53400_A0r_fields,
  52122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52124         149,
  52125         -1,
  52126     },
  52127 #endif /* chips */
  52128 
  52129 #if defined(BCM_53570_A0)
  52130     { /* SOC_REG_INT_GTFCS_BCM53570_A0r */
  52131         soc_block_list[2],
  52132         soc_portreg,
  52133         1,
  52134         0,
  52135         0x3200,
  52136         SOC_REG_FLAG_COUNTER |
  52137                           SOC_REG_FLAG_ED_CNTR,
  52138         0,
  52139         1,
  52140         soc_GR1023_BCM53400_A0r_fields,
  52141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52142         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52143         204,
  52144         -1,
  52145     },
  52146 #endif /* chips */
  52147 
  52148 #if defined(BCM_53570_B0)
  52149     { /* SOC_REG_INT_GTFCS_BCM53570_B0r */
  52150         soc_block_list[2],
  52151         soc_portreg,
  52152         1,
  52153         0,
  52154         0x3200,
  52155         SOC_REG_FLAG_COUNTER |
  52156                           SOC_REG_FLAG_ED_CNTR,
  52157         0,
  52158         1,
  52159         soc_GR1023_BCM53400_A0r_fields,
  52160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52162         208,
  52163         -1,
  52164     },
  52165 #endif /* chips */
  52166 
  52167 #if defined(BCM_56142_A0)
  52168     { /* SOC_REG_INT_GTFCS_BCM56142_A0r */
  52169         soc_block_list[210],
  52170         soc_portreg,
  52171         1,
  52172         0,
  52173         0xa1,
  52174         SOC_REG_FLAG_COUNTER |
  52175                           SOC_REG_FLAG_ED_CNTR,
  52176         0,
  52177         1,
  52178         soc_GR1023r_fields,
  52179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52180         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52181         208,
  52182         -1,
  52183     },
  52184 #endif /* chips */
  52185 
  52186 #if defined(BCM_56150_A0)
  52187     { /* SOC_REG_INT_GTFCS_BCM56150_A0r */
  52188         soc_block_list[2],
  52189         soc_portreg,
  52190         1,
  52191         0,
  52192         0x2100,
  52193         SOC_REG_FLAG_COUNTER |
  52194                           SOC_REG_FLAG_ED_CNTR,
  52195         0,
  52196         1,
  52197         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  52198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52200         128,
  52201         -1,
  52202     },
  52203 #endif /* chips */
  52204 
  52205 #if defined(BCM_56160_A0)
  52206     { /* SOC_REG_INT_GTFCS_BCM56160_A0r */
  52207         soc_block_list[2],
  52208         soc_portreg,
  52209         1,
  52210         0,
  52211         0x3200,
  52212         SOC_REG_FLAG_COUNTER |
  52213                           SOC_REG_FLAG_ED_CNTR,
  52214         0,
  52215         1,
  52216         soc_GR1023_BCM53400_A0r_fields,
  52217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52218         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52219         149,
  52220         -1,
  52221     },
  52222 #endif /* chips */
  52223 
  52224 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  52225     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  52226     { /* SOC_REG_INT_GTFCS_BCM56224_A0r */
  52227         soc_block_list[2],
  52228         soc_portreg,
  52229         1,
  52230         0,
  52231         0x21,
  52232         SOC_REG_FLAG_COUNTER |
  52233                           SOC_REG_FLAG_ED_CNTR,
  52234         0,
  52235         1,
  52236         soc_GR1023r_fields,
  52237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52238         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52239         67,
  52240         -1,
  52241     },
  52242 #endif /* chips */
  52243 
  52244 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  52245     { /* SOC_REG_INT_GTFCS_BCM56334_A0r */
  52246         soc_block_list[210],
  52247         soc_portreg,
  52248         1,
  52249         0,
  52250         0xa1,
  52251         SOC_REG_FLAG_COUNTER |
  52252                           SOC_REG_FLAG_ED_CNTR,
  52253         0,
  52254         1,
  52255         soc_GR1023r_fields,
  52256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52257         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52258         203,
  52259         -1,
  52260     },
  52261 #endif /* chips */
  52262 
  52263 #if defined(BCM_56370_A0)
  52264     { /* SOC_REG_INT_GTFCS_BCM56370_A0r */
  52265         soc_block_list[9],
  52266         soc_portreg,
  52267         1,
  52268         0,
  52269         0x2200,
  52270         SOC_REG_FLAG_COUNTER |
  52271                           SOC_REG_FLAG_ED_CNTR,
  52272         0,
  52273         1,
  52274         soc_GR1023_BCM53400_A0r_fields,
  52275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52276         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52277         94,
  52278         -1,
  52279         3,
  52280     },
  52281 #endif /* chips */
  52282 
  52283 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  52284     { /* SOC_REG_INT_GTFCS_BCM56440_A0r */
  52285         soc_block_list[2],
  52286         soc_portreg,
  52287         1,
  52288         0,
  52289         0xa2,
  52290         SOC_REG_FLAG_COUNTER |
  52291                           SOC_REG_FLAG_ED_CNTR,
  52292         0,
  52293         1,
  52294         soc_GR1023r_fields,
  52295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52296         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52297         201,
  52298         -1,
  52299     },
  52300 #endif /* chips */
  52301 
  52302 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  52303     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  52304     { /* SOC_REG_INT_GTFCS_BCM56624_A0r */
  52305         soc_block_list[205],
  52306         soc_portreg,
  52307         1,
  52308         0,
  52309         0xae,
  52310         SOC_REG_FLAG_COUNTER |
  52311                           SOC_REG_FLAG_ED_CNTR,
  52312         0,
  52313         1,
  52314         soc_GR1023r_fields,
  52315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52316         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52317         216,
  52318         -1,
  52319     },
  52320 #endif /* chips */
  52321 
  52322 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  52323     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  52324     { /* SOC_REG_INT_GTFCS_BCM56634_A0r */
  52325         soc_block_list[207],
  52326         soc_portreg,
  52327         1,
  52328         0,
  52329         0xae,
  52330         SOC_REG_FLAG_COUNTER |
  52331                           SOC_REG_FLAG_ED_CNTR,
  52332         0,
  52333         1,
  52334         soc_GR1023r_fields,
  52335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52336         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52337         216,
  52338         -1,
  52339     },
  52340 #endif /* chips */
  52341 
  52342 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  52343     { /* SOC_REG_INT_GTFCS_BCM56685_A0r */
  52344         soc_block_list[209],
  52345         soc_portreg,
  52346         1,
  52347         0,
  52348         0xae,
  52349         SOC_REG_FLAG_COUNTER |
  52350                           SOC_REG_FLAG_ED_CNTR,
  52351         0,
  52352         1,
  52353         soc_GR1023r_fields,
  52354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52355         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52356         216,
  52357         -1,
  52358     },
  52359 #endif /* chips */
  52360 
  52361 #if defined(BCM_56800_A0)
  52362     { /* SOC_REG_INT_GTFCS_BCM56800_A0r */
  52363         soc_block_list[9],
  52364         soc_portreg,
  52365         1,
  52366         0,
  52367         0x73,
  52368         SOC_REG_FLAG_COUNTER |
  52369                           SOC_REG_FLAG_ED_CNTR,
  52370         0,
  52371         1,
  52372         soc_GR1023r_fields,
  52373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52375         157,
  52376         -1,
  52377     },
  52378 #endif /* chips */
  52379 
  52380 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  52381     { /* SOC_REG_INT_GTFCS_BCM56820_A0r */
  52382         soc_block_list[206],
  52383         soc_portreg,
  52384         1,
  52385         0,
  52386         0xaf,
  52387         SOC_REG_FLAG_COUNTER |
  52388                           SOC_REG_FLAG_ED_CNTR,
  52389         0,
  52390         1,
  52391         soc_GR1023r_fields,
  52392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52393         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52394         227,
  52395         -1,
  52396     },
  52397 #endif /* chips */
  52398 
  52399 #if defined(BCM_88375_A0)
  52400     { /* SOC_REG_INT_GTFCS_BCM88375_A0r */
  52401         soc_block_list[2],
  52402         soc_portreg,
  52403         1,
  52404         0,
  52405         0x2100,
  52406         SOC_REG_FLAG_COUNTER,
  52407         0,
  52408         1,
  52409         soc_GTFCS_BCM88375_A0r_fields,
  52410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52411         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52412         33,
  52413         -1,
  52414     },
  52415 #endif /* chips */
  52416 
  52417 #if defined(BCM_88375_B0)
  52418     { /* SOC_REG_INT_GTFCS_BCM88375_B0r */
  52419         soc_block_list[2],
  52420         soc_portreg,
  52421         1,
  52422         0,
  52423         0x2100,
  52424         SOC_REG_FLAG_COUNTER,
  52425         0,
  52426         1,
  52427         soc_GTFCS_BCM88375_B0r_fields,
  52428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52429         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52430         33,
  52431         -1,
  52432     },
  52433 #endif /* chips */
  52434 
  52435 #if defined(BCM_88470_A0)
  52436     { /* SOC_REG_INT_GTFCS_BCM88470_A0r */
  52437         soc_block_list[2],
  52438         soc_portreg,
  52439         1,
  52440         0,
  52441         0x2100,
  52442         SOC_REG_FLAG_COUNTER,
  52443         0,
  52444         1,
  52445         soc_GTFCS_BCM88470_A0r_fields,
  52446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52447         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52448         33,
  52449         -1,
  52450     },
  52451 #endif /* chips */
  52452 
  52453 #if defined(BCM_88470_B0)
  52454     { /* SOC_REG_INT_GTFCS_BCM88470_B0r */
  52455         soc_block_list[2],
  52456         soc_portreg,
  52457         1,
  52458         0,
  52459         0x2100,
  52460         SOC_REG_FLAG_COUNTER,
  52461         0,
  52462         1,
  52463         soc_GTFCS_BCM88470_B0r_fields,
  52464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52465         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52466         33,
  52467         -1,
  52468     },
  52469 #endif /* chips */
  52470 
  52471 #if defined(BCM_88675_A0)
  52472     { /* SOC_REG_INT_GTFCS_BCM88675_A0r */
  52473         soc_block_list[2],
  52474         soc_portreg,
  52475         1,
  52476         0,
  52477         0x2100,
  52478         SOC_REG_FLAG_COUNTER,
  52479         0,
  52480         1,
  52481         soc_GTFCSr_fields,
  52482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52483         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52484         33,
  52485         -1,
  52486     },
  52487 #endif /* chips */
  52488 
  52489 #if defined(BCM_88675_B0)
  52490     { /* SOC_REG_INT_GTFCS_BCM88675_B0r */
  52491         soc_block_list[2],
  52492         soc_portreg,
  52493         1,
  52494         0,
  52495         0x2100,
  52496         SOC_REG_FLAG_COUNTER,
  52497         0,
  52498         1,
  52499         soc_GTFCS_BCM88675_B0r_fields,
  52500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52501         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52502         33,
  52503         -1,
  52504     },
  52505 #endif /* chips */
  52506 
  52507 #if defined(BCM_88680_A0)
  52508     { /* SOC_REG_INT_GTFCS_BCM88680_A0r */
  52509         soc_block_list[2],
  52510         soc_portreg,
  52511         1,
  52512         0,
  52513         0x2100,
  52514         SOC_REG_FLAG_COUNTER,
  52515         0,
  52516         1,
  52517         soc_GTFCS_BCM88680_A0r_fields,
  52518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52519         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52520         33,
  52521         -1,
  52522     },
  52523 #endif /* chips */
  52524 
  52525 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  52526     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  52527     { /* SOC_REG_INT_GTFRGr */
  52528         soc_block_list[2],
  52529         soc_portreg,
  52530         1,
  52531         0,
  52532         0x35,
  52533         SOC_REG_FLAG_COUNTER |
  52534                           SOC_REG_FLAG_ED_CNTR,
  52535         0,
  52536         1,
  52537         soc_GR1023r_fields,
  52538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52540         87,
  52541         -1,
  52542     },
  52543 #endif /* chips */
  52544 
  52545 #if defined(BCM_53570_A0)
  52546     { /* SOC_REG_INT_GTFRGPr */
  52547         soc_block_list[2],
  52548         soc_portreg,
  52549         1,
  52550         0,
  52551         0x9000,
  52552         SOC_REG_FLAG_COUNTER |
  52553                           SOC_REG_FLAG_ED_CNTR,
  52554         0,
  52555         1,
  52556         soc_GR1023_BCM53400_A0r_fields,
  52557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52559         298,
  52560         -1,
  52561     },
  52562 #endif /* chips */
  52563 
  52564 #if defined(BCM_53570_B0)
  52565     { /* SOC_REG_INT_GTFRGP_BCM53570_B0r */
  52566         soc_block_list[2],
  52567         soc_portreg,
  52568         1,
  52569         0,
  52570         0x9000,
  52571         SOC_REG_FLAG_COUNTER |
  52572                           SOC_REG_FLAG_ED_CNTR,
  52573         0,
  52574         1,
  52575         soc_GR1023_BCM53400_A0r_fields,
  52576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52577         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52578         302,
  52579         -1,
  52580     },
  52581 #endif /* chips */
  52582 
  52583 #if defined(BCM_53400_A0)
  52584     { /* SOC_REG_INT_GTFRG_BCM53400_A0r */
  52585         soc_block_list[9],
  52586         soc_portreg,
  52587         1,
  52588         0,
  52589         0x2a00,
  52590         SOC_REG_FLAG_COUNTER |
  52591                           SOC_REG_FLAG_ED_CNTR,
  52592         0,
  52593         1,
  52594         soc_GR1023_BCM53400_A0r_fields,
  52595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52596         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52597         141,
  52598         -1,
  52599     },
  52600 #endif /* chips */
  52601 
  52602 #if defined(BCM_53540_A0)
  52603     { /* SOC_REG_INT_GTFRG_BCM53540_A0r */
  52604         soc_block_list[2],
  52605         soc_portreg,
  52606         1,
  52607         0,
  52608         0x3b00,
  52609         SOC_REG_FLAG_COUNTER |
  52610                           SOC_REG_FLAG_ED_CNTR,
  52611         0,
  52612         1,
  52613         soc_GR1023_BCM53400_A0r_fields,
  52614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52616         158,
  52617         -1,
  52618     },
  52619 #endif /* chips */
  52620 
  52621 #if defined(BCM_53570_A0)
  52622     { /* SOC_REG_INT_GTFRG_BCM53570_A0r */
  52623         soc_block_list[2],
  52624         soc_portreg,
  52625         1,
  52626         0,
  52627         0x3b00,
  52628         SOC_REG_FLAG_COUNTER |
  52629                           SOC_REG_FLAG_ED_CNTR,
  52630         0,
  52631         1,
  52632         soc_GR1023_BCM53400_A0r_fields,
  52633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52634         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52635         213,
  52636         -1,
  52637     },
  52638 #endif /* chips */
  52639 
  52640 #if defined(BCM_53570_B0)
  52641     { /* SOC_REG_INT_GTFRG_BCM53570_B0r */
  52642         soc_block_list[2],
  52643         soc_portreg,
  52644         1,
  52645         0,
  52646         0x3b00,
  52647         SOC_REG_FLAG_COUNTER |
  52648                           SOC_REG_FLAG_ED_CNTR,
  52649         0,
  52650         1,
  52651         soc_GR1023_BCM53400_A0r_fields,
  52652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52654         217,
  52655         -1,
  52656     },
  52657 #endif /* chips */
  52658 
  52659 #if defined(BCM_56142_A0)
  52660     { /* SOC_REG_INT_GTFRG_BCM56142_A0r */
  52661         soc_block_list[210],
  52662         soc_portreg,
  52663         1,
  52664         0,
  52665         0xaa,
  52666         SOC_REG_FLAG_COUNTER |
  52667                           SOC_REG_FLAG_ED_CNTR,
  52668         0,
  52669         1,
  52670         soc_GR1023r_fields,
  52671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52672         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52673         217,
  52674         -1,
  52675     },
  52676 #endif /* chips */
  52677 
  52678 #if defined(BCM_56150_A0)
  52679     { /* SOC_REG_INT_GTFRG_BCM56150_A0r */
  52680         soc_block_list[2],
  52681         soc_portreg,
  52682         1,
  52683         0,
  52684         0x2a00,
  52685         SOC_REG_FLAG_COUNTER |
  52686                           SOC_REG_FLAG_ED_CNTR,
  52687         0,
  52688         1,
  52689         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  52690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52692         137,
  52693         -1,
  52694     },
  52695 #endif /* chips */
  52696 
  52697 #if defined(BCM_56160_A0)
  52698     { /* SOC_REG_INT_GTFRG_BCM56160_A0r */
  52699         soc_block_list[2],
  52700         soc_portreg,
  52701         1,
  52702         0,
  52703         0x3b00,
  52704         SOC_REG_FLAG_COUNTER |
  52705                           SOC_REG_FLAG_ED_CNTR,
  52706         0,
  52707         1,
  52708         soc_GR1023_BCM53400_A0r_fields,
  52709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52710         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52711         158,
  52712         -1,
  52713     },
  52714 #endif /* chips */
  52715 
  52716 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  52717     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  52718     { /* SOC_REG_INT_GTFRG_BCM56224_A0r */
  52719         soc_block_list[2],
  52720         soc_portreg,
  52721         1,
  52722         0,
  52723         0x2a,
  52724         SOC_REG_FLAG_COUNTER |
  52725                           SOC_REG_FLAG_ED_CNTR,
  52726         0,
  52727         1,
  52728         soc_GR1023r_fields,
  52729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52730         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52731         76,
  52732         -1,
  52733     },
  52734 #endif /* chips */
  52735 
  52736 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  52737     { /* SOC_REG_INT_GTFRG_BCM56334_A0r */
  52738         soc_block_list[210],
  52739         soc_portreg,
  52740         1,
  52741         0,
  52742         0xaa,
  52743         SOC_REG_FLAG_COUNTER |
  52744                           SOC_REG_FLAG_ED_CNTR,
  52745         0,
  52746         1,
  52747         soc_GR1023r_fields,
  52748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52749         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52750         212,
  52751         -1,
  52752     },
  52753 #endif /* chips */
  52754 
  52755 #if defined(BCM_56370_A0)
  52756     { /* SOC_REG_INT_GTFRG_BCM56370_A0r */
  52757         soc_block_list[9],
  52758         soc_portreg,
  52759         1,
  52760         0,
  52761         0x2b00,
  52762         SOC_REG_FLAG_COUNTER |
  52763                           SOC_REG_FLAG_ED_CNTR,
  52764         0,
  52765         1,
  52766         soc_GR1023_BCM53400_A0r_fields,
  52767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52768         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52769         103,
  52770         -1,
  52771         3,
  52772     },
  52773 #endif /* chips */
  52774 
  52775 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  52776     { /* SOC_REG_INT_GTFRG_BCM56440_A0r */
  52777         soc_block_list[2],
  52778         soc_portreg,
  52779         1,
  52780         0,
  52781         0xab,
  52782         SOC_REG_FLAG_COUNTER |
  52783                           SOC_REG_FLAG_ED_CNTR,
  52784         0,
  52785         1,
  52786         soc_GR1023r_fields,
  52787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52788         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52789         210,
  52790         -1,
  52791     },
  52792 #endif /* chips */
  52793 
  52794 #if defined(BCM_56514_A0)
  52795     { /* SOC_REG_INT_GTFRG_BCM56514_A0r */
  52796         soc_block_list[2],
  52797         soc_portreg,
  52798         1,
  52799         0,
  52800         0x37,
  52801         SOC_REG_FLAG_COUNTER |
  52802                           SOC_REG_FLAG_ED_CNTR,
  52803         0,
  52804         1,
  52805         soc_GR1023r_fields,
  52806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52808         89,
  52809         -1,
  52810     },
  52811 #endif /* chips */
  52812 
  52813 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  52814     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  52815     { /* SOC_REG_INT_GTFRG_BCM56624_A0r */
  52816         soc_block_list[205],
  52817         soc_portreg,
  52818         1,
  52819         0,
  52820         0xb7,
  52821         SOC_REG_FLAG_COUNTER |
  52822                           SOC_REG_FLAG_ED_CNTR,
  52823         0,
  52824         1,
  52825         soc_GR1023r_fields,
  52826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52828         225,
  52829         -1,
  52830     },
  52831 #endif /* chips */
  52832 
  52833 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  52834     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  52835     { /* SOC_REG_INT_GTFRG_BCM56634_A0r */
  52836         soc_block_list[207],
  52837         soc_portreg,
  52838         1,
  52839         0,
  52840         0xb7,
  52841         SOC_REG_FLAG_COUNTER |
  52842                           SOC_REG_FLAG_ED_CNTR,
  52843         0,
  52844         1,
  52845         soc_GR1023r_fields,
  52846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52847         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52848         225,
  52849         -1,
  52850     },
  52851 #endif /* chips */
  52852 
  52853 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  52854     { /* SOC_REG_INT_GTFRG_BCM56685_A0r */
  52855         soc_block_list[209],
  52856         soc_portreg,
  52857         1,
  52858         0,
  52859         0xb7,
  52860         SOC_REG_FLAG_COUNTER |
  52861                           SOC_REG_FLAG_ED_CNTR,
  52862         0,
  52863         1,
  52864         soc_GR1023r_fields,
  52865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52866         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52867         225,
  52868         -1,
  52869     },
  52870 #endif /* chips */
  52871 
  52872 #if defined(BCM_56800_A0)
  52873     { /* SOC_REG_INT_GTFRG_BCM56800_A0r */
  52874         soc_block_list[9],
  52875         soc_portreg,
  52876         1,
  52877         0,
  52878         0x7c,
  52879         SOC_REG_FLAG_COUNTER |
  52880                           SOC_REG_FLAG_ED_CNTR,
  52881         0,
  52882         1,
  52883         soc_GR1023r_fields,
  52884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52886         166,
  52887         -1,
  52888     },
  52889 #endif /* chips */
  52890 
  52891 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  52892     { /* SOC_REG_INT_GTFRG_BCM56820_A0r */
  52893         soc_block_list[206],
  52894         soc_portreg,
  52895         1,
  52896         0,
  52897         0xb8,
  52898         SOC_REG_FLAG_COUNTER |
  52899                           SOC_REG_FLAG_ED_CNTR,
  52900         0,
  52901         1,
  52902         soc_GR1023r_fields,
  52903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52904         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52905         236,
  52906         -1,
  52907     },
  52908 #endif /* chips */
  52909 
  52910 #if defined(BCM_88375_A0)
  52911     { /* SOC_REG_INT_GTFRG_BCM88375_A0r */
  52912         soc_block_list[2],
  52913         soc_portreg,
  52914         1,
  52915         0,
  52916         0x2a00,
  52917         SOC_REG_FLAG_COUNTER,
  52918         0,
  52919         1,
  52920         soc_GTFRG_BCM88375_A0r_fields,
  52921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52923         42,
  52924         -1,
  52925     },
  52926 #endif /* chips */
  52927 
  52928 #if defined(BCM_88375_B0)
  52929     { /* SOC_REG_INT_GTFRG_BCM88375_B0r */
  52930         soc_block_list[2],
  52931         soc_portreg,
  52932         1,
  52933         0,
  52934         0x2a00,
  52935         SOC_REG_FLAG_COUNTER,
  52936         0,
  52937         1,
  52938         soc_GTFRG_BCM88375_B0r_fields,
  52939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52941         42,
  52942         -1,
  52943     },
  52944 #endif /* chips */
  52945 
  52946 #if defined(BCM_88470_A0)
  52947     { /* SOC_REG_INT_GTFRG_BCM88470_A0r */
  52948         soc_block_list[2],
  52949         soc_portreg,
  52950         1,
  52951         0,
  52952         0x2a00,
  52953         SOC_REG_FLAG_COUNTER,
  52954         0,
  52955         1,
  52956         soc_GTFRG_BCM88470_A0r_fields,
  52957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52959         42,
  52960         -1,
  52961     },
  52962 #endif /* chips */
  52963 
  52964 #if defined(BCM_88470_B0)
  52965     { /* SOC_REG_INT_GTFRG_BCM88470_B0r */
  52966         soc_block_list[2],
  52967         soc_portreg,
  52968         1,
  52969         0,
  52970         0x2a00,
  52971         SOC_REG_FLAG_COUNTER,
  52972         0,
  52973         1,
  52974         soc_GTFRG_BCM88470_B0r_fields,
  52975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52976         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52977         42,
  52978         -1,
  52979     },
  52980 #endif /* chips */
  52981 
  52982 #if defined(BCM_88675_A0)
  52983     { /* SOC_REG_INT_GTFRG_BCM88675_A0r */
  52984         soc_block_list[2],
  52985         soc_portreg,
  52986         1,
  52987         0,
  52988         0x2a00,
  52989         SOC_REG_FLAG_COUNTER,
  52990         0,
  52991         1,
  52992         soc_GTFRGr_fields,
  52993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52994         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52995         42,
  52996         -1,
  52997     },
  52998 #endif /* chips */
  52999 
  53000 #if defined(BCM_88675_B0)
  53001     { /* SOC_REG_INT_GTFRG_BCM88675_B0r */
  53002         soc_block_list[2],
  53003         soc_portreg,
  53004         1,
  53005         0,
  53006         0x2a00,
  53007         SOC_REG_FLAG_COUNTER,
  53008         0,
  53009         1,
  53010         soc_GTFRG_BCM88675_B0r_fields,
  53011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53012         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53013         42,
  53014         -1,
  53015     },
  53016 #endif /* chips */
  53017 
  53018 #if defined(BCM_88680_A0)
  53019     { /* SOC_REG_INT_GTFRG_BCM88680_A0r */
  53020         soc_block_list[2],
  53021         soc_portreg,
  53022         1,
  53023         0,
  53024         0x2a00,
  53025         SOC_REG_FLAG_COUNTER,
  53026         0,
  53027         1,
  53028         soc_GTFRG_BCM88680_A0r_fields,
  53029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53030         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53031         42,
  53032         -1,
  53033     },
  53034 #endif /* chips */
  53035 
  53036 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  53037     defined(BCM_56504_B0)
  53038     { /* SOC_REG_INT_GTJBRr */
  53039         soc_block_list[2],
  53040         soc_portreg,
  53041         1,
  53042         0,
  53043         0x2b,
  53044         SOC_REG_FLAG_COUNTER |
  53045                           SOC_REG_FLAG_ED_CNTR,
  53046         0,
  53047         1,
  53048         soc_GR1023r_fields,
  53049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53050         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53051         77,
  53052         -1,
  53053     },
  53054 #endif /* chips */
  53055 
  53056 #if defined(BCM_53570_A0)
  53057     { /* SOC_REG_INT_GTJBRPr */
  53058         soc_block_list[2],
  53059         soc_portreg,
  53060         1,
  53061         0,
  53062         0x8700,
  53063         SOC_REG_FLAG_COUNTER,
  53064         0,
  53065         1,
  53066         soc_GR1023_BCM53400_A0r_fields,
  53067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53068         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53069         289,
  53070         -1,
  53071     },
  53072 #endif /* chips */
  53073 
  53074 #if defined(BCM_53570_B0)
  53075     { /* SOC_REG_INT_GTJBRP_BCM53570_B0r */
  53076         soc_block_list[2],
  53077         soc_portreg,
  53078         1,
  53079         0,
  53080         0x8700,
  53081         SOC_REG_FLAG_COUNTER,
  53082         0,
  53083         1,
  53084         soc_GR1023_BCM53400_A0r_fields,
  53085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53086         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53087         293,
  53088         -1,
  53089     },
  53090 #endif /* chips */
  53091 
  53092 #if defined(BCM_53400_A0)
  53093     { /* SOC_REG_INT_GTJBR_BCM53400_A0r */
  53094         soc_block_list[9],
  53095         soc_portreg,
  53096         1,
  53097         0,
  53098         0x2000,
  53099         SOC_REG_FLAG_COUNTER,
  53100         0,
  53101         1,
  53102         soc_GR1023_BCM53400_A0r_fields,
  53103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53105         131,
  53106         -1,
  53107     },
  53108 #endif /* chips */
  53109 
  53110 #if defined(BCM_53540_A0)
  53111     { /* SOC_REG_INT_GTJBR_BCM53540_A0r */
  53112         soc_block_list[2],
  53113         soc_portreg,
  53114         1,
  53115         0,
  53116         0x3100,
  53117         SOC_REG_FLAG_COUNTER,
  53118         0,
  53119         1,
  53120         soc_GR1023_BCM53400_A0r_fields,
  53121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53122         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53123         148,
  53124         -1,
  53125     },
  53126 #endif /* chips */
  53127 
  53128 #if defined(BCM_53570_A0)
  53129     { /* SOC_REG_INT_GTJBR_BCM53570_A0r */
  53130         soc_block_list[2],
  53131         soc_portreg,
  53132         1,
  53133         0,
  53134         0x3100,
  53135         SOC_REG_FLAG_COUNTER,
  53136         0,
  53137         1,
  53138         soc_GR1023_BCM53400_A0r_fields,
  53139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53141         203,
  53142         -1,
  53143     },
  53144 #endif /* chips */
  53145 
  53146 #if defined(BCM_53570_B0)
  53147     { /* SOC_REG_INT_GTJBR_BCM53570_B0r */
  53148         soc_block_list[2],
  53149         soc_portreg,
  53150         1,
  53151         0,
  53152         0x3100,
  53153         SOC_REG_FLAG_COUNTER,
  53154         0,
  53155         1,
  53156         soc_GR1023_BCM53400_A0r_fields,
  53157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53159         207,
  53160         -1,
  53161     },
  53162 #endif /* chips */
  53163 
  53164 #if defined(BCM_56142_A0)
  53165     { /* SOC_REG_INT_GTJBR_BCM56142_A0r */
  53166         soc_block_list[210],
  53167         soc_portreg,
  53168         1,
  53169         0,
  53170         0xa0,
  53171         SOC_REG_FLAG_COUNTER,
  53172         0,
  53173         1,
  53174         soc_GR1023r_fields,
  53175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53176         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53177         207,
  53178         -1,
  53179     },
  53180 #endif /* chips */
  53181 
  53182 #if defined(BCM_56150_A0)
  53183     { /* SOC_REG_INT_GTJBR_BCM56150_A0r */
  53184         soc_block_list[2],
  53185         soc_portreg,
  53186         1,
  53187         0,
  53188         0x2000,
  53189         SOC_REG_FLAG_COUNTER,
  53190         0,
  53191         1,
  53192         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  53193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53194         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53195         127,
  53196         -1,
  53197     },
  53198 #endif /* chips */
  53199 
  53200 #if defined(BCM_56160_A0)
  53201     { /* SOC_REG_INT_GTJBR_BCM56160_A0r */
  53202         soc_block_list[2],
  53203         soc_portreg,
  53204         1,
  53205         0,
  53206         0x3100,
  53207         SOC_REG_FLAG_COUNTER,
  53208         0,
  53209         1,
  53210         soc_GR1023_BCM53400_A0r_fields,
  53211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53212         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53213         148,
  53214         -1,
  53215     },
  53216 #endif /* chips */
  53217 
  53218 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  53219     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  53220     { /* SOC_REG_INT_GTJBR_BCM56224_A0r */
  53221         soc_block_list[2],
  53222         soc_portreg,
  53223         1,
  53224         0,
  53225         0x20,
  53226         SOC_REG_FLAG_COUNTER,
  53227         0,
  53228         1,
  53229         soc_GR1023r_fields,
  53230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53232         66,
  53233         -1,
  53234     },
  53235 #endif /* chips */
  53236 
  53237 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  53238     { /* SOC_REG_INT_GTJBR_BCM56334_A0r */
  53239         soc_block_list[210],
  53240         soc_portreg,
  53241         1,
  53242         0,
  53243         0xa0,
  53244         SOC_REG_FLAG_COUNTER,
  53245         0,
  53246         1,
  53247         soc_GR1023r_fields,
  53248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53250         202,
  53251         -1,
  53252     },
  53253 #endif /* chips */
  53254 
  53255 #if defined(BCM_56370_A0)
  53256     { /* SOC_REG_INT_GTJBR_BCM56370_A0r */
  53257         soc_block_list[9],
  53258         soc_portreg,
  53259         1,
  53260         0,
  53261         0x2100,
  53262         SOC_REG_FLAG_COUNTER,
  53263         0,
  53264         1,
  53265         soc_GR1023_BCM53400_A0r_fields,
  53266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53267         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53268         93,
  53269         -1,
  53270         3,
  53271     },
  53272 #endif /* chips */
  53273 
  53274 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  53275     { /* SOC_REG_INT_GTJBR_BCM56440_A0r */
  53276         soc_block_list[2],
  53277         soc_portreg,
  53278         1,
  53279         0,
  53280         0xa1,
  53281         SOC_REG_FLAG_COUNTER,
  53282         0,
  53283         1,
  53284         soc_GR1023r_fields,
  53285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53286         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53287         200,
  53288         -1,
  53289     },
  53290 #endif /* chips */
  53291 
  53292 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  53293     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  53294     { /* SOC_REG_INT_GTJBR_BCM56624_A0r */
  53295         soc_block_list[205],
  53296         soc_portreg,
  53297         1,
  53298         0,
  53299         0xad,
  53300         SOC_REG_FLAG_COUNTER,
  53301         0,
  53302         1,
  53303         soc_GR1023r_fields,
  53304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53305         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53306         215,
  53307         -1,
  53308     },
  53309 #endif /* chips */
  53310 
  53311 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  53312     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  53313     { /* SOC_REG_INT_GTJBR_BCM56634_A0r */
  53314         soc_block_list[207],
  53315         soc_portreg,
  53316         1,
  53317         0,
  53318         0xad,
  53319         SOC_REG_FLAG_COUNTER,
  53320         0,
  53321         1,
  53322         soc_GR1023r_fields,
  53323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53324         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53325         215,
  53326         -1,
  53327     },
  53328 #endif /* chips */
  53329 
  53330 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  53331     { /* SOC_REG_INT_GTJBR_BCM56685_A0r */
  53332         soc_block_list[209],
  53333         soc_portreg,
  53334         1,
  53335         0,
  53336         0xad,
  53337         SOC_REG_FLAG_COUNTER,
  53338         0,
  53339         1,
  53340         soc_GR1023r_fields,
  53341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53342         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53343         215,
  53344         -1,
  53345     },
  53346 #endif /* chips */
  53347 
  53348 #if defined(BCM_56800_A0)
  53349     { /* SOC_REG_INT_GTJBR_BCM56800_A0r */
  53350         soc_block_list[9],
  53351         soc_portreg,
  53352         1,
  53353         0,
  53354         0x72,
  53355         SOC_REG_FLAG_COUNTER,
  53356         0,
  53357         1,
  53358         soc_GR1023r_fields,
  53359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53360         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53361         156,
  53362         -1,
  53363     },
  53364 #endif /* chips */
  53365 
  53366 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  53367     { /* SOC_REG_INT_GTJBR_BCM56820_A0r */
  53368         soc_block_list[206],
  53369         soc_portreg,
  53370         1,
  53371         0,
  53372         0xae,
  53373         SOC_REG_FLAG_COUNTER,
  53374         0,
  53375         1,
  53376         soc_GR1023r_fields,
  53377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53378         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53379         226,
  53380         -1,
  53381     },
  53382 #endif /* chips */
  53383 
  53384 #if defined(BCM_88375_A0)
  53385     { /* SOC_REG_INT_GTJBR_BCM88375_A0r */
  53386         soc_block_list[2],
  53387         soc_portreg,
  53388         1,
  53389         0,
  53390         0x2000,
  53391         SOC_REG_FLAG_COUNTER,
  53392         0,
  53393         1,
  53394         soc_GTJBR_BCM88375_A0r_fields,
  53395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53396         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53397         32,
  53398         -1,
  53399     },
  53400 #endif /* chips */
  53401 
  53402 #if defined(BCM_88375_B0)
  53403     { /* SOC_REG_INT_GTJBR_BCM88375_B0r */
  53404         soc_block_list[2],
  53405         soc_portreg,
  53406         1,
  53407         0,
  53408         0x2000,
  53409         SOC_REG_FLAG_COUNTER,
  53410         0,
  53411         1,
  53412         soc_GTJBR_BCM88375_B0r_fields,
  53413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53414         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53415         32,
  53416         -1,
  53417     },
  53418 #endif /* chips */
  53419 
  53420 #if defined(BCM_88470_A0)
  53421     { /* SOC_REG_INT_GTJBR_BCM88470_A0r */
  53422         soc_block_list[2],
  53423         soc_portreg,
  53424         1,
  53425         0,
  53426         0x2000,
  53427         SOC_REG_FLAG_COUNTER,
  53428         0,
  53429         1,
  53430         soc_GTJBR_BCM88470_A0r_fields,
  53431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53433         32,
  53434         -1,
  53435     },
  53436 #endif /* chips */
  53437 
  53438 #if defined(BCM_88470_B0)
  53439     { /* SOC_REG_INT_GTJBR_BCM88470_B0r */
  53440         soc_block_list[2],
  53441         soc_portreg,
  53442         1,
  53443         0,
  53444         0x2000,
  53445         SOC_REG_FLAG_COUNTER,
  53446         0,
  53447         1,
  53448         soc_GTJBR_BCM88470_B0r_fields,
  53449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53451         32,
  53452         -1,
  53453     },
  53454 #endif /* chips */
  53455 
  53456 #if defined(BCM_88675_A0)
  53457     { /* SOC_REG_INT_GTJBR_BCM88675_A0r */
  53458         soc_block_list[2],
  53459         soc_portreg,
  53460         1,
  53461         0,
  53462         0x2000,
  53463         SOC_REG_FLAG_COUNTER,
  53464         0,
  53465         1,
  53466         soc_GTJBRr_fields,
  53467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53469         32,
  53470         -1,
  53471     },
  53472 #endif /* chips */
  53473 
  53474 #if defined(BCM_88675_B0)
  53475     { /* SOC_REG_INT_GTJBR_BCM88675_B0r */
  53476         soc_block_list[2],
  53477         soc_portreg,
  53478         1,
  53479         0,
  53480         0x2000,
  53481         SOC_REG_FLAG_COUNTER,
  53482         0,
  53483         1,
  53484         soc_GTJBR_BCM88675_B0r_fields,
  53485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53487         32,
  53488         -1,
  53489     },
  53490 #endif /* chips */
  53491 
  53492 #if defined(BCM_88680_A0)
  53493     { /* SOC_REG_INT_GTJBR_BCM88680_A0r */
  53494         soc_block_list[2],
  53495         soc_portreg,
  53496         1,
  53497         0,
  53498         0x2000,
  53499         SOC_REG_FLAG_COUNTER,
  53500         0,
  53501         1,
  53502         soc_GTJBR_BCM88680_A0r_fields,
  53503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53504         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53505         32,
  53506         -1,
  53507     },
  53508 #endif /* chips */
  53509 
  53510 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  53511     defined(BCM_56504_B0)
  53512     { /* SOC_REG_INT_GTLCLr */
  53513         soc_block_list[2],
  53514         soc_portreg,
  53515         1,
  53516         0,
  53517         0x33,
  53518         SOC_REG_FLAG_COUNTER |
  53519                           SOC_REG_FLAG_ED_CNTR,
  53520         0,
  53521         1,
  53522         soc_GR1023r_fields,
  53523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53524         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53525         85,
  53526         -1,
  53527     },
  53528 #endif /* chips */
  53529 
  53530 #if defined(BCM_53570_A0)
  53531     { /* SOC_REG_INT_GTLCLPr */
  53532         soc_block_list[2],
  53533         soc_portreg,
  53534         1,
  53535         0,
  53536         0x8e00,
  53537         SOC_REG_FLAG_COUNTER |
  53538                           SOC_REG_FLAG_ED_CNTR,
  53539         0,
  53540         1,
  53541         soc_GR1023_BCM53400_A0r_fields,
  53542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53544         296,
  53545         -1,
  53546     },
  53547 #endif /* chips */
  53548 
  53549 #if defined(BCM_53570_B0)
  53550     { /* SOC_REG_INT_GTLCLP_BCM53570_B0r */
  53551         soc_block_list[2],
  53552         soc_portreg,
  53553         1,
  53554         0,
  53555         0x8e00,
  53556         SOC_REG_FLAG_COUNTER |
  53557                           SOC_REG_FLAG_ED_CNTR,
  53558         0,
  53559         1,
  53560         soc_GR1023_BCM53400_A0r_fields,
  53561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53562         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53563         300,
  53564         -1,
  53565     },
  53566 #endif /* chips */
  53567 
  53568 #if defined(BCM_53400_A0)
  53569     { /* SOC_REG_INT_GTLCL_BCM53400_A0r */
  53570         soc_block_list[9],
  53571         soc_portreg,
  53572         1,
  53573         0,
  53574         0x2800,
  53575         SOC_REG_FLAG_COUNTER |
  53576                           SOC_REG_FLAG_ED_CNTR,
  53577         0,
  53578         1,
  53579         soc_GR1023_BCM53400_A0r_fields,
  53580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53582         139,
  53583         -1,
  53584     },
  53585 #endif /* chips */
  53586 
  53587 #if defined(BCM_53540_A0)
  53588     { /* SOC_REG_INT_GTLCL_BCM53540_A0r */
  53589         soc_block_list[2],
  53590         soc_portreg,
  53591         1,
  53592         0,
  53593         0x3900,
  53594         SOC_REG_FLAG_COUNTER |
  53595                           SOC_REG_FLAG_ED_CNTR,
  53596         0,
  53597         1,
  53598         soc_GR1023_BCM53400_A0r_fields,
  53599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53600         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53601         156,
  53602         -1,
  53603     },
  53604 #endif /* chips */
  53605 
  53606 #if defined(BCM_53570_A0)
  53607     { /* SOC_REG_INT_GTLCL_BCM53570_A0r */
  53608         soc_block_list[2],
  53609         soc_portreg,
  53610         1,
  53611         0,
  53612         0x3900,
  53613         SOC_REG_FLAG_COUNTER |
  53614                           SOC_REG_FLAG_ED_CNTR,
  53615         0,
  53616         1,
  53617         soc_GR1023_BCM53400_A0r_fields,
  53618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53619         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53620         211,
  53621         -1,
  53622     },
  53623 #endif /* chips */
  53624 
  53625 #if defined(BCM_53570_B0)
  53626     { /* SOC_REG_INT_GTLCL_BCM53570_B0r */
  53627         soc_block_list[2],
  53628         soc_portreg,
  53629         1,
  53630         0,
  53631         0x3900,
  53632         SOC_REG_FLAG_COUNTER |
  53633                           SOC_REG_FLAG_ED_CNTR,
  53634         0,
  53635         1,
  53636         soc_GR1023_BCM53400_A0r_fields,
  53637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53638         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53639         215,
  53640         -1,
  53641     },
  53642 #endif /* chips */
  53643 
  53644 #if defined(BCM_56142_A0)
  53645     { /* SOC_REG_INT_GTLCL_BCM56142_A0r */
  53646         soc_block_list[210],
  53647         soc_portreg,
  53648         1,
  53649         0,
  53650         0xa8,
  53651         SOC_REG_FLAG_COUNTER |
  53652                           SOC_REG_FLAG_ED_CNTR,
  53653         0,
  53654         1,
  53655         soc_GR1023r_fields,
  53656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53657         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53658         215,
  53659         -1,
  53660     },
  53661 #endif /* chips */
  53662 
  53663 #if defined(BCM_56150_A0)
  53664     { /* SOC_REG_INT_GTLCL_BCM56150_A0r */
  53665         soc_block_list[2],
  53666         soc_portreg,
  53667         1,
  53668         0,
  53669         0x2800,
  53670         SOC_REG_FLAG_COUNTER |
  53671                           SOC_REG_FLAG_ED_CNTR,
  53672         0,
  53673         1,
  53674         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  53675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53676         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53677         135,
  53678         -1,
  53679     },
  53680 #endif /* chips */
  53681 
  53682 #if defined(BCM_56160_A0)
  53683     { /* SOC_REG_INT_GTLCL_BCM56160_A0r */
  53684         soc_block_list[2],
  53685         soc_portreg,
  53686         1,
  53687         0,
  53688         0x3900,
  53689         SOC_REG_FLAG_COUNTER |
  53690                           SOC_REG_FLAG_ED_CNTR,
  53691         0,
  53692         1,
  53693         soc_GR1023_BCM53400_A0r_fields,
  53694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53695         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53696         156,
  53697         -1,
  53698     },
  53699 #endif /* chips */
  53700 
  53701 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  53702     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  53703     { /* SOC_REG_INT_GTLCL_BCM56224_A0r */
  53704         soc_block_list[2],
  53705         soc_portreg,
  53706         1,
  53707         0,
  53708         0x28,
  53709         SOC_REG_FLAG_COUNTER |
  53710                           SOC_REG_FLAG_ED_CNTR,
  53711         0,
  53712         1,
  53713         soc_GR1023r_fields,
  53714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53715         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53716         74,
  53717         -1,
  53718     },
  53719 #endif /* chips */
  53720 
  53721 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  53722     { /* SOC_REG_INT_GTLCL_BCM56334_A0r */
  53723         soc_block_list[210],
  53724         soc_portreg,
  53725         1,
  53726         0,
  53727         0xa8,
  53728         SOC_REG_FLAG_COUNTER |
  53729                           SOC_REG_FLAG_ED_CNTR,
  53730         0,
  53731         1,
  53732         soc_GR1023r_fields,
  53733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53734         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53735         210,
  53736         -1,
  53737     },
  53738 #endif /* chips */
  53739 
  53740 #if defined(BCM_56370_A0)
  53741     { /* SOC_REG_INT_GTLCL_BCM56370_A0r */
  53742         soc_block_list[9],
  53743         soc_portreg,
  53744         1,
  53745         0,
  53746         0x2900,
  53747         SOC_REG_FLAG_COUNTER |
  53748                           SOC_REG_FLAG_ED_CNTR,
  53749         0,
  53750         1,
  53751         soc_GR1023_BCM53400_A0r_fields,
  53752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53754         101,
  53755         -1,
  53756         3,
  53757     },
  53758 #endif /* chips */
  53759 
  53760 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  53761     { /* SOC_REG_INT_GTLCL_BCM56440_A0r */
  53762         soc_block_list[2],
  53763         soc_portreg,
  53764         1,
  53765         0,
  53766         0xa9,
  53767         SOC_REG_FLAG_COUNTER |
  53768                           SOC_REG_FLAG_ED_CNTR,
  53769         0,
  53770         1,
  53771         soc_GR1023r_fields,
  53772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53774         208,
  53775         -1,
  53776     },
  53777 #endif /* chips */
  53778 
  53779 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  53780     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  53781     { /* SOC_REG_INT_GTLCL_BCM56624_A0r */
  53782         soc_block_list[205],
  53783         soc_portreg,
  53784         1,
  53785         0,
  53786         0xb5,
  53787         SOC_REG_FLAG_COUNTER |
  53788                           SOC_REG_FLAG_ED_CNTR,
  53789         0,
  53790         1,
  53791         soc_GR1023r_fields,
  53792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53793         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53794         223,
  53795         -1,
  53796     },
  53797 #endif /* chips */
  53798 
  53799 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  53800     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  53801     { /* SOC_REG_INT_GTLCL_BCM56634_A0r */
  53802         soc_block_list[207],
  53803         soc_portreg,
  53804         1,
  53805         0,
  53806         0xb5,
  53807         SOC_REG_FLAG_COUNTER |
  53808                           SOC_REG_FLAG_ED_CNTR,
  53809         0,
  53810         1,
  53811         soc_GR1023r_fields,
  53812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53814         223,
  53815         -1,
  53816     },
  53817 #endif /* chips */
  53818 
  53819 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  53820     { /* SOC_REG_INT_GTLCL_BCM56685_A0r */
  53821         soc_block_list[209],
  53822         soc_portreg,
  53823         1,
  53824         0,
  53825         0xb5,
  53826         SOC_REG_FLAG_COUNTER |
  53827                           SOC_REG_FLAG_ED_CNTR,
  53828         0,
  53829         1,
  53830         soc_GR1023r_fields,
  53831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53833         223,
  53834         -1,
  53835     },
  53836 #endif /* chips */
  53837 
  53838 #if defined(BCM_56800_A0)
  53839     { /* SOC_REG_INT_GTLCL_BCM56800_A0r */
  53840         soc_block_list[9],
  53841         soc_portreg,
  53842         1,
  53843         0,
  53844         0x7a,
  53845         SOC_REG_FLAG_COUNTER |
  53846                           SOC_REG_FLAG_ED_CNTR,
  53847         0,
  53848         1,
  53849         soc_GR1023r_fields,
  53850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53851         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53852         164,
  53853         -1,
  53854     },
  53855 #endif /* chips */
  53856 
  53857 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  53858     { /* SOC_REG_INT_GTLCL_BCM56820_A0r */
  53859         soc_block_list[206],
  53860         soc_portreg,
  53861         1,
  53862         0,
  53863         0xb6,
  53864         SOC_REG_FLAG_COUNTER |
  53865                           SOC_REG_FLAG_ED_CNTR,
  53866         0,
  53867         1,
  53868         soc_GR1023r_fields,
  53869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53870         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53871         234,
  53872         -1,
  53873     },
  53874 #endif /* chips */
  53875 
  53876 #if defined(BCM_88375_A0)
  53877     { /* SOC_REG_INT_GTLCL_BCM88375_A0r */
  53878         soc_block_list[2],
  53879         soc_portreg,
  53880         1,
  53881         0,
  53882         0x2800,
  53883         SOC_REG_FLAG_COUNTER,
  53884         0,
  53885         1,
  53886         soc_GTLCL_BCM88375_A0r_fields,
  53887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53889         40,
  53890         -1,
  53891     },
  53892 #endif /* chips */
  53893 
  53894 #if defined(BCM_88375_B0)
  53895     { /* SOC_REG_INT_GTLCL_BCM88375_B0r */
  53896         soc_block_list[2],
  53897         soc_portreg,
  53898         1,
  53899         0,
  53900         0x2800,
  53901         SOC_REG_FLAG_COUNTER,
  53902         0,
  53903         1,
  53904         soc_GTLCL_BCM88375_B0r_fields,
  53905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53907         40,
  53908         -1,
  53909     },
  53910 #endif /* chips */
  53911 
  53912 #if defined(BCM_88470_A0)
  53913     { /* SOC_REG_INT_GTLCL_BCM88470_A0r */
  53914         soc_block_list[2],
  53915         soc_portreg,
  53916         1,
  53917         0,
  53918         0x2800,
  53919         SOC_REG_FLAG_COUNTER,
  53920         0,
  53921         1,
  53922         soc_GTLCL_BCM88470_A0r_fields,
  53923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53925         40,
  53926         -1,
  53927     },
  53928 #endif /* chips */
  53929 
  53930 #if defined(BCM_88470_B0)
  53931     { /* SOC_REG_INT_GTLCL_BCM88470_B0r */
  53932         soc_block_list[2],
  53933         soc_portreg,
  53934         1,
  53935         0,
  53936         0x2800,
  53937         SOC_REG_FLAG_COUNTER,
  53938         0,
  53939         1,
  53940         soc_GTLCL_BCM88470_B0r_fields,
  53941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53943         40,
  53944         -1,
  53945     },
  53946 #endif /* chips */
  53947 
  53948 #if defined(BCM_88675_A0)
  53949     { /* SOC_REG_INT_GTLCL_BCM88675_A0r */
  53950         soc_block_list[2],
  53951         soc_portreg,
  53952         1,
  53953         0,
  53954         0x2800,
  53955         SOC_REG_FLAG_COUNTER,
  53956         0,
  53957         1,
  53958         soc_GTLCLr_fields,
  53959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53960         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53961         40,
  53962         -1,
  53963     },
  53964 #endif /* chips */
  53965 
  53966 #if defined(BCM_88675_B0)
  53967     { /* SOC_REG_INT_GTLCL_BCM88675_B0r */
  53968         soc_block_list[2],
  53969         soc_portreg,
  53970         1,
  53971         0,
  53972         0x2800,
  53973         SOC_REG_FLAG_COUNTER,
  53974         0,
  53975         1,
  53976         soc_GTLCL_BCM88675_B0r_fields,
  53977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53978         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53979         40,
  53980         -1,
  53981     },
  53982 #endif /* chips */
  53983 
  53984 #if defined(BCM_88680_A0)
  53985     { /* SOC_REG_INT_GTLCL_BCM88680_A0r */
  53986         soc_block_list[2],
  53987         soc_portreg,
  53988         1,
  53989         0,
  53990         0x2800,
  53991         SOC_REG_FLAG_COUNTER,
  53992         0,
  53993         1,
  53994         soc_GTLCL_BCM88680_A0r_fields,
  53995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53997         40,
  53998         -1,
  53999     },
  54000 #endif /* chips */
  54001 
  54002 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  54003     defined(BCM_56504_B0)
  54004     { /* SOC_REG_INT_GTMCAr */
  54005         soc_block_list[2],
  54006         soc_portreg,
  54007         1,
  54008         0,
  54009         0x28,
  54010         SOC_REG_FLAG_COUNTER,
  54011         0,
  54012         1,
  54013         soc_GR1023r_fields,
  54014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54015         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54016         74,
  54017         -1,
  54018     },
  54019 #endif /* chips */
  54020 
  54021 #if defined(BCM_53570_A0)
  54022     { /* SOC_REG_INT_GTMCAPr */
  54023         soc_block_list[2],
  54024         soc_portreg,
  54025         1,
  54026         0,
  54027         0x9200,
  54028         SOC_REG_FLAG_COUNTER,
  54029         0,
  54030         1,
  54031         soc_GR1023_BCM53400_A0r_fields,
  54032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54034         300,
  54035         -1,
  54036     },
  54037 #endif /* chips */
  54038 
  54039 #if defined(BCM_53570_B0)
  54040     { /* SOC_REG_INT_GTMCAP_BCM53570_B0r */
  54041         soc_block_list[2],
  54042         soc_portreg,
  54043         1,
  54044         0,
  54045         0x9200,
  54046         SOC_REG_FLAG_COUNTER,
  54047         0,
  54048         1,
  54049         soc_GR1023_BCM53400_A0r_fields,
  54050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54052         304,
  54053         -1,
  54054     },
  54055 #endif /* chips */
  54056 
  54057 #if defined(BCM_53400_A0)
  54058     { /* SOC_REG_INT_GTMCA_BCM53400_A0r */
  54059         soc_block_list[9],
  54060         soc_portreg,
  54061         1,
  54062         0,
  54063         0x2c00,
  54064         SOC_REG_FLAG_COUNTER,
  54065         0,
  54066         1,
  54067         soc_GR1023_BCM53400_A0r_fields,
  54068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54070         143,
  54071         -1,
  54072     },
  54073 #endif /* chips */
  54074 
  54075 #if defined(BCM_53540_A0)
  54076     { /* SOC_REG_INT_GTMCA_BCM53540_A0r */
  54077         soc_block_list[2],
  54078         soc_portreg,
  54079         1,
  54080         0,
  54081         0x3d00,
  54082         SOC_REG_FLAG_COUNTER,
  54083         0,
  54084         1,
  54085         soc_GR1023_BCM53400_A0r_fields,
  54086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54088         160,
  54089         -1,
  54090     },
  54091 #endif /* chips */
  54092 
  54093 #if defined(BCM_53570_A0)
  54094     { /* SOC_REG_INT_GTMCA_BCM53570_A0r */
  54095         soc_block_list[2],
  54096         soc_portreg,
  54097         1,
  54098         0,
  54099         0x3d00,
  54100         SOC_REG_FLAG_COUNTER,
  54101         0,
  54102         1,
  54103         soc_GR1023_BCM53400_A0r_fields,
  54104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54105         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54106         215,
  54107         -1,
  54108     },
  54109 #endif /* chips */
  54110 
  54111 #if defined(BCM_53570_B0)
  54112     { /* SOC_REG_INT_GTMCA_BCM53570_B0r */
  54113         soc_block_list[2],
  54114         soc_portreg,
  54115         1,
  54116         0,
  54117         0x3d00,
  54118         SOC_REG_FLAG_COUNTER,
  54119         0,
  54120         1,
  54121         soc_GR1023_BCM53400_A0r_fields,
  54122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54124         219,
  54125         -1,
  54126     },
  54127 #endif /* chips */
  54128 
  54129 #if defined(BCM_56142_A0)
  54130     { /* SOC_REG_INT_GTMCA_BCM56142_A0r */
  54131         soc_block_list[210],
  54132         soc_portreg,
  54133         1,
  54134         0,
  54135         0xac,
  54136         SOC_REG_FLAG_COUNTER,
  54137         0,
  54138         1,
  54139         soc_GR1023r_fields,
  54140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54142         219,
  54143         -1,
  54144     },
  54145 #endif /* chips */
  54146 
  54147 #if defined(BCM_56150_A0)
  54148     { /* SOC_REG_INT_GTMCA_BCM56150_A0r */
  54149         soc_block_list[2],
  54150         soc_portreg,
  54151         1,
  54152         0,
  54153         0x2c00,
  54154         SOC_REG_FLAG_COUNTER,
  54155         0,
  54156         1,
  54157         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  54158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54160         139,
  54161         -1,
  54162     },
  54163 #endif /* chips */
  54164 
  54165 #if defined(BCM_56160_A0)
  54166     { /* SOC_REG_INT_GTMCA_BCM56160_A0r */
  54167         soc_block_list[2],
  54168         soc_portreg,
  54169         1,
  54170         0,
  54171         0x3d00,
  54172         SOC_REG_FLAG_COUNTER,
  54173         0,
  54174         1,
  54175         soc_GR1023_BCM53400_A0r_fields,
  54176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54178         160,
  54179         -1,
  54180     },
  54181 #endif /* chips */
  54182 
  54183 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  54184     { /* SOC_REG_INT_GTMCA_BCM56334_A0r */
  54185         soc_block_list[210],
  54186         soc_portreg,
  54187         1,
  54188         0,
  54189         0xac,
  54190         SOC_REG_FLAG_COUNTER,
  54191         0,
  54192         1,
  54193         soc_GR1023r_fields,
  54194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54195         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54196         214,
  54197         -1,
  54198     },
  54199 #endif /* chips */
  54200 
  54201 #if defined(BCM_56370_A0)
  54202     { /* SOC_REG_INT_GTMCA_BCM56370_A0r */
  54203         soc_block_list[9],
  54204         soc_portreg,
  54205         1,
  54206         0,
  54207         0x2d00,
  54208         SOC_REG_FLAG_COUNTER,
  54209         0,
  54210         1,
  54211         soc_GR1023_BCM53400_A0r_fields,
  54212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54213         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54214         105,
  54215         -1,
  54216         3,
  54217     },
  54218 #endif /* chips */
  54219 
  54220 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  54221     { /* SOC_REG_INT_GTMCA_BCM56440_A0r */
  54222         soc_block_list[2],
  54223         soc_portreg,
  54224         1,
  54225         0,
  54226         0xad,
  54227         SOC_REG_FLAG_COUNTER,
  54228         0,
  54229         1,
  54230         soc_GR1023r_fields,
  54231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54233         212,
  54234         -1,
  54235     },
  54236 #endif /* chips */
  54237 
  54238 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  54239     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  54240     { /* SOC_REG_INT_GTMCA_BCM56624_A0r */
  54241         soc_block_list[205],
  54242         soc_portreg,
  54243         1,
  54244         0,
  54245         0xaa,
  54246         SOC_REG_FLAG_COUNTER,
  54247         0,
  54248         1,
  54249         soc_GR1023r_fields,
  54250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54252         212,
  54253         -1,
  54254     },
  54255 #endif /* chips */
  54256 
  54257 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  54258     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  54259     { /* SOC_REG_INT_GTMCA_BCM56634_A0r */
  54260         soc_block_list[207],
  54261         soc_portreg,
  54262         1,
  54263         0,
  54264         0xaa,
  54265         SOC_REG_FLAG_COUNTER,
  54266         0,
  54267         1,
  54268         soc_GR1023r_fields,
  54269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54270         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54271         212,
  54272         -1,
  54273     },
  54274 #endif /* chips */
  54275 
  54276 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  54277     { /* SOC_REG_INT_GTMCA_BCM56685_A0r */
  54278         soc_block_list[209],
  54279         soc_portreg,
  54280         1,
  54281         0,
  54282         0xaa,
  54283         SOC_REG_FLAG_COUNTER,
  54284         0,
  54285         1,
  54286         soc_GR1023r_fields,
  54287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54288         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54289         212,
  54290         -1,
  54291     },
  54292 #endif /* chips */
  54293 
  54294 #if defined(BCM_56800_A0)
  54295     { /* SOC_REG_INT_GTMCA_BCM56800_A0r */
  54296         soc_block_list[9],
  54297         soc_portreg,
  54298         1,
  54299         0,
  54300         0x6f,
  54301         SOC_REG_FLAG_COUNTER,
  54302         0,
  54303         1,
  54304         soc_GR1023r_fields,
  54305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54307         153,
  54308         -1,
  54309     },
  54310 #endif /* chips */
  54311 
  54312 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  54313     { /* SOC_REG_INT_GTMCA_BCM56820_A0r */
  54314         soc_block_list[206],
  54315         soc_portreg,
  54316         1,
  54317         0,
  54318         0xab,
  54319         SOC_REG_FLAG_COUNTER,
  54320         0,
  54321         1,
  54322         soc_GR1023r_fields,
  54323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54324         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54325         223,
  54326         -1,
  54327     },
  54328 #endif /* chips */
  54329 
  54330 #if defined(BCM_88375_A0)
  54331     { /* SOC_REG_INT_GTMCA_BCM88375_A0r */
  54332         soc_block_list[2],
  54333         soc_portreg,
  54334         1,
  54335         0,
  54336         0x2c00,
  54337         SOC_REG_FLAG_COUNTER,
  54338         0,
  54339         1,
  54340         soc_GTMCA_BCM88375_A0r_fields,
  54341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54342         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54343         44,
  54344         -1,
  54345     },
  54346 #endif /* chips */
  54347 
  54348 #if defined(BCM_88375_B0)
  54349     { /* SOC_REG_INT_GTMCA_BCM88375_B0r */
  54350         soc_block_list[2],
  54351         soc_portreg,
  54352         1,
  54353         0,
  54354         0x2c00,
  54355         SOC_REG_FLAG_COUNTER,
  54356         0,
  54357         1,
  54358         soc_GTMCA_BCM88375_B0r_fields,
  54359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54360         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54361         44,
  54362         -1,
  54363     },
  54364 #endif /* chips */
  54365 
  54366 #if defined(BCM_88470_A0)
  54367     { /* SOC_REG_INT_GTMCA_BCM88470_A0r */
  54368         soc_block_list[2],
  54369         soc_portreg,
  54370         1,
  54371         0,
  54372         0x2c00,
  54373         SOC_REG_FLAG_COUNTER,
  54374         0,
  54375         1,
  54376         soc_GTMCA_BCM88470_A0r_fields,
  54377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54378         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54379         44,
  54380         -1,
  54381     },
  54382 #endif /* chips */
  54383 
  54384 #if defined(BCM_88470_B0)
  54385     { /* SOC_REG_INT_GTMCA_BCM88470_B0r */
  54386         soc_block_list[2],
  54387         soc_portreg,
  54388         1,
  54389         0,
  54390         0x2c00,
  54391         SOC_REG_FLAG_COUNTER,
  54392         0,
  54393         1,
  54394         soc_GTMCA_BCM88470_B0r_fields,
  54395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54396         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54397         44,
  54398         -1,
  54399     },
  54400 #endif /* chips */
  54401 
  54402 #if defined(BCM_88675_A0)
  54403     { /* SOC_REG_INT_GTMCA_BCM88675_A0r */
  54404         soc_block_list[2],
  54405         soc_portreg,
  54406         1,
  54407         0,
  54408         0x2c00,
  54409         SOC_REG_FLAG_COUNTER,
  54410         0,
  54411         1,
  54412         soc_GTMCAr_fields,
  54413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54414         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54415         44,
  54416         -1,
  54417     },
  54418 #endif /* chips */
  54419 
  54420 #if defined(BCM_88675_B0)
  54421     { /* SOC_REG_INT_GTMCA_BCM88675_B0r */
  54422         soc_block_list[2],
  54423         soc_portreg,
  54424         1,
  54425         0,
  54426         0x2c00,
  54427         SOC_REG_FLAG_COUNTER,
  54428         0,
  54429         1,
  54430         soc_GTMCA_BCM88675_B0r_fields,
  54431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54433         44,
  54434         -1,
  54435     },
  54436 #endif /* chips */
  54437 
  54438 #if defined(BCM_88680_A0)
  54439     { /* SOC_REG_INT_GTMCA_BCM88680_A0r */
  54440         soc_block_list[2],
  54441         soc_portreg,
  54442         1,
  54443         0,
  54444         0x2c00,
  54445         SOC_REG_FLAG_COUNTER,
  54446         0,
  54447         1,
  54448         soc_GTMCA_BCM88680_A0r_fields,
  54449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54451         44,
  54452         -1,
  54453     },
  54454 #endif /* chips */
  54455 
  54456 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  54457     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  54458     { /* SOC_REG_INT_GTMCLr */
  54459         soc_block_list[2],
  54460         soc_portreg,
  54461         1,
  54462         0,
  54463         0x32,
  54464         SOC_REG_FLAG_COUNTER |
  54465                           SOC_REG_FLAG_ED_CNTR,
  54466         0,
  54467         1,
  54468         soc_GR1023r_fields,
  54469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54470         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54471         84,
  54472         -1,
  54473     },
  54474 #endif /* chips */
  54475 
  54476 #if defined(BCM_53570_A0)
  54477     { /* SOC_REG_INT_GTMCLPr */
  54478         soc_block_list[2],
  54479         soc_portreg,
  54480         1,
  54481         0,
  54482         0x8d00,
  54483         SOC_REG_FLAG_COUNTER,
  54484         0,
  54485         1,
  54486         soc_GR1023_BCM53400_A0r_fields,
  54487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54488         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54489         295,
  54490         -1,
  54491     },
  54492 #endif /* chips */
  54493 
  54494 #if defined(BCM_53570_B0)
  54495     { /* SOC_REG_INT_GTMCLP_BCM53570_B0r */
  54496         soc_block_list[2],
  54497         soc_portreg,
  54498         1,
  54499         0,
  54500         0x8d00,
  54501         SOC_REG_FLAG_COUNTER,
  54502         0,
  54503         1,
  54504         soc_GR1023_BCM53400_A0r_fields,
  54505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54506         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54507         299,
  54508         -1,
  54509     },
  54510 #endif /* chips */
  54511 
  54512 #if defined(BCM_53400_A0)
  54513     { /* SOC_REG_INT_GTMCL_BCM53400_A0r */
  54514         soc_block_list[9],
  54515         soc_portreg,
  54516         1,
  54517         0,
  54518         0x2700,
  54519         SOC_REG_FLAG_COUNTER,
  54520         0,
  54521         1,
  54522         soc_GR1023_BCM53400_A0r_fields,
  54523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54524         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54525         138,
  54526         -1,
  54527     },
  54528 #endif /* chips */
  54529 
  54530 #if defined(BCM_53540_A0)
  54531     { /* SOC_REG_INT_GTMCL_BCM53540_A0r */
  54532         soc_block_list[2],
  54533         soc_portreg,
  54534         1,
  54535         0,
  54536         0x3800,
  54537         SOC_REG_FLAG_COUNTER,
  54538         0,
  54539         1,
  54540         soc_GR1023_BCM53400_A0r_fields,
  54541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54542         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54543         155,
  54544         -1,
  54545     },
  54546 #endif /* chips */
  54547 
  54548 #if defined(BCM_53570_A0)
  54549     { /* SOC_REG_INT_GTMCL_BCM53570_A0r */
  54550         soc_block_list[2],
  54551         soc_portreg,
  54552         1,
  54553         0,
  54554         0x3800,
  54555         SOC_REG_FLAG_COUNTER,
  54556         0,
  54557         1,
  54558         soc_GR1023_BCM53400_A0r_fields,
  54559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54560         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54561         210,
  54562         -1,
  54563     },
  54564 #endif /* chips */
  54565 
  54566 #if defined(BCM_53570_B0)
  54567     { /* SOC_REG_INT_GTMCL_BCM53570_B0r */
  54568         soc_block_list[2],
  54569         soc_portreg,
  54570         1,
  54571         0,
  54572         0x3800,
  54573         SOC_REG_FLAG_COUNTER,
  54574         0,
  54575         1,
  54576         soc_GR1023_BCM53400_A0r_fields,
  54577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54578         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54579         214,
  54580         -1,
  54581     },
  54582 #endif /* chips */
  54583 
  54584 #if defined(BCM_56142_A0)
  54585     { /* SOC_REG_INT_GTMCL_BCM56142_A0r */
  54586         soc_block_list[210],
  54587         soc_portreg,
  54588         1,
  54589         0,
  54590         0xa7,
  54591         SOC_REG_FLAG_COUNTER,
  54592         0,
  54593         1,
  54594         soc_GR1023r_fields,
  54595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54596         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54597         214,
  54598         -1,
  54599     },
  54600 #endif /* chips */
  54601 
  54602 #if defined(BCM_56150_A0)
  54603     { /* SOC_REG_INT_GTMCL_BCM56150_A0r */
  54604         soc_block_list[2],
  54605         soc_portreg,
  54606         1,
  54607         0,
  54608         0x2700,
  54609         SOC_REG_FLAG_COUNTER,
  54610         0,
  54611         1,
  54612         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  54613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54614         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54615         134,
  54616         -1,
  54617     },
  54618 #endif /* chips */
  54619 
  54620 #if defined(BCM_56160_A0)
  54621     { /* SOC_REG_INT_GTMCL_BCM56160_A0r */
  54622         soc_block_list[2],
  54623         soc_portreg,
  54624         1,
  54625         0,
  54626         0x3800,
  54627         SOC_REG_FLAG_COUNTER,
  54628         0,
  54629         1,
  54630         soc_GR1023_BCM53400_A0r_fields,
  54631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54632         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54633         155,
  54634         -1,
  54635     },
  54636 #endif /* chips */
  54637 
  54638 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  54639     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  54640     { /* SOC_REG_INT_GTMCL_BCM56224_A0r */
  54641         soc_block_list[2],
  54642         soc_portreg,
  54643         1,
  54644         0,
  54645         0x27,
  54646         SOC_REG_FLAG_COUNTER,
  54647         0,
  54648         1,
  54649         soc_GR1023r_fields,
  54650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54652         73,
  54653         -1,
  54654     },
  54655 #endif /* chips */
  54656 
  54657 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  54658     { /* SOC_REG_INT_GTMCL_BCM56334_A0r */
  54659         soc_block_list[210],
  54660         soc_portreg,
  54661         1,
  54662         0,
  54663         0xa7,
  54664         SOC_REG_FLAG_COUNTER,
  54665         0,
  54666         1,
  54667         soc_GR1023r_fields,
  54668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54670         209,
  54671         -1,
  54672     },
  54673 #endif /* chips */
  54674 
  54675 #if defined(BCM_56370_A0)
  54676     { /* SOC_REG_INT_GTMCL_BCM56370_A0r */
  54677         soc_block_list[9],
  54678         soc_portreg,
  54679         1,
  54680         0,
  54681         0x2800,
  54682         SOC_REG_FLAG_COUNTER,
  54683         0,
  54684         1,
  54685         soc_GR1023_BCM53400_A0r_fields,
  54686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54687         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54688         100,
  54689         -1,
  54690         3,
  54691     },
  54692 #endif /* chips */
  54693 
  54694 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  54695     { /* SOC_REG_INT_GTMCL_BCM56440_A0r */
  54696         soc_block_list[2],
  54697         soc_portreg,
  54698         1,
  54699         0,
  54700         0xa8,
  54701         SOC_REG_FLAG_COUNTER,
  54702         0,
  54703         1,
  54704         soc_GR1023r_fields,
  54705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54706         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54707         207,
  54708         -1,
  54709     },
  54710 #endif /* chips */
  54711 
  54712 #if defined(BCM_56514_A0)
  54713     { /* SOC_REG_INT_GTMCL_BCM56514_A0r */
  54714         soc_block_list[2],
  54715         soc_portreg,
  54716         1,
  54717         0,
  54718         0x34,
  54719         SOC_REG_FLAG_COUNTER,
  54720         0,
  54721         1,
  54722         soc_GR1023r_fields,
  54723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54724         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54725         86,
  54726         -1,
  54727     },
  54728 #endif /* chips */
  54729 
  54730 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  54731     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  54732     { /* SOC_REG_INT_GTMCL_BCM56624_A0r */
  54733         soc_block_list[205],
  54734         soc_portreg,
  54735         1,
  54736         0,
  54737         0xb4,
  54738         SOC_REG_FLAG_COUNTER,
  54739         0,
  54740         1,
  54741         soc_GR1023r_fields,
  54742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54744         222,
  54745         -1,
  54746     },
  54747 #endif /* chips */
  54748 
  54749 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  54750     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  54751     { /* SOC_REG_INT_GTMCL_BCM56634_A0r */
  54752         soc_block_list[207],
  54753         soc_portreg,
  54754         1,
  54755         0,
  54756         0xb4,
  54757         SOC_REG_FLAG_COUNTER,
  54758         0,
  54759         1,
  54760         soc_GR1023r_fields,
  54761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54763         222,
  54764         -1,
  54765     },
  54766 #endif /* chips */
  54767 
  54768 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  54769     { /* SOC_REG_INT_GTMCL_BCM56685_A0r */
  54770         soc_block_list[209],
  54771         soc_portreg,
  54772         1,
  54773         0,
  54774         0xb4,
  54775         SOC_REG_FLAG_COUNTER,
  54776         0,
  54777         1,
  54778         soc_GR1023r_fields,
  54779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54781         222,
  54782         -1,
  54783     },
  54784 #endif /* chips */
  54785 
  54786 #if defined(BCM_56800_A0)
  54787     { /* SOC_REG_INT_GTMCL_BCM56800_A0r */
  54788         soc_block_list[9],
  54789         soc_portreg,
  54790         1,
  54791         0,
  54792         0x79,
  54793         SOC_REG_FLAG_COUNTER,
  54794         0,
  54795         1,
  54796         soc_GR1023r_fields,
  54797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54798         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54799         163,
  54800         -1,
  54801     },
  54802 #endif /* chips */
  54803 
  54804 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  54805     { /* SOC_REG_INT_GTMCL_BCM56820_A0r */
  54806         soc_block_list[206],
  54807         soc_portreg,
  54808         1,
  54809         0,
  54810         0xb5,
  54811         SOC_REG_FLAG_COUNTER,
  54812         0,
  54813         1,
  54814         soc_GR1023r_fields,
  54815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54816         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54817         233,
  54818         -1,
  54819     },
  54820 #endif /* chips */
  54821 
  54822 #if defined(BCM_88375_A0)
  54823     { /* SOC_REG_INT_GTMCL_BCM88375_A0r */
  54824         soc_block_list[2],
  54825         soc_portreg,
  54826         1,
  54827         0,
  54828         0x2700,
  54829         SOC_REG_FLAG_COUNTER,
  54830         0,
  54831         1,
  54832         soc_GTMCL_BCM88375_A0r_fields,
  54833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54834         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54835         39,
  54836         -1,
  54837     },
  54838 #endif /* chips */
  54839 
  54840 #if defined(BCM_88375_B0)
  54841     { /* SOC_REG_INT_GTMCL_BCM88375_B0r */
  54842         soc_block_list[2],
  54843         soc_portreg,
  54844         1,
  54845         0,
  54846         0x2700,
  54847         SOC_REG_FLAG_COUNTER,
  54848         0,
  54849         1,
  54850         soc_GTMCL_BCM88375_B0r_fields,
  54851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54852         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54853         39,
  54854         -1,
  54855     },
  54856 #endif /* chips */
  54857 
  54858 #if defined(BCM_88470_A0)
  54859     { /* SOC_REG_INT_GTMCL_BCM88470_A0r */
  54860         soc_block_list[2],
  54861         soc_portreg,
  54862         1,
  54863         0,
  54864         0x2700,
  54865         SOC_REG_FLAG_COUNTER,
  54866         0,
  54867         1,
  54868         soc_GTMCL_BCM88470_A0r_fields,
  54869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54871         39,
  54872         -1,
  54873     },
  54874 #endif /* chips */
  54875 
  54876 #if defined(BCM_88470_B0)
  54877     { /* SOC_REG_INT_GTMCL_BCM88470_B0r */
  54878         soc_block_list[2],
  54879         soc_portreg,
  54880         1,
  54881         0,
  54882         0x2700,
  54883         SOC_REG_FLAG_COUNTER,
  54884         0,
  54885         1,
  54886         soc_GTMCL_BCM88470_B0r_fields,
  54887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54889         39,
  54890         -1,
  54891     },
  54892 #endif /* chips */
  54893 
  54894 #if defined(BCM_88675_A0)
  54895     { /* SOC_REG_INT_GTMCL_BCM88675_A0r */
  54896         soc_block_list[2],
  54897         soc_portreg,
  54898         1,
  54899         0,
  54900         0x2700,
  54901         SOC_REG_FLAG_COUNTER,
  54902         0,
  54903         1,
  54904         soc_GTMCLr_fields,
  54905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54907         39,
  54908         -1,
  54909     },
  54910 #endif /* chips */
  54911 
  54912 #if defined(BCM_88675_B0)
  54913     { /* SOC_REG_INT_GTMCL_BCM88675_B0r */
  54914         soc_block_list[2],
  54915         soc_portreg,
  54916         1,
  54917         0,
  54918         0x2700,
  54919         SOC_REG_FLAG_COUNTER,
  54920         0,
  54921         1,
  54922         soc_GTMCL_BCM88675_B0r_fields,
  54923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54925         39,
  54926         -1,
  54927     },
  54928 #endif /* chips */
  54929 
  54930 #if defined(BCM_88680_A0)
  54931     { /* SOC_REG_INT_GTMCL_BCM88680_A0r */
  54932         soc_block_list[2],
  54933         soc_portreg,
  54934         1,
  54935         0,
  54936         0x2700,
  54937         SOC_REG_FLAG_COUNTER,
  54938         0,
  54939         1,
  54940         soc_GTMCL_BCM88680_A0r_fields,
  54941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54943         39,
  54944         -1,
  54945     },
  54946 #endif /* chips */
  54947 
  54948 #if defined(BCM_53570_A0)
  54949     { /* SOC_REG_INT_GTMFAEPr */
  54950         soc_block_list[2],
  54951         soc_portreg,
  54952         1,
  54953         0,
  54954         0xa500,
  54955         SOC_REG_FLAG_COUNTER,
  54956         0,
  54957         1,
  54958         soc_GR1023_BCM53400_A0r_fields,
  54959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54960         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54961         319,
  54962         -1,
  54963     },
  54964 #endif /* chips */
  54965 
  54966 #if defined(BCM_53570_B0)
  54967     { /* SOC_REG_INT_GTMFAEP_BCM53570_B0r */
  54968         soc_block_list[2],
  54969         soc_portreg,
  54970         1,
  54971         0,
  54972         0xa500,
  54973         SOC_REG_FLAG_COUNTER,
  54974         0,
  54975         1,
  54976         soc_GR1023_BCM53400_A0r_fields,
  54977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54978         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54979         323,
  54980         -1,
  54981     },
  54982 #endif /* chips */
  54983 
  54984 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  54985     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  54986     { /* SOC_REG_INT_GTMGVr */
  54987         soc_block_list[2],
  54988         soc_portreg,
  54989         1,
  54990         0,
  54991         0x23,
  54992         SOC_REG_FLAG_COUNTER,
  54993         0,
  54994         1,
  54995         soc_GR1023r_fields,
  54996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54997         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54998         69,
  54999         -1,
  55000     },
  55001 #endif /* chips */
  55002 
  55003 #if defined(BCM_53570_A0)
  55004     { /* SOC_REG_INT_GTMGVPr */
  55005         soc_block_list[2],
  55006         soc_portreg,
  55007         1,
  55008         0,
  55009         0x9a00,
  55010         SOC_REG_FLAG_COUNTER,
  55011         0,
  55012         1,
  55013         soc_GR1023_BCM53400_A0r_fields,
  55014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55015         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55016         308,
  55017         -1,
  55018     },
  55019 #endif /* chips */
  55020 
  55021 #if defined(BCM_53570_B0)
  55022     { /* SOC_REG_INT_GTMGVP_BCM53570_B0r */
  55023         soc_block_list[2],
  55024         soc_portreg,
  55025         1,
  55026         0,
  55027         0x9a00,
  55028         SOC_REG_FLAG_COUNTER,
  55029         0,
  55030         1,
  55031         soc_GR1023_BCM53400_A0r_fields,
  55032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55034         312,
  55035         -1,
  55036     },
  55037 #endif /* chips */
  55038 
  55039 #if defined(BCM_53400_A0)
  55040     { /* SOC_REG_INT_GTMGV_BCM53400_A0r */
  55041         soc_block_list[9],
  55042         soc_portreg,
  55043         1,
  55044         0,
  55045         0x3400,
  55046         SOC_REG_FLAG_COUNTER,
  55047         0,
  55048         1,
  55049         soc_GR1023_BCM53400_A0r_fields,
  55050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55052         151,
  55053         -1,
  55054     },
  55055 #endif /* chips */
  55056 
  55057 #if defined(BCM_53540_A0)
  55058     { /* SOC_REG_INT_GTMGV_BCM53540_A0r */
  55059         soc_block_list[2],
  55060         soc_portreg,
  55061         1,
  55062         0,
  55063         0x4500,
  55064         SOC_REG_FLAG_COUNTER,
  55065         0,
  55066         1,
  55067         soc_GR1023_BCM53400_A0r_fields,
  55068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55070         168,
  55071         -1,
  55072     },
  55073 #endif /* chips */
  55074 
  55075 #if defined(BCM_53570_A0)
  55076     { /* SOC_REG_INT_GTMGV_BCM53570_A0r */
  55077         soc_block_list[2],
  55078         soc_portreg,
  55079         1,
  55080         0,
  55081         0x4500,
  55082         SOC_REG_FLAG_COUNTER,
  55083         0,
  55084         1,
  55085         soc_GR1023_BCM53400_A0r_fields,
  55086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55088         223,
  55089         -1,
  55090     },
  55091 #endif /* chips */
  55092 
  55093 #if defined(BCM_53570_B0)
  55094     { /* SOC_REG_INT_GTMGV_BCM53570_B0r */
  55095         soc_block_list[2],
  55096         soc_portreg,
  55097         1,
  55098         0,
  55099         0x4500,
  55100         SOC_REG_FLAG_COUNTER,
  55101         0,
  55102         1,
  55103         soc_GR1023_BCM53400_A0r_fields,
  55104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55105         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55106         227,
  55107         -1,
  55108     },
  55109 #endif /* chips */
  55110 
  55111 #if defined(BCM_56142_A0)
  55112     { /* SOC_REG_INT_GTMGV_BCM56142_A0r */
  55113         soc_block_list[210],
  55114         soc_portreg,
  55115         1,
  55116         0,
  55117         0xb4,
  55118         SOC_REG_FLAG_COUNTER,
  55119         0,
  55120         1,
  55121         soc_GR1023r_fields,
  55122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55124         227,
  55125         -1,
  55126     },
  55127 #endif /* chips */
  55128 
  55129 #if defined(BCM_56150_A0)
  55130     { /* SOC_REG_INT_GTMGV_BCM56150_A0r */
  55131         soc_block_list[2],
  55132         soc_portreg,
  55133         1,
  55134         0,
  55135         0x3400,
  55136         SOC_REG_FLAG_COUNTER,
  55137         0,
  55138         1,
  55139         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  55140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55142         147,
  55143         -1,
  55144     },
  55145 #endif /* chips */
  55146 
  55147 #if defined(BCM_56160_A0)
  55148     { /* SOC_REG_INT_GTMGV_BCM56160_A0r */
  55149         soc_block_list[2],
  55150         soc_portreg,
  55151         1,
  55152         0,
  55153         0x4500,
  55154         SOC_REG_FLAG_COUNTER,
  55155         0,
  55156         1,
  55157         soc_GR1023_BCM53400_A0r_fields,
  55158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55160         168,
  55161         -1,
  55162     },
  55163 #endif /* chips */
  55164 
  55165 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  55166     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  55167     { /* SOC_REG_INT_GTMGV_BCM56224_A0r */
  55168         soc_block_list[2],
  55169         soc_portreg,
  55170         1,
  55171         0,
  55172         0x34,
  55173         SOC_REG_FLAG_COUNTER,
  55174         0,
  55175         1,
  55176         soc_GR1023r_fields,
  55177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55178         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55179         86,
  55180         -1,
  55181     },
  55182 #endif /* chips */
  55183 
  55184 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  55185     { /* SOC_REG_INT_GTMGV_BCM56334_A0r */
  55186         soc_block_list[210],
  55187         soc_portreg,
  55188         1,
  55189         0,
  55190         0xb4,
  55191         SOC_REG_FLAG_COUNTER,
  55192         0,
  55193         1,
  55194         soc_GR1023r_fields,
  55195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55196         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55197         222,
  55198         -1,
  55199     },
  55200 #endif /* chips */
  55201 
  55202 #if defined(BCM_56370_A0)
  55203     { /* SOC_REG_INT_GTMGV_BCM56370_A0r */
  55204         soc_block_list[9],
  55205         soc_portreg,
  55206         1,
  55207         0,
  55208         0x3500,
  55209         SOC_REG_FLAG_COUNTER,
  55210         0,
  55211         1,
  55212         soc_GR1023_BCM53400_A0r_fields,
  55213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55214         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55215         113,
  55216         -1,
  55217         3,
  55218     },
  55219 #endif /* chips */
  55220 
  55221 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  55222     { /* SOC_REG_INT_GTMGV_BCM56440_A0r */
  55223         soc_block_list[2],
  55224         soc_portreg,
  55225         1,
  55226         0,
  55227         0xb5,
  55228         SOC_REG_FLAG_COUNTER,
  55229         0,
  55230         1,
  55231         soc_GR1023r_fields,
  55232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55233         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55234         220,
  55235         -1,
  55236     },
  55237 #endif /* chips */
  55238 
  55239 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  55240     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  55241     { /* SOC_REG_INT_GTMGV_BCM56624_A0r */
  55242         soc_block_list[205],
  55243         soc_portreg,
  55244         1,
  55245         0,
  55246         0xa5,
  55247         SOC_REG_FLAG_COUNTER,
  55248         0,
  55249         1,
  55250         soc_GR1023r_fields,
  55251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55252         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55253         207,
  55254         -1,
  55255     },
  55256 #endif /* chips */
  55257 
  55258 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  55259     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  55260     { /* SOC_REG_INT_GTMGV_BCM56634_A0r */
  55261         soc_block_list[207],
  55262         soc_portreg,
  55263         1,
  55264         0,
  55265         0xa5,
  55266         SOC_REG_FLAG_COUNTER,
  55267         0,
  55268         1,
  55269         soc_GR1023r_fields,
  55270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55272         207,
  55273         -1,
  55274     },
  55275 #endif /* chips */
  55276 
  55277 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  55278     { /* SOC_REG_INT_GTMGV_BCM56685_A0r */
  55279         soc_block_list[209],
  55280         soc_portreg,
  55281         1,
  55282         0,
  55283         0xa5,
  55284         SOC_REG_FLAG_COUNTER,
  55285         0,
  55286         1,
  55287         soc_GR1023r_fields,
  55288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55289         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55290         207,
  55291         -1,
  55292     },
  55293 #endif /* chips */
  55294 
  55295 #if defined(BCM_56800_A0)
  55296     { /* SOC_REG_INT_GTMGV_BCM56800_A0r */
  55297         soc_block_list[9],
  55298         soc_portreg,
  55299         1,
  55300         0,
  55301         0x6a,
  55302         SOC_REG_FLAG_COUNTER,
  55303         0,
  55304         1,
  55305         soc_GR1023r_fields,
  55306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55308         148,
  55309         -1,
  55310     },
  55311 #endif /* chips */
  55312 
  55313 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  55314     { /* SOC_REG_INT_GTMGV_BCM56820_A0r */
  55315         soc_block_list[206],
  55316         soc_portreg,
  55317         1,
  55318         0,
  55319         0xa6,
  55320         SOC_REG_FLAG_COUNTER,
  55321         0,
  55322         1,
  55323         soc_GR1023r_fields,
  55324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55326         218,
  55327         -1,
  55328     },
  55329 #endif /* chips */
  55330 
  55331 #if defined(BCM_88375_A0)
  55332     { /* SOC_REG_INT_GTMGV_BCM88375_A0r */
  55333         soc_block_list[2],
  55334         soc_portreg,
  55335         1,
  55336         0,
  55337         0x3400,
  55338         SOC_REG_FLAG_COUNTER,
  55339         0,
  55340         1,
  55341         soc_GTMGV_BCM88375_A0r_fields,
  55342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55344         52,
  55345         -1,
  55346     },
  55347 #endif /* chips */
  55348 
  55349 #if defined(BCM_88375_B0)
  55350     { /* SOC_REG_INT_GTMGV_BCM88375_B0r */
  55351         soc_block_list[2],
  55352         soc_portreg,
  55353         1,
  55354         0,
  55355         0x3400,
  55356         SOC_REG_FLAG_COUNTER,
  55357         0,
  55358         1,
  55359         soc_GTMGV_BCM88375_B0r_fields,
  55360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55361         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55362         52,
  55363         -1,
  55364     },
  55365 #endif /* chips */
  55366 
  55367 #if defined(BCM_88470_A0)
  55368     { /* SOC_REG_INT_GTMGV_BCM88470_A0r */
  55369         soc_block_list[2],
  55370         soc_portreg,
  55371         1,
  55372         0,
  55373         0x3400,
  55374         SOC_REG_FLAG_COUNTER,
  55375         0,
  55376         1,
  55377         soc_GTMGV_BCM88470_A0r_fields,
  55378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55379         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55380         52,
  55381         -1,
  55382     },
  55383 #endif /* chips */
  55384 
  55385 #if defined(BCM_88470_B0)
  55386     { /* SOC_REG_INT_GTMGV_BCM88470_B0r */
  55387         soc_block_list[2],
  55388         soc_portreg,
  55389         1,
  55390         0,
  55391         0x3400,
  55392         SOC_REG_FLAG_COUNTER,
  55393         0,
  55394         1,
  55395         soc_GTMGV_BCM88470_B0r_fields,
  55396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55398         52,
  55399         -1,
  55400     },
  55401 #endif /* chips */
  55402 
  55403 #if defined(BCM_88675_A0)
  55404     { /* SOC_REG_INT_GTMGV_BCM88675_A0r */
  55405         soc_block_list[2],
  55406         soc_portreg,
  55407         1,
  55408         0,
  55409         0x3400,
  55410         SOC_REG_FLAG_COUNTER,
  55411         0,
  55412         1,
  55413         soc_GTMGVr_fields,
  55414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55416         52,
  55417         -1,
  55418     },
  55419 #endif /* chips */
  55420 
  55421 #if defined(BCM_88675_B0)
  55422     { /* SOC_REG_INT_GTMGV_BCM88675_B0r */
  55423         soc_block_list[2],
  55424         soc_portreg,
  55425         1,
  55426         0,
  55427         0x3400,
  55428         SOC_REG_FLAG_COUNTER,
  55429         0,
  55430         1,
  55431         soc_GTMGV_BCM88675_B0r_fields,
  55432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55433         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55434         52,
  55435         -1,
  55436     },
  55437 #endif /* chips */
  55438 
  55439 #if defined(BCM_88680_A0)
  55440     { /* SOC_REG_INT_GTMGV_BCM88680_A0r */
  55441         soc_block_list[2],
  55442         soc_portreg,
  55443         1,
  55444         0,
  55445         0x3400,
  55446         SOC_REG_FLAG_COUNTER,
  55447         0,
  55448         1,
  55449         soc_GTMGV_BCM88680_A0r_fields,
  55450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55451         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55452         52,
  55453         -1,
  55454     },
  55455 #endif /* chips */
  55456 
  55457 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  55458     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  55459     { /* SOC_REG_INT_GTNCLr */
  55460         soc_block_list[2],
  55461         soc_portreg,
  55462         1,
  55463         0,
  55464         0x36,
  55465         SOC_REG_FLAG_COUNTER |
  55466                           SOC_REG_FLAG_ED_CNTR,
  55467         0,
  55468         1,
  55469         soc_GR1023r_fields,
  55470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55472         88,
  55473         -1,
  55474     },
  55475 #endif /* chips */
  55476 
  55477 #if defined(BCM_53570_A0)
  55478     { /* SOC_REG_INT_GTNCLPr */
  55479         soc_block_list[2],
  55480         soc_portreg,
  55481         1,
  55482         0,
  55483         0x9100,
  55484         SOC_REG_FLAG_COUNTER,
  55485         0,
  55486         1,
  55487         soc_GR1023_BCM53400_A0r_fields,
  55488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55490         299,
  55491         -1,
  55492     },
  55493 #endif /* chips */
  55494 
  55495 #if defined(BCM_53570_B0)
  55496     { /* SOC_REG_INT_GTNCLP_BCM53570_B0r */
  55497         soc_block_list[2],
  55498         soc_portreg,
  55499         1,
  55500         0,
  55501         0x9100,
  55502         SOC_REG_FLAG_COUNTER,
  55503         0,
  55504         1,
  55505         soc_GR1023_BCM53400_A0r_fields,
  55506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55508         303,
  55509         -1,
  55510     },
  55511 #endif /* chips */
  55512 
  55513 #if defined(BCM_53400_A0)
  55514     { /* SOC_REG_INT_GTNCL_BCM53400_A0r */
  55515         soc_block_list[9],
  55516         soc_portreg,
  55517         1,
  55518         0,
  55519         0x2b00,
  55520         SOC_REG_FLAG_COUNTER,
  55521         0,
  55522         1,
  55523         soc_GR1023_BCM53400_A0r_fields,
  55524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55525         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55526         142,
  55527         -1,
  55528     },
  55529 #endif /* chips */
  55530 
  55531 #if defined(BCM_53540_A0)
  55532     { /* SOC_REG_INT_GTNCL_BCM53540_A0r */
  55533         soc_block_list[2],
  55534         soc_portreg,
  55535         1,
  55536         0,
  55537         0x3c00,
  55538         SOC_REG_FLAG_COUNTER,
  55539         0,
  55540         1,
  55541         soc_GR1023_BCM53400_A0r_fields,
  55542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55544         159,
  55545         -1,
  55546     },
  55547 #endif /* chips */
  55548 
  55549 #if defined(BCM_53570_A0)
  55550     { /* SOC_REG_INT_GTNCL_BCM53570_A0r */
  55551         soc_block_list[2],
  55552         soc_portreg,
  55553         1,
  55554         0,
  55555         0x3c00,
  55556         SOC_REG_FLAG_COUNTER,
  55557         0,
  55558         1,
  55559         soc_GR1023_BCM53400_A0r_fields,
  55560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55562         214,
  55563         -1,
  55564     },
  55565 #endif /* chips */
  55566 
  55567 #if defined(BCM_53570_B0)
  55568     { /* SOC_REG_INT_GTNCL_BCM53570_B0r */
  55569         soc_block_list[2],
  55570         soc_portreg,
  55571         1,
  55572         0,
  55573         0x3c00,
  55574         SOC_REG_FLAG_COUNTER,
  55575         0,
  55576         1,
  55577         soc_GR1023_BCM53400_A0r_fields,
  55578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55580         218,
  55581         -1,
  55582     },
  55583 #endif /* chips */
  55584 
  55585 #if defined(BCM_56142_A0)
  55586     { /* SOC_REG_INT_GTNCL_BCM56142_A0r */
  55587         soc_block_list[210],
  55588         soc_portreg,
  55589         1,
  55590         0,
  55591         0xab,
  55592         SOC_REG_FLAG_COUNTER,
  55593         0,
  55594         1,
  55595         soc_GR1023r_fields,
  55596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55598         218,
  55599         -1,
  55600     },
  55601 #endif /* chips */
  55602 
  55603 #if defined(BCM_56150_A0)
  55604     { /* SOC_REG_INT_GTNCL_BCM56150_A0r */
  55605         soc_block_list[2],
  55606         soc_portreg,
  55607         1,
  55608         0,
  55609         0x2b00,
  55610         SOC_REG_FLAG_COUNTER,
  55611         0,
  55612         1,
  55613         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  55614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55616         138,
  55617         -1,
  55618     },
  55619 #endif /* chips */
  55620 
  55621 #if defined(BCM_56160_A0)
  55622     { /* SOC_REG_INT_GTNCL_BCM56160_A0r */
  55623         soc_block_list[2],
  55624         soc_portreg,
  55625         1,
  55626         0,
  55627         0x3c00,
  55628         SOC_REG_FLAG_COUNTER,
  55629         0,
  55630         1,
  55631         soc_GR1023_BCM53400_A0r_fields,
  55632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55634         159,
  55635         -1,
  55636     },
  55637 #endif /* chips */
  55638 
  55639 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  55640     { /* SOC_REG_INT_GTNCL_BCM56334_A0r */
  55641         soc_block_list[210],
  55642         soc_portreg,
  55643         1,
  55644         0,
  55645         0xab,
  55646         SOC_REG_FLAG_COUNTER,
  55647         0,
  55648         1,
  55649         soc_GR1023r_fields,
  55650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55652         213,
  55653         -1,
  55654     },
  55655 #endif /* chips */
  55656 
  55657 #if defined(BCM_56370_A0)
  55658     { /* SOC_REG_INT_GTNCL_BCM56370_A0r */
  55659         soc_block_list[9],
  55660         soc_portreg,
  55661         1,
  55662         0,
  55663         0x2c00,
  55664         SOC_REG_FLAG_COUNTER,
  55665         0,
  55666         1,
  55667         soc_GR1023_BCM53400_A0r_fields,
  55668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55670         104,
  55671         -1,
  55672         3,
  55673     },
  55674 #endif /* chips */
  55675 
  55676 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  55677     { /* SOC_REG_INT_GTNCL_BCM56440_A0r */
  55678         soc_block_list[2],
  55679         soc_portreg,
  55680         1,
  55681         0,
  55682         0xac,
  55683         SOC_REG_FLAG_COUNTER,
  55684         0,
  55685         1,
  55686         soc_GR1023r_fields,
  55687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55688         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55689         211,
  55690         -1,
  55691     },
  55692 #endif /* chips */
  55693 
  55694 #if defined(BCM_56514_A0)
  55695     { /* SOC_REG_INT_GTNCL_BCM56514_A0r */
  55696         soc_block_list[2],
  55697         soc_portreg,
  55698         1,
  55699         0,
  55700         0x38,
  55701         SOC_REG_FLAG_COUNTER,
  55702         0,
  55703         1,
  55704         soc_GR1023r_fields,
  55705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55706         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55707         90,
  55708         -1,
  55709     },
  55710 #endif /* chips */
  55711 
  55712 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  55713     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  55714     { /* SOC_REG_INT_GTNCL_BCM56624_A0r */
  55715         soc_block_list[205],
  55716         soc_portreg,
  55717         1,
  55718         0,
  55719         0xb8,
  55720         SOC_REG_FLAG_COUNTER,
  55721         0,
  55722         1,
  55723         soc_GR1023r_fields,
  55724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55725         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55726         226,
  55727         -1,
  55728     },
  55729 #endif /* chips */
  55730 
  55731 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  55732     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  55733     { /* SOC_REG_INT_GTNCL_BCM56634_A0r */
  55734         soc_block_list[207],
  55735         soc_portreg,
  55736         1,
  55737         0,
  55738         0xb8,
  55739         SOC_REG_FLAG_COUNTER,
  55740         0,
  55741         1,
  55742         soc_GR1023r_fields,
  55743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55744         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55745         226,
  55746         -1,
  55747     },
  55748 #endif /* chips */
  55749 
  55750 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  55751     { /* SOC_REG_INT_GTNCL_BCM56685_A0r */
  55752         soc_block_list[209],
  55753         soc_portreg,
  55754         1,
  55755         0,
  55756         0xb8,
  55757         SOC_REG_FLAG_COUNTER,
  55758         0,
  55759         1,
  55760         soc_GR1023r_fields,
  55761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55763         226,
  55764         -1,
  55765     },
  55766 #endif /* chips */
  55767 
  55768 #if defined(BCM_56800_A0)
  55769     { /* SOC_REG_INT_GTNCL_BCM56800_A0r */
  55770         soc_block_list[9],
  55771         soc_portreg,
  55772         1,
  55773         0,
  55774         0x7d,
  55775         SOC_REG_FLAG_COUNTER,
  55776         0,
  55777         1,
  55778         soc_GR1023r_fields,
  55779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55781         167,
  55782         -1,
  55783     },
  55784 #endif /* chips */
  55785 
  55786 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  55787     { /* SOC_REG_INT_GTNCL_BCM56820_A0r */
  55788         soc_block_list[206],
  55789         soc_portreg,
  55790         1,
  55791         0,
  55792         0xb9,
  55793         SOC_REG_FLAG_COUNTER,
  55794         0,
  55795         1,
  55796         soc_GR1023r_fields,
  55797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55798         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55799         237,
  55800         -1,
  55801     },
  55802 #endif /* chips */
  55803 
  55804 #if defined(BCM_88375_A0)
  55805     { /* SOC_REG_INT_GTNCL_BCM88375_A0r */
  55806         soc_block_list[2],
  55807         soc_portreg,
  55808         1,
  55809         0,
  55810         0x2b00,
  55811         SOC_REG_FLAG_COUNTER,
  55812         0,
  55813         1,
  55814         soc_GTNCL_BCM88375_A0r_fields,
  55815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55816         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55817         43,
  55818         -1,
  55819     },
  55820 #endif /* chips */
  55821 
  55822 #if defined(BCM_88375_B0)
  55823     { /* SOC_REG_INT_GTNCL_BCM88375_B0r */
  55824         soc_block_list[2],
  55825         soc_portreg,
  55826         1,
  55827         0,
  55828         0x2b00,
  55829         SOC_REG_FLAG_COUNTER,
  55830         0,
  55831         1,
  55832         soc_GTNCL_BCM88375_B0r_fields,
  55833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55834         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55835         43,
  55836         -1,
  55837     },
  55838 #endif /* chips */
  55839 
  55840 #if defined(BCM_88470_A0)
  55841     { /* SOC_REG_INT_GTNCL_BCM88470_A0r */
  55842         soc_block_list[2],
  55843         soc_portreg,
  55844         1,
  55845         0,
  55846         0x2b00,
  55847         SOC_REG_FLAG_COUNTER,
  55848         0,
  55849         1,
  55850         soc_GTNCL_BCM88470_A0r_fields,
  55851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55852         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55853         43,
  55854         -1,
  55855     },
  55856 #endif /* chips */
  55857 
  55858 #if defined(BCM_88470_B0)
  55859     { /* SOC_REG_INT_GTNCL_BCM88470_B0r */
  55860         soc_block_list[2],
  55861         soc_portreg,
  55862         1,
  55863         0,
  55864         0x2b00,
  55865         SOC_REG_FLAG_COUNTER,
  55866         0,
  55867         1,
  55868         soc_GTNCL_BCM88470_B0r_fields,
  55869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55871         43,
  55872         -1,
  55873     },
  55874 #endif /* chips */
  55875 
  55876 #if defined(BCM_88675_A0)
  55877     { /* SOC_REG_INT_GTNCL_BCM88675_A0r */
  55878         soc_block_list[2],
  55879         soc_portreg,
  55880         1,
  55881         0,
  55882         0x2b00,
  55883         SOC_REG_FLAG_COUNTER,
  55884         0,
  55885         1,
  55886         soc_GTNCLr_fields,
  55887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55889         43,
  55890         -1,
  55891     },
  55892 #endif /* chips */
  55893 
  55894 #if defined(BCM_88675_B0)
  55895     { /* SOC_REG_INT_GTNCL_BCM88675_B0r */
  55896         soc_block_list[2],
  55897         soc_portreg,
  55898         1,
  55899         0,
  55900         0x2b00,
  55901         SOC_REG_FLAG_COUNTER,
  55902         0,
  55903         1,
  55904         soc_GTNCL_BCM88675_B0r_fields,
  55905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55907         43,
  55908         -1,
  55909     },
  55910 #endif /* chips */
  55911 
  55912 #if defined(BCM_88680_A0)
  55913     { /* SOC_REG_INT_GTNCL_BCM88680_A0r */
  55914         soc_block_list[2],
  55915         soc_portreg,
  55916         1,
  55917         0,
  55918         0x2b00,
  55919         SOC_REG_FLAG_COUNTER,
  55920         0,
  55921         1,
  55922         soc_GTNCL_BCM88680_A0r_fields,
  55923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  55925         43,
  55926         -1,
  55927     },
  55928 #endif /* chips */
  55929 
  55930 #if defined(BCM_53570_A0)
  55931     { /* SOC_REG_INT_GTNFFPr */
  55932         soc_block_list[2],
  55933         soc_portreg,
  55934         1,
  55935         0,
  55936         0xa200,
  55937         SOC_REG_FLAG_COUNTER,
  55938         0,
  55939         1,
  55940         soc_GR1023_BCM53400_A0r_fields,
  55941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55942         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55943         316,
  55944         -1,
  55945     },
  55946 #endif /* chips */
  55947 
  55948 #if defined(BCM_53570_B0)
  55949     { /* SOC_REG_INT_GTNFFP_BCM53570_B0r */
  55950         soc_block_list[2],
  55951         soc_portreg,
  55952         1,
  55953         0,
  55954         0xa200,
  55955         SOC_REG_FLAG_COUNTER,
  55956         0,
  55957         1,
  55958         soc_GR1023_BCM53400_A0r_fields,
  55959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55960         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55961         320,
  55962         -1,
  55963     },
  55964 #endif /* chips */
  55965 
  55966 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  55967     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  55968     { /* SOC_REG_INT_GTOVRr */
  55969         soc_block_list[2],
  55970         soc_portreg,
  55971         1,
  55972         0,
  55973         0x2e,
  55974         SOC_REG_FLAG_COUNTER |
  55975                           SOC_REG_FLAG_ED_CNTR,
  55976         0,
  55977         1,
  55978         soc_GR1023r_fields,
  55979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55980         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  55981         80,
  55982         -1,
  55983     },
  55984 #endif /* chips */
  55985 
  55986 #if defined(BCM_53570_A0)
  55987     { /* SOC_REG_INT_GTOVRPr */
  55988         soc_block_list[2],
  55989         soc_portreg,
  55990         1,
  55991         0,
  55992         0x8900,
  55993         SOC_REG_FLAG_COUNTER |
  55994                           SOC_REG_FLAG_ED_CNTR,
  55995         0,
  55996         1,
  55997         soc_GR1023_BCM53400_A0r_fields,
  55998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55999         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56000         291,
  56001         -1,
  56002     },
  56003 #endif /* chips */
  56004 
  56005 #if defined(BCM_53570_B0)
  56006     { /* SOC_REG_INT_GTOVRP_BCM53570_B0r */
  56007         soc_block_list[2],
  56008         soc_portreg,
  56009         1,
  56010         0,
  56011         0x8900,
  56012         SOC_REG_FLAG_COUNTER |
  56013                           SOC_REG_FLAG_ED_CNTR,
  56014         0,
  56015         1,
  56016         soc_GR1023_BCM53400_A0r_fields,
  56017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56018         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56019         295,
  56020         -1,
  56021     },
  56022 #endif /* chips */
  56023 
  56024 #if defined(BCM_53400_A0)
  56025     { /* SOC_REG_INT_GTOVR_BCM53400_A0r */
  56026         soc_block_list[9],
  56027         soc_portreg,
  56028         1,
  56029         0,
  56030         0x2300,
  56031         SOC_REG_FLAG_COUNTER |
  56032                           SOC_REG_FLAG_ED_CNTR,
  56033         0,
  56034         1,
  56035         soc_GR1023_BCM53400_A0r_fields,
  56036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56037         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56038         134,
  56039         -1,
  56040     },
  56041 #endif /* chips */
  56042 
  56043 #if defined(BCM_53540_A0)
  56044     { /* SOC_REG_INT_GTOVR_BCM53540_A0r */
  56045         soc_block_list[2],
  56046         soc_portreg,
  56047         1,
  56048         0,
  56049         0x3400,
  56050         SOC_REG_FLAG_COUNTER |
  56051                           SOC_REG_FLAG_ED_CNTR,
  56052         0,
  56053         1,
  56054         soc_GR1023_BCM53400_A0r_fields,
  56055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56056         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56057         151,
  56058         -1,
  56059     },
  56060 #endif /* chips */
  56061 
  56062 #if defined(BCM_53570_A0)
  56063     { /* SOC_REG_INT_GTOVR_BCM53570_A0r */
  56064         soc_block_list[2],
  56065         soc_portreg,
  56066         1,
  56067         0,
  56068         0x3400,
  56069         SOC_REG_FLAG_COUNTER |
  56070                           SOC_REG_FLAG_ED_CNTR,
  56071         0,
  56072         1,
  56073         soc_GR1023_BCM53400_A0r_fields,
  56074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56075         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56076         206,
  56077         -1,
  56078     },
  56079 #endif /* chips */
  56080 
  56081 #if defined(BCM_53570_B0)
  56082     { /* SOC_REG_INT_GTOVR_BCM53570_B0r */
  56083         soc_block_list[2],
  56084         soc_portreg,
  56085         1,
  56086         0,
  56087         0x3400,
  56088         SOC_REG_FLAG_COUNTER |
  56089                           SOC_REG_FLAG_ED_CNTR,
  56090         0,
  56091         1,
  56092         soc_GR1023_BCM53400_A0r_fields,
  56093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56094         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56095         210,
  56096         -1,
  56097     },
  56098 #endif /* chips */
  56099 
  56100 #if defined(BCM_56142_A0)
  56101     { /* SOC_REG_INT_GTOVR_BCM56142_A0r */
  56102         soc_block_list[210],
  56103         soc_portreg,
  56104         1,
  56105         0,
  56106         0xa3,
  56107         SOC_REG_FLAG_COUNTER |
  56108                           SOC_REG_FLAG_ED_CNTR,
  56109         0,
  56110         1,
  56111         soc_GR1023r_fields,
  56112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56113         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56114         210,
  56115         -1,
  56116     },
  56117 #endif /* chips */
  56118 
  56119 #if defined(BCM_56150_A0)
  56120     { /* SOC_REG_INT_GTOVR_BCM56150_A0r */
  56121         soc_block_list[2],
  56122         soc_portreg,
  56123         1,
  56124         0,
  56125         0x2300,
  56126         SOC_REG_FLAG_COUNTER |
  56127                           SOC_REG_FLAG_ED_CNTR,
  56128         0,
  56129         1,
  56130         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  56131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56132         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56133         130,
  56134         -1,
  56135     },
  56136 #endif /* chips */
  56137 
  56138 #if defined(BCM_56160_A0)
  56139     { /* SOC_REG_INT_GTOVR_BCM56160_A0r */
  56140         soc_block_list[2],
  56141         soc_portreg,
  56142         1,
  56143         0,
  56144         0x3400,
  56145         SOC_REG_FLAG_COUNTER |
  56146                           SOC_REG_FLAG_ED_CNTR,
  56147         0,
  56148         1,
  56149         soc_GR1023_BCM53400_A0r_fields,
  56150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56151         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56152         151,
  56153         -1,
  56154     },
  56155 #endif /* chips */
  56156 
  56157 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  56158     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  56159     { /* SOC_REG_INT_GTOVR_BCM56224_A0r */
  56160         soc_block_list[2],
  56161         soc_portreg,
  56162         1,
  56163         0,
  56164         0x23,
  56165         SOC_REG_FLAG_COUNTER |
  56166                           SOC_REG_FLAG_ED_CNTR,
  56167         0,
  56168         1,
  56169         soc_GR1023r_fields,
  56170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56171         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56172         69,
  56173         -1,
  56174     },
  56175 #endif /* chips */
  56176 
  56177 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  56178     { /* SOC_REG_INT_GTOVR_BCM56334_A0r */
  56179         soc_block_list[210],
  56180         soc_portreg,
  56181         1,
  56182         0,
  56183         0xa3,
  56184         SOC_REG_FLAG_COUNTER |
  56185                           SOC_REG_FLAG_ED_CNTR,
  56186         0,
  56187         1,
  56188         soc_GR1023r_fields,
  56189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56190         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56191         205,
  56192         -1,
  56193     },
  56194 #endif /* chips */
  56195 
  56196 #if defined(BCM_56370_A0)
  56197     { /* SOC_REG_INT_GTOVR_BCM56370_A0r */
  56198         soc_block_list[9],
  56199         soc_portreg,
  56200         1,
  56201         0,
  56202         0x2400,
  56203         SOC_REG_FLAG_COUNTER |
  56204                           SOC_REG_FLAG_ED_CNTR,
  56205         0,
  56206         1,
  56207         soc_GR1023_BCM53400_A0r_fields,
  56208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56209         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56210         96,
  56211         -1,
  56212         3,
  56213     },
  56214 #endif /* chips */
  56215 
  56216 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  56217     { /* SOC_REG_INT_GTOVR_BCM56440_A0r */
  56218         soc_block_list[2],
  56219         soc_portreg,
  56220         1,
  56221         0,
  56222         0xa4,
  56223         SOC_REG_FLAG_COUNTER |
  56224                           SOC_REG_FLAG_ED_CNTR,
  56225         0,
  56226         1,
  56227         soc_GR1023r_fields,
  56228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56229         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56230         203,
  56231         -1,
  56232     },
  56233 #endif /* chips */
  56234 
  56235 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  56236     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  56237     { /* SOC_REG_INT_GTOVR_BCM56624_A0r */
  56238         soc_block_list[205],
  56239         soc_portreg,
  56240         1,
  56241         0,
  56242         0xb0,
  56243         SOC_REG_FLAG_COUNTER |
  56244                           SOC_REG_FLAG_ED_CNTR,
  56245         0,
  56246         1,
  56247         soc_GR1023r_fields,
  56248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56250         218,
  56251         -1,
  56252     },
  56253 #endif /* chips */
  56254 
  56255 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  56256     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  56257     { /* SOC_REG_INT_GTOVR_BCM56634_A0r */
  56258         soc_block_list[207],
  56259         soc_portreg,
  56260         1,
  56261         0,
  56262         0xb0,
  56263         SOC_REG_FLAG_COUNTER |
  56264                           SOC_REG_FLAG_ED_CNTR,
  56265         0,
  56266         1,
  56267         soc_GR1023r_fields,
  56268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56269         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56270         218,
  56271         -1,
  56272     },
  56273 #endif /* chips */
  56274 
  56275 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  56276     { /* SOC_REG_INT_GTOVR_BCM56685_A0r */
  56277         soc_block_list[209],
  56278         soc_portreg,
  56279         1,
  56280         0,
  56281         0xb0,
  56282         SOC_REG_FLAG_COUNTER |
  56283                           SOC_REG_FLAG_ED_CNTR,
  56284         0,
  56285         1,
  56286         soc_GR1023r_fields,
  56287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56288         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56289         218,
  56290         -1,
  56291     },
  56292 #endif /* chips */
  56293 
  56294 #if defined(BCM_56800_A0)
  56295     { /* SOC_REG_INT_GTOVR_BCM56800_A0r */
  56296         soc_block_list[9],
  56297         soc_portreg,
  56298         1,
  56299         0,
  56300         0x75,
  56301         SOC_REG_FLAG_COUNTER |
  56302                           SOC_REG_FLAG_ED_CNTR,
  56303         0,
  56304         1,
  56305         soc_GR1023r_fields,
  56306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56308         159,
  56309         -1,
  56310     },
  56311 #endif /* chips */
  56312 
  56313 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  56314     { /* SOC_REG_INT_GTOVR_BCM56820_A0r */
  56315         soc_block_list[206],
  56316         soc_portreg,
  56317         1,
  56318         0,
  56319         0xb1,
  56320         SOC_REG_FLAG_COUNTER |
  56321                           SOC_REG_FLAG_ED_CNTR,
  56322         0,
  56323         1,
  56324         soc_GR1023r_fields,
  56325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56326         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56327         229,
  56328         -1,
  56329     },
  56330 #endif /* chips */
  56331 
  56332 #if defined(BCM_88375_A0)
  56333     { /* SOC_REG_INT_GTOVR_BCM88375_A0r */
  56334         soc_block_list[2],
  56335         soc_portreg,
  56336         1,
  56337         0,
  56338         0x2300,
  56339         SOC_REG_FLAG_COUNTER,
  56340         0,
  56341         1,
  56342         soc_GTOVR_BCM88375_A0r_fields,
  56343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56344         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56345         35,
  56346         -1,
  56347     },
  56348 #endif /* chips */
  56349 
  56350 #if defined(BCM_88375_B0)
  56351     { /* SOC_REG_INT_GTOVR_BCM88375_B0r */
  56352         soc_block_list[2],
  56353         soc_portreg,
  56354         1,
  56355         0,
  56356         0x2300,
  56357         SOC_REG_FLAG_COUNTER,
  56358         0,
  56359         1,
  56360         soc_GTOVR_BCM88375_B0r_fields,
  56361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56362         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56363         35,
  56364         -1,
  56365     },
  56366 #endif /* chips */
  56367 
  56368 #if defined(BCM_88470_A0)
  56369     { /* SOC_REG_INT_GTOVR_BCM88470_A0r */
  56370         soc_block_list[2],
  56371         soc_portreg,
  56372         1,
  56373         0,
  56374         0x2300,
  56375         SOC_REG_FLAG_COUNTER,
  56376         0,
  56377         1,
  56378         soc_GTOVR_BCM88470_A0r_fields,
  56379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56380         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56381         35,
  56382         -1,
  56383     },
  56384 #endif /* chips */
  56385 
  56386 #if defined(BCM_88470_B0)
  56387     { /* SOC_REG_INT_GTOVR_BCM88470_B0r */
  56388         soc_block_list[2],
  56389         soc_portreg,
  56390         1,
  56391         0,
  56392         0x2300,
  56393         SOC_REG_FLAG_COUNTER,
  56394         0,
  56395         1,
  56396         soc_GTOVR_BCM88470_B0r_fields,
  56397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56398         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56399         35,
  56400         -1,
  56401     },
  56402 #endif /* chips */
  56403 
  56404 #if defined(BCM_88675_A0)
  56405     { /* SOC_REG_INT_GTOVR_BCM88675_A0r */
  56406         soc_block_list[2],
  56407         soc_portreg,
  56408         1,
  56409         0,
  56410         0x2300,
  56411         SOC_REG_FLAG_COUNTER,
  56412         0,
  56413         1,
  56414         soc_GTOVRr_fields,
  56415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56416         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56417         35,
  56418         -1,
  56419     },
  56420 #endif /* chips */
  56421 
  56422 #if defined(BCM_88675_B0)
  56423     { /* SOC_REG_INT_GTOVR_BCM88675_B0r */
  56424         soc_block_list[2],
  56425         soc_portreg,
  56426         1,
  56427         0,
  56428         0x2300,
  56429         SOC_REG_FLAG_COUNTER,
  56430         0,
  56431         1,
  56432         soc_GTOVR_BCM88675_B0r_fields,
  56433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56434         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56435         35,
  56436         -1,
  56437     },
  56438 #endif /* chips */
  56439 
  56440 #if defined(BCM_88680_A0)
  56441     { /* SOC_REG_INT_GTOVR_BCM88680_A0r */
  56442         soc_block_list[2],
  56443         soc_portreg,
  56444         1,
  56445         0,
  56446         0x2300,
  56447         SOC_REG_FLAG_COUNTER,
  56448         0,
  56449         1,
  56450         soc_GTOVR_BCM88680_A0r_fields,
  56451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56452         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56453         35,
  56454         -1,
  56455     },
  56456 #endif /* chips */
  56457 
  56458 #if defined(BCM_56370_A0)
  56459     { /* SOC_REG_INT_GTPFCr */
  56460         soc_block_list[9],
  56461         soc_portreg,
  56462         1,
  56463         0,
  56464         0x3d00,
  56465         SOC_REG_FLAG_COUNTER,
  56466         0,
  56467         1,
  56468         soc_GR1023_BCM53400_A0r_fields,
  56469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56470         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56471         121,
  56472         -1,
  56473         3,
  56474     },
  56475 #endif /* chips */
  56476 
  56477 #if defined(BCM_56160_A0)
  56478     { /* SOC_REG_INT_GTPFC0r */
  56479         soc_block_list[2],
  56480         soc_portreg,
  56481         1,
  56482         0,
  56483         0x4e00,
  56484         SOC_REG_FLAG_COUNTER,
  56485         0,
  56486         1,
  56487         soc_GR1023_BCM53400_A0r_fields,
  56488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56490         177,
  56491         -1,
  56492     },
  56493 #endif /* chips */
  56494 
  56495 #if defined(BCM_56160_A0)
  56496     { /* SOC_REG_INT_GTPFC1r */
  56497         soc_block_list[2],
  56498         soc_portreg,
  56499         1,
  56500         0,
  56501         0x4f00,
  56502         SOC_REG_FLAG_COUNTER,
  56503         0,
  56504         1,
  56505         soc_GR1023_BCM53400_A0r_fields,
  56506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56508         178,
  56509         -1,
  56510     },
  56511 #endif /* chips */
  56512 
  56513 #if defined(BCM_56160_A0)
  56514     { /* SOC_REG_INT_GTPFC2r */
  56515         soc_block_list[2],
  56516         soc_portreg,
  56517         1,
  56518         0,
  56519         0x5000,
  56520         SOC_REG_FLAG_COUNTER,
  56521         0,
  56522         1,
  56523         soc_GR1023_BCM53400_A0r_fields,
  56524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56525         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56526         179,
  56527         -1,
  56528     },
  56529 #endif /* chips */
  56530 
  56531 #if defined(BCM_56160_A0)
  56532     { /* SOC_REG_INT_GTPFC3r */
  56533         soc_block_list[2],
  56534         soc_portreg,
  56535         1,
  56536         0,
  56537         0x5100,
  56538         SOC_REG_FLAG_COUNTER,
  56539         0,
  56540         1,
  56541         soc_GR1023_BCM53400_A0r_fields,
  56542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56544         180,
  56545         -1,
  56546     },
  56547 #endif /* chips */
  56548 
  56549 #if defined(BCM_56160_A0)
  56550     { /* SOC_REG_INT_GTPFC4r */
  56551         soc_block_list[2],
  56552         soc_portreg,
  56553         1,
  56554         0,
  56555         0x5200,
  56556         SOC_REG_FLAG_COUNTER,
  56557         0,
  56558         1,
  56559         soc_GR1023_BCM53400_A0r_fields,
  56560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56562         181,
  56563         -1,
  56564     },
  56565 #endif /* chips */
  56566 
  56567 #if defined(BCM_56160_A0)
  56568     { /* SOC_REG_INT_GTPFC5r */
  56569         soc_block_list[2],
  56570         soc_portreg,
  56571         1,
  56572         0,
  56573         0x5300,
  56574         SOC_REG_FLAG_COUNTER,
  56575         0,
  56576         1,
  56577         soc_GR1023_BCM53400_A0r_fields,
  56578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56580         182,
  56581         -1,
  56582     },
  56583 #endif /* chips */
  56584 
  56585 #if defined(BCM_56160_A0)
  56586     { /* SOC_REG_INT_GTPFC6r */
  56587         soc_block_list[2],
  56588         soc_portreg,
  56589         1,
  56590         0,
  56591         0x5400,
  56592         SOC_REG_FLAG_COUNTER,
  56593         0,
  56594         1,
  56595         soc_GR1023_BCM53400_A0r_fields,
  56596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56598         183,
  56599         -1,
  56600     },
  56601 #endif /* chips */
  56602 
  56603 #if defined(BCM_56160_A0)
  56604     { /* SOC_REG_INT_GTPFC7r */
  56605         soc_block_list[2],
  56606         soc_portreg,
  56607         1,
  56608         0,
  56609         0x5500,
  56610         SOC_REG_FLAG_COUNTER,
  56611         0,
  56612         1,
  56613         soc_GR1023_BCM53400_A0r_fields,
  56614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56616         184,
  56617         -1,
  56618     },
  56619 #endif /* chips */
  56620 
  56621 #if defined(BCM_53540_A0)
  56622     { /* SOC_REG_INT_GTPFC0_BCM53540_A0r */
  56623         soc_block_list[2],
  56624         soc_portreg,
  56625         1,
  56626         0,
  56627         0x4e00,
  56628         SOC_REG_FLAG_COUNTER,
  56629         0,
  56630         1,
  56631         soc_GR1023_BCM53400_A0r_fields,
  56632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56634         177,
  56635         -1,
  56636     },
  56637 #endif /* chips */
  56638 
  56639 #if defined(BCM_53570_A0)
  56640     { /* SOC_REG_INT_GTPFC0_BCM53570_A0r */
  56641         soc_block_list[2],
  56642         soc_portreg,
  56643         1,
  56644         0,
  56645         0x5600,
  56646         SOC_REG_FLAG_COUNTER,
  56647         0,
  56648         1,
  56649         soc_GR1023_BCM53400_A0r_fields,
  56650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56652         240,
  56653         -1,
  56654     },
  56655 #endif /* chips */
  56656 
  56657 #if defined(BCM_53570_B0)
  56658     { /* SOC_REG_INT_GTPFC0_BCM53570_B0r */
  56659         soc_block_list[2],
  56660         soc_portreg,
  56661         1,
  56662         0,
  56663         0x5600,
  56664         SOC_REG_FLAG_COUNTER,
  56665         0,
  56666         1,
  56667         soc_GR1023_BCM53400_A0r_fields,
  56668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56670         244,
  56671         -1,
  56672     },
  56673 #endif /* chips */
  56674 
  56675 #if defined(BCM_53540_A0)
  56676     { /* SOC_REG_INT_GTPFC1_BCM53540_A0r */
  56677         soc_block_list[2],
  56678         soc_portreg,
  56679         1,
  56680         0,
  56681         0x4f00,
  56682         SOC_REG_FLAG_COUNTER,
  56683         0,
  56684         1,
  56685         soc_GR1023_BCM53400_A0r_fields,
  56686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56687         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56688         178,
  56689         -1,
  56690     },
  56691 #endif /* chips */
  56692 
  56693 #if defined(BCM_53570_A0)
  56694     { /* SOC_REG_INT_GTPFC1_BCM53570_A0r */
  56695         soc_block_list[2],
  56696         soc_portreg,
  56697         1,
  56698         0,
  56699         0x5700,
  56700         SOC_REG_FLAG_COUNTER,
  56701         0,
  56702         1,
  56703         soc_GR1023_BCM53400_A0r_fields,
  56704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56706         241,
  56707         -1,
  56708     },
  56709 #endif /* chips */
  56710 
  56711 #if defined(BCM_53570_B0)
  56712     { /* SOC_REG_INT_GTPFC1_BCM53570_B0r */
  56713         soc_block_list[2],
  56714         soc_portreg,
  56715         1,
  56716         0,
  56717         0x5700,
  56718         SOC_REG_FLAG_COUNTER,
  56719         0,
  56720         1,
  56721         soc_GR1023_BCM53400_A0r_fields,
  56722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56724         245,
  56725         -1,
  56726     },
  56727 #endif /* chips */
  56728 
  56729 #if defined(BCM_53540_A0)
  56730     { /* SOC_REG_INT_GTPFC2_BCM53540_A0r */
  56731         soc_block_list[2],
  56732         soc_portreg,
  56733         1,
  56734         0,
  56735         0x5000,
  56736         SOC_REG_FLAG_COUNTER,
  56737         0,
  56738         1,
  56739         soc_GR1023_BCM53400_A0r_fields,
  56740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56742         179,
  56743         -1,
  56744     },
  56745 #endif /* chips */
  56746 
  56747 #if defined(BCM_53570_A0)
  56748     { /* SOC_REG_INT_GTPFC2_BCM53570_A0r */
  56749         soc_block_list[2],
  56750         soc_portreg,
  56751         1,
  56752         0,
  56753         0x5800,
  56754         SOC_REG_FLAG_COUNTER,
  56755         0,
  56756         1,
  56757         soc_GR1023_BCM53400_A0r_fields,
  56758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56760         242,
  56761         -1,
  56762     },
  56763 #endif /* chips */
  56764 
  56765 #if defined(BCM_53570_B0)
  56766     { /* SOC_REG_INT_GTPFC2_BCM53570_B0r */
  56767         soc_block_list[2],
  56768         soc_portreg,
  56769         1,
  56770         0,
  56771         0x5800,
  56772         SOC_REG_FLAG_COUNTER,
  56773         0,
  56774         1,
  56775         soc_GR1023_BCM53400_A0r_fields,
  56776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56778         246,
  56779         -1,
  56780     },
  56781 #endif /* chips */
  56782 
  56783 #if defined(BCM_53540_A0)
  56784     { /* SOC_REG_INT_GTPFC3_BCM53540_A0r */
  56785         soc_block_list[2],
  56786         soc_portreg,
  56787         1,
  56788         0,
  56789         0x5100,
  56790         SOC_REG_FLAG_COUNTER,
  56791         0,
  56792         1,
  56793         soc_GR1023_BCM53400_A0r_fields,
  56794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56796         180,
  56797         -1,
  56798     },
  56799 #endif /* chips */
  56800 
  56801 #if defined(BCM_53570_A0)
  56802     { /* SOC_REG_INT_GTPFC3_BCM53570_A0r */
  56803         soc_block_list[2],
  56804         soc_portreg,
  56805         1,
  56806         0,
  56807         0x5900,
  56808         SOC_REG_FLAG_COUNTER,
  56809         0,
  56810         1,
  56811         soc_GR1023_BCM53400_A0r_fields,
  56812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56814         243,
  56815         -1,
  56816     },
  56817 #endif /* chips */
  56818 
  56819 #if defined(BCM_53570_B0)
  56820     { /* SOC_REG_INT_GTPFC3_BCM53570_B0r */
  56821         soc_block_list[2],
  56822         soc_portreg,
  56823         1,
  56824         0,
  56825         0x5900,
  56826         SOC_REG_FLAG_COUNTER,
  56827         0,
  56828         1,
  56829         soc_GR1023_BCM53400_A0r_fields,
  56830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56832         247,
  56833         -1,
  56834     },
  56835 #endif /* chips */
  56836 
  56837 #if defined(BCM_53540_A0)
  56838     { /* SOC_REG_INT_GTPFC4_BCM53540_A0r */
  56839         soc_block_list[2],
  56840         soc_portreg,
  56841         1,
  56842         0,
  56843         0x5200,
  56844         SOC_REG_FLAG_COUNTER,
  56845         0,
  56846         1,
  56847         soc_GR1023_BCM53400_A0r_fields,
  56848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56850         181,
  56851         -1,
  56852     },
  56853 #endif /* chips */
  56854 
  56855 #if defined(BCM_53570_A0)
  56856     { /* SOC_REG_INT_GTPFC4_BCM53570_A0r */
  56857         soc_block_list[2],
  56858         soc_portreg,
  56859         1,
  56860         0,
  56861         0x5a00,
  56862         SOC_REG_FLAG_COUNTER,
  56863         0,
  56864         1,
  56865         soc_GR1023_BCM53400_A0r_fields,
  56866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56867         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56868         244,
  56869         -1,
  56870     },
  56871 #endif /* chips */
  56872 
  56873 #if defined(BCM_53570_B0)
  56874     { /* SOC_REG_INT_GTPFC4_BCM53570_B0r */
  56875         soc_block_list[2],
  56876         soc_portreg,
  56877         1,
  56878         0,
  56879         0x5a00,
  56880         SOC_REG_FLAG_COUNTER,
  56881         0,
  56882         1,
  56883         soc_GR1023_BCM53400_A0r_fields,
  56884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56886         248,
  56887         -1,
  56888     },
  56889 #endif /* chips */
  56890 
  56891 #if defined(BCM_53540_A0)
  56892     { /* SOC_REG_INT_GTPFC5_BCM53540_A0r */
  56893         soc_block_list[2],
  56894         soc_portreg,
  56895         1,
  56896         0,
  56897         0x5300,
  56898         SOC_REG_FLAG_COUNTER,
  56899         0,
  56900         1,
  56901         soc_GR1023_BCM53400_A0r_fields,
  56902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56904         182,
  56905         -1,
  56906     },
  56907 #endif /* chips */
  56908 
  56909 #if defined(BCM_53570_A0)
  56910     { /* SOC_REG_INT_GTPFC5_BCM53570_A0r */
  56911         soc_block_list[2],
  56912         soc_portreg,
  56913         1,
  56914         0,
  56915         0x5b00,
  56916         SOC_REG_FLAG_COUNTER,
  56917         0,
  56918         1,
  56919         soc_GR1023_BCM53400_A0r_fields,
  56920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56922         245,
  56923         -1,
  56924     },
  56925 #endif /* chips */
  56926 
  56927 #if defined(BCM_53570_B0)
  56928     { /* SOC_REG_INT_GTPFC5_BCM53570_B0r */
  56929         soc_block_list[2],
  56930         soc_portreg,
  56931         1,
  56932         0,
  56933         0x5b00,
  56934         SOC_REG_FLAG_COUNTER,
  56935         0,
  56936         1,
  56937         soc_GR1023_BCM53400_A0r_fields,
  56938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56940         249,
  56941         -1,
  56942     },
  56943 #endif /* chips */
  56944 
  56945 #if defined(BCM_53540_A0)
  56946     { /* SOC_REG_INT_GTPFC6_BCM53540_A0r */
  56947         soc_block_list[2],
  56948         soc_portreg,
  56949         1,
  56950         0,
  56951         0x5400,
  56952         SOC_REG_FLAG_COUNTER,
  56953         0,
  56954         1,
  56955         soc_GR1023_BCM53400_A0r_fields,
  56956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56958         183,
  56959         -1,
  56960     },
  56961 #endif /* chips */
  56962 
  56963 #if defined(BCM_53570_A0)
  56964     { /* SOC_REG_INT_GTPFC6_BCM53570_A0r */
  56965         soc_block_list[2],
  56966         soc_portreg,
  56967         1,
  56968         0,
  56969         0x5c00,
  56970         SOC_REG_FLAG_COUNTER,
  56971         0,
  56972         1,
  56973         soc_GR1023_BCM53400_A0r_fields,
  56974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56976         246,
  56977         -1,
  56978     },
  56979 #endif /* chips */
  56980 
  56981 #if defined(BCM_53570_B0)
  56982     { /* SOC_REG_INT_GTPFC6_BCM53570_B0r */
  56983         soc_block_list[2],
  56984         soc_portreg,
  56985         1,
  56986         0,
  56987         0x5c00,
  56988         SOC_REG_FLAG_COUNTER,
  56989         0,
  56990         1,
  56991         soc_GR1023_BCM53400_A0r_fields,
  56992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  56994         250,
  56995         -1,
  56996     },
  56997 #endif /* chips */
  56998 
  56999 #if defined(BCM_53540_A0)
  57000     { /* SOC_REG_INT_GTPFC7_BCM53540_A0r */
  57001         soc_block_list[2],
  57002         soc_portreg,
  57003         1,
  57004         0,
  57005         0x5500,
  57006         SOC_REG_FLAG_COUNTER,
  57007         0,
  57008         1,
  57009         soc_GR1023_BCM53400_A0r_fields,
  57010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57012         184,
  57013         -1,
  57014     },
  57015 #endif /* chips */
  57016 
  57017 #if defined(BCM_53570_A0)
  57018     { /* SOC_REG_INT_GTPFC7_BCM53570_A0r */
  57019         soc_block_list[2],
  57020         soc_portreg,
  57021         1,
  57022         0,
  57023         0x5d00,
  57024         SOC_REG_FLAG_COUNTER,
  57025         0,
  57026         1,
  57027         soc_GR1023_BCM53400_A0r_fields,
  57028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57030         247,
  57031         -1,
  57032     },
  57033 #endif /* chips */
  57034 
  57035 #if defined(BCM_53570_B0)
  57036     { /* SOC_REG_INT_GTPFC7_BCM53570_B0r */
  57037         soc_block_list[2],
  57038         soc_portreg,
  57039         1,
  57040         0,
  57041         0x5d00,
  57042         SOC_REG_FLAG_COUNTER,
  57043         0,
  57044         1,
  57045         soc_GR1023_BCM53400_A0r_fields,
  57046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57048         251,
  57049         -1,
  57050     },
  57051 #endif /* chips */
  57052 
  57053 #if defined(BCM_53570_A0)
  57054     { /* SOC_REG_INT_GTPFCOFF0r */
  57055         soc_block_list[2],
  57056         soc_portreg,
  57057         1,
  57058         0,
  57059         0x4e00,
  57060         SOC_REG_FLAG_COUNTER,
  57061         0,
  57062         1,
  57063         soc_GR1023_BCM53400_A0r_fields,
  57064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57065         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57066         232,
  57067         -1,
  57068     },
  57069 #endif /* chips */
  57070 
  57071 #if defined(BCM_53570_A0)
  57072     { /* SOC_REG_INT_GTPFCOFF1r */
  57073         soc_block_list[2],
  57074         soc_portreg,
  57075         1,
  57076         0,
  57077         0x4f00,
  57078         SOC_REG_FLAG_COUNTER,
  57079         0,
  57080         1,
  57081         soc_GR1023_BCM53400_A0r_fields,
  57082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57084         233,
  57085         -1,
  57086     },
  57087 #endif /* chips */
  57088 
  57089 #if defined(BCM_53570_A0)
  57090     { /* SOC_REG_INT_GTPFCOFF2r */
  57091         soc_block_list[2],
  57092         soc_portreg,
  57093         1,
  57094         0,
  57095         0x5000,
  57096         SOC_REG_FLAG_COUNTER,
  57097         0,
  57098         1,
  57099         soc_GR1023_BCM53400_A0r_fields,
  57100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57101         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57102         234,
  57103         -1,
  57104     },
  57105 #endif /* chips */
  57106 
  57107 #if defined(BCM_53570_A0)
  57108     { /* SOC_REG_INT_GTPFCOFF3r */
  57109         soc_block_list[2],
  57110         soc_portreg,
  57111         1,
  57112         0,
  57113         0x5100,
  57114         SOC_REG_FLAG_COUNTER,
  57115         0,
  57116         1,
  57117         soc_GR1023_BCM53400_A0r_fields,
  57118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57119         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57120         235,
  57121         -1,
  57122     },
  57123 #endif /* chips */
  57124 
  57125 #if defined(BCM_53570_A0)
  57126     { /* SOC_REG_INT_GTPFCOFF4r */
  57127         soc_block_list[2],
  57128         soc_portreg,
  57129         1,
  57130         0,
  57131         0x5200,
  57132         SOC_REG_FLAG_COUNTER,
  57133         0,
  57134         1,
  57135         soc_GR1023_BCM53400_A0r_fields,
  57136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57137         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57138         236,
  57139         -1,
  57140     },
  57141 #endif /* chips */
  57142 
  57143 #if defined(BCM_53570_A0)
  57144     { /* SOC_REG_INT_GTPFCOFF5r */
  57145         soc_block_list[2],
  57146         soc_portreg,
  57147         1,
  57148         0,
  57149         0x5300,
  57150         SOC_REG_FLAG_COUNTER,
  57151         0,
  57152         1,
  57153         soc_GR1023_BCM53400_A0r_fields,
  57154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57155         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57156         237,
  57157         -1,
  57158     },
  57159 #endif /* chips */
  57160 
  57161 #if defined(BCM_53570_A0)
  57162     { /* SOC_REG_INT_GTPFCOFF6r */
  57163         soc_block_list[2],
  57164         soc_portreg,
  57165         1,
  57166         0,
  57167         0x5400,
  57168         SOC_REG_FLAG_COUNTER,
  57169         0,
  57170         1,
  57171         soc_GR1023_BCM53400_A0r_fields,
  57172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57174         238,
  57175         -1,
  57176     },
  57177 #endif /* chips */
  57178 
  57179 #if defined(BCM_53570_A0)
  57180     { /* SOC_REG_INT_GTPFCOFF7r */
  57181         soc_block_list[2],
  57182         soc_portreg,
  57183         1,
  57184         0,
  57185         0x5500,
  57186         SOC_REG_FLAG_COUNTER,
  57187         0,
  57188         1,
  57189         soc_GR1023_BCM53400_A0r_fields,
  57190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57192         239,
  57193         -1,
  57194     },
  57195 #endif /* chips */
  57196 
  57197 #if defined(BCM_53570_B0)
  57198     { /* SOC_REG_INT_GTPFCOFF0_BCM53570_B0r */
  57199         soc_block_list[2],
  57200         soc_portreg,
  57201         1,
  57202         0,
  57203         0x4e00,
  57204         SOC_REG_FLAG_COUNTER,
  57205         0,
  57206         1,
  57207         soc_GR1023_BCM53400_A0r_fields,
  57208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57209         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57210         236,
  57211         -1,
  57212     },
  57213 #endif /* chips */
  57214 
  57215 #if defined(BCM_53570_B0)
  57216     { /* SOC_REG_INT_GTPFCOFF1_BCM53570_B0r */
  57217         soc_block_list[2],
  57218         soc_portreg,
  57219         1,
  57220         0,
  57221         0x4f00,
  57222         SOC_REG_FLAG_COUNTER,
  57223         0,
  57224         1,
  57225         soc_GR1023_BCM53400_A0r_fields,
  57226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57227         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57228         237,
  57229         -1,
  57230     },
  57231 #endif /* chips */
  57232 
  57233 #if defined(BCM_53570_B0)
  57234     { /* SOC_REG_INT_GTPFCOFF2_BCM53570_B0r */
  57235         soc_block_list[2],
  57236         soc_portreg,
  57237         1,
  57238         0,
  57239         0x5000,
  57240         SOC_REG_FLAG_COUNTER,
  57241         0,
  57242         1,
  57243         soc_GR1023_BCM53400_A0r_fields,
  57244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57245         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57246         238,
  57247         -1,
  57248     },
  57249 #endif /* chips */
  57250 
  57251 #if defined(BCM_53570_B0)
  57252     { /* SOC_REG_INT_GTPFCOFF3_BCM53570_B0r */
  57253         soc_block_list[2],
  57254         soc_portreg,
  57255         1,
  57256         0,
  57257         0x5100,
  57258         SOC_REG_FLAG_COUNTER,
  57259         0,
  57260         1,
  57261         soc_GR1023_BCM53400_A0r_fields,
  57262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57264         239,
  57265         -1,
  57266     },
  57267 #endif /* chips */
  57268 
  57269 #if defined(BCM_53570_B0)
  57270     { /* SOC_REG_INT_GTPFCOFF4_BCM53570_B0r */
  57271         soc_block_list[2],
  57272         soc_portreg,
  57273         1,
  57274         0,
  57275         0x5200,
  57276         SOC_REG_FLAG_COUNTER,
  57277         0,
  57278         1,
  57279         soc_GR1023_BCM53400_A0r_fields,
  57280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57281         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57282         240,
  57283         -1,
  57284     },
  57285 #endif /* chips */
  57286 
  57287 #if defined(BCM_53570_B0)
  57288     { /* SOC_REG_INT_GTPFCOFF5_BCM53570_B0r */
  57289         soc_block_list[2],
  57290         soc_portreg,
  57291         1,
  57292         0,
  57293         0x5300,
  57294         SOC_REG_FLAG_COUNTER,
  57295         0,
  57296         1,
  57297         soc_GR1023_BCM53400_A0r_fields,
  57298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57300         241,
  57301         -1,
  57302     },
  57303 #endif /* chips */
  57304 
  57305 #if defined(BCM_53570_B0)
  57306     { /* SOC_REG_INT_GTPFCOFF6_BCM53570_B0r */
  57307         soc_block_list[2],
  57308         soc_portreg,
  57309         1,
  57310         0,
  57311         0x5400,
  57312         SOC_REG_FLAG_COUNTER,
  57313         0,
  57314         1,
  57315         soc_GR1023_BCM53400_A0r_fields,
  57316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57317         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57318         242,
  57319         -1,
  57320     },
  57321 #endif /* chips */
  57322 
  57323 #if defined(BCM_53570_B0)
  57324     { /* SOC_REG_INT_GTPFCOFF7_BCM53570_B0r */
  57325         soc_block_list[2],
  57326         soc_portreg,
  57327         1,
  57328         0,
  57329         0x5500,
  57330         SOC_REG_FLAG_COUNTER,
  57331         0,
  57332         1,
  57333         soc_GR1023_BCM53400_A0r_fields,
  57334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57335         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57336         243,
  57337         -1,
  57338     },
  57339 #endif /* chips */
  57340 
  57341 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  57342     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  57343     { /* SOC_REG_INT_GTPKTr */
  57344         soc_block_list[2],
  57345         soc_portreg,
  57346         1,
  57347         0,
  57348         0x27,
  57349         SOC_REG_FLAG_COUNTER,
  57350         0,
  57351         1,
  57352         soc_GR1023r_fields,
  57353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57354         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57355         73,
  57356         -1,
  57357     },
  57358 #endif /* chips */
  57359 
  57360 #if defined(BCM_53570_A0)
  57361     { /* SOC_REG_INT_GTPKTPr */
  57362         soc_block_list[2],
  57363         soc_portreg,
  57364         1,
  57365         0,
  57366         0x9e00,
  57367         SOC_REG_FLAG_COUNTER,
  57368         0,
  57369         1,
  57370         soc_GR1023_BCM53400_A0r_fields,
  57371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57372         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57373         312,
  57374         -1,
  57375     },
  57376 #endif /* chips */
  57377 
  57378 #if defined(BCM_53570_B0)
  57379     { /* SOC_REG_INT_GTPKTP_BCM53570_B0r */
  57380         soc_block_list[2],
  57381         soc_portreg,
  57382         1,
  57383         0,
  57384         0x9e00,
  57385         SOC_REG_FLAG_COUNTER,
  57386         0,
  57387         1,
  57388         soc_GR1023_BCM53400_A0r_fields,
  57389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57390         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57391         316,
  57392         -1,
  57393     },
  57394 #endif /* chips */
  57395 
  57396 #if defined(BCM_53400_A0)
  57397     { /* SOC_REG_INT_GTPKT_BCM53400_A0r */
  57398         soc_block_list[9],
  57399         soc_portreg,
  57400         1,
  57401         0,
  57402         0x3800,
  57403         SOC_REG_FLAG_COUNTER,
  57404         0,
  57405         1,
  57406         soc_GR1023_BCM53400_A0r_fields,
  57407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57408         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57409         155,
  57410         -1,
  57411     },
  57412 #endif /* chips */
  57413 
  57414 #if defined(BCM_53540_A0)
  57415     { /* SOC_REG_INT_GTPKT_BCM53540_A0r */
  57416         soc_block_list[2],
  57417         soc_portreg,
  57418         1,
  57419         0,
  57420         0x4900,
  57421         SOC_REG_FLAG_COUNTER,
  57422         0,
  57423         1,
  57424         soc_GR1023_BCM53400_A0r_fields,
  57425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57426         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57427         172,
  57428         -1,
  57429     },
  57430 #endif /* chips */
  57431 
  57432 #if defined(BCM_53570_A0)
  57433     { /* SOC_REG_INT_GTPKT_BCM53570_A0r */
  57434         soc_block_list[2],
  57435         soc_portreg,
  57436         1,
  57437         0,
  57438         0x4900,
  57439         SOC_REG_FLAG_COUNTER,
  57440         0,
  57441         1,
  57442         soc_GR1023_BCM53400_A0r_fields,
  57443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57444         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57445         227,
  57446         -1,
  57447     },
  57448 #endif /* chips */
  57449 
  57450 #if defined(BCM_53570_B0)
  57451     { /* SOC_REG_INT_GTPKT_BCM53570_B0r */
  57452         soc_block_list[2],
  57453         soc_portreg,
  57454         1,
  57455         0,
  57456         0x4900,
  57457         SOC_REG_FLAG_COUNTER,
  57458         0,
  57459         1,
  57460         soc_GR1023_BCM53400_A0r_fields,
  57461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57462         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57463         231,
  57464         -1,
  57465     },
  57466 #endif /* chips */
  57467 
  57468 #if defined(BCM_56142_A0)
  57469     { /* SOC_REG_INT_GTPKT_BCM56142_A0r */
  57470         soc_block_list[210],
  57471         soc_portreg,
  57472         1,
  57473         0,
  57474         0xb8,
  57475         SOC_REG_FLAG_COUNTER,
  57476         0,
  57477         1,
  57478         soc_GR1023r_fields,
  57479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57480         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57481         231,
  57482         -1,
  57483     },
  57484 #endif /* chips */
  57485 
  57486 #if defined(BCM_56150_A0)
  57487     { /* SOC_REG_INT_GTPKT_BCM56150_A0r */
  57488         soc_block_list[2],
  57489         soc_portreg,
  57490         1,
  57491         0,
  57492         0x3800,
  57493         SOC_REG_FLAG_COUNTER,
  57494         0,
  57495         1,
  57496         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  57497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57498         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57499         151,
  57500         -1,
  57501     },
  57502 #endif /* chips */
  57503 
  57504 #if defined(BCM_56160_A0)
  57505     { /* SOC_REG_INT_GTPKT_BCM56160_A0r */
  57506         soc_block_list[2],
  57507         soc_portreg,
  57508         1,
  57509         0,
  57510         0x4900,
  57511         SOC_REG_FLAG_COUNTER,
  57512         0,
  57513         1,
  57514         soc_GR1023_BCM53400_A0r_fields,
  57515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57516         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57517         172,
  57518         -1,
  57519     },
  57520 #endif /* chips */
  57521 
  57522 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  57523     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  57524     { /* SOC_REG_INT_GTPKT_BCM56224_A0r */
  57525         soc_block_list[2],
  57526         soc_portreg,
  57527         1,
  57528         0,
  57529         0x38,
  57530         SOC_REG_FLAG_COUNTER,
  57531         0,
  57532         1,
  57533         soc_GR1023r_fields,
  57534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57535         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57536         90,
  57537         -1,
  57538     },
  57539 #endif /* chips */
  57540 
  57541 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  57542     { /* SOC_REG_INT_GTPKT_BCM56334_A0r */
  57543         soc_block_list[210],
  57544         soc_portreg,
  57545         1,
  57546         0,
  57547         0xb8,
  57548         SOC_REG_FLAG_COUNTER,
  57549         0,
  57550         1,
  57551         soc_GR1023r_fields,
  57552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57554         226,
  57555         -1,
  57556     },
  57557 #endif /* chips */
  57558 
  57559 #if defined(BCM_56370_A0)
  57560     { /* SOC_REG_INT_GTPKT_BCM56370_A0r */
  57561         soc_block_list[9],
  57562         soc_portreg,
  57563         1,
  57564         0,
  57565         0x3900,
  57566         SOC_REG_FLAG_COUNTER,
  57567         0,
  57568         1,
  57569         soc_GR1023_BCM53400_A0r_fields,
  57570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57572         117,
  57573         -1,
  57574         3,
  57575     },
  57576 #endif /* chips */
  57577 
  57578 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  57579     { /* SOC_REG_INT_GTPKT_BCM56440_A0r */
  57580         soc_block_list[2],
  57581         soc_portreg,
  57582         1,
  57583         0,
  57584         0xba,
  57585         SOC_REG_FLAG_COUNTER,
  57586         0,
  57587         1,
  57588         soc_GR1023r_fields,
  57589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57590         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57591         225,
  57592         -1,
  57593     },
  57594 #endif /* chips */
  57595 
  57596 #if defined(BCM_56514_A0)
  57597     { /* SOC_REG_INT_GTPKT_BCM56514_A0r */
  57598         soc_block_list[2],
  57599         soc_portreg,
  57600         1,
  57601         0,
  57602         0x29,
  57603         SOC_REG_FLAG_COUNTER,
  57604         0,
  57605         1,
  57606         soc_GR1023r_fields,
  57607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57608         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57609         75,
  57610         -1,
  57611     },
  57612 #endif /* chips */
  57613 
  57614 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  57615     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  57616     { /* SOC_REG_INT_GTPKT_BCM56624_A0r */
  57617         soc_block_list[205],
  57618         soc_portreg,
  57619         1,
  57620         0,
  57621         0xa9,
  57622         SOC_REG_FLAG_COUNTER,
  57623         0,
  57624         1,
  57625         soc_GR1023r_fields,
  57626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57628         211,
  57629         -1,
  57630     },
  57631 #endif /* chips */
  57632 
  57633 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  57634     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  57635     { /* SOC_REG_INT_GTPKT_BCM56634_A0r */
  57636         soc_block_list[207],
  57637         soc_portreg,
  57638         1,
  57639         0,
  57640         0xa9,
  57641         SOC_REG_FLAG_COUNTER,
  57642         0,
  57643         1,
  57644         soc_GR1023r_fields,
  57645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57646         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57647         211,
  57648         -1,
  57649     },
  57650 #endif /* chips */
  57651 
  57652 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  57653     { /* SOC_REG_INT_GTPKT_BCM56685_A0r */
  57654         soc_block_list[209],
  57655         soc_portreg,
  57656         1,
  57657         0,
  57658         0xa9,
  57659         SOC_REG_FLAG_COUNTER,
  57660         0,
  57661         1,
  57662         soc_GR1023r_fields,
  57663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57665         211,
  57666         -1,
  57667     },
  57668 #endif /* chips */
  57669 
  57670 #if defined(BCM_56800_A0)
  57671     { /* SOC_REG_INT_GTPKT_BCM56800_A0r */
  57672         soc_block_list[9],
  57673         soc_portreg,
  57674         1,
  57675         0,
  57676         0x6e,
  57677         SOC_REG_FLAG_COUNTER,
  57678         0,
  57679         1,
  57680         soc_GR1023r_fields,
  57681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57682         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57683         152,
  57684         -1,
  57685     },
  57686 #endif /* chips */
  57687 
  57688 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  57689     { /* SOC_REG_INT_GTPKT_BCM56820_A0r */
  57690         soc_block_list[206],
  57691         soc_portreg,
  57692         1,
  57693         0,
  57694         0xaa,
  57695         SOC_REG_FLAG_COUNTER,
  57696         0,
  57697         1,
  57698         soc_GR1023r_fields,
  57699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57701         222,
  57702         -1,
  57703     },
  57704 #endif /* chips */
  57705 
  57706 #if defined(BCM_88375_A0)
  57707     { /* SOC_REG_INT_GTPKT_BCM88375_A0r */
  57708         soc_block_list[2],
  57709         soc_portreg,
  57710         1,
  57711         0,
  57712         0x3800,
  57713         SOC_REG_FLAG_COUNTER,
  57714         0,
  57715         1,
  57716         soc_GTPKT_BCM88375_A0r_fields,
  57717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57718         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57719         56,
  57720         -1,
  57721     },
  57722 #endif /* chips */
  57723 
  57724 #if defined(BCM_88375_B0)
  57725     { /* SOC_REG_INT_GTPKT_BCM88375_B0r */
  57726         soc_block_list[2],
  57727         soc_portreg,
  57728         1,
  57729         0,
  57730         0x3800,
  57731         SOC_REG_FLAG_COUNTER,
  57732         0,
  57733         1,
  57734         soc_GTPKT_BCM88375_B0r_fields,
  57735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57736         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57737         56,
  57738         -1,
  57739     },
  57740 #endif /* chips */
  57741 
  57742 #if defined(BCM_88470_A0)
  57743     { /* SOC_REG_INT_GTPKT_BCM88470_A0r */
  57744         soc_block_list[2],
  57745         soc_portreg,
  57746         1,
  57747         0,
  57748         0x3800,
  57749         SOC_REG_FLAG_COUNTER,
  57750         0,
  57751         1,
  57752         soc_GTPKT_BCM88470_A0r_fields,
  57753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57754         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57755         56,
  57756         -1,
  57757     },
  57758 #endif /* chips */
  57759 
  57760 #if defined(BCM_88470_B0)
  57761     { /* SOC_REG_INT_GTPKT_BCM88470_B0r */
  57762         soc_block_list[2],
  57763         soc_portreg,
  57764         1,
  57765         0,
  57766         0x3800,
  57767         SOC_REG_FLAG_COUNTER,
  57768         0,
  57769         1,
  57770         soc_GTPKT_BCM88470_B0r_fields,
  57771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57772         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57773         56,
  57774         -1,
  57775     },
  57776 #endif /* chips */
  57777 
  57778 #if defined(BCM_88675_A0)
  57779     { /* SOC_REG_INT_GTPKT_BCM88675_A0r */
  57780         soc_block_list[2],
  57781         soc_portreg,
  57782         1,
  57783         0,
  57784         0x3800,
  57785         SOC_REG_FLAG_COUNTER,
  57786         0,
  57787         1,
  57788         soc_GTPKTr_fields,
  57789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57791         56,
  57792         -1,
  57793     },
  57794 #endif /* chips */
  57795 
  57796 #if defined(BCM_88675_B0)
  57797     { /* SOC_REG_INT_GTPKT_BCM88675_B0r */
  57798         soc_block_list[2],
  57799         soc_portreg,
  57800         1,
  57801         0,
  57802         0x3800,
  57803         SOC_REG_FLAG_COUNTER,
  57804         0,
  57805         1,
  57806         soc_GTPKT_BCM88675_B0r_fields,
  57807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57808         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57809         56,
  57810         -1,
  57811     },
  57812 #endif /* chips */
  57813 
  57814 #if defined(BCM_88680_A0)
  57815     { /* SOC_REG_INT_GTPKT_BCM88680_A0r */
  57816         soc_block_list[2],
  57817         soc_portreg,
  57818         1,
  57819         0,
  57820         0x3800,
  57821         SOC_REG_FLAG_COUNTER,
  57822         0,
  57823         1,
  57824         soc_GTPKT_BCM88680_A0r_fields,
  57825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57826         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  57827         56,
  57828         -1,
  57829     },
  57830 #endif /* chips */
  57831 
  57832 #if defined(BCM_56514_A0)
  57833     { /* SOC_REG_INT_GTPOKr */
  57834         soc_block_list[2],
  57835         soc_portreg,
  57836         1,
  57837         0,
  57838         0x3b,
  57839         SOC_REG_FLAG_COUNTER,
  57840         0,
  57841         1,
  57842         soc_GR1023r_fields,
  57843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57844         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57845         93,
  57846         -1,
  57847     },
  57848 #endif /* chips */
  57849 
  57850 #if defined(BCM_53570_A0)
  57851     { /* SOC_REG_INT_GTPOKPr */
  57852         soc_block_list[2],
  57853         soc_portreg,
  57854         1,
  57855         0,
  57856         0xa100,
  57857         SOC_REG_FLAG_COUNTER,
  57858         0,
  57859         1,
  57860         soc_GR1023_BCM53400_A0r_fields,
  57861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57862         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57863         315,
  57864         -1,
  57865     },
  57866 #endif /* chips */
  57867 
  57868 #if defined(BCM_53570_B0)
  57869     { /* SOC_REG_INT_GTPOKP_BCM53570_B0r */
  57870         soc_block_list[2],
  57871         soc_portreg,
  57872         1,
  57873         0,
  57874         0xa100,
  57875         SOC_REG_FLAG_COUNTER,
  57876         0,
  57877         1,
  57878         soc_GR1023_BCM53400_A0r_fields,
  57879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57880         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57881         319,
  57882         -1,
  57883     },
  57884 #endif /* chips */
  57885 
  57886 #if defined(BCM_53400_A0)
  57887     { /* SOC_REG_INT_GTPOK_BCM53400_A0r */
  57888         soc_block_list[9],
  57889         soc_portreg,
  57890         1,
  57891         0,
  57892         0x3b00,
  57893         SOC_REG_FLAG_COUNTER,
  57894         0,
  57895         1,
  57896         soc_GR1023_BCM53400_A0r_fields,
  57897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57899         158,
  57900         -1,
  57901     },
  57902 #endif /* chips */
  57903 
  57904 #if defined(BCM_53540_A0)
  57905     { /* SOC_REG_INT_GTPOK_BCM53540_A0r */
  57906         soc_block_list[2],
  57907         soc_portreg,
  57908         1,
  57909         0,
  57910         0x4c00,
  57911         SOC_REG_FLAG_COUNTER,
  57912         0,
  57913         1,
  57914         soc_GR1023_BCM53400_A0r_fields,
  57915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57916         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57917         175,
  57918         -1,
  57919     },
  57920 #endif /* chips */
  57921 
  57922 #if defined(BCM_53570_A0)
  57923     { /* SOC_REG_INT_GTPOK_BCM53570_A0r */
  57924         soc_block_list[2],
  57925         soc_portreg,
  57926         1,
  57927         0,
  57928         0x4c00,
  57929         SOC_REG_FLAG_COUNTER,
  57930         0,
  57931         1,
  57932         soc_GR1023_BCM53400_A0r_fields,
  57933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57934         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57935         230,
  57936         -1,
  57937     },
  57938 #endif /* chips */
  57939 
  57940 #if defined(BCM_53570_B0)
  57941     { /* SOC_REG_INT_GTPOK_BCM53570_B0r */
  57942         soc_block_list[2],
  57943         soc_portreg,
  57944         1,
  57945         0,
  57946         0x4c00,
  57947         SOC_REG_FLAG_COUNTER,
  57948         0,
  57949         1,
  57950         soc_GR1023_BCM53400_A0r_fields,
  57951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57952         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57953         234,
  57954         -1,
  57955     },
  57956 #endif /* chips */
  57957 
  57958 #if defined(BCM_56142_A0)
  57959     { /* SOC_REG_INT_GTPOK_BCM56142_A0r */
  57960         soc_block_list[210],
  57961         soc_portreg,
  57962         1,
  57963         0,
  57964         0xbb,
  57965         SOC_REG_FLAG_COUNTER,
  57966         0,
  57967         1,
  57968         soc_GR1023r_fields,
  57969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57971         234,
  57972         -1,
  57973     },
  57974 #endif /* chips */
  57975 
  57976 #if defined(BCM_56150_A0)
  57977     { /* SOC_REG_INT_GTPOK_BCM56150_A0r */
  57978         soc_block_list[2],
  57979         soc_portreg,
  57980         1,
  57981         0,
  57982         0x3b00,
  57983         SOC_REG_FLAG_COUNTER,
  57984         0,
  57985         1,
  57986         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  57987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57988         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  57989         154,
  57990         -1,
  57991     },
  57992 #endif /* chips */
  57993 
  57994 #if defined(BCM_56160_A0)
  57995     { /* SOC_REG_INT_GTPOK_BCM56160_A0r */
  57996         soc_block_list[2],
  57997         soc_portreg,
  57998         1,
  57999         0,
  58000         0x4c00,
  58001         SOC_REG_FLAG_COUNTER,
  58002         0,
  58003         1,
  58004         soc_GR1023_BCM53400_A0r_fields,
  58005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58006         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58007         175,
  58008         -1,
  58009     },
  58010 #endif /* chips */
  58011 
  58012 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  58013     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  58014     { /* SOC_REG_INT_GTPOK_BCM56224_A0r */
  58015         soc_block_list[2],
  58016         soc_portreg,
  58017         1,
  58018         0,
  58019         0x3b,
  58020         SOC_REG_FLAG_COUNTER,
  58021         0,
  58022         1,
  58023         soc_GR1023r_fields,
  58024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58026         93,
  58027         -1,
  58028     },
  58029 #endif /* chips */
  58030 
  58031 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  58032     { /* SOC_REG_INT_GTPOK_BCM56334_A0r */
  58033         soc_block_list[210],
  58034         soc_portreg,
  58035         1,
  58036         0,
  58037         0xbb,
  58038         SOC_REG_FLAG_COUNTER,
  58039         0,
  58040         1,
  58041         soc_GR1023r_fields,
  58042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58044         229,
  58045         -1,
  58046     },
  58047 #endif /* chips */
  58048 
  58049 #if defined(BCM_56370_A0)
  58050     { /* SOC_REG_INT_GTPOK_BCM56370_A0r */
  58051         soc_block_list[9],
  58052         soc_portreg,
  58053         1,
  58054         0,
  58055         0x3c00,
  58056         SOC_REG_FLAG_COUNTER,
  58057         0,
  58058         1,
  58059         soc_GR1023_BCM53400_A0r_fields,
  58060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58061         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58062         120,
  58063         -1,
  58064         3,
  58065     },
  58066 #endif /* chips */
  58067 
  58068 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  58069     { /* SOC_REG_INT_GTPOK_BCM56440_A0r */
  58070         soc_block_list[2],
  58071         soc_portreg,
  58072         1,
  58073         0,
  58074         0xbd,
  58075         SOC_REG_FLAG_COUNTER,
  58076         0,
  58077         1,
  58078         soc_GR1023r_fields,
  58079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58080         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58081         228,
  58082         -1,
  58083     },
  58084 #endif /* chips */
  58085 
  58086 #if defined(BCM_56624_A0) || defined(BCM_56680_A0)
  58087     { /* SOC_REG_INT_GTPOK_BCM56624_A0r */
  58088         soc_block_list[205],
  58089         soc_portreg,
  58090         1,
  58091         0,
  58092         0xbb,
  58093         SOC_REG_FLAG_COUNTER,
  58094         0,
  58095         1,
  58096         soc_GR1023r_fields,
  58097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58098         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58099         229,
  58100         -1,
  58101     },
  58102 #endif /* chips */
  58103 
  58104 #if defined(BCM_56624_B0) || defined(BCM_56680_B0)
  58105     { /* SOC_REG_INT_GTPOK_BCM56624_B0r */
  58106         soc_block_list[205],
  58107         soc_portreg,
  58108         1,
  58109         0,
  58110         0xbb,
  58111         SOC_REG_FLAG_COUNTER |
  58112                           SOC_REG_FLAG_ED_CNTR,
  58113         0,
  58114         1,
  58115         soc_GR1023r_fields,
  58116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58118         229,
  58119         -1,
  58120     },
  58121 #endif /* chips */
  58122 
  58123 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  58124     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  58125     { /* SOC_REG_INT_GTPOK_BCM56634_A0r */
  58126         soc_block_list[207],
  58127         soc_portreg,
  58128         1,
  58129         0,
  58130         0xbb,
  58131         SOC_REG_FLAG_COUNTER |
  58132                           SOC_REG_FLAG_ED_CNTR,
  58133         0,
  58134         1,
  58135         soc_GR1023r_fields,
  58136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58137         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58138         229,
  58139         -1,
  58140     },
  58141 #endif /* chips */
  58142 
  58143 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  58144     { /* SOC_REG_INT_GTPOK_BCM56685_A0r */
  58145         soc_block_list[209],
  58146         soc_portreg,
  58147         1,
  58148         0,
  58149         0xbb,
  58150         SOC_REG_FLAG_COUNTER |
  58151                           SOC_REG_FLAG_ED_CNTR,
  58152         0,
  58153         1,
  58154         soc_GR1023r_fields,
  58155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58156         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58157         229,
  58158         -1,
  58159     },
  58160 #endif /* chips */
  58161 
  58162 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  58163     { /* SOC_REG_INT_GTPOK_BCM56820_A0r */
  58164         soc_block_list[206],
  58165         soc_portreg,
  58166         1,
  58167         0,
  58168         0xbc,
  58169         SOC_REG_FLAG_COUNTER,
  58170         0,
  58171         1,
  58172         soc_GR1023r_fields,
  58173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58174         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58175         240,
  58176         -1,
  58177     },
  58178 #endif /* chips */
  58179 
  58180 #if defined(BCM_88375_A0)
  58181     { /* SOC_REG_INT_GTPOK_BCM88375_A0r */
  58182         soc_block_list[2],
  58183         soc_portreg,
  58184         1,
  58185         0,
  58186         0x3b00,
  58187         SOC_REG_FLAG_COUNTER,
  58188         0,
  58189         1,
  58190         soc_GTPOK_BCM88375_A0r_fields,
  58191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58192         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58193         59,
  58194         -1,
  58195     },
  58196 #endif /* chips */
  58197 
  58198 #if defined(BCM_88375_B0)
  58199     { /* SOC_REG_INT_GTPOK_BCM88375_B0r */
  58200         soc_block_list[2],
  58201         soc_portreg,
  58202         1,
  58203         0,
  58204         0x3b00,
  58205         SOC_REG_FLAG_COUNTER,
  58206         0,
  58207         1,
  58208         soc_GTPOK_BCM88375_B0r_fields,
  58209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58210         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58211         59,
  58212         -1,
  58213     },
  58214 #endif /* chips */
  58215 
  58216 #if defined(BCM_88470_A0)
  58217     { /* SOC_REG_INT_GTPOK_BCM88470_A0r */
  58218         soc_block_list[2],
  58219         soc_portreg,
  58220         1,
  58221         0,
  58222         0x3b00,
  58223         SOC_REG_FLAG_COUNTER,
  58224         0,
  58225         1,
  58226         soc_GTPOK_BCM88470_A0r_fields,
  58227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58228         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58229         59,
  58230         -1,
  58231     },
  58232 #endif /* chips */
  58233 
  58234 #if defined(BCM_88470_B0)
  58235     { /* SOC_REG_INT_GTPOK_BCM88470_B0r */
  58236         soc_block_list[2],
  58237         soc_portreg,
  58238         1,
  58239         0,
  58240         0x3b00,
  58241         SOC_REG_FLAG_COUNTER,
  58242         0,
  58243         1,
  58244         soc_GTPOK_BCM88470_B0r_fields,
  58245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58246         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58247         59,
  58248         -1,
  58249     },
  58250 #endif /* chips */
  58251 
  58252 #if defined(BCM_88675_A0)
  58253     { /* SOC_REG_INT_GTPOK_BCM88675_A0r */
  58254         soc_block_list[2],
  58255         soc_portreg,
  58256         1,
  58257         0,
  58258         0x3b00,
  58259         SOC_REG_FLAG_COUNTER,
  58260         0,
  58261         1,
  58262         soc_GTPOKr_fields,
  58263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58264         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58265         59,
  58266         -1,
  58267     },
  58268 #endif /* chips */
  58269 
  58270 #if defined(BCM_88675_B0)
  58271     { /* SOC_REG_INT_GTPOK_BCM88675_B0r */
  58272         soc_block_list[2],
  58273         soc_portreg,
  58274         1,
  58275         0,
  58276         0x3b00,
  58277         SOC_REG_FLAG_COUNTER,
  58278         0,
  58279         1,
  58280         soc_GTPOK_BCM88675_B0r_fields,
  58281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58282         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58283         59,
  58284         -1,
  58285     },
  58286 #endif /* chips */
  58287 
  58288 #if defined(BCM_88680_A0)
  58289     { /* SOC_REG_INT_GTPOK_BCM88680_A0r */
  58290         soc_block_list[2],
  58291         soc_portreg,
  58292         1,
  58293         0,
  58294         0x3b00,
  58295         SOC_REG_FLAG_COUNTER,
  58296         0,
  58297         1,
  58298         soc_GTPOK_BCM88680_A0r_fields,
  58299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58300         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58301         59,
  58302         -1,
  58303     },
  58304 #endif /* chips */
  58305 
  58306 #if defined(BCM_53570_A0)
  58307     { /* SOC_REG_INT_GTRMFPr */
  58308         soc_block_list[2],
  58309         soc_portreg,
  58310         1,
  58311         0,
  58312         0xa400,
  58313         SOC_REG_FLAG_COUNTER,
  58314         0,
  58315         1,
  58316         soc_GR1023_BCM53400_A0r_fields,
  58317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58319         318,
  58320         -1,
  58321     },
  58322 #endif /* chips */
  58323 
  58324 #if defined(BCM_53570_B0)
  58325     { /* SOC_REG_INT_GTRMFP_BCM53570_B0r */
  58326         soc_block_list[2],
  58327         soc_portreg,
  58328         1,
  58329         0,
  58330         0xa400,
  58331         SOC_REG_FLAG_COUNTER,
  58332         0,
  58333         1,
  58334         soc_GR1023_BCM53400_A0r_fields,
  58335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58336         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58337         322,
  58338         -1,
  58339     },
  58340 #endif /* chips */
  58341 
  58342 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  58343     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  58344     { /* SOC_REG_INT_GTSCLr */
  58345         soc_block_list[2],
  58346         soc_portreg,
  58347         1,
  58348         0,
  58349         0x31,
  58350         SOC_REG_FLAG_COUNTER |
  58351                           SOC_REG_FLAG_ED_CNTR,
  58352         0,
  58353         1,
  58354         soc_GR1023r_fields,
  58355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58357         83,
  58358         -1,
  58359     },
  58360 #endif /* chips */
  58361 
  58362 #if defined(BCM_53570_A0)
  58363     { /* SOC_REG_INT_GTSCLPr */
  58364         soc_block_list[2],
  58365         soc_portreg,
  58366         1,
  58367         0,
  58368         0x8c00,
  58369         SOC_REG_FLAG_COUNTER,
  58370         0,
  58371         1,
  58372         soc_GR1023_BCM53400_A0r_fields,
  58373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58375         294,
  58376         -1,
  58377     },
  58378 #endif /* chips */
  58379 
  58380 #if defined(BCM_53570_B0)
  58381     { /* SOC_REG_INT_GTSCLP_BCM53570_B0r */
  58382         soc_block_list[2],
  58383         soc_portreg,
  58384         1,
  58385         0,
  58386         0x8c00,
  58387         SOC_REG_FLAG_COUNTER,
  58388         0,
  58389         1,
  58390         soc_GR1023_BCM53400_A0r_fields,
  58391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58393         298,
  58394         -1,
  58395     },
  58396 #endif /* chips */
  58397 
  58398 #if defined(BCM_53400_A0)
  58399     { /* SOC_REG_INT_GTSCL_BCM53400_A0r */
  58400         soc_block_list[9],
  58401         soc_portreg,
  58402         1,
  58403         0,
  58404         0x2600,
  58405         SOC_REG_FLAG_COUNTER,
  58406         0,
  58407         1,
  58408         soc_GR1023_BCM53400_A0r_fields,
  58409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58410         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58411         137,
  58412         -1,
  58413     },
  58414 #endif /* chips */
  58415 
  58416 #if defined(BCM_53540_A0)
  58417     { /* SOC_REG_INT_GTSCL_BCM53540_A0r */
  58418         soc_block_list[2],
  58419         soc_portreg,
  58420         1,
  58421         0,
  58422         0x3700,
  58423         SOC_REG_FLAG_COUNTER,
  58424         0,
  58425         1,
  58426         soc_GR1023_BCM53400_A0r_fields,
  58427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58429         154,
  58430         -1,
  58431     },
  58432 #endif /* chips */
  58433 
  58434 #if defined(BCM_53570_A0)
  58435     { /* SOC_REG_INT_GTSCL_BCM53570_A0r */
  58436         soc_block_list[2],
  58437         soc_portreg,
  58438         1,
  58439         0,
  58440         0x3700,
  58441         SOC_REG_FLAG_COUNTER,
  58442         0,
  58443         1,
  58444         soc_GR1023_BCM53400_A0r_fields,
  58445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58446         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58447         209,
  58448         -1,
  58449     },
  58450 #endif /* chips */
  58451 
  58452 #if defined(BCM_53570_B0)
  58453     { /* SOC_REG_INT_GTSCL_BCM53570_B0r */
  58454         soc_block_list[2],
  58455         soc_portreg,
  58456         1,
  58457         0,
  58458         0x3700,
  58459         SOC_REG_FLAG_COUNTER,
  58460         0,
  58461         1,
  58462         soc_GR1023_BCM53400_A0r_fields,
  58463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58464         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58465         213,
  58466         -1,
  58467     },
  58468 #endif /* chips */
  58469 
  58470 #if defined(BCM_56142_A0)
  58471     { /* SOC_REG_INT_GTSCL_BCM56142_A0r */
  58472         soc_block_list[210],
  58473         soc_portreg,
  58474         1,
  58475         0,
  58476         0xa6,
  58477         SOC_REG_FLAG_COUNTER,
  58478         0,
  58479         1,
  58480         soc_GR1023r_fields,
  58481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58482         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58483         213,
  58484         -1,
  58485     },
  58486 #endif /* chips */
  58487 
  58488 #if defined(BCM_56150_A0)
  58489     { /* SOC_REG_INT_GTSCL_BCM56150_A0r */
  58490         soc_block_list[2],
  58491         soc_portreg,
  58492         1,
  58493         0,
  58494         0x2600,
  58495         SOC_REG_FLAG_COUNTER,
  58496         0,
  58497         1,
  58498         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  58499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58500         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58501         133,
  58502         -1,
  58503     },
  58504 #endif /* chips */
  58505 
  58506 #if defined(BCM_56160_A0)
  58507     { /* SOC_REG_INT_GTSCL_BCM56160_A0r */
  58508         soc_block_list[2],
  58509         soc_portreg,
  58510         1,
  58511         0,
  58512         0x3700,
  58513         SOC_REG_FLAG_COUNTER,
  58514         0,
  58515         1,
  58516         soc_GR1023_BCM53400_A0r_fields,
  58517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58518         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58519         154,
  58520         -1,
  58521     },
  58522 #endif /* chips */
  58523 
  58524 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  58525     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  58526     { /* SOC_REG_INT_GTSCL_BCM56224_A0r */
  58527         soc_block_list[2],
  58528         soc_portreg,
  58529         1,
  58530         0,
  58531         0x26,
  58532         SOC_REG_FLAG_COUNTER,
  58533         0,
  58534         1,
  58535         soc_GR1023r_fields,
  58536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58538         72,
  58539         -1,
  58540     },
  58541 #endif /* chips */
  58542 
  58543 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  58544     { /* SOC_REG_INT_GTSCL_BCM56334_A0r */
  58545         soc_block_list[210],
  58546         soc_portreg,
  58547         1,
  58548         0,
  58549         0xa6,
  58550         SOC_REG_FLAG_COUNTER,
  58551         0,
  58552         1,
  58553         soc_GR1023r_fields,
  58554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58556         208,
  58557         -1,
  58558     },
  58559 #endif /* chips */
  58560 
  58561 #if defined(BCM_56370_A0)
  58562     { /* SOC_REG_INT_GTSCL_BCM56370_A0r */
  58563         soc_block_list[9],
  58564         soc_portreg,
  58565         1,
  58566         0,
  58567         0x2700,
  58568         SOC_REG_FLAG_COUNTER,
  58569         0,
  58570         1,
  58571         soc_GR1023_BCM53400_A0r_fields,
  58572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58574         99,
  58575         -1,
  58576         3,
  58577     },
  58578 #endif /* chips */
  58579 
  58580 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  58581     { /* SOC_REG_INT_GTSCL_BCM56440_A0r */
  58582         soc_block_list[2],
  58583         soc_portreg,
  58584         1,
  58585         0,
  58586         0xa7,
  58587         SOC_REG_FLAG_COUNTER,
  58588         0,
  58589         1,
  58590         soc_GR1023r_fields,
  58591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58592         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58593         206,
  58594         -1,
  58595     },
  58596 #endif /* chips */
  58597 
  58598 #if defined(BCM_56514_A0)
  58599     { /* SOC_REG_INT_GTSCL_BCM56514_A0r */
  58600         soc_block_list[2],
  58601         soc_portreg,
  58602         1,
  58603         0,
  58604         0x33,
  58605         SOC_REG_FLAG_COUNTER,
  58606         0,
  58607         1,
  58608         soc_GR1023r_fields,
  58609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58610         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58611         85,
  58612         -1,
  58613     },
  58614 #endif /* chips */
  58615 
  58616 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  58617     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  58618     { /* SOC_REG_INT_GTSCL_BCM56624_A0r */
  58619         soc_block_list[205],
  58620         soc_portreg,
  58621         1,
  58622         0,
  58623         0xb3,
  58624         SOC_REG_FLAG_COUNTER,
  58625         0,
  58626         1,
  58627         soc_GR1023r_fields,
  58628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58630         221,
  58631         -1,
  58632     },
  58633 #endif /* chips */
  58634 
  58635 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  58636     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  58637     { /* SOC_REG_INT_GTSCL_BCM56634_A0r */
  58638         soc_block_list[207],
  58639         soc_portreg,
  58640         1,
  58641         0,
  58642         0xb3,
  58643         SOC_REG_FLAG_COUNTER,
  58644         0,
  58645         1,
  58646         soc_GR1023r_fields,
  58647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58649         221,
  58650         -1,
  58651     },
  58652 #endif /* chips */
  58653 
  58654 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  58655     { /* SOC_REG_INT_GTSCL_BCM56685_A0r */
  58656         soc_block_list[209],
  58657         soc_portreg,
  58658         1,
  58659         0,
  58660         0xb3,
  58661         SOC_REG_FLAG_COUNTER,
  58662         0,
  58663         1,
  58664         soc_GR1023r_fields,
  58665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58666         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58667         221,
  58668         -1,
  58669     },
  58670 #endif /* chips */
  58671 
  58672 #if defined(BCM_56800_A0)
  58673     { /* SOC_REG_INT_GTSCL_BCM56800_A0r */
  58674         soc_block_list[9],
  58675         soc_portreg,
  58676         1,
  58677         0,
  58678         0x78,
  58679         SOC_REG_FLAG_COUNTER,
  58680         0,
  58681         1,
  58682         soc_GR1023r_fields,
  58683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58684         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58685         162,
  58686         -1,
  58687     },
  58688 #endif /* chips */
  58689 
  58690 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  58691     { /* SOC_REG_INT_GTSCL_BCM56820_A0r */
  58692         soc_block_list[206],
  58693         soc_portreg,
  58694         1,
  58695         0,
  58696         0xb4,
  58697         SOC_REG_FLAG_COUNTER,
  58698         0,
  58699         1,
  58700         soc_GR1023r_fields,
  58701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58703         232,
  58704         -1,
  58705     },
  58706 #endif /* chips */
  58707 
  58708 #if defined(BCM_88375_A0)
  58709     { /* SOC_REG_INT_GTSCL_BCM88375_A0r */
  58710         soc_block_list[2],
  58711         soc_portreg,
  58712         1,
  58713         0,
  58714         0x2600,
  58715         SOC_REG_FLAG_COUNTER,
  58716         0,
  58717         1,
  58718         soc_GTSCL_BCM88375_A0r_fields,
  58719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58721         38,
  58722         -1,
  58723     },
  58724 #endif /* chips */
  58725 
  58726 #if defined(BCM_88375_B0)
  58727     { /* SOC_REG_INT_GTSCL_BCM88375_B0r */
  58728         soc_block_list[2],
  58729         soc_portreg,
  58730         1,
  58731         0,
  58732         0x2600,
  58733         SOC_REG_FLAG_COUNTER,
  58734         0,
  58735         1,
  58736         soc_GTSCL_BCM88375_B0r_fields,
  58737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58739         38,
  58740         -1,
  58741     },
  58742 #endif /* chips */
  58743 
  58744 #if defined(BCM_88470_A0)
  58745     { /* SOC_REG_INT_GTSCL_BCM88470_A0r */
  58746         soc_block_list[2],
  58747         soc_portreg,
  58748         1,
  58749         0,
  58750         0x2600,
  58751         SOC_REG_FLAG_COUNTER,
  58752         0,
  58753         1,
  58754         soc_GTSCL_BCM88470_A0r_fields,
  58755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58757         38,
  58758         -1,
  58759     },
  58760 #endif /* chips */
  58761 
  58762 #if defined(BCM_88470_B0)
  58763     { /* SOC_REG_INT_GTSCL_BCM88470_B0r */
  58764         soc_block_list[2],
  58765         soc_portreg,
  58766         1,
  58767         0,
  58768         0x2600,
  58769         SOC_REG_FLAG_COUNTER,
  58770         0,
  58771         1,
  58772         soc_GTSCL_BCM88470_B0r_fields,
  58773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58775         38,
  58776         -1,
  58777     },
  58778 #endif /* chips */
  58779 
  58780 #if defined(BCM_88675_A0)
  58781     { /* SOC_REG_INT_GTSCL_BCM88675_A0r */
  58782         soc_block_list[2],
  58783         soc_portreg,
  58784         1,
  58785         0,
  58786         0x2600,
  58787         SOC_REG_FLAG_COUNTER,
  58788         0,
  58789         1,
  58790         soc_GTSCLr_fields,
  58791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58792         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58793         38,
  58794         -1,
  58795     },
  58796 #endif /* chips */
  58797 
  58798 #if defined(BCM_88675_B0)
  58799     { /* SOC_REG_INT_GTSCL_BCM88675_B0r */
  58800         soc_block_list[2],
  58801         soc_portreg,
  58802         1,
  58803         0,
  58804         0x2600,
  58805         SOC_REG_FLAG_COUNTER,
  58806         0,
  58807         1,
  58808         soc_GTSCL_BCM88675_B0r_fields,
  58809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58810         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58811         38,
  58812         -1,
  58813     },
  58814 #endif /* chips */
  58815 
  58816 #if defined(BCM_88680_A0)
  58817     { /* SOC_REG_INT_GTSCL_BCM88680_A0r */
  58818         soc_block_list[2],
  58819         soc_portreg,
  58820         1,
  58821         0,
  58822         0x2600,
  58823         SOC_REG_FLAG_COUNTER,
  58824         0,
  58825         1,
  58826         soc_GTSCL_BCM88680_A0r_fields,
  58827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58828         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58829         38,
  58830         -1,
  58831     },
  58832 #endif /* chips */
  58833 
  58834 #if defined(BCM_56514_A0)
  58835     { /* SOC_REG_INT_GTUCr */
  58836         soc_block_list[2],
  58837         soc_portreg,
  58838         1,
  58839         0,
  58840         0x3a,
  58841         SOC_REG_FLAG_COUNTER,
  58842         0,
  58843         1,
  58844         soc_GR1023r_fields,
  58845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58846         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58847         92,
  58848         -1,
  58849     },
  58850 #endif /* chips */
  58851 
  58852 #if defined(BCM_53570_A0)
  58853     { /* SOC_REG_INT_GTUCPr */
  58854         soc_block_list[2],
  58855         soc_portreg,
  58856         1,
  58857         0,
  58858         0xa000,
  58859         SOC_REG_FLAG_COUNTER,
  58860         0,
  58861         1,
  58862         soc_GR1023_BCM53400_A0r_fields,
  58863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58864         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58865         314,
  58866         -1,
  58867     },
  58868 #endif /* chips */
  58869 
  58870 #if defined(BCM_53570_B0)
  58871     { /* SOC_REG_INT_GTUCP_BCM53570_B0r */
  58872         soc_block_list[2],
  58873         soc_portreg,
  58874         1,
  58875         0,
  58876         0xa000,
  58877         SOC_REG_FLAG_COUNTER,
  58878         0,
  58879         1,
  58880         soc_GR1023_BCM53400_A0r_fields,
  58881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58882         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58883         318,
  58884         -1,
  58885     },
  58886 #endif /* chips */
  58887 
  58888 #if defined(BCM_53400_A0)
  58889     { /* SOC_REG_INT_GTUC_BCM53400_A0r */
  58890         soc_block_list[9],
  58891         soc_portreg,
  58892         1,
  58893         0,
  58894         0x3a00,
  58895         SOC_REG_FLAG_COUNTER,
  58896         0,
  58897         1,
  58898         soc_GR1023_BCM53400_A0r_fields,
  58899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58901         157,
  58902         -1,
  58903     },
  58904 #endif /* chips */
  58905 
  58906 #if defined(BCM_53540_A0)
  58907     { /* SOC_REG_INT_GTUC_BCM53540_A0r */
  58908         soc_block_list[2],
  58909         soc_portreg,
  58910         1,
  58911         0,
  58912         0x4b00,
  58913         SOC_REG_FLAG_COUNTER,
  58914         0,
  58915         1,
  58916         soc_GR1023_BCM53400_A0r_fields,
  58917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58919         174,
  58920         -1,
  58921     },
  58922 #endif /* chips */
  58923 
  58924 #if defined(BCM_53570_A0)
  58925     { /* SOC_REG_INT_GTUC_BCM53570_A0r */
  58926         soc_block_list[2],
  58927         soc_portreg,
  58928         1,
  58929         0,
  58930         0x4b00,
  58931         SOC_REG_FLAG_COUNTER,
  58932         0,
  58933         1,
  58934         soc_GR1023_BCM53400_A0r_fields,
  58935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58936         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58937         229,
  58938         -1,
  58939     },
  58940 #endif /* chips */
  58941 
  58942 #if defined(BCM_53570_B0)
  58943     { /* SOC_REG_INT_GTUC_BCM53570_B0r */
  58944         soc_block_list[2],
  58945         soc_portreg,
  58946         1,
  58947         0,
  58948         0x4b00,
  58949         SOC_REG_FLAG_COUNTER,
  58950         0,
  58951         1,
  58952         soc_GR1023_BCM53400_A0r_fields,
  58953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58954         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58955         233,
  58956         -1,
  58957     },
  58958 #endif /* chips */
  58959 
  58960 #if defined(BCM_56142_A0)
  58961     { /* SOC_REG_INT_GTUC_BCM56142_A0r */
  58962         soc_block_list[210],
  58963         soc_portreg,
  58964         1,
  58965         0,
  58966         0xba,
  58967         SOC_REG_FLAG_COUNTER,
  58968         0,
  58969         1,
  58970         soc_GR1023r_fields,
  58971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58972         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58973         233,
  58974         -1,
  58975     },
  58976 #endif /* chips */
  58977 
  58978 #if defined(BCM_56150_A0)
  58979     { /* SOC_REG_INT_GTUC_BCM56150_A0r */
  58980         soc_block_list[2],
  58981         soc_portreg,
  58982         1,
  58983         0,
  58984         0x3a00,
  58985         SOC_REG_FLAG_COUNTER,
  58986         0,
  58987         1,
  58988         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  58989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58990         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58991         153,
  58992         -1,
  58993     },
  58994 #endif /* chips */
  58995 
  58996 #if defined(BCM_56160_A0)
  58997     { /* SOC_REG_INT_GTUC_BCM56160_A0r */
  58998         soc_block_list[2],
  58999         soc_portreg,
  59000         1,
  59001         0,
  59002         0x4b00,
  59003         SOC_REG_FLAG_COUNTER,
  59004         0,
  59005         1,
  59006         soc_GR1023_BCM53400_A0r_fields,
  59007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59008         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59009         174,
  59010         -1,
  59011     },
  59012 #endif /* chips */
  59013 
  59014 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  59015     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  59016     { /* SOC_REG_INT_GTUC_BCM56224_A0r */
  59017         soc_block_list[2],
  59018         soc_portreg,
  59019         1,
  59020         0,
  59021         0x3a,
  59022         SOC_REG_FLAG_COUNTER,
  59023         0,
  59024         1,
  59025         soc_GR1023r_fields,
  59026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59027         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59028         92,
  59029         -1,
  59030     },
  59031 #endif /* chips */
  59032 
  59033 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  59034     { /* SOC_REG_INT_GTUC_BCM56334_A0r */
  59035         soc_block_list[210],
  59036         soc_portreg,
  59037         1,
  59038         0,
  59039         0xba,
  59040         SOC_REG_FLAG_COUNTER,
  59041         0,
  59042         1,
  59043         soc_GR1023r_fields,
  59044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59046         228,
  59047         -1,
  59048     },
  59049 #endif /* chips */
  59050 
  59051 #if defined(BCM_56370_A0)
  59052     { /* SOC_REG_INT_GTUC_BCM56370_A0r */
  59053         soc_block_list[9],
  59054         soc_portreg,
  59055         1,
  59056         0,
  59057         0x3b00,
  59058         SOC_REG_FLAG_COUNTER,
  59059         0,
  59060         1,
  59061         soc_GR1023_BCM53400_A0r_fields,
  59062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59064         119,
  59065         -1,
  59066         3,
  59067     },
  59068 #endif /* chips */
  59069 
  59070 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  59071     { /* SOC_REG_INT_GTUC_BCM56440_A0r */
  59072         soc_block_list[2],
  59073         soc_portreg,
  59074         1,
  59075         0,
  59076         0xbc,
  59077         SOC_REG_FLAG_COUNTER,
  59078         0,
  59079         1,
  59080         soc_GR1023r_fields,
  59081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59082         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59083         227,
  59084         -1,
  59085     },
  59086 #endif /* chips */
  59087 
  59088 #if defined(BCM_56624_A0) || defined(BCM_56680_A0)
  59089     { /* SOC_REG_INT_GTUC_BCM56624_A0r */
  59090         soc_block_list[205],
  59091         soc_portreg,
  59092         1,
  59093         0,
  59094         0xba,
  59095         SOC_REG_FLAG_COUNTER,
  59096         0,
  59097         1,
  59098         soc_GR1023r_fields,
  59099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59100         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59101         228,
  59102         -1,
  59103     },
  59104 #endif /* chips */
  59105 
  59106 #if defined(BCM_56624_B0) || defined(BCM_56680_B0)
  59107     { /* SOC_REG_INT_GTUC_BCM56624_B0r */
  59108         soc_block_list[205],
  59109         soc_portreg,
  59110         1,
  59111         0,
  59112         0xba,
  59113         SOC_REG_FLAG_COUNTER |
  59114                           SOC_REG_FLAG_ED_CNTR,
  59115         0,
  59116         1,
  59117         soc_GR1023r_fields,
  59118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59119         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59120         228,
  59121         -1,
  59122     },
  59123 #endif /* chips */
  59124 
  59125 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  59126     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  59127     { /* SOC_REG_INT_GTUC_BCM56634_A0r */
  59128         soc_block_list[207],
  59129         soc_portreg,
  59130         1,
  59131         0,
  59132         0xba,
  59133         SOC_REG_FLAG_COUNTER |
  59134                           SOC_REG_FLAG_ED_CNTR,
  59135         0,
  59136         1,
  59137         soc_GR1023r_fields,
  59138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59139         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59140         228,
  59141         -1,
  59142     },
  59143 #endif /* chips */
  59144 
  59145 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  59146     { /* SOC_REG_INT_GTUC_BCM56685_A0r */
  59147         soc_block_list[209],
  59148         soc_portreg,
  59149         1,
  59150         0,
  59151         0xba,
  59152         SOC_REG_FLAG_COUNTER |
  59153                           SOC_REG_FLAG_ED_CNTR,
  59154         0,
  59155         1,
  59156         soc_GR1023r_fields,
  59157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59159         228,
  59160         -1,
  59161     },
  59162 #endif /* chips */
  59163 
  59164 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  59165     { /* SOC_REG_INT_GTUC_BCM56820_A0r */
  59166         soc_block_list[206],
  59167         soc_portreg,
  59168         1,
  59169         0,
  59170         0xbb,
  59171         SOC_REG_FLAG_COUNTER,
  59172         0,
  59173         1,
  59174         soc_GR1023r_fields,
  59175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59176         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59177         239,
  59178         -1,
  59179     },
  59180 #endif /* chips */
  59181 
  59182 #if defined(BCM_88375_A0)
  59183     { /* SOC_REG_INT_GTUC_BCM88375_A0r */
  59184         soc_block_list[2],
  59185         soc_portreg,
  59186         1,
  59187         0,
  59188         0x3a00,
  59189         SOC_REG_FLAG_COUNTER,
  59190         0,
  59191         1,
  59192         soc_GTUC_BCM88375_A0r_fields,
  59193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59194         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59195         58,
  59196         -1,
  59197     },
  59198 #endif /* chips */
  59199 
  59200 #if defined(BCM_88375_B0)
  59201     { /* SOC_REG_INT_GTUC_BCM88375_B0r */
  59202         soc_block_list[2],
  59203         soc_portreg,
  59204         1,
  59205         0,
  59206         0x3a00,
  59207         SOC_REG_FLAG_COUNTER,
  59208         0,
  59209         1,
  59210         soc_GTUC_BCM88375_B0r_fields,
  59211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59212         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59213         58,
  59214         -1,
  59215     },
  59216 #endif /* chips */
  59217 
  59218 #if defined(BCM_88470_A0)
  59219     { /* SOC_REG_INT_GTUC_BCM88470_A0r */
  59220         soc_block_list[2],
  59221         soc_portreg,
  59222         1,
  59223         0,
  59224         0x3a00,
  59225         SOC_REG_FLAG_COUNTER,
  59226         0,
  59227         1,
  59228         soc_GTUC_BCM88470_A0r_fields,
  59229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59230         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59231         58,
  59232         -1,
  59233     },
  59234 #endif /* chips */
  59235 
  59236 #if defined(BCM_88470_B0)
  59237     { /* SOC_REG_INT_GTUC_BCM88470_B0r */
  59238         soc_block_list[2],
  59239         soc_portreg,
  59240         1,
  59241         0,
  59242         0x3a00,
  59243         SOC_REG_FLAG_COUNTER,
  59244         0,
  59245         1,
  59246         soc_GTUC_BCM88470_B0r_fields,
  59247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59248         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59249         58,
  59250         -1,
  59251     },
  59252 #endif /* chips */
  59253 
  59254 #if defined(BCM_88675_A0)
  59255     { /* SOC_REG_INT_GTUC_BCM88675_A0r */
  59256         soc_block_list[2],
  59257         soc_portreg,
  59258         1,
  59259         0,
  59260         0x3a00,
  59261         SOC_REG_FLAG_COUNTER,
  59262         0,
  59263         1,
  59264         soc_GTUCr_fields,
  59265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59266         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59267         58,
  59268         -1,
  59269     },
  59270 #endif /* chips */
  59271 
  59272 #if defined(BCM_88675_B0)
  59273     { /* SOC_REG_INT_GTUC_BCM88675_B0r */
  59274         soc_block_list[2],
  59275         soc_portreg,
  59276         1,
  59277         0,
  59278         0x3a00,
  59279         SOC_REG_FLAG_COUNTER,
  59280         0,
  59281         1,
  59282         soc_GTUC_BCM88675_B0r_fields,
  59283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59284         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59285         58,
  59286         -1,
  59287     },
  59288 #endif /* chips */
  59289 
  59290 #if defined(BCM_88680_A0)
  59291     { /* SOC_REG_INT_GTUC_BCM88680_A0r */
  59292         soc_block_list[2],
  59293         soc_portreg,
  59294         1,
  59295         0,
  59296         0x3a00,
  59297         SOC_REG_FLAG_COUNTER,
  59298         0,
  59299         1,
  59300         soc_GTUC_BCM88680_A0r_fields,
  59301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59302         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59303         58,
  59304         -1,
  59305     },
  59306 #endif /* chips */
  59307 
  59308 #if defined(BCM_53570_A0)
  59309     { /* SOC_REG_INT_GTVMFPr */
  59310         soc_block_list[2],
  59311         soc_portreg,
  59312         1,
  59313         0,
  59314         0xa300,
  59315         SOC_REG_FLAG_COUNTER,
  59316         0,
  59317         1,
  59318         soc_GR1023_BCM53400_A0r_fields,
  59319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59321         317,
  59322         -1,
  59323     },
  59324 #endif /* chips */
  59325 
  59326 #if defined(BCM_53570_B0)
  59327     { /* SOC_REG_INT_GTVMFP_BCM53570_B0r */
  59328         soc_block_list[2],
  59329         soc_portreg,
  59330         1,
  59331         0,
  59332         0xa300,
  59333         SOC_REG_FLAG_COUNTER,
  59334         0,
  59335         1,
  59336         soc_GR1023_BCM53400_A0r_fields,
  59337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59339         321,
  59340         -1,
  59341     },
  59342 #endif /* chips */
  59343 
  59344 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  59345     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  59346     defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  59347     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  59348     { /* SOC_REG_INT_GTXCFr */
  59349         soc_block_list[2],
  59350         soc_portreg,
  59351         1,
  59352         0,
  59353         0x2d,
  59354         SOC_REG_FLAG_COUNTER,
  59355         0,
  59356         1,
  59357         soc_GR1023r_fields,
  59358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59359         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59360         79,
  59361         -1,
  59362     },
  59363 #endif /* chips */
  59364 
  59365 #if defined(BCM_53400_A0)
  59366     { /* SOC_REG_INT_GTXCF_BCM53400_A0r */
  59367         soc_block_list[9],
  59368         soc_portreg,
  59369         1,
  59370         0,
  59371         0x2200,
  59372         SOC_REG_FLAG_COUNTER,
  59373         0,
  59374         1,
  59375         soc_GR1023_BCM53400_A0r_fields,
  59376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59378         133,
  59379         -1,
  59380     },
  59381 #endif /* chips */
  59382 
  59383 #if defined(BCM_53540_A0)
  59384     { /* SOC_REG_INT_GTXCF_BCM53540_A0r */
  59385         soc_block_list[2],
  59386         soc_portreg,
  59387         1,
  59388         0,
  59389         0x3300,
  59390         SOC_REG_FLAG_COUNTER,
  59391         0,
  59392         1,
  59393         soc_GR1023_BCM53400_A0r_fields,
  59394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59395         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59396         150,
  59397         -1,
  59398     },
  59399 #endif /* chips */
  59400 
  59401 #if defined(BCM_53570_A0)
  59402     { /* SOC_REG_INT_GTXCF_BCM53570_A0r */
  59403         soc_block_list[2],
  59404         soc_portreg,
  59405         1,
  59406         0,
  59407         0x3300,
  59408         SOC_REG_FLAG_COUNTER,
  59409         0,
  59410         1,
  59411         soc_GR1023_BCM53400_A0r_fields,
  59412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59413         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59414         205,
  59415         -1,
  59416     },
  59417 #endif /* chips */
  59418 
  59419 #if defined(BCM_53570_B0)
  59420     { /* SOC_REG_INT_GTXCF_BCM53570_B0r */
  59421         soc_block_list[2],
  59422         soc_portreg,
  59423         1,
  59424         0,
  59425         0x3300,
  59426         SOC_REG_FLAG_COUNTER,
  59427         0,
  59428         1,
  59429         soc_GR1023_BCM53400_A0r_fields,
  59430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59431         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59432         209,
  59433         -1,
  59434     },
  59435 #endif /* chips */
  59436 
  59437 #if defined(BCM_56142_A0)
  59438     { /* SOC_REG_INT_GTXCF_BCM56142_A0r */
  59439         soc_block_list[210],
  59440         soc_portreg,
  59441         1,
  59442         0,
  59443         0xa2,
  59444         SOC_REG_FLAG_COUNTER,
  59445         0,
  59446         1,
  59447         soc_GR1023r_fields,
  59448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59449         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59450         209,
  59451         -1,
  59452     },
  59453 #endif /* chips */
  59454 
  59455 #if defined(BCM_56150_A0)
  59456     { /* SOC_REG_INT_GTXCF_BCM56150_A0r */
  59457         soc_block_list[2],
  59458         soc_portreg,
  59459         1,
  59460         0,
  59461         0x2200,
  59462         SOC_REG_FLAG_COUNTER,
  59463         0,
  59464         1,
  59465         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  59466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59467         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59468         129,
  59469         -1,
  59470     },
  59471 #endif /* chips */
  59472 
  59473 #if defined(BCM_56160_A0)
  59474     { /* SOC_REG_INT_GTXCF_BCM56160_A0r */
  59475         soc_block_list[2],
  59476         soc_portreg,
  59477         1,
  59478         0,
  59479         0x3300,
  59480         SOC_REG_FLAG_COUNTER,
  59481         0,
  59482         1,
  59483         soc_GR1023_BCM53400_A0r_fields,
  59484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59486         150,
  59487         -1,
  59488     },
  59489 #endif /* chips */
  59490 
  59491 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  59492     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  59493     { /* SOC_REG_INT_GTXCF_BCM56224_A0r */
  59494         soc_block_list[2],
  59495         soc_portreg,
  59496         1,
  59497         0,
  59498         0x22,
  59499         SOC_REG_FLAG_COUNTER,
  59500         0,
  59501         1,
  59502         soc_GR1023r_fields,
  59503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59505         68,
  59506         -1,
  59507     },
  59508 #endif /* chips */
  59509 
  59510 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  59511     { /* SOC_REG_INT_GTXCF_BCM56334_A0r */
  59512         soc_block_list[210],
  59513         soc_portreg,
  59514         1,
  59515         0,
  59516         0xa2,
  59517         SOC_REG_FLAG_COUNTER,
  59518         0,
  59519         1,
  59520         soc_GR1023r_fields,
  59521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59522         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59523         204,
  59524         -1,
  59525     },
  59526 #endif /* chips */
  59527 
  59528 #if defined(BCM_56370_A0)
  59529     { /* SOC_REG_INT_GTXCF_BCM56370_A0r */
  59530         soc_block_list[9],
  59531         soc_portreg,
  59532         1,
  59533         0,
  59534         0x2300,
  59535         SOC_REG_FLAG_COUNTER,
  59536         0,
  59537         1,
  59538         soc_GR1023_BCM53400_A0r_fields,
  59539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59540         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59541         95,
  59542         -1,
  59543         3,
  59544     },
  59545 #endif /* chips */
  59546 
  59547 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  59548     { /* SOC_REG_INT_GTXCF_BCM56440_A0r */
  59549         soc_block_list[2],
  59550         soc_portreg,
  59551         1,
  59552         0,
  59553         0xa3,
  59554         SOC_REG_FLAG_COUNTER,
  59555         0,
  59556         1,
  59557         soc_GR1023r_fields,
  59558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59559         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59560         202,
  59561         -1,
  59562     },
  59563 #endif /* chips */
  59564 
  59565 #if defined(BCM_56514_A0)
  59566     { /* SOC_REG_INT_GTXCF_BCM56514_A0r */
  59567         soc_block_list[2],
  59568         soc_portreg,
  59569         1,
  59570         0,
  59571         0x2f,
  59572         SOC_REG_FLAG_COUNTER,
  59573         0,
  59574         1,
  59575         soc_GR1023r_fields,
  59576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59577         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59578         81,
  59579         -1,
  59580     },
  59581 #endif /* chips */
  59582 
  59583 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  59584     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  59585     { /* SOC_REG_INT_GTXCF_BCM56624_A0r */
  59586         soc_block_list[205],
  59587         soc_portreg,
  59588         1,
  59589         0,
  59590         0xaf,
  59591         SOC_REG_FLAG_COUNTER,
  59592         0,
  59593         1,
  59594         soc_GR1023r_fields,
  59595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59596         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59597         217,
  59598         -1,
  59599     },
  59600 #endif /* chips */
  59601 
  59602 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  59603     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  59604     { /* SOC_REG_INT_GTXCF_BCM56634_A0r */
  59605         soc_block_list[207],
  59606         soc_portreg,
  59607         1,
  59608         0,
  59609         0xaf,
  59610         SOC_REG_FLAG_COUNTER,
  59611         0,
  59612         1,
  59613         soc_GR1023r_fields,
  59614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59616         217,
  59617         -1,
  59618     },
  59619 #endif /* chips */
  59620 
  59621 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  59622     { /* SOC_REG_INT_GTXCF_BCM56685_A0r */
  59623         soc_block_list[209],
  59624         soc_portreg,
  59625         1,
  59626         0,
  59627         0xaf,
  59628         SOC_REG_FLAG_COUNTER,
  59629         0,
  59630         1,
  59631         soc_GR1023r_fields,
  59632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59634         217,
  59635         -1,
  59636     },
  59637 #endif /* chips */
  59638 
  59639 #if defined(BCM_56800_A0)
  59640     { /* SOC_REG_INT_GTXCF_BCM56800_A0r */
  59641         soc_block_list[9],
  59642         soc_portreg,
  59643         1,
  59644         0,
  59645         0x74,
  59646         SOC_REG_FLAG_COUNTER,
  59647         0,
  59648         1,
  59649         soc_GR1023r_fields,
  59650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59652         158,
  59653         -1,
  59654     },
  59655 #endif /* chips */
  59656 
  59657 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  59658     { /* SOC_REG_INT_GTXCF_BCM56820_A0r */
  59659         soc_block_list[206],
  59660         soc_portreg,
  59661         1,
  59662         0,
  59663         0xb0,
  59664         SOC_REG_FLAG_COUNTER,
  59665         0,
  59666         1,
  59667         soc_GR1023r_fields,
  59668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59670         228,
  59671         -1,
  59672     },
  59673 #endif /* chips */
  59674 
  59675 #if defined(BCM_88375_A0)
  59676     { /* SOC_REG_INT_GTXCF_BCM88375_A0r */
  59677         soc_block_list[2],
  59678         soc_portreg,
  59679         1,
  59680         0,
  59681         0x2200,
  59682         SOC_REG_FLAG_COUNTER,
  59683         0,
  59684         1,
  59685         soc_GTXCF_BCM88375_A0r_fields,
  59686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59687         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59688         34,
  59689         -1,
  59690     },
  59691 #endif /* chips */
  59692 
  59693 #if defined(BCM_88375_B0)
  59694     { /* SOC_REG_INT_GTXCF_BCM88375_B0r */
  59695         soc_block_list[2],
  59696         soc_portreg,
  59697         1,
  59698         0,
  59699         0x2200,
  59700         SOC_REG_FLAG_COUNTER,
  59701         0,
  59702         1,
  59703         soc_GTXCF_BCM88375_B0r_fields,
  59704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59705         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59706         34,
  59707         -1,
  59708     },
  59709 #endif /* chips */
  59710 
  59711 #if defined(BCM_88470_A0)
  59712     { /* SOC_REG_INT_GTXCF_BCM88470_A0r */
  59713         soc_block_list[2],
  59714         soc_portreg,
  59715         1,
  59716         0,
  59717         0x2200,
  59718         SOC_REG_FLAG_COUNTER,
  59719         0,
  59720         1,
  59721         soc_GTXCF_BCM88470_A0r_fields,
  59722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59724         34,
  59725         -1,
  59726     },
  59727 #endif /* chips */
  59728 
  59729 #if defined(BCM_88470_B0)
  59730     { /* SOC_REG_INT_GTXCF_BCM88470_B0r */
  59731         soc_block_list[2],
  59732         soc_portreg,
  59733         1,
  59734         0,
  59735         0x2200,
  59736         SOC_REG_FLAG_COUNTER,
  59737         0,
  59738         1,
  59739         soc_GTXCF_BCM88470_B0r_fields,
  59740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59742         34,
  59743         -1,
  59744     },
  59745 #endif /* chips */
  59746 
  59747 #if defined(BCM_88675_A0)
  59748     { /* SOC_REG_INT_GTXCF_BCM88675_A0r */
  59749         soc_block_list[2],
  59750         soc_portreg,
  59751         1,
  59752         0,
  59753         0x2200,
  59754         SOC_REG_FLAG_COUNTER,
  59755         0,
  59756         1,
  59757         soc_GTXCFr_fields,
  59758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59760         34,
  59761         -1,
  59762     },
  59763 #endif /* chips */
  59764 
  59765 #if defined(BCM_88675_B0)
  59766     { /* SOC_REG_INT_GTXCF_BCM88675_B0r */
  59767         soc_block_list[2],
  59768         soc_portreg,
  59769         1,
  59770         0,
  59771         0x2200,
  59772         SOC_REG_FLAG_COUNTER,
  59773         0,
  59774         1,
  59775         soc_GTXCF_BCM88675_B0r_fields,
  59776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59778         34,
  59779         -1,
  59780     },
  59781 #endif /* chips */
  59782 
  59783 #if defined(BCM_88680_A0)
  59784     { /* SOC_REG_INT_GTXCF_BCM88680_A0r */
  59785         soc_block_list[2],
  59786         soc_portreg,
  59787         1,
  59788         0,
  59789         0x2200,
  59790         SOC_REG_FLAG_COUNTER,
  59791         0,
  59792         1,
  59793         soc_GTXCF_BCM88680_A0r_fields,
  59794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59796         34,
  59797         -1,
  59798     },
  59799 #endif /* chips */
  59800 
  59801 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  59802     defined(BCM_56504_B0)
  59803     { /* SOC_REG_INT_GTXCLr */
  59804         soc_block_list[2],
  59805         soc_portreg,
  59806         1,
  59807         0,
  59808         0x34,
  59809         SOC_REG_FLAG_COUNTER |
  59810                           SOC_REG_FLAG_ED_CNTR,
  59811         0,
  59812         1,
  59813         soc_GR1023r_fields,
  59814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59815         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59816         86,
  59817         -1,
  59818     },
  59819 #endif /* chips */
  59820 
  59821 #if defined(BCM_53570_A0)
  59822     { /* SOC_REG_INT_GTXCLPr */
  59823         soc_block_list[2],
  59824         soc_portreg,
  59825         1,
  59826         0,
  59827         0x8f00,
  59828         SOC_REG_FLAG_COUNTER |
  59829                           SOC_REG_FLAG_ED_CNTR,
  59830         0,
  59831         1,
  59832         soc_GR1023_BCM53400_A0r_fields,
  59833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59835         297,
  59836         -1,
  59837     },
  59838 #endif /* chips */
  59839 
  59840 #if defined(BCM_53570_B0)
  59841     { /* SOC_REG_INT_GTXCLP_BCM53570_B0r */
  59842         soc_block_list[2],
  59843         soc_portreg,
  59844         1,
  59845         0,
  59846         0x8f00,
  59847         SOC_REG_FLAG_COUNTER |
  59848                           SOC_REG_FLAG_ED_CNTR,
  59849         0,
  59850         1,
  59851         soc_GR1023_BCM53400_A0r_fields,
  59852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59854         301,
  59855         -1,
  59856     },
  59857 #endif /* chips */
  59858 
  59859 #if defined(BCM_53400_A0)
  59860     { /* SOC_REG_INT_GTXCL_BCM53400_A0r */
  59861         soc_block_list[9],
  59862         soc_portreg,
  59863         1,
  59864         0,
  59865         0x2900,
  59866         SOC_REG_FLAG_COUNTER |
  59867                           SOC_REG_FLAG_ED_CNTR,
  59868         0,
  59869         1,
  59870         soc_GR1023_BCM53400_A0r_fields,
  59871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59873         140,
  59874         -1,
  59875     },
  59876 #endif /* chips */
  59877 
  59878 #if defined(BCM_53540_A0)
  59879     { /* SOC_REG_INT_GTXCL_BCM53540_A0r */
  59880         soc_block_list[2],
  59881         soc_portreg,
  59882         1,
  59883         0,
  59884         0x3a00,
  59885         SOC_REG_FLAG_COUNTER |
  59886                           SOC_REG_FLAG_ED_CNTR,
  59887         0,
  59888         1,
  59889         soc_GR1023_BCM53400_A0r_fields,
  59890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59892         157,
  59893         -1,
  59894     },
  59895 #endif /* chips */
  59896 
  59897 #if defined(BCM_53570_A0)
  59898     { /* SOC_REG_INT_GTXCL_BCM53570_A0r */
  59899         soc_block_list[2],
  59900         soc_portreg,
  59901         1,
  59902         0,
  59903         0x3a00,
  59904         SOC_REG_FLAG_COUNTER |
  59905                           SOC_REG_FLAG_ED_CNTR,
  59906         0,
  59907         1,
  59908         soc_GR1023_BCM53400_A0r_fields,
  59909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59910         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59911         212,
  59912         -1,
  59913     },
  59914 #endif /* chips */
  59915 
  59916 #if defined(BCM_53570_B0)
  59917     { /* SOC_REG_INT_GTXCL_BCM53570_B0r */
  59918         soc_block_list[2],
  59919         soc_portreg,
  59920         1,
  59921         0,
  59922         0x3a00,
  59923         SOC_REG_FLAG_COUNTER |
  59924                           SOC_REG_FLAG_ED_CNTR,
  59925         0,
  59926         1,
  59927         soc_GR1023_BCM53400_A0r_fields,
  59928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59929         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59930         216,
  59931         -1,
  59932     },
  59933 #endif /* chips */
  59934 
  59935 #if defined(BCM_56142_A0)
  59936     { /* SOC_REG_INT_GTXCL_BCM56142_A0r */
  59937         soc_block_list[210],
  59938         soc_portreg,
  59939         1,
  59940         0,
  59941         0xa9,
  59942         SOC_REG_FLAG_COUNTER |
  59943                           SOC_REG_FLAG_ED_CNTR,
  59944         0,
  59945         1,
  59946         soc_GR1023r_fields,
  59947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59948         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59949         216,
  59950         -1,
  59951     },
  59952 #endif /* chips */
  59953 
  59954 #if defined(BCM_56150_A0)
  59955     { /* SOC_REG_INT_GTXCL_BCM56150_A0r */
  59956         soc_block_list[2],
  59957         soc_portreg,
  59958         1,
  59959         0,
  59960         0x2900,
  59961         SOC_REG_FLAG_COUNTER |
  59962                           SOC_REG_FLAG_ED_CNTR,
  59963         0,
  59964         1,
  59965         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  59966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59967         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59968         136,
  59969         -1,
  59970     },
  59971 #endif /* chips */
  59972 
  59973 #if defined(BCM_56160_A0)
  59974     { /* SOC_REG_INT_GTXCL_BCM56160_A0r */
  59975         soc_block_list[2],
  59976         soc_portreg,
  59977         1,
  59978         0,
  59979         0x3a00,
  59980         SOC_REG_FLAG_COUNTER |
  59981                           SOC_REG_FLAG_ED_CNTR,
  59982         0,
  59983         1,
  59984         soc_GR1023_BCM53400_A0r_fields,
  59985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59986         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59987         157,
  59988         -1,
  59989     },
  59990 #endif /* chips */
  59991 
  59992 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  59993     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  59994     { /* SOC_REG_INT_GTXCL_BCM56224_A0r */
  59995         soc_block_list[2],
  59996         soc_portreg,
  59997         1,
  59998         0,
  59999         0x29,
  60000         SOC_REG_FLAG_COUNTER |
  60001                           SOC_REG_FLAG_ED_CNTR,
  60002         0,
  60003         1,
  60004         soc_GR1023r_fields,
  60005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60006         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60007         75,
  60008         -1,
  60009     },
  60010 #endif /* chips */
  60011 
  60012 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  60013     { /* SOC_REG_INT_GTXCL_BCM56334_A0r */
  60014         soc_block_list[210],
  60015         soc_portreg,
  60016         1,
  60017         0,
  60018         0xa9,
  60019         SOC_REG_FLAG_COUNTER |
  60020                           SOC_REG_FLAG_ED_CNTR,
  60021         0,
  60022         1,
  60023         soc_GR1023r_fields,
  60024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60026         211,
  60027         -1,
  60028     },
  60029 #endif /* chips */
  60030 
  60031 #if defined(BCM_56370_A0)
  60032     { /* SOC_REG_INT_GTXCL_BCM56370_A0r */
  60033         soc_block_list[9],
  60034         soc_portreg,
  60035         1,
  60036         0,
  60037         0x2a00,
  60038         SOC_REG_FLAG_COUNTER |
  60039                           SOC_REG_FLAG_ED_CNTR,
  60040         0,
  60041         1,
  60042         soc_GR1023_BCM53400_A0r_fields,
  60043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60044         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60045         102,
  60046         -1,
  60047         3,
  60048     },
  60049 #endif /* chips */
  60050 
  60051 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  60052     { /* SOC_REG_INT_GTXCL_BCM56440_A0r */
  60053         soc_block_list[2],
  60054         soc_portreg,
  60055         1,
  60056         0,
  60057         0xaa,
  60058         SOC_REG_FLAG_COUNTER |
  60059                           SOC_REG_FLAG_ED_CNTR,
  60060         0,
  60061         1,
  60062         soc_GR1023r_fields,
  60063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60064         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60065         209,
  60066         -1,
  60067     },
  60068 #endif /* chips */
  60069 
  60070 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  60071     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  60072     { /* SOC_REG_INT_GTXCL_BCM56624_A0r */
  60073         soc_block_list[205],
  60074         soc_portreg,
  60075         1,
  60076         0,
  60077         0xb6,
  60078         SOC_REG_FLAG_COUNTER |
  60079                           SOC_REG_FLAG_ED_CNTR,
  60080         0,
  60081         1,
  60082         soc_GR1023r_fields,
  60083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60084         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60085         224,
  60086         -1,
  60087     },
  60088 #endif /* chips */
  60089 
  60090 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  60091     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  60092     { /* SOC_REG_INT_GTXCL_BCM56634_A0r */
  60093         soc_block_list[207],
  60094         soc_portreg,
  60095         1,
  60096         0,
  60097         0xb6,
  60098         SOC_REG_FLAG_COUNTER |
  60099                           SOC_REG_FLAG_ED_CNTR,
  60100         0,
  60101         1,
  60102         soc_GR1023r_fields,
  60103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60105         224,
  60106         -1,
  60107     },
  60108 #endif /* chips */
  60109 
  60110 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  60111     { /* SOC_REG_INT_GTXCL_BCM56685_A0r */
  60112         soc_block_list[209],
  60113         soc_portreg,
  60114         1,
  60115         0,
  60116         0xb6,
  60117         SOC_REG_FLAG_COUNTER |
  60118                           SOC_REG_FLAG_ED_CNTR,
  60119         0,
  60120         1,
  60121         soc_GR1023r_fields,
  60122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60124         224,
  60125         -1,
  60126     },
  60127 #endif /* chips */
  60128 
  60129 #if defined(BCM_56800_A0)
  60130     { /* SOC_REG_INT_GTXCL_BCM56800_A0r */
  60131         soc_block_list[9],
  60132         soc_portreg,
  60133         1,
  60134         0,
  60135         0x7b,
  60136         SOC_REG_FLAG_COUNTER |
  60137                           SOC_REG_FLAG_ED_CNTR,
  60138         0,
  60139         1,
  60140         soc_GR1023r_fields,
  60141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60142         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60143         165,
  60144         -1,
  60145     },
  60146 #endif /* chips */
  60147 
  60148 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  60149     { /* SOC_REG_INT_GTXCL_BCM56820_A0r */
  60150         soc_block_list[206],
  60151         soc_portreg,
  60152         1,
  60153         0,
  60154         0xb7,
  60155         SOC_REG_FLAG_COUNTER |
  60156                           SOC_REG_FLAG_ED_CNTR,
  60157         0,
  60158         1,
  60159         soc_GR1023r_fields,
  60160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60162         235,
  60163         -1,
  60164     },
  60165 #endif /* chips */
  60166 
  60167 #if defined(BCM_88375_A0)
  60168     { /* SOC_REG_INT_GTXCL_BCM88375_A0r */
  60169         soc_block_list[2],
  60170         soc_portreg,
  60171         1,
  60172         0,
  60173         0x2900,
  60174         SOC_REG_FLAG_COUNTER,
  60175         0,
  60176         1,
  60177         soc_GTXCL_BCM88375_A0r_fields,
  60178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60179         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60180         41,
  60181         -1,
  60182     },
  60183 #endif /* chips */
  60184 
  60185 #if defined(BCM_88375_B0)
  60186     { /* SOC_REG_INT_GTXCL_BCM88375_B0r */
  60187         soc_block_list[2],
  60188         soc_portreg,
  60189         1,
  60190         0,
  60191         0x2900,
  60192         SOC_REG_FLAG_COUNTER,
  60193         0,
  60194         1,
  60195         soc_GTXCL_BCM88375_B0r_fields,
  60196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60198         41,
  60199         -1,
  60200     },
  60201 #endif /* chips */
  60202 
  60203 #if defined(BCM_88470_A0)
  60204     { /* SOC_REG_INT_GTXCL_BCM88470_A0r */
  60205         soc_block_list[2],
  60206         soc_portreg,
  60207         1,
  60208         0,
  60209         0x2900,
  60210         SOC_REG_FLAG_COUNTER,
  60211         0,
  60212         1,
  60213         soc_GTXCL_BCM88470_A0r_fields,
  60214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60215         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60216         41,
  60217         -1,
  60218     },
  60219 #endif /* chips */
  60220 
  60221 #if defined(BCM_88470_B0)
  60222     { /* SOC_REG_INT_GTXCL_BCM88470_B0r */
  60223         soc_block_list[2],
  60224         soc_portreg,
  60225         1,
  60226         0,
  60227         0x2900,
  60228         SOC_REG_FLAG_COUNTER,
  60229         0,
  60230         1,
  60231         soc_GTXCL_BCM88470_B0r_fields,
  60232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60233         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60234         41,
  60235         -1,
  60236     },
  60237 #endif /* chips */
  60238 
  60239 #if defined(BCM_88675_A0)
  60240     { /* SOC_REG_INT_GTXCL_BCM88675_A0r */
  60241         soc_block_list[2],
  60242         soc_portreg,
  60243         1,
  60244         0,
  60245         0x2900,
  60246         SOC_REG_FLAG_COUNTER,
  60247         0,
  60248         1,
  60249         soc_GTXCLr_fields,
  60250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60251         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60252         41,
  60253         -1,
  60254     },
  60255 #endif /* chips */
  60256 
  60257 #if defined(BCM_88675_B0)
  60258     { /* SOC_REG_INT_GTXCL_BCM88675_B0r */
  60259         soc_block_list[2],
  60260         soc_portreg,
  60261         1,
  60262         0,
  60263         0x2900,
  60264         SOC_REG_FLAG_COUNTER,
  60265         0,
  60266         1,
  60267         soc_GTXCL_BCM88675_B0r_fields,
  60268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60269         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60270         41,
  60271         -1,
  60272     },
  60273 #endif /* chips */
  60274 
  60275 #if defined(BCM_88680_A0)
  60276     { /* SOC_REG_INT_GTXCL_BCM88680_A0r */
  60277         soc_block_list[2],
  60278         soc_portreg,
  60279         1,
  60280         0,
  60281         0x2900,
  60282         SOC_REG_FLAG_COUNTER,
  60283         0,
  60284         1,
  60285         soc_GTXCL_BCM88680_A0r_fields,
  60286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60288         41,
  60289         -1,
  60290     },
  60291 #endif /* chips */
  60292 
  60293 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  60294     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  60295     { /* SOC_REG_INT_GTXPFr */
  60296         soc_block_list[2],
  60297         soc_portreg,
  60298         1,
  60299         0,
  60300         0x2a,
  60301         SOC_REG_FLAG_COUNTER,
  60302         0,
  60303         1,
  60304         soc_GR1023r_fields,
  60305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60307         76,
  60308         -1,
  60309     },
  60310 #endif /* chips */
  60311 
  60312 #if defined(BCM_53400_A0)
  60313     { /* SOC_REG_INT_GTXPF_BCM53400_A0r */
  60314         soc_block_list[9],
  60315         soc_portreg,
  60316         1,
  60317         0,
  60318         0x1f00,
  60319         SOC_REG_FLAG_COUNTER,
  60320         0,
  60321         1,
  60322         soc_GR1023_BCM53400_A0r_fields,
  60323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60324         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60325         130,
  60326         -1,
  60327     },
  60328 #endif /* chips */
  60329 
  60330 #if defined(BCM_53540_A0)
  60331     { /* SOC_REG_INT_GTXPF_BCM53540_A0r */
  60332         soc_block_list[2],
  60333         soc_portreg,
  60334         1,
  60335         0,
  60336         0x3000,
  60337         SOC_REG_FLAG_COUNTER,
  60338         0,
  60339         1,
  60340         soc_GR1023_BCM53400_A0r_fields,
  60341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60342         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60343         147,
  60344         -1,
  60345     },
  60346 #endif /* chips */
  60347 
  60348 #if defined(BCM_53570_A0)
  60349     { /* SOC_REG_INT_GTXPF_BCM53570_A0r */
  60350         soc_block_list[2],
  60351         soc_portreg,
  60352         1,
  60353         0,
  60354         0x3000,
  60355         SOC_REG_FLAG_COUNTER,
  60356         0,
  60357         1,
  60358         soc_GR1023_BCM53400_A0r_fields,
  60359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60360         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60361         202,
  60362         -1,
  60363     },
  60364 #endif /* chips */
  60365 
  60366 #if defined(BCM_53570_B0)
  60367     { /* SOC_REG_INT_GTXPF_BCM53570_B0r */
  60368         soc_block_list[2],
  60369         soc_portreg,
  60370         1,
  60371         0,
  60372         0x3000,
  60373         SOC_REG_FLAG_COUNTER,
  60374         0,
  60375         1,
  60376         soc_GR1023_BCM53400_A0r_fields,
  60377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60378         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60379         206,
  60380         -1,
  60381     },
  60382 #endif /* chips */
  60383 
  60384 #if defined(BCM_56142_A0)
  60385     { /* SOC_REG_INT_GTXPF_BCM56142_A0r */
  60386         soc_block_list[210],
  60387         soc_portreg,
  60388         1,
  60389         0,
  60390         0x9f,
  60391         SOC_REG_FLAG_COUNTER,
  60392         0,
  60393         1,
  60394         soc_GR1023r_fields,
  60395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60397         206,
  60398         -1,
  60399     },
  60400 #endif /* chips */
  60401 
  60402 #if defined(BCM_56150_A0)
  60403     { /* SOC_REG_INT_GTXPF_BCM56150_A0r */
  60404         soc_block_list[2],
  60405         soc_portreg,
  60406         1,
  60407         0,
  60408         0x1f00,
  60409         SOC_REG_FLAG_COUNTER,
  60410         0,
  60411         1,
  60412         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  60413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60414         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60415         126,
  60416         -1,
  60417     },
  60418 #endif /* chips */
  60419 
  60420 #if defined(BCM_56160_A0)
  60421     { /* SOC_REG_INT_GTXPF_BCM56160_A0r */
  60422         soc_block_list[2],
  60423         soc_portreg,
  60424         1,
  60425         0,
  60426         0x3000,
  60427         SOC_REG_FLAG_COUNTER,
  60428         0,
  60429         1,
  60430         soc_GR1023_BCM53400_A0r_fields,
  60431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60433         147,
  60434         -1,
  60435     },
  60436 #endif /* chips */
  60437 
  60438 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  60439     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  60440     { /* SOC_REG_INT_GTXPF_BCM56224_A0r */
  60441         soc_block_list[2],
  60442         soc_portreg,
  60443         1,
  60444         0,
  60445         0x1f,
  60446         SOC_REG_FLAG_COUNTER,
  60447         0,
  60448         1,
  60449         soc_GR1023r_fields,
  60450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60451         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60452         65,
  60453         -1,
  60454     },
  60455 #endif /* chips */
  60456 
  60457 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  60458     { /* SOC_REG_INT_GTXPF_BCM56334_A0r */
  60459         soc_block_list[210],
  60460         soc_portreg,
  60461         1,
  60462         0,
  60463         0x9f,
  60464         SOC_REG_FLAG_COUNTER,
  60465         0,
  60466         1,
  60467         soc_GR1023r_fields,
  60468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60469         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60470         201,
  60471         -1,
  60472     },
  60473 #endif /* chips */
  60474 
  60475 #if defined(BCM_56370_A0)
  60476     { /* SOC_REG_INT_GTXPF_BCM56370_A0r */
  60477         soc_block_list[9],
  60478         soc_portreg,
  60479         1,
  60480         0,
  60481         0x2000,
  60482         SOC_REG_FLAG_COUNTER,
  60483         0,
  60484         1,
  60485         soc_GR1023_BCM53400_A0r_fields,
  60486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60488         92,
  60489         -1,
  60490         3,
  60491     },
  60492 #endif /* chips */
  60493 
  60494 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  60495     { /* SOC_REG_INT_GTXPF_BCM56440_A0r */
  60496         soc_block_list[2],
  60497         soc_portreg,
  60498         1,
  60499         0,
  60500         0xa0,
  60501         SOC_REG_FLAG_COUNTER,
  60502         0,
  60503         1,
  60504         soc_GR1023r_fields,
  60505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60506         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60507         199,
  60508         -1,
  60509     },
  60510 #endif /* chips */
  60511 
  60512 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  60513     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
  60514     defined(BCM_56514_A0)
  60515     { /* SOC_REG_INT_GTXPF_BCM56514_A0r */
  60516         soc_block_list[2],
  60517         soc_portreg,
  60518         1,
  60519         0,
  60520         0x2c,
  60521         SOC_REG_FLAG_COUNTER,
  60522         0,
  60523         1,
  60524         soc_GR1023r_fields,
  60525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60526         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60527         78,
  60528         -1,
  60529     },
  60530 #endif /* chips */
  60531 
  60532 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  60533     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  60534     { /* SOC_REG_INT_GTXPF_BCM56624_A0r */
  60535         soc_block_list[205],
  60536         soc_portreg,
  60537         1,
  60538         0,
  60539         0xac,
  60540         SOC_REG_FLAG_COUNTER,
  60541         0,
  60542         1,
  60543         soc_GR1023r_fields,
  60544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60545         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60546         214,
  60547         -1,
  60548     },
  60549 #endif /* chips */
  60550 
  60551 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  60552     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  60553     { /* SOC_REG_INT_GTXPF_BCM56634_A0r */
  60554         soc_block_list[207],
  60555         soc_portreg,
  60556         1,
  60557         0,
  60558         0xac,
  60559         SOC_REG_FLAG_COUNTER,
  60560         0,
  60561         1,
  60562         soc_GR1023r_fields,
  60563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60564         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60565         214,
  60566         -1,
  60567     },
  60568 #endif /* chips */
  60569 
  60570 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  60571     { /* SOC_REG_INT_GTXPF_BCM56685_A0r */
  60572         soc_block_list[209],
  60573         soc_portreg,
  60574         1,
  60575         0,
  60576         0xac,
  60577         SOC_REG_FLAG_COUNTER,
  60578         0,
  60579         1,
  60580         soc_GR1023r_fields,
  60581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60582         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60583         214,
  60584         -1,
  60585     },
  60586 #endif /* chips */
  60587 
  60588 #if defined(BCM_56800_A0)
  60589     { /* SOC_REG_INT_GTXPF_BCM56800_A0r */
  60590         soc_block_list[9],
  60591         soc_portreg,
  60592         1,
  60593         0,
  60594         0x71,
  60595         SOC_REG_FLAG_COUNTER,
  60596         0,
  60597         1,
  60598         soc_GR1023r_fields,
  60599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60600         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60601         155,
  60602         -1,
  60603     },
  60604 #endif /* chips */
  60605 
  60606 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  60607     { /* SOC_REG_INT_GTXPF_BCM56820_A0r */
  60608         soc_block_list[206],
  60609         soc_portreg,
  60610         1,
  60611         0,
  60612         0xad,
  60613         SOC_REG_FLAG_COUNTER,
  60614         0,
  60615         1,
  60616         soc_GR1023r_fields,
  60617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60618         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60619         225,
  60620         -1,
  60621     },
  60622 #endif /* chips */
  60623 
  60624 #if defined(BCM_88375_A0)
  60625     { /* SOC_REG_INT_GTXPF_BCM88375_A0r */
  60626         soc_block_list[2],
  60627         soc_portreg,
  60628         1,
  60629         0,
  60630         0x1f00,
  60631         SOC_REG_FLAG_COUNTER,
  60632         0,
  60633         1,
  60634         soc_GTXPF_BCM88375_A0r_fields,
  60635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60637         31,
  60638         -1,
  60639     },
  60640 #endif /* chips */
  60641 
  60642 #if defined(BCM_88375_B0)
  60643     { /* SOC_REG_INT_GTXPF_BCM88375_B0r */
  60644         soc_block_list[2],
  60645         soc_portreg,
  60646         1,
  60647         0,
  60648         0x1f00,
  60649         SOC_REG_FLAG_COUNTER,
  60650         0,
  60651         1,
  60652         soc_GTXPF_BCM88375_B0r_fields,
  60653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60654         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60655         31,
  60656         -1,
  60657     },
  60658 #endif /* chips */
  60659 
  60660 #if defined(BCM_88470_A0)
  60661     { /* SOC_REG_INT_GTXPF_BCM88470_A0r */
  60662         soc_block_list[2],
  60663         soc_portreg,
  60664         1,
  60665         0,
  60666         0x1f00,
  60667         SOC_REG_FLAG_COUNTER,
  60668         0,
  60669         1,
  60670         soc_GTXPF_BCM88470_A0r_fields,
  60671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60672         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60673         31,
  60674         -1,
  60675     },
  60676 #endif /* chips */
  60677 
  60678 #if defined(BCM_88470_B0)
  60679     { /* SOC_REG_INT_GTXPF_BCM88470_B0r */
  60680         soc_block_list[2],
  60681         soc_portreg,
  60682         1,
  60683         0,
  60684         0x1f00,
  60685         SOC_REG_FLAG_COUNTER,
  60686         0,
  60687         1,
  60688         soc_GTXPF_BCM88470_B0r_fields,
  60689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60690         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60691         31,
  60692         -1,
  60693     },
  60694 #endif /* chips */
  60695 
  60696 #if defined(BCM_88675_A0)
  60697     { /* SOC_REG_INT_GTXPF_BCM88675_A0r */
  60698         soc_block_list[2],
  60699         soc_portreg,
  60700         1,
  60701         0,
  60702         0x1f00,
  60703         SOC_REG_FLAG_COUNTER,
  60704         0,
  60705         1,
  60706         soc_GTXPFr_fields,
  60707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60708         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60709         31,
  60710         -1,
  60711     },
  60712 #endif /* chips */
  60713 
  60714 #if defined(BCM_88675_B0)
  60715     { /* SOC_REG_INT_GTXPF_BCM88675_B0r */
  60716         soc_block_list[2],
  60717         soc_portreg,
  60718         1,
  60719         0,
  60720         0x1f00,
  60721         SOC_REG_FLAG_COUNTER,
  60722         0,
  60723         1,
  60724         soc_GTXPF_BCM88675_B0r_fields,
  60725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60726         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60727         31,
  60728         -1,
  60729     },
  60730 #endif /* chips */
  60731 
  60732 #if defined(BCM_88680_A0)
  60733     { /* SOC_REG_INT_GTXPF_BCM88680_A0r */
  60734         soc_block_list[2],
  60735         soc_portreg,
  60736         1,
  60737         0,
  60738         0x1f00,
  60739         SOC_REG_FLAG_COUNTER,
  60740         0,
  60741         1,
  60742         soc_GTXPF_BCM88680_A0r_fields,
  60743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60744         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60745         31,
  60746         -1,
  60747     },
  60748 #endif /* chips */
  60749 
  60750 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  60751     { /* SOC_REG_INT_GTXPPr */
  60752         soc_block_list[206],
  60753         soc_portreg,
  60754         1,
  60755         0,
  60756         0xbd,
  60757         SOC_REG_FLAG_COUNTER |
  60758                           SOC_REG_FLAG_ED_CNTR,
  60759         0,
  60760         1,
  60761         soc_GR1023r_fields,
  60762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60764         241,
  60765         -1,
  60766     },
  60767 #endif /* chips */
  60768 
  60769 #if defined(BCM_53540_A0)
  60770     { /* SOC_REG_INT_GTXPP_BCM53540_A0r */
  60771         soc_block_list[2],
  60772         soc_portreg,
  60773         1,
  60774         0,
  60775         0x4d00,
  60776         SOC_REG_FLAG_COUNTER,
  60777         0,
  60778         1,
  60779         soc_GR1023_BCM53400_A0r_fields,
  60780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60782         176,
  60783         -1,
  60784     },
  60785 #endif /* chips */
  60786 
  60787 #if defined(BCM_53570_A0)
  60788     { /* SOC_REG_INT_GTXPP_BCM53570_A0r */
  60789         soc_block_list[2],
  60790         soc_portreg,
  60791         1,
  60792         0,
  60793         0x4d00,
  60794         SOC_REG_FLAG_COUNTER,
  60795         0,
  60796         1,
  60797         soc_GR1023_BCM53400_A0r_fields,
  60798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60800         231,
  60801         -1,
  60802     },
  60803 #endif /* chips */
  60804 
  60805 #if defined(BCM_53570_B0)
  60806     { /* SOC_REG_INT_GTXPP_BCM53570_B0r */
  60807         soc_block_list[2],
  60808         soc_portreg,
  60809         1,
  60810         0,
  60811         0x4d00,
  60812         SOC_REG_FLAG_COUNTER,
  60813         0,
  60814         1,
  60815         soc_GR1023_BCM53400_A0r_fields,
  60816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60818         235,
  60819         -1,
  60820     },
  60821 #endif /* chips */
  60822 
  60823 #if defined(BCM_56160_A0)
  60824     { /* SOC_REG_INT_GTXPP_BCM56160_A0r */
  60825         soc_block_list[2],
  60826         soc_portreg,
  60827         1,
  60828         0,
  60829         0x4d00,
  60830         SOC_REG_FLAG_COUNTER,
  60831         0,
  60832         1,
  60833         soc_GR1023_BCM53400_A0r_fields,
  60834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60835         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60836         176,
  60837         -1,
  60838     },
  60839 #endif /* chips */
  60840 
  60841 #if defined(BCM_88675_A0)
  60842     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTERr */
  60843         soc_block_list[2],
  60844         soc_portreg,
  60845         1,
  60846         0,
  60847         0x3f00,
  60848         SOC_REG_FLAG_COUNTER,
  60849         0,
  60850         1,
  60851         soc_GTX_EEE_LPI_DURATION_COUNTERr_fields,
  60852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60854         63,
  60855         -1,
  60856     },
  60857 #endif /* chips */
  60858 
  60859 #if defined(BCM_53400_A0)
  60860     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM53400_A0r */
  60861         soc_block_list[9],
  60862         soc_portreg,
  60863         1,
  60864         0,
  60865         0x3f00,
  60866         SOC_REG_FLAG_COUNTER,
  60867         0,
  60868         1,
  60869         soc_GR1023_BCM53400_A0r_fields,
  60870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60872         162,
  60873         -1,
  60874     },
  60875 #endif /* chips */
  60876 
  60877 #if defined(BCM_53540_A0)
  60878     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM53540_A0r */
  60879         soc_block_list[2],
  60880         soc_portreg,
  60881         1,
  60882         0,
  60883         0x5900,
  60884         SOC_REG_FLAG_COUNTER,
  60885         0,
  60886         1,
  60887         soc_GR1023_BCM53400_A0r_fields,
  60888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60889         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60890         188,
  60891         -1,
  60892     },
  60893 #endif /* chips */
  60894 
  60895 #if defined(BCM_53570_A0)
  60896     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM53570_A0r */
  60897         soc_block_list[2],
  60898         soc_portreg,
  60899         1,
  60900         0,
  60901         0x6100,
  60902         SOC_REG_FLAG_COUNTER,
  60903         0,
  60904         1,
  60905         soc_GR1023_BCM53400_A0r_fields,
  60906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60907         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60908         251,
  60909         -1,
  60910     },
  60911 #endif /* chips */
  60912 
  60913 #if defined(BCM_53570_B0)
  60914     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM53570_B0r */
  60915         soc_block_list[2],
  60916         soc_portreg,
  60917         1,
  60918         0,
  60919         0x6100,
  60920         SOC_REG_FLAG_COUNTER,
  60921         0,
  60922         1,
  60923         soc_GR1023_BCM53400_A0r_fields,
  60924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60926         255,
  60927         -1,
  60928     },
  60929 #endif /* chips */
  60930 
  60931 #if defined(BCM_56150_A0)
  60932     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM56150_A0r */
  60933         soc_block_list[2],
  60934         soc_portreg,
  60935         1,
  60936         0,
  60937         0x3f00,
  60938         SOC_REG_FLAG_COUNTER,
  60939         0,
  60940         1,
  60941         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  60942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60943         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60944         158,
  60945         -1,
  60946     },
  60947 #endif /* chips */
  60948 
  60949 #if defined(BCM_56160_A0)
  60950     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM56160_A0r */
  60951         soc_block_list[2],
  60952         soc_portreg,
  60953         1,
  60954         0,
  60955         0x5900,
  60956         SOC_REG_FLAG_COUNTER,
  60957         0,
  60958         1,
  60959         soc_GR1023_BCM53400_A0r_fields,
  60960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60961         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60962         188,
  60963         -1,
  60964     },
  60965 #endif /* chips */
  60966 
  60967 #if defined(BCM_56370_A0)
  60968     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM56370_A0r */
  60969         soc_block_list[9],
  60970         soc_portreg,
  60971         1,
  60972         0,
  60973         0x4100,
  60974         SOC_REG_FLAG_COUNTER,
  60975         0,
  60976         1,
  60977         soc_GR1023_BCM53400_A0r_fields,
  60978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60979         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60980         125,
  60981         -1,
  60982         3,
  60983     },
  60984 #endif /* chips */
  60985 
  60986 #if defined(BCM_88375_A0)
  60987     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM88375_A0r */
  60988         soc_block_list[2],
  60989         soc_portreg,
  60990         1,
  60991         0,
  60992         0x3f00,
  60993         SOC_REG_FLAG_COUNTER,
  60994         0,
  60995         1,
  60996         soc_GTX_EEE_LPI_DURATION_COUNTER_BCM88375_A0r_fields,
  60997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60998         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60999         63,
  61000         -1,
  61001     },
  61002 #endif /* chips */
  61003 
  61004 #if defined(BCM_88375_B0)
  61005     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM88375_B0r */
  61006         soc_block_list[2],
  61007         soc_portreg,
  61008         1,
  61009         0,
  61010         0x3f00,
  61011         SOC_REG_FLAG_COUNTER,
  61012         0,
  61013         1,
  61014         soc_GTX_EEE_LPI_DURATION_COUNTER_BCM88375_B0r_fields,
  61015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61016         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61017         63,
  61018         -1,
  61019     },
  61020 #endif /* chips */
  61021 
  61022 #if defined(BCM_88470_A0)
  61023     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM88470_A0r */
  61024         soc_block_list[2],
  61025         soc_portreg,
  61026         1,
  61027         0,
  61028         0x3f00,
  61029         SOC_REG_FLAG_COUNTER,
  61030         0,
  61031         1,
  61032         soc_GTX_EEE_LPI_DURATION_COUNTER_BCM88470_A0r_fields,
  61033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61034         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61035         63,
  61036         -1,
  61037     },
  61038 #endif /* chips */
  61039 
  61040 #if defined(BCM_88470_B0)
  61041     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM88470_B0r */
  61042         soc_block_list[2],
  61043         soc_portreg,
  61044         1,
  61045         0,
  61046         0x3f00,
  61047         SOC_REG_FLAG_COUNTER,
  61048         0,
  61049         1,
  61050         soc_GTX_EEE_LPI_DURATION_COUNTER_BCM88470_B0r_fields,
  61051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61052         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61053         63,
  61054         -1,
  61055     },
  61056 #endif /* chips */
  61057 
  61058 #if defined(BCM_88675_B0)
  61059     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM88675_B0r */
  61060         soc_block_list[2],
  61061         soc_portreg,
  61062         1,
  61063         0,
  61064         0x3f00,
  61065         SOC_REG_FLAG_COUNTER,
  61066         0,
  61067         1,
  61068         soc_GTX_EEE_LPI_DURATION_COUNTER_BCM88675_B0r_fields,
  61069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61070         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61071         63,
  61072         -1,
  61073     },
  61074 #endif /* chips */
  61075 
  61076 #if defined(BCM_88680_A0)
  61077     { /* SOC_REG_INT_GTX_EEE_LPI_DURATION_COUNTER_BCM88680_A0r */
  61078         soc_block_list[2],
  61079         soc_portreg,
  61080         1,
  61081         0,
  61082         0x3f00,
  61083         SOC_REG_FLAG_COUNTER,
  61084         0,
  61085         1,
  61086         soc_GTX_EEE_LPI_DURATION_COUNTER_BCM88680_A0r_fields,
  61087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61088         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61089         63,
  61090         -1,
  61091     },
  61092 #endif /* chips */
  61093 
  61094 #if defined(BCM_88675_A0)
  61095     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTERr */
  61096         soc_block_list[2],
  61097         soc_portreg,
  61098         1,
  61099         0,
  61100         0x3e00,
  61101         SOC_REG_FLAG_COUNTER,
  61102         0,
  61103         1,
  61104         soc_GTX_EEE_LPI_EVENT_COUNTERr_fields,
  61105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61106         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61107         62,
  61108         -1,
  61109     },
  61110 #endif /* chips */
  61111 
  61112 #if defined(BCM_53400_A0)
  61113     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM53400_A0r */
  61114         soc_block_list[9],
  61115         soc_portreg,
  61116         1,
  61117         0,
  61118         0x3e00,
  61119         SOC_REG_FLAG_COUNTER,
  61120         0,
  61121         1,
  61122         soc_GR1023_BCM53400_A0r_fields,
  61123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61124         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61125         161,
  61126         -1,
  61127     },
  61128 #endif /* chips */
  61129 
  61130 #if defined(BCM_53540_A0)
  61131     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM53540_A0r */
  61132         soc_block_list[2],
  61133         soc_portreg,
  61134         1,
  61135         0,
  61136         0x5800,
  61137         SOC_REG_FLAG_COUNTER,
  61138         0,
  61139         1,
  61140         soc_GR1023_BCM53400_A0r_fields,
  61141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61142         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61143         187,
  61144         -1,
  61145     },
  61146 #endif /* chips */
  61147 
  61148 #if defined(BCM_53570_A0)
  61149     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM53570_A0r */
  61150         soc_block_list[2],
  61151         soc_portreg,
  61152         1,
  61153         0,
  61154         0x6000,
  61155         SOC_REG_FLAG_COUNTER,
  61156         0,
  61157         1,
  61158         soc_GR1023_BCM53400_A0r_fields,
  61159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61161         250,
  61162         -1,
  61163     },
  61164 #endif /* chips */
  61165 
  61166 #if defined(BCM_53570_B0)
  61167     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM53570_B0r */
  61168         soc_block_list[2],
  61169         soc_portreg,
  61170         1,
  61171         0,
  61172         0x6000,
  61173         SOC_REG_FLAG_COUNTER,
  61174         0,
  61175         1,
  61176         soc_GR1023_BCM53400_A0r_fields,
  61177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61178         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61179         254,
  61180         -1,
  61181     },
  61182 #endif /* chips */
  61183 
  61184 #if defined(BCM_56150_A0)
  61185     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM56150_A0r */
  61186         soc_block_list[2],
  61187         soc_portreg,
  61188         1,
  61189         0,
  61190         0x3e00,
  61191         SOC_REG_FLAG_COUNTER,
  61192         0,
  61193         1,
  61194         soc_RX_EEE_LPI_DURATION_COUNTER_BCM56450_A0r_fields,
  61195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61196         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61197         157,
  61198         -1,
  61199     },
  61200 #endif /* chips */
  61201 
  61202 #if defined(BCM_56160_A0)
  61203     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM56160_A0r */
  61204         soc_block_list[2],
  61205         soc_portreg,
  61206         1,
  61207         0,
  61208         0x5800,
  61209         SOC_REG_FLAG_COUNTER,
  61210         0,
  61211         1,
  61212         soc_GR1023_BCM53400_A0r_fields,
  61213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61214         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61215         187,
  61216         -1,
  61217     },
  61218 #endif /* chips */
  61219 
  61220 #if defined(BCM_56370_A0)
  61221     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM56370_A0r */
  61222         soc_block_list[9],
  61223         soc_portreg,
  61224         1,
  61225         0,
  61226         0x4000,
  61227         SOC_REG_FLAG_COUNTER,
  61228         0,
  61229         1,
  61230         soc_GR1023_BCM53400_A0r_fields,
  61231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61233         124,
  61234         -1,
  61235         3,
  61236     },
  61237 #endif /* chips */
  61238 
  61239 #if defined(BCM_88375_A0)
  61240     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM88375_A0r */
  61241         soc_block_list[2],
  61242         soc_portreg,
  61243         1,
  61244         0,
  61245         0x3e00,
  61246         SOC_REG_FLAG_COUNTER,
  61247         0,
  61248         1,
  61249         soc_GTX_EEE_LPI_EVENT_COUNTER_BCM88375_A0r_fields,
  61250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61251         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61252         62,
  61253         -1,
  61254     },
  61255 #endif /* chips */
  61256 
  61257 #if defined(BCM_88375_B0)
  61258     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM88375_B0r */
  61259         soc_block_list[2],
  61260         soc_portreg,
  61261         1,
  61262         0,
  61263         0x3e00,
  61264         SOC_REG_FLAG_COUNTER,
  61265         0,
  61266         1,
  61267         soc_GTX_EEE_LPI_EVENT_COUNTER_BCM88375_B0r_fields,
  61268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61269         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61270         62,
  61271         -1,
  61272     },
  61273 #endif /* chips */
  61274 
  61275 #if defined(BCM_88470_A0)
  61276     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM88470_A0r */
  61277         soc_block_list[2],
  61278         soc_portreg,
  61279         1,
  61280         0,
  61281         0x3e00,
  61282         SOC_REG_FLAG_COUNTER,
  61283         0,
  61284         1,
  61285         soc_GTX_EEE_LPI_EVENT_COUNTER_BCM88470_A0r_fields,
  61286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61288         62,
  61289         -1,
  61290     },
  61291 #endif /* chips */
  61292 
  61293 #if defined(BCM_88470_B0)
  61294     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM88470_B0r */
  61295         soc_block_list[2],
  61296         soc_portreg,
  61297         1,
  61298         0,
  61299         0x3e00,
  61300         SOC_REG_FLAG_COUNTER,
  61301         0,
  61302         1,
  61303         soc_GTX_EEE_LPI_EVENT_COUNTER_BCM88470_B0r_fields,
  61304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61306         62,
  61307         -1,
  61308     },
  61309 #endif /* chips */
  61310 
  61311 #if defined(BCM_88675_B0)
  61312     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM88675_B0r */
  61313         soc_block_list[2],
  61314         soc_portreg,
  61315         1,
  61316         0,
  61317         0x3e00,
  61318         SOC_REG_FLAG_COUNTER,
  61319         0,
  61320         1,
  61321         soc_GTX_EEE_LPI_EVENT_COUNTER_BCM88675_B0r_fields,
  61322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61323         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61324         62,
  61325         -1,
  61326     },
  61327 #endif /* chips */
  61328 
  61329 #if defined(BCM_88680_A0)
  61330     { /* SOC_REG_INT_GTX_EEE_LPI_EVENT_COUNTER_BCM88680_A0r */
  61331         soc_block_list[2],
  61332         soc_portreg,
  61333         1,
  61334         0,
  61335         0x3e00,
  61336         SOC_REG_FLAG_COUNTER,
  61337         0,
  61338         1,
  61339         soc_GTX_EEE_LPI_EVENT_COUNTER_BCM88680_A0r_fields,
  61340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61341         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61342         62,
  61343         -1,
  61344     },
  61345 #endif /* chips */
  61346 
  61347 #if defined(BCM_56800_A0)
  61348     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_CONFIGr */
  61349         soc_block_list[9],
  61350         soc_portreg,
  61351         1,
  61352         0,
  61353         0xa08,
  61354         0,
  61355         0,
  61356         3,
  61357         soc_GXPORT_LAG_FAILOVER_CONFIGr_fields,
  61358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61359         SOC_RESET_MASK_DEC(0x00000005, 0x00000000)
  61360         -1,
  61361         -1,
  61362     },
  61363 #endif /* chips */
  61364 
  61365 #if defined(BCM_56142_A0)
  61366     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_CONFIG_BCM56142_A0r */
  61367         soc_block_list[14],
  61368         soc_portreg,
  61369         1,
  61370         0,
  61371         0xb00,
  61372         0,
  61373         0,
  61374         1,
  61375         soc_GXPORT_LAG_FAILOVER_CONFIG_BCM56142_A0r_fields,
  61376         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  61377         SOC_RESET_MASK_DEC(0x0000000d, 0x00000000)
  61378         -1,
  61379         -1,
  61380     },
  61381 #endif /* chips */
  61382 
  61383 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  61384     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_CONFIG_BCM56334_A0r */
  61385         soc_block_list[14],
  61386         soc_portreg,
  61387         1,
  61388         0,
  61389         0xb00,
  61390         0,
  61391         0,
  61392         4,
  61393         soc_GXPORT_LAG_FAILOVER_CONFIG_BCM56624_A0r_fields,
  61394         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  61395         SOC_RESET_MASK_DEC(0x0000000d, 0x00000000)
  61396         -1,
  61397         -1,
  61398     },
  61399 #endif /* chips */
  61400 
  61401 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  61402     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  61403     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_CONFIG_BCM56624_A0r */
  61404         soc_block_list[205],
  61405         soc_portreg,
  61406         1,
  61407         0,
  61408         0xb00,
  61409         0,
  61410         0,
  61411         4,
  61412         soc_GXPORT_LAG_FAILOVER_CONFIG_BCM56624_A0r_fields,
  61413         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  61414         SOC_RESET_MASK_DEC(0x0000000d, 0x00000000)
  61415         -1,
  61416         -1,
  61417     },
  61418 #endif /* chips */
  61419 
  61420 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  61421     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  61422     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_CONFIG_BCM56634_A0r */
  61423         soc_block_list[207],
  61424         soc_portreg,
  61425         1,
  61426         0,
  61427         0xb00,
  61428         0,
  61429         0,
  61430         4,
  61431         soc_GXPORT_LAG_FAILOVER_CONFIG_BCM56624_A0r_fields,
  61432         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  61433         SOC_RESET_MASK_DEC(0x0000000d, 0x00000000)
  61434         -1,
  61435         -1,
  61436     },
  61437 #endif /* chips */
  61438 
  61439 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  61440     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_CONFIG_BCM56685_A0r */
  61441         soc_block_list[209],
  61442         soc_portreg,
  61443         1,
  61444         0,
  61445         0xb00,
  61446         0,
  61447         0,
  61448         4,
  61449         soc_GXPORT_LAG_FAILOVER_CONFIG_BCM56624_A0r_fields,
  61450         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  61451         SOC_RESET_MASK_DEC(0x0000000d, 0x00000000)
  61452         -1,
  61453         -1,
  61454     },
  61455 #endif /* chips */
  61456 
  61457 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  61458     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_CONFIG_BCM56820_A0r */
  61459         soc_block_list[9],
  61460         soc_portreg,
  61461         1,
  61462         0,
  61463         0xc06,
  61464         0,
  61465         0,
  61466         4,
  61467         soc_GXPORT_LAG_FAILOVER_CONFIG_BCM56624_A0r_fields,
  61468         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  61469         SOC_RESET_MASK_DEC(0x0000000d, 0x00000000)
  61470         -1,
  61471         -1,
  61472     },
  61473 #endif /* chips */
  61474 
  61475 #if defined(BCM_56800_A0)
  61476     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_STATUSr */
  61477         soc_block_list[9],
  61478         soc_portreg,
  61479         1,
  61480         0,
  61481         0xa09,
  61482         SOC_REG_FLAG_RO,
  61483         0,
  61484         1,
  61485         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  61486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61488         -1,
  61489         -1,
  61490     },
  61491 #endif /* chips */
  61492 
  61493 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  61494     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_STATUS_BCM56334_A0r */
  61495         soc_block_list[14],
  61496         soc_portreg,
  61497         1,
  61498         0,
  61499         0xb01,
  61500         SOC_REG_FLAG_RO,
  61501         0,
  61502         1,
  61503         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  61504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61505         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61506         -1,
  61507         -1,
  61508     },
  61509 #endif /* chips */
  61510 
  61511 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  61512     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  61513     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_STATUS_BCM56624_A0r */
  61514         soc_block_list[205],
  61515         soc_portreg,
  61516         1,
  61517         0,
  61518         0xb01,
  61519         SOC_REG_FLAG_RO,
  61520         0,
  61521         1,
  61522         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  61523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61524         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61525         -1,
  61526         -1,
  61527     },
  61528 #endif /* chips */
  61529 
  61530 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  61531     defined(BCM_56634_A0) || defined(BCM_56634_B0)
  61532     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_STATUS_BCM56634_A0r */
  61533         soc_block_list[207],
  61534         soc_portreg,
  61535         1,
  61536         0,
  61537         0xb01,
  61538         SOC_REG_FLAG_RO,
  61539         0,
  61540         1,
  61541         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  61542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61544         -1,
  61545         -1,
  61546     },
  61547 #endif /* chips */
  61548 
  61549 #if defined(BCM_56685_A0) || defined(BCM_56685_B0)
  61550     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_STATUS_BCM56685_A0r */
  61551         soc_block_list[209],
  61552         soc_portreg,
  61553         1,
  61554         0,
  61555         0xb01,
  61556         SOC_REG_FLAG_RO,
  61557         0,
  61558         1,
  61559         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  61560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61562         -1,
  61563         -1,
  61564     },
  61565 #endif /* chips */
  61566 
  61567 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  61568     { /* SOC_REG_INT_GXPORT_LAG_FAILOVER_STATUS_BCM56820_A0r */
  61569         soc_block_list[9],
  61570         soc_portreg,
  61571         1,
  61572         0,
  61573         0xc07,
  61574         SOC_REG_FLAG_RO,
  61575         0,
  61576         1,
  61577         soc_GXPORT_LAG_FAILOVER_STATUSr_fields,
  61578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61580         -1,
  61581         -1,
  61582     },
  61583 #endif /* chips */
  61584